Initial file dump from open source releaseHEADmaster

1 files changed, 156 insertions, 0 deletions

diff --git a/include/soc/sprd/chip_x35lt8/__regs_aon_clk.h b/include/soc/sprd/chip_x35lt8/__regs_aon_clk.h
new file mode 100644
index 00000000..04713eb0
--- /dev/null
+++ b/include/soc/sprd/chip_x35lt8/__regs_aon_clk.h
@@ -0,0 +1,156 @@
+/* the head file modifier:     g   2015-03-19 17:10:17*/
+
+/*
+* Copyright (C) 2013 Spreadtrum Communications Inc.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License
+* as published by the Free Software Foundation; either version 2
+* of the License, or (at your option) any later version.
+* 
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+* GNU General Public License for more details.
+*
+*************************************************
+* Automatically generated C header: do not edit *
+*************************************************
+*/
+
+#ifndef __SCI_GLB_REGS_H__
+#error  "Don't include this file directly, Pls include sci_glb_regs.h"
+#endif 
+
+
+#ifndef __H_REGS_AON_CLK_CORE_HEADFILE_H__
+#define __H_REGS_AON_CLK_CORE_HEADFILE_H__ __FILE__
+
+#define  REGS_AON_CLK_CORE
+
+/* registers definitions for AON_CLK_CORE */
+#define REG_AON_CLK_CORE_clk_pub_ahb_cfg		SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x20)/*clk_pub_ahb_cfg*/
+#define REG_AON_CLK_CORE_clk_aon_apb_cfg		SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x24)/*clk_aon_apb_cfg*/
+#define REG_AON_CLK_CORE_clk_adi_cfg			SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x28)/*clk_adi_cfg*/
+#define REG_AON_CLK_CORE_clk_pwm0_cfg			SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x2c)/*clk_pwm0_cfg*/
+#define REG_AON_CLK_CORE_clk_pwm1_cfg			SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x30)/*clk_pwm1_cfg*/
+#define REG_AON_CLK_CORE_clk_pwm2_cfg			SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x34)/*clk_pwm2_cfg*/
+#define REG_AON_CLK_CORE_clk_pwm3_cfg			SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x38)/*clk_pwm3_cfg*/
+#define REG_AON_CLK_CORE_clk_arm7_uart_cfg		SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x3c)/*clk_arm7_uart_cfg*/
+#define REG_AON_CLK_CORE_clk_thm_cfg			SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x40)/*clk_thm_cfg*/
+#define REG_AON_CLK_CORE_clk_mspi_cfg			SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x44)/*clk_mspi_cfg*/
+#define REG_AON_CLK_CORE_clk_i2c_cfg			SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x48)/*clk_i2c_cfg*/
+#define REG_AON_CLK_CORE_clk_gpu_avs_cfg		SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x4c)/*clk_gpu_avs_cfg*/
+#define REG_AON_CLK_CORE_clk_audif_cfg			SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x50)/*clk_audif_cfg*/
+#define REG_AON_CLK_CORE_clk_apcpu_dap_cfg		SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x54)/*clk_apcpu_dap_cfg*/
+#define REG_AON_CLK_CORE_clk_emc_cfg			SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x58)/*clk_emc_cfg*/
+#define REG_AON_CLK_CORE_clk_apcpu_ts_cfg		SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x5c)/*clk_apcpu_ts_cfg*/
+#define REG_AON_CLK_CORE_clk_djtag_tck_cfg		SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x60)/*clk_djtag_tck_cfg*/
+#define REG_AON_CLK_CORE_clk_arm7_ahb_cfg		SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x64)/*clk_arm7_ahb_cfg*/
+#define REG_AON_CLK_CORE_clk_ca5_ts_cfg			SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x68)/*clk_ca5_ts_cfg*/
+#define REG_AON_CLK_CORE_clk_ca53_big_avs_cfg		SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x6c)/*clk_ca53_big_avs_cfg*/
+#define REG_AON_CLK_CORE_clk_ca53_lit_avs_cfg		SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x70)/*clk_ca53_lit_avs_cfg*/
+#define REG_AON_CLK_CORE_clk_cci_cfg			SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x74)/*clk_cci_cfg*/
+#define REG_AON_CLK_CORE_clk_cssys_cfg			SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x78)/*clk_cssys_cfg*/
+/* registers definitions for controller REGS_AON_CLK */
+#define REG_AON_CLK_PUB_AHB_CFG         REG_AON_CLK_CORE_clk_pub_ahb_cfg
+#define REG_AON_CLK_AON_APB_CFG         REG_AON_CLK_CORE_clk_aon_apb_cfg
+#define REG_AON_CLK_ADI_CFG             REG_AON_CLK_CORE_clk_adi_cfg
+#define REG_AON_CLK_PWM0_CFG            REG_AON_CLK_CORE_clk_pwm0_cfg
+#define REG_AON_CLK_PWM1_CFG            REG_AON_CLK_CORE_clk_pwm1_cfg
+#define REG_AON_CLK_PWM2_CFG            REG_AON_CLK_CORE_clk_pwm2_cfg
+#define REG_AON_CLK_PWM3_CFG            REG_AON_CLK_CORE_clk_pwm3_cfg
+#define REG_AON_CLK_ARM7_UART_CFG       REG_AON_CLK_CORE_clk_arm7_uart_cfg
+#define REG_AON_CLK_THM_CFG             REG_AON_CLK_CORE_clk_thm_cfg
+#define REG_AON_CLK_MSPI_CFG            REG_AON_CLK_CORE_clk_mspi_cfg
+#define REG_AON_CLK_I2C_CFG             REG_AON_CLK_CORE_clk_i2c_cfg
+#define REG_AON_CLK_AVS_CFG             REG_AON_CLK_CORE_clk_avs_cfg
+#define REG_AON_CLK_AUDIF_CFG           REG_AON_CLK_CORE_clk_audif_cfg
+#define REG_AON_CLK_CA7_DAP_CFG         REG_AON_CLK_CORE_clk_apcpu_dap_cfg
+#define REG_AON_CLK_EMC_CFG             REG_AON_CLK_CORE_clk_emc_cfg
+#define REG_AON_CLK_CA7_TS_CFG          REG_AON_CLK_CORE_clk_apcpu_ts_cfg
+#define REG_AON_CLK_DJTAG_CLK_CFG       REG_AON_CLK_CORE_clk_djtag_tck_cfg
+#define REG_AON_CLK_ARM7_AHB_CFG        REG_AON_CLK_CORE_clk_arm7_ahb_cfg
+#define REG_AON_CLK_CA5_TS_CFG          REG_AON_CLK_CORE_clk_ca5_ts_cfg	
+/* vars definitions for controller REGS_AON_CLK */
+#define PUB_AHB_CLK_SEL_SHIFT		(0x0)
+#define PUB_AHB_CLK_SEL_MASK		(0x3 << PUB_AHB_CLK_SEL_SHIFT)
+
+
+/* bits definitions for register REG_AON_CLK_CORE_clk_pub_ahb_cfg */
+#define BITS_CLK_PUB_AHB_DIV(_X_)				( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_CLK_PUB_AHB_SEL(_X_)				( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_AON_CLK_CORE_clk_aon_apb_cfg */
+#define BITS_CLK_AON_APB_DIV(_X_)				( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_CLK_AON_APB_SEL(_X_)				( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_AON_CLK_CORE_clk_adi_cfg */
+#define BITS_CLK_ADI_SEL(_X_)					( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_AON_CLK_CORE_clk_pwm0_cfg */
+#define BITS_CLK_PWM0_SEL(_X_)					( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_AON_CLK_CORE_clk_pwm1_cfg */
+#define BITS_CLK_PWM1_SEL(_X_)					( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_AON_CLK_CORE_clk_pwm2_cfg */
+#define BITS_CLK_PWM2_SEL(_X_)					( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_AON_CLK_CORE_clk_pwm3_cfg */
+#define BITS_CLK_PWM3_SEL(_X_)					( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_AON_CLK_CORE_clk_arm7_uart_cfg */
+#define BITS_CLK_ARM7_UART_SEL(_X_)				( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_AON_CLK_CORE_clk_thm_cfg */
+#define BIT_CLK_THM_SEL						( BIT(0) )
+
+/* bits definitions for register REG_AON_CLK_CORE_clk_mspi_cfg */
+#define BITS_CLK_MSPI_SEL(_X_)					( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_AON_CLK_CORE_clk_i2c_cfg */
+#define BITS_CLK_I2C_SEL(_X_)					( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_AON_CLK_CORE_clk_gpu_avs_cfg */
+#define BITS_CLK_GPU_AVS_SEL(_X_)				( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_AON_CLK_CORE_clk_audif_cfg */
+#define BITS_CLK_AUDIF_SEL(_X_)					( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_AON_CLK_CORE_clk_apcpu_dap_cfg */
+#define BITS_CLK_APCPU_DAP_SEL(_X_)				( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_AON_CLK_CORE_clk_emc_cfg */
+#define BITS_CLK_EMC_DIV(_X_)		( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_CLK_EMC_SEL(_X_)		( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
+
+/* bits definitions for register REG_AON_CLK_CORE_clk_apcpu_ts_cfg */
+#define BITS_CLK_APCPU_TS_SEL(_X_)				( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_AON_CLK_CORE_clk_djtag_tck_cfg */
+#define BIT_CLK_DJTAG_TCK_PAD_SEL				( BIT(16) )
+#define BIT_CLK_DJTAG_TCK_SEL					( BIT(0) )
+
+/* bits definitions for register REG_AON_CLK_CORE_clk_arm7_ahb_cfg */
+#define BITS_CLK_ARM7_AHB_DIV(_X_)				( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_CLK_ARM7_AHB_SEL(_X_)				( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_AON_CLK_CORE_clk_ca5_ts_cfg */
+#define BITS_CLK_CA5_TS_SEL(_X_)				( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_AON_CLK_CORE_clk_ca53_big_avs_cfg */
+#define BITS_CLK_CA53_BIG_AVS_SEL(_X_)				( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_AON_CLK_CORE_clk_ca53_lit_avs_cfg */
+#define BITS_CLK_CA53_LIT_AVS_SEL(_X_)				( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_AON_CLK_CORE_clk_cci_cfg */
+#define BITS_CLK_CCI_DIV(_X_)					( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_CLK_CCI_SEL(_X_)					( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_AON_CLK_CORE_clk_cssys_cfg */
+#define BITS_CLK_CSSYS_DIV(_X_)					( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_CLK_CSSYS_SEL(_X_)					( (_X_) & (BIT(0)|BIT(1)) )
+
+#endif