diff options
| author | Yuval Adam <_@yuv.al> | 2017-08-30 08:25:59 +0000 |
|---|---|---|
| committer | Yuval Adam <_@yuv.al> | 2017-08-30 08:25:59 +0000 |
| commit | 8e4bff4cab0ddac6060645b0715210484d02ff40 (patch) | |
| tree | 3a5c3024371a04692a3a6d9974d001cdff8ebf84 /include/soc | |
Diffstat (limited to 'include/soc')
263 files changed, 74413 insertions, 0 deletions
diff --git a/include/soc/sprd/__board-coreprime3g_ve.h b/include/soc/sprd/__board-coreprime3g_ve.h new file mode 100644 index 00000000..cc0fe16f --- /dev/null +++ b/include/soc/sprd/__board-coreprime3g_ve.h @@ -0,0 +1,136 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __GPIO_SCX35GA_H__ +#define __GPIO_SCX35GA_H__ + +#ifndef __ASM_ARCH_BOARD_H +#error "Don't include this file directly, include <mach/board.h>" +#endif + +#define GPIO_TOUCH_RESET 81 +#define GPIO_TOUCH_IRQ 82 + +#define GPIO_IF_PMIC_SDA 159 +#define GPIO_IF_PMIC_SCL 160 +#define GPIO_IF_PMIC_IRQ 161 +#define GPIO_FUELGAUGE_SCL 65 +#define GPIO_FUELGAUGE_SDA 66 +#define GPIO_FUELGAUGE_ALERT 153 +#define GPIO_MUIC_SDA 150 +#define GPIO_MUIC_SCL 151 +#define GPIO_MUIC_IRQ 152 + +#define GPIO_SENSOR_RESET 186//41 +#define GPIO_SUB_SENSOR_RESET 238 +#define GPIO_MAIN_SENSOR_PWN 188//42 +#define GPIO_SUB_SENSOR_PWN 187//43 +#define CAM_FLASH_ENF_GPIO 81 +#define CAM_FLASH_ENT_GPIO 82 +#define SPRD_FLASH_ON 1 +#define SPRD_FLASH_OFF 0 +#define GPIO_TOUCHKEY_LED_EN 116 + +#define SPRD_FLASH_OFST 0x890 +#define SPRD_FLASH_CTRL_BIT 0x8000 +#define SPRD_FLASH_LOW_VAL 0x3 +#define SPRD_FLASH_HIGH_VAL 0xF +#define SPRD_FLASH_LOW_CUR 110 +#define SPRD_FLASH_HIGH_CUR 470 + +#define USB_OTG_CABLE_DETECT 72 + +#define EIC_CHARGER_DETECT (A_EIC_START + 0) +#define EIC_POWER_PBINT2 (A_EIC_START + 1) +#define EIC_POWER_PBINT (A_EIC_START + 2) +#define EIC_AUD_HEAD_BUTTON (A_EIC_START + 3) +#define EIC_CHG_CV_STATE (A_EIC_START + 4) +#define EIC_AUD_HEAD_INST (A_EIC_START + 5) +#define EIC_VCHG_OVI (A_EIC_START + 6) +#define EIC_VBAT_OVI (A_EIC_START + 7) +#define EIC_AUD_HEAD_INST2 (A_EIC_START + 8) + +#define EIC_KEY_POWER (EIC_POWER_PBINT) +#define HEADSET_BUTTON_GPIO 239 +#define HEADSET_DETECT_GPIO 237 +#define HEADSET_SWITCH_GPIO 0 +#define HEADSET_AMP_GPIO 131 +#define HEADSET_EXT_MICBIAS_GPIO 123 + +#define HEADSET_IRQ_TRIGGER_LEVEL_DETECT 0 +#define HEADSET_IRQ_TRIGGER_LEVEL_BUTTON 0 + +#define HEADSET_ADC_MIN_KEY_MEDIA 0 +#define HEADSET_ADC_MAX_KEY_MEDIA 190 +#define HEADSET_ADC_MIN_KEY_VOLUMEUP 191 +#define HEADSET_ADC_MAX_KEY_VOLUMEUP 347 +#define HEADSET_ADC_MIN_KEY_VOLUMEDOWN 348 +#define HEADSET_ADC_MAX_KEY_VOLUMEDOWN 760 +#define HEADSET_ADC_THRESHOLD_3POLE_DETECT 1170 +#define HEADSET_ADC_THRESHOLD_4POLE_DETECT 2700 +#define HEADSET_IRQ_THRESHOLD_BUTTON 1 +#define HEADSET_HEADMICBIAS_VOLTAGE 3000000 + + +#define SPI0_BACKLIGHT_EN_GPIO 214 +#define SPI0_BACKLIGHT_PWM_GPIO 234 + +#define SPI0_CMMB_CS_GPIO 156 +#define SPI1_WIFI_CS_GPIO 44 + +#define GPIO_BK 136 + +#define GPIO_CMMB_RESET 144 +#define GPIO_CMMB_INT 143 +#define GPIO_CMMB_26M_CLK_EN 197 + +#define GPIO_BT_RESET 233 +#define GPIO_BT_POWER 231 +#define GPIO_BT2AP_WAKE 232 +#define GPIO_AP2BT_WAKE 235 + +#define GPIO_WIFI_SHUTDOWN 230 +//#define GPIO_WIFI_IRQ 234 +#define GPIO_WIFI_IRQ 148 +#define GPIO_PROX_INT 216 +#define GPIO_GYRO_INT1 163 +#define GPIO_M_RSTN 161 +#define GPIO_M_DRDY 164 + +#define GPIO_SDIO_DETECT 75 + +#define SPRD_PIN_SDIO0_OFFSET 0x0184 +#define SPRD_PIN_SDIO0_SIZE 7 +#define SPRD_PIN_SDIO0_D3_INDEX 0 +#define SPRD_PIN_SDIO0_D3_GPIO 100 +#define SPRD_PIN_SDIO0_SD_FUNC 0 +#define SPRD_PIN_SDIO0_GPIO_FUNC 3 + +/* ION config info +LCD: + 960x540 + +Video Playing: + 1080p 8 ref-frame + +Video Recording: + 720p + +Camera: + 8M, support ZSL, support preview/capture rotation +*/ + +#define SPRD_ION_SIZE (52 * SZ_1M) +#define SPRD_ION_OVERLAY_SIZE (7 * SZ_1M) + +#endif diff --git a/include/soc/sprd/__board-coreprimelite.h b/include/soc/sprd/__board-coreprimelite.h new file mode 100644 index 00000000..73e17606 --- /dev/null +++ b/include/soc/sprd/__board-coreprimelite.h @@ -0,0 +1,128 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __GPIO_SC8810_H__ +#define __GPIO_SC8810_H__ + +#ifndef __ASM_ARCH_BOARD_H +#error "Don't include this file directly, include <mach/board.h>" +#endif + +#define GPIO_TOUCH_RESET 145 +#define GPIO_TOUCH_IRQ 144 + +#define GPIO_MAIN_SENSOR_RESET 44 +#define GPIO_MAIN_SENSOR_PWN 46 +#define GPIO_SUB_SENSOR_RESET 45 +#define GPIO_SUB_SENSOR_PWN 47 + +#define USB_OTG_CABLE_DETECT 126 + +#define SPRD_FLASH_OFST 0x890 +#define SPRD_FLASH_CTRL_BIT 0x8000 +#define SPRD_FLASH_LOW_VAL 0x3 +#define SPRD_FLASH_HIGH_VAL 0xF +#define SPRD_FLASH_LOW_CUR 110 +#define SPRD_FLASH_HIGH_CUR 470 + +#define GPIO_KEY_VOLUMEDOWN 124 +#define GPIO_KEY_VOLUMEUP 125 +//#define GPIO_KEY_CAMERA 0 +//#define GPIO_KEY_HOME 0 + +#define EIC_CHARGER_DETECT (A_EIC_START + 0) +#define EIC_POWER_PBINT2 (A_EIC_START + 1) +#define EIC_POWER_PBINT (A_EIC_START + 2) +#define EIC_AUD_HEAD_BUTTON (A_EIC_START + 3) +#define EIC_CHG_CV_STATE (A_EIC_START + 4) +#define EIC_AUD_HEAD_INST (A_EIC_START + 5) +#define EIC_VCHG_OVI (A_EIC_START + 6) +#define EIC_VBAT_OVI (A_EIC_START + 7) +#define EIC_AUD_HEAD_INST2 (A_EIC_START + 8) + +#define EIC_KEY_POWER (EIC_POWER_PBINT) + +#define HEADSET_BUTTON_GPIO (EIC_AUD_HEAD_BUTTON) +#define HEADSET_DETECT_GPIO (EIC_AUD_HEAD_INST2) +#define HEADSET_SWITCH_GPIO 0 + +#define HEADSET_IRQ_TRIGGER_LEVEL_DETECT 1 +#define HEADSET_IRQ_TRIGGER_LEVEL_BUTTON 1 + +#define HEADSET_ADC_MIN_KEY_MEDIA 0 +#define HEADSET_ADC_MAX_KEY_MEDIA 170 +#define HEADSET_ADC_MIN_KEY_VOLUMEUP 171 +#define HEADSET_ADC_MAX_KEY_VOLUMEUP 430 +#define HEADSET_ADC_MIN_KEY_VOLUMEDOWN 431 +#define HEADSET_ADC_MAX_KEY_VOLUMEDOWN 760 +#define HEADSET_ADC_THRESHOLD_3POLE_DETECT 100 +#define HEADSET_ADC_THRESHOLD_4POLE_DETECT 3100 +#define HEADSET_IRQ_THRESHOLD_BUTTON 1 +#define HEADSET_HEADMICBIAS_VOLTAGE 3000000 + +#define SPI0_CMMB_CS_GPIO 32 +#define SPI1_WIFI_CS_GPIO 44 + +#define GPIO_BK 143 +#define MSENSOR_DRDY_GPIO 53 +#define GPIO_PLSENSOR_IRQ 213 +/*For bcm4343 power on/off and sleep/wake */ +#define GPIO_BT_RESET 122 +#define GPIO_BT_POWER 131 +#define GPIO_BT2AP_WAKE 133 +#define GPIO_AP2BT_WAKE 132 + +/*#define GPIO_BT_RESET 194 */ +#define GPIO_WIFI_POWERON 189 +#define GPIO_WIFI_SHUTDOWN 130 +#define GPIO_WIFI_IRQ 97 + +#define GPIO_PROX_INT 140 +#define GPIO_GPS_ONOFF 174 + +#define GPIO_SDIO_DETECT 75 + +#define SPRD_PIN_SDIO0_OFFSET 0x01E0 +#define SPRD_PIN_SDIO0_SIZE 7 +#define SPRD_PIN_SDIO0_D3_INDEX 0 +#define SPRD_PIN_SDIO0_D3_GPIO 100 +#define SPRD_PIN_SDIO0_SD_FUNC 0 +#define SPRD_PIN_SDIO0_GPIO_FUNC 3 + +#define SIPC_SMEM_ADDR (CONFIG_PHYS_OFFSET + 120 * SZ_1M) +#define CPT_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#define CPT_TOTAL_SIZE (SZ_1M * 18) +#define CPT_RING_ADDR (CPT_START_ADDR + CPT_TOTAL_SIZE - SZ_4K) +#define CPT_RING_SIZE (SZ_4K) +#define CPT_SMEM_SIZE (SZ_1M * 2) +#define CPW_START_ADDR (CONFIG_PHYS_OFFSET + 150 * SZ_1M) +#define CPW_TOTAL_SIZE (SZ_1M * 33) +#define CPW_RING_ADDR (CPW_START_ADDR + CPW_TOTAL_SIZE - SZ_4K) +#define CPW_RING_SIZE (SZ_4K) +#define CPW_SMEM_SIZE (SZ_1M * 2) +#define WCN_START_ADDR (CONFIG_PHYS_OFFSET + 320 * SZ_1M) +#define WCN_TOTAL_SIZE (SZ_1M * 5) +#define WCN_RING_ADDR (WCN_START_ADDR + WCN_TOTAL_SIZE - SZ_4K) +#define WCN_RING_SIZE (SZ_4K) +#define WCN_SMEM_SIZE (SZ_1M * 2) +#define GGE_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#define GGE_TOTAL_SIZE (SZ_1M * 22) +#define GGE_RING_ADDR (GGE_START_ADDR + GGE_TOTAL_SIZE - SZ_4K) +#define GGE_RING_SIZE (SZ_4K) +#define GGE_SMEM_SIZE (SZ_1M * 2) +#define LTE_START_ADDR (CONFIG_PHYS_OFFSET + 150 * SZ_1M) +#define LTE_TOTAL_SIZE (SZ_1M * 64) +#define LTE_RING_ADDR (LTE_START_ADDR + LTE_TOTAL_SIZE - SZ_4K) +#define LTE_RING_SIZE (SZ_4K) +#define LTE_SMEM_SIZE (SZ_1M * 2) +#endif diff --git a/include/soc/sprd/__board-grandprime3g_ve.h b/include/soc/sprd/__board-grandprime3g_ve.h new file mode 100755 index 00000000..cc0fe16f --- /dev/null +++ b/include/soc/sprd/__board-grandprime3g_ve.h @@ -0,0 +1,136 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __GPIO_SCX35GA_H__ +#define __GPIO_SCX35GA_H__ + +#ifndef __ASM_ARCH_BOARD_H +#error "Don't include this file directly, include <mach/board.h>" +#endif + +#define GPIO_TOUCH_RESET 81 +#define GPIO_TOUCH_IRQ 82 + +#define GPIO_IF_PMIC_SDA 159 +#define GPIO_IF_PMIC_SCL 160 +#define GPIO_IF_PMIC_IRQ 161 +#define GPIO_FUELGAUGE_SCL 65 +#define GPIO_FUELGAUGE_SDA 66 +#define GPIO_FUELGAUGE_ALERT 153 +#define GPIO_MUIC_SDA 150 +#define GPIO_MUIC_SCL 151 +#define GPIO_MUIC_IRQ 152 + +#define GPIO_SENSOR_RESET 186//41 +#define GPIO_SUB_SENSOR_RESET 238 +#define GPIO_MAIN_SENSOR_PWN 188//42 +#define GPIO_SUB_SENSOR_PWN 187//43 +#define CAM_FLASH_ENF_GPIO 81 +#define CAM_FLASH_ENT_GPIO 82 +#define SPRD_FLASH_ON 1 +#define SPRD_FLASH_OFF 0 +#define GPIO_TOUCHKEY_LED_EN 116 + +#define SPRD_FLASH_OFST 0x890 +#define SPRD_FLASH_CTRL_BIT 0x8000 +#define SPRD_FLASH_LOW_VAL 0x3 +#define SPRD_FLASH_HIGH_VAL 0xF +#define SPRD_FLASH_LOW_CUR 110 +#define SPRD_FLASH_HIGH_CUR 470 + +#define USB_OTG_CABLE_DETECT 72 + +#define EIC_CHARGER_DETECT (A_EIC_START + 0) +#define EIC_POWER_PBINT2 (A_EIC_START + 1) +#define EIC_POWER_PBINT (A_EIC_START + 2) +#define EIC_AUD_HEAD_BUTTON (A_EIC_START + 3) +#define EIC_CHG_CV_STATE (A_EIC_START + 4) +#define EIC_AUD_HEAD_INST (A_EIC_START + 5) +#define EIC_VCHG_OVI (A_EIC_START + 6) +#define EIC_VBAT_OVI (A_EIC_START + 7) +#define EIC_AUD_HEAD_INST2 (A_EIC_START + 8) + +#define EIC_KEY_POWER (EIC_POWER_PBINT) +#define HEADSET_BUTTON_GPIO 239 +#define HEADSET_DETECT_GPIO 237 +#define HEADSET_SWITCH_GPIO 0 +#define HEADSET_AMP_GPIO 131 +#define HEADSET_EXT_MICBIAS_GPIO 123 + +#define HEADSET_IRQ_TRIGGER_LEVEL_DETECT 0 +#define HEADSET_IRQ_TRIGGER_LEVEL_BUTTON 0 + +#define HEADSET_ADC_MIN_KEY_MEDIA 0 +#define HEADSET_ADC_MAX_KEY_MEDIA 190 +#define HEADSET_ADC_MIN_KEY_VOLUMEUP 191 +#define HEADSET_ADC_MAX_KEY_VOLUMEUP 347 +#define HEADSET_ADC_MIN_KEY_VOLUMEDOWN 348 +#define HEADSET_ADC_MAX_KEY_VOLUMEDOWN 760 +#define HEADSET_ADC_THRESHOLD_3POLE_DETECT 1170 +#define HEADSET_ADC_THRESHOLD_4POLE_DETECT 2700 +#define HEADSET_IRQ_THRESHOLD_BUTTON 1 +#define HEADSET_HEADMICBIAS_VOLTAGE 3000000 + + +#define SPI0_BACKLIGHT_EN_GPIO 214 +#define SPI0_BACKLIGHT_PWM_GPIO 234 + +#define SPI0_CMMB_CS_GPIO 156 +#define SPI1_WIFI_CS_GPIO 44 + +#define GPIO_BK 136 + +#define GPIO_CMMB_RESET 144 +#define GPIO_CMMB_INT 143 +#define GPIO_CMMB_26M_CLK_EN 197 + +#define GPIO_BT_RESET 233 +#define GPIO_BT_POWER 231 +#define GPIO_BT2AP_WAKE 232 +#define GPIO_AP2BT_WAKE 235 + +#define GPIO_WIFI_SHUTDOWN 230 +//#define GPIO_WIFI_IRQ 234 +#define GPIO_WIFI_IRQ 148 +#define GPIO_PROX_INT 216 +#define GPIO_GYRO_INT1 163 +#define GPIO_M_RSTN 161 +#define GPIO_M_DRDY 164 + +#define GPIO_SDIO_DETECT 75 + +#define SPRD_PIN_SDIO0_OFFSET 0x0184 +#define SPRD_PIN_SDIO0_SIZE 7 +#define SPRD_PIN_SDIO0_D3_INDEX 0 +#define SPRD_PIN_SDIO0_D3_GPIO 100 +#define SPRD_PIN_SDIO0_SD_FUNC 0 +#define SPRD_PIN_SDIO0_GPIO_FUNC 3 + +/* ION config info +LCD: + 960x540 + +Video Playing: + 1080p 8 ref-frame + +Video Recording: + 720p + +Camera: + 8M, support ZSL, support preview/capture rotation +*/ + +#define SPRD_ION_SIZE (52 * SZ_1M) +#define SPRD_ION_OVERLAY_SIZE (7 * SZ_1M) + +#endif diff --git a/include/soc/sprd/__board-grandprime_dtv.h b/include/soc/sprd/__board-grandprime_dtv.h new file mode 100644 index 00000000..50157da4 --- /dev/null +++ b/include/soc/sprd/__board-grandprime_dtv.h @@ -0,0 +1,136 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __GPIO_SCX35GA_H__ +#define __GPIO_SCX35GA_H__ + +#ifndef __ASM_ARCH_BOARD_H +#error "Don't include this file directly, include <mach/board.h>" +#endif + +#define GPIO_TOUCH_RESET 81 +#define GPIO_TOUCH_IRQ 82 + +#define GPIO_IF_PMIC_SDA 159 +#define GPIO_IF_PMIC_SCL 160 +#define GPIO_IF_PMIC_IRQ 161 +#define GPIO_FUELGAUGE_SCL 65 +#define GPIO_FUELGAUGE_SDA 66 +#define GPIO_FUELGAUGE_ALERT 153 +#define GPIO_MUIC_SDA 150 +#define GPIO_MUIC_SCL 151 +#define GPIO_MUIC_IRQ 152 + +#define GPIO_SENSOR_RESET 186/*41*/ +#define GPIO_SUB_SENSOR_RESET 238 +#define GPIO_MAIN_SENSOR_PWN 188/*42*/ +#define GPIO_SUB_SENSOR_PWN 187/*43*/ +#define CAM_FLASH_ENF_GPIO 81 +#define CAM_FLASH_ENT_GPIO 82 +#define SPRD_FLASH_ON 1 +#define SPRD_FLASH_OFF 0 +#define GPIO_TOUCHKEY_LED_EN 116 + +#define SPRD_FLASH_OFST 0x890 +#define SPRD_FLASH_CTRL_BIT 0x8000 +#define SPRD_FLASH_LOW_VAL 0x3 +#define SPRD_FLASH_HIGH_VAL 0xF +#define SPRD_FLASH_LOW_CUR 110 +#define SPRD_FLASH_HIGH_CUR 470 + +#define USB_OTG_CABLE_DETECT 72 + +#define EIC_CHARGER_DETECT (A_EIC_START + 0) +#define EIC_POWER_PBINT2 (A_EIC_START + 1) +#define EIC_POWER_PBINT (A_EIC_START + 2) +#define EIC_AUD_HEAD_BUTTON (A_EIC_START + 3) +#define EIC_CHG_CV_STATE (A_EIC_START + 4) +#define EIC_AUD_HEAD_INST (A_EIC_START + 5) +#define EIC_VCHG_OVI (A_EIC_START + 6) +#define EIC_VBAT_OVI (A_EIC_START + 7) +#define EIC_AUD_HEAD_INST2 (A_EIC_START + 8) + +#define EIC_KEY_POWER (EIC_POWER_PBINT) +#define HEADSET_BUTTON_GPIO 239 +#define HEADSET_DETECT_GPIO 237 +#define HEADSET_SWITCH_GPIO 0 +#define HEADSET_AMP_GPIO 131 +#define HEADSET_EXT_MICBIAS_GPIO 123 + +#define HEADSET_IRQ_TRIGGER_LEVEL_DETECT 0 +#define HEADSET_IRQ_TRIGGER_LEVEL_BUTTON 0 + +#define HEADSET_ADC_MIN_KEY_MEDIA 0 +#define HEADSET_ADC_MAX_KEY_MEDIA 190 +#define HEADSET_ADC_MIN_KEY_VOLUMEUP 191 +#define HEADSET_ADC_MAX_KEY_VOLUMEUP 347 +#define HEADSET_ADC_MIN_KEY_VOLUMEDOWN 348 +#define HEADSET_ADC_MAX_KEY_VOLUMEDOWN 760 +#define HEADSET_ADC_THRESHOLD_3POLE_DETECT 1170 +#define HEADSET_ADC_THRESHOLD_4POLE_DETECT 2700 +#define HEADSET_IRQ_THRESHOLD_BUTTON 1 +#define HEADSET_HEADMICBIAS_VOLTAGE 3000000 + + +#define SPI0_BACKLIGHT_EN_GPIO 214 +#define SPI0_BACKLIGHT_PWM_GPIO 234 + +#define SPI0_CMMB_CS_GPIO 156 +#define SPI1_WIFI_CS_GPIO 44 + +#define GPIO_BK 136 + +#define GPIO_CMMB_RESET 144 +#define GPIO_CMMB_INT 143 +#define GPIO_CMMB_26M_CLK_EN 197 + +#define GPIO_BT_RESET 233 +#define GPIO_BT_POWER 231 +#define GPIO_BT2AP_WAKE 232 +#define GPIO_AP2BT_WAKE 235 + +#define GPIO_WIFI_SHUTDOWN 230 +/*#define GPIO_WIFI_IRQ 234*/ +#define GPIO_WIFI_IRQ 148 +#define GPIO_PROX_INT 216 +#define GPIO_GYRO_INT1 163 +#define GPIO_M_RSTN 161 +#define GPIO_M_DRDY 164 + +#define GPIO_SDIO_DETECT 75 + +#define SPRD_PIN_SDIO0_OFFSET 0x0184 +#define SPRD_PIN_SDIO0_SIZE 7 +#define SPRD_PIN_SDIO0_D3_INDEX 0 +#define SPRD_PIN_SDIO0_D3_GPIO 100 +#define SPRD_PIN_SDIO0_SD_FUNC 0 +#define SPRD_PIN_SDIO0_GPIO_FUNC 3 + +/* ION config info +LCD: + 960x540 + +Video Playing: + 1080p 8 ref-frame + +Video Recording: + 720p + +Camera: + 8M, support ZSL, support preview/capture rotation +*/ + +#define SPRD_ION_SIZE (52 * SZ_1M) +#define SPRD_ION_OVERLAY_SIZE (7 * SZ_1M) + +#endif diff --git a/include/soc/sprd/__board-pikeayoung2dtv.h b/include/soc/sprd/__board-pikeayoung2dtv.h new file mode 100644 index 00000000..cc0fe16f --- /dev/null +++ b/include/soc/sprd/__board-pikeayoung2dtv.h @@ -0,0 +1,136 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __GPIO_SCX35GA_H__ +#define __GPIO_SCX35GA_H__ + +#ifndef __ASM_ARCH_BOARD_H +#error "Don't include this file directly, include <mach/board.h>" +#endif + +#define GPIO_TOUCH_RESET 81 +#define GPIO_TOUCH_IRQ 82 + +#define GPIO_IF_PMIC_SDA 159 +#define GPIO_IF_PMIC_SCL 160 +#define GPIO_IF_PMIC_IRQ 161 +#define GPIO_FUELGAUGE_SCL 65 +#define GPIO_FUELGAUGE_SDA 66 +#define GPIO_FUELGAUGE_ALERT 153 +#define GPIO_MUIC_SDA 150 +#define GPIO_MUIC_SCL 151 +#define GPIO_MUIC_IRQ 152 + +#define GPIO_SENSOR_RESET 186//41 +#define GPIO_SUB_SENSOR_RESET 238 +#define GPIO_MAIN_SENSOR_PWN 188//42 +#define GPIO_SUB_SENSOR_PWN 187//43 +#define CAM_FLASH_ENF_GPIO 81 +#define CAM_FLASH_ENT_GPIO 82 +#define SPRD_FLASH_ON 1 +#define SPRD_FLASH_OFF 0 +#define GPIO_TOUCHKEY_LED_EN 116 + +#define SPRD_FLASH_OFST 0x890 +#define SPRD_FLASH_CTRL_BIT 0x8000 +#define SPRD_FLASH_LOW_VAL 0x3 +#define SPRD_FLASH_HIGH_VAL 0xF +#define SPRD_FLASH_LOW_CUR 110 +#define SPRD_FLASH_HIGH_CUR 470 + +#define USB_OTG_CABLE_DETECT 72 + +#define EIC_CHARGER_DETECT (A_EIC_START + 0) +#define EIC_POWER_PBINT2 (A_EIC_START + 1) +#define EIC_POWER_PBINT (A_EIC_START + 2) +#define EIC_AUD_HEAD_BUTTON (A_EIC_START + 3) +#define EIC_CHG_CV_STATE (A_EIC_START + 4) +#define EIC_AUD_HEAD_INST (A_EIC_START + 5) +#define EIC_VCHG_OVI (A_EIC_START + 6) +#define EIC_VBAT_OVI (A_EIC_START + 7) +#define EIC_AUD_HEAD_INST2 (A_EIC_START + 8) + +#define EIC_KEY_POWER (EIC_POWER_PBINT) +#define HEADSET_BUTTON_GPIO 239 +#define HEADSET_DETECT_GPIO 237 +#define HEADSET_SWITCH_GPIO 0 +#define HEADSET_AMP_GPIO 131 +#define HEADSET_EXT_MICBIAS_GPIO 123 + +#define HEADSET_IRQ_TRIGGER_LEVEL_DETECT 0 +#define HEADSET_IRQ_TRIGGER_LEVEL_BUTTON 0 + +#define HEADSET_ADC_MIN_KEY_MEDIA 0 +#define HEADSET_ADC_MAX_KEY_MEDIA 190 +#define HEADSET_ADC_MIN_KEY_VOLUMEUP 191 +#define HEADSET_ADC_MAX_KEY_VOLUMEUP 347 +#define HEADSET_ADC_MIN_KEY_VOLUMEDOWN 348 +#define HEADSET_ADC_MAX_KEY_VOLUMEDOWN 760 +#define HEADSET_ADC_THRESHOLD_3POLE_DETECT 1170 +#define HEADSET_ADC_THRESHOLD_4POLE_DETECT 2700 +#define HEADSET_IRQ_THRESHOLD_BUTTON 1 +#define HEADSET_HEADMICBIAS_VOLTAGE 3000000 + + +#define SPI0_BACKLIGHT_EN_GPIO 214 +#define SPI0_BACKLIGHT_PWM_GPIO 234 + +#define SPI0_CMMB_CS_GPIO 156 +#define SPI1_WIFI_CS_GPIO 44 + +#define GPIO_BK 136 + +#define GPIO_CMMB_RESET 144 +#define GPIO_CMMB_INT 143 +#define GPIO_CMMB_26M_CLK_EN 197 + +#define GPIO_BT_RESET 233 +#define GPIO_BT_POWER 231 +#define GPIO_BT2AP_WAKE 232 +#define GPIO_AP2BT_WAKE 235 + +#define GPIO_WIFI_SHUTDOWN 230 +//#define GPIO_WIFI_IRQ 234 +#define GPIO_WIFI_IRQ 148 +#define GPIO_PROX_INT 216 +#define GPIO_GYRO_INT1 163 +#define GPIO_M_RSTN 161 +#define GPIO_M_DRDY 164 + +#define GPIO_SDIO_DETECT 75 + +#define SPRD_PIN_SDIO0_OFFSET 0x0184 +#define SPRD_PIN_SDIO0_SIZE 7 +#define SPRD_PIN_SDIO0_D3_INDEX 0 +#define SPRD_PIN_SDIO0_D3_GPIO 100 +#define SPRD_PIN_SDIO0_SD_FUNC 0 +#define SPRD_PIN_SDIO0_GPIO_FUNC 3 + +/* ION config info +LCD: + 960x540 + +Video Playing: + 1080p 8 ref-frame + +Video Recording: + 720p + +Camera: + 8M, support ZSL, support preview/capture rotation +*/ + +#define SPRD_ION_SIZE (52 * SZ_1M) +#define SPRD_ION_OVERLAY_SIZE (7 * SZ_1M) + +#endif diff --git a/include/soc/sprd/__board-sharkls_z3lte.h b/include/soc/sprd/__board-sharkls_z3lte.h new file mode 100755 index 00000000..ef445fcf --- /dev/null +++ b/include/soc/sprd/__board-sharkls_z3lte.h @@ -0,0 +1,128 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __GPIO_SC8810_H__ +#define __GPIO_SC8810_H__ + +#ifndef __ASM_ARCH_BOARD_H +#error "Don't include this file directly, include <mach/board.h>" +#endif + +#define GPIO_TOUCH_RESET 145 +#define GPIO_TOUCH_IRQ 144 + +#define GPIO_MAIN_SENSOR_RESET 44 +#define GPIO_MAIN_SENSOR_PWN 46 +#define GPIO_SUB_SENSOR_RESET 45 +#define GPIO_SUB_SENSOR_PWN 47 + +#define USB_OTG_CABLE_DETECT 126 + +#define SPRD_FLASH_OFST 0x890 +#define SPRD_FLASH_CTRL_BIT 0x8000 +#define SPRD_FLASH_LOW_VAL 0x3 +#define SPRD_FLASH_HIGH_VAL 0xF +#define SPRD_FLASH_LOW_CUR 110 +#define SPRD_FLASH_HIGH_CUR 470 + +#define GPIO_KEY_VOLUMEDOWN 124 +#define GPIO_KEY_VOLUMEUP 125 +//#define GPIO_KEY_CAMERA 0 +//#define GPIO_KEY_HOME 0 + +#define EIC_CHARGER_DETECT (A_EIC_START + 0) +#define EIC_POWER_PBINT2 (A_EIC_START + 1) +#define EIC_POWER_PBINT (A_EIC_START + 2) +#define EIC_AUD_HEAD_BUTTON (A_EIC_START + 3) +#define EIC_CHG_CV_STATE (A_EIC_START + 4) +#define EIC_AUD_HEAD_INST (A_EIC_START + 5) +#define EIC_VCHG_OVI (A_EIC_START + 6) +#define EIC_VBAT_OVI (A_EIC_START + 7) +#define EIC_AUD_HEAD_INST2 (A_EIC_START + 8) + +#define EIC_KEY_POWER (EIC_POWER_PBINT) + +#define HEADSET_BUTTON_GPIO (EIC_AUD_HEAD_BUTTON) +#define HEADSET_DETECT_GPIO (EIC_AUD_HEAD_INST2) +#define HEADSET_SWITCH_GPIO 0 + +#define HEADSET_IRQ_TRIGGER_LEVEL_DETECT 1 +#define HEADSET_IRQ_TRIGGER_LEVEL_BUTTON 1 + +#define HEADSET_ADC_MIN_KEY_MEDIA 0 +#define HEADSET_ADC_MAX_KEY_MEDIA 170 +#define HEADSET_ADC_MIN_KEY_VOLUMEUP 171 +#define HEADSET_ADC_MAX_KEY_VOLUMEUP 430 +#define HEADSET_ADC_MIN_KEY_VOLUMEDOWN 431 +#define HEADSET_ADC_MAX_KEY_VOLUMEDOWN 760 +#define HEADSET_ADC_THRESHOLD_3POLE_DETECT 100 +#define HEADSET_ADC_THRESHOLD_4POLE_DETECT 3100 +#define HEADSET_IRQ_THRESHOLD_BUTTON 1 +#define HEADSET_HEADMICBIAS_VOLTAGE 3000000 + +#define SPI0_CMMB_CS_GPIO 32 +#define SPI1_WIFI_CS_GPIO 44 + +#define GPIO_BK 143 +#define MSENSOR_DRDY_GPIO 53 +#define GPIO_PLSENSOR_IRQ 213 +/*For bcm4343 power on/off and sleep/wake */ +#define GPIO_BT_RESET 122 +#define GPIO_BT_POWER 131 +#define GPIO_BT2AP_WAKE 133 +#define GPIO_AP2BT_WAKE 132 + +/*#define GPIO_BT_RESET 194 */ +#define GPIO_WIFI_POWERON 189 +#define GPIO_WIFI_SHUTDOWN 130 +#define GPIO_WIFI_IRQ 97 + +#define GPIO_PROX_INT 140 +#define GPIO_GPS_ONOFF 174 + +#define GPIO_SDIO_DETECT 75 + +#define SPRD_PIN_SDIO0_OFFSET 0x01E0 +#define SPRD_PIN_SDIO0_SIZE 7 +#define SPRD_PIN_SDIO0_D3_INDEX 0 +#define SPRD_PIN_SDIO0_D3_GPIO 100 +#define SPRD_PIN_SDIO0_SD_FUNC 0 +#define SPRD_PIN_SDIO0_GPIO_FUNC 3 + +#define SIPC_SMEM_ADDR (CONFIG_PHYS_OFFSET + 120 * SZ_1M) +#define CPT_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#define CPT_TOTAL_SIZE (SZ_1M * 18) +#define CPT_RING_ADDR (CPT_START_ADDR + CPT_TOTAL_SIZE - SZ_4K) +#define CPT_RING_SIZE (SZ_4K) +#define CPT_SMEM_SIZE (SZ_1M * 2) +#define CPW_START_ADDR (CONFIG_PHYS_OFFSET + 150 * SZ_1M) +#define CPW_TOTAL_SIZE (SZ_1M * 33) +#define CPW_RING_ADDR (CPW_START_ADDR + CPW_TOTAL_SIZE - SZ_4K) +#define CPW_RING_SIZE (SZ_4K) +#define CPW_SMEM_SIZE (SZ_1M * 2) +#define WCN_START_ADDR (CONFIG_PHYS_OFFSET + 320 * SZ_1M) +#define WCN_TOTAL_SIZE (SZ_1M * 5) +#define WCN_RING_ADDR (WCN_START_ADDR + WCN_TOTAL_SIZE - SZ_4K) +#define WCN_RING_SIZE (SZ_4K) +#define WCN_SMEM_SIZE (SZ_1M * 2) +#define GGE_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#define GGE_TOTAL_SIZE (SZ_1M * 22) +#define GGE_RING_ADDR (GGE_START_ADDR + GGE_TOTAL_SIZE - SZ_4K) +#define GGE_RING_SIZE (SZ_4K) +#define GGE_SMEM_SIZE (SZ_1M * 2) +#define LTE_START_ADDR (CONFIG_PHYS_OFFSET + 150 * SZ_1M) +#define LTE_TOTAL_SIZE (SZ_1M * 83) +#define LTE_RING_ADDR (LTE_START_ADDR + LTE_TOTAL_SIZE - SZ_4K) +#define LTE_RING_SIZE (SZ_4K) +#define LTE_SMEM_SIZE (SZ_1M * 2) +#endif diff --git a/include/soc/sprd/__board-sp7720ea.h b/include/soc/sprd/__board-sp7720ea.h new file mode 100644 index 00000000..c4b3f6cd --- /dev/null +++ b/include/soc/sprd/__board-sp7720ea.h @@ -0,0 +1,115 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __GPIO_SCX30G_sp7720ea_H__ +#define __GPIO_SCX30G_sp7720ea_H__ + +#ifndef __ASM_ARCH_BOARD_H +#error "Don't include this file directly, include <mach/board.h>" +#endif + +#define GPIO_TOUCH_RESET 81 +#define GPIO_TOUCH_IRQ 82 + +#define GPIO_SENSOR_RESET 186//41 +#define GPIO_MAIN_SENSOR_PWN 187//42 +#define GPIO_SUB_SENSOR_PWN 188//43 + +#define SPRD_FLASH_OFST 0x890 +#define SPRD_FLASH_CTRL_BIT 0x8000 +#define SPRD_FLASH_LOW_VAL 0x3 +#define SPRD_FLASH_HIGH_VAL 0xF +#define SPRD_FLASH_LOW_CUR 110 +#define SPRD_FLASH_HIGH_CUR 470 + +#define USB_OTG_CABLE_DETECT 72 + +#define EIC_CHARGER_DETECT (A_EIC_START + 0) +#define EIC_POWER_PBINT2 (A_EIC_START + 1) +#define EIC_POWER_PBINT (A_EIC_START + 2) +#define EIC_AUD_HEAD_BUTTON (A_EIC_START + 3) +#define EIC_CHG_CV_STATE (A_EIC_START + 4) +#define EIC_AUD_HEAD_INST (A_EIC_START + 5) +#define EIC_VCHG_OVI (A_EIC_START + 6) +#define EIC_VBAT_OVI (A_EIC_START + 7) +#define EIC_AUD_HEAD_INST2 (A_EIC_START + 8) + + +#define EIC_KEY_POWER (EIC_POWER_PBINT) +#define HEADSET_BUTTON_GPIO (EIC_AUD_HEAD_BUTTON) +#define HEADSET_DETECT_GPIO (EIC_AUD_HEAD_INST2) +#define HEADSET_SWITCH_GPIO 0 + +#define HEADSET_IRQ_TRIGGER_LEVEL_DETECT 1 +#define HEADSET_IRQ_TRIGGER_LEVEL_BUTTON 1 + +#define HEADSET_ADC_MIN_KEY_MEDIA 0 +#define HEADSET_ADC_MAX_KEY_MEDIA 170 +#define HEADSET_ADC_MIN_KEY_VOLUMEUP 171 +#define HEADSET_ADC_MAX_KEY_VOLUMEUP 430 +#define HEADSET_ADC_MIN_KEY_VOLUMEDOWN 431 +#define HEADSET_ADC_MAX_KEY_VOLUMEDOWN 760 +#define HEADSET_ADC_THRESHOLD_3POLE_DETECT 100 +#define HEADSET_ADC_THRESHOLD_4POLE_DETECT 3100 +#define HEADSET_IRQ_THRESHOLD_BUTTON 1 +#define HEADSET_HEADMICBIAS_VOLTAGE 3000000 + +#define SPI0_CMMB_CS_GPIO 156 +#define SPI1_WIFI_CS_GPIO 44 + +#define GPIO_BK 136 + +#define GPIO_CMMB_RESET 144 +#define GPIO_CMMB_INT 143 +#define GPIO_CMMB_26M_CLK_EN 197 + +#define GPIO_BT_RESET 233 +#define GPIO_BT_POWER 231 +#define GPIO_BT2AP_WAKE 232 +#define GPIO_AP2BT_WAKE 235 + +#define GPIO_WIFI_SHUTDOWN 230 +#define GPIO_WIFI_IRQ 234 + +#define GPIO_PROX_INT 216 +#define GPIO_GYRO_INT1 163 +#define GPIO_M_RSTN 161 +#define GPIO_M_DRDY 164 + +#define GPIO_SDIO_DETECT 75 + +#define SPRD_PIN_SDIO0_OFFSET 0x0184 +#define SPRD_PIN_SDIO0_SIZE 7 +#define SPRD_PIN_SDIO0_D3_INDEX 0 +#define SPRD_PIN_SDIO0_D3_GPIO 100 +#define SPRD_PIN_SDIO0_SD_FUNC 0 +#define SPRD_PIN_SDIO0_GPIO_FUNC 3 + +/* ION config info +LCD: + 960x540 + +Video Playing: + 1080p 8 ref-frame + +Video Recording: + 720p + +Camera: + 8M, support ZSL, support preview/capture rotation +*/ + +#define SPRD_ION_MM_SIZE (52 * SZ_1M) +#define SPRD_ION_OVERLAY_SIZE (4 * SZ_1M) + +#endif diff --git a/include/soc/sprd/__board-sp7731gea.h b/include/soc/sprd/__board-sp7731gea.h new file mode 100644 index 00000000..c41da938 --- /dev/null +++ b/include/soc/sprd/__board-sp7731gea.h @@ -0,0 +1,113 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __GPIO_SCX35GA_H__ +#define __GPIO_SCX35GA_H__ + +#ifndef __ASM_ARCH_BOARD_H +#error "Don't include this file directly, include <mach/board.h>" +#endif + +#define GPIO_TOUCH_RESET 81 +#define GPIO_TOUCH_IRQ 82 + +#define GPIO_SENSOR_RESET 186//41 +#define GPIO_MAIN_SENSOR_PWN 187//42 +#define GPIO_SUB_SENSOR_PWN 188//43 + +#define SPRD_FLASH_OFST 0x890 +#define SPRD_FLASH_CTRL_BIT 0x8000 +#define SPRD_FLASH_LOW_VAL 0x3 +#define SPRD_FLASH_HIGH_VAL 0xF +#define SPRD_FLASH_LOW_CUR 110 +#define SPRD_FLASH_HIGH_CUR 470 + +#define USB_OTG_CABLE_DETECT 72 + +#define EIC_CHARGER_DETECT (A_EIC_START + 0) +#define EIC_POWER_PBINT2 (A_EIC_START + 1) +#define EIC_POWER_PBINT (A_EIC_START + 2) +#define EIC_AUD_HEAD_BUTTON (A_EIC_START + 3) +#define EIC_CHG_CV_STATE (A_EIC_START + 4) +#define EIC_AUD_HEAD_INST2 (A_EIC_START + 5) +#define EIC_VCHG_OVI (A_EIC_START + 6) +#define EIC_VBAT_OVI (A_EIC_START + 7) + +#define EIC_KEY_POWER (EIC_POWER_PBINT) +#define HEADSET_BUTTON_GPIO (EIC_AUD_HEAD_BUTTON) +#define HEADSET_DETECT_GPIO (EIC_AUD_HEAD_INST2) +#define HEADSET_SWITCH_GPIO 0 + +#define HEADSET_IRQ_TRIGGER_LEVEL_DETECT 1 +#define HEADSET_IRQ_TRIGGER_LEVEL_BUTTON 1 + +#define HEADSET_ADC_MIN_KEY_MEDIA 0 +#define HEADSET_ADC_MAX_KEY_MEDIA 170 +#define HEADSET_ADC_MIN_KEY_VOLUMEUP 171 +#define HEADSET_ADC_MAX_KEY_VOLUMEUP 430 +#define HEADSET_ADC_MIN_KEY_VOLUMEDOWN 431 +#define HEADSET_ADC_MAX_KEY_VOLUMEDOWN 760 +#define HEADSET_ADC_THRESHOLD_3POLE_DETECT 100 +#define HEADSET_ADC_THRESHOLD_4POLE_DETECT 3100 +#define HEADSET_IRQ_THRESHOLD_BUTTON 1 +#define HEADSET_HEADMICBIAS_VOLTAGE 3000000 + +#define SPI0_CMMB_CS_GPIO 156 +#define SPI1_WIFI_CS_GPIO 44 + +#define GPIO_BK 136 + +#define GPIO_CMMB_RESET 144 +#define GPIO_CMMB_INT 143 +#define GPIO_CMMB_26M_CLK_EN 197 + +#define GPIO_BT_RESET 233 +#define GPIO_BT_POWER 231 +#define GPIO_BT2AP_WAKE 232 +#define GPIO_AP2BT_WAKE 235 + +#define GPIO_WIFI_SHUTDOWN 230 +#define GPIO_WIFI_IRQ 234 + +#define GPIO_PROX_INT 216 +#define GPIO_GYRO_INT1 163 +#define GPIO_M_RSTN 161 +#define GPIO_M_DRDY 164 + +#define GPIO_SDIO_DETECT 75 + +#define SPRD_PIN_SDIO0_OFFSET 0x0184 +#define SPRD_PIN_SDIO0_SIZE 7 +#define SPRD_PIN_SDIO0_D3_INDEX 0 +#define SPRD_PIN_SDIO0_D3_GPIO 100 +#define SPRD_PIN_SDIO0_SD_FUNC 0 +#define SPRD_PIN_SDIO0_GPIO_FUNC 3 + +/* ION config info +LCD: + 960x540 + +Video Playing: + 1080p 8 ref-frame + +Video Recording: + 720p + +Camera: + 8M, support ZSL, support preview/capture rotation +*/ + +#define SPRD_ION_MM_SIZE (52 * SZ_1M) +#define SPRD_ION_OVERLAY_SIZE (4 * SZ_1M) + +#endif diff --git a/include/soc/sprd/__board-sp7731gea_hd.h b/include/soc/sprd/__board-sp7731gea_hd.h new file mode 100644 index 00000000..c41da938 --- /dev/null +++ b/include/soc/sprd/__board-sp7731gea_hd.h @@ -0,0 +1,113 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __GPIO_SCX35GA_H__ +#define __GPIO_SCX35GA_H__ + +#ifndef __ASM_ARCH_BOARD_H +#error "Don't include this file directly, include <mach/board.h>" +#endif + +#define GPIO_TOUCH_RESET 81 +#define GPIO_TOUCH_IRQ 82 + +#define GPIO_SENSOR_RESET 186//41 +#define GPIO_MAIN_SENSOR_PWN 187//42 +#define GPIO_SUB_SENSOR_PWN 188//43 + +#define SPRD_FLASH_OFST 0x890 +#define SPRD_FLASH_CTRL_BIT 0x8000 +#define SPRD_FLASH_LOW_VAL 0x3 +#define SPRD_FLASH_HIGH_VAL 0xF +#define SPRD_FLASH_LOW_CUR 110 +#define SPRD_FLASH_HIGH_CUR 470 + +#define USB_OTG_CABLE_DETECT 72 + +#define EIC_CHARGER_DETECT (A_EIC_START + 0) +#define EIC_POWER_PBINT2 (A_EIC_START + 1) +#define EIC_POWER_PBINT (A_EIC_START + 2) +#define EIC_AUD_HEAD_BUTTON (A_EIC_START + 3) +#define EIC_CHG_CV_STATE (A_EIC_START + 4) +#define EIC_AUD_HEAD_INST2 (A_EIC_START + 5) +#define EIC_VCHG_OVI (A_EIC_START + 6) +#define EIC_VBAT_OVI (A_EIC_START + 7) + +#define EIC_KEY_POWER (EIC_POWER_PBINT) +#define HEADSET_BUTTON_GPIO (EIC_AUD_HEAD_BUTTON) +#define HEADSET_DETECT_GPIO (EIC_AUD_HEAD_INST2) +#define HEADSET_SWITCH_GPIO 0 + +#define HEADSET_IRQ_TRIGGER_LEVEL_DETECT 1 +#define HEADSET_IRQ_TRIGGER_LEVEL_BUTTON 1 + +#define HEADSET_ADC_MIN_KEY_MEDIA 0 +#define HEADSET_ADC_MAX_KEY_MEDIA 170 +#define HEADSET_ADC_MIN_KEY_VOLUMEUP 171 +#define HEADSET_ADC_MAX_KEY_VOLUMEUP 430 +#define HEADSET_ADC_MIN_KEY_VOLUMEDOWN 431 +#define HEADSET_ADC_MAX_KEY_VOLUMEDOWN 760 +#define HEADSET_ADC_THRESHOLD_3POLE_DETECT 100 +#define HEADSET_ADC_THRESHOLD_4POLE_DETECT 3100 +#define HEADSET_IRQ_THRESHOLD_BUTTON 1 +#define HEADSET_HEADMICBIAS_VOLTAGE 3000000 + +#define SPI0_CMMB_CS_GPIO 156 +#define SPI1_WIFI_CS_GPIO 44 + +#define GPIO_BK 136 + +#define GPIO_CMMB_RESET 144 +#define GPIO_CMMB_INT 143 +#define GPIO_CMMB_26M_CLK_EN 197 + +#define GPIO_BT_RESET 233 +#define GPIO_BT_POWER 231 +#define GPIO_BT2AP_WAKE 232 +#define GPIO_AP2BT_WAKE 235 + +#define GPIO_WIFI_SHUTDOWN 230 +#define GPIO_WIFI_IRQ 234 + +#define GPIO_PROX_INT 216 +#define GPIO_GYRO_INT1 163 +#define GPIO_M_RSTN 161 +#define GPIO_M_DRDY 164 + +#define GPIO_SDIO_DETECT 75 + +#define SPRD_PIN_SDIO0_OFFSET 0x0184 +#define SPRD_PIN_SDIO0_SIZE 7 +#define SPRD_PIN_SDIO0_D3_INDEX 0 +#define SPRD_PIN_SDIO0_D3_GPIO 100 +#define SPRD_PIN_SDIO0_SD_FUNC 0 +#define SPRD_PIN_SDIO0_GPIO_FUNC 3 + +/* ION config info +LCD: + 960x540 + +Video Playing: + 1080p 8 ref-frame + +Video Recording: + 720p + +Camera: + 8M, support ZSL, support preview/capture rotation +*/ + +#define SPRD_ION_MM_SIZE (52 * SZ_1M) +#define SPRD_ION_OVERLAY_SIZE (4 * SZ_1M) + +#endif diff --git a/include/soc/sprd/__board-sp7731gea_hd2.h b/include/soc/sprd/__board-sp7731gea_hd2.h new file mode 100644 index 00000000..c41da938 --- /dev/null +++ b/include/soc/sprd/__board-sp7731gea_hd2.h @@ -0,0 +1,113 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __GPIO_SCX35GA_H__ +#define __GPIO_SCX35GA_H__ + +#ifndef __ASM_ARCH_BOARD_H +#error "Don't include this file directly, include <mach/board.h>" +#endif + +#define GPIO_TOUCH_RESET 81 +#define GPIO_TOUCH_IRQ 82 + +#define GPIO_SENSOR_RESET 186//41 +#define GPIO_MAIN_SENSOR_PWN 187//42 +#define GPIO_SUB_SENSOR_PWN 188//43 + +#define SPRD_FLASH_OFST 0x890 +#define SPRD_FLASH_CTRL_BIT 0x8000 +#define SPRD_FLASH_LOW_VAL 0x3 +#define SPRD_FLASH_HIGH_VAL 0xF +#define SPRD_FLASH_LOW_CUR 110 +#define SPRD_FLASH_HIGH_CUR 470 + +#define USB_OTG_CABLE_DETECT 72 + +#define EIC_CHARGER_DETECT (A_EIC_START + 0) +#define EIC_POWER_PBINT2 (A_EIC_START + 1) +#define EIC_POWER_PBINT (A_EIC_START + 2) +#define EIC_AUD_HEAD_BUTTON (A_EIC_START + 3) +#define EIC_CHG_CV_STATE (A_EIC_START + 4) +#define EIC_AUD_HEAD_INST2 (A_EIC_START + 5) +#define EIC_VCHG_OVI (A_EIC_START + 6) +#define EIC_VBAT_OVI (A_EIC_START + 7) + +#define EIC_KEY_POWER (EIC_POWER_PBINT) +#define HEADSET_BUTTON_GPIO (EIC_AUD_HEAD_BUTTON) +#define HEADSET_DETECT_GPIO (EIC_AUD_HEAD_INST2) +#define HEADSET_SWITCH_GPIO 0 + +#define HEADSET_IRQ_TRIGGER_LEVEL_DETECT 1 +#define HEADSET_IRQ_TRIGGER_LEVEL_BUTTON 1 + +#define HEADSET_ADC_MIN_KEY_MEDIA 0 +#define HEADSET_ADC_MAX_KEY_MEDIA 170 +#define HEADSET_ADC_MIN_KEY_VOLUMEUP 171 +#define HEADSET_ADC_MAX_KEY_VOLUMEUP 430 +#define HEADSET_ADC_MIN_KEY_VOLUMEDOWN 431 +#define HEADSET_ADC_MAX_KEY_VOLUMEDOWN 760 +#define HEADSET_ADC_THRESHOLD_3POLE_DETECT 100 +#define HEADSET_ADC_THRESHOLD_4POLE_DETECT 3100 +#define HEADSET_IRQ_THRESHOLD_BUTTON 1 +#define HEADSET_HEADMICBIAS_VOLTAGE 3000000 + +#define SPI0_CMMB_CS_GPIO 156 +#define SPI1_WIFI_CS_GPIO 44 + +#define GPIO_BK 136 + +#define GPIO_CMMB_RESET 144 +#define GPIO_CMMB_INT 143 +#define GPIO_CMMB_26M_CLK_EN 197 + +#define GPIO_BT_RESET 233 +#define GPIO_BT_POWER 231 +#define GPIO_BT2AP_WAKE 232 +#define GPIO_AP2BT_WAKE 235 + +#define GPIO_WIFI_SHUTDOWN 230 +#define GPIO_WIFI_IRQ 234 + +#define GPIO_PROX_INT 216 +#define GPIO_GYRO_INT1 163 +#define GPIO_M_RSTN 161 +#define GPIO_M_DRDY 164 + +#define GPIO_SDIO_DETECT 75 + +#define SPRD_PIN_SDIO0_OFFSET 0x0184 +#define SPRD_PIN_SDIO0_SIZE 7 +#define SPRD_PIN_SDIO0_D3_INDEX 0 +#define SPRD_PIN_SDIO0_D3_GPIO 100 +#define SPRD_PIN_SDIO0_SD_FUNC 0 +#define SPRD_PIN_SDIO0_GPIO_FUNC 3 + +/* ION config info +LCD: + 960x540 + +Video Playing: + 1080p 8 ref-frame + +Video Recording: + 720p + +Camera: + 8M, support ZSL, support preview/capture rotation +*/ + +#define SPRD_ION_MM_SIZE (52 * SZ_1M) +#define SPRD_ION_OVERLAY_SIZE (4 * SZ_1M) + +#endif diff --git a/include/soc/sprd/__board-sp7731gea_hdr.h b/include/soc/sprd/__board-sp7731gea_hdr.h new file mode 100644 index 00000000..c41da938 --- /dev/null +++ b/include/soc/sprd/__board-sp7731gea_hdr.h @@ -0,0 +1,113 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __GPIO_SCX35GA_H__ +#define __GPIO_SCX35GA_H__ + +#ifndef __ASM_ARCH_BOARD_H +#error "Don't include this file directly, include <mach/board.h>" +#endif + +#define GPIO_TOUCH_RESET 81 +#define GPIO_TOUCH_IRQ 82 + +#define GPIO_SENSOR_RESET 186//41 +#define GPIO_MAIN_SENSOR_PWN 187//42 +#define GPIO_SUB_SENSOR_PWN 188//43 + +#define SPRD_FLASH_OFST 0x890 +#define SPRD_FLASH_CTRL_BIT 0x8000 +#define SPRD_FLASH_LOW_VAL 0x3 +#define SPRD_FLASH_HIGH_VAL 0xF +#define SPRD_FLASH_LOW_CUR 110 +#define SPRD_FLASH_HIGH_CUR 470 + +#define USB_OTG_CABLE_DETECT 72 + +#define EIC_CHARGER_DETECT (A_EIC_START + 0) +#define EIC_POWER_PBINT2 (A_EIC_START + 1) +#define EIC_POWER_PBINT (A_EIC_START + 2) +#define EIC_AUD_HEAD_BUTTON (A_EIC_START + 3) +#define EIC_CHG_CV_STATE (A_EIC_START + 4) +#define EIC_AUD_HEAD_INST2 (A_EIC_START + 5) +#define EIC_VCHG_OVI (A_EIC_START + 6) +#define EIC_VBAT_OVI (A_EIC_START + 7) + +#define EIC_KEY_POWER (EIC_POWER_PBINT) +#define HEADSET_BUTTON_GPIO (EIC_AUD_HEAD_BUTTON) +#define HEADSET_DETECT_GPIO (EIC_AUD_HEAD_INST2) +#define HEADSET_SWITCH_GPIO 0 + +#define HEADSET_IRQ_TRIGGER_LEVEL_DETECT 1 +#define HEADSET_IRQ_TRIGGER_LEVEL_BUTTON 1 + +#define HEADSET_ADC_MIN_KEY_MEDIA 0 +#define HEADSET_ADC_MAX_KEY_MEDIA 170 +#define HEADSET_ADC_MIN_KEY_VOLUMEUP 171 +#define HEADSET_ADC_MAX_KEY_VOLUMEUP 430 +#define HEADSET_ADC_MIN_KEY_VOLUMEDOWN 431 +#define HEADSET_ADC_MAX_KEY_VOLUMEDOWN 760 +#define HEADSET_ADC_THRESHOLD_3POLE_DETECT 100 +#define HEADSET_ADC_THRESHOLD_4POLE_DETECT 3100 +#define HEADSET_IRQ_THRESHOLD_BUTTON 1 +#define HEADSET_HEADMICBIAS_VOLTAGE 3000000 + +#define SPI0_CMMB_CS_GPIO 156 +#define SPI1_WIFI_CS_GPIO 44 + +#define GPIO_BK 136 + +#define GPIO_CMMB_RESET 144 +#define GPIO_CMMB_INT 143 +#define GPIO_CMMB_26M_CLK_EN 197 + +#define GPIO_BT_RESET 233 +#define GPIO_BT_POWER 231 +#define GPIO_BT2AP_WAKE 232 +#define GPIO_AP2BT_WAKE 235 + +#define GPIO_WIFI_SHUTDOWN 230 +#define GPIO_WIFI_IRQ 234 + +#define GPIO_PROX_INT 216 +#define GPIO_GYRO_INT1 163 +#define GPIO_M_RSTN 161 +#define GPIO_M_DRDY 164 + +#define GPIO_SDIO_DETECT 75 + +#define SPRD_PIN_SDIO0_OFFSET 0x0184 +#define SPRD_PIN_SDIO0_SIZE 7 +#define SPRD_PIN_SDIO0_D3_INDEX 0 +#define SPRD_PIN_SDIO0_D3_GPIO 100 +#define SPRD_PIN_SDIO0_SD_FUNC 0 +#define SPRD_PIN_SDIO0_GPIO_FUNC 3 + +/* ION config info +LCD: + 960x540 + +Video Playing: + 1080p 8 ref-frame + +Video Recording: + 720p + +Camera: + 8M, support ZSL, support preview/capture rotation +*/ + +#define SPRD_ION_MM_SIZE (52 * SZ_1M) +#define SPRD_ION_OVERLAY_SIZE (4 * SZ_1M) + +#endif diff --git a/include/soc/sprd/__board-sp7731gea_qhd.h b/include/soc/sprd/__board-sp7731gea_qhd.h new file mode 100644 index 00000000..c41da938 --- /dev/null +++ b/include/soc/sprd/__board-sp7731gea_qhd.h @@ -0,0 +1,113 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __GPIO_SCX35GA_H__ +#define __GPIO_SCX35GA_H__ + +#ifndef __ASM_ARCH_BOARD_H +#error "Don't include this file directly, include <mach/board.h>" +#endif + +#define GPIO_TOUCH_RESET 81 +#define GPIO_TOUCH_IRQ 82 + +#define GPIO_SENSOR_RESET 186//41 +#define GPIO_MAIN_SENSOR_PWN 187//42 +#define GPIO_SUB_SENSOR_PWN 188//43 + +#define SPRD_FLASH_OFST 0x890 +#define SPRD_FLASH_CTRL_BIT 0x8000 +#define SPRD_FLASH_LOW_VAL 0x3 +#define SPRD_FLASH_HIGH_VAL 0xF +#define SPRD_FLASH_LOW_CUR 110 +#define SPRD_FLASH_HIGH_CUR 470 + +#define USB_OTG_CABLE_DETECT 72 + +#define EIC_CHARGER_DETECT (A_EIC_START + 0) +#define EIC_POWER_PBINT2 (A_EIC_START + 1) +#define EIC_POWER_PBINT (A_EIC_START + 2) +#define EIC_AUD_HEAD_BUTTON (A_EIC_START + 3) +#define EIC_CHG_CV_STATE (A_EIC_START + 4) +#define EIC_AUD_HEAD_INST2 (A_EIC_START + 5) +#define EIC_VCHG_OVI (A_EIC_START + 6) +#define EIC_VBAT_OVI (A_EIC_START + 7) + +#define EIC_KEY_POWER (EIC_POWER_PBINT) +#define HEADSET_BUTTON_GPIO (EIC_AUD_HEAD_BUTTON) +#define HEADSET_DETECT_GPIO (EIC_AUD_HEAD_INST2) +#define HEADSET_SWITCH_GPIO 0 + +#define HEADSET_IRQ_TRIGGER_LEVEL_DETECT 1 +#define HEADSET_IRQ_TRIGGER_LEVEL_BUTTON 1 + +#define HEADSET_ADC_MIN_KEY_MEDIA 0 +#define HEADSET_ADC_MAX_KEY_MEDIA 170 +#define HEADSET_ADC_MIN_KEY_VOLUMEUP 171 +#define HEADSET_ADC_MAX_KEY_VOLUMEUP 430 +#define HEADSET_ADC_MIN_KEY_VOLUMEDOWN 431 +#define HEADSET_ADC_MAX_KEY_VOLUMEDOWN 760 +#define HEADSET_ADC_THRESHOLD_3POLE_DETECT 100 +#define HEADSET_ADC_THRESHOLD_4POLE_DETECT 3100 +#define HEADSET_IRQ_THRESHOLD_BUTTON 1 +#define HEADSET_HEADMICBIAS_VOLTAGE 3000000 + +#define SPI0_CMMB_CS_GPIO 156 +#define SPI1_WIFI_CS_GPIO 44 + +#define GPIO_BK 136 + +#define GPIO_CMMB_RESET 144 +#define GPIO_CMMB_INT 143 +#define GPIO_CMMB_26M_CLK_EN 197 + +#define GPIO_BT_RESET 233 +#define GPIO_BT_POWER 231 +#define GPIO_BT2AP_WAKE 232 +#define GPIO_AP2BT_WAKE 235 + +#define GPIO_WIFI_SHUTDOWN 230 +#define GPIO_WIFI_IRQ 234 + +#define GPIO_PROX_INT 216 +#define GPIO_GYRO_INT1 163 +#define GPIO_M_RSTN 161 +#define GPIO_M_DRDY 164 + +#define GPIO_SDIO_DETECT 75 + +#define SPRD_PIN_SDIO0_OFFSET 0x0184 +#define SPRD_PIN_SDIO0_SIZE 7 +#define SPRD_PIN_SDIO0_D3_INDEX 0 +#define SPRD_PIN_SDIO0_D3_GPIO 100 +#define SPRD_PIN_SDIO0_SD_FUNC 0 +#define SPRD_PIN_SDIO0_GPIO_FUNC 3 + +/* ION config info +LCD: + 960x540 + +Video Playing: + 1080p 8 ref-frame + +Video Recording: + 720p + +Camera: + 8M, support ZSL, support preview/capture rotation +*/ + +#define SPRD_ION_MM_SIZE (52 * SZ_1M) +#define SPRD_ION_OVERLAY_SIZE (4 * SZ_1M) + +#endif diff --git a/include/soc/sprd/__board-sp7731gepike.h b/include/soc/sprd/__board-sp7731gepike.h new file mode 100644 index 00000000..c41da938 --- /dev/null +++ b/include/soc/sprd/__board-sp7731gepike.h @@ -0,0 +1,113 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __GPIO_SCX35GA_H__ +#define __GPIO_SCX35GA_H__ + +#ifndef __ASM_ARCH_BOARD_H +#error "Don't include this file directly, include <mach/board.h>" +#endif + +#define GPIO_TOUCH_RESET 81 +#define GPIO_TOUCH_IRQ 82 + +#define GPIO_SENSOR_RESET 186//41 +#define GPIO_MAIN_SENSOR_PWN 187//42 +#define GPIO_SUB_SENSOR_PWN 188//43 + +#define SPRD_FLASH_OFST 0x890 +#define SPRD_FLASH_CTRL_BIT 0x8000 +#define SPRD_FLASH_LOW_VAL 0x3 +#define SPRD_FLASH_HIGH_VAL 0xF +#define SPRD_FLASH_LOW_CUR 110 +#define SPRD_FLASH_HIGH_CUR 470 + +#define USB_OTG_CABLE_DETECT 72 + +#define EIC_CHARGER_DETECT (A_EIC_START + 0) +#define EIC_POWER_PBINT2 (A_EIC_START + 1) +#define EIC_POWER_PBINT (A_EIC_START + 2) +#define EIC_AUD_HEAD_BUTTON (A_EIC_START + 3) +#define EIC_CHG_CV_STATE (A_EIC_START + 4) +#define EIC_AUD_HEAD_INST2 (A_EIC_START + 5) +#define EIC_VCHG_OVI (A_EIC_START + 6) +#define EIC_VBAT_OVI (A_EIC_START + 7) + +#define EIC_KEY_POWER (EIC_POWER_PBINT) +#define HEADSET_BUTTON_GPIO (EIC_AUD_HEAD_BUTTON) +#define HEADSET_DETECT_GPIO (EIC_AUD_HEAD_INST2) +#define HEADSET_SWITCH_GPIO 0 + +#define HEADSET_IRQ_TRIGGER_LEVEL_DETECT 1 +#define HEADSET_IRQ_TRIGGER_LEVEL_BUTTON 1 + +#define HEADSET_ADC_MIN_KEY_MEDIA 0 +#define HEADSET_ADC_MAX_KEY_MEDIA 170 +#define HEADSET_ADC_MIN_KEY_VOLUMEUP 171 +#define HEADSET_ADC_MAX_KEY_VOLUMEUP 430 +#define HEADSET_ADC_MIN_KEY_VOLUMEDOWN 431 +#define HEADSET_ADC_MAX_KEY_VOLUMEDOWN 760 +#define HEADSET_ADC_THRESHOLD_3POLE_DETECT 100 +#define HEADSET_ADC_THRESHOLD_4POLE_DETECT 3100 +#define HEADSET_IRQ_THRESHOLD_BUTTON 1 +#define HEADSET_HEADMICBIAS_VOLTAGE 3000000 + +#define SPI0_CMMB_CS_GPIO 156 +#define SPI1_WIFI_CS_GPIO 44 + +#define GPIO_BK 136 + +#define GPIO_CMMB_RESET 144 +#define GPIO_CMMB_INT 143 +#define GPIO_CMMB_26M_CLK_EN 197 + +#define GPIO_BT_RESET 233 +#define GPIO_BT_POWER 231 +#define GPIO_BT2AP_WAKE 232 +#define GPIO_AP2BT_WAKE 235 + +#define GPIO_WIFI_SHUTDOWN 230 +#define GPIO_WIFI_IRQ 234 + +#define GPIO_PROX_INT 216 +#define GPIO_GYRO_INT1 163 +#define GPIO_M_RSTN 161 +#define GPIO_M_DRDY 164 + +#define GPIO_SDIO_DETECT 75 + +#define SPRD_PIN_SDIO0_OFFSET 0x0184 +#define SPRD_PIN_SDIO0_SIZE 7 +#define SPRD_PIN_SDIO0_D3_INDEX 0 +#define SPRD_PIN_SDIO0_D3_GPIO 100 +#define SPRD_PIN_SDIO0_SD_FUNC 0 +#define SPRD_PIN_SDIO0_GPIO_FUNC 3 + +/* ION config info +LCD: + 960x540 + +Video Playing: + 1080p 8 ref-frame + +Video Recording: + 720p + +Camera: + 8M, support ZSL, support preview/capture rotation +*/ + +#define SPRD_ION_MM_SIZE (52 * SZ_1M) +#define SPRD_ION_OVERLAY_SIZE (4 * SZ_1M) + +#endif diff --git a/include/soc/sprd/__board-sp7732Aea.h b/include/soc/sprd/__board-sp7732Aea.h new file mode 100644 index 00000000..eb4b6825 --- /dev/null +++ b/include/soc/sprd/__board-sp7732Aea.h @@ -0,0 +1,115 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __GPIO_SCX35GA_H__ +#define __GPIO_SCX35GA_H__ + +#ifndef __ASM_ARCH_BOARD_H +#error "Don't include this file directly, include <mach/board.h>" +#endif + +#define GPIO_TOUCH_RESET 81 +#define GPIO_TOUCH_IRQ 82 + +#define GPIO_SENSOR_RESET 186//41 +#define GPIO_MAIN_SENSOR_PWN 187//42 +#define GPIO_SUB_SENSOR_PWN 188//43 +#define GPIO_CAM_FLASH_EN 235 +#define GPIO_CAM_FLASH_MODE 234 + +#define SPRD_FLASH_OFST 0x890 +#define SPRD_FLASH_CTRL_BIT 0x8000 +#define SPRD_FLASH_LOW_VAL 0x3 +#define SPRD_FLASH_HIGH_VAL 0xF +#define SPRD_FLASH_LOW_CUR 110 +#define SPRD_FLASH_HIGH_CUR 470 + +#define USB_OTG_CABLE_DETECT 72 + +#define EIC_CHARGER_DETECT (A_EIC_START + 0) +#define EIC_POWER_PBINT2 (A_EIC_START + 1) +#define EIC_POWER_PBINT (A_EIC_START + 2) +#define EIC_AUD_HEAD_BUTTON (A_EIC_START + 3) +#define EIC_CHG_CV_STATE (A_EIC_START + 4) +#define EIC_AUD_HEAD_INST2 (A_EIC_START + 5) +#define EIC_VCHG_OVI (A_EIC_START + 6) +#define EIC_VBAT_OVI (A_EIC_START + 7) + +#define EIC_KEY_POWER (EIC_POWER_PBINT) +#define HEADSET_BUTTON_GPIO (EIC_AUD_HEAD_BUTTON) +#define HEADSET_DETECT_GPIO (EIC_AUD_HEAD_INST2) +#define HEADSET_SWITCH_GPIO 0 + +#define HEADSET_IRQ_TRIGGER_LEVEL_DETECT 1 +#define HEADSET_IRQ_TRIGGER_LEVEL_BUTTON 1 + +#define HEADSET_ADC_MIN_KEY_MEDIA 0 +#define HEADSET_ADC_MAX_KEY_MEDIA 170 +#define HEADSET_ADC_MIN_KEY_VOLUMEUP 171 +#define HEADSET_ADC_MAX_KEY_VOLUMEUP 430 +#define HEADSET_ADC_MIN_KEY_VOLUMEDOWN 431 +#define HEADSET_ADC_MAX_KEY_VOLUMEDOWN 760 +#define HEADSET_ADC_THRESHOLD_3POLE_DETECT 100 +#define HEADSET_ADC_THRESHOLD_4POLE_DETECT 3100 +#define HEADSET_IRQ_THRESHOLD_BUTTON 1 +#define HEADSET_HEADMICBIAS_VOLTAGE 3000000 + +#define SPI0_CMMB_CS_GPIO 156 +#define SPI1_WIFI_CS_GPIO 44 + +#define GPIO_BK 136 + +#define GPIO_CMMB_RESET 144 +#define GPIO_CMMB_INT 143 +#define GPIO_CMMB_26M_CLK_EN 197 + +#define GPIO_BT_RESET 233 +#define GPIO_BT_POWER 231 +#define GPIO_BT2AP_WAKE 232 +#define GPIO_AP2BT_WAKE 235 + +#define GPIO_WIFI_SHUTDOWN 230 +#define GPIO_WIFI_IRQ 234 + +#define GPIO_PROX_INT 216 +#define GPIO_GYRO_INT1 163 +#define GPIO_M_RSTN 161 +#define GPIO_M_DRDY 164 + +#define GPIO_SDIO_DETECT 75 + +#define SPRD_PIN_SDIO0_OFFSET 0x0184 +#define SPRD_PIN_SDIO0_SIZE 7 +#define SPRD_PIN_SDIO0_D3_INDEX 0 +#define SPRD_PIN_SDIO0_D3_GPIO 100 +#define SPRD_PIN_SDIO0_SD_FUNC 0 +#define SPRD_PIN_SDIO0_GPIO_FUNC 3 + +/* ION config info +LCD: + 960x540 + +Video Playing: + 1080p 8 ref-frame + +Video Recording: + 720p + +Camera: + 8M, support ZSL, support preview/capture rotation +*/ + +#define SPRD_ION_MM_SIZE (52 * SZ_1M) +#define SPRD_ION_OVERLAY_SIZE (4 * SZ_1M) + +#endif diff --git a/include/soc/sprd/__board-sp8730seea.h b/include/soc/sprd/__board-sp8730seea.h new file mode 100644 index 00000000..eb4b6825 --- /dev/null +++ b/include/soc/sprd/__board-sp8730seea.h @@ -0,0 +1,115 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __GPIO_SCX35GA_H__ +#define __GPIO_SCX35GA_H__ + +#ifndef __ASM_ARCH_BOARD_H +#error "Don't include this file directly, include <mach/board.h>" +#endif + +#define GPIO_TOUCH_RESET 81 +#define GPIO_TOUCH_IRQ 82 + +#define GPIO_SENSOR_RESET 186//41 +#define GPIO_MAIN_SENSOR_PWN 187//42 +#define GPIO_SUB_SENSOR_PWN 188//43 +#define GPIO_CAM_FLASH_EN 235 +#define GPIO_CAM_FLASH_MODE 234 + +#define SPRD_FLASH_OFST 0x890 +#define SPRD_FLASH_CTRL_BIT 0x8000 +#define SPRD_FLASH_LOW_VAL 0x3 +#define SPRD_FLASH_HIGH_VAL 0xF +#define SPRD_FLASH_LOW_CUR 110 +#define SPRD_FLASH_HIGH_CUR 470 + +#define USB_OTG_CABLE_DETECT 72 + +#define EIC_CHARGER_DETECT (A_EIC_START + 0) +#define EIC_POWER_PBINT2 (A_EIC_START + 1) +#define EIC_POWER_PBINT (A_EIC_START + 2) +#define EIC_AUD_HEAD_BUTTON (A_EIC_START + 3) +#define EIC_CHG_CV_STATE (A_EIC_START + 4) +#define EIC_AUD_HEAD_INST2 (A_EIC_START + 5) +#define EIC_VCHG_OVI (A_EIC_START + 6) +#define EIC_VBAT_OVI (A_EIC_START + 7) + +#define EIC_KEY_POWER (EIC_POWER_PBINT) +#define HEADSET_BUTTON_GPIO (EIC_AUD_HEAD_BUTTON) +#define HEADSET_DETECT_GPIO (EIC_AUD_HEAD_INST2) +#define HEADSET_SWITCH_GPIO 0 + +#define HEADSET_IRQ_TRIGGER_LEVEL_DETECT 1 +#define HEADSET_IRQ_TRIGGER_LEVEL_BUTTON 1 + +#define HEADSET_ADC_MIN_KEY_MEDIA 0 +#define HEADSET_ADC_MAX_KEY_MEDIA 170 +#define HEADSET_ADC_MIN_KEY_VOLUMEUP 171 +#define HEADSET_ADC_MAX_KEY_VOLUMEUP 430 +#define HEADSET_ADC_MIN_KEY_VOLUMEDOWN 431 +#define HEADSET_ADC_MAX_KEY_VOLUMEDOWN 760 +#define HEADSET_ADC_THRESHOLD_3POLE_DETECT 100 +#define HEADSET_ADC_THRESHOLD_4POLE_DETECT 3100 +#define HEADSET_IRQ_THRESHOLD_BUTTON 1 +#define HEADSET_HEADMICBIAS_VOLTAGE 3000000 + +#define SPI0_CMMB_CS_GPIO 156 +#define SPI1_WIFI_CS_GPIO 44 + +#define GPIO_BK 136 + +#define GPIO_CMMB_RESET 144 +#define GPIO_CMMB_INT 143 +#define GPIO_CMMB_26M_CLK_EN 197 + +#define GPIO_BT_RESET 233 +#define GPIO_BT_POWER 231 +#define GPIO_BT2AP_WAKE 232 +#define GPIO_AP2BT_WAKE 235 + +#define GPIO_WIFI_SHUTDOWN 230 +#define GPIO_WIFI_IRQ 234 + +#define GPIO_PROX_INT 216 +#define GPIO_GYRO_INT1 163 +#define GPIO_M_RSTN 161 +#define GPIO_M_DRDY 164 + +#define GPIO_SDIO_DETECT 75 + +#define SPRD_PIN_SDIO0_OFFSET 0x0184 +#define SPRD_PIN_SDIO0_SIZE 7 +#define SPRD_PIN_SDIO0_D3_INDEX 0 +#define SPRD_PIN_SDIO0_D3_GPIO 100 +#define SPRD_PIN_SDIO0_SD_FUNC 0 +#define SPRD_PIN_SDIO0_GPIO_FUNC 3 + +/* ION config info +LCD: + 960x540 + +Video Playing: + 1080p 8 ref-frame + +Video Recording: + 720p + +Camera: + 8M, support ZSL, support preview/capture rotation +*/ + +#define SPRD_ION_MM_SIZE (52 * SZ_1M) +#define SPRD_ION_OVERLAY_SIZE (4 * SZ_1M) + +#endif diff --git a/include/soc/sprd/__board-sp8730seea_hd.h b/include/soc/sprd/__board-sp8730seea_hd.h new file mode 100644 index 00000000..eb4b6825 --- /dev/null +++ b/include/soc/sprd/__board-sp8730seea_hd.h @@ -0,0 +1,115 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __GPIO_SCX35GA_H__ +#define __GPIO_SCX35GA_H__ + +#ifndef __ASM_ARCH_BOARD_H +#error "Don't include this file directly, include <mach/board.h>" +#endif + +#define GPIO_TOUCH_RESET 81 +#define GPIO_TOUCH_IRQ 82 + +#define GPIO_SENSOR_RESET 186//41 +#define GPIO_MAIN_SENSOR_PWN 187//42 +#define GPIO_SUB_SENSOR_PWN 188//43 +#define GPIO_CAM_FLASH_EN 235 +#define GPIO_CAM_FLASH_MODE 234 + +#define SPRD_FLASH_OFST 0x890 +#define SPRD_FLASH_CTRL_BIT 0x8000 +#define SPRD_FLASH_LOW_VAL 0x3 +#define SPRD_FLASH_HIGH_VAL 0xF +#define SPRD_FLASH_LOW_CUR 110 +#define SPRD_FLASH_HIGH_CUR 470 + +#define USB_OTG_CABLE_DETECT 72 + +#define EIC_CHARGER_DETECT (A_EIC_START + 0) +#define EIC_POWER_PBINT2 (A_EIC_START + 1) +#define EIC_POWER_PBINT (A_EIC_START + 2) +#define EIC_AUD_HEAD_BUTTON (A_EIC_START + 3) +#define EIC_CHG_CV_STATE (A_EIC_START + 4) +#define EIC_AUD_HEAD_INST2 (A_EIC_START + 5) +#define EIC_VCHG_OVI (A_EIC_START + 6) +#define EIC_VBAT_OVI (A_EIC_START + 7) + +#define EIC_KEY_POWER (EIC_POWER_PBINT) +#define HEADSET_BUTTON_GPIO (EIC_AUD_HEAD_BUTTON) +#define HEADSET_DETECT_GPIO (EIC_AUD_HEAD_INST2) +#define HEADSET_SWITCH_GPIO 0 + +#define HEADSET_IRQ_TRIGGER_LEVEL_DETECT 1 +#define HEADSET_IRQ_TRIGGER_LEVEL_BUTTON 1 + +#define HEADSET_ADC_MIN_KEY_MEDIA 0 +#define HEADSET_ADC_MAX_KEY_MEDIA 170 +#define HEADSET_ADC_MIN_KEY_VOLUMEUP 171 +#define HEADSET_ADC_MAX_KEY_VOLUMEUP 430 +#define HEADSET_ADC_MIN_KEY_VOLUMEDOWN 431 +#define HEADSET_ADC_MAX_KEY_VOLUMEDOWN 760 +#define HEADSET_ADC_THRESHOLD_3POLE_DETECT 100 +#define HEADSET_ADC_THRESHOLD_4POLE_DETECT 3100 +#define HEADSET_IRQ_THRESHOLD_BUTTON 1 +#define HEADSET_HEADMICBIAS_VOLTAGE 3000000 + +#define SPI0_CMMB_CS_GPIO 156 +#define SPI1_WIFI_CS_GPIO 44 + +#define GPIO_BK 136 + +#define GPIO_CMMB_RESET 144 +#define GPIO_CMMB_INT 143 +#define GPIO_CMMB_26M_CLK_EN 197 + +#define GPIO_BT_RESET 233 +#define GPIO_BT_POWER 231 +#define GPIO_BT2AP_WAKE 232 +#define GPIO_AP2BT_WAKE 235 + +#define GPIO_WIFI_SHUTDOWN 230 +#define GPIO_WIFI_IRQ 234 + +#define GPIO_PROX_INT 216 +#define GPIO_GYRO_INT1 163 +#define GPIO_M_RSTN 161 +#define GPIO_M_DRDY 164 + +#define GPIO_SDIO_DETECT 75 + +#define SPRD_PIN_SDIO0_OFFSET 0x0184 +#define SPRD_PIN_SDIO0_SIZE 7 +#define SPRD_PIN_SDIO0_D3_INDEX 0 +#define SPRD_PIN_SDIO0_D3_GPIO 100 +#define SPRD_PIN_SDIO0_SD_FUNC 0 +#define SPRD_PIN_SDIO0_GPIO_FUNC 3 + +/* ION config info +LCD: + 960x540 + +Video Playing: + 1080p 8 ref-frame + +Video Recording: + 720p + +Camera: + 8M, support ZSL, support preview/capture rotation +*/ + +#define SPRD_ION_MM_SIZE (52 * SZ_1M) +#define SPRD_ION_OVERLAY_SIZE (4 * SZ_1M) + +#endif diff --git a/include/soc/sprd/__board-sp8730seea_jig.h b/include/soc/sprd/__board-sp8730seea_jig.h new file mode 100644 index 00000000..86cc1eca --- /dev/null +++ b/include/soc/sprd/__board-sp8730seea_jig.h @@ -0,0 +1,115 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __GPIO_SCX35GA_H__ +#define __GPIO_SCX35GA_H__ + +#ifndef __ASM_ARCH_BOARD_H +#error "Don't include this file directly, include <mach/board.h>" +#endif + +#define GPIO_TOUCH_RESET 81 +#define GPIO_TOUCH_IRQ 82 + +#define GPIO_SENSOR_RESET 186 +#define GPIO_MAIN_SENSOR_PWN 187 +#define GPIO_SUB_SENSOR_PWN 188 +#define GPIO_CAM_FLASH_EN 235 +#define GPIO_CAM_FLASH_MODE 234 + +#define SPRD_FLASH_OFST 0x890 +#define SPRD_FLASH_CTRL_BIT 0x8000 +#define SPRD_FLASH_LOW_VAL 0x3 +#define SPRD_FLASH_HIGH_VAL 0xF +#define SPRD_FLASH_LOW_CUR 110 +#define SPRD_FLASH_HIGH_CUR 470 + +#define USB_OTG_CABLE_DETECT 72 + +#define EIC_CHARGER_DETECT (A_EIC_START + 0) +#define EIC_POWER_PBINT2 (A_EIC_START + 1) +#define EIC_POWER_PBINT (A_EIC_START + 2) +#define EIC_AUD_HEAD_BUTTON (A_EIC_START + 3) +#define EIC_CHG_CV_STATE (A_EIC_START + 4) +#define EIC_AUD_HEAD_INST2 (A_EIC_START + 5) +#define EIC_VCHG_OVI (A_EIC_START + 6) +#define EIC_VBAT_OVI (A_EIC_START + 7) + +#define EIC_KEY_POWER (EIC_POWER_PBINT) +#define HEADSET_BUTTON_GPIO (EIC_AUD_HEAD_BUTTON) +#define HEADSET_DETECT_GPIO (EIC_AUD_HEAD_INST2) +#define HEADSET_SWITCH_GPIO 0 + +#define HEADSET_IRQ_TRIGGER_LEVEL_DETECT 1 +#define HEADSET_IRQ_TRIGGER_LEVEL_BUTTON 1 + +#define HEADSET_ADC_MIN_KEY_MEDIA 0 +#define HEADSET_ADC_MAX_KEY_MEDIA 170 +#define HEADSET_ADC_MIN_KEY_VOLUMEUP 171 +#define HEADSET_ADC_MAX_KEY_VOLUMEUP 430 +#define HEADSET_ADC_MIN_KEY_VOLUMEDOWN 431 +#define HEADSET_ADC_MAX_KEY_VOLUMEDOWN 760 +#define HEADSET_ADC_THRESHOLD_3POLE_DETECT 100 +#define HEADSET_ADC_THRESHOLD_4POLE_DETECT 3100 +#define HEADSET_IRQ_THRESHOLD_BUTTON 1 +#define HEADSET_HEADMICBIAS_VOLTAGE 3000000 + +#define SPI0_CMMB_CS_GPIO 156 +#define SPI1_WIFI_CS_GPIO 44 + +#define GPIO_BK 136 + +#define GPIO_CMMB_RESET 144 +#define GPIO_CMMB_INT 143 +#define GPIO_CMMB_26M_CLK_EN 197 + +#define GPIO_BT_RESET 233 +#define GPIO_BT_POWER 231 +#define GPIO_BT2AP_WAKE 232 +#define GPIO_AP2BT_WAKE 235 + +#define GPIO_WIFI_SHUTDOWN 230 +#define GPIO_WIFI_IRQ 234 + +#define GPIO_PROX_INT 216 +#define GPIO_GYRO_INT1 163 +#define GPIO_M_RSTN 161 +#define GPIO_M_DRDY 164 + +#define GPIO_SDIO_DETECT 75 + +#define SPRD_PIN_SDIO0_OFFSET 0x0184 +#define SPRD_PIN_SDIO0_SIZE 7 +#define SPRD_PIN_SDIO0_D3_INDEX 0 +#define SPRD_PIN_SDIO0_D3_GPIO 100 +#define SPRD_PIN_SDIO0_SD_FUNC 0 +#define SPRD_PIN_SDIO0_GPIO_FUNC 3 + +/* ION config info +LCD: + 960x540 + +Video Playing: + 1080p 8 ref-frame + +Video Recording: + 720p + +Camera: + 8M, support ZSL, support preview/capture rotation +*/ + +#define SPRD_ION_MM_SIZE (52 * SZ_1M) +#define SPRD_ION_OVERLAY_SIZE (4 * SZ_1M) + +#endif diff --git a/include/soc/sprd/__board-sp8730seea_qhd.h b/include/soc/sprd/__board-sp8730seea_qhd.h new file mode 100644 index 00000000..eb4b6825 --- /dev/null +++ b/include/soc/sprd/__board-sp8730seea_qhd.h @@ -0,0 +1,115 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __GPIO_SCX35GA_H__ +#define __GPIO_SCX35GA_H__ + +#ifndef __ASM_ARCH_BOARD_H +#error "Don't include this file directly, include <mach/board.h>" +#endif + +#define GPIO_TOUCH_RESET 81 +#define GPIO_TOUCH_IRQ 82 + +#define GPIO_SENSOR_RESET 186//41 +#define GPIO_MAIN_SENSOR_PWN 187//42 +#define GPIO_SUB_SENSOR_PWN 188//43 +#define GPIO_CAM_FLASH_EN 235 +#define GPIO_CAM_FLASH_MODE 234 + +#define SPRD_FLASH_OFST 0x890 +#define SPRD_FLASH_CTRL_BIT 0x8000 +#define SPRD_FLASH_LOW_VAL 0x3 +#define SPRD_FLASH_HIGH_VAL 0xF +#define SPRD_FLASH_LOW_CUR 110 +#define SPRD_FLASH_HIGH_CUR 470 + +#define USB_OTG_CABLE_DETECT 72 + +#define EIC_CHARGER_DETECT (A_EIC_START + 0) +#define EIC_POWER_PBINT2 (A_EIC_START + 1) +#define EIC_POWER_PBINT (A_EIC_START + 2) +#define EIC_AUD_HEAD_BUTTON (A_EIC_START + 3) +#define EIC_CHG_CV_STATE (A_EIC_START + 4) +#define EIC_AUD_HEAD_INST2 (A_EIC_START + 5) +#define EIC_VCHG_OVI (A_EIC_START + 6) +#define EIC_VBAT_OVI (A_EIC_START + 7) + +#define EIC_KEY_POWER (EIC_POWER_PBINT) +#define HEADSET_BUTTON_GPIO (EIC_AUD_HEAD_BUTTON) +#define HEADSET_DETECT_GPIO (EIC_AUD_HEAD_INST2) +#define HEADSET_SWITCH_GPIO 0 + +#define HEADSET_IRQ_TRIGGER_LEVEL_DETECT 1 +#define HEADSET_IRQ_TRIGGER_LEVEL_BUTTON 1 + +#define HEADSET_ADC_MIN_KEY_MEDIA 0 +#define HEADSET_ADC_MAX_KEY_MEDIA 170 +#define HEADSET_ADC_MIN_KEY_VOLUMEUP 171 +#define HEADSET_ADC_MAX_KEY_VOLUMEUP 430 +#define HEADSET_ADC_MIN_KEY_VOLUMEDOWN 431 +#define HEADSET_ADC_MAX_KEY_VOLUMEDOWN 760 +#define HEADSET_ADC_THRESHOLD_3POLE_DETECT 100 +#define HEADSET_ADC_THRESHOLD_4POLE_DETECT 3100 +#define HEADSET_IRQ_THRESHOLD_BUTTON 1 +#define HEADSET_HEADMICBIAS_VOLTAGE 3000000 + +#define SPI0_CMMB_CS_GPIO 156 +#define SPI1_WIFI_CS_GPIO 44 + +#define GPIO_BK 136 + +#define GPIO_CMMB_RESET 144 +#define GPIO_CMMB_INT 143 +#define GPIO_CMMB_26M_CLK_EN 197 + +#define GPIO_BT_RESET 233 +#define GPIO_BT_POWER 231 +#define GPIO_BT2AP_WAKE 232 +#define GPIO_AP2BT_WAKE 235 + +#define GPIO_WIFI_SHUTDOWN 230 +#define GPIO_WIFI_IRQ 234 + +#define GPIO_PROX_INT 216 +#define GPIO_GYRO_INT1 163 +#define GPIO_M_RSTN 161 +#define GPIO_M_DRDY 164 + +#define GPIO_SDIO_DETECT 75 + +#define SPRD_PIN_SDIO0_OFFSET 0x0184 +#define SPRD_PIN_SDIO0_SIZE 7 +#define SPRD_PIN_SDIO0_D3_INDEX 0 +#define SPRD_PIN_SDIO0_D3_GPIO 100 +#define SPRD_PIN_SDIO0_SD_FUNC 0 +#define SPRD_PIN_SDIO0_GPIO_FUNC 3 + +/* ION config info +LCD: + 960x540 + +Video Playing: + 1080p 8 ref-frame + +Video Recording: + 720p + +Camera: + 8M, support ZSL, support preview/capture rotation +*/ + +#define SPRD_ION_MM_SIZE (52 * SZ_1M) +#define SPRD_ION_OVERLAY_SIZE (4 * SZ_1M) + +#endif diff --git a/include/soc/sprd/__board-sp8830fpga.h b/include/soc/sprd/__board-sp8830fpga.h new file mode 100644 index 00000000..f646653b --- /dev/null +++ b/include/soc/sprd/__board-sp8830fpga.h @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __GPIO_SC8810_H__ +#define __GPIO_SC8810_H__ + +#ifndef __ASM_ARCH_BOARD_H +#error "Don't include this file directly, include <mach/board.h>" +#endif + +#define GPIO_TOUCH_RESET 142 +#define GPIO_TOUCH_IRQ 141 + +#define HEADSET_SWITCH_GPIO 237 +#define GPIO_SENSOR_RESET 41 +#define GPIO_MAIN_SENSOR_PWN 42 +#define GPIO_SUB_SENSOR_PWN 43 + +#define USB_OTG_CABLE_DETECT 72 + +#define SPRD_FLASH_OFST 0x890 +#define SPRD_FLASH_CTRL_BIT 0x8000 +#define SPRD_FLASH_LOW_VAL 0x3 +#define SPRD_FLASH_HIGH_VAL 0xF +#define SPRD_FLASH_LOW_CUR 110 +#define SPRD_FLASH_HIGH_CUR 470 + +#define EIC_CHARGER_DETECT (A_EIC_START + 2) +#define EIC_KEY_POWER (A_EIC_START + 3) +#define HEADSET_BUTTON_GPIO (A_EIC_START + 4) +#define HEADSET_DETECT_GPIO 139 +#define EIC_AUD_HEAD_INST2 (A_EIC_START + 5) + +/*fixme */ +#define EIC_CHG_CV_STATE (A_EIC_START + 4) +#define EIC_VCHG_OVI (A_EIC_START + 6) + +#define GPIO_KEY_VOLUMEDOWN 124 +#define GPIO_KEY_VOLUMEUP 125 +//#define GPIO_KEY_CAMERA 0 +//#define GPIO_KEY_HOME 0 + +#define HEADSET_IRQ_TRIGGER_LEVEL_DETECT 1 +#define HEADSET_IRQ_TRIGGER_LEVEL_BUTTON 1 + +#define HEADSET_ADC_MIN_KEY_MEDIA 0 +#define HEADSET_ADC_MAX_KEY_MEDIA 170 +#define HEADSET_ADC_MIN_KEY_VOLUMEUP 171 +#define HEADSET_ADC_MAX_KEY_VOLUMEUP 430 +#define HEADSET_ADC_MIN_KEY_VOLUMEDOWN 431 +#define HEADSET_ADC_MAX_KEY_VOLUMEDOWN 760 +#define HEADSET_ADC_THRESHOLD_3POLE_DETECT 100 +#define HEADSET_ADC_THRESHOLD_4POLE_DETECT 3100 +#define HEADSET_IRQ_THRESHOLD_BUTTON 1 +#define HEADSET_HEADMICBIAS_VOLTAGE 3000000 + +#define SPI0_CMMB_CS_GPIO 32 +#define SPI1_WIFI_CS_GPIO 44 + +#define GPIO_BK 143 +#define MSENSOR_DRDY_GPIO 53 +#define GPIO_PLSENSOR_IRQ 213 + +#define GPIO_BT_RESET 194 +#define GPIO_WIFI_POWERON 189 +#define GPIO_WIFI_RESET 190 +#define GPIO_WIFI_IRQ -1 + +#define GPIO_GPS_ONOFF 174 + +#define GPIO_SDIO_DETECT 75 + +#define SPRD_PIN_SDIO0_OFFSET 0x01E0 +#define SPRD_PIN_SDIO0_SIZE 7 +#define SPRD_PIN_SDIO0_D3_INDEX 0 +#define SPRD_PIN_SDIO0_D3_GPIO 100 +#define SPRD_PIN_SDIO0_SD_FUNC 0 +#define SPRD_PIN_SDIO0_GPIO_FUNC 3 + +#endif diff --git a/include/soc/sprd/__board-sp9630ea3mn.h b/include/soc/sprd/__board-sp9630ea3mn.h new file mode 100644 index 00000000..ae555772 --- /dev/null +++ b/include/soc/sprd/__board-sp9630ea3mn.h @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __GPIO_SC8810_H__ +#define __GPIO_SC8810_H__ + +#ifndef __ASM_ARCH_BOARD_H +#error "Don't include this file directly, include <mach/board.h>" +#endif + +#define GPIO_TOUCH_RESET 145 +#define GPIO_TOUCH_IRQ 144 + +#define GPIO_MAIN_SENSOR_RESET 44 +#define GPIO_MAIN_SENSOR_PWN 46 +#define GPIO_SUB_SENSOR_RESET 45 +#define GPIO_SUB_SENSOR_PWN 47 + +#define USB_OTG_CABLE_DETECT 126 + +#define SPRD_FLASH_OFST 0x890 +#define SPRD_FLASH_CTRL_BIT 0x8000 +#define SPRD_FLASH_LOW_VAL 0x3 +#define SPRD_FLASH_HIGH_VAL 0xF +#define SPRD_FLASH_LOW_CUR 110 +#define SPRD_FLASH_HIGH_CUR 470 + +#define GPIO_KEY_VOLUMEDOWN 124 +#define GPIO_KEY_VOLUMEUP 125 + +#define EIC_CHARGER_DETECT (A_EIC_START + 0) +#define EIC_POWER_PBINT2 (A_EIC_START + 1) +#define EIC_POWER_PBINT (A_EIC_START + 2) +#define EIC_AUD_HEAD_BUTTON (A_EIC_START + 3) +#define EIC_CHG_CV_STATE (A_EIC_START + 4) +#define EIC_AUD_HEAD_INST (A_EIC_START + 5) +#define EIC_VCHG_OVI (A_EIC_START + 6) +#define EIC_VBAT_OVI (A_EIC_START + 7) +#define EIC_AUD_HEAD_INST2 (A_EIC_START + 8) + +#define EIC_KEY_POWER (EIC_POWER_PBINT) + +#define HEADSET_BUTTON_GPIO (EIC_AUD_HEAD_BUTTON) +#define HEADSET_DETECT_GPIO (EIC_AUD_HEAD_INST2) +#define HEADSET_SWITCH_GPIO 0 + +#define HEADSET_IRQ_TRIGGER_LEVEL_DETECT 1 +#define HEADSET_IRQ_TRIGGER_LEVEL_BUTTON 1 + +#define HEADSET_ADC_MIN_KEY_MEDIA 0 +#define HEADSET_ADC_MAX_KEY_MEDIA 170 +#define HEADSET_ADC_MIN_KEY_VOLUMEUP 171 +#define HEADSET_ADC_MAX_KEY_VOLUMEUP 430 +#define HEADSET_ADC_MIN_KEY_VOLUMEDOWN 431 +#define HEADSET_ADC_MAX_KEY_VOLUMEDOWN 760 +#define HEADSET_ADC_THRESHOLD_3POLE_DETECT 100 +#define HEADSET_ADC_THRESHOLD_4POLE_DETECT 3100 +#define HEADSET_IRQ_THRESHOLD_BUTTON 1 +#define HEADSET_HEADMICBIAS_VOLTAGE 3000000 + +#define SPI0_CMMB_CS_GPIO 32 +#define SPI1_WIFI_CS_GPIO 44 + +#define GPIO_BK 143 +#define MSENSOR_DRDY_GPIO 53 +#define GPIO_PLSENSOR_IRQ 213 +/*For bcm4343 power on/off and sleep/wake */ +#define GPIO_BT_RESET 122 +#define GPIO_BT_POWER 131 +#define GPIO_BT2AP_WAKE 133 +#define GPIO_AP2BT_WAKE 132 + +/*#define GPIO_BT_RESET 194 */ +#define GPIO_WIFI_POWERON 189 +#define GPIO_WIFI_SHUTDOWN 130 +#define GPIO_WIFI_IRQ 97 + +#define GPIO_PROX_INT 140 +#define GPIO_GPS_ONOFF 174 + +#define GPIO_SDIO_DETECT 75 + +#define SPRD_PIN_SDIO0_OFFSET 0x01E0 +#define SPRD_PIN_SDIO0_SIZE 7 +#define SPRD_PIN_SDIO0_D3_INDEX 0 +#define SPRD_PIN_SDIO0_D3_GPIO 100 +#define SPRD_PIN_SDIO0_SD_FUNC 0 +#define SPRD_PIN_SDIO0_GPIO_FUNC 3 + +/*#define CP related featrue */ +#define SIPC_SMEM_ADDR (CONFIG_PHYS_OFFSET + 120 * SZ_1M) + +#define CPT_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#define CPT_TOTAL_SIZE (SZ_1M * 18) +#define CPT_RING_ADDR (CPT_START_ADDR + CPT_TOTAL_SIZE - SZ_4K) +#define CPT_RING_SIZE (SZ_4K) +#define CPT_SMEM_SIZE (SZ_1M * 2) + +#define CPW_START_ADDR (CONFIG_PHYS_OFFSET + 150 * SZ_1M) +#define CPW_TOTAL_SIZE (SZ_1M * 33) +#define CPW_RING_ADDR (CPW_START_ADDR + CPW_TOTAL_SIZE - SZ_4K) +#define CPW_RING_SIZE (SZ_4K) +#define CPW_SMEM_SIZE (SZ_1M * 2) + +#define WCN_START_ADDR (CONFIG_PHYS_OFFSET + 320 * SZ_1M) +#define WCN_TOTAL_SIZE (SZ_1M * 5) +#define WCN_RING_ADDR (WCN_START_ADDR + WCN_TOTAL_SIZE - SZ_4K) +#define WCN_RING_SIZE (SZ_4K) +#define WCN_SMEM_SIZE (SZ_1M * 2) + +#define GGE_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#define GGE_TOTAL_SIZE (SZ_1M * 22) +#define GGE_RING_ADDR (GGE_START_ADDR + GGE_TOTAL_SIZE - SZ_4K) +#define GGE_RING_SIZE (SZ_4K) +#define GGE_SMEM_SIZE (SZ_1M * 2) + +#define LTE_START_ADDR (CONFIG_PHYS_OFFSET + 150 * SZ_1M) +#define LTE_TOTAL_SIZE (SZ_1M * 64) +#define LTE_RING_ADDR (LTE_START_ADDR + LTE_TOTAL_SIZE - SZ_4K) +#define LTE_RING_SIZE (SZ_4K) +#define LTE_SMEM_SIZE (SZ_1M * 2) + +#endif diff --git a/include/soc/sprd/__board-sp9630ea4mn.h b/include/soc/sprd/__board-sp9630ea4mn.h new file mode 100644 index 00000000..b249954c --- /dev/null +++ b/include/soc/sprd/__board-sp9630ea4mn.h @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __GPIO_SC8810_H__ +#define __GPIO_SC8810_H__ + +#ifndef __ASM_ARCH_BOARD_H +#error "Don't include this file directly, include <mach/board.h>" +#endif + +#define GPIO_TOUCH_RESET 145 +#define GPIO_TOUCH_IRQ 144 + +#define GPIO_MAIN_SENSOR_RESET 44 +#define GPIO_MAIN_SENSOR_PWN 46 +#define GPIO_SUB_SENSOR_RESET 45 +#define GPIO_SUB_SENSOR_PWN 47 + +#define USB_OTG_CABLE_DETECT 126 + +#define SPRD_FLASH_OFST 0x890 +#define SPRD_FLASH_CTRL_BIT 0x8000 +#define SPRD_FLASH_LOW_VAL 0x3 +#define SPRD_FLASH_HIGH_VAL 0xF +#define SPRD_FLASH_LOW_CUR 110 +#define SPRD_FLASH_HIGH_CUR 470 + +#define GPIO_KEY_VOLUMEDOWN 124 +#define GPIO_KEY_VOLUMEUP 125 + +#define EIC_CHARGER_DETECT (A_EIC_START + 0) +#define EIC_POWER_PBINT2 (A_EIC_START + 1) +#define EIC_POWER_PBINT (A_EIC_START + 2) +#define EIC_AUD_HEAD_BUTTON (A_EIC_START + 3) +#define EIC_CHG_CV_STATE (A_EIC_START + 4) +#define EIC_AUD_HEAD_INST (A_EIC_START + 5) +#define EIC_VCHG_OVI (A_EIC_START + 6) +#define EIC_VBAT_OVI (A_EIC_START + 7) +#define EIC_AUD_HEAD_INST2 (A_EIC_START + 8) + +#define EIC_KEY_POWER (EIC_POWER_PBINT) + +#define HEADSET_BUTTON_GPIO (EIC_AUD_HEAD_BUTTON) +#define HEADSET_DETECT_GPIO (EIC_AUD_HEAD_INST2) +#define HEADSET_SWITCH_GPIO 0 + +#define HEADSET_IRQ_TRIGGER_LEVEL_DETECT 1 +#define HEADSET_IRQ_TRIGGER_LEVEL_BUTTON 1 + +#define HEADSET_ADC_MIN_KEY_MEDIA 0 +#define HEADSET_ADC_MAX_KEY_MEDIA 170 +#define HEADSET_ADC_MIN_KEY_VOLUMEUP 171 +#define HEADSET_ADC_MAX_KEY_VOLUMEUP 430 +#define HEADSET_ADC_MIN_KEY_VOLUMEDOWN 431 +#define HEADSET_ADC_MAX_KEY_VOLUMEDOWN 760 +#define HEADSET_ADC_THRESHOLD_3POLE_DETECT 100 +#define HEADSET_ADC_THRESHOLD_4POLE_DETECT 3100 +#define HEADSET_IRQ_THRESHOLD_BUTTON 1 +#define HEADSET_HEADMICBIAS_VOLTAGE 3000000 + +#define SPI0_CMMB_CS_GPIO 32 +#define SPI1_WIFI_CS_GPIO 44 + +#define GPIO_BK 143 +#define MSENSOR_DRDY_GPIO 53 +#define GPIO_PLSENSOR_IRQ 213 +/*For bcm4343 power on/off and sleep/wake */ +#define GPIO_BT_RESET 122 +#define GPIO_BT_POWER 131 +#define GPIO_BT2AP_WAKE 133 +#define GPIO_AP2BT_WAKE 132 + +/*#define GPIO_BT_RESET 194 */ +#define GPIO_WIFI_POWERON 189 +#define GPIO_WIFI_SHUTDOWN 130 +#define GPIO_WIFI_IRQ 97 + +#define GPIO_PROX_INT 140 +#define GPIO_GPS_ONOFF 174 + +#define GPIO_SDIO_DETECT 75 + +#define SPRD_PIN_SDIO0_OFFSET 0x01E0 +#define SPRD_PIN_SDIO0_SIZE 7 +#define SPRD_PIN_SDIO0_D3_INDEX 0 +#define SPRD_PIN_SDIO0_D3_GPIO 100 +#define SPRD_PIN_SDIO0_SD_FUNC 0 +#define SPRD_PIN_SDIO0_GPIO_FUNC 3 + +/*#define CP related featrue */ +#define SIPC_SMEM_ADDR (CONFIG_PHYS_OFFSET + 120 * SZ_1M) + +#define CPT_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#define CPT_TOTAL_SIZE (SZ_1M * 18) +#define CPT_RING_ADDR (CPT_START_ADDR + CPT_TOTAL_SIZE - SZ_4K) +#define CPT_RING_SIZE (SZ_4K) +#define CPT_SMEM_SIZE (SZ_1M * 2) + +#define CPW_START_ADDR (CONFIG_PHYS_OFFSET + 150 * SZ_1M) +#define CPW_TOTAL_SIZE (SZ_1M * 33) +#define CPW_RING_ADDR (CPW_START_ADDR + CPW_TOTAL_SIZE - SZ_4K) +#define CPW_RING_SIZE (SZ_4K) +#define CPW_SMEM_SIZE (SZ_1M * 2) + +#define WCN_START_ADDR (CONFIG_PHYS_OFFSET + 320 * SZ_1M) +#define WCN_TOTAL_SIZE (SZ_1M * 5) +#define WCN_RING_ADDR (WCN_START_ADDR + WCN_TOTAL_SIZE - SZ_4K) +#define WCN_RING_SIZE (SZ_4K) +#define WCN_SMEM_SIZE (SZ_1M * 2) + +#define GGE_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#define GGE_TOTAL_SIZE (SZ_1M * 22) +#define GGE_RING_ADDR (GGE_START_ADDR + GGE_TOTAL_SIZE - SZ_4K) +#define GGE_RING_SIZE (SZ_4K) +#define GGE_SMEM_SIZE (SZ_1M * 2) + +#define LTE_START_ADDR (CONFIG_PHYS_OFFSET + 150 * SZ_1M) +#define LTE_TOTAL_SIZE (SZ_1M * 80) +#define LTE_RING_ADDR (LTE_START_ADDR + LTE_TOTAL_SIZE - SZ_4K) +#define LTE_RING_SIZE (SZ_4K) +#define LTE_SMEM_SIZE (SZ_1M * 2) + +#endif diff --git a/include/soc/sprd/__board-sp9820ea.h b/include/soc/sprd/__board-sp9820ea.h new file mode 100644 index 00000000..78ec1439 --- /dev/null +++ b/include/soc/sprd/__board-sp9820ea.h @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __GPIO_SC8810_H__ +#define __GPIO_SC8810_H__ + +#ifndef __ASM_ARCH_BOARD_H +#error "Don't include this file directly, include <mach/board.h>" +#endif + +#define GPIO_TOUCH_RESET 145 +#define GPIO_TOUCH_IRQ 144 + +#define GPIO_MAIN_SENSOR_RESET 44 +#define GPIO_MAIN_SENSOR_PWN 46 +#define GPIO_SUB_SENSOR_RESET 45 +#define GPIO_SUB_SENSOR_PWN 47 + +#define USB_OTG_CABLE_DETECT 126 + +#define SPRD_FLASH_OFST 0x890 +#define SPRD_FLASH_CTRL_BIT 0x8000 +#define SPRD_FLASH_LOW_VAL 0x3 +#define SPRD_FLASH_HIGH_VAL 0xF +#define SPRD_FLASH_LOW_CUR 110 +#define SPRD_FLASH_HIGH_CUR 470 + +#define GPIO_KEY_VOLUMEDOWN 124 +#define GPIO_KEY_VOLUMEUP 125 + +#define EIC_CHARGER_DETECT (A_EIC_START + 0) +#define EIC_POWER_PBINT2 (A_EIC_START + 1) +#define EIC_POWER_PBINT (A_EIC_START + 2) +#define EIC_AUD_HEAD_BUTTON (A_EIC_START + 3) +#define EIC_CHG_CV_STATE (A_EIC_START + 4) +#define EIC_AUD_HEAD_INST (A_EIC_START + 5) +#define EIC_VCHG_OVI (A_EIC_START + 6) +#define EIC_VBAT_OVI (A_EIC_START + 7) +#define EIC_AUD_HEAD_INST2 (A_EIC_START + 8) + +#define EIC_KEY_POWER (EIC_POWER_PBINT) + +#define HEADSET_BUTTON_GPIO (EIC_AUD_HEAD_BUTTON) +#define HEADSET_DETECT_GPIO (EIC_AUD_HEAD_INST2) +#define HEADSET_SWITCH_GPIO 0 + +#define HEADSET_IRQ_TRIGGER_LEVEL_DETECT 1 +#define HEADSET_IRQ_TRIGGER_LEVEL_BUTTON 1 + +#define HEADSET_ADC_MIN_KEY_MEDIA 0 +#define HEADSET_ADC_MAX_KEY_MEDIA 170 +#define HEADSET_ADC_MIN_KEY_VOLUMEUP 171 +#define HEADSET_ADC_MAX_KEY_VOLUMEUP 430 +#define HEADSET_ADC_MIN_KEY_VOLUMEDOWN 431 +#define HEADSET_ADC_MAX_KEY_VOLUMEDOWN 760 +#define HEADSET_ADC_THRESHOLD_3POLE_DETECT 100 +#define HEADSET_ADC_THRESHOLD_4POLE_DETECT 3100 +#define HEADSET_IRQ_THRESHOLD_BUTTON 1 +#define HEADSET_HEADMICBIAS_VOLTAGE 3000000 + +#define SPI0_CMMB_CS_GPIO 32 +#define SPI1_WIFI_CS_GPIO 44 + +#define GPIO_BK 143 +#define MSENSOR_DRDY_GPIO 53 +#define GPIO_PLSENSOR_IRQ 213 +/*For bcm4343 power on/off and sleep/wake */ +#define GPIO_BT_RESET 122 +#define GPIO_BT_POWER 131 +#define GPIO_BT2AP_WAKE 133 +#define GPIO_AP2BT_WAKE 132 + +/*#define GPIO_BT_RESET 194 */ +#define GPIO_WIFI_POWERON 189 +#define GPIO_WIFI_SHUTDOWN 130 +#define GPIO_WIFI_IRQ 97 + +#define GPIO_PROX_INT 140 +#define GPIO_GPS_ONOFF 174 + +#define GPIO_SDIO_DETECT 75 + +#define SPRD_PIN_SDIO0_OFFSET 0x01E0 +#define SPRD_PIN_SDIO0_SIZE 7 +#define SPRD_PIN_SDIO0_D3_INDEX 0 +#define SPRD_PIN_SDIO0_D3_GPIO 100 +#define SPRD_PIN_SDIO0_SD_FUNC 0 +#define SPRD_PIN_SDIO0_GPIO_FUNC 3 + +#define SIPC_SMEM_ADDR (CONFIG_PHYS_OFFSET + 120 * SZ_1M) +#define CPT_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#define CPT_TOTAL_SIZE (SZ_1M * 18) +#define CPT_RING_ADDR (CPT_START_ADDR + CPT_TOTAL_SIZE - SZ_4K) +#define CPT_RING_SIZE (SZ_4K) +#define CPT_SMEM_SIZE (SZ_1M * 2) +#define CPW_START_ADDR (CONFIG_PHYS_OFFSET + 150 * SZ_1M) +#define CPW_TOTAL_SIZE (SZ_1M * 33) +#define CPW_RING_ADDR (CPW_START_ADDR + CPW_TOTAL_SIZE - SZ_4K) +#define CPW_RING_SIZE (SZ_4K) +#define CPW_SMEM_SIZE (SZ_1M * 2) +#define WCN_START_ADDR (CONFIG_PHYS_OFFSET + 320 * SZ_1M) +#define WCN_TOTAL_SIZE (SZ_1M * 5) +#define WCN_RING_ADDR (WCN_START_ADDR + WCN_TOTAL_SIZE - SZ_4K) +#define WCN_RING_SIZE (SZ_4K) +#define WCN_SMEM_SIZE (SZ_1M * 2) +#define GGE_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#define GGE_TOTAL_SIZE (SZ_1M * 22) +#define GGE_RING_ADDR (GGE_START_ADDR + GGE_TOTAL_SIZE - SZ_4K) +#define GGE_RING_SIZE (SZ_4K) +#define GGE_SMEM_SIZE (SZ_1M * 2) +#define LTE_START_ADDR (CONFIG_PHYS_OFFSET + 150 * SZ_1M) +#define LTE_TOTAL_SIZE (SZ_1M * 64) +#define LTE_RING_ADDR (LTE_START_ADDR + LTE_TOTAL_SIZE - SZ_4K) +#define LTE_RING_SIZE (SZ_4K) +#define LTE_SMEM_SIZE (SZ_1M * 2) +#endif diff --git a/include/soc/sprd/__board-sp9820fpga.h b/include/soc/sprd/__board-sp9820fpga.h new file mode 100644 index 00000000..78ec1439 --- /dev/null +++ b/include/soc/sprd/__board-sp9820fpga.h @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __GPIO_SC8810_H__ +#define __GPIO_SC8810_H__ + +#ifndef __ASM_ARCH_BOARD_H +#error "Don't include this file directly, include <mach/board.h>" +#endif + +#define GPIO_TOUCH_RESET 145 +#define GPIO_TOUCH_IRQ 144 + +#define GPIO_MAIN_SENSOR_RESET 44 +#define GPIO_MAIN_SENSOR_PWN 46 +#define GPIO_SUB_SENSOR_RESET 45 +#define GPIO_SUB_SENSOR_PWN 47 + +#define USB_OTG_CABLE_DETECT 126 + +#define SPRD_FLASH_OFST 0x890 +#define SPRD_FLASH_CTRL_BIT 0x8000 +#define SPRD_FLASH_LOW_VAL 0x3 +#define SPRD_FLASH_HIGH_VAL 0xF +#define SPRD_FLASH_LOW_CUR 110 +#define SPRD_FLASH_HIGH_CUR 470 + +#define GPIO_KEY_VOLUMEDOWN 124 +#define GPIO_KEY_VOLUMEUP 125 + +#define EIC_CHARGER_DETECT (A_EIC_START + 0) +#define EIC_POWER_PBINT2 (A_EIC_START + 1) +#define EIC_POWER_PBINT (A_EIC_START + 2) +#define EIC_AUD_HEAD_BUTTON (A_EIC_START + 3) +#define EIC_CHG_CV_STATE (A_EIC_START + 4) +#define EIC_AUD_HEAD_INST (A_EIC_START + 5) +#define EIC_VCHG_OVI (A_EIC_START + 6) +#define EIC_VBAT_OVI (A_EIC_START + 7) +#define EIC_AUD_HEAD_INST2 (A_EIC_START + 8) + +#define EIC_KEY_POWER (EIC_POWER_PBINT) + +#define HEADSET_BUTTON_GPIO (EIC_AUD_HEAD_BUTTON) +#define HEADSET_DETECT_GPIO (EIC_AUD_HEAD_INST2) +#define HEADSET_SWITCH_GPIO 0 + +#define HEADSET_IRQ_TRIGGER_LEVEL_DETECT 1 +#define HEADSET_IRQ_TRIGGER_LEVEL_BUTTON 1 + +#define HEADSET_ADC_MIN_KEY_MEDIA 0 +#define HEADSET_ADC_MAX_KEY_MEDIA 170 +#define HEADSET_ADC_MIN_KEY_VOLUMEUP 171 +#define HEADSET_ADC_MAX_KEY_VOLUMEUP 430 +#define HEADSET_ADC_MIN_KEY_VOLUMEDOWN 431 +#define HEADSET_ADC_MAX_KEY_VOLUMEDOWN 760 +#define HEADSET_ADC_THRESHOLD_3POLE_DETECT 100 +#define HEADSET_ADC_THRESHOLD_4POLE_DETECT 3100 +#define HEADSET_IRQ_THRESHOLD_BUTTON 1 +#define HEADSET_HEADMICBIAS_VOLTAGE 3000000 + +#define SPI0_CMMB_CS_GPIO 32 +#define SPI1_WIFI_CS_GPIO 44 + +#define GPIO_BK 143 +#define MSENSOR_DRDY_GPIO 53 +#define GPIO_PLSENSOR_IRQ 213 +/*For bcm4343 power on/off and sleep/wake */ +#define GPIO_BT_RESET 122 +#define GPIO_BT_POWER 131 +#define GPIO_BT2AP_WAKE 133 +#define GPIO_AP2BT_WAKE 132 + +/*#define GPIO_BT_RESET 194 */ +#define GPIO_WIFI_POWERON 189 +#define GPIO_WIFI_SHUTDOWN 130 +#define GPIO_WIFI_IRQ 97 + +#define GPIO_PROX_INT 140 +#define GPIO_GPS_ONOFF 174 + +#define GPIO_SDIO_DETECT 75 + +#define SPRD_PIN_SDIO0_OFFSET 0x01E0 +#define SPRD_PIN_SDIO0_SIZE 7 +#define SPRD_PIN_SDIO0_D3_INDEX 0 +#define SPRD_PIN_SDIO0_D3_GPIO 100 +#define SPRD_PIN_SDIO0_SD_FUNC 0 +#define SPRD_PIN_SDIO0_GPIO_FUNC 3 + +#define SIPC_SMEM_ADDR (CONFIG_PHYS_OFFSET + 120 * SZ_1M) +#define CPT_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#define CPT_TOTAL_SIZE (SZ_1M * 18) +#define CPT_RING_ADDR (CPT_START_ADDR + CPT_TOTAL_SIZE - SZ_4K) +#define CPT_RING_SIZE (SZ_4K) +#define CPT_SMEM_SIZE (SZ_1M * 2) +#define CPW_START_ADDR (CONFIG_PHYS_OFFSET + 150 * SZ_1M) +#define CPW_TOTAL_SIZE (SZ_1M * 33) +#define CPW_RING_ADDR (CPW_START_ADDR + CPW_TOTAL_SIZE - SZ_4K) +#define CPW_RING_SIZE (SZ_4K) +#define CPW_SMEM_SIZE (SZ_1M * 2) +#define WCN_START_ADDR (CONFIG_PHYS_OFFSET + 320 * SZ_1M) +#define WCN_TOTAL_SIZE (SZ_1M * 5) +#define WCN_RING_ADDR (WCN_START_ADDR + WCN_TOTAL_SIZE - SZ_4K) +#define WCN_RING_SIZE (SZ_4K) +#define WCN_SMEM_SIZE (SZ_1M * 2) +#define GGE_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#define GGE_TOTAL_SIZE (SZ_1M * 22) +#define GGE_RING_ADDR (GGE_START_ADDR + GGE_TOTAL_SIZE - SZ_4K) +#define GGE_RING_SIZE (SZ_4K) +#define GGE_SMEM_SIZE (SZ_1M * 2) +#define LTE_START_ADDR (CONFIG_PHYS_OFFSET + 150 * SZ_1M) +#define LTE_TOTAL_SIZE (SZ_1M * 64) +#define LTE_RING_ADDR (LTE_START_ADDR + LTE_TOTAL_SIZE - SZ_4K) +#define LTE_RING_SIZE (SZ_4K) +#define LTE_SMEM_SIZE (SZ_1M * 2) +#endif diff --git a/include/soc/sprd/__board-sp9830aea_5m_h100.h b/include/soc/sprd/__board-sp9830aea_5m_h100.h new file mode 100644 index 00000000..654212a2 --- /dev/null +++ b/include/soc/sprd/__board-sp9830aea_5m_h100.h @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __GPIO_SC8810_H__ +#define __GPIO_SC8810_H__ + +#ifndef __ASM_ARCH_BOARD_H +#error "Don't include this file directly, include <mach/board.h>" +#endif + +#define GPIO_TOUCH_RESET 145 +#define GPIO_TOUCH_IRQ 144 + +#define GPIO_MAIN_SENSOR_RESET 44 +#define GPIO_MAIN_SENSOR_PWN 46 +#define GPIO_SUB_SENSOR_RESET 45 +#define GPIO_SUB_SENSOR_PWN 47 + +#define USB_OTG_CABLE_DETECT 126 + +#define SPRD_FLASH_OFST 0x890 +#define SPRD_FLASH_CTRL_BIT 0x8000 +#define SPRD_FLASH_LOW_VAL 0x3 +#define SPRD_FLASH_HIGH_VAL 0xF +#define SPRD_FLASH_LOW_CUR 110 +#define SPRD_FLASH_HIGH_CUR 470 + +#define GPIO_KEY_VOLUMEDOWN 124 +#define GPIO_KEY_VOLUMEUP 125 + +#define EIC_CHARGER_DETECT (A_EIC_START + 0) +#define EIC_POWER_PBINT2 (A_EIC_START + 1) +#define EIC_POWER_PBINT (A_EIC_START + 2) +#define EIC_AUD_HEAD_BUTTON (A_EIC_START + 3) +#define EIC_CHG_CV_STATE (A_EIC_START + 4) +#define EIC_AUD_HEAD_INST (A_EIC_START + 5) +#define EIC_VCHG_OVI (A_EIC_START + 6) +#define EIC_VBAT_OVI (A_EIC_START + 7) +#define EIC_AUD_HEAD_INST2 (A_EIC_START + 8) + +#define EIC_KEY_POWER (EIC_POWER_PBINT) + +#define HEADSET_BUTTON_GPIO (EIC_AUD_HEAD_BUTTON) +#define HEADSET_DETECT_GPIO (EIC_AUD_HEAD_INST2) +#define HEADSET_SWITCH_GPIO 0 + +#define HEADSET_IRQ_TRIGGER_LEVEL_DETECT 1 +#define HEADSET_IRQ_TRIGGER_LEVEL_BUTTON 1 + +#define HEADSET_ADC_MIN_KEY_MEDIA 0 +#define HEADSET_ADC_MAX_KEY_MEDIA 170 +#define HEADSET_ADC_MIN_KEY_VOLUMEUP 171 +#define HEADSET_ADC_MAX_KEY_VOLUMEUP 430 +#define HEADSET_ADC_MIN_KEY_VOLUMEDOWN 431 +#define HEADSET_ADC_MAX_KEY_VOLUMEDOWN 760 +#define HEADSET_ADC_THRESHOLD_3POLE_DETECT 100 +#define HEADSET_ADC_THRESHOLD_4POLE_DETECT 3100 +#define HEADSET_IRQ_THRESHOLD_BUTTON 1 +#define HEADSET_HEADMICBIAS_VOLTAGE 3000000 + +#define SPI0_CMMB_CS_GPIO 32 +#define SPI1_WIFI_CS_GPIO 44 + +#define GPIO_BK 143 +#define MSENSOR_DRDY_GPIO 53 +#define GPIO_PLSENSOR_IRQ 213 +/*For bcm4343 power on/off and sleep/wake */ +#define GPIO_BT_RESET 122 +#define GPIO_BT_POWER 131 +#define GPIO_BT2AP_WAKE 133 +#define GPIO_AP2BT_WAKE 132 + +/*#define GPIO_BT_RESET 194 */ +#define GPIO_WIFI_POWERON 189 +#define GPIO_WIFI_SHUTDOWN 130 +#define GPIO_WIFI_IRQ 97 + +#define GPIO_PROX_INT 140 +#define GPIO_GPS_ONOFF 174 + +#define GPIO_SDIO_DETECT 75 + +#define SPRD_PIN_SDIO0_OFFSET 0x01E0 +#define SPRD_PIN_SDIO0_SIZE 7 +#define SPRD_PIN_SDIO0_D3_INDEX 0 +#define SPRD_PIN_SDIO0_D3_GPIO 100 +#define SPRD_PIN_SDIO0_SD_FUNC 0 +#define SPRD_PIN_SDIO0_GPIO_FUNC 3 + +/*#define CP related featrue */ +#define SIPC_SMEM_ADDR (CONFIG_PHYS_OFFSET + 120 * SZ_1M) + +#define CPT_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#define CPT_TOTAL_SIZE (SZ_1M * 18) +#define CPT_RING_ADDR (CPT_START_ADDR + CPT_TOTAL_SIZE - SZ_4K) +#define CPT_RING_SIZE (SZ_4K) +#define CPT_SMEM_SIZE (SZ_1M * 2) + +#define CPW_START_ADDR (CONFIG_PHYS_OFFSET + 150* SZ_1M) +#define CPW_TOTAL_SIZE (SZ_1M * 33) +#define CPW_RING_ADDR (CPW_START_ADDR + CPW_TOTAL_SIZE - SZ_4K) +#define CPW_RING_SIZE (SZ_4K) +#define CPW_SMEM_SIZE (SZ_1M * 2) + +#define WCN_START_ADDR (CONFIG_PHYS_OFFSET + 320 * SZ_1M) +#define WCN_TOTAL_SIZE (SZ_1M * 5) +#define WCN_RING_ADDR (WCN_START_ADDR + WCN_TOTAL_SIZE - SZ_4K) +#define WCN_RING_SIZE (SZ_4K) +#define WCN_SMEM_SIZE (SZ_1M * 2) + +#define GGE_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#define GGE_TOTAL_SIZE (SZ_1M * 22) +#define GGE_RING_ADDR (GGE_START_ADDR + GGE_TOTAL_SIZE - SZ_4K) +#define GGE_RING_SIZE (SZ_4K) +#define GGE_SMEM_SIZE (SZ_1M * 2) + +#define LTE_START_ADDR (CONFIG_PHYS_OFFSET + 150 * SZ_1M) +#define LTE_TOTAL_SIZE (SZ_1M * 83) +#define LTE_RING_ADDR (LTE_START_ADDR + LTE_TOTAL_SIZE - SZ_4K) +#define LTE_RING_SIZE (SZ_4K) +#define LTE_SMEM_SIZE (SZ_1M * 2) + +#endif diff --git a/include/soc/sprd/__board-sp9830aea_5m_volte.h b/include/soc/sprd/__board-sp9830aea_5m_volte.h new file mode 100644 index 00000000..7c69fcdc --- /dev/null +++ b/include/soc/sprd/__board-sp9830aea_5m_volte.h @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __GPIO_SC8810_H__ +#define __GPIO_SC8810_H__ + +#ifndef __ASM_ARCH_BOARD_H +#error "Don't include this file directly, include <mach/board.h>" +#endif + +#define GPIO_TOUCH_RESET 145 +#define GPIO_TOUCH_IRQ 144 + +#define GPIO_MAIN_SENSOR_RESET 44 +#define GPIO_MAIN_SENSOR_PWN 46 +#define GPIO_SUB_SENSOR_RESET 45 +#define GPIO_SUB_SENSOR_PWN 47 + +#define USB_OTG_CABLE_DETECT 126 + +#define SPRD_FLASH_OFST 0x890 +#define SPRD_FLASH_CTRL_BIT 0x8000 +#define SPRD_FLASH_LOW_VAL 0x3 +#define SPRD_FLASH_HIGH_VAL 0xF +#define SPRD_FLASH_LOW_CUR 110 +#define SPRD_FLASH_HIGH_CUR 470 + +#define GPIO_KEY_VOLUMEDOWN 124 +#define GPIO_KEY_VOLUMEUP 125 + +#define EIC_CHARGER_DETECT (A_EIC_START + 0) +#define EIC_POWER_PBINT2 (A_EIC_START + 1) +#define EIC_POWER_PBINT (A_EIC_START + 2) +#define EIC_AUD_HEAD_BUTTON (A_EIC_START + 3) +#define EIC_CHG_CV_STATE (A_EIC_START + 4) +#define EIC_AUD_HEAD_INST (A_EIC_START + 5) +#define EIC_VCHG_OVI (A_EIC_START + 6) +#define EIC_VBAT_OVI (A_EIC_START + 7) +#define EIC_AUD_HEAD_INST2 (A_EIC_START + 8) + +#define EIC_KEY_POWER (EIC_POWER_PBINT) + +#define HEADSET_BUTTON_GPIO (EIC_AUD_HEAD_BUTTON) +#define HEADSET_DETECT_GPIO (EIC_AUD_HEAD_INST2) +#define HEADSET_SWITCH_GPIO 0 + +#define HEADSET_IRQ_TRIGGER_LEVEL_DETECT 1 +#define HEADSET_IRQ_TRIGGER_LEVEL_BUTTON 1 + +#define HEADSET_ADC_MIN_KEY_MEDIA 0 +#define HEADSET_ADC_MAX_KEY_MEDIA 170 +#define HEADSET_ADC_MIN_KEY_VOLUMEUP 171 +#define HEADSET_ADC_MAX_KEY_VOLUMEUP 430 +#define HEADSET_ADC_MIN_KEY_VOLUMEDOWN 431 +#define HEADSET_ADC_MAX_KEY_VOLUMEDOWN 760 +#define HEADSET_ADC_THRESHOLD_3POLE_DETECT 100 +#define HEADSET_ADC_THRESHOLD_4POLE_DETECT 3100 +#define HEADSET_IRQ_THRESHOLD_BUTTON 1 +#define HEADSET_HEADMICBIAS_VOLTAGE 3000000 + +#define SPI0_CMMB_CS_GPIO 32 +#define SPI1_WIFI_CS_GPIO 44 + +#define GPIO_BK 143 +#define MSENSOR_DRDY_GPIO 53 +#define GPIO_PLSENSOR_IRQ 213 +/*For bcm4343 power on/off and sleep/wake */ +#define GPIO_BT_RESET 122 +#define GPIO_BT_POWER 131 +#define GPIO_BT2AP_WAKE 133 +#define GPIO_AP2BT_WAKE 132 + +/*#define GPIO_BT_RESET 194 */ +#define GPIO_WIFI_POWERON 189 +#define GPIO_WIFI_SHUTDOWN 130 +#define GPIO_WIFI_IRQ 97 + +#define GPIO_PROX_INT 140 +#define GPIO_GPS_ONOFF 174 + +#define GPIO_SDIO_DETECT 75 + +#define SPRD_PIN_SDIO0_OFFSET 0x01E0 +#define SPRD_PIN_SDIO0_SIZE 7 +#define SPRD_PIN_SDIO0_D3_INDEX 0 +#define SPRD_PIN_SDIO0_D3_GPIO 100 +#define SPRD_PIN_SDIO0_SD_FUNC 0 +#define SPRD_PIN_SDIO0_GPIO_FUNC 3 + +/*#define CP related featrue */ +#define SIPC_SMEM_ADDR (CONFIG_PHYS_OFFSET + 120 * SZ_1M) + +#define CPT_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#define CPT_TOTAL_SIZE (SZ_1M * 18) +#define CPT_RING_ADDR (CPT_START_ADDR + CPT_TOTAL_SIZE - SZ_4K) +#define CPT_RING_SIZE (SZ_4K) +#define CPT_SMEM_SIZE (SZ_1M * 2) + +#define CPW_START_ADDR (CONFIG_PHYS_OFFSET + 150* SZ_1M) +#define CPW_TOTAL_SIZE (SZ_1M * 33) +#define CPW_RING_ADDR (CPW_START_ADDR + CPW_TOTAL_SIZE - SZ_4K) +#define CPW_RING_SIZE (SZ_4K) +#define CPW_SMEM_SIZE (SZ_1M * 2) + +#define WCN_START_ADDR (CONFIG_PHYS_OFFSET + 320 * SZ_1M) +#define WCN_TOTAL_SIZE (SZ_1M * 5) +#define WCN_RING_ADDR (WCN_START_ADDR + WCN_TOTAL_SIZE - SZ_4K) +#define WCN_RING_SIZE (SZ_4K) +#define WCN_SMEM_SIZE (SZ_1M * 2) + +#define GGE_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#define GGE_TOTAL_SIZE (SZ_1M * 22) +#define GGE_RING_ADDR (GGE_START_ADDR + GGE_TOTAL_SIZE - SZ_4K) +#define GGE_RING_SIZE (SZ_4K) +#define GGE_SMEM_SIZE (SZ_1M * 2) + +#define LTE_START_ADDR (CONFIG_PHYS_OFFSET + 150 * SZ_1M) +#define LTE_TOTAL_SIZE (SZ_1M * 93) +#define LTE_RING_ADDR (LTE_START_ADDR + LTE_TOTAL_SIZE - SZ_4K) +#define LTE_RING_SIZE (SZ_4K) +#define LTE_SMEM_SIZE (SZ_1M * 2) + +#endif diff --git a/include/soc/sprd/__board-sp9830aeb_5m_h100.h b/include/soc/sprd/__board-sp9830aeb_5m_h100.h new file mode 100644 index 00000000..654212a2 --- /dev/null +++ b/include/soc/sprd/__board-sp9830aeb_5m_h100.h @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __GPIO_SC8810_H__ +#define __GPIO_SC8810_H__ + +#ifndef __ASM_ARCH_BOARD_H +#error "Don't include this file directly, include <mach/board.h>" +#endif + +#define GPIO_TOUCH_RESET 145 +#define GPIO_TOUCH_IRQ 144 + +#define GPIO_MAIN_SENSOR_RESET 44 +#define GPIO_MAIN_SENSOR_PWN 46 +#define GPIO_SUB_SENSOR_RESET 45 +#define GPIO_SUB_SENSOR_PWN 47 + +#define USB_OTG_CABLE_DETECT 126 + +#define SPRD_FLASH_OFST 0x890 +#define SPRD_FLASH_CTRL_BIT 0x8000 +#define SPRD_FLASH_LOW_VAL 0x3 +#define SPRD_FLASH_HIGH_VAL 0xF +#define SPRD_FLASH_LOW_CUR 110 +#define SPRD_FLASH_HIGH_CUR 470 + +#define GPIO_KEY_VOLUMEDOWN 124 +#define GPIO_KEY_VOLUMEUP 125 + +#define EIC_CHARGER_DETECT (A_EIC_START + 0) +#define EIC_POWER_PBINT2 (A_EIC_START + 1) +#define EIC_POWER_PBINT (A_EIC_START + 2) +#define EIC_AUD_HEAD_BUTTON (A_EIC_START + 3) +#define EIC_CHG_CV_STATE (A_EIC_START + 4) +#define EIC_AUD_HEAD_INST (A_EIC_START + 5) +#define EIC_VCHG_OVI (A_EIC_START + 6) +#define EIC_VBAT_OVI (A_EIC_START + 7) +#define EIC_AUD_HEAD_INST2 (A_EIC_START + 8) + +#define EIC_KEY_POWER (EIC_POWER_PBINT) + +#define HEADSET_BUTTON_GPIO (EIC_AUD_HEAD_BUTTON) +#define HEADSET_DETECT_GPIO (EIC_AUD_HEAD_INST2) +#define HEADSET_SWITCH_GPIO 0 + +#define HEADSET_IRQ_TRIGGER_LEVEL_DETECT 1 +#define HEADSET_IRQ_TRIGGER_LEVEL_BUTTON 1 + +#define HEADSET_ADC_MIN_KEY_MEDIA 0 +#define HEADSET_ADC_MAX_KEY_MEDIA 170 +#define HEADSET_ADC_MIN_KEY_VOLUMEUP 171 +#define HEADSET_ADC_MAX_KEY_VOLUMEUP 430 +#define HEADSET_ADC_MIN_KEY_VOLUMEDOWN 431 +#define HEADSET_ADC_MAX_KEY_VOLUMEDOWN 760 +#define HEADSET_ADC_THRESHOLD_3POLE_DETECT 100 +#define HEADSET_ADC_THRESHOLD_4POLE_DETECT 3100 +#define HEADSET_IRQ_THRESHOLD_BUTTON 1 +#define HEADSET_HEADMICBIAS_VOLTAGE 3000000 + +#define SPI0_CMMB_CS_GPIO 32 +#define SPI1_WIFI_CS_GPIO 44 + +#define GPIO_BK 143 +#define MSENSOR_DRDY_GPIO 53 +#define GPIO_PLSENSOR_IRQ 213 +/*For bcm4343 power on/off and sleep/wake */ +#define GPIO_BT_RESET 122 +#define GPIO_BT_POWER 131 +#define GPIO_BT2AP_WAKE 133 +#define GPIO_AP2BT_WAKE 132 + +/*#define GPIO_BT_RESET 194 */ +#define GPIO_WIFI_POWERON 189 +#define GPIO_WIFI_SHUTDOWN 130 +#define GPIO_WIFI_IRQ 97 + +#define GPIO_PROX_INT 140 +#define GPIO_GPS_ONOFF 174 + +#define GPIO_SDIO_DETECT 75 + +#define SPRD_PIN_SDIO0_OFFSET 0x01E0 +#define SPRD_PIN_SDIO0_SIZE 7 +#define SPRD_PIN_SDIO0_D3_INDEX 0 +#define SPRD_PIN_SDIO0_D3_GPIO 100 +#define SPRD_PIN_SDIO0_SD_FUNC 0 +#define SPRD_PIN_SDIO0_GPIO_FUNC 3 + +/*#define CP related featrue */ +#define SIPC_SMEM_ADDR (CONFIG_PHYS_OFFSET + 120 * SZ_1M) + +#define CPT_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#define CPT_TOTAL_SIZE (SZ_1M * 18) +#define CPT_RING_ADDR (CPT_START_ADDR + CPT_TOTAL_SIZE - SZ_4K) +#define CPT_RING_SIZE (SZ_4K) +#define CPT_SMEM_SIZE (SZ_1M * 2) + +#define CPW_START_ADDR (CONFIG_PHYS_OFFSET + 150* SZ_1M) +#define CPW_TOTAL_SIZE (SZ_1M * 33) +#define CPW_RING_ADDR (CPW_START_ADDR + CPW_TOTAL_SIZE - SZ_4K) +#define CPW_RING_SIZE (SZ_4K) +#define CPW_SMEM_SIZE (SZ_1M * 2) + +#define WCN_START_ADDR (CONFIG_PHYS_OFFSET + 320 * SZ_1M) +#define WCN_TOTAL_SIZE (SZ_1M * 5) +#define WCN_RING_ADDR (WCN_START_ADDR + WCN_TOTAL_SIZE - SZ_4K) +#define WCN_RING_SIZE (SZ_4K) +#define WCN_SMEM_SIZE (SZ_1M * 2) + +#define GGE_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#define GGE_TOTAL_SIZE (SZ_1M * 22) +#define GGE_RING_ADDR (GGE_START_ADDR + GGE_TOTAL_SIZE - SZ_4K) +#define GGE_RING_SIZE (SZ_4K) +#define GGE_SMEM_SIZE (SZ_1M * 2) + +#define LTE_START_ADDR (CONFIG_PHYS_OFFSET + 150 * SZ_1M) +#define LTE_TOTAL_SIZE (SZ_1M * 83) +#define LTE_RING_ADDR (LTE_START_ADDR + LTE_TOTAL_SIZE - SZ_4K) +#define LTE_RING_SIZE (SZ_4K) +#define LTE_SMEM_SIZE (SZ_1M * 2) + +#endif diff --git a/include/soc/sprd/__board-sp9830aec_4m_h100.h b/include/soc/sprd/__board-sp9830aec_4m_h100.h new file mode 100644 index 00000000..654212a2 --- /dev/null +++ b/include/soc/sprd/__board-sp9830aec_4m_h100.h @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __GPIO_SC8810_H__ +#define __GPIO_SC8810_H__ + +#ifndef __ASM_ARCH_BOARD_H +#error "Don't include this file directly, include <mach/board.h>" +#endif + +#define GPIO_TOUCH_RESET 145 +#define GPIO_TOUCH_IRQ 144 + +#define GPIO_MAIN_SENSOR_RESET 44 +#define GPIO_MAIN_SENSOR_PWN 46 +#define GPIO_SUB_SENSOR_RESET 45 +#define GPIO_SUB_SENSOR_PWN 47 + +#define USB_OTG_CABLE_DETECT 126 + +#define SPRD_FLASH_OFST 0x890 +#define SPRD_FLASH_CTRL_BIT 0x8000 +#define SPRD_FLASH_LOW_VAL 0x3 +#define SPRD_FLASH_HIGH_VAL 0xF +#define SPRD_FLASH_LOW_CUR 110 +#define SPRD_FLASH_HIGH_CUR 470 + +#define GPIO_KEY_VOLUMEDOWN 124 +#define GPIO_KEY_VOLUMEUP 125 + +#define EIC_CHARGER_DETECT (A_EIC_START + 0) +#define EIC_POWER_PBINT2 (A_EIC_START + 1) +#define EIC_POWER_PBINT (A_EIC_START + 2) +#define EIC_AUD_HEAD_BUTTON (A_EIC_START + 3) +#define EIC_CHG_CV_STATE (A_EIC_START + 4) +#define EIC_AUD_HEAD_INST (A_EIC_START + 5) +#define EIC_VCHG_OVI (A_EIC_START + 6) +#define EIC_VBAT_OVI (A_EIC_START + 7) +#define EIC_AUD_HEAD_INST2 (A_EIC_START + 8) + +#define EIC_KEY_POWER (EIC_POWER_PBINT) + +#define HEADSET_BUTTON_GPIO (EIC_AUD_HEAD_BUTTON) +#define HEADSET_DETECT_GPIO (EIC_AUD_HEAD_INST2) +#define HEADSET_SWITCH_GPIO 0 + +#define HEADSET_IRQ_TRIGGER_LEVEL_DETECT 1 +#define HEADSET_IRQ_TRIGGER_LEVEL_BUTTON 1 + +#define HEADSET_ADC_MIN_KEY_MEDIA 0 +#define HEADSET_ADC_MAX_KEY_MEDIA 170 +#define HEADSET_ADC_MIN_KEY_VOLUMEUP 171 +#define HEADSET_ADC_MAX_KEY_VOLUMEUP 430 +#define HEADSET_ADC_MIN_KEY_VOLUMEDOWN 431 +#define HEADSET_ADC_MAX_KEY_VOLUMEDOWN 760 +#define HEADSET_ADC_THRESHOLD_3POLE_DETECT 100 +#define HEADSET_ADC_THRESHOLD_4POLE_DETECT 3100 +#define HEADSET_IRQ_THRESHOLD_BUTTON 1 +#define HEADSET_HEADMICBIAS_VOLTAGE 3000000 + +#define SPI0_CMMB_CS_GPIO 32 +#define SPI1_WIFI_CS_GPIO 44 + +#define GPIO_BK 143 +#define MSENSOR_DRDY_GPIO 53 +#define GPIO_PLSENSOR_IRQ 213 +/*For bcm4343 power on/off and sleep/wake */ +#define GPIO_BT_RESET 122 +#define GPIO_BT_POWER 131 +#define GPIO_BT2AP_WAKE 133 +#define GPIO_AP2BT_WAKE 132 + +/*#define GPIO_BT_RESET 194 */ +#define GPIO_WIFI_POWERON 189 +#define GPIO_WIFI_SHUTDOWN 130 +#define GPIO_WIFI_IRQ 97 + +#define GPIO_PROX_INT 140 +#define GPIO_GPS_ONOFF 174 + +#define GPIO_SDIO_DETECT 75 + +#define SPRD_PIN_SDIO0_OFFSET 0x01E0 +#define SPRD_PIN_SDIO0_SIZE 7 +#define SPRD_PIN_SDIO0_D3_INDEX 0 +#define SPRD_PIN_SDIO0_D3_GPIO 100 +#define SPRD_PIN_SDIO0_SD_FUNC 0 +#define SPRD_PIN_SDIO0_GPIO_FUNC 3 + +/*#define CP related featrue */ +#define SIPC_SMEM_ADDR (CONFIG_PHYS_OFFSET + 120 * SZ_1M) + +#define CPT_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#define CPT_TOTAL_SIZE (SZ_1M * 18) +#define CPT_RING_ADDR (CPT_START_ADDR + CPT_TOTAL_SIZE - SZ_4K) +#define CPT_RING_SIZE (SZ_4K) +#define CPT_SMEM_SIZE (SZ_1M * 2) + +#define CPW_START_ADDR (CONFIG_PHYS_OFFSET + 150* SZ_1M) +#define CPW_TOTAL_SIZE (SZ_1M * 33) +#define CPW_RING_ADDR (CPW_START_ADDR + CPW_TOTAL_SIZE - SZ_4K) +#define CPW_RING_SIZE (SZ_4K) +#define CPW_SMEM_SIZE (SZ_1M * 2) + +#define WCN_START_ADDR (CONFIG_PHYS_OFFSET + 320 * SZ_1M) +#define WCN_TOTAL_SIZE (SZ_1M * 5) +#define WCN_RING_ADDR (WCN_START_ADDR + WCN_TOTAL_SIZE - SZ_4K) +#define WCN_RING_SIZE (SZ_4K) +#define WCN_SMEM_SIZE (SZ_1M * 2) + +#define GGE_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#define GGE_TOTAL_SIZE (SZ_1M * 22) +#define GGE_RING_ADDR (GGE_START_ADDR + GGE_TOTAL_SIZE - SZ_4K) +#define GGE_RING_SIZE (SZ_4K) +#define GGE_SMEM_SIZE (SZ_1M * 2) + +#define LTE_START_ADDR (CONFIG_PHYS_OFFSET + 150 * SZ_1M) +#define LTE_TOTAL_SIZE (SZ_1M * 83) +#define LTE_RING_ADDR (LTE_START_ADDR + LTE_TOTAL_SIZE - SZ_4K) +#define LTE_RING_SIZE (SZ_4K) +#define LTE_SMEM_SIZE (SZ_1M * 2) + +#endif diff --git a/include/soc/sprd/__board-sp9830iea_4m_h100.h b/include/soc/sprd/__board-sp9830iea_4m_h100.h new file mode 100644 index 00000000..2959aea4 --- /dev/null +++ b/include/soc/sprd/__board-sp9830iea_4m_h100.h @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __GPIO_SC8810_H__ +#define __GPIO_SC8810_H__ + +#ifndef __ASM_ARCH_BOARD_H +#error "Don't include this file directly, include <mach/board.h>" +#endif + +#define GPIO_TOUCH_RESET 145 +#define GPIO_TOUCH_IRQ 144 + +#define GPIO_MAIN_SENSOR_RESET 44 +#define GPIO_MAIN_SENSOR_PWN 46 +#define GPIO_SUB_SENSOR_RESET 45 +#define GPIO_SUB_SENSOR_PWN 47 + +#define USB_OTG_CABLE_DETECT 126 + +#define SPRD_FLASH_OFST 0x890 +#define SPRD_FLASH_CTRL_BIT 0x8000 +#define SPRD_FLASH_LOW_VAL 0x3 +#define SPRD_FLASH_HIGH_VAL 0xF +#define SPRD_FLASH_LOW_CUR 110 +#define SPRD_FLASH_HIGH_CUR 470 + +#define GPIO_KEY_VOLUMEDOWN 124 +#define GPIO_KEY_VOLUMEUP 125 + +#define EIC_CHARGER_DETECT (A_EIC_START + 0) +#define EIC_POWER_PBINT2 (A_EIC_START + 1) +#define EIC_POWER_PBINT (A_EIC_START + 2) +#define EIC_AUD_HEAD_BUTTON (A_EIC_START + 3) +#define EIC_CHG_CV_STATE (A_EIC_START + 4) +#define EIC_AUD_HEAD_INST (A_EIC_START + 5) +#define EIC_VCHG_OVI (A_EIC_START + 6) +#define EIC_VBAT_OVI (A_EIC_START + 7) +#define EIC_AUD_HEAD_INST2 (A_EIC_START + 8) + +#define EIC_KEY_POWER (EIC_POWER_PBINT) + +#define HEADSET_BUTTON_GPIO (EIC_AUD_HEAD_BUTTON) +#define HEADSET_DETECT_GPIO (EIC_AUD_HEAD_INST2) +#define HEADSET_SWITCH_GPIO 0 + +#define HEADSET_IRQ_TRIGGER_LEVEL_DETECT 1 +#define HEADSET_IRQ_TRIGGER_LEVEL_BUTTON 1 + +#define HEADSET_ADC_MIN_KEY_MEDIA 0 +#define HEADSET_ADC_MAX_KEY_MEDIA 170 +#define HEADSET_ADC_MIN_KEY_VOLUMEUP 171 +#define HEADSET_ADC_MAX_KEY_VOLUMEUP 430 +#define HEADSET_ADC_MIN_KEY_VOLUMEDOWN 431 +#define HEADSET_ADC_MAX_KEY_VOLUMEDOWN 760 +#define HEADSET_ADC_THRESHOLD_3POLE_DETECT 100 +#define HEADSET_ADC_THRESHOLD_4POLE_DETECT 3100 +#define HEADSET_IRQ_THRESHOLD_BUTTON 1 +#define HEADSET_HEADMICBIAS_VOLTAGE 3000000 + +#define SPI0_CMMB_CS_GPIO 32 +#define SPI1_WIFI_CS_GPIO 44 + +#define GPIO_BK 143 +#define MSENSOR_DRDY_GPIO 53 +#define GPIO_PLSENSOR_IRQ 213 +/*For bcm4343 power on/off and sleep/wake */ +#define GPIO_BT_RESET 122 +#define GPIO_BT_POWER 131 +#define GPIO_BT2AP_WAKE 133 +#define GPIO_AP2BT_WAKE 132 + +/*#define GPIO_BT_RESET 194 */ +#define GPIO_WIFI_POWERON 189 +#define GPIO_WIFI_SHUTDOWN 130 +#define GPIO_WIFI_IRQ 97 + +#define GPIO_PROX_INT 140 +#define GPIO_GPS_ONOFF 174 + +#define GPIO_SDIO_DETECT 75 + +#define SPRD_PIN_SDIO0_OFFSET 0x01E0 +#define SPRD_PIN_SDIO0_SIZE 7 +#define SPRD_PIN_SDIO0_D3_INDEX 0 +#define SPRD_PIN_SDIO0_D3_GPIO 100 +#define SPRD_PIN_SDIO0_SD_FUNC 0 +#define SPRD_PIN_SDIO0_GPIO_FUNC 3 + +#define SIPC_SMEM_ADDR (CONFIG_PHYS_OFFSET + 120 * SZ_1M) +#define CPT_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#define CPT_TOTAL_SIZE (SZ_1M * 18) +#define CPT_RING_ADDR (CPT_START_ADDR + CPT_TOTAL_SIZE - SZ_4K) +#define CPT_RING_SIZE (SZ_4K) +#define CPT_SMEM_SIZE (SZ_1M * 2) +#define CPW_START_ADDR (CONFIG_PHYS_OFFSET + 150 * SZ_1M) +#define CPW_TOTAL_SIZE (SZ_1M * 33) +#define CPW_RING_ADDR (CPW_START_ADDR + CPW_TOTAL_SIZE - SZ_4K) +#define CPW_RING_SIZE (SZ_4K) +#define CPW_SMEM_SIZE (SZ_1M * 2) +#define WCN_START_ADDR (CONFIG_PHYS_OFFSET + 320 * SZ_1M) +#define WCN_TOTAL_SIZE (SZ_1M * 5) +#define WCN_RING_ADDR (WCN_START_ADDR + WCN_TOTAL_SIZE - SZ_4K) +#define WCN_RING_SIZE (SZ_4K) +#define WCN_SMEM_SIZE (SZ_1M * 2) +#define GGE_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#define GGE_TOTAL_SIZE (SZ_1M * 22) +#define GGE_RING_ADDR (GGE_START_ADDR + GGE_TOTAL_SIZE - SZ_4K) +#define GGE_RING_SIZE (SZ_4K) +#define GGE_SMEM_SIZE (SZ_1M * 2) +#define LTE_START_ADDR (CONFIG_PHYS_OFFSET + 150 * SZ_1M) +#define LTE_TOTAL_SIZE (SZ_1M * 80) +#define LTE_RING_ADDR (LTE_START_ADDR + LTE_TOTAL_SIZE - SZ_4K) +#define LTE_RING_SIZE (SZ_4K) +#define LTE_SMEM_SIZE (SZ_1M * 2) +#endif diff --git a/include/soc/sprd/__board-sp9830iea_5m_h100.h b/include/soc/sprd/__board-sp9830iea_5m_h100.h new file mode 100644 index 00000000..654212a2 --- /dev/null +++ b/include/soc/sprd/__board-sp9830iea_5m_h100.h @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __GPIO_SC8810_H__ +#define __GPIO_SC8810_H__ + +#ifndef __ASM_ARCH_BOARD_H +#error "Don't include this file directly, include <mach/board.h>" +#endif + +#define GPIO_TOUCH_RESET 145 +#define GPIO_TOUCH_IRQ 144 + +#define GPIO_MAIN_SENSOR_RESET 44 +#define GPIO_MAIN_SENSOR_PWN 46 +#define GPIO_SUB_SENSOR_RESET 45 +#define GPIO_SUB_SENSOR_PWN 47 + +#define USB_OTG_CABLE_DETECT 126 + +#define SPRD_FLASH_OFST 0x890 +#define SPRD_FLASH_CTRL_BIT 0x8000 +#define SPRD_FLASH_LOW_VAL 0x3 +#define SPRD_FLASH_HIGH_VAL 0xF +#define SPRD_FLASH_LOW_CUR 110 +#define SPRD_FLASH_HIGH_CUR 470 + +#define GPIO_KEY_VOLUMEDOWN 124 +#define GPIO_KEY_VOLUMEUP 125 + +#define EIC_CHARGER_DETECT (A_EIC_START + 0) +#define EIC_POWER_PBINT2 (A_EIC_START + 1) +#define EIC_POWER_PBINT (A_EIC_START + 2) +#define EIC_AUD_HEAD_BUTTON (A_EIC_START + 3) +#define EIC_CHG_CV_STATE (A_EIC_START + 4) +#define EIC_AUD_HEAD_INST (A_EIC_START + 5) +#define EIC_VCHG_OVI (A_EIC_START + 6) +#define EIC_VBAT_OVI (A_EIC_START + 7) +#define EIC_AUD_HEAD_INST2 (A_EIC_START + 8) + +#define EIC_KEY_POWER (EIC_POWER_PBINT) + +#define HEADSET_BUTTON_GPIO (EIC_AUD_HEAD_BUTTON) +#define HEADSET_DETECT_GPIO (EIC_AUD_HEAD_INST2) +#define HEADSET_SWITCH_GPIO 0 + +#define HEADSET_IRQ_TRIGGER_LEVEL_DETECT 1 +#define HEADSET_IRQ_TRIGGER_LEVEL_BUTTON 1 + +#define HEADSET_ADC_MIN_KEY_MEDIA 0 +#define HEADSET_ADC_MAX_KEY_MEDIA 170 +#define HEADSET_ADC_MIN_KEY_VOLUMEUP 171 +#define HEADSET_ADC_MAX_KEY_VOLUMEUP 430 +#define HEADSET_ADC_MIN_KEY_VOLUMEDOWN 431 +#define HEADSET_ADC_MAX_KEY_VOLUMEDOWN 760 +#define HEADSET_ADC_THRESHOLD_3POLE_DETECT 100 +#define HEADSET_ADC_THRESHOLD_4POLE_DETECT 3100 +#define HEADSET_IRQ_THRESHOLD_BUTTON 1 +#define HEADSET_HEADMICBIAS_VOLTAGE 3000000 + +#define SPI0_CMMB_CS_GPIO 32 +#define SPI1_WIFI_CS_GPIO 44 + +#define GPIO_BK 143 +#define MSENSOR_DRDY_GPIO 53 +#define GPIO_PLSENSOR_IRQ 213 +/*For bcm4343 power on/off and sleep/wake */ +#define GPIO_BT_RESET 122 +#define GPIO_BT_POWER 131 +#define GPIO_BT2AP_WAKE 133 +#define GPIO_AP2BT_WAKE 132 + +/*#define GPIO_BT_RESET 194 */ +#define GPIO_WIFI_POWERON 189 +#define GPIO_WIFI_SHUTDOWN 130 +#define GPIO_WIFI_IRQ 97 + +#define GPIO_PROX_INT 140 +#define GPIO_GPS_ONOFF 174 + +#define GPIO_SDIO_DETECT 75 + +#define SPRD_PIN_SDIO0_OFFSET 0x01E0 +#define SPRD_PIN_SDIO0_SIZE 7 +#define SPRD_PIN_SDIO0_D3_INDEX 0 +#define SPRD_PIN_SDIO0_D3_GPIO 100 +#define SPRD_PIN_SDIO0_SD_FUNC 0 +#define SPRD_PIN_SDIO0_GPIO_FUNC 3 + +/*#define CP related featrue */ +#define SIPC_SMEM_ADDR (CONFIG_PHYS_OFFSET + 120 * SZ_1M) + +#define CPT_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#define CPT_TOTAL_SIZE (SZ_1M * 18) +#define CPT_RING_ADDR (CPT_START_ADDR + CPT_TOTAL_SIZE - SZ_4K) +#define CPT_RING_SIZE (SZ_4K) +#define CPT_SMEM_SIZE (SZ_1M * 2) + +#define CPW_START_ADDR (CONFIG_PHYS_OFFSET + 150* SZ_1M) +#define CPW_TOTAL_SIZE (SZ_1M * 33) +#define CPW_RING_ADDR (CPW_START_ADDR + CPW_TOTAL_SIZE - SZ_4K) +#define CPW_RING_SIZE (SZ_4K) +#define CPW_SMEM_SIZE (SZ_1M * 2) + +#define WCN_START_ADDR (CONFIG_PHYS_OFFSET + 320 * SZ_1M) +#define WCN_TOTAL_SIZE (SZ_1M * 5) +#define WCN_RING_ADDR (WCN_START_ADDR + WCN_TOTAL_SIZE - SZ_4K) +#define WCN_RING_SIZE (SZ_4K) +#define WCN_SMEM_SIZE (SZ_1M * 2) + +#define GGE_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#define GGE_TOTAL_SIZE (SZ_1M * 22) +#define GGE_RING_ADDR (GGE_START_ADDR + GGE_TOTAL_SIZE - SZ_4K) +#define GGE_RING_SIZE (SZ_4K) +#define GGE_SMEM_SIZE (SZ_1M * 2) + +#define LTE_START_ADDR (CONFIG_PHYS_OFFSET + 150 * SZ_1M) +#define LTE_TOTAL_SIZE (SZ_1M * 83) +#define LTE_RING_ADDR (LTE_START_ADDR + LTE_TOTAL_SIZE - SZ_4K) +#define LTE_RING_SIZE (SZ_4K) +#define LTE_SMEM_SIZE (SZ_1M * 2) + +#endif diff --git a/include/soc/sprd/__board-sp9830ieb_5m_h100.h b/include/soc/sprd/__board-sp9830ieb_5m_h100.h new file mode 100644 index 00000000..654212a2 --- /dev/null +++ b/include/soc/sprd/__board-sp9830ieb_5m_h100.h @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __GPIO_SC8810_H__ +#define __GPIO_SC8810_H__ + +#ifndef __ASM_ARCH_BOARD_H +#error "Don't include this file directly, include <mach/board.h>" +#endif + +#define GPIO_TOUCH_RESET 145 +#define GPIO_TOUCH_IRQ 144 + +#define GPIO_MAIN_SENSOR_RESET 44 +#define GPIO_MAIN_SENSOR_PWN 46 +#define GPIO_SUB_SENSOR_RESET 45 +#define GPIO_SUB_SENSOR_PWN 47 + +#define USB_OTG_CABLE_DETECT 126 + +#define SPRD_FLASH_OFST 0x890 +#define SPRD_FLASH_CTRL_BIT 0x8000 +#define SPRD_FLASH_LOW_VAL 0x3 +#define SPRD_FLASH_HIGH_VAL 0xF +#define SPRD_FLASH_LOW_CUR 110 +#define SPRD_FLASH_HIGH_CUR 470 + +#define GPIO_KEY_VOLUMEDOWN 124 +#define GPIO_KEY_VOLUMEUP 125 + +#define EIC_CHARGER_DETECT (A_EIC_START + 0) +#define EIC_POWER_PBINT2 (A_EIC_START + 1) +#define EIC_POWER_PBINT (A_EIC_START + 2) +#define EIC_AUD_HEAD_BUTTON (A_EIC_START + 3) +#define EIC_CHG_CV_STATE (A_EIC_START + 4) +#define EIC_AUD_HEAD_INST (A_EIC_START + 5) +#define EIC_VCHG_OVI (A_EIC_START + 6) +#define EIC_VBAT_OVI (A_EIC_START + 7) +#define EIC_AUD_HEAD_INST2 (A_EIC_START + 8) + +#define EIC_KEY_POWER (EIC_POWER_PBINT) + +#define HEADSET_BUTTON_GPIO (EIC_AUD_HEAD_BUTTON) +#define HEADSET_DETECT_GPIO (EIC_AUD_HEAD_INST2) +#define HEADSET_SWITCH_GPIO 0 + +#define HEADSET_IRQ_TRIGGER_LEVEL_DETECT 1 +#define HEADSET_IRQ_TRIGGER_LEVEL_BUTTON 1 + +#define HEADSET_ADC_MIN_KEY_MEDIA 0 +#define HEADSET_ADC_MAX_KEY_MEDIA 170 +#define HEADSET_ADC_MIN_KEY_VOLUMEUP 171 +#define HEADSET_ADC_MAX_KEY_VOLUMEUP 430 +#define HEADSET_ADC_MIN_KEY_VOLUMEDOWN 431 +#define HEADSET_ADC_MAX_KEY_VOLUMEDOWN 760 +#define HEADSET_ADC_THRESHOLD_3POLE_DETECT 100 +#define HEADSET_ADC_THRESHOLD_4POLE_DETECT 3100 +#define HEADSET_IRQ_THRESHOLD_BUTTON 1 +#define HEADSET_HEADMICBIAS_VOLTAGE 3000000 + +#define SPI0_CMMB_CS_GPIO 32 +#define SPI1_WIFI_CS_GPIO 44 + +#define GPIO_BK 143 +#define MSENSOR_DRDY_GPIO 53 +#define GPIO_PLSENSOR_IRQ 213 +/*For bcm4343 power on/off and sleep/wake */ +#define GPIO_BT_RESET 122 +#define GPIO_BT_POWER 131 +#define GPIO_BT2AP_WAKE 133 +#define GPIO_AP2BT_WAKE 132 + +/*#define GPIO_BT_RESET 194 */ +#define GPIO_WIFI_POWERON 189 +#define GPIO_WIFI_SHUTDOWN 130 +#define GPIO_WIFI_IRQ 97 + +#define GPIO_PROX_INT 140 +#define GPIO_GPS_ONOFF 174 + +#define GPIO_SDIO_DETECT 75 + +#define SPRD_PIN_SDIO0_OFFSET 0x01E0 +#define SPRD_PIN_SDIO0_SIZE 7 +#define SPRD_PIN_SDIO0_D3_INDEX 0 +#define SPRD_PIN_SDIO0_D3_GPIO 100 +#define SPRD_PIN_SDIO0_SD_FUNC 0 +#define SPRD_PIN_SDIO0_GPIO_FUNC 3 + +/*#define CP related featrue */ +#define SIPC_SMEM_ADDR (CONFIG_PHYS_OFFSET + 120 * SZ_1M) + +#define CPT_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#define CPT_TOTAL_SIZE (SZ_1M * 18) +#define CPT_RING_ADDR (CPT_START_ADDR + CPT_TOTAL_SIZE - SZ_4K) +#define CPT_RING_SIZE (SZ_4K) +#define CPT_SMEM_SIZE (SZ_1M * 2) + +#define CPW_START_ADDR (CONFIG_PHYS_OFFSET + 150* SZ_1M) +#define CPW_TOTAL_SIZE (SZ_1M * 33) +#define CPW_RING_ADDR (CPW_START_ADDR + CPW_TOTAL_SIZE - SZ_4K) +#define CPW_RING_SIZE (SZ_4K) +#define CPW_SMEM_SIZE (SZ_1M * 2) + +#define WCN_START_ADDR (CONFIG_PHYS_OFFSET + 320 * SZ_1M) +#define WCN_TOTAL_SIZE (SZ_1M * 5) +#define WCN_RING_ADDR (WCN_START_ADDR + WCN_TOTAL_SIZE - SZ_4K) +#define WCN_RING_SIZE (SZ_4K) +#define WCN_SMEM_SIZE (SZ_1M * 2) + +#define GGE_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#define GGE_TOTAL_SIZE (SZ_1M * 22) +#define GGE_RING_ADDR (GGE_START_ADDR + GGE_TOTAL_SIZE - SZ_4K) +#define GGE_RING_SIZE (SZ_4K) +#define GGE_SMEM_SIZE (SZ_1M * 2) + +#define LTE_START_ADDR (CONFIG_PHYS_OFFSET + 150 * SZ_1M) +#define LTE_TOTAL_SIZE (SZ_1M * 83) +#define LTE_RING_ADDR (LTE_START_ADDR + LTE_TOTAL_SIZE - SZ_4K) +#define LTE_RING_SIZE (SZ_4K) +#define LTE_SMEM_SIZE (SZ_1M * 2) + +#endif diff --git a/include/soc/sprd/__board-sp9830iec_4m_h100.h b/include/soc/sprd/__board-sp9830iec_4m_h100.h new file mode 100644 index 00000000..654212a2 --- /dev/null +++ b/include/soc/sprd/__board-sp9830iec_4m_h100.h @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __GPIO_SC8810_H__ +#define __GPIO_SC8810_H__ + +#ifndef __ASM_ARCH_BOARD_H +#error "Don't include this file directly, include <mach/board.h>" +#endif + +#define GPIO_TOUCH_RESET 145 +#define GPIO_TOUCH_IRQ 144 + +#define GPIO_MAIN_SENSOR_RESET 44 +#define GPIO_MAIN_SENSOR_PWN 46 +#define GPIO_SUB_SENSOR_RESET 45 +#define GPIO_SUB_SENSOR_PWN 47 + +#define USB_OTG_CABLE_DETECT 126 + +#define SPRD_FLASH_OFST 0x890 +#define SPRD_FLASH_CTRL_BIT 0x8000 +#define SPRD_FLASH_LOW_VAL 0x3 +#define SPRD_FLASH_HIGH_VAL 0xF +#define SPRD_FLASH_LOW_CUR 110 +#define SPRD_FLASH_HIGH_CUR 470 + +#define GPIO_KEY_VOLUMEDOWN 124 +#define GPIO_KEY_VOLUMEUP 125 + +#define EIC_CHARGER_DETECT (A_EIC_START + 0) +#define EIC_POWER_PBINT2 (A_EIC_START + 1) +#define EIC_POWER_PBINT (A_EIC_START + 2) +#define EIC_AUD_HEAD_BUTTON (A_EIC_START + 3) +#define EIC_CHG_CV_STATE (A_EIC_START + 4) +#define EIC_AUD_HEAD_INST (A_EIC_START + 5) +#define EIC_VCHG_OVI (A_EIC_START + 6) +#define EIC_VBAT_OVI (A_EIC_START + 7) +#define EIC_AUD_HEAD_INST2 (A_EIC_START + 8) + +#define EIC_KEY_POWER (EIC_POWER_PBINT) + +#define HEADSET_BUTTON_GPIO (EIC_AUD_HEAD_BUTTON) +#define HEADSET_DETECT_GPIO (EIC_AUD_HEAD_INST2) +#define HEADSET_SWITCH_GPIO 0 + +#define HEADSET_IRQ_TRIGGER_LEVEL_DETECT 1 +#define HEADSET_IRQ_TRIGGER_LEVEL_BUTTON 1 + +#define HEADSET_ADC_MIN_KEY_MEDIA 0 +#define HEADSET_ADC_MAX_KEY_MEDIA 170 +#define HEADSET_ADC_MIN_KEY_VOLUMEUP 171 +#define HEADSET_ADC_MAX_KEY_VOLUMEUP 430 +#define HEADSET_ADC_MIN_KEY_VOLUMEDOWN 431 +#define HEADSET_ADC_MAX_KEY_VOLUMEDOWN 760 +#define HEADSET_ADC_THRESHOLD_3POLE_DETECT 100 +#define HEADSET_ADC_THRESHOLD_4POLE_DETECT 3100 +#define HEADSET_IRQ_THRESHOLD_BUTTON 1 +#define HEADSET_HEADMICBIAS_VOLTAGE 3000000 + +#define SPI0_CMMB_CS_GPIO 32 +#define SPI1_WIFI_CS_GPIO 44 + +#define GPIO_BK 143 +#define MSENSOR_DRDY_GPIO 53 +#define GPIO_PLSENSOR_IRQ 213 +/*For bcm4343 power on/off and sleep/wake */ +#define GPIO_BT_RESET 122 +#define GPIO_BT_POWER 131 +#define GPIO_BT2AP_WAKE 133 +#define GPIO_AP2BT_WAKE 132 + +/*#define GPIO_BT_RESET 194 */ +#define GPIO_WIFI_POWERON 189 +#define GPIO_WIFI_SHUTDOWN 130 +#define GPIO_WIFI_IRQ 97 + +#define GPIO_PROX_INT 140 +#define GPIO_GPS_ONOFF 174 + +#define GPIO_SDIO_DETECT 75 + +#define SPRD_PIN_SDIO0_OFFSET 0x01E0 +#define SPRD_PIN_SDIO0_SIZE 7 +#define SPRD_PIN_SDIO0_D3_INDEX 0 +#define SPRD_PIN_SDIO0_D3_GPIO 100 +#define SPRD_PIN_SDIO0_SD_FUNC 0 +#define SPRD_PIN_SDIO0_GPIO_FUNC 3 + +/*#define CP related featrue */ +#define SIPC_SMEM_ADDR (CONFIG_PHYS_OFFSET + 120 * SZ_1M) + +#define CPT_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#define CPT_TOTAL_SIZE (SZ_1M * 18) +#define CPT_RING_ADDR (CPT_START_ADDR + CPT_TOTAL_SIZE - SZ_4K) +#define CPT_RING_SIZE (SZ_4K) +#define CPT_SMEM_SIZE (SZ_1M * 2) + +#define CPW_START_ADDR (CONFIG_PHYS_OFFSET + 150* SZ_1M) +#define CPW_TOTAL_SIZE (SZ_1M * 33) +#define CPW_RING_ADDR (CPW_START_ADDR + CPW_TOTAL_SIZE - SZ_4K) +#define CPW_RING_SIZE (SZ_4K) +#define CPW_SMEM_SIZE (SZ_1M * 2) + +#define WCN_START_ADDR (CONFIG_PHYS_OFFSET + 320 * SZ_1M) +#define WCN_TOTAL_SIZE (SZ_1M * 5) +#define WCN_RING_ADDR (WCN_START_ADDR + WCN_TOTAL_SIZE - SZ_4K) +#define WCN_RING_SIZE (SZ_4K) +#define WCN_SMEM_SIZE (SZ_1M * 2) + +#define GGE_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#define GGE_TOTAL_SIZE (SZ_1M * 22) +#define GGE_RING_ADDR (GGE_START_ADDR + GGE_TOTAL_SIZE - SZ_4K) +#define GGE_RING_SIZE (SZ_4K) +#define GGE_SMEM_SIZE (SZ_1M * 2) + +#define LTE_START_ADDR (CONFIG_PHYS_OFFSET + 150 * SZ_1M) +#define LTE_TOTAL_SIZE (SZ_1M * 83) +#define LTE_RING_ADDR (LTE_START_ADDR + LTE_TOTAL_SIZE - SZ_4K) +#define LTE_RING_SIZE (SZ_4K) +#define LTE_SMEM_SIZE (SZ_1M * 2) + +#endif diff --git a/include/soc/sprd/__board-sp9836aea.h b/include/soc/sprd/__board-sp9836aea.h new file mode 100644 index 00000000..35ef27a7 --- /dev/null +++ b/include/soc/sprd/__board-sp9836aea.h @@ -0,0 +1,136 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __GPIO_SC8810_H__ +#define __GPIO_SC8810_H__ + +#ifndef __ASM_ARCH_BOARD_H +#error "Don't include this file directly, include <mach/board.h>" +#endif + +#define GPIO_TOUCH_RESET 145 +#define GPIO_TOUCH_IRQ 144 + +#define GPIO_MAIN_SENSOR_RESET 44 +#define GPIO_MAIN_SENSOR_PWN 46 +#define GPIO_SUB_SENSOR_RESET 45 +#define GPIO_SUB_SENSOR_PWN 47 + +#define USB_OTG_CABLE_DETECT 126 + +#define SPRD_FLASH_OFST 0x890 +#define SPRD_FLASH_CTRL_BIT 0x8000 +#define SPRD_FLASH_LOW_VAL 0x3 +#define SPRD_FLASH_HIGH_VAL 0xF +#define SPRD_FLASH_LOW_CUR 110 +#define SPRD_FLASH_HIGH_CUR 470 + +#define GPIO_KEY_VOLUMEDOWN 124 +#define GPIO_KEY_VOLUMEUP 125 +//#define GPIO_KEY_CAMERA 0 +//#define GPIO_KEY_HOME 0 + +#define EIC_CHARGER_DETECT (A_EIC_START + 0) +#define EIC_POWER_PBINT2 (A_EIC_START + 1) +#define EIC_POWER_PBINT (A_EIC_START + 2) +#define EIC_AUD_HEAD_BUTTON (A_EIC_START + 3) +#define EIC_CHG_CV_STATE (A_EIC_START + 4) +#define EIC_AUD_HEAD_INST (A_EIC_START + 5) +#define EIC_VCHG_OVI (A_EIC_START + 6) +#define EIC_VBAT_OVI (A_EIC_START + 7) +#define EIC_AUD_HEAD_INST2 (A_EIC_START + 8) + +#define EIC_KEY_POWER (EIC_POWER_PBINT) + +#define HEADSET_BUTTON_GPIO (EIC_AUD_HEAD_BUTTON) +#define HEADSET_DETECT_GPIO (EIC_AUD_HEAD_INST2) +#define HEADSET_SWITCH_GPIO 0 + +#define HEADSET_IRQ_TRIGGER_LEVEL_DETECT 1 +#define HEADSET_IRQ_TRIGGER_LEVEL_BUTTON 1 + +#define HEADSET_ADC_MIN_KEY_MEDIA 0 +#define HEADSET_ADC_MAX_KEY_MEDIA 170 +#define HEADSET_ADC_MIN_KEY_VOLUMEUP 171 +#define HEADSET_ADC_MAX_KEY_VOLUMEUP 430 +#define HEADSET_ADC_MIN_KEY_VOLUMEDOWN 431 +#define HEADSET_ADC_MAX_KEY_VOLUMEDOWN 760 +#define HEADSET_ADC_THRESHOLD_3POLE_DETECT 100 +#define HEADSET_ADC_THRESHOLD_4POLE_DETECT 3100 +#define HEADSET_IRQ_THRESHOLD_BUTTON 1 +#define HEADSET_HEADMICBIAS_VOLTAGE 3000000 + +#define SPI0_CMMB_CS_GPIO 32 +#define SPI1_WIFI_CS_GPIO 44 + +#define GPIO_BK 143 +#define MSENSOR_DRDY_GPIO 53 +#define GPIO_PLSENSOR_IRQ 213 +/*For bcm4343 power on/off and sleep/wake */ +#define GPIO_BT_RESET 122 +#define GPIO_BT_POWER 131 +#define GPIO_BT2AP_WAKE 133 +#define GPIO_AP2BT_WAKE 132 + +/*#define GPIO_BT_RESET 194 */ +#define GPIO_WIFI_POWERON 189 +#define GPIO_WIFI_SHUTDOWN 130 +#define GPIO_WIFI_IRQ 97 + +#define GPIO_PROX_INT 140 +#define GPIO_GPS_ONOFF 174 + +#define GPIO_SDIO_DETECT 75 + +#define SPRD_PIN_SDIO0_OFFSET 0x01E0 +#define SPRD_PIN_SDIO0_SIZE 7 +#define SPRD_PIN_SDIO0_D3_INDEX 0 +#define SPRD_PIN_SDIO0_D3_GPIO 100 +#define SPRD_PIN_SDIO0_SD_FUNC 0 +#define SPRD_PIN_SDIO0_GPIO_FUNC 3 + +/*#define CP related featrue */ +#define SIPC_SMEM_ADDR (CONFIG_PHYS_OFFSET + 120 * SZ_1M) + +#define CPT_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#define CPT_TOTAL_SIZE (SZ_1M * 18) +#define CPT_RING_ADDR (CPT_START_ADDR + CPT_TOTAL_SIZE - SZ_4K) +#define CPT_RING_SIZE (SZ_4K) +#define CPT_SMEM_SIZE (SZ_1M * 2) + +#define CPW_START_ADDR (CONFIG_PHYS_OFFSET + 150* SZ_1M) +#define CPW_TOTAL_SIZE (SZ_1M * 33) +#define CPW_RING_ADDR (CPW_START_ADDR + CPW_TOTAL_SIZE - SZ_4K) +#define CPW_RING_SIZE (SZ_4K) +#define CPW_SMEM_SIZE (SZ_1M * 2) + +#define WCN_START_ADDR (CONFIG_PHYS_OFFSET + 320 * SZ_1M) +#define WCN_TOTAL_SIZE (SZ_1M * 5) +#define WCN_RING_ADDR (WCN_START_ADDR + WCN_TOTAL_SIZE - SZ_4K) +#define WCN_RING_SIZE (SZ_4K) +#define WCN_SMEM_SIZE (SZ_1M * 2) + +#define GGE_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#define GGE_TOTAL_SIZE (SZ_1M * 22) +#define GGE_RING_ADDR (GGE_START_ADDR + GGE_TOTAL_SIZE - SZ_4K) +#define GGE_RING_SIZE (SZ_4K) +#define GGE_SMEM_SIZE (SZ_1M * 2) + +#define LTE_START_ADDR (CONFIG_PHYS_OFFSET + 150 * SZ_1M) +#define LTE_TOTAL_SIZE (SZ_1M * 80) +#define LTE_RING_ADDR (LTE_START_ADDR + LTE_TOTAL_SIZE - SZ_4K) +#define LTE_RING_SIZE (SZ_4K) +#define LTE_SMEM_SIZE (SZ_1M * 2) + + +#endif diff --git a/include/soc/sprd/__board-sp9838aea.h b/include/soc/sprd/__board-sp9838aea.h new file mode 100644 index 00000000..a79c91eb --- /dev/null +++ b/include/soc/sprd/__board-sp9838aea.h @@ -0,0 +1,136 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __GPIO_SC8810_H__ +#define __GPIO_SC8810_H__ + +#ifndef __ASM_ARCH_BOARD_H +#error "Don't include this file directly, include <mach/board.h>" +#endif + +#define GPIO_TOUCH_RESET 145 +#define GPIO_TOUCH_IRQ 144 + +#define GPIO_MAIN_SENSOR_RESET 44 +#define GPIO_MAIN_SENSOR_PWN 46 +#define GPIO_SUB_SENSOR_RESET 45 +#define GPIO_SUB_SENSOR_PWN 47 + +#define USB_OTG_CABLE_DETECT 126 + +#define SPRD_FLASH_OFST 0x890 +#define SPRD_FLASH_CTRL_BIT 0x8000 +#define SPRD_FLASH_LOW_VAL 0x3 +#define SPRD_FLASH_HIGH_VAL 0xF +#define SPRD_FLASH_LOW_CUR 110 +#define SPRD_FLASH_HIGH_CUR 470 + +#define GPIO_KEY_VOLUMEDOWN 124 +#define GPIO_KEY_VOLUMEUP 125 +//#define GPIO_KEY_CAMERA 0 +//#define GPIO_KEY_HOME 0 + +#define EIC_CHARGER_DETECT (A_EIC_START + 0) +#define EIC_POWER_PBINT2 (A_EIC_START + 1) +#define EIC_POWER_PBINT (A_EIC_START + 2) +#define EIC_AUD_HEAD_BUTTON (A_EIC_START + 3) +#define EIC_CHG_CV_STATE (A_EIC_START + 4) +#define EIC_AUD_HEAD_INST (A_EIC_START + 5) +#define EIC_VCHG_OVI (A_EIC_START + 6) +#define EIC_VBAT_OVI (A_EIC_START + 7) +#define EIC_AUD_HEAD_INST2 (A_EIC_START + 8) + +#define EIC_KEY_POWER (EIC_POWER_PBINT) + +#define HEADSET_BUTTON_GPIO (EIC_AUD_HEAD_BUTTON) +#define HEADSET_DETECT_GPIO (EIC_AUD_HEAD_INST2) +#define HEADSET_SWITCH_GPIO 0 + +#define HEADSET_IRQ_TRIGGER_LEVEL_DETECT 1 +#define HEADSET_IRQ_TRIGGER_LEVEL_BUTTON 1 + +#define HEADSET_ADC_MIN_KEY_MEDIA 0 +#define HEADSET_ADC_MAX_KEY_MEDIA 170 +#define HEADSET_ADC_MIN_KEY_VOLUMEUP 171 +#define HEADSET_ADC_MAX_KEY_VOLUMEUP 430 +#define HEADSET_ADC_MIN_KEY_VOLUMEDOWN 431 +#define HEADSET_ADC_MAX_KEY_VOLUMEDOWN 760 +#define HEADSET_ADC_THRESHOLD_3POLE_DETECT 100 +#define HEADSET_ADC_THRESHOLD_4POLE_DETECT 3100 +#define HEADSET_IRQ_THRESHOLD_BUTTON 1 +#define HEADSET_HEADMICBIAS_VOLTAGE 3000000 + +#define SPI0_CMMB_CS_GPIO 32 +#define SPI1_WIFI_CS_GPIO 44 + +#define GPIO_BK 143 +#define MSENSOR_DRDY_GPIO 53 +#define GPIO_PLSENSOR_IRQ 213 +/*For bcm4343 power on/off and sleep/wake */ +#define GPIO_BT_RESET 122 +#define GPIO_BT_POWER 131 +#define GPIO_BT2AP_WAKE 133 +#define GPIO_AP2BT_WAKE 132 + +/*#define GPIO_BT_RESET 194 */ +#define GPIO_WIFI_POWERON 189 +#define GPIO_WIFI_SHUTDOWN 130 +#define GPIO_WIFI_IRQ 97 + +#define GPIO_PROX_INT 140 +#define GPIO_GPS_ONOFF 174 + +#define GPIO_SDIO_DETECT 75 + +#define SPRD_PIN_SDIO0_OFFSET 0x01E0 +#define SPRD_PIN_SDIO0_SIZE 7 +#define SPRD_PIN_SDIO0_D3_INDEX 0 +#define SPRD_PIN_SDIO0_D3_GPIO 100 +#define SPRD_PIN_SDIO0_SD_FUNC 0 +#define SPRD_PIN_SDIO0_GPIO_FUNC 3 + +/*#define CP related featrue */ +#define SIPC_SMEM_ADDR (CONFIG_PHYS_OFFSET + 120 * SZ_1M) + +#define CPT_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#define CPT_TOTAL_SIZE (SZ_1M * 18) +#define CPT_RING_ADDR (CPT_START_ADDR + CPT_TOTAL_SIZE - SZ_4K) +#define CPT_RING_SIZE (SZ_4K) +#define CPT_SMEM_SIZE (SZ_1M * 2) + +#define CPW_START_ADDR (CONFIG_PHYS_OFFSET + 150* SZ_1M) +#define CPW_TOTAL_SIZE (SZ_1M * 33) +#define CPW_RING_ADDR (CPW_START_ADDR + CPW_TOTAL_SIZE - SZ_4K) +#define CPW_RING_SIZE (SZ_4K) +#define CPW_SMEM_SIZE (SZ_1M * 2) + +#define WCN_START_ADDR (CONFIG_PHYS_OFFSET + 320 * SZ_1M) +#define WCN_TOTAL_SIZE (SZ_1M * 5) +#define WCN_RING_ADDR (WCN_START_ADDR + WCN_TOTAL_SIZE - SZ_4K) +#define WCN_RING_SIZE (SZ_4K) +#define WCN_SMEM_SIZE (SZ_1M * 2) + +#define GGE_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#define GGE_TOTAL_SIZE (SZ_1M * 22) +#define GGE_RING_ADDR (GGE_START_ADDR + GGE_TOTAL_SIZE - SZ_4K) +#define GGE_RING_SIZE (SZ_4K) +#define GGE_SMEM_SIZE (SZ_1M * 2) + +#define LTE_START_ADDR (CONFIG_PHYS_OFFSET + 150 * SZ_1M) +#define LTE_TOTAL_SIZE (SZ_1M * 83) +#define LTE_RING_ADDR (LTE_START_ADDR + LTE_TOTAL_SIZE - SZ_4K) +#define LTE_RING_SIZE (SZ_4K) +#define LTE_SMEM_SIZE (SZ_1M * 2) + + +#endif diff --git a/include/soc/sprd/__board-ss_sharklt8.h b/include/soc/sprd/__board-ss_sharklt8.h new file mode 100644 index 00000000..b0cdf7ed --- /dev/null +++ b/include/soc/sprd/__board-ss_sharklt8.h @@ -0,0 +1,136 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __BOARD_SS_SHARKLT8_H__ +#define __BOARD_SS_SHARKLT8_H__ + +#ifndef __ASM_ARCH_BOARD_H +#error "Don't include this file directly, include <mach/board.h>" +#endif + +#define GPIO_TOUCH_RESET 145 +#define GPIO_TOUCH_IRQ 144 + +#define GPIO_MAIN_SENSOR_RESET 44 +#define GPIO_MAIN_SENSOR_PWN 46 +#define GPIO_SUB_SENSOR_RESET 45 +#define GPIO_SUB_SENSOR_PWN 47 + +#define USB_OTG_CABLE_DETECT 126 + +#define SPRD_FLASH_OFST 0x890 +#define SPRD_FLASH_CTRL_BIT 0x8000 +#define SPRD_FLASH_LOW_VAL 0x3 +#define SPRD_FLASH_HIGH_VAL 0xF +#define SPRD_FLASH_LOW_CUR 110 +#define SPRD_FLASH_HIGH_CUR 470 + +#define GPIO_KEY_VOLUMEDOWN 124 +#define GPIO_KEY_VOLUMEUP 125 +//#define GPIO_KEY_CAMERA 0 +//#define GPIO_KEY_HOME 0 + +#define EIC_CHARGER_DETECT (A_EIC_START + 0) +#define EIC_POWER_PBINT2 (A_EIC_START + 1) +#define EIC_POWER_PBINT (A_EIC_START + 2) +#define EIC_AUD_HEAD_BUTTON (A_EIC_START + 3) +#define EIC_CHG_CV_STATE (A_EIC_START + 4) +#define EIC_AUD_HEAD_INST (A_EIC_START + 5) +#define EIC_VCHG_OVI (A_EIC_START + 6) +#define EIC_VBAT_OVI (A_EIC_START + 7) +#define EIC_AUD_HEAD_INST2 (A_EIC_START + 8) + +#define EIC_KEY_POWER (EIC_POWER_PBINT) + +#define HEADSET_BUTTON_GPIO (EIC_AUD_HEAD_BUTTON) +#define HEADSET_DETECT_GPIO (EIC_AUD_HEAD_INST2) +#define HEADSET_SWITCH_GPIO 0 + +#define HEADSET_IRQ_TRIGGER_LEVEL_DETECT 1 +#define HEADSET_IRQ_TRIGGER_LEVEL_BUTTON 1 + +#define HEADSET_ADC_MIN_KEY_MEDIA 0 +#define HEADSET_ADC_MAX_KEY_MEDIA 170 +#define HEADSET_ADC_MIN_KEY_VOLUMEUP 171 +#define HEADSET_ADC_MAX_KEY_VOLUMEUP 430 +#define HEADSET_ADC_MIN_KEY_VOLUMEDOWN 431 +#define HEADSET_ADC_MAX_KEY_VOLUMEDOWN 760 +#define HEADSET_ADC_THRESHOLD_3POLE_DETECT 100 +#define HEADSET_ADC_THRESHOLD_4POLE_DETECT 3100 +#define HEADSET_IRQ_THRESHOLD_BUTTON 1 +#define HEADSET_HEADMICBIAS_VOLTAGE 3000000 + +#define SPI0_CMMB_CS_GPIO 32 +#define SPI1_WIFI_CS_GPIO 44 + +#define GPIO_BK 143 +#define MSENSOR_DRDY_GPIO 53 +#define GPIO_PLSENSOR_IRQ 213 +/*For bcm4343 power on/off and sleep/wake */ +#define GPIO_BT_RESET 122 +#define GPIO_BT_POWER 131 +#define GPIO_BT2AP_WAKE 133 +#define GPIO_AP2BT_WAKE 132 + +/*#define GPIO_BT_RESET 194 */ +#define GPIO_WIFI_POWERON 189 +#define GPIO_WIFI_SHUTDOWN 130 +#define GPIO_WIFI_IRQ 97 + +#define GPIO_PROX_INT 140 +#define GPIO_GPS_ONOFF 174 + +#define GPIO_SDIO_DETECT 75 + +#define SPRD_PIN_SDIO0_OFFSET 0x01E0 +#define SPRD_PIN_SDIO0_SIZE 7 +#define SPRD_PIN_SDIO0_D3_INDEX 0 +#define SPRD_PIN_SDIO0_D3_GPIO 100 +#define SPRD_PIN_SDIO0_SD_FUNC 0 +#define SPRD_PIN_SDIO0_GPIO_FUNC 3 + +/*#define CP related featrue */ +#define SIPC_SMEM_ADDR (CONFIG_PHYS_OFFSET + 120 * SZ_1M) + +#define CPT_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#define CPT_TOTAL_SIZE (SZ_1M * 18) +#define CPT_RING_ADDR (CPT_START_ADDR + CPT_TOTAL_SIZE - SZ_4K) +#define CPT_RING_SIZE (SZ_4K) +#define CPT_SMEM_SIZE (SZ_1M * 2) + +#define CPW_START_ADDR (CONFIG_PHYS_OFFSET + 150* SZ_1M) +#define CPW_TOTAL_SIZE (SZ_1M * 33) +#define CPW_RING_ADDR (CPW_START_ADDR + CPW_TOTAL_SIZE - SZ_4K) +#define CPW_RING_SIZE (SZ_4K) +#define CPW_SMEM_SIZE (SZ_1M * 2) + +#define WCN_START_ADDR (CONFIG_PHYS_OFFSET + 320 * SZ_1M) +#define WCN_TOTAL_SIZE (SZ_1M * 5) +#define WCN_RING_ADDR (WCN_START_ADDR + WCN_TOTAL_SIZE - SZ_4K) +#define WCN_RING_SIZE (SZ_4K) +#define WCN_SMEM_SIZE (SZ_1M * 2) + +#define GGE_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#define GGE_TOTAL_SIZE (SZ_1M * 22) +#define GGE_RING_ADDR (GGE_START_ADDR + GGE_TOTAL_SIZE - SZ_4K) +#define GGE_RING_SIZE (SZ_4K) +#define GGE_SMEM_SIZE (SZ_1M * 2) + +#define LTE_START_ADDR (CONFIG_PHYS_OFFSET + 150 * SZ_1M) +#define LTE_TOTAL_SIZE (SZ_1M * 83) +#define LTE_RING_ADDR (LTE_START_ADDR + LTE_TOTAL_SIZE - SZ_4K) +#define LTE_RING_SIZE (SZ_4K) +#define LTE_SMEM_SIZE (SZ_1M * 2) + + +#endif diff --git a/include/soc/sprd/__board-tizenz3_3g.h b/include/soc/sprd/__board-tizenz3_3g.h new file mode 100644 index 00000000..cc0fe16f --- /dev/null +++ b/include/soc/sprd/__board-tizenz3_3g.h @@ -0,0 +1,136 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __GPIO_SCX35GA_H__ +#define __GPIO_SCX35GA_H__ + +#ifndef __ASM_ARCH_BOARD_H +#error "Don't include this file directly, include <mach/board.h>" +#endif + +#define GPIO_TOUCH_RESET 81 +#define GPIO_TOUCH_IRQ 82 + +#define GPIO_IF_PMIC_SDA 159 +#define GPIO_IF_PMIC_SCL 160 +#define GPIO_IF_PMIC_IRQ 161 +#define GPIO_FUELGAUGE_SCL 65 +#define GPIO_FUELGAUGE_SDA 66 +#define GPIO_FUELGAUGE_ALERT 153 +#define GPIO_MUIC_SDA 150 +#define GPIO_MUIC_SCL 151 +#define GPIO_MUIC_IRQ 152 + +#define GPIO_SENSOR_RESET 186//41 +#define GPIO_SUB_SENSOR_RESET 238 +#define GPIO_MAIN_SENSOR_PWN 188//42 +#define GPIO_SUB_SENSOR_PWN 187//43 +#define CAM_FLASH_ENF_GPIO 81 +#define CAM_FLASH_ENT_GPIO 82 +#define SPRD_FLASH_ON 1 +#define SPRD_FLASH_OFF 0 +#define GPIO_TOUCHKEY_LED_EN 116 + +#define SPRD_FLASH_OFST 0x890 +#define SPRD_FLASH_CTRL_BIT 0x8000 +#define SPRD_FLASH_LOW_VAL 0x3 +#define SPRD_FLASH_HIGH_VAL 0xF +#define SPRD_FLASH_LOW_CUR 110 +#define SPRD_FLASH_HIGH_CUR 470 + +#define USB_OTG_CABLE_DETECT 72 + +#define EIC_CHARGER_DETECT (A_EIC_START + 0) +#define EIC_POWER_PBINT2 (A_EIC_START + 1) +#define EIC_POWER_PBINT (A_EIC_START + 2) +#define EIC_AUD_HEAD_BUTTON (A_EIC_START + 3) +#define EIC_CHG_CV_STATE (A_EIC_START + 4) +#define EIC_AUD_HEAD_INST (A_EIC_START + 5) +#define EIC_VCHG_OVI (A_EIC_START + 6) +#define EIC_VBAT_OVI (A_EIC_START + 7) +#define EIC_AUD_HEAD_INST2 (A_EIC_START + 8) + +#define EIC_KEY_POWER (EIC_POWER_PBINT) +#define HEADSET_BUTTON_GPIO 239 +#define HEADSET_DETECT_GPIO 237 +#define HEADSET_SWITCH_GPIO 0 +#define HEADSET_AMP_GPIO 131 +#define HEADSET_EXT_MICBIAS_GPIO 123 + +#define HEADSET_IRQ_TRIGGER_LEVEL_DETECT 0 +#define HEADSET_IRQ_TRIGGER_LEVEL_BUTTON 0 + +#define HEADSET_ADC_MIN_KEY_MEDIA 0 +#define HEADSET_ADC_MAX_KEY_MEDIA 190 +#define HEADSET_ADC_MIN_KEY_VOLUMEUP 191 +#define HEADSET_ADC_MAX_KEY_VOLUMEUP 347 +#define HEADSET_ADC_MIN_KEY_VOLUMEDOWN 348 +#define HEADSET_ADC_MAX_KEY_VOLUMEDOWN 760 +#define HEADSET_ADC_THRESHOLD_3POLE_DETECT 1170 +#define HEADSET_ADC_THRESHOLD_4POLE_DETECT 2700 +#define HEADSET_IRQ_THRESHOLD_BUTTON 1 +#define HEADSET_HEADMICBIAS_VOLTAGE 3000000 + + +#define SPI0_BACKLIGHT_EN_GPIO 214 +#define SPI0_BACKLIGHT_PWM_GPIO 234 + +#define SPI0_CMMB_CS_GPIO 156 +#define SPI1_WIFI_CS_GPIO 44 + +#define GPIO_BK 136 + +#define GPIO_CMMB_RESET 144 +#define GPIO_CMMB_INT 143 +#define GPIO_CMMB_26M_CLK_EN 197 + +#define GPIO_BT_RESET 233 +#define GPIO_BT_POWER 231 +#define GPIO_BT2AP_WAKE 232 +#define GPIO_AP2BT_WAKE 235 + +#define GPIO_WIFI_SHUTDOWN 230 +//#define GPIO_WIFI_IRQ 234 +#define GPIO_WIFI_IRQ 148 +#define GPIO_PROX_INT 216 +#define GPIO_GYRO_INT1 163 +#define GPIO_M_RSTN 161 +#define GPIO_M_DRDY 164 + +#define GPIO_SDIO_DETECT 75 + +#define SPRD_PIN_SDIO0_OFFSET 0x0184 +#define SPRD_PIN_SDIO0_SIZE 7 +#define SPRD_PIN_SDIO0_D3_INDEX 0 +#define SPRD_PIN_SDIO0_D3_GPIO 100 +#define SPRD_PIN_SDIO0_SD_FUNC 0 +#define SPRD_PIN_SDIO0_GPIO_FUNC 3 + +/* ION config info +LCD: + 960x540 + +Video Playing: + 1080p 8 ref-frame + +Video Recording: + 720p + +Camera: + 8M, support ZSL, support preview/capture rotation +*/ + +#define SPRD_ION_SIZE (52 * SZ_1M) +#define SPRD_ION_OVERLAY_SIZE (7 * SZ_1M) + +#endif diff --git a/include/soc/sprd/__board-tshark2tabe.h b/include/soc/sprd/__board-tshark2tabe.h new file mode 100755 index 00000000..cc0fe16f --- /dev/null +++ b/include/soc/sprd/__board-tshark2tabe.h @@ -0,0 +1,136 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __GPIO_SCX35GA_H__ +#define __GPIO_SCX35GA_H__ + +#ifndef __ASM_ARCH_BOARD_H +#error "Don't include this file directly, include <mach/board.h>" +#endif + +#define GPIO_TOUCH_RESET 81 +#define GPIO_TOUCH_IRQ 82 + +#define GPIO_IF_PMIC_SDA 159 +#define GPIO_IF_PMIC_SCL 160 +#define GPIO_IF_PMIC_IRQ 161 +#define GPIO_FUELGAUGE_SCL 65 +#define GPIO_FUELGAUGE_SDA 66 +#define GPIO_FUELGAUGE_ALERT 153 +#define GPIO_MUIC_SDA 150 +#define GPIO_MUIC_SCL 151 +#define GPIO_MUIC_IRQ 152 + +#define GPIO_SENSOR_RESET 186//41 +#define GPIO_SUB_SENSOR_RESET 238 +#define GPIO_MAIN_SENSOR_PWN 188//42 +#define GPIO_SUB_SENSOR_PWN 187//43 +#define CAM_FLASH_ENF_GPIO 81 +#define CAM_FLASH_ENT_GPIO 82 +#define SPRD_FLASH_ON 1 +#define SPRD_FLASH_OFF 0 +#define GPIO_TOUCHKEY_LED_EN 116 + +#define SPRD_FLASH_OFST 0x890 +#define SPRD_FLASH_CTRL_BIT 0x8000 +#define SPRD_FLASH_LOW_VAL 0x3 +#define SPRD_FLASH_HIGH_VAL 0xF +#define SPRD_FLASH_LOW_CUR 110 +#define SPRD_FLASH_HIGH_CUR 470 + +#define USB_OTG_CABLE_DETECT 72 + +#define EIC_CHARGER_DETECT (A_EIC_START + 0) +#define EIC_POWER_PBINT2 (A_EIC_START + 1) +#define EIC_POWER_PBINT (A_EIC_START + 2) +#define EIC_AUD_HEAD_BUTTON (A_EIC_START + 3) +#define EIC_CHG_CV_STATE (A_EIC_START + 4) +#define EIC_AUD_HEAD_INST (A_EIC_START + 5) +#define EIC_VCHG_OVI (A_EIC_START + 6) +#define EIC_VBAT_OVI (A_EIC_START + 7) +#define EIC_AUD_HEAD_INST2 (A_EIC_START + 8) + +#define EIC_KEY_POWER (EIC_POWER_PBINT) +#define HEADSET_BUTTON_GPIO 239 +#define HEADSET_DETECT_GPIO 237 +#define HEADSET_SWITCH_GPIO 0 +#define HEADSET_AMP_GPIO 131 +#define HEADSET_EXT_MICBIAS_GPIO 123 + +#define HEADSET_IRQ_TRIGGER_LEVEL_DETECT 0 +#define HEADSET_IRQ_TRIGGER_LEVEL_BUTTON 0 + +#define HEADSET_ADC_MIN_KEY_MEDIA 0 +#define HEADSET_ADC_MAX_KEY_MEDIA 190 +#define HEADSET_ADC_MIN_KEY_VOLUMEUP 191 +#define HEADSET_ADC_MAX_KEY_VOLUMEUP 347 +#define HEADSET_ADC_MIN_KEY_VOLUMEDOWN 348 +#define HEADSET_ADC_MAX_KEY_VOLUMEDOWN 760 +#define HEADSET_ADC_THRESHOLD_3POLE_DETECT 1170 +#define HEADSET_ADC_THRESHOLD_4POLE_DETECT 2700 +#define HEADSET_IRQ_THRESHOLD_BUTTON 1 +#define HEADSET_HEADMICBIAS_VOLTAGE 3000000 + + +#define SPI0_BACKLIGHT_EN_GPIO 214 +#define SPI0_BACKLIGHT_PWM_GPIO 234 + +#define SPI0_CMMB_CS_GPIO 156 +#define SPI1_WIFI_CS_GPIO 44 + +#define GPIO_BK 136 + +#define GPIO_CMMB_RESET 144 +#define GPIO_CMMB_INT 143 +#define GPIO_CMMB_26M_CLK_EN 197 + +#define GPIO_BT_RESET 233 +#define GPIO_BT_POWER 231 +#define GPIO_BT2AP_WAKE 232 +#define GPIO_AP2BT_WAKE 235 + +#define GPIO_WIFI_SHUTDOWN 230 +//#define GPIO_WIFI_IRQ 234 +#define GPIO_WIFI_IRQ 148 +#define GPIO_PROX_INT 216 +#define GPIO_GYRO_INT1 163 +#define GPIO_M_RSTN 161 +#define GPIO_M_DRDY 164 + +#define GPIO_SDIO_DETECT 75 + +#define SPRD_PIN_SDIO0_OFFSET 0x0184 +#define SPRD_PIN_SDIO0_SIZE 7 +#define SPRD_PIN_SDIO0_D3_INDEX 0 +#define SPRD_PIN_SDIO0_D3_GPIO 100 +#define SPRD_PIN_SDIO0_SD_FUNC 0 +#define SPRD_PIN_SDIO0_GPIO_FUNC 3 + +/* ION config info +LCD: + 960x540 + +Video Playing: + 1080p 8 ref-frame + +Video Recording: + 720p + +Camera: + 8M, support ZSL, support preview/capture rotation +*/ + +#define SPRD_ION_SIZE (52 * SZ_1M) +#define SPRD_ION_OVERLAY_SIZE (7 * SZ_1M) + +#endif diff --git a/include/soc/sprd/__clock_tree.h b/include/soc/sprd/__clock_tree.h new file mode 100644 index 00000000..6153a773 --- /dev/null +++ b/include/soc/sprd/__clock_tree.h @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2013 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ +#ifndef __ASM_ARCH_SCI_CLOCK_TREE_H +#define __ASM_ARCH_SCI_CLOCK_TREE_H + +#if defined(CONFIG_SC_FPGA) + #if defined(CONFIG_ARCH_SCX35L) + #include "chip_x35l/__clock_tree.h" + #elif defined(CONFIG_ARCH_SCX20L) + #include "chip_x20l/__clock_tree.h" + #endif +#endif + +#if defined(CONFIG_ARCH_SCX30G) +#include "chip_x30g/__clock_tree.h" +#elif defined(CONFIG_ARCH_SCX15) +#include "chip_x15/__clock_tree.h" + +#elif defined(CONFIG_ARCH_SCX35L) + #if defined(CONFIG_ARCH_SCX20L) + #include "chip_x20l/__scx20l_clock_tree.h" + #else + #include "chip_x35l/__scx35l_clock_tree.h" + #endif +#elif defined(CONFIG_ARCH_SCX35) +#include "chip_x35/__clock_tree.h" +#elif defined(CONFIG_ARCH_SC8825) +#include "__sc8825_clock_tree.h" +#else +#error "Unknown architecture specification" +#endif + +#endif diff --git a/include/soc/sprd/__hardware-sc7731.h b/include/soc/sprd/__hardware-sc7731.h new file mode 100644 index 00000000..7974b99b --- /dev/null +++ b/include/soc/sprd/__hardware-sc7731.h @@ -0,0 +1,236 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARCH_HARDWARE_SCX30G_H +#define __ASM_ARCH_HARDWARE_SCX30G_H + +#ifndef __ASM_ARCH_SCI_HARDWARE_H +#error "Don't include this file directly, include <mach/hardware.h>" +#endif + +/* + * 8830 internal I/O mappings + * 0x30000000-0x50000000 AON. + * We have the following mapping according to asic spec. + * We have set some trap gaps in the vaddr. + */ +#define SCI_IOMAP_BASE 0xF5000000 + +#define SCI_IOMAP(x) (SCI_IOMAP_BASE + (x)) + +#define SCI_IOMEMMAP_BASE 0xcc800000 + +#define SCI_IOMEMMAP(x) (SCI_IOMEMMAP_BASE + (x)) + +#ifndef SCI_ADDR +#define SCI_ADDR(_b_, _o_) ( (u32)(_b_) + (_o_) ) +#endif + +#define LL_DEBUG_UART_PHYS SPRD_UART1_PHYS +#define LL_DEBUG_UART_BASE SPRD_UART1_BASE + + +#include <soc/sprd/iomap.h> + +#if !defined __ASSEMBLER__ +extern unsigned long sprd_adi_base; +extern unsigned long sprd_adi_phys; +#define SPRD_ADI_BASE sprd_adi_base +#define SPRD_ADI_PHYS sprd_adi_phys + +#define SPRD_ADISLAVE_BASE (SPRD_ADI_BASE+0x8000) +#define SPRD_ADISLAVE_PHYS (SPRD_ADI_PHYS+0x8000) +#define REGS_ADISLAVE_BASE SPRD_ADISLAVE_BASE +#define REGS_ADISLAVE_PHYS SPRD_ADISLAVE_PHYS +#endif + +#define SPRD_UART0_BASE SCI_IOMAP(0x360000) +#define SPRD_UART0_PHYS 0x70000000 +#define SPRD_UART0_SIZE SZ_4K + +#define SPRD_UART1_BASE SCI_IOMAP(0x362000) +#define SPRD_UART1_PHYS 0x70100000 +#define SPRD_UART1_SIZE SZ_4K + +#define SPRD_UART2_BASE SCI_IOMAP(0x364000) +#define SPRD_UART2_PHYS 0x70200000 +#define SPRD_UART2_SIZE SZ_4K + +#define SPRD_UART3_BASE SCI_IOMAP(0x366000) +#define SPRD_UART3_PHYS 0x70300000 +#define SPRD_UART3_SIZE SZ_4K + +#define SPRD_UART4_BASE SCI_IOMAP(0x368000) +#define SPRD_UART4_PHYS 0x70400000 +#define SPRD_UART4_SIZE SZ_4K + + +#define SPRD_IRAM0_BASE SCI_IOMAP(0x3d0000) +#define SPRD_IRAM0_PHYS 0x0 +#define SPRD_IRAM0_SIZE SZ_4K + +#define SPRD_IRAM0H_BASE SCI_IOMAP(0x3d1000) +#define SPRD_IRAM0H_PHYS 0x1000 +#define SPRD_IRAM0H_SIZE SZ_4K + +#define SPRD_IRAM1_BASE SCI_IOMAP(0x3d4000) +#define SPRD_IRAM1_PHYS 0x50000000 +#define SPRD_IRAM1_SIZE (SZ_8K + SZ_4K) + +#define SPRD_IRAM2_BASE SCI_IOMAP(0x3d7000) +#define SPRD_IRAM2_PHYS 0x50004000 +#define SPRD_IRAM2_SIZE (SZ_32K + SZ_4K) + +#define SPRD_PWM_BASE SCI_IOMAP(0x20a000) +#define SPRD_PWM_PHYS 0X40260000 +#define SPRD_PWM_SIZE SZ_4K + +#define SPRD_LPDDR2_BASE SCI_IOMAP(0x160000) +#define SPRD_LPDDR2_PHYS 0X30000000 +#define SPRD_LPDDR2_SIZE SZ_4K + +#define SPRD_LPDDR2_PHY_BASE SCI_IOMAP(0x170000) +#define SPRD_LPDDR2_PHY_PHYS 0X30010000 +#define SPRD_LPDDR2_PHY_SIZE SZ_4K + +#define SPRD_SDIO1_PHYS 0X20400000 +#define SPRD_SDIO1_SIZE SZ_4K + +#define SPRD_MALI_PHYS 0X60000000 + +#define CORE_GIC_CPU_VA (SPRD_CORE_BASE + 0x2000) +#define CORE_GIC_DIS_VA (SPRD_CORE_BASE + 0x1000) + +#define HOLDING_PEN_VADDR (SPRD_AHB_BASE + 0x14) +#define CPU_JUMP_VADDR (HOLDING_PEN_VADDR + 0X4) + +/* registers for watchdog ,RTC, touch panel, aux adc, analog die... */ +#define SPRD_MISC_BASE ((unsigned int)SPRD_ADI_BASE) +#define SPRD_MISC_PHYS ((unsigned int)SPRD_ADI_PHYS) + +#define ANA_PWM_BASE (SPRD_ADISLAVE_BASE + 0x20 ) +#define ANA_WDG_BASE (SPRD_ADISLAVE_BASE + 0x40 ) +#define ANA_RTC_BASE (SPRD_ADISLAVE_BASE + 0x80 ) +#define ANA_EIC_BASE (SPRD_ADISLAVE_BASE + 0x100 ) +#define ANA_PIN_BASE (SPRD_ADISLAVE_BASE + 0x180 ) +#define ANA_THM_BASE (SPRD_ADISLAVE_BASE + 0x280 ) +#define ADC_BASE (SPRD_ADISLAVE_BASE + 0x300 ) +#define ANA_CTL_INT_BASE (SPRD_ADISLAVE_BASE + 0x380 ) +#define ANA_BTLC_INT_BASE (SPRD_ADISLAVE_BASE + 0x3c0 ) +#define ANA_AUDIFA_INT_BASE (SPRD_ADISLAVE_BASE + 0x400 ) +#define ANA_GPIO_INT_BASE (SPRD_ADISLAVE_BASE + 0x480 ) +#define ANA_FPU_INT_BASE (SPRD_ADISLAVE_BASE + 0x500 ) +#define ANA_AUDCFGA_INT_BASE (SPRD_ADISLAVE_BASE + 0x600 ) +#define ANA_HDT_INT_BASE (SPRD_ADISLAVE_BASE + 0x700 ) +#define ANA_CTL_GLB_BASE (SPRD_ADISLAVE_BASE + 0x800 ) + +#define SPRD_ANA_PIN_BASE ((unsigned int)SPRD_ADI_BASE + 0x8180) + +#ifndef REGS_AHB_BASE +#define REGS_AHB_BASE ( SPRD_AHB_BASE + 0x200) +#endif + +#define SPRD_IRAM_BASE SPRD_IRAM0_BASE + 0x1000 +#define SPRD_IRAM_PHYS SPRD_IRAM0_PHYS + 0x1000 +#define SPRD_IRAM_SIZE SZ_4K +#define SPRD_GREG_BASE SPRD_AONAPB_BASE +#define SPRD_GREG_PHYS SPRD_AONAPB_PHYS +#define SPRD_GREG_SIZE SZ_64K + +#ifndef REGS_GLB_BASE +#define REGS_GLB_BASE ( SPRD_GREG_BASE ) +#define ANA_REGS_GLB_BASE ( ANA_CTL_GLB_BASE ) +#endif + +#define CHIP_ID_LOW_REG (SPRD_AHB_BASE + 0xfc) + +#define SPRD_GPTIMER_BASE SPRD_GPTIMER0_BASE +//#define REG_GLB_GEN0 SPRD_AONAPB_BASE +#define SPRD_EFUSE_BASE SPRD_UIDEFUSE_BASE + +#define REGS_AP_AHB_BASE SPRD_AHB_BASE +#define REGS_AP_APB_BASE SPRD_APBREG_BASE +#define REGS_AON_APB_BASE SPRD_AONAPB_BASE +#define REGS_GPU_APB_BASE SPRD_GPUAPB_BASE +#define REGS_MM_AHB_BASE SPRD_MMAHB_BASE +#define REGS_PMU_APB_BASE SPRD_PMU_BASE +#define REGS_AON_CLK_BASE SPRD_AONCKG_BASE +#define REGS_AP_CLK_BASE SPRD_APBCKG_BASE +#define REGS_GPU_CLK_BASE SPRD_GPUCKG_BASE +#define REGS_MM_CLK_BASE SPRD_MMCKG_BASE +#define REGS_PUB_APB_BASE SPRD_PUB_BASE + +#if defined(CONFIG_ARCH_SCX15) +#if defined(CONFIG_SPRD_MODEM_TD) +#define SIPC_SMEM_ADDR (CONFIG_PHYS_OFFSET + 120 * SZ_1M) +#define CPT_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#define CPT_TOTAL_SIZE (SZ_1M * 18) +#define CPT_RING_ADDR (CPT_START_ADDR + CPT_TOTAL_SIZE - SZ_4K) +#define CPT_RING_SIZE (SZ_4K) +#define CPT_SMEM_SIZE (SZ_1M + SZ_256K) +#define WCN_START_ADDR (CONFIG_PHYS_OFFSET + 168 * SZ_1M) +#define WCN_TOTAL_SIZE 0x281000//(SZ_1M * 5) +#define WCN_RING_ADDR (WCN_START_ADDR + WCN_TOTAL_SIZE - SZ_4K) +#define WCN_RING_SIZE (SZ_4K) +#define WCN_SMEM_SIZE (SZ_512K + SZ_256K) +#else +#define SIPC_SMEM_ADDR (CONFIG_PHYS_OFFSET + 120 * SZ_1M) +#define CPW_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#define CPW_TOTAL_SIZE 0x18A0000 //(SZ_1M * 32) +#define CPW_RING_ADDR (CPW_START_ADDR + CPW_TOTAL_SIZE - SZ_4K) +#define CPW_RING_SIZE (SZ_4K) +#define CPW_SMEM_SIZE (SZ_1M + SZ_256K) +#define WCN_START_ADDR (CONFIG_PHYS_OFFSET + 168 * SZ_1M) +#define WCN_TOTAL_SIZE 0x281000//(SZ_1M * 5) +#define WCN_RING_ADDR (WCN_START_ADDR + WCN_TOTAL_SIZE - SZ_4K) +#define WCN_RING_SIZE (SZ_4K) +#define WCN_SMEM_SIZE (SZ_512K + SZ_256K) +#endif +#else +#define SIPC_SMEM_ADDR (CONFIG_PHYS_OFFSET + 120 * SZ_1M) + +#define CPT_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#define CPT_TOTAL_SIZE (SZ_1M * 18) +#define CPT_RING_ADDR (CPT_START_ADDR + CPT_TOTAL_SIZE - SZ_4K) +#define CPT_RING_SIZE (SZ_4K) +#define CPT_SMEM_SIZE (SZ_1M + SZ_256K) + +#ifdef CONFIG_ARCH_SCX30G +#define CPW_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#else +#define CPW_START_ADDR (CONFIG_PHYS_OFFSET + 256 * SZ_1M) +#endif +#if defined(CONFIG_MODEM_W_MEMCUT) +#define CPW_TOTAL_SIZE (SZ_1M * 28) +#elif defined CONFIG_ARCH_SCX30G +#define CPW_TOTAL_SIZE (SZ_1M * 27) +#else +#define CPW_TOTAL_SIZE (SZ_1M * 33) +#endif +#define CPW_RING_ADDR (CPW_START_ADDR + CPW_TOTAL_SIZE - SZ_4K) +#define CPW_RING_SIZE (SZ_4K) +#define CPW_SMEM_SIZE (SZ_1M + SZ_256K) + +#if defined(CONFIG_ARCH_SCX30G) +#define WCN_START_ADDR (CONFIG_PHYS_OFFSET + 168 * SZ_1M)//Tshark moves cp2 to 168M +#define WCN_TOTAL_SIZE 0x201000//Tshark 8830gea memcut to 2M+4k +#else +#define WCN_START_ADDR (CONFIG_PHYS_OFFSET + 320 * SZ_1M) +#define WCN_TOTAL_SIZE 0x281000//(SZ_1M * 5) +#endif +#define WCN_RING_ADDR (WCN_START_ADDR + WCN_TOTAL_SIZE - SZ_4K) +#define WCN_RING_SIZE (SZ_4K) +#define WCN_SMEM_SIZE (SZ_512K + SZ_256K) +#endif + +#endif diff --git a/include/soc/sprd/__hardware-sc8830.h b/include/soc/sprd/__hardware-sc8830.h new file mode 100644 index 00000000..c5421259 --- /dev/null +++ b/include/soc/sprd/__hardware-sc8830.h @@ -0,0 +1,645 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARCH_HARDWARE_SCX35_H +#define __ASM_ARCH_HARDWARE_SCX35_H + +#ifndef __ASM_ARCH_SCI_HARDWARE_H +#error "Don't include this file directly, include <mach/hardware.h>" +#endif + +/* + * 8830 internal I/O mappings + * 0x30000000-0x50000000 AON. + * We have the following mapping according to asic spec. + * We have set some trap gaps in the vaddr. + */ +#define SCI_IOMAP_BASE 0xF5000000 + +#define SCI_IOMAP(x) (SCI_IOMAP_BASE + (x)) + +#define SCI_IOMEMMAP_BASE 0xcc800000 + +#define SCI_IOMEMMAP(x) (SCI_IOMEMMAP_BASE + (x)) + +#ifndef SCI_ADDR +#define SCI_ADDR(_b_, _o_) ( (u32)(_b_) + (_o_) ) +#endif + +#define LL_DEBUG_UART_PHYS SPRD_UART1_PHYS +#define LL_DEBUG_UART_BASE SPRD_UART1_BASE + +//8830 mapping begin. From [0xEB000000 -- ] +#define SPRD_CORESIGHT_BASE SCI_IOMAP(0x0) +#define SPRD_CORESIGHT_PHYS 0x10000000 +#define SPRD_CORESIGHT_SIZE SZ_64K + +#define SPRD_CORE_BASE SCI_IOMAP(0x10000) +#define SPRD_CORE_PHYS 0x12000000 +#define SPRD_CORE_SIZE SZ_64K + +#define SPRD_DMA0_BASE SCI_IOMAP(0x112000) +#define SPRD_DMA0_PHYS 0X20100000 +#define SPRD_DMA0_SIZE SZ_16K + +#define SPRD_USB_BASE SCI_IOMAP(0x116000) +#define SPRD_USB_PHYS 0X20200000 +#define SPRD_USB_SIZE SZ_4K + +#define SPRD_SDIO0_BASE SCI_IOMAP(0x117000) +#define SPRD_SDIO0_PHYS 0X20300000 +#define SPRD_SDIO0_SIZE SZ_4K + +#define SPRD_SDIO1_BASE SCI_IOMAP(0x118000) +#define SPRD_SDIO1_PHYS 0X20400000 +#define SPRD_SDIO1_SIZE SZ_4K + +#define SPRD_MEMNAND_SYSTEM_BASE SCI_IOMEMMAP(0x00000) +#define SPRD_MEMNAND_SYSTEM_PHYS 0x8c800000 +#define SPRD_MEMNAND_SYSTEM_SIZE (0xaa00000) + + +#define SPRD_MEMNAND_USERDATA_BASE SCI_IOMEMMAP(0xaa00000) +#define SPRD_MEMNAND_USERDATA_PHYS 0X97200000 +#define SPRD_MEMNAND_USERDATA_SIZE (0x6a00000) + + +#define SPRD_MEMNAND_CACHE_BASE SCI_IOMEMMAP(0x6a00000+0xaa00000) +#define SPRD_MEMNAND_CACHE_PHYS (0X97200000+0x6a00000) +#define SPRD_MEMNAND_CACHE_SIZE (0x2400000) + +#define SPRD_SDIO2_BASE SCI_IOMAP(0x11a000) +#define SPRD_SDIO2_PHYS 0X20500000 +#define SPRD_SDIO2_SIZE SZ_4K + +#define SPRD_EMMC_BASE SCI_IOMAP(0x11c000) +#define SPRD_EMMC_PHYS 0X20600000 +#define SPRD_EMMC_SIZE SZ_4K + +#define SPRD_DRM_BASE SCI_IOMAP(0x120000) +#define SPRD_DRM_PHYS 0X20700000 +#define SPRD_DRM_SIZE SZ_4K + +#define SPRD_LCDC_BASE SCI_IOMAP(0x122000) +#define SPRD_LCDC_PHYS 0X20800000 +#define SPRD_LCDC_SIZE SZ_4K + +#define SPRD_LCDC1_BASE SCI_IOMAP(0x124000) +#define SPRD_LCDC1_PHYS 0X20900000 +#define SPRD_LCDC1_SIZE SZ_4K + +#define SPRD_GSP_BASE SCI_IOMAP(0x126000) +#define SPRD_GSP_PHYS 0X20A00000 +#define SPRD_GSP_SIZE SZ_4K + +#define SPRD_NFC_BASE SCI_IOMAP(0x128000) +#define SPRD_NFC_PHYS 0X20B00000 +#define SPRD_NFC_SIZE SZ_4K + +#define SPRD_HWLOCK0_BASE SCI_IOMAP(0x12a000) +#define SPRD_HWLOCK0_PHYS 0X20c00000 +#define SPRD_HWLOCK0_SIZE SZ_4K + +#define SPRD_AHB_BASE SCI_IOMAP(0x130000) +#define SPRD_AHB_PHYS 0X20D00000 +#define SPRD_AHB_SIZE SZ_64K + +#define SPRD_BM0_BASE SCI_IOMAP(0x140000) +#define SPRD_BM0_PHYS 0X20E00000 +#define SPRD_BM0_SIZE SZ_4K + +#define SPRD_BM1_BASE SCI_IOMAP(0x142000) +#define SPRD_BM1_PHYS 0X20F00000 +#define SPRD_BM1_SIZE SZ_4K + +#define SPRD_BM2_BASE SCI_IOMAP(0x144000) +#define SPRD_BM2_PHYS 0X21000000 +#define SPRD_BM2_SIZE SZ_4K + +#define SPRD_DSI_BASE SCI_IOMAP(0x146000) +#define SPRD_DSI_PHYS 0X21800000 +#define SPRD_DSI_SIZE SZ_4K + +#define SPRD_GPS_BASE SCI_IOMAP(0x150000) +#define SPRD_GPS_PHYS 0X21C00000 +#define SPRD_GPS_SIZE SZ_4K + +#define SPRD_LPDDR2_BASE SCI_IOMAP(0x160000) +#define SPRD_LPDDR2_PHYS 0X30000000 +#define SPRD_LPDDR2_SIZE SZ_4K + +#define SPRD_LPDDR2_PHY_BASE SCI_IOMAP(0x170000) +#define SPRD_LPDDR2_PHY_PHYS 0X30010000 +#define SPRD_LPDDR2_PHY_SIZE SZ_4K + +#define SPRD_PUB_BASE SCI_IOMAP(0x180000) +#define SPRD_PUB_PHYS 0X30020000 +#define SPRD_PUB_SIZE SZ_64K + +#define SPRD_AXIBM0_BASE SCI_IOMAP(0x19e000) +#define SPRD_AXIBM0_PHYS 0X30040000 +#define SPRD_AXIBM0_SIZE SZ_4K + +#define SPRD_AXIBM1_BASE SCI_IOMAP(0x1a0000) +#define SPRD_AXIBM1_PHYS 0X30050000 +#define SPRD_AXIBM1_SIZE (SZ_4K) + +#define SPRD_AXIBM2_BASE SCI_IOMAP(0x1a2000) +#define SPRD_AXIBM2_PHYS 0X30060000 +#define SPRD_AXIBM2_SIZE (SZ_4K) + +#define SPRD_AXIBM3_BASE SCI_IOMAP(0x1a4000) +#define SPRD_AXIBM3_PHYS 0X30070000 +#define SPRD_AXIBM3_SIZE (SZ_4K) + +#define SPRD_AXIBM4_BASE SCI_IOMAP(0x1a6000) +#define SPRD_AXIBM4_PHYS 0X30080000 +#define SPRD_AXIBM4_SIZE (SZ_4K) + +#define SPRD_AXIBM5_BASE SCI_IOMAP(0x1a8000) +#define SPRD_AXIBM5_PHYS 0X30090000 +#define SPRD_AXIBM5_SIZE (SZ_4K) + +#define SPRD_AXIBM6_BASE SCI_IOMAP(0x1aa000) +#define SPRD_AXIBM6_PHYS 0X300A0000 +#define SPRD_AXIBM6_SIZE (SZ_4K) + +#define SPRD_AXIBM7_BASE SCI_IOMAP(0x1ac000) +#define SPRD_AXIBM7_PHYS 0X300B0000 +#define SPRD_AXIBM7_SIZE (SZ_4K) + +#define SPRD_AXIBM8_BASE SCI_IOMAP(0x1ae000) +#define SPRD_AXIBM8_PHYS 0X300C0000 +#define SPRD_AXIBM8_SIZE (SZ_4K) + +#define SPRD_AXIBM9_BASE SCI_IOMAP(0x1b0000) +#define SPRD_AXIBM9_PHYS 0X300D0000 +#define SPRD_AXIBM9_SIZE (SZ_4K) + +#define SPRD_AUDIO_BASE SCI_IOMAP(0x1c0000) +#define SPRD_AUDIO_PHYS 0X40000000 +#define SPRD_AUDIO_SIZE SZ_8K + +#define SPRD_AUDIO_IF_BASE SCI_IOMAP(0x1d0000) +#define SPRD_AUDIO_IF_PHYS 0X40010000 +#define SPRD_AUDIO_IF_SIZE SZ_4K + +#define SPRD_VBC_BASE SCI_IOMAP(0x1e0000) +#define SPRD_VBC_PHYS 0X40020000 +#define SPRD_VBC_SIZE SZ_4K + SZ_8K + +#define SPRD_SYSTIMER_CMP_BASE SCI_IOMAP(0x1f2000) +#define SPRD_SYSTIMER_CMP_PHYS 0X40040000 +#define SPRD_SYSTIMER_CMP_SIZE SZ_4K + +#define SPRD_GPTIMER0_BASE SCI_IOMAP(0x1f4000) +#define SPRD_GPTIMER0_PHYS 0X40050000 +#define SPRD_GPTIMER0_SIZE SZ_4K + +#define SPRD_HWLOCK1_BASE SCI_IOMAP(0x1f6000) +#define SPRD_HWLOCK1_PHYS 0X40060000 +#define SPRD_HWLOCK1_SIZE SZ_4K + +#define SPRD_RFSPI_BASE SCI_IOMAP(0x1f8000) +#define SPRD_RFSPI_PHYS 0X40070000 +#define SPRD_RFSPI_SIZE SZ_4K + +#define SPRD_I2C_BASE SCI_IOMAP(0x1fa000) +#define SPRD_I2C_PHYS 0X40080000 +#define SPRD_I2C_SIZE SZ_4K + +#define SPRD_INT_BASE SCI_IOMAP(0x1fc000) +#define SPRD_INT_PHYS 0X40200000 +#define SPRD_INT_SIZE SZ_4K + +#define SPRD_EIC_BASE SCI_IOMAP(0x200000) +#define SPRD_EIC_PHYS 0X40210000 +#define SPRD_EIC_SIZE SZ_4K + +#define SPRD_APTIMER0_BASE SCI_IOMAP(0x202000) +#define SPRD_APTIMER0_PHYS 0X40220000 +#define SPRD_APTIMER0_SIZE SZ_4K + +#define SPRD_SYSCNT_BASE SCI_IOMAP(0x204000) +#define SPRD_SYSCNT_PHYS 0X40230000 +#define SPRD_SYSCNT_SIZE SZ_4K + +#define SPRD_UIDEFUSE_BASE SCI_IOMAP(0x206000) +#define SPRD_UIDEFUSE_PHYS 0X40240000 +#define SPRD_UIDEFUSE_SIZE SZ_4K + +#define SPRD_KPD_BASE SCI_IOMAP(0x208000) +#define SPRD_KPD_PHYS 0X40250000 +#define SPRD_KPD_SIZE SZ_4K + +#define SPRD_PWM_BASE SCI_IOMAP(0x20a000) +#define SPRD_PWM_PHYS 0X40260000 +#define SPRD_PWM_SIZE SZ_4K + +#define SPRD_FM_BASE SCI_IOMAP(0x210000) +#define SPRD_FM_PHYS 0X40270000 +#define SPRD_FM_SIZE SZ_4K + +#define SPRD_GPIO_BASE SCI_IOMAP(0x220000) +#define SPRD_GPIO_PHYS 0X40280000 +#define SPRD_GPIO_SIZE SZ_4K + +#define SPRD_WDG_BASE SCI_IOMAP(0x222000) +#define SPRD_WDG_PHYS 0X40290000 +#define SPRD_WDG_SIZE SZ_4K + +#define SPRD_PIN_BASE SCI_IOMAP(0x224000) +#define SPRD_PIN_PHYS 0X402A0000 +#define SPRD_PIN_SIZE SZ_4K + +#define SPRD_PMU_BASE SCI_IOMAP(0x230000) +#define SPRD_PMU_PHYS 0X402B0000 +#define SPRD_PMU_SIZE SZ_64K + +#define SPRD_IPI_BASE SCI_IOMAP(0x240000) +#define SPRD_IPI_PHYS 0X402C0000 +#define SPRD_IPI_SIZE SZ_4K + +#define SPRD_AONCKG_BASE SCI_IOMAP(0x242000) +#define SPRD_AONCKG_PHYS 0X402D0000 +#define SPRD_AONCKG_SIZE SZ_4K + +#define SPRD_AONAPB_BASE SCI_IOMAP(0x250000) +#define SPRD_AONAPB_PHYS 0X402E0000 +#define SPRD_AONAPB_SIZE SZ_64K + +#define SPRD_THM_BASE SCI_IOMAP(0x260000) +#define SPRD_THM_PHYS 0X402F0000 +#define SPRD_THM_SIZE SZ_4K + +#define SPRD_AVSCA7_BASE SCI_IOMAP(0x270000) +#define SPRD_AVSCA7_PHYS 0X40300000 +#define SPRD_AVSCA7_SIZE SZ_4K + +#define SPRD_AVSTOP_BASE SCI_IOMAP(0x280000) +#define SPRD_AVSTOP_PHYS 0X40310000 +#define SPRD_AVSTOP_SIZE SZ_4K + +// +#define SPRD_CA7WDG_BASE SCI_IOMAP(0x290000) +#define SPRD_CA7WDG_PHYS 0X40320000 +#define SPRD_CA7WDG_SIZE SZ_4K + +#define SPRD_APTIMER1_BASE SCI_IOMAP(0x292000) +#define SPRD_APTIMER1_PHYS 0X40330000 +#define SPRD_APTIMER1_SIZE SZ_4K + +#define SPRD_APTIMER2_BASE SCI_IOMAP(0x294000) +#define SPRD_APTIMER2_PHYS 0X40340000 +#define SPRD_APTIMER2_SIZE SZ_4K +// + +#define SPRD_CA7TS0_BASE SCI_IOMAP(0x2a0000) +#define SPRD_CA7TS0_PHYS 0X40400000 +#define SPRD_CA7TS0_SIZE SZ_4K + +#define SPRD_CA7TS1_BASE SCI_IOMAP(0x2b0000) +#define SPRD_CA7TS1_PHYS 0X40410000 +#define SPRD_CA7TS1_SIZE SZ_4K + +#define SPRD_MALI_BASE SCI_IOMAP(0x2c0000) +#define SPRD_MALI_PHYS 0X60000000 +#define SPRD_MALI_SIZE SZ_4K + +#define SPRD_GPUAPB_BASE SCI_IOMAP(0x2d0000) +#define SPRD_GPUAPB_PHYS 0X60100000 +#define SPRD_GPUAPB_SIZE SZ_4K + +#define SPRD_GPUCKG_BASE SCI_IOMAP(0x2e0000) +#define SPRD_GPUCKG_PHYS 0X60200000 +#define SPRD_GPUCKG_SIZE SZ_4K + +#define SPRD_DCAM_BASE SCI_IOMAP(0x2f0000) +#define SPRD_DCAM_PHYS 0X60800000 +#define SPRD_DCAM_SIZE SZ_64K + +#define SPRD_VSP_BASE SCI_IOMAP(0x300000) +#define SPRD_VSP_PHYS 0X60900000 +#define SPRD_VSP_SIZE (SZ_32K + SZ_16K) + +#define SPRD_ISP_BASE SCI_IOMAP(0x310000) +#define SPRD_ISP_PHYS 0X60A00000 +#define SPRD_ISP_SIZE SZ_32K + +#define SPRD_JPG_BASE SCI_IOMAP(0x320000) +#define SPRD_JPG_PHYS 0X60B00000 +#define SPRD_JPG_SIZE SZ_32K + +#define SPRD_CSI2_BASE SCI_IOMAP(0x330000) +#define SPRD_CSI2_PHYS 0X60C00000 +#define SPRD_CSI2_SIZE SZ_4K + +#define SPRD_MMAHB_BASE SCI_IOMAP(0x340000) +#define SPRD_MMAHB_PHYS 0X60D00000 +#define SPRD_MMAHB_SIZE SZ_16K + +#define SPRD_MMCKG_BASE SCI_IOMAP(0x350000) +#define SPRD_MMCKG_PHYS 0X60E00000 +#define SPRD_MMCKG_SIZE SZ_4K + +#define SPRD_UART0_BASE SCI_IOMAP(0x360000) +#define SPRD_UART0_PHYS 0X70000000 +#define SPRD_UART0_SIZE SZ_4K + +#define SPRD_UART1_BASE SCI_IOMAP(0x362000) +#define SPRD_UART1_PHYS 0X70100000 +#define SPRD_UART1_SIZE SZ_4K + +#define SPRD_UART2_BASE SCI_IOMAP(0x364000) +#define SPRD_UART2_PHYS 0X70200000 +#define SPRD_UART2_SIZE SZ_4K + +#define SPRD_UART3_BASE SCI_IOMAP(0x366000) +#define SPRD_UART3_PHYS 0X70300000 +#define SPRD_UART3_SIZE SZ_4K + +#define SPRD_UART4_BASE SCI_IOMAP(0x368000) +#define SPRD_UART4_PHYS 0X70400000 +#define SPRD_UART4_SIZE SZ_4K + +#define SPRD_I2C0_BASE SCI_IOMAP(0x36a000) +#define SPRD_I2C0_PHYS 0X70500000 +#define SPRD_I2C0_SIZE SZ_4K + +#define SPRD_I2C1_BASE SCI_IOMAP(0x36c000) +#define SPRD_I2C1_PHYS 0X70600000 +#define SPRD_I2C1_SIZE SZ_4K + +#define SPRD_I2C2_BASE SCI_IOMAP(0x370000) +#define SPRD_I2C2_PHYS 0X70700000 +#define SPRD_I2C2_SIZE SZ_4K + +#define SPRD_I2C3_BASE SCI_IOMAP(0x372000) +#define SPRD_I2C3_PHYS 0X70800000 +#define SPRD_I2C3_SIZE SZ_4K + +#define SPRD_I2C4_BASE SCI_IOMAP(0x374000) +#define SPRD_I2C4_PHYS 0X70900000 +#define SPRD_I2C4_SIZE SZ_4K + +#define SPRD_SPI0_BASE SCI_IOMAP(0x376000) +#define SPRD_SPI0_PHYS 0X70A00000 +#define SPRD_SPI0_SIZE SZ_4K + +#define SPRD_SPI1_BASE SCI_IOMAP(0x378000) +#define SPRD_SPI1_PHYS 0X70B00000 +#define SPRD_SPI1_SIZE SZ_4K + +#define SPRD_SPI2_BASE SCI_IOMAP(0x37a000) +#define SPRD_SPI2_PHYS 0X70C00000 +#define SPRD_SPI2_SIZE SZ_4K + +#define SPRD_IIS0_BASE SCI_IOMAP(0x37c000) +#define SPRD_IIS0_PHYS 0X70D00000 +#define SPRD_IIS0_SIZE SZ_4K + +#define SPRD_IIS1_BASE SCI_IOMAP(0x380000) +#define SPRD_IIS1_PHYS 0X70E00000 +#define SPRD_IIS1_SIZE SZ_4K + +#define SPRD_IIS2_BASE SCI_IOMAP(0x382000) +#define SPRD_IIS2_PHYS 0X70F00000 +#define SPRD_IIS2_SIZE SZ_4K + +#define SPRD_IIS3_BASE SCI_IOMAP(0x384000) +#define SPRD_IIS3_PHYS 0X71000000 +#define SPRD_IIS3_SIZE SZ_4K + +#define SPRD_SIM0_BASE SCI_IOMAP(0x390000) +#define SPRD_SIM0_PHYS 0X71100000 +#define SPRD_SIM0_SIZE SZ_4K + +#define SPRD_APBCKG_BASE SCI_IOMAP(0x3a0000) +#define SPRD_APBCKG_PHYS 0X71200000 +#define SPRD_APBCKG_SIZE SZ_4K + +#define SPRD_APBREG_BASE SCI_IOMAP(0x3b0000) +#define SPRD_APBREG_PHYS 0X71300000 +#define SPRD_APBREG_SIZE SZ_64K + +#define SPRD_INTC0_BASE SCI_IOMAP(0x3c0000) +#define SPRD_INTC0_PHYS 0X71400000 +#define SPRD_INTC0_SIZE SZ_4K + +#define SPRD_INTC1_BASE SCI_IOMAP(0x3c2000) +#define SPRD_INTC1_PHYS 0X71500000 +#define SPRD_INTC1_SIZE SZ_4K + +#define SPRD_INTC2_BASE SCI_IOMAP(0x3c4000) +#define SPRD_INTC2_PHYS 0X71600000 +#define SPRD_INTC2_SIZE SZ_4K + +#define SPRD_INTC3_BASE SCI_IOMAP(0x3c6000) +#define SPRD_INTC3_PHYS 0X71700000 +#define SPRD_INTC3_SIZE SZ_4K + +#define SPRD_IRAM0_BASE SCI_IOMAP(0x3d0000) +#define SPRD_IRAM0_PHYS 0X0 +#define SPRD_IRAM0_SIZE SZ_4K + +#define SPRD_IRAM0H_BASE SCI_IOMAP(0x3d1000) +#define SPRD_IRAM0H_PHYS 0X1000 +#define SPRD_IRAM0H_SIZE SZ_4K + +#if 0 +#define SPRD_IRAM1_BASE SCI_IOMAP(0x3e0000) +#define SPRD_IRAM1_PHYS 0X50000000 +#define SPRD_IRAM1_SIZE (SZ_32K + SZ_16K + SZ_4K) +#else +#define SPRD_IRAM1_BASE SCI_IOMAP(0x3d4000) +#define SPRD_IRAM1_PHYS 0x50000000 +#define SPRD_IRAM1_SIZE (SZ_8K + SZ_4K) + +#define SPRD_IRAM2_BASE SCI_IOMAP(0x3d7000) +#define SPRD_IRAM2_PHYS 0x50004000 +#define SPRD_IRAM2_SIZE (SZ_32K + SZ_4K) +#endif +/*begin mapping adie master and slave address */ +#define SPRD_ADI_BASE SCI_IOMAP(0x3f0000) +#define SPRD_ADI_PHYS 0X40030000 +#define SPRD_ADI_SIZE (SZ_4K) + +#define SPRD_ADISLAVE_BASE SCI_IOMAP(0x3f0000 + SZ_32K) +#define SPRD_ADISLAVE_PHYS 0X40038000 +#define SPRD_ADISLAVE_SIZE (SZ_4K) +/*end*/ +#if defined(CONFIG_ARCH_SCX15) +#define SPRD_ZIPENC_BASE SCI_IOMAP(0x3fc000) +#define SPRD_ZIPENC_PHYS 0X21200000 +#define SPRD_ZIPENC_SIZE (SZ_4K) +#define SPRD_ZIPDEC_BASE SCI_IOMAP(0x400000) +#define SPRD_ZIPDEC_PHYS 0X21300000 +#define SPRD_ZIPDEC_SIZE (SZ_4K) + +#define SPRD_GSPMMU_BASE SCI_IOMAP(0x410000) +#define SPRD_GSPMMU_PHYS 0X21400000 +#define SPRD_GSPMMU_SIZE (SZ_64K + SZ_4K) + +#define SPRD_MMMMU_BASE SCI_IOMAP(0x430000) +#define SPRD_MMMMU_PHYS 0X60F00000 +#define SPRD_MMMMU_SIZE (SZ_64K + SZ_4K) +#endif + +#if defined(CONFIG_ARCH_SCX30G) +#define SPRD_ZIPENC_BASE SCI_IOMAP(0x3fc000) +#define SPRD_ZIPENC_PHYS 0X21200000 +#define SPRD_ZIPENC_SIZE (SZ_4K) + +#define SPRD_ZIPDEC_BASE SCI_IOMAP(0x400000) +#define SPRD_ZIPDEC_PHYS 0X21300000 +#define SPRD_ZIPDEC_SIZE (SZ_4K) + +#define SPRD_GSPMMU_BASE SCI_IOMAP(0x410000) +#define SPRD_GSPMMU_PHYS 0X21400000 +#define SPRD_GSPMMU_SIZE (SZ_64K) + +#define SPRD_MMMMU_BASE SCI_IOMAP(0x430000) +#define SPRD_MMMMU_PHYS 0X60F00000 +#define SPRD_MMMMU_SIZE (SZ_128K + SZ_4K) +#endif + +#define CORE_GIC_CPU_VA (SPRD_CORE_BASE + 0x2000) +#define CORE_GIC_DIS_VA (SPRD_CORE_BASE + 0x1000) + +#ifdef CONFIG_ARCH_SCX30G +#define HOLDING_PEN_VADDR (SPRD_AHB_BASE + 0x14) +#else +#define HOLDING_PEN_VADDR (SPRD_AHB_BASE + 0x4c) +#endif +#define CPU_JUMP_VADDR (HOLDING_PEN_VADDR + 0X4) + + +/* registers for watchdog ,RTC, touch panel, aux adc, analog die... */ +#define SPRD_MISC_BASE ((unsigned int)SPRD_ADI_BASE) +#define SPRD_MISC_PHYS ((unsigned int)SPRD_ADI_PHYS) + +#define ANA_PWM_BASE (SPRD_ADISLAVE_BASE + 0x20 ) +#define ANA_WDG_BASE (SPRD_ADISLAVE_BASE + 0x40 ) +#define ANA_RTC_BASE (SPRD_ADISLAVE_BASE + 0x80 ) +#define ANA_EIC_BASE (SPRD_ADISLAVE_BASE + 0x100 ) +#define ANA_PIN_BASE (SPRD_ADISLAVE_BASE + 0x180 ) +#define ANA_THM_BASE (SPRD_ADISLAVE_BASE + 0x280 ) +#define ADC_BASE (SPRD_ADISLAVE_BASE + 0x300 ) +#define ANA_CTL_INT_BASE (SPRD_ADISLAVE_BASE + 0x380 ) +#define ANA_BTLC_INT_BASE (SPRD_ADISLAVE_BASE + 0x3c0 ) +#define ANA_AUDIFA_INT_BASE (SPRD_ADISLAVE_BASE + 0x400 ) +#define ANA_GPIO_INT_BASE (SPRD_ADISLAVE_BASE + 0x480 ) +#define ANA_FPU_INT_BASE (SPRD_ADISLAVE_BASE + 0x500 ) +#define ANA_AUDCFGA_INT_BASE (SPRD_ADISLAVE_BASE + 0x600 ) +#define ANA_HDT_INT_BASE (SPRD_ADISLAVE_BASE + 0x700 ) +#define ANA_CTL_GLB_BASE (SPRD_ADISLAVE_BASE + 0x800 ) + +#define SPRD_ANA_PIN_BASE ((unsigned int)SPRD_ADI_BASE + 0x8180) + +#ifndef REGS_AHB_BASE +#define REGS_AHB_BASE ( SPRD_AHB_BASE + 0x200) +#endif + +#define SPRD_IRAM_BASE SPRD_IRAM0_BASE + 0x1000 +#define SPRD_IRAM_PHYS SPRD_IRAM0_PHYS + 0x1000 +#define SPRD_IRAM_SIZE SZ_4K +#define SPRD_GREG_BASE SPRD_AONAPB_BASE +#define SPRD_GREG_PHYS SPRD_AONAPB_PHYS +#define SPRD_GREG_SIZE SZ_64K + +#ifndef REGS_GLB_BASE +#define REGS_GLB_BASE ( SPRD_GREG_BASE ) +#define ANA_REGS_GLB_BASE ( ANA_CTL_GLB_BASE ) +#endif + +#define CHIP_ID_LOW_REG (SPRD_AHB_BASE + 0xfc) + +#define SPRD_GPTIMER_BASE SPRD_GPTIMER0_BASE +//#define REG_GLB_GEN0 SPRD_AONAPB_BASE +#define SPRD_EFUSE_BASE SPRD_UIDEFUSE_BASE + +#define REGS_AP_AHB_BASE SPRD_AHB_BASE +#define REGS_AP_APB_BASE SPRD_APBREG_BASE +#define REGS_AON_APB_BASE SPRD_AONAPB_BASE +#define REGS_GPU_APB_BASE SPRD_GPUAPB_BASE +#define REGS_MM_AHB_BASE SPRD_MMAHB_BASE +#define REGS_PMU_APB_BASE SPRD_PMU_BASE +#define REGS_AON_CLK_BASE SPRD_AONCKG_BASE +#define REGS_AP_CLK_BASE SPRD_APBCKG_BASE +#define REGS_GPU_CLK_BASE SPRD_GPUCKG_BASE +#define REGS_MM_CLK_BASE SPRD_MMCKG_BASE +#define REGS_PUB_APB_BASE SPRD_PUB_BASE + +#if defined(CONFIG_ARCH_SCX15) +#if defined(CONFIG_SPRD_MODEM_TD) +#define SIPC_SMEM_ADDR (CONFIG_PHYS_OFFSET + 120 * SZ_1M) +#define CPT_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#define CPT_TOTAL_SIZE (SZ_1M * 18) +#define CPT_RING_ADDR (CPT_START_ADDR + CPT_TOTAL_SIZE - SZ_4K) +#define CPT_RING_SIZE (SZ_4K) +#define CPT_SMEM_SIZE (SZ_1M + SZ_256K) +#define WCN_START_ADDR (CONFIG_PHYS_OFFSET + 168 * SZ_1M) +#define WCN_TOTAL_SIZE 0x281000//(SZ_1M * 5) +#define WCN_RING_ADDR (WCN_START_ADDR + WCN_TOTAL_SIZE - SZ_4K) +#define WCN_RING_SIZE (SZ_4K) +#define WCN_SMEM_SIZE (SZ_512K + SZ_256K) +#else +#define SIPC_SMEM_ADDR (CONFIG_PHYS_OFFSET + 120 * SZ_1M) +#define CPW_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#define CPW_TOTAL_SIZE 0x18A0000 //(SZ_1M * 32) +#define CPW_RING_ADDR (CPW_START_ADDR + CPW_TOTAL_SIZE - SZ_4K) +#define CPW_RING_SIZE (SZ_4K) +#define CPW_SMEM_SIZE (SZ_1M + SZ_256K) +#define WCN_START_ADDR (CONFIG_PHYS_OFFSET + 168 * SZ_1M) +#define WCN_TOTAL_SIZE 0x281000//(SZ_1M * 5) +#define WCN_RING_ADDR (WCN_START_ADDR + WCN_TOTAL_SIZE - SZ_4K) +#define WCN_RING_SIZE (SZ_4K) +#define WCN_SMEM_SIZE (SZ_512K + SZ_256K) +#endif +#else +#define SIPC_SMEM_ADDR (CONFIG_PHYS_OFFSET + 120 * SZ_1M) + +#define CPT_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#define CPT_TOTAL_SIZE (SZ_1M * 18) +#define CPT_RING_ADDR (CPT_START_ADDR + CPT_TOTAL_SIZE - SZ_4K) +#define CPT_RING_SIZE (SZ_4K) +#define CPT_SMEM_SIZE (SZ_1M + SZ_256K) + +#ifdef CONFIG_ARCH_SCX30G +#define CPW_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M) +#else +#define CPW_START_ADDR (CONFIG_PHYS_OFFSET + 256 * SZ_1M) +#endif +#if defined(CONFIG_MODEM_W_MEMCUT) +#define CPW_TOTAL_SIZE (SZ_1M * 28) +#elif defined CONFIG_ARCH_SCX30G +#define CPW_TOTAL_SIZE (SZ_1M * 27) +#else +#define CPW_TOTAL_SIZE (SZ_1M * 33) +#endif +#define CPW_RING_ADDR (CPW_START_ADDR + CPW_TOTAL_SIZE - SZ_4K) +#define CPW_RING_SIZE (SZ_4K) +#define CPW_SMEM_SIZE (SZ_1M + SZ_256K) + +#if defined(CONFIG_ARCH_SCX30G) +#define WCN_START_ADDR (CONFIG_PHYS_OFFSET + 168 * SZ_1M)//Tshark moves cp2 to 168M +#define WCN_TOTAL_SIZE 0x201000//Tshark 8830gea memcut to 2M+4k +#else +#define WCN_START_ADDR (CONFIG_PHYS_OFFSET + 320 * SZ_1M) +#define WCN_TOTAL_SIZE 0x281000//(SZ_1M * 5) +#endif +#define WCN_RING_ADDR (WCN_START_ADDR + WCN_TOTAL_SIZE - SZ_4K) +#define WCN_RING_SIZE (SZ_4K) +#define WCN_SMEM_SIZE (SZ_512K + SZ_256K) +#endif +#endif diff --git a/include/soc/sprd/__hardware-sc9630.h b/include/soc/sprd/__hardware-sc9630.h new file mode 100755 index 00000000..67311eb7 --- /dev/null +++ b/include/soc/sprd/__hardware-sc9630.h @@ -0,0 +1,168 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARCH_HARDWARE_SCX35L_H +#define __ASM_ARCH_HARDWARE_SCX35L_H + +#ifndef __ASM_ARCH_SCI_HARDWARE_H +#error "Don't include this file directly, include <mach/hardware.h>" +#endif + +#define SCI_IOMAP_BASE 0xF5000000 + +#define SCI_IOMAP(x) (SCI_IOMAP_BASE + (x)) + +#define SCI_IOMEMMAP_BASE 0xcc800000 + +#define SCI_IOMEMMAP(x) (SCI_IOMEMMAP_BASE + (x)) + +#ifndef SCI_ADDR +#define SCI_ADDR(_b_, _o_) ( (u32)(_b_) + (_o_) ) +#endif + +#define LL_DEBUG_UART_PHYS SPRD_UART1_PHYS +#define LL_DEBUG_UART_BASE SPRD_UART1_BASE + +#include <soc/sprd/iomap.h> + +#if !defined __ASSEMBLER__ +extern unsigned long sprd_adi_base; +extern unsigned long sprd_adi_phys; +#define SPRD_ADI_BASE sprd_adi_base +#define SPRD_ADI_PHYS sprd_adi_phys +#define CONFIG_PHYS_OFFSET 0x80000000 + +#define SPRD_ADISLAVE_BASE (SPRD_ADI_BASE+0x8000) +#define SPRD_ADISLAVE_PHYS (SPRD_ADI_PHYS+0x8000) +#define REGS_ADISLAVE_BASE SPRD_ADISLAVE_BASE +#define REGS_ADISLAVE_PHYS SPRD_ADISLAVE_PHYS +#endif + +#define SPRD_UART0_BASE SCI_IOMAP(0x360000) +#define SPRD_UART0_PHYS 0x70000000 +#define SPRD_UART0_SIZE SZ_4K + +#define SPRD_UART1_BASE SCI_IOMAP(0x362000) +#define SPRD_UART1_PHYS 0x70100000 +#define SPRD_UART1_SIZE SZ_4K + +#define SPRD_UART2_BASE SCI_IOMAP(0x364000) +#define SPRD_UART2_PHYS 0x70200000 +#define SPRD_UART2_SIZE SZ_4K + +#define SPRD_UART3_BASE SCI_IOMAP(0x366000) +#define SPRD_UART3_PHYS 0x70300000 +#define SPRD_UART3_SIZE SZ_4K + +#define SPRD_UART4_BASE SCI_IOMAP(0x368000) +#define SPRD_UART4_PHYS 0x70400000 +#define SPRD_UART4_SIZE SZ_4K + +#ifdef CONFIG_ARCH_SCX20L +#define SPRD_ARM7AHBRF_BASE SCI_IOMAP(0x36A000) +#define SPRD_ARM7AHBRF_PHYS 0x50820000 +#define SPRD_ARM7AHBRF_SIZE SZ_4K +#endif + +#define SPRD_IRAM0_BASE SCI_IOMAP(0x3d0000) +#define SPRD_IRAM0_PHYS 0x0 +#define SPRD_IRAM0_SIZE SZ_4K + +#define SPRD_IRAM0H_BASE SCI_IOMAP(0x3d1000) +#define SPRD_IRAM0H_PHYS 0x1000 +#define SPRD_IRAM0H_SIZE SZ_4K + +#define SPRD_IRAM1_BASE SCI_IOMAP(0x3e0000) +#define SPRD_IRAM1_PHYS 0x50000000 +#define SPRD_IRAM1_SIZE (SZ_32K + SZ_8K + SZ_4K + SZ_2K) + +#define SPRD_IRAM2_BASE SCI_IOMAP(0x3d7000) +#define SPRD_IRAM2_PHYS 0x50002000 +#define SPRD_IRAM2_SIZE (SZ_16K + SZ_4K + SZ_2K + SZ_1K) + +#define SPRD_PWM_BASE SCI_IOMAP(0x20a000) +#define SPRD_PWM_PHYS 0X40260000 +#define SPRD_PWM_SIZE SZ_4K + +#define SPRD_LPDDR2_BASE SCI_IOMAP(0x160000) +#define SPRD_LPDDR2_PHYS 0X30000000 +#define SPRD_LPDDR2_SIZE SZ_4K + +#define SPRD_SDIO1_PHYS 0X20400000 +#define SPRD_SDIO1_SIZE SZ_4K + + +#define SPRD_MALI_PHYS 0X60000000 + +#define CORE_GIC_CPU_VA (SPRD_CORE_BASE + 0x2000) +#define CORE_GIC_DIS_VA (SPRD_CORE_BASE + 0x1000) + +#define HOLDING_PEN_VADDR (SPRD_AHB_BASE + 0x14) +#define CPU_JUMP_VADDR (HOLDING_PEN_VADDR + 0X4) + +/* registers for watchdog ,RTC, touch panel, aux adc, analog die... */ +#define SPRD_MISC_BASE ((unsigned int)SPRD_ADI_BASE) +#define SPRD_MISC_PHYS ((unsigned int)SPRD_ADI_PHYS) + +#define ANA_PWM_BASE (SPRD_ADISLAVE_BASE + 0x20 ) +#define ANA_WDG_BASE (SPRD_ADISLAVE_BASE + 0x40 ) +#define ANA_RTC_BASE (SPRD_ADISLAVE_BASE + 0x80 ) +#define ANA_EIC_BASE (SPRD_ADISLAVE_BASE + 0x100 ) +#define ANA_PIN_BASE (SPRD_ADISLAVE_BASE + 0x180 ) +#define ANA_THM_BASE (SPRD_ADISLAVE_BASE + 0x280 ) +#define ADC_BASE (SPRD_ADISLAVE_BASE + 0x300 ) +#define ANA_CTL_INT_BASE (SPRD_ADISLAVE_BASE + 0x380 ) +#define ANA_BTLC_INT_BASE (SPRD_ADISLAVE_BASE + 0x3c0 ) +#define ANA_AUDIFA_INT_BASE (SPRD_ADISLAVE_BASE + 0x400 ) +#define ANA_GPIO_INT_BASE (SPRD_ADISLAVE_BASE + 0x480 ) +#define ANA_FPU_INT_BASE (SPRD_ADISLAVE_BASE + 0x500 ) +#define ANA_AUDCFGA_INT_BASE (SPRD_ADISLAVE_BASE + 0x600 ) +#define ANA_HDT_INT_BASE (SPRD_ADISLAVE_BASE + 0x700 ) +#define ANA_CTL_GLB_BASE (SPRD_ADISLAVE_BASE + 0x800 ) + +#ifndef REGS_AHB_BASE +#define REGS_AHB_BASE ( SPRD_AHB_BASE + 0x200) +#endif + +#define SPRD_IRAM_BASE SPRD_IRAM0_BASE + 0x1000 +#define SPRD_IRAM_PHYS SPRD_IRAM0_PHYS + 0x1000 +#define SPRD_IRAM_SIZE SZ_4K +#define SPRD_GREG_BASE SPRD_AONAPB_BASE +#define SPRD_GREG_PHYS SPRD_AONAPB_PHYS +#define SPRD_GREG_SIZE SZ_64K + +#ifndef REGS_GLB_BASE +#define REGS_GLB_BASE ( SPRD_GREG_BASE ) +#define ANA_REGS_GLB_BASE ( ANA_CTL_GLB_BASE ) +#endif + +#define CHIP_ID_LOW_REG (SPRD_AHB_BASE + 0xfc) + +#define SPRD_GPTIMER_BASE SPRD_GPTIMER0_BASE +#define SPRD_EFUSE_BASE SPRD_UIDEFUSE_BASE + +#define REGS_AP_AHB_BASE SPRD_AHB_BASE +#define REGS_AP_APB_BASE SPRD_APBREG_BASE +#define REGS_AON_APB_BASE SPRD_AONAPB_BASE +#define REGS_GPU_APB_BASE SPRD_GPUAPB_BASE +#define REGS_MM_AHB_BASE SPRD_MMAHB_BASE +#define REGS_PMU_APB_BASE SPRD_PMU_BASE +#define REGS_AON_CLK_BASE SPRD_AONCKG_BASE +#define REGS_AP_CLK_BASE SPRD_APBCKG_BASE +#define REGS_GPU_CLK_BASE SPRD_GPUCKG_BASE +#define REGS_MM_CLK_BASE SPRD_MMCKG_BASE +#define REGS_PUB_APB_BASE SPRD_PUB_BASE +#define REGS_ARM7_AHB_RF_BASE SPRD_ARM7AHBRF_BASE + + +#endif diff --git a/include/soc/sprd/__irqs-sc8830.h b/include/soc/sprd/__irqs-sc8830.h Binary files differnew file mode 100755 index 00000000..373c1ed2 --- /dev/null +++ b/include/soc/sprd/__irqs-sc8830.h diff --git a/include/soc/sprd/__regs_ahb.h b/include/soc/sprd/__regs_ahb.h new file mode 100644 index 00000000..0046bc42 --- /dev/null +++ b/include/soc/sprd/__regs_ahb.h @@ -0,0 +1,373 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __REGS_AHB_H__ +#define __REGS_AHB_H__ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, include <mach/sci_glb_regs.h>" +#endif + +#define REGS_AHB + +/* registers definitions for controller REGS_AHB */ +#define REG_AHB_AHB_CTL0 SCI_ADDR(REGS_AHB_BASE, 0x0000) +#define REG_AHB_AHB_CTL1 SCI_ADDR(REGS_AHB_BASE, 0x0004) +#define REG_AHB_AHB_CTL2 SCI_ADDR(REGS_AHB_BASE, 0x0008) +#define REG_AHB_AHB_CTL3 SCI_ADDR(REGS_AHB_BASE, 0x000c) +#define REG_AHB_SOFT_RST SCI_ADDR(REGS_AHB_BASE, 0x0010) +#define REG_AHB_AHB_PAUSE SCI_ADDR(REGS_AHB_BASE, 0x0014) +#define REG_AHB_REMAP SCI_ADDR(REGS_AHB_BASE, 0x0018) +#define REG_AHB_MIPI_PHY_CTRL SCI_ADDR(REGS_AHB_BASE, 0x001c) +#define REG_AHB_DISPC_CTRL SCI_ADDR(REGS_AHB_BASE, 0x0020) +#define REG_AHB_ARM_CLK SCI_ADDR(REGS_AHB_BASE, 0x0024) +#define REG_AHB_AHB_SDIO_CTRL SCI_ADDR(REGS_AHB_BASE, 0x0028) +#define REG_AHB_AHB_CTL4 SCI_ADDR(REGS_AHB_BASE, 0x002c) +#define REG_AHB_AHB_CTL5 SCI_ADDR(REGS_AHB_BASE, 0x0030) +#define REG_AHB_AHB_STATUS SCI_ADDR(REGS_AHB_BASE, 0x0034) +#define REG_AHB_CA5_CFG SCI_ADDR(REGS_AHB_BASE, 0x0038) +#define REG_AHB_ISP_CTRL SCI_ADDR(REGS_AHB_BASE, 0x003c) +#define REG_AHB_HOLDING_PEN SCI_ADDR(REGS_AHB_BASE, 0x0040) +#define REG_AHB_JMP_ADDR_CPU0 SCI_ADDR(REGS_AHB_BASE, 0x0044) +#define REG_AHB_JMP_ADDR_CPU1 SCI_ADDR(REGS_AHB_BASE, 0x0048) +#define REG_AHB_CP_AHB_ARM_CLK SCI_ADDR(REGS_AHB_BASE, 0x004c) +#define REG_AHB_CP_AHB_CTL SCI_ADDR(REGS_AHB_BASE, 0x0050) +#define REG_AHB_CP_RST SCI_ADDR(REGS_AHB_BASE, 0x0054) +#define REG_AHB_CP_SLEEP_CTRL SCI_ADDR(REGS_AHB_BASE, 0x0058) +#define REG_AHB_DEEPSLEEP_STATUS SCI_ADDR(REGS_AHB_BASE, 0x005c) +#define REG_AHB_DDR_PHY_Z_VALUE SCI_ADDR(REGS_AHB_BASE, 0x0060) +#define REG_AHB_DSP_JTAG_CTRL SCI_ADDR(REGS_AHB_BASE, 0x0080) +#define REG_AHB_DSP_BOOT_EN SCI_ADDR(REGS_AHB_BASE, 0x0084) +#define REG_AHB_DSP_BOOT_VEC SCI_ADDR(REGS_AHB_BASE, 0x0088) +#define REG_AHB_DSP_RST SCI_ADDR(REGS_AHB_BASE, 0x008c) +#define REG_AHB_BIGEND_PORT SCI_ADDR(REGS_AHB_BASE, 0x0090) +#define REG_AHB_USB_PHY_TUNE SCI_ADDR(REGS_AHB_BASE, 0x00a0) +#define REG_AHB_USB_PHY_TEST SCI_ADDR(REGS_AHB_BASE, 0x00a4) +#define REG_AHB_USB_PHY_CTRL SCI_ADDR(REGS_AHB_BASE, 0x00a8) +#define REG_AHB_AHB_SPR_REG SCI_ADDR(REGS_AHB_BASE, 0x00c0) +#define REG_AHB_MTX_CTRL SCI_ADDR(REGS_AHB_BASE, 0x0100) +#define REG_AHB_EMC_CTRL_CFG0 SCI_ADDR(REGS_AHB_BASE, 0x0104) +#define REG_AHB_EMC_CTRL_CFG1 SCI_ADDR(REGS_AHB_BASE, 0x0108) +#define REG_AHB_EMC_CLIENT_CTRL SCI_ADDR(REGS_AHB_BASE, 0x010c) +#define REG_AHB_EMC_PORT0_REMAP SCI_ADDR(REGS_AHB_BASE, 0x0110) +#define REG_AHB_EMC_PORT1_REMAP SCI_ADDR(REGS_AHB_BASE, 0x0114) +#define REG_AHB_EMC_PORT2_REMAP SCI_ADDR(REGS_AHB_BASE, 0x0118) +#define REG_AHB_EMC_PORT3_REMAP SCI_ADDR(REGS_AHB_BASE, 0x011c) +#define REG_AHB_EMC_PORT4_REMAP SCI_ADDR(REGS_AHB_BASE, 0x0120) +#define REG_AHB_EMC_PORT5_REMAP SCI_ADDR(REGS_AHB_BASE, 0x0124) +#define REG_AHB_EMC_PORT6_REMAP SCI_ADDR(REGS_AHB_BASE, 0x0128) +#define REG_AHB_EMC_PORT7_REMAP SCI_ADDR(REGS_AHB_BASE, 0x012c) +#define REG_AHB_MSTX_SIM0_CTL00 SCI_ADDR(REGS_AHB_BASE, 0x0130) +#define REG_AHB_MSTX_SIM0_CTL01 SCI_ADDR(REGS_AHB_BASE, 0x0134) +#define REG_AHB_MSTX_SIM1_CTL00 SCI_ADDR(REGS_AHB_BASE, 0x0140) +#define REG_AHB_MSTX_SIM1_CTL01 SCI_ADDR(REGS_AHB_BASE, 0x0144) +#define REG_AHB_MSTX_SIM2_CTL00 SCI_ADDR(REGS_AHB_BASE, 0x0150) +#define REG_AHB_MSTX_SIM2_CTL01 SCI_ADDR(REGS_AHB_BASE, 0x0154) +#define REG_AHB_MSTX_SIM3_CTL00 SCI_ADDR(REGS_AHB_BASE, 0x0160) +#define REG_AHB_MSTX_SIM3_CTL01 SCI_ADDR(REGS_AHB_BASE, 0x0164) +#define REG_AHB_MSTX_SIM4_CTL00 SCI_ADDR(REGS_AHB_BASE, 0x0170) +#define REG_AHB_MSTX_SIM4_CTL01 SCI_ADDR(REGS_AHB_BASE, 0x0174) +#define REG_AHB_MSTX_SIM4_CTL10 SCI_ADDR(REGS_AHB_BASE, 0x0178) +#define REG_AHB_MSTX_SIM4_CTL11 SCI_ADDR(REGS_AHB_BASE, 0x017c) +#define REG_AHB_DSPX_SIM0_CTL00 SCI_ADDR(REGS_AHB_BASE, 0x0180) +#define REG_AHB_DSPX_SIM0_CTL01 SCI_ADDR(REGS_AHB_BASE, 0x0184) +#define REG_AHB_CHIP_ID SCI_ADDR(REGS_AHB_BASE, 0x01fc) + +/* bits definitions for register REG_AHB_AHB_CTL0 */ +#define BIT_AXIBUSMON2_EB ( BIT(31) ) +#define BIT_AXIBUSMON1_EB ( BIT(30) ) +#define BIT_AXIBUSMON0_EB ( BIT(29) ) +#define BIT_EMC_EB ( BIT(28) ) +#define BIT_AHB_ARCH_EB ( BIT(27) ) +#define BIT_SPINLOCK_EB ( BIT(25) ) +#define BIT_SDIO2_EB ( BIT(24) ) +#define BIT_EMMC_EB ( BIT(23) ) +#define BIT_DISPC_EB ( BIT(22) ) +#define BIT_G3D_EB ( BIT(21) ) +#define BIT_SDIO1_EB ( BIT(19) ) +#define BIT_DRM_EB ( BIT(18) ) +#define BIT_BUSMON4_EB ( BIT(17) ) +#define BIT_BUSMON3_EB ( BIT(16) ) +#define BIT_BUSMON2_EB ( BIT(15) ) +#define BIT_ROT_EB ( BIT(14) ) +#define BIT_VSP_EB ( BIT(13) ) +#define BIT_ISP_EB ( BIT(12) ) +#define BIT_BUSMON1_EB ( BIT(11) ) +#define BIT_DCAM_MIPI_EB ( BIT(10) ) +#define BIT_CCIR_EB ( BIT(9) ) +#define BIT_NFC_EB ( BIT(8) ) +#define BIT_BUSMON0_EB ( BIT(7) ) +#define BIT_DMA_EB ( BIT(6) ) +#define BIT_USBD_EB ( BIT(5) ) +#define BIT_SDIO0_EB ( BIT(4) ) +#define BIT_LCDC_EB ( BIT(3) ) +#define BIT_CCIR_IN_EB ( BIT(2) ) +#define BIT_DCAM_EB ( BIT(1) ) + +/* bits definitions for register REG_AHB_AHB_CTL1 */ +#define BIT_ARM_DAHB_SLP_EN ( BIT(16) ) +#define BIT_MSTMTX_AUTO_GATE_EN ( BIT(14) ) +#define BIT_MCU_AUTO_GATE_EN ( BIT(13) ) +#define BIT_AHB_AUTO_GATE_EN ( BIT(12) ) +#define BIT_ARM_AUTO_GATE_EN ( BIT(11) ) +#define BIT_APB_FRC_SLEEP ( BIT(10) ) +#define BIT_EMC_CH_AUTO_GATE_EN ( BIT(9) ) +#define BIT_EMC_AUTO_GATE_EN ( BIT(8) ) + +/* bits definitions for register REG_AHB_AHB_CTL2 */ +#define BIT_DISPMTX_CLK_EN ( BIT(11) ) +#define BIT_MMMTX_CLK_EN ( BIT(10) ) +#define BIT_DISPC_CORE_CLK_EN ( BIT(9) ) +#define BIT_LCDC_CORE_CLK_EN ( BIT(8) ) +#define BIT_ISP_CORE_CLK_EN ( BIT(7) ) +#define BIT_VSP_CORE_CLK_EN ( BIT(6) ) +#define BIT_DCAM_CORE_CLK_EN ( BIT(5) ) +#define BITS_MCU_SHM0_CTRL(_x_) ( (_x_) << 3 & (BIT(3)|BIT(4)) ) + +/* bits definitions for register REG_AHB_AHB_CTL3 */ +#define BIT_CLK_ULPI_EN ( BIT(10) ) +#define BIT_UTMI_SUSPEND_INV ( BIT(9) ) +#define BIT_UTMIFS_TX_EN_INV ( BIT(8) ) +#define BIT_CLK_UTMIFS_EN ( BIT(7) ) +#define BIT_CLK_USB_REF_EN ( BIT(6) ) +#define BIT_BUSMON_SEL1 ( BIT(5) ) +#define BIT_BUSMON_SEL0 ( BIT(4) ) +#define BIT_USB_M_HBIGENDIAN ( BIT(2) ) +#define BIT_USB_S_HBIGEIDIAN ( BIT(1) ) +#define BIT_CLK_USB_REF_SEL ( BIT(0) ) + +/* bits definitions for register REG_AHB_SOFT_RST */ +#define BIT_DISPMTX_SOFT_RST ( BIT(31) ) +#define BIT_MMMTX_SOFT_RST ( BIT(30) ) +#define BIT_CA5_CORE1_SOFT_RST ( BIT(29) ) +#define BIT_CA5_CORE0_SOFT_RST ( BIT(28) ) +#define BIT_MIPI_CSIHOST_SOFT_RST ( BIT(27) ) +#define BIT_MIPI_DSIHOST_SOFT_RST ( BIT(26) ) +#define BIT_SPINLOCK_SOFT_RST ( BIT(25) ) +#define BIT_CAM1_SOFT_RST ( BIT(24) ) +#define BIT_CAM0_SOFT_RST ( BIT(23) ) +#define BIT_SD2_SOFT_RST ( BIT(22) ) +#define BIT_EMMC_SOFT_RST ( BIT(21) ) +#define BIT_DISPC_SOFT_RST ( BIT(20) ) +#define BIT_G3D_SOFT_RST ( BIT(19) ) +#define BIT_DBG_SOFT_RST ( BIT(18) ) +#define BIT_CA2AP_AB_SOFT_RST ( BIT(17) ) +#define BIT_SD1_SOFT_RST ( BIT(16) ) +#define BIT_VSP_SOFT_RST ( BIT(15) ) +#define BIT_ADC_SOFT_RST ( BIT(14) ) +#define BIT_DRM_SOFT_RST ( BIT(13) ) +#define BIT_SD0_SOFT_RST ( BIT(12) ) +#define BIT_EMC_SOFT_RST ( BIT(11) ) +#define BIT_ROT_SOFT_RST ( BIT(10) ) +#define BIT_ISP_SOFT_RST ( BIT(8) ) +#define BIT_USBPHY_SOFT_RST ( BIT(7) ) +#define BIT_USBD_UTMI_SOFT_RST ( BIT(6) ) +#define BIT_NFC_SOFT_RST ( BIT(5) ) +#define BIT_LCDC_SOFT_RST ( BIT(3) ) +#define BIT_CCIR_SOFT_RST ( BIT(2) ) +#define BIT_DCAM_SOFT_RST ( BIT(1) ) +#define BIT_DMA_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_AHB_AHB_PAUSE */ +#define BIT_MCU_DEEP_SLP_EN ( BIT(2) ) +#define BIT_MCU_SYS_SLP_EN ( BIT(1) ) +#define BIT_MCU_CORE_FRC_SLP ( BIT(0) ) + +/* bits definitions for register REG_AHB_REMAP */ +#define BITS_ARM_RES_STRAPPIN(_x_) ( (_x_) << 30 & (BIT(30)|BIT(31)) ) +#define BIT_FUNC_TEST_MODE_AS_SEL ( BIT(8) ) +#define BIT_FUNC_TEST_MODE ( BIT(7) ) +#define BIT_ARM_BOOT_MD3 ( BIT(6) ) +#define BIT_ARM_BOOT_MD2 ( BIT(5) ) +#define BIT_ARM_BOOT_MD1 ( BIT(4) ) +#define BIT_ARM_BOOT_MD0 ( BIT(3) ) +#define BIT_USB_DLOAD_EN ( BIT(2) ) +#define BIT_REMAP ( BIT(0) ) + +/* bits definitions for register REG_AHB_MIPI_PHY_CTRL */ +#define BIT_MIPI_CPHY_EN ( BIT(1) ) +#define BIT_MIPI_DPHY_EN ( BIT(0) ) + +/* bits definitions for register REG_AHB_DISPC_CTRL */ +#define BITS_CLK_DISPC_DPI_DIV(_x_) ( (_x_) << 19 & (BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)) ) +#define BITS_CLK_DISPC_DPIPLL_SEL(_x_) ( (_x_) << 17 & (BIT(17)|BIT(18)) ) +#define BITS_CLK_DISPC_DBI_DIV(_x_) ( (_x_) << 11 & (BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_CLK_DISPC_DBIPLL_SEL(_x_) ( (_x_) << 9 & (BIT(9)|BIT(10)) ) +#define BITS_CLK_DISPC_DIV(_x_) ( (_x_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_CLK_DISPC_PLL_SEL(_x_) ( (_x_) << 1 & (BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AHB_ARM_CLK */ +#define BITS_AHB_DIV_INUSE(_x_) ( (_x_) << 27 & (BIT(27)|BIT(28)|BIT(29)) ) +#define BIT_AHB_ERR_YET ( BIT(26) ) +#define BIT_AHB_ERR_CLR ( BIT(25) ) +#define BITS_CLK_MCU_SEL(_x_) ( (_x_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_CLK_ARM_PERI_DIV(_x_) ( (_x_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_CLK_DBG_DIV(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_CLK_EMC_SEL(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_CLK_EMC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CLK_AHB_DIV(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_CLK_EMC_SYNC_SEL ( BIT(3) ) +#define BITS_CLK_ARM_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AHB_AHB_SDIO_CTRL */ +#define BIT_EMMC_SLOT_SEL ( BIT(5) ) +#define BIT_SDIO2_SLOT_SEL ( BIT(4) ) +#define BITS_SDIO1_SLOT_SEL(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_SDIO0_SLOT_SEL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AHB_AHB_CTL4 */ +#define BIT_RX_CLK_SEL_ARM ( BIT(31) ) +#define BIT_RX_CLK_INV_ARM ( BIT(30) ) +#define BIT_RX_INV ( BIT(29) ) + +/* bits definitions for register REG_AHB_AHB_CTL5 */ +#define BIT_BUSMON4_BIGEND_EN ( BIT(17) ) +#define BIT_BUSMON3_BIGEND_EN ( BIT(16) ) +#define BIT_BUSMON2_BIGEND_EN ( BIT(15) ) +#define BIT_EMMC_BIGEND_EN ( BIT(14) ) +#define BIT_SDIO2_BIGEND_EN ( BIT(13) ) +#define BIT_DISPC_BIGEND_EN ( BIT(12) ) +#define BIT_SDIO1_BIGEND_EN ( BIT(11) ) +#define BIT_SHRAM0_BIGEND_EN ( BIT(9) ) +#define BIT_BUSMON1_BIGEND_EN ( BIT(8) ) +#define BIT_BUSMON0_BIGEND_EN ( BIT(7) ) +#define BIT_ROT_BIGEND_EN ( BIT(6) ) +#define BIT_SDIO0_BIGEND_EN ( BIT(3) ) +#define BIT_LCDC_BIGEND_EN ( BIT(2) ) +#define BIT_DMA_BIGEND_EN ( BIT(0) ) + +/* bits definitions for register REG_AHB_AHB_STATUS */ +#define BIT_APB_PERI_EN ( BIT(20) ) +#define BIT_DSP_MAHB_SLP_EN ( BIT(19) ) +#define BIT_DMA_BUSY ( BIT(18) ) +#define BIT_EMC_SLEEP ( BIT(17) ) +#define BIT_EMC_STOP ( BIT(16) ) +#define BITS_EMC_CTL_STA(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BIT_EMC_STOP_CH7 ( BIT(7) ) +#define BIT_EMC_STOP_CH6 ( BIT(6) ) +#define BIT_EMC_STOP_CH5 ( BIT(5) ) +#define BIT_EMC_STOP_CH4 ( BIT(4) ) +#define BIT_EMC_STOP_CH3 ( BIT(3) ) +#define BIT_EMC_STOP_CH2 ( BIT(2) ) +#define BIT_EMC_STOP_CH1 ( BIT(1) ) +#define BIT_EMC_STOP_CH0 ( BIT(0) ) + +/* bits definitions for register REG_AHB_CA5_CFG */ +#define BIT_CA5_WDRESET_EN ( BIT(18) ) +#define BIT_CA5_TS_EN ( BIT(17) ) +#define BIT_CA5_CORE1_GATE_EN ( BIT(16) ) +#define BIT_CA5_CFGSDISABLE ( BIT(13) ) +#define BITS_CA5_CLK_AXI_DIV(_x_) ( (_x_) << 11 & (BIT(11)|BIT(12)) ) +#define BIT_CA5_CLK_DBG_EN_SEL ( BIT(10) ) +#define BIT_CA5_CLK_DBG_EN ( BIT(9) ) +#define BIT_CA5_DBGEN ( BIT(8) ) +#define BIT_CA5_NIDEN ( BIT(7) ) +#define BIT_CA5_SPIDEN ( BIT(6) ) +#define BIT_CA5_SPNIDEN ( BIT(5) ) +#define BIT_CA5_CPI15DISABLE ( BIT(4) ) +#define BIT_CA5_TEINIT ( BIT(3) ) +#define BIT_CA5_L1RSTDISABLE ( BIT(2) ) +#define BIT_CA5_L2CFGEND ( BIT(1) ) +#define BIT_CA5_L2SPNIDEN ( BIT(0) ) + +/* bits definitions for register REG_AHB_ISP_CTRL */ +#define BITS_CLK_ISP_DIV(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)) ) +#define BITS_CLK_ISPPLL_SEL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AHB_CP_AHB_ARM_CLK */ +#define BITS_CP_AHB_DIV_INUSE(_x_) ( (_x_) << 27 & (BIT(27)|BIT(28)|BIT(29)) ) +#define BIT_CP_AHB_ERR_YET ( BIT(26) ) +#define BIT_CP_AHB_ERR_CLR ( BIT(25) ) +#define BITS_CLK_CP_MCU_SEL(_x_) ( (_x_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_CLK_CP_AHB_DIV(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BITS_CLK_CP_ARM_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AHB_CP_AHB_CTL */ +#define BIT_CP_AP_JTAG_CHAIN_EN ( BIT(3) ) +#define BIT_ASHB_CPTOAP_EN_I ( BIT(2) ) +#define BIT_CP_RAM_SEL ( BIT(1) ) +#define BIT_CLK_CP_EN ( BIT(0) ) + +/* bits definitions for register REG_AHB_CP_RST */ +#define BIT_CP_CORE_SRST_N ( BIT(0) ) + +/* bits definitions for register REG_AHB_CP_SLEEP_CTRL */ +#define BIT_FORCE_CP_DEEP_SLEEP_EN ( BIT(0) ) + +/* bits definitions for register REG_AHB_DEEPSLEEP_STATUS */ +#define BITS_CP_SLEEP_FLAG(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_AP_SLEEP_FLAG(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AHB_DDR_PHY_Z_VALUE */ +#define BITS_DDR_PHY_Z_VALUE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_AHB_DSP_JTAG_CTRL */ +#define BIT_CEVA_SW_JTAG_ENA ( BIT(8) ) +#define BIT_STDO ( BIT(4) ) +#define BIT_STCK ( BIT(3) ) +#define BIT_STMS ( BIT(2) ) +#define BIT_STDI ( BIT(1) ) +#define BIT_STRTCK ( BIT(0) ) + +/* bits definitions for register REG_AHB_DSP_BOOT_EN */ +#define BIT_ASHB_ARMTODSP_EN_I ( BIT(2) ) +#define BIT_FRC_CLK_DSP_EN ( BIT(1) ) +#define BIT_DSP_BOOT_EN ( BIT(0) ) + +/* bits definitions for register REG_AHB_DSP_RST */ +#define BIT_DSP_SYS_SRST ( BIT(1) ) +#define BIT_DSP_CORE_SRST_N ( BIT(0) ) + +/* bits definitions for register REG_AHB_BIGEND_PORT */ +#define BIT_AHB_BIGEND_PROT ( BIT(31) ) +#define BITS_BIGEND_PROT_VAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AHB_USB_PHY_TUNE */ +#define BITS_OTGTUNE(_x_) ( (_x_) << 28 & (BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_COMPDISTUNE(_x_) ( (_x_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BIT_TXPREEMPPULSETUNE ( BIT(20) ) +#define BITS_TXRESTUNE(_x_) ( (_x_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_TXHSXVTUNE(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_TXVREFTUNE(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_TXPREEMPAMP(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_TXRISETUNE(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_TXFSLSTUNE(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_SQRXTUNE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AHB_USB_PHY_CTRL */ +#define BIT_TXBITSTUFFENH ( BIT(23) ) +#define BIT_TXBITSTUFFEN ( BIT(22) ) +#define BIT_DMPULLDOWN ( BIT(21) ) +#define BIT_DPPULLDOWN ( BIT(20) ) +#define BIT_DMPULLUP ( BIT(9) ) +#define BIT_COMMONONN ( BIT(8) ) +#define BITS_REFCLKSEL(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_USBPHY_FSEL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AHB_MTX_CTRL */ +#define BIT_DSPP_BUF_EN ( BIT(10) ) +#define BIT_DSPD_BUF_EN ( BIT(9) ) +#define BIT_DSP_MTX_DMA_BUF_EN ( BIT(8) ) +#define BIT_MST_MTX_MST_BUF_EN ( BIT(7) ) +#define BIT_MST_MTX_MST_BUF_FRC_EN ( BIT(6) ) + +/* vars definitions for controller REGS_AHB */ +#define REG_AHB_SET(A) ( A + 0x1000 ) +#define REG_AHB_CLR(A) ( A + 0x2000 ) + +#endif //__REGS_AHB_H__ diff --git a/include/soc/sprd/__regs_ana_glb.h b/include/soc/sprd/__regs_ana_glb.h new file mode 100644 index 00000000..a1d51c99 --- /dev/null +++ b/include/soc/sprd/__regs_ana_glb.h @@ -0,0 +1,571 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __ANA_REGS_GLB_H__ +#define __ANA_REGS_GLB_H__ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, include <mach/sci_glb_regs.h>" +#endif + +#define ANA_REGS_GLB + +/* registers definitions for controller ANA_REGS_GLB */ +#define ANA_REG_GLB_ANA_APB_CLK_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x000) +#define ANA_REG_GLB_ANA_APB_ARM_RST SCI_ADDR(ANA_REGS_GLB_BASE, 0x004) +#define ANA_REG_GLB_LDO_PD_SET SCI_ADDR(ANA_REGS_GLB_BASE, 0x008) +#define ANA_REG_GLB_LDO_PD_RST SCI_ADDR(ANA_REGS_GLB_BASE, 0x00c) +#define ANA_REG_GLB_LDO_PD_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x010) +#define ANA_REG_GLB_LDO_PD_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x014) +#define ANA_REG_GLB_LDO_VCTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x018) +#define ANA_REG_GLB_LDO_VCTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x01c) +#define ANA_REG_GLB_LDO_VCTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x020) +#define ANA_REG_GLB_LDO_VCTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x024) +#define ANA_REG_GLB_LDO_VCTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x028) +#define ANA_REG_GLB_LDO_SLP_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x030) +#define ANA_REG_GLB_LDO_SLP_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x034) +#define ANA_REG_GLB_LDO_SLP_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x038) +#define ANA_REG_GLB_LDO_SLP_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x03c) +#define ANA_REG_GLB_DCDC_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x040) +#define ANA_REG_GLB_DCDC_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x044) +#define ANA_REG_GLB_DCDC_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x048) +#define ANA_REG_GLB_DCDC_CTRL_DS SCI_ADDR(ANA_REGS_GLB_BASE, 0x04c) +#define ANA_REG_GLB_DCDC_CTRL_CAL SCI_ADDR(ANA_REGS_GLB_BASE, 0x050) +#define ANA_REG_GLB_PLL_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x054) +#define ANA_REG_GLB_APLLMN SCI_ADDR(ANA_REGS_GLB_BASE, 0x058) +#define ANA_REG_GLB_APLLWAIT SCI_ADDR(ANA_REGS_GLB_BASE, 0x05c) +#define ANA_REG_GLB_RTC_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x060) +#define ANA_REG_GLB_BUF26M_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x064) +#define ANA_REG_GLB_CHGR_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x068) +#define ANA_REG_GLB_CHGR_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x06c) +#define ANA_REG_GLB_LED_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x070) +#define ANA_REG_GLB_VIBRATOR_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x074) +#define ANA_REG_GLB_VIBRATOR_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x078) +#define ANA_REG_GLB_ARM_AUD_CLK_RST SCI_ADDR(ANA_REGS_GLB_BASE, 0x07c) +#define ANA_REG_GLB_ANA_MIXED_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x080) +#define ANA_REG_GLB_ANA_STATUS SCI_ADDR(ANA_REGS_GLB_BASE, 0x084) +#define ANA_REG_GLB_RST_STATUS SCI_ADDR(ANA_REGS_GLB_BASE, 0x088) +#define ANA_REG_GLB_MCU_WR_PROT SCI_ADDR(ANA_REGS_GLB_BASE, 0x08c) +#define ANA_REG_GLB_VIBR_WR_PROT SCI_ADDR(ANA_REGS_GLB_BASE, 0x090) +#define ANA_REG_GLB_INT_GPI_DEBUG SCI_ADDR(ANA_REGS_GLB_BASE, 0x094) +#define ANA_REG_GLB_HWRST_RTC SCI_ADDR(ANA_REGS_GLB_BASE, 0x098) +#define ANA_REG_GLB_DCDCOTP_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x09c) +#define ANA_REG_GLB_POR_SRC_STAT SCI_ADDR(ANA_REGS_GLB_BASE, 0x0a0) +#define ANA_REG_GLB_POR_SRC_FLAG_CLR SCI_ADDR(ANA_REGS_GLB_BASE, 0x0a4) +#define ANA_REG_GLB_HW_REBOOT_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0a8) +#define ANA_REG_GLB_DCDCARM_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0ac) +#define ANA_REG_GLB_DCDCARM_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0b0) +#define ANA_REG_GLB_DCDCARM_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0b4) +#define ANA_REG_GLB_DCDCARM_CTRL_CAL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0b8) +#define ANA_REG_GLB_DCDCMEM_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0bc) +#define ANA_REG_GLB_DCDCMEM_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0c0) +#define ANA_REG_GLB_DCDCMEM_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0c4) +#define ANA_REG_GLB_DCDCMEM_CTRL_CAL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0c8) +#define ANA_REG_GLB_DDR2_BUF_CTRL0_DS SCI_ADDR(ANA_REGS_GLB_BASE, 0x0cc) +#define ANA_REG_GLB_DDR2_BUF_CTRL1_DS SCI_ADDR(ANA_REGS_GLB_BASE, 0x0d0) +#define ANA_REG_GLB_EFS_PROT SCI_ADDR(ANA_REGS_GLB_BASE, 0x0d4) +#define ANA_REG_GLB_EFS_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0d8) +#define ANA_REG_GLB_DCDCLDO_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0dc) +#define ANA_REG_GLB_DCDCLDO_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0e0) +#define ANA_REG_GLB_DCDCLDO_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0e4) +#define ANA_REG_GLB_DCDCLDO_CTRL_CAL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0e8) +#define ANA_REG_GLB_AFUSE_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0ec) +#define ANA_REG_GLB_AFUSE_OUT_LOW SCI_ADDR(ANA_REGS_GLB_BASE, 0x0f0) +#define ANA_REG_GLB_AFUSE_OUT_HIGH SCI_ADDR(ANA_REGS_GLB_BASE, 0x0f4) +#define ANA_REG_GLB_CHIP_ID_LOW SCI_ADDR(ANA_REGS_GLB_BASE, 0x0f8) +#define ANA_REG_GLB_CHIP_ID_HIGH SCI_ADDR(ANA_REGS_GLB_BASE, 0x0fc) + +/* bits definitions for register ANA_REG_GLB_ANA_APB_CLK_EN */ +#define BIT_ANA_CHGRWDG_EB ( BIT(15) ) +#define BIT_ANA_CLK_AUXAD_EN ( BIT(14) ) +#define BIT_ANA_CLK_AUXADC_EN ( BIT(13) ) +#define BIT_ANA_RTC_TPC_EB ( BIT(12) ) +#define BIT_ANA_RTC_EIC_EB ( BIT(11) ) +#define BIT_ANA_RTC_WDG_EB ( BIT(10) ) +#define BIT_ANA_RTC_RTC_EB ( BIT(9) ) +#define BIT_ANA_RTC_ARCH_EB ( BIT(8) ) +#define BIT_ANA_PINREG_EB ( BIT(7) ) +#define BIT_ANA_GPIO_EB ( BIT(6) ) +#define BIT_ANA_ADC_EB ( BIT(5) ) +#define BIT_ANA_TPC_EB ( BIT(4) ) +#define BIT_ANA_EIC_EB ( BIT(3) ) +#define BIT_ANA_WDG_EB ( BIT(2) ) +#define BIT_ANA_RTC_EB ( BIT(1) ) +#define BIT_ANA_APB_ARCH_EB ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_ANA_APB_ARM_RST */ +#define BIT_ANA_GPIO_SOFT_RST ( BIT(7) ) +#define BIT_ANA_EIC_SOFT_RST ( BIT(6) ) +#define BIT_ANA_TPC_SOFT_RST ( BIT(5) ) +#define BIT_ANA_ADC_SOFT_RST ( BIT(4) ) +#define BIT_ANA_WDG_SOFT_RST ( BIT(3) ) +#define BIT_ANA_CHGWDG_SOFT_RST ( BIT(2) ) +#define BIT_ANA_RTC_SOFT_RST ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_PD_SET */ +#define BIT_DCDC_LDO_PD ( BIT(9) ) +#define BIT_LDO_VDD25_PD ( BIT(8) ) +#define BIT_LDO_VDD18_PD ( BIT(7) ) +#define BIT_LDO_VDD28_PD ( BIT(6) ) +#define BIT_LDO_VDDAVDDBB_PD ( BIT(5) ) +#define BIT_LDO_RF_PD ( BIT(4) ) +#define BIT_DCDC_MEM_PD ( BIT(3) ) +#define BIT_DCDC_ARM_PD ( BIT(2) ) +#define BIT_DCDC_PD ( BIT(1) ) +#define BIT_BG_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_PD_RST */ +#define BIT_DCDC_LDO_RST ( BIT(9) ) +#define BIT_LDO_VDD25_RST ( BIT(8) ) +#define BIT_LDO_VDD18_RST ( BIT(7) ) +#define BIT_LDO_VDD28_RST ( BIT(6) ) +#define BIT_LDO_VDDAVDDBB_RST ( BIT(5) ) +#define BIT_LDO_RF_RST ( BIT(4) ) +#define BIT_DCDC_MEM_RST ( BIT(3) ) +#define BIT_DCDC_ARM_RST ( BIT(2) ) +#define BIT_DCDC_RST ( BIT(1) ) +#define BIT_BG_RST ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_PD_CTRL0 */ +#define BIT_LDO_BP_CAMMOT_RST ( BIT(15) ) +#define BIT_LDO_BPCAMMOT ( BIT(14) ) +#define BIT_LDO_BPCAMA_RST ( BIT(13) ) +#define BIT_LDO_BPCAMA ( BIT(12) ) +#define BIT_LDO_BPCAMIO_RST ( BIT(11) ) +#define BIT_LDO_BPCAMIO ( BIT(10) ) +#define BIT_LDO_BPCAMCORE_RST ( BIT(9) ) +#define BIT_LDO_BPCAMCORE ( BIT(8) ) +#define BIT_LDO_BPSIM1_RST ( BIT(7) ) +#define BIT_LDO_BPSIM1 ( BIT(6) ) +#define BIT_LDO_BPSIM0_RST ( BIT(5) ) +#define BIT_LDO_BPSIM0 ( BIT(4) ) +#define BIT_LDO_BPUSB_RST ( BIT(1) ) +#define BIT_LDO_BPUSB ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_PD_CTRL1 */ +#define BIT_LDO_BPCMMB1V2_RST ( BIT(13) ) +#define BIT_LDO_BPCMMB1V2 ( BIT(12) ) +#define BIT_LDO_BPCMMB1P8_RST ( BIT(11) ) +#define BIT_LDO_BPCMMB1P8 ( BIT(10) ) +#define BIT_LDO_BPVDD3V_RST ( BIT(7) ) +#define BIT_LDO_BPVDD3V ( BIT(6) ) +#define BIT_LDO_BPSD3_RST ( BIT(5) ) +#define BIT_LDO_BPSD3 ( BIT(4) ) +#define BIT_LDO_BPSD1_RST ( BIT(3) ) +#define BIT_LDO_BPSD1 ( BIT(2) ) +#define BIT_LDO_BPSD0_RST ( BIT(1) ) +#define BIT_LDO_BPSD0 ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_VCTRL0 */ +#define BITS_LDO_AVDDBB_VCTL(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_RF_VCTL(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_LDO_RTC_VCTL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_VCTRL1 */ +#define BITS_LDO_USB_VCTL(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_VDD3V_VCTL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_LDO_SIM1_VCTL(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_LDO_SIM0_VCTL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_VCTRL2 */ +#define BITS_LDO_CAMMOT_VCTL(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_CAMA_VCTL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_LDO_CAMIO_VCTL(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_LDO_CAMCORE_VCTL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_VCTRL3 */ +#define BITS_LDO_SD0_VCTL(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_VDD25_VCTL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_LDO_VDD18_VCTL(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_LDO_VDD28_VCTL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_VCTRL4 */ +#define BITS_LDO_CMMB1V2_VCTL(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_CMMB1P8_VCTL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_LDO_SD3_VCTL(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_LDO_SD1_VCTL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SLP_CTRL0 */ +#define BIT_LDOSD3_BP_EN ( BIT(15) ) +#define BIT_LDOSD1_BP_EN ( BIT(14) ) +#define BIT_LDOVDD25_BP_EN ( BIT(13) ) +#define BIT_LDOVDD18_BP_EN ( BIT(12) ) +#define BIT_LDOVDD28_BP_EN ( BIT(11) ) +#define BIT_LDOVAVDDBB_BP_EN ( BIT(10) ) +#define BIT_LDOSD0_BP_EN ( BIT(9) ) +#define BIT_LDOCAMMOT_BP_EN ( BIT(8) ) +#define BIT_LDOCAMA_BP_EN ( BIT(7) ) +#define BIT_LDOCAMIO_BP_EN ( BIT(6) ) +#define BIT_LDOCAMCORE_BP_EN ( BIT(5) ) +#define BIT_LDOUSB_BP_EN ( BIT(4) ) +#define BIT_LDOSIM1_BP_EN ( BIT(3) ) +#define BIT_LDOSIM0_BP_EN ( BIT(2) ) +#define BIT_LDORF_BP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SLP_CTRL1 */ +#define BIT_FSM_SLPPD_EN ( BIT(15) ) +#define BIT_SLP_AUDIO_AUXMICBIAS_PD_EN ( BIT(12) ) +#define BIT_SLP_AUDIO_MICBIAS_PD_EN ( BIT(11) ) +#define BIT_SLP_AUDIO_VBO_PD_EN ( BIT(10) ) +#define BIT_SLP_AUDIO_VB_PD_EN ( BIT(9) ) +#define BIT_SLP_AUDIO_BG_IBIAS_PD_EN ( BIT(8) ) +#define BIT_SLP_AUDIO_BG_PD_EN ( BIT(7) ) +#define BIT_SLP_AUDIO_VCMBUF_PD_EN ( BIT(6) ) +#define BIT_SLP_AUDIO_VCM_PD_EN ( BIT(5) ) +#define BIT_DCDC_ARM_BP_EN ( BIT(4) ) +#define BIT_LDOCMMB1P8_BP_EN ( BIT(3) ) +#define BIT_LDOCMMB1V2_BP_EN ( BIT(2) ) +#define BIT_LDOVDD3V_BP_EN ( BIT(1) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SLP_CTRL2 */ +#define BITS_ARMDCDC_ISO_ON_NUM(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_ARMDCDC_ISO_OFF_NUM(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SLP_CTRL3 */ +#define BITS_ARMDCDC_PWR_ON_DLY(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL0 */ +#define BIT_DCDC_FRECUT_RST ( BIT(15) ) +#define BIT_DCDC_FRECUT ( BIT(14) ) +#define BIT_DCDC_PFM_RST ( BIT(13) ) +#define BIT_DCDC_PFM ( BIT(12) ) +#define BIT_DCDC_DCM_RST ( BIT(11) ) +#define BIT_DCDC_DCM ( BIT(10) ) +#define BIT_DCDC_DEDT_EN_RST ( BIT(9) ) +#define BIT_DCDC_DEDT_EN ( BIT(8) ) +#define BITS_DCDC_CTL_40NM_RST(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BITS_DCDC_CTL_40NM(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL1 */ +#define BITS_DCDC_PDRSLOW_RST(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DCDC_PDRSLOW(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BIT_DCDC_CL_CTRL_RST ( BIT(7) ) +#define BIT_DCDC_CL_CTRL ( BIT(6) ) +#define BIT_DCDC_BP_LP_EN_RST ( BIT(5) ) +#define BIT_DCDC_BP_LP_EN ( BIT(4) ) +#define BIT_DCDC_OSCSYCEN_SW ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL2 */ +#define BIT_DCDC_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BITS_DCDC_RESERVER_RST(_x_) ( (_x_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_DCDC_RESERVER(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL_DS */ +#define BITS_DCDC_LVL_DLY(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DCDC_CTL_40NM_DS_RST(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BITS_DCDC_CTL_40NM_DS(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL_CAL */ +#define BITS_DCDC_CAL_RST(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BITS_DCDC_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_PLL_CTRL */ +#define BIT_APLL_MN_WE ( BIT(3) ) +#define BIT_APLL_PD_EN ( BIT(2) ) +#define BIT_APLL_FORECE_PD ( BIT(1) ) +#define BIT_APLL_FORECE_PD_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_APLLMN */ +#define BITS_APLLM(_x_) ( (_x_) << 11 & (BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_APLLN(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register ANA_REG_GLB_APLLWAIT */ +#define BITS_APLLWAIT(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_RTC_CTRL */ +#define BITS_VBATBK_RES(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_VBATBK_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_32K_START_CUR(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_BUF26M_CTRL */ +#define BIT_CLK26M_NORMAL_EN ( BIT(15) ) +#define BIT_SINDRV_ENA_SQUARE ( BIT(3) ) +#define BIT_SINDRV_ENA ( BIT(2) ) +#define BITS_SINDRV_LVL(_x_) ( (_x_) << 1 & (BIT(1)|BIT(2)) ) +#define BIT_CLIP_MODE ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL0 */ +#define BIT_RECHG ( BIT(12) ) +#define BIT_CHGR_PWM_EN_RST ( BIT(11) ) +#define BIT_CHGR_PWM_EN ( BIT(10) ) +#define BIT_CHGR_CC_EN_RST ( BIT(1) ) +#define BIT_CHGR_CC_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL1 */ +#define BITS_CHGR_RTCCTL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_CHGR_CTL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LED_CTRL */ +#define BIT_KPLED_PD_RST ( BIT(12) ) +#define BIT_KPLED_PD ( BIT(11) ) +#define BITS_KPLED_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BIT_WHTLED_PD_RST ( BIT(6) ) +#define BIT_WHTLED_PD ( BIT(5) ) +#define BITS_WHTLED_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_VIBRATOR_CTRL0 */ +#define BITS_VIBR_STABLE_V_B(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_VIBR_INIT_V_A(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_VIBR_V_BP(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_VIBR_PD_RST ( BIT(3) ) +#define BIT_VIBR_PD ( BIT(2) ) +#define BIT_VIBR_BD_EN ( BIT(1) ) +#define BIT_RTC_VIBR_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_VIBRATOR_CTRL1 */ +#define BITS_VIBR_CONVERT_V_COUNT(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_ARM_AUD_CLK_RST */ +#define BIT_AUD_ARM_ACC ( BIT(15) ) +#define BIT_AUDRX_ARM_SOFT_RST ( BIT(10) ) +#define BIT_AUDTX_ARM_SOFT_RST ( BIT(9) ) +#define BIT_AUD_ARM_SOFT_RST ( BIT(8) ) +#define BIT_AUD6M5_CLK_RX_INV_ARM_ENN ( BIT(7) ) +#define BIT_AUD6M5_CLK_TX_INV_ARM_EN ( BIT(6) ) +#define BIT_AUDIF_CLK_RX_INV_ARM_EN ( BIT(5) ) +#define BIT_AUDIF_CLK_TXT_INV_ARM_EN ( BIT(4) ) +#define BIT_CLK_AUD_6M5_ARM_EN ( BIT(3) ) +#define BIT_CLK_AUDIF_ARM_EN ( BIT(2) ) +#define BIT_RTC_AUD_ARM_EN ( BIT(1) ) +#define BIT_AUD_ARM_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_ANA_MIXED_CTRL */ +#define BIT_PTEST_PD_SET ( BIT(15) ) +#define BITS_UVHO_T_RST(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_UVHO_T(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_VIBR_PWR_ERR_CLR ( BIT(7) ) +#define BIT_CLKBT_EN ( BIT(6) ) +#define BITS_CLK_26M_REGS0(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BIT_UVHO_EN_RST ( BIT(3) ) +#define BIT_UVHO_EN ( BIT(2) ) +#define BIT_OTP_EN_RST ( BIT(1) ) +#define BIT_OTP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_ANA_STATUS */ +#define BIT_VIBR_PWR_ERR ( BIT(15) ) +#define BIT_ANA_BONDOPT2 ( BIT(10) ) +#define BIT_STS_VIBR_PD ( BIT(9) ) +#define BIT_STS_WHTLED_PD ( BIT(8) ) +#define BITS_PA_OCP_FLAG(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_PA_OTP_OTP(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BIT_CHGR_ON ( BIT(3) ) +#define BIT_CHGR_STDBY ( BIT(2) ) +#define BIT_ANA_BONDOPT1 ( BIT(1) ) +#define BIT_ANA_BONDOPT0 ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_RST_STATUS */ +#define BITS_ALL_HRST_MON(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_POR_HRST_MON(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_WDG_HRST_MON(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register ANA_REG_GLB_MCU_WR_PROT */ +#define BITS_MCU_WR_PROT(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_VIBR_WR_PROT */ +#define BITS_VIBR_WR_PROT(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_HWRST_RTC */ +#define BITS_HWRST_RTC_REG(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_HWRST_RTC_SET(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_DCDCOTP_CTRL */ +#define BITS_DCDC_OTP_OPTION(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BIT_DCDC_OTP_INT_CLR ( BIT(13) ) +#define BIT_DCDC_OPT_STS_RTC ( BIT(12) ) +#define BIT_DCDC_OTP_EN_RST ( BIT(9) ) +#define BIT_DCDC_OTP_EN ( BIT(8) ) +#define BITS_DCDC_OTP_S_RST(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DCDC_OTP_S(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)) ) +#define BIT_DCDC_OTP_VBEOP_RST ( BIT(1) ) +#define BIT_DCDC_OTP_VBEOP ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_POR_SRC_STAT */ +#define BIT_POR_PBCHGR_MASK_SET ( BIT(15) ) +#define BIT_EXT_RSTN_FLAG ( BIT(10) ) +#define BIT_CHGR_INT_FLAG ( BIT(9) ) +#define BIT_PB_INT2_FLAG ( BIT(8) ) +#define BIT_PB_INT_FLAG ( BIT(7) ) +#define BIT_ALARM_INT_SET ( BIT(6) ) +#define BIT_CHGR_INT_1S_SET ( BIT(5) ) +#define BIT_CHGR_INT_DEBC ( BIT(4) ) +#define BIT_PB_INT2_1S_SET ( BIT(3) ) +#define BIT_PB_INT2_DEBC ( BIT(2) ) +#define BIT_PB_INT_1S_SET ( BIT(1) ) +#define BIT_PB_INT_DEBC ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_POR_SRC_FLAG_CLR */ +#define BIT_EXT_RSTN_FLAG_RST ( BIT(3) ) +#define BIT_CHGR_INT_FLAG_RST ( BIT(2) ) +#define BIT_PBINT2_FLAG_RST ( BIT(1) ) +#define BIT_PBINT_FLAG_RST ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_HW_REBOOT_CTRL */ +#define BIT_PBINT_HW_PD_EN ( BIT(8) ) +#define BIT_PBINT_6S_FLAG_CLR ( BIT(7) ) +#define BIT_PBINT_6S_FLAG ( BIT(6) ) +#define BITS_PBINT_HW_PD_THRESHOLD_RST(_x_)( (_x_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_PBINT_HW_PD_THRESHOLD_SET(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register ANA_REG_GLB_DCDCARM_CTRL0 */ +#define BIT_DCDCARM_FRECUT_RST ( BIT(15) ) +#define BIT_DCDCARM_FRECUT ( BIT(14) ) +#define BIT_DCDCARM_PFM_RST ( BIT(13) ) +#define BIT_DCDCARM_PFM ( BIT(12) ) +#define BIT_DCDCARM_DCM_RST ( BIT(11) ) +#define BIT_DCDCARM_DCM ( BIT(10) ) +#define BIT_DCDCARM_DEDT_EN_RST ( BIT(9) ) +#define BIT_DCDCARM_DEDT_EN ( BIT(8) ) +#define BITS_DCDCARM_CTL_RST(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BITS_DCDCARM_CTL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register ANA_REG_GLB_DCDCARM_CTRL1 */ +#define BITS_DCDCARM_PDRSLOW_RST(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DCDCARM_PDRSLOW(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BIT_DCDCARM_CL_CTRL_RST ( BIT(7) ) +#define BIT_DCDCARM_CL_CTRL ( BIT(6) ) +#define BIT_DCDCARM_OSCSYCEN_SW ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDCARM_CTRL2 */ +#define BIT_DCDCARM_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDCARM_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDCARM_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BITS_DCDCARM_RESERVER_RST(_x_) ( (_x_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_DCDCARM_RESERVER(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register ANA_REG_GLB_DCDCARM_CTRL_CAL */ +#define BITS_DCDCARM_CAL_RST(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BITS_DCDCARM_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDCMEM_CTRL0 */ +#define BIT_DCDCMEM_FRECUT_RST ( BIT(15) ) +#define BIT_DCDCMEM_FRECUT ( BIT(14) ) +#define BIT_DCDCMEM_PFM_RST ( BIT(13) ) +#define BIT_DCDCMEM_PFM ( BIT(12) ) +#define BIT_DCDCMEM_DCM_RST ( BIT(11) ) +#define BIT_DCDCMEM_DCM ( BIT(10) ) +#define BIT_DCDCMEM_DEDT_EN_RST ( BIT(9) ) +#define BIT_DCDCMEM_DEDT_EN ( BIT(8) ) +#define BITS_DCDCMEM_CTL_40NM_RST(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_DCDCMEM_CTL_40NM(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDCMEM_CTRL1 */ +#define BITS_DCDCMEM_PDRSLOW_RST(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DCDCMEM_PDRSLOW(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BIT_DCDCMEM_CL_CTRL_RST ( BIT(7) ) +#define BIT_DCDCMEM_CL_CTRL ( BIT(6) ) +#define BIT_DCDCMEM_OSCSYCEN_SW ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDCMEM_CTRL2 */ +#define BIT_DCDCMEM_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDCMEM_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDCMEM_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BITS_DCDCMEM_RESERVER_RST(_x_) ( (_x_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_DCDCMEM_RESERVER(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register ANA_REG_GLB_DCDCMEM_CTRL_CAL */ +#define BITS_DCDCMEM_CAL_RST(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BITS_DCDCMEM_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DDR2_BUF_CTRL0_DS */ +#define BITS_DDR2_BUF_CHNS_DS_RST(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DDR2_BUF_CHNS_DS(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_DDR2_BUF_CHNS_RST(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_DDR2_BUF_CHNS(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_DDR2_BUF_S_DS_RST(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_DDR2_BUF_S_DS(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_DDR2_BUF_S_RST(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DDR2_BUF_S(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DDR2_BUF_CTRL1_DS */ +#define BIT_DDR2_BUF_PD_HW_RST ( BIT(3) ) +#define BIT_DDR2_BUF_PD_HW ( BIT(2) ) +#define BIT_DDR2_BUF_PD_RST ( BIT(1) ) +#define BIT_DDR2_BUF_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_EFS_PROT */ +/* write 16hC686 will set ana_efs_prot to 1; write other value will reset ana_efs_prot to 0. + */ +#define BITS_ANA_WFS_WD(_x_) ( (_x_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ANA_EFS_PROT ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_EFS_CTRL */ +#define BIT_EFS_2P5V_PWR_ON ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDCLDO_CTRL0 */ +#define BIT_DCDCLDO_FRECUT_RST ( BIT(15) ) +#define BIT_DCDCLDO_FRECUT ( BIT(14) ) +#define BIT_DCDCLDO_PFM_RST ( BIT(13) ) +#define BIT_DCDCLDO_PFM ( BIT(12) ) +#define BIT_DCDCLDO_DCM_RST ( BIT(11) ) +#define BIT_DCDCLDO_DCM ( BIT(10) ) +#define BIT_DCDCLDO_DEDT_EN_RST ( BIT(9) ) +#define BIT_DCDCLDO_DEDT_EN ( BIT(8) ) +#define BITS_DCDCLDO_CTL_RST(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BITS_DCDCLDO_CTL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register ANA_REG_GLB_DCDCLDO_CTRL1 */ +#define BITS_DCDCLDO_PDRSLOW_RST(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DCDCLDO_PDRSLOW(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BIT_DCDCLDO_CL_CTRL_RST ( BIT(7) ) +#define BIT_DCDCLDO_CL_CTRL ( BIT(6) ) +#define BIT_DCDCLDO_OSCSYCEN_SW ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDCLDO_CTRL2 */ +#define BIT_DCDCLDO_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDCLDO_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDCLDO_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BITS_DCDCLDO_RESERVER_RST(_x_) ( (_x_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_DCDCLDO_RESERVER(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register ANA_REG_GLB_DCDCLDO_CTRL_CAL */ +#define BITS_DCDCLDO_CAL_RST(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BITS_DCDCLDO_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_AFUSE_CTRL */ +/* prot key is 8ha2, it must write with rd_dly value + */ +#define BITS_AFUSE_RD_DLY_PROT(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +/* Software write 1 to this bit to issue an afuse read request, + * and polling this bit, it will be cleared to 0 when afuse_out data successfully sampled + * into AFUSE_OUT_LOW and HIGH register in the following. + */ +#define BIT_AFUSE_RD_REQ ( BIT(7) ) +#define BITS_AFUSE_RD_DLY(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) + +#define SHFT_AFUSE_RD_DLY ( 0 ) +#define MASK_AFUSE_RD_DLY ( BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6) ) + +/* bits definitions for register ANA_REG_GLB_AFUSE_OUT_LOW */ +#define BITS_AFUSE_OUT_LOW(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_AFUSE_OUT_HIGH */ +#define BITS_AFUSE_OUT_HIGH(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_CHIP_ID_LOW */ +#define BITS_CHIP_ID_LOW(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_CHIP_ID_HIGH */ +#define BITS_CHIP_ID_HIGH(_x_) ( (_x_) << 0 ) + +/* vars definitions for controller ANA_REGS_GLB */ +#define KEY_EFS_PROT ( 0xc686UL ) +#define KEY_RD_DLY ( 0xa2UL ) + +#endif //__ANA_REGS_GLB_H__ diff --git a/include/soc/sprd/__regs_ana_glb2.h b/include/soc/sprd/__regs_ana_glb2.h new file mode 100644 index 00000000..861e4630 --- /dev/null +++ b/include/soc/sprd/__regs_ana_glb2.h @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __ANA_REGS_GLB2_H__ +#define __ANA_REGS_GLB2_H__ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, include <mach/sci_glb_regs.h>" +#endif + +#define ANA_REGS_GLB2 + +/* registers definitions for controller ANA_REGS_GLB2 */ +#define ANA_REG_GLB2_LDO_TRIM0 SCI_ADDR(ANA_REGS_GLB2_BASE, 0x0000) +#define ANA_REG_GLB2_LDO_TRIM1 SCI_ADDR(ANA_REGS_GLB2_BASE, 0x0004) +#define ANA_REG_GLB2_LDO_TRIM2 SCI_ADDR(ANA_REGS_GLB2_BASE, 0x0008) +#define ANA_REG_GLB2_LDO_TRIM3 SCI_ADDR(ANA_REGS_GLB2_BASE, 0x000c) +#define ANA_REG_GLB2_LDO_TRIM4 SCI_ADDR(ANA_REGS_GLB2_BASE, 0x0010) +#define ANA_REG_GLB2_LDO_TRIM5 SCI_ADDR(ANA_REGS_GLB2_BASE, 0x0014) +#define ANA_REG_GLB2_LDO_TRIM6 SCI_ADDR(ANA_REGS_GLB2_BASE, 0x0018) +#define ANA_REG_GLB2_LDO_TRIM7 SCI_ADDR(ANA_REGS_GLB2_BASE, 0x001c) +#define ANA_REG_GLB2_LDO_TRIM8 SCI_ADDR(ANA_REGS_GLB2_BASE, 0x0020) +#define ANA_REG_GLB2_LDO_TRIM_SEL SCI_ADDR(ANA_REGS_GLB2_BASE, 0x0024) + +/* bits definitions for register ANA_REG_GLB2_LDO_TRIM0 */ +#define BITS_TRIM_VDD18(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BITS_TRIM_VDD28(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB2_LDO_TRIM1 */ +#define BITS_TRIM_VDD25(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BITS_TRIM_VDD3V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB2_LDO_TRIM2 */ +#define BITS_TRIM_DVDD18(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BITS_TRIM_SD0(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB2_LDO_TRIM3 */ +#define BITS_TRIM_SD1(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BITS_TRIM_SD3(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB2_LDO_TRIM4 */ +#define BITS_TRIM_VSIM(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BITS_TRIM_USB(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB2_LDO_TRIM5 */ +#define BITS_TRIM_RF(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BITS_TRIM_ABB(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB2_LDO_TRIM6 */ +#define BITS_TRIM_CAMA(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BITS_TRIM_CAMCORE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB2_LDO_TRIM7 */ +#define BITS_TRIM_CAMIO(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BITS_TRIM_CAMMOT(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB2_LDO_TRIM8 */ +#define BITS_TRIM_CMMB1V2(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BITS_TRIM_CMMB1V8(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB2_LDO_TRIM_SEL */ +#define BITS_LDO_RF_CAL_EN(_x_) ( (_x_) & (BIT(0)) ) +#define BITS_LDO_ABB_CAL_EN(_x_) ( (_x_) & (BIT(1)) ) +#define BITS_LDO_CAMA_CAL_EN(_x_) ( (_x_) & (BIT(0)|BIT(1)) ) +#define BITS_LDO_VDD3V_CAL_EN(_x_) ( (_x_) & (BIT(5)) ) +#define BITS_LDO_VDD28_CAL_EN(_x_) ( (_x_) & (BIT(2)|BIT(5)) ) +#define BITS_LDO_VSIM_CAL_EN(_x_) ( (_x_) & (BIT(3)|BIT(5)) ) +#define BITS_LDO_CAMMOT_CAL_EN(_x_) ( (_x_) & (BIT(2)|BIT(3)|BIT(5)) ) +#define BITS_LDO_SD0_CAL_EN(_x_) ( (_x_) & (BIT(4)|BIT(5)) ) +#define BITS_LDO_USB_CAL_EN(_x_) ( (_x_) & (BIT(2)|BIT(4)|BIT(5)) ) +#define BITS_LDO_DVDD18_CAL_EN(_x_) ( (_x_) & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_LDO_VDD25_CAL_EN(_x_) ( (_x_) & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_LDO_CAMIO_CAL_EN(_x_) ( (_x_) & (BIT(6)) ) +#define BITS_LDO_CAMCORE_CAL_EN(_x_) ( (_x_) & (BIT(7)) ) +#define BITS_LDO_CMMB1P2_CAL_EN(_x_) ( (_x_) & (BIT(6)|BIT(7)) ) +#define BITS_LDO_CMMB1P8_CAL_EN(_x_) ( (_x_) & (BIT(8)) ) +#define BITS_LDO_VDD18_CAL_EN(_x_) ( (_x_) & (BIT(6)|BIT(8)) ) +#define BITS_LDO_SD1_CAL_EN(_x_) ( (_x_) & (BIT(7)|BIT(8)) ) +#define BITS_LDO_SD3_CAL_EN(_x_) ( (_x_) & (BIT(6)|BIT(7)|BIT(8)) ) + +/* vars definitions for controller ANA_REGS_GLB2 */ + +#endif //__ANA_REGS_GLB2_H__ diff --git a/include/soc/sprd/__regs_emc.h b/include/soc/sprd/__regs_emc.h new file mode 100644 index 00000000..b183bd18 --- /dev/null +++ b/include/soc/sprd/__regs_emc.h @@ -0,0 +1,159 @@ +#ifndef REGS_EMC_H_
+#define REGS_EMC_H_
+
+#ifndef __SCI_GLB_REGS_H__
+#error "Don't include this file directly, include <mach/sci_glb_regs.h>"
+#endif
+
+#define UMCTL_CFG_ADD_SCFG 0x000
+#define UMCTL_CFG_ADD_SCTL 0x004//moves the uPCTL from one state to another
+#define UMCTL_CFG_ADD_STAT 0x008//provides information about the current state of the uPCTL
+#define UMCTL_CFG_ADD_MCMD 0x040
+#define UMCTL_CFG_ADD_POWCTL 0x044
+#define UMCTL_CFG_ADD_POWSTAT 0x048
+#define UMCTL_CFG_ADD_MCFG1 0x07C
+#define UMCTL_CFG_ADD_MCFG 0x080
+#define UMCTL_CFG_ADD_PPCFG 0x084
+#define UMCTL_CFG_ADD_TOGCNT1U 0x0c0
+#define UMCTL_CFG_ADD_TINIT 0x0c4
+#define UMCTL_CFG_ADD_TRSTH 0x0c8
+#define UMCTL_CFG_ADD_TOGCNT100N 0x0cc
+#define UMCTL_CFG_ADD_TREFI 0x0d0
+#define UMCTL_CFG_ADD_TMRD 0x0d4
+#define UMCTL_CFG_ADD_TRFC 0x0d8
+#define UMCTL_CFG_ADD_TRP 0x0dc
+#define UMCTL_CFG_ADD_TRTW 0x0e0
+#define UMCTL_CFG_ADD_TAL 0x0e4
+#define UMCTL_CFG_ADD_TCL 0x0e8
+#define UMCTL_CFG_ADD_TCWL 0x0ec
+#define UMCTL_CFG_ADD_TRAS 0x0f0
+#define UMCTL_CFG_ADD_TRC 0x0f4
+#define UMCTL_CFG_ADD_TRCD 0x0f8
+#define UMCTL_CFG_ADD_TRRD 0x0fc
+#define UMCTL_CFG_ADD_TRTP 0x100
+#define UMCTL_CFG_ADD_TWR 0x104
+#define UMCTL_CFG_ADD_TWTR 0x108
+#define UMCTL_CFG_ADD_TEXSR 0x10c
+#define UMCTL_CFG_ADD_TXP 0x110
+#define UMCTL_CFG_ADD_TXPDLL 0x114
+#define UMCTL_CFG_ADD_TZQCS 0x118
+#define UMCTL_CFG_ADD_TZQCSI 0x11C
+#define UMCTL_CFG_ADD_TDQS 0x120
+#define UMCTL_CFG_ADD_TCKSRE 0x124
+#define UMCTL_CFG_ADD_TCKSRX 0x128
+#define UMCTL_CFG_ADD_TCKE 0x12c
+#define UMCTL_CFG_ADD_TMOD 0x130
+#define UMCTL_CFG_ADD_TRSTL 0x134
+#define UMCTL_CFG_ADD_TZQCL 0x138
+#define UMCTL_CFG_ADD_TCKESR 0x13c
+#define UMCTL_CFG_ADD_TDPD 0x140
+#define UMCTL_CFG_ADD_DTUWACTL 0x200
+#define UMCTL_CFG_ADD_DTURACTL 0x204
+#define UMCTL_CFG_ADD_DTUCFG 0x208
+#define UMCTL_CFG_ADD_DTUECTL 0x20C
+#define UMCTL_CFG_ADD_DTUWD0 0x210
+#define UMCTL_CFG_ADD_DTUWD1 0x214
+#define UMCTL_CFG_ADD_DTUWD2 0x218
+#define UMCTL_CFG_ADD_DTUWD3 0x21c
+#define UMCTL_CFG_ADD_DTURD0 0x224
+#define UMCTL_CFG_ADD_DTURD1 0x228
+#define UMCTL_CFG_ADD_DTURD2 0x22C
+#define UMCTL_CFG_ADD_DTURD3 0x230
+#define UMCTL_CFG_ADD_DFITPHYWRDATA 0x250
+#define UMCTL_CFG_ADD_DFITPHYWRLAT 0x254
+#define UMCTL_CFG_ADD_DFITRDDATAEN 0x260
+#define UMCTL_CFG_ADD_DFITPHYRDLAT 0x264
+#define UMCTL_CFG_ADD_DFISTSTAT0 0x2c0
+#define UMCTL_CFG_ADD_DFISTCFG0 0x2c4
+#define UMCTL_CFG_ADD_DFISTCFG1 0x2c8
+#define UMCTL_CFG_ADD_DFISTCFG2 0x2d8
+#define UMCTL_CFG_ADD_DFILPCFG0 0x2f0
+#define UMCTL_CFG_ADD_PCFG_0 0x400
+#define UMCTL_CFG_ADD_PCFG_1 0x404
+#define UMCTL_CFG_ADD_PCFG_2 0x408
+#define UMCTL_CFG_ADD_PCFG_3 0x40c
+#define UMCTL_CFG_ADD_PCFG_4 0x410
+#define UMCTL_CFG_ADD_PCFG_5 0x414
+#define UMCTL_CFG_ADD_PCFG_6 0x418
+#define UMCTL_CFG_ADD_PCFG_7 0x41c
+#define UMCTL_CFG_ADD_DCFG_CS0 0x484
+#define UMCTL_CFG_ADD_DCFG_CS1 0x494
+//}}}
+
+//publ configure registers declaration.//{{{
+//copied from PUBL FPGA cfg module. here shift them(<< 2)
+#define PUBL_CFG_ADD_RIDR (0x00 * 4) // R - Revision Identification Register
+#define PUBL_CFG_ADD_PIR (0x01 * 4) // R/W - PHY Initialization Register
+#define PUBL_CFG_ADD_PGCR (0x02 * 4) // R/W - PHY General Configuration Register
+#define PUBL_CFG_ADD_PGSR (0x03 * 4) // R - PHY General Status Register
+#define PUBL_CFG_ADD_DLLGCR (0x04 * 4) // R/W - DLL General Control Register
+#define PUBL_CFG_ADD_ACDLLCR (0x05 * 4) // R/W - AC DLL Control Register
+#define PUBL_CFG_ADD_PTR0 (0x06 * 4) // R/W - PHY Timing Register 0
+#define PUBL_CFG_ADD_PTR1 (0x07 * 4) // R/W - PHY Timing Register 1
+#define PUBL_CFG_ADD_PTR2 (0x08 * 4) // R/W - PHY Timing Register 2
+#define PUBL_CFG_ADD_ACIOCR (0x09 * 4) // R/W - AC I/O Configuration Register
+#define PUBL_CFG_ADD_DXCCR (0x0A * 4) // R/W - DATX8 I/O Configuration Register
+#define PUBL_CFG_ADD_DSGCR (0x0B * 4) // R/W - DFI Configuration Register
+#define PUBL_CFG_ADD_DCR (0x0C * 4) // R/W - DRAM Configuration Register
+#define PUBL_CFG_ADD_DTPR0 (0x0D * 4) // R/W - SDRAM Timing Parameters Register 0
+#define PUBL_CFG_ADD_DTPR1 (0x0E * 4) // R/W - SDRAM Timing Parameters Register 1
+#define PUBL_CFG_ADD_DTPR2 (0x0F * 4) // R/W - SDRAM Timing Parameters Register 2
+#define PUBL_CFG_ADD_MR0 (0x10 * 4) // R/W - Mode Register
+#define PUBL_CFG_ADD_MR1 (0x11 * 4) // R/W - Ext}ed Mode Register
+#define PUBL_CFG_ADD_MR2 (0x12 * 4) // R/W - Ext}ed Mode Register 2
+#define PUBL_CFG_ADD_MR3 (0x13 * 4) // R/W - Ext}ed Mode Register 3
+#define PUBL_CFG_ADD_ODTCR (0x14 * 4) // R/W - ODT Configuration Register
+#define PUBL_CFG_ADD_DTAR (0x15 * 4) // R/W - Data Training Address Register
+#define PUBL_CFG_ADD_DTDR0 (0x16 * 4) // R/W - Data Training Data Register 0
+#define PUBL_CFG_ADD_DTDR1 (0x17 * 4) // R/W - Data Training Data Register 1
+#define PUBL_CFG_ADD_DCUAR (0x30 * 4) // R/W - DCU Address Register
+#define PUBL_CFG_ADD_DCUDR (0x31 * 4) // R/W - DCU Data Register
+#define PUBL_CFG_ADD_DCURR (0x32 * 4) // R/W - DCU Run Register
+#define PUBL_CFG_ADD_DCUSR0 (0x36 * 4) // R/W - DCU status register
+#define PUBL_CFG_ADD_BISTRR (0x40 * 4) // R/W - BIST run register
+#define PUBL_CFG_ADD_BISTMSKR0 (0x41 * 4) // R/W - BIST Mask Register 0
+#define PUBL_CFG_ADD_BISTMSKR1 (0x42 * 4) // R/W - BIST Mask Register 1
+#define PUBL_CFG_ADD_BISTWCR (0x43 * 4) // R/W - BIST Word Count Register
+#define PUBL_CFG_ADD_BISTLSR (0x44 * 4) // R/W - BIST LFSR Seed Register
+#define PUBL_CFG_ADD_BISTAR0 (0x45 * 4) // R/W - BIST Address Register 0
+#define PUBL_CFG_ADD_BISTAR1 (0x46 * 4) // R/W - BIST Address Register 1
+#define PUBL_CFG_ADD_BISTAR2 (0x47 * 4) // R/W - BIST Address Register 2
+#define PUBL_CFG_ADD_BISTUDPR (0x48 * 4) // R/W - BIST User Data Pattern Register
+#define PUBL_CFG_ADD_BISTGSR (0x49 * 4) // R/W - BIST General Status Register
+#define PUBL_CFG_ADD_BISTWER (0x4a * 4) // R/W - BIST Word Error Register
+#define PUBL_CFG_ADD_BISTBER0 (0x4b * 4) // R/W - BIST Bit Error Register 0
+#define PUBL_CFG_ADD_BISTBER1 (0x4c * 4) // R/W - BIST Bit Error Register 1
+#define PUBL_CFG_ADD_BISTBER2 (0x4d * 4) // R/W - BIST Bit Error Register 2
+#define PUBL_CFG_ADD_BISTWCSR (0x4e * 4) // R/W - BIST Word Count Status Register
+#define PUBL_CFG_ADD_BISTFWR0 (0x4f * 4) // R/W - BIST Fail Word Register 0
+#define PUBL_CFG_ADD_BISTFWR1 (0x50 * 4) // R/W - BIST Fail Word Register 1
+#define PUBL_CFG_ADD_ZQ0CR0 (0x60 * 4) // R/W - ZQ 0 Impedance Control Register 0
+#define PUBL_CFG_ADD_ZQ0CR1 (0x61 * 4) // R/W - ZQ 1
+#define PUBL_CFG_ADD_DX0GCR (0x70 * 4) // R/W - DATX8 0 General Configuration Register
+#define PUBL_CFG_ADD_DX0GSR0 (0x71 * 4) // R - DATX8 0 General Status Register 0
+#define PUBL_CFG_ADD_DX0GSR1 (0x72 * 4) // R - DATX8 0 General Status Register 1
+#define PUBL_CFG_ADD_DX0DLLCR (0x73 * 4) // R - DATX8 0 DLL Control Register
+#define PUBL_CFG_ADD_DX0DQTR (0x74 * 4) // R - DATX8 0 DLL Control Register
+#define PUBL_CFG_ADD_DX0DQSTR (0x75 * 4) // R/W
+
+#define PUBL_CFG_ADD_DX1GCR (0x80 * 4) // R/W - DATX8 1 General Configuration Register
+#define PUBL_CFG_ADD_DX1GSR0 (0x81 * 4) // R - DATX8 1 General Status Register 0
+#define PUBL_CFG_ADD_DX1GSR1 (0x82 * 4) // R - DATX8 1 General Status Register 1
+#define PUBL_CFG_ADD_DX1DLLCR (0x83 * 4) // R - DATX8 1 DLL Control Register
+#define PUBL_CFG_ADD_DX1DQTR (0x84 * 4) // R - DATX8 1 DLL Control Register
+#define PUBL_CFG_ADD_DX1DQSTR (0x85 * 4) // R/W
+
+#define PUBL_CFG_ADD_DX2GCR (0x90 * 4) // R/W - DATX8 2 General Configuration Register
+#define PUBL_CFG_ADD_DX2GSR0 (0x91 * 4) // R - DATX8 2 General Status Register 0
+#define PUBL_CFG_ADD_DX2GSR1 (0x92 * 4) // R - DATX8 2 General Status Register 1
+#define PUBL_CFG_ADD_DX2DLLCR (0x93 * 4) // R - DATX8 2 DLL Control Register
+#define PUBL_CFG_ADD_DX2DQTR (0x94 * 4) // R - DATX8 2 DLL Control Register
+#define PUBL_CFG_ADD_DX2DQSTR (0x95 * 4) // R/W
+
+#define PUBL_CFG_ADD_DX3GCR (0xa0 * 4) // R/W - DATX8 3 General Configuration Register
+#define PUBL_CFG_ADD_DX3GSR0 (0xa1 * 4) // R - DATX8 3 General Status Register 0
+#define PUBL_CFG_ADD_DX3GSR1 (0xa2 * 4) // R - DATX8 3 General Status Register 1
+#define PUBL_CFG_ADD_DX3DLLCR (0xa3 * 4) // R - DATX8 3 DLL Control Register
+#define PUBL_CFG_ADD_DX3DQTR (0xa4 * 4) // R - DATX8 3 DLL Control Register
+#define PUBL_CFG_ADD_DX3DQSTR (0xa5 * 4) // R/W
+#endif
\ No newline at end of file diff --git a/include/soc/sprd/__regs_glb.h b/include/soc/sprd/__regs_glb.h new file mode 100644 index 00000000..47c272fe --- /dev/null +++ b/include/soc/sprd/__regs_glb.h @@ -0,0 +1,585 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __REGS_GLB_H__ +#define __REGS_GLB_H__ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, include <mach/sci_glb_regs.h>" +#endif + +#define REGS_GLB + +/* registers definitions for controller REGS_GLB */ +#define REG_GLB_MCU_SOFT_RST SCI_ADDR(REGS_GLB_BASE, 0x0004) +#define REG_GLB_GEN0 SCI_ADDR(REGS_GLB_BASE, 0x0008) +#define REG_GLB_PCTRL SCI_ADDR(REGS_GLB_BASE, 0x000c) +#define REG_GLB_GEN1 SCI_ADDR(REGS_GLB_BASE, 0x0018) +#define REG_GLB_GEN3 SCI_ADDR(REGS_GLB_BASE, 0x001c) +#define REG_GLB_HWRST SCI_ADDR(REGS_GLB_BASE, 0x0020) +#define REG_GLB_M_PLL_CTL0 SCI_ADDR(REGS_GLB_BASE, 0x0024) +#define REG_GLB_PINCTL SCI_ADDR(REGS_GLB_BASE, 0x0028) +#define REG_GLB_GEN2 SCI_ADDR(REGS_GLB_BASE, 0x002c) +#define REG_GLB_ARMBOOT SCI_ADDR(REGS_GLB_BASE, 0x0030) +#define REG_GLB_STC_DSP_ST SCI_ADDR(REGS_GLB_BASE, 0x0034) +#define REG_GLB_TD_PLL_CTL SCI_ADDR(REGS_GLB_BASE, 0x003c) +#define REG_GLB_D_PLL_CTL SCI_ADDR(REGS_GLB_BASE, 0x0040) +#define REG_GLB_BUSCLK SCI_ADDR(REGS_GLB_BASE, 0x0044) +#define REG_GLB_ARCH SCI_ADDR(REGS_GLB_BASE, 0x0048) +#define REG_GLB_SOFT_RST SCI_ADDR(REGS_GLB_BASE, 0x004c) +#define REG_GLB_G_PLL_CTL SCI_ADDR(REGS_GLB_BASE, 0x0050) +#define REG_GLB_NFCMEMDLY SCI_ADDR(REGS_GLB_BASE, 0x0058) +#define REG_GLB_CLKDLY SCI_ADDR(REGS_GLB_BASE, 0x005c) +#define REG_GLB_GEN4 SCI_ADDR(REGS_GLB_BASE, 0x0060) +#define REG_GLB_A_PLLMN SCI_ADDR(REGS_GLB_BASE, 0x0064) +#define REG_GLB_POWCTL0 SCI_ADDR(REGS_GLB_BASE, 0x0068) +#define REG_GLB_POWCTL1 SCI_ADDR(REGS_GLB_BASE, 0x006c) +#define REG_GLB_PLL_SCR SCI_ADDR(REGS_GLB_BASE, 0x0070) +#define REG_GLB_CLK_EN SCI_ADDR(REGS_GLB_BASE, 0x0074) +#define REG_GLB_CLK26M_ANA_CTL SCI_ADDR(REGS_GLB_BASE, 0x0078) +#define REG_GLB_CLK_GEN5 SCI_ADDR(REGS_GLB_BASE, 0x007c) +#define REG_GLB_DDR_PHY_RETENTION SCI_ADDR(REGS_GLB_BASE, 0x0080) +#define REG_GLB_MM_PWR_CTL SCI_ADDR(REGS_GLB_BASE, 0x0084) +#define REG_GLB_CEVA_L1RAM_PWR_CTL SCI_ADDR(REGS_GLB_BASE, 0x0088) +#define REG_GLB_GSM_PWR_CTL SCI_ADDR(REGS_GLB_BASE, 0x008c) +#define REG_GLB_TD_PWR_CTL SCI_ADDR(REGS_GLB_BASE, 0x0090) +#define REG_GLB_PERI_PWR_CTL SCI_ADDR(REGS_GLB_BASE, 0x0094) +#define REG_GLB_ARM_SYS_PWR_CTL SCI_ADDR(REGS_GLB_BASE, 0x009c) +#define REG_GLB_G3D_PWR_CTL SCI_ADDR(REGS_GLB_BASE, 0x00a0) +#define REG_GLB_CHIP_DSLEEP_STAT SCI_ADDR(REGS_GLB_BASE, 0x00a4) +#define REG_GLB_PWR_CTRL_NUM1 SCI_ADDR(REGS_GLB_BASE, 0x00a8) +#define REG_GLB_PWR_CTRL_NUM2 SCI_ADDR(REGS_GLB_BASE, 0x00ac) +#define REG_GLB_PWR_CTRL_NUM3 SCI_ADDR(REGS_GLB_BASE, 0x00b0) +#define REG_GLB_PWR_CTRL_NUM4 SCI_ADDR(REGS_GLB_BASE, 0x00b4) +#define REG_GLB_PWR_CTRL_NUM5 SCI_ADDR(REGS_GLB_BASE, 0x00b8) +#define REG_GLB_ARM9_SYS_PWR_CTL SCI_ADDR(REGS_GLB_BASE, 0x00bc) +#define REG_GLB_DMA_CTRL SCI_ADDR(REGS_GLB_BASE, 0x00c0) +#define REG_GLB_DMA_AP_CP_SEL SCI_ADDR(REGS_GLB_BASE, 0x00c4) +#define REG_GLB_SLEEP_INT_AP_SEL SCI_ADDR(REGS_GLB_BASE, 0x00c8) +#define REG_GLB_SLEEP_INT_CP_SEL SCI_ADDR(REGS_GLB_BASE, 0x00cc) +#define REG_GLB_TEST_CLK_CTRL SCI_ADDR(REGS_GLB_BASE, 0x00d0) +#define REG_GLB_TP_DLYC_LEN SCI_ADDR(REGS_GLB_BASE, 0x00d4) +#define REG_GLB_MIPI_PHY_CTRL SCI_ADDR(REGS_GLB_BASE, 0x00d8) +#define REG_GLB_BOND_OPTION SCI_ADDR(REGS_GLB_BASE, 0x0100) + +/* bits definitions for register REG_GLB_MCU_SOFT_RST */ +/* MCU soft reset the whole MCU sub-system, processor core, AHB and APB + * this bit will be self-cleared to zero after set + */ +#define BIT_MCU_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_GLB_GEN0 */ +#define BIT_IC3_EB ( BIT(31) ) +#define BIT_IC2_EB ( BIT(30) ) +#define BIT_IC1_EB ( BIT(29) ) +#define BIT_RTC_TMR_EB ( BIT(28) ) +#define BIT_RTC_SYST0_EB ( BIT(27) ) +#define BIT_RTC_KPD_EB ( BIT(26) ) +#define BIT_IIS1_EB ( BIT(25) ) +#define BIT_RTC_EIC_EB ( BIT(24) ) +#define BIT_UART2_EB ( BIT(22) ) +#define BIT_UART1_EB ( BIT(21) ) +#define BIT_UART0_EB ( BIT(20) ) +#define BIT_SYST0_EB ( BIT(19) ) +#define BIT_SPI1_EB ( BIT(18) ) +#define BIT_SPI0_EB ( BIT(17) ) +#define BIT_SIM1_EB ( BIT(16) ) +#define BIT_EPT_EB ( BIT(15) ) +#define BIT_CCIR_MCLK_EN ( BIT(14) ) +#define BIT_PINREG_EB ( BIT(13) ) +#define BIT_IIS0_EB ( BIT(12) ) +/* MCU soft reset DSP Z-bus Accelerators, it will be self-cleared to zero after set + */ +#define BIT_MCU_DSP_RST ( BIT(10) ) +#define BIT_EIC_EB ( BIT(9) ) +#define BIT_KPD_EB ( BIT(8) ) +#define BIT_EFUSE_EB ( BIT(7) ) +#define BIT_ADI_EB ( BIT(6) ) +#define BIT_GPIO_EB ( BIT(5) ) +#define BIT_I2C0_EB ( BIT(4) ) +#define BIT_SIM0_EB ( BIT(3) ) +#define BIT_TMR_EB ( BIT(2) ) +#define BIT_SPI2_EB ( BIT(1) ) +#define BIT_UART3_EB ( BIT(0) ) + +/* bits definitions for register REG_GLB_PCTRL */ +#define BIT_IIS0_CTL_SEL ( BIT(31) ) +#define BIT_IIS1_CTL_SEL ( BIT(30) ) +#define BITS_CLK_AUX1_DIV(_x_) ( (_x_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BIT_GPLL_CNT_DONE ( BIT(17) ) +#define BIT_MCU_GPLL_EN ( BIT(16) ) +#define BIT_ROM_FORCE_ON ( BIT(10) ) +/* All clock gatings will be invalid ,ad then all clock enable, for debug use */ +#define BIT_CLK_ALL_EN ( BIT(9) ) +/* Owner selection for UART1, <0: ARM control, 1: DSP control> */ +#define BIT_UART1_CTL_SEL ( BIT(8) ) +/* Flag indicating MPLL is stable, active high. Only for SW debug. */ +#define BIT_MPLL_CNT_DONE ( BIT(7) ) +#define BIT_TDPLL_CNT_DONE ( BIT(6) ) +#define BIT_DPLL_CNT_DONE ( BIT(5) ) +#define BIT_ARM_JTAG_EN ( BIT(4) ) +#define BIT_MCU_DPLL_EN ( BIT(3) ) +#define BIT_MCU_TDPLL_EN ( BIT(2) ) +#define BIT_MCU_MPLL_EN ( BIT(1) ) +/* MCU force deepsleep. for debug use. */ +#define BIT_MCU_FORECE_DEEP_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_GLB_GEN1 */ +#define BIT_AUD_CTL_SEL ( BIT(22) ) +#define BIT_AUDIF_AUTO_EN ( BIT(21) ) +#define BITS_AUDIF_SEL(_x_) ( (_x_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_RTC_ARCH_EB ( BIT(18) ) +#define BIT_AUD_CLK_SEL ( BIT(17) ) +#define BIT_VBC_EN ( BIT(14) ) +#define BIT_AUD_TOP_EB ( BIT(13) ) +#define BIT_AUD_IF_EB ( BIT(12) ) +#define BIT_CLK_AUX1_EN ( BIT(11) ) +#define BIT_CLK_AUX0_EN ( BIT(10) ) +#define BIT_MPLL_CTL_WE ( BIT(9) ) +#define BITS_CLK_AUX0_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_GLB_GEN3 */ +#define BITS_CCIR_MCLK_DIV(_x_) ( (_x_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BIT_JTAG_DAISY_EN ( BIT(23) ) +#define BITS_CLK_UART3_DIV(_x_) ( (_x_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_CLK_UART3_SEL(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_CLK_IIS1_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_CLK_SPI2_DIV(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_CLK_SPI2_SEL(_x_) ( (_x_) << 3 & (BIT(3)|BIT(4)) ) + +/* bits definitions for register REG_GLB_HWRST */ +#define BITS_HWRST(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +#define SHFT_HWRST ( 8 ) +#define MASK_HWRST ( BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15) ) + +/* bits definitions for register REG_GLB_M_PLL_CTL0 */ +#define BITS_MPLL_REFIN(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_MPLL_LPF(_x_) ( (_x_) << 13 & (BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_MPLL_IBIAS(_x_) ( (_x_) << 11 & (BIT(11)|BIT(12)) ) +#define BITS_MPLL_N(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +#define SHFT_MPLL_REFIN ( 16 ) +#define MASK_MPLL_REFIN ( BIT(16)|BIT(17) ) + +#define SHFT_MPLL_N ( 0 ) +#define MASK_MPLL_N ( BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10) ) + +/* bits definitions for register REG_GLB_PINCTL */ +#define BITS_AJTAG_PIN_IN_SEL(_x_) ( (_x_) << 19 & (BIT(19)|BIT(20)) ) +#define BITS_CCIRCK_PIN_IN_SEL(_x_) ( (_x_) << 17 & (BIT(17)|BIT(18)) ) +#define BIT_CP_VBC_BYPASS_EN ( BIT(16) ) +#define BIT_FM_VBC_BYPASS_EN ( BIT(15) ) +#define BIT_UART_LOOP_SEL ( BIT(14) ) +#define BIT_PCM_LOOP_SEL ( BIT(13) ) +#define BIT_DJTAG_PIN_IN_SEL ( BIT(12) ) +#define BIT_SPI1_PIN_IN_SEL ( BIT(11) ) +#define BIT_FMARK_POL_INV ( BIT(6) ) +#define BIT_SIM1_PIN_IN_SEL ( BIT(5) ) +#define BIT_SIM0_PIN_IN_SEL ( BIT(4) ) + +/* bits definitions for register REG_GLB_GEN2 */ +#define BITS_CLK_IIS0_DIV(_x_) ( (_x_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_CLK_SPI0_DIV(_x_) ( (_x_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_CLK_GPU_AXI_DIV(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)|BIT(16)) ) +#define BITS_CLK_SPI1_DIV(_x_) ( (_x_) << 11 & (BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_CLK_NFC_DIV(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_CLK_NFC_SEL(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CLK_GPU_AXI_SEL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_GLB_ARMBOOT */ +#define BITS_ARMBOOT_ADDR(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +#define SHFT_ARMBOOT_ADDR ( 0 ) +#define MASK_ARMBOOT_ADDR ( BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15) ) + +/* bits definitions for register REG_GLB_STC_DSP_ST */ +#define BITS_STC_DSP_STATE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_GLB_TD_PLL_CTL */ +#define BIT_TDPLL_DIV2OUT_FORCE_PD ( BIT(11) ) +#define BIT_TDPLL_DIV3OUT_FORCE_PD ( BIT(10) ) +#define BIT_TDPLL_DIV4OUT_FORCE_PD ( BIT(9) ) +#define BIT_TDPLL_DIV5OUT_FORCE_PD ( BIT(8) ) +#define BITS_TDPLL_REFIN(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)) ) +#define BITS_TDPLL_LPF(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)) ) +#define BITS_TDPLL_IBIAS(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_GLB_D_PLL_CTL */ +#define BITS_DPLL_REFIN(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_DPLL_LPF(_x_) ( (_x_) << 13 & (BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DPLL_IBIAS(_x_) ( (_x_) << 11 & (BIT(11)|BIT(12)) ) +#define BITS_DPLL_N(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +#define SHFT_DPLL_N ( 0 ) +#define MASK_DPLL_N ( BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10) ) + +/* bits definitions for register REG_GLB_BUSCLK */ +#define BIT_ARM_VB_SEL ( BIT(28) ) +#define BIT_ARM_VBC_ACC_CP ( BIT(27) ) +#define BIT_ARM_VBC_ACC ( BIT(26) ) +#define BITS_PWRON_DLY_CTRL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BIT_ARM_VBC_ANAON ( BIT(6) ) +#define BIT_ARM_VBC_AD1ON ( BIT(5) ) +#define BIT_ARM_VBC_AD0ON ( BIT(4) ) +#define BIT_ARM_VBC_DA1ON ( BIT(3) ) +#define BIT_ARM_VBC_DA0ON ( BIT(2) ) +#define BIT_VBC_ARM_RST ( BIT(1) ) +#define BIT_VBDA_IIS_DATA_SEL ( BIT(0) ) + +/* bits definitions for register REG_GLB_ARCH */ +#define BIT_ARCH_EB ( BIT(10) ) + +/* bits definitions for register REG_GLB_SOFT_RST */ +#define BIT_SPI2_RST ( BIT(31) ) +#define BIT_UART3_RST ( BIT(30) ) +#define BIT_EIC_RST ( BIT(29) ) +#define BIT_EFUSE_RST ( BIT(28) ) +#define BIT_PWM3_RST ( BIT(27) ) +#define BIT_PWM2_RST ( BIT(26) ) +#define BIT_PWM1_RST ( BIT(25) ) +#define BIT_PWM0_RST ( BIT(24) ) +#define BIT_ADI_RST ( BIT(22) ) +#define BIT_GPIO_RST ( BIT(21) ) +#define BIT_PINREG_RST ( BIT(20) ) +#define BIT_SYST0_RST ( BIT(19) ) +#define BIT_VBC_RST ( BIT(18) ) +#define BIT_IIS1_RST ( BIT(17) ) +#define BIT_IIS0_RST ( BIT(16) ) +#define BIT_SPI1_RST ( BIT(15) ) +#define BIT_SPI0_RST ( BIT(14) ) +#define BIT_UART2_RST ( BIT(13) ) +#define BIT_UART1_RST ( BIT(12) ) +#define BIT_UART0_RST ( BIT(11) ) +#define BIT_EPT_RST ( BIT(10) ) +#define BIT_AUD_IF_RST ( BIT(9) ) +#define BIT_TMR_RST ( BIT(8) ) +#define BIT_AUD_TOP_RST ( BIT(7) ) +#define BIT_SIM1_RST ( BIT(6) ) +#define BIT_SIM0_RST ( BIT(5) ) +#define BIT_I2C3_RST ( BIT(4) ) +#define BIT_I2C2_RST ( BIT(3) ) +#define BIT_I2C1_RST ( BIT(2) ) +#define BIT_KPD_RST ( BIT(1) ) +#define BIT_I2C0_RST ( BIT(0) ) + +/* bits definitions for register REG_GLB_G_PLL_CTL */ +#define BITS_GPLL_REFIN(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_GPLL_LPF(_x_) ( (_x_) << 13 & (BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_GPLL_IBIAS(_x_) ( (_x_) << 11 & (BIT(11)|BIT(12)) ) +#define BITS_GPLL_N(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +#define SHFT_GPLL_N ( 0 ) +#define MASK_GPLL_N ( BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10) ) + +/* bits definitions for register REG_GLB_NFCMEMDLY */ +#define BITS_NFC_MEM_DLY(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) + +/* bits definitions for register REG_GLB_CLKDLY */ +#define BITS_CLK_SPI1_SEL(_x_) ( (_x_) << 30 & (BIT(30)|BIT(31)) ) +#define BIT_CLK_ADI_EN_ARM ( BIT(29) ) +#define BIT_CLK_ADI_SEL ( BIT(28) ) +#define BITS_CLK_SPI0_SEL(_x_) ( (_x_) << 26 & (BIT(26)|BIT(27)) ) +#define BITS_CLK_UART2_SEL(_x_) ( (_x_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_CLK_UART1_SEL(_x_) ( (_x_) << 22 & (BIT(22)|BIT(23)) ) +#define BITS_CLK_UART0_SEL(_x_) ( (_x_) << 20 & (BIT(20)|BIT(21)) ) +#define BITS_CLK_CCIR_DLY_SEL(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_CLK_APB_SEL(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DSP_STATUS(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_MCU_VBC_RST ( BIT(2) ) +#define BIT_CHIP_SLEEP_REC_ARM ( BIT(1) ) +#define BIT_CHIP_SLP_ARM_CLR ( BIT(0) ) + +/* bits definitions for register REG_GLB_GEN4 */ +#define BIT_XTLBUF_WAIT_SEL ( BIT(31) ) +#define BIT_PLL_WAIT_SEL ( BIT(30) ) +#define BIT_XTL_WAIT_SEL ( BIT(29) ) +#define BITS_ARM_XTLBUF_WAIT(_x_) ( (_x_) << 21 & (BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) ) +#define BITS_ARM_PLL_WAIT(_x_) ( (_x_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_ARM_XTL_WAIT(_x_) ( (_x_) << 3 & (BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BITS_CLK_LCDC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_GLB_A_PLLMN */ +#define BITS_A_PLLMN(_x_) ( (_x_) << 0 ) + +/* bits definitions for register REG_GLB_POWCTL0 */ +#define BITS_ARM_PWR_ON_DLY(_x_) ( (_x_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BIT_ARM_SLP_POWOFF_AUTO_EN ( BIT(23) ) +#define BIT_ARM_PCELL_SWAP ( BIT(16) ) +#define BITS_ARM_ISO_ON_NUM(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_ARM_ISO_OFF_NUM(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +#define SHFT_ARM_PWR_ON_DLY ( 24 ) +#define MASK_ARM_PWR_ON_DLY ( BIT(24)|BIT(25)|BIT(26) ) + +#define SHFT_ARM_ISO_ON_NUM ( 8 ) +#define MASK_ARM_ISO_ON_NUM ( BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15) ) + +#define SHFT_ARM_ISO_OFF_NUM ( 0 ) +#define MASK_ARM_ISO_OFF_NUM ( BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7) ) + +/* bits definitions for register REG_GLB_POWCTL1 */ +#define BIT_DSP_ROM_FORCE_PD ( BIT(5) ) +#define BIT_MCU_ROM_FORCE_PD ( BIT(4) ) +#define BIT_DSP_ROM_SLP_PD_EN ( BIT(2) ) +#define BIT_MCU_ROM_SLP_PD_EN ( BIT(0) ) + +/* bits definitions for register REG_GLB_PLL_SCR */ +#define BITS_CLK_DCAMMIPIPLL_SEL(_x_) ( (_x_) << 22 & (BIT(22)|BIT(23)) ) +#define BITS_CLK_CCIRPLL_SEL(_x_) ( (_x_) << 20 & (BIT(20)|BIT(21)) ) +#define BITS_CLK_CCIRMCLKPLL_SEL(_x_) ( (_x_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_CLK_IIS1PLL_SEL(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_CLK_AUX1PLL_SEL(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_CLK_AUX0PLL_SEL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_CLK_IIS0PLL_SEL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_CLK_LCDPLL_SEL(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_CLK_DCAMPLL_SEL(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CLK_VSPPLL_SEL(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_GLB_CLK_EN */ +#define BIT_CLK_PWM3_SEL ( BIT(28) ) +#define BIT_CLK_PWM2_SEL ( BIT(27) ) +#define BIT_CLK_PWM1_SEL ( BIT(26) ) +#define BIT_CLK_PWM0_SEL ( BIT(25) ) +#define BIT_PWM3_EB ( BIT(24) ) +#define BIT_PWM2_EB ( BIT(23) ) +#define BIT_PWM1_EB ( BIT(22) ) +#define BIT_PWM0_EB ( BIT(21) ) +#define BIT_APB_PERI_FRC_ON ( BIT(20) ) +#define BIT_APB_PERI_FRC_SLP ( BIT(19) ) +#define BIT_MCU_XTLEN_AUTOPD_EN ( BIT(18) ) +#define BITS_BUFON_CTRL(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)) ) +#define BIT_CLK_TDCAL_EN ( BIT(9) ) +#define BIT_CLK_TDFIR_EN ( BIT(7) ) + +/* bits definitions for register REG_GLB_CLK26M_ANA_CTL */ +#define BITS_REC_CLK26MHZ_RESERVE(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_REC_CLK26MHZ_CUR_SEL ( BIT(4) ) +#define BIT_REC_CLK26MHZ_BUF_AUTO_EN ( BIT(3) ) +#define BIT_REC_CLK26MHZ_BUF_FORCE_PD ( BIT(2) ) +#define BIT_CLK26M_ANA_SEL ( BIT(1) ) +#define BIT_CLK26M_ANA_FORCE_EN ( BIT(0) ) + +/* bits definitions for register REG_GLB_CLK_GEN5 */ +#define BITS_CLK_SDIO_SRC_DIV(_x_) ( (_x_) << 26 & (BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BIT_CLK_SDIO_SRC_EN ( BIT(25) ) +#define BITS_CLK_EMMCPLL_SEL(_x_) ( (_x_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_CLK_SDIO2PLL_SEL(_x_) ( (_x_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_CLK_SDIO1PLL_SEL(_x_) ( (_x_) << 19 & (BIT(19)|BIT(20)) ) +#define BITS_CLK_SDIO0PLL_SEL(_x_) ( (_x_) << 17 & (BIT(17)|BIT(18)) ) +#define BIT_LDO_USB_PD ( BIT(9) ) +#define BITS_CLK_UART2_DIV(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_CLK_UART1_DIV(_x_) ( (_x_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_CLK_UART0_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_GLB_DDR_PHY_RETENTION */ +#define BIT_DDR_PHY_RET_STATUS ( BIT(3) ) +#define BIT_DDR_PHY_RET_CLEAR ( BIT(2) ) +#define BIT_DDR_PHY_AUTO_RET_EN ( BIT(1) ) +#define BIT_FORCE_DDR_PHY_RET ( BIT(0) ) + +/* bits definitions for register REG_GLB_MM_PWR_CTL */ +#define BITS_MM_PWR_ON_DLY(_x_) ( (_x_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BIT_MM_POW_FORCE_PD ( BIT(23) ) +#define BIT_MM_SLP_POWOFF_AUTO_EN ( BIT(22) ) +#define BIT_MM_PCELL_SWAP ( BIT(21) ) +#define BITS_PD_MM_STATUS(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_MM_ISO_ON_NUM(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_MM_ISO_OFF_NUM(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +#define SHFT_MM_PWR_ON_DLY ( 24 ) +#define MASK_MM_PWR_ON_DLY ( BIT(24)|BIT(25)|BIT(26) ) + +#define SHFT_MM_ISO_ON_NUM ( 8 ) +#define MASK_MM_ISO_ON_NUM ( BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15) ) + +#define SHFT_MM_ISO_OFF_NUM ( 0 ) +#define MASK_MM_ISO_OFF_NUM ( BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7) ) + +/* bits definitions for register REG_GLB_CEVA_L1RAM_PWR_CTL */ +#define BITS_CEVA_L1RAM_PWR_ON_DLY(_x_) ( (_x_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BIT_CEVA_L1RAM_POW_FORCE_PD ( BIT(23) ) +#define BIT_CEVA_L1RAM_SLP_POWOFF_AUTO_EN ( BIT(22) ) +#define BIT_CEVA_L1RAM_PCELL_SWAP ( BIT(21) ) +#define BITS_PD_CEVA_L1RAM_STATUS(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_CEVA_L1RAM_ISO_ON_NUM(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_CEVA_L1RAM_ISO_OFF_NUM(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +#define SHFT_CEVA_L1RAM_PWR_ON_DLY ( 24 ) +#define MASK_CEVA_L1RAM_PWR_ON_DLY ( BIT(24)|BIT(25)|BIT(26) ) + +#define SHFT_CEVA_L1RAM_ISO_ON_NUM ( 8 ) +#define MASK_CEVA_L1RAM_ISO_ON_NUM ( BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15) ) + +#define SHFT_CEVA_L1RAM_ISO_OFF_NUM ( 0 ) +#define MASK_CEVA_L1RAM_ISO_OFF_NUM ( BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7) ) + +/* bits definitions for register REG_GLB_GSM_PWR_CTL */ +#define BITS_GSM_PWR_ON_DLY(_x_) ( (_x_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BIT_MCU_GSM_POW_FORCE_PD ( BIT(23) ) +#define BIT_GSM_PCELL_SWAP ( BIT(21) ) +#define BITS_PD_GSM_STATUS(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_GSM_ISO_ON_NUM(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_GSM_ISO_OFF_NUM(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +#define SHFT_GSM_PWR_ON_DLY ( 24 ) +#define MASK_GSM_PWR_ON_DLY ( BIT(24)|BIT(25)|BIT(26) ) + +#define SHFT_GSM_ISO_ON_NUM ( 8 ) +#define MASK_GSM_ISO_ON_NUM ( BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15) ) + +#define SHFT_GSM_ISO_OFF_NUM ( 0 ) +#define MASK_GSM_ISO_OFF_NUM ( BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7) ) + +/* bits definitions for register REG_GLB_TD_PWR_CTL */ +#define BITS_TD_PWR_ON_DLY(_x_) ( (_x_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BIT_MCU_TD_POW_FORCE_PD ( BIT(23) ) +#define BIT_TD_PCELL_SWAP ( BIT(21) ) +#define BITS_PD_TD_STATUS(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_TD_ISO_ON_NUM(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_TD_ISO_OFF_NUM(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +#define SHFT_TD_PWR_ON_DLY ( 24 ) +#define MASK_TD_PWR_ON_DLY ( BIT(24)|BIT(25)|BIT(26) ) + +#define SHFT_TD_ISO_ON_NUM ( 8 ) +#define MASK_TD_ISO_ON_NUM ( BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15) ) + +#define SHFT_TD_ISO_OFF_NUM ( 0 ) +#define MASK_TD_ISO_OFF_NUM ( BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7) ) + +/* bits definitions for register REG_GLB_PERI_PWR_CTL */ +#define BITS_PERI_PWR_ON_DLY(_x_) ( (_x_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BIT_PERI_POW_FORCE_PD ( BIT(23) ) +#define BIT_PERI_SLP_POWOFF_AUTO_EN ( BIT(22) ) +#define BIT_PERI_PCELL_SWAP ( BIT(21) ) +#define BITS_PD_PERI_STATUS(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_PERI_ISO_ON_NUM(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PERI_ISO_OFF_NUM(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +#define SHFT_PERI_PWR_ON_DLY ( 24 ) +#define MASK_PERI_PWR_ON_DLY ( BIT(24)|BIT(25)|BIT(26) ) + +#define SHFT_PERI_ISO_ON_NUM ( 8 ) +#define MASK_PERI_ISO_ON_NUM ( BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15) ) + +#define SHFT_PERI_ISO_OFF_NUM ( 0 ) +#define MASK_PERI_ISO_OFF_NUM ( BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7) ) + +/* bits definitions for register REG_GLB_ARM_SYS_PWR_CTL */ +#define BITS_ARM_SYS_PWR_ON_DLY(_x_) ( (_x_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BIT_ARM_SYS_POW_FORCE_PD ( BIT(23) ) +#define BIT_ARM_SYS_SLP_POWOFF_AUTO_EN ( BIT(22) ) +#define BIT_ARM_SYS_PCELL_SWAP ( BIT(21) ) +#define BITS_PD_ARM_SYS_STATUS(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_ARM_SYS_ISO_ON_NUM(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_ARM_SYS_ISO_OFF_NUM(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +#define SHFT_ARM_SYS_PWR_ON_DLY ( 24 ) +#define MASK_ARM_SYS_PWR_ON_DLY ( BIT(24)|BIT(25)|BIT(26) ) + +#define SHFT_ARM_SYS_ISO_ON_NUM ( 8 ) +#define MASK_ARM_SYS_ISO_ON_NUM ( BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15) ) + +#define SHFT_ARM_SYS_ISO_OFF_NUM ( 0 ) +#define MASK_ARM_SYS_ISO_OFF_NUM ( BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7) ) + +/* bits definitions for register REG_GLB_G3D_PWR_CTL */ +#define BITS_G3D_PWR_ON_DLY(_x_) ( (_x_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BIT_G3D_POW_FORCE_PD ( BIT(23) ) +#define BIT_G3D_SLP_POWOFF_AUTO_EN ( BIT(22) ) +#define BIT_G3D_PCELL_SWAP ( BIT(21) ) +#define BITS_PD_G3D_STATUS(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_G3D_ISO_ON_NUM(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_G3D_ISO_OFF_NUM(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +#define SHFT_G3D_PWR_ON_DLY ( 24 ) +#define MASK_G3D_PWR_ON_DLY ( BIT(24)|BIT(25)|BIT(26) ) + +#define SHFT_G3D_ISO_ON_NUM ( 8 ) +#define MASK_G3D_ISO_ON_NUM ( BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15) ) + +#define SHFT_G3D_ISO_OFF_NUM ( 0 ) +#define MASK_G3D_ISO_OFF_NUM ( BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7) ) + +/* bits definitions for register REG_GLB_CHIP_DSLEEP_STAT */ +#define BIT_CHIP_DSLEEP ( BIT(0) ) + +/* bits definitions for register REG_GLB_PWR_CTRL_NUM1 */ +#define BITS_ARM_SYS_PWR_OFF_NUM(_x_) ( (_x_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ARM_SYS_PWR_ON_NUM(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_ARM_PWR_OFF_NUM(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_ARM_PWR_ON_NUM(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_GLB_PWR_CTRL_NUM2 */ +#define BITS_G3D_PWR_OFF_NUM(_x_) ( (_x_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_G3D_PWR_ON_NUM(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_MM_PWR_OFF_NUM(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_MM_PWR_ON_NUM(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_GLB_PWR_CTRL_NUM3 */ +#define BITS_CEVA_L1RAM_PWR_OFF_NUM(_x_)( (_x_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_CEVA_L1RAM_PWR_ON_NUM(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PERI_PWR_OFF_NUM(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PERI_PWR_ON_NUM(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_GLB_PWR_CTRL_NUM4 */ +#define BITS_GSM_PWR_OFF_NUM(_x_) ( (_x_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_GSM_PWR_ON_NUM(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_TD_PWR_OFF_NUM(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_TD_PWR_ON_NUM(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_GLB_PWR_CTRL_NUM5 */ +#define BITS_ARM9_PWR_OFF_NUM(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_ARM9_PWR_ON_NUM(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_GLB_ARM9_SYS_PWR_CTL */ +#define BITS_ARM9_SYS_PWR_ON_DLY(_x_) ( (_x_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BIT_ARM9_SYS_POW_FORCE_PD ( BIT(23) ) +#define BIT_ARM9_SYS_SLP_POWOFF_AUTO_EN ( BIT(22) ) +#define BIT_ARM9_SYS_PCELL_SWAP ( BIT(21) ) +#define BITS_PD_ARM9_SYS_STATUS(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_ARM9_SYS_ISO_ON_NUM(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_ARM9_SYS_ISO_OFF_NUM(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +#define SHFT_ARM9_SYS_PWR_ON_DLY ( 24 ) +#define MASK_ARM9_SYS_PWR_ON_DLY ( BIT(24)|BIT(25)|BIT(26) ) + +#define SHFT_ARM9_SYS_ISO_ON_NUM ( 8 ) +#define MASK_ARM9_SYS_ISO_ON_NUM ( BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15) ) + +#define SHFT_ARM9_SYS_ISO_OFF_NUM ( 0 ) +#define MASK_ARM9_SYS_ISO_OFF_NUM ( BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7) ) + +/* bits definitions for register REG_GLB_DMA_CTRL */ +#define BIT_DMA_SPI_SEL ( BIT(0) ) + +/* bits definitions for register REG_GLB_TP_DLYC_LEN */ +#define BITS_TD(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) + +/* bits definitions for register REG_GLB_MIPI_PHY_CTRL */ +#define BIT_FORCE_DSI_PHY_RSTZ ( BIT(3) ) +#define BIT_FORCE_DSI_PHY_SHUTDWNZ ( BIT(2) ) +#define BIT_FORCE_CSI_PHY_RSTZ ( BIT(1) ) +#define BIT_FORCE_CSI_PHY_SHUTDWNZ ( BIT(0) ) + +/* vars definitions for controller REGS_GLB */ +#define REG_GLB_SET(A) ( A + 0x1000 ) +#define REG_GLB_CLR(A) ( A + 0x2000 ) + +#endif //__REGS_GLB_H__ diff --git a/include/soc/sprd/__regulator_map.h b/include/soc/sprd/__regulator_map.h new file mode 100644 index 00000000..b6aca278 --- /dev/null +++ b/include/soc/sprd/__regulator_map.h @@ -0,0 +1,128 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +/* + * Regulator Name[0], Regulator Type[1], Power Off Ctrl[2] and Bit[3], Power On Ctrl[4] and Bit[5], Slp Ctrl[6] and Bit[7], + * Voltage Trimming Ctrl[8] and Bits[9], Voltage Ctrl[10] and Bits[11], Voltage Select Count[12] and List[13 ... ...] + */ + + SCI_REGU_REG(vddcama, 0, ANA_REG_GLB_LDO_PD_CTRL0, BIT(12), ANA_REG_GLB_LDO_PD_CTRL0, BIT(13), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(7), + ANA_REG_GLB2_LDO_TRIM6, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12), ANA_REG_GLB_LDO_VCTRL2, BIT(8)|BIT(9)|BIT(10)|BIT(11), 4, 2800, 3000, 2500, 1800); + + SCI_REGU_REG(vddcamio, 0, ANA_REG_GLB_LDO_PD_CTRL0, BIT(10), ANA_REG_GLB_LDO_PD_CTRL0, BIT(11), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(6), + ANA_REG_GLB2_LDO_TRIM7, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12), ANA_REG_GLB_LDO_VCTRL2, BIT(4)|BIT(5)|BIT(6)|BIT(7), 4, 1500, 1800, 1300, 1200); + + SCI_REGU_REG(vddcamcore, 0, ANA_REG_GLB_LDO_PD_CTRL0, BIT(8), ANA_REG_GLB_LDO_PD_CTRL0, BIT(9), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(5), + ANA_REG_GLB2_LDO_TRIM6, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_VCTRL2, BIT(0)|BIT(1)|BIT(2)|BIT(3), 4, 1500, 1800, 1300, 1200); + + SCI_REGU_REG(vddcammot, 0, ANA_REG_GLB_LDO_PD_CTRL0, BIT(14), ANA_REG_GLB_LDO_PD_CTRL0, BIT(15), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(8), + ANA_REG_GLB2_LDO_TRIM7, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_VCTRL2, BIT(12)|BIT(13)|BIT(14)|BIT(15), 4, 3000, 3300, 2800, 1800); + + SCI_REGU_REG(vddrf, 0, ANA_REG_GLB_LDO_PD_SET, BIT(4), ANA_REG_GLB_LDO_PD_RST, BIT(4), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(0), + ANA_REG_GLB2_LDO_TRIM5, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12), ANA_REG_GLB_LDO_VCTRL0, BIT(4)|BIT(5)|BIT(6)|BIT(7), 4, 2850, 2950, 2500, 1800); + + SCI_REGU_REG(vddsim0, 0, ANA_REG_GLB_LDO_PD_CTRL0, BIT(4), ANA_REG_GLB_LDO_PD_CTRL0, BIT(5), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(2), + ANA_REG_GLB2_LDO_TRIM4, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12), ANA_REG_GLB_LDO_VCTRL1, BIT(0)|BIT(1)|BIT(2)|BIT(3), 4, 1800, 2900, 3000, 3100); + + SCI_REGU_REG(vddsim1, 0, ANA_REG_GLB_LDO_PD_CTRL0, BIT(6), ANA_REG_GLB_LDO_PD_CTRL0, BIT(7), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(3), + ANA_REG_GLB2_LDO_TRIM4, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12), ANA_REG_GLB_LDO_VCTRL1, BIT(4)|BIT(5)|BIT(6)|BIT(7), 4, 1800, 2900, 3000, 3100); + + SCI_REGU_REG(vddcmmb1p2, 0, ANA_REG_GLB_LDO_PD_CTRL1, BIT(12), ANA_REG_GLB_LDO_PD_CTRL1, BIT(13), ANA_REG_GLB_LDO_SLP_CTRL1, BIT(2), + ANA_REG_GLB2_LDO_TRIM8, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12), ANA_REG_GLB_LDO_VCTRL4, BIT(12)|BIT(13)|BIT(14)|BIT(15), 4, 1500, 1800, 1300, 1200); + + SCI_REGU_REG(vddcmmb1p8, 0, ANA_REG_GLB_LDO_PD_CTRL1, BIT(10), ANA_REG_GLB_LDO_PD_CTRL1, BIT(11), ANA_REG_GLB_LDO_SLP_CTRL1, BIT(3), + ANA_REG_GLB2_LDO_TRIM8, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_VCTRL4, BIT(8)|BIT(9)|BIT(10)|BIT(11), 4, 1500, 1800, 1300, 1200); + + SCI_REGU_REG(vddsd0, 0, ANA_REG_GLB_LDO_PD_CTRL1, BIT(0), ANA_REG_GLB_LDO_PD_CTRL1, BIT(1), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(9), + ANA_REG_GLB2_LDO_TRIM2, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_VCTRL3, BIT(12)|BIT(13)|BIT(14)|BIT(15), 4, 2800, 3000, 2500, 1800); + + SCI_REGU_REG(vddsd1, 0, ANA_REG_GLB_LDO_PD_CTRL1, BIT(2), ANA_REG_GLB_LDO_PD_CTRL1, BIT(3), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(14), + ANA_REG_GLB2_LDO_TRIM3, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12), ANA_REG_GLB_LDO_VCTRL4, BIT(0)|BIT(1)|BIT(2)|BIT(3), 4, 1500, 1800, 1300, 1200); + + SCI_REGU_REG(vddsd3, 0, ANA_REG_GLB_LDO_PD_CTRL1, BIT(4), ANA_REG_GLB_LDO_PD_CTRL1, BIT(5), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(15), + ANA_REG_GLB2_LDO_TRIM3, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_VCTRL4, BIT(4)|BIT(5)|BIT(6)|BIT(7), 4, 1500, 1800, 1300, 1200); + + SCI_REGU_REG(vdd3v, 0, ANA_REG_GLB_LDO_PD_CTRL1, BIT(6), ANA_REG_GLB_LDO_PD_CTRL1, BIT(7), ANA_REG_GLB_LDO_SLP_CTRL1, BIT(1), + ANA_REG_GLB2_LDO_TRIM1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_VCTRL1, BIT(8)|BIT(9)|BIT(10)|BIT(11), 4, 2800, 3000, 2500, 1800); + + SCI_REGU_REG(vdd18, 0, ANA_REG_GLB_LDO_PD_SET, BIT(7), ANA_REG_GLB_LDO_PD_RST, BIT(7), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(12), + ANA_REG_GLB2_LDO_TRIM0, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12), ANA_REG_GLB_LDO_VCTRL3, BIT(4)|BIT(5)|BIT(6)|BIT(7), 4, 1500, 1800, 1300, 1200); + + SCI_REGU_REG(vdd28, 0, ANA_REG_GLB_LDO_PD_SET, BIT(6), ANA_REG_GLB_LDO_PD_RST, BIT(6), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(11), + ANA_REG_GLB2_LDO_TRIM0, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_VCTRL3, BIT(0)|BIT(1)|BIT(2)|BIT(3), 4, 2800, 3000, 2650, 1800); + + SCI_REGU_REG(vddmem, 2, ANA_REG_GLB_LDO_PD_SET, BIT(3), ANA_REG_GLB_LDO_PD_RST, BIT(3), 0, 0, + ANA_REG_GLB_DCDCMEM_CTRL_CAL, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_DCDCMEM_CTRL0, BIT(0)|BIT(1), 4, 1200, 1100, 1300, 1400); + + SCI_REGU_REG(vddmem1, 2, ANA_REG_GLB_LDO_PD_SET, BIT(3), ANA_REG_GLB_LDO_PD_RST, BIT(3), 0, 0, + ANA_REG_GLB_DCDCMEM_CTRL_CAL, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_DCDCMEM_CTRL0, BIT(0)|BIT(1), 4, 1800, 1700, 1900, 2000); + + SCI_REGU_REG(vddarm, 2, ANA_REG_GLB_LDO_PD_SET, BIT(2), ANA_REG_GLB_LDO_PD_RST, BIT(2), 0, 0, + ANA_REG_GLB_DCDCARM_CTRL_CAL, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_DCDCARM_CTRL0, BIT(0)|BIT(1)|BIT(2), 8, 1100, 700, 800, 900, 1000, 650, 1200, 1300); + + SCI_REGU_REG(vddcore, 2, ANA_REG_GLB_LDO_PD_SET, BIT(1), ANA_REG_GLB_LDO_PD_RST, BIT(1), 0, 0, + ANA_REG_GLB_DCDC_CTRL_CAL, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_DCDC_CTRL0, BIT(0)|BIT(1)|BIT(2), 8, 1100, 700, 800, 900, 1000, 650, 1200, 1300); + + SCI_REGU_REG(dcdcldo, 2, ANA_REG_GLB_LDO_PD_SET, BIT(9), ANA_REG_GLB_LDO_PD_RST, BIT(9), 0, 0, + ANA_REG_GLB_DCDCLDO_CTRL_CAL, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_DCDCLDO_CTRL0, BIT(0)|BIT(1)|BIT(2), 8, 2200, 1800, 1900, 2000, 2100, 2300, 2400, 2500); + + SCI_REGU_REG(vddusb, 0, ANA_REG_GLB_LDO_PD_CTRL0, BIT(0), ANA_REG_GLB_LDO_PD_CTRL0, BIT(1), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(4), + ANA_REG_GLB2_LDO_TRIM4, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_VCTRL1, BIT(12)|BIT(13)|BIT(14)|BIT(15), 4, 3300, 3400, 3200, 3100); + + SCI_REGU_REG(vddusbd, 1, REG_GLB_CLK_GEN5, BIT(9), REG_GLB_CLK_GEN5, BIT(9), 0, 0, + 0, 0, 0, 0, 0); + + SCI_REGU_REG(vdd25, 0, ANA_REG_GLB_LDO_PD_SET, BIT(8), ANA_REG_GLB_LDO_PD_RST, BIT(8), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(13), + ANA_REG_GLB2_LDO_TRIM1, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12), ANA_REG_GLB_LDO_VCTRL3, BIT(8)|BIT(9)|BIT(10)|BIT(11), 4, 2500, 2750, 3000, 2900); + + SCI_REGU_REG(vdd_a, 0, 0, 0, 0, 0, 0, 0, + ANA_REG_GLB2_LDO_TRIM2, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12), 0, 0, 0); + + SCI_REGU_REG(avddbb, 0, ANA_REG_GLB_LDO_PD_SET, BIT(5), ANA_REG_GLB_LDO_PD_RST, BIT(5), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(10), + ANA_REG_GLB2_LDO_TRIM5, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_VCTRL0, BIT(12)|BIT(13)|BIT(14)|BIT(15), 4, 3000, 3100, 2900, 2800); + + SCI_REGU_REG(audio_vbo, 0, 0, 0, 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(10), + 0, 0, 0, 0, 8, 2900, 3100, 3200, 3300, 3400, 3500, 3600, 3800); + + SCI_REGU_REG(audio_vb, 0, 0, 0, 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(9), + 0, 0, 0, 0, 8, 2900, 3100, 3200, 3300, 3400, 3500, 3600, 3800); + + SCI_REGU_REG(vddrtc, 0, 0, 0, 0, 0, 0, 0, + 0, 0, ANA_REG_GLB_LDO_VCTRL0, BIT(0)|BIT(1)|BIT(2)|BIT(3), 4, 1800, 1700, 1600, 1500); + + SCI_REGU_REG(vbatbk, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 4, 2600, 3000, 2800, 3100); + + SCI_REGU_REG(audio_micbias, 0, 0, 0, 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(11), + 0, 0, 0, 0, 4, 1900, 2100, 2300, 2500); + + SCI_REGU_REG(audio_auxmicbias, 0, 0, 0, 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(12), + 0, 0, 0, 0, 4, 1900, 2100, 2300, 2500); + + SCI_REGU_REG(audio_bg_ibias, 0, 0, 0, 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(8), + 0, 0, 0, 0, 0); + + SCI_REGU_REG(audio_bg, 0, 0, 0, 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(7), + 0, 0, 0, 0, 0); + + SCI_REGU_REG(audio_vcmbuf, 0, 0, 0, 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(6), + 0, 0, 0, 0, 0); + + SCI_REGU_REG(audio_vcm, 0, 0, 0, 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(5), + 0, 0, 0, 0, 0); + diff --git a/include/soc/sprd/__sc8830_clock_tree.h b/include/soc/sprd/__sc8830_clock_tree.h new file mode 100644 index 00000000..b16fb239 --- /dev/null +++ b/include/soc/sprd/__sc8830_clock_tree.h @@ -0,0 +1,527 @@ +/* + * Copyright (C) 2013 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +/* + * Clock (0)Name, Clock (1)fixed rate, Clock Enable (2)Ctrl and (3)Bit, + * Clock Divisor (4)Ctrl and (5)Bit, Clock Parent (6)Ctrl and (7)Bit, + * and Parent Select (15)Count and (16)Lists[ ... ...] + */ + +SCI_CLK_ADD(ext_26m, 26000000, REG_PMU_APB_CGM_AP_EN, BIT(0), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(ext_32k, 32768, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_mpll, 0, REG_PMU_APB_CGM_AP_EN, BIT(6), + REG_AON_APB_MPLL_CFG, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_dpll, 0, REG_PMU_APB_CGM_AP_EN, BIT(1), + REG_AON_APB_DPLL_CFG, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_td_sel_i, 0, REG_PMU_APB_TDPLL_REL_CFG, BIT(0), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_w_sel_i, 0, REG_PMU_APB_WPLL_REL_CFG, BIT(0), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_c_sel_i, 0, REG_PMU_APB_CPLL_REL_CFG, BIT(0), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_wifi_sel_i, 0, REG_PMU_APB_WIFIPLL1_REL_CFG, BIT(0), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_tdpll, 768000000, REG_PMU_APB_CGM_AP_EN, BIT(3), + 0, 0, 0, 0, + 1, &clk_td_sel_i); + +SCI_CLK_ADD(clk_wpll, 921600000, REG_PMU_APB_CGM_AP_EN, BIT(5), + 0, 0, 0, 0, + 1, &clk_w_sel_i); + +SCI_CLK_ADD(clk_cpll, 624000000, REG_PMU_APB_CGM_AP_EN, BIT(2), + 0, 0, 0, 0, + 1, &clk_c_sel_i); + +SCI_CLK_ADD(clk_wifipll, 880000000, REG_PMU_APB_CGM_AP_EN, BIT(4), + 0, 0, 0, 0, + 1, &clk_wifi_sel_i); + +SCI_CLK_ADD(clk_300m, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(0), + 3, 0, 0, 0, + 1, &clk_mpll); + +SCI_CLK_ADD(clk_37m5, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(1), + 24, 0, 0, 0, + 1, &clk_mpll); + +SCI_CLK_ADD(clk_533m, 0, 0, 0, + 0, 0, 0, 0, + 1, &clk_dpll); + +SCI_CLK_ADD(clk_66m, 66000000, REG_PMU_APB_PLL_DIV_EN1, BIT(2), + 0, 0, 0, 0, + 1, &clk_dpll); + +SCI_CLK_ADD(clk_51m2_w, 51200000, REG_PMU_APB_PLL_DIV_EN1, BIT(23), + 0, 0, 0, 0, + 1, &clk_wpll); + +SCI_CLK_ADD(clk_40m, 40000000, REG_PMU_APB_PLL_DIV_EN1, BIT(27), + 0, 0, 0, 0, + 1, &clk_wifipll); + +SCI_CLK_ADD(clk_312m, 0, REG_PMU_APB_CGM_AP_EN, BIT(7), + 2, 0, 0, 0, + 1, &clk_cpll); + +SCI_CLK_ADD(clk_208m, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(17), + 3, 0, 0, 0, + 1, &clk_cpll); + +SCI_CLK_ADD(clk_104m, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(18), + 6, 0, 0, 0, + 1, &clk_cpll); + +SCI_CLK_ADD(clk_52m, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(19), + 12, 0, 0, 0, + 1, &clk_cpll); + +SCI_CLK_ADD(clk_384m, 0, REG_PMU_APB_CGM_AP_EN, BIT(8), + 2, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_192m, 0, REG_PMU_APB_CGM_AP_EN, BIT(10), + 4, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_96m, 0, REG_PMU_APB_CGM_AP_EN, BIT(13), + 8, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_48m, 0, REG_PMU_APB_CGM_AP_EN, BIT(17), + 16, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_24m, 0, REG_PMU_APB_CGM_AP_EN, BIT(18), + 32, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_12m, 0, REG_PMU_APB_CGM_AP_EN, BIT(19), + 64, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_256m, 0, REG_PMU_APB_CGM_AP_EN, BIT(9), + 3, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_128m, 0, REG_PMU_APB_CGM_AP_EN, BIT(12), + 6, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_64m, 0, REG_PMU_APB_CGM_AP_EN, BIT(15), + 12, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_153m6, 0, REG_PMU_APB_CGM_AP_EN, BIT(11), + 5, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_51m2, 0, REG_PMU_APB_CGM_AP_EN, BIT(16), + 15, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_76m8, 0, REG_PMU_APB_CGM_AP_EN, BIT(14), + 10, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_38m4, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(15), + 20, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_mcu, 0, 0, 0, + REG_AP_AHB_CA7_CKG_CFG, BIT(4)|BIT(5)|BIT(6), REG_AP_AHB_CA7_CKG_CFG, BIT(0)|BIT(1)|BIT(2), + 7, &ext_26m, &clk_dpll, &clk_cpll, &clk_tdpll, &clk_wifipll, &clk_wpll, &clk_mpll); + +SCI_CLK_ADD(clk_arm, 0, 0, 0, + 0, 0, 0, 0, + 1, &clk_mcu); + +SCI_CLK_ADD(clk_axi, 0, 0, 0, + REG_AP_AHB_CA7_CKG_CFG, BIT(8)|BIT(9)|BIT(10), 0, 0, + 1, &clk_mcu); + +SCI_CLK_ADD(clk_dbg, 0, REG_AP_AHB_MISC_CKG_EN, BIT(8), + REG_AP_AHB_CA7_CKG_CFG, BIT(16)|BIT(17)|BIT(18), 0, 0, + 1, &clk_mcu); + +SCI_CLK_ADD(clk_ahb, 0, 0, 0, + 0, 0, REG_AP_CLK_AP_AHB_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_76m8, &clk_128m, &clk_192m); + +SCI_CLK_ADD(clk_apb, 0, 0, 0, + 0, 0, REG_AP_CLK_AP_APB_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_64m, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_pub_ahb, 0, 0, 0, + 0, 0, REG_AON_CLK_PUB_AHB_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_emc, 0, 0, 0, + REG_AON_CLK_EMC_CFG, BIT(8)|BIT(9), REG_AON_CLK_EMC_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_256m, &clk_384m, &clk_533m); + +SCI_CLK_ADD(clk_aon_apb, 0, 0, 0, + REG_AON_CLK_AON_APB_CFG, BIT(8)|BIT(9), REG_AON_CLK_AON_APB_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_76m8, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_disp_emc, 0, REG_AON_APB_APB_EB1, BIT(11), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_gsp, 0, REG_AP_AHB_AHB_EB, BIT(3), + 0, 0, REG_AP_CLK_GSP_CFG, BIT(0)|BIT(1), + 4, &clk_96m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_disc0, 0, REG_AP_AHB_AHB_EB, BIT(1), + REG_AP_CLK_DISPC0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_DISPC0_CFG, BIT(0)|BIT(1), + 4, &clk_153m6, &clk_192m, &clk_256m, &clk_312m); + +SCI_CLK_ADD(clk_disc0_dbi, 0, REG_AP_AHB_AHB_EB, BIT(1), + REG_AP_CLK_DISPC0_DBI_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_DISPC0_DBI_CFG, BIT(0)|BIT(1), + 4, &clk_128m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_disc0_dpi, 0, REG_AP_AHB_AHB_EB, BIT(1), + REG_AP_CLK_DISPC0_DPI_CFG, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), REG_AP_CLK_DISPC0_DPI_CFG, BIT(0)|BIT(1), + 4, &clk_128m, &clk_153m6, &clk_192m, &clk_384m); + +SCI_CLK_ADD(clk_disc1, 0, REG_AP_AHB_AHB_EB, BIT(2), + REG_AP_CLK_DISPC1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_DISPC1_CFG, BIT(0)|BIT(1), + 4, &clk_153m6, &clk_192m, &clk_256m, &clk_312m); + +SCI_CLK_ADD(clk_disc1_dbi, 0, REG_AP_AHB_AHB_EB, BIT(2), + REG_AP_CLK_DISPC1_DBI_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_DISPC1_DBI_CFG, BIT(0)|BIT(1), + 4, &clk_128m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_disc1_dpi, 0, REG_AP_AHB_AHB_EB, BIT(2), + REG_AP_CLK_DISPC1_DPI_CFG, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), REG_AP_CLK_DISPC1_DPI_CFG, BIT(0)|BIT(1), + 4, &clk_128m, &clk_153m6, &clk_192m, &clk_384m); + +SCI_CLK_ADD(clk_nfc, 0, REG_AP_AHB_AHB_EB, BIT(6), + REG_AP_CLK_NFC_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_NFC_CFG, BIT(0)|BIT(1), + 3, &clk_64m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_sdio0, 0, REG_AP_AHB_AHB_EB, BIT(8), + REG_AP_CLK_SDIO0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_SDIO0_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_192m, &clk_256m, &clk_312m); + +SCI_CLK_ADD(clk_sdio1, 0, REG_AP_AHB_AHB_EB, BIT(9), + 0, 0, REG_AP_CLK_SDIO1_CFG, BIT(0)|BIT(1), + 4, &clk_48m, &clk_76m8, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_sdio2, 0, REG_AP_AHB_AHB_EB, BIT(10), + 0, 0, REG_AP_CLK_SDIO2_CFG, BIT(0)|BIT(1), + 4, &clk_48m, &clk_76m8, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_emmc, 0, REG_AP_AHB_AHB_EB, BIT(11), + 0, 0, REG_AP_CLK_EMMC_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_192m, &clk_256m, &clk_312m); + +SCI_CLK_ADD(clk_gps_tcxo, 64000000, REG_AP_CLK_GPS_TCXO_CFG, BIT(16), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_gps, 0, REG_AP_AHB_AHB_EB, BIT(12), + 0, 0, REG_AP_CLK_GPS_CFG, BIT(0), + 2, &clk_64m, &clk_76m8); + +SCI_CLK_ADD(clk_usb_ref, 0, REG_AP_AHB_AHB_EB, BIT(4), + 0, 0, REG_AP_CLK_USB_REF_CFG, BIT(0), + 2, &clk_12m, &clk_24m); + +SCI_CLK_ADD(clk_uart0, 0, REG_AP_APB_APB_EB, BIT(13), + REG_AP_CLK_UART0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_UART0_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart1, 0, REG_AP_APB_APB_EB, BIT(14), + REG_AP_CLK_UART1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_UART1_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart2, 0, REG_AP_APB_APB_EB, BIT(15), + REG_AP_CLK_UART2_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_UART2_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart3, 0, REG_AP_APB_APB_EB, BIT(16), + REG_AP_CLK_UART3_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_UART3_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart4, 0, REG_AP_APB_APB_EB, BIT(17), + REG_AP_CLK_UART4_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_UART4_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_i2c0, 0, REG_AP_APB_APB_EB, BIT(8), + REG_AP_CLK_I2C0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_I2C0_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_i2c1, 0, REG_AP_APB_APB_EB, BIT(9), + REG_AP_CLK_I2C1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_I2C1_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_i2c2, 0, REG_AP_APB_APB_EB, BIT(10), + REG_AP_CLK_I2C2_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_I2C2_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_i2c3, 0, REG_AP_APB_APB_EB, BIT(11), + REG_AP_CLK_I2C3_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_I2C3_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_i2c4, 0, REG_AP_APB_APB_EB, BIT(12), + REG_AP_CLK_I2C4_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_I2C4_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_spi0, 0, REG_AP_APB_APB_EB, BIT(5), + REG_AP_CLK_SPI0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_SPI0_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_spi1, 0, REG_AP_APB_APB_EB, BIT(6), + REG_AP_CLK_SPI1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_SPI1_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_spi2, 0, REG_AP_APB_APB_EB, BIT(7), + REG_AP_CLK_SPI2_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_SPI2_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_iis0, 0, REG_AP_APB_APB_EB, BIT(1), + REG_AP_CLK_IIS0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_IIS0_CFG, BIT(0)|BIT(1), + 3, &ext_26m, &clk_76m8, &clk_128m); + +SCI_CLK_ADD(clk_iis1, 0, REG_AP_APB_APB_EB, BIT(2), + REG_AP_CLK_IIS1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_IIS1_CFG, BIT(0)|BIT(1), + 3, &ext_26m, &clk_76m8, &clk_128m); + +SCI_CLK_ADD(clk_iis2, 0, REG_AP_APB_APB_EB, BIT(3), + REG_AP_CLK_IIS2_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_IIS2_CFG, BIT(0)|BIT(1), + 3, &ext_26m, &clk_76m8, &clk_128m); + +SCI_CLK_ADD(clk_iis3, 0, REG_AP_APB_APB_EB, BIT(4), + REG_AP_CLK_IIS3_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_IIS3_CFG, BIT(0)|BIT(1), + 3, &ext_26m, &clk_76m8, &clk_128m); + +SCI_CLK_ADD(clk_gpu_top_i, 0, REG_PMU_APB_PD_GPU_TOP_CFG+1, BIT(25), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_gpu_i, 0, REG_AON_APB_APB_EB0, BIT(27), + 0, 0, 0, 0, + 1, &clk_gpu_top_i); + +SCI_CLK_ADD(clk_gpu, 0, &clk_gpu_i, 0, + REG_GPU_APB_APB_CLK_CTRL, BIT(2)|BIT(3), REG_GPU_APB_APB_CLK_CTRL, BIT(0)|BIT(1), + 4, &clk_208m, &clk_256m, &clk_300m, &clk_312m); + +SCI_CLK_ADD(clk_mm_top_i, 0, REG_PMU_APB_PD_MM_TOP_CFG+1, BIT(25), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_mm_i, 0, REG_AON_APB_APB_EB0, BIT(25), + 0, 0, 0, 0, + 1, &clk_mm_top_i); + +SCI_CLK_ADD(clk_mm_ahb, 0, 0, 0, + 0, 0, REG_MM_CLK_MM_AHB_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_mm_mtx_axi, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(8), + 0, 0, 0, 0, + 1, &clk_mm_i); + +SCI_CLK_ADD(clk_mm_axi, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(7), + 0, 0, 0, 0, + 1, &clk_mm_mtx_axi); + +SCI_CLK_ADD(clk_mm_ckg_i, 0, REG_MM_AHB_AHB_EB, BIT(6), + 0, 0, 0, 0, + 1, &clk_mm_i); + +SCI_CLK_ADD(clk_jpg_i, 0, REG_MM_AHB_AHB_EB, BIT(5), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_jpg_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(6), + 0, 0, 0, 0, + 1, &clk_jpg_i); + +SCI_CLK_ADD(clk_jpg, 0, &clk_jpg_ckg_i, 0, + 0, 0, REG_MM_CLK_JPG_CFG, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_vsp_i, 0, REG_MM_AHB_AHB_EB, BIT(3), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_vsp_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(5), + 0, 0, 0, 0, + 1, &clk_vsp_i); + +SCI_CLK_ADD(clk_vsp, 0, &clk_vsp_ckg_i, 0, + 0, 0, REG_MM_CLK_VSP_CFG, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_isp_i, 0, REG_MM_AHB_AHB_EB, BIT(2), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_isp_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(4), + 0, 0, 0, 0, + 1, &clk_isp_i); + +SCI_CLK_ADD(clk_isp, 0, &clk_isp_ckg_i, 0, + 0, 0, REG_MM_CLK_ISP_CFG, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_sensor_i, 0, REG_MM_AHB_AHB_EB, BIT(1), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_sensor_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(2), + 0, 0, 0, 0, + 1, &clk_sensor_i); + +SCI_CLK_ADD(clk_sensor, 0, &clk_sensor_ckg_i, 0, + REG_MM_CLK_SENSOR_CFG, BIT(8)|BIT(9)|BIT(10), REG_MM_CLK_SENSOR_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_76m8, &clk_96m); + +SCI_CLK_ADD(clk_ccir_in, 64000000, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_ccir_i, 0, REG_MM_AHB_AHB_EB, BIT(1), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_ccir, 0, &clk_ccir_i, 0, + 0, 0, REG_MM_CLK_CCIR_CFG, BIT(16), + 2, &clk_24m, &clk_ccir_in); + +SCI_CLK_ADD(clk_dcam_i, 0, REG_MM_AHB_AHB_EB, BIT(0), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_dcam_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(3), + 0, 0, 0, 0, + 1, &clk_dcam_i); + +SCI_CLK_ADD(clk_dcam, 0, &clk_dcam_ckg_i, 0, + 0, 0, REG_MM_CLK_DCAM_CFG, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_csi_i, 0, REG_MM_AHB_AHB_EB, BIT(4), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_csi_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(1), + 0, 0, 0, 0, + 1, &clk_csi_i); + +SCI_CLK_ADD(clk_cphy_cfg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(0), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_dcam_mipi, 0, &clk_cphy_cfg_i, 0, + 0, 0, 0, 0, + 1, &clk_csi_ckg_i); + +SCI_CLK_ADD(clk_aud, 0, REG_AON_APB_APB_EB0, BIT(18), + 0, 0, 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_audif, 0, REG_AON_APB_APB_EB0, BIT(17), + 0, 0, REG_AON_CLK_AUDIF_CFG, BIT(0)|BIT(1), + 3, &ext_26m, &clk_38m4, &clk_51m2); + +SCI_CLK_ADD(clk_vbc, 0, REG_AON_APB_APB_EB0, BIT(19), + 0, 0, 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_fm_in, 64000000, REG_AON_CLK_FM_CFG, BIT(16), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_fm, 0, REG_AON_APB_APB_EB0, BIT(1), + 0, 0, 0, 0, + 1, &clk_fm_in); + +SCI_CLK_ADD(clk_adi, 0, REG_AON_APB_APB_EB0, BIT(16), + 0, 0, REG_AON_CLK_ADI_CFG, BIT(0)|BIT(1), + 3, &ext_26m, &clk_51m2, &clk_76m8); + +SCI_CLK_ADD(clk_aux0, 0, REG_AON_APB_APB_EB1, BIT(2), + REG_AON_APB_AON_CGM_CFG, BIT(16)|BIT(17)|BIT(18)|BIT(19), REG_AON_APB_AON_CGM_CFG, BIT(0)|BIT(1)|BIT(2)|BIT(3), + 10, &ext_32k, &ext_26m, &ext_26m, &clk_48m, &clk_52m, &clk_51m2, &clk_37m5, &clk_40m, &clk_66m, &clk_40m); + +SCI_CLK_ADD(clk_aux1, 0, REG_AON_APB_APB_EB1, BIT(3), + REG_AON_APB_AON_CGM_CFG, BIT(20)|BIT(21)|BIT(22)|BIT(23), REG_AON_APB_AON_CGM_CFG, BIT(4)|BIT(5)|BIT(6)|BIT(7), + 10, &ext_32k, &ext_26m, &ext_26m, &clk_48m, &clk_52m, &clk_51m2, &clk_37m5, &clk_40m, &clk_66m, &clk_40m); + +SCI_CLK_ADD(clk_aux2, 0, REG_AON_APB_APB_EB1, BIT(4), + REG_AON_APB_AON_CGM_CFG, BIT(24)|BIT(25)|BIT(26)|BIT(27), REG_AON_APB_AON_CGM_CFG, BIT(8)|BIT(9)|BIT(10)|BIT(11), + 10, &ext_32k, &ext_26m, &ext_26m, &clk_48m, &clk_52m, &clk_51m2, &clk_37m5, &clk_40m, &clk_66m, &clk_40m); + +SCI_CLK_ADD(clk_pwm0, 0, REG_AON_APB_APB_EB0, BIT(4), + 0, 0, REG_AON_CLK_PWM0_CFG, BIT(0), + 2, &ext_32k, &ext_26m); + +SCI_CLK_ADD(clk_pwm1, 0, REG_AON_APB_APB_EB0, BIT(5), + 0, 0, REG_AON_CLK_PWM1_CFG, BIT(0), + 2, &ext_32k, &ext_26m); + +SCI_CLK_ADD(clk_pwm2, 0, REG_AON_APB_APB_EB0, BIT(6), + 0, 0, REG_AON_CLK_PWM2_CFG, BIT(0), + 2, &ext_32k, &ext_26m); + +SCI_CLK_ADD(clk_pwm3, 0, REG_AON_APB_APB_EB0, BIT(7), + 0, 0, REG_AON_CLK_PWM3_CFG, BIT(0), + 2, &ext_32k, &ext_26m); + +SCI_CLK_ADD(clk_efuse, 0, REG_AON_APB_APB_EB0, BIT(13), + 0, 0, 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_dap, 0, REG_AON_APB_APB_EB0, BIT(30), + 0, 0, REG_AON_CLK_CA7_DAP_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_76m8, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_ts, 0, REG_AON_APB_APB_EB0, BIT(28), + 0, 0, REG_AON_CLK_CA7_TS_CFG, BIT(0)|BIT(1), + 4, &ext_32k, &ext_26m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_mspi, 0, REG_AON_APB_APB_EB0, BIT(23), + 0, 0, REG_AON_CLK_MSPI_CFG, BIT(0)|BIT(1), + 3, &clk_52m, &clk_76m8, &clk_96m); + +SCI_CLK_ADD(clk_i2c, 0, REG_AON_APB_APB_EB0, BIT(31), + 0, 0, REG_AON_CLK_I2C_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_avs0, 0, REG_AON_APB_APB_EB0, BIT(6), + 0, 0, REG_AON_CLK_AVS0_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_avs1, 0, REG_AON_APB_APB_EB0, BIT(7), + 0, 0, REG_AON_CLK_AVS1_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + diff --git a/include/soc/sprd/__sc8830_dmc_dfs.h b/include/soc/sprd/__sc8830_dmc_dfs.h new file mode 100644 index 00000000..6afc127c --- /dev/null +++ b/include/soc/sprd/__sc8830_dmc_dfs.h @@ -0,0 +1,166 @@ + #ifndef __SC8830_DMC_DFS_H +#define __SC8830_DMC_DFS_H +#define EMC_DLL_SWITCH_DISABLE_MODE 0x0 +#define EMC_DLL_SWITCH_ENABLE_MODE 0x1 +#define EMC_DLL_NOT_SWITCH_MODE 0x2 +#define EMC_DLL_MODE_MASK (0x3) +#define EMC_CLK_DIV_OFFSET 2 + +#define EMC_FREQ_SWITCH_STATUS_OFFSET (4) +#define EMC_FREQ_SWITCH_COMPLETE (1) +#define EMC_FREQ_SWITCH_STATUS_MASK (0xf << EMC_FREQ_SWITCH_STATUS_OFFSET) + +#define EMC_DDR_TYPE_LPDDR1 0 +#define EMC_DDR_TYPE_LPDDR2 1 +#define EMC_DDR_TYPE_LPDDR3 2 +#define EMC_DDR_TYPE_DDR2 3 +#define EMC_DDR_TYPE_DDR3 4 +#define EMC_DDR_TYPE_OFFSET 8 +#define EMC_DDR_TYPE_MASK (0xf << EMC_DDR_TYPE_OFFSET) + +#define EMC_CLK_FREQ_OFFSET (12) +#define EMC_CLK_FREQ_MASK (0xfff << EMC_CLK_FREQ_OFFSET) + +#define EMC_FREQ_NORMAL_SCENE 0x0 //normal lcd power off +#define EMC_FREQ_MP4_SENE 0x1 //play mp4 mode +#define EMC_FREQ_NORMAL_SWITCH_SENE 0x02 +#define EMC_FREQ_DEEP_SLEEP_SENE 0x03 +#define EMC_FREQ_RESUME_SENE 0x04 +#define EMC_FREQ_SENE_OFFSET 24 +#define EMC_FREQ_SENE_MASK (0xf << EMC_FREQ_SENE_OFFSET) + +#define EMC_BSP_BPS_200_CLR 0x0 +#define EMC_BSP_BPS_200_SET 0x1 +#define EMC_BSP_BPS_200_NOT_CHANGE 0x2 +#define EMC_BSP_BPS_200_OFFSET 28 +#define EMC_BSP_BPS_200_MASK (0xf << EMC_BSP_BPS_200_OFFSET) + +#define EMC_PARAM_IDX_OFFSET 28 +#define EMC_PARAM_IDX_MASK (0XF << EMC_PARAM_IDX_OFFSET) +#define DMC_CHANGE_FREQ_WAIT_TIMEOUT 100 +typedef struct +{ + u32 ddr_clk; + //umctl reg + u32 umctl2_rfshtmg; + u32 umctl2_init0; + u32 umctl2_init1; + u32 umctl2_init2; + u32 umctl2_init3; + u32 umctl2_init4; + u32 umctl2_init5; + u32 umctl2_dramtmg0; + u32 umctl2_dramtmg1; + u32 umctl2_dramtmg2; + u32 umctl2_dramtmg3; + u32 umctl2_dramtmg4; + u32 umctl2_dramtmg5; + u32 umctl2_dramtmg6; + u32 umctl2_dramtmg7; + u32 umctl2_dramtmg8; + u32 umctl2_dfitmg0; + u32 umctl2_dfitmg1; + //publ reg + u32 publ_ptr0; + u32 publ_ptr1; + u32 publ_dtpr0; + u32 publ_dtpr1; + u32 publ_dtpr2; + u32 publ_mr0; + u32 publ_mr1; + u32 publ_mr2; + u32 publ_mr3; + u32 publ_dx0gcr; + u32 publ_dx1gcr; + u32 publ_dx2gcr; + u32 publ_dx3gcr; + u32 publ_dx0dqstr; + u32 publ_dx1dqstr; + u32 publ_dx2dqstr; + u32 publ_dx3dqstr; +}ddr_dfs_val_t; + +typedef struct +{ + u32 ddr_clk; + + //umctl reg + u32 umctl_rfshtmg; + u32 umctl_dramtmg0; + u32 umctl_dramtmg1; + u32 umctl_dramtmg2; + u32 umctl_dramtmg3; + u32 umctl_dramtmg4; + u32 umctl_dramtmg5; + u32 umctl_dramtmg7; + u32 umctl_dramtmg8; + u32 umctl_dfitmg0; + u32 umctl_init3; + u32 umctl_zqctl0; + u32 umctl_zqctl1; + + //publ reg + u32 publ_mr2; + u32 publ_dx0gtr; + u32 publ_dx1gtr; + u32 publ_dx2gtr; + u32 publ_dx3gtr; + u32 publ_pgcr3; + u32 publ_acmdlr; + u32 publ_dx0mdlr; + u32 publ_dx1mdlr; + u32 publ_dx2mdlr; + u32 publ_dx3mdlr; + u32 publ_aclcdlr; + u32 publ_dx0lcdlr0; + u32 publ_dx1lcdlr0; + u32 publ_dx2lcdlr0; + u32 publ_dx3lcdlr0; + u32 publ_dx0lcdlr1; + u32 publ_dx1lcdlr1; + u32 publ_dx2lcdlr1; + u32 publ_dx3lcdlr1; + u32 publ_dx0lcdlr2; + u32 publ_dx1lcdlr2; + u32 publ_dx2lcdlr2; + u32 publ_dx3lcdlr2; + u32 publ_dsgcr; + u32 publ_dtpr0; + u32 publ_dtpr1; + u32 publ_dtpr2; + u32 publ_dtpr3; + u32 resevered; +}ddr_dfs_v2_t; + +typedef struct +{ + u32 ddr_clk; + + u32 publ_acmdlr; + u32 publ_dx0mdlr; + u32 publ_dx1mdlr; + u32 publ_dx2mdlr; + u32 publ_dx3mdlr; + + u32 publ_aclcdlr; + u32 publ_dx0lcdlr0; + u32 publ_dx1lcdlr0; + u32 publ_dx2lcdlr0; + u32 publ_dx3lcdlr0; + u32 publ_dx0lcdlr1; + u32 publ_dx1lcdlr1; + u32 publ_dx2lcdlr1; + u32 publ_dx3lcdlr1; + u32 publ_dx0lcdlr2; + u32 publ_dx1lcdlr2; + u32 publ_dx2lcdlr2; + u32 publ_dx3lcdlr2; +} publ_calc_t; + +#define AP_DMC_DFS_MAX_REQ 3 +#define AP_UNVALID_REQ 0 +struct dmc_req_array { + /*if the req[n] is 0 the req[n] is the last request from AP*/ + u32 req[AP_DMC_DFS_MAX_REQ]; +}; +#endif //__SC8830_DMC_DFS_H diff --git a/include/soc/sprd/__sc8830_regulator_map.h b/include/soc/sprd/__sc8830_regulator_map.h new file mode 100644 index 00000000..f07e09cc --- /dev/null +++ b/include/soc/sprd/__sc8830_regulator_map.h @@ -0,0 +1,135 @@ +/* + * Copyright (C) 2013 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +/* + * Regulator (0)Name, Regulator (1)Type, Power Off (2)Ctrl and (3)Bit, Power On (4)Ctrl and (5)Bit, Sleep (6)Ctrl and (7)Bit, + * Voltage Trimming (8)Ctrl and (9)Bits, Calibration (10)Ctrl and (11)Bits, + * Voltage (12)Default, Voltage (13)Ctrl and (14)Bits, Voltage Select (15)Count and Voltage (16)List[ ... ...] + */ +#if defined(CONFIG_ARCH_SCX15) +#else + + SCI_REGU_REG(vddcore, 2, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(9), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(9), 0, 0, + ANA_REG_GLB_DCDC_CORE_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(16)|BIT(18)|BIT(19), + 0, ANA_REG_GLB_DCDC_CORE_ADI, BIT(5)|BIT(6)|BIT(7), 8, 1100, 700, 800, 900, 1000, 650, 1200, 1300); + + SCI_REGU_REG(vddarm, 2, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(10), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(10), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(9), + ANA_REG_GLB_DCDC_ARM_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(17)|BIT(18)|BIT(19), + 0, ANA_REG_GLB_DCDC_ARM_ADI, BIT(5)|BIT(6)|BIT(7), 8, 1100, 700, 800, 900, 1000, 650, 1200, 1300); + + SCI_REGU_REG(vddmem, 2, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(11), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(11), 0, 0, + ANA_REG_GLB_DCDC_MEM_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(16)|BIT(17)|BIT(18)|BIT(19), + 0, ANA_REG_GLB_DCDC_MEM_ADI, BIT(5), 2, 1200, 1250); + + SCI_REGU_REG(vddldo, 2, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(12), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(12), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(12), + ANA_REG_GLB_DCDC_GEN_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(20), + 2400, ANA_REG_GLB_DCDC_GEN_ADI, BIT(5)|BIT(6)|BIT(7), 8, 2200, 1800, 1900, 2000, 2100, 2300, 2400, 2500); + + SCI_REGU_REG(vddwpa, 2, ANA_REG_GLB_LDO_PD_CTRL, BIT(11), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL0, BIT(11), + ANA_REG_GLB_DCDC_WPA_ADI, BIT(0)|BIT(1)|BIT(2), ANA_REG_GLB_LDO_CAL_SEL, BIT(16)|BIT(20), + 0, 0, 0, 0); + + SCI_REGU_REG(vddwrf, 2, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(13), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(13), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(10), + ANA_REG_GLB_DCDC_WRF_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(17)|BIT(20), + 0, ANA_REG_GLB_DCDC_WRF_ADI, BIT(5)|BIT(6), 4, 2600, 2700, 2800, 2900); + + SCI_REGU_REG(vdd18, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(1), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(1), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(0), + ANA_REG_GLB_LDO_CAL_CTRL0, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(6)|BIT(7)|BIT(17)|BIT(18)|BIT(20), + 1800, ANA_REG_GLB_LDO_V_CTRL0, BIT(0)|BIT(1), 4, 1500, 1800, 1300, 1200); + + SCI_REGU_REG(vdd28, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(2), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(2), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(1), + ANA_REG_GLB_LDO_CAL_CTRL0, BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_LDO_CAL_SEL, BIT(8)|BIT(10)|BIT(16)|BIT(18)|BIT(20), + 2800, ANA_REG_GLB_LDO_V_CTRL0, BIT(2)|BIT(3), 4, 2800, 3000, 2650, 1800); + + SCI_REGU_REG(vdd25, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(3), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(3), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(2), + ANA_REG_GLB_LDO_CAL_CTRL0, BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_CAL_SEL, BIT(9)|BIT(10)|BIT(16)|BIT(18)|BIT(20), + 2500, ANA_REG_GLB_LDO_V_CTRL0, BIT(4)|BIT(5), 4, 2500, 2750, 3000, 2900); + + SCI_REGU_REG(vddrf0, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(4), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(4), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(3), + ANA_REG_GLB_LDO_CAL_CTRL1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(11)|BIT(13)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 2850, ANA_REG_GLB_LDO_V_CTRL0, BIT(6)|BIT(7), 4, 2850, 2950, 2500, 1800); + + SCI_REGU_REG(vddrf1, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(5), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(5), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(4), + ANA_REG_GLB_LDO_CAL_CTRL1, BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_LDO_CAL_SEL, BIT(13)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 2850, ANA_REG_GLB_LDO_V_CTRL0, BIT(8)|BIT(9), 4, 2850, 2950, 2500, 1800); + + SCI_REGU_REG(vddrf2, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(6), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(6), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(5), + ANA_REG_GLB_LDO_CAL_CTRL1, BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_CAL_SEL, BIT(11)|BIT(12)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 2850, ANA_REG_GLB_LDO_V_CTRL0, BIT(10)|BIT(11), 4, 2850, 2950, 2500, 1800); + + SCI_REGU_REG(vddemmcio, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(7), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(7), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(6), + ANA_REG_GLB_LDO_CAL_CTRL2, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(7)|BIT(17)|BIT(18)|BIT(20), + 1800, ANA_REG_GLB_LDO_V_CTRL0, BIT(12)|BIT(13), 4, 1500, 1800, 1300, 1200); + + SCI_REGU_REG(vddemmccore, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(8), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(8), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(7), + ANA_REG_GLB_LDO_CAL_CTRL2, BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_LDO_CAL_SEL, BIT(10)|BIT(16)|BIT(18)|BIT(20), + 3000, ANA_REG_GLB_LDO_V_CTRL0, BIT(14)|BIT(15), 4, 2800, 3000, 2500, 1800); + + SCI_REGU_REG(avdd18, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(0), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(0), + ANA_REG_GLB_LDO_CAL_CTRL3, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(5)|BIT(7)|BIT(17)|BIT(18)|BIT(20), + 1800, ANA_REG_GLB_LDO_V_CTRL1, BIT(0)|BIT(1), 4, 1500, 1800, 1300, 1200); + + SCI_REGU_REG(vddsd, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(1), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(1), + ANA_REG_GLB_LDO_CAL_CTRL3, BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_LDO_CAL_SEL, BIT(11)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 2800, ANA_REG_GLB_LDO_V_CTRL1, BIT(2)|BIT(3), 4, 2800, 3000, 2500, 1800); + + SCI_REGU_REG(vddsim0, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(2), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(2), + ANA_REG_GLB_LDO_CAL_CTRL4, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(9)|BIT(16)|BIT(18)|BIT(20), + 1800, ANA_REG_GLB_LDO_V_CTRL1, BIT(4)|BIT(5), 4, 1800, 2900, 3000, 3100); + + SCI_REGU_REG(vddsim1, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(3), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(3), + ANA_REG_GLB_LDO_CAL_CTRL4, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(9)|BIT(16)|BIT(18)|BIT(20), + 0, ANA_REG_GLB_LDO_V_CTRL1, BIT(6)|BIT(7), 4, 1800, 2900, 3000, 3100); + + SCI_REGU_REG(vddsim2, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(4), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(4), + ANA_REG_GLB_LDO_CAL_CTRL4, BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_LDO_CAL_SEL, BIT(8)|BIT(9)|BIT(16)|BIT(18)|BIT(20), + 1800, ANA_REG_GLB_LDO_V_CTRL1, BIT(8)|BIT(9), 4, 2800, 3000, 2500, 1800); + + SCI_REGU_REG(vddcama, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(5), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(5), + ANA_REG_GLB_LDO_CAL_CTRL4, BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_CAL_SEL, BIT(12)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 2800, ANA_REG_GLB_LDO_V_CTRL2, BIT(0)|BIT(1), 4, 2800, 3000, 2500, 1800); + + SCI_REGU_REG(vddcamd, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(6), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(6), + ANA_REG_GLB_LDO_CAL_CTRL5, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(5)|BIT(6)|BIT(17)|BIT(18)|BIT(20), + 1500, ANA_REG_GLB_LDO_V_CTRL2, BIT(2)|BIT(3), 4, 1500, 1800, 1300, 1200); + + SCI_REGU_REG(vddcamio, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(7), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(7), + ANA_REG_GLB_LDO_CAL_CTRL5, BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_LDO_CAL_SEL, BIT(5)|BIT(17)|BIT(18)|BIT(20), + 1800, ANA_REG_GLB_LDO_V_CTRL2, BIT(4)|BIT(5), 4, 1500, 1800, 2500, 2800); + + SCI_REGU_REG(vddcammot, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(8), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(8), + ANA_REG_GLB_LDO_CAL_CTRL5, BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_CAL_SEL, BIT(12)|BIT(13)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 2800, ANA_REG_GLB_LDO_V_CTRL2, BIT(6)|BIT(7), 4, 3000, 3300, 2800, 1800); + + SCI_REGU_REG(vddusb, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(9), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(9), + ANA_REG_GLB_LDO_CAL_CTRL2, BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_CAL_SEL, BIT(8)|BIT(9)|BIT(10)|BIT(16)|BIT(18)|BIT(20), + 3300, ANA_REG_GLB_LDO_V_CTRL2, BIT(8)|BIT(9), 4, 3300, 3400, 3200, 3100); + + SCI_REGU_REG(vddclsg, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(10), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(10), + ANA_REG_GLB_LDO_CAL_CTRL6, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(6)|BIT(17)|BIT(18)|BIT(20), + 0, ANA_REG_GLB_LDO_V_CTRL2, BIT(10)|BIT(11), 4, 1500, 1800, 1300, 1200); + + SCI_REGU_REG(chg_pump, 0, ANA_REG_GLB_CHGR_CTRL2, BIT(8), 0, 0, 0, 0, + ANA_REG_GLB_CHGR_CTRL2, BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13), 0, 0, + 5000, ANA_REG_GLB_CHGR_CTRL0, BIT(2)|BIT(3), 4, 5000, 5200, 5300, 4800); + + SCI_REGU_REG(led_flash, 4, 0, 0, ANA_REG_GLB_FLASH_CTRL, BIT(15), 0, 0, + ANA_REG_GLB_FLASH_CTRL, BIT(4)|BIT(5)|BIT(6), 0, 0, + 4000, ANA_REG_GLB_FLASH_CTRL, BIT(0)|BIT(1)|BIT(2)|BIT(3), 0); +#endif + diff --git a/include/soc/sprd/__sprd_audio_power.h b/include/soc/sprd/__sprd_audio_power.h new file mode 100644 index 00000000..33219b82 --- /dev/null +++ b/include/soc/sprd/__sprd_audio_power.h @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2013 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARCH_AUDIO_POWER_H +#define __ASM_ARCH_AUDIO_POWER_H + +#define FIXED_AUDIO_POWER 1 + +/* power setting */ +static inline int arch_audio_power_write_mask(int reg, int val, int mask) +{ + int ret = 0; + +#if FIXED_AUDIO_POWER + ret = arch_audio_codec_write_mask(reg, val, mask); +#endif + + return ret; +} + +static inline int arch_audio_power_write(int reg, int val) +{ + int ret = 0; + +#if FIXED_AUDIO_POWER + ret = arch_audio_codec_write(reg, val); +#endif + + return ret; +} + +static inline int arch_audio_power_read(int reg) +{ + int ret = 0; + +#if FIXED_AUDIO_POWER + ret = arch_audio_codec_read(reg); +#endif + + return ret; +} + +#endif diff --git a/include/soc/sprd/__sprd_audio_sc8825.h b/include/soc/sprd/__sprd_audio_sc8825.h new file mode 100644 index 00000000..f8d3517e --- /dev/null +++ b/include/soc/sprd/__sprd_audio_sc8825.h @@ -0,0 +1,785 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARCH_AUDIO_GLB_SC8825_H +#define __ASM_ARCH_AUDIO_GLB_SC8825_H + +#ifndef __ASM_ARCH_AUDIO_GLB_H +#error "Don't include this file directly, include <mach/sprd-audio.h>" +#endif + +#include <linux/delay.h> +#include <mach/hardware.h> +#include <mach/sci.h> +#include <mach/sci_glb_regs.h> +#include <mach/adi.h> +#include <mach/dma.h> +#include <mach/irqs.h> + +/* OKAY, this is for other else owner + if you do not care the audio config + you can set FIXED_AUDIO to 0 + for compile happy. +*/ +/* FIXME */ +#define FIXED_AUDIO 1 + +enum { + AUDIO_NO_CHANGE, + AUDIO_TO_DSP_CTRL, + AUDIO_TO_ARM_CTRL, + AUDIO_TO_ARM_CP_CTRL, +}; + +#if FIXED_AUDIO +#define VBC_BASE SPRD_VB_BASE +#define CODEC_DP_BASE (SPRD_VB_BASE + 0x1000) +#if ((SPRD_MISC_BASE + 0x0700) & BIT(15)) +#define CODEC_AP_BASE ((SPRD_MISC_BASE + 0x0700) & ~BIT(15)) +#define CODEC_AP_OFFSET (0x8000) +#else +#define CODEC_AP_BASE (SPRD_MISC_BASE + 0x0700) +#define CODEC_AP_OFFSET (0) +#endif +#define VBC_PHY_BASE SPRD_VB_PHYS +#define CODEC_DP_PHY_BASE (SPRD_VB_PHYS + 0x1000) +#define CODEC_AP_PHY_BASE (SPRD_MISC_PHYS + 0x0700) +#define CODEC_AP_IRQ (IRQ_ANA_AUD_INT) +#define CODEC_DP_IRQ (IRQ_REQ_AUD_INT) + +#define SPRD_IRAM_ALL_PHYS (0x00000000) +#define SPRD_IRAM_ALL_SIZE SZ_32K + +#else + +#define VBC_BASE (0) +#define CODEC_DP_BASE (0) +#define CODEC_AP_BASE (0) +#define VBC_PHY_BASE (0) +#define CODEC_DP_PHY_BASE (0) +#define CODEC_AP_PHY_BASE (0) +#define CODEC_AP_IRQ (0) +#define CODEC_DP_IRQ (0) +#define SPRD_IRAM_ALL_PHYS (0) +#define SPRD_IRAM_ALL_SIZE (0) +#endif + +/* ------------------------------------------------------------------------- */ + +/* NOTE: all function maybe will call by atomic funtion + don NOT any complex oprations. Just register. +return + 0: unchanged + 1: changed + ohter error +*/ +/* vbc setting */ + +static inline int arch_audio_vbc_reg_enable(void) +{ + int ret = 0; + +#if FIXED_AUDIO + sci_glb_set(REG_GLB_GEN1, BIT_VBC_EN); +#endif + + return ret; +} + +static inline int arch_audio_vbc_reg_disable(void) +{ + int ret = 0; + +#if FIXED_AUDIO + sci_glb_clr(REG_GLB_GEN1, BIT_VBC_EN); +#endif + + return ret; +} + +static inline int arch_audio_vbc_enable(void) +{ + int ret = 0; + +#if FIXED_AUDIO + sci_glb_set(REG_GLB_BUSCLK, BIT_ARM_VBC_ANAON); +#endif + + return ret; +} + +static inline int arch_audio_vbc_disable(void) +{ + int ret = 0; + +#if FIXED_AUDIO + sci_glb_clr(REG_GLB_BUSCLK, BIT_ARM_VBC_ANAON); +#endif + + return ret; +} + +static inline int arch_audio_vbc_reset(void); +static inline int arch_audio_vbc_switch(int master) +{ + int ret = 0; + +#if FIXED_AUDIO + switch (master) { + case AUDIO_TO_ARM_CTRL: + sci_glb_set(REG_GLB_BUSCLK, BIT_ARM_VBC_ACC); + sci_glb_clr(REG_GLB_BUSCLK, BIT_ARM_VBC_ACC_CP); + arch_audio_vbc_reset(); + break; + case AUDIO_TO_ARM_CP_CTRL: + arch_audio_vbc_reset(); + sci_glb_set(REG_GLB_BUSCLK, BIT_ARM_VBC_ACC); + sci_glb_set(REG_GLB_BUSCLK, BIT_ARM_VBC_ACC_CP); + break; + case AUDIO_TO_DSP_CTRL: + arch_audio_vbc_reset(); + sci_glb_clr(REG_GLB_BUSCLK, BIT_ARM_VBC_ACC); + break; + case AUDIO_NO_CHANGE: + ret = sci_glb_read(REG_GLB_BUSCLK, BIT_ARM_VBC_ACC); + if (ret == 0) { + ret = AUDIO_TO_DSP_CTRL; + } else { + ret = sci_glb_read(REG_GLB_BUSCLK, BIT_ARM_VBC_ACC_CP); + if (ret == 0) + ret = AUDIO_TO_ARM_CTRL; + else + ret = AUDIO_TO_ARM_CP_CTRL; + } + break; + default: + ret = -ENODEV; + break; + } +#endif + + return ret; +} + +static inline int arch_audio_vbc_ad_enable(int chan) +{ + int ret = 0; + +#if FIXED_AUDIO + switch (chan) { + case 0: + sci_glb_set(REG_GLB_BUSCLK, BIT_ARM_VBC_AD0ON); + break; + case 1: + sci_glb_set(REG_GLB_BUSCLK, BIT_ARM_VBC_AD1ON); + break; + default: + ret = -ENODEV; + break; + } +#endif + + return ret; +} + +static inline int arch_audio_vbc_ad_disable(int chan) +{ + int ret = 0; + +#if FIXED_AUDIO + switch (chan) { + case 0: + sci_glb_clr(REG_GLB_BUSCLK, BIT_ARM_VBC_AD0ON); + break; + case 1: + sci_glb_clr(REG_GLB_BUSCLK, BIT_ARM_VBC_AD1ON); + break; + default: + ret = -ENODEV; + break; + } +#endif + + return ret; +} + +static inline int arch_audio_vbc_da_enable(int chan) +{ + int ret = 0; + +#if FIXED_AUDIO + switch (chan) { + case 0: + sci_glb_set(REG_GLB_BUSCLK, BIT_ARM_VBC_DA0ON); + break; + case 1: + sci_glb_set(REG_GLB_BUSCLK, BIT_ARM_VBC_DA1ON); + break; + default: + ret = -ENODEV; + break; + } +#endif + + return ret; +} + +static inline int arch_audio_vbc_da_disable(int chan) +{ + int ret = 0; + +#if FIXED_AUDIO + switch (chan) { + case 0: + sci_glb_clr(REG_GLB_BUSCLK, BIT_ARM_VBC_DA0ON); + break; + case 1: + sci_glb_clr(REG_GLB_BUSCLK, BIT_ARM_VBC_DA1ON); + break; + default: + ret = -ENODEV; + break; + } +#endif + + return ret; +} + +static inline int arch_audio_vbc_da_dma_info(int chan) +{ + int ret = 0; + +#if FIXED_AUDIO + switch (chan) { + case 0: + ret = DMA_VB_DA0; + break; + case 1: + ret = DMA_VB_DA1; + break; + default: + ret = -ENODEV; + break; + } +#endif + + return ret; +} + +static inline int arch_audio_vbc_ad_dma_info(int chan) +{ + int ret = 0; + +#if FIXED_AUDIO + switch (chan) { + case 0: + ret = DMA_VB_AD0; + break; + case 1: + ret = DMA_VB_AD1; + break; + default: + ret = -ENODEV; + break; + } +#endif + + return ret; +} + +static inline int arch_audio_vbc_reset(void) +{ + int ret = 0; + +#if FIXED_AUDIO + sci_glb_set(REG_GLB_SOFT_RST, BIT_VBC_RST); + udelay(10); + sci_glb_clr(REG_GLB_SOFT_RST, BIT_VBC_RST); +#endif + + return ret; +} + +/* some SOC will move this into vbc module */ +static inline int arch_audio_vbc_ad_int_clr(void) +{ + int ret = 0; + +#if FIXED_AUDIO +#endif + + return ret; +} + +/* some SOC will move this into vbc module */ +static inline int arch_audio_vbc_da_int_clr(void) +{ + int ret = 0; + +#if FIXED_AUDIO +#endif + + return ret; +} + +/* some SOC will move this into vbc module */ +static inline int arch_audio_vbc_is_ad_int(void) +{ + int ret = 0; + +#if FIXED_AUDIO +#endif + + return ret; +} + +/* some SOC will move this into vbc module */ +static inline int arch_audio_vbc_is_da_int(void) +{ + int ret = 0; + +#if FIXED_AUDIO +#endif + + return ret; +} + +/* ------------------------------------------------------------------------- */ + +/* codec setting */ +static inline int arch_audio_codec_write_mask(int reg, int val, int mask) +{ + int ret = 0; + +#if FIXED_AUDIO + ret = sci_adi_write(reg + CODEC_AP_OFFSET, val, mask); +#endif + + return ret; +} + +static inline int arch_audio_codec_write(int reg, int val) +{ + int ret = 0; + +#if FIXED_AUDIO + ret = sci_adi_write(reg + CODEC_AP_OFFSET, val, 0xFFFF); +#endif + + return ret; +} + +static inline int arch_audio_codec_read(int reg) +{ + int ret = 0; + +#if FIXED_AUDIO + ret = sci_adi_read(reg + CODEC_AP_OFFSET); +#endif + + return ret; +} + +static inline int arch_audio_codec_audif_enable(int auto_clk) +{ + int ret = 0; + +#if FIXED_AUDIO + if (auto_clk) { + sci_glb_clr(REG_GLB_GEN1, BIT_AUD_IF_EB); + sci_glb_set(REG_GLB_GEN1, BIT_AUDIF_AUTO_EN); + } else { + sci_glb_set(REG_GLB_GEN1, BIT_AUD_IF_EB); + sci_glb_clr(REG_GLB_GEN1, BIT_AUDIF_AUTO_EN); + } +#endif + + return ret; +} + +static inline int arch_audio_codec_audif_disable(void) +{ + int ret = 0; + +#if FIXED_AUDIO + sci_glb_clr(REG_GLB_GEN1, BIT_AUDIF_AUTO_EN); + sci_glb_clr(REG_GLB_GEN1, BIT_AUD_IF_EB); +#endif + + return ret; +} + +static inline int arch_audio_codec_digital_reg_enable(void) +{ + int ret = 0; + +#if FIXED_AUDIO + sci_glb_set(REG_GLB_GEN1, BIT_AUD_TOP_EB); + if (ret >= 0) + arch_audio_codec_audif_enable(1); +#endif + + return ret; +} + +static inline int arch_audio_codec_digital_reg_disable(void) +{ + int ret = 0; + +#if FIXED_AUDIO + arch_audio_codec_audif_disable(); + sci_glb_clr(REG_GLB_GEN1, BIT_AUD_TOP_EB); +#endif + + return ret; +} + +static inline int arch_audio_codec_analog_reg_enable(void) +{ + int ret = 0; + +#if FIXED_AUDIO + ret = + sci_adi_write(ANA_REG_GLB_ARM_AUD_CLK_RST, BIT_AUD_ARM_EN, + BIT_AUD_ARM_EN); + + if (ret >= 0) { + /* Disable Sleep Control Audio Power */ + ret = sci_adi_write(ANA_REG_GLB_LDO_SLP_CTRL1, 0, 0x1FE0); + } +#endif + + return ret; +} + +static inline int arch_audio_codec_analog_reg_disable(void) +{ + int ret = 0; + +#if FIXED_AUDIO + ret = sci_adi_write(ANA_REG_GLB_ARM_AUD_CLK_RST, 0, BIT_AUD_ARM_EN); +#endif + + return ret; +} + +static inline int arch_audio_codec_analog_enable(void) +{ + int ret = 0; + +#if FIXED_AUDIO + int mask = BIT_AUD6M5_CLK_TX_INV_ARM_EN | + BIT_RTC_AUD_ARM_EN | BIT_CLK_AUD_6M5_ARM_EN | BIT_CLK_AUDIF_ARM_EN; + ret = sci_adi_write(ANA_REG_GLB_ARM_AUD_CLK_RST, mask, mask); +#endif + + return ret; +} + +static inline int arch_audio_codec_digital_enable(void) +{ + int ret = 0; + +#if FIXED_AUDIO +#endif + + return ret; +} + +static inline int arch_audio_codec_analog_disable(void) +{ + int ret = 0; + +#if FIXED_AUDIO + int mask = + BIT_RTC_AUD_ARM_EN | BIT_CLK_AUD_6M5_ARM_EN | BIT_CLK_AUDIF_ARM_EN; + ret = sci_adi_write(ANA_REG_GLB_ARM_AUD_CLK_RST, 0, mask); +#endif + + return ret; +} + +static inline int arch_audio_codec_digital_disable(void) +{ + int ret = 0; + +#if FIXED_AUDIO +#endif + + return ret; +} + +static inline int arch_audio_codec_switch(int master) +{ + int ret = 0; + +#if FIXED_AUDIO + switch (master) { + case AUDIO_TO_ARM_CTRL: + sci_glb_set(REG_GLB_GEN1, BIT_AUD_CTL_SEL | BIT_AUD_CLK_SEL); + sci_glb_set(REG_GLB_BUSCLK, BIT_ARM_VB_SEL); + ret = + sci_adi_write(ANA_REG_GLB_ARM_AUD_CLK_RST, + BIT_AUD_ARM_ACC, BIT_AUD_ARM_ACC); + break; + case AUDIO_TO_DSP_CTRL: + sci_glb_clr(REG_GLB_GEN1, BIT_AUD_CTL_SEL | BIT_AUD_CLK_SEL); + sci_glb_clr(REG_GLB_BUSCLK, BIT_ARM_VB_SEL); + ret = + sci_adi_write(ANA_REG_GLB_ARM_AUD_CLK_RST, 0, + BIT_AUD_ARM_ACC); + break; + case AUDIO_NO_CHANGE: + ret = + sci_adi_read(ANA_REG_GLB_ARM_AUD_CLK_RST) & BIT_AUD_ARM_ACC; + if (ret == 0) + ret = AUDIO_TO_DSP_CTRL; + else + ret = AUDIO_TO_ARM_CTRL; + break; + default: + ret = -ENODEV; + break; + } +#endif + + return ret; +} + +static inline int arch_audio_codec_reset(void) +{ + int ret = 0; + +#if FIXED_AUDIO + int mask = + BIT_AUD_ARM_SOFT_RST | BIT_AUDTX_ARM_SOFT_RST | + BIT_AUDRX_ARM_SOFT_RST; + sci_glb_set(REG_GLB_SOFT_RST, BIT_AUD_TOP_RST); + sci_glb_set(REG_GLB_SOFT_RST, BIT_AUD_IF_RST); + ret = sci_adi_write(ANA_REG_GLB_ARM_AUD_CLK_RST, mask, mask); + udelay(10); + sci_glb_clr(REG_GLB_SOFT_RST, BIT_AUD_TOP_RST); + sci_glb_clr(REG_GLB_SOFT_RST, BIT_AUD_IF_RST); + if (ret >= 0) + ret = sci_adi_write(ANA_REG_GLB_ARM_AUD_CLK_RST, 0, mask); +#endif + + return ret; +} + +static inline int arch_audio_codec_digital_reset(void) +{ + int ret = 0; + +#if FIXED_AUDIO +#endif + + return ret; +} + +static inline int arch_audio_codec_analog_reset(void) +{ + int ret = 0; + +#if FIXED_AUDIO +#endif + + return ret; +} + +/* ------------------------------------------------------------------------- */ + +/* i2s setting */ +static inline const char *arch_audio_i2s_clk_name(int id) +{ +#if FIXED_AUDIO + switch (id) { + case 0: + return "clk_iis0"; + break; + case 1: + return "clk_iis1"; + break; + default: + break; + } +#endif + return NULL; +} + +static inline int arch_audio_i2s_enable(int id) +{ + int ret = 0; + +#if FIXED_AUDIO + switch (id) { + case 0: + sci_glb_set(REG_GLB_GEN0, BIT_IIS0_EB); + break; + case 1: + sci_glb_set(REG_GLB_GEN0, BIT_IIS1_EB); + break; + default: + ret = -ENODEV; + break; + } +#endif + + return ret; +} + +static inline int arch_audio_i2s_disable(int id) +{ + int ret = 0; + +#if FIXED_AUDIO + switch (id) { + case 0: + sci_glb_clr(REG_GLB_GEN0, BIT_IIS0_EB); + break; + case 1: + sci_glb_clr(REG_GLB_GEN0, BIT_IIS1_EB); + break; + default: + ret = -ENODEV; + break; + } +#endif + + return ret; +} + +static inline int arch_audio_i2s_tx_dma_info(int id) +{ + int ret = 0; + +#if FIXED_AUDIO + switch (id) { + case 0: + ret = DMA_IIS_TX; + break; + case 1: + ret = DMA_IIS1_TX; + break; + default: + ret = -ENODEV; + break; + } +#endif + + return ret; +} + +static inline int arch_audio_i2s_rx_dma_info(int id) +{ + int ret = 0; + +#if FIXED_AUDIO + switch (id) { + case 0: + ret = DMA_IIS_RX; + break; + case 1: + ret = DMA_IIS1_RX; + break; + default: + ret = -ENODEV; + break; + } + +#endif + + return ret; +} + +static inline int arch_audio_i2s_reset(int id) +{ + int ret = 0; + +#if FIXED_AUDIO + switch (id) { + case 0: + sci_glb_set(REG_GLB_SOFT_RST, BIT_IIS0_RST); + udelay(10); + sci_glb_clr(REG_GLB_SOFT_RST, BIT_IIS0_RST); + break; + case 1: + sci_glb_set(REG_GLB_SOFT_RST, BIT_IIS1_RST); + udelay(10); + sci_glb_clr(REG_GLB_SOFT_RST, BIT_IIS1_RST); + break; + default: + ret = -ENODEV; + break; + } +#endif + + return ret; +} + +static inline int arch_audio_i2s_switch(int id, int master) +{ + int ret = 0; + +#if FIXED_AUDIO + switch (id) { + case 0: + switch (master) { + case AUDIO_TO_ARM_CTRL: + sci_glb_clr(REG_GLB_PCTRL, BIT_IIS0_CTL_SEL); + break; + case AUDIO_TO_DSP_CTRL: + sci_glb_set(REG_GLB_PCTRL, BIT_IIS0_CTL_SEL); + break; + case AUDIO_NO_CHANGE: + ret = sci_glb_read(REG_GLB_PCTRL, BIT_IIS0_CTL_SEL); + if (ret != 0) + ret = AUDIO_TO_DSP_CTRL; + else + ret = AUDIO_TO_ARM_CTRL; + break; + default: + ret = -ENODEV; + break; + } + break; + case 1: + switch (master) { + case AUDIO_TO_ARM_CTRL: + sci_glb_clr(REG_GLB_PCTRL, BIT_IIS1_CTL_SEL); + break; + case AUDIO_TO_DSP_CTRL: + sci_glb_set(REG_GLB_PCTRL, BIT_IIS1_CTL_SEL); + break; + case AUDIO_NO_CHANGE: + ret = sci_glb_read(REG_GLB_PCTRL, BIT_IIS1_CTL_SEL); + if (ret != 0) + ret = AUDIO_TO_DSP_CTRL; + else + ret = AUDIO_TO_ARM_CTRL; + break; + default: + ret = -ENODEV; + break; + } + break; + default: + ret = -ENODEV; + break; + } +#endif + + return ret; +} + +#endif diff --git a/include/soc/sprd/__sprd_audio_sc8830.h b/include/soc/sprd/__sprd_audio_sc8830.h new file mode 100644 index 00000000..82da0ef1 --- /dev/null +++ b/include/soc/sprd/__sprd_audio_sc8830.h @@ -0,0 +1,1007 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARCH_AUDIO_GLB_SCX35_H +#define __ASM_ARCH_AUDIO_GLB_SCX35_H + +#ifndef __ASM_ARCH_AUDIO_GLB_H +#error "Don't include this file directly, include <mach/sprd-audio.h>" +#endif + +#include <linux/delay.h> + +#include <soc/sprd/hardware.h> +#include <soc/sprd/sci.h> +#include <soc/sprd/sci_glb_regs.h> +#include <soc/sprd/adi.h> +#include <soc/sprd/dma.h> +#include <mach/irqs.h> + +/* OKAY, this is for other else owner + if you do not care the audio config + you can set FIXED_AUDIO to 0 + for compile happy. +*/ +/* FIXME */ +#define FIXED_AUDIO 1 + +enum { + AUDIO_NO_CHANGE, + AUDIO_TO_CP0_DSP_CTRL, + AUDIO_TO_CP1_DSP_CTRL, + AUDIO_TO_AP_ARM_CTRL, + AUDIO_TO_ARM_CTRL = AUDIO_TO_AP_ARM_CTRL, + AUDIO_TO_CP0_ARM_CTRL, + AUDIO_TO_CP1_ARM_CTRL, + AUDIO_TO_CP2_ARM_CTRL, +}; + +#if FIXED_AUDIO + +#if 1 +#define CODEC_DP_BASE (0x1000) +#define VBC_BASE (0x1000) +#define CODEC_AP_BASE (0x2000) +#define CODEC_AP_OFFSET (0) + +#define CODEC_DP_BASE_DEFAULT 0x40000000 +#define CODEC_DP_SIZE_DEFAULT SZ_8K + +#define VBC_BASE_DEFAULT 0x40020000 +#define VBC_BASE_SIZE_DEFAULT SZ_4K + SZ_8K + +#define VBC_PHY_BASE 0 +#else +#define VBC_BASE (SPRD_VBC_BASE) + +#define CODEC_DP_BASE SPRD_AUDIO_BASE +#define VBC_PHY_BASE SPRD_VBC_PHYS + +/* CODEC_AP_BASE: the bit15 cann't be 1 for asoc reg.*/ +#if (ANA_AUDCFGA_INT_BASE & BIT(15)) +#define CODEC_AP_BASE (ANA_AUDCFGA_INT_BASE & ~(BIT(15))) +#define CODEC_AP_OFFSET (0x8000) +#else +#define CODEC_AP_BASE (ANA_AUDCFGA_INT_BASE) +#define CODEC_AP_OFFSET (0) +#endif +#endif +/* for CP2 */ +#define VBC_CP2_PHY_BASE (0x02020000) +#define CP2_PHYS_VBDA0 (VBC_CP2_PHY_BASE + 0x0000) +#define CP2_PHYS_VBDA1 (VBC_CP2_PHY_BASE + 0x0004) + +#define CODEC_DP_PHY_BASE SPRD_AUDIO_PHYS +#define CODEC_AP_PHY_BASE (SPRD_ADISLAVE_PHYS + 0x0600) +#define CODEC_AP_IRQ (IRQ_ANA_AUD_INT) +#define CODEC_DP_IRQ (IRQ_REQ_AUD_INT) + +#define SPRD_IRAM_ALL_PHYS (SPRD_IRAM2_PHYS) +#define SPRD_IRAM_ALL_SIZE (SPRD_IRAM2_SIZE) + +#define CLASS_G_LDO_ID "vddclsg" +#endif + +/* ------------------------------------------------------------------------- */ + +/* NOTE: all function maybe will call by atomic funtion + don NOT any complex oprations. Just register. +return + 0: unchanged + 1: changed + ohter error +*/ +/* vbc setting */ + +static inline int arch_audio_vbc_reg_enable(void) +{ + int ret = 0; + +#if FIXED_AUDIO + sci_glb_set(REG_AON_APB_APB_EB0, BIT_VBC_EB); +#endif + + return ret; +} + +static inline int arch_audio_vbc_reg_disable(void) +{ + int ret = 0; + +#if FIXED_AUDIO + sci_glb_clr(REG_AON_APB_APB_EB0, BIT_VBC_EB); +#endif + + return ret; +} + +static inline int arch_audio_vbc_enable(void) +{ + int ret = 0; + +#if FIXED_AUDIO +#endif + + return ret; +} + +static inline int arch_audio_vbc_disable(void) +{ + int ret = 0; + +#if FIXED_AUDIO +#endif + + return ret; +} + +static inline int arch_audio_vbc_reset(void); +static inline int arch_audio_vbc_switch(int master) +{ + int ret = 0; +#if FIXED_AUDIO + int val = 0; + int mask = + BITS_VBC_AFIFO_INT_SYS_SEL(3) | BITS_VBC_DA01_INT_SYS_SEL(3) | + BITS_VBC_AD01_INT_SYS_SEL(3) + | BITS_VBC_AD23_INT_SYS_SEL(3) | BITS_VBC_DA01_DMA_SYS_SEL(3) | + BITS_VBC_AD01_DMA_SYS_SEL(3) + | BITS_VBC_AD23_DMA_SYS_SEL(3); + + if (master != AUDIO_NO_CHANGE) { + sci_glb_set(REG_AON_APB_CP0_WPROT_EN, BIT(6)); + sci_glb_set(REG_AON_APB_CP1_WPROT_EN, BIT(6)); + sci_glb_set(REG_AON_APB_CP2_WPROT_EN, BIT(6)); + } + switch (master) { + case AUDIO_TO_AP_ARM_CTRL: + val = + BITS_VBC_AFIFO_INT_SYS_SEL(0) | BITS_VBC_DA01_INT_SYS_SEL(0) + | BITS_VBC_AD01_INT_SYS_SEL(0) + | BITS_VBC_AD23_INT_SYS_SEL(0) | + BITS_VBC_DA01_DMA_SYS_SEL(0) | BITS_VBC_AD01_DMA_SYS_SEL(0) + | BITS_VBC_AD23_DMA_SYS_SEL(0); + sci_glb_write(REG_AON_APB_VBC_CTRL, val, mask); + sci_glb_clr(REG_AON_APB_AP_WPROT_EN, BIT(6)); + arch_audio_vbc_reset(); + arch_audio_vbc_reg_disable(); + break; + case AUDIO_TO_CP0_DSP_CTRL: + arch_audio_vbc_reset(); + arch_audio_vbc_reg_enable(); + sci_glb_clr(REG_AON_APB_CP0_WPROT_EN, BIT(6)); + val = + BITS_VBC_AFIFO_INT_SYS_SEL(1) | BITS_VBC_DA01_INT_SYS_SEL(1) + | BITS_VBC_AD01_INT_SYS_SEL(1) + | BITS_VBC_AD23_INT_SYS_SEL(1) | + BITS_VBC_DA01_DMA_SYS_SEL(1) | BITS_VBC_AD01_DMA_SYS_SEL(1) + | BITS_VBC_AD23_DMA_SYS_SEL(1); + sci_glb_write(REG_AON_APB_VBC_CTRL, val, mask); + sci_glb_write(REG_AON_APB_VBC_CTRL, 0, + (BIT_VBC_DMA_CP0_ARM_SEL | + BIT_VBC_DMA_CP0_ARM_SEL)); + break; + case AUDIO_TO_CP1_DSP_CTRL: + arch_audio_vbc_reset(); + arch_audio_vbc_reg_enable(); + sci_glb_clr(REG_AON_APB_CP1_WPROT_EN, BIT(6)); + val = + BITS_VBC_AFIFO_INT_SYS_SEL(2) | BITS_VBC_DA01_INT_SYS_SEL(2) + | BITS_VBC_AD01_INT_SYS_SEL(2) + | BITS_VBC_AD23_INT_SYS_SEL(2) | + BITS_VBC_DA01_DMA_SYS_SEL(2) | BITS_VBC_AD01_DMA_SYS_SEL(2) + | BITS_VBC_AD23_DMA_SYS_SEL(2); + sci_glb_write(REG_AON_APB_VBC_CTRL, val, mask); + sci_glb_write(REG_AON_APB_VBC_CTRL, 0, + (BIT_VBC_DMA_CP1_ARM_SEL | + BIT_VBC_DMA_CP1_ARM_SEL)); + break; + case AUDIO_TO_CP0_ARM_CTRL: + arch_audio_vbc_reset(); + arch_audio_vbc_reg_enable(); + sci_glb_clr(REG_AON_APB_CP0_WPROT_EN, BIT(6)); + val = + BITS_VBC_AFIFO_INT_SYS_SEL(1) | BITS_VBC_DA01_INT_SYS_SEL(1) + | BITS_VBC_AD01_INT_SYS_SEL(1) + | BITS_VBC_AD23_INT_SYS_SEL(1) | + BITS_VBC_DA01_DMA_SYS_SEL(1) | BITS_VBC_AD01_DMA_SYS_SEL(1) + | BITS_VBC_AD23_DMA_SYS_SEL(1); + sci_glb_write(REG_AON_APB_VBC_CTRL, + (val | BIT_VBC_INT_CP0_ARM_SEL | + BIT_VBC_DMA_CP0_ARM_SEL), + (mask | BIT_VBC_INT_CP0_ARM_SEL | + BIT_VBC_DMA_CP0_ARM_SEL)); + break; + case AUDIO_TO_CP1_ARM_CTRL: + arch_audio_vbc_reset(); + arch_audio_vbc_reg_enable(); + sci_glb_clr(REG_AON_APB_CP1_WPROT_EN, BIT(6)); + val = + BITS_VBC_AFIFO_INT_SYS_SEL(2) | BITS_VBC_DA01_INT_SYS_SEL(2) + | BITS_VBC_AD01_INT_SYS_SEL(2) + | BITS_VBC_AD23_INT_SYS_SEL(2) | + BITS_VBC_DA01_DMA_SYS_SEL(2) | BITS_VBC_AD01_DMA_SYS_SEL(2) + | BITS_VBC_AD23_DMA_SYS_SEL(2); + sci_glb_write(REG_AON_APB_VBC_CTRL, + (val | BIT_VBC_INT_CP1_ARM_SEL | + BIT_VBC_DMA_CP1_ARM_SEL), + (mask | BIT_VBC_INT_CP1_ARM_SEL | + BIT_VBC_DMA_CP1_ARM_SEL)); + break; + case AUDIO_TO_CP2_ARM_CTRL: + sci_glb_clr(REG_AON_APB_CP2_WPROT_EN, BIT(6)); + val = + BITS_VBC_AFIFO_INT_SYS_SEL(3) | BITS_VBC_DA01_INT_SYS_SEL(3) + | BITS_VBC_AD01_INT_SYS_SEL(3) + | BITS_VBC_AD23_INT_SYS_SEL(3) | + BITS_VBC_DA01_DMA_SYS_SEL(3) | BITS_VBC_AD01_DMA_SYS_SEL(3) + | BITS_VBC_AD23_DMA_SYS_SEL(3); + sci_glb_write(REG_AON_APB_VBC_CTRL, val, mask); + break; + case AUDIO_NO_CHANGE: + ret = + sci_glb_read(REG_AON_APB_VBC_CTRL, + BITS_VBC_DA01_INT_SYS_SEL(3)); + if (ret == BITS_VBC_DA01_INT_SYS_SEL(0)) { + ret = AUDIO_TO_AP_ARM_CTRL; + } else if (ret == BITS_VBC_DA01_INT_SYS_SEL(1)) { + ret = + sci_glb_read(REG_AON_APB_VBC_CTRL, + BIT_VBC_INT_CP0_ARM_SEL); + if (ret) + ret = AUDIO_TO_CP0_ARM_CTRL; + else + ret = AUDIO_TO_CP0_DSP_CTRL; + } else if (ret == BITS_VBC_DA01_INT_SYS_SEL(2)) { + ret = + sci_glb_read(REG_AON_APB_VBC_CTRL, + BIT_VBC_INT_CP1_ARM_SEL); + if (ret) + ret = AUDIO_TO_CP1_ARM_CTRL; + else + ret = AUDIO_TO_CP1_DSP_CTRL; + } else if (ret == BITS_VBC_DA01_INT_SYS_SEL(3)) { + ret = AUDIO_TO_CP2_ARM_CTRL; + } + break; + default: + ret = -ENODEV; + break; + } +#endif + + return ret; +} + +static inline int arch_audio_vbc_da_dma_info(int chan) +{ + int ret = 0; + +#if FIXED_AUDIO + switch (chan) { + case 0: + ret = DMA_VB_DA0; + break; + case 1: + ret = DMA_VB_DA1; + break; + default: + ret = -ENODEV; + break; + } +#endif + + return ret; +} + +static inline int arch_audio_vbc_ad_dma_info(int chan) +{ + int ret = 0; + +#if FIXED_AUDIO + switch (chan) { + case 0: + ret = DMA_VB_AD0; + break; + case 1: + ret = DMA_VB_AD1; + break; + default: + ret = -ENODEV; + break; + } +#endif + + return ret; +} + +static inline int arch_audio_vbc_ad23_dma_info(int chan) +{ + int ret = 0; + +#if FIXED_AUDIO + switch (chan) { + case 0: + ret = DMA_VB_AD2; + break; + case 1: + ret = DMA_VB_AD3; + break; + default: + ret = -ENODEV; + break; + } +#endif + + return ret; +} + +static inline int arch_audio_vbc_reset(void) +{ + int ret = 0; + +#if FIXED_AUDIO + sci_glb_set(REG_AON_APB_APB_RST0, BIT_VBC_SOFT_RST); + udelay(10); + sci_glb_clr(REG_AON_APB_APB_RST0, BIT_VBC_SOFT_RST); +#endif + + return ret; +} + +#if 1 +/* some SOC will move this into vbc module */ +static inline int arch_audio_vbc_ad_int_clr(void) +{ + int ret = 0; + +#if FIXED_AUDIO + sci_glb_set((SPRD_INTC0_BASE + 0x0C), IRQ_REQ_AUD_VBC_AD01_INT); +#endif + + return ret; +} + +static inline int arch_audio_vbc_ad23_int_clr(void) +{ + int ret = 0; + +#if FIXED_AUDIO + sci_glb_set((SPRD_INTC0_BASE + 0x0C), IRQ_REQ_AUD_VBC_AD23_INT); +#endif + + return ret; +} + +/* some SOC will move this into vbc module */ +static inline int arch_audio_vbc_da_int_clr(void) +{ + int ret = 0; + +#if FIXED_AUDIO + sci_glb_set((SPRD_INTC0_BASE + 0x0C), IRQ_REQ_AUD_VBC_DA_INT); +#endif + + return ret; +} + +/* some SOC will move this into vbc module */ +static inline int arch_audio_vbc_is_ad_int(void) +{ + int ret = 0; + +#if FIXED_AUDIO + sci_glb_read((SPRD_INTC0_BASE + 0x0), IRQ_REQ_AUD_VBC_AD01_INT); +#endif + + return ret; +} + +/* some SOC will move this into vbc module */ +static inline int arch_audio_vbc_is_ad23_int(void) +{ + int ret = 0; + +#if FIXED_AUDIO + sci_glb_read((SPRD_INTC0_BASE + 0x0), IRQ_REQ_AUD_VBC_AD23_INT); +#endif + + return ret; +} + +/* some SOC will move this into vbc module */ +static inline int arch_audio_vbc_is_da_int(void) +{ + int ret = 0; + +#if FIXED_AUDIO + sci_glb_read((SPRD_INTC0_BASE + 0x0), IRQ_REQ_AUD_VBC_DA_INT); +#endif + + return ret; +} +#endif +/* ------------------------------------------------------------------------- */ + +/* codec setting */ +static inline int arch_audio_codec_write_mask(int reg, int val, int mask) +{ + int ret = 0; + +#if FIXED_AUDIO + ret = sci_adi_write((reg + CODEC_AP_OFFSET + ANA_AUDCFGA_INT_BASE - CODEC_AP_BASE), val, mask); +#endif + + return ret; +} + +static inline int arch_audio_codec_write(int reg, int val) +{ + int ret = 0; + +#if FIXED_AUDIO + ret = sci_adi_write((reg + CODEC_AP_OFFSET + ANA_AUDCFGA_INT_BASE - CODEC_AP_BASE), val, 0xFFFF); +#endif + + return ret; +} + +static inline int arch_audio_codec_read(int reg) +{ + int ret = 0; + +#if FIXED_AUDIO + ret = sci_adi_read(reg + CODEC_AP_OFFSET + ANA_AUDCFGA_INT_BASE - CODEC_AP_BASE); +#endif + + return ret; +} + +static inline int arch_audio_codec_audif_enable(int auto_clk) +{ + int ret = 0; + +#if FIXED_AUDIO + if (auto_clk) { + sci_glb_clr(REG_AON_APB_APB_EB0, BIT_AUDIF_EB); + sci_glb_set(REG_AON_APB_VBC_CTRL, BIT_AUDIF_CKG_AUTO_EN); + } else { + sci_glb_set(REG_AON_APB_APB_EB0, BIT_AUDIF_EB); + sci_glb_clr(REG_AON_APB_VBC_CTRL, BIT_AUDIF_CKG_AUTO_EN); + } +#endif + + return ret; +} + +static inline int arch_audio_codec_audif_disable(void) +{ + int ret = 0; + +#if FIXED_AUDIO + sci_glb_clr(REG_AON_APB_APB_EB0, BIT_AUDIF_EB); + sci_glb_clr(REG_AON_APB_VBC_CTRL, BIT_AUDIF_CKG_AUTO_EN); +#endif + + return ret; +} + +static inline int arch_audio_codec_digital_reg_enable(void) +{ + int ret = 0; + +#if FIXED_AUDIO + ret = sci_glb_set(REG_AON_APB_APB_EB0, BIT_AUD_EB); + if (ret >= 0) + arch_audio_codec_audif_enable(1); +#endif + + return ret; +} + +static inline int arch_audio_codec_digital_reg_disable(void) +{ + int ret = 0; + +#if FIXED_AUDIO + arch_audio_codec_audif_disable(); + sci_glb_clr(REG_AON_APB_APB_EB0, BIT_AUD_EB); +#endif + + return ret; +} + +static inline int arch_audio_codec_analog_reg_enable(void) +{ + int ret = 0; + +#if FIXED_AUDIO + ret = + sci_adi_write(ANA_REG_GLB_ARM_MODULE_EN, BIT_ANA_AUD_EN, + BIT_ANA_AUD_EN); + if (ret >= 0) { + /* Disable Sleep Control Audio Power */ +#if defined(CONFIG_ARCH_SCX15) || defined(CONFIG_ADIE_SC2723S) || defined(CONFIG_ADIE_SC2723) + ret = sci_adi_write(ANA_REG_GLB_AUD_SLP_CTRL, 0, 0xFFFF); +#else + ret = sci_adi_write(ANA_REG_GLB_AUD_SLP_CTRL4, 0, 0xFFFF); +#endif + } +#endif + + return ret; +} + +static inline int arch_audio_codec_analog_reg_disable(void) +{ + int ret = 0; + +#if FIXED_AUDIO + ret = sci_adi_write(ANA_REG_GLB_ARM_MODULE_EN, 0, BIT_ANA_AUD_EN); +#endif + + return ret; +} + +static inline int arch_audio_codec_analog_enable(void) +{ + int ret = 0; + +#if FIXED_AUDIO + /* AUDIF , 6.5M */ + int mask = BIT_CLK_AUD_6P5M_EN | BIT_CLK_AUDIF_EN; + sci_adi_write(ANA_REG_GLB_ARM_CLK_EN, mask, mask); +#if defined(CONFIG_ARCH_SCX15) || defined(CONFIG_ADIE_SC2723S) || defined(CONFIG_ADIE_SC2723) + sci_adi_write(ANA_REG_GLB_AUDIO_CTRL0, BIT_CLK_AUD_6P5M_TX_INV_EN, + BIT_CLK_AUD_6P5M_TX_INV_EN); +#else + sci_adi_write(ANA_REG_GLB_AUDIO_CTRL, BIT_CLK_AUD_6P5M_TX_INV_EN, + BIT_CLK_AUD_6P5M_TX_INV_EN); +#endif +#if defined(CONFIG_ADIE_SC2723S) + /* disable ADSYNC reuse in tshark*/ + sci_adi_write(ANA_AUDIFA_INT_BASE, 0, BIT(4)); +#endif + /* RTC */ + sci_adi_write(ANA_REG_GLB_RTC_CLK_EN, BIT_RTC_AUD_EN, BIT_RTC_AUD_EN); + /* 26M */ + sci_adi_write(ANA_REG_GLB_XTL_WAIT_CTRL, BIT_XTL_EN, BIT_XTL_EN); + + /* FIXME: disable deepsleep force power off audio ldo */ +#if defined(CONFIG_ARCH_SCX15) || defined(CONFIG_ADIE_SC2723S) || defined(CONFIG_ADIE_SC2723) + sci_adi_write(ANA_REG_GLB_AUD_SLP_CTRL, 0, 0xFFFF); +#else + sci_adi_write(ANA_REG_GLB_AUD_SLP_CTRL4, 0, 0xFFFF); +#endif + +#endif + return ret; +} + +static inline int arch_audio_codec_digital_enable(void) +{ + int ret = 0; + +#if FIXED_AUDIO + /* internal digital 26M enable */ + sci_glb_write(REG_AON_APB_SINDRV_CTRL, BIT_SINDRV_ENA, BIT_SINDRV_ENA); +#endif + + return ret; +} + +static inline int arch_audio_codec_analog_disable(void) +{ + int ret = 0; + +#if FIXED_AUDIO + /* AUDIF , 6.5M */ + int mask = BIT_CLK_AUD_6P5M_EN | BIT_CLK_AUDIF_EN; + sci_adi_write(ANA_REG_GLB_ARM_CLK_EN, 0, mask); +#if defined(CONFIG_ARCH_SCX15) || defined(CONFIG_ADIE_SC2723S) || defined(CONFIG_ADIE_SC2723) + sci_adi_write(ANA_REG_GLB_AUDIO_CTRL0, BIT_CLK_AUD_6P5M_TX_INV_EN, + BIT_CLK_AUD_6P5M_TX_INV_EN); +#else + sci_adi_write(ANA_REG_GLB_AUDIO_CTRL, BIT_CLK_AUD_6P5M_TX_INV_EN, + BIT_CLK_AUD_6P5M_TX_INV_EN); +#endif + /* RTC */ + sci_adi_write(ANA_REG_GLB_RTC_CLK_EN, 0, BIT_RTC_AUD_EN); + /* 26M this is shared with adc, so we cann't close it */ + /* sci_adi_write(ANA_REG_GLB_XTL_WAIT_CTRL, 0, BIT_XTL_EN); */ +#endif + + return ret; +} + +static inline int arch_audio_codec_digital_disable(void) +{ + int ret = 0; + +#if FIXED_AUDIO + /* internal digital 26M disable */ + sci_glb_write(REG_AON_APB_SINDRV_CTRL, 0, BIT_SINDRV_ENA); + +#endif + + return ret; +} + +static inline int arch_audio_codec_switch(int master) +{ + int ret = 0; + +#if FIXED_AUDIO + switch (master) { + case AUDIO_TO_AP_ARM_CTRL: + sci_glb_write(REG_AON_APB_VBC_CTRL, BITS_AUD_INT_SYS_SEL(0), + BITS_AUD_INT_SYS_SEL(3)); + break; + case AUDIO_TO_CP0_ARM_CTRL: + sci_glb_write(REG_AON_APB_VBC_CTRL, BITS_AUD_INT_SYS_SEL(1), + BITS_AUD_INT_SYS_SEL(3)); + break; + case AUDIO_TO_CP1_ARM_CTRL: + sci_glb_write(REG_AON_APB_VBC_CTRL, BITS_AUD_INT_SYS_SEL(2), + BITS_AUD_INT_SYS_SEL(3)); + break; + case AUDIO_TO_CP2_ARM_CTRL: + sci_glb_write(REG_AON_APB_VBC_CTRL, BITS_AUD_INT_SYS_SEL(3), + BITS_AUD_INT_SYS_SEL(3)); + break; + case AUDIO_NO_CHANGE: + ret = + sci_glb_read(REG_AON_APB_VBC_CTRL, BITS_AUD_INT_SYS_SEL(3)); + if (ret == 0) { + ret = AUDIO_TO_AP_ARM_CTRL; + } else if (ret == 1) { + ret = AUDIO_TO_CP0_ARM_CTRL; + } else if (ret == 2) { + ret = AUDIO_TO_CP1_ARM_CTRL; + } else if (ret == 3) { + ret = AUDIO_TO_CP2_ARM_CTRL; + } + break; + default: + ret = -ENODEV; + break; + } +#endif + + return ret; +} + +static inline int arch_audio_codec_reset(void) +{ + int ret = 0; + +#if FIXED_AUDIO + int mask = + BIT_ANA_AUD_SOFT_RST | BIT_ANA_AUDTX_SOFT_RST | + BIT_ANA_AUDRX_SOFT_RST; + sci_glb_set(REG_AON_APB_APB_RST0, BIT_AUD_SOFT_RST); + sci_glb_set(REG_AON_APB_APB_RST0, BIT_AUDIF_SOFT_RST); + ret = sci_adi_write(ANA_REG_GLB_ARM_RST, mask, mask); + udelay(10); + sci_glb_clr(REG_AON_APB_APB_RST0, BIT_AUD_SOFT_RST); + sci_glb_clr(REG_AON_APB_APB_RST0, BIT_AUDIF_SOFT_RST); + if (ret >= 0) + ret = sci_adi_write(ANA_REG_GLB_ARM_RST, 0, mask); +#endif + + return ret; +} + +static inline int arch_audio_codec_digital_reset(void) +{ + int ret = 0; + +#if FIXED_AUDIO + sci_glb_set(REG_AON_APB_APB_RST0, BIT_AUD_SOFT_RST); + sci_glb_set(REG_AON_APB_APB_RST0, BIT_AUDIF_SOFT_RST); + udelay(10); + sci_glb_clr(REG_AON_APB_APB_RST0, BIT_AUD_SOFT_RST); + sci_glb_clr(REG_AON_APB_APB_RST0, BIT_AUDIF_SOFT_RST); +#endif + + return ret; +} + +static inline int arch_audio_codec_analog_reset(void) +{ + int ret = 0; + +#if FIXED_AUDIO + int mask = + BIT_ANA_AUD_SOFT_RST | BIT_ANA_AUDTX_SOFT_RST | + BIT_ANA_AUDRX_SOFT_RST; + ret = sci_adi_write(ANA_REG_GLB_ARM_RST, mask, mask); + udelay(10); + if (ret >= 0) + ret = sci_adi_write(ANA_REG_GLB_ARM_RST, 0, mask); +#endif + + return ret; +} + +static inline int arch_audio_sleep_xtl_enable(void) +{ + +#if FIXED_AUDIO + sci_glb_set(REG_PMU_APB_SLEEP_CTRL, BIT_AP_SLEEP_XTL_ON); +#endif + return 0; +} +static inline int arch_audio_sleep_xtl_disable(void) +{ + +#if FIXED_AUDIO + sci_glb_clr(REG_PMU_APB_SLEEP_CTRL, BIT_AP_SLEEP_XTL_ON); +#endif + return 0; +} + +static inline int arch_audio_memory_sleep_enable(void) +{ +#if FIXED_AUDIO + sci_glb_clr(REG_PMU_APB_MEM_PD_CFG0, BITS_AON_MEM_PD_CFG_VBC(3)); + sci_glb_clr(REG_PMU_APB_MEM_PD_CFG0, BITS_AON_MEM_PD_CFG_AUD(3)); +#endif + return 0; +} + +static inline int arch_audio_memory_sleep_disable(void) +{ +#if FIXED_AUDIO + sci_glb_set(REG_PMU_APB_MEM_PD_CFG0, BITS_AON_MEM_PD_CFG_VBC(1)); + sci_glb_set(REG_PMU_APB_MEM_PD_CFG0, BITS_AON_MEM_PD_CFG_AUD(1)); +#endif + return 0; +} + +static inline int arch_audio_codec_adie_loop_clk_en(int on) +{ + int ret = 0; + if (on) + ret = sci_adi_write(ANA_REG_GLB_ARM_CLK_EN, BIT_CLK_AUD_LOOP_EN, BIT_CLK_AUD_LOOP_EN); + else + ret = sci_adi_write(ANA_REG_GLB_ARM_CLK_EN, 0, BIT_CLK_AUD_LOOP_EN); + return ret; +} + +/* ------------------------------------------------------------------------- */ + +/* i2s setting */ +static inline const char *arch_audio_i2s_clk_name(int id) +{ +#if FIXED_AUDIO + switch (id) { + case 0: + return "clk_iis0"; + break; + case 1: + return "clk_iis1"; + break; + case 2: + return "clk_iis2"; + break; + case 3: + return "clk_iis3"; + break; + default: + break; + } +#endif + return NULL; +} + +static inline int arch_audio_i2s_enable(int id) +{ + int ret = 0; + +#if FIXED_AUDIO + switch (id) { + case 0: + sci_glb_set(REG_AP_APB_APB_EB, BIT_IIS0_EB); + break; + case 1: + sci_glb_set(REG_AP_APB_APB_EB, BIT_IIS1_EB); + break; + case 2: + sci_glb_set(REG_AP_APB_APB_EB, BIT_IIS2_EB); + break; + case 3: + sci_glb_set(REG_AP_APB_APB_EB, BIT_IIS3_EB); + break; + default: + ret = -ENODEV; + break; + } +#endif + + return ret; +} + +static inline int arch_audio_i2s_disable(int id) +{ + int ret = 0; + +#if FIXED_AUDIO + switch (id) { + case 0: + sci_glb_clr(REG_AP_APB_APB_EB, BIT_IIS0_EB); + break; + case 1: + sci_glb_clr(REG_AP_APB_APB_EB, BIT_IIS1_EB); + break; + case 2: + sci_glb_clr(REG_AP_APB_APB_EB, BIT_IIS2_EB); + break; + case 3: + sci_glb_clr(REG_AP_APB_APB_EB, BIT_IIS3_EB); + break; + default: + ret = -ENODEV; + break; + } +#endif + + return ret; +} + +static inline int arch_audio_i2s_tx_dma_info(int id) +{ + int ret = 0; + +#if FIXED_AUDIO + switch (id) { + case 0: + ret = DMA_IIS0_TX; + break; + case 1: + ret = DMA_IIS1_TX; + break; + case 2: + ret = DMA_IIS2_TX; + break; + case 3: + ret = DMA_IIS3_TX; + break; + default: + ret = -ENODEV; + break; + } +#endif + + return ret; +} + +static inline int arch_audio_i2s_rx_dma_info(int id) +{ + int ret = 0; + +#if FIXED_AUDIO + switch (id) { + case 0: + ret = DMA_IIS0_RX; + break; + case 1: + ret = DMA_IIS1_RX; + break; + case 2: + ret = DMA_IIS2_RX; + break; + case 3: + ret = DMA_IIS3_RX; + break; + default: + ret = -ENODEV; + break; + } + +#endif + + return ret; +} + +static inline int arch_audio_i2s_reset(int id) +{ + int ret = 0; + +#if FIXED_AUDIO + switch (id) { + case 0: + sci_glb_set(REG_AP_APB_APB_RST, BIT_IIS0_SOFT_RST); + udelay(10); + sci_glb_clr(REG_AP_APB_APB_RST, BIT_IIS0_SOFT_RST); + break; + case 1: + sci_glb_set(REG_AP_APB_APB_RST, BIT_IIS1_SOFT_RST); + udelay(10); + sci_glb_clr(REG_AP_APB_APB_RST, BIT_IIS1_SOFT_RST); + break; + case 2: + sci_glb_set(REG_AP_APB_APB_RST, BIT_IIS2_SOFT_RST); + udelay(10); + sci_glb_clr(REG_AP_APB_APB_RST, BIT_IIS2_SOFT_RST); + break; + case 3: + sci_glb_set(REG_AP_APB_APB_RST, BIT_IIS3_SOFT_RST); + udelay(10); + sci_glb_clr(REG_AP_APB_APB_RST, BIT_IIS3_SOFT_RST); + break; + default: + ret = -ENODEV; + break; + } +#endif + + return ret; +} + +/* sc8830 AP IIS and CP IIS are different. AP IIS cann't switch to other master*/ +static inline int arch_audio_i2s_switch(int id, int master) +{ + int ret = 0; + +#if FIXED_AUDIO + switch (master) { + case AUDIO_TO_AP_ARM_CTRL: + break; + case AUDIO_NO_CHANGE: + ret = AUDIO_TO_AP_ARM_CTRL; + break; + default: + ret = -ENODEV; + break; + } +#endif + + return ret; +} + +#endif + +#define AUDIO_VBC_REG_DUMP_LIST(t) { \ + REG_PAIR(t, REG_AON_APB_APB_EB0, 1, __raw_readl) \ + REG_PAIR(t, REG_AON_APB_APB_RST0, 1, __raw_readl) \ + REG_PAIR(t, REG_AON_APB_SINDRV_CTRL, 1, __raw_readl) \ + REG_PAIR(t, REG_AON_APB_VBC_CTRL, 1, __raw_readl) \ + REG_PAIR(t, REG_AON_APB_AP_WPROT_EN, 1, __raw_readl) \ + REG_PAIR(t, REG_AON_APB_CP0_WPROT_EN, 1, __raw_readl) \ + REG_PAIR(t, REG_AON_APB_CP1_WPROT_EN, 1, __raw_readl) \ + REG_PAIR(t, REG_AON_APB_CP2_WPROT_EN, 1, __raw_readl) \ +} + +#define AUDIO_CODEC_REG_DUMP_LIST(t) { \ + REG_PAIR(t, SPRD_INTC0_BASE, 4, __raw_readl) \ + REG_PAIR(t, REG_PMU_APB_SLEEP_CTRL, 1, __raw_readl) \ + REG_PAIR(t, REG_PMU_APB_MEM_PD_CFG0, 1, __raw_readl) \ + REG_PAIR(t, ANA_AUDIFA_INT_BASE, 1, sci_adi_read) \ + REG_PAIR(t, ANA_REG_GLB_ARM_MODULE_EN, 1, sci_adi_read) \ + REG_PAIR(t, ANA_REG_GLB_ARM_CLK_EN, 1, sci_adi_read) \ + REG_PAIR(t, ANA_REG_GLB_AUD_SLP_CTRL, 1, sci_adi_read) \ + REG_PAIR(t, ANA_REG_GLB_AUDIO_CTRL0, 1, sci_adi_read) \ + REG_PAIR(t, ANA_REG_GLB_RTC_CLK_EN, 1, sci_adi_read) \ + REG_PAIR(t, ANA_REG_GLB_XTL_WAIT_CTRL, 1, sci_adi_read) \ + REG_PAIR(t, ANA_REG_GLB_ARM_RST, 1, sci_adi_read) \ +} + +#define AUDIO_IIS_REG_DUMP_LIST(t) { \ + REG_PAIR(t, REG_AP_APB_APB_EB, 1, __raw_readl) \ + REG_PAIR(t, REG_AP_APB_APB_RST, 1, __raw_readl) \ +} +/* +REG_PAIR(t, ANA_REG_GLB_AUDIO_CTRL, 1, sci_adi_read) \ +REG_PAIR(t, ANA_REG_GLB_AUD_SLP_CTRL4, 1, sci_adi_read) \ +*/ diff --git a/include/soc/sprd/__sprd_audio_sc8835l.h b/include/soc/sprd/__sprd_audio_sc8835l.h new file mode 100755 index 00000000..9d757862 --- /dev/null +++ b/include/soc/sprd/__sprd_audio_sc8835l.h @@ -0,0 +1,963 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARCH_AUDIO_GLB_SCX35L_H +#define __ASM_ARCH_AUDIO_GLB_SCX35L_H + +#ifndef __ASM_ARCH_AUDIO_GLB_H +#error "Don't include this file directly, include <mach/sprd-audio.h>" +#endif + +#include <linux/delay.h> + +#include <soc/sprd/hardware.h> +#include <soc/sprd/sci.h> +#include <soc/sprd/sci_glb_regs.h> +#include <soc/sprd/adi.h> +#include <soc/sprd/irqs.h> +#ifndef CONFIG_SND_SOC_SPRD_AUDIO_DMA_ENGINE +#include <soc/sprd/dma.h> +#else +#include <../../../drivers/dma/sprd_dma.h> +#endif + +/* OKAY, this is for other else owner + if you do not care the audio config + you can set FIXED_AUDIO to 0 + for compile happy. +*/ +/* FIXME */ +#define FIXED_AUDIO 1 + +enum { + AUDIO_NO_CHANGE, + AUDIO_TO_CP0_DSP_CTRL, + AUDIO_TO_CP1_DSP_CTRL, + AUDIO_TO_AP_ARM_CTRL, + AUDIO_TO_ARM_CTRL = AUDIO_TO_AP_ARM_CTRL, + AUDIO_TO_CP0_ARM_CTRL, + AUDIO_TO_CP1_ARM_CTRL, + AUDIO_TO_CP2_ARM_CTRL, +}; + +#if FIXED_AUDIO + +#if 1 +#define CODEC_DP_BASE (0x1000) +#define VBC_BASE (0x1000) +#define CODEC_AP_BASE (0x2000) +#define CODEC_AP_OFFSET (0) + +#define CODEC_DP_BASE_DEFAULT 0x40000000 +#define CODEC_DP_SIZE_DEFAULT SZ_8K + +#define VBC_BASE_DEFAULT 0x40020000 +#define VBC_BASE_SIZE_DEFAULT SZ_4K + SZ_8K + +#define VBC_PHY_BASE 0 +#else +#define VBC_BASE (SPRD_VBC_BASE) +#define CODEC_DP_BASE SPRD_AUDIO_BASE +#define VBC_PHY_BASE SPRD_VBC_PHYS + +/* CODEC_AP_BASE: the bit15 cann't be 1 for asoc reg.*/ +#if (ANA_AUDCFGA_INT_BASE & BIT(15)) +#define CODEC_AP_BASE (ANA_AUDCFGA_INT_BASE & ~(BIT(15))) +#define CODEC_AP_OFFSET (0x8000) +#else +#define CODEC_AP_BASE (ANA_AUDCFGA_INT_BASE) +#define CODEC_AP_OFFSET (0) +#endif +#endif +/* for CP2 */ +#define VBC_CP2_PHY_BASE (0x02020000) +#define CP2_PHYS_VBDA0 (VBC_CP2_PHY_BASE + 0x0000) +#define CP2_PHYS_VBDA1 (VBC_CP2_PHY_BASE + 0x0004) + +#define CODEC_DP_PHY_BASE SPRD_AUDIO_PHYS +#define CODEC_AP_PHY_BASE (SPRD_ADISLAVE_PHYS + 0x0600) +#define CODEC_AP_IRQ (IRQ_ANA_AUD_INT) +#define CODEC_DP_IRQ (IRQ_REQ_AUD_INT) + +#define SPRD_IRAM_ALL_PHYS (SPRD_IRAM2_PHYS) +#define SPRD_IRAM_ALL_SIZE (SPRD_IRAM2_SIZE) + +#define CLASS_G_LDO_ID "vddclsg" +#endif + +/* ------------------------------------------------------------------------- */ + +/* NOTE: all function maybe will call by atomic funtion + don NOT any complex oprations. Just register. +return + 0: unchanged + 1: changed + ohter error +*/ +/* vbc setting */ + +static inline int arch_audio_vbc_reg_enable(void) +{ + int ret = 0; + +#if FIXED_AUDIO + sci_glb_set(REG_AON_APB_APB_EB0, BIT_VBC_EB); +#endif + + return ret; +} + +static inline int arch_audio_vbc_reg_disable(void) +{ + int ret = 0; + +#if FIXED_AUDIO + sci_glb_clr(REG_AON_APB_APB_EB0, BIT_VBC_EB); +#endif + + return ret; +} + +static inline int arch_audio_vbc_enable(void) +{ + int ret = 0; + +#if FIXED_AUDIO +#endif + + return ret; +} + +static inline int arch_audio_vbc_disable(void) +{ + int ret = 0; + +#if FIXED_AUDIO +#endif + + return ret; +} + +static inline int arch_audio_vbc_reset(void); +static inline int arch_audio_vbc_switch(int master) +{ + int ret = 0; +#if FIXED_AUDIO + int val = 0; + int mask = + BITS_VBC_AFIFO_INT_SYS_SEL(3) | BITS_VBC_DA01_INT_SYS_SEL(3) | + BITS_VBC_AD01_INT_SYS_SEL(3) + | BITS_VBC_AD23_INT_SYS_SEL(3) | BITS_VBC_DA01_DMA_SYS_SEL(3) | + BITS_VBC_AD01_DMA_SYS_SEL(3) + | BITS_VBC_AD23_DMA_SYS_SEL(3); + + if (master != AUDIO_NO_CHANGE) { + sci_glb_set(REG_AON_APB_CP0_WPROT_EN0, BIT(6)); + sci_glb_set(REG_AON_APB_CP1_WPROT_EN0, BIT(6)); + //changed by jian.chen + //sci_glb_set(REG_AON_APB_CP2_WPROT_EN, BIT(6)); + } + switch (master) { + case AUDIO_TO_AP_ARM_CTRL: + val = + BITS_VBC_AFIFO_INT_SYS_SEL(0) | BITS_VBC_DA01_INT_SYS_SEL(0) + | BITS_VBC_AD01_INT_SYS_SEL(0) + | BITS_VBC_AD23_INT_SYS_SEL(0); + #ifndef CONFIG_SND_SOC_SPRD_AUDIO_USE_AON_DMA + val |= + (BITS_VBC_DA01_DMA_SYS_SEL(0) | BITS_VBC_AD01_DMA_SYS_SEL(0) + | BITS_VBC_AD23_DMA_SYS_SEL(0)); + #else + /* Capture will only use AP DMA for the limitation of IRAM size */ + val |= + (BITS_VBC_DA01_DMA_SYS_SEL(2) | BITS_VBC_AD01_DMA_SYS_SEL(0) + | BITS_VBC_AD23_DMA_SYS_SEL(0)); + #endif + sci_glb_write(REG_AON_APB_VBC_CTRL, val, mask); + sci_glb_clr(REG_AON_APB_AP_WPROT_EN0, BIT(6)); + arch_audio_vbc_reset(); + arch_audio_vbc_reg_disable(); + break; + case AUDIO_TO_CP0_DSP_CTRL: + arch_audio_vbc_reset(); + arch_audio_vbc_reg_enable(); + sci_glb_clr(REG_AON_APB_CP0_WPROT_EN0, BIT(6)); + val = + BITS_VBC_AFIFO_INT_SYS_SEL(1) | BITS_VBC_DA01_INT_SYS_SEL(1) + | BITS_VBC_AD01_INT_SYS_SEL(1) + | BITS_VBC_AD23_INT_SYS_SEL(1) | + BITS_VBC_DA01_DMA_SYS_SEL(1) | BITS_VBC_AD01_DMA_SYS_SEL(1) + | BITS_VBC_AD23_DMA_SYS_SEL(1); + sci_glb_write(REG_AON_APB_VBC_CTRL, val, mask); +#ifndef CONFIG_ARCH_SCX20L + sci_glb_write(REG_AON_APB_VBC_CTRL, 0, + (BIT_VBC_DMA_CP0_ARM_SEL | + BIT_VBC_DMA_CP0_ARM_SEL)); +#endif + break; + case AUDIO_TO_CP1_DSP_CTRL: + arch_audio_vbc_reset(); + arch_audio_vbc_reg_enable(); + sci_glb_clr(REG_AON_APB_CP1_WPROT_EN0, BIT(6)); + val = + BITS_VBC_AFIFO_INT_SYS_SEL(2) | BITS_VBC_DA01_INT_SYS_SEL(2) + | BITS_VBC_AD01_INT_SYS_SEL(2) + | BITS_VBC_AD23_INT_SYS_SEL(2) | + BITS_VBC_DA01_DMA_SYS_SEL(2) | BITS_VBC_AD01_DMA_SYS_SEL(2) + | BITS_VBC_AD23_DMA_SYS_SEL(2); + sci_glb_write(REG_AON_APB_VBC_CTRL, val, mask); +#ifndef CONFIG_ARCH_SCX20L + sci_glb_write(REG_AON_APB_VBC_CTRL, 0, + (BIT_VBC_DMA_CP1_ARM_SEL | + BIT_VBC_DMA_CP1_ARM_SEL)); +#endif + break; + case AUDIO_TO_CP0_ARM_CTRL: + arch_audio_vbc_reset(); + arch_audio_vbc_reg_enable(); + sci_glb_clr(REG_AON_APB_CP0_WPROT_EN0, BIT(6)); + val = + BITS_VBC_AFIFO_INT_SYS_SEL(1) | BITS_VBC_DA01_INT_SYS_SEL(1) + | BITS_VBC_AD01_INT_SYS_SEL(1) + | BITS_VBC_AD23_INT_SYS_SEL(1) | + BITS_VBC_DA01_DMA_SYS_SEL(1) | BITS_VBC_AD01_DMA_SYS_SEL(1) + | BITS_VBC_AD23_DMA_SYS_SEL(1); +#ifndef CONFIG_ARCH_SCX20L + sci_glb_write(REG_AON_APB_VBC_CTRL, + (val | BIT_VBC_INT_CP0_ARM_SEL | + BIT_VBC_DMA_CP0_ARM_SEL), + (mask | BIT_VBC_INT_CP0_ARM_SEL | + BIT_VBC_DMA_CP0_ARM_SEL)); +#endif + break; + case AUDIO_TO_CP1_ARM_CTRL: + arch_audio_vbc_reset(); + arch_audio_vbc_reg_enable(); + sci_glb_clr(REG_AON_APB_CP1_WPROT_EN0, BIT(6)); + val = + BITS_VBC_AFIFO_INT_SYS_SEL(2) | BITS_VBC_DA01_INT_SYS_SEL(2) + | BITS_VBC_AD01_INT_SYS_SEL(2) + | BITS_VBC_AD23_INT_SYS_SEL(2) | + BITS_VBC_DA01_DMA_SYS_SEL(2) | BITS_VBC_AD01_DMA_SYS_SEL(2) + | BITS_VBC_AD23_DMA_SYS_SEL(2); +#ifndef CONFIG_ARCH_SCX20L + sci_glb_write(REG_AON_APB_VBC_CTRL, + (val | BIT_VBC_INT_CP1_ARM_SEL | + BIT_VBC_DMA_CP1_ARM_SEL), + (mask | BIT_VBC_INT_CP1_ARM_SEL | + BIT_VBC_DMA_CP1_ARM_SEL)); +#endif + break; + //changed by jian.chen + /* + case AUDIO_TO_CP2_ARM_CTRL: + sci_glb_clr(REG_AON_APB_CP2_WPROT_EN, BIT(6)); + val = + BITS_VBC_AFIFO_INT_SYS_SEL(3) | BITS_VBC_DA01_INT_SYS_SEL(3) + | BITS_VBC_AD01_INT_SYS_SEL(3) + | BITS_VBC_AD23_INT_SYS_SEL(3) | + BITS_VBC_DA01_DMA_SYS_SEL(3) | BITS_VBC_AD01_DMA_SYS_SEL(3) + | BITS_VBC_AD23_DMA_SYS_SEL(3); + sci_glb_write(REG_AON_APB_VBC_CTRL, val, mask); + break; + */ + case AUDIO_NO_CHANGE: + ret = + sci_glb_read(REG_AON_APB_VBC_CTRL, + BITS_VBC_DA01_INT_SYS_SEL(3)); + if (ret == BITS_VBC_DA01_INT_SYS_SEL(0)) { + ret = AUDIO_TO_AP_ARM_CTRL; + } else if (ret == BITS_VBC_DA01_INT_SYS_SEL(1)) { +#ifndef CONFIG_ARCH_SCX20L + ret = + sci_glb_read(REG_AON_APB_VBC_CTRL, + BIT_VBC_INT_CP0_ARM_SEL); + if (ret) + ret = AUDIO_TO_CP0_ARM_CTRL; + else +#endif + ret = AUDIO_TO_CP0_DSP_CTRL; + } else if (ret == BITS_VBC_DA01_INT_SYS_SEL(2)) { +#ifndef CONFIG_ARCH_SCX20L + ret = + sci_glb_read(REG_AON_APB_VBC_CTRL, + BIT_VBC_INT_CP1_ARM_SEL); + if (ret) + ret = AUDIO_TO_CP1_ARM_CTRL; + else +#endif + ret = AUDIO_TO_CP1_DSP_CTRL; + } else if (ret == BITS_VBC_DA01_INT_SYS_SEL(3)) { + ret = AUDIO_TO_CP2_ARM_CTRL; + } + break; + default: + ret = -ENODEV; + break; + } +#endif + + return ret; +} + +static inline int arch_audio_vbc_da_dma_info(int chan) +{ + int ret = 0; + +#if FIXED_AUDIO + switch (chan) { + case 0: + ret = DMA_VB_DA0; + break; + case 1: + ret = DMA_VB_DA1; + break; + default: + ret = -ENODEV; + break; + } +#endif + + return ret; +} + +static inline int arch_audio_vbc_ad_dma_info(int chan) +{ + int ret = 0; + +#if FIXED_AUDIO + switch (chan) { + case 0: + ret = DMA_VB_AD0; + break; + case 1: + ret = DMA_VB_AD1; + break; + default: + ret = -ENODEV; + break; + } +#endif + + return ret; +} + +static inline int arch_audio_vbc_ad23_dma_info(int chan) +{ + int ret = 0; + +#if FIXED_AUDIO + switch (chan) { + case 0: + ret = DMA_VB_AD2; + break; + case 1: + ret = DMA_VB_AD3; + break; + default: + ret = -ENODEV; + break; + } +#endif + + return ret; +} + +static inline int arch_audio_vbc_reset(void) +{ + int ret = 0; + +#if FIXED_AUDIO + sci_glb_set(REG_AON_APB_APB_RST0, BIT_VBC_SOFT_RST); + udelay(10); + sci_glb_clr(REG_AON_APB_APB_RST0, BIT_VBC_SOFT_RST); +#endif + + return ret; +} + +#if 1 +/* some SOC will move this into vbc module */ +static inline int arch_audio_vbc_ad_int_clr(void) +{ + int ret = 0; + + + return ret; +} + +static inline int arch_audio_vbc_ad23_int_clr(void) +{ + int ret = 0; + + + return ret; +} + +/* some SOC will move this into vbc module */ +static inline int arch_audio_vbc_da_int_clr(void) +{ + int ret = 0; + + + return ret; +} + +/* some SOC will move this into vbc module */ +static inline int arch_audio_vbc_is_ad_int(void) +{ + int ret = 0; + + + return ret; +} + +/* some SOC will move this into vbc module */ +static inline int arch_audio_vbc_is_ad23_int(void) +{ + int ret = 0; + + + return ret; +} + +/* some SOC will move this into vbc module */ +static inline int arch_audio_vbc_is_da_int(void) +{ + int ret = 0; + + + return ret; +} +#endif +/* ------------------------------------------------------------------------- */ + +/* codec setting */ +static inline int arch_audio_codec_write_mask(int reg, int val, int mask) +{ + int ret = 0; + +#if FIXED_AUDIO + ret = sci_adi_write((reg + CODEC_AP_OFFSET + ANA_AUDCFGA_INT_BASE - CODEC_AP_BASE), val, mask); +#endif + + return ret; +} + +static inline int arch_audio_codec_write(int reg, int val) +{ + int ret = 0; + +#if FIXED_AUDIO + ret = sci_adi_write((reg + CODEC_AP_OFFSET + ANA_AUDCFGA_INT_BASE - CODEC_AP_BASE), val, 0xFFFF); +#endif + + return ret; +} + +static inline int arch_audio_codec_read(int reg) +{ + int ret = 0; + +#if FIXED_AUDIO + ret = sci_adi_read(reg + CODEC_AP_OFFSET + ANA_AUDCFGA_INT_BASE - CODEC_AP_BASE); +#endif + + return ret; +} + +static inline int arch_audio_codec_audif_enable(int auto_clk) +{ + int ret = 0; + +#if FIXED_AUDIO + if (auto_clk) { + sci_glb_clr(REG_AON_APB_APB_EB0, BIT_AUDIF_EB); + sci_glb_set(REG_AON_APB_VBC_CTRL, BIT_AUDIF_CKG_AUTO_EN); + } else { + sci_glb_set(REG_AON_APB_APB_EB0, BIT_AUDIF_EB); + sci_glb_clr(REG_AON_APB_VBC_CTRL, BIT_AUDIF_CKG_AUTO_EN); + } +#endif + + return ret; +} + +static inline int arch_audio_codec_audif_disable(void) +{ + int ret = 0; + +#if FIXED_AUDIO + sci_glb_clr(REG_AON_APB_APB_EB0, BIT_AUDIF_EB); + sci_glb_clr(REG_AON_APB_VBC_CTRL, BIT_AUDIF_CKG_AUTO_EN); +#endif + + return ret; +} + +static inline int arch_audio_codec_digital_reg_enable(void) +{ + int ret = 0; + +#if FIXED_AUDIO + ret = sci_glb_set(REG_AON_APB_APB_EB0, BIT_AUD_EB); + if (ret >= 0) + arch_audio_codec_audif_enable(0); +#endif + + return ret; +} + +static inline int arch_audio_codec_digital_reg_disable(void) +{ + int ret = 0; + +#if FIXED_AUDIO + arch_audio_codec_audif_disable(); + sci_glb_clr(REG_AON_APB_APB_EB0, BIT_AUD_EB); +#endif + + return ret; +} + +static inline int arch_audio_codec_analog_reg_enable(void) +{ + int ret = 0; + +#if FIXED_AUDIO + ret = + sci_adi_write(ANA_REG_GLB_ARM_MODULE_EN, BIT_ANA_AUD_EN, + BIT_ANA_AUD_EN); + if (ret >= 0) { + /* Disable Sleep Control Audio Power */ + ret = sci_adi_write(ANA_REG_GLB_AUD_SLP_CTRL, 0, 0xFFFF); + } +#endif + + return ret; +} + +static inline int arch_audio_codec_analog_reg_disable(void) +{ + int ret = 0; + +#if FIXED_AUDIO + ret = sci_adi_write(ANA_REG_GLB_ARM_MODULE_EN, 0, BIT_ANA_AUD_EN); +#endif + + return ret; +} + +static inline int arch_audio_codec_analog_enable(void) +{ + int ret = 0; + +#if FIXED_AUDIO + /* AUDIF , 6.5M */ + int mask = BIT_CLK_AUD_6P5M_EN | BIT_CLK_AUDIF_EN; + sci_adi_write(ANA_REG_GLB_ARM_CLK_EN, mask, mask); + sci_adi_write(ANA_REG_GLB_AUDIO_CTRL0, BIT_CLK_AUD_6P5M_TX_INV_EN, + BIT_CLK_AUD_6P5M_TX_INV_EN); + /* RTC */ + sci_adi_write(ANA_REG_GLB_RTC_CLK_EN, BIT_RTC_AUD_EN, BIT_RTC_AUD_EN); + /* 26M */ + sci_adi_write(ANA_REG_GLB_XTL_WAIT_CTRL, BIT_XTL_EN, BIT_XTL_EN); + + /* FIXME: disable deepsleep force power off audio ldo */ + sci_adi_write(ANA_REG_GLB_AUD_SLP_CTRL, 0, 0xFFFF); +#endif + return ret; +} + +static inline int arch_audio_codec_digital_enable(void) +{ + int ret = 0; + +#if FIXED_AUDIO + /* internal digital 26M enable */ + sci_glb_write(REG_AON_APB_SINDRV_CTRL, BIT_SINDRV_ENA, BIT_SINDRV_ENA); +#endif + + return ret; +} + +static inline int arch_audio_codec_analog_disable(void) +{ + int ret = 0; + +#if FIXED_AUDIO + /* AUDIF , 6.5M */ + int mask = BIT_CLK_AUD_6P5M_EN | BIT_CLK_AUDIF_EN; + sci_adi_write(ANA_REG_GLB_ARM_CLK_EN, 0, mask); + sci_adi_write(ANA_REG_GLB_AUDIO_CTRL0, BIT_CLK_AUD_6P5M_TX_INV_EN, + BIT_CLK_AUD_6P5M_TX_INV_EN); + /* RTC */ + sci_adi_write(ANA_REG_GLB_RTC_CLK_EN, 0, BIT_RTC_AUD_EN); + /* 26M this is shared with adc, so we cann't close it */ + /* sci_adi_write(ANA_REG_GLB_XTL_WAIT_CTRL, 0, BIT_XTL_EN); */ +#endif + + return ret; +} + +static inline int arch_audio_codec_digital_disable(void) +{ + int ret = 0; + +#if FIXED_AUDIO + /* internal digital 26M disable */ + sci_glb_write(REG_AON_APB_SINDRV_CTRL, 0, BIT_SINDRV_ENA); + +#endif + + return ret; +} + +static inline int arch_audio_codec_switch(int master) +{ + int ret = 0; + +#if FIXED_AUDIO + switch (master) { + case AUDIO_TO_AP_ARM_CTRL: + sci_glb_write(REG_AON_APB_VBC_CTRL, BITS_AUD_INT_SYS_SEL(0), + BITS_AUD_INT_SYS_SEL(3)); + break; + case AUDIO_TO_CP0_ARM_CTRL: + sci_glb_write(REG_AON_APB_VBC_CTRL, BITS_AUD_INT_SYS_SEL(1), + BITS_AUD_INT_SYS_SEL(3)); + break; + case AUDIO_TO_CP1_ARM_CTRL: + sci_glb_write(REG_AON_APB_VBC_CTRL, BITS_AUD_INT_SYS_SEL(2), + BITS_AUD_INT_SYS_SEL(3)); + break; + case AUDIO_TO_CP2_ARM_CTRL: + sci_glb_write(REG_AON_APB_VBC_CTRL, BITS_AUD_INT_SYS_SEL(3), + BITS_AUD_INT_SYS_SEL(3)); + break; + case AUDIO_NO_CHANGE: + ret = + sci_glb_read(REG_AON_APB_VBC_CTRL, BITS_AUD_INT_SYS_SEL(3)); + if (ret == 0) { + ret = AUDIO_TO_AP_ARM_CTRL; + } else if (ret == 1) { + ret = AUDIO_TO_CP0_ARM_CTRL; + } else if (ret == 2) { + ret = AUDIO_TO_CP1_ARM_CTRL; + } else if (ret == 3) { + ret = AUDIO_TO_CP2_ARM_CTRL; + } + break; + default: + ret = -ENODEV; + break; + } +#endif + + return ret; +} + +static inline int arch_audio_codec_reset(void) +{ + int ret = 0; + +#if FIXED_AUDIO + int mask = + BIT_ANA_AUD_SOFT_RST | BIT_ANA_AUDTX_SOFT_RST | + BIT_ANA_AUDRX_SOFT_RST; + sci_glb_set(REG_AON_APB_APB_RST0, BIT_AUD_SOFT_RST); + sci_glb_set(REG_AON_APB_APB_RST0, BIT_AUDIF_SOFT_RST); + ret = sci_adi_write(ANA_REG_GLB_ARM_RST, mask, mask); + udelay(10); + sci_glb_clr(REG_AON_APB_APB_RST0, BIT_AUD_SOFT_RST); + sci_glb_clr(REG_AON_APB_APB_RST0, BIT_AUDIF_SOFT_RST); + if (ret >= 0) + ret = sci_adi_write(ANA_REG_GLB_ARM_RST, 0, mask); +#endif + + return ret; +} + +static inline int arch_audio_codec_digital_reset(void) +{ + int ret = 0; + +#if FIXED_AUDIO + sci_glb_set(REG_AON_APB_APB_RST0, BIT_AUD_SOFT_RST); + sci_glb_set(REG_AON_APB_APB_RST0, BIT_AUDIF_SOFT_RST); + udelay(10); + sci_glb_clr(REG_AON_APB_APB_RST0, BIT_AUD_SOFT_RST); + sci_glb_clr(REG_AON_APB_APB_RST0, BIT_AUDIF_SOFT_RST); +#endif + + return ret; +} + +static inline int arch_audio_codec_analog_reset(void) +{ + int ret = 0; + +#if FIXED_AUDIO + int mask = + BIT_ANA_AUD_SOFT_RST | BIT_ANA_AUDTX_SOFT_RST | + BIT_ANA_AUDRX_SOFT_RST; + ret = sci_adi_write(ANA_REG_GLB_ARM_RST, mask, mask); + udelay(10); + if (ret >= 0) + ret = sci_adi_write(ANA_REG_GLB_ARM_RST, 0, mask); +#endif + + return ret; +} + +static inline int arch_audio_sleep_xtl_enable(void) +{ + +#if FIXED_AUDIO + sci_glb_set(REG_PMU_APB_SLEEP_XTLON_CTRL, BIT_AP_SLEEP_XTL_ON); +#endif + return 0; +} +static inline int arch_audio_sleep_xtl_disable(void) +{ + +#if FIXED_AUDIO + sci_glb_clr(REG_PMU_APB_SLEEP_XTLON_CTRL, BIT_AP_SLEEP_XTL_ON); +#endif + return 0; +} + +static inline int arch_audio_memory_sleep_enable(void) +{ +#if 0 +#if FIXED_AUDIO + sci_glb_clr(REG_PMU_APB_MEM_PD_CFG0, BITS_AON_MEM_PD_CFG_VBC(3)); + sci_glb_clr(REG_PMU_APB_MEM_PD_CFG0, BITS_AON_MEM_PD_CFG_AUD(3)); +#endif + return 0; +#endif +} + +static inline int arch_audio_memory_sleep_disable(void) +{ +#if 0 +#if FIXED_AUDIO + sci_glb_set(REG_PMU_APB_MEM_PD_CFG0, BITS_AON_MEM_PD_CFG_VBC(1)); + sci_glb_set(REG_PMU_APB_MEM_PD_CFG0, BITS_AON_MEM_PD_CFG_AUD(1)); +#endif + return 0; +#endif +} + +static inline int arch_audio_codec_adie_loop_clk_en(int on) +{ + int ret = 0; + if (on) + ret = sci_adi_write(ANA_REG_GLB_ARM_CLK_EN, BIT_CLK_AUD_LOOP_EN, BIT_CLK_AUD_LOOP_EN); + else + ret = sci_adi_write(ANA_REG_GLB_ARM_CLK_EN, 0, BIT_CLK_AUD_LOOP_EN); + return ret; +} + +/* ------------------------------------------------------------------------- */ + +/* i2s setting */ +static inline const char *arch_audio_i2s_clk_name(int id) +{ +#if FIXED_AUDIO + switch (id) { + case 0: + return "clk_iis0"; + break; + case 1: + return "clk_iis1"; + break; + case 2: + return "clk_iis2"; + break; + case 3: + return "clk_iis3"; + break; + default: + break; + } +#endif + return NULL; +} + +static inline int arch_audio_i2s_enable(int id) +{ + int ret = 0; + +#if FIXED_AUDIO + switch (id) { + case 0: + sci_glb_set(REG_AP_APB_APB_EB, BIT_IIS0_EB); + break; + case 1: + sci_glb_set(REG_AP_APB_APB_EB, BIT_IIS1_EB); + break; + case 2: + sci_glb_set(REG_AP_APB_APB_EB, BIT_IIS2_EB); + break; + case 3: + sci_glb_set(REG_AP_APB_APB_EB, BIT_IIS3_EB); + break; + default: + ret = -ENODEV; + break; + } +#endif + + return ret; +} + +static inline int arch_audio_i2s_disable(int id) +{ + int ret = 0; + +#if FIXED_AUDIO + switch (id) { + case 0: + sci_glb_clr(REG_AP_APB_APB_EB, BIT_IIS0_EB); + break; + case 1: + sci_glb_clr(REG_AP_APB_APB_EB, BIT_IIS1_EB); + break; + case 2: + sci_glb_clr(REG_AP_APB_APB_EB, BIT_IIS2_EB); + break; + case 3: + sci_glb_clr(REG_AP_APB_APB_EB, BIT_IIS3_EB); + break; + default: + ret = -ENODEV; + break; + } +#endif + + return ret; +} + +static inline int arch_audio_i2s_tx_dma_info(int id) +{ + int ret = 0; + +#if FIXED_AUDIO + switch (id) { + case 0: + ret = DMA_IIS0_TX; + break; + case 1: + ret = DMA_IIS1_TX; + break; + case 2: + ret = DMA_IIS2_TX; + break; + case 3: + ret = DMA_IIS3_TX; + break; + default: + ret = -ENODEV; + break; + } +#endif + + return ret; +} + +static inline int arch_audio_i2s_rx_dma_info(int id) +{ + int ret = 0; + +#if FIXED_AUDIO + switch (id) { + case 0: + ret = DMA_IIS0_RX; + break; + case 1: + ret = DMA_IIS1_RX; + break; + case 2: + ret = DMA_IIS2_RX; + break; + case 3: + ret = DMA_IIS3_RX; + break; + default: + ret = -ENODEV; + break; + } + +#endif + + return ret; +} + +static inline int arch_audio_i2s_reset(int id) +{ + int ret = 0; + +#if FIXED_AUDIO + switch (id) { + case 0: + sci_glb_set(REG_AP_APB_APB_RST, BIT_IIS0_SOFT_RST); + udelay(10); + sci_glb_clr(REG_AP_APB_APB_RST, BIT_IIS0_SOFT_RST); + break; + case 1: + sci_glb_set(REG_AP_APB_APB_RST, BIT_IIS1_SOFT_RST); + udelay(10); + sci_glb_clr(REG_AP_APB_APB_RST, BIT_IIS1_SOFT_RST); + break; + case 2: + sci_glb_set(REG_AP_APB_APB_RST, BIT_IIS2_SOFT_RST); + udelay(10); + sci_glb_clr(REG_AP_APB_APB_RST, BIT_IIS2_SOFT_RST); + break; + case 3: + sci_glb_set(REG_AP_APB_APB_RST, BIT_IIS3_SOFT_RST); + udelay(10); + sci_glb_clr(REG_AP_APB_APB_RST, BIT_IIS3_SOFT_RST); + break; + default: + ret = -ENODEV; + break; + } +#endif + + return ret; +} + +/* sc8830 AP IIS and CP IIS are different. AP IIS cann't switch to other master*/ +static inline int arch_audio_i2s_switch(int id, int master) +{ + int ret = 0; + +#if FIXED_AUDIO + switch (master) { + case AUDIO_TO_AP_ARM_CTRL: + break; + case AUDIO_NO_CHANGE: + ret = AUDIO_TO_AP_ARM_CTRL; + break; + default: + ret = -ENODEV; + break; + } +#endif + + return ret; +} + +#endif diff --git a/include/soc/sprd/adc.h b/include/soc/sprd/adc.h new file mode 100644 index 00000000..46473272 --- /dev/null +++ b/include/soc/sprd/adc.h @@ -0,0 +1,144 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************ + * Automatically generated C config: don't edit * + ************************************************ + */ + +#ifndef __CTL_ADC_H__ +#define __CTL_ADC_H__ + +/* adc channel definition */ +#define ADC_CHANNEL_INVALID -1 +enum adc_channel { + ADC_CHANNEL_0 = 0, //ADCI0 + ADC_CHANNEL_1 = 1, //ADCI1 + ADC_CHANNEL_2 = 2, //ADCI2 + ADC_CHANNEL_3 = 3, //ADCI3 + ADC_CHANNEL_PROG = 4, + ADC_CHANNEL_VBAT = 5, + ADC_CHANNEL_VCHGSEN = 6, + ADC_CHANNEL_VCHGBG = 7, + ADC_CHANNEL_ISENSE = 8, + ADC_CHANNEL_TPYD = 9, + ADC_CHANNEL_TPYU = 10, + ADC_CHANNEL_TPXR = 11, + ADC_CHANNEL_TPXL = 12, + ADC_CHANNEL_DCDCCORE = 13, + ADC_CHANNEL_DCDCARM = 14, + ADC_CHANNEL_DCDCMEM = 15, + ADC_CHANNEL_DCDCLDO = 16, +#if defined(CONFIG_ARCH_SC8825) + ADC_CHANNEL_VBATBK = 17, + ADC_CHANNEL_HEADMIC = 18, + ADC_CHANNEL_LDO0 = 19, /* ldo rf/abb/cama */ + ADC_CHANNEL_LDO1 = 20, /* ldo v3v/v28/vsim0/vsim1/cammot/sd0/usb/dvdd18/v25 */ + ADC_CHANNEL_LDO2 = 21, /* ldo camio/camcore/cmmb1v2/cmmb1v8/v18/sd1/sd3/ */ + ADC_MAX = 21, +#elif defined(CONFIG_ARCH_SCX35) + ADC_CHANNEL_DCDCGPU = 17, + ADC_CHANNEL_DCDCWRF = 18, + ADC_CHANNEL_VBATBK = 19, + ADC_CHANNEL_HEADMIC = 20, + ADC_CHANNEL_LDO0 = 21, + ADC_CHANNEL_LDO1 = 22, + ADC_CHANNEL_LDO2 = 23, + ADC_CHANNEL_WHTLED = 24, + ADC_CHANNEL_OTP = 25, + ADC_CHANNEL_LPLDO0 = 26, /*SIM0/SIM1/SIM2/EMMCCORE/VDD28/VDD25/USB, Low power mode reference*/ + ADC_CHANNEL_LPLDO1 = 27, /*CAMD/EMMCIO/VDD18/AVDD18/CAMIO/CLSG, Low power mode reference*/ + ADC_CHANNEL_LPLDO2 = 28, /*RF0/RF1/RF2/CAMA/SD/CAMMOT, Low power mode reference*/ + ADC_CHANNEL_WHTLED_VFB = 29, + ADC_CHANNEL_USBDP = 30, + ADC_CHANNEL_USBDM = 31, + ADC_MAX = 31, +#endif +}; + +struct adc_sample_data { + int sample_num; /* from 1 to 15 */ + int sample_bits; /*0: 10bits mode, 1:12 bits mode */ + int signal_mode; /*0:resistance,1:capacitance */ + int sample_speed; /*0:quick mode, 1: slow mode */ + int scale; /*0:little scale, 1:big scale */ + int hw_channel_delay; /*0:disable, 1:enable */ + int channel_id; /*channel id of software, Or dedicatid hw channel number */ + int channel_type; /*0: software, 1: slow hardware , 2: fast hardware */ + int *pbuf; +}; + +void sci_adc_init(void); +void sci_adc_dump_register(void); + +/* +* Use this interface to get adc values and you can config adc sample behavior. +* The max number adc value is 16 now, Pls notice the return value; +*/ +int sci_adc_get_values(struct adc_sample_data *adc); + +/* + * get adc channel voltage divider ratio. + */ +void sci_adc_get_vol_ratio(unsigned int channel_id, int scale, unsigned int* div_numerators, + unsigned int* div_denominators ); + +/* + * get mux adc channel voltage divider ratio. + */ +unsigned int sci_adc_get_ratio(unsigned int channel_id, int scale, int mux); + + +/* + * Use this interface to get one adc value and this function have set default + * adc sample behavior. + */ +static inline int sci_adc_get_value(unsigned int channel, int scale) +{ + struct adc_sample_data adc; + int32_t result[1]; + + adc.channel_id = channel; + adc.channel_type = 0; + adc.hw_channel_delay = 0; + adc.pbuf = &result[0]; + adc.sample_bits = 1; + adc.sample_num = 1; + adc.sample_speed = 0; + adc.scale = scale; + adc.signal_mode = 0; + + if (0 != sci_adc_get_values(&adc)) { + printk("sci_adc_get_value, return error\n"); + sci_adc_dump_register(); + BUG(); + } + + return result[0]; +} + +/* + * get adc channel raw data + */ +int sci_get_adc_data(unsigned int channel, unsigned int scale); + +/* + * get adc channel voltage + */ +int sci_adc_vol_request(unsigned int channel, int scale, int mux, int* adc_data); + +/* + * Use this interface to get adc value by current sense + */ +int sci_adc_get_value_by_isen(unsigned int channel, int scale, int isen); + +#endif diff --git a/include/soc/sprd/adi.h b/include/soc/sprd/adi.h new file mode 100755 index 00000000..525a5419 --- /dev/null +++ b/include/soc/sprd/adi.h @@ -0,0 +1,106 @@ +/* * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ADI_H__ +#define __ADI_H__ + +#define SPRD_ADISLAVE_BASE (SPRD_ADI_BASE+0x8000) +#define SPRD_ADISLAVE_PHYS (SPRD_ADI_PHYS+0x8000) +#define REGS_ADISLAVE_BASE SPRD_ADISLAVE_BASE +#define REGS_ADISLAVE_PHYS SPRD_ADISLAVE_PHYS + +#define REGS_MISC_BASE (SPRD_ADI_BASE) +#define REGS_MISC_PHYS (SPRD_ADI_PHYS) + +#ifdef CONFIG_SC_INTERNAL_ADI +int sci_adi_init(void); + +int sci_adi_read(unsigned long reg); + +int sci_is_adi_vaddr(unsigned long reg); + +/* + * using adi method to translate pysical address to virtual address + * return 0 is ok. + */ +int sci_adi_p2v(unsigned long paddr, unsigned long *vaddr); + + +/* + * WARN: the arguments (reg, value) is different from + * the general __raw_writel(value, reg) + * For sci_adi_write_fast: if set sync 1, then this function will + * return until the val have reached hardware.otherwise, just + * async write(is maybe in software buffer) + */ +int sci_adi_write_fast(unsigned long reg, u16 val, u32 sync); +int sci_adi_write(unsigned long reg, u16 or_val, u16 clear_msk); +void __init ana_init_irq(void); + +#else + +#include <asm-generic/errno-base.h> + +static inline int sci_adi_init(void) +{ + return -ENODEV; +} + +static inline int sci_adi_read(unsigned long reg) +{ + return -ENODEV; +} + +static inline int sci_is_adi_vaddr(unsigned long vaddr) +{ + return 0; +} + +/* + * using adi method to translate pysical address to virtual address + * return 0 is ok. + */ +static inline int sci_adi_p2v(unsigned long paddr, unsigned long *vaddr) +{ + return -ENODEV; +} + +static inline int sci_adi_write_fast(unsigned long reg, u16 val, u32 sync) +{ + return -ENODEV; +} + +static inline int sci_adi_write(unsigned long reg, u16 or_val, u16 clear_msk) +{ + return -ENODEV; +} + +static inline void ana_init_irq(void){ } + +#endif +static inline int sci_adi_raw_write(unsigned long reg, u16 val) +{ + return sci_adi_write_fast(reg, val, 1); +} + +static inline int sci_adi_set(unsigned long reg, u16 bits) +{ + return sci_adi_write(reg, bits, 0); +} + +static inline int sci_adi_clr(unsigned long reg, u16 bits) +{ + return sci_adi_write(reg, 0, bits); +} + +#endif diff --git a/include/soc/sprd/arch_lock.h b/include/soc/sprd/arch_lock.h new file mode 100644 index 00000000..649daed4 --- /dev/null +++ b/include/soc/sprd/arch_lock.h @@ -0,0 +1,181 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * Author: steve.zhan <steve.zhan@spreadtrum.com> + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ARCH_LOCK_H +#define __ARCH_LOCK_H + +#include <linux/hwspinlock.h> +#include <linux/io.h> + +#include <soc/sprd/sci.h> +#include <soc/sprd/sci_glb_regs.h> + +#define arch_get_hwlock(_ID_) (hwlocks[_ID_]) + +/* processor specific write lock id */ +#define HWSPINLOCK_WRITE_KEY (0x1) + +/* hwspinlock id */ +#define HWLOCK_ADI (0) +#define HWLOCK_GLB (1) +#define HWLOCK_AGPIO (2) +#define HWLOCK_AEIC (3) +#define HWLOCK_ADC (4) +#define HWLOCK_EFUSE (8) + +/* untoken lock value */ +#define HWSPINLOCK_NOTTAKEN_V1 (0x55aa10c5) +#define HWSPINLOCK_NOTTAKEN_V0 (0x524c534c) + +/* hwspinlock number */ +#ifdef CONFIG_ARCH_WHALE + #define HWSPINLOCK_ID_TOTAL_NUMS (32) +#else + #define HWSPINLOCK_ID_TOTAL_NUMS (64) +#endif + +#define arch_hwlock_fast(_LOCK_ID_) do { \ + while (!arch_hwlock_fast_trylock(_LOCK_ID_)) \ + cpu_relax();} while (0) + +#define arch_hwunlock_fast(_LOCK_ID_) do { \ + arch_hwlock_fast_unlock(_LOCK_ID_);} while (0) + +extern int hwspinlock_vid_early; +extern struct hwspinlock *hwlocks[]; +int early_hwspinlocks_init(void); +int sprd_hwspinlock_isbusy(unsigned int lock_id); +int sprd_hwspinlocks_isbusy(void); +int sprd_hwspinlock_master_id(unsigned int lock_id); +int sprd_record_hwlock_sts(unsigned int lock_id, unsigned int sts); + +static void early_fast_hwlock_init(unsigned int lock_id) +{ + static int early_hwlock_init = 0; + + if (early_hwlock_init == 0){ + writel_relaxed(BIT_SPINLOCK_EB, (void __iomem *)(REG_GLB_SET(REG_AP_AHB_AHB_EB))); + writel_relaxed(BIT_SPLK_EB, (void __iomem *)(REG_GLB_SET(REG_AON_APB_APB_EB0))); + } + + if (lock_id < 31) + hwspinlock_vid_early = readl_relaxed((void *)(SPRD_HWSPINLOCK1_BASE + 0xFFC)); + else if(lock_id < 63) + hwspinlock_vid_early = readl_relaxed((void *)(SPRD_HWSPINLOCK0_BASE + 0xFFC)); + else + hwspinlock_vid_early = 0; + + early_hwlock_init = 1; +} + +static unsigned long early_hwlock_addr(unsigned int id) +{ + unsigned long addr = 0; + + if (hwspinlock_vid_early == 0x100 || hwspinlock_vid_early == 0x200 + || hwspinlock_vid_early == 0x300) { + if (id < 31) + addr = SPRD_HWSPINLOCK1_BASE + 0x800 + 0x4*id; + else if(id < 63) + addr = SPRD_HWSPINLOCK0_BASE + 0x800 + 0x4*id; + else + printk(KERN_ERR "hwspinlock id [%d] is wrong!\n",id); + } else if (hwspinlock_vid_early == 0x0) { + addr = SPRD_HWSPINLOCK0_BASE + 0x80 + 0x4*id; + } else + printk(KERN_ERR "hwspinlock module version [0x%x] is wrong!\n",hwspinlock_vid_early); + + return addr; +} + +static int arch_hwlock_fast_trylock(unsigned int lock_id) +{ + void __iomem *addr; + + early_fast_hwlock_init(lock_id); + addr = (void __iomem *)early_hwlock_addr(lock_id); + if (!addr){ + printk(KERN_ERR "Hwspinlock [%d] lock failed,get wrong addr!\n",lock_id); + return -ENXIO; + } + + if (hwspinlock_vid_early == 0x100 || hwspinlock_vid_early == 0x200 + || hwspinlock_vid_early == 0x300) { + if (!readl_relaxed(addr)) + goto __locked; + } else if (hwspinlock_vid_early == 0) { + if (HWSPINLOCK_NOTTAKEN_V0 == __raw_readl(addr)) { + writel_relaxed(HWSPINLOCK_WRITE_KEY, addr); + if (HWSPINLOCK_WRITE_KEY == readl_relaxed(addr)) { + goto __locked; + } + } + } + + printk(KERN_ERR "Hwspinlock [%d] lock failed!\n",lock_id); + return 0; + +__locked: +#ifdef CONFIG_64BIT + dsb(sy); +#else + dsb(); +#endif + sprd_record_hwlock_sts(lock_id, 1); + return 1; +} + +static void arch_hwlock_fast_unlock(unsigned int lock_id) +{ + void __iomem *addr = (void __iomem *)early_hwlock_addr(lock_id); +#ifdef CONFIG_64BIT + dsb(sy); +#else + dsb(); +#endif + + if (hwspinlock_vid_early == 0x100 || hwspinlock_vid_early == 0x200 + || hwspinlock_vid_early == 0x300) + writel_relaxed(HWSPINLOCK_NOTTAKEN_V1, addr); + else + writel_relaxed(HWSPINLOCK_NOTTAKEN_V0, addr); + + sprd_record_hwlock_sts(lock_id, 0); +} + +static void __arch_default_lock(unsigned int lock_id, unsigned long *flags) +{ +#ifdef CONFIG_SC_FPGA +/* for the hwspinlock not in the bitfile */ +#else + if (hwlocks[lock_id]) + WARN_ON(IS_ERR_VALUE + (hwspin_lock_timeout_irqsave(hwlocks[lock_id], -1, flags))); + else + arch_hwlock_fast(lock_id); +#endif +} + +static void __arch_default_unlock(unsigned int lock_id, unsigned long *flags) +{ +#ifdef CONFIG_SC_FPGA +/* for the hwspinlock not in the bitfile */ +#else + if (hwlocks[lock_id]) + hwspin_unlock_irqrestore(hwlocks[lock_id], flags); + else + arch_hwunlock_fast(lock_id); +#endif +} + +#endif diff --git a/include/soc/sprd/arch_misc.h b/include/soc/sprd/arch_misc.h new file mode 100644 index 00000000..2696115c --- /dev/null +++ b/include/soc/sprd/arch_misc.h @@ -0,0 +1,171 @@ +/* + * Copyright (C) 2013 Spreadtrum Communications Inc. + * Copyright (C) steve.zhan + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#define SCX35_ALPHA_TAPOUT (0x8300aaaa) +#define SCX35_ALPHA_TAPOUT_MASK (0xFFFFFFFF) + +#define SCX35_BETA_TAPOUT (0x8300a001) +#define SCX35_BETA_TAPOUT_MASK (0xFFFFFFFF) + +#define SCX35G_ALPHA_TAPOUT (0x8730b000) +#define SCX35G_ALPHA_TAPOUT_MASK (0xFFFFF000) + +#define SCX30G2_ALPHA_TAPOUT (0x8730C000) +#define SCX30G2_ALPHA_TAPOUT_MASK (0xFFFFF000) + +#define SCX9630_ALPHA_TAPOUT (0x96300000) +#define SCX9630_ALPHA_TAPOUT_MASK (0xFFFFF000) + +#define SCX35L64_ALPHA_TAPOUT (0x96310000) +#define SCX35L64_ALPHA_TAPOUT_MASK (0xFFFF0000) + +#define SCX9820_ALPHA_TAPOUT (0x96320000) +#define SCX9820_ALPHA_TAPOUT_MASK (0xFFFF0000) + +#define SCX7720_ALPHA_TAPOUT (0x88600000) +#define SCX7720_ALPHA_TAPOUT_MASK (0xFFFF0000) + +#define SCX9830I_ALPHA_TAPOUT (0x6b4c5300) +#define SCX9830I_ALPHA_TAPOUT_MASK (0xFFFFFFFF) + +/** + * sci_get_chip_id - read chip id + * + * + * Return read the chip id + */ +u32 sci_get_chip_id(void); + +/** + * sci_get_ana_chip_id - read a-die chip id + * + * Return the a-die chip id, example: 0X2711A000 + */ +u32 sci_get_ana_chip_id(void); + +#define MASK_ANA_VER ( 0xFFF ) +enum sci_ana_chip_ver { + SC2711AA = 0x000, + SC2711AB = 0x000, /* discard */ + SC2711AC = 0x002, + SC2711BA = 0x100, + SC2713CA = 0xA00, + + /* SC2723 */ + SC2723ES = 0x090, + SC2723TS = 0x0C0, + //TODO: Add more ana chip version here +}; + +/** + * sci_get_ana_chip_ver - read a-die chip version + * + * Return the a-die chip version, example: 0X100 + */ +int sci_get_ana_chip_ver(void); + +/** + * sci_ana_chip_vers_is_compatible + * + * Check if the given "chip_ver" string matches the a-die chip on board + */ +static inline int sci_ana_chip_ver_is_compatible(enum sci_ana_chip_ver compat) +{ + return sci_get_ana_chip_ver() == (u32)compat; +} + +/** + * + * sc_init_chip_id(void) - read chip id from hardware and save it. + * + */ +void __init sc_init_chip_id(void); + +void set_section_ro(unsigned long virt, unsigned long numsections); + + +#define IS_CPU(name, id, mask) \ +static inline int soc_id_is_##name(void) \ +{ \ + pr_info("chip id is %x\n",sci_get_chip_id()); \ + return ((sci_get_chip_id() & mask) == (id & mask)); \ +} + +IS_CPU(sc8735v0, SCX35_ALPHA_TAPOUT, SCX35_ALPHA_TAPOUT_MASK) +IS_CPU(sc8735v1, SCX35_BETA_TAPOUT, SCX35_BETA_TAPOUT_MASK) +IS_CPU(sc8735gv0, SCX35G_ALPHA_TAPOUT, SCX35G_ALPHA_TAPOUT_MASK) +IS_CPU(sc8730g2v0, SCX30G2_ALPHA_TAPOUT, SCX30G2_ALPHA_TAPOUT_MASK) +IS_CPU(sc9631v0, SCX35L64_ALPHA_TAPOUT, SCX35L64_ALPHA_TAPOUT_MASK) +IS_CPU(sc9630v0, SCX9630_ALPHA_TAPOUT, SCX9630_ALPHA_TAPOUT_MASK) +IS_CPU(sc9820v0, SCX9820_ALPHA_TAPOUT, SCX9820_ALPHA_TAPOUT_MASK) +IS_CPU(sc7720v0, SCX7720_ALPHA_TAPOUT, SCX7720_ALPHA_TAPOUT_MASK) +IS_CPU(sc9830iv0, SCX9830I_ALPHA_TAPOUT, SCX9830I_ALPHA_TAPOUT_MASK) + + +/*Driver can use this MACRO to distinguish different chip code */ +#define soc_is_scx35_v0() soc_id_is_sc8735v0() +#define soc_is_scx35_v1() soc_id_is_sc8735v1() +#define soc_is_scx35g_v0() soc_id_is_sc8735gv0() +#define soc_is_scx30g2_v0() soc_id_is_sc8730g2v0() +#define soc_is_scx35l64_v0() soc_id_is_sc9631v0() +#define soc_is_scx9630_v0() soc_id_is_sc9630v0() +#define soc_is_scx9820_v0() soc_id_is_sc9820v0() +#define soc_is_scx7720_v0() soc_id_is_sc7720v0() +#define soc_is_scx9830i_v0() soc_id_is_sc9830iv0() + + +/** +* read value from virtual address. Pls make sure val is not NULL. +* return 0 is successful +*/ +int sci_read_va(ulong vreg, ulong *val); + +/** +* write value to virtual address. if clear_msk is ~0, or_val will fully set to vreg. +* return 0 is successful +*/ +int sci_write_va(ulong vreg, const ulong or_val, const u32 clear_msk); + +/** +* read value from pysical address. Pls make sure val is not NULL. +* return 0 is successful +*/ +int sci_read_pa(ulong preg, ulong *val); + +/** +* write value to pysical address. if clear_msk is ~0, or_val will fully set to paddr. +* return 0 is successful +*/ +int sci_write_pa(ulong paddr, const ulong or_val, const u32 clear_msk); + +#define SPRD_CHIPID_7715 (0x77150000) +#define SPRD_CHIPID_8815 (0X88150000) + +static inline int soc_is_sc7715(void) +{ + unsigned int flag = 0; + flag = sci_get_chip_id() & 0xffff0000; + if ((SPRD_CHIPID_7715 == flag) + ||(SPRD_CHIPID_8815 == flag)) + { + return 1; + } + else + { + pr_err("%s error chip id\n", __func__); + return 0; + } +} diff --git a/include/soc/sprd/board.h b/include/soc/sprd/board.h new file mode 100644 index 00000000..3e2be639 --- /dev/null +++ b/include/soc/sprd/board.h @@ -0,0 +1,451 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARCH_BOARD_H +#define __ASM_ARCH_BOARD_H + +#ifdef CONFIG_MACH_SP8825EA +#include "__board-sp8825ea.h" +#endif + +#ifdef CONFIG_MACH_SPX35EA +#include "__board-sp8830ea.h" +#endif + +#ifdef CONFIG_MACH_SPX35EB +#include "__board-sp8830eb.h" +#endif + +#ifdef CONFIG_MACH_SP8835EB +#include "__board-sp8835eb.h" +#endif + +#ifdef CONFIG_MACH_SPX35EC +#include "__board-sp8830ec.h" +#endif + +#ifdef CONFIG_MACH_SP8830GEA +#include "__board-sp8830gea.h" +#endif + +#ifdef CONFIG_MACH_SP8730SEA +#include "__board-sp8730sea.h" +#endif + +#ifdef CONFIG_MACH_SP7730GGA +#include "__board-sp7730gga.h" +#endif + +#ifdef CONFIG_MACH_SP7731GGA_LC +#include "__board-sp7731gga_lc.h" +#endif + +#ifdef CONFIG_MACH_SP7730GGA_LC +#include "__board-sp7730gga_lc.h" +#endif + +#ifdef CONFIG_MACH_SP7730GGAOPENPHONE +#include "__board-sp7730ggaopenphone.h" +#endif + +#ifdef CONFIG_MACH_SP7731GEA +#include "__board-sp7731gea.h" +#endif + +#ifdef CONFIG_MACH_SP7732AEA +#include "__board-sp7732Aea.h" +#endif + +#ifdef CONFIG_MACH_SP8730SEEA +#include "__board-sp8730seea.h" +#endif + +#ifdef CONFIG_MACH_SP8730SEEA_QHD +#include "__board-sp8730seea_qhd.h" +#endif + +#ifdef CONFIG_MACH_SP8730SEEA_JIG +#include "__board-sp8730seea_jig.h" +#endif + +#ifdef CONFIG_MACH_SP7731GEA_HD2 +#include "__board-sp7731gea_hd2.h" +#endif + +#ifdef CONFIG_MACH_SP7731GEA_QHD +#include "__board-sp7731gea_qhd.h" +#endif + +#ifdef CONFIG_MACH_SP7731GEA_HD +#include "__board-sp7731gea_hd.h" +#endif + +#ifdef CONFIG_MACH_SP7720EA +#include "__board-sp7720ea.h" +#endif + +#ifdef CONFIG_MACH_SP7731GEA_HDR +#include "__board-sp7731gea_hdr.h" +#endif + +#ifdef CONFIG_MACH_SP7731GEPIKE +#include "__board-sp7731gepike.h" +#endif + +#ifdef CONFIG_MACH_SP7731GEA_FWVGA +#include "__board-sp7731gea_fwvga.h" +#endif + +#ifdef CONFIG_MACH_SP7731GEAOPENPHONE +#include "__board-sp7731geaopenphone.h" +#endif + +#ifdef CONFIG_MACH_SP7731GEA_LC +#include "__board-sp7731gea_lc.h" +#endif + +#ifdef CONFIG_MACH_SP8830GA +#include "__board-sp8830ga.h" +#endif + +#ifdef CONFIG_MACH_SP7730GA +#include "__board-sp7730ga.h" +#endif + +#ifdef CONFIG_MACH_KANAS_W +#include "__board-kanas_w.h" +#endif + +#ifdef CONFIG_MACH_KANAS_TD +#include "__board-kanas_td.h" +#endif + +#ifdef CONFIG_MACH_SP7730EC +#include "__board-sp7730ec.h" +#endif + +#ifdef CONFIG_MACH_SC9620OPENPHONE +#include "__board-sc9620openphone.h" +#endif + +#ifdef CONFIG_MACH_SC9620OPENPHONE_ZT +#include "__board-sc9620openphone_zt.h" +#endif + +#ifdef CONFIG_MACH_SC9620FPGA +#include "__board-sc9620fpga.h" +#endif + +#ifdef CONFIG_MACH_SP7730ECTRISIM +#include "__board-sp7730ectrisim.h" +#endif + +#ifdef CONFIG_MACH_SP5735EA +#include "__board-sp5735ea.h" +#endif + +#ifdef CONFIG_MACH_SP5735C1EA +#include "__board-sp5735c1ea.h" +#endif + +#if defined (CONFIG_MACH_SPX35FPGA) || defined (CONFIG_MACH_SPX15FPGA) || defined(CONFIG_MACH_SPX35LFPGA) || defined(CONFIG_MACH_PIKELFPGA) +#include "__board-sp8830fpga.h" +#endif + +#ifdef CONFIG_MACH_SP9820FPGA +#include "__board-sp9820fpga.h" +#endif + +#ifdef CONFIG_MACH_SP9820EA +#include "__board-sp9820ea.h" +#endif + +#ifdef CONFIG_MACH_COREPRIMELITE +#include "__board-coreprimelite.h" +#endif + +#ifdef CONFIG_MACH_TIZENZ3_3G +#include "__board-tizenz3_3g.h" +#endif + +#ifdef CONFIG_MACH_SHARKLS_Z3LTE +#include "__board-sharkls_z3lte.h" +#endif + +#if defined (CONFIG_MACH_SP9836AEA_4MOD) || defined(CONFIG_MACH_SP9836AEA_3MOD) +#include "__board-sp9836aea.h" +#endif + +#if defined (CONFIG_MACH_SP9838AEA_5MOD) || defined(CONFIG_MACH_SP9838AEA_POWER_DEBUG) || defined(CONFIG_MACH_SP9838AEA_8CORE_LIGHT_SLEEP) || defined(CONFIG_MACH_SP9838AEA_FHD) || defined(CONFIG_MACH_SP9838AEA_FPGA) +#include "__board-sp9838aea.h" +#endif + +#if defined (CONFIG_MACH_SS_SHARKLT8) || defined(CONFIG_MACH_SS_SHARKLT8LIGHTSLEEP) +#include "__board-ss_sharklt8.h" +#endif + +#ifdef CONFIG_MACH_SP9630EA3MN +#include "__board-sp9630ea3mn.h" +#endif + +#ifdef CONFIG_MACH_SP9630EA4MN +#include "__board-sp9630ea4mn.h" +#endif + +#ifdef CONFIG_MACH_SP9830AEA_5M_H100 +#include "__board-sp9830aea_5m_h100.h" +#endif + +#ifdef CONFIG_MACH_SP9830AEA_5M_VOLTE +#include "__board-sp9830aea_5m_volte.h" +#endif + +#ifdef CONFIG_MACH_SP9830AEB_5M_H100 +#include "__board-sp9830aeb_5m_h100.h" +#endif + +#ifdef CONFIG_MACH_SP9830AEC_4M_H100 +#include "__board-sp9830aec_4m_h100.h" +#endif + +#ifdef CONFIG_MACH_SP9830IEA_4M_H100 +#include "__board-sp9830iea_4m_h100.h" +#endif + +#ifdef CONFIG_MACH_SP9830IEA_5M_H100 +#include "__board-sp9830iea_5m_h100.h" +#endif + +#ifdef CONFIG_MACH_SP9830IEB_5M_H100 +#include "__board-sp9830ieb_5m_h100.h" +#endif + +#ifdef CONFIG_MACH_SP9830IEC_4M_H100 +#include "__board-sp9830iec_4m_h100.h" +#endif + +#ifdef CONFIG_MACH_SP7735EC +#include "__board-sp7735ec.h" +#endif + +#if defined (CONFIG_MACH_SP7715EA) || defined(CONFIG_MACH_SPX15) +#include "__board-sp7715ea.h" +#endif + +#ifdef CONFIG_MACH_SP7715EATRISIM +#include "__board-sp7715eatrisim.h" +#endif + +#ifdef CONFIG_MACH_SP7715EAOPENPHONE +#include "__board-sp7715eaopenphone.h" +#endif + +#ifdef CONFIG_MACH_SP6815GA +#include "__board-sp6815ga.h" +#endif +#ifdef CONFIG_MACH_SP7715GA +#include "__board-sp7715ga.h" +#endif + +#ifdef CONFIG_MACH_SP7715GATRISIM +#include "__board-sp7715gatrisim.h" +#endif + +#ifdef CONFIG_MACH_SP8815GA +#include "__board-sp8815ga.h" +#endif + +#ifdef CONFIG_MACH_SP8815GAOPENPHONE +#include "__board-sp8815gaopenphone.h" +#endif + +#ifdef CONFIG_MACH_POCKET2 +#include "__board-pocket2.h" +#endif + +#ifdef CONFIG_MACH_CORSICA_VE +#include "__board-corsica_ve.h" +#endif + +#ifdef CONFIG_MACH_VIVALTO +#include "__board-vivalto.h" +#endif + +#ifdef CONFIG_MACH_YOUNG2 +#include "__board-young2.h" +#endif + +#ifdef CONFIG_MACH_HIGGS +#include "__board-higgs.h" +#endif + +#ifdef CONFIG_MACH_TSHARKWSAMSUNG +#include "__board-tsharkwsamsung.h" +#endif + +#ifdef CONFIG_MACH_CORE3 +#include "__board-core3.h" +#endif +#ifdef CONFIG_MACH_TSHARK2TABE +#include "__board-tshark2tabe.h" +#endif +#ifdef CONFIG_MACH_GRANDPRIME3G_VE +#include "__board-grandprime3g_ve.h" +#endif +#ifdef CONFIG_MACH_GRANDPRIME_DTV +#include "__board-grandprime_dtv.h" +#endif +#ifdef CONFIG_MACH_PIKEAYOUNG2DTV +#include "__board-pikeayoung2dtv.h" +#endif + +#ifdef CONFIG_MACH_COREPRIME3G_VE +#include "__board-coreprime3g_ve.h" +#endif +#include <asm/sizes.h> + +#ifdef CONFIG_SPRD_IOMMU + #define SPRD_H264_DECODE_SIZE (0 * SZ_1M) +#else + #define SPRD_H264_DECODE_SIZE (25 * SZ_1M) +#endif + +#ifdef CONFIG_ION + #ifdef CONFIG_ARCH_SCX35 + #ifdef CONFIG_SPRD_IOMMU + #define SPRD_ION_MM_SIZE (0 * SZ_1M) + #else + #ifndef SPRD_ION_MM_SIZE /* should be defined in "__board-sp**.h" already */ + #define SPRD_ION_MM_SIZE (76 * SZ_1M) + #endif + #endif + + #ifndef SPRD_ION_OVERLAY_SIZE /* should be defined in "__board-sp**.h" already */ + #define SPRD_ION_OVERLAY_SIZE (12 * SZ_1M) + #endif + #else + #ifndef SPRD_ION_MM_SIZE + #define SPRD_ION_MM_SIZE (CONFIG_SPRD_ION_MM_SIZE * SZ_1M) + #endif + + #ifndef SPRD_ION_OVERLAY_SIZE + #define SPRD_ION_OVERLAY_SIZE (CONFIG_SPRD_ION_OVERLAY_SIZE * SZ_1M) + #endif + #endif +#else /* !ION */ + #define SPRD_ION_MM_SIZE (0 * SZ_1M) + #define SPRD_ION_OVERLAY_SIZE (0 * SZ_1M) +#endif + +#ifdef CONFIG_CMA +#ifdef CONFIG_SPRD_IOMMU + #define CMA_MARGIN (0 * SZ_1M) + #define CMA_RESERVE (0 * SZ_1M) + #define CMA_THRESHOLD (0 * SZ_1M) +#else + #define CMA_MARGIN (0 * SZ_1M) + #define CMA_RESERVE (25 * SZ_1M) + #define CMA_THRESHOLD (4 * SZ_1M) +#endif + #define CMA_ALIGNMENT (4 * SZ_1M) + #define SPRD_ION_MEM_RAW_SIZE (SPRD_ION_MM_SIZE + SPRD_ION_OVERLAY_SIZE + CMA_MARGIN - CMA_RESERVE) + /* ALIGN UP */ + #define SPRD_ION_MEM_SIZE (((SPRD_ION_MEM_RAW_SIZE + (CMA_ALIGNMENT - 1)) & (~(CMA_ALIGNMENT - 1))) + CMA_RESERVE) +#else + #define SPRD_ION_MEM_SIZE (SPRD_ION_MM_SIZE + SPRD_ION_OVERLAY_SIZE) +#endif + +#define SPRD_ION_BASE_USE_VARIABLE +#ifndef SPRD_ION_BASE_USE_VARIABLE +#if defined(CONFIG_MACH_SP7715GA) || defined(CONFIG_MACH_SP7715GATRISIM) || defined(CONFIG_MACH_SP8815GA) || defined(CONFIG_MACH_SP8815GAOPENPHONE) || defined(CONFIG_MACH_SP6815GA) || defined(CONFIG_MACH_SP7731GEA_LC) || defined(CONFIG_MACH_SP7731GGA_LC) || defined(CONFIG_MACH_SP7730GGA_LC)/* Nand 4+2 */ +#define SPRD_ION_MEM_BASE \ + ((CONFIG_PHYS_OFFSET & (~(SZ_256M - 1))) + SZ_256M - SPRD_ION_MEM_SIZE) +#else +#define SPRD_ION_MEM_BASE \ + ((CONFIG_PHYS_OFFSET & (~(SZ_512M - 1))) + SZ_512M - SPRD_ION_MEM_SIZE) +#endif +#else + +#if (defined(CONFIG_MACH_SP8730SEEA) \ + || defined(CONFIG_MACH_SP7732AEA) \ + || defined(CONFIG_MACH_SP8730SEEA_QHD) || defined(CONFIG_MACH_SP8730SEEA_JIG) \ + || defined(CONFIG_MACH_TSHARKCOREPRIME) \ + || defined(CONFIG_MACH_TSHARKGRANDNEO) \ + || defined(CONFIG_MACH_COREPRIME3G_VE) || defined(CONFIG_MACH_TIZENZ3_3G) || defined(CONFIG_MACH_GRANDPRIME_DTV) \ + || defined(CONFIG_MACH_SP9830I) \ + || defined(CONFIG_MACH_SP9830AEA_5M_H100) \ + || defined(CONFIG_MACH_SP9830AEC_4M_H100) \ + || defined(CONFIG_MACH_SP9830AEA_5M_VOLTE) \ + || defined(CONFIG_MACH_SP9630EA4MN) \ + || defined(CONFIG_MACH_SP9630EB4MN) \ + || defined(CONFIG_MACH_GRANDPRIME3G_VE) \ + || defined(CONFIG_MACH_SP7720EA) \ + || defined(CONFIG_MACH_SP7731GEA_HD) \ + || defined(CONFIG_MACH_SP7731GEA_HDR) \ + || defined(CONFIG_MACH_SP7731GEPIKE) \ + || defined(CONFIG_MACH_SP7731GEA_HD2) \ + || defined(CONFIG_MACH_SP7731GEA_QHD)) +#define SPRD_ION_MEM_BASE \ + ((CONFIG_PHYS_OFFSET & (~(SZ_1G - 1))) + SZ_1G - SPRD_ION_MEM_SIZE) +#elif (defined(CONFIG_MACH_TSHARK2TABE)) +#define SPRD_ION_MEM_BASE \ + ((CONFIG_PHYS_OFFSET & (~(SZ_1G_512M - 1))) + SZ_1G_512M - SPRD_ION_MEM_SIZE) +#else +extern phys_addr_t sprd_reserve_limit; +#define SPRD_ION_MEM_BASE (sprd_reserve_limit - SPRD_ION_MEM_SIZE) +#endif + +#endif + + +#define SPRD_ION_MM_BASE (SPRD_ION_MEM_BASE) +#define SPRD_ION_OVERLAY_BASE (SPRD_ION_MEM_BASE + SPRD_ION_MM_SIZE) + +#ifdef CONFIG_PSTORE_RAM +#define SPRD_RAM_CONSOLE_SIZE 0x20000 +#define SPRD_RAM_CONSOLE_START (SPRD_ION_MEM_BASE - SPRD_RAM_CONSOLE_SIZE) +#else +#define SPRD_RAM_CONSOLE_START (SPRD_ION_MEM_BASE) +#endif + +#ifdef CONFIG_FB_LCD_RESERVE_MEM +//#define SPRD_FB_MEM_SIZE SZ_8M +#define SPRD_FB_MEM_SIZE (CONFIG_SPRD_FB_SIZE*SZ_1M) +#define SPRD_FB_MEM_BASE (SPRD_RAM_CONSOLE_START - SPRD_FB_MEM_SIZE) +#endif + +#ifdef CONFIG_SPRD_IQ +#define SPRD_IQ_SIZE SZ_128M +#endif + +//#define SPRD_SYSDUMP_MAGIC (SPRD_ION_MEM_BASE + SPRD_ION_MEM_SIZE - SZ_1M) +#define SPRD_SYSDUMP_MAGIC (0x80000000 + 0x20000000 - (1024<<10)) + +struct sysdump_mem { + unsigned long paddr; + unsigned long vaddr; + unsigned long soff; + size_t size; + int type; +}; + +enum sysdump_type { + SYSDUMP_RAM, + SYSDUMP_MODEM, + SYSDUMP_IOMEM, +}; + +extern int sprd_dump_mem_num; +extern struct sysdump_mem sprd_dump_mem[]; + +#endif diff --git a/include/soc/sprd/busmonitor.h b/include/soc/sprd/busmonitor.h new file mode 100644 index 00000000..8fe21dac --- /dev/null +++ b/include/soc/sprd/busmonitor.h @@ -0,0 +1,374 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SPRD_BUSMONITOR_H__ +#define __SPRD_BUSMONITOR_H__ + +#define AXI_BM_INTC_REG 0x00 +#define AXI_BM_CFG_REG 0x04 +#define AXI_BM_ADDR_MIN_REG 0x08 +#define AXI_BM_ADDR_MAX_REG 0x0C +#define AXI_BM_ADDR_MSK_REG 0x10 +#define AXI_BM_DATA_MIN_L_REG 0x14 +#define AXI_BM_DATA_MIN_H_REG 0x18 +#define AXI_BM_DATA_MAX_L_REG 0x1C +#define AXI_BM_DATA_MAX_H_REG 0x20 +#define AXI_BM_DATA_MSK_L_REG 0x24 +#define AXI_BM_DATA_MSK_H_REG 0x28 +#define AXI_BM_CNT_WIN_LEN_REG 0x2C +#define AXI_BM_PEAK_WIN_LEN_REG 0x30 +#define AXI_BM_MATCH_ADDR_REG 0x34 +#define AXI_BM_MATCH_CMD_REG 0x38 +#define AXI_BM_MATCH_DATA_L_REG 0x3C +#define AXI_BM_MATCH_DATA_H_REG 0x40 +#define AXI_BM_RTRANS_IN_WIN_REG 0x44 +#define AXI_BM_RBW_IN_WIN_REG 0x48 +#define AXI_BM_RLATENCY_IN_WIN_REG 0x4C +#define AXI_BM_WTRANS_IN_WIN_REG 0x50 +#define AXI_BM_WBW_IN_WIN_REG 0x54 +#define AXI_BM_WLATENCY_IN_WIN_REG 0x58 +#define AXI_BM_PEAKBW_IN_WIN_REG 0x5C +#define AXI_BM_MATCH_ID_REG 0x64 + +#define AXI_BM_BUS_STATUS_REG 0X68 + + +#define AHB_BM_INTC_REG 0x00 + +#define SPRD_BM_SUCCESS 0 +#define BM_INT_MSK_STS BIT(31) +#define BM_INT_CLR BIT(29) +#define BM_INT_EN BIT(28) +#define BM_CNT_CLR BIT(4) +#define BM_CNT_START BIT(3) +#define BM_CNT_EN BIT(1) +#define BM_CHN_EN BIT(0) + +#define BM_BS_AWVALID BIT(9) +#define BM_BS_AWREADY BIT(8) +#define BM_BS_WVALID BIT(7) +#define BM_BS_WREADY BIT(6) +#define BM_BS_BVALID BIT(5) +#define BM_BS_BREADY BIT(4) +#define BM_BS_ARVALID BIT(3) +#define BM_BS_ARREADY BIT(2) +#define BM_BS_RVALID BIT(1) +#define BM_BS_RREADY BIT(0) + +#define BM_DEBUG_ALL_CHANNEL 0xFF +#define BM_CHANNEL_ENABLE_FLAGE 0x03FF0000 +#define BM_CHN_NAME_CMD_OFFSET 0x7 + +#define BM_DBG(f,x...) printk(KERN_DEBUG "BM_DEBGU " f, ##x) +#define BM_INFO(f,x...) printk(KERN_INFO "BM_INFO " f, ##x) +#define BM_WRN(f,x...) printk(KERN_WARNING"BM_WRN " f, ##x) +#define BM_ERR(f,x...) printk(KERN_ERR "BM_ERR " f, ##x) + +#define PER_COUTN_LIST_SIZE 128 +/*the buf can store 8 secondes data*/ +#define PER_COUNT_RECORD_SIZE 800 +#define PER_COUNT_BUF_SIZE (64 * 4 * PER_COUNT_RECORD_SIZE) + +#define LOG_FILE_PATH "/mnt/obb/axi_per_log" +//#define LOG_FILE_PATH "/storage/sdcard0/axi_per_log" +/*the log file size about 1.5Mbytes per min*/ +#define LOG_FILE_SECONDS (60 * 30) +#define LOG_FILE_MAX_RECORDS (LOG_FILE_SECONDS * 100) +#define BM_CONTINUE_DEBUG_SIZE 20 + +static struct file *log_file; +static struct semaphore bm_seam; +static int buf_read_index; +static int buf_write_index; +static bool bm_irq_in_process; +/*the star log include a lot of unuseful info, we need skip it.*/ +static int buf_skip_cnt; +long long t_stamp; +static void *per_buf = NULL; + +/*depending on the platform*/ +enum sci_bm_index { + AXI_BM0 = 0x0, + AXI_BM1, + AXI_BM2, + AXI_BM3, + AXI_BM4, + AXI_BM5, + AXI_BM6, + AXI_BM7, + AXI_BM8, + AXI_BM9, + AHB_BM0, + AHB_BM1, + AHB_BM2, + BM_SIZE, +}; + +enum sci_ahb_bm_index { + AHB_BM0_CHN0 = AHB_BM0, + AHB_BM0_CHN1, + AHB_BM0_CHN2, + AHB_BM0_CHN3, + AHB_BM1_CHN0, + AHB_BM1_CHN1, + AHB_BM1_CHN2, + AHB_BM1_CHN3, + AHB_BM2_CHN0, + AHB_BM2_CHN1, + AHB_BM2_CHN2, + BM_CHANNEL_SIZE, +}; + +struct bm_callback_desc { + void (*fun)(void *); + void *data; +}; +static struct bm_callback_desc bm_callback_set[BM_SIZE]; + +enum sci_bm_cmd_index { + BM_STATE = 0x0, + BM_CHANNELS, + BM_AXI_DEBUG_SET, + BM_AHB_DEBUG_SET, + BM_PERFORM_SET, + BM_PERFORM_UNSET, + BM_OCCUR, + BM_CONTINUE_SET, + BM_CONTINUE_UNSET, + BM_DFS_SET, + BM_DFS_UNSET, + BM_PANIC_SET, + BM_PANIC_UNSET, + BM_BW_CNT_START, + BM_BW_CNT_STOP, + BM_BW_CNT_RESUME, + BM_BW_CNT, + BM_BW_CNT_CLR, + BM_DBG_INT_CLR, + BM_DBG_INT_SET, + BM_DISABLE, + BM_ENABLE, + BM_PROF_SET, + BM_PROF_CLR, + BM_CHN_CNT, + BM_RD_CNT, + BM_WR_CNT, + BM_RD_BW, + BM_WR_BW, + BM_RD_LATENCY, + BM_WR_LATENCY, + BM_KERNEL_TIME, + BM_CMD_MAX, +}; + +enum sci_bm_chn { + CHN0 = 0x0, + CHN1, + CHN2, + CHN3, +}; + +enum sci_bm_mode { + R_MODE, + W_MODE, + RW_MODE, + /* + PER_MODE, + RST_BUF_MODE, + */ +}; + +struct bm_per_info { + u32 count; + u32 t_start; + u32 t_stop; + u32 tmp1; + u32 tmp2; + u32 per_data[10][6]; +}; + +struct sci_bm_cfg { + u32 bm_bits; + u32 win_len; + u32 addr_min; + u32 addr_max; + u32 addr_msk; + u32 data_min_l; + u32 data_min_h; + u32 data_max_l; + u32 data_max_h; + u32 data_msk_l; + u32 data_msk_h; + u32 chn; + u32 fun; + u32 data; + u32 peak_win_len; + enum sci_bm_mode bm_mode; +}; + +struct sci_bm_reg { + u32 intc; + u32 cfg; + u32 addr_min; + u32 addr_max; + u32 addr_msk; + u32 data_min_l; + u32 data_min_h; + u32 data_max_l; + u32 data_max_h; + u32 data_msk_l; + u32 data_msk_h; + u32 cnt_win_len; + u32 peak_win_len; + u32 match_addr; + u32 match_cmd; + u32 match_data_l; + u32 match_data_h; + u32 rtrans_in_win; + u32 rbw_in_win; + u32 rlatency_in_win; + u32 wtrans_in_win; + u32 wbw_in_win; + u32 wlatency_in_win; + u32 peakbw_in_win; +}; + +struct bm_debug_info{ + u32 bm_index; + u32 msk_addr; + u32 msk_cmd; + u32 msk_data_l; + u32 msk_data_h; + u32 msk_id; +}; +static struct bm_debug_info debug_bm_int_info[BM_SIZE]; + +struct bm_continue_debug{ + bool bm_continue_dbg; + u32 loop_cnt; + u32 current_cnt; + struct bm_debug_info bm_ctn_info[BM_CONTINUE_DEBUG_SIZE]; +}; +static struct bm_continue_debug bm_ctn_dbg; + +//pls do not modify the head of the struct, if you want to add same para, pls add at the end of the struct. +struct bm_state_info{ + u32 bm_def_mode; + u32 axi_bm_cnt;//the count of axi bm + u32 ahb_bm_chn;//the count of ahb bm channels + //the star of the channels. + u32 cpu_chn; + u32 disp_chn; + u32 gpu_chn; + u32 ap_zip_chn; + u32 zip_chn; + u32 ap_chn; + u32 mm_chn; + u32 cp0_arm0_chn; + u32 cp0_arm1_chn; + u32 cp0_dsp_chn; + u32 cp0_arm0_1_chn; + u32 cp1_lte_chn; + u32 cp1_dsp_chn; + u32 cp1_arm_chn; + u32 cp2_chn; + + //ahb channels. + u32 ap_dap; + u32 ap_cpu; + u32 ap_dma_r; + u32 ap_dma_w; + u32 ap_sdio_0; + u32 ap_sdio_1; + u32 ap_sdio_2; + u32 ap_emmc; + u32 ap_nfc; + u32 ap_usb; + u32 ap_hsic; + u32 ap_otg; + u32 ap_nandc; + bool bm_dbg_st; + bool bm_dfs_off_st; + bool bm_panic_st; + bool bm_stack_st; +}; +static struct bm_state_info bm_st_info; + +struct bm_id_name { + unsigned char *chn_name; + unsigned long chn_type; /*1 for axi channel, 0 for ahb channel*/ +}; +static struct bm_id_name bm_chn_name[36]; +#define BM_AXI_TOTAL_CHN_NAME 15 +#define BM_AHB_TOTAL_CHN_NAME 13 +static struct bm_id_name bm_name_list[36] = { + {"CPU"}, + {"DISP"}, + {"GPU"}, + {"AP/ZIP"}, + {"ZIP"}, + {"AP"}, + {"MM"}, + {"CP0 ARM0"}, + {"CP0 ARM1"}, + {"CP0 DSP"}, + {"CP0 ARM0/1"}, + {"CP1 LTEACC/HARQ"}, + {"CP1 DSP"}, + {"CP1 CA5"}, + {"CP2"}, + + {"AP DAP"}, + {"AP CPU"}, + {"AP DMA READ"}, + {"AP DMA WRITE"}, + {"AP SDIO 0"}, + {"AP SDIO 1"}, + {"AP SDIO 2"}, + {"AP EMMC"}, + {"AP NFC"}, + {"AP USB"}, + {"AP HSIC"}, + {"AP OTG"}, + {"AP NANDC"}, + {""}, +}; + +struct bm_chn_def_val { + u32 str_addr; + u32 end_addr; + u32 min_data; + u32 max_data; + u32 bm_mask; + u32 mode; + u32 chn_sel; +}; +static struct bm_chn_def_val bm_store_vale[BM_SIZE]; +static struct bm_chn_def_val bm_def_value[BM_SIZE] = { + {0x00000000, 0x00000000, 0x0fffffff, 0x00000000, W_MODE, 0}, + {0x00000000, 0x00000000, 0x0fffffff, 0x00000000, W_MODE, 0}, + {0x00000000, 0x00000000, 0x0fffffff, 0x00000000, W_MODE, 0}, + {0x00000000, 0x00000000, 0x0fffffff, 0x00000000, W_MODE, 0}, + {0x00000000, 0x00000000, 0x0fffffff, 0x00000000, W_MODE, 0}, + {0x8D600000, 0x9F8AD000, 0x0fffffff, 0x00000000, W_MODE, 0}, + {0x8D600000, 0x9F8AD000, 0x0fffffff, 0x00000000, W_MODE, 0}, + {0x8D600000, 0x9F8AD000, 0x0fffffff, 0x00000000, W_MODE, 0}, + {0x8D600000, 0x9F8AD000, 0x0fffffff, 0x00000000, W_MODE, 0}, + {0x8D600000, 0x9F8AD000, 0x0fffffff, 0x00000000, W_MODE, 0}, + + {0x00000000, 0x00000000, 0x00000000, 0x00000000, W_MODE, 0}, + {0x00000000, 0x00000000, 0x00000000, 0x00000000, W_MODE, 0}, + {0x00000000, 0x00000000, 0x00000000, 0x00000000, W_MODE, 0}, +}; + +#endif diff --git a/include/soc/sprd/chip_x20/__clock_tree.h b/include/soc/sprd/chip_x20/__clock_tree.h new file mode 100644 index 00000000..23461560 --- /dev/null +++ b/include/soc/sprd/chip_x20/__clock_tree.h @@ -0,0 +1,548 @@ +/* + * Copyright (C) 2013 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +/* + * Clock (0)Name, Clock (1)fixed rate, Clock Enable (2)Ctrl and (3)Bit, + * Clock Divisor (4)Ctrl and (5)Bit, Clock Parent (6)Ctrl and (7)Bit, + * and Parent Select (15)Count and (16)Lists[ ... ...] + */ + +SCI_CLK_ADD(ext_26m, 26000000, REG_PMU_APB_CGM_AP_EN, BIT(0), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(ext_32k, 32768, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_mpll, 0, REG_PMU_APB_CGM_AP_EN, BIT(6), + REG_AON_APB_MPLL_CFG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_dpll, 0, REG_PMU_APB_CGM_AP_EN, BIT(1), + REG_AON_APB_DPLL_CFG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_td_sel_i, 0, REG_PMU_APB_TDPLL_REL_CFG, BIT(0), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_w_sel_i, 0, REG_PMU_APB_WPLL_REL_CFG, BIT(0), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_c_sel_i, 0, REG_PMU_APB_CPLL_REL_CFG, BIT(0), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_wifi_sel_i, 0, REG_PMU_APB_WIFIPLL1_REL_CFG, BIT(0), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_tdpll, 0, REG_PMU_APB_CGM_AP_EN, BIT(3), + REG_AON_APB_TDPLL_CFG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_wpll, 0, REG_PMU_APB_CGM_AP_EN, BIT(5), + REG_AON_APB_WPLL_CFG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, + 1, &clk_w_sel_i); + +SCI_CLK_ADD(clk_cpll, 0, REG_PMU_APB_CGM_AP_EN, BIT(2), + REG_AON_APB_CPLL_CFG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, + 1, &clk_c_sel_i); + +SCI_CLK_ADD(clk_wifipll, 0, REG_PMU_APB_CGM_AP_EN, BIT(4), + REG_AON_APB_WIFIPLL1_CFG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, + 1, &clk_wifi_sel_i); + +SCI_CLK_ADD(clk_460m8, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(20), + 2, 0, 0, 0, + 1, &clk_wpll); + +SCI_CLK_ADD(clk_300m, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(0), + 3, 0, 0, 0, + 1, &clk_mpll); + +SCI_CLK_ADD(clk_37m5, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(1), + 24, 0, 0, 0, + 1, &clk_mpll); + +SCI_CLK_ADD(clk_66m, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(2), + 16, 0, 0, 0, + 1, &clk_dpll); + +SCI_CLK_ADD(clk_51m2_w, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(23), + 18, 0, 0, 0, + 1, &clk_wpll); + +SCI_CLK_ADD(clk_40m, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(27), + 22, 0, 0, 0, + 1, &clk_wifipll); + +SCI_CLK_ADD(clk_312m, 0, REG_PMU_APB_CGM_AP_EN, BIT(7), + 2, 0, 0, 0, + 1, &clk_cpll); + +SCI_CLK_ADD(clk_208m, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(17), + 3, 0, 0, 0, + 1, &clk_cpll); + +SCI_CLK_ADD(clk_104m, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(18), + 6, 0, 0, 0, + 1, &clk_cpll); + +SCI_CLK_ADD(clk_52m, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(19), + 12, 0, 0, 0, + 1, &clk_cpll); + +SCI_CLK_ADD(clk_384m, 0, REG_PMU_APB_CGM_AP_EN, BIT(8), + 2, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_192m, 0, REG_PMU_APB_CGM_AP_EN, BIT(10), + 4, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_96m, 0, REG_PMU_APB_CGM_AP_EN, BIT(13), + 8, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_48m, 0, REG_PMU_APB_CGM_AP_EN, BIT(17), + 16, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_24m, 0, REG_PMU_APB_CGM_AP_EN, BIT(18), + 32, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_12m, 0, REG_PMU_APB_CGM_AP_EN, BIT(19), + 64, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_256m, 0, REG_PMU_APB_CGM_AP_EN, BIT(9), + 3, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_128m, 0, REG_PMU_APB_CGM_AP_EN, BIT(12), + 6, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_64m, 0, REG_PMU_APB_CGM_AP_EN, BIT(15), + 12, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_153m6, 0, REG_PMU_APB_CGM_AP_EN, BIT(11), + 5, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_51m2, 0, REG_PMU_APB_CGM_AP_EN, BIT(16), + 15, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_76m8, 0, REG_PMU_APB_CGM_AP_EN, BIT(14), + 10, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_38m4, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(15), + 20, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_mcu, 0, 0, 0, + REG_AP_AHB_CA7_CKG_CFG, BIT(4)|BIT(5)|BIT(6), REG_AP_AHB_CA7_CKG_CFG, BIT(0)|BIT(1)|BIT(2), + 7, &ext_26m, &clk_dpll, &clk_cpll, &clk_tdpll, &clk_wifipll, &clk_wpll, &clk_mpll); + +SCI_CLK_ADD(clk_arm, 0, 0, 0, + 0, 0, 0, 0, + 1, &clk_mcu); + +SCI_CLK_ADD(clk_axi, 0, 0, 0, + REG_AP_AHB_CA7_CKG_CFG, BIT(8)|BIT(9)|BIT(10), 0, 0, + 1, &clk_mcu); + +SCI_CLK_ADD(clk_dbg, 0, REG_AP_AHB_MISC_CKG_EN, BIT(8), + REG_AP_AHB_CA7_CKG_CFG, BIT(16)|BIT(17)|BIT(18), 0, 0, + 1, &clk_mcu); + +SCI_CLK_ADD(clk_ap_ahb, 0, 0, 0, + 0, 0, REG_AP_CLK_AP_AHB_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_76m8, &clk_128m, &clk_192m); + +SCI_CLK_ADD(clk_ap_apb, 0, 0, 0, + 0, 0, REG_AP_CLK_AP_APB_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_64m, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_pub_ahb, 0, 0, 0, + 0, 0, REG_AON_CLK_PUB_AHB_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_emc, 0, 0, 0, + REG_AON_CLK_EMC_CFG, BIT(8)|BIT(9), REG_AON_CLK_EMC_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_cpll, &clk_tdpll, &clk_dpll); + +SCI_CLK_ADD(clk_aon_apb, 0, 0, 0, + REG_AON_CLK_AON_APB_CFG, BIT(8)|BIT(9), REG_AON_CLK_AON_APB_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_76m8, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_disp_emc, 0, REG_AON_APB_APB_EB1, BIT(11), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_gsp_emc, 0, REG_AON_APB_APB_EB1, BIT(13), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_gsp, 0, REG_AP_AHB_AHB_EB, BIT(3), + 0, 0, REG_AP_CLK_GSP_CFG, BIT(0)|BIT(1), + 4, &clk_96m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_disc0, 0, REG_AP_AHB_AHB_EB, BIT(1), + REG_AP_CLK_DISPC0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_DISPC0_CFG, BIT(0)|BIT(1), + 4, &clk_153m6, &clk_192m, &clk_256m, &clk_312m); + +SCI_CLK_ADD(clk_disc0_dbi, 0, REG_AP_AHB_AHB_EB, BIT(1), + REG_AP_CLK_DISPC0_DBI_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_DISPC0_DBI_CFG, BIT(0)|BIT(1), + 4, &clk_128m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_disc0_dpi, 0, REG_AP_AHB_AHB_EB, BIT(1), + REG_AP_CLK_DISPC0_DPI_CFG, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), REG_AP_CLK_DISPC0_DPI_CFG, BIT(0)|BIT(1), + 4, &clk_128m, &clk_153m6, &clk_192m, &clk_384m); + +SCI_CLK_ADD(clk_disc1, 0, REG_AP_AHB_AHB_EB, BIT(2), + REG_AP_CLK_DISPC1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_DISPC1_CFG, BIT(0)|BIT(1), + 4, &clk_153m6, &clk_192m, &clk_256m, &clk_312m); + +SCI_CLK_ADD(clk_disc1_dbi, 0, REG_AP_AHB_AHB_EB, BIT(2), + REG_AP_CLK_DISPC1_DBI_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_DISPC1_DBI_CFG, BIT(0)|BIT(1), + 4, &clk_128m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_disc1_dpi, 0, REG_AP_AHB_AHB_EB, BIT(2), + REG_AP_CLK_DISPC1_DPI_CFG, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), REG_AP_CLK_DISPC1_DPI_CFG, BIT(0)|BIT(1), + 4, &clk_128m, &clk_153m6, &clk_192m, &clk_384m); + +/* +SCI_CLK_ADD(clk_zipdec_emc, 0, REG_AP_AHB_AHB_EB, BIT(21), + 0, 0, REG_AP_CLK_ZIPENC_CFG, BIT(0)|BIT(1), + 4, &clk_96m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_zipenc_emc, 0, REG_AP_AHB_AHB_EB, BIT(20), + 0, 0, REG_AP_CLK_ZIPENC_CFG, BIT(0)|BIT(1), + 4, &clk_96m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_nandc_ecc, 0, REG_AP_AHB_AHB_EB, BIT(19), + 0, 0, REG_AP_CLK_NANDC_ECC_CFG, BIT(0), + 2, &clk_153m6, &clk_192m); + +*/ +SCI_CLK_ADD(clk_nfc, 0, REG_AP_AHB_AHB_EB, BIT(6), + REG_AP_CLK_NFC_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_NFC_CFG, BIT(0)|BIT(1), + 3, &clk_64m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_sdio0, 0, REG_AP_AHB_AHB_EB, BIT(8), + REG_AP_CLK_SDIO0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_SDIO0_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_256m, &clk_312m, &clk_384m); + +SCI_CLK_ADD(clk_sdio1, 0, REG_AP_AHB_AHB_EB, BIT(9), + 0, 0, REG_AP_CLK_SDIO1_CFG, BIT(0)|BIT(1), + 4, &clk_48m, &clk_76m8, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_sdio2, 0, REG_AP_AHB_AHB_EB, BIT(10), + 0, 0, REG_AP_CLK_SDIO2_CFG, BIT(0)|BIT(1), + 4, &clk_48m, &clk_76m8, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_emmc, 0, REG_AP_AHB_AHB_EB, BIT(11), + 0, 0, REG_AP_CLK_EMMC_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_256m, &clk_312m, &clk_384m); + +SCI_CLK_ADD(clk_gps_tcxo, 64000000, REG_AP_CLK_GPS_TCXO_CFG, BIT(16), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_gps, 0, REG_AP_AHB_AHB_EB, BIT(12), + 0, 0, REG_AP_CLK_GPS_CFG, BIT(0), + 2, &clk_64m, &clk_76m8); + +SCI_CLK_ADD(clk_usb_ref, 0, REG_AP_AHB_AHB_EB, BIT(4), + 0, 0, REG_AP_CLK_USB_REF_CFG, BIT(0), + 2, &clk_12m, &clk_24m); + +SCI_CLK_ADD(clk_uart0, 0, REG_AP_APB_APB_EB, BIT(13), + REG_AP_CLK_UART0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_UART0_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart1, 0, REG_AP_APB_APB_EB, BIT(14), + REG_AP_CLK_UART1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_UART1_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart2, 0, REG_AP_APB_APB_EB, BIT(15), + REG_AP_CLK_UART2_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_UART2_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart3, 0, REG_AP_APB_APB_EB, BIT(16), + REG_AP_CLK_UART3_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_UART3_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart4, 0, REG_AP_APB_APB_EB, BIT(17), + REG_AP_CLK_UART4_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_UART4_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_i2c0, 0, REG_AP_APB_APB_EB, BIT(8), + REG_AP_CLK_I2C0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_I2C0_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_i2c1, 0, REG_AP_APB_APB_EB, BIT(9), + REG_AP_CLK_I2C1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_I2C1_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_i2c2, 0, REG_AP_APB_APB_EB, BIT(10), + REG_AP_CLK_I2C2_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_I2C2_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_i2c3, 0, REG_AP_APB_APB_EB, BIT(11), + REG_AP_CLK_I2C3_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_I2C3_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_i2c4, 0, REG_AP_APB_APB_EB, BIT(12), + REG_AP_CLK_I2C4_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_I2C4_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_spi0, 0, REG_AP_APB_APB_EB, BIT(5), + REG_AP_CLK_SPI0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_SPI0_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_spi1, 0, REG_AP_APB_APB_EB, BIT(6), + REG_AP_CLK_SPI1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_SPI1_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_spi2, 0, REG_AP_APB_APB_EB, BIT(7), + REG_AP_CLK_SPI2_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_SPI2_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_iis0, 0, REG_AP_APB_APB_EB, BIT(1), + REG_AP_CLK_IIS0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_IIS0_CFG, BIT(0)|BIT(1), + 3, &ext_26m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_iis1, 0, REG_AP_APB_APB_EB, BIT(2), + REG_AP_CLK_IIS1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_IIS1_CFG, BIT(0)|BIT(1), + 3, &ext_26m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_iis2, 0, REG_AP_APB_APB_EB, BIT(3), + REG_AP_CLK_IIS2_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_IIS2_CFG, BIT(0)|BIT(1), + 3, &ext_26m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_iis3, 0, REG_AP_APB_APB_EB, BIT(4), + REG_AP_CLK_IIS3_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_IIS3_CFG, BIT(0)|BIT(1), + 3, &ext_26m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_gpu_top_i, 0, REG_PMU_APB_PD_GPU_TOP_CFG+1, BIT(25), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_gpu_i, 0, REG_AON_APB_APB_EB0, BIT(27), + 0, 0, 0, 0, + 1, &clk_gpu_top_i); + +SCI_CLK_ADD(clk_gpu, 0, &clk_gpu_i, 0, + REG_GPU_APB_APB_CLK_CTRL, BIT(4)|BIT(5), REG_GPU_APB_APB_CLK_CTRL, BIT(0)|BIT(1)|BIT(2), + 7, &clk_153m6, &clk_208m, &clk_256m, &clk_300m, &clk_312m, &clk_384m, &clk_460m8); + +SCI_CLK_ADD(clk_mm_top_i, 0, REG_PMU_APB_PD_MM_TOP_CFG+1, BIT(25), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_mm_i, 0, REG_AON_APB_APB_EB0, BIT(25), + 0, 0, 0, 0, + 1, &clk_mm_top_i); + +SCI_CLK_ADD(clk_mm_ahb, 0, 0, 0, + 0, 0, REG_MM_CLK_MM_AHB_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_mm_mtx_axi, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(8), + 0, 0, 0, 0, + 1, &clk_mm_i); + +SCI_CLK_ADD(clk_mm_axi, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(7), + 0, 0, 0, 0, + 1, &clk_mm_mtx_axi); + +SCI_CLK_ADD(clk_mmu, 0, REG_MM_AHB_AHB_EB, BIT(7), + 0, 0, 0, 0, + 1, &clk_mm_ahb); +SCI_CLK_ADD(clk_mm_ckg_i, 0, REG_MM_AHB_AHB_EB, BIT(6), + 0, 0, 0, 0, + 1, &clk_mm_i); + +SCI_CLK_ADD(clk_jpg_i, 0, REG_MM_AHB_AHB_EB, BIT(5), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_jpg_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(6), + 0, 0, 0, 0, + 1, &clk_jpg_i); + +SCI_CLK_ADD(clk_jpg, 0, &clk_jpg_ckg_i, 0, + 0, 0, REG_MM_CLK_JPG_CFG, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_vsp_i, 0, REG_MM_AHB_AHB_EB, BIT(3), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_vsp_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(5), + 0, 0, 0, 0, + 1, &clk_vsp_i); + +SCI_CLK_ADD(clk_vsp, 0, &clk_vsp_ckg_i, 0, + 0, 0, REG_MM_CLK_VSP_CFG, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_isp_i, 0, REG_MM_AHB_AHB_EB, BIT(2), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_isp_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(4), + 0, 0, 0, 0, + 1, &clk_isp_i); + +SCI_CLK_ADD(clk_isp, 0, &clk_isp_ckg_i, 0, + 0, 0, REG_MM_CLK_ISP_CFG, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_256m, &clk_312m); + +SCI_CLK_ADD(clk_sensor_i, 0, REG_MM_AHB_AHB_EB, BIT(1), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_sensor_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(2), + 0, 0, 0, 0, + 1, &clk_sensor_i); + +SCI_CLK_ADD(clk_sensor, 0, &clk_sensor_ckg_i, 0, + REG_MM_CLK_SENSOR_CFG, BIT(8)|BIT(9)|BIT(10), REG_MM_CLK_SENSOR_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_76m8, &clk_96m); + +SCI_CLK_ADD(clk_ccir_in, 64000000, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_ccir_i, 0, REG_MM_AHB_AHB_EB, BIT(1), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_ccir, 0, &clk_ccir_i, 0, + 0, 0, REG_MM_CLK_CCIR_CFG, BIT(16), + 2, &clk_24m, &clk_ccir_in); + +SCI_CLK_ADD(clk_dcam_i, 0, REG_MM_AHB_AHB_EB, BIT(0), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_dcam_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(3), + 0, 0, 0, 0, + 1, &clk_dcam_i); + +SCI_CLK_ADD(clk_dcam, 0, &clk_dcam_ckg_i, 0, + 0, 0, REG_MM_CLK_DCAM_CFG, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_256m, &clk_312m); + +SCI_CLK_ADD(clk_csi_i, 0, REG_MM_AHB_AHB_EB, BIT(4), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_csi_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(1), + 0, 0, 0, 0, + 1, &clk_csi_i); + +SCI_CLK_ADD(clk_cphy_cfg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(0), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_dcam_mipi, 0, &clk_cphy_cfg_i, 0, + 0, 0, 0, 0, + 1, &clk_csi_ckg_i); + +SCI_CLK_ADD(clk_aud, 0, REG_AON_APB_APB_EB0, BIT(18), + 0, 0, 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_audif, 0, REG_AON_APB_APB_EB0, BIT(17), + 0, 0, REG_AON_CLK_AUDIF_CFG, BIT(0)|BIT(1), + 3, &ext_26m, &clk_38m4, &clk_51m2); + +SCI_CLK_ADD(clk_vbc, 0, REG_AON_APB_APB_EB0, BIT(19), + 0, 0, 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_fm_in, 64000000, REG_AON_CLK_FM_CFG, BIT(16), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_fm, 0, REG_AON_APB_APB_EB0, BIT(1), + 0, 0, 0, 0, + 1, &clk_fm_in); + +SCI_CLK_ADD(clk_adi, 0, REG_AON_APB_APB_EB0, BIT(16), + 0, 0, REG_AON_CLK_ADI_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_38m4, &clk_51m2, &clk_64m); + +SCI_CLK_ADD(clk_aux0, 0, REG_AON_APB_APB_EB1, BIT(2), + REG_AON_APB_AON_CGM_CFG, BIT(16)|BIT(17)|BIT(18)|BIT(19), REG_AON_APB_AON_CGM_CFG, BIT(0)|BIT(1)|BIT(2)|BIT(3), + 10, &ext_32k, &ext_26m, &ext_26m, &clk_48m, &clk_52m, &clk_51m2, &clk_37m5, &clk_40m, &clk_66m, &clk_40m); + +SCI_CLK_ADD(clk_aux1, 0, REG_AON_APB_APB_EB1, BIT(3), + REG_AON_APB_AON_CGM_CFG, BIT(20)|BIT(21)|BIT(22)|BIT(23), REG_AON_APB_AON_CGM_CFG, BIT(4)|BIT(5)|BIT(6)|BIT(7), + 10, &ext_32k, &ext_26m, &ext_26m, &clk_48m, &clk_52m, &clk_51m2, &clk_37m5, &clk_40m, &clk_66m, &clk_40m); + +SCI_CLK_ADD(clk_aux2, 0, REG_AON_APB_APB_EB1, BIT(4), + REG_AON_APB_AON_CGM_CFG, BIT(24)|BIT(25)|BIT(26)|BIT(27), REG_AON_APB_AON_CGM_CFG, BIT(8)|BIT(9)|BIT(10)|BIT(11), + 10, &ext_32k, &ext_26m, &ext_26m, &clk_48m, &clk_52m, &clk_51m2, &clk_37m5, &clk_40m, &clk_66m, &clk_40m); + +SCI_CLK_ADD(clk_pwm0, 0, REG_AON_APB_APB_EB0, BIT(4), + 0, 0, REG_AON_CLK_PWM0_CFG, BIT(0), + 2, &ext_32k, &ext_26m); + +SCI_CLK_ADD(clk_pwm1, 0, REG_AON_APB_APB_EB0, BIT(5), + 0, 0, REG_AON_CLK_PWM1_CFG, BIT(0), + 2, &ext_32k, &ext_26m); + +SCI_CLK_ADD(clk_pwm2, 0, REG_AON_APB_APB_EB0, BIT(6), + 0, 0, REG_AON_CLK_PWM2_CFG, BIT(0), + 2, &ext_32k, &ext_26m); + +SCI_CLK_ADD(clk_pwm3, 0, REG_AON_APB_APB_EB0, BIT(7), + 0, 0, REG_AON_CLK_PWM3_CFG, BIT(0), + 2, &ext_32k, &ext_26m); + +SCI_CLK_ADD(clk_efuse, 0, REG_AON_APB_APB_EB0, BIT(13), + 0, 0, 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_ca7_dap, 0, REG_AON_APB_APB_EB0, BIT(30), + 0, 0, REG_AON_CLK_CA7_DAP_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_76m8, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_ca7_ts, 0, REG_AON_APB_APB_EB0, BIT(28), + 0, 0, REG_AON_CLK_CA7_TS_CFG, BIT(0)|BIT(1), + 4, &ext_32k, &ext_26m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_mspi, 0, REG_AON_APB_APB_EB0, BIT(23), + 0, 0, REG_AON_CLK_MSPI_CFG, BIT(0)|BIT(1), + 3, &ext_26m, &clk_52m, &clk_76m8, &clk_96m); + +SCI_CLK_ADD(clk_i2c, 0, REG_AON_APB_APB_EB0, BIT(31), + 0, 0, REG_AON_CLK_I2C_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_avs0, 0, REG_AON_APB_APB_EB0, BIT(6), + 0, 0, REG_AON_CLK_AVS0_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_avs1, 0, REG_AON_APB_APB_EB0, BIT(7), + 0, 0, REG_AON_CLK_AVS1_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + diff --git a/include/soc/sprd/chip_x20/__regs_ada_apb_rf.h b/include/soc/sprd/chip_x20/__regs_ada_apb_rf.h new file mode 100644 index 00000000..0ca65ecf --- /dev/null +++ b/include/soc/sprd/chip_x20/__regs_ada_apb_rf.h @@ -0,0 +1,177 @@ +/*
+ * Copyright (C) 2014 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+#ifndef __SCI_GLB_REGS_H__
+#error "Don't include this file directly, Pls include sci_glb_regs.h"
+#endif
+
+
+#ifndef __H_REGS_ADA_APB_RF_HEADFILE_H__
+#define __H_REGS_ADA_APB_RF_HEADFILE_H__ __FILE__
+
+#define REGS_ADA_APB_RF
+
+/* registers definitions for ADA_APB_RF */
+#define REG_ADA_APB_RF_APB_DAC_CTR0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0000)
+#define REG_ADA_APB_RF_APB_DAC_CTR1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0004)
+#define REG_ADA_APB_RF_APB_DAC_CTR2 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0008)
+#define REG_ADA_APB_RF_APB_DAC_CTR3 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x000C)
+#define REG_ADA_APB_RF_APB_DAC_CTR4 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0010)
+#define REG_ADA_APB_RF_APB_DAC_STS0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0014)
+#define REG_ADA_APB_RF_APB_DAC_STS1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0018)
+#define REG_ADA_APB_RF_APB_ADC0_CTR0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x001C)
+#define REG_ADA_APB_RF_APB_ADC0_CTR1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0020)
+#define REG_ADA_APB_RF_APB_ADC0_CTR2 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0024)
+#define REG_ADA_APB_RF_APB_ADC0_CTR3 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0028)
+#define REG_ADA_APB_RF_APB_CAL_CTR0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0030)
+#define REG_ADA_APB_RF_APB_CAL_CTR1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0034)
+#define REG_ADA_APB_RF_APB_CAL_CTR3 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x003C)
+#define REG_ADA_APB_RF_APB_CAL_STS0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0044)
+#define REG_ADA_APB_RF_APB_CAL_STS1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0048)
+#define REG_ADA_APB_RF_APB_ADA_CTRL0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0054)
+#define REG_ADA_APB_RF_APB_ADA_CTRL1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0058)
+#define REG_ADA_APB_RF_APB_RX_GSM_DFT SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x005C)
+#define REG_ADA_APB_RF_APB_RX_3G_DFT SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0060)
+
+
+
+/* bits definitions for register REG_ADA_APB_RF_APB_DAC_CTR0 */
+#define BITS_DAC_PCTRL_1(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
+#define BIT_DAC_OUT_SEL_1 ( BIT(17) )
+#define BIT_DAC_CLK_SEL_1 ( BIT(16) )
+#define BITS_DAC_PCTRL_0(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) )
+#define BIT_DAC_OUT_SEL_0 ( BIT(1) )
+#define BIT_DAC_CLK_SEL_0 ( BIT(0) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_DAC_CTR1 */
+#define BITS_DAC_WD_OVR(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DAC_WADDR_OVR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_DAC_WLE_OVR ( BIT(2) )
+#define BIT_DAC_W_OVR_I_QN ( BIT(1) )
+#define BIT_DAC_W_OVR_EN ( BIT(0) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_DAC_CTR2 */
+#define BITS_DAC_RSV(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) )
+#define BIT_DAC_IQ_OUT_MSB_INV ( BIT(21) )
+#define BIT_DAC_IQ_IN_MSB_INV ( BIT(20) )
+#define BIT_DAC_OVR_EN_CAL ( BIT(19) )
+#define BIT_DAC_EN_OOSCAL ( BIT(18) )
+#define BIT_DAC_IQ_SWAP ( BIT(17) )
+#define BIT_DAC_CAL_START ( BIT(16) )
+#define BITS_DAC_OFFSETI(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DAC_OFFSETQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_DAC_CTR3 */
+#define BITS_DAC_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) )
+#define BITS_DAC_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_DAC_CTR4 */
+#define BITS_DAC_I_CAL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) )
+#define BITS_DAC_Q_CAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_DAC_STS0 */
+#define BITS_DAC_WTI(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DAC_WTQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_DAC_STS1 */
+#define BITS_DAC_DA_STATE(_X_) ( (_X_) << 17 & (BIT(17)|BIT(18)) )
+#define BIT_DAC_DONE ( BIT(16) )
+#define BITS_DAC_WQ_OVR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_ADC0_CTR0 */
+#define BITS_ADC0_CALRDOUT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
+#define BIT_ADC0_CAL_SOFT_RST ( BIT(10) )
+#define BIT_ADC0_CALRD ( BIT(9) )
+#define BIT_ADC0_CALEN ( BIT(8) )
+#define BITS_ADC0_CALADDR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_ADC0_CTR1 */
+#define BITS_ADC0_DLL_OUT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
+#define BITS_ADC0_DLLOOF(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)) )
+#define BIT_ADC0_IQ_SWAP ( BIT(14) )
+#define BITS_ADC0_DLLIN(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
+#define BIT_ADC0_IQ_OUT_MSB_INV ( BIT(7) )
+#define BIT_ADC0_IQ_IN_MSB_INV ( BIT(6) )
+#define BIT_ADC0_DLL_SOFT_RST ( BIT(4) )
+#define BIT_ADC0_DLLWR ( BIT(3) )
+#define BIT_ADC0_DLLRD ( BIT(2) )
+#define BIT_ADC0_DLLEN ( BIT(1) )
+#define BIT_ADC0_DEBUG_EN ( BIT(0) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_ADC0_CTR2 */
+#define BITS_ADC0_RSV_0(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_ADC0_DIG_CLK_SEL_0 ( BIT(11) )
+#define BIT_ADC0_VCM_SEL_0 ( BIT(10) )
+#define BITS_ADC0_DELAY_CAP_0(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ADC0_BIT_SEL_0(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) )
+#define BITS_ADC0_VREF_SEL_0(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_ADC0_VREF_BOOST_0(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_ADC0_QUANT_BOOST_0(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_ADC0_CTR3 */
+#define BITS_ADC0_RSV_1(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_ADC0_DIG_CLK_SEL_1 ( BIT(11) )
+#define BIT_ADC0_VCM_SEL_1 ( BIT(10) )
+#define BITS_ADC0_DELAY_CAP_1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ADC0_BIT_SEL_1(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) )
+#define BITS_ADC0_VREF_SEL_1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_ADC0_VREF_BOOST_1(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_ADC0_QUANT_BOOST_1(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_CAL_CTR0 */
+#define BIT_LDO_EN_AUTO_EN ( BIT(27) )
+#define BIT_LDO_EN_FRC ( BIT(26) )
+#define BIT_BG_EN_AUTO_EN ( BIT(25) )
+#define BIT_BG_EN_FRC ( BIT(24) )
+#define BITS_ADC_CLK_CAL_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_ADA_CAL_WAIT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BIT_CLK_ADA_CAL_EN ( BIT(6) )
+#define BIT_DAC_PD_CAL ( BIT(5) )
+#define BIT_ADC0_EN_CAL ( BIT(3) )
+#define BIT_ADC0_CAL ( BIT(1) )
+#define BIT_ADA_MODE_SEL ( BIT(0) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_CAL_CTR1 */
+#define BITS_ADC0_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) )
+#define BITS_ADC0_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_CAL_CTR3 */
+#define BIT_ADA0_CAL_START ( BIT(0) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_CAL_STS0 */
+#define BIT_ADA0_CAL_DONE ( BIT(31) )
+#define BITS_ADC0_I_CAL_RESULT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_CAL_STS1 */
+#define BITS_ADC0_Q_CAL_RESULT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_ADA_CTRL0 */
+#define BITS_ADA_AUTO_CTRL(_X_) (_X_)
+
+/* bits definitions for register REG_ADA_APB_RF_APB_ADA_CTRL1 */
+#define BITS_ADA_FRC_CTRL(_X_) (_X_)
+
+/* bits definitions for register REG_ADA_APB_RF_APB_RX_GSM_DFT */
+#define BITS_RX_GSM_DFT_Q(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) )
+#define BITS_RX_GSM_DFT_I(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_RX_3G_DFT */
+#define BITS_RX_3G_DFT_Q(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) )
+#define BITS_RX_3G_DFT_I(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
+
+#endif
diff --git a/include/soc/sprd/chip_x20/__regs_ahb_rf_cp2.h b/include/soc/sprd/chip_x20/__regs_ahb_rf_cp2.h new file mode 100644 index 00000000..d7cf335a --- /dev/null +++ b/include/soc/sprd/chip_x20/__regs_ahb_rf_cp2.h @@ -0,0 +1,160 @@ +/*
+ * Copyright (C) 2014 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+#ifndef __SCI_GLB_REGS_H__
+#error "Don't include this file directly, Pls include sci_glb_regs.h"
+#endif
+
+
+#ifndef __H_REGS_AHB_RF_CP2_HEADFILE_H__
+#define __H_REGS_AHB_RF_CP2_HEADFILE_H__ __FILE__
+
+#define REGS_AHB_RF_CP2
+
+/* registers definitions for AHB_RF_CP2 */
+#define REG_AHB_RF_CP2_AHB_RST0 SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x0000)
+#define REG_AHB_RF_CP2_AHB_EB0 SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x0004)
+#define REG_AHB_RF_CP2_ARCH_EB_REG SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x0084)
+#define REG_AHB_RF_CP2_AHB_BUS_CTL0 SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x00A0)
+#define REG_AHB_RF_CP2_AHB_BUS_CTL1 SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x00A4)
+#define REG_AHB_RF_CP2_AHB_BUS_CTL2 SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x00A8)
+#define REG_AHB_RF_CP2_AHB_SYS_CTL0 SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x00B0)
+#define REG_AHB_RF_CP2_AHB_SYS_CTL3 SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x00BC)
+#define REG_AHB_RF_CP2_AHB_SLP_CTL0 SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x00D0)
+#define REG_AHB_RF_CP2_AHB_SLP_CTL1 SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x00D4)
+#define REG_AHB_RF_CP2_AHB_SLP_CTL2 SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x00D8)
+#define REG_AHB_RF_CP2_AHB_SYS_CTL6 SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x00E0)
+#define REG_AHB_RF_CP2_AHB_SLP_STS0 SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x0100)
+#define REG_AHB_RF_CP2_AHB_MTX_CTL0 SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x0110)
+#define REG_AHB_RF_CP2_AHB_MTX_CTL1 SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x0114)
+#define REG_AHB_RF_CP2_AHB_MTX_CTL2 SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x0118)
+#define REG_AHB_RF_CP2_AHB_MTX_CTL3 SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x011C)
+#define REG_AHB_RF_CP2_AHB_MTX_CTL4 SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x0120)
+#define REG_AHB_RF_CP2_AHB_MTX_CTL5 SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x0124)
+#define REG_AHB_RF_CP2_AHB_MTX_CTL6 SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x0128)
+#define REG_AHB_RF_CP2_AHB_ARCH_PORT SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x0130)
+#define REG_AHB_RF_CP2_AHB_CHIP_ID SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x03FC)
+
+
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_RST0 */
+#define BIT_VPU_SOFT_RST ( BIT(3) )
+#define BIT_RFSBI_SOFT_RST ( BIT(2) )
+#define BIT_BUSM_SOFT_RST ( BIT(1) )
+#define BIT_DMA_SOFT_RST ( BIT(0) )
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_EB0 */
+#define BIT_WIFI_DBG_EB ( BIT(4) )
+#define BIT_BUSMON1_EB ( BIT(3) )
+#define BIT_BUSMON0_EB ( BIT(2) )
+#define BIT_RFSBI_EB ( BIT(1) )
+#define BIT_DMA_EB ( BIT(0) )
+
+/* bits definitions for register REG_AHB_RF_CP2_ARCH_EB_REG */
+#define BIT_ARCH_EB ( BIT(0) )
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_BUS_CTL0 */
+#define BIT_M5_PAUSE_HW0_EN ( BIT(5) )
+#define BIT_M4_PAUSE_HW0_EN ( BIT(4) )
+#define BIT_M3_PAUSE_HW0_EN ( BIT(3) )
+#define BIT_M2_PAUSE_HW0_EN ( BIT(2) )
+#define BIT_M1_PAUSE_HW0_EN ( BIT(1) )
+#define BIT_M0_PAUSE_HW0_EN ( BIT(0) )
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_BUS_CTL1 */
+#define BIT_M5_PAUSE_HW1_EN ( BIT(5) )
+#define BIT_M4_PAUSE_HW1_EN ( BIT(4) )
+#define BIT_M3_PAUSE_HW1_EN ( BIT(3) )
+#define BIT_M2_PAUSE_HW1_EN ( BIT(2) )
+#define BIT_M1_PAUSE_HW1_EN ( BIT(1) )
+#define BIT_M0_PAUSE_HW1_EN ( BIT(0) )
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_BUS_CTL2 */
+#define BIT_M5_PAUSE_SW ( BIT(5) )
+#define BIT_M4_PAUSE_SW ( BIT(4) )
+#define BIT_M3_PAUSE_SW ( BIT(3) )
+#define BIT_M2_PAUSE_SW ( BIT(2) )
+#define BIT_M1_PAUSE_SW ( BIT(1) )
+#define BIT_M0_PAUSE_SW ( BIT(0) )
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_SYS_CTL0 */
+#define BITS_WIFI_MON_OUT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)) )
+#define BITS_BUSMON1_CHN_SEL(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) )
+#define BITS_BUSMON0_CHN_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_WIFI_MON_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_SYS_CTL3 */
+#define BITS_DMA_REQ_HW_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) )
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_SLP_CTL0 */
+#define BIT_APB_STOP ( BIT(5) )
+#define BIT_MCU_CORE_SLP ( BIT(1) )
+#define BIT_MCU_FORCE_SYS_SLP ( BIT(0) )
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_SLP_CTL1 */
+#define BIT_MCU_LIGHT_SLEEP_EN ( BIT(8) )
+#define BIT_DMA_ACT_LIGHT_EN ( BIT(7) )
+#define BIT_DMA_SLP_MODE ( BIT(6) )
+#define BIT_MCU_DEEP_SLP_EN ( BIT(4) )
+#define BIT_MCU_SYS_SLP_EN ( BIT(3) )
+#define BIT_MCU_DMA_WAKE_UP_EN ( BIT(2) )
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_SLP_CTL2 */
+#define BITS_DMA_REQ_WAKE_EN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) )
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_SYS_CTL6 */
+#define BIT_PTEST ( BIT(0) )
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_SLP_STS0 */
+#define BIT_MTX_M5_STOP ( BIT(5) )
+#define BIT_MTX_M4_STOP ( BIT(4) )
+#define BIT_MTX_M3_STOP ( BIT(3) )
+#define BIT_MTX_M2_STOP ( BIT(2) )
+#define BIT_MTX_M1_STOP ( BIT(1) )
+#define BIT_MTX_M0_STOP ( BIT(0) )
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_MTX_CTL0 */
+#define BITS_MATRIX_CTRL0(_X_) (_X_)
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_MTX_CTL1 */
+#define BITS_MATRIX_CTRL1(_X_) (_X_)
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_MTX_CTL2 */
+#define BITS_MATRIX_CTRL2(_X_) (_X_)
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_MTX_CTL3 */
+#define BITS_MATRIX_CTRL3(_X_) (_X_)
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_MTX_CTL4 */
+#define BITS_MATRIX_CTRL4(_X_) (_X_)
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_MTX_CTL5 */
+#define BITS_MATRIX_CTRL5(_X_) (_X_)
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_MTX_CTL6 */
+#define BITS_MATRIX_CTRL6(_X_) (_X_)
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_ARCH_PORT */
+#define BIT_MCU_PROT ( BIT(16) )
+#define BITS_ARCH_PROT_VAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_CHIP_ID */
+#define BITS_ID_BASE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_MX_REG(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+#endif
diff --git a/include/soc/sprd/chip_x20/__regs_ana_apb_if.h b/include/soc/sprd/chip_x20/__regs_ana_apb_if.h new file mode 100644 index 00000000..aac3136d --- /dev/null +++ b/include/soc/sprd/chip_x20/__regs_ana_apb_if.h @@ -0,0 +1,932 @@ +/*
+ * Copyright (C) 2014 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+#ifndef __SCI_GLB_REGS_H__
+#error "Don't include this file directly, Pls include sci_glb_regs.h"
+#endif
+
+
+#ifndef __H_REGS_ANA_APB_IF_HEADFILE_H__
+#define __H_REGS_ANA_APB_IF_HEADFILE_H__ __FILE__
+
+#define REGS_ANA_APB_IF
+
+/* registers definitions for ANA_APB_IF */
+#define REG_ANA_APB_IF_ARM_MODULE_EN SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0000)
+#define REG_ANA_APB_IF_ARM_CLK_EN SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0004)
+#define REG_ANA_APB_IF_RTC_CLK_EN SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0008)
+#define REG_ANA_APB_IF_ARM_RST SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x000C)
+#define REG_ANA_APB_IF_LDO_DCDC_PD_RTCSET SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0010)
+#define REG_ANA_APB_IF_LDO_DCDC_PD_RTCCLR SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0014)
+#define REG_ANA_APB_IF_RTC_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0018)
+#define REG_ANA_APB_IF_LDO_PD_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x001C)
+#define REG_ANA_APB_IF_LDO_V_CTRL0 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0020)
+#define REG_ANA_APB_IF_LDO_V_CTRL1 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0024)
+#define REG_ANA_APB_IF_LDO_V_CTRL2 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0028)
+#define REG_ANA_APB_IF_LDO_CAL_CTRL0 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x002C)
+#define REG_ANA_APB_IF_LDO_CAL_CTRL1 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0030)
+#define REG_ANA_APB_IF_LDO_CAL_CTRL2 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0034)
+#define REG_ANA_APB_IF_LDO_CAL_CTRL3 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0038)
+#define REG_ANA_APB_IF_LDO_CAL_CTRL4 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x003C)
+#define REG_ANA_APB_IF_LDO_CAL_CTRL5 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0040)
+#define REG_ANA_APB_IF_LDO_CAL_CTRL6 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0044)
+#define REG_ANA_APB_IF_AUXAD_CTL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0048)
+#define REG_ANA_APB_IF_DCDC_CTRL0 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x004C)
+#define REG_ANA_APB_IF_DCDC_CTRL1 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0050)
+#define REG_ANA_APB_IF_DCDC_CTRL2 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0054)
+#define REG_ANA_APB_IF_DCDC_CTRL3 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0058)
+#define REG_ANA_APB_IF_DCDC_CTRL4 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x005C)
+#define REG_ANA_APB_IF_DCDC_CTRL5 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0060)
+#define REG_ANA_APB_IF_DCDC_CTRL6 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0064)
+#define REG_ANA_APB_IF_DDR2_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0068)
+#define REG_ANA_APB_IF_SLP_WAIT_DCDCARM SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x006C)
+#define REG_ANA_APB_IF_LDO1828_XTL_CTL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0070)
+#define REG_ANA_APB_IF_LDO_SLP_CTRL0 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0074)
+#define REG_ANA_APB_IF_LDO_SLP_CTRL1 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0078)
+#define REG_ANA_APB_IF_LDO_SLP_CTRL2 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x007C)
+#define REG_ANA_APB_IF_LDO_SLP_CTRL3 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0080)
+#define REG_ANA_APB_IF_AUD_SLP_CTRL4 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0084)
+#define REG_ANA_APB_IF_DCDC_SLP_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0088)
+#define REG_ANA_APB_IF_XTL_WAIT_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x008C)
+#define REG_ANA_APB_IF_FLASH_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0090)
+#define REG_ANA_APB_IF_WHTLED_CTRL0 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0094)
+#define REG_ANA_APB_IF_WHTLED_CTRL1 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0098)
+#define REG_ANA_APB_IF_WHTLED_CTRL2 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x009C)
+#define REG_ANA_APB_IF_ANA_DRV_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00A0)
+#define REG_ANA_APB_IF_VIBR_CTRL0 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00A4)
+#define REG_ANA_APB_IF_VIBR_CTRL1 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00A8)
+#define REG_ANA_APB_IF_VIBR_CTRL2 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00AC)
+#define REG_ANA_APB_IF_VIBR_WR_PROT_VALUE SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00B0)
+#define REG_ANA_APB_IF_AUDIO_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00B4)
+#define REG_ANA_APB_IF_CHGR_CTRL0 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00B8)
+#define REG_ANA_APB_IF_CHGR_CTRL1 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00BC)
+#define REG_ANA_APB_IF_CHGR_CTRL2 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00C0)
+#define REG_ANA_APB_IF_CHGR_STATUS SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00C4)
+#define REG_ANA_APB_IF_ANA_MIXED_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00C8)
+#define REG_ANA_APB_IF_PWR_XTL_EN0 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00CC)
+#define REG_ANA_APB_IF_PWR_XTL_EN1 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00D0)
+#define REG_ANA_APB_IF_PWR_XTL_EN2 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00D4)
+#define REG_ANA_APB_IF_PWR_XTL_EN3 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00D8)
+#define REG_ANA_APB_IF_PWR_XTL_EN4 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00DC)
+#define REG_ANA_APB_IF_PWR_XTL_EN5 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00E0)
+#define REG_ANA_APB_IF_ANA_STATUS SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00E4)
+#define REG_ANA_APB_IF_POR_RST_MONITOR SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00E8)
+#define REG_ANA_APB_IF_WDG_RST_MONITOR SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00EC)
+#define REG_ANA_APB_IF_POR_PIN_RST_MONITOR SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00F0)
+#define REG_ANA_APB_IF_POR_SRC_FLAG SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00F4)
+#define REG_ANA_APB_IF_POR_7S_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00F8)
+#define REG_ANA_APB_IF_INT_DEBUG SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00FC)
+#define REG_ANA_APB_IF_GPI_DEBUG SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0100)
+#define REG_ANA_APB_IF_HWRST_RTC SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0104)
+#define REG_ANA_APB_IF_CHIP_ID_LOW SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0108)
+#define REG_ANA_APB_IF_CHIP_ID_HIGH SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x010C)
+#define REG_ANA_APB_IF_ARM_MF_REG SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0110)
+#define REG_ANA_APB_IF_AFUSE_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0114)
+#define REG_ANA_APB_IF_AFUSE_OUT0 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0118)
+#define REG_ANA_APB_IF_AFUSE_OUT1 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x011C)
+#define REG_ANA_APB_IF_AFUSE_OUT2 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0120)
+#define REG_ANA_APB_IF_AFUSE_OUT3 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0124)
+#define REG_ANA_APB_IF_CA_CTRL4 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0128)
+#define REG_ANA_APB_IF_MCU_WR_PROT_VALUE SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x012C)
+#define REG_ANA_APB_IF_MP_PWR_CTRL0 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0130 )
+#define REG_ANA_APB_IF_MP_PWR_CTRL1 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0134)
+#define REG_ANA_APB_IF_MP_PWR_CTRL2 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0138)
+#define REG_ANA_APB_IF_MP_PWR_CTRL3 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x013C)
+#define REG_ANA_APB_IF_MP_LDO_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0140)
+#define REG_ANA_APB_IF_MP_CHG_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0144)
+#define REG_ANA_APB_IF_MP_MISC_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0148)
+#define REG_ANA_APB_IF_MP_DCDC_DEDT_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x014C)
+#define REG_ANA_APB_IF_CA_CTRL0 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0150)
+#define REG_ANA_APB_IF_CA_CTRL1 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0154)
+#define REG_ANA_APB_IF_CA_CTRL2 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0158)
+#define REG_ANA_APB_IF_CA_CTRL3 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x015C)
+#define REG_ANA_APB_IF_DCDC_CORE_ADI SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0160)
+#define REG_ANA_APB_IF_DCDC_ARM_ADI SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0164)
+#define REG_ANA_APB_IF_DCDC_MEM_ADI SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0168)
+#define REG_ANA_APB_IF_DCDC_GEN_ADI SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x016C)
+#define REG_ANA_APB_IF_DCDC_WRF_ADI SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0170)
+#define REG_ANA_APB_IF_DCDC_WPA_ADI SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0174)
+#define REG_ANA_APB_IF_DCDC_WPA_DCM_ADI SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x017C)
+
+
+
+/* bits definitions for register REG_ANA_APB_IF_ARM_MODULE_EN */
+#define BIT_ANA_THM_EN ( BIT(12) )
+#define BIT_ANA_BLTC_EN ( BIT(10) )
+#define BIT_ANA_PINREG_EN ( BIT(9) )
+#define BIT_ANA_FGU_EN ( BIT(8) )
+#define BIT_ANA_GPIO_EN ( BIT(7) )
+#define BIT_ANA_ADC_EN ( BIT(6) )
+#define BIT_ANA_HDT_EN ( BIT(5) )
+#define BIT_ANA_AUD_EN ( BIT(4) )
+#define BIT_ANA_EIC_EN ( BIT(3) )
+#define BIT_ANA_WDG_EN ( BIT(2) )
+#define BIT_ANA_RTC_EN ( BIT(1) )
+
+/* bits definitions for register REG_ANA_APB_IF_ARM_CLK_EN */
+#define BIT_ANA_CLK_AUXAD_EN ( BIT(9) )
+#define BIT_ANA_CLK_AUXADC_EN ( BIT(8) )
+#define BIT_ANA_CLK_AUD_HID_EN ( BIT(5) )
+#define BIT_ANA_CLK_AUD_HBD_EN ( BIT(4) )
+#define BIT_ANA_CLK_AUD_LOOP_EN ( BIT(3) )
+#define BIT_ANA_CLK_AUD_6P5M_EN ( BIT(2) )
+#define BIT_ANA_CLK_AUDIF_EN ( BIT(1) )
+
+/* bits definitions for register REG_ANA_APB_IF_RTC_CLK_EN */
+#define BIT_ANA_RTC_FLASH_EN ( BIT(13) )
+#define BIT_ANA_RTC_THMA_AUTO_EN ( BIT(12) )
+#define BIT_ANA_RTC_THMA_EN ( BIT(11) )
+#define BIT_ANA_RTC_THM_EN ( BIT(10) )
+#define BIT_ANA_RTC_BLTC_EN ( BIT(8) )
+#define BIT_ANA_RTC_FGU_EN ( BIT(7) )
+#define BIT_ANA_RTC_FGUA_EN ( BIT(6) )
+#define BIT_ANA_RTC_VIBR_EN ( BIT(5) )
+#define BIT_ANA_RTC_AUD_EN ( BIT(4) )
+#define BIT_ANA_RTC_EIC_EN ( BIT(3) )
+#define BIT_ANA_RTC_WDG_EN ( BIT(2) )
+#define BIT_ANA_RTC_RTC_EN ( BIT(1) )
+#define BIT_ANA_RTC_ARCH_EN ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_ARM_RST */
+#define BIT_ANA_THMA_SOFT_RST ( BIT(14) )
+#define BIT_ANA_THM_SOFT_RST ( BIT(13) )
+#define BIT_ANA_AUD_32K_SOFT_RST ( BIT(12) )
+#define BIT_ANA_AUDTX_SOFT_RST ( BIT(11) )
+#define BIT_ANA_AUDRX_SOFT_RST ( BIT(10) )
+#define BIT_ANA_AUD_SOFT_RST ( BIT(9) )
+#define BIT_ANA_AUD_HDT_SOFT_RST ( BIT(8) )
+#define BIT_ANA_GPIO_SOFT_RST ( BIT(7) )
+#define BIT_ANA_ADC_SOFT_RST ( BIT(6) )
+#define BIT_ANA_PWM0_SOFT_RST ( BIT(5) )
+#define BIT_ANA_FGU_SOFT_RST ( BIT(4) )
+#define BIT_ANA_EIC_SOFT_RST ( BIT(3) )
+#define BIT_ANA_WDG_SOFT_RST ( BIT(2) )
+#define BIT_ANA_RTC_SOFT_RST ( BIT(1) )
+#define BIT_ANA_BLTC_SOFT_RST ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_DCDC_PD_RTCSET */
+#define BIT_ANA_LDO_AVDD18_PD_RTCSET ( BIT(15) )
+#define BIT_ANA_DCDC_OTP_PD_RTCSET ( BIT(14) )
+#define BIT_ANA_DCDC_WRF_PD_RTCSET ( BIT(13) )
+#define BIT_ANA_DCDC_GEN_PD_RTCSET ( BIT(12) )
+#define BIT_ANA_DCDC_MEM_PD_RTCSET ( BIT(11) )
+#define BIT_ANA_DCDC_ARM_PD_RTCSET ( BIT(10) )
+#define BIT_ANA_DCDC_CORE_PD_RTCSET ( BIT(9) )
+#define BIT_ANA_LDO_EMMCCORE_PD_RTCSET ( BIT(8) )
+#define BIT_ANA_LDO_EMMCIO_PD_RTCSET ( BIT(7) )
+#define BIT_ANA_LDO_RF2_PD_RTCSET ( BIT(6) )
+#define BIT_ANA_LDO_RF1_PD_RTCSET ( BIT(5) )
+#define BIT_ANA_LDO_RF0_PD_RTCSET ( BIT(4) )
+#define BIT_ANA_LDO_VDD25_PD_RTCSET ( BIT(3) )
+#define BIT_ANA_LDO_VDD28_PD_RTCSET ( BIT(2) )
+#define BIT_ANA_LDO_VDD18_PD_RTCSET ( BIT(1) )
+#define BIT_ANA_BG_PD_RTCSET ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_DCDC_PD_RTCCLR */
+#define BIT_ANA_LDO_AVDD18_PD_RTCCLR ( BIT(15) )
+#define BIT_ANA_DCDC_OTP_PD_RTCCLR ( BIT(14) )
+#define BIT_ANA_DCDC_WRF_PD_RTCCLR ( BIT(13) )
+#define BIT_ANA_DCDC_GEN_PD_RTCCLR ( BIT(12) )
+#define BIT_ANA_DCDC_MEM_PD_RTCCLR ( BIT(11) )
+#define BIT_ANA_DCDC_ARM_PD_RTCCLR ( BIT(10) )
+#define BIT_ANA_DCDC_CORE_PD_RTCCLR ( BIT(9) )
+#define BIT_ANA_LDO_EMMCCORE_PD_RTCCLR ( BIT(8) )
+#define BIT_ANA_LDO_EMMCIO_PD_RTCCLR ( BIT(7) )
+#define BIT_ANA_LDO_RF2_PD_RTCCLR ( BIT(6) )
+#define BIT_ANA_LDO_RF1_PD_RTCCLR ( BIT(5) )
+#define BIT_ANA_LDO_RF0_PD_RTCCLR ( BIT(4) )
+#define BIT_ANA_LDO_VDD25_PD_RTCCLR ( BIT(3) )
+#define BIT_ANA_LDO_VDD28_PD_RTCCLR ( BIT(2) )
+#define BIT_ANA_LDO_VDD18_PD_RTCCLR ( BIT(1) )
+#define BIT_ANA_BG_PD_RTCCLR ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_RTC_CTRL */
+#define BITS_ANA_XOSC32K_CTL_STS(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BIT_ANA_XOSC32K_CTL_B3_RTCCLR ( BIT(7) )
+#define BIT_ANA_XOSC32K_CTL_B2_RTCCLR ( BIT(6) )
+#define BIT_ANA_XOSC32K_CTL_B1_RTCCLR ( BIT(5) )
+#define BIT_ANA_XOSC32K_CTL_B0_RTCCLR ( BIT(4) )
+#define BIT_ANA_XOSC32K_CTL_B3_RTCSET ( BIT(3) )
+#define BIT_ANA_XOSC32K_CTL_B2_RTCSET ( BIT(2) )
+#define BIT_ANA_XOSC32K_CTL_B1_RTCSET ( BIT(1) )
+#define BIT_ANA_XOSC32K_CTL_B0_RTCSET ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_PD_CTRL */
+#define BIT_ANA_LDO_LPREF_PD_SW ( BIT(12) )
+#define BIT_ANA_DCDC_WPA_PD ( BIT(11) )
+#define BIT_ANA_LDO_CLSG_PD ( BIT(10) )
+#define BIT_ANA_LDO_USB_PD ( BIT(9) )
+#define BIT_ANA_LDO_CAMMOT_PD ( BIT(8) )
+#define BIT_ANA_LDO_CAMIO_PD ( BIT(7) )
+#define BIT_ANA_LDO_CAMD_PD ( BIT(6) )
+#define BIT_ANA_LDO_CAMA_PD ( BIT(5) )
+#define BIT_ANA_LDO_SIM2_PD ( BIT(4) )
+#define BIT_ANA_LDO_SIM1_PD ( BIT(3) )
+#define BIT_ANA_LDO_SIM0_PD ( BIT(2) )
+#define BIT_ANA_LDO_SD_PD ( BIT(1) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_V_CTRL0 */
+#define BITS_ANA_LDO_EMMCCORE_V(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) )
+#define BITS_ANA_LDO_EMMCIO_V(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) )
+#define BITS_ANA_LDO_RF2_V(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
+#define BITS_ANA_LDO_RF1_V(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ANA_LDO_RF0_V(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) )
+#define BITS_ANA_LDO_VDD25_V(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_ANA_LDO_VDD28_V(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_ANA_LDO_VDD18_V(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_V_CTRL1 */
+#define BITS_ANA_LDO_SIM2_V(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ANA_LDO_SIM1_V(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) )
+#define BITS_ANA_LDO_SIM0_V(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_ANA_LDO_SD_V(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_ANA_LDO_AVDD18_V(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_V_CTRL2 */
+#define BITS_ANA_VBATBK_RES(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) )
+#define BITS_ANA_VBATBK_V(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) )
+#define BITS_ANA_LDO_CLSG_V(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
+#define BITS_ANA_LDO_USB_V(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ANA_LDO_CAMMOT_V(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) )
+#define BITS_ANA_LDO_CAMIO_V(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_ANA_LDO_CAMD_V(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_ANA_LDO_CAMA_V(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_CAL_CTRL0 */
+#define BITS_ANA_LDO_VDD25_CAL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_ANA_LDO_VDD28_CAL(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_ANA_LDO_VDD18_CAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_CAL_CTRL1 */
+#define BITS_ANA_LDO_RF2_CAL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_ANA_LDO_RF1_CAL(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_ANA_LDO_RF0_CAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_CAL_CTRL2 */
+#define BITS_ANA_LDO_USB_CAL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_ANA_LDO_EMMCCORE_CAL(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_ANA_LDO_EMMCIO_CAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_CAL_CTRL3 */
+#define BITS_ANA_LDO_SD_CAL(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_ANA_LDO_AVDD18_CAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_CAL_CTRL4 */
+#define BITS_ANA_LDO_CAMA_CAL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_ANA_LDO_SIM2_CAL(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_ANA_LDO_SIM_CAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_CAL_CTRL5 */
+#define BITS_ANA_LDO_CAMMOT_CAL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_ANA_LDO_CAMIO_CAL(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_ANA_LDO_CAMD_CAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_CAL_CTRL6 */
+#define BITS_ANA_LDOA_CAL_SEL(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)) )
+#define BITS_ANA_LDOD_CAL_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) )
+#define BITS_ANA_LDODCDC_CAL_SEL(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_ANA_LDO_CLSG_CAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_AUXAD_CTL */
+#define BIT_ANA_AUXAD_CURRENTSEN_EN ( BIT(6) )
+#define BIT_ANA_AUXAD_CURRENTSEL ( BIT(5) )
+#define BITS_ANA_AUXAD_CURRENT_IBS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_CTRL0 */
+#define BIT_ANA_DCDC_CORE_LP_EN ( BIT(15) )
+#define BIT_ANA_DCDC_CORE_CL_CTRL ( BIT(14) )
+#define BITS_ANA_DCDC_CORE_PDRSLOW(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
+#define BIT_ANA_DCDC_CORE_PFM ( BIT(9) )
+#define BIT_ANA_DCDC_CORE_DCM ( BIT(8) )
+#define BIT_ANA_DCDC_ARM_LP_EN ( BIT(7) )
+#define BIT_ANA_DCDC_ARM_CL_CTRL ( BIT(6) )
+#define BITS_ANA_DCDC_ARM_PDRSLOW(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+#define BIT_ANA_DCDC_ARM_PFM ( BIT(1) )
+#define BIT_ANA_DCDC_ARM_DCM ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_CTRL1 */
+#define BIT_ANA_DCDC_MEM_LP_EN ( BIT(15) )
+#define BIT_ANA_DCDC_MEM_CL_CTRL ( BIT(14) )
+#define BITS_ANA_DCDC_MEM_PDRSLOW(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
+#define BIT_ANA_DCDC_MEM_PFM ( BIT(9) )
+#define BIT_ANA_DCDC_MEM_DCM ( BIT(8) )
+#define BIT_ANA_DCDC_GEN_LP_EN ( BIT(7) )
+#define BIT_ANA_DCDC_GEN_CL_CTRL ( BIT(6) )
+#define BITS_ANA_DCDC_GEN_PDRSLOW(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+#define BIT_ANA_DCDC_GEN_PFM ( BIT(1) )
+#define BIT_ANA_DCDC_GEN_DCM ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_CTRL2 */
+#define BIT_ANA_DCDC_BG_LP_EN ( BIT(15) )
+#define BIT_ANA_DCDC_OTP_CHIP_PD_FLAG_CLR ( BIT(14) )
+#define BIT_ANA_DCDC_OTP_CHIP_PD_FLAG ( BIT(13) )
+#define BIT_ANA_DCDC_OTP_AUTO_PD_EN ( BIT(12) )
+#define BIT_ANA_DCDC_OTP_VBEOP ( BIT(11) )
+#define BITS_ANA_DCDC_OTP_S(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) )
+#define BIT_ANA_DCDC_WRF_LP_EN ( BIT(7) )
+#define BIT_ANA_DCDC_WRF_CL_CTRL ( BIT(6) )
+#define BITS_ANA_DCDC_WRF_PDRSLOW(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+#define BIT_ANA_DCDC_WRF_PFM ( BIT(1) )
+#define BIT_ANA_DCDC_WRF_DCM ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_CTRL3 */
+#define BIT_ANA_DCDC_WPA_LP_EN ( BIT(8) )
+#define BIT_ANA_DCDC_WPA_CL_CTRL ( BIT(7) )
+#define BIT_ANA_DCDC_WPA_ZXOP ( BIT(6) )
+#define BITS_ANA_DCDC_WPA_PDRSLOW(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+#define BIT_ANA_DCDC_WPA_PFM ( BIT(1) )
+#define BIT_ANA_DCDC_WPA_APTEN ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_CTRL4 */
+#define BIT_ANA_DCDC_CORE_OSCSYCEN_SW ( BIT(15) )
+#define BIT_ANA_DCDC_CORE_OSCSYCEN_HW_EN ( BIT(14) )
+#define BIT_ANA_DCDC_CORE_OSCSYC_DIV_EN ( BIT(13) )
+#define BITS_ANA_DCDC_CORE_OSCSYC_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
+#define BIT_ANA_DCDC_ARM_OSCSYCEN_SW ( BIT(7) )
+#define BIT_ANA_DCDC_ARM_OSCSYCEN_HW_EN ( BIT(6) )
+#define BIT_ANA_DCDC_ARM_OSCSYC_DIV_EN ( BIT(5) )
+#define BITS_ANA_DCDC_ARM_OSCSYC_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_CTRL5 */
+#define BIT_ANA_DCDC_MEM_OSCSYCEN_SW ( BIT(15) )
+#define BIT_ANA_DCDC_MEM_OSCSYCEN_HW_EN ( BIT(14) )
+#define BIT_ANA_DCDC_MEM_OSCSYC_DIV_EN ( BIT(13) )
+#define BITS_ANA_DCDC_MEM_OSCSYC_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
+#define BIT_ANA_DCDC_GEN_OSCSYCEN_SW ( BIT(7) )
+#define BIT_ANA_DCDC_GEN_OSCSYCEN_HW_EN ( BIT(6) )
+#define BIT_ANA_DCDC_GEN_OSCSYC_DIV_EN ( BIT(5) )
+#define BITS_ANA_DCDC_GEN_OSCSYC_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_CTRL6 */
+#define BIT_ANA_DCDC_WPA_OSCSYCEN_SW ( BIT(15) )
+#define BIT_ANA_DCDC_WPA_OSCSYCEN_HW_EN ( BIT(14) )
+#define BIT_ANA_DCDC_WPA_OSCSYC_DIV_EN ( BIT(13) )
+#define BITS_ANA_DCDC_WPA_OSCSYC_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
+#define BIT_ANA_DCDC_WRF_OSCSYCEN_SW ( BIT(7) )
+#define BIT_ANA_DCDC_WRF_OSCSYCEN_HW_EN ( BIT(6) )
+#define BIT_ANA_DCDC_WRF_OSCSYC_DIV_EN ( BIT(5) )
+#define BITS_ANA_DCDC_WRF_OSCSYC_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_DDR2_CTRL */
+#define BIT_ANA_DDR2_BUF_PD_HW ( BIT(9) )
+#define BITS_ANA_DDR2_BUF_S_DS(_X_) ( (_X_) << 7 & (BIT(7)|BIT(8)) )
+#define BITS_ANA_DDR2_BUF_CHNS_DS(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)) )
+#define BIT_ANA_DDR2_BUF_PD ( BIT(4) )
+#define BITS_ANA_DDR2_BUF_S(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_ANA_DDR2_BUF_CHNS(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_ANA_APB_IF_SLP_WAIT_DCDCARM */
+#define BITS_ANA_SLP_IN_WAIT_DCDCARM(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_ANA_SLP_OUT_WAIT_DCDCARM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO1828_XTL_CTL */
+#define BIT_ANA_LDO_VDD18_EXT_XTL2_EN ( BIT(11) )
+#define BIT_ANA_LDO_VDD18_EXT_XTL1_EN ( BIT(10) )
+#define BIT_ANA_LDO_VDD18_EXT_XTL0_EN ( BIT(9) )
+#define BIT_ANA_LDO_VDD18_XTL2_EN ( BIT(8) )
+#define BIT_ANA_LDO_VDD18_XTL1_EN ( BIT(7) )
+#define BIT_ANA_LDO_VDD18_XTL0_EN ( BIT(6) )
+#define BIT_ANA_LDO_VDD28_EXT_XTL2_EN ( BIT(5) )
+#define BIT_ANA_LDO_VDD28_EXT_XTL1_EN ( BIT(4) )
+#define BIT_ANA_LDO_VDD28_EXT_XTL0_EN ( BIT(3) )
+#define BIT_ANA_LDO_VDD28_XTL2_EN ( BIT(2) )
+#define BIT_ANA_LDO_VDD28_XTL1_EN ( BIT(1) )
+#define BIT_ANA_LDO_VDD28_XTL0_EN ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_SLP_CTRL0 */
+#define BIT_ANA_SLP_IO_EN ( BIT(15) )
+#define BIT_ANA_SLP_DCDC_OTP_PD_EN ( BIT(13) )
+#define BIT_ANA_SLP_DCDCGEN_PD_EN ( BIT(12) )
+#define BIT_ANA_SLP_DCDCWPA_PD_EN ( BIT(11) )
+#define BIT_ANA_SLP_DCDCWRF_PD_EN ( BIT(10) )
+#define BIT_ANA_SLP_DCDCARM_PD_EN ( BIT(9) )
+#define BIT_ANA_SLP_LDOEMMCCORE_PD_EN ( BIT(7) )
+#define BIT_ANA_SLP_LDOEMMCIO_PD_EN ( BIT(6) )
+#define BIT_ANA_SLP_LDORF2_PD_EN ( BIT(5) )
+#define BIT_ANA_SLP_LDORF1_PD_EN ( BIT(4) )
+#define BIT_ANA_SLP_LDORF0_PD_EN ( BIT(3) )
+#define BIT_ANA_SLP_LDOVDD25_PD_EN ( BIT(2) )
+#define BIT_ANA_SLP_LDOVDD28_PD_EN ( BIT(1) )
+#define BIT_ANA_SLP_LDOVDD18_PD_EN ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_SLP_CTRL1 */
+#define BIT_ANA_SLP_LDO_PD_EN ( BIT(12) )
+#define BIT_ANA_SLP_LDOLPREF_PD_EN ( BIT(11) )
+#define BIT_ANA_SLP_LDOCLSG_PD_EN ( BIT(10) )
+#define BIT_ANA_SLP_LDOUSB_PD_EN ( BIT(9) )
+#define BIT_ANA_SLP_LDOCAMMOT_PD_EN ( BIT(8) )
+#define BIT_ANA_SLP_LDOCAMIO_PD_EN ( BIT(7) )
+#define BIT_ANA_SLP_LDOCAMD_PD_EN ( BIT(6) )
+#define BIT_ANA_SLP_LDOCAMA_PD_EN ( BIT(5) )
+#define BIT_ANA_SLP_LDOSIM2_PD_EN ( BIT(4) )
+#define BIT_ANA_SLP_LDOSIM1_PD_EN ( BIT(3) )
+#define BIT_ANA_SLP_LDOSIM0_PD_EN ( BIT(2) )
+#define BIT_ANA_SLP_LDOSD_PD_EN ( BIT(1) )
+#define BIT_ANA_SLP_LDOAVDD18_PD_EN ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_SLP_CTRL2 */
+#define BIT_ANA_SLP_DCDC_BG_LP_EN ( BIT(15) )
+#define BIT_ANA_SLP_DCDCCORE_LP_EN ( BIT(11) )
+#define BIT_ANA_SLP_DCDCMEM_LP_EN ( BIT(10) )
+#define BIT_ANA_SLP_DCDCARM_LP_EN ( BIT(9) )
+#define BIT_ANA_SLP_DCDCGEN_LP_EN ( BIT(8) )
+#define BIT_ANA_SLP_DCDCWPA_LP_EN ( BIT(6) )
+#define BIT_ANA_SLP_DCDCWRF_LP_EN ( BIT(5) )
+#define BIT_ANA_SLP_LDOEMMCCORE_LP_EN ( BIT(4) )
+#define BIT_ANA_SLP_LDOEMMCIO_LP_EN ( BIT(3) )
+#define BIT_ANA_SLP_LDORF2_LP_EN ( BIT(2) )
+#define BIT_ANA_SLP_LDORF1_LP_EN ( BIT(1) )
+#define BIT_ANA_SLP_LDORF0_LP_EN ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_SLP_CTRL3 */
+#define BIT_ANA_SLP_BG_LP_EN ( BIT(15) )
+#define BIT_ANA_SLP_LDOVDD25_LP_EN ( BIT(13) )
+#define BIT_ANA_SLP_LDOVDD28_LP_EN ( BIT(12) )
+#define BIT_ANA_SLP_LDOVDD18_LP_EN ( BIT(11) )
+#define BIT_ANA_SLP_LDOCLSG_LP_EN ( BIT(10) )
+#define BIT_ANA_SLP_LDOUSB_LP_EN ( BIT(9) )
+#define BIT_ANA_SLP_LDOCAMMOT_LP_EN ( BIT(8) )
+#define BIT_ANA_SLP_LDOCAMIO_LP_EN ( BIT(7) )
+#define BIT_ANA_SLP_LDOCAMD_LP_EN ( BIT(6) )
+#define BIT_ANA_SLP_LDOCAMA_LP_EN ( BIT(5) )
+#define BIT_ANA_SLP_LDOSIM2_LP_EN ( BIT(4) )
+#define BIT_ANA_SLP_LDOSIM1_LP_EN ( BIT(3) )
+#define BIT_ANA_SLP_LDOSIM0_LP_EN ( BIT(2) )
+#define BIT_ANA_SLP_LDOSD_LP_EN ( BIT(1) )
+#define BIT_ANA_SLP_LDOAVDD18_LP_EN ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_AUD_SLP_CTRL4 */
+#define BIT_ANA_SLP_AUD_PA_SW_PD_EN ( BIT(15) )
+#define BIT_ANA_SLP_AUD_PA_LDO_PD_EN ( BIT(14) )
+#define BIT_ANA_SLP_AUD_PA_PD_EN ( BIT(13) )
+#define BIT_ANA_SLP_AUD_OVP_PD_PD_EN ( BIT(9) )
+#define BIT_ANA_SLP_AUD_OVP_LDO_PD_EN ( BIT(8) )
+#define BIT_ANA_SLP_AUD_VB_PD_EN ( BIT(7) )
+#define BIT_ANA_SLP_AUD_VBO_PD_EN ( BIT(6) )
+#define BIT_ANA_SLP_AUD_HEADMICBIAS_PD_EN ( BIT(5) )
+#define BIT_ANA_SLP_AUD_MICBIAS_HV_PD_EN ( BIT(2) )
+#define BIT_ANA_SLP_AUD_HEADMIC_PD_EN ( BIT(1) )
+#define BIT_ANA_SLP_AUD_PMUR1_PD_EN ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_SLP_CTRL */
+#define BITS_ANA_SLP_DCDCCORE_VOL_DROP_CNT(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_ANA_DCDC_CORE_CTL_DS_SW(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
+
+/* bits definitions for register REG_ANA_APB_IF_XTL_WAIT_CTRL */
+#define BIT_ANA_SLP_XTLBUF_PD_EN ( BIT(9) )
+#define BIT_ANA_XTL_EN ( BIT(8) )
+#define BITS_ANA_XTL_WAIT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_ANA_APB_IF_FLASH_CTRL */
+#define BIT_ANA_FLASH_PON ( BIT(15) )
+#define BIT_ANA_FLASH_V_HW_EN ( BIT(6) )
+#define BITS_ANA_FLASH_V_HW_STEP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_ANA_FLASH_V_SW(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_ANA_APB_IF_WHTLED_CTRL0 */
+#define BIT_ANA_WHTLED_PD_STS ( BIT(15) )
+#define BITS_ANA_WHTLED_DC(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BIT_ANA_WHTLED_BOOST_EN ( BIT(8) )
+#define BIT_ANA_WHTLED_SERIES_EN ( BIT(7) )
+#define BITS_ANA_WHTLED_V(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) )
+#define BIT_ANA_WHTLED_PD ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_WHTLED_CTRL1 */
+#define BIT_ANA_LCM_CABC_PWM_SEL ( BIT(15) )
+#define BIT_ANA_RTC_PWM0_EN ( BIT(14) )
+#define BIT_ANA_PWM0_EN ( BIT(13) )
+#define BITS_ANA_WHTLED_ISET(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_ANA_WHTLED_FRE_AD(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)) )
+#define BITS_ANA_WHTLED_CLMIT_OP(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_ANA_APB_IF_WHTLED_CTRL2 */
+#define BIT_ANA_WHTLED_DIMMING_SEL ( BIT(15) )
+#define BIT_ANA_WHTLED_PD_SEL ( BIT(14) )
+#define BIT_ANA_WHTLED_DIS_OVST ( BIT(13) )
+#define BIT_ANA_WHTLED_DIM_SEL ( BIT(12) )
+#define BIT_ANA_WHTLED_DE_BIAS ( BIT(11) )
+#define BIT_ANA_WHTLED_BUFF_SHT ( BIT(10) )
+#define BITS_ANA_WHTLED_STB_OP(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BIT_ANA_WHTLED_CAP_OPTION ( BIT(7) )
+#define BIT_ANA_WHTLED_OVP_DIS ( BIT(6) )
+#define BITS_ANA_WHTLED_REF_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+
+/* bits definitions for register REG_ANA_APB_IF_ANA_DRV_CTRL */
+#define BIT_ANA_SLP_RGB_PD_EN ( BIT(14) )
+#define BIT_ANA_RGB_PD_HW_EN ( BIT(13) )
+#define BITS_ANA_RGB_V(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
+#define BITS_ANA_KPLED_V(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_ANA_RGB_PD_SW ( BIT(2) )
+#define BIT_ANA_KPLED_PD ( BIT(1) )
+#define BIT_ANA_KPLED_PD_STS ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_VIBR_CTRL0 */
+#define BITS_ANA_VIBR_STABLE_V_HW(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_ANA_VIBR_INIT_V_HW(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_ANA_VIBR_V_SW(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_ANA_VIBR_PON ( BIT(2) )
+#define BIT_ANA_VIBR_SW_EN ( BIT(1) )
+
+/* bits definitions for register REG_ANA_APB_IF_VIBR_CTRL1 */
+#define BITS_ANA_VIBR_V_CONVERT_CNT_HW(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ANA_APB_IF_VIBR_CTRL2 */
+#define BIT_ANA_VIBR_PWR_ON_STS ( BIT(15) )
+#define BIT_ANA_VIBR_HW_FLOW_ERR1 ( BIT(14) )
+#define BIT_ANA_VIBR_HW_FLOW_ERR1_CLR ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_VIBR_WR_PROT_VALUE */
+#define BIT_ANA_VIBR_WR_PROT ( BIT(15) )
+#define BITS_ANA_VIBR_WR_PROT_VALUE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+
+/* bits definitions for register REG_ANA_APB_IF_AUDIO_CTRL */
+#define BIT_ANA_AUD_SLP_APP_RST_EN ( BIT(10) )
+#define BITS_ANA_CLK_AUD_HBD_DIV(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BIT_ANA_CLK_AUD_LOOP_INV_EN ( BIT(4) )
+#define BIT_ANA_CLK_AUDIF_TX_INV_EN ( BIT(3) )
+#define BIT_ANA_CLK_AUDIF_RX_INV_EN ( BIT(2) )
+#define BIT_ANA_CLK_AUD_6P5M_TX_INV_EN ( BIT(1) )
+#define BIT_ANA_CLK_AUD_6P5M_RX_INV_EN ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_CHGR_CTRL0 */
+#define BIT_ANA_CHGR_PD_STS ( BIT(15) )
+#define BITS_ANA_CHGR_CV_V(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_ANA_CHGR_END_V(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_ANA_CHG_PUMP_V(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BIT_ANA_CHGR_PD_RTCCLR ( BIT(1) )
+#define BIT_ANA_CHGR_PD_RTCSET ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_CHGR_CTRL1 */
+#define BIT_ANA_DP_DM_SW_EN ( BIT(15) )
+#define BITS_ANA_CHGR_CC_I(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_ANA_VBAT_OVP_V(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_ANA_VCHG_OVP_V(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+
+/* bits definitions for register REG_ANA_APB_IF_CHGR_CTRL2 */
+#define BITS_ANA_CHG_PUMP_CAL(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
+#define BIT_ANA_CHG_PUMP_PD ( BIT(8) )
+#define BIT_ANA_CHGR_CC_EN ( BIT(1) )
+#define BIT_ANA_RECHG ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_CHGR_STATUS */
+#define BIT_ANA_CHG_DET_DONE ( BIT(11) )
+#define BIT_ANA_DP_LOW ( BIT(10) )
+#define BIT_ANA_DCP_DET ( BIT(9) )
+#define BIT_ANA_CHG_DET ( BIT(8) )
+#define BIT_ANA_SDP_INT ( BIT(7) )
+#define BIT_ANA_DCP_INT ( BIT(6) )
+#define BIT_ANA_CDP_INT ( BIT(5) )
+#define BIT_ANA_CHGR_CV_STATUS ( BIT(4) )
+#define BIT_ANA_CHGR_ON ( BIT(3) )
+#define BIT_ANA_CHGR_INT ( BIT(2) )
+#define BIT_ANA_VBAT_OVI ( BIT(1) )
+#define BIT_ANA_VCHG_OVI ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_ANA_MIXED_CTRL */
+#define BIT_ANA_PTEST_PD_RTCSET ( BIT(15) )
+#define BIT_ANA_THM_CHIP_PD_FLAG ( BIT(8) )
+#define BIT_ANA_THM_CHIP_PD_FLAG_CLR ( BIT(7) )
+#define BITS_ANA_THM_CAL_SEL(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)) )
+#define BIT_ANA_THM_AUTO_PD_EN ( BIT(4) )
+#define BIT_ANA_BG_LP_EN ( BIT(3) )
+#define BITS_ANA_UVHO_T(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)) )
+#define BIT_ANA_UVHO_EN ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_PWR_XTL_EN0 */
+#define BIT_ANA_LDO_XTL_EN ( BIT(15) )
+#define BIT_ANA_LDO_RF1_EXT_XTL2_EN ( BIT(11) )
+#define BIT_ANA_LDO_RF1_EXT_XTL1_EN ( BIT(10) )
+#define BIT_ANA_LDO_RF1_EXT_XTL0_EN ( BIT(9) )
+#define BIT_ANA_LDO_RF1_XTL2_EN ( BIT(8) )
+#define BIT_ANA_LDO_RF1_XTL1_EN ( BIT(7) )
+#define BIT_ANA_LDO_RF1_XTL0_EN ( BIT(6) )
+#define BIT_ANA_LDO_RF0_EXT_XTL2_EN ( BIT(5) )
+#define BIT_ANA_LDO_RF0_EXT_XTL1_EN ( BIT(4) )
+#define BIT_ANA_LDO_RF0_EXT_XTL0_EN ( BIT(3) )
+#define BIT_ANA_LDO_RF0_XTL2_EN ( BIT(2) )
+#define BIT_ANA_LDO_RF0_XTL1_EN ( BIT(1) )
+#define BIT_ANA_LDO_RF0_XTL0_EN ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_PWR_XTL_EN1 */
+#define BIT_ANA_LDO_VDD25_EXT_XTL2_EN ( BIT(11) )
+#define BIT_ANA_LDO_VDD25_EXT_XTL1_EN ( BIT(10) )
+#define BIT_ANA_LDO_VDD25_EXT_XTL0_EN ( BIT(9) )
+#define BIT_ANA_LDO_VDD25_XTL2_EN ( BIT(8) )
+#define BIT_ANA_LDO_VDD25_XTL1_EN ( BIT(7) )
+#define BIT_ANA_LDO_VDD25_XTL0_EN ( BIT(6) )
+#define BIT_ANA_LDO_RF2_EXT_XTL2_EN ( BIT(5) )
+#define BIT_ANA_LDO_RF2_EXT_XTL1_EN ( BIT(4) )
+#define BIT_ANA_LDO_RF2_EXT_XTL0_EN ( BIT(3) )
+#define BIT_ANA_LDO_RF2_XTL2_EN ( BIT(2) )
+#define BIT_ANA_LDO_RF2_XTL1_EN ( BIT(1) )
+#define BIT_ANA_LDO_RF2_XTL0_EN ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_PWR_XTL_EN2 */
+#define BIT_ANA_LDO_AVDD18_EXT_XTL2_EN ( BIT(11) )
+#define BIT_ANA_LDO_AVDD18_EXT_XTL1_EN ( BIT(10) )
+#define BIT_ANA_LDO_AVDD18_EXT_XTL0_EN ( BIT(9) )
+#define BIT_ANA_LDO_AVDD18_XTL2_EN ( BIT(8) )
+#define BIT_ANA_LDO_AVDD18_XTL1_EN ( BIT(7) )
+#define BIT_ANA_LDO_AVDD18_XTL0_EN ( BIT(6) )
+#define BIT_ANA_LDO_SIM2_EXT_XTL2_EN ( BIT(5) )
+#define BIT_ANA_LDO_SIM2_EXT_XTL1_EN ( BIT(4) )
+#define BIT_ANA_LDO_SIM2_EXT_XTL0_EN ( BIT(3) )
+#define BIT_ANA_LDO_SIM2_XTL2_EN ( BIT(2) )
+#define BIT_ANA_LDO_SIM2_XTL1_EN ( BIT(1) )
+#define BIT_ANA_LDO_SIM2_XTL0_EN ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_PWR_XTL_EN3 */
+#define BIT_ANA_DCDC_BG_EXT_XTL2_EN ( BIT(11) )
+#define BIT_ANA_DCDC_BG_EXT_XTL1_EN ( BIT(10) )
+#define BIT_ANA_DCDC_BG_EXT_XTL0_EN ( BIT(9) )
+#define BIT_ANA_DCDC_BG_XTL2_EN ( BIT(8) )
+#define BIT_ANA_DCDC_BG_XTL1_EN ( BIT(7) )
+#define BIT_ANA_DCDC_BG_XTL0_EN ( BIT(6) )
+#define BIT_ANA_BG_EXT_XTL2_EN ( BIT(5) )
+#define BIT_ANA_BG_EXT_XTL1_EN ( BIT(4) )
+#define BIT_ANA_BG_EXT_XTL0_EN ( BIT(3) )
+#define BIT_ANA_BG_XTL2_EN ( BIT(2) )
+#define BIT_ANA_BG_XTL1_EN ( BIT(1) )
+#define BIT_ANA_BG_XTL0_EN ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_PWR_XTL_EN4 */
+#define BIT_ANA_DCDC_WRF_XTL2_EN ( BIT(14) )
+#define BIT_ANA_DCDC_WRF_XTL1_EN ( BIT(13) )
+#define BIT_ANA_DCDC_WRF_XTL0_EN ( BIT(12) )
+#define BIT_ANA_DCDC_WPA_XTL2_EN ( BIT(11) )
+#define BIT_ANA_DCDC_WPA_XTL1_EN ( BIT(10) )
+#define BIT_ANA_DCDC_WPA_XTL0_EN ( BIT(9) )
+#define BIT_ANA_DCDC_MEM_XTL2_EN ( BIT(8) )
+#define BIT_ANA_DCDC_MEM_XTL1_EN ( BIT(7) )
+#define BIT_ANA_DCDC_MEM_XTL0_EN ( BIT(6) )
+#define BIT_ANA_DCDC_GEN_XTL2_EN ( BIT(5) )
+#define BIT_ANA_DCDC_GEN_XTL1_EN ( BIT(4) )
+#define BIT_ANA_DCDC_GEN_XTL0_EN ( BIT(3) )
+#define BIT_ANA_DCDC_CORE_XTL2_EN ( BIT(2) )
+#define BIT_ANA_DCDC_CORE_XTL1_EN ( BIT(1) )
+#define BIT_ANA_DCDC_CORE_XTL0_EN ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_PWR_XTL_EN5 */
+#define BIT_ANA_DCDC_WRF_EXT_XTL2_EN ( BIT(14) )
+#define BIT_ANA_DCDC_WRF_EXT_XTL1_EN ( BIT(13) )
+#define BIT_ANA_DCDC_WRF_EXT_XTL0_EN ( BIT(12) )
+#define BIT_ANA_DCDC_WPA_EXT_XTL2_EN ( BIT(11) )
+#define BIT_ANA_DCDC_WPA_EXT_XTL1_EN ( BIT(10) )
+#define BIT_ANA_DCDC_WPA_EXT_XTL0_EN ( BIT(9) )
+#define BIT_ANA_DCDC_MEM_EXT_XTL2_EN ( BIT(8) )
+#define BIT_ANA_DCDC_MEM_EXT_XTL1_EN ( BIT(7) )
+#define BIT_ANA_DCDC_MEM_EXT_XTL0_EN ( BIT(6) )
+#define BIT_ANA_DCDC_GEN_EXT_XTL2_EN ( BIT(5) )
+#define BIT_ANA_DCDC_GEN_EXT_XTL1_EN ( BIT(4) )
+#define BIT_ANA_DCDC_GEN_EXT_XTL0_EN ( BIT(3) )
+#define BIT_ANA_DCDC_CORE_EXT_XTL2_EN ( BIT(2) )
+#define BIT_ANA_DCDC_CORE_EXT_XTL1_EN ( BIT(1) )
+#define BIT_ANA_DCDC_CORE_EXT_XTL0_EN ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_ANA_STATUS */
+#define BIT_ANA_BONDOPT6 ( BIT(6) )
+#define BIT_ANA_BONDOPT5 ( BIT(5) )
+#define BIT_ANA_BONDOPT4 ( BIT(4) )
+#define BIT_ANA_BONDOPT3 ( BIT(3) )
+#define BIT_ANA_BONDOPT2 ( BIT(2) )
+#define BIT_ANA_BONDOPT1 ( BIT(1) )
+#define BIT_ANA_BONDOPT0 ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_POR_RST_MONITOR */
+#define BITS_ANA_POR_RST_MONITOR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ANA_APB_IF_WDG_RST_MONITOR */
+#define BITS_ANA_WDG_RST_MONITOR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ANA_APB_IF_POR_PIN_RST_MONITOR */
+#define BITS_ANA_POR_PIN_RST_MONITOR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ANA_APB_IF_POR_SRC_FLAG */
+#define BIT_ANA_POR_SW_FORCE_ON ( BIT(15) )
+#define BITS_ANA_POR_SRC_FLAG(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+
+/* bits definitions for register REG_ANA_APB_IF_POR_7S_CTRL */
+#define BIT_ANA_PBINT_7S_FLAG_CLR ( BIT(15) )
+#define BIT_ANA_EXT_RSTN_FLAG_CLR ( BIT(14) )
+#define BIT_ANA_CHGR_INT_FLAG_CLR ( BIT(13) )
+#define BIT_ANA_PBINT2_FLAG_CLR ( BIT(12) )
+#define BIT_ANA_PBINT_FLAG_CLR ( BIT(11) )
+#define BIT_ANA_PBINT_7S_RST_SWMODE_RTCSTS ( BIT(10) )
+#define BIT_ANA_PBINT_7S_RST_SWMODE_RTCCLR ( BIT(9) )
+#define BIT_ANA_PBINT_7S_RST_SWMODE_RTCSET ( BIT(8) )
+#define BITS_ANA_PBINT_7S_RST_THRESHOLD(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_ANA_PBINT_7S_RST_DISABLE ( BIT(3) )
+#define BIT_ANA_PBINT_7S_RST_MODE_RTCSTS ( BIT(2) )
+#define BIT_ANA_PBINT_7S_RST_MODE_RTCCLR ( BIT(1) )
+#define BIT_ANA_PBINT_7S_RST_MODE_RTCSET ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_INT_DEBUG */
+#define BIT_ANA_OTP_INT_DEB ( BIT(10) )
+#define BIT_ANA_THM_INT_DEB ( BIT(9) )
+#define BIT_ANA_AUD_PROT_INT_DEB ( BIT(8) )
+#define BIT_ANA_AUD_HEADBTN_INT_DEB ( BIT(7) )
+#define BIT_ANA_EIC_INT_DEB ( BIT(6) )
+#define BIT_ANA_FGU_INT_DEB ( BIT(5) )
+#define BIT_ANA_WDG_INT_DEB ( BIT(4) )
+#define BIT_ANA_RTC_INT_DEB ( BIT(3) )
+#define BIT_ANA_GPIO_INT_DEB ( BIT(2) )
+#define BIT_ANA_ADC_INT_DEB ( BIT(1) )
+#define BIT_ANA_INT_DEBUG_EN ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_GPI_DEBUG */
+#define BIT_ANA_HEAD_INSERT2_DEB ( BIT(9) )
+#define BIT_ANA_HEAD_INSERT_DEB ( BIT(8) )
+#define BIT_ANA_HEAD_BUTTON_DEB ( BIT(7) )
+#define BIT_ANA_PBINT2_DEB ( BIT(6) )
+#define BIT_ANA_PBINT_DEB ( BIT(5) )
+#define BIT_ANA_VCHG_OVI_DEB ( BIT(4) )
+#define BIT_ANA_VBAT_OVI_DEB ( BIT(3) )
+#define BIT_ANA_CHGR_INT_DEB ( BIT(2) )
+#define BIT_ANA_GPI_DEBUG_EN ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_HWRST_RTC */
+#define BITS_ANA_HWRST_RTC_REG_STS(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_ANA_HWRST_RTC_REG_SET(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_ANA_APB_IF_CHIP_ID_LOW */
+#define BITS_ANA_CHIP_ID_LOW(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ANA_APB_IF_CHIP_ID_HIGH */
+#define BITS_ANA_CHIP_ID_HIGH(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ANA_APB_IF_ARM_MF_REG */
+#define BITS_ANA_ARM_MF_REG(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ANA_APB_IF_AFUSE_CTRL */
+#define BIT_ANA_AFUSE_READ_REQ ( BIT(7) )
+#define BITS_ANA_AFUSE_READ_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) )
+
+/* bits definitions for register REG_ANA_APB_IF_AFUSE_OUT0 */
+#define BITS_ANA_AFUSE_OUT0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ANA_APB_IF_AFUSE_OUT1 */
+#define BITS_ANA_AFUSE_OUT1(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ANA_APB_IF_AFUSE_OUT2 */
+#define BITS_ANA_AFUSE_OUT2(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ANA_APB_IF_AFUSE_OUT3 */
+#define BITS_ANA_AFUSE_OUT3(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ANA_APB_IF_CA_CTRL4 */
+#define BIT_ANA_EXT_RSTN_PD_EN ( BIT(14) )
+#define BIT_ANA_PB_7S_RST_PD_EN ( BIT(13) )
+#define BIT_ANA_WDG_RST_PD_EN ( BIT(12) )
+#define BIT_ANA_SW_RST_EMMCIO_PD_EN ( BIT(11) )
+#define BIT_ANA_SW_RST_EMMCCORE_PD_EN ( BIT(10) )
+#define BITS_ANA_SW_RST_PD_THRESHOLD(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+
+/* bits definitions for register REG_ANA_APB_IF_MCU_WR_PROT_VALUE */
+#define BIT_ANA_MCU_WR_PROT ( BIT(15) )
+#define BITS_ANA_MCU_WR_PROT_VALUE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+
+/* bits definitions for register REG_ANA_APB_IF_MP_PWR_CTRL0 */
+#define BIT_ANA_LDO_SIM1_EXT_XTL2_EN ( BIT(15) )
+#define BIT_ANA_LDO_SIM1_EXT_XTL1_EN ( BIT(14) )
+#define BIT_ANA_LDO_SIM1_EXT_XTL0_EN ( BIT(13) )
+#define BIT_ANA_LDO_SIM1_XTL2_EN ( BIT(12) )
+#define BIT_ANA_LDO_SIM1_XTL1_EN ( BIT(11) )
+#define BIT_ANA_LDO_SIM1_XTL0_EN ( BIT(10) )
+#define BIT_ANA_LDO_SIM0_EXT_XTL2_EN ( BIT(9) )
+#define BIT_ANA_LDO_SIM0_EXT_XTL1_EN ( BIT(8) )
+#define BIT_ANA_LDO_SIM0_EXT_XTL0_EN ( BIT(7) )
+#define BIT_ANA_LDO_SIM0_XTL2_EN ( BIT(6) )
+#define BIT_ANA_LDO_SIM0_XTL1_EN ( BIT(5) )
+#define BIT_ANA_LDO_SIM0_XTL0_EN ( BIT(4) )
+#define BIT_ANA_PWR_OFF_SEQ_EN ( BIT(3) )
+#define BIT_ANA_DCDC_CORE_SLP_OUT_STEP_EN ( BIT(1) )
+#define BIT_ANA_DCDC_CORE_SLP_IN_STEP_EN ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_MP_PWR_CTRL1 */
+#define BITS_ANA_DCDC_CORE_CTL_SLP_STEP5(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_ANA_DCDC_CORE_CTL_SLP_STEP4(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_ANA_DCDC_CORE_CTL_SLP_STEP3(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) )
+#define BITS_ANA_DCDC_CORE_CTL_SLP_STEP2(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) )
+#define BITS_ANA_DCDC_CORE_CTL_SLP_STEP1(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
+
+/* bits definitions for register REG_ANA_APB_IF_MP_PWR_CTRL2 */
+#define BITS_ANA_DCDC_CORE_CAL_SLP_STEP3(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_ANA_DCDC_CORE_CAL_SLP_STEP2(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_ANA_DCDC_CORE_CAL_SLP_STEP1(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_MP_PWR_CTRL3 */
+#define BITS_ANA_DCDC_ARM_STBOP(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) )
+#define BITS_ANA_DCDC_CORE_STBOP(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
+#define BITS_ANA_DCDC_CORE_CAL_SLP_STEP5(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_ANA_DCDC_CORE_CAL_SLP_STEP4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_MP_LDO_CTRL */
+#define BITS_ANA_LDOD_LP_CAL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_ANA_LDOA_LP_CAL(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_ANA_LDODCDC_LP_CAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_MP_CHG_CTRL */
+#define BIT_ANA_CHGR_INT_EN ( BIT(8) )
+#define BIT_ANA_CHGR_DRV ( BIT(5) )
+#define BIT_ANA_CHGR_OSC ( BIT(4) )
+#define BITS_ANA_CHGR_DPM(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_ANA_CHGR_ITERM(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_ANA_APB_IF_MP_MISC_CTRL */
+#define BITS_ANA_LDO_RF1_V_BOND(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)) )
+#define BITS_ANA_LDO_VDD25_V_BOND(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)) )
+#define BITS_ANA_DCDC_ARM_CTL_BOND(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) )
+#define BITS_ANA_DCDC_CORE_CTL_BOND(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) )
+#define BIT_ANA_DCOFFSET_EN ( BIT(2) )
+#define BIT_ANA_CHOP_EN ( BIT(1) )
+#define BIT_ANA_WHTLED_EXT_RES_CTRL ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_MP_DCDC_DEDT_CTRL */
+#define BITS_ANA_DCDC_WPA_DEDT_EN(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
+#define BITS_ANA_DCDC_WRF_DEDT_EN(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ANA_DCDC_GEN_DEDT_EN(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) )
+#define BITS_ANA_DCDC_MEM_DEDT_EN(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_ANA_DCDC_ARM_DEDT_EN(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_ANA_DCDC_CORE_DEDT_EN(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_ANA_APB_IF_CA_CTRL0 */
+#define BITS_ANA_SD_CLK_P(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) )
+#define BIT_ANA_SD_CHOP_CAP_EN ( BIT(13) )
+#define BIT_ANA_LDO_CAMIO_V_B2 ( BIT(12) )
+#define BIT_ANA_LDO_CAMIO_EXT_XTL2_EN ( BIT(11) )
+#define BIT_ANA_LDO_CAMIO_EXT_XTL1_EN ( BIT(10) )
+#define BIT_ANA_LDO_CAMIO_EXT_XTL0_EN ( BIT(9) )
+#define BIT_ANA_LDO_CAMIO_XTL2_EN ( BIT(8) )
+#define BIT_ANA_LDO_CAMIO_XTL1_EN ( BIT(7) )
+#define BIT_ANA_LDO_CAMIO_XTL0_EN ( BIT(6) )
+#define BIT_ANA_LDO_CAMD_EXT_XTL2_EN ( BIT(5) )
+#define BIT_ANA_LDO_CAMD_EXT_XTL1_EN ( BIT(4) )
+#define BIT_ANA_LDO_CAMD_EXT_XTL0_EN ( BIT(3) )
+#define BIT_ANA_LDO_CAMD_XTL2_EN ( BIT(2) )
+#define BIT_ANA_LDO_CAMD_XTL1_EN ( BIT(1) )
+#define BIT_ANA_LDO_CAMD_XTL0_EN ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_CA_CTRL1 */
+#define BITS_ANA_SMPL_MODE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ANA_APB_IF_CA_CTRL2 */
+#define BIT_ANA_SMPL_PWR_ON_FLAG ( BIT(15) )
+#define BIT_ANA_SMPL_MODE_WR_ACK_FLAG ( BIT(14) )
+#define BIT_ANA_SMPL_PWR_ON_FLAG_CLR ( BIT(13) )
+#define BIT_ANA_SMPL_MODE_WR_ACK_FLAG_CLR ( BIT(12) )
+#define BIT_ANA_SMPL_PWR_ON_SET ( BIT(11) )
+#define BIT_ANA_SLP_LDOKPLED_PD_EN ( BIT(9) )
+#define BIT_ANA_LDO_KPLED_PD ( BIT(8) )
+#define BITS_ANA_LDO_KPLED_V(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_ANA_APB_IF_CA_CTRL3 */
+#define BITS_ANA_VBAT_CRASH_V(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) )
+#define BIT_ANA_PBINT_7S_AUTO_ON_EN_CLR ( BIT(13) )
+#define BIT_ANA_PBINT_7S_AUTO_ON_EN_SET ( BIT(12) )
+#define BIT_ANA_VIBR_LDO_EN ( BIT(10) )
+#define BIT_ANA_SLP_LDOVIBR_PD_EN ( BIT(9) )
+#define BIT_ANA_LDO_VIBR_PD ( BIT(8) )
+#define BITS_ANA_LDO_VIBR_V(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_CORE_ADI */
+#define BITS_ANA_DCDC_CORE_CTL_SW_ADI(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_ANA_DCDC_CORE_CAL_SW_ADI(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_ARM_ADI */
+#define BITS_ANA_DCDC_ARM_CTL_ADI(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_ANA_DCDC_ARM_CAL_ADI(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_MEM_ADI */
+#define BIT_ANA_DCDC_MEM_CTL_ADI ( BIT(5) )
+#define BITS_ANA_DCDC_MEM_CAL_ADI(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_GEN_ADI */
+#define BITS_ANA_DCDC_GEN_CTL_ADI(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_ANA_DCDC_GEN_CAL_ADI(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_WRF_ADI */
+#define BITS_ANA_DCDC_WRF_CTL_ADI(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)) )
+#define BITS_ANA_DCDC_WRF_CAL_ADI(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_WPA_ADI */
+#define BITS_ANA_DCDC_WPA_CAL_ADI(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_WPA_DCM_ADI */
+#define BIT_ANA_DCDC_WPA_DCM_ADI ( BIT(0) )
+
+#endif
diff --git a/include/soc/sprd/chip_x20/__regs_ana_sc2713s_glb.h b/include/soc/sprd/chip_x20/__regs_ana_sc2713s_glb.h new file mode 100644 index 00000000..844a48da --- /dev/null +++ b/include/soc/sprd/chip_x20/__regs_ana_sc2713s_glb.h @@ -0,0 +1,931 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __REGS_ANA_SC2713S_GLB_H__ +#define __REGS_ANA_SC2713S_GLB_H__ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, include <mach/sci_glb_regs.h>" +#endif + +#define ANA_REGS_GLB + +/* registers definitions for controller ANA_REGS_GLB */ +#define ANA_REG_GLB_ARM_MODULE_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0000) +#define ANA_REG_GLB_ARM_CLK_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0004) +#define ANA_REG_GLB_RTC_CLK_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0008) +#define ANA_REG_GLB_ARM_RST SCI_ADDR(ANA_REGS_GLB_BASE, 0x000C) +#define ANA_REG_GLB_LDO_DCDC_PD_RTCSET SCI_ADDR(ANA_REGS_GLB_BASE, 0x0010) +#define ANA_REG_GLB_LDO_DCDC_PD_RTCCLR SCI_ADDR(ANA_REGS_GLB_BASE, 0x0014) +#define ANA_REG_GLB_RTC_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0018) +#define ANA_REG_GLB_LDO_PD_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x001C) +#define ANA_REG_GLB_LDO_V_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0020) +#define ANA_REG_GLB_LDO_V_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0024) +#define ANA_REG_GLB_LDO_V_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0028) +#define ANA_REG_GLB_LDO_CAL_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x002C) +#define ANA_REG_GLB_LDO_CAL_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0030) +#define ANA_REG_GLB_LDO_CAL_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0034) +#define ANA_REG_GLB_LDO_CAL_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0038) +#define ANA_REG_GLB_LDO_CAL_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x003C) +#define ANA_REG_GLB_LDO_CAL_CTRL5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0040) +#define ANA_REG_GLB_LDO_CAL_CTRL6 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0044) +#define ANA_REG_GLB_AUXAD_CTL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0048) +#define ANA_REG_GLB_DCDC_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x004C) +#define ANA_REG_GLB_DCDC_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0050) +#define ANA_REG_GLB_DCDC_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0054) +#define ANA_REG_GLB_DCDC_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0058) +#define ANA_REG_GLB_DCDC_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x005C) +#define ANA_REG_GLB_DCDC_CTRL5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0060) +#define ANA_REG_GLB_DCDC_CTRL6 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0064) +#define ANA_REG_GLB_DDR2_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0068) +#define ANA_REG_GLB_SLP_WAIT_DCDCARM SCI_ADDR(ANA_REGS_GLB_BASE, 0x006C) +#define ANA_REG_GLB_LDO1828_XTL_CTL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0070) +#define ANA_REG_GLB_LDO_SLP_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0074) +#define ANA_REG_GLB_LDO_SLP_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0078) +#define ANA_REG_GLB_LDO_SLP_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x007C) +#define ANA_REG_GLB_LDO_SLP_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0080) +#define ANA_REG_GLB_AUD_SLP_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0084) +#define ANA_REG_GLB_DCDC_SLP_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0088) +#define ANA_REG_GLB_XTL_WAIT_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x008C) +#define ANA_REG_GLB_FLASH_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0090) +#define ANA_REG_GLB_WHTLED_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0094) +#define ANA_REG_GLB_WHTLED_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0098) +#define ANA_REG_GLB_WHTLED_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x009C) +#define ANA_REG_GLB_ANA_DRV_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A0) +#define ANA_REG_GLB_VIBR_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A4) +#define ANA_REG_GLB_VIBR_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A8) +#define ANA_REG_GLB_VIBR_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00AC) +#define ANA_REG_GLB_VIBR_WR_PROT_VALUE SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B0) +#define ANA_REG_GLB_AUDIO_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B4) +#define ANA_REG_GLB_CHGR_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B8) +#define ANA_REG_GLB_CHGR_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00BC) +#define ANA_REG_GLB_CHGR_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C0) +#define ANA_REG_GLB_CHGR_STATUS SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C4) +#define ANA_REG_GLB_ANA_MIXED_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C8) +#define ANA_REG_GLB_PWR_XTL_EN0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00CC) +#define ANA_REG_GLB_PWR_XTL_EN1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D0) +#define ANA_REG_GLB_PWR_XTL_EN2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D4) +#define ANA_REG_GLB_PWR_XTL_EN3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D8) +#define ANA_REG_GLB_PWR_XTL_EN4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00DC) +#define ANA_REG_GLB_PWR_XTL_EN5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E0) +#define ANA_REG_GLB_ANA_STATUS SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E4) +#define ANA_REG_GLB_POR_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E8) +#define ANA_REG_GLB_WDG_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x00EC) +#define ANA_REG_GLB_POR_PIN_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F0) +#define ANA_REG_GLB_POR_SRC_FLAG SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F4) +#define ANA_REG_GLB_POR_7S_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F8) +#define ANA_REG_GLB_INT_DEBUG SCI_ADDR(ANA_REGS_GLB_BASE, 0x00FC) +#define ANA_REG_GLB_GPI_DEBUG SCI_ADDR(ANA_REGS_GLB_BASE, 0x0100) +#define ANA_REG_GLB_HWRST_RTC SCI_ADDR(ANA_REGS_GLB_BASE, 0x0104) +#define ANA_REG_GLB_CHIP_ID_LOW SCI_ADDR(ANA_REGS_GLB_BASE, 0x0108) +#define ANA_REG_GLB_CHIP_ID_HIGH SCI_ADDR(ANA_REGS_GLB_BASE, 0x010C) +#define ANA_REG_GLB_ARM_MF_REG SCI_ADDR(ANA_REGS_GLB_BASE, 0x0110) +#define ANA_REG_GLB_AFUSE_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0114) +#define ANA_REG_GLB_AFUSE_OUT0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0118) +#define ANA_REG_GLB_AFUSE_OUT1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x011C) +#define ANA_REG_GLB_AFUSE_OUT2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0120) +#define ANA_REG_GLB_AFUSE_OUT3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0124) +#define ANA_REG_GLB_CA_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0128) +#define ANA_REG_GLB_MCU_WR_PROT_VALUE SCI_ADDR(ANA_REGS_GLB_BASE, 0x012C) +#define ANA_REG_GLB_MP_PWR_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0130) +#define ANA_REG_GLB_MP_PWR_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0134) +#define ANA_REG_GLB_MP_PWR_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0138) +#define ANA_REG_GLB_MP_PWR_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x013C) +#define ANA_REG_GLB_MP_LDO_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0140) +#define ANA_REG_GLB_MP_CHG_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0144) +#define ANA_REG_GLB_MP_MISC_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0148) +#define ANA_REG_GLB_MP_DCDC_DEDT_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x014C) +#define ANA_REG_GLB_CA_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0150) +#define ANA_REG_GLB_CA_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0154) +#define ANA_REG_GLB_CA_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0158) +#define ANA_REG_GLB_CA_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x015C) +#define ANA_REG_GLB_DCDC_CORE_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0160) +#define ANA_REG_GLB_DCDC_ARM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0164) +#define ANA_REG_GLB_DCDC_MEM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0168) +#define ANA_REG_GLB_DCDC_GEN_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x016C) +#define ANA_REG_GLB_DCDC_WRF_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0170) +#define ANA_REG_GLB_DCDC_WPA_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0174) +#define ANA_REG_GLB_DCDC_WPA_DCM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x017C) + +#define ANA_REG_GLB_LDO_CAL_SEL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0044) + +/* bits definitions for register ANA_REG_GLB_ARM_MODULE_EN */ +#define BIT_ANA_THM_EN ( BIT(12) ) +#define BIT_ANA_BLTC_EN ( BIT(10) ) +#define BIT_ANA_PINREG_EN ( BIT(9) ) +#define BIT_ANA_FGU_EN ( BIT(8) ) +#define BIT_ANA_GPIO_EN ( BIT(7) ) +#define BIT_ANA_ADC_EN ( BIT(6) ) +#define BIT_ANA_HDT_EN ( BIT(5) ) +#define BIT_ANA_AUD_EN ( BIT(4) ) +#define BIT_ANA_EIC_EN ( BIT(3) ) +#define BIT_ANA_WDG_EN ( BIT(2) ) +#define BIT_ANA_RTC_EN ( BIT(1) ) + +/* bits definitions for register ANA_REG_GLB_ARM_CLK_EN */ +#define BIT_CLK_AUXAD_EN ( BIT(9) ) +#define BIT_CLK_AUXADC_EN ( BIT(8) ) +#define BIT_CLK_AUD_HID_EN ( BIT(5) ) +#define BIT_CLK_AUD_HBD_EN ( BIT(4) ) +#define BIT_CLK_AUD_LOOP_EN ( BIT(3) ) +#define BIT_CLK_AUD_6P5M_EN ( BIT(2) ) +#define BIT_CLK_AUDIF_EN ( BIT(1) ) + +/* bits definitions for register ANA_REG_GLB_RTC_CLK_EN */ +#define BIT_RTC_FLASH_EN ( BIT(13) ) +#define BIT_RTC_THMA_AUTO_EN ( BIT(12) ) +#define BIT_RTC_THMA_EN ( BIT(11) ) +#define BIT_RTC_THM_EN ( BIT(10) ) +#define BIT_RTC_BLTC_EN ( BIT(8) ) +#define BIT_RTC_FGU_EN ( BIT(7) ) +#define BIT_RTC_FGUA_EN ( BIT(6) ) +#define BIT_RTC_VIBR_EN ( BIT(5) ) +#define BIT_RTC_AUD_EN ( BIT(4) ) +#define BIT_RTC_EIC_EN ( BIT(3) ) +#define BIT_RTC_WDG_EN ( BIT(2) ) +#define BIT_RTC_RTC_EN ( BIT(1) ) +#define BIT_RTC_ARCH_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_ARM_RST */ +#define BIT_ANA_THMA_SOFT_RST ( BIT(14) ) +#define BIT_ANA_THM_SOFT_RST ( BIT(13) ) +#define BIT_ANA_AUD_32K_SOFT_RST ( BIT(12) ) +#define BIT_ANA_AUDTX_SOFT_RST ( BIT(11) ) +#define BIT_ANA_AUDRX_SOFT_RST ( BIT(10) ) +#define BIT_ANA_AUD_SOFT_RST ( BIT(9) ) +#define BIT_ANA_AUD_HDT_SOFT_RST ( BIT(8) ) +#define BIT_ANA_GPIO_SOFT_RST ( BIT(7) ) +#define BIT_ANA_ADC_SOFT_RST ( BIT(6) ) +#define BIT_ANA_PWM0_SOFT_RST ( BIT(5) ) +#define BIT_ANA_FGU_SOFT_RST ( BIT(4) ) +#define BIT_ANA_EIC_SOFT_RST ( BIT(3) ) +#define BIT_ANA_WDG_SOFT_RST ( BIT(2) ) +#define BIT_ANA_RTC_SOFT_RST ( BIT(1) ) +#define BIT_ANA_BLTC_SOFT_RST ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_DCDC_PD_RTCSET */ +#define BIT_LDO_AVDD18_PD_RTCSET ( BIT(15) ) +#define BIT_DCDC_OTP_PD_RTCSET ( BIT(14) ) +#define BIT_DCDC_WRF_PD_RTCSET ( BIT(13) ) +#define BIT_DCDC_GEN_PD_RTCSET ( BIT(12) ) +#define BIT_DCDC_MEM_PD_RTCSET ( BIT(11) ) +#define BIT_DCDC_ARM_PD_RTCSET ( BIT(10) ) +#define BIT_DCDC_CORE_PD_RTCSET ( BIT(9) ) +#define BIT_LDO_EMMCCORE_PD_RTCSET ( BIT(8) ) +#define BIT_LDO_EMMCIO_PD_RTCSET ( BIT(7) ) +#define BIT_LDO_RF2_PD_RTCSET ( BIT(6) ) +#define BIT_LDO_RF1_PD_RTCSET ( BIT(5) ) +#define BIT_LDO_RF0_PD_RTCSET ( BIT(4) ) +#define BIT_LDO_VDD25_PD_RTCSET ( BIT(3) ) +#define BIT_LDO_VDD28_PD_RTCSET ( BIT(2) ) +#define BIT_LDO_VDD18_PD_RTCSET ( BIT(1) ) +#define BIT_BG_PD_RTCSET ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_DCDC_PD_RTCCLR */ +#define BIT_LDO_AVDD18_PD_RTCCLR ( BIT(15) ) +#define BIT_DCDC_OTP_PD_RTCCLR ( BIT(14) ) +#define BIT_DCDC_WRF_PD_RTCCLR ( BIT(13) ) +#define BIT_DCDC_GEN_PD_RTCCLR ( BIT(12) ) +#define BIT_DCDC_MEM_PD_RTCCLR ( BIT(11) ) +#define BIT_DCDC_ARM_PD_RTCCLR ( BIT(10) ) +#define BIT_DCDC_CORE_PD_RTCCLR ( BIT(9) ) +#define BIT_LDO_EMMCCORE_PD_RTCCLR ( BIT(8) ) +#define BIT_LDO_EMMCIO_PD_RTCCLR ( BIT(7) ) +#define BIT_LDO_RF2_PD_RTCCLR ( BIT(6) ) +#define BIT_LDO_RF1_PD_RTCCLR ( BIT(5) ) +#define BIT_LDO_RF0_PD_RTCCLR ( BIT(4) ) +#define BIT_LDO_VDD25_PD_RTCCLR ( BIT(3) ) +#define BIT_LDO_VDD28_PD_RTCCLR ( BIT(2) ) +#define BIT_LDO_VDD18_PD_RTCCLR ( BIT(1) ) +#define BIT_BG_PD_RTCCLR ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_RTC_CTRL */ +#define BITS_XOSC32K_CTL_STS(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BIT_XOSC32K_CTL_B3_RTCCLR ( BIT(7) ) +#define BIT_XOSC32K_CTL_B2_RTCCLR ( BIT(6) ) +#define BIT_XOSC32K_CTL_B1_RTCCLR ( BIT(5) ) +#define BIT_XOSC32K_CTL_B0_RTCCLR ( BIT(4) ) +#define BIT_XOSC32K_CTL_B3_RTCSET ( BIT(3) ) +#define BIT_XOSC32K_CTL_B2_RTCSET ( BIT(2) ) +#define BIT_XOSC32K_CTL_B1_RTCSET ( BIT(1) ) +#define BIT_XOSC32K_CTL_B0_RTCSET ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_PD_CTRL */ +#define BIT_LDO_LPREF_PD_SW ( BIT(12) ) +#define BIT_DCDC_WPA_PD ( BIT(11) ) +#define BIT_LDO_CLSG_PD ( BIT(10) ) +#define BIT_LDO_USB_PD ( BIT(9) ) +#define BIT_LDO_CAMMOT_PD ( BIT(8) ) +#define BIT_LDO_CAMIO_PD ( BIT(7) ) +#define BIT_LDO_CAMD_PD ( BIT(6) ) +#define BIT_LDO_CAMA_PD ( BIT(5) ) +#define BIT_LDO_SIM2_PD ( BIT(4) ) +#define BIT_LDO_SIM1_PD ( BIT(3) ) +#define BIT_LDO_SIM0_PD ( BIT(2) ) +#define BIT_LDO_SD_PD ( BIT(1) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL0 */ +#define BITS_LDO_EMMCCORE_V(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_LDO_EMMCIO_V(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_LDO_RF2_V(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_LDO_RF1_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_LDO_RF0_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_LDO_VDD25_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_LDO_VDD28_V(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_LDO_VDD18_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL1 */ +#define BITS_LDO_SIM2_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_LDO_SIM1_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_LDO_SIM0_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_LDO_SD_V(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_LDO_AVDD18_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL2 */ +#define BITS_VBATBK_RES(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_VBATBK_V(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_LDO_CLSG_V(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_LDO_USB_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_LDO_CAMMOT_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_LDO_CAMIO_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_LDO_CAMD_V(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_LDO_CAMA_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL0 */ +#define BITS_LDO_VDD25_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_VDD28_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_VDD18_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL1 */ +#define BITS_LDO_RF2_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_RF1_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_RF0_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL2 */ +#define BITS_LDO_USB_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_EMMCCORE_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_EMMCIO_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL3 */ +#define BITS_LDO_SD_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_AVDD18_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL4 */ +#define BITS_LDO_CAMA_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_SIM2_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_SIM_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL5 */ +#define BITS_LDO_CAMMOT_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_CAMIO_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_CAMD_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL6 */ +#define BITS_LDOA_CAL_SEL(_x_) ( (_x_) << 11 & (BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_LDOD_CAL_SEL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_LDODCDC_CAL_SEL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_LDO_CLSG_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_AUXAD_CTL */ +#define BIT_AUXAD_CURRENTSEN_EN ( BIT(6) ) +#define BIT_AUXAD_CURRENTSEL ( BIT(5) ) +#define BITS_AUXAD_CURRENT_IBS(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL0 */ +#define BIT_DCDC_CORE_LP_EN ( BIT(15) ) +#define BIT_DCDC_CORE_CL_CTRL ( BIT(14) ) +#define BITS_DCDC_CORE_PDRSLOW(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_DCDC_CORE_PFM ( BIT(9) ) +#define BIT_DCDC_CORE_DCM ( BIT(8) ) +#define BIT_DCDC_ARM_LP_EN ( BIT(7) ) +#define BIT_DCDC_ARM_CL_CTRL ( BIT(6) ) +#define BITS_DCDC_ARM_PDRSLOW(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) +#define BIT_DCDC_ARM_PFM ( BIT(1) ) +#define BIT_DCDC_ARM_DCM ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL1 */ +#define BIT_DCDC_MEM_LP_EN ( BIT(15) ) +#define BIT_DCDC_MEM_CL_CTRL ( BIT(14) ) +#define BITS_DCDC_MEM_PDRSLOW(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_DCDC_MEM_PFM ( BIT(9) ) +#define BIT_DCDC_MEM_DCM ( BIT(8) ) +#define BIT_DCDC_GEN_LP_EN ( BIT(7) ) +#define BIT_DCDC_GEN_CL_CTRL ( BIT(6) ) +#define BITS_DCDC_GEN_PDRSLOW(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) +#define BIT_DCDC_GEN_PFM ( BIT(1) ) +#define BIT_DCDC_GEN_DCM ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL2 */ +#define BIT_DCDC_BG_LP_EN ( BIT(15) ) +#define BIT_DCDC_OTP_CHIP_PD_FLAG_CLR ( BIT(14) ) +#define BIT_DCDC_OTP_CHIP_PD_FLAG ( BIT(13) ) +#define BIT_DCDC_OTP_AUTO_PD_EN ( BIT(12) ) +#define BIT_DCDC_OTP_VBEOP ( BIT(11) ) +#define BITS_DCDC_OTP_S(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BIT_DCDC_WRF_LP_EN ( BIT(7) ) +#define BIT_DCDC_WRF_CL_CTRL ( BIT(6) ) +#define BITS_DCDC_WRF_PDRSLOW(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) +#define BIT_DCDC_WRF_PFM ( BIT(1) ) +#define BIT_DCDC_WRF_DCM ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL3 */ +#define BIT_DCDC_WPA_LP_EN ( BIT(8) ) +#define BIT_DCDC_WPA_CL_CTRL ( BIT(7) ) +#define BIT_DCDC_WPA_ZXOP ( BIT(6) ) +#define BITS_DCDC_WPA_PDRSLOW(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) +#define BIT_DCDC_WPA_PFM ( BIT(1) ) +#define BIT_DCDC_WPA_APTEN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL4 */ +#define BIT_DCDC_CORE_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_CORE_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_CORE_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_CORE_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_ARM_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_ARM_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_ARM_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_ARM_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL5 */ +#define BIT_DCDC_MEM_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_MEM_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_MEM_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_MEM_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_GEN_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_GEN_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_GEN_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_GEN_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL6 */ +#define BIT_DCDC_WPA_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_WPA_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_WPA_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_WPA_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_WRF_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_WRF_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_WRF_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_WRF_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DDR2_CTRL */ +#define BIT_DDR2_BUF_PD_HW ( BIT(9) ) +#define BITS_DDR2_BUF_S_DS(_x_) ( (_x_) << 7 & (BIT(7)|BIT(8)) ) +#define BITS_DDR2_BUF_CHNS_DS(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)) ) +#define BIT_DDR2_BUF_PD ( BIT(4) ) +#define BITS_DDR2_BUF_S(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DDR2_BUF_CHNS(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_SLP_WAIT_DCDCARM */ +#define BITS_SLP_IN_WAIT_DCDCARM(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_SLP_OUT_WAIT_DCDCARM(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO1828_XTL_CTL */ +#define BIT_LDO_VDD18_EXT_XTL2_EN ( BIT(11) ) +#define BIT_LDO_VDD18_EXT_XTL1_EN ( BIT(10) ) +#define BIT_LDO_VDD18_EXT_XTL0_EN ( BIT(9) ) +#define BIT_LDO_VDD18_XTL2_EN ( BIT(8) ) +#define BIT_LDO_VDD18_XTL1_EN ( BIT(7) ) +#define BIT_LDO_VDD18_XTL0_EN ( BIT(6) ) +#define BIT_LDO_VDD28_EXT_XTL2_EN ( BIT(5) ) +#define BIT_LDO_VDD28_EXT_XTL1_EN ( BIT(4) ) +#define BIT_LDO_VDD28_EXT_XTL0_EN ( BIT(3) ) +#define BIT_LDO_VDD28_XTL2_EN ( BIT(2) ) +#define BIT_LDO_VDD28_XTL1_EN ( BIT(1) ) +#define BIT_LDO_VDD28_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SLP_CTRL0 */ +#define BIT_SLP_IO_EN ( BIT(15) ) +#define BIT_SLP_DCDC_OTP_PD_EN ( BIT(13) ) +#define BIT_SLP_DCDCGEN_PD_EN ( BIT(12) ) +#define BIT_SLP_DCDCWPA_PD_EN ( BIT(11) ) +#define BIT_SLP_DCDCWRF_PD_EN ( BIT(10) ) +#define BIT_SLP_DCDCARM_PD_EN ( BIT(9) ) +#define BIT_SLP_LDOEMMCCORE_PD_EN ( BIT(7) ) +#define BIT_SLP_LDOEMMCIO_PD_EN ( BIT(6) ) +#define BIT_SLP_LDORF2_PD_EN ( BIT(5) ) +#define BIT_SLP_LDORF1_PD_EN ( BIT(4) ) +#define BIT_SLP_LDORF0_PD_EN ( BIT(3) ) +#define BIT_SLP_LDOVDD25_PD_EN ( BIT(2) ) +#define BIT_SLP_LDOVDD28_PD_EN ( BIT(1) ) +#define BIT_SLP_LDOVDD18_PD_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SLP_CTRL1 */ +#define BIT_SLP_LDO_PD_EN ( BIT(12) ) +#define BIT_SLP_LDOLPREF_PD_EN ( BIT(11) ) +#define BIT_SLP_LDOCLSG_PD_EN ( BIT(10) ) +#define BIT_SLP_LDOUSB_PD_EN ( BIT(9) ) +#define BIT_SLP_LDOCAMMOT_PD_EN ( BIT(8) ) +#define BIT_SLP_LDOCAMIO_PD_EN ( BIT(7) ) +#define BIT_SLP_LDOCAMD_PD_EN ( BIT(6) ) +#define BIT_SLP_LDOCAMA_PD_EN ( BIT(5) ) +#define BIT_SLP_LDOSIM2_PD_EN ( BIT(4) ) +#define BIT_SLP_LDOSIM1_PD_EN ( BIT(3) ) +#define BIT_SLP_LDOSIM0_PD_EN ( BIT(2) ) +#define BIT_SLP_LDOSD_PD_EN ( BIT(1) ) +#define BIT_SLP_LDOAVDD18_PD_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SLP_CTRL2 */ +#define BIT_SLP_DCDC_BG_LP_EN ( BIT(15) ) +#define BIT_SLP_DCDCCORE_LP_EN ( BIT(11) ) +#define BIT_SLP_DCDCMEM_LP_EN ( BIT(10) ) +#define BIT_SLP_DCDCARM_LP_EN ( BIT(9) ) +#define BIT_SLP_DCDCGEN_LP_EN ( BIT(8) ) +#define BIT_SLP_DCDCWPA_LP_EN ( BIT(6) ) +#define BIT_SLP_DCDCWRF_LP_EN ( BIT(5) ) +#define BIT_SLP_LDOEMMCCORE_LP_EN ( BIT(4) ) +#define BIT_SLP_LDOEMMCIO_LP_EN ( BIT(3) ) +#define BIT_SLP_LDORF2_LP_EN ( BIT(2) ) +#define BIT_SLP_LDORF1_LP_EN ( BIT(1) ) +#define BIT_SLP_LDORF0_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SLP_CTRL3 */ +#define BIT_SLP_BG_LP_EN ( BIT(15) ) +#define BIT_SLP_LDOVDD25_LP_EN ( BIT(13) ) +#define BIT_SLP_LDOVDD28_LP_EN ( BIT(12) ) +#define BIT_SLP_LDOVDD18_LP_EN ( BIT(11) ) +#define BIT_SLP_LDOCLSG_LP_EN ( BIT(10) ) +#define BIT_SLP_LDOUSB_LP_EN ( BIT(9) ) +#define BIT_SLP_LDOCAMMOT_LP_EN ( BIT(8) ) +#define BIT_SLP_LDOCAMIO_LP_EN ( BIT(7) ) +#define BIT_SLP_LDOCAMD_LP_EN ( BIT(6) ) +#define BIT_SLP_LDOCAMA_LP_EN ( BIT(5) ) +#define BIT_SLP_LDOSIM2_LP_EN ( BIT(4) ) +#define BIT_SLP_LDOSIM1_LP_EN ( BIT(3) ) +#define BIT_SLP_LDOSIM0_LP_EN ( BIT(2) ) +#define BIT_SLP_LDOSD_LP_EN ( BIT(1) ) +#define BIT_SLP_LDOAVDD18_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_AUD_SLP_CTRL4 */ +#define BIT_SLP_AUD_PA_SW_PD_EN ( BIT(15) ) +#define BIT_SLP_AUD_PA_LDO_PD_EN ( BIT(14) ) +#define BIT_SLP_AUD_PA_PD_EN ( BIT(13) ) +#define BIT_SLP_AUD_OVP_PD_PD_EN ( BIT(9) ) +#define BIT_SLP_AUD_OVP_LDO_PD_EN ( BIT(8) ) +#define BIT_SLP_AUD_VB_PD_EN ( BIT(7) ) +#define BIT_SLP_AUD_VBO_PD_EN ( BIT(6) ) +#define BIT_SLP_AUD_HEADMICBIAS_PD_EN ( BIT(5) ) +#define BIT_SLP_AUD_MICBIAS_HV_PD_EN ( BIT(2) ) +#define BIT_SLP_AUD_HEADMIC_PD_EN ( BIT(1) ) +#define BIT_SLP_AUD_PMUR1_PD_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL */ +#define BITS_SLP_DCDCCORE_VOL_DROP_CNT(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DCDC_CORE_CTL_DS(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register ANA_REG_GLB_XTL_WAIT_CTRL */ +#define BIT_SLP_XTLBUF_PD_EN ( BIT(9) ) +#define BIT_XTL_EN ( BIT(8) ) +#define BITS_XTL_WAIT(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_FLASH_CTRL */ +#define BIT_FLASH_PON ( BIT(15) ) +#define BIT_FLASH_V_HW_EN ( BIT(6) ) +#define BITS_FLASH_V_HW_STEP(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_FLASH_V_SW(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register ANA_REG_GLB_WHTLED_CTRL0 */ +#define BIT_WHTLED_PD_STS ( BIT(15) ) +#define BITS_WHTLED_DC(_x_) ( (_x_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BIT_WHTLED_BOOST_EN ( BIT(8) ) +#define BIT_WHTLED_SERIES_EN ( BIT(7) ) +#define BITS_WHTLED_V(_x_) ( (_x_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_WHTLED_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_WHTLED_CTRL1 */ +#define BIT_LCM_CABC_PWM_SEL ( BIT(15) ) +#define BIT_RTC_PWM0_EN ( BIT(14) ) +#define BIT_PWM0_EN ( BIT(13) ) +#define BITS_WHTLED_ISET(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_WHTLED_FRE_AD(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)) ) +#define BITS_WHTLED_CLMIT_OP(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_WHTLED_CTRL2 */ +#define BIT_WHTLED_DIMMING_SEL ( BIT(15) ) +#define BIT_WHTLED_PD_SEL ( BIT(14) ) +#define BIT_WHTLED_DIS_OVST ( BIT(13) ) +#define BIT_WHTLED_DIM_SEL ( BIT(12) ) +#define BIT_WHTLED_DE_BIAS ( BIT(11) ) +#define BIT_WHTLED_BUFF_SHT ( BIT(10) ) +#define BITS_WHTLED_STB_OP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_WHTLED_CAP_OPTION ( BIT(7) ) +#define BIT_WHTLED_OVP_DIS ( BIT(6) ) +#define BITS_WHTLED_REF_DC(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register ANA_REG_GLB_ANA_DRV_CTRL */ +#define BIT_SLP_RGB_PD_EN ( BIT(14) ) +#define BIT_RGB_PD_HW_EN ( BIT(13) ) +#define BITS_RGB_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BITS_KPLED_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_RGB_PD_SW ( BIT(2) ) +#define BIT_KPLED_PD ( BIT(1) ) +#define BIT_KPLED_PD_STS ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_VIBR_CTRL0 */ +#define BITS_VIBR_STABLE_V_HW(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_VIBR_INIT_V_HW(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_VIBR_V_SW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_VIBR_PON ( BIT(2) ) +#define BIT_VIBR_SW_EN ( BIT(1) ) + +/* bits definitions for register ANA_REG_GLB_VIBR_CTRL1 */ +#define BITS_VIBR_V_CONVERT_CNT_HW(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_VIBR_CTRL2 */ +#define BIT_VIBR_PWR_ON_STS ( BIT(15) ) +#define BIT_VIBR_HW_FLOW_ERR1 ( BIT(14) ) +#define BIT_VIBR_HW_FLOW_ERR1_CLR ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_VIBR_WR_PROT_VALUE */ +#define BIT_VIBR_WR_PROT ( BIT(15) ) +#define BITS_VIBR_WR_PROT_VALUE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_AUDIO_CTRL */ +#define BIT_AUD_SLP_APP_RST_EN ( BIT(10) ) +#define BITS_CLK_AUD_HBD_DIV(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BIT_CLK_AUD_LOOP_INV_EN ( BIT(4) ) +#define BIT_CLK_AUDIF_TX_INV_EN ( BIT(3) ) +#define BIT_CLK_AUDIF_RX_INV_EN ( BIT(2) ) +#define BIT_CLK_AUD_6P5M_TX_INV_EN ( BIT(1) ) +#define BIT_CLK_AUD_6P5M_RX_INV_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL0 */ +#define BIT_CHGR_PD_STS ( BIT(15) ) +#define BITS_CHGR_CV_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CHGR_END_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CHG_PUMP_V(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BIT_CHGR_PD_RTCCLR ( BIT(1) ) +#define BIT_CHGR_PD_RTCSET ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL1 */ +#define BIT_DP_DM_SW_EN ( BIT(15) ) +#define BITS_CHGR_CC_I(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_VBAT_OVP_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_VCHG_OVP_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL2 */ +#define BITS_CHG_PUMP_CAL(_x_) ( (_x_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_CHG_PUMP_PD ( BIT(8) ) +#define BIT_CHGR_CC_EN ( BIT(1) ) +#define BIT_RECHG ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_STATUS */ +#define BIT_CHG_DET_DONE ( BIT(11) ) +#define BIT_DP_LOW ( BIT(10) ) +#define BIT_DCP_DET ( BIT(9) ) +#define BIT_CHG_DET ( BIT(8) ) +#define BIT_SDP_INT ( BIT(7) ) +#define BIT_DCP_INT ( BIT(6) ) +#define BIT_CDP_INT ( BIT(5) ) +#define BIT_CHGR_CV_STATUS ( BIT(4) ) +#define BIT_CHGR_ON ( BIT(3) ) +#define BIT_CHGR_INT ( BIT(2) ) +#define BIT_VBAT_OVI ( BIT(1) ) +#define BIT_VCHG_OVI ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_ANA_MIXED_CTRL */ +#define BIT_PTEST_PD_RTCSET ( BIT(15) ) +#define BIT_THM_CHIP_PD_FLAG ( BIT(8) ) +#define BIT_THM_CHIP_PD_FLAG_CLR ( BIT(7) ) +#define BITS_THM_CAL_SEL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)) ) +#define BIT_THM_AUTO_PD_EN ( BIT(4) ) +#define BIT_BG_LP_EN ( BIT(3) ) +#define BITS_UVHO_T(_x_) ( (_x_) << 1 & (BIT(1)|BIT(2)) ) +#define BIT_UVHO_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN0 */ +#define BIT_LDO_XTL_EN ( BIT(15) ) +#define BIT_LDO_RF1_EXT_XTL2_EN ( BIT(11) ) +#define BIT_LDO_RF1_EXT_XTL1_EN ( BIT(10) ) +#define BIT_LDO_RF1_EXT_XTL0_EN ( BIT(9) ) +#define BIT_LDO_RF1_XTL2_EN ( BIT(8) ) +#define BIT_LDO_RF1_XTL1_EN ( BIT(7) ) +#define BIT_LDO_RF1_XTL0_EN ( BIT(6) ) +#define BIT_LDO_RF0_EXT_XTL2_EN ( BIT(5) ) +#define BIT_LDO_RF0_EXT_XTL1_EN ( BIT(4) ) +#define BIT_LDO_RF0_EXT_XTL0_EN ( BIT(3) ) +#define BIT_LDO_RF0_XTL2_EN ( BIT(2) ) +#define BIT_LDO_RF0_XTL1_EN ( BIT(1) ) +#define BIT_LDO_RF0_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN1 */ +#define BIT_LDO_VDD25_EXT_XTL2_EN ( BIT(11) ) +#define BIT_LDO_VDD25_EXT_XTL1_EN ( BIT(10) ) +#define BIT_LDO_VDD25_EXT_XTL0_EN ( BIT(9) ) +#define BIT_LDO_VDD25_XTL2_EN ( BIT(8) ) +#define BIT_LDO_VDD25_XTL1_EN ( BIT(7) ) +#define BIT_LDO_VDD25_XTL0_EN ( BIT(6) ) +#define BIT_LDO_RF2_EXT_XTL2_EN ( BIT(5) ) +#define BIT_LDO_RF2_EXT_XTL1_EN ( BIT(4) ) +#define BIT_LDO_RF2_EXT_XTL0_EN ( BIT(3) ) +#define BIT_LDO_RF2_XTL2_EN ( BIT(2) ) +#define BIT_LDO_RF2_XTL1_EN ( BIT(1) ) +#define BIT_LDO_RF2_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN2 */ +#define BIT_LDO_AVDD18_EXT_XTL2_EN ( BIT(11) ) +#define BIT_LDO_AVDD18_EXT_XTL1_EN ( BIT(10) ) +#define BIT_LDO_AVDD18_EXT_XTL0_EN ( BIT(9) ) +#define BIT_LDO_AVDD18_XTL2_EN ( BIT(8) ) +#define BIT_LDO_AVDD18_XTL1_EN ( BIT(7) ) +#define BIT_LDO_AVDD18_XTL0_EN ( BIT(6) ) +#define BIT_LDO_SIM2_EXT_XTL2_EN ( BIT(5) ) +#define BIT_LDO_SIM2_EXT_XTL1_EN ( BIT(4) ) +#define BIT_LDO_SIM2_EXT_XTL0_EN ( BIT(3) ) +#define BIT_LDO_SIM2_XTL2_EN ( BIT(2) ) +#define BIT_LDO_SIM2_XTL1_EN ( BIT(1) ) +#define BIT_LDO_SIM2_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN3 */ +#define BIT_DCDC_BG_EXT_XTL2_EN ( BIT(11) ) +#define BIT_DCDC_BG_EXT_XTL1_EN ( BIT(10) ) +#define BIT_DCDC_BG_EXT_XTL0_EN ( BIT(9) ) +#define BIT_DCDC_BG_XTL2_EN ( BIT(8) ) +#define BIT_DCDC_BG_XTL1_EN ( BIT(7) ) +#define BIT_DCDC_BG_XTL0_EN ( BIT(6) ) +#define BIT_BG_EXT_XTL2_EN ( BIT(5) ) +#define BIT_BG_EXT_XTL1_EN ( BIT(4) ) +#define BIT_BG_EXT_XTL0_EN ( BIT(3) ) +#define BIT_BG_XTL2_EN ( BIT(2) ) +#define BIT_BG_XTL1_EN ( BIT(1) ) +#define BIT_BG_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN4 */ +#define BIT_DCDC_WRF_XTL2_EN ( BIT(14) ) +#define BIT_DCDC_WRF_XTL1_EN ( BIT(13) ) +#define BIT_DCDC_WRF_XTL0_EN ( BIT(12) ) +#define BIT_DCDC_WPA_XTL2_EN ( BIT(11) ) +#define BIT_DCDC_WPA_XTL1_EN ( BIT(10) ) +#define BIT_DCDC_WPA_XTL0_EN ( BIT(9) ) +#define BIT_DCDC_MEM_XTL2_EN ( BIT(8) ) +#define BIT_DCDC_MEM_XTL1_EN ( BIT(7) ) +#define BIT_DCDC_MEM_XTL0_EN ( BIT(6) ) +#define BIT_DCDC_GEN_XTL2_EN ( BIT(5) ) +#define BIT_DCDC_GEN_XTL1_EN ( BIT(4) ) +#define BIT_DCDC_GEN_XTL0_EN ( BIT(3) ) +#define BIT_DCDC_CORE_XTL2_EN ( BIT(2) ) +#define BIT_DCDC_CORE_XTL1_EN ( BIT(1) ) +#define BIT_DCDC_CORE_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN5 */ +#define BIT_DCDC_WRF_EXT_XTL2_EN ( BIT(14) ) +#define BIT_DCDC_WRF_EXT_XTL1_EN ( BIT(13) ) +#define BIT_DCDC_WRF_EXT_XTL0_EN ( BIT(12) ) +#define BIT_DCDC_WPA_EXT_XTL2_EN ( BIT(11) ) +#define BIT_DCDC_WPA_EXT_XTL1_EN ( BIT(10) ) +#define BIT_DCDC_WPA_EXT_XTL0_EN ( BIT(9) ) +#define BIT_DCDC_MEM_EXT_XTL2_EN ( BIT(8) ) +#define BIT_DCDC_MEM_EXT_XTL1_EN ( BIT(7) ) +#define BIT_DCDC_MEM_EXT_XTL0_EN ( BIT(6) ) +#define BIT_DCDC_GEN_EXT_XTL2_EN ( BIT(5) ) +#define BIT_DCDC_GEN_EXT_XTL1_EN ( BIT(4) ) +#define BIT_DCDC_GEN_EXT_XTL0_EN ( BIT(3) ) +#define BIT_DCDC_CORE_EXT_XTL2_EN ( BIT(2) ) +#define BIT_DCDC_CORE_EXT_XTL1_EN ( BIT(1) ) +#define BIT_DCDC_CORE_EXT_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_ANA_STATUS */ +#define BIT_BONDOPT6 ( BIT(6) ) +#define BIT_BONDOPT5 ( BIT(5) ) +#define BIT_BONDOPT4 ( BIT(4) ) +#define BIT_BONDOPT3 ( BIT(3) ) +#define BIT_BONDOPT2 ( BIT(2) ) +#define BIT_BONDOPT1 ( BIT(1) ) +#define BIT_BONDOPT0 ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_POR_RST_MONITOR */ +#define BITS_POR_RST_MONITOR(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_WDG_RST_MONITOR */ +#define BITS_WDG_RST_MONITOR(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_POR_PIN_RST_MONITOR */ +#define BITS_POR_PIN_RST_MONITOR(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_POR_SRC_FLAG */ +#define BIT_POR_SW_FORCE_ON ( BIT(15) ) +#define BITS_POR_SRC_FLAG(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_POR_7S_CTRL */ +#define BIT_PBINT_7S_FLAG_CLR ( BIT(15) ) +#define BIT_EXT_RSTN_FLAG_CLR ( BIT(14) ) +#define BIT_CHGR_INT_FLAG_CLR ( BIT(13) ) +#define BIT_PBINT2_FLAG_CLR ( BIT(12) ) +#define BIT_PBINT_FLAG_CLR ( BIT(11) ) +#define BIT_PBINT_7S_RST_SWMODE_RTCSTS ( BIT(10) ) +#define BIT_PBINT_7S_RST_SWMODE_RTCCLR ( BIT(9) ) +#define BIT_PBINT_7S_RST_SWMODE_RTCSET ( BIT(8) ) +#define BITS_PBINT_7S_RST_THRESHOLD(_x_)( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_PBINT_7S_RST_DISABLE ( BIT(3) ) +#define BIT_PBINT_7S_RST_MODE_RTCSTS ( BIT(2) ) +#define BIT_PBINT_7S_RST_MODE_RTCCLR ( BIT(1) ) +#define BIT_PBINT_7S_RST_MODE_RTCSET ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_INT_DEBUG */ +#define BIT_OTP_INT_DEB ( BIT(10) ) +#define BIT_THM_INT_DEB ( BIT(9) ) +#define BIT_AUD_PROT_INT_DEB ( BIT(8) ) +#define BIT_AUD_HEADBTN_INT_DEB ( BIT(7) ) +#define BIT_EIC_INT_DEB ( BIT(6) ) +#define BIT_FGU_INT_DEB ( BIT(5) ) +#define BIT_WDG_INT_DEB ( BIT(4) ) +#define BIT_RTC_INT_DEB ( BIT(3) ) +#define BIT_GPIO_INT_DEB ( BIT(2) ) +#define BIT_ADC_INT_DEB ( BIT(1) ) +#define BIT_INT_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_GPI_DEBUG */ +#define BIT_HEAD_INSERT2_DEB ( BIT(9) ) +#define BIT_HEAD_INSERT_DEB ( BIT(8) ) +#define BIT_HEAD_BUTTON_DEB ( BIT(7) ) +#define BIT_PBINT2_DEB ( BIT(6) ) +#define BIT_PBINT_DEB ( BIT(5) ) +#define BIT_VCHG_OVI_DEB ( BIT(4) ) +#define BIT_VBAT_OVI_DEB ( BIT(3) ) +#define BIT_CHGR_INT_DEB ( BIT(2) ) +#define BIT_GPI_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_HWRST_RTC */ +#define BITS_HWRST_RTC_REG_STS(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_HWRST_RTC_REG_SET(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_CHIP_ID_LOW */ +#define BITS_CHIP_ID_LOW(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_CHIP_ID_HIGH */ +#define BITS_CHIP_ID_HIGH(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_ARM_MF_REG */ +#define BITS_ARM_MF_REG(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_AFUSE_CTRL */ +#define BIT_AFUSE_READ_REQ ( BIT(7) ) +#define BITS_AFUSE_READ_DLY(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) + +/* bits definitions for register ANA_REG_GLB_AFUSE_OUT0 */ +#define BITS_AFUSE_OUT0(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_AFUSE_OUT1 */ +#define BITS_AFUSE_OUT1(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_AFUSE_OUT2 */ +#define BITS_AFUSE_OUT2(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_AFUSE_OUT3 */ +#define BITS_AFUSE_OUT3(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_CA_CTRL4 */ +#define BIT_EXT_RSTN_PD_EN ( BIT(14) ) +#define BIT_PB_7S_RST_PD_EN ( BIT(13) ) +#define BIT_WDG_RST_PD_EN ( BIT(12) ) +#define BIT_SW_RST_EMMCIO_PD_EN ( BIT(11) ) +#define BIT_SW_RST_EMMCCORE_PD_EN ( BIT(10) ) +#define BITS_SW_RST_PD_THRESHOLD(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) + +/* bits definitions for register ANA_REG_GLB_MCU_WR_PROT_VALUE */ +#define BIT_MCU_WR_PROT ( BIT(15) ) +#define BITS_MCU_WR_PROT_VALUE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_MP_PWR_CTRL0 */ +#define BIT_LDO_SIM1_EXT_XTL2_EN ( BIT(15) ) +#define BIT_LDO_SIM1_EXT_XTL1_EN ( BIT(14) ) +#define BIT_LDO_SIM1_EXT_XTL0_EN ( BIT(13) ) +#define BIT_LDO_SIM1_XTL2_EN ( BIT(12) ) +#define BIT_LDO_SIM1_XTL1_EN ( BIT(11) ) +#define BIT_LDO_SIM1_XTL0_EN ( BIT(10) ) +#define BIT_LDO_SIM0_EXT_XTL2_EN ( BIT(9) ) +#define BIT_LDO_SIM0_EXT_XTL1_EN ( BIT(8) ) +#define BIT_LDO_SIM0_EXT_XTL0_EN ( BIT(7) ) +#define BIT_LDO_SIM0_XTL2_EN ( BIT(6) ) +#define BIT_LDO_SIM0_XTL1_EN ( BIT(5) ) +#define BIT_LDO_SIM0_XTL0_EN ( BIT(4) ) +#define BIT_PWR_OFF_SEQ_EN ( BIT(3) ) +#define BIT_DCDC_CORE_SLP_OUT_STEP_EN ( BIT(1) ) +#define BIT_DCDC_CORE_SLP_IN_STEP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_MP_PWR_CTRL1 */ +#define BITS_DCDC_CORE_CTL_SLP_STEP5(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_DCDC_CORE_CTL_SLP_STEP4(_x_) ( (_x_) << 9 & (BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DCDC_CORE_CTL_SLP_STEP3(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_DCDC_CORE_CTL_SLP_STEP2(_x_) ( (_x_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_DCDC_CORE_CTL_SLP_STEP1(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register ANA_REG_GLB_MP_PWR_CTRL2 */ +#define BITS_DCDC_CORE_CAL_SLP_STEP3(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_DCDC_CORE_CAL_SLP_STEP2(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CAL_SLP_STEP1(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_MP_PWR_CTRL3 */ +#define BITS_DCDC_ARM_STBOP(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_DCDC_CORE_STBOP(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_DCDC_CORE_CAL_SLP_STEP5(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CAL_SLP_STEP4(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_MP_LDO_CTRL */ +#define BITS_LDOD_LP_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDOA_LP_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDODCDC_LP_CAL(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_MP_CHG_CTRL */ +#define BIT_CHGR_INT_EN ( BIT(8) ) +#define BIT_CHGR_DRV ( BIT(5) ) +#define BIT_CHGR_OSC ( BIT(4) ) +#define BITS_CHGR_DPM(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_CHGR_ITERM(_x_) ( (_x_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_MP_MISC_CTRL */ +#define BITS_LDO_RF1_V_BOND(_x_) ( (_x_) << 11 & (BIT(11)|BIT(12)) ) +#define BITS_LDO_VDD25_V_BOND(_x_) ( (_x_) << 9 & (BIT(9)|BIT(10)) ) +#define BITS_DCDC_ARM_CTL_BOND(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_DCDC_CORE_CTL_BOND(_x_) ( (_x_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BIT_DCOFFSET_EN ( BIT(2) ) +#define BIT_CHOP_EN ( BIT(1) ) +#define BIT_WHTLED_EXT_RES_CTRL ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_MP_DCDC_DEDT_CTRL */ +#define BITS_DCDC_WPA_DEDT_EN(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_DCDC_WRF_DEDT_EN(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_DCDC_GEN_DEDT_EN(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_DCDC_MEM_DEDT_EN(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_DCDC_ARM_DEDT_EN(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DCDC_CORE_DEDT_EN(_x_) ( (_x_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_CA_CTRL0 */ +#define BITS_SD_CLK_P(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BIT_SD_CHOP_CAP_EN ( BIT(13) ) +#define BIT_LDO_CAMIO_V_B2 ( BIT(12) ) +#define BIT_LDO_CAMIO_EXT_XTL2_EN ( BIT(11) ) +#define BIT_LDO_CAMIO_EXT_XTL1_EN ( BIT(10) ) +#define BIT_LDO_CAMIO_EXT_XTL0_EN ( BIT(9) ) +#define BIT_LDO_CAMIO_XTL2_EN ( BIT(8) ) +#define BIT_LDO_CAMIO_XTL1_EN ( BIT(7) ) +#define BIT_LDO_CAMIO_XTL0_EN ( BIT(6) ) +#define BIT_LDO_CAMD_EXT_XTL2_EN ( BIT(5) ) +#define BIT_LDO_CAMD_EXT_XTL1_EN ( BIT(4) ) +#define BIT_LDO_CAMD_EXT_XTL0_EN ( BIT(3) ) +#define BIT_LDO_CAMD_XTL2_EN ( BIT(2) ) +#define BIT_LDO_CAMD_XTL1_EN ( BIT(1) ) +#define BIT_LDO_CAMD_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CA_CTRL1 */ +#define BITS_SMPL_MODE(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_CA_CTRL2 */ +#define BIT_SMPL_PWR_ON_FLAG ( BIT(15) ) +#define BIT_SMPL_MODE_WR_ACK_FLAG ( BIT(14) ) +#define BIT_SMPL_PWR_ON_FLAG_CLR ( BIT(13) ) +#define BIT_SMPL_MODE_WR_ACK_FLAG_CLR ( BIT(12) ) +#define BIT_SMPL_PWR_ON_SET ( BIT(11) ) +#define BIT_SLP_LDOKPLED_PD_EN ( BIT(9) ) +#define BIT_LDO_KPLED_PD ( BIT(8) ) +#define BITS_LDO_KPLED_V(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_CA_CTRL3 */ +#define BITS_VBAT_CRASH_V(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BIT_PBINT_7S_AUTO_ON_EN_CLR ( BIT(13) ) +#define BIT_PBINT_7S_AUTO_ON_EN_SET ( BIT(12) ) +#define BIT_VIBR_LDO_EN ( BIT(10) ) +#define BIT_SLP_LDOVIBR_PD_EN ( BIT(9) ) +#define BIT_LDO_VIBR_PD ( BIT(8) ) +#define BITS_LDO_VIBR_V(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CORE_ADI */ +#define BITS_DCDC_CORE_CTL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DCDC_CORE_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_ARM_ADI */ +#define BITS_DCDC_ARM_CTL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DCDC_ARM_CAL_ADI(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_MEM_ADI */ +#define BIT_DCDC_MEM_CTL_ADI ( BIT(5) ) +#define BITS_DCDC_MEM_CAL_ADI(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_GEN_ADI */ +#define BITS_DCDC_GEN_CTL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DCDC_GEN_CAL_ADI(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_WRF_ADI */ +#define BITS_DCDC_WRF_CTL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)) ) +#define BITS_DCDC_WRF_CAL_ADI(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_WPA_ADI */ +#define BITS_DCDC_WPA_CAL_ADI(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_WPA_DCM_ADI */ +#define BIT_DCDC_WPA_DCM_ADI ( BIT(0) ) + +#endif /* __REGS_ANA_SC2713S_GLB_H__ */ diff --git a/include/soc/sprd/chip_x20/__regs_ana_sc2723_glb.h b/include/soc/sprd/chip_x20/__regs_ana_sc2723_glb.h new file mode 100644 index 00000000..f707171c --- /dev/null +++ b/include/soc/sprd/chip_x20/__regs_ana_sc2723_glb.h @@ -0,0 +1,949 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __ANA_REGS_GLB_H__ +#define __ANA_REGS_GLB_H__ + +#define ANA_REGS_GLB + +/* registers definitions for controller ANA_REGS_GLB */ +#define ANA_REG_GLB_ARM_MODULE_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0000) +#define ANA_REG_GLB_ARM_CLK_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0004) +#define ANA_REG_GLB_RTC_CLK_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0008) +#define ANA_REG_GLB_ARM_RST SCI_ADDR(ANA_REGS_GLB_BASE, 0x000C) +#define ANA_REG_GLB_LDO_DCDC_PD SCI_ADDR(ANA_REGS_GLB_BASE, 0x0010) +#define ANA_REG_GLB_LDO_PD_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0014) +#define ANA_REG_GLB_LDO_V_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0018) +#define ANA_REG_GLB_LDO_V_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x001C) +#define ANA_REG_GLB_LDO_V_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0020) +#define ANA_REG_GLB_LDO_V_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0024) +#define ANA_REG_GLB_LDO_V_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0028) +#define ANA_REG_GLB_LDO_V_CTRL5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x002C) +#define ANA_REG_GLB_LDO_V_CTRL6 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0030) +#define ANA_REG_GLB_LDO_V_CTRL7 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0034) +#define ANA_REG_GLB_LDO_V_CTRL8 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0038) +#define ANA_REG_GLB_LDO_V_CTRL9 SCI_ADDR(ANA_REGS_GLB_BASE, 0x003C) +#define ANA_REG_GLB_LDO_V_CTRL10 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0040) +#define ANA_REG_GLB_LDO_V_CTRL11 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0044) +#define ANA_REG_GLB_LDO_LP_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0048) +#define ANA_REG_GLB_DCDC_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x004C) +#define ANA_REG_GLB_DCDC_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0050) +#define ANA_REG_GLB_DCDC_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0054) +#define ANA_REG_GLB_DCDC_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0058) +#define ANA_REG_GLB_DCDC_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x005C) +#define ANA_REG_GLB_DCDC_CTRL5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0060) +#define ANA_REG_GLB_DCDC_CTRL6 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0064) +#define ANA_REG_GLB_DCDC_CTRL7 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0068) +#define ANA_REG_GLB_DCDC_CTRL8 SCI_ADDR(ANA_REGS_GLB_BASE, 0x006C) +#define ANA_REG_GLB_DCDC_CTRL9 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0070) +#define ANA_REG_GLB_DCDC_CTRL10 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0074) +#define ANA_REG_GLB_DCDC_CTRL11 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0078) +#define ANA_REG_GLB_DCDC_CTRL12 SCI_ADDR(ANA_REGS_GLB_BASE, 0x007C) +#define ANA_REG_GLB_DCDC_CTRL13 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0080) +#define ANA_REG_GLB_DCDC_CTRL14 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0084) +#define ANA_REG_GLB_DCDC_CTRL15 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0088) +#define ANA_REG_GLB_SLP_WAIT_DCDCARM SCI_ADDR(ANA_REGS_GLB_BASE, 0x008C) +#define ANA_REG_GLB_PWR_SLP_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0090) +#define ANA_REG_GLB_PWR_SLP_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0094) +#define ANA_REG_GLB_PWR_SLP_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0098) +#define ANA_REG_GLB_PWR_SLP_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x009C) +#define ANA_REG_GLB_PWR_SLP_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A0) +#define ANA_REG_GLB_AUD_SLP_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A4) +#define ANA_REG_GLB_DCDC_SLP_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A8) +#define ANA_REG_GLB_DCDC_SLP_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00AC) +#define ANA_REG_GLB_DCDC_SLP_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B0) +#define ANA_REG_GLB_DCDC_SLP_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B4) +#define ANA_REG_GLB_DCDC_SLP_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B8) +#define ANA_REG_GLB_DCDC_SLP_CTRL5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00BC) +#define ANA_REG_GLB_PWR_SEL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C0) +#define ANA_REG_GLB_PWR_XTL_EN0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C4) +#define ANA_REG_GLB_PWR_XTL_EN1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C8) +#define ANA_REG_GLB_PWR_XTL_EN2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00CC) +#define ANA_REG_GLB_PWR_XTL_EN3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D0) +#define ANA_REG_GLB_32KLESS_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D4) +#define ANA_REG_GLB_32KLESS_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D8) +#define ANA_REG_GLB_32KLESS_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00DC) +#define ANA_REG_GLB_32KLESS_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E0) +#define ANA_REG_GLB_AUXAD_CTL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E4) +#define ANA_REG_GLB_XTL_WAIT_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E8) +#define ANA_REG_GLB_RGB_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00EC) +#define ANA_REG_GLB_WHTLED_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F0) +#define ANA_REG_GLB_KPLED_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F4) +#define ANA_REG_GLB_VIBR_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F8) +#define ANA_REG_GLB_AUDIO_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00FC) +#define ANA_REG_GLB_AUDIO_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0100) +#define ANA_REG_GLB_CHGR_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0104) +#define ANA_REG_GLB_CHGR_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0108) +#define ANA_REG_GLB_CHGR_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x010C) +#define ANA_REG_GLB_CHGR_DET_FGU_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0110) +#define ANA_REG_GLB_CHGR_STATUS SCI_ADDR(ANA_REGS_GLB_BASE, 0x0114) +#define ANA_REG_GLB_MIXED_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0118) +#define ANA_REG_GLB_MIXED_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x011C) +#define ANA_REG_GLB_SWRST_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0120) +#define ANA_REG_GLB_POR_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x0124) +#define ANA_REG_GLB_WDG_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x0128) +#define ANA_REG_GLB_POR_PIN_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x012C) +#define ANA_REG_GLB_POR_SRC_FLAG SCI_ADDR(ANA_REGS_GLB_BASE, 0x0130) +#define ANA_REG_GLB_POR_7S_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0134) +#define ANA_REG_GLB_HWRST_RTC SCI_ADDR(ANA_REGS_GLB_BASE, 0x0138) +#define ANA_REG_GLB_CHIP_ID_LOW SCI_ADDR(ANA_REGS_GLB_BASE, 0x013C) +#define ANA_REG_GLB_CHIP_ID_HIGH SCI_ADDR(ANA_REGS_GLB_BASE, 0x0140) +#define ANA_REG_GLB_ARM_MF_REG SCI_ADDR(ANA_REGS_GLB_BASE, 0x0144) +#define ANA_REG_GLB_ARCH_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0148) +#define ANA_REG_GLB_MCU_WR_PROT_VALUE SCI_ADDR(ANA_REGS_GLB_BASE, 0x014C) +#define ANA_REG_GLB_PWR_WR_PROT_VALUE SCI_ADDR(ANA_REGS_GLB_BASE, 0x0150) +#define ANA_REG_GLB_SMPL_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0154) +#define ANA_REG_GLB_SMPL_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0158) +#define ANA_REG_GLB_RTC_RST0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x015C) +#define ANA_REG_GLB_RTC_RST1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0160) +#define ANA_REG_GLB_RTC_RST2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0164) +#define ANA_REG_GLB_LDO_SHPT_PD1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0188) +#define ANA_REG_GLB_LDO_SHPT_PD2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x018C) +#define ANA_REG_GLB_BATDET_CUR_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0190) +#define ANA_REG_GLB_RTC_CLK_STOP SCI_ADDR(ANA_REGS_GLB_BASE, 0x0194) +#define ANA_REG_GLB_VBAT_DROP_CNT SCI_ADDR(ANA_REGS_GLB_BASE, 0x0198) +#define ANA_REG_GLB_DCDC_DISCHRG SCI_ADDR(ANA_REGS_GLB_BASE, 0x019C) +#define ANA_REG_GLB_DCDC_CORE_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0200) +#define ANA_REG_GLB_DCDC_ARM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0204) +#define ANA_REG_GLB_DCDC_MEM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0208) +#define ANA_REG_GLB_DCDC_GEN_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x020C) +#define ANA_REG_GLB_DCDC_WPA_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0210) +#define ANA_REG_GLB_DCDC_WPA_DCM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0214) +#define ANA_REG_GLB_DCDC_CON_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0218) +#define ANA_REG_GLB_DCDC_RF_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x021C) + +/* bits definitions for register ANA_REG_GLB_ARM_MODULE_EN */ +#define BIT_ANA_IMPD_ADC_EN ( BIT(12) ) +#define BIT_ANA_THM_EN ( BIT(11) ) +#define BIT_ANA_BLTC_EN ( BIT(10) ) +#define BIT_ANA_PINREG_EN ( BIT(9) ) +#define BIT_ANA_FGU_EN ( BIT(8) ) +#define BIT_ANA_EFS_EN ( BIT(7) ) +#define BIT_ANA_ADC_EN ( BIT(6) ) +#define BIT_ANA_HDT_EN ( BIT(5) ) +#define BIT_ANA_AUD_EN ( BIT(4) ) +#define BIT_ANA_EIC_EN ( BIT(3) ) +#define BIT_ANA_WDG_EN ( BIT(2) ) +#define BIT_ANA_RTC_EN ( BIT(1) ) +#define BIT_ANA_CAL_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_ARM_CLK_EN */ +#define BIT_CLK_IMPD_ADC_EN ( BIT(10) ) +#define BIT_CLK_AUXAD_EN ( BIT(9) ) +#define BIT_CLK_AUXADC_EN ( BIT(8) ) +#define BITS_CLK_CAL_SRC_SEL(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BIT_CLK_CAL_EN ( BIT(5) ) +#define BIT_CLK_AUD_HID_EN ( BIT(4) ) +#define BIT_CLK_AUD_HBD_EN ( BIT(3) ) +#define BIT_CLK_AUD_LOOP_EN ( BIT(2) ) +#define BIT_CLK_AUD_6P5M_EN ( BIT(1) ) +#define BIT_CLK_AUDIF_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_RTC_CLK_EN */ +#define BIT_RTC_EFS_EN ( BIT(12) ) +#define BIT_RTC_THMA_AUTO_EN ( BIT(11) ) +#define BIT_RTC_THMA_EN ( BIT(10) ) +#define BIT_RTC_THM_EN ( BIT(9) ) +#define BIT_RTC_BLTC_EN ( BIT(8) ) +#define BIT_RTC_FGU_EN ( BIT(7) ) +#define BIT_RTC_FGUA_EN ( BIT(6) ) +#define BIT_RTC_VIBR_EN ( BIT(5) ) +#define BIT_RTC_AUD_EN ( BIT(4) ) +#define BIT_RTC_EIC_EN ( BIT(3) ) +#define BIT_RTC_WDG_EN ( BIT(2) ) +#define BIT_RTC_RTC_EN ( BIT(1) ) +#define BIT_RTC_ARCH_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_ARM_RST */ +#define BIT_ANA_THMA_SOFT_RST ( BIT(15) ) +#define BIT_ANA_THM_SOFT_RST ( BIT(14) ) +#define BIT_ANA_BLTC_SOFT_RST ( BIT(13) ) +#define BIT_ANA_AUD_32K_SOFT_RST ( BIT(12) ) +#define BIT_ANA_AUDTX_SOFT_RST ( BIT(11) ) +#define BIT_ANA_AUDRX_SOFT_RST ( BIT(10) ) +#define BIT_ANA_AUD_SOFT_RST ( BIT(9) ) +#define BIT_ANA_AUD_HDT_SOFT_RST ( BIT(8) ) +#define BIT_ANA_EFS_SOFT_RST ( BIT(7) ) +#define BIT_ANA_ADC_SOFT_RST ( BIT(6) ) +#define BIT_ANA_PWM0_SOFT_RST ( BIT(5) ) +#define BIT_ANA_FGU_SOFT_RST ( BIT(4) ) +#define BIT_ANA_EIC_SOFT_RST ( BIT(3) ) +#define BIT_ANA_WDG_SOFT_RST ( BIT(2) ) +#define BIT_ANA_RTC_SOFT_RST ( BIT(1) ) +#define BIT_ANA_CAL_SOFT_RST ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_DCDC_PD */ +#define BIT_LDO_EMM_PD ( BIT(15) ) +#define BIT_DCDC_TOPCLK6M_PD ( BIT(14) ) +#define BIT_DCDC_RF_PD ( BIT(13) ) +#define BIT_DCDC_GEN_PD ( BIT(12) ) +#define BIT_DCDC_MEM_PD ( BIT(11) ) +#define BIT_DCDC_ARM_PD ( BIT(10) ) +#define BIT_DCDC_CORE_PD ( BIT(9) ) +#define BIT_LDO_RF0_PD ( BIT(8) ) +#define BIT_LDO_EMMCCORE_PD ( BIT(7) ) +#define BIT_LDO_GEN1_PD ( BIT(6) ) +#define BIT_LDO_DCXO_PD ( BIT(5) ) +#define BIT_LDO_GEN0_PD ( BIT(4) ) +#define BIT_LDO_VDD25_PD ( BIT(3) ) +#define BIT_LDO_VDD28_PD ( BIT(2) ) +#define BIT_LDO_VDD18_PD ( BIT(1) ) +#define BIT_BG_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_PD_CTRL */ +#define BIT_LDO_LPREF_PD_SW ( BIT(15) ) +#define BIT_DCDC_WPA_PD ( BIT(14) ) +#define BIT_DCDC_CON_PD ( BIT(13) ) +#define BIT_LDO_WIFIPA_PD ( BIT(11) ) +#define BIT_LDO_SDCORE_PD ( BIT(10) ) +#define BIT_LDO_USB_PD ( BIT(8) ) +#define BIT_LDO_CAMMOT_PD ( BIT(7) ) +#define BIT_LDO_CAMIO_PD ( BIT(6) ) +#define BIT_LDO_CAMD_PD ( BIT(5) ) +#define BIT_LDO_CAMA_PD ( BIT(4) ) +#define BIT_LDO_SIM2_PD ( BIT(3) ) +#define BIT_LDO_SIM1_PD ( BIT(2) ) +#define BIT_LDO_SIM0_PD ( BIT(1) ) +#define BIT_LDO_SDIO_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL0 */ +#define BITS_LDO_RF0_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_WIFIPA_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL1 */ +#define BITS_LDO_CAMIO_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_CAMD_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL2 */ +#define BITS_LDO_GEN0_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL3 */ +#define BITS_LDO_GEN1_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_VDD28_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL4 */ +#define BITS_LDO_SIM0_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_SDIO_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL5 */ +#define BITS_LDO_SIM2_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_SIM1_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL6 */ +#define BITS_LDO_SDCORE_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_CAMA_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL7 */ +#define BITS_LDO_EMMCCORE_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_CAMMOT_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL8 */ +#define BITS_LDO_DCXO_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_DCXO_LP_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL9 */ +#define BITS_LDO_VDD18_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_USB_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL10 */ +#define BITS_LDO_VDD25_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL11 */ +#define BITS_VBATBK_V(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_LDOB_CAL_SEL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_LDOA_CAL_SEL (_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_LDOD_CAL_SEL(_x_) ( (_x_) << 3 & (BIT(3)|BIT(4)) ) +#define BITS_LDODCDC_CAL_SEL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_LP_CTRL */ +#define BITS_LDOB_LP_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDOA_LP_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDODCDC_LP_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL0 */ +#define BITS_DCDC_CORE_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_CORE_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_CORE_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_CORE_QKRSPS ( BIT(3) ) +#define BIT_DCDC_CORE_PFM ( BIT(2) ) +#define BIT_DCDC_CORE_DCM ( BIT(1) ) +#define BIT_DCDC_CORE_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL1 */ +#define BITS_DCDC_MEM_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_MEM_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_MEM_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_MEM_QKRSPS ( BIT(3) ) +#define BIT_DCDC_MEM_PFM ( BIT(2) ) +#define BIT_DCDC_MEM_DCM ( BIT(1) ) +#define BIT_DCDC_MEM_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL2 */ +#define BITS_DCDC_GEN_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_GEN_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_GEN_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_GEN_QKRSPS ( BIT(3) ) +#define BIT_DCDC_GEN_PFM ( BIT(2) ) +#define BIT_DCDC_GEN_DCM ( BIT(1) ) +#define BIT_DCDC_GEN_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL3 */ +#define BITS_DCDC_ARM_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_ARM_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_ARM_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_ARM_QKRSPS ( BIT(3) ) +#define BIT_DCDC_ARM_PFM ( BIT(2) ) +#define BIT_DCDC_ARM_DCM ( BIT(1) ) +#define BIT_DCDC_ARM_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL4 */ +#define BITS_DCDC_WPA_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_WPA_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_WPA_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_WPA_QKRSPS ( BIT(3) ) +#define BIT_DCDC_WPA_PFM ( BIT(2) ) +#define BIT_DCDC_WPA_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL5 */ +#define BITS_DCDC_RF_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_RF_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_RF_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_RF_QKRSPS ( BIT(3) ) +#define BIT_DCDC_RF_PFM ( BIT(2) ) +#define BIT_DCDC_RF_DCM ( BIT(1) ) +#define BIT_DCDC_RF_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL6 */ +#define BITS_DCDC_CON_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_CON_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_CON_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_CON_QKRSPS ( BIT(3) ) +#define BIT_DCDC_CON_PFM ( BIT(2) ) +#define BIT_DCDC_CON_DCM ( BIT(1) ) +#define BIT_DCDC_CON_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL7 */ +#define BITS_DCDC_MEM_CF(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_DCDC_MEM_PFMAD(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_DCDC_MEM_CL_CTRL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_DCDC_CORE_DUALSEL ( BIT(7) ) +#define BIT_DCDC_CORE_MERGEEN ( BIT(6) ) +#define BITS_DCDC_CORE_CF(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_DCDC_CORE_PFMAD(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DCDC_CORE_CL_CTRL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL8 */ +#define BIT_DCDC_ARM_DUALSEL ( BIT(15) ) +#define BIT_DCDC_ARM_MERGEEN ( BIT(14) ) +#define BITS_DCDC_ARM_CF(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_DCDC_ARM_PFMAD(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_DCDC_ARM_CL_CTRL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_DCDC_GEN_CF(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_DCDC_GEN_PFMAD(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DCDC_GEN_CL_CTRL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL9 */ +#define BIT_DCDC_CON_MERGEEN ( BIT(14) ) +#define BITS_DCDC_CON_CF(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_DCDC_CON_PFMAD(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_DCDC_CON_CL_CTRL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_DCDC_RF_MERGEEN ( BIT(6) ) +#define BITS_DCDC_RF_CF(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_DCDC_RF_PFMAD(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DCDC_RF_CL_CTRL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL10 */ +#define BIT_DCDC_WPA_BPOUT_SOFTW ( BIT(15) ) +#define BITS_DCDC_WPA_VBAT_DIV(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BIT_DCDC_WPA_BPEN ( BIT(11) ) +#define BIT_DCDC_WPA_BPMODE ( BIT(10) ) +#define BIT_DCDC_WPA_DEGEN ( BIT(9) ) +#define BIT_DCDC_WPA_APTEN ( BIT(8) ) +#define BITS_DCDC_WPA_DEBC_SEL(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_DCDC_WPA_CF(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_DCDC_WPA_PFMAD(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DCDC_WPA_CL_CTRL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL11 */ +#define BIT_DCDC_3MCLKCAL_EN ( BIT(13) ) +#define BIT_DCDC_2MCLKCAL_EN ( BIT(12) ) +#define BITS_DCDC_6MFRECAL_SW(_x_) ( (_x_) << 7 & (BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DCDC_4MFRECAL_SW(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_DCDC_CLK_SP_SEL ( BIT(1) ) +#define BIT_DCDC_CLK_SP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL12 */ +#define BIT_DCDC_CORE_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_CORE_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_CORE_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_CORE_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_ARM_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_ARM_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_ARM_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_ARM_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL13 */ +#define BIT_DCDC_MEM_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_MEM_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_MEM_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_MEM_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_GEN_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_GEN_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_GEN_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_GEN_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL14 */ +#define BIT_DCDC_WPA_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_WPA_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_WPA_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_WPA_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_RF_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_RF_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_RF_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_RF_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL15 */ +#define BITS_DCDC_CAL_SEL(_x_) ( (_x_) << 13 & (BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_DCDC_CON_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_CON_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_CON_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_CON_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_SLP_WAIT_DCDCARM */ +#define BITS_SLP_IN_WAIT_DCDCARM(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_SLP_OUT_WAIT_DCDCARM(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL0 */ +#define BIT_SLP_IO_EN ( BIT(15) ) +#define BIT_SLP_DCDCRF_PD_EN ( BIT(13) ) +#define BIT_SLP_DCDCCON_PD_EN ( BIT(12) ) +#define BIT_SLP_DCDCGEN_PD_EN ( BIT(11) ) +#define BIT_SLP_DCDCWPA_PD_EN ( BIT(10) ) +#define BIT_SLP_DCDCARM_PD_EN ( BIT(9) ) +#define BIT_SLP_LDOVDD25_PD_EN ( BIT(8) ) +#define BIT_SLP_LDORF0_PD_EN ( BIT(7) ) +#define BIT_SLP_LDOEMMCCORE_PD_EN ( BIT(6) ) +#define BIT_SLP_LDOGEN0_PD_EN ( BIT(5) ) +#define BIT_SLP_LDODCXO_PD_EN ( BIT(4) ) +#define BIT_SLP_LDOGEN1_PD_EN ( BIT(3) ) +#define BIT_SLP_LDOWIFIPA_PD_EN ( BIT(2) ) +#define BIT_SLP_LDOVDD28_PD_EN ( BIT(1) ) +#define BIT_SLP_LDOVDD18_PD_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL1 */ +#define BIT_SLP_LDO_PD_EN ( BIT(15) ) +#define BIT_SLP_LDOLPREF_PD_EN ( BIT(14) ) +#define BIT_SLP_LDOSDCORE_PD_EN ( BIT(9) ) +#define BIT_SLP_LDOUSB_PD_EN ( BIT(8) ) +#define BIT_SLP_LDOCAMMOT_PD_EN ( BIT(7) ) +#define BIT_SLP_LDOCAMIO_PD_EN ( BIT(6) ) +#define BIT_SLP_LDOCAMD_PD_EN ( BIT(5) ) +#define BIT_SLP_LDOCAMA_PD_EN ( BIT(4) ) +#define BIT_SLP_LDOSIM2_PD_EN ( BIT(3) ) +#define BIT_SLP_LDOSIM1_PD_EN ( BIT(2) ) +#define BIT_SLP_LDOSIM0_PD_EN ( BIT(1) ) +#define BIT_SLP_LDOSDIO_PD_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL2 */ +#define BIT_SLP_DCDCRF_LP_EN ( BIT(14) ) +#define BIT_SLP_DCDCCON_LP_EN ( BIT(13) ) +#define BIT_SLP_DCDCCORE_LP_EN ( BIT(12) ) +#define BIT_SLP_DCDCMEM_LP_EN ( BIT(11) ) +#define BIT_SLP_DCDCARM_LP_EN ( BIT(10) ) +#define BIT_SLP_DCDCGEN_LP_EN ( BIT(9) ) +#define BIT_SLP_DCDCWPA_LP_EN ( BIT(8) ) +#define BIT_SLP_LDORF0_LP_EN ( BIT(7) ) +#define BIT_SLP_LDOEMMCCORE_LP_EN ( BIT(6) ) +#define BIT_SLP_LDOGEN0_LP_EN ( BIT(5) ) +#define BIT_SLP_LDODCXO_LP_EN ( BIT(4) ) +#define BIT_SLP_LDOGEN1_LP_EN ( BIT(3) ) +#define BIT_SLP_LDOWIFIPA_LP_EN ( BIT(2) ) +#define BIT_SLP_LDOVDD28_LP_EN ( BIT(1) ) +#define BIT_SLP_LDOVDD18_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL3 */ +#define BIT_SLP_BG_LP_EN ( BIT(15) ) +#define BIT_LDOVDD25_LP_EN_SW ( BIT(14) ) +#define BIT_LDOSDCORE_LP_EN_SW ( BIT(13) ) +#define BIT_LDOUSB_LP_EN_SW ( BIT(12) ) +#define BIT_SLP_LDOVDD25_LP_EN ( BIT(10) ) +#define BIT_SLP_LDOSDCORE_LP_EN ( BIT(9) ) +#define BIT_SLP_LDOUSB_LP_EN ( BIT(8) ) +#define BIT_SLP_LDOCAMMOT_LP_EN ( BIT(7) ) +#define BIT_SLP_LDOCAMIO_LP_EN ( BIT(6) ) +#define BIT_SLP_LDOCAMD_LP_EN ( BIT(5) ) +#define BIT_SLP_LDOCAMA_LP_EN ( BIT(4) ) +#define BIT_SLP_LDOSIM2_LP_EN ( BIT(3) ) +#define BIT_SLP_LDOSIM1_LP_EN ( BIT(2) ) +#define BIT_SLP_LDOSIM0_LP_EN ( BIT(1) ) +#define BIT_SLP_LDOSDIO_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL4 */ +#define BIT_LDOCAMIO_LP_EN_SW ( BIT(15) ) +#define BIT_LDOCAMMOT_LP_EN_SW ( BIT(14) ) +#define BIT_LDOCAMD_LP_EN_SW ( BIT(13) ) +#define BIT_LDOCAMA_LP_EN_SW ( BIT(12) ) +#define BIT_LDOSIM2_LP_EN_SW ( BIT(11) ) +#define BIT_LDOSIM1_LP_EN_SW ( BIT(10) ) +#define BIT_LDOSIM0_LP_EN_SW ( BIT(9) ) +#define BIT_LDOSDIO_LP_EN_SW ( BIT(8) ) +#define BIT_LDORF0_LP_EN_SW ( BIT(7) ) +#define BIT_LDOEMMCCORE_LP_EN_SW ( BIT(6) ) +#define BIT_LDOGEN0_LP_EN_SW ( BIT(5) ) +#define BIT_LDODCXO_LP_EN_SW ( BIT(4) ) +#define BIT_LDOGEN1_LP_EN_SW ( BIT(3) ) +#define BIT_LDOWIFIPA_LP_EN_SW ( BIT(2) ) +#define BIT_LDOVDD28_LP_EN_SW ( BIT(1) ) +#define BIT_LDOVDD18_LP_EN_SW ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_AUD_SLP_CTRL */ +#define BIT_SLP_AUD_PMUR1_PD_EN ( BIT(14) ) +#define BIT_SLP_AUD_PA_SW_PD_EN ( BIT(13) ) +#define BIT_SLP_AUD_PA_LDO_PD_EN ( BIT(12) ) +#define BIT_SLP_AUD_PA_PD_EN ( BIT(11) ) +#define BIT_SLP_AUD_OVP_PD_PD_EN ( BIT(10) ) +#define BIT_SLP_AUD_OVP_LDO_PD_EN ( BIT(9) ) +#define BIT_SLP_AUD_LDOCG_PD_PD_EN ( BIT(8) ) +#define BIT_SLP_AUD_VB_PD_EN ( BIT(7) ) +#define BIT_SLP_AUD_VBO_PD_EN ( BIT(6) ) +#define BIT_SLP_AUD_HEADMICBIAS_PD_EN ( BIT(5) ) +#define BIT_SLP_AUD_HEADMIC_SLEEP_PD_EN ( BIT(4) ) +#define BIT_SLP_AUD_PLGPD_PD_EN ( BIT(3) ) +#define BIT_SLP_AUD_VB_NLEAK_PD ( BIT(2) ) +#define BITS_SLP_AUD_PMUR0_PD_EN(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL0 */ +#define BITS_SLP_DCDCCORE_VOL_DROP_CNT(_x_)( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_PWR_OFF_SEQ_EN ( BIT(2) ) +#define BIT_DCDC_CORE_SLP_OUT_STEP_EN ( BIT(1) ) +#define BIT_DCDC_CORE_SLP_IN_STEP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL1 */ +#define BITS_DCDC_CORE_CAL_DS_SW(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CTRL_DS_SW(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL2 */ +#define BITS_DCDC_CORE_CTRL_SLP_STEP3(_x_)( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_DCDC_CORE_CTRL_SLP_STEP2(_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CTRL_SLP_STEP1(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL3 */ +#define BITS_DCDC_CORE_CTRL_SLP_STEP5(_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CTRL_SLP_STEP4(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL4 */ +#define BITS_DCDC_CORE_CAL_SLP_STEP3(_x_)( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_DCDC_CORE_CAL_SLP_STEP2(_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CAL_SLP_STEP1(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL5 */ +#define BITS_DCDC_CORE_CAL_SLP_STEP5(_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CAL_SLP_STEP4(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SEL */ +#define BIT_LDO_GEN0_SW_SEL ( BIT(13) ) +#define BIT_LDO_GEN1_SW_SEL ( BIT(12) ) +#define BIT_LDO_RF0_SW_SEL ( BIT(11) ) +#define BIT_LDO_VDD18_SW_SEL ( BIT(10) ) +#define BIT_LDO_VDD28_SW_SEL ( BIT(9) ) +#define BIT_LDO_DCXO_SW_SEL ( BIT(8) ) +#define BIT_LDO_EMMCCORE_SW_SEL ( BIT(7) ) +#define BIT_LDO_VDD25_SW_SEL ( BIT(6) ) +#define BIT_DCDC_RF_SW_SEL ( BIT(5) ) +#define BIT_DCDC_GEN_SW_SEL ( BIT(4) ) +#define BIT_DCDC_MEM_SW_SEL ( BIT(3) ) +#define BIT_DCDC_ARM_SW_SEL ( BIT(2) ) +#define BIT_DCDC_CORE_SLP_SW_SEL ( BIT(1) ) +#define BIT_DCDC_CORE_NOR_SW_SEL ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN0 */ +#define BIT_LDO_XTL_EN ( BIT(15) ) +#define BIT_LDO_GEN0_EXT_XTL0_EN ( BIT(14) ) +#define BIT_LDO_GEN0_XTL1_EN ( BIT(13) ) +#define BIT_LDO_GEN0_XTL0_EN ( BIT(12) ) +#define BIT_LDO_GEN1_EXT_XTL0_EN ( BIT(11) ) +#define BIT_LDO_GEN1_XTL1_EN ( BIT(10) ) +#define BIT_LDO_GEN1_XTL0_EN ( BIT(9) ) +#define BIT_LDO_DCXO_EXT_XTL0_EN ( BIT(8) ) +#define BIT_LDO_DCXO_XTL1_EN ( BIT(7) ) +#define BIT_LDO_DCXO_XTL0_EN ( BIT(6) ) +#define BIT_LDO_VDD18_EXT_XTL0_EN ( BIT(5) ) +#define BIT_LDO_VDD18_XTL1_EN ( BIT(4) ) +#define BIT_LDO_VDD18_XTL0_EN ( BIT(3) ) +#define BIT_LDO_VDD28_EXT_XTL0_EN ( BIT(2) ) +#define BIT_LDO_VDD28_XTL1_EN ( BIT(1) ) +#define BIT_LDO_VDD28_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN1 */ +#define BIT_LDO_RF0_EXT_XTL0_EN ( BIT(14) ) +#define BIT_LDO_RF0_XTL1_EN ( BIT(13) ) +#define BIT_LDO_RF0_XTL0_EN ( BIT(12) ) +#define BIT_LDO_WIFIPA_EXT_XTL0_EN ( BIT(11) ) +#define BIT_LDO_WIFIPA_XTL1_EN ( BIT(10) ) +#define BIT_LDO_WIFIPA_XTL0_EN ( BIT(9) ) +#define BIT_LDO_SIM2_EXT_XTL0_EN ( BIT(8) ) +#define BIT_LDO_SIM2_XTL1_EN ( BIT(7) ) +#define BIT_LDO_SIM2_XTL0_EN ( BIT(6) ) +#define BIT_LDO_SIM1_EXT_XTL0_EN ( BIT(5) ) +#define BIT_LDO_SIM1_XTL1_EN ( BIT(4) ) +#define BIT_LDO_SIM1_XTL0_EN ( BIT(3) ) +#define BIT_LDO_SIM0_EXT_XTL0_EN ( BIT(2) ) +#define BIT_LDO_SIM0_XTL1_EN ( BIT(1) ) +#define BIT_LDO_SIM0_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN2 */ +#define BIT_LDO_VDD25_EXT_XTL0_EN ( BIT(11) ) +#define BIT_LDO_VDD25_XTL1_EN ( BIT(10) ) +#define BIT_LDO_VDD25_XTL0_EN ( BIT(9) ) +#define BIT_DCDC_RF_EXT_XTL0_EN ( BIT(8) ) +#define BIT_DCDC_RF_XTL1_EN ( BIT(7) ) +#define BIT_DCDC_RF_XTL0_EN ( BIT(6) ) +#define BIT_XO_EXT_XTL0_EN ( BIT(5) ) +#define BIT_XO_XTL1_EN ( BIT(4) ) +#define BIT_XO_XTL0_EN ( BIT(3) ) +#define BIT_BG_EXT_XTL0_EN ( BIT(2) ) +#define BIT_BG_XTL1_EN ( BIT(1) ) +#define BIT_BG_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN3 */ +#define BIT_DCDC_CON_EXT_XTL0_EN ( BIT(14) ) +#define BIT_DCDC_CON_XTL1_EN ( BIT(13) ) +#define BIT_DCDC_CON_XTL0_EN ( BIT(12) ) +#define BIT_DCDC_WPA_EXT_XTL0_EN ( BIT(11) ) +#define BIT_DCDC_WPA_XTL1_EN ( BIT(10) ) +#define BIT_DCDC_WPA_XTL0_EN ( BIT(9) ) +#define BIT_DCDC_MEM_EXT_XTL0_EN ( BIT(8) ) +#define BIT_DCDC_MEM_XTL1_EN ( BIT(7) ) +#define BIT_DCDC_MEM_XTL0_EN ( BIT(6) ) +#define BIT_DCDC_GEN_EXT_XTL0_EN ( BIT(5) ) +#define BIT_DCDC_GEN_XTL1_EN ( BIT(4) ) +#define BIT_DCDC_GEN_XTL0_EN ( BIT(3) ) +#define BIT_DCDC_CORE_EXT_XTL0_EN ( BIT(2) ) +#define BIT_DCDC_CORE_XTL1_EN ( BIT(1) ) +#define BIT_DCDC_CORE_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_32KLESS_CTRL0 */ +#define BIT_RC_MODE_WR_ACK_FLAG ( BIT(14) ) +#define BIT_XO_LOW_CUR_FLAG ( BIT(13) ) +#define BIT_XO_LOW_CUR_FRC_RTCSET ( BIT(12) ) +#define BIT_XO_LOW_CUR_FRC_RTCCLR ( BIT(11) ) +#define BIT_RC_MODE_WR_ACK_FLAG_CLR ( BIT(10) ) +#define BIT_XO_LOW_CUR_FLAG_CLR ( BIT(9) ) +#define BIT_XO_LOW_CUR_CNT_CLR ( BIT(8) ) +#define BIT_LDO_DCXO_LP_PD_RTCSET ( BIT(7) ) +#define BIT_LDO_DCXO_LP_PD_RTCCLR ( BIT(6) ) +#define BIT_SLP_XO_LOW_CUR_EN ( BIT(5) ) +#define BIT_XO_LOW_CUR_EN ( BIT(3) ) +#define BIT_EXT_32K_PD ( BIT(2) ) +#define BIT_RC_32K_SEL ( BIT(1) ) +#define BIT_RC_32K_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_32KLESS_CTRL1 */ +#define BITS_RC_MODE(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_32KLESS_CTRL2 */ +#define BITS_XO_LOW_CUR_CNT_LOW(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_32KLESS_CTRL3 */ +#define BITS_XO_LOW_CUR_CNT_HIGH(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_AUXAD_CTL */ +#define BIT_AUXAD_CURRENTSEN_EN ( BIT(6) ) +#define BIT_AUXAD_CURRENTSEL ( BIT(5) ) +#define BITS_AUXAD_CURRENT_IBS(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_XTL_WAIT_CTRL */ +#define BIT_SLP_XTLBUF_PD_EN ( BIT(9) ) +#define BIT_XTL_EN ( BIT(8) ) +#define BITS_XTL_WAIT(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_RGB_CTRL */ +#define BIT_RTC_PWM0_EN ( BIT(15) ) +#define BIT_PWM0_EN ( BIT(14) ) +#define BIT_IB_REX_EN ( BIT(12) ) +#define BIT_IB_TRIM_EM_SEL ( BIT(11) ) +#define BITS_RGB_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) ) +#define BIT_SLP_RGB_PD_EN ( BIT(2) ) +#define BIT_RGB_PD_HW_EN ( BIT(1) ) +#define BIT_RGB_PD_SW ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_WHTLED_CTRL */ +#define BITS_IB_TRIM(_x_) ( (_x_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_WHTLED_SERIES_EN ( BIT(8) ) +#define BIT_WHTLED_PD_SEL ( BIT(7) ) +#define BITS_WHTLED_V(_x_) ( (_x_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_WHTLED_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_KPLED_CTRL */ +#define BITS_KPLED_V(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_KPLED_PD ( BIT(11) ) +#define BIT_KPLED_PULLDOWN_EN ( BIT(10) ) +#define BIT_SLP_LDOKPLED_PD_EN ( BIT(9) ) +#define BIT_LDO_KPLED_PD ( BIT(8) ) +#define BITS_LDO_KPLED_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_VIBR_CTRL0 */ +#define BITS_CUR_DRV_CAL_SEL(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BIT_VIBR_PULLDOWN_EN ( BIT(11) ) +#define BIT_VIBR_PULLUP_EN ( BIT(10) ) +#define BIT_SLP_LDOVIBR_PD_EN ( BIT(9) ) +#define BIT_LDO_VIBR_PD ( BIT(8) ) +#define BITS_LDO_VIBR_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_AUDIO_CTRL0 */ +#define BIT_AUD_SLP_APP_RST_EN ( BIT(15) ) +#define BITS_CLK_AUD_HBD_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_CLK_AUD_LOOP_INV_EN ( BIT(4) ) +#define BIT_CLK_AUDIF_TX_INV_EN ( BIT(3) ) +#define BIT_CLK_AUDIF_RX_INV_EN ( BIT(2) ) +#define BIT_CLK_AUD_6P5M_TX_INV_EN ( BIT(1) ) +#define BIT_CLK_AUD_6P5M_RX_INV_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_AUDIO_CTRL1 */ +#define BIT_IMPD_ADC_SOFT_RST ( BIT(7) ) +#define BIT_HEAD_INSERT_EIC_EN ( BIT(6) ) +#define BIT_AUDIO_CHP_CLK_DIV_EN ( BIT(5) ) +#define BITS_AUDIO_CHP_CLK_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL0 */ +#define BIT_CHGLDO_DIS ( BIT(15) ) +#define BITS_CHGR_CV_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CHGR_END_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BIT_CHGR_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL1 */ +#define BITS_CHGR_CC_I(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_VBAT_OVP_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_VCHG_OVP_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL2 */ +#define BIT_CHGR_INT_EN ( BIT(15) ) +#define BIT_CHGR_DRV ( BIT(7) ) +#define BIT_CHGR_OSC ( BIT(6) ) +#define BITS_CHGR_DPM(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CHGR_ITERM(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BIT_CHGR_CC_EN ( BIT(1) ) +#define BIT_RECHG ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_DET_FGU_CTRL */ +#define BIT_FGUA_SOFT_RST ( BIT(13) ) +#define BIT_LDO_FGU_PD ( BIT(12) ) +#define BIT_SD_CHOP_CAP_EN ( BIT(8) ) +#define BITS_SD_CLK_P(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BIT_SD_DCOFFSET_EN ( BIT(5) ) +#define BIT_SD_CHOP_EN ( BIT(4) ) +#define BIT_DP_DM_AUX_EN ( BIT(1) ) +#define BIT_DP_DM_SW_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_STATUS */ +#define BIT_CHG_DET_DONE ( BIT(11) ) +#define BIT_DP_LOW ( BIT(10) ) +#define BIT_DCP_DET ( BIT(9) ) +#define BIT_CHG_DET ( BIT(8) ) +#define BIT_SDP_INT ( BIT(7) ) +#define BIT_DCP_INT ( BIT(6) ) +#define BIT_CDP_INT ( BIT(5) ) +#define BIT_CHGR_CV_STATUS ( BIT(4) ) +#define BIT_CHGR_ON ( BIT(3) ) +#define BIT_CHGR_INT ( BIT(2) ) +#define BIT_VBAT_OVI ( BIT(1) ) +#define BIT_VCHG_OVI ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_MIXED_CTRL0 */ +#define BIT_PTEST_PD_RTCSET ( BIT(15) ) +#define BIT_DCDC_V_CTRL_MODE ( BIT(14) ) +#define BIT_LDO_RAMP_EN ( BIT(13) ) +#define BIT_BG_LP_EN ( BIT(12) ) +#define BITS_VBAT_CRASH_V(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BIT_OVLO_EN ( BIT(9) ) +#define BITS_OVLO_CAL(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_OVLO_V(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_OVLO_T(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_MIXED_CTRL1 */ +#define BITS_XOSC32K_CTL(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_BATON_T(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BIT_BATDET_LDO_SEL ( BIT(9) ) +#define BIT_THM_CHIP_PD_FLAG ( BIT(8) ) +#define BIT_THM_CHIP_PD_FLAG_CLR ( BIT(7) ) +#define BITS_THM_CAL_SEL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)) ) +#define BIT_THM_AUTO_PD_EN ( BIT(4) ) +#define BIT_ALL_GPI_DEB ( BIT(3) ) +#define BIT_GPI_DEBUG_EN ( BIT(2) ) +#define BIT_ALL_INT_DEB ( BIT(1) ) +#define BIT_INT_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_SWRST_CTRL */ +#define BIT_POR_RTC_PD ( BIT(15) ) +#define BITS_POR_RTC_I(_x_) ( (_x_) << 13 & (BIT(13)|BIT(14)) ) +#define BIT_SW_RST_GEN1_PD_EN ( BIT(12) ) +#define BIT_SW_RST_GEN0_PD_EN ( BIT(11) ) +#define BIT_EXT_RSTN_PD_EN ( BIT(10) ) +#define BIT_PB_7S_RST_PD_EN ( BIT(9) ) +#define BIT_SW_RST_EMMCCORE_PD_EN ( BIT(8) ) +#define BIT_KEY2_7S_RST_EN ( BIT(7) ) +#define BIT_WDG_RST_PD_EN ( BIT(6) ) +#define BITS_SW_RST_PD_THRESHOLD(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register ANA_REG_GLB_POR_RST_MONITOR */ +#define BITS_POR_RST_MONITOR(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_WDG_RST_MONITOR */ +#define BITS_WDG_RST_MONITOR(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_POR_PIN_RST_MONITOR */ +#define BITS_POR_PIN_RST_MONITOR(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_POR_SRC_FLAG */ +#define BIT_POR_SW_FORCE_ON ( BIT(15) ) +#define BITS_POR_SRC_FLAG(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_POR_7S_CTRL */ +#define BIT_PBINT_7S_FLAG_CLR ( BIT(15) ) +#define BIT_EXT_RSTN_FLAG_CLR ( BIT(14) ) +#define BIT_CHGR_INT_FLAG_CLR ( BIT(13) ) +#define BIT_PBINT2_FLAG_CLR ( BIT(12) ) +#define BIT_PBINT_FLAG_CLR ( BIT(11) ) +#define BIT_PBINT_7S_RST_SWMODE ( BIT(8) ) +#define BITS_PBINT_7S_RST_THRESHOLD(_x_)( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_PBINT_7S_AUTO_ON_EN ( BIT(2) ) +#define BIT_PBINT_7S_RST_DISABLE ( BIT(1) ) +#define BIT_PBINT_7S_RST_MODE ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_HWRST_RTC */ +#define BITS_HWRST_RTC_REG_STS(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_HWRST_RTC_REG_SET(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_CHIP_ID_LOW */ +#define BITS_CHIP_ID_LOW(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_CHIP_ID_HIGH */ +#define BITS_CHIP_ID_HIGH(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_ARM_MF_REG */ +#define BITS_ARM_MF_REG(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_ARCH_EN */ +#define BIT_ARCH_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_MCU_WR_PROT_VALUE */ +#define BIT_MCU_WR_PROT ( BIT(15) ) +#define BITS_MCU_WR_PROT_VALUE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_PWR_WR_PROT_VALUE */ +#define BIT_PWR_WR_PROT ( BIT(15) ) +#define BITS_PWR_WR_PROT_VALUE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_SMPL_CTRL0 */ +#define BITS_SMPL_MODE(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_SMPL_CTRL1 */ +#define BIT_SMPL_PWR_ON_FLAG ( BIT(15) ) +#define BIT_SMPL_MODE_WR_ACK_FLAG ( BIT(14) ) +#define BIT_SMPL_PWR_ON_FLAG_CLR ( BIT(13) ) +#define BIT_SMPL_MODE_WR_ACK_FLAG_CLR ( BIT(12) ) +#define BIT_SMPL_PWR_ON_SET ( BIT(11) ) +#define BIT_SMPL_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_RTC_RST0 */ +#define BITS_RTC_CLK_FLAG_SET(_x_) ( (_x_) << 15 & (BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_RTC_RST1 */ +#define BITS_RTC_CLK_FLAG_CLR(_x_) ( (_x_) << 15 & (BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_RTC_RST2 */ +#define BITS_RTC_CLK_FLAG_RTC(_x_) ( (_x_) << 15 & (BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SHPT_PD1 */ +#define BIT_LDO_USB_SHPT_PD ( BIT(12) ) +#define BIT_LDO_DCXO_SHPT_PD ( BIT(11) ) +#define BIT_LDO_WIFIPA_SHPT_PD ( BIT(10) ) +#define BIT_LDO_VDD25_SHPT_PD ( BIT(9) ) +#define BIT_LDO_VDD28_SHPT_PD ( BIT(8) ) +#define BIT_LDO_SDIO_SHPT_PD ( BIT(7) ) +#define BIT_LDO_SDCORE_SHPT_PD ( BIT(6) ) +#define BIT_LDO_EMMCCORE_SHPT_PD ( BIT(5) ) +#define BIT_LDO_SIM2_SHPT_PD ( BIT(4) ) +#define BIT_LDO_SIM1_SHPT_PD ( BIT(3) ) +#define BIT_LDO_SIM0_SHPT_PD ( BIT(2) ) +#define BIT_LDO_CAMMOT_SHPT_PD ( BIT(1) ) +#define BIT_LDO_CAMA_SHPT_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SHPT_PD2 */ +#define BIT_LDO_RF0_SHPT_PD ( BIT(7) ) +#define BIT_LDO_GEN1_SHPT_PD ( BIT(6) ) +#define BIT_LDO_GEN0_SHPT_PD ( BIT(5) ) +#define BIT_LDO_CAMD_SHPT_PD ( BIT(4) ) +#define BIT_LDO_VDD18_SHPT_PD ( BIT(3) ) +#define BIT_LDO_CAMIO_SHPT_PD ( BIT(2) ) +#define BIT_LDO_KPLED_SHPT_PD ( BIT(1) ) +#define BIT_LDO_VIBR_SHPT_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_BATDET_CUR_CTRL */ +#define BIT_BATDET_CUR_EN ( BIT(4) ) +#define BITS_BATDET_CUR_I(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register ANA_REG_GLB_RTC_CLK_STOP */ +#define BIT_RTC_CLK_STOP_FLAG ( BIT(7) ) +#define BITS_RTC_CLK_STOP_THRESHOLD(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) + +/* bits definitions for register ANA_REG_GLB_VBAT_DROP_CNT */ +#define BITS_VBAT_DROP_CNT(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_DISCHRG */ +#define BITS_DCDC_ARM_DISCHRG(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_DCDC_CORE_DISCHRG(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_DCDC_MEM_DISCHRG(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_DCDC_GEN_DISCHRG(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_DCDC_RF_DISCHRG(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_DCDC_CON_DISCHRG(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DCDC_WPA_DISCHRG(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CORE_ADI */ +#define BITS_DCDC_CORE_CTL_SW_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CAL_SW_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_ARM_ADI */ +#define BITS_DCDC_ARM_CTL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_ARM_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_MEM_ADI */ +#define BITS_DCDC_MEM_CTRL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_MEM_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_GEN_ADI */ +#define BITS_DCDC_GEN_CTRL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_GEN_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_WPA_ADI */ +#define BITS_DCDC_WPA_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_WPA_DCM_ADI */ +#define BIT_DCDC_WPA_DCM_ADI ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CON_ADI */ +#define BITS_DCDC_CON_CTRL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CON_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_RF_ADI */ +#define BITS_DCDC_RF_CTRL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_RF_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* vars definitions for controller ANA_REGS_GLB */ + +#endif /* __ANA_REGS_GLB_H__ */ diff --git a/include/soc/sprd/chip_x20/__regs_aon_apb.h b/include/soc/sprd/chip_x20/__regs_aon_apb.h new file mode 100644 index 00000000..e7996dfc --- /dev/null +++ b/include/soc/sprd/chip_x20/__regs_aon_apb.h @@ -0,0 +1,715 @@ +/* the head file modifier: ang 2015-01-12 21:07:29*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_AON_APB_HEADFILE_H__ +#define __H_REGS_AON_APB_HEADFILE_H__ __FILE__ + +#define REGS_AON_APB + +/* registers definitions for AON_APB */ +#define REG_AON_APB_APB_EB0 SCI_ADDR(REGS_AON_APB_BASE, 0x0000)/*AHB_EB0*/ +#define REG_AON_APB_APB_EB1 SCI_ADDR(REGS_AON_APB_BASE, 0x0004)/*AHB_EB1*/ +#define REG_AON_APB_APB_RST0 SCI_ADDR(REGS_AON_APB_BASE, 0x0008)/*AHB_RST0*/ +#define REG_AON_APB_APB_RST1 SCI_ADDR(REGS_AON_APB_BASE, 0x000C)/*AHB_RST1*/ +#define REG_AON_APB_APB_RTC_EB SCI_ADDR(REGS_AON_APB_BASE, 0x0010)/*APB_RTC_EB*/ +#define REG_AON_APB_REC_26MHZ_BUF_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0014)/*REC_26MHZ_BUF_CFG*/ +#define REG_AON_APB_SINDRV_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0018)/*SINDRV_CTRL*/ +#define REG_AON_APB_ADA_SEL_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x001C)/*ADA_SEL_CTRL*/ +#define REG_AON_APB_VBC_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0020)/*VBC_CTRL*/ +#define REG_AON_APB_PWR_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0024)/*PWR_CTRL*/ +#define REG_AON_APB_TS_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0028)/*TS_CFG*/ +#define REG_AON_APB_BOOT_MODE SCI_ADDR(REGS_AON_APB_BASE, 0x002C)/*BOOT_MODE*/ +#define REG_AON_APB_BB_BG_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0030)/*BB_BG_CTRL*/ +#define REG_AON_APB_CP_ARM_JTAG_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0034)/*CP_ARM_JTAG_CTRL*/ +#define REG_AON_APB_PLL_SOFT_CNT_DONE SCI_ADDR(REGS_AON_APB_BASE, 0x0038)/*PLL_SOFT_CNT_DONE*/ +#define REG_AON_APB_DCXO_LC_REG0 SCI_ADDR(REGS_AON_APB_BASE, 0x003C)/*DCXO_LC_REG0*/ +#define REG_AON_APB_DCXO_LC_REG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0040)/*DCXO_LC_REG1*/ +#define REG_AON_APB_DSI_PHY_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0048)/*DSI_PHY_CTRL*/ +#define REG_AON_APB_CSI0_PHY_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x004C)/*CSI0_PHY_CTRL*/ +#define REG_AON_APB_CSI1_PHY_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0050)/*CSI1_PHY_CTRL*/ +#define REG_AON_APB_FUNC_TEST_BOOT_ADDR SCI_ADDR(REGS_AON_APB_BASE, 0x0054)/*FUNC_TEST_BOOT_ADDR*/ +#define REG_AON_APB_RINGOSC_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0058)/*RINGOSC_CTRL*/ +#define REG_AON_APB_RINGOSC_OBS_CNT SCI_ADDR(REGS_AON_APB_BASE, 0x005C)/*RINGOSC_OBS_CNT*/ +#define REG_AON_APB_DDR_ZQ_CONTROL SCI_ADDR(REGS_AON_APB_BASE, 0x0060)/*DDR_ZQ_CONTROL*/ +#define REG_AON_APB_WBT_BG_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0064)/*WBT_BG_CTRL*/ +#define REG_AON_APB_CLK_DMC_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0080)/*CLK_DMC_CFG*/ +#define REG_AON_APB_SOFT_DFS_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0084)/*SOFT_DFS_CTRL*/ +#define REG_AON_APB_CLK26M_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0088)/*CLK26M_CFG*/ +#define REG_AON_APB_HARD_DFS_CTRL_LO SCI_ADDR(REGS_AON_APB_BASE, 0x0090)/*HARD_DFS_CTRL_LO*/ +#define REG_AON_APB_HARD_DFS_CTRL_HI SCI_ADDR(REGS_AON_APB_BASE, 0x0094)/*HARD_DFS_CTRL_HI*/ +#define REG_AON_APB_AON_CHIP_ID SCI_ADDR(REGS_AON_APB_BASE, 0x00FC)/*AON_CHIP_ID*/ +#define REG_AON_APB_MPLL_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3000)/*MPLL_CFG*/ +#define REG_AON_APB_DPLL_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3004)/*DPLL_CFG*/ +#define REG_AON_APB_TDPLL_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3008)/*TDPLL_CFG*/ +#define REG_AON_APB_CPLL_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x300C)/*CPLL_CFG*/ +#define REG_AON_APB_WIFIPLL0_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3010)/*WIFIPLL0_CFG*/ +#define REG_AON_APB_WIFIPLL1_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3014)/*WIFIPLL1_CFG*/ +#define REG_AON_APB_WPLL_CFG0 SCI_ADDR(REGS_AON_APB_BASE, 0x3018)/*WPLL_CFG0*/ +#define REG_AON_APB_WPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x301C)/*WPLL_CFG1*/ +#define REG_AON_APB_AON_CGM_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3020)/*AON_CGM_CFG*/ +#define REG_AON_APB_CP0_ADDR_REMAP_CTRL0 SCI_ADDR(REGS_AON_APB_BASE, 0x3024)/*CP0_ADDR_REMAP_CTRL0*/ +#define REG_AON_APB_CP0_ADDR_REMAP_CTRL1 SCI_ADDR(REGS_AON_APB_BASE, 0x3028)/*CP0_ADDR_REMAP_CTRL1*/ +#define REG_AON_APB_CP1_ADDR_REMAP_CTRL0 SCI_ADDR(REGS_AON_APB_BASE, 0x302C)/*CP1_ADDR_REMAP_CTRL0*/ +#define REG_AON_APB_CP1_ADDR_REMAP_CTRL1 SCI_ADDR(REGS_AON_APB_BASE, 0x3030)/*CP1_ADDR_REMAP_CTRL1*/ +#define REG_AON_APB_CP2_ADDR_REMAP_CTRL0 SCI_ADDR(REGS_AON_APB_BASE, 0x3034)/*CP2_ADDR_REMAP_CTRL0*/ +#define REG_AON_APB_CP2_ADDR_REMAP_CTRL1 SCI_ADDR(REGS_AON_APB_BASE, 0x3038)/*CP2_ADDR_REMAP_CTRL1*/ +#define REG_AON_APB_IO_DLY_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x303C)/*IO_DLY_CTRL*/ +#define REG_AON_APB_AP_WPROT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x3040)/*AP_WPROT_EN*/ +#define REG_AON_APB_CP0_WPROT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x3044)/*CP0_WPROT_EN*/ +#define REG_AON_APB_CP1_WPROT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x3048)/*CP1_WPROT_EN*/ +#define REG_AON_APB_CP2_WPROT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x304C)/*CP2_WPROT_EN*/ +#define REG_AON_APB_PMU_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3050)/*PMU_RST_MONITOR*/ +#define REG_AON_APB_THM_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3054)/*THM_RST_MONITOR*/ +#define REG_AON_APB_AP_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3058)/*AP_RST_MONITOR*/ +#define REG_AON_APB_CA7_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x305C)/*CA7_RST_MONITOR*/ +#define REG_AON_APB_BOND_OPT0 SCI_ADDR(REGS_AON_APB_BASE, 0x3060)/*BOND_OPT0*/ +#define REG_AON_APB_BOND_OPT1 SCI_ADDR(REGS_AON_APB_BASE, 0x3064)/*BOND_OPT1*/ +#define REG_AON_APB_RES_REG0 SCI_ADDR(REGS_AON_APB_BASE, 0x3068)/*RES_REG0*/ +#define REG_AON_APB_RES_REG1 SCI_ADDR(REGS_AON_APB_BASE, 0x306C)/*RES_REG1*/ +#define REG_AON_APB_MPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x3070)/*MPLL_CFG1*/ +#define REG_AON_APB_DPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x3074)/*DPLL_CFG1*/ +#define REG_AON_APB_TDPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x3078)/*TDPLL_CFG1*/ +#define REG_AON_APB_CPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x307C)/*CPLL_CFG1*/ +#define REG_AON_APB_WIFIPLL1_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x3080)/*WIFIPLL1_CFG1*/ +#define REG_AON_APB_WIFIPLL2_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x3084)/*WIFIPLL2_CFG1*/ +#define REG_AON_APB_AON_QOS_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3088)/*AON_QOS_CFG*/ +#define REG_AON_APB_BB_LDO_CAL_START SCI_ADDR(REGS_AON_APB_BASE, 0x308C)/*BB_LDO_CAL_START*/ +#define REG_AON_APB_WBT_BG_LDO SCI_ADDR(REGS_AON_APB_BASE, 0x3090)/*WBT_BG_LDO*/ +#define REG_AON_APB_ANA_BB_MISC SCI_ADDR(REGS_AON_APB_BASE, 0x3094)/*ANA_BB_MISC*/ +#define REG_AON_APB_DJTAG_MUX_SEL SCI_ADDR(REGS_AON_APB_BASE, 0x3098)/*DJTAG_MUX_SEL*/ +#define REG_AON_APB_BBPLL_RESERVED_0 SCI_ADDR(REGS_AON_APB_BASE, 0x309C)/*BBPLL_RESERVED_0*/ +#define REG_AON_APB_BBPLL_RESERVED_1 SCI_ADDR(REGS_AON_APB_BASE, 0x30A0)/*BBPLL_RESERVED_1*/ +#define REG_AON_APB_RPLL_CFG0 SCI_ADDR(REGS_AON_APB_BASE, 0x30A4)/*RPLL_CFG0*/ +#define REG_AON_APB_AON_DEBUG_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x30A8)/*AON_DEBUG_CFG*/ + + + +/* bits definitions for register REG_AON_APB_APB_EB0 */ +#define BIT_I2C_EB ( BIT(31) ) +#define BIT_CA7_DAP_EB ( BIT(30) ) +#define BIT_CA7_TS1_EB ( BIT(29) ) +#define BIT_CA7_TS0_EB ( BIT(28) ) +#define BIT_GPU_EB ( BIT(27) ) +#define BIT_AON_CKG_EB ( BIT(26) ) +#define BIT_MM_EB ( BIT(25) ) +#define BIT_AP_WDG_EB ( BIT(24) ) +#define BIT_MSPI_EB ( BIT(23) ) +#define BIT_SPLK_EB ( BIT(22) ) +#define BIT_IPI_EB ( BIT(21) ) +#define BIT_PIN_EB ( BIT(20) ) +#define BIT_VBC_EB ( BIT(19) ) +#define BIT_AUD_EB ( BIT(18) ) +#define BIT_AUDIF_EB ( BIT(17) ) +#define BIT_ADI_EB ( BIT(16) ) +#define BIT_INTC_EB ( BIT(15) ) +#define BIT_EIC_EB ( BIT(14) ) +#define BIT_EFUSE_EB ( BIT(13) ) +#define BIT_AP_TMR0_EB ( BIT(12) ) +#define BIT_AON_TMR_EB ( BIT(11) ) +#define BIT_AP_SYST_EB ( BIT(10) ) +#define BIT_AON_SYST_EB ( BIT(9) ) +#define BIT_KPD_EB ( BIT(8) ) +#define BIT_PWM3_EB ( BIT(7) ) +#define BIT_PWM2_EB ( BIT(6) ) +#define BIT_PWM1_EB ( BIT(5) ) +#define BIT_PWM0_EB ( BIT(4) ) +#define BIT_GPIO_EB ( BIT(3) ) +#define BIT_TPC_EB ( BIT(2) ) +#define BIT_FM_EB ( BIT(1) ) +#define BIT_ADC_EB ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_APB_EB1 */ +#define BIT_EMC_REF_CKG_EN ( BIT(20) ) +#define BIT_DJTAG_EB ( BIT(19) ) +#define BIT_RINGOSC_EB ( BIT(18) ) +#define BIT_PUB_REG_EB ( BIT(17) ) +#define BIT_DMC_EB ( BIT(16) ) +#define BIT_RFTI_SBI_EB ( BIT(15) ) +#define BIT_MDAR_EB ( BIT(14) ) +#define BIT_GSP_EMC_EB ( BIT(13) ) +#define BIT_ZIP_EMC_EB ( BIT(12) ) +#define BIT_DISP_EMC_EB ( BIT(11) ) +#define BIT_AP_TMR2_EB ( BIT(10) ) +#define BIT_AP_TMR1_EB ( BIT(9) ) +#define BIT_CA7_WDG_EB ( BIT(8) ) +#define BIT_AVS1_EB ( BIT(7) ) +#define BIT_AVS0_EB ( BIT(6) ) +#define BIT_PROBE_EB ( BIT(5) ) +#define BIT_AUX2_EB ( BIT(4) ) +#define BIT_AUX1_EB ( BIT(3) ) +#define BIT_AUX0_EB ( BIT(2) ) +#define BIT_THM_EB ( BIT(1) ) +#define BIT_PMU_EB ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_APB_RST0 */ +#define BIT_I2C_SOFT_RST ( BIT(30) ) +#define BIT_CA7_TS1_SOFT_RST ( BIT(29) ) +#define BIT_CA7_TS0_SOFT_RST ( BIT(28) ) +#define BIT_DAP_MTX_SOFT_RST ( BIT(27) ) +#define BIT_MSPI1_SOFT_RST ( BIT(26) ) +#define BIT_MSPI0_SOFT_RST ( BIT(25) ) +#define BIT_SPLK_SOFT_RST ( BIT(24) ) +#define BIT_IPI_SOFT_RST ( BIT(23) ) +#define BIT_AON_CKG_SOFT_RST ( BIT(22) ) +#define BIT_PIN_SOFT_RST ( BIT(21) ) +#define BIT_VBC_SOFT_RST ( BIT(20) ) +#define BIT_AUD_SOFT_RST ( BIT(19) ) +#define BIT_AUDIF_SOFT_RST ( BIT(18) ) +#define BIT_ADI_SOFT_RST ( BIT(17) ) +#define BIT_INTC_SOFT_RST ( BIT(16) ) +#define BIT_EIC_SOFT_RST ( BIT(15) ) +#define BIT_EFUSE_SOFT_RST ( BIT(14) ) +#define BIT_AP_WDG_SOFT_RST ( BIT(13) ) +#define BIT_AP_TMR0_SOFT_RST ( BIT(12) ) +#define BIT_AON_TMR_SOFT_RST ( BIT(11) ) +#define BIT_AP_SYST_SOFT_RST ( BIT(10) ) +#define BIT_AON_SYST_SOFT_RST ( BIT(9) ) +#define BIT_KPD_SOFT_RST ( BIT(8) ) +#define BIT_PWM3_SOFT_RST ( BIT(7) ) +#define BIT_PWM2_SOFT_RST ( BIT(6) ) +#define BIT_PWM1_SOFT_RST ( BIT(5) ) +#define BIT_PWM0_SOFT_RST ( BIT(4) ) +#define BIT_GPIO_SOFT_RST ( BIT(3) ) +#define BIT_TPC_SOFT_RST ( BIT(2) ) +#define BIT_FM_SOFT_RST ( BIT(1) ) +#define BIT_ADC_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_APB_RST1 */ +#define BIT_PUB_DJTAG_SOFT_RST ( BIT(23) ) +#define BIT_GPU_DJTAG_SOFT_RST ( BIT(22) ) +#define BIT_MM_DJTAG_SOFT_RST ( BIT(21) ) +#define BIT_CP2_DJTAG_SOFT_RST ( BIT(20) ) +#define BIT_CP0_DJTAG_SOFT_RST ( BIT(19) ) +#define BIT_AP_DJTAG_SOFT_RST ( BIT(18) ) +#define BIT_AON_DJTAG_SOFT_RST ( BIT(17) ) +#define BIT_LVDSRF_CALI_SOFT_RST ( BIT(16) ) +#define BIT_LTH_SOFT_RST ( BIT(15) ) +#define BIT_RINGOSC_SOFT_RST ( BIT(14) ) +#define BIT_RFTI_SBI_SOFT_RST ( BIT(13) ) +#define BIT_MDAR_SOFT_RST ( BIT(12) ) +#define BIT_BB_CAL_SOFT_RST ( BIT(11) ) +#define BIT_DCXO_LC_SOFT_RST ( BIT(10) ) +#define BIT_AP_TMR2_SOFT_RST ( BIT(9) ) +#define BIT_AP_TMR1_SOFT_RST ( BIT(8) ) +#define BIT_CA7_WDG_SOFT_RST ( BIT(7) ) +#define BIT_AVS1_SOFT_RST ( BIT(6) ) +#define BIT_AVS0_SOFT_RST ( BIT(5) ) +#define BIT_DMC_PHY_SOFT_RST ( BIT(4) ) +#define BIT_GPU_THMA_SOFT_RST ( BIT(3) ) +#define BIT_ARM_THMA_SOFT_RST ( BIT(2) ) +#define BIT_THM_SOFT_RST ( BIT(1) ) +#define BIT_PMU_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_APB_RTC_EB */ +#define BIT_BB_CAL_RTC_EB ( BIT(18) ) +#define BIT_DCXO_LC_RTC_EB ( BIT(17) ) +#define BIT_AP_TMR2_RTC_EB ( BIT(16) ) +#define BIT_AP_TMR1_RTC_EB ( BIT(15) ) +#define BIT_GPU_THMA_RTC_AUTO_EN ( BIT(14) ) +#define BIT_ARM_THMA_RTC_AUTO_EN ( BIT(13) ) +#define BIT_GPU_THMA_RTC_EB ( BIT(12) ) +#define BIT_ARM_THMA_RTC_EB ( BIT(11) ) +#define BIT_THM_RTC_EB ( BIT(10) ) +#define BIT_CA7_WDG_RTC_EB ( BIT(9) ) +#define BIT_AP_WDG_RTC_EB ( BIT(8) ) +#define BIT_EIC_RTCDV5_EB ( BIT(7) ) +#define BIT_EIC_RTC_EB ( BIT(6) ) +#define BIT_AP_TMR0_RTC_EB ( BIT(5) ) +#define BIT_AON_TMR_RTC_EB ( BIT(4) ) +#define BIT_AP_SYST_RTC_EB ( BIT(3) ) +#define BIT_AON_SYST_RTC_EB ( BIT(2) ) +#define BIT_KPD_RTC_EB ( BIT(1) ) +#define BIT_ARCH_RTC_EB ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_REC_26MHZ_BUF_CFG */ +#define BITS_PLL_PROBE_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_REC_26MHZ_1_FORCE_PD ( BIT(5) ) +#define BIT_REC_26MHZ_1_CUR_SEL ( BIT(4) ) +#define BIT_REC_26MHZ_0_CUR_SEL ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_SINDRV_CTRL */ +#define BITS_SINDRV_LVL(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)) ) +#define BIT_SINDRV_CLIP_MODE ( BIT(2) ) +#define BIT_SINDRV_ENA_SQUARE ( BIT(1) ) +#define BIT_SINDRV_ENA ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_ADA_SEL_CTRL */ +#define BIT_RAM_TD_MODE_SEL ( BIT(4) ) +#define BIT_TW_MODE_SEL ( BIT(3) ) +#define BIT_WGADC_DIV_EN ( BIT(2) ) +#define BIT_AFCDAC_SYS_SEL ( BIT(1) ) +#define BIT_APCDAC_SYS_SEL ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_VBC_CTRL */ +#define BIT_AUDIF_CKG_AUTO_EN ( BIT(20) ) +#define BITS_AUD_INT_SYS_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_VBC_AFIFO_INT_SYS_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_VBC_AD23_INT_SYS_SEL(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_VBC_AD01_INT_SYS_SEL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_VBC_DA01_INT_SYS_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_VBC_AD23_DMA_SYS_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_VBC_AD01_DMA_SYS_SEL(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_VBC_DA01_DMA_SYS_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BIT_VBC_INT_CP0_ARM_SEL ( BIT(3) ) +#define BIT_VBC_INT_CP1_ARM_SEL ( BIT(2) ) +#define BIT_VBC_DMA_CP0_ARM_SEL ( BIT(1) ) +#define BIT_VBC_DMA_CP1_ARM_SEL ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_PWR_CTRL */ +#define BIT_DSI_PHY_PD_S ( BIT(15) ) +#define BIT_CSI1_PHY_PD_S ( BIT(14) ) +#define BIT_CSI0_PHY_PD_S ( BIT(13) ) +#define BIT_DSI_PHY_PD ( BIT(12) ) +#define BIT_CSI1_PHY_PD ( BIT(11) ) +#define BIT_CSI0_PHY_PD ( BIT(10) ) +#define BIT_CA7_TS1_STOP ( BIT(9) ) +#define BIT_CA7_TS0_STOP ( BIT(8) ) +#define BIT_EFUSE_BIST_PWR_ON ( BIT(3) ) +#define BIT_FORCE_DSI_PHY_SHUTDOWNZ ( BIT(2) ) +#define BIT_FORCE_CSI_PHY_SHUTDOWNZ ( BIT(1) ) +#define BIT_USB_PHY_PD ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_TS_CFG */ +#define BIT_CSYSACK_TS_LP_2 ( BIT(13) ) +#define BIT_CSYSREQ_TS_LP_2 ( BIT(12) ) +#define BIT_CSYSACK_TS_LP_1 ( BIT(11) ) +#define BIT_CSYSREQ_TS_LP_1 ( BIT(10) ) +#define BIT_CSYSACK_TS_LP_0 ( BIT(9) ) +#define BIT_CSYSREQ_TS_LP_0 ( BIT(8) ) +#define BIT_EVENTACK_RESTARTREQ_TS01 ( BIT(4) ) +#define BIT_EVENT_RESTARTREQ_TS01 ( BIT(1) ) +#define BIT_EVENT_HALTREQ_TS01 ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_BOOT_MODE */ +#define BIT_WPLL_OVR_FREQ_SEL ( BIT(12) ) +#define BIT_PTEST_FUNC_ATSPEED_SEL ( BIT(8) ) +#define BIT_PTEST_FUNC_MODE ( BIT(7) ) +#define BIT_PTEST_FUNC_DMA_MODE ( BIT(6) ) +#define BIT_USB_DLOAD_EN ( BIT(4) ) +#define BIT_ARM_BOOT_MD3 ( BIT(3) ) +#define BIT_ARM_BOOT_MD2 ( BIT(2) ) +#define BIT_ARM_BOOT_MD1 ( BIT(1) ) +#define BIT_ARM_BOOT_MD0 ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_BB_BG_CTRL */ +#define BIT_BB_CON_BG ( BIT(22) ) +#define BITS_BB_BG_RSV(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)) ) +#define BITS_BB_LDO_V(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BIT_BB_BG_RBIAS_EN ( BIT(15) ) +#define BIT_BB_BG_IEXT_IB_EN ( BIT(14) ) +#define BITS_BB_LDO_REFCTRL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) ) +#define BIT_BB_LDO_AUTO_PD_EN ( BIT(11) ) +#define BIT_BB_LDO_SLP_PD_EN ( BIT(10) ) +#define BIT_BB_LDO_FORCE_ON ( BIT(9) ) +#define BIT_BB_LDO_FORCE_PD ( BIT(8) ) +#define BIT_BB_BG_AUTO_PD_EN ( BIT(3) ) +#define BIT_BB_BG_SLP_PD_EN ( BIT(2) ) +#define BIT_BB_BG_FORCE_ON ( BIT(1) ) +#define BIT_BB_BG_FORCE_PD ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_CP_ARM_JTAG_CTRL */ +#define BITS_CP_ARM_JTAG_PIN_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AON_APB_PLL_SOFT_CNT_DONE */ +#define BIT_XTLBUF1_SOFT_CNT_DONE ( BIT(9) ) +#define BIT_XTLBUF0_SOFT_CNT_DONE ( BIT(8) ) +#define BIT_WIFIPLL2_SOFT_CNT_DONE ( BIT(6) ) +#define BIT_WIFIPLL1_SOFT_CNT_DONE ( BIT(5) ) +#define BIT_CPLL_SOFT_CNT_DONE ( BIT(4) ) +#define BIT_WPLL_SOFT_CNT_DONE ( BIT(3) ) +#define BIT_TDPLL_SOFT_CNT_DONE ( BIT(2) ) +#define BIT_DPLL_SOFT_CNT_DONE ( BIT(1) ) +#define BIT_MPLL_SOFT_CNT_DONE ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_DCXO_LC_REG0 */ +#define BIT_DCXO_LC_FLAG ( BIT(8) ) +#define BIT_DCXO_LC_FLAG_CLR ( BIT(1) ) +#define BIT_DCXO_LC_CNT_CLR ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_DCXO_LC_REG1 */ +#define BITS_DCXO_LC_CNT(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_DSI_PHY_CTRL */ +#define BIT_DSI_PHY_IF_SEL ( BIT(24) ) +#define BITS_DSI_PHY_TRIMBG(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DSI_PHY_TX_RCTL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DSI_PHY_RESERVED(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AON_APB_CSI0_PHY_CTRL */ +#define BIT_CSI0_PHY_IF_SEL ( BIT(24) ) +#define BITS_CSI0_PHY_RX_RCTL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_CSI0_PHY_RESERVED(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AON_APB_CSI1_PHY_CTRL */ +#define BIT_CSI1_PHY_IF_SEL ( BIT(24) ) +#define BITS_CSI1_PHY_RX_RCTL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_CSI1_PHY_RESERVED(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AON_APB_FUNC_TEST_BOOT_ADDR */ +#define BITS_FUNC_TEST_BOOT_ADDR(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_RINGOSC_CTRL */ +#define BITS_RINGOSC_CNT_CLK_NUM(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) ) +#define BIT_AP_RINGOSC_EN_CA7_TOP ( BIT(15) ) +#define BIT_AP_RINGOSC_EN_AP_TOP ( BIT(14) ) +#define BITS_AP_RINGOSC_CTRL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_RINGOSC_CTRL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_AON_APB_RINGOSC_OBS_CNT */ +#define BIT_RINGOSC_OBS_CNT_OVERFLOW ( BIT(16) ) +#define BITS_RINGOSC_OBS_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AON_APB_DDR_ZQ_CONTROL */ +#define BIT_DDR_ZQ_CALOVER ( BIT(17) ) +#define BIT_DDR_ZQ_PD ( BIT(16) ) +#define BIT_DDR_ZQ_CAL ( BIT(15) ) +#define BITS_DDR_ZQ_ZPROG(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_DDR_ZQ_DRVP(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DDR_ZQ_DRVN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register REG_AON_APB_WBT_BG_CTRL */ +#define BIT_WBT_LDO_CAL_RST ( BIT(25) ) +#define BIT_WBT_LDO_CAL_START ( BIT(24) ) +#define BIT_WBT_LDO_CAL_CLK ( BIT(23) ) +#define BIT_WBT_CON_BG ( BIT(22) ) +#define BITS_WBT_LDO_V(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)|BIT(21)) ) +#define BIT_WBT_BG_RBIAS_EN ( BIT(17) ) +#define BIT_WBT_BG_IEXT_IB_EN ( BIT(16) ) +#define BIT_WBT_LDO_AUTO_PD_EN ( BIT(11) ) +#define BIT_WBT_LDO_SLP_PD_EN ( BIT(10) ) +#define BIT_WBT_LDO_FORCE_ON ( BIT(9) ) +#define BIT_WBT_LDO_FORCE_PD ( BIT(8) ) +#define BIT_WBT_BG_AUTO_PD_EN ( BIT(3) ) +#define BIT_WBT_BG_SLP_PD_EN ( BIT(2) ) +#define BIT_WBT_BG_FORCE_ON ( BIT(1) ) +#define BIT_WBT_BG_FORCE_PD ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_CLK_DMC_CFG */ +#define BITS_CLK_DMC_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_DMC_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_APB_SOFT_DFS_CTRL */ +#define BITS_PUB_DFS_SW_SWITCH_PERIOD(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PUB_DFS_SW_RATIO(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_PUB_DFS_SW_FRQ_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BIT_PUB_DFS_SW_RESP ( BIT(3) ) +#define BIT_PUB_DFS_SW_ACK ( BIT(2) ) +#define BIT_PUB_DFS_SW_REQ ( BIT(1) ) +#define BIT_PUB_DFS_SW_ENABLE ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_CLK26M_CFG */ +#define BIT_CLKBAK_EN ( BIT(4) ) +#define BIT_CLK26MHZ_A2D_1_SEL ( BIT(3) ) +#define BIT_CLK26MHZ_A2D_0_SEL ( BIT(2) ) +#define BITS_CLK26M_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_APB_HARD_DFS_CTRL_LO */ +#define BITS_PUB_DFS_HW_INITIAL_FREQ(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)) ) +#define BIT_PUB_DFS_HW_STOP ( BIT(2) ) +#define BIT_PUB_DFS_HW_START ( BIT(1) ) +#define BIT_PUB_DFS_HW_ENABLE ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_HARD_DFS_CTRL_HI */ +#define BITS_PUB_DFS_HW_SWITCH_PERIOD(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_PUB_DFS_HW_F3_RATIO(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_PUB_DFS_HW_F2_RATIO(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_PUB_DFS_HW_F1_RATIO(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_PUB_DFS_HW_F0_RATIO(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register REG_AON_APB_AON_CHIP_ID */ +#define BITS_AON_CHIP_ID(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_MPLL_CFG */ +#define BITS_MPLL_REFIN(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_MPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_MPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_MPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AON_APB_DPLL_CFG */ +#define BITS_DPLL_REFIN(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_DPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_DPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_DPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AON_APB_TDPLL_CFG */ +#define BIT_TDPLL_DIV5_FORCE_PD ( BIT(31) ) +#define BIT_TDPLL_DIV3_FORCE_PD ( BIT(30) ) +#define BIT_TDPLL_DIV2_FORCE_PD ( BIT(29) ) +#define BIT_TDPLL_DIV5_PD_AUTO ( BIT(28) ) +#define BIT_TDPLL_DIV3_PD_AUTO ( BIT(27) ) +#define BIT_TDPLL_DIV2_PD_AUTO ( BIT(26) ) +#define BITS_TDPLL_REFIN(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_TDPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_TDPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_TDPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AON_APB_CPLL_CFG */ +#define BITS_CPLL_REFIN(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_CPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_CPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_CPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AON_APB_WIFIPLL0_CFG */ +#define BITS_WIFIPLL1_REFIN(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_WIFIPLL1_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_WIFIPLL1_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_WIFIPLL1_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AON_APB_WIFIPLL1_CFG */ +#define BITS_WIFIPLL2_REFIN(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_WIFIPLL2_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_WIFIPLL2_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_WIFIPLL2_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AON_APB_WPLL_CFG0 */ +#define BITS_WPLL_REFIN(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_WPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_WPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_WPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AON_APB_WPLL_CFG1 */ +#define BITS_WPLL_KINT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_WPLL_DIV_S ( BIT(10) ) +#define BITS_WPLL_RSV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_WPLL_MOD_EN ( BIT(7) ) +#define BIT_WPLL_SDM_EN ( BIT(6) ) +#define BITS_WPLL_NINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_AON_APB_AON_CGM_CFG */ +#define BITS_PROBE_CKG_DIV(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_AUX2_CKG_DIV(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_AUX1_CKG_DIV(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_AUX0_CKG_DIV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_PROBE_CKG_SEL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_AUX2_CKG_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_AUX1_CKG_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_AUX0_CKG_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_CP0_ADDR_REMAP_CTRL0 */ +#define BITS_CP0_ADDR_B7_REMAP(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_CP0_ADDR_B6_REMAP(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_CP0_ADDR_B5_REMAP(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_CP0_ADDR_B4_REMAP(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_CP0_ADDR_B3_REMAP(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_CP0_ADDR_B2_REMAP(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CP0_ADDR_B1_REMAP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_CP0_ADDR_B0_REMAP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_CP0_ADDR_REMAP_CTRL1 */ +#define BIT_CP0_PUB_IRAM_B8_PROT_EN ( BIT(12) ) +#define BIT_CP0_PUB_IRAM_B7_PROT_EN ( BIT(11) ) +#define BIT_CP0_PUB_IRAM_B6_PROT_EN ( BIT(10) ) +#define BIT_CP0_PUB_IRAM_B5_PROT_EN ( BIT(9) ) +#define BIT_CP0_PUB_IRAM_B4_PROT_EN ( BIT(8) ) +#define BIT_CP0_PUB_IRAM_B3_PROT_EN ( BIT(7) ) +#define BIT_CP0_PUB_IRAM_B2_PROT_EN ( BIT(6) ) +#define BIT_CP0_PUB_IRAM_B1_PROT_EN ( BIT(5) ) +#define BIT_CP0_PUB_IRAM_B0_PROT_EN ( BIT(4) ) +#define BITS_CP0_ADDR_B8_REMAP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_CP1_ADDR_REMAP_CTRL0 */ +#define BITS_CP1_ADDR_B7_REMAP(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_CP1_ADDR_B6_REMAP(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_CP1_ADDR_B5_REMAP(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_CP1_ADDR_B4_REMAP(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_CP1_ADDR_B3_REMAP(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_CP1_ADDR_B2_REMAP(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CP1_ADDR_B1_REMAP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_CP1_ADDR_B0_REMAP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_CP1_ADDR_REMAP_CTRL1 */ +#define BIT_CP1_PUB_IRAM_B8_PROT_EN ( BIT(12) ) +#define BIT_CP1_PUB_IRAM_B7_PROT_EN ( BIT(11) ) +#define BIT_CP1_PUB_IRAM_B6_PROT_EN ( BIT(10) ) +#define BIT_CP1_PUB_IRAM_B5_PROT_EN ( BIT(9) ) +#define BIT_CP1_PUB_IRAM_B4_PROT_EN ( BIT(8) ) +#define BIT_CP1_PUB_IRAM_B3_PROT_EN ( BIT(7) ) +#define BIT_CP1_PUB_IRAM_B2_PROT_EN ( BIT(6) ) +#define BIT_CP1_PUB_IRAM_B1_PROT_EN ( BIT(5) ) +#define BIT_CP1_PUB_IRAM_B0_PROT_EN ( BIT(4) ) +#define BITS_CP1_ADDR_B8_REMAP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_CP2_ADDR_REMAP_CTRL0 */ +#define BITS_CP2_ADDR_B7_REMAP(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_CP2_ADDR_B6_REMAP(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_CP2_ADDR_B5_REMAP(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_CP2_ADDR_B4_REMAP(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_CP2_ADDR_B3_REMAP(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_CP2_ADDR_B2_REMAP(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CP2_ADDR_B1_REMAP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_CP2_ADDR_B0_REMAP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_CP2_ADDR_REMAP_CTRL1 */ +#define BIT_CP2_PUB_IRAM_B8_PROT_EN ( BIT(12) ) +#define BIT_CP2_PUB_IRAM_B7_PROT_EN ( BIT(11) ) +#define BIT_CP2_PUB_IRAM_B6_PROT_EN ( BIT(10) ) +#define BIT_CP2_PUB_IRAM_B5_PROT_EN ( BIT(9) ) +#define BIT_CP2_PUB_IRAM_B4_PROT_EN ( BIT(8) ) +#define BIT_CP2_PUB_IRAM_B3_PROT_EN ( BIT(7) ) +#define BIT_CP2_PUB_IRAM_B2_PROT_EN ( BIT(6) ) +#define BIT_CP2_PUB_IRAM_B1_PROT_EN ( BIT(5) ) +#define BIT_CP2_PUB_IRAM_B0_PROT_EN ( BIT(4) ) +#define BITS_CP2_ADDR_B8_REMAP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_IO_DLY_CTRL */ +#define BITS_CLK_CCIR_DLY_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CLK_CP1DSP_DLY_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_CLK_CP0DSP_DLY_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_AP_WPROT_EN */ +#define BITS_AP_AWADDR_WPROT_EN(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CP0_WPROT_EN */ +#define BITS_CP0_AWADDR_WPROT_EN(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CP1_WPROT_EN */ +#define BITS_CP1_AWADDR_WPROT_EN(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CP2_WPROT_EN */ +#define BITS_CP2_AWADDR_WPROT_EN(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_PMU_RST_MONITOR */ +#define BITS_PMU_RST_MONITOR(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_THM_RST_MONITOR */ +#define BITS_THM_RST_MONITOR(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_AP_RST_MONITOR */ +#define BITS_AP_RST_MONITOR(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CA7_RST_MONITOR */ +#define BITS_CA7_RST_MONITOR(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_BOND_OPT0 */ +#define BITS_BOND_OPTION0(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_BOND_OPT1 */ +#define BITS_BOND_OPTION1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_RES_REG0 */ +#define BITS_RES_REG0(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_RES_REG1 */ +#define BITS_RES_REG1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_MPLL_CFG1 */ +#define BITS_MPLL_KINT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_MPLL_DIV_S ( BIT(10) ) +#define BITS_MPLL_RSV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_MPLL_MOD_EN ( BIT(7) ) +#define BIT_MPLL_SDM_EN ( BIT(6) ) +#define BITS_MPLL_NINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_AON_APB_DPLL_CFG1 */ +#define BITS_DPLL_KINT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_DPLL_DIV_S ( BIT(10) ) +#define BITS_DPLL_RSV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_DPLL_MOD_EN ( BIT(7) ) +#define BIT_DPLL_SDM_EN ( BIT(6) ) +#define BITS_DPLL_NINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_AON_APB_TDPLL_CFG1 */ +#define BITS_TDPLL_KINT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_TDPLL_DIV_S ( BIT(10) ) +#define BITS_TDPLL_RSV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_TDPLL_MOD_EN ( BIT(7) ) +#define BIT_TDPLL_SDM_EN ( BIT(6) ) +#define BITS_TDPLL_NINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_AON_APB_CPLL_CFG1 */ +#define BITS_CPLL_KINT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_CPLL_DIV_S ( BIT(10) ) +#define BITS_CPLL_RSV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_CPLL_MOD_EN ( BIT(7) ) +#define BIT_CPLL_SDM_EN ( BIT(6) ) +#define BITS_CPLL_NINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_AON_APB_WIFIPLL1_CFG1 */ +#define BITS_WIFIPLL1_KINT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_WIFIPLL1_DIV_S ( BIT(10) ) +#define BITS_WIFIPLL1_RSV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_WIFIPLL1_MOD_EN ( BIT(7) ) +#define BIT_WIFIPLL1_SDM_EN ( BIT(6) ) +#define BITS_WIFIPLL1_NINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_AON_APB_WIFIPLL2_CFG1 */ +#define BITS_WIFIPLL2_KINT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_WIFIPLL2_DIV_S ( BIT(10) ) +#define BITS_WIFIPLL2_RSV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_WIFIPLL2_MOD_EN ( BIT(7) ) +#define BIT_WIFIPLL2_SDM_EN ( BIT(6) ) +#define BITS_WIFIPLL2_NINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_AON_APB_AON_QOS_CFG */ +#define BITS_QOS_R_GPU(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_QOS_W_GPU(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_QOS_R_GSP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_QOS_W_GSP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_BB_LDO_CAL_START */ +#define BIT_BB_LDO_CAL_START ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_WBT_BG_LDO */ +#define BITS_WBT_BG_RESERVED(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_WBT_RESERVED(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AON_APB_ANA_BB_MISC */ +#define BITS_ANA_BB_RESERVED(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AON_APB_DJTAG_MUX_SEL */ +#define BIT_DJTAG_AON_SEL ( BIT(6) ) +#define BIT_DJTAG_PUB_SEL ( BIT(5) ) +#define BIT_DJTAG_CP2_SEL ( BIT(4) ) +#define BIT_DJTAG_CP0_SEL ( BIT(3) ) +#define BIT_DJTAG_GPU_SEL ( BIT(2) ) +#define BIT_DJTAG_MM_SEL ( BIT(1) ) +#define BIT_DJTAG_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_BBPLL_RESERVED_0 */ +#define BITS_WPLL_RESERVED(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_TDPLL_RESERVED(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_MPLL_RESERVED(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_CPLL_RESERVED(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_AON_APB_BBPLL_RESERVED_1 */ +#define BITS_LVDSRF_LVPLL_RESERVED(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_RPLL_RESERVED(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_AON_APB_RPLL_CFG0 */ +#define BIT_LVDS_LVPLL_REF_SEL_CTRL ( BIT(10) ) +#define BIT_LVDS_LVPLL_REF_SEL ( BIT(9) ) +#define BITS_RPLL_PD_CTRL(_X_) ( (_X_) << 7 & (BIT(7)|BIT(8)) ) +#define BIT_RPLL_RST_CTRL ( BIT(6) ) +#define BIT_BBPLL_REFCLK_SEL_CTRL ( BIT(5) ) +#define BIT_RPLL_26MTESTOUT_EN ( BIT(4) ) +#define BIT_CLK26MHZ_MUXTUNE_EN ( BIT(3) ) +#define BIT_BBPLL_REFCLK_SEL ( BIT(2) ) +#define BIT_RPLL_RST ( BIT(1) ) +#define BIT_RPLL_PD ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_AON_DEBUG_CFG */ +#define BITS_AON_DEBUG_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +#endif diff --git a/include/soc/sprd/chip_x20/__regs_aon_clk.h b/include/soc/sprd/chip_x20/__regs_aon_clk.h new file mode 100644 index 00000000..9f93b73c --- /dev/null +++ b/include/soc/sprd/chip_x20/__regs_aon_clk.h @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __REGS_AON_CLK_H__ +#define __REGS_AON_CLK_H__ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, include <mach/sci_glb_regs.h>" +#endif + +#define REGS_AON_CLK + +/* registers definitions for controller REGS_AON_CLK */ +#define REG_AON_CLK_PUB_AHB_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0020) +#define REG_AON_CLK_EMC_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0024) +#define REG_AON_CLK_AON_APB_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0028) +#define REG_AON_CLK_AUDIF_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x002c) +#define REG_AON_CLK_FM_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0030) +#define REG_AON_CLK_ADI_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0034) +#define REG_AON_CLK_PWM0_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0038) +#define REG_AON_CLK_PWM1_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x003c) +#define REG_AON_CLK_PWM2_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0040) +#define REG_AON_CLK_PWM3_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0044) +#define REG_AON_CLK_THM_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0048) +#define REG_AON_CLK_CA7_DAP_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x004C) +#define REG_AON_CLK_CA7_TS_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0050) +#define REG_AON_CLK_MSPI_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0054) +#define REG_AON_CLK_I2C_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0058) +#define REG_AON_CLK_RFTI_SBI_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x005C) +#define REG_AON_CLK_AVS0_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0060) +#define REG_AON_CLK_AVS1_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0064) +#define REG_AON_CLK_DJTAG_TCK_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0068) + + +/* vars definitions for controller REGS_AON_CLK */ + +#endif //__REGS_AON_CLK_H__ diff --git a/include/soc/sprd/chip_x20/__regs_ap_ahb.h b/include/soc/sprd/chip_x20/__regs_ap_ahb.h new file mode 100644 index 00000000..b300b1a5 --- /dev/null +++ b/include/soc/sprd/chip_x20/__regs_ap_ahb.h @@ -0,0 +1,395 @@ +/* the head file modifier: ang 2015-01-13 20:46:24*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_AP_AHB_HEADFILE_H__ +#define __H_REGS_AP_AHB_HEADFILE_H__ __FILE__ + +#define REGS_AP_AHB + +/* registers definitions for AP_AHB */ +#define REG_AP_AHB_AHB_EB SCI_ADDR(REGS_AP_AHB_BASE, 0x0000)/*AHB_EB*/ +#define REG_AP_AHB_AHB_RST SCI_ADDR(REGS_AP_AHB_BASE, 0x0004)/*AHB_RST*/ +#define REG_AP_AHB_CA7_RST_SET SCI_ADDR(REGS_AP_AHB_BASE, 0x0008)/*CA7_RST_SET*/ +#define REG_AP_AHB_AP_SYS_FORCE_SLEEP_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x000C)/*AP_SYS_FORCE_SLEEP_CFG*/ +#define REG_AP_AHB_AP_SYS_AUTO_SLEEP_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x0010)/*AP_SYS_AUTO_SLEEP_CFG*/ +#define REG_AP_AHB_HOLDING_PEN SCI_ADDR(REGS_AP_AHB_BASE, 0x0014)/*HOLDING_PEN*/ +#define REG_AP_AHB_JMP_ADDR_CA7_C0 SCI_ADDR(REGS_AP_AHB_BASE, 0x0018)/*JMP_ADDR_CA7_C0*/ +#define REG_AP_AHB_JMP_ADDR_CA7_C1 SCI_ADDR(REGS_AP_AHB_BASE, 0x001C)/*JMP_ADDR_CA7_C1*/ +#define REG_AP_AHB_JMP_ADDR_CA7_C2 SCI_ADDR(REGS_AP_AHB_BASE, 0x0020)/*JMP_ADDR_CA7_C2*/ +#define REG_AP_AHB_JMP_ADDR_CA7_C3 SCI_ADDR(REGS_AP_AHB_BASE, 0x0024)/*JMP_ADDR_CA7_C3*/ +#define REG_AP_AHB_CA7_C0_PU_LOCK SCI_ADDR(REGS_AP_AHB_BASE, 0x0028)/*CA7_C0_PU_LOCK*/ +#define REG_AP_AHB_CA7_C1_PU_LOCK SCI_ADDR(REGS_AP_AHB_BASE, 0x002C)/*CA7_C1_PU_LOCK*/ +#define REG_AP_AHB_CA7_C2_PU_LOCK SCI_ADDR(REGS_AP_AHB_BASE, 0x0030)/*CA7_C2_PU_LOCK*/ +#define REG_AP_AHB_CA7_C3_PU_LOCK SCI_ADDR(REGS_AP_AHB_BASE, 0x0034)/*CA7_C3_PU_LOCK*/ +#define REG_AP_AHB_CA7_CKG_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x3000)/*CA7_CKG_CFG*/ +#define REG_AP_AHB_MCU_PAUSE SCI_ADDR(REGS_AP_AHB_BASE, 0x3004)/*MCU_PAUSE*/ +#define REG_AP_AHB_MISC_CKG_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x3008)/*MISC_CKG_EN*/ +#define REG_AP_AHB_MISC_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x300C)/*MISC_CFG*/ +#define REG_AP_AHB_AP_MTX_S3_PRIO0 SCI_ADDR(REGS_AP_AHB_BASE, 0x3010)/*AP_MTX_S3_PRIO0*/ +#define REG_AP_AHB_AP_MTX_S3_PRIO1 SCI_ADDR(REGS_AP_AHB_BASE, 0x3014)/*AP_MTX_S3_PRIO1*/ +#define REG_AP_AHB_AP_MTX_S3_PRIO2 SCI_ADDR(REGS_AP_AHB_BASE, 0x3018)/*AP_MTX_S3_PRIO2*/ +#define REG_AP_AHB_AP_MTX_S2_PRIO0 SCI_ADDR(REGS_AP_AHB_BASE, 0x301C)/*AP_MTX_S2_PRIO0*/ +#define REG_AP_AHB_AP_MTX_S1_PRIO0 SCI_ADDR(REGS_AP_AHB_BASE, 0x3020)/*AP_MTX_S1_PRIO0*/ +#define REG_AP_AHB_AP_MTX_S0_PRIO0 SCI_ADDR(REGS_AP_AHB_BASE, 0x3024)/*AP_MTX_S0_PRIO0*/ +#define REG_AP_AHB_AP_MTX_S0_PRIO1 SCI_ADDR(REGS_AP_AHB_BASE, 0x3028)/*AP_MTX_S0_PRIO1*/ +#define REG_AP_AHB_AP_MTX_S0_PRIO2 SCI_ADDR(REGS_AP_AHB_BASE, 0x302C)/*AP_MTX_S0_PRIO2*/ +#define REG_AP_AHB_AP_MAIN_MTX_HPROT_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x3030)/*AP_MAIN_MTX_HPROT_CFG*/ +#define REG_AP_AHB_CA7_STANDBY_STATUS SCI_ADDR(REGS_AP_AHB_BASE, 0x3034)/*CA7_STANDBY_STATUS*/ +#define REG_AP_AHB_NANC_CLK_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x3038)/*NANDC_CLK_CFG*/ +#define REG_AP_AHB_LVDS_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x303C)/*LVDS_CFG*/ +#define REG_AP_AHB_LVDS_PLL_CFG0 SCI_ADDR(REGS_AP_AHB_BASE, 0x3040)/*LVDS_PLL_CFG0*/ +#define REG_AP_AHB_LVDS_PLL_CFG1 SCI_ADDR(REGS_AP_AHB_BASE, 0x3044)/*LVDS_PLL_CFG1*/ +#define REG_AP_AHB_CA7_C0_AUTO_FORCE_SHUTDOWN_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x3048)/*CA7_C0_AUTO_FORCE_SHUTDOWN_EN*/ +#define REG_AP_AHB_CA7_C1_AUTO_FORCE_SHUTDOWN_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x304C)/*CA7_C1_AUTO_FORCE_SHUTDOWN_EN*/ +#define REG_AP_AHB_CA7_C2_AUTO_FORCE_SHUTDOWN_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x3050)/*CA7_C2_AUTO_FORCE_SHUTDOWN_EN*/ +#define REG_AP_AHB_CA7_C3_AUTO_FORCE_SHUTDOWN_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x3054)/*CA7_C3_AUTO_FORCE_SHUTDOWN_EN*/ +#define REG_AP_AHB_AP_QOS_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x3058)/*AP_QOS_CFG*/ +#define REG_AP_AHB_CHIP_ID SCI_ADDR(REGS_AP_AHB_BASE, 0x30FC)/*CHIP_ID*/ + + + +/* bits definitions for register REG_AP_AHB_AHB_EB */ +#define BIT_LVDS_EB ( BIT(22) ) +#define BIT_ZIPDEC_EB ( BIT(21) ) +#define BIT_ZIPENC_EB ( BIT(20) ) +#define BIT_NANDC_ECC_EB ( BIT(19) ) +#define BIT_NANDC_2X_EB ( BIT(18) ) +#define BIT_NANDC_EB ( BIT(17) ) +#define BIT_BUSMON2_EB ( BIT(16) ) +#define BIT_BUSMON1_EB ( BIT(15) ) +#define BIT_BUSMON0_EB ( BIT(14) ) +#define BIT_SPINLOCK_EB ( BIT(13) ) +#define BIT_GPS_EB ( BIT(12) ) +#define BIT_EMMC_EB ( BIT(11) ) +#define BIT_SDIO2_EB ( BIT(10) ) +#define BIT_SDIO1_EB ( BIT(9) ) +#define BIT_SDIO0_EB ( BIT(8) ) +#define BIT_DRM_EB ( BIT(7) ) +#define BIT_NFC_EB ( BIT(6) ) +#define BIT_DMA_EB ( BIT(5) ) +#define BIT_USB_EB ( BIT(4) ) +#define BIT_GSP_EB ( BIT(3) ) +#define BIT_DISPC1_EB ( BIT(2) ) +#define BIT_DISPC0_EB ( BIT(1) ) +#define BIT_DSI_EB ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_AHB_RST */ +#define BIT_LVDS_SOFT_RST ( BIT(25) ) +#define BIT_ZIP_MTX_SOFT_RST ( BIT(24) ) +#define BIT_ZIPDEC_SOFT_RST ( BIT(23) ) +#define BIT_ZIPENC_SOFT_RST ( BIT(22) ) +#define BIT_NANDC_SOFT_RST ( BIT(20) ) +#define BIT_BUSMON2_SOFT_RST ( BIT(19) ) +#define BIT_BUSMON1_SOFT_RST ( BIT(18) ) +#define BIT_BUSMON0_SOFT_RST ( BIT(17) ) +#define BIT_SPINLOCK_SOFT_RST ( BIT(16) ) +#define BIT_GPS_SOFT_RST ( BIT(15) ) +#define BIT_EMMC_SOFT_RST ( BIT(14) ) +#define BIT_SDIO2_SOFT_RST ( BIT(13) ) +#define BIT_SDIO1_SOFT_RST ( BIT(12) ) +#define BIT_SDIO0_SOFT_RST ( BIT(11) ) +#define BIT_DRM_SOFT_RST ( BIT(10) ) +#define BIT_NFC_SOFT_RST ( BIT(9) ) +#define BIT_DMA_SOFT_RST ( BIT(8) ) +#define BIT_USB_PHY_SOFT_RST ( BIT(7) ) +#define BIT_USB_UTMI_SOFT_RST ( BIT(6) ) +#define BIT_USB_SOFT_RST ( BIT(5) ) +#define BIT_DISP_MTX_SOFT_RST ( BIT(4) ) +#define BIT_GSP_SOFT_RST ( BIT(3) ) +#define BIT_DISPC1_SOFT_RST ( BIT(2) ) +#define BIT_DISPC0_SOFT_RST ( BIT(1) ) +#define BIT_DSI_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_CA7_RST_SET */ +#define BIT_CA7_CS_DBG_SOFT_RST ( BIT(14) ) +#define BIT_CA7_L2_SOFT_RST ( BIT(13) ) +#define BIT_CA7_SOCDBG_SOFT_RST ( BIT(12) ) +#define BITS_CA7_ETM_SOFT_RST(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CA7_DBG_SOFT_RST(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_CA7_CORE_SOFT_RST(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AP_AHB_AP_SYS_FORCE_SLEEP_CFG */ +#define BIT_AP_PERI_FORCE_ON ( BIT(2) ) +#define BIT_AP_PERI_FORCE_SLP ( BIT(1) ) +#define BIT_AP_APB_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_AP_SYS_AUTO_SLEEP_CFG */ +#define BIT_GSP_CKG_FORCE_EN ( BIT(9) ) +#define BIT_GSP_AUTO_GATE_EN ( BIT(8) ) +#define BIT_AP_AHB_AUTO_GATE_EN ( BIT(5) ) +#define BIT_AP_EMC_AUTO_GATE_EN ( BIT(4) ) +#define BIT_CA7_EMC_AUTO_GATE_EN ( BIT(3) ) +#define BIT_CA7_DBG_FORCE_SLEEP ( BIT(2) ) +#define BIT_CA7_DBG_AUTO_GATE_EN ( BIT(1) ) +#define BIT_CA7_CORE_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_HOLDING_PEN */ +#define BITS_HOLDING_PEN(_X_) (_X_) + +/* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C0 */ +#define BITS_JMP_ADDR_CA7_C0(_X_) (_X_) + +/* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C1 */ +#define BITS_JMP_ADDR_CA7_C1(_X_) (_X_) + +/* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C2 */ +#define BITS_JMP_ADDR_CA7_C2(_X_) (_X_) + +/* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C3 */ +#define BITS_JMP_ADDR_CA7_C3(_X_) (_X_) + +/* bits definitions for register REG_AP_AHB_CA7_C0_PU_LOCK */ +#define BIT_CA7_C0_PU_LOCK ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_CA7_C1_PU_LOCK */ +#define BIT_CA7_C1_PU_LOCK ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_CA7_C2_PU_LOCK */ +#define BIT_CA7_C2_PU_LOCK ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_CA7_C3_PU_LOCK */ +#define BIT_CA7_C3_PU_LOCK ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_CA7_CKG_CFG */ +#define BITS_CA7_DBG_CKG_DIV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)) ) +#define BITS_CA7_AXI_CKG_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CA7_MCU_CKG_DIV(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BITS_CA7_MCU_CKG_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AP_AHB_MCU_PAUSE */ +#define BIT_DMA_ACT_LIGHT_EN ( BIT(5) ) +#define BIT_MCU_SLEEP_FOLLOW_CA7_EN ( BIT(4) ) +#define BIT_MCU_LIGHT_SLEEP_EN ( BIT(3) ) +#define BIT_MCU_DEEP_SLEEP_EN ( BIT(2) ) +#define BIT_MCU_SYS_SLEEP_EN ( BIT(1) ) +#define BIT_MCU_CORE_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_MISC_CKG_EN */ +#define BIT_GPS_TCXO_INV_SEL ( BIT(13) ) +#define BIT_GPS_26M_INV_SEL ( BIT(12) ) +#define BIT_ASHB_CA7_DBG_VLD ( BIT(9) ) +#define BIT_ASHB_CA7_DBG_EN ( BIT(8) ) +#define BIT_DISP_TMC_CKG_EN ( BIT(4) ) +#define BIT_DPHY_REF_CKG_EN ( BIT(1) ) +#define BIT_DPHY_CFG_CKG_EN ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_MISC_CFG */ +#define BITS_EMMC_SLOT_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_SDIO0_SLOT_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_BUSMON2_CHN_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_BUSMON1_CHN_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_BUSMON0_CHN_SEL ( BIT(4) ) +#define BITS_SDIO2_SLOT_SEL(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_SDIO1_SLOT_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_AHB_AP_MTX_S3_PRIO0 */ +#define BITS_PRI_M6TOS3_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_PRI_M6TOS3_SEL(_X_) ( (_X_) << 26 & (BIT(26)|BIT(27)) ) +#define BIT_PRI_M6TOS3_RND_EN ( BIT(25) ) +#define BIT_PRI_M6TOS3_ADJ_EN ( BIT(24) ) +#define BITS_PRI_M7TOS3_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PRI_M7TOS3_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BIT_PRI_M7TOS3_RND_EN ( BIT(17) ) +#define BIT_PRI_M7TOS3_ADJ_EN ( BIT(16) ) +#define BITS_PRI_M8TOS3_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PRI_M8TOS3_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BIT_PRI_M8TOS3_RND_EN ( BIT(9) ) +#define BIT_PRI_M8TOS3_ADJ_EN ( BIT(8) ) +#define BITS_PRI_M9TOS3_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_PRI_M9TOS3_SEL(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) ) +#define BIT_PRI_M9TOS3_RND_EN ( BIT(1) ) +#define BIT_PRI_M9TOS3_ADJ_EN ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_AP_MTX_S3_PRIO1 */ +#define BITS_PRI_M2TOS3_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_PRI_M2TOS3_SEL(_X_) ( (_X_) << 26 & (BIT(26)|BIT(27)) ) +#define BIT_PRI_M2TOS3_RND_EN ( BIT(25) ) +#define BIT_PRI_M2TOS3_ADJ_EN ( BIT(24) ) +#define BITS_PRI_M3TOS3_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PRI_M3TOS3_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BIT_PRI_M3TOS3_RND_EN ( BIT(17) ) +#define BIT_PRI_M3TOS3_ADJ_EN ( BIT(16) ) +#define BITS_PRI_M4TOS3_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PRI_M4TOS3_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BIT_PRI_M4TOS3_RND_EN ( BIT(9) ) +#define BIT_PRI_M4TOS3_ADJ_EN ( BIT(8) ) +#define BITS_PRI_M5TOS3_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_PRI_M5TOS3_SEL(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) ) +#define BIT_PRI_M5TOS3_RND_EN ( BIT(1) ) +#define BIT_PRI_M5TOS3_ADJ_EN ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_AP_MTX_S3_PRIO2 */ +#define BITS_PRI_M0TOS3_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_PRI_M0TOS3_SEL(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) ) +#define BIT_PRI_M0TOS3_RND_EN ( BIT(1) ) +#define BIT_PRI_M0TOS3_ADJ_EN ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_AP_MTX_S2_PRIO0 */ +#define BITS_PRI_M0TOS2_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_PRI_M0TOS2_SEL(_X_) ( (_X_) << 26 & (BIT(26)|BIT(27)) ) +#define BIT_PRI_M0TOS2_RND_EN ( BIT(25) ) +#define BIT_PRI_M0TOS2_ADJ_EN ( BIT(24) ) +#define BITS_PRI_M1TOS2_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PRI_M1TOS2_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BIT_PRI_M1TOS2_RND_EN ( BIT(17) ) +#define BIT_PRI_M1TOS2_ADJ_EN ( BIT(16) ) +#define BITS_PRI_M2TOS2_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PRI_M2TOS2_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BIT_PRI_M2TOS2_RND_EN ( BIT(9) ) +#define BIT_PRI_M2TOS2_ADJ_EN ( BIT(8) ) +#define BITS_PRI_M3TOS2_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_PRI_M3TOS2_SEL(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) ) +#define BIT_PRI_M3TOS2_RND_EN ( BIT(1) ) +#define BIT_PRI_M3TOS2_ADJ_EN ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_AP_MTX_S1_PRIO0 */ +#define BITS_PRI_M0TOS1_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_PRI_M0TOS1_SEL(_X_) ( (_X_) << 26 & (BIT(26)|BIT(27)) ) +#define BIT_PRI_M0TOS1_RND_EN ( BIT(25) ) +#define BIT_PRI_M0TOS1_ADJ_EN ( BIT(24) ) +#define BITS_PRI_M2TOS1_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PRI_M2TOS1_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BIT_PRI_M2TOS1_RND_EN ( BIT(17) ) +#define BIT_PRI_M2TOS1_ADJ_EN ( BIT(16) ) +#define BITS_PRI_M3TOS1_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PRI_M3TOS1_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BIT_PRI_M3TOS1_RND_EN ( BIT(9) ) +#define BIT_PRI_M3TOS1_ADJ_EN ( BIT(8) ) +#define BITS_PRI_M8TOS1_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_PRI_M8TOS1_SEL(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) ) +#define BIT_PRI_M8TOS1_RND_EN ( BIT(1) ) +#define BIT_PRI_M8TOS1_ADJ_EN ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_AP_MTX_S0_PRIO0 */ +#define BITS_PRI_M0TOS0_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_PRI_M0TOS0_SEL(_X_) ( (_X_) << 26 & (BIT(26)|BIT(27)) ) +#define BIT_PRI_M0TOS0_RND_EN ( BIT(25) ) +#define BIT_PRI_M0TOS0_ADJ_EN ( BIT(24) ) +#define BITS_PRI_M1TOS0_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PRI_M1TOS0_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BIT_PRI_M1TOS0_RND_EN ( BIT(17) ) +#define BIT_PRI_M1TOS0_ADJ_EN ( BIT(16) ) +#define BITS_PRI_M2TOS0_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PRI_M2TOS0_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BIT_PRI_M2TOS0_RND_EN ( BIT(9) ) +#define BIT_PRI_M2TOS0_ADJ_EN ( BIT(8) ) +#define BITS_PRI_M3TOS0_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_PRI_M3TOS0_SEL(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) ) +#define BIT_PRI_M3TOS0_RND_EN ( BIT(1) ) +#define BIT_PRI_M3TOS0_ADJ_EN ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_AP_MTX_S0_PRIO1 */ +#define BITS_PRI_M4TOS1_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_PRI_M4TOS1_SEL(_X_) ( (_X_) << 26 & (BIT(26)|BIT(27)) ) +#define BIT_PRI_M4TOS1_RND_EN ( BIT(25) ) +#define BIT_PRI_M4TOS1_ADJ_EN ( BIT(24) ) +#define BITS_PRI_M5TOS1_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PRI_M5TOS1_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BIT_PRI_M5TOS1_RND_EN ( BIT(17) ) +#define BIT_PRI_M5TOS1_ADJ_EN ( BIT(16) ) +#define BITS_PRI_M6TOS1_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PRI_M6TOS1_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BIT_PRI_M6TOS1_RND_EN ( BIT(9) ) +#define BIT_PRI_M6TOS1_ADJ_EN ( BIT(8) ) +#define BITS_PRI_M7TOS1_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_PRI_M7TOS1_SEL(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) ) +#define BIT_PRI_M7TOS1_RND_EN ( BIT(1) ) +#define BIT_PRI_M7TOS1_ADJ_EN ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_AP_MTX_S0_PRIO2 */ +#define BITS_PRI_M9TOS1_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_PRI_M9TOS1_SEL(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) ) +#define BIT_PRI_M9TOS1_RND_EN ( BIT(1) ) +#define BIT_PRI_M9TOS1_ADJ_EN ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_AP_MAIN_MTX_HPROT_CFG */ +#define BITS_HPROT_NFC(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_HPROT_EMMC(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_HPROT_SDIO2(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_HPROT_SDIO1(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_HPROT_SDIO0(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_HPROT_DMAW(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_HPROT_DMAR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AP_AHB_CA7_STANDBY_STATUS */ +#define BIT_CA7_STANDBYWFIL2 ( BIT(12) ) +#define BITS_CA7_ETMSTANDBYWFX(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CA7_STANDBYWFE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_CA7_STANDBYWFI(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AP_AHB_NANC_CLK_CFG */ +#define BITS_CLK_NANDC_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CLK_NANDC2X_DIV(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_CLK_NANDC2X_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_AHB_LVDS_CFG */ +#define BITS_LVDS_TXCLKDATA(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_LVDS_TXCOM(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_LVDS_TXSLEW(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_LVDS_TXSW(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_LVDS_TXRERSER(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_LVDS_PRE_EMP(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)) ) +#define BIT_LVDS_TXPD ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_LVDS_PLL_CFG0 */ +#define BIT_LPLL_LOCK_DET ( BIT(31) ) +#define BITS_LPLL_POST_DIV(_X_) ( (_X_) << 26 & (BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_LPLL_REFIN(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_LPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BIT_LPLL_DIV_S ( BIT(18) ) +#define BITS_LPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_LPLLN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AP_AHB_LVDS_PLL_CFG1 */ +#define BITS_LPLL_KINT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_LPLL_RSV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BIT_LPLL_MOD_EN ( BIT(7) ) +#define BIT_LPLL_SDM_EN ( BIT(6) ) +#define BITS_LPLL_NINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_AP_AHB_CA7_C0_AUTO_FORCE_SHUTDOWN_EN */ +#define BIT_CA7_C0_AUTO_FORCE_SHUTDOWN_EN ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_CA7_C1_AUTO_FORCE_SHUTDOWN_EN */ +#define BIT_CA7_C1_AUTO_FORCE_SHUTDOWN_EN ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_CA7_C2_AUTO_FORCE_SHUTDOWN_EN */ +#define BIT_CA7_C2_AUTO_FORCE_SHUTDOWN_EN ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_CA7_C3_AUTO_FORCE_SHUTDOWN_EN */ +#define BIT_CA7_C3_AUTO_FORCE_SHUTDOWN_EN ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_AP_QOS_CFG */ +#define BITS_QOS_R_TMC(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_QOS_W_TMC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_QOS_R_DISPC1(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_QOS_W_DISPC1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_QOS_R_DISPC0(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_QOS_W_DISPC0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AP_AHB_CHIP_ID */ +#define BITS_CHIP_ID(_X_) (_X_) + +#endif diff --git a/include/soc/sprd/chip_x20/__regs_ap_apb.h b/include/soc/sprd/chip_x20/__regs_ap_apb.h new file mode 100644 index 00000000..7e35a991 --- /dev/null +++ b/include/soc/sprd/chip_x20/__regs_ap_apb.h @@ -0,0 +1,148 @@ +/* the head file modifier: ang 2015-01-13 20:47:26*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_AP_APB_HEADFILE_H__ +#define __H_REGS_AP_APB_HEADFILE_H__ __FILE__ + +#define REGS_AP_APB + +/* registers definitions for AP_APB */ +#define REG_AP_APB_APB_EB SCI_ADDR(REGS_AP_APB_BASE, 0x0000)/*AHB_EB*/ +#define REG_AP_APB_APB_RST SCI_ADDR(REGS_AP_APB_BASE, 0x0004)/*AHB_RST*/ +#define REG_AP_APB_USB_CTRL0 SCI_ADDR(REGS_AP_APB_BASE, 0x0010)/*USB_PHY_TUNE*/ +#define REG_AP_APB_USB_CTRL1 SCI_ADDR(REGS_AP_APB_BASE, 0x0014)/*USB_PHY_TUNE*/ +#define REG_AP_APB_LVDS_DISP_CTRL0 SCI_ADDR(REGS_AP_APB_BASE, 0x0018)/*MISC_CKG_EN*/ +#define REG_AP_APB_USB_PHY_TEST SCI_ADDR(REGS_AP_APB_BASE, 0x3004)/*MISC_CKG_EN*/ +#define REG_AP_APB_USB_PHY_CTRL SCI_ADDR(REGS_AP_APB_BASE, 0x3008)/*USB_PHY_CTRL*/ +#define REG_AP_APB_APB_MISC_CTRL SCI_ADDR(REGS_AP_APB_BASE, 0x300C)/*APB_MISC_CTRL*/ + + + +/* bits definitions for register REG_AP_APB_APB_EB */ +#define BIT_INTC3_EB ( BIT(22) ) +#define BIT_INTC2_EB ( BIT(21) ) +#define BIT_INTC1_EB ( BIT(20) ) +#define BIT_INTC0_EB ( BIT(19) ) +#define BIT_AP_CKG_EB ( BIT(18) ) +#define BIT_UART4_EB ( BIT(17) ) +#define BIT_UART3_EB ( BIT(16) ) +#define BIT_UART2_EB ( BIT(15) ) +#define BIT_UART1_EB ( BIT(14) ) +#define BIT_UART0_EB ( BIT(13) ) +#define BIT_I2C4_EB ( BIT(12) ) +#define BIT_I2C3_EB ( BIT(11) ) +#define BIT_I2C2_EB ( BIT(10) ) +#define BIT_I2C1_EB ( BIT(9) ) +#define BIT_I2C0_EB ( BIT(8) ) +#define BIT_SPI2_EB ( BIT(7) ) +#define BIT_SPI1_EB ( BIT(6) ) +#define BIT_SPI0_EB ( BIT(5) ) +#define BIT_IIS3_EB ( BIT(4) ) +#define BIT_IIS2_EB ( BIT(3) ) +#define BIT_IIS1_EB ( BIT(2) ) +#define BIT_IIS0_EB ( BIT(1) ) +#define BIT_SIM0_EB ( BIT(0) ) + +/* bits definitions for register REG_AP_APB_APB_RST */ +#define BIT_INTC3_SOFT_RST ( BIT(22) ) +#define BIT_INTC2_SOFT_RST ( BIT(21) ) +#define BIT_INTC1_SOFT_RST ( BIT(20) ) +#define BIT_INTC0_SOFT_RST ( BIT(19) ) +#define BIT_CKG_SOFT_RST ( BIT(18) ) +#define BIT_UART4_SOFT_RST ( BIT(17) ) +#define BIT_UART3_SOFT_RST ( BIT(16) ) +#define BIT_UART2_SOFT_RST ( BIT(15) ) +#define BIT_UART1_SOFT_RST ( BIT(14) ) +#define BIT_UART0_SOFT_RST ( BIT(13) ) +#define BIT_I2C4_SOFT_RST ( BIT(12) ) +#define BIT_I2C3_SOFT_RST ( BIT(11) ) +#define BIT_I2C2_SOFT_RST ( BIT(10) ) +#define BIT_I2C1_SOFT_RST ( BIT(9) ) +#define BIT_I2C0_SOFT_RST ( BIT(8) ) +#define BIT_SPI2_SOFT_RST ( BIT(7) ) +#define BIT_SPI1_SOFT_RST ( BIT(6) ) +#define BIT_SPI0_SOFT_RST ( BIT(5) ) +#define BIT_IIS3_SOFT_RST ( BIT(4) ) +#define BIT_IIS2_SOFT_RST ( BIT(3) ) +#define BIT_IIS1_SOFT_RST ( BIT(2) ) +#define BIT_IIS0_SOFT_RST ( BIT(1) ) +#define BIT_SIM0_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_AP_APB_USB_CTRL0 */ +#define BITS_USB20_TUNEHSAMP(_X_) ( (_X_) << 30 & (BIT(30)|BIT(31)) ) +#define BITS_USB20_TUNEPLLS(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)) ) +#define BITS_USB20_TUNERISE(_X_) ( (_X_) << 26 & (BIT(26)|BIT(27)) ) +#define BITS_USB20_TUNESQ(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_USB20_TUNEDSC(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_USB20_TUNEOTG(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BIT_USB20_TXBITSTUFFENABLE ( BIT(17) ) +#define BIT_USB20_TXBITSTUFFENABLEH ( BIT(16) ) +#define BITS_USB20_RESERVED(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AP_APB_USB_CTRL1 */ +#define BIT_HSIC_PLLON ( BIT(16) ) +#define BIT_USB20_REXTENABLE ( BIT(15) ) +#define BIT_USB20_S_ID ( BIT(14) ) +#define BITS_USB20_TF12KRES(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_USB20_TFHSRES(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_USB20_TUNEEQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AP_APB_LVDS_DISP_CTRL0 */ +#define BIT_LVDSDIS_OFF_CL ( BIT(14) ) +#define BIT_LVDSDIS_OFF_OCT ( BIT(13) ) +#define BITS_LVDSDIS_TXPD(_X_) ( (_X_) << 7 & (BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BITS_LVDSDIS_TXIMP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BITS_LVDSDIS_TXRESERVED(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AP_APB_USB_PHY_TEST */ +#define BIT_ATERESET ( BIT(31) ) +#define BIT_VBUS_VALID_EXT_SEL ( BIT(26) ) +#define BIT_VBUS_VALID_EXT ( BIT(25) ) +#define BIT_OTGDISABLE ( BIT(24) ) +#define BIT_TESTBURNIN ( BIT(21) ) +#define BIT_LOOPBACKENB ( BIT(20) ) +#define BITS_TESTDATAOUT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_VATESTENB(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) ) +#define BIT_TESTCLK ( BIT(13) ) +#define BIT_TESTDATAOUTSEL ( BIT(12) ) +#define BITS_TESTADDR(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_TESTDATAIN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_AP_APB_USB_PHY_CTRL */ +#define BITS_SS_SCALEDOWNMODE(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BIT_TXBITSTUFFENH ( BIT(23) ) +#define BIT_TXBITSTUFFEN ( BIT(22) ) +#define BIT_DMPULLDOWN ( BIT(21) ) +#define BIT_DPPULLDOWN ( BIT(20) ) +#define BIT_DMPULLUP ( BIT(9) ) +#define BIT_COMMONONN ( BIT(8) ) +#define BITS_REFCLKSEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_FSEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AP_APB_APB_MISC_CTRL */ +#define BIT_SIM_CLK_POLARITY ( BIT(1) ) +#define BIT_FMARK_POLARITY_INV ( BIT(0) ) + +#endif diff --git a/include/soc/sprd/chip_x20/__regs_ap_clk.h b/include/soc/sprd/chip_x20/__regs_ap_clk.h new file mode 100644 index 00000000..379b3de0 --- /dev/null +++ b/include/soc/sprd/chip_x20/__regs_ap_clk.h @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __REGS_AP_CLK_H__ +#define __REGS_AP_CLK_H__ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, include <mach/sci_glb_regs.h>" +#endif + +#define REGS_AP_CLK + +/* registers definitions for controller REGS_AP_CLK */ +#define REG_AP_CLK_AP_AHB_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0020) +#define REG_AP_CLK_AP_APB_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0024) +#define REG_AP_CLK_GSP_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0028) +#define REG_AP_CLK_DISPC0_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x002c) +#define REG_AP_CLK_DISPC0_DBI_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0030) +#define REG_AP_CLK_DISPC0_DPI_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0034) +#define REG_AP_CLK_DISPC1_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0038) +#define REG_AP_CLK_DISPC1_DBI_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x003c) +#define REG_AP_CLK_DISPC1_DPI_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0040) +#define REG_AP_CLK_NFC_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0044) +#define REG_AP_CLK_SDIO0_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0048) +#define REG_AP_CLK_SDIO1_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x004c) +#define REG_AP_CLK_SDIO2_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0050) +#define REG_AP_CLK_EMMC_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0054) +#define REG_AP_CLK_GPS_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0058) +#define REG_AP_CLK_GPS_TCXO_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x005c) +#define REG_AP_CLK_USB_REF_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0060) +#define REG_AP_CLK_UART0_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0064) +#define REG_AP_CLK_UART1_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0068) +#define REG_AP_CLK_UART2_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x006c) +#define REG_AP_CLK_UART3_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0070) +#define REG_AP_CLK_UART4_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0074) +#define REG_AP_CLK_I2C0_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0078) +#define REG_AP_CLK_I2C1_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x007c) +#define REG_AP_CLK_I2C2_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0080) +#define REG_AP_CLK_I2C3_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0084) +#define REG_AP_CLK_I2C4_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0088) +#define REG_AP_CLK_SPI0_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x008c) +#define REG_AP_CLK_SPI1_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0090) +#define REG_AP_CLK_SPI2_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0094) +#define REG_AP_CLK_IIS0_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0098) +#define REG_AP_CLK_IIS1_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x009c) +#define REG_AP_CLK_IIS2_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x00a0) +#define REG_AP_CLK_IIS3_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x00a4) +#define REG_AP_CLK_ZIPENC_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x00a8) +#define REG_AP_CLK_ZIPDEC_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x00ac) + +/* vars definitions for controller REGS_AP_CLK */ + +#endif //__REGS_AP_CLK_H__ diff --git a/include/soc/sprd/chip_x20/__regs_apb_rf_cp2.h b/include/soc/sprd/chip_x20/__regs_apb_rf_cp2.h new file mode 100644 index 00000000..edddb5f5 --- /dev/null +++ b/include/soc/sprd/chip_x20/__regs_apb_rf_cp2.h @@ -0,0 +1,454 @@ +/*
+ * Copyright (C) 2014 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+#ifndef __SCI_GLB_REGS_H__
+#error "Don't include this file directly, Pls include sci_glb_regs.h"
+#endif
+
+
+#ifndef __H_REGS_APB_RF_CP2_HEADFILE_H__
+#define __H_REGS_APB_RF_CP2_HEADFILE_H__ __FILE__
+
+#define REGS_APB_RF_CP2
+
+/* registers definitions for APB_RF_CP2 */
+#define REG_APB_RF_CP2_APB_RST SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0000)
+#define REG_APB_RF_CP2_MCU_SOFT_RST SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0004)
+#define REG_APB_RF_CP2_APB_EB SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0018)
+#define REG_APB_RF_CP2_APB_EB1 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x001C)
+#define REG_APB_RF_CP2_APB_CLK_CTL0 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0020)
+#define REG_APB_RF_CP2_APB_CLK_CTL1 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0024)
+#define REG_APB_RF_CP2_APB_SLP_CTL0 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0030)
+#define REG_APB_RF_CP2_APB_INT_STS0 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0034)
+#define REG_APB_RF_CP2_APB_INT_SET_CLR0 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0038)
+#define REG_APB_RF_CP2_WIFI_BUF_BASE SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x003C)
+#define REG_APB_RF_CP2_CLK_TOP_CTRL0 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0040)
+#define REG_APB_RF_CP2_CLK_TOP_CTRL1 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0044)
+#define REG_APB_RF_CP2_FPGADEBUG SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0048)
+#define REG_APB_RF_CP2_APB_BT_DAC_CTR0 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0050)
+#define REG_APB_RF_CP2_APB_BT_DAC_CTR1 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0054)
+#define REG_APB_RF_CP2_APB_BT_DAC_CTR2 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0058)
+#define REG_APB_RF_CP2_APB_BT_DAC_STS0 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x005C)
+#define REG_APB_RF_CP2_APB_BT_DAC_STS1 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0060)
+#define REG_APB_RF_CP2_APB_BT_ADC_CTR0 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0064)
+#define REG_APB_RF_CP2_APB_BT_ADC_CTR1 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0068)
+#define REG_APB_RF_CP2_APB_BT_ADC_CTR2 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x006C)
+#define REG_APB_RF_CP2_WIFI_SYS0 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0070)
+#define REG_APB_RF_CP2_WIFI_SYS1 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0074)
+#define REG_APB_RF_CP2_APB_WIFI_ADC_CTR0 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0078)
+#define REG_APB_RF_CP2_APB_WIFI_ADC_CTR1 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x007C)
+#define REG_APB_RF_CP2_ARM7_RDATA_FROM_ARM9 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0080)
+#define REG_APB_RF_CP2_ARM7_WDATA_TO_ARM9 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0084)
+#define REG_APB_RF_CP2_CP2_BB_CTRL SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0088)
+#define REG_APB_RF_CP2_WIFI_BT_CFG0 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0090)
+#define REG_APB_RF_CP2_WIFI_BT_CFG1 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0094)
+#define REG_APB_RF_CP2_WIFI_BT_CFG2 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0098)
+#define REG_APB_RF_CP2_WIFI_BT_CFG3 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x009C)
+#define REG_APB_RF_CP2_WIFI_DFT_CTRTL0 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00A0)
+#define REG_APB_RF_CP2_WIFI_DFT_CTRTL1 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00A4)
+#define REG_APB_RF_CP2_WIFI_DFT_CTRTL2 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00A8)
+#define REG_APB_RF_CP2_WB_ADA_CTRTL0 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00B0)
+#define REG_APB_RF_CP2_WB_ADA_CTRTL1 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00B4)
+#define REG_APB_RF_CP2_WB_ADA_CTRTL2 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00B8)
+#define REG_APB_RF_CP2_WB_ADA_CTRTL3 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00BC)
+#define REG_APB_RF_CP2_WB_ADA_RESULT0 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00C0)
+#define REG_APB_RF_CP2_WB_ADA_RESULT1 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00C4)
+#define REG_APB_RF_CP2_WB_ADA_RESULT2 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00C8)
+#define REG_APB_RF_CP2_WB_ADA_RESULT3 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00CC)
+#define REG_APB_RF_CP2_WB_DBG_RESULT0 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00D0)
+#define REG_APB_RF_CP2_WB_DBG_RESULT1 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00D4)
+#define REG_APB_RF_CP2_WB_DAC_DBG_DAT SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00D8)
+#define REG_APB_RF_CP2_BT_FUNC_DBG SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00DC)
+#define REG_APB_RF_CP2_APB_ARCH_PORT SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0100)
+#define REG_APB_RF_CP2_IN_AXI_ADDR SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0104)
+#define REG_APB_RF_CP2_IN_CFG_SIZE SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0108)
+#define REG_APB_RF_CP2_APB_MISC_CTL SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0200)
+#define REG_APB_RF_CP2_APB_MISC_CTL1 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0204)
+#define REG_APB_RF_CP2_WIFI_SARADC_CTRL0 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0208)
+#define REG_APB_RF_CP2_WIFI_SARADC_CTRL1 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x020C)
+#define REG_APB_RF_CP2_BT_SARADC_CTRL1 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0210)
+#define REG_APB_RF_CP2_BT_SARADC_CTRL2 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0214)
+#define REG_APB_RF_CP2_WBT_DAC_CTRL0 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0218)
+#define REG_APB_RF_CP2_WBT_ANA_STS0 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x022C)
+#define REG_APB_RF_CP2_WBT_ANA_STS1 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0230)
+#define REG_APB_RF_CP2_WIFI_CTRL0 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0234)
+#define REG_APB_RF_CP2_WIFI_DAC_DFT SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0238)
+#define REG_APB_RF_CP2_WIFI_ADC_DFT SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x023C)
+
+
+
+/* bits definitions for register REG_APB_RF_CP2_APB_RST */
+#define BIT_PHY_SOFT_RST ( BIT(20) )
+#define BIT_MAC_SOFT_RST ( BIT(19) )
+#define BIT_GPIO_SOFT_RST ( BIT(18) )
+#define BIT_ADI_SOFT_RST ( BIT(17) )
+#define BIT_VBC_SOFT_RST ( BIT(16) )
+#define BIT_AUD_SOFT_RST ( BIT(15) )
+#define BIT_VPU_SOFT_RST ( BIT(14) )
+#define BIT_FM_SOFT_RST ( BIT(13) )
+#define BIT_IPI_SOFT_RST ( BIT(12) )
+#define BIT_WIFI_SOFT_RST ( BIT(11) )
+#define BIT_IIS_SOFT_RST ( BIT(10) )
+#define BIT_EIC_SOFT_RST ( BIT(9) )
+#define BIT_BT_SOFT_RST ( BIT(8) )
+#define BIT_WDG_SOFT_RST ( BIT(7) )
+#define BIT_TMR1_SOFT_RST ( BIT(6) )
+#define BIT_TMR0_SOFT_RST ( BIT(5) )
+#define BIT_SYST_SOFT_RST ( BIT(4) )
+#define BIT_UART1_SOFT_RST ( BIT(3) )
+#define BIT_UART0_SOFT_RST ( BIT(2) )
+
+/* bits definitions for register REG_APB_RF_CP2_MCU_SOFT_RST */
+#define BIT_MCU_SOFT_RST_SET ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_EB */
+#define BIT_GPIO_EB ( BIT(24) )
+#define BIT_ADI_EB ( BIT(23) )
+#define BIT_VBC_EB ( BIT(22) )
+#define BIT_AUD_EB ( BIT(21) )
+#define BIT_VPU_EB ( BIT(20) )
+#define BIT_FM_EB ( BIT(19) )
+#define BIT_IPI_EB ( BIT(18) )
+#define BIT_WIFI_EB ( BIT(17) )
+#define BIT_IIS_EB ( BIT(16) )
+#define BIT_EIC_RTCDV5_EB ( BIT(15) )
+#define BIT_EIC_EB ( BIT(14) )
+#define BIT_BT_RTC_EB ( BIT(13) )
+#define BIT_TMR1_RTC_EB ( BIT(12) )
+#define BIT_TMR0_RTC_EB ( BIT(11) )
+#define BIT_SYST_RTC_EB ( BIT(10) )
+#define BIT_WDG_RTC_EB ( BIT(9) )
+#define BIT_BT_EB ( BIT(8) )
+#define BIT_WDG_EB ( BIT(7) )
+#define BIT_TMR1_EB ( BIT(6) )
+#define BIT_TMR0_EB ( BIT(5) )
+#define BIT_SYST_EB ( BIT(4) )
+#define BIT_UART1_EB ( BIT(3) )
+#define BIT_UART0_EB ( BIT(2) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_EB1 */
+#define BIT_APB_ARCH_RTC_EB ( BIT(1) )
+#define BIT_APB_ARCH_EB ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_CLK_CTL0 */
+#define BITS_CLK_WTDAC_CTRL(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_CLK_BT_26M_SRC_SEL ( BIT(19) )
+#define BITS_CLK_BT_DA_SEL(_X_) ( (_X_) << 17 & (BIT(17)|BIT(18)) )
+#define BITS_CLK_BT_AD_SEL(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)) )
+#define BITS_CLK_UART0_SEL(_X_) ( (_X_) << 13 & (BIT(13)|BIT(14)) )
+#define BIT_CLK_BT_26M_SEL ( BIT(12) )
+#define BIT_CLK_BT_24M_SEL ( BIT(11) )
+#define BITS_CLK_IIS_SEL(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)) )
+#define BITS_CLK_VPU_SEL(_X_) ( (_X_) << 7 & (BIT(7)|BIT(8)) )
+#define BITS_CLK_UART1_SEL(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)) )
+#define BIT_CLK_WIFI_120M_EN ( BIT(4) )
+#define BIT_CLK_WIFI_26M_EN ( BIT(3) )
+#define BIT_CLK_WIFI_80M_EN ( BIT(2) )
+#define BIT_CLK_WIFI_44M_EN ( BIT(1) )
+#define BIT_CLK_WIFI_40M_EN ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_CLK_CTL1 */
+#define BITS_CLK_IIS_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_SLP_CTL0 */
+#define BIT_APB_FORCE_ON ( BIT(2) )
+#define BIT_APB_FORCE_SLEEP ( BIT(1) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_INT_STS0 */
+#define BIT_ARM9_FRQ ( BIT(3) )
+#define BIT_ARM9_IRQ ( BIT(2) )
+#define BIT_ARM7_MCU_FRQ ( BIT(1) )
+#define BIT_ARM7_MCU_IRQ ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_INT_SET_CLR0 */
+#define BIT_ARM9_FRQ_CLR ( BIT(3) )
+#define BIT_ARM9_IRQ_CLR ( BIT(2) )
+#define BIT_ARM7_MCU_FRQ_SET ( BIT(1) )
+#define BIT_ARM7_MCU_IRQ_SET ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_BUF_BASE */
+#define BITS_WIFI_BUF_BASE(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_CLK_TOP_CTRL0 */
+#define BITS_CLK_TOP_CTRL0(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_CLK_TOP_CTRL1 */
+#define BITS_CLK_TOP_CTRL1(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_FPGADEBUG */
+#define BITS_FPGADEBUG(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_APB_BT_DAC_CTR0 */
+#define BITS_BT_DAC_BG_CTR(_X_) ( (_X_) << 30 & (BIT(30)|BIT(31)) )
+#define BIT_BT_DAC_EN_ADC ( BIT(26) )
+#define BIT_BT_DAC_CLK_SEL ( BIT(25) )
+#define BIT_BT_DAC_EN_MIDRANGE ( BIT(24) )
+#define BITS_BT_DAC_Q_DC(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_BT_DAC_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_BT_DAC_CTR1 */
+#define BITS_BT_DAC_SEL(_X_) ( (_X_) << 29 & (BIT(29)|BIT(30)) )
+#define BIT_BT_DAC_BOOSTI_EN ( BIT(28) )
+#define BITS_BT_DAC_CFG(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)|BIT(27)) )
+#define BIT_BT_DAC_CAL_CLK_SEL ( BIT(24) )
+#define BIT_BT_DAC_PD ( BIT(23) )
+#define BITS_BT_DAC_WADDR_OVR(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)|BIT(22)) )
+#define BIT_BT_DAC_WLE_OVR ( BIT(18) )
+#define BITS_BT_DAC_WD_OVR(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)) )
+#define BIT_BT_DAC_W_OVR_I_QN ( BIT(1) )
+#define BIT_BT_DAC_W_OVR_EN ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_BT_DAC_CTR2 */
+#define BIT_BB_BG_EN ( BIT(21) )
+#define BIT_BB_LDO_EN ( BIT(20) )
+#define BIT_BT_DAC_OVR_EN_CAL ( BIT(19) )
+#define BIT_BT_DAC_EN_OOSCAL ( BIT(18) )
+#define BIT_BT_DAC_IQ_SWAP ( BIT(17) )
+#define BIT_BT_DAC_CAL_START ( BIT(16) )
+#define BITS_BT_DAC_OFFSETI(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_BT_DAC_OFFSETQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_BT_DAC_STS0 */
+#define BITS_BT_DAC_WTI(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_BT_DAC_WTQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_BT_DAC_STS1 */
+#define BITS_BT_DAC_DA_STATE(_X_) ( (_X_) << 17 & (BIT(17)|BIT(18)) )
+#define BIT_BT_DAC_DONE ( BIT(16) )
+#define BITS_BT_DAC_WQ_OVR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_BT_ADC_CTR0 */
+#define BITS_BT_ADC_SARSPD(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) )
+#define BITS_BT_ADC_CMPSPD(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) )
+#define BITS_BT_ADC_ADJ(_X_) ( (_X_) << 7 & (BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)) )
+#define BITS_BT_ADC_REFBIAS(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) )
+#define BITS_BT_ADC_CMPBIAS(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BIT_BT_ADC_MODE ( BIT(1) )
+#define BIT_BT_ADC_EN ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_BT_ADC_CTR1 */
+#define BIT_BT_ADC_CAL ( BIT(18) )
+#define BITS_BT_ADC_DUTY(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) )
+#define BITS_BT_ADC_DLL_D(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BIT_BT_ADC_DLL_RD ( BIT(8) )
+#define BIT_BT_ADC_DLL_SUG ( BIT(7) )
+#define BITS_BT_ADC_DLL_SET(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) )
+#define BIT_BT_ADC_DLL_OVR ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_BT_ADC_CTR2 */
+#define BITS_BT_PTA_SL(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BIT_BT_CTRL ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_SYS0 */
+#define BITS_WIFIMAB_CTRL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_WIFISAB_CTRL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_SYS1 */
+#define BITS_WIFIMAB_STS(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_WIFISAB_STS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_WIFI_ADC_CTR0 */
+#define BITS_WIFI_ADC_SARSPD(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) )
+#define BITS_WIFI_ADC_CMPSPD(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) )
+#define BITS_WIFI_ADC_ADJ(_X_) ( (_X_) << 7 & (BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)) )
+#define BITS_WIFI_ADC_REFBIAS(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) )
+#define BITS_WIFI_ADC_CMPBIAS(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BIT_WIFI_ADC_MODE ( BIT(1) )
+#define BIT_WIFI_ADC_EN ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_WIFI_ADC_CTR1 */
+#define BIT_WIFI_ADC_CAL ( BIT(18) )
+#define BITS_WIFI_ADC_DUTY(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) )
+#define BITS_WIFI_ADC_DLL_D(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BIT_WIFI_ADC_DLL_RD ( BIT(8) )
+#define BIT_WIFI_ADC_DLL_SUG ( BIT(7) )
+#define BITS_WIFI_ADC_DLL_SET(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) )
+#define BIT_WIFI_ADC_DLL_OVR ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_ARM7_RDATA_FROM_ARM9 */
+#define BITS_ARM7_RDATA_FROM_ARM9(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_ARM7_WDATA_TO_ARM9 */
+#define BITS_ARM7_WDATA_TO_ARM9(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_CP2_BB_CTRL */
+#define BITS_BB_LOCAL_CTRL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_BT_CFG0 */
+#define BITS_WIFI_BT_CFG0(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_BT_CFG1 */
+#define BITS_WIFI_BT_CFG1(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_BT_CFG2 */
+#define BITS_WIFI_BT_CFG2(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_BT_CFG3 */
+#define BITS_WIFI_BT_CFG3(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_DFT_CTRTL0 */
+#define BITS_WIFI_DFT_CTRTL0(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_DFT_CTRTL1 */
+#define BITS_WIFI_DFT_CTRTL1(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_DFT_CTRTL2 */
+#define BITS_WIFI_DFT_CTRTL2(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WB_ADA_CTRTL0 */
+#define BITS_WB_ADA_CTRTL0(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WB_ADA_CTRTL1 */
+#define BITS_WB_ADA_CTRTL1(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WB_ADA_CTRTL2 */
+#define BITS_WB_ADA_CTRTL2(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WB_ADA_CTRTL3 */
+#define BITS_WB_ADA_CTRTL3(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WB_ADA_RESULT0 */
+#define BITS_WB_ADA_RESULT0(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WB_ADA_RESULT1 */
+#define BITS_WB_ADA_RESULT1(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WB_ADA_RESULT2 */
+#define BITS_WB_ADA_RESULT2(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WB_ADA_RESULT3 */
+#define BITS_WB_ADA_RESULT3(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WB_DBG_RESULT0 */
+#define BITS_WB_DBG_RESULT0(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WB_DBG_RESULT1 */
+#define BITS_WB_DBG_RESULT1(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WB_DAC_DBG_DAT */
+#define BITS_WBDAC_IQ_TEST_DAT(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_BT_FUNC_DBG */
+#define BITS_BT_FUNC_DBG(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_APB_ARCH_PORT */
+#define BIT_MCU_PROT_GLB ( BIT(16) )
+#define BITS_MCU_PROT_CHECK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_APB_RF_CP2_IN_AXI_ADDR */
+#define BITS_IN_AXI_ADDR(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_IN_CFG_SIZE */
+#define BITS_IN_CFG_SIZE(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_APB_MISC_CTL */
+#define BIT_FPGA_SPI_SEL ( BIT(16) )
+#define BIT_TEST_DBG_MODE3 ( BIT(10) )
+#define BIT_TEST_DBG_MODE2 ( BIT(9) )
+#define BIT_TEST_DBG_MODE1 ( BIT(8) )
+#define BIT_TEST_DBG_MODE0 ( BIT(7) )
+#define BIT_BT_MAHB_SLEEP_EN ( BIT(6) )
+#define BIT_DSP2BT_IND ( BIT(5) )
+#define BIT_ROM_CLK_FORCE_EN ( BIT(4) )
+#define BIT_ARM7_JTAG_EN ( BIT(3) )
+#define BITS_ARM7_CACHE_SIZE(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)) )
+#define BIT_ARM7_CACHE_EN ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_MISC_CTL1 */
+#define BITS_ARM7_HWRST1_REG(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_SARADC_CTRL0 */
+#define BIT_WIFI_SARAD_CLK_SEL ( BIT(26) )
+#define BIT_WIFI_SARAD_DEBUG_EN ( BIT(25) )
+#define BITS_WIFI_SARAD_CALADDR(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) )
+#define BIT_WIFI_SARAD_CALEN ( BIT(18) )
+#define BIT_WIFI_SARAD_CALRD ( BIT(17) )
+#define BIT_WIFI_SARAD_CAL_RSTN ( BIT(16) )
+#define BIT_WIFI_SARAD_DLLEN ( BIT(15) )
+#define BITS_WIFI_SARAD_DLLIN(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_WIFI_SARAD_DLLOOF(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) )
+#define BIT_WIFI_SARAD_DLLRD ( BIT(2) )
+#define BIT_WIFI_SARAD_DLLWR ( BIT(1) )
+#define BIT_WIFI_SARAD_DLL_RSTN ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_SARADC_CTRL1 */
+#define BITS_WIFI_SARAD_QUANT_BOOST(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) )
+#define BITS_WIFI_SARAD_VREF_BOOST(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) )
+#define BITS_WIFI_SARAD_VREF_SEL(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) )
+#define BITS_WIFI_SARAD_BIT_SEL(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) )
+#define BITS_WIFI_SARAD_DELAY_CAP(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) )
+#define BIT_WIFI_SARAD_VCM_SEL ( BIT(18) )
+#define BIT_WIFI_SARAD_DIG_CLK_SEL ( BIT(17) )
+#define BIT_WIFI_SARAD_CAL ( BIT(16) )
+#define BITS_WIFI_SARAD_RESERVE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_APB_RF_CP2_BT_SARADC_CTRL1 */
+#define BIT_BT_SARAD_PD ( BIT(27) )
+#define BIT_BT_SARAD_ADCS_EN ( BIT(26) )
+#define BIT_BT_SARAD_DEBUG_EN ( BIT(25) )
+#define BITS_BT_SARAD_CALADDR(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) )
+#define BIT_BT_SARAD_CALEN ( BIT(18) )
+#define BIT_BT_SARAD_CALRD ( BIT(17) )
+#define BIT_BT_SARAD_CAL_RSTN ( BIT(16) )
+#define BIT_BT_SARAD_DLLEN ( BIT(15) )
+#define BITS_BT_SARAD_DLLIN(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_BT_SARAD_DLLOOF(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) )
+#define BIT_BT_SARAD_DLLRD ( BIT(2) )
+#define BIT_BT_SARAD_DLLWR ( BIT(1) )
+#define BIT_BT_SARAD_DLL_RSTN ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_BT_SARADC_CTRL2 */
+#define BITS_BT_SARAD_QUANT_BOOST(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) )
+#define BITS_BT_SARAD_VREF_BOOST(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) )
+#define BITS_BT_SARAD_VREF_SEL(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) )
+#define BITS_BT_SARAD_BIT_SEL(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) )
+#define BITS_BT_SARAD_DELAY_CAP(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) )
+#define BIT_BT_SARAD_VCM_SEL ( BIT(18) )
+#define BIT_BT_SARAD_DIG_CLK_SEL ( BIT(17) )
+#define BIT_BT_SARAD_CAL ( BIT(16) )
+#define BITS_BT_SARAD_RESERVE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_APB_RF_CP2_WBT_DAC_CTRL0 */
+#define BIT_WBT_DAC_SOFT_RST ( BIT(8) )
+#define BITS_WBT_DAC_PCTRL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) )
+#define BITS_WBT_DAC_RESERVE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_APB_RF_CP2_WBT_ANA_STS0 */
+#define BITS_WIFI_SARAD_CALRDOUT(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_WIFI_SARAD_DLL_OUT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+
+/* bits definitions for register REG_APB_RF_CP2_WBT_ANA_STS1 */
+#define BIT_WIFIPLL2_LOCK_DONE ( BIT(21) )
+#define BIT_WIFIPLL1_LOCK_DONE ( BIT(20) )
+#define BITS_BT_SARAD_CALRDOUT(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_BT_SARAD_DLL_OUT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_CTRL0 */
+#define BITS_WIFI_IN_CAP_SWT(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) )
+#define BITS_WIFI_SLEEP_CFG(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
+#define BIT_WB_EN_B_RG ( BIT(2) )
+#define BIT_WB_EN_A_RG ( BIT(1) )
+#define BIT_WB_EN_SEL ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_DAC_DFT */
+#define BITS_WIFI_DAC_DFT(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_ADC_DFT */
+#define BITS_WIFI_ADC_DFT(_X_) (_X_)
+
+#endif
diff --git a/include/soc/sprd/chip_x20/__regs_avs_apb.h b/include/soc/sprd/chip_x20/__regs_avs_apb.h new file mode 100644 index 00000000..e5153c36 --- /dev/null +++ b/include/soc/sprd/chip_x20/__regs_avs_apb.h @@ -0,0 +1,165 @@ +/*
+ * Copyright (C) 2014 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+#ifndef __SCI_GLB_REGS_H__
+#error "Don't include this file directly, Pls include sci_glb_regs.h"
+#endif
+
+
+#ifndef __H_REGS_AVS_APB_HEADFILE_H__
+#define __H_REGS_AVS_APB_HEADFILE_H__ __FILE__
+
+#define REGS_AVS_APB
+
+/* registers definitions for AVS_APB */
+#define REG_AVS_APB_AVS_TUNE_LMT_CFG SCI_ADDR(REGS_AVS_APB_BASE, 0x0000)
+#define REG_AVS_APB_AVS_TUNE_STATUS SCI_ADDR(REGS_AVS_APB_BASE, 0x0004)
+#define REG_AVS_APB_AVS_CFG SCI_ADDR(REGS_AVS_APB_BASE, 0x0008)
+#define REG_AVS_APB_AVS_TUNE_STEP_CFG SCI_ADDR(REGS_AVS_APB_BASE, 0x000C)
+#define REG_AVS_APB_AVS_WAIT_CFG SCI_ADDR(REGS_AVS_APB_BASE, 0x0010)
+#define REG_AVS_APB_AVS_INT_CFG SCI_ADDR(REGS_AVS_APB_BASE, 0x0014)
+#define REG_AVS_APB_AVS_START_SINGLE_ACT SCI_ADDR(REGS_AVS_APB_BASE, 0x0018)
+#define REG_AVS_APB_AVS_START_REPEAT_ACT SCI_ADDR(REGS_AVS_APB_BASE, 0x001C)
+#define REG_AVS_APB_AVS_HPM_EN SCI_ADDR(REGS_AVS_APB_BASE, 0x0020)
+#define REG_AVS_APB_AVS_HPM_RPT_ANLS SCI_ADDR(REGS_AVS_APB_BASE, 0x0024)
+#define REG_AVS_APB_AVS_HPM_RPT_VLD_STATUS_0 SCI_ADDR(REGS_AVS_APB_BASE, 0x0028)
+#define REG_AVS_APB_AVS_HPM_RPT_VLD_STATUS_1 SCI_ADDR(REGS_AVS_APB_BASE, 0x002C)
+#define REG_AVS_APB_AVS_HPM_RPT_VLD_STATUS_2 SCI_ADDR(REGS_AVS_APB_BASE, 0x0030)
+#define REG_AVS_APB_AVS_HPM_RPT_VLD_STATUS_3 SCI_ADDR(REGS_AVS_APB_BASE, 0x0034)
+#define REG_AVS_APB_AVS_HPM_DLY_WIND_SEL SCI_ADDR(REGS_AVS_APB_BASE, 0x0038)
+#define REG_AVS_APB_FSM_STS SCI_ADDR(REGS_AVS_APB_BASE, 0x0040)
+
+
+
+/* bits definitions for register REG_AVS_APB_AVS_TUNE_LMT_CFG */
+#define BITS_VOLT_TUNE_VAL_MAX(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_VOLT_TUNE_VAL_MIN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_AVS_APB_AVS_TUNE_STATUS */
+#define BITS_VOLT_TUNE_VAL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_VOLT_OBS_VAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_AVS_APB_AVS_CFG */
+#define BIT_HPM15_RPT_CHKSUM_ERR_EN ( BIT(31) )
+#define BIT_HPM14_RPT_CHKSUM_ERR_EN ( BIT(30) )
+#define BIT_HPM13_RPT_CHKSUM_ERR_EN ( BIT(29) )
+#define BIT_HPM12_RPT_CHKSUM_ERR_EN ( BIT(28) )
+#define BIT_HPM11_RPT_CHKSUM_ERR_EN ( BIT(27) )
+#define BIT_HPM10_RPT_CHKSUM_ERR_EN ( BIT(26) )
+#define BIT_HPM9_RPT_CHKSUM_ERR_EN ( BIT(25) )
+#define BIT_HPM8_RPT_CHKSUM_ERR_EN ( BIT(24) )
+#define BIT_HPM7_RPT_CHKSUM_ERR_EN ( BIT(23) )
+#define BIT_HPM6_RPT_CHKSUM_ERR_EN ( BIT(22) )
+#define BIT_HPM5_RPT_CHKSUM_ERR_EN ( BIT(21) )
+#define BIT_HPM4_RPT_CHKSUM_ERR_EN ( BIT(20) )
+#define BIT_HPM3_RPT_CHKSUM_ERR_EN ( BIT(19) )
+#define BIT_HPM2_RPT_CHKSUM_ERR_EN ( BIT(18) )
+#define BIT_HPM1_RPT_CHKSUM_ERR_EN ( BIT(17) )
+#define BIT_HPM0_RPT_CHKSUM_ERR_EN ( BIT(16) )
+#define BIT_PAUSE_OCCUR_ERR_EN ( BIT(8) )
+#define BIT_VOLT_TUNE_FORBIDEN ( BIT(4) )
+#define BIT_VOLT_OBS_FORBIDEN ( BIT(0) )
+
+/* bits definitions for register REG_AVS_APB_AVS_TUNE_STEP_CFG */
+#define BITS_VOLT_TUNE_DOWN_STEP(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) )
+#define BITS_VOLT_TUNE_UP_STEP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) )
+
+/* bits definitions for register REG_AVS_APB_AVS_WAIT_CFG */
+#define BITS_RND_INTVAL_WAIT_NUM(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_VOLT_STB_WAIT_NUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_AVS_APB_AVS_INT_CFG */
+#define BIT_INT_RPT_FORMAT_ERR_CLR ( BIT(14) )
+#define BIT_INT_RPT_ANLS_ERR_CLR ( BIT(13) )
+#define BIT_INT_VOLT_TUNE_ERR_CLR ( BIT(12) )
+#define BIT_INT_RPT_FORMAT_ERR_MASK_STATUS ( BIT(10) )
+#define BIT_INT_RPT_ANLS_ERR_MASK_STATUS ( BIT(9) )
+#define BIT_INT_VOLT_TUNE_ERR_MASK_STATUS ( BIT(8) )
+#define BIT_INT_RPT_FORMAT_ERR_RAW_STATUS ( BIT(6) )
+#define BIT_INT_RPT_ANLS_ERR_RAW_STATUS ( BIT(5) )
+#define BIT_INT_VOLT_TUNE_ERR_RAW_STATUS ( BIT(4) )
+#define BIT_INT_RPT_FORMAT_ERR_EN ( BIT(2) )
+#define BIT_INT_RPT_ANLS_ERR_EN ( BIT(1) )
+#define BIT_INT_VOLT_TUNE_ERR_EN ( BIT(0) )
+
+/* bits definitions for register REG_AVS_APB_AVS_START_SINGLE_ACT */
+#define BIT_AVS_START_SINGLE_ACT ( BIT(0) )
+
+/* bits definitions for register REG_AVS_APB_AVS_START_REPEAT_ACT */
+#define BIT_AVS_START_REPEAT_ACT ( BIT(0) )
+
+/* bits definitions for register REG_AVS_APB_AVS_HPM_EN */
+#define BIT_HPM15_EN ( BIT(15) )
+#define BIT_HPM14_EN ( BIT(14) )
+#define BIT_HPM13_EN ( BIT(13) )
+#define BIT_HPM12_EN ( BIT(12) )
+#define BIT_HPM11_EN ( BIT(11) )
+#define BIT_HPM10_EN ( BIT(10) )
+#define BIT_HPM9_EN ( BIT(9) )
+#define BIT_HPM8_EN ( BIT(8) )
+#define BIT_HPM7_EN ( BIT(7) )
+#define BIT_HPM6_EN ( BIT(6) )
+#define BIT_HPM5_EN ( BIT(5) )
+#define BIT_HPM4_EN ( BIT(4) )
+#define BIT_HPM3_EN ( BIT(3) )
+#define BIT_HPM2_EN ( BIT(2) )
+#define BIT_HPM1_EN ( BIT(1) )
+#define BIT_HPM0_EN ( BIT(0) )
+
+/* bits definitions for register REG_AVS_APB_AVS_HPM_RPT_ANLS */
+#define BITS_HPM_RPT_FF_ANLS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_HPM_RPT_7F_ANLS(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) )
+#define BITS_HPM_RPT_3F_ANLS(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) )
+#define BITS_HPM_RPT_1F_ANLS(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
+#define BITS_HPM_RPT_0F_ANLS(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_HPM_RPT_07_ANLS(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) )
+#define BITS_HPM_RPT_03_ANLS(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_HPM_RPT_01_ANLS(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_HPM_RPT_00_ANLS(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_AVS_APB_AVS_HPM_RPT_VLD_STATUS_0 */
+#define BITS_HPM3_RPT_VLD(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_HPM2_RPT_VLD(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_HPM1_RPT_VLD(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_HPM0_RPT_VLD(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_AVS_APB_AVS_HPM_RPT_VLD_STATUS_1 */
+#define BITS_HPM7_RPT_VLD(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_HPM6_RPT_VLD(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_HPM5_RPT_VLD(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_HPM4_RPT_VLD(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_AVS_APB_AVS_HPM_RPT_VLD_STATUS_2 */
+#define BITS_HPM11_RPT_VLD(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_HPM10_RPT_VLD(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_HPM9_RPT_VLD(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_HPM8_RPT_VLD(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_AVS_APB_AVS_HPM_RPT_VLD_STATUS_3 */
+#define BITS_HPM15_RPT_VLD(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_HPM14_RPT_VLD(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_HPM13_RPT_VLD(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_HPM12_RPT_VLD(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_AVS_APB_AVS_HPM_DLY_WIND_SEL */
+#define BITS_DLY_WIND_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_AVS_APB_FSM_STS */
+#define BITS_AVS_FSM_STS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+#endif
diff --git a/include/soc/sprd/chip_x20/__regs_cp_ahb_rf.h b/include/soc/sprd/chip_x20/__regs_cp_ahb_rf.h new file mode 100644 index 00000000..1ed8bbcd --- /dev/null +++ b/include/soc/sprd/chip_x20/__regs_cp_ahb_rf.h @@ -0,0 +1,273 @@ +/*
+ * Copyright (C) 2014 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+#ifndef __SCI_GLB_REGS_H__
+#error "Don't include this file directly, Pls include sci_glb_regs.h"
+#endif
+
+
+#ifndef __H_REGS_CP_AHB_RF_HEADFILE_H__
+#define __H_REGS_CP_AHB_RF_HEADFILE_H__ __FILE__
+
+#define REGS_CP_AHB_RF
+
+/* registers definitions for CP_AHB_RF */
+#define REG_CP_AHB_RF_AHB_EB0_STS SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0008)
+#define REG_CP_AHB_RF_AHB_RST0_STS SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0014)
+#define REG_CP_AHB_RF_ARCH_EB SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0018)
+#define REG_CP_AHB_RF_AHB_REMAP SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x001C)
+#define REG_CP_AHB_RF_AHB_MISC_CTL SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0020)
+#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL0 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0024)
+#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL1 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0028)
+#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL2 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x002C)
+#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL3 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0030)
+#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL4 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0034)
+#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL5 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0038)
+#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL6 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x003C)
+#define REG_CP_AHB_RF_AHB_PAUSE SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0040)
+#define REG_CP_AHB_RF_AHB_SLP_CTL SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0044)
+#define REG_CP_AHB_RF_AHB_SLP_STS SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0048)
+#define REG_CP_AHB_RF_MCU_CLK_CTL SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x004C)
+#define REG_CP_AHB_RF_DSP_CTL SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0050)
+#define REG_CP_AHB_RF_DSP_BOOT_VECTOR SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0054)
+#define REG_CP_AHB_RF_DSP_RST SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0058)
+#define REG_CP_AHB_RF_DSP_JTAG_CTL SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x005C)
+#define REG_CP_AHB_RF_MCU_C2C_SEMA SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0060)
+#define REG_CP_AHB_RF_CHIP_ID SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x01FC)
+
+
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_EB0_STS */
+#define BIT_LZMA_EN ( BIT(11) )
+#define BIT_WCDMA_EN5 ( BIT(9) )
+#define BIT_WCDMA_EN4 ( BIT(8) )
+#define BIT_WCDMA_EN3 ( BIT(7) )
+#define BIT_WCDMA_EN2 ( BIT(6) )
+#define BIT_WCDMA_EN1 ( BIT(5) )
+#define BIT_WCDMA_EN0 ( BIT(4) )
+#define BIT_BUSMON2_EN ( BIT(3) )
+#define BIT_BUSMON1_EN ( BIT(2) )
+#define BIT_BUSMON0_EN ( BIT(1) )
+#define BIT_DMA_EN ( BIT(0) )
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_RST0_STS */
+#define BIT_LZMA_SOFT_RST ( BIT(8) )
+#define BIT_WSYS_SOFT_RST ( BIT(6) )
+#define BIT_ARM2_SOFT_RST ( BIT(5) )
+#define BIT_ARM1_SOFT_RST ( BIT(4) )
+#define BIT_BUSMON2_SOFT_RST ( BIT(3) )
+#define BIT_BUSMON1_SOFT_RST ( BIT(2) )
+#define BIT_BUSMON0_SOFT_RST ( BIT(1) )
+#define BIT_DMA_SOFT_RST ( BIT(0) )
+
+/* bits definitions for register REG_CP_AHB_RF_ARCH_EB */
+#define BIT_AHB_ARCH_EB ( BIT(0) )
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_REMAP */
+#define BIT_PTEST_FUNC_ATSPEED_SEL ( BIT(2) )
+#define BIT_PTEST_FUNC_MODE ( BIT(1) )
+#define BIT_REMAP ( BIT(0) )
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_MISC_CTL */
+#define BITS_LZMA_M_PROT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMA_W_PROT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMA_R_PROT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_MCU_SHM_CTRL(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) )
+#define BIT_RF_SWT_AUTO_EN ( BIT(1) )
+#define BIT_WCDMA_ASHB_EN ( BIT(0) )
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL0 */
+#define BITS_ARMMTX_M3TOS0_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_ARMMTX_M3TOS0_ADJ_EN ( BIT(27) )
+#define BIT_ARMMTX_M3TOS0_RND_EN ( BIT(26) )
+#define BITS_ARMMTX_M3TOS0_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
+#define BITS_ARMMTX_M2TOS0_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BIT_ARMMTX_M2TOS0_ADJ_EN ( BIT(19) )
+#define BIT_ARMMTX_M2TOS0_RND_EN ( BIT(18) )
+#define BITS_ARMMTX_M2TOS0_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_ARMMTX_M1TOS0_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BIT_ARMMTX_M1TOS0_ADJ_EN ( BIT(11) )
+#define BIT_ARMMTX_M1TOS0_RND_EN ( BIT(10) )
+#define BITS_ARMMTX_M1TOS0_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ARMMTX_M0TOS0_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_ARMMTX_M0TOS0_ADJ_EN ( BIT(3) )
+#define BIT_ARMMTX_M0TOS0_RND_EN ( BIT(2) )
+#define BITS_ARMMTX_M0TOS0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL1 */
+#define BITS_ARMMTX_M3TOS1_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_ARMMTX_M3TOS1_ADJ_EN ( BIT(27) )
+#define BIT_ARMMTX_M3TOS1_RND_EN ( BIT(26) )
+#define BITS_ARMMTX_M3TOS1_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
+#define BITS_ARMMTX_M2TOS1_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BIT_ARMMTX_M2TOS1_ADJ_EN ( BIT(19) )
+#define BIT_ARMMTX_M2TOS1_RND_EN ( BIT(18) )
+#define BITS_ARMMTX_M2TOS1_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_ARMMTX_M1TOS1_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BIT_ARMMTX_M1TOS1_ADJ_EN ( BIT(11) )
+#define BIT_ARMMTX_M1TOS1_RND_EN ( BIT(10) )
+#define BITS_ARMMTX_M1TOS1_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ARMMTX_M0TOS1_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_ARMMTX_M0TOS1_ADJ_EN ( BIT(3) )
+#define BIT_ARMMTX_M0TOS1_RND_EN ( BIT(2) )
+#define BITS_ARMMTX_M0TOS1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL2 */
+#define BITS_ARMMTX_M1TOS2_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_ARMMTX_M1TOS2_ADJ_EN ( BIT(27) )
+#define BIT_ARMMTX_M1TOS2_RND_EN ( BIT(26) )
+#define BITS_ARMMTX_M1TOS2_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
+#define BITS_ARMMTX_M0TOS2_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BIT_ARMMTX_M0TOS2_ADJ_EN ( BIT(19) )
+#define BIT_ARMMTX_M0TOS2_RND_EN ( BIT(18) )
+#define BITS_ARMMTX_M0TOS2_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_ARMMTX_M5TOS1_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BIT_ARMMTX_M5TOS1_ADJ_EN ( BIT(11) )
+#define BIT_ARMMTX_M5TOS1_RND_EN ( BIT(10) )
+#define BITS_ARMMTX_M5TOS1_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ARMMTX_M4TOS1_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_ARMMTX_M4TOS1_ADJ_EN ( BIT(3) )
+#define BIT_ARMMTX_M4TOS1_RND_EN ( BIT(2) )
+#define BITS_ARMMTX_M4TOS1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL3 */
+#define BITS_ARMMTX_M5TOS2_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_ARMMTX_M5TOS2_ADJ_EN ( BIT(27) )
+#define BIT_ARMMTX_M5TOS2_RND_EN ( BIT(26) )
+#define BITS_ARMMTX_M5TOS2_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
+#define BITS_ARMMTX_M5TOS4_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BIT_ARMMTX_M5TOS4_ADJ_EN ( BIT(19) )
+#define BIT_ARMMTX_M5TOS4_RND_EN ( BIT(18) )
+#define BITS_ARMMTX_M5TOS4_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_ARMMTX_M3TOS2_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BIT_ARMMTX_M3TOS2_ADJ_EN ( BIT(11) )
+#define BIT_ARMMTX_M3TOS2_RND_EN ( BIT(10) )
+#define BITS_ARMMTX_M3TOS2_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ARMMTX_M2TOS2_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_ARMMTX_M2TOS2_ADJ_EN ( BIT(3) )
+#define BIT_ARMMTX_M2TOS2_RND_EN ( BIT(2) )
+#define BITS_ARMMTX_M2TOS2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL4 */
+#define BITS_ARMMTX_M4TOS3_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BIT_ARMMTX_M4TOS3_ADJ_EN ( BIT(19) )
+#define BIT_ARMMTX_M4TOS3_RND_EN ( BIT(18) )
+#define BITS_ARMMTX_M4TOS3_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_ARMMTX_M1TOS3_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BIT_ARMMTX_M1TOS3_ADJ_EN ( BIT(11) )
+#define BIT_ARMMTX_M1TOS3_RND_EN ( BIT(10) )
+#define BITS_ARMMTX_M1TOS3_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ARMMTX_M0TOS3_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_ARMMTX_M0TOS3_ADJ_EN ( BIT(3) )
+#define BIT_ARMMTX_M0TOS3_RND_EN ( BIT(2) )
+#define BITS_ARMMTX_M0TOS3_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL5 */
+#define BITS_ARMMTX_M4TOS0_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_ARMMTX_M4TOS0_ADJ_EN ( BIT(27) )
+#define BIT_ARMMTX_M4TOS0_RND_EN ( BIT(26) )
+#define BITS_ARMMTX_M4TOS0_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
+#define BITS_ARMMTX_M4TOS4_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BIT_ARMMTX_M4TOS4_ADJ_EN ( BIT(19) )
+#define BIT_ARMMTX_M4TOS4_RND_EN ( BIT(18) )
+#define BITS_ARMMTX_M4TOS4_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_ARMMTX_M1TOS4_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BIT_ARMMTX_M1TOS4_ADJ_EN ( BIT(11) )
+#define BIT_ARMMTX_M1TOS4_RND_EN ( BIT(10) )
+#define BITS_ARMMTX_M1TOS4_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ARMMTX_M0TOS4_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_ARMMTX_M0TOS4_ADJ_EN ( BIT(3) )
+#define BIT_ARMMTX_M0TOS4_RND_EN ( BIT(2) )
+#define BITS_ARMMTX_M0TOS4_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL6 */
+#define BITS_ARMMTX_M3TOS5_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_ARMMTX_M3TOS5_ADJ_EN ( BIT(27) )
+#define BIT_ARMMTX_M3TOS5_RND_EN ( BIT(26) )
+#define BITS_ARMMTX_M3TOS5_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
+#define BITS_ARMMTX_M2TOS5_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BIT_ARMMTX_M2TOS5_ADJ_EN ( BIT(19) )
+#define BIT_ARMMTX_M2TOS5_RND_EN ( BIT(18) )
+#define BITS_ARMMTX_M2TOS5_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_ARMMTX_M1TOS5_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BIT_ARMMTX_M1TOS5_ADJ_EN ( BIT(11) )
+#define BIT_ARMMTX_M1TOS5_RND_EN ( BIT(10) )
+#define BITS_ARMMTX_M1TOS5_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ARMMTX_M0TOS5_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_ARMMTX_M0TOS5_ADJ_EN ( BIT(3) )
+#define BIT_ARMMTX_M0TOS5_RND_EN ( BIT(2) )
+#define BITS_ARMMTX_M0TOS5_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_PAUSE */
+#define BIT_MCU_LIGHT_SLEEP_EN ( BIT(4) )
+#define BIT_APB_SLEEP ( BIT(3) )
+#define BIT_MCU_DEEP_SLEEP_EN ( BIT(2) )
+#define BIT_MCU_SYS_SLEEP_EN ( BIT(1) )
+#define BIT_MCU_CORE_SLEEP ( BIT(0) )
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_SLP_CTL */
+#define BIT_ARM_DAHB_SLEEP_EN ( BIT(4) )
+#define BIT_MCUMTX_AUTO_GATE_EN ( BIT(3) )
+#define BIT_MCU_AUTO_GATE_EN ( BIT(2) )
+#define BIT_AHB_AUTO_GATE_EN ( BIT(1) )
+#define BIT_ARM_AUTO_GATE_EN ( BIT(0) )
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_SLP_STS */
+#define BIT_APB_PERI_SLEEP ( BIT(3) )
+#define BIT_DSP_MAHB_SLEEP_EN ( BIT(2) )
+#define BIT_DMA_BUSY ( BIT(1) )
+#define BIT_EMC_SLEEP ( BIT(0) )
+
+/* bits definitions for register REG_CP_AHB_RF_MCU_CLK_CTL */
+#define BITS_CLK_LZMA_SEL(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)) )
+#define BIT_CLK_CP_DBG_SEL ( BIT(21) )
+#define BIT_CLK_MCU_DBG_SEL ( BIT(20) )
+#define BITS_CLK_COM_DBG_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
+#define BITS_CLK_SYS_DBG_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_CLK_AHB_DIV(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_CLK_MCU_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) )
+#define BITS_CLK_APB_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_CLK_MCU_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
+
+/* bits definitions for register REG_CP_AHB_RF_DSP_CTL */
+#define BIT_ASHB_ARMTODSP_EN ( BIT(2) )
+#define BIT_FRC_CLK_DSP_EN ( BIT(1) )
+#define BIT_DSP_BOOT_EN ( BIT(0) )
+
+/* bits definitions for register REG_CP_AHB_RF_DSP_BOOT_VECTOR */
+#define BITS_DSP_BOOT_VECTOR(_X_) (_X_)
+
+/* bits definitions for register REG_CP_AHB_RF_DSP_RST */
+#define BIT_DSP_SYS_SRST ( BIT(1) )
+#define BIT_DSP_CORE_SRST_N ( BIT(0) )
+
+/* bits definitions for register REG_CP_AHB_RF_DSP_JTAG_CTL */
+#define BIT_CEVA_SW_JTAG_ENA ( BIT(8) )
+#define BIT_STDO ( BIT(4) )
+#define BIT_STCK ( BIT(3) )
+#define BIT_STMS ( BIT(2) )
+#define BIT_STDI ( BIT(1) )
+#define BIT_STRTCK ( BIT(0) )
+
+/* bits definitions for register REG_CP_AHB_RF_MCU_C2C_SEMA */
+#define BITS_MCU_C2C_SEMA(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_CP_AHB_RF_CHIP_ID */
+#define BITS_CHIP_ID(_X_) (_X_)
+
+#endif
diff --git a/include/soc/sprd/chip_x20/__regs_cp_apb_rf.h b/include/soc/sprd/chip_x20/__regs_cp_apb_rf.h new file mode 100644 index 00000000..37a4d057 --- /dev/null +++ b/include/soc/sprd/chip_x20/__regs_cp_apb_rf.h @@ -0,0 +1,203 @@ +/*
+ * Copyright (C) 2014 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+#ifndef __SCI_GLB_REGS_H__
+#error "Don't include this file directly, Pls include sci_glb_regs.h"
+#endif
+
+
+#ifndef __H_REGS_CP_APB_RF_HEADFILE_H__
+#define __H_REGS_CP_APB_RF_HEADFILE_H__ __FILE__
+
+#define REGS_CP_APB_RF
+
+/* registers definitions for CP_APB_RF */
+#define REG_CP_APB_RF_APB_EB0_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0008)
+#define REG_CP_APB_RF_APB_RST0_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0014)
+#define REG_CP_APB_RF_APB_MCU_RST SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0018)
+#define REG_CP_APB_RF_APB_CLK_SEL0 SCI_ADDR(REGS_CP_APB_RF_BASE, 0x001C)
+#define REG_CP_APB_RF_APB_CLK_DIV0 SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0020)
+#define REG_CP_APB_RF_APB_ARCH_EB SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0024)
+#define REG_CP_APB_RF_APB_MISC_CTL0 SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0028)
+#define REG_CP_APB_RF_APB_MISC_CTL1 SCI_ADDR(REGS_CP_APB_RF_BASE, 0x002C)
+#define REG_CP_APB_RF_APB_PIN_SEL SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0040)
+#define REG_CP_APB_RF_APB_SLP_CTL SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0044)
+#define REG_CP_APB_RF_APB_WSYS_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0048)
+#define REG_CP_APB_RF_APB_SLP_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0050)
+#define REG_CP_APB_RF_APB_ROM_PD_CTL SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0054)
+#define REG_CP_APB_RF_APB_BUS_CTL0 SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0058)
+#define REG_CP_APB_RF_APB_DSP_INT_CLR SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0074)
+#define REG_CP_APB_RF_APB_MISC_INT_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0078)
+#define REG_CP_APB_RF_APB_HWRST SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0080)
+#define REG_CP_APB_RF_APB_ARM_BOOT_ADDR SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0084)
+
+
+
+/* bits definitions for register REG_CP_APB_RF_APB_EB0_STS */
+#define BIT_ADA_EB ( BIT(18) )
+#define BIT_RFFE_EB ( BIT(17) )
+#define BIT_EPT_EB ( BIT(16) )
+#define BIT_GPIO_EB ( BIT(15) )
+#define BIT_TMR_RTC_EB ( BIT(14) )
+#define BIT_TMR_EB ( BIT(13) )
+#define BIT_SYSTMR_RTC_EB ( BIT(12) )
+#define BIT_SYSTMR_EB ( BIT(11) )
+#define BIT_IIS3_EB ( BIT(10) )
+#define BIT_IIS2_EB ( BIT(9) )
+#define BIT_IIS1_EB ( BIT(8) )
+#define BIT_IIS0_EB ( BIT(7) )
+#define BIT_SIM2_EB ( BIT(6) )
+#define BIT_SIM1_EB ( BIT(5) )
+#define BIT_SIM0_EB ( BIT(4) )
+#define BIT_UART1_EB ( BIT(3) )
+#define BIT_UART0_EB ( BIT(2) )
+#define BIT_WDG_RTC_EB ( BIT(1) )
+#define BIT_WDG_EB ( BIT(0) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_RST0_STS */
+#define BIT_ADA_TX_SOFT_RST ( BIT(18) )
+#define BIT_ADA_RX_SOFT_RST ( BIT(17) )
+#define BIT_ADA_SOFT_RST ( BIT(16) )
+#define BIT_RFFE_SOFT_RST ( BIT(15) )
+#define BIT_MCU_DSP_RST ( BIT(14) )
+#define BIT_EPT_SOFT_RST ( BIT(13) )
+#define BIT_GPIO_SOFT_RST ( BIT(12) )
+#define BIT_TMR_SOFT_RST ( BIT(11) )
+#define BIT_SYSTMR_SOFT_RST ( BIT(10) )
+#define BIT_IIS3_SOFT_RST ( BIT(9) )
+#define BIT_IIS2_SOFT_RST ( BIT(8) )
+#define BIT_IIS1_SOFT_RST ( BIT(7) )
+#define BIT_IIS0_SOFT_RST ( BIT(6) )
+#define BIT_SIM2_SOFT_RST ( BIT(5) )
+#define BIT_SIM1_SOFT_RST ( BIT(4) )
+#define BIT_SIM0_SOFT_RST ( BIT(3) )
+#define BIT_UART1_SOFT_RST ( BIT(2) )
+#define BIT_UART0_SOFT_RST ( BIT(1) )
+#define BIT_WDG_SOFT_RST ( BIT(0) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_MCU_RST */
+#define BIT_MCU_SOFT_RST_SET ( BIT(0) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_CLK_SEL0 */
+#define BITS_CLK_IIS3_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
+#define BITS_CLK_IIS2_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_CLK_IIS1_SEL(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) )
+#define BITS_CLK_IIS0_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_CLK_UART1_SEL(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_CLK_UART0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_CLK_DIV0 */
+#define BITS_CLK_IIS2_DIV(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
+#define BITS_CLK_IIS1_DIV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)) )
+#define BITS_CLK_IIS0_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
+#define BITS_CLK_UART1_DIV(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) )
+#define BITS_CLK_UART0_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_ARCH_EB */
+#define BITS_CLK_IIS3_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
+#define BIT_RTC_ARCH_EB ( BIT(1) )
+#define BIT_APB_ARCH_EB ( BIT(0) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_MISC_CTL0 */
+#define BIT_ALL_CLK_EN ( BIT(28) )
+#define BIT_DMA_LSLP_EN ( BIT(27) )
+#define BIT_WAKEUP_XTL_EN_3G_W ( BIT(26) )
+#define BIT_WAKEUP_XTL_EN_2G ( BIT(25) )
+#define BIT_ARM_JTAG_EN ( BIT(24) )
+#define BIT_WAKEUP_XTL_EN_3G_TD ( BIT(23) )
+#define BITS_ARM_FRC_STOP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_MISC_CTL1 */
+#define BITS_BUFON_CTRL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) )
+#define BIT_SIM2_CLK_POLARITY ( BIT(3) )
+#define BIT_SIM1_CLK_POLARITY ( BIT(2) )
+#define BIT_SIM0_CLK_POLARITY ( BIT(1) )
+#define BIT_ROM_CLK_EN ( BIT(0) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_PIN_SEL */
+#define BIT_DJTAG_PIN_IN_SEL ( BIT(0) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_SLP_CTL */
+#define BIT_APB_PERI_FRC_ON ( BIT(20) )
+#define BIT_APB_PERI_FRC_SLP ( BIT(16) )
+#define BIT_MCU_XTLEN_AUTOPD_EN ( BIT(12) )
+#define BIT_CHIP_SLP_ARM_CLR ( BIT(4) )
+#define BIT_MCU_FORCE_WSYS_LT_STOP ( BIT(2) )
+#define BIT_MCU_FORCE_WSYS_STOP ( BIT(1) )
+#define BIT_MCU_FORCE_DEEP_SLEEP ( BIT(0) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_WSYS_STS */
+#define BITS_DEEP_SLP_DBG(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_WSYS_STATUS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_SLP_STS */
+#define BIT_DSP_MAHB_SLEEP_EN ( BIT(28) )
+#define BIT_MCU_PERI_STOP ( BIT(27) )
+#define BIT_DSP_PERI_STOP ( BIT(26) )
+#define BIT_ECC_CKG_EN ( BIT(25) )
+#define BIT_QBC_CKG_EN ( BIT(24) )
+#define BIT_DSP_DPLL_EN ( BIT(23) )
+#define BIT_DSP_TDPLL_EN ( BIT(22) )
+#define BIT_DSP_MPLL_EN ( BIT(21) )
+#define BIT_STC_TMR_AUTOPD_XTL_EN ( BIT(20) )
+#define BIT_RFT_TMR_AUTOPD_XTL_EN ( BIT(19) )
+#define BIT_STC_TMR_AUTOPD_RF_EN ( BIT(18) )
+#define BIT_RFT_TMR_AUTOPD_RF_EN ( BIT(17) )
+#define BIT_CHIP_SLEEP_REC_ARM ( BIT(16) )
+#define BIT_DSP_CORE_STOP ( BIT(15) )
+#define BIT_DSP_MTX_STOP ( BIT(14) )
+#define BIT_DSP_AHB_STOP ( BIT(13) )
+#define BIT_DSP_SYS_STOP ( BIT(12) )
+#define BIT_DSP_DEEP_STOP ( BIT(11) )
+#define BIT_ASHB_DSPTOARM_EN ( BIT(10) )
+#define BIT_ASHB_ARMTODSP_VALID ( BIT(9) )
+#define BIT_EMC_STOP_CH3 ( BIT(8) )
+#define BIT_EMC_STOP_CH4 ( BIT(7) )
+#define BIT_EMC_STOP_CH5 ( BIT(6) )
+#define BIT_FRC_WAKE_EN ( BIT(5) )
+#define BIT_TMR_WAKE_AFC ( BIT(4) )
+#define BIT_SCH_SLEEP ( BIT(3) )
+#define BIT_DSP_STOP ( BIT(2) )
+#define BIT_MCU_STOP ( BIT(1) )
+#define BIT_EMC_STOP ( BIT(0) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_ROM_PD_CTL */
+#define BIT_ROM_FORCE_ON ( BIT(0) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_BUS_CTL0 */
+#define BIT_ADA_CTRL_SEL ( BIT(6) )
+#define BIT_RFFE_CTRL_SEL ( BIT(5) )
+#define BIT_IIS3_CTRL_SEL ( BIT(4) )
+#define BIT_IIS2_CTRL_SEL ( BIT(3) )
+#define BIT_IIS1_CTRL_SEL ( BIT(2) )
+#define BIT_IIS0_CTRL_SEL ( BIT(1) )
+#define BIT_UART1_CTRL_SEL ( BIT(0) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_DSP_INT_CLR */
+#define BIT_RFT_INT_CLR ( BIT(2) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_MISC_INT_STS */
+#define BIT_RFT_INT ( BIT(2) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_HWRST */
+#define BITS_HWRST_REG(_X_) (_X_)
+
+/* bits definitions for register REG_CP_APB_RF_APB_ARM_BOOT_ADDR */
+#define BITS_ARMBOOT_ADDR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+#endif
diff --git a/include/soc/sprd/chip_x20/__regs_gpu_apb_rf.h b/include/soc/sprd/chip_x20/__regs_gpu_apb_rf.h new file mode 100644 index 00000000..653b935b --- /dev/null +++ b/include/soc/sprd/chip_x20/__regs_gpu_apb_rf.h @@ -0,0 +1,44 @@ +/* the head file modifier: ang 2015-01-13 20:56:47*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_GPU_APB_HEADFILE_H__ +#define __H_REGS_GPU_APB_HEADFILE_H__ __FILE__ + +#define REGS_GPU_APB + +/* registers definitions for GPU_APB */ +#define REG_GPU_APB_APB_RST SCI_ADDR(REGS_GPU_APB_BASE, 0x0000)/*APB_RST*/ +#define REG_GPU_APB_APB_CLK_CTRL SCI_ADDR(REGS_GPU_APB_BASE, 0x0004)/*APB_CLK_CTRL*/ + + + +/* bits definitions for register REG_GPU_APB_APB_RST */ +#define BIT_GPU_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_GPU_APB_APB_CLK_CTRL */ +#define BITS_CLK_GPU_DIV(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CLK_GPU_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +#endif diff --git a/include/soc/sprd/chip_x20/__regs_mm_ahb_rf.h b/include/soc/sprd/chip_x20/__regs_mm_ahb_rf.h new file mode 100644 index 00000000..57b83d30 --- /dev/null +++ b/include/soc/sprd/chip_x20/__regs_mm_ahb_rf.h @@ -0,0 +1,102 @@ +/* the head file modifier: ang 2015-01-13 20:58:18*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_MM_AHB_HEADFILE_H__ +#define __H_REGS_MM_AHB_HEADFILE_H__ __FILE__ + +#define REGS_MM_AHB + +/* registers definitions for MM_AHB */ +#define REG_MM_AHB_AHB_EB SCI_ADDR(REGS_MM_AHB_BASE, 0x0000)/*AHB_EB*/ +#define REG_MM_AHB_AHB_RST SCI_ADDR(REGS_MM_AHB_BASE, 0x0004)/*AHB_RST*/ +#define REG_MM_AHB_GEN_CKG_CFG SCI_ADDR(REGS_MM_AHB_BASE, 0x0008)/*GEN_CKG_CFG*/ +#define REG_MM_AHB_MIPI_CSI2_CTRL SCI_ADDR(REGS_MM_AHB_BASE, 0x000C)/*MIPI_CSI2_CTRL*/ +#define REG_MM_AHB_MM_QOS_CFG_0 SCI_ADDR(REGS_MM_AHB_BASE, 0x0010)/*MM_QOS_CFG_0*/ +#define REG_MM_AHB_MM_QOS_CFG_1 SCI_ADDR(REGS_MM_AHB_BASE, 0x0014)/*MM_QOS_CFG_1*/ + + + +/* bits definitions for register REG_MM_AHB_AHB_EB */ +#define BIT_VPP_EB ( BIT(8) ) +#define BIT_MMU_EB ( BIT(7) ) +#define BIT_MM_CKG_EB ( BIT(6) ) +#define BIT_JPG_EB ( BIT(5) ) +#define BIT_CSI_EB ( BIT(4) ) +#define BIT_VSP_EB ( BIT(3) ) +#define BIT_ISP_EB ( BIT(2) ) +#define BIT_CCIR_EB ( BIT(1) ) +#define BIT_DCAM_EB ( BIT(0) ) + +/* bits definitions for register REG_MM_AHB_AHB_RST */ +#define BIT_VPP_SOFT_RST ( BIT(15) ) +#define BIT_MMU_SOFT_RST ( BIT(14) ) +#define BIT_MM_CKG_SOFT_RST ( BIT(13) ) +#define BIT_MM_MTX_SOFT_RST ( BIT(12) ) +#define BIT_OR1200_SOFT_RST ( BIT(11) ) +#define BIT_ROT_SOFT_RST ( BIT(10) ) +#define BIT_CAM2_SOFT_RST ( BIT(9) ) +#define BIT_CAM1_SOFT_RST ( BIT(8) ) +#define BIT_CAM0_SOFT_RST ( BIT(7) ) +#define BIT_JPG_SOFT_RST ( BIT(6) ) +#define BIT_CSI_SOFT_RST ( BIT(5) ) +#define BIT_VSP_SOFT_RST ( BIT(4) ) +#define BIT_ISP_CFG_SOFT_RST ( BIT(3) ) +#define BIT_ISP_LOG_SOFT_RST ( BIT(2) ) +#define BIT_CCIR_SOFT_RST ( BIT(1) ) +#define BIT_DCAM_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_MM_AHB_GEN_CKG_CFG */ +#define BIT_VPP_AXI_CKG_EN ( BIT(9) ) +#define BIT_MM_MTX_AXI_CKG_EN ( BIT(8) ) +#define BIT_MM_AXI_CKG_EN ( BIT(7) ) +#define BIT_JPG_AXI_CKG_EN ( BIT(6) ) +#define BIT_VSP_AXI_CKG_EN ( BIT(5) ) +#define BIT_ISP_AXI_CKG_EN ( BIT(4) ) +#define BIT_DCAM_AXI_CKG_EN ( BIT(3) ) +#define BIT_SENSOR_CKG_EN ( BIT(2) ) +#define BIT_MIPI_CSI_CKG_EN ( BIT(1) ) +#define BIT_CPHY_CFG_CKG_EN ( BIT(0) ) + +/* bits definitions for register REG_MM_AHB_MIPI_CSI2_CTRL */ +#define BITS_MIPI_CPHY_SAMPLE_SEL(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)) ) +#define BIT_MIPI_CPHY_SYNC_MODE ( BIT(2) ) +#define BIT_MIPI_CPHY_TEST_CTL ( BIT(1) ) +#define BIT_MIPI_CPHY_SEL ( BIT(0) ) + +/* bits definitions for register REG_MM_AHB_MM_QOS_CFG_0 */ +#define BITS_QOS_R_DCAM(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_QOS_W_DCAM(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_QOS_R_JPG(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_QOS_W_JPG(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_QOS_R_ISP(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_QOS_W_ISP(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_QOS_R_VSP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_QOS_W_VSP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_MM_QOS_CFG_1 */ +#define BITS_QOS_R_VPP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_QOS_W_VPP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +#endif diff --git a/include/soc/sprd/chip_x20/__regs_mm_clk.h b/include/soc/sprd/chip_x20/__regs_mm_clk.h new file mode 100644 index 00000000..6a3d7e65 --- /dev/null +++ b/include/soc/sprd/chip_x20/__regs_mm_clk.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __REGS_MM_CLK_H__ +#define __REGS_MM_CLK_H__ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, include <mach/sci_glb_regs.h>" +#endif + +#define REGS_MM_CLK + +/* registers definitions for controller REGS_MM_CLK */ +#define REG_MM_CLK_MM_AHB_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0020) +#define REG_MM_CLK_SENSOR_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0024) +#define REG_MM_CLK_CCIR_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0028) +#define REG_MM_CLK_DCAM_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x002c) +#define REG_MM_CLK_VSP_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0030) +#define REG_MM_CLK_ISP_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0034) +#define REG_MM_CLK_JPG_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0038) +#define REG_MM_CLK_VPP_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x003C) + +/* vars definitions for controller REGS_MM_CLK */ + +#endif //__REGS_MM_CLK_H__ diff --git a/include/soc/sprd/chip_x20/__regs_pinmap.h b/include/soc/sprd/chip_x20/__regs_pinmap.h new file mode 100755 index 00000000..49ab259a --- /dev/null +++ b/include/soc/sprd/chip_x20/__regs_pinmap.h @@ -0,0 +1,274 @@ +#ifndef __ASM_ARM_ARCH_PINMAP_H +#error "Don't include this file directly, Pls include pinmap.h" +#endif + +#ifndef _REGS_PINMAP_H_ +#define _REGS_PINMAP_H_ + +#define CTL_PIN_BASE (SPRD_PIN_BASE) + +/* registers definitions for controller CTL_PIN */ +#define REG_PIN_CTRL0 ( 0x0000 ) +#define REG_PIN_CTRL1 ( 0x0004 ) +#define REG_PIN_CTRL2 ( 0x0008 ) +#define REG_PIN_CTRL3 ( 0x000c ) +#define REG_PIN_CTRL4 ( 0x0010 ) +#define REG_PIN_CTRL5 ( 0x0014 ) + +#define REG_PIN_TRACECLK ( 0x0020 ) +#define REG_PIN_TRACECTRL ( 0x0024 ) +#define REG_PIN_TRACEDAT0 ( 0x0028 ) +#define REG_PIN_TRACEDAT1 ( 0x002c ) +#define REG_PIN_TRACEDAT2 ( 0x0030 ) +#define REG_PIN_TRACEDAT3 ( 0x0034 ) +#define REG_PIN_TRACEDAT4 ( 0x0038 ) +#define REG_PIN_TRACEDAT5 ( 0x003c ) +#define REG_PIN_TRACEDAT6 ( 0x0040 ) +#define REG_PIN_TRACEDAT7 ( 0x0044 ) +#define REG_PIN_U0TXD ( 0x0048 ) +#define REG_PIN_U0RXD ( 0x004c ) +#define REG_PIN_U0CTS ( 0x0050 ) +#define REG_PIN_U0RTS ( 0x0054 ) +#define REG_PIN_U1TXD ( 0x0058 ) +#define REG_PIN_U1RXD ( 0x005c ) +#define REG_PIN_U2TXD ( 0x0060 ) +#define REG_PIN_U2RXD ( 0x0064 ) +#define REG_PIN_U3TXD ( 0x0068 ) +#define REG_PIN_U3RXD ( 0x006c ) +#define REG_PIN_U3CTS ( 0x0070 ) +#define REG_PIN_U3RTS ( 0x0074 ) +#define REG_PIN_CP2_RFCTL0 ( 0x0078 ) +#define REG_PIN_CP2_RFCTL1 ( 0x007c ) +#define REG_PIN_CP2_RFCTL2 ( 0x0080 ) +#define REG_PIN_WIFI_AGCGAIN3 ( 0x0084 ) +#define REG_PIN_WIFI_AGCGAIN4 ( 0x0088 ) +#define REG_PIN_WIFI_AGCGAIN5 ( 0x008c ) +#define REG_PIN_WIFI_AGCGAIN6 ( 0x0090 ) +#define REG_PIN_RFSDA0 ( 0x0094 ) +#define REG_PIN_RFSCK0 ( 0x0098 ) +#define REG_PIN_RFSEN0 ( 0x009c ) +#define REG_PIN_RFSDA1 ( 0x00a0 ) +#define REG_PIN_RFSCK1 ( 0x00a4 ) +#define REG_PIN_RFSEN1 ( 0x00a8 ) +#define REG_PIN_CP1_RFCTL0 ( 0x00ac ) +#define REG_PIN_CP1_RFCTL1 ( 0x00b0 ) +#define REG_PIN_CP1_RFCTL2 ( 0x00b4 ) +#define REG_PIN_CP1_RFCTL3 ( 0x00b8 ) +#define REG_PIN_CP1_RFCTL4 ( 0x00bc ) +#define REG_PIN_CP1_RFCTL5 ( 0x00c0 ) +#define REG_PIN_CP1_RFCTL6 ( 0x00c4 ) +#define REG_PIN_CP1_RFCTL7 ( 0x00c8 ) +#define REG_PIN_CP1_RFCTL8 ( 0x00cc ) +#define REG_PIN_CP1_RFCTL9 ( 0x00d0 ) +#define REG_PIN_CP1_RFCTL10 ( 0x00d4 ) +#define REG_PIN_CP1_RFCTL11 ( 0x00d8 ) +#define REG_PIN_CP1_RFCTL12 ( 0x00dc ) +#define REG_PIN_CP1_RFCTL13 ( 0x00e0 ) +#define REG_PIN_CP1_RFCTL14 ( 0x00e4 ) +#define REG_PIN_CP1_RFCTL15 ( 0x00e8 ) +#define REG_PIN_CP0_RFCTL0 ( 0x00ec ) +#define REG_PIN_CP0_RFCTL1 ( 0x00f0 ) +#define REG_PIN_CP0_RFCTL2 ( 0x00f4 ) +#define REG_PIN_CP0_RFCTL3 ( 0x00f8 ) +#define REG_PIN_CP0_RFCTL4 ( 0x00fc ) +#define REG_PIN_CP0_RFCTL5 ( 0x0100 ) +#define REG_PIN_CP0_RFCTL6 ( 0x0104 ) +#define REG_PIN_CP0_RFCTL7 ( 0x0108 ) +#define REG_PIN_XTLEN ( 0x010c ) +#define REG_PIN_SCL3 ( 0x0110 ) +#define REG_PIN_SDA3 ( 0x0114 ) +#define REG_PIN_SPI0_CSN ( 0x0118 ) +#define REG_PIN_SPI0_DO ( 0x011c ) +#define REG_PIN_SPI0_DI ( 0x0120 ) +#define REG_PIN_SPI0_CLK ( 0x0124 ) +#define REG_PIN_EXTINT0 ( 0x0128 ) +#define REG_PIN_EXTINT1 ( 0x012c ) +#define REG_PIN_SCL1 ( 0x0130 ) +#define REG_PIN_SDA1 ( 0x0134 ) +#define REG_PIN_SIMCLK0 ( 0x0138 ) +#define REG_PIN_SIMDA0 ( 0x013c ) +#define REG_PIN_SIMRST0 ( 0x0140 ) +#define REG_PIN_SIMCLK1 ( 0x0144 ) +#define REG_PIN_SIMDA1 ( 0x0148 ) +#define REG_PIN_SIMRST1 ( 0x014c ) +#define REG_PIN_SIMCLK2 ( 0x0150 ) +#define REG_PIN_SIMDA2 ( 0x0154 ) +#define REG_PIN_SIMRST2 ( 0x0158 ) +#define REG_PIN_MEMS_MIC_CLK0 ( 0x015c ) +#define REG_PIN_MEMS_MIC_DATA0 ( 0x0160 ) +#define REG_PIN_MEMS_MIC_CLK1 ( 0x0164 ) +#define REG_PIN_MEMS_MIC_DATA1 ( 0x0168 ) +#define REG_PIN_SD1_CLK ( 0x016c ) +#define REG_PIN_SD1_CMD ( 0x0170 ) +#define REG_PIN_SD1_D0 ( 0x0174 ) +#define REG_PIN_SD1_D1 ( 0x0178 ) +#define REG_PIN_SD1_D2 ( 0x017c ) +#define REG_PIN_SD1_D3 ( 0x0180 ) +#define REG_PIN_SD0_D3 ( 0x0184 ) +#define REG_PIN_SD0_D2 ( 0x0188 ) +#define REG_PIN_SD0_CMD ( 0x018c ) +#define REG_PIN_SD0_D0 ( 0x0190 ) +#define REG_PIN_SD0_D1 ( 0x0194 ) +#define REG_PIN_SD0_CLK1 ( 0x0198 ) +#define REG_PIN_SD0_CLK0 ( 0x019c ) +#define REG_PIN_PTEST ( 0x01a0 ) +#define REG_PIN_ANA_INT ( 0x01a4 ) +#define REG_PIN_EXT_RST_B ( 0x01a8 ) +#define REG_PIN_CHIP_SLEEP ( 0x01ac ) +#define REG_PIN_XTL_BUF_EN0 ( 0x01b0 ) +#define REG_PIN_XTL_BUF_EN1 ( 0x01b4 ) +#define REG_PIN_XTL_BUF_EN2 ( 0x01b8 ) +#define REG_PIN_CLK_32K ( 0x01bc ) +#define REG_PIN_AUD_SCLK ( 0x01c0 ) +#define REG_PIN_AUD_DANGL ( 0x01c4 ) +#define REG_PIN_AUD_DANGR ( 0x01c8 ) +#define REG_PIN_AUD_ADD0 ( 0x01cc ) +#define REG_PIN_AUD_ADSYNC ( 0x01d0 ) +#define REG_PIN_AUD_DAD1 ( 0x01d4 ) +#define REG_PIN_AUD_DAD0 ( 0x01d8 ) +#define REG_PIN_AUD_DASYNC ( 0x01dc ) +#define REG_PIN_ADI_D ( 0x01e0 ) +#define REG_PIN_ADI_SYNC ( 0x01e4 ) +#define REG_PIN_ADI_SCLK ( 0x01e8 ) +#define REG_PIN_LCD_CSN1 ( 0x01ec ) +#define REG_PIN_LCD_CSN0 ( 0x01f0 ) +#define REG_PIN_LCD_RSTN ( 0x01f4 ) +#define REG_PIN_LCD_CD ( 0x01f8 ) +#define REG_PIN_LCD_FMARK ( 0x01fc ) +#define REG_PIN_LCD_WRN ( 0x0200 ) +#define REG_PIN_LCD_RDN ( 0x0204 ) +#define REG_PIN_LCD_D0 ( 0x0208 ) +#define REG_PIN_LCD_D1 ( 0x020c ) +#define REG_PIN_LCD_D2 ( 0x0210 ) +#define REG_PIN_LCD_D3 ( 0x0214 ) +#define REG_PIN_LCD_D4 ( 0x0218 ) +#define REG_PIN_LCD_D5 ( 0x021c ) +#define REG_PIN_LCD_D6 ( 0x0220 ) +#define REG_PIN_LCD_D7 ( 0x0224 ) +#define REG_PIN_LCD_D8 ( 0x0228 ) +#define REG_PIN_LCD_D9 ( 0x022c ) +#define REG_PIN_LCD_D10 ( 0x0230 ) +#define REG_PIN_LCD_D11 ( 0x0234 ) +#define REG_PIN_LCD_D12 ( 0x0238 ) +#define REG_PIN_LCD_D13 ( 0x023c ) +#define REG_PIN_LCD_D14 ( 0x0240 ) +#define REG_PIN_LCD_D15 ( 0x0244 ) +#define REG_PIN_LCD_D16 ( 0x0248 ) +#define REG_PIN_LCD_D17 ( 0x024c ) +#define REG_PIN_LCD_D18 ( 0x0250 ) +#define REG_PIN_LCD_D19 ( 0x0254 ) +#define REG_PIN_LCD_D20 ( 0x0258 ) +#define REG_PIN_LCD_D21 ( 0x025c ) +#define REG_PIN_LCD_D22 ( 0x0260 ) +#define REG_PIN_LCD_D23 ( 0x0264 ) +#define REG_PIN_SPI2_CSN ( 0x0268 ) +#define REG_PIN_SPI2_DO ( 0x026c ) +#define REG_PIN_SPI2_DI ( 0x0270 ) +#define REG_PIN_SPI2_CLK ( 0x0274 ) +#define REG_PIN_EMMC_CLK ( 0x0278 ) +#define REG_PIN_EMMC_CMD ( 0x027c ) +#define REG_PIN_EMMC_D0 ( 0x0280 ) +#define REG_PIN_EMMC_D1 ( 0x0284 ) +#define REG_PIN_EMMC_D2 ( 0x0288 ) +#define REG_PIN_EMMC_D3 ( 0x028c ) +#define REG_PIN_EMMC_D4 ( 0x0290 ) +#define REG_PIN_EMMC_D5 ( 0x0294 ) +#define REG_PIN_EMMC_D6 ( 0x0298 ) +#define REG_PIN_EMMC_D7 ( 0x029c ) +#define REG_PIN_EMMC_RST ( 0x02a0 ) +#define REG_PIN_NFWPN ( 0x02a4 ) +#define REG_PIN_NFRB ( 0x02a8 ) +#define REG_PIN_NFCLE ( 0x02ac ) +#define REG_PIN_NFALE ( 0x02b0 ) +#define REG_PIN_NFCEN0 ( 0x02b4 ) +#define REG_PIN_NFCEN1 ( 0x02b8 ) +#define REG_PIN_NFREN ( 0x02bc ) +#define REG_PIN_NFWEN ( 0x02c0 ) +#define REG_PIN_NFD0 ( 0x02c4 ) +#define REG_PIN_NFD1 ( 0x02c8 ) +#define REG_PIN_NFD2 ( 0x02cc ) +#define REG_PIN_NFD3 ( 0x02d0 ) +#define REG_PIN_NFD4 ( 0x02d4 ) +#define REG_PIN_NFD5 ( 0x02d8 ) +#define REG_PIN_NFD6 ( 0x02dc ) +#define REG_PIN_NFD7 ( 0x02e0 ) +#define REG_PIN_NFD8 ( 0x02e4 ) +#define REG_PIN_NFD9 ( 0x02e8 ) +#define REG_PIN_NFD10 ( 0x02ec ) +#define REG_PIN_NFD11 ( 0x02f0 ) +#define REG_PIN_NFD12 ( 0x02f4 ) +#define REG_PIN_NFD13 ( 0x02f8 ) +#define REG_PIN_NFD14 ( 0x02fc ) +#define REG_PIN_NFD15 ( 0x0300 ) +#define REG_PIN_CCIRCK0 ( 0x0304 ) +#define REG_PIN_CCIRCK1 ( 0x0308 ) +#define REG_PIN_CCIRMCLK ( 0x030c ) +#define REG_PIN_CCIRHS ( 0x0310 ) +#define REG_PIN_CCIRVS ( 0x0314 ) +#define REG_PIN_CCIRD0 ( 0x0318 ) +#define REG_PIN_CCIRD1 ( 0x031c ) +#define REG_PIN_CCIRD2 ( 0x0320 ) +#define REG_PIN_CCIRD3 ( 0x0324 ) +#define REG_PIN_CCIRD4 ( 0x0328 ) +#define REG_PIN_CCIRD5 ( 0x032c ) +#define REG_PIN_CCIRD6 ( 0x0330 ) +#define REG_PIN_CCIRD7 ( 0x0334 ) +#define REG_PIN_CCIRD8 ( 0x0338 ) +#define REG_PIN_CCIRD9 ( 0x033c ) +#define REG_PIN_CCIRRST ( 0x0340 ) +#define REG_PIN_CCIRPD1 ( 0x0344 ) +#define REG_PIN_CCIRPD0 ( 0x0348 ) +#define REG_PIN_SCL0 ( 0x034c ) +#define REG_PIN_SDA0 ( 0x0350 ) +#define REG_PIN_KEYOUT0 ( 0x0354 ) +#define REG_PIN_KEYOUT1 ( 0x0358 ) +#define REG_PIN_KEYOUT2 ( 0x035c ) +#define REG_PIN_KEYIN0 ( 0x0360 ) +#define REG_PIN_KEYIN1 ( 0x0364 ) +#define REG_PIN_KEYIN2 ( 0x0368 ) +#define REG_PIN_SCL2 ( 0x036c ) +#define REG_PIN_SDA2 ( 0x0370 ) +#define REG_PIN_CLK_AUX0 ( 0x0374 ) +#define REG_PIN_IIS0DI ( 0x0378 ) +#define REG_PIN_IIS0DO ( 0x037c ) +#define REG_PIN_IIS0CLK ( 0x0380 ) +#define REG_PIN_IIS0LRCK ( 0x0384 ) +#define REG_PIN_IIS0MCK ( 0x0388 ) +#define REG_PIN_IIS1DI ( 0x038c ) +#define REG_PIN_IIS1DO ( 0x0390 ) +#define REG_PIN_IIS1CLK ( 0x0394 ) +#define REG_PIN_IIS1LRCK ( 0x0398 ) +#define REG_PIN_IIS1MCK ( 0x039c ) +#define REG_PIN_MTDO ( 0x03a0 ) +#define REG_PIN_MTDI ( 0x03a4 ) +#define REG_PIN_MTCK ( 0x03a8 ) +#define REG_PIN_MTMS ( 0x03ac ) +#define REG_PIN_MTRST_N ( 0x03b0 ) + + + +/* bits definitions for register REG_PIN_XXX */ +#define BITS_PIN_DS(_x_) ( ((_x_) << 18) & (BIT_18|BIT_19|BIT_20|BIT_21) ) +#define BIT_PIN_SLP_AP ( BIT_13 ) +#define BIT_PIN_SLP_CP0 ( BIT_14 ) +#define BIT_PIN_SLP_CP1 ( BIT_15 ) +#define BIT_PIN_SLP_CP2 ( BIT_16 ) +#define BITS_PIN_SLP(_x_) ( ((_x_) << 13) & (BIT_13|BIT_14|BIT_15|BIT_16) ) +#define BIT_PIN_WPU_SEL ( BIT_12 ) +#define BIT_PIN_WPU ( BIT_7 ) +#define BIT_PIN_WPD ( BIT_6 ) +#define BITS_PIN_AF(_x_) ( ((_x_) << 4) & (BIT_4|BIT_5) ) +#define BIT_PIN_SLP_WPU ( BIT_3 ) +#define BIT_PIN_SLP_WPD ( BIT_2 ) +#define BIT_PIN_SLP_IE ( BIT_1 ) +#define BIT_PIN_SLP_OE ( BIT_0 ) + +/* vars definitions for controller CTL_PIN */ +#define BIT_PIN_NUL ( 0 ) +#define BIT_PIN_SLP_NUL ( 0 ) +#define BIT_PIN_SLP_Z ( 0 ) +#define BIT_PIN_WPU_SEL ( BIT_12 ) +#define BIT_PIN_WPUS ( BIT_12 ) +#define BIT_PIN_NULL ( 0 ) + +#endif diff --git a/include/soc/sprd/chip_x20/__regs_pmu_apb.h b/include/soc/sprd/chip_x20/__regs_pmu_apb.h new file mode 100644 index 00000000..017347f0 --- /dev/null +++ b/include/soc/sprd/chip_x20/__regs_pmu_apb.h @@ -0,0 +1,1032 @@ +/* the head file modifier: ang 2015-01-13 19:49:27*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_PMU_APB_HEADFILE_H__ +#define __H_REGS_PMU_APB_HEADFILE_H__ __FILE__ + +#define REGS_PMU_APB + +/* registers definitions for PMU_APB */ +#define REG_PMU_APB_PD_CA7_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0000)/*PD_CA7_TOP_CFG*/ +#define REG_PMU_APB_PD_CA7_C0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0004)/*PD_CA7_C0_CFG*/ +#define REG_PMU_APB_PD_CA7_C1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0008)/*PD_CA7_C1_CFG*/ +#define REG_PMU_APB_PD_CA7_C2_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x000C)/*PD_CA7_C2_CFG*/ +#define REG_PMU_APB_PD_CA7_C3_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0010)/*PD_CA7_C3_CFG*/ +#define REG_PMU_APB_PD_AP_DISP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0014)/*PD_AP_DISP_CFG*/ +#define REG_PMU_APB_PD_AP_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0018)/*PD_AP_SYS_CFG*/ +#define REG_PMU_APB_PD_MM_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x001C)/*PD_MM_TOP_CFG*/ +#define REG_PMU_APB_PD_GPU_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0020)/*PD_GPU_TOP_CFG*/ +#define REG_PMU_APB_PD_CP0_ARM9_0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0024)/*PD_CP0_ARM9_0_CFG*/ +#define REG_PMU_APB_PD_CP0_ARM9_1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0028)/*PD_CP0_ARM9_1_CFG*/ +#define REG_PMU_APB_PD_CP0_ARM9_2_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x002C)/*PD_CP0_ARM9_2_CFG*/ +#define REG_PMU_APB_PD_CP0_HU3GE_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0030)/*PD_CP0_HU3GE_CFG*/ +#define REG_PMU_APB_PD_CP0_GSM_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0034)/*PD_CP0_GSM_CFG*/ +#define REG_PMU_APB_PD_CP0_TD_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0038)/*PD_CP0_TD_CFG*/ +#define REG_PMU_APB_PD_CP0_CEVA_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x003C)/*PD_CP0_CEVA_CFG*/ +#define REG_PMU_APB_PD_CP0_HARQ_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0040)/*PD_CP0_HARQ_CFG*/ +#define REG_PMU_APB_PD_CP0_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0044)/*PD_CP0_SYS_CFG*/ +#define REG_PMU_APB_PD_CP1_ARM9_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0048)/*PD_CP1_ARM9_CFG*/ +#define REG_PMU_APB_PD_CP1_GSM_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x004C)/*PD_CP1_GSM_CFG*/ +#define REG_PMU_APB_PD_CP1_TD_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0050)/*PD_CP1_TD_CFG*/ +#define REG_PMU_APB_PD_CP1_L1RAM_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0054)/*PD_CP1_L1RAM_CFG*/ +#define REG_PMU_APB_PD_CP1_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0058)/*PD_CP1_SYS_CFG*/ +#define REG_PMU_APB_PD_CP2_ARM9_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x005C)/*PD_CP2_ARM9_CFG*/ +#define REG_PMU_APB_PD_CP2_WIFI_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0060)/*PD_CP2_WIFI_CFG*/ +#define REG_PMU_APB_AP_WAKEUP_POR_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0064)/*AP_WAKEUP_POR_CFG*/ +#define REG_PMU_APB_PD_CP2_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0068)/*PD_CP2_SYS_CFG*/ +#define REG_PMU_APB_PD_PUB_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x006C)/*PD_PUB_SYS_CFG*/ +#define REG_PMU_APB_XTL_WAIT_CNT SCI_ADDR(REGS_PMU_APB_BASE, 0x0070)/*XTL_WAIT_CNT*/ +#define REG_PMU_APB_XTLBUF_WAIT_CNT SCI_ADDR(REGS_PMU_APB_BASE, 0x0074)/*XTLBUF_WAIT_CNT*/ +#define REG_PMU_APB_PLL_WAIT_CNT1 SCI_ADDR(REGS_PMU_APB_BASE, 0x0078)/*PLL_WAIT_CNT1*/ +#define REG_PMU_APB_PLL_WAIT_CNT2 SCI_ADDR(REGS_PMU_APB_BASE, 0x007C)/*PLL_WAIT_CNT2*/ +#define REG_PMU_APB_XTL0_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0080)/*XTL0_REL_CFG*/ +#define REG_PMU_APB_XTL1_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0084)/*XTL1_REL_CFG*/ +#define REG_PMU_APB_XTL2_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0088)/*XTL1_REL_CFG*/ +#define REG_PMU_APB_XTLBUF0_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x008C)/*XTLBUF0_REL_CFG*/ +#define REG_PMU_APB_XTLBUF1_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0090)/*XTLBUF1_REL_CFG*/ +#define REG_PMU_APB_MPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0094)/*MPLL_REL_CFG*/ +#define REG_PMU_APB_DPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0098)/*DPLL_REL_CFG*/ +#define REG_PMU_APB_TDPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x009C)/*TDPLL_REL_CFG*/ +#define REG_PMU_APB_WPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00A0)/*WPLL_REL_CFG*/ +#define REG_PMU_APB_CPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00A4)/*CPLL_REL_CFG*/ +#define REG_PMU_APB_WIFIPLL1_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00A8)/*WIFIPLL1_REL_CFG*/ +#define REG_PMU_APB_WIFIPLL2_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00AC)/*WIFIPLL2_REL_CFG*/ +#define REG_PMU_APB_CP_SOFT_RST SCI_ADDR(REGS_PMU_APB_BASE, 0x00B0)/*CP_SOFT_RST*/ +#define REG_PMU_APB_CP_SLP_STATUS_DBG0 SCI_ADDR(REGS_PMU_APB_BASE, 0x00B4)/*CP_SLP_STATUS_DBG0*/ +#define REG_PMU_APB_CP_SLP_STATUS_DBG1 SCI_ADDR(REGS_PMU_APB_BASE, 0x00B8)/*CP_SLP_STATUS_DBG1*/ +#define REG_PMU_APB_PWR_STATUS0_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00BC)/*PWR_STATUS0_DBG*/ +#define REG_PMU_APB_PWR_STATUS1_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00C0)/*PWR_STATUS1_DBG*/ +#define REG_PMU_APB_PWR_STATUS2_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00C4)/*PWR_STATUS2_DBG*/ +#define REG_PMU_APB_PWR_STATUS3_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00C8)/*PWR_STATUS3_DBG*/ +#define REG_PMU_APB_SLEEP_CTRL SCI_ADDR(REGS_PMU_APB_BASE, 0x00CC)/*SLEEP_CTRL*/ +#define REG_PMU_APB_DDR_SLEEP_CTRL SCI_ADDR(REGS_PMU_APB_BASE, 0x00D0)/*DDR_SLEEP_CTRL*/ +#define REG_PMU_APB_SLEEP_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x00D4)/*SLEEP_STATUS*/ +#define REG_PMU_APB_PLL_DIV_AUTO_GATE_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x00D8)/*PLL_DIV_AUTO_GATE_EN*/ +#define REG_PMU_APB_PLL_DIV_EN1 SCI_ADDR(REGS_PMU_APB_BASE, 0x00DC)/*PLL_DIV_EN1*/ +#define REG_PMU_APB_PLL_DIV_EN2 SCI_ADDR(REGS_PMU_APB_BASE, 0x00E0)/*PLL_DIV_EN2*/ +#define REG_PMU_APB_CA7_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00E4)/*CA7_TOP_CFG*/ +#define REG_PMU_APB_CA7_C0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00E8)/*CA7_C0_CFG*/ +#define REG_PMU_APB_CA7_C1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00EC)/*CA7_C1_CFG*/ +#define REG_PMU_APB_CA7_C2_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00F0)/*CA7_C2_CFG*/ +#define REG_PMU_APB_CA7_C3_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00F4)/*CA7_C3_CFG*/ +#define REG_PMU_APB_DDR_CHN_SLEEP_CTRL0 SCI_ADDR(REGS_PMU_APB_BASE, 0x00F8)/*DDR_CHN_SLEEP_CTRL0*/ +#define REG_PMU_APB_DDR_CHN_SLEEP_CTRL1 SCI_ADDR(REGS_PMU_APB_BASE, 0x00FC)/*DDR_CHN_SLEEP_CTRL1*/ +#define REG_PMU_APB_BISR_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0100)/*BISR_CFG*/ +#define REG_PMU_APB_CGM_AP_AUTO_GATE_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0104)/*CGM_AP_AUTO_GATE_EN*/ +#define REG_PMU_APB_CGM_GPU_MM_AUTO_GATE_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0108)/*CGM_GPU_MM_AUTO_GATE_EN*/ +#define REG_PMU_APB_CGM_CP0_AUTO_GATE_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x010C)/*CGM_CP0_AUTO_GATE_EN*/ +#define REG_PMU_APB_CGM_CP1_AUTO_GATE_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0110)/*CGM_CP1_AUTO_GATE_EN*/ +#define REG_PMU_APB_CGM_CP2_AUTO_GATE_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0114)/*CGM_CP2_AUTO_GATE_EN*/ +#define REG_PMU_APB_CGM_AP_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0118)/*CGM_AP_EN*/ +#define REG_PMU_APB_CGM_GPU_MM_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x011C)/*CGM_GPU_MM_EN*/ +#define REG_PMU_APB_CGM_CP0_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0120)/*CGM_CP0_EN*/ +#define REG_PMU_APB_CGM_CP1_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0124)/*CGM_CP1_EN*/ +#define REG_PMU_APB_CGM_CP2_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0128)/*CGM_CP2_EN*/ +#define REG_PMU_APB_DDR_OP_MODE_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x012C)/*DDR_OP_MODE_CFG*/ +#define REG_PMU_APB_DDR_PHY_RET_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0130)/*DDR_PHY_RET_CFG*/ +#define REG_PMU_APB_26M_SEL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0134)/*26M_SEL_CFG*/ +#define REG_PMU_APB_MEM_PD_CFG0 SCI_ADDR(REGS_PMU_APB_BASE, 0x0138)/*MEM_PD_CFG0*/ +#define REG_PMU_APB_MEM_PD_CFG1 SCI_ADDR(REGS_PMU_APB_BASE, 0x013C)/*MEM_PD_CFG1*/ +#define REG_PMU_APB_PD_DDR_PUBL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0140)/*PD_DDR_PUBL_CFG*/ +#define REG_PMU_APB_PD_DDR_PHY_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0144)/*PD_DDR_PHY_CFG*/ +#define REG_PMU_APB_BISR_CFG2 SCI_ADDR(REGS_PMU_APB_BASE, 0x0148)/*BISR_CFG2*/ +#define REG_PMU_APB_DEBUG_PD0 SCI_ADDR(REGS_PMU_APB_BASE, 0x014C)/*DEBUG_PD0*/ +#define REG_PMU_APB_DEBUG_PD1 SCI_ADDR(REGS_PMU_APB_BASE, 0x0150)/*DEBUG_PD1*/ +#define REG_PMU_APB_DEBUG_PD2 SCI_ADDR(REGS_PMU_APB_BASE, 0x0154)/*DEBUG_PD2*/ +#define REG_PMU_APB_DEBUG_PD3 SCI_ADDR(REGS_PMU_APB_BASE, 0x0158)/*DEBUG_PD3*/ +#define REG_PMU_APB_INT_DISABLE SCI_ADDR(REGS_PMU_APB_BASE, 0x015C)/*INT_DIABLE*/ +#define REG_PMU_APB_PMU_DEBUG_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0160)/*PMU_DEBUG_CFG*/ + + + +/* bits definitions for register REG_PMU_APB_PD_CA7_TOP_CFG */ +#define BIT_PD_CA7_TOP_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_PD_CA7_TOP_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CA7_TOP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA7_TOP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA7_C0_CFG */ +#define BIT_PD_CA7_C0_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_PD_CA7_C0_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CA7_C0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA7_C0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA7_C1_CFG */ +#define BIT_PD_CA7_C1_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_PD_CA7_C1_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA7_C1_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CA7_C1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA7_C1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA7_C2_CFG */ +#define BIT_PD_CA7_C2_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_PD_CA7_C2_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA7_C2_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CA7_C2_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA7_C2_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA7_C3_CFG */ +#define BIT_PD_CA7_C3_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_PD_CA7_C3_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA7_C3_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CA7_C3_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA7_C3_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_AP_DISP_CFG */ + +/* bits definitions for register REG_PMU_APB_PD_AP_SYS_CFG */ +#define BIT_PD_AP_SYS_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_AP_SYS_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_AP_SYS_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_MM_TOP_CFG */ +#define BIT_PD_MM_TOP_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_MM_TOP_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_MM_TOP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_MM_TOP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_GPU_TOP_CFG */ +#define BIT_PD_GPU_TOP_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_GPU_TOP_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_GPU_TOP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_GPU_TOP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_0_CFG */ +#define BIT_PD_CP0_ARM9_0_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_ARM9_0_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_ARM9_0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_ARM9_0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_ARM9_0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_1_CFG */ +#define BIT_PD_CP0_ARM9_1_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_ARM9_1_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_ARM9_1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_ARM9_1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_ARM9_1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_2_CFG */ +#define BIT_PD_CP0_ARM9_2_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_ARM9_2_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_ARM9_2_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_ARM9_2_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_ARM9_2_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_HU3GE_CFG */ +#define BIT_PD_CP0_HU3GE_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_HU3GE_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_HU3GE_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_HU3GE_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_HU3GE_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_GSM_CFG */ +#define BIT_PD_CP0_GSM_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_GSM_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_GSM_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_GSM_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_GSM_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_TD_CFG */ +#define BIT_PD_CP0_TD_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_TD_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_TD_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_TD_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_TD_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_CEVA_CFG */ +#define BIT_PD_CP0_CEVA_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_CEVA_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_CEVA_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_CEVA_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_CEVA_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_HARQ_CFG */ +#define BIT_PD_CP0_HARQ_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_HARQ_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_HARQ_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_HARQ_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_HARQ_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_SYS_CFG */ +#define BIT_CP0_FORCE_DEEP_SLEEP ( BIT(28) ) +#define BIT_PD_CP0_SYS_FORCE_SHUTDOWN ( BIT(25) ) +#define BITS_PD_CP0_SYS_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_SYS_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_SYS_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_ARM9_CFG */ +#define BIT_PD_CP1_ARM9_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP1_ARM9_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP1_ARM9_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_ARM9_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_ARM9_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_GSM_CFG */ +#define BIT_PD_CP1_GSM_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP1_GSM_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP1_GSM_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_GSM_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_GSM_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_TD_CFG */ +#define BIT_PD_CP1_TD_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP1_TD_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP1_TD_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_TD_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_TD_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_L1RAM_CFG */ +#define BIT_PD_CP1_L1RAM_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP1_L1RAM_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP1_L1RAM_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_L1RAM_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_L1RAM_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_SYS_CFG */ +#define BIT_CP1_FORCE_DEEP_SLEEP ( BIT(28) ) +#define BIT_PD_CP1_SYS_FORCE_SHUTDOWN ( BIT(25) ) +#define BITS_PD_CP1_SYS_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_SYS_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_SYS_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP2_ARM9_CFG */ +#define BIT_PD_CP2_ARM9_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP2_ARM9_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP2_ARM9_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP2_ARM9_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP2_ARM9_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP2_WIFI_CFG */ +#define BIT_PD_CP2_WIFI_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP2_WIFI_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP2_WIFI_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP2_WIFI_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP2_WIFI_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_AP_WAKEUP_POR_CFG */ +#define BIT_AP_WAKEUP_POR_N ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_PD_CP2_SYS_CFG */ +#define BIT_CP2_FORCE_DEEP_SLEEP ( BIT(28) ) +#define BIT_PD_CP2_SYS_FORCE_SHUTDOWN ( BIT(25) ) +#define BITS_PD_CP2_SYS_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP2_SYS_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP2_SYS_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_PUB_SYS_CFG */ +#define BIT_PD_PUB_SYS_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_PUB_SYS_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_PUB_SYS_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_XTL_WAIT_CNT */ +#define BITS_XTL1_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_XTL0_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_XTLBUF_WAIT_CNT */ +#define BITS_XTLBUF1_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_XTLBUF0_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PLL_WAIT_CNT1 */ +#define BITS_WPLL_WAIT_CNT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_TDPLL_WAIT_CNT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DPLL_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_MPLL_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PLL_WAIT_CNT2 */ +#define BITS_WIFIPLL2_WAIT_CNT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_WIFIPLL1_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_CPLL_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_XTL0_REL_CFG */ +#define BIT_XTL0_CP2_SEL ( BIT(3) ) +#define BIT_XTL0_CP1_SEL ( BIT(2) ) +#define BIT_XTL0_CP0_SEL ( BIT(1) ) +#define BIT_XTL0_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_XTL1_REL_CFG */ +#define BIT_XTL1_CP2_SEL ( BIT(3) ) +#define BIT_XTL1_CP1_SEL ( BIT(2) ) +#define BIT_XTL1_CP0_SEL ( BIT(1) ) +#define BIT_XTL1_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_XTL2_REL_CFG */ +#define BIT_XTL2_CP2_SEL ( BIT(3) ) +#define BIT_XTL2_CP1_SEL ( BIT(2) ) +#define BIT_XTL2_CP0_SEL ( BIT(1) ) +#define BIT_XTL2_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_XTLBUF0_REL_CFG */ +#define BIT_XTLBUF0_CP2_SEL ( BIT(3) ) +#define BIT_XTLBUF0_CP1_SEL ( BIT(2) ) +#define BIT_XTLBUF0_CP0_SEL ( BIT(1) ) +#define BIT_XTLBUF0_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_XTLBUF1_REL_CFG */ +#define BIT_XTLBUF1_CP2_SEL ( BIT(3) ) +#define BIT_XTLBUF1_CP1_SEL ( BIT(2) ) +#define BIT_XTLBUF1_CP0_SEL ( BIT(1) ) +#define BIT_XTLBUF1_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_MPLL_REL_CFG */ +#define BIT_MPLL_REF_SEL ( BIT(4) ) +#define BIT_MPLL_CP2_SEL ( BIT(3) ) +#define BIT_MPLL_CP1_SEL ( BIT(2) ) +#define BIT_MPLL_CP0_SEL ( BIT(1) ) +#define BIT_MPLL_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_DPLL_REL_CFG */ +#define BIT_DPLL_REF_SEL ( BIT(4) ) +#define BIT_DPLL_CP2_SEL ( BIT(3) ) +#define BIT_DPLL_CP1_SEL ( BIT(2) ) +#define BIT_DPLL_CP0_SEL ( BIT(1) ) +#define BIT_DPLL_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_TDPLL_REL_CFG */ +#define BIT_TDPLL_REF_SEL ( BIT(4) ) +#define BIT_TDPLL_CP2_SEL ( BIT(3) ) +#define BIT_TDPLL_CP1_SEL ( BIT(2) ) +#define BIT_TDPLL_CP0_SEL ( BIT(1) ) +#define BIT_TDPLL_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_WPLL_REL_CFG */ +#define BIT_WPLL_REF_SEL ( BIT(4) ) +#define BIT_WPLL_CP2_SEL ( BIT(3) ) +#define BIT_WPLL_CP1_SEL ( BIT(2) ) +#define BIT_WPLL_CP0_SEL ( BIT(1) ) +#define BIT_WPLL_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CPLL_REL_CFG */ +#define BIT_CPLL_REF_SEL ( BIT(4) ) +#define BIT_CPLL_CP2_SEL ( BIT(3) ) +#define BIT_CPLL_CP1_SEL ( BIT(2) ) +#define BIT_CPLL_CP0_SEL ( BIT(1) ) +#define BIT_CPLL_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_WIFIPLL1_REL_CFG */ +#define BIT_WIFIPLL1_REF_SEL ( BIT(4) ) +#define BIT_WIFIPLL1_CP2_SEL ( BIT(3) ) +#define BIT_WIFIPLL1_CP1_SEL ( BIT(2) ) +#define BIT_WIFIPLL1_CP0_SEL ( BIT(1) ) +#define BIT_WIFIPLL1_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_WIFIPLL2_REL_CFG */ +#define BIT_WIFIPLL2_REF_SEL ( BIT(4) ) +#define BIT_WIFIPLL2_CP2_SEL ( BIT(3) ) +#define BIT_WIFIPLL2_CP1_SEL ( BIT(2) ) +#define BIT_WIFIPLL2_CP0_SEL ( BIT(1) ) +#define BIT_WIFIPLL2_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CP_SOFT_RST */ +#define BIT_PUB_SOFT_RST ( BIT(6) ) +#define BIT_AP_SOFT_RST ( BIT(5) ) +#define BIT_GPU_SOFT_RST ( BIT(4) ) +#define BIT_MM_SOFT_RST ( BIT(3) ) +#define BIT_CP2_SOFT_RST ( BIT(2) ) +#define BIT_CP1_SOFT_RST ( BIT(1) ) +#define BIT_CP0_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CP_SLP_STATUS_DBG0 */ +#define BITS_CP1_DEEP_SLP_DBG(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_CP0_DEEP_SLP_DBG(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_PMU_APB_CP_SLP_STATUS_DBG1 */ +#define BITS_CP2_DEEP_SLP_DBG(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_PMU_APB_PWR_STATUS0_DBG */ +#define BITS_PD_MM_TOP_STATE(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_PD_GPU_TOP_STATE(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_PD_CA7_C3_STATE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_PD_CA7_C2_STATE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA7_C1_STATE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_PD_CA7_C0_STATE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_PD_CA7_TOP_STATE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PWR_STATUS1_DBG */ +#define BITS_PD_CP0_SYS_STATE(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_PD_CP0_GSM_STATE(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_HU3GE_STATE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_PD_CP0_ARM9_2_STATE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_ARM9_1_STATE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_PD_CP0_ARM9_0_STATE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_PD_AP_SYS_STATE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PWR_STATUS2_DBG */ +#define BITS_PD_CP2_WIFI_STATE(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_PD_CP2_ARM9_STATE(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_SYS_STATE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_PD_CP1_L1RAM_STATE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_TD_STATE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_PD_CP1_GSM_STATE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_PD_CP1_ARM9_STATE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PWR_STATUS3_DBG */ +#define BITS_PD_CP0_HARQ_STATE(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_PD_CP0_CEVA_STATE(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_TD_STATE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_PD_DDR_PHY_STATE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_DDR_PUBL_STATE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_PD_PUB_SYS_STATE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_PD_CP2_SYS_STATE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_SLEEP_CTRL */ +#define BIT_CP0_FORCE_SLEEP ( BIT(12) ) +#define BIT_CP2_SLEEP_XTL_ON ( BIT(11) ) +#define BIT_CP1_SLEEP_XTL_ON ( BIT(10) ) +#define BIT_CP0_SLEEP_XTL_ON ( BIT(9) ) +#define BIT_AP_SLEEP_XTL_ON ( BIT(8) ) +#define BIT_DISP_DEEP_SLEEP ( BIT(6) ) +#define BIT_GPU_DEEP_SLEEP ( BIT(5) ) +#define BIT_MM_DEEP_SLEEP ( BIT(4) ) +#define BIT_CP2_DEEP_SLEEP ( BIT(3) ) +#define BIT_CP1_DEEP_SLEEP ( BIT(2) ) +#define BIT_CP0_DEEP_SLEEP ( BIT(1) ) +#define BIT_AP_DEEP_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_DDR_SLEEP_CTRL */ +#define BIT_DDR_PUBL_APB_SOFT_RST ( BIT(12) ) +#define BIT_DDR_UMCTL_APB_SOFT_RST ( BIT(11) ) +#define BIT_DDR_PUBL_SOFT_RST ( BIT(10) ) +#define BIT_DDR_UMCTL_SOFT_RST ( BIT(9) ) +#define BIT_DDR_PHY_SOFT_RST ( BIT(8) ) +#define BIT_DDR_PHY_AUTO_GATE_EN ( BIT(6) ) +#define BIT_DDR_PUBL_AUTO_GATE_EN ( BIT(5) ) +#define BIT_DDR_UMCTL_AUTO_GATE_EN ( BIT(4) ) +#define BIT_DDR_PHY_EB ( BIT(2) ) +#define BIT_DDR_UMCTL_EB ( BIT(1) ) +#define BIT_DDR_PUBL_EB ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_SLEEP_STATUS */ +#define BITS_CP2_SLP_STATUS(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_CP1_SLP_STATUS(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CP0_SLP_STATUS(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_AP_SLP_STATUS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PLL_DIV_AUTO_GATE_EN */ +#define BIT_WIFIPLL2_DIV_AUTO_GATE_EN ( BIT(6) ) +#define BIT_WIFIPLL1_DIV_AUTO_GATE_EN ( BIT(5) ) +#define BIT_WPLL_DIV_AUTO_GATE_EN ( BIT(4) ) +#define BIT_TDPLL_DIV_AUTO_GATE_EN ( BIT(3) ) +#define BIT_CPLL_DIV_AUTO_GATE_EN ( BIT(2) ) +#define BIT_DPLL_DIV_AUTO_GATE_EN ( BIT(1) ) +#define BIT_MPLL_DIV_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_PLL_DIV_EN1 */ +#define BIT_WIFIPLL2_80M_EN ( BIT(31) ) +#define BIT_WIFIPLL2_160M_EN ( BIT(30) ) +#define BIT_WIFIPLL2_120M_EN ( BIT(29) ) +#define BIT_WIFIPLL1_20M_EN ( BIT(28) ) +#define BIT_WIFIPLL1_40M_EN ( BIT(27) ) +#define BIT_WIFIPLL1_80M_EN ( BIT(26) ) +#define BIT_WIFIPLL1_44M_EN ( BIT(25) ) +#define BIT_WPLL_76M8_EN ( BIT(24) ) +#define BIT_WPLL_51M2_EN ( BIT(23) ) +#define BIT_WPLL_102M4_EN ( BIT(22) ) +#define BIT_WPLL_307M2_EN ( BIT(21) ) +#define BIT_WPLL_460M8_EN ( BIT(20) ) +#define BIT_CPLL_52M_EN ( BIT(19) ) +#define BIT_CPLL_104M_EN ( BIT(18) ) +#define BIT_CPLL_208M_EN ( BIT(17) ) +#define BIT_CPLL_312M_EN ( BIT(16) ) +#define BIT_TDPLL_38M4_EN ( BIT(15) ) +#define BIT_TDPLL_76M8_EN ( BIT(14) ) +#define BIT_TDPLL_51M2_EN ( BIT(13) ) +#define BIT_TDPLL_153M6_EN ( BIT(12) ) +#define BIT_TDPLL_64M_EN ( BIT(11) ) +#define BIT_TDPLL_128M_EN ( BIT(10) ) +#define BIT_TDPLL_256M_EN ( BIT(9) ) +#define BIT_TDPLL_12M_EN ( BIT(8) ) +#define BIT_TDPLL_24M_EN ( BIT(7) ) +#define BIT_TDPLL_48M_EN ( BIT(6) ) +#define BIT_TDPLL_96M_EN ( BIT(5) ) +#define BIT_TDPLL_192M_EN ( BIT(4) ) +#define BIT_TDPLL_384M_EN ( BIT(3) ) +#define BIT_DPLL_44M_EN ( BIT(2) ) +#define BIT_MPLL_37M5_EN ( BIT(1) ) +#define BIT_MPLL_300M_EN ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_PLL_DIV_EN2 */ +#define BIT_DPLL_533M_EN ( BIT(2) ) +#define BIT_WIFIPLL2_20M_EN ( BIT(1) ) +#define BIT_WIFIPLL2_40M_EN ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CA7_TOP_CFG */ +#define BIT_CA7_L2RSTDISABLE ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CA7_C0_CFG */ +#define BIT_CA7_VINITHI_C0 ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CA7_C1_CFG */ +#define BIT_CA7_VINITHI_C1 ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CA7_C2_CFG */ +#define BIT_CA7_VINITHI_C2 ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CA7_C3_CFG */ +#define BIT_CA7_VINITHI_C3 ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_DDR_CHN_SLEEP_CTRL0 */ +#define BIT_DDR_CTRL_AXI_LP_EN ( BIT(31) ) +#define BIT_DDR_CTRL_CGM_SEL ( BIT(30) ) +#define BIT_DDR_CHN9_AXI_LP_EN ( BIT(25) ) +#define BIT_DDR_CHN8_AXI_LP_EN ( BIT(24) ) +#define BIT_DDR_CHN7_AXI_LP_EN ( BIT(23) ) +#define BIT_DDR_CHN6_AXI_LP_EN ( BIT(22) ) +#define BIT_DDR_CHN5_AXI_LP_EN ( BIT(21) ) +#define BIT_DDR_CHN4_AXI_LP_EN ( BIT(20) ) +#define BIT_DDR_CHN3_AXI_LP_EN ( BIT(19) ) +#define BIT_DDR_CHN2_AXI_LP_EN ( BIT(18) ) +#define BIT_DDR_CHN1_AXI_LP_EN ( BIT(17) ) +#define BIT_DDR_CHN0_AXI_LP_EN ( BIT(16) ) +#define BIT_DDR_CHN9_CGM_SEL ( BIT(9) ) +#define BIT_DDR_CHN8_CGM_SEL ( BIT(8) ) +#define BIT_DDR_CHN7_CGM_SEL ( BIT(7) ) +#define BIT_DDR_CHN6_CGM_SEL ( BIT(6) ) +#define BIT_DDR_CHN5_CGM_SEL ( BIT(5) ) +#define BIT_DDR_CHN4_CGM_SEL ( BIT(4) ) +#define BIT_DDR_CHN3_CGM_SEL ( BIT(3) ) +#define BIT_DDR_CHN2_CGM_SEL ( BIT(2) ) +#define BIT_DDR_CHN1_CGM_SEL ( BIT(1) ) +#define BIT_DDR_CHN0_CGM_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_DDR_CHN_SLEEP_CTRL1 */ +#define BIT_DDR_CHN9_AXI_STOP_SEL ( BIT(9) ) +#define BIT_DDR_CHN8_AXI_STOP_SEL ( BIT(8) ) +#define BIT_DDR_CHN7_AXI_STOP_SEL ( BIT(7) ) +#define BIT_DDR_CHN6_AXI_STOP_SEL ( BIT(6) ) +#define BIT_DDR_CHN5_AXI_STOP_SEL ( BIT(5) ) +#define BIT_DDR_CHN4_AXI_STOP_SEL ( BIT(4) ) +#define BIT_DDR_CHN3_AXI_STOP_SEL ( BIT(3) ) +#define BIT_DDR_CHN2_AXI_STOP_SEL ( BIT(2) ) +#define BIT_DDR_CHN1_AXI_STOP_SEL ( BIT(1) ) +#define BIT_DDR_CHN0_AXI_STOP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_BISR_CFG */ +#define BIT_PD_CP0_CEVA_BISR_DONE ( BIT(31) ) +#define BIT_PD_CP0_TD_BISR_DONE ( BIT(30) ) +#define BIT_PD_CP1_TD_BISR_DONE ( BIT(29) ) +#define BIT_PD_CP1_SYS_BISR_DONE ( BIT(28) ) +#define BIT_PD_CP0_HU3GE_BISR_DONE ( BIT(27) ) +#define BIT_PD_CP0_SYS_BISR_DONE ( BIT(26) ) +#define BIT_PD_MM_TOP_BISR_DONE ( BIT(25) ) +#define BIT_PD_GPU_TOP_BISR_DONE ( BIT(24) ) +#define BIT_PD_CP0_CEVA_BISR_BUSY ( BIT(23) ) +#define BIT_PD_CP0_TD_BISR_BUSY ( BIT(22) ) +#define BIT_PD_CP1_TD_BISR_BUSY ( BIT(21) ) +#define BIT_PD_CP1_SYS_BISR_BUSY ( BIT(20) ) +#define BIT_PD_CP0_HU3GE_BISR_BUSY ( BIT(19) ) +#define BIT_PD_CP0_SYS_BISR_BUSY ( BIT(18) ) +#define BIT_PD_MM_TOP_BISR_BUSY ( BIT(17) ) +#define BIT_PD_GPU_TOP_BISR_BUSY ( BIT(16) ) +#define BIT_PD_CP0_CEVA_BISR_FORCE_EN ( BIT(15) ) +#define BIT_PD_CP0_TD_BISR_FORCE_EN ( BIT(14) ) +#define BIT_PD_CP1_TD_BISR_FORCE_EN ( BIT(13) ) +#define BIT_PD_CP1_SYS_BISR_FORCE_EN ( BIT(12) ) +#define BIT_PD_CP0_HU3GE_BISR_FORCE_EN ( BIT(11) ) +#define BIT_PD_CP0_SYS_BISR_FORCE_EN ( BIT(10) ) +#define BIT_PD_MM_TOP_BISR_FORCE_EN ( BIT(9) ) +#define BIT_PD_GPU_TOP_BISR_FORCE_EN ( BIT(8) ) +#define BIT_PD_CP1_TD_BISR_FORCE_BYP ( BIT(7) ) +#define BIT_PD_CP0_CEVA_BISR_FORCE_BYP ( BIT(6) ) +#define BIT_PD_CP0_TD_BISR_FORCE_BYP ( BIT(5) ) +#define BIT_PD_CP1_SYS_BISR_FORCE_BYP ( BIT(4) ) +#define BIT_PD_CP0_HU3GE_BISR_FORCE_BYP ( BIT(3) ) +#define BIT_PD_CP0_SYS_BISR_FORCE_BYP ( BIT(2) ) +#define BIT_PD_MM_TOP_BISR_FORCE_BYP ( BIT(1) ) +#define BIT_PD_GPU_TOP_BISR_FORCE_BYP ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CGM_AP_AUTO_GATE_EN */ +#define BIT_CGM_307M2_AP_AUTO_GATE_EN ( BIT(21) ) +#define BIT_CGM_208M_AP_AUTO_GATE_EN ( BIT(20) ) +#define BIT_CGM_12M_AP_AUTO_GATE_EN ( BIT(19) ) +#define BIT_CGM_24M_AP_AUTO_GATE_EN ( BIT(18) ) +#define BIT_CGM_48M_AP_AUTO_GATE_EN ( BIT(17) ) +#define BIT_CGM_51M2_AP_AUTO_GATE_EN ( BIT(16) ) +#define BIT_CGM_64M_AP_AUTO_GATE_EN ( BIT(15) ) +#define BIT_CGM_76M8_AP_AUTO_GATE_EN ( BIT(14) ) +#define BIT_CGM_96M_AP_AUTO_GATE_EN ( BIT(13) ) +#define BIT_CGM_128M_AP_AUTO_GATE_EN ( BIT(12) ) +#define BIT_CGM_153M6_AP_AUTO_GATE_EN ( BIT(11) ) +#define BIT_CGM_192M_AP_AUTO_GATE_EN ( BIT(10) ) +#define BIT_CGM_256M_AP_AUTO_GATE_EN ( BIT(9) ) +#define BIT_CGM_384M_AP_AUTO_GATE_EN ( BIT(8) ) +#define BIT_CGM_312M_AP_AUTO_GATE_EN ( BIT(7) ) +#define BIT_CGM_MPLL_AP_AUTO_GATE_EN ( BIT(6) ) +#define BIT_CGM_WPLL_AP_AUTO_GATE_EN ( BIT(5) ) +#define BIT_CGM_WIFIPLL1_AP_AUTO_GATE_EN ( BIT(4) ) +#define BIT_CGM_TDPLL_AP_AUTO_GATE_EN ( BIT(3) ) +#define BIT_CGM_CPLL_AP_AUTO_GATE_EN ( BIT(2) ) +#define BIT_CGM_DPLL_AP_AUTO_GATE_EN ( BIT(1) ) +#define BIT_CGM_26M_AP_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CGM_GPU_MM_AUTO_GATE_EN */ +#define BIT_CGM_312M_MM_AUTO_GATE_EN ( BIT(27) ) +#define BIT_CGM_12M_MM_AUTO_GATE_EN ( BIT(26) ) +#define BIT_CGM_24M_MM_AUTO_GATE_EN ( BIT(25) ) +#define BIT_CGM_48M_MM_AUTO_GATE_EN ( BIT(24) ) +#define BIT_CGM_64M_MM_AUTO_GATE_EN ( BIT(23) ) +#define BIT_CGM_76M8_MM_AUTO_GATE_EN ( BIT(22) ) +#define BIT_CGM_96M_MM_AUTO_GATE_EN ( BIT(21) ) +#define BIT_CGM_128M_MM_AUTO_GATE_EN ( BIT(20) ) +#define BIT_CGM_153M6_MM_AUTO_GATE_EN ( BIT(19) ) +#define BIT_CGM_192M_MM_AUTO_GATE_EN ( BIT(18) ) +#define BIT_CGM_256M_MM_AUTO_GATE_EN ( BIT(17) ) +#define BIT_CGM_26M_MM_AUTO_GATE_EN ( BIT(16) ) +#define BIT_CGM_153_6M_GPU_AUTO_GATE_EN ( BIT(6) ) +#define BIT_CGM_384M_GPU_AUTO_GATE_EN ( BIT(5) ) +#define BIT_CGM_460_8M_GPU_AUTO_GATE_EN ( BIT(4) ) +#define BIT_CGM_256M_GPU_AUTO_GATE_EN ( BIT(3) ) +#define BIT_CGM_208M_GPU_AUTO_GATE_EN ( BIT(2) ) +#define BIT_CGM_312M_GPU_AUTO_GATE_EN ( BIT(1) ) +#define BIT_CGM_512M_GPU_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CGM_CP0_AUTO_GATE_EN */ +#define BIT_CGM_312M_CP0_AUTO_GATE_EN ( BIT(16) ) +#define BIT_CGM_208M_CP0_AUTO_GATE_EN ( BIT(15) ) +#define BIT_CGM_256M_CP0_AUTO_GATE_EN ( BIT(14) ) +#define BIT_CGM_460M8_CP0W_AUTO_GATE_EN ( BIT(13) ) +#define BIT_CGM_307M2_CP0W_AUTO_GATE_EN ( BIT(12) ) +#define BIT_CGM_51M2_CP0W_AUTO_GATE_EN ( BIT(11) ) +#define BIT_CGM_76M8_CP0W_AUTO_GATE_EN ( BIT(10) ) +#define BIT_CGM_102M4_CP0W_AUTO_GATE_EN ( BIT(9) ) +#define BIT_CGM_192M_CP0_AUTO_GATE_EN ( BIT(8) ) +#define BIT_CGM_51M2_CP0_AUTO_GATE_EN ( BIT(7) ) +#define BIT_CGM_76M8_CP0_AUTO_GATE_EN ( BIT(6) ) +#define BIT_CGM_153M6_CP0_AUTO_GATE_EN ( BIT(5) ) +#define BIT_CGM_48M_CP0_AUTO_GATE_EN ( BIT(4) ) +#define BIT_CGM_64M_CP0_AUTO_GATE_EN ( BIT(3) ) +#define BIT_CGM_96M_CP0_AUTO_GATE_EN ( BIT(2) ) +#define BIT_CGM_128M_CP0_AUTO_GATE_EN ( BIT(1) ) +#define BIT_CGM_26M_CP0_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CGM_CP1_AUTO_GATE_EN */ +#define BIT_CGM_312M_CP1_AUTO_GATE_EN ( BIT(10) ) +#define BIT_CGM_256M_CP1_AUTO_GATE_EN ( BIT(9) ) +#define BIT_CGM_192M_CP1_AUTO_GATE_EN ( BIT(8) ) +#define BIT_CGM_51M2_CP1_AUTO_GATE_EN ( BIT(7) ) +#define BIT_CGM_76M8_CP1_AUTO_GATE_EN ( BIT(6) ) +#define BIT_CGM_153M6_CP1_AUTO_GATE_EN ( BIT(5) ) +#define BIT_CGM_48M_CP1_AUTO_GATE_EN ( BIT(4) ) +#define BIT_CGM_96M_CP1_AUTO_GATE_EN ( BIT(3) ) +#define BIT_CGM_64M_CP1_AUTO_GATE_EN ( BIT(2) ) +#define BIT_CGM_128M_CP1_AUTO_GATE_EN ( BIT(1) ) +#define BIT_CGM_26M_CP1_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CGM_CP2_AUTO_GATE_EN */ +#define BIT_CGM_153M6_CP2_AUTO_GATE_EN ( BIT(12) ) +#define BIT_CGM_20M_CP2WF2_AUTO_GATE_EN ( BIT(11) ) +#define BIT_CGM_80M_CP2WF2_AUTO_GATE_EN ( BIT(10) ) +#define BIT_CGM_120M_CP2WF2_AUTO_GATE_EN ( BIT(9) ) +#define BIT_CGM_160M_CP2WF2_AUTO_GATE_EN ( BIT(8) ) +#define BIT_CGM_20M_CP2WF1_AUTO_GATE_EN ( BIT(7) ) +#define BIT_CGM_44M_CP2WF1_AUTO_GATE_EN ( BIT(6) ) +#define BIT_CGM_80M_CP2WF1_AUTO_GATE_EN ( BIT(5) ) +#define BIT_CGM_256M_CP2_AUTO_GATE_EN ( BIT(4) ) +#define BIT_CGM_104M_CP2_AUTO_GATE_EN ( BIT(3) ) +#define BIT_CGM_208M_CP2_AUTO_GATE_EN ( BIT(2) ) +#define BIT_CGM_312M_CP2_AUTO_GATE_EN ( BIT(1) ) +#define BIT_CGM_26M_CP2_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CGM_AP_EN */ +#define BIT_CGM_307M2_AP_EN ( BIT(21) ) +#define BIT_CGM_208M_AP_EN ( BIT(20) ) +#define BIT_CGM_12M_AP_EN ( BIT(19) ) +#define BIT_CGM_24M_AP_EN ( BIT(18) ) +#define BIT_CGM_48M_AP_EN ( BIT(17) ) +#define BIT_CGM_51M2_AP_EN ( BIT(16) ) +#define BIT_CGM_64M_AP_EN ( BIT(15) ) +#define BIT_CGM_76M8_AP_EN ( BIT(14) ) +#define BIT_CGM_96M_AP_EN ( BIT(13) ) +#define BIT_CGM_128M_AP_EN ( BIT(12) ) +#define BIT_CGM_153M6_AP_EN ( BIT(11) ) +#define BIT_CGM_192M_AP_EN ( BIT(10) ) +#define BIT_CGM_256M_AP_EN ( BIT(9) ) +#define BIT_CGM_384M_AP_EN ( BIT(8) ) +#define BIT_CGM_312M_AP_EN ( BIT(7) ) +#define BIT_CGM_MPLL_AP_EN ( BIT(6) ) +#define BIT_CGM_WPLL_AP_EN ( BIT(5) ) +#define BIT_CGM_WIFIPLL1_AP_EN ( BIT(4) ) +#define BIT_CGM_TDPLL_AP_EN ( BIT(3) ) +#define BIT_CGM_CPLL_AP_EN ( BIT(2) ) +#define BIT_CGM_DPLL_AP_EN ( BIT(1) ) +#define BIT_CGM_26M_AP_EN ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CGM_GPU_MM_EN */ +#define BIT_CGM_312M_MM_EN ( BIT(27) ) +#define BIT_CGM_12M_MM_EN ( BIT(26) ) +#define BIT_CGM_24M_MM_EN ( BIT(25) ) +#define BIT_CGM_48M_MM_EN ( BIT(24) ) +#define BIT_CGM_64M_MM_EN ( BIT(23) ) +#define BIT_CGM_76M8_MM_EN ( BIT(22) ) +#define BIT_CGM_96M_MM_EN ( BIT(21) ) +#define BIT_CGM_128M_MM_EN ( BIT(20) ) +#define BIT_CGM_153M6_MM_EN ( BIT(19) ) +#define BIT_CGM_192M_MM_EN ( BIT(18) ) +#define BIT_CGM_256M_MM_EN ( BIT(17) ) +#define BIT_CGM_26M_MM_EN ( BIT(16) ) +#define BIT_CGM_153_6M_GPU_EN ( BIT(6) ) +#define BIT_CGM_384M_GPU_EN ( BIT(5) ) +#define BIT_CGM_460_8M_GPU_EN ( BIT(4) ) +#define BIT_CGM_256M_GPU_EN ( BIT(3) ) +#define BIT_CGM_208M_GPU_EN ( BIT(2) ) +#define BIT_CGM_312M_GPU_EN ( BIT(1) ) +#define BIT_CGM_512M_GPU_EN ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CGM_CP0_EN */ +#define BIT_CGM_312M_CP0_EN ( BIT(16) ) +#define BIT_CGM_208M_CP0_EN ( BIT(15) ) +#define BIT_CGM_256M_CP0_EN ( BIT(14) ) +#define BIT_CGM_460M8_CP0W_EN ( BIT(13) ) +#define BIT_CGM_307M2_CP0W_EN ( BIT(12) ) +#define BIT_CGM_51M2_CP0W_EN ( BIT(11) ) +#define BIT_CGM_76M8_CP0W_EN ( BIT(10) ) +#define BIT_CGM_102M4_CP0W_EN ( BIT(9) ) +#define BIT_CGM_192M_CP0_EN ( BIT(8) ) +#define BIT_CGM_51M2_CP0_EN ( BIT(7) ) +#define BIT_CGM_76M8_CP0_EN ( BIT(6) ) +#define BIT_CGM_153M6_CP0_EN ( BIT(5) ) +#define BIT_CGM_48M_CP0_EN ( BIT(4) ) +#define BIT_CGM_64M_CP0_EN ( BIT(3) ) +#define BIT_CGM_96M_CP0_EN ( BIT(2) ) +#define BIT_CGM_128M_CP0_EN ( BIT(1) ) +#define BIT_CGM_26M_CP0_EN ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CGM_CP1_EN */ +#define BIT_CGM_312M_CP1_EN ( BIT(10) ) +#define BIT_CGM_256M_CP1_EN ( BIT(9) ) +#define BIT_CGM_192M_CP1_EN ( BIT(8) ) +#define BIT_CGM_51M2_CP1_EN ( BIT(7) ) +#define BIT_CGM_76M8_CP1_EN ( BIT(6) ) +#define BIT_CGM_153M6_CP1_EN ( BIT(5) ) +#define BIT_CGM_48M_CP1_EN ( BIT(4) ) +#define BIT_CGM_96M_CP1_EN ( BIT(3) ) +#define BIT_CGM_64M_CP1_EN ( BIT(2) ) +#define BIT_CGM_128M_CP1_EN ( BIT(1) ) +#define BIT_CGM_26M_CP1_EN ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CGM_CP2_EN */ +#define BIT_CGM_153M6_CP2_EN ( BIT(12) ) +#define BIT_CGM_20M_CP2WF2_EN ( BIT(11) ) +#define BIT_CGM_80M_CP2WF2_EN ( BIT(10) ) +#define BIT_CGM_120M_CP2WF2_EN ( BIT(9) ) +#define BIT_CGM_160M_CP2WF2_EN ( BIT(8) ) +#define BIT_CGM_20M_CP2WF1_EN ( BIT(7) ) +#define BIT_CGM_44M_CP2WF1_EN ( BIT(6) ) +#define BIT_CGM_80M_CP2WF1_EN ( BIT(5) ) +#define BIT_CGM_256M_CP2_EN ( BIT(4) ) +#define BIT_CGM_104M_CP2_EN ( BIT(3) ) +#define BIT_CGM_208M_CP2_EN ( BIT(2) ) +#define BIT_CGM_312M_CP2_EN ( BIT(1) ) +#define BIT_CGM_26M_CP2_EN ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_DDR_OP_MODE_CFG */ +#define BIT_DDR_PHY_RET_EN ( BIT(28) ) +#define BIT_DDR_PUBL_RET_EN ( BIT(27) ) +#define BIT_DDR_PHY_ISO_RST_EN ( BIT(26) ) +#define BIT_DDR_UMCTL_RET_EN ( BIT(25) ) +#define BIT_DDR_PHY_AUTO_RET_EN ( BIT(24) ) +#define BITS_DDR_OPERATE_MODE_CNT_LMT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DDR_OPERATE_MODE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_DDR_OPERATE_MODE_IDLE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_PMU_APB_DDR_PHY_RET_CFG */ +#define BIT_DDR_PHY_CKE_RET_EN ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_26M_SEL_CFG */ +#define BIT_CLK26MHZ_REF_1_SEL ( BIT(10) ) +#define BIT_AON_MEM_PD_EN_CP2 ( BIT(9) ) +#define BIT_AON_MEM_PD_EN_CP0 ( BIT(8) ) +#define BIT_AON_MEM_PD_EN_AP ( BIT(7) ) +#define BIT_LPLL_REF_SEL ( BIT(6) ) +#define BIT_PUB_26M_SEL ( BIT(5) ) +#define BIT_AON_26M_SEL ( BIT(4) ) +#define BIT_CP2_26M_SEL ( BIT(3) ) +#define BIT_CP1_26M_SEL ( BIT(2) ) +#define BIT_CP0_26M_SEL ( BIT(1) ) +#define BIT_AP_26M_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_MEM_PD_CFG0 */ +#define BITS_CP0_W_MEM_PD_CFG_HARQ(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_CP0_W_MEM_PD_CFG_UART1(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)) ) +#define BITS_CP0_W_MEM_PD_CFG_UART0(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)) ) +#define BITS_CP0_W_MEM_PD_CFG_IRAM(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_CP0_W_MEM_PD_CFG_PERIF(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_AON_MEM_PD_CFG_IRAM(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_AON_MEM_PD_CFG_IMC3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_AON_MEM_PD_CFG_IMC2(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_AON_MEM_PD_CFG_IMC1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_AON_MEM_PD_CFG_IMC0(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_AON_MEM_PD_CFG_VBC(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_AON_MEM_PD_CFG_AUD(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_AON_MEM_PD_CFG_FM(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_PMU_APB_MEM_PD_CFG1 */ +#define BITS_CP0_DSP_MEM_PD_CFG_DMA(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_CP0_DSP_MEM_PD_CFG_SHM(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)) ) +#define BITS_CP0_DSP_MEM_PD_CFG_RFT(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)) ) +#define BITS_CP0_DSP_MEM_PD_CFG_STC(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_CP0_ARM_MEM_PD_CFG_IIS3(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_CP0_ARM_MEM_PD_CFG_IIS2(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_CP0_ARM_MEM_PD_CFG_IIS1(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_CP0_ARM_MEM_PD_CFG_IIS0(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_CP0_ARM_MEM_PD_CFG_UART1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_CP0_ARM_MEM_PD_CFG_UART0(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_CP0_ARM_MEM_PD_CFG_EPT(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CP0_ARM_MEM_PD_CFG_LZMA(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_CP0_ARM_MEM_PD_CFG_DMA(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_PMU_APB_PD_DDR_PUBL_CFG */ +#define BIT_PD_DDR_PUBL_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_DDR_PUBL_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_DDR_PUBL_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_DDR_PUBL_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_DDR_PUBL_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_DDR_PHY_CFG */ +#define BIT_PD_DDR_PHY_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_DDR_PHY_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_DDR_PHY_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_DDR_PHY_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_DDR_PHY_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_BISR_CFG2 */ +#define BIT_PD_CA7_TOP_BISR_DONE ( BIT(15) ) +#define BIT_PD_CA7_TOP_BISR_BUSY ( BIT(14) ) +#define BIT_PD_CA7_TOP_BISR_FORCE_EN ( BIT(13) ) +#define BIT_PD_CA7_TOP_BISR_FORCE_BYP ( BIT(12) ) +#define BIT_PD_CP0_HARQ_BISR_DONE ( BIT(11) ) +#define BIT_PD_CP0_HARQ_BISR_BUSY ( BIT(10) ) +#define BIT_PD_CP0_HARQ_BISR_FORCE_EN ( BIT(9) ) +#define BIT_PD_CP0_HARQ_BISR_FORCE_BYP ( BIT(8) ) +#define BIT_PD_CP2_WIFI_BISR_DONE ( BIT(7) ) +#define BIT_PD_AP_SYS_BISR_DONE ( BIT(6) ) +#define BIT_PD_CP2_WIFI_BISR_BUSY ( BIT(5) ) +#define BIT_PD_AP_SYS_BISR_BUSY ( BIT(4) ) +#define BIT_PD_CP2_WIFI_BISR_FORCE_EN ( BIT(3) ) +#define BIT_PD_AP_SYS_BISR_FORCE_EN ( BIT(2) ) +#define BIT_PD_CP2_WIFI_BISR_FORCE_BYP ( BIT(1) ) +#define BIT_PD_AP_SYS_BISR_FORCE_BYP ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_DEBUG_PD0 */ +#define BIT_PD_DDR_PHY_SHUTDOWN_D_B ( BIT(27) ) +#define BIT_PD_DDR_PUBL_SHUTDOWN_D_B ( BIT(26) ) +#define BIT_PD_PUB_SYS_SHUTDOWN_D_B ( BIT(25) ) +#define BIT_PD_CP2_WIFI_SHUTDOWN_D_B ( BIT(24) ) +#define BIT_PD_CP2_ARM9_SHUTDOWN_D_B ( BIT(23) ) +#define BIT_PD_CP2_SYS_SHUTDOWN_D_B ( BIT(22) ) +#define BIT_PD_CP1_L1RAM_SHUTDOWN_D_B ( BIT(21) ) +#define BIT_PD_CP1_TD_SHUTDOWN_D_B ( BIT(20) ) +#define BIT_PD_CP1_GSM_SHUTDOWN_D_B ( BIT(19) ) +#define BIT_PD_CP1_ARM9_SHUTDOWN_D_B ( BIT(18) ) +#define BIT_PD_CP1_SYS_SHUTDOWN_D_B ( BIT(17) ) +#define BIT_PD_CP0_CEVA_SHUTDOWN_D_B ( BIT(16) ) +#define BIT_PD_CP0_TD_SHUTDOWN_D_B ( BIT(15) ) +#define BIT_PD_CP0_GSM_SHUTDOWN_D_B ( BIT(14) ) +#define BIT_PD_CP0_HARQ_SHUTDOWN_D_B ( BIT(13) ) +#define BIT_PD_CP0_HU3GE_SHUTDOWN_D_B ( BIT(12) ) +#define BIT_PD_CP0_ARM9_2_SHUTDOWN_D_B ( BIT(11) ) +#define BIT_PD_CP0_ARM9_1_SHUTDOWN_D_B ( BIT(10) ) +#define BIT_PD_CP0_ARM9_0_SHUTDOWN_D_B ( BIT(9) ) +#define BIT_PD_CP0_SYS_SHUTDOWN_D_B ( BIT(8) ) +#define BIT_PD_GPU_TOP_SHUTDOWN_D_B ( BIT(7) ) +#define BIT_PD_MM_TOP_SHUTDOWN_D_B ( BIT(6) ) +#define BIT_PD_CA7_C3_SHUTDOWN_D_B ( BIT(5) ) +#define BIT_PD_CA7_C2_SHUTDOWN_D_B ( BIT(4) ) +#define BIT_PD_CA7_C1_SHUTDOWN_D_B ( BIT(3) ) +#define BIT_PD_CA7_C0_SHUTDOWN_D_B ( BIT(2) ) +#define BIT_PD_CA7_TOP_SHUTDOWN_D_B ( BIT(1) ) +#define BIT_PD_AP_SYS_SHUTDOWN_D_B ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_DEBUG_PD1 */ +#define BIT_PD_DDR_PHY_SHUTDOWN_M_B ( BIT(27) ) +#define BIT_PD_DDR_PUBL_SHUTDOWN_M_B ( BIT(26) ) +#define BIT_PD_PUB_SYS_SHUTDOWN_M_B ( BIT(25) ) +#define BIT_PD_CP2_WIFI_SHUTDOWN_M_B ( BIT(24) ) +#define BIT_PD_CP2_ARM9_SHUTDOWN_M_B ( BIT(23) ) +#define BIT_PD_CP2_SYS_SHUTDOWN_M_B ( BIT(22) ) +#define BIT_PD_CP1_L1RAM_SHUTDOWN_M_B ( BIT(21) ) +#define BIT_PD_CP1_TD_SHUTDOWN_M_B ( BIT(20) ) +#define BIT_PD_CP1_GSM_SHUTDOWN_M_B ( BIT(19) ) +#define BIT_PD_CP1_ARM9_SHUTDOWN_M_B ( BIT(18) ) +#define BIT_PD_CP1_SYS_SHUTDOWN_M_B ( BIT(17) ) +#define BIT_PD_CP0_CEVA_SHUTDOWN_M_B ( BIT(16) ) +#define BIT_PD_CP0_TD_SHUTDOWN_M_B ( BIT(15) ) +#define BIT_PD_CP0_GSM_SHUTDOWN_M_B ( BIT(14) ) +#define BIT_PD_CP0_HARQ_SHUTDOWN_M_B ( BIT(13) ) +#define BIT_PD_CP0_HU3GE_SHUTDOWN_M_B ( BIT(12) ) +#define BIT_PD_CP0_ARM9_2_SHUTDOWN_M_B ( BIT(11) ) +#define BIT_PD_CP0_ARM9_1_SHUTDOWN_M_B ( BIT(10) ) +#define BIT_PD_CP0_ARM9_0_SHUTDOWN_M_B ( BIT(9) ) +#define BIT_PD_CP0_SYS_SHUTDOWN_M_B ( BIT(8) ) +#define BIT_PD_GPU_TOP_SHUTDOWN_M_B ( BIT(7) ) +#define BIT_PD_MM_TOP_SHUTDOWN_M_B ( BIT(6) ) +#define BIT_PD_CA7_C3_SHUTDOWN_M_B ( BIT(5) ) +#define BIT_PD_CA7_C2_SHUTDOWN_M_B ( BIT(4) ) +#define BIT_PD_CA7_C1_SHUTDOWN_M_B ( BIT(3) ) +#define BIT_PD_CA7_C0_SHUTDOWN_M_B ( BIT(2) ) +#define BIT_PD_CA7_TOP_SHUTDOWN_M_B ( BIT(1) ) +#define BIT_PD_AP_SYS_SHUTDOWN_M_B ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_DEBUG_PD2 */ +#define BIT_PD_DDR_PHY_ACK_M ( BIT(27) ) +#define BIT_PD_DDR_PUBL_ACK_M ( BIT(26) ) +#define BIT_PD_PUB_SYS_ACK_M ( BIT(25) ) +#define BIT_PD_CP2_WIFI_ACK_M ( BIT(24) ) +#define BIT_PD_CP2_ARM9_ACK_M ( BIT(23) ) +#define BIT_PD_CP2_SYS_ACK_M ( BIT(22) ) +#define BIT_PD_CP1_L1RAM_ACK_M ( BIT(21) ) +#define BIT_PD_CP1_TD_ACK_M ( BIT(20) ) +#define BIT_PD_CP1_GSM_ACK_M ( BIT(19) ) +#define BIT_PD_CP1_ARM9_ACK_M ( BIT(18) ) +#define BIT_PD_CP1_SYS_ACK_M ( BIT(17) ) +#define BIT_PD_CP0_CEVA_ACK_M ( BIT(16) ) +#define BIT_PD_CP0_TD_ACK_M ( BIT(15) ) +#define BIT_PD_CP0_GSM_ACK_M ( BIT(14) ) +#define BIT_PD_CP0_HARQ_ACK_M ( BIT(13) ) +#define BIT_PD_CP0_HU3GE_ACK_M ( BIT(12) ) +#define BIT_PD_CP0_ARM9_2_ACK_M ( BIT(11) ) +#define BIT_PD_CP0_ARM9_1_ACK_M ( BIT(10) ) +#define BIT_PD_CP0_ARM9_0_ACK_M ( BIT(9) ) +#define BIT_PD_CP0_SYS_ACK_M ( BIT(8) ) +#define BIT_PD_GPU_TOP_ACK_M ( BIT(7) ) +#define BIT_PD_MM_TOP_ACK_M ( BIT(6) ) +#define BIT_PD_CA7_C3_ACK_M ( BIT(5) ) +#define BIT_PD_CA7_C2_ACK_M ( BIT(4) ) +#define BIT_PD_CA7_C1_ACK_M ( BIT(3) ) +#define BIT_PD_CA7_C0_ACK_M ( BIT(2) ) +#define BIT_PD_CA7_TOP_ACK_M ( BIT(1) ) +#define BIT_PD_AP_SYS_ACK_M ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_DEBUG_PD3 */ +#define BIT_PD_DDR_PHY_ACK_D ( BIT(27) ) +#define BIT_PD_DDR_PUBL_ACK_D ( BIT(26) ) +#define BIT_PD_PUB_SYS_ACK_D ( BIT(25) ) +#define BIT_PD_CP2_WIFI_ACK_D ( BIT(24) ) +#define BIT_PD_CP2_ARM9_ACK_D ( BIT(23) ) +#define BIT_PD_CP2_SYS_ACK_D ( BIT(22) ) +#define BIT_PD_CP1_L1RAM_ACK_D ( BIT(21) ) +#define BIT_PD_CP1_TD_ACK_D ( BIT(20) ) +#define BIT_PD_CP1_GSM_ACK_D ( BIT(19) ) +#define BIT_PD_CP1_ARM9_ACK_D ( BIT(18) ) +#define BIT_PD_CP1_SYS_ACK_D ( BIT(17) ) +#define BIT_PD_CP0_CEVA_ACK_D ( BIT(16) ) +#define BIT_PD_CP0_TD_ACK_D ( BIT(15) ) +#define BIT_PD_CP0_GSM_ACK_D ( BIT(14) ) +#define BIT_PD_CP0_HARQ_ACK_D ( BIT(13) ) +#define BIT_PD_CP0_HU3GE_ACK_D ( BIT(12) ) +#define BIT_PD_CP0_ARM9_2_ACK_D ( BIT(11) ) +#define BIT_PD_CP0_ARM9_1_ACK_D ( BIT(10) ) +#define BIT_PD_CP0_ARM9_0_ACK_D ( BIT(9) ) +#define BIT_PD_CP0_SYS_ACK_D ( BIT(8) ) +#define BIT_PD_GPU_TOP_ACK_D ( BIT(7) ) +#define BIT_PD_MM_TOP_ACK_D ( BIT(6) ) +#define BIT_PD_CA7_C3_ACK_D ( BIT(5) ) +#define BIT_PD_CA7_C2_ACK_D ( BIT(4) ) +#define BIT_PD_CA7_C1_ACK_D ( BIT(3) ) +#define BIT_PD_CA7_C0_ACK_D ( BIT(2) ) +#define BIT_PD_CA7_TOP_ACK_D ( BIT(1) ) +#define BIT_PD_AP_SYS_ACK_D ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_INT_DISABLE */ +#define BIT_CP2_INT_DISABLE ( BIT(2) ) +#define BIT_CP0_INT_DISABLE ( BIT(1) ) +#define BIT_AP_INT_DISABLE ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_PMU_DEBUG_CFG */ +#define BITS_PMU_DEBUG_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +#endif diff --git a/include/soc/sprd/chip_x20/__regs_pub_apb.h b/include/soc/sprd/chip_x20/__regs_pub_apb.h new file mode 100644 index 00000000..be6df61d --- /dev/null +++ b/include/soc/sprd/chip_x20/__regs_pub_apb.h @@ -0,0 +1,477 @@ +/*
+ * Copyright (C) 2014 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+#ifndef __SCI_GLB_REGS_H__
+#error "Don't include this file directly, Pls include sci_glb_regs.h"
+#endif
+
+
+#ifndef __H_REGS_PUB_APB_HEADFILE_H__
+#define __H_REGS_PUB_APB_HEADFILE_H__ __FILE__
+
+#define REGS_PUB_APB
+
+/* registers definitions for PUB_APB */
+#define REG_PUB_APB_BUSMON_CNT_START SCI_ADDR(REGS_PUB_APB_BASE, 0x0000)
+#define REG_PUB_APB_BUSMON_CFG SCI_ADDR(REGS_PUB_APB_BASE, 0x0004)
+#define REG_PUB_APB_DDR_EB SCI_ADDR(REGS_PUB_APB_BASE, 0x0008)
+#define REG_PUB_APB_DDR_SOFT_RST SCI_ADDR(REGS_PUB_APB_BASE, 0x000C)
+#define REG_PUB_APB_DDR_QOS_CFG1 SCI_ADDR(REGS_PUB_APB_BASE, 0x0010)
+#define REG_PUB_APB_DDR_QOS_CFG2 SCI_ADDR(REGS_PUB_APB_BASE, 0x0014)
+#define REG_PUB_APB_DDR_QOS_CFG3 SCI_ADDR(REGS_PUB_APB_BASE, 0x0018)
+#define REG_PUB_APB_DDR_MRR_STATUS SCI_ADDR(REGS_PUB_APB_BASE, 0x001C)
+#define REG_PUB_APB_DDR_ID2QOS_SEL SCI_ADDR(REGS_PUB_APB_BASE, 0x003C)
+#define REG_PUB_APB_DDR_ID2QOS_RCFG0 SCI_ADDR(REGS_PUB_APB_BASE, 0x0040)
+#define REG_PUB_APB_DDR_ID2QOS_RCFG1 SCI_ADDR(REGS_PUB_APB_BASE, 0x0044)
+#define REG_PUB_APB_DDR_ID2QOS_RCFG2 SCI_ADDR(REGS_PUB_APB_BASE, 0x0048)
+#define REG_PUB_APB_DDR_ID2QOS_RCFG3 SCI_ADDR(REGS_PUB_APB_BASE, 0x004c)
+#define REG_PUB_APB_DDR_ID2QOS_RCFG4 SCI_ADDR(REGS_PUB_APB_BASE, 0x0050)
+#define REG_PUB_APB_DDR_ID2QOS_RCFG5 SCI_ADDR(REGS_PUB_APB_BASE, 0x0054)
+#define REG_PUB_APB_DDR_ID2QOS_RCFG6 SCI_ADDR(REGS_PUB_APB_BASE, 0x0058)
+#define REG_PUB_APB_DDR_ID2QOS_RCFG7 SCI_ADDR(REGS_PUB_APB_BASE, 0x005c)
+#define REG_PUB_APB_DDR_ID2QOS_RCFG8 SCI_ADDR(REGS_PUB_APB_BASE, 0x0060)
+#define REG_PUB_APB_DDR_ID2QOS_RCFG9 SCI_ADDR(REGS_PUB_APB_BASE, 0x0064)
+#define REG_PUB_APB_DDR_ID2QOS_WCFG0 SCI_ADDR(REGS_PUB_APB_BASE, 0x0080)
+#define REG_PUB_APB_DDR_ID2QOS_WCFG1 SCI_ADDR(REGS_PUB_APB_BASE, 0x0084)
+#define REG_PUB_APB_DDR_ID2QOS_WCFG2 SCI_ADDR(REGS_PUB_APB_BASE, 0x0088)
+#define REG_PUB_APB_DDR_ID2QOS_WCFG3 SCI_ADDR(REGS_PUB_APB_BASE, 0x008c)
+#define REG_PUB_APB_DDR_ID2QOS_WCFG4 SCI_ADDR(REGS_PUB_APB_BASE, 0x0090)
+#define REG_PUB_APB_DDR_ID2QOS_WCFG5 SCI_ADDR(REGS_PUB_APB_BASE, 0x0094)
+#define REG_PUB_APB_DDR_ID2QOS_WCFG6 SCI_ADDR(REGS_PUB_APB_BASE, 0x0098)
+#define REG_PUB_APB_DDR_ID2QOS_WCFG7 SCI_ADDR(REGS_PUB_APB_BASE, 0x009c)
+#define REG_PUB_APB_DDR_ID2QOS_WCFG8 SCI_ADDR(REGS_PUB_APB_BASE, 0x00a0)
+#define REG_PUB_APB_DDR_ID2QOS_WCFG9 SCI_ADDR(REGS_PUB_APB_BASE, 0x00a4)
+#define REG_PUB_APB_DFI_TIMEOUT_CFG SCI_ADDR(REGS_PUB_APB_BASE, 0x0100)
+#define REG_PUB_APB_DFI_TIMEOUT_STATUS SCI_ADDR(REGS_PUB_APB_BASE, 0x0104)
+#define REG_PUB_APB_DFI_TIMEOUT_EN_CNT SCI_ADDR(REGS_PUB_APB_BASE, 0x0108)
+#define REG_PUB_APB_DFI_TIMEOUT_VALID_CNT SCI_ADDR(REGS_PUB_APB_BASE, 0x010c)
+#define REG_PUB_APB_DMC_PORT_REMAP_EN SCI_ADDR(REGS_PUB_APB_BASE, 0x3000)
+#define REG_PUB_APB_DMC_PORTS_MPU_EN SCI_ADDR(REGS_PUB_APB_BASE, 0x3004)
+#define REG_PUB_APB_DMC_PORT0_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3008)
+#define REG_PUB_APB_DMC_PORT1_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x300C)
+#define REG_PUB_APB_DMC_PORT2_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3010)
+#define REG_PUB_APB_DMC_PORT3_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3014)
+#define REG_PUB_APB_DMC_PORT4_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3018)
+#define REG_PUB_APB_DMC_PORT5_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x301C)
+#define REG_PUB_APB_DMC_PORT6_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3020)
+#define REG_PUB_APB_DMC_PORT7_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3024)
+#define REG_PUB_APB_DMC_PORT8_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3028)
+#define REG_PUB_APB_DMC_PORT9_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x302C)
+#define REG_PUB_APB_DMC_PORT0_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3030)
+#define REG_PUB_APB_DMC_PORT1_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3034)
+#define REG_PUB_APB_DMC_PORT2_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3038)
+#define REG_PUB_APB_DMC_PORT3_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x303C)
+#define REG_PUB_APB_DMC_PORT4_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3040)
+#define REG_PUB_APB_DMC_PORT5_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3044)
+#define REG_PUB_APB_DMC_PORT6_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3048)
+#define REG_PUB_APB_DMC_PORT7_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3050)
+#define REG_PUB_APB_DMC_PORT8_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3054)
+#define REG_PUB_APB_DMC_PORT9_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3058)
+#define REG_PUB_APB_DMC_PORT0_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x305C)
+#define REG_PUB_APB_DMC_PORT1_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3060)
+#define REG_PUB_APB_DMC_PORT2_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3064)
+#define REG_PUB_APB_DMC_PORT3_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3068)
+#define REG_PUB_APB_DMC_PORT4_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x306C)
+#define REG_PUB_APB_DMC_PORT5_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3070)
+#define REG_PUB_APB_DMC_PORT6_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3074)
+#define REG_PUB_APB_DMC_PORT7_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3078)
+#define REG_PUB_APB_DMC_PORT8_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x307C)
+#define REG_PUB_APB_DMC_PORT9_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3080)
+
+
+
+/* bits definitions for register REG_PUB_APB_BUSMON_CNT_START */
+#define BIT_PUB_BUSMON_CNT_START ( BIT(0) )
+
+/* bits definitions for register REG_PUB_APB_BUSMON_CFG */
+#define BIT_PUB_BUSMON9_EB ( BIT(25) )
+#define BIT_PUB_BUSMON8_EB ( BIT(24) )
+#define BIT_PUB_BUSMON7_EB ( BIT(23) )
+#define BIT_PUB_BUSMON6_EB ( BIT(22) )
+#define BIT_PUB_BUSMON5_EB ( BIT(21) )
+#define BIT_PUB_BUSMON4_EB ( BIT(20) )
+#define BIT_PUB_BUSMON3_EB ( BIT(19) )
+#define BIT_PUB_BUSMON2_EB ( BIT(18) )
+#define BIT_PUB_BUSMON1_EB ( BIT(17) )
+#define BIT_PUB_BUSMON0_EB ( BIT(16) )
+#define BIT_PUB_BUSMON9_SOFT_RST ( BIT(9) )
+#define BIT_PUB_BUSMON8_SOFT_RST ( BIT(8) )
+#define BIT_PUB_BUSMON7_SOFT_RST ( BIT(7) )
+#define BIT_PUB_BUSMON6_SOFT_RST ( BIT(6) )
+#define BIT_PUB_BUSMON5_SOFT_RST ( BIT(5) )
+#define BIT_PUB_BUSMON4_SOFT_RST ( BIT(4) )
+#define BIT_PUB_BUSMON3_SOFT_RST ( BIT(3) )
+#define BIT_PUB_BUSMON2_SOFT_RST ( BIT(2) )
+#define BIT_PUB_BUSMON1_SOFT_RST ( BIT(1) )
+#define BIT_PUB_BUSMON0_SOFT_RST ( BIT(0) )
+
+/* bits definitions for register REG_PUB_APB_DDR_EB */
+
+/* bits definitions for register REG_PUB_APB_DDR_SOFT_RST */
+
+/* bits definitions for register REG_PUB_APB_DDR_QOS_CFG1 */
+#define BITS_DMC_ARQOS_3(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_AWQOS_3(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_ARQOS_2(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_AWQOS_2(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_ARQOS_1(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_AWQOS_1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_ARQOS_0(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_AWQOS_0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_QOS_CFG2 */
+#define BITS_DMC_ARQOS_7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_AWQOS_7(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_ARQOS_6(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_AWQOS_6(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_ARQOS_5(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_AWQOS_5(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_ARQOS_4(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_AWQOS_4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_QOS_CFG3 */
+#define BITS_DMC_ARQOS_9(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_AWQOS_9(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_ARQOS_8(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_AWQOS_8(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_MRR_STATUS */
+#define BIT_DDRC_CO_RD_MRR_DATA_VALID ( BIT(8) )
+#define BITS_DDRC_CO_RD_MRR_DATA(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_SEL */
+#define BITS_DMC_ID_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) )
+#define BITS_DMC_QOS_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG0 */
+#define BITS_DMC_ARQOS_0_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_ARQOS_0_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_ARQOS_0_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_ARQOS_0_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_ARQOS_0_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_ARQOS_0_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_ARQOS_0_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_ARQOS_0_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG1 */
+#define BITS_DMC_ARQOS_1_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_ARQOS_1_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_ARQOS_1_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_ARQOS_1_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_ARQOS_1_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_ARQOS_1_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_ARQOS_1_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_ARQOS_1_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG2 */
+#define BITS_DMC_ARQOS_2_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_ARQOS_2_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_ARQOS_2_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_ARQOS_2_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_ARQOS_2_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_ARQOS_2_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_ARQOS_2_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_ARQOS_2_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG3 */
+#define BITS_DMC_ARQOS_3_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_ARQOS_3_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_ARQOS_3_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_ARQOS_3_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_ARQOS_3_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_ARQOS_3_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_ARQOS_3_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_ARQOS_3_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG4 */
+#define BITS_DMC_ARQOS_4_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_ARQOS_4_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_ARQOS_4_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_ARQOS_4_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_ARQOS_4_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_ARQOS_4_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_ARQOS_4_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_ARQOS_4_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG5 */
+#define BITS_DMC_ARQOS_5_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_ARQOS_5_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_ARQOS_5_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_ARQOS_5_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_ARQOS_5_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_ARQOS_5_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_ARQOS_5_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_ARQOS_5_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG6 */
+#define BITS_DMC_ARQOS_6_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_ARQOS_6_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_ARQOS_6_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_ARQOS_6_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_ARQOS_6_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_ARQOS_6_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_ARQOS_6_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_ARQOS_6_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG7 */
+#define BITS_DMC_ARQOS_7_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_ARQOS_7_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_ARQOS_7_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_ARQOS_7_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_ARQOS_7_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_ARQOS_7_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_ARQOS_7_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_ARQOS_7_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG8 */
+#define BITS_DMC_ARQOS_8_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_ARQOS_8_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_ARQOS_8_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_ARQOS_8_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_ARQOS_8_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_ARQOS_8_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_ARQOS_8_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_ARQOS_8_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG9 */
+#define BITS_DMC_ARQOS_9_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_ARQOS_9_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_ARQOS_9_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_ARQOS_9_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_ARQOS_9_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_ARQOS_9_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_ARQOS_9_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_ARQOS_9_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG0 */
+#define BITS_DMC_AWQOS_0_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_AWQOS_0_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_AWQOS_0_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_AWQOS_0_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_AWQOS_0_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_AWQOS_0_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_AWQOS_0_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_AWQOS_0_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG1 */
+#define BITS_DMC_AWQOS_1_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_AWQOS_1_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_AWQOS_1_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_AWQOS_1_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_AWQOS_1_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_AWQOS_1_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_AWQOS_1_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_AWQOS_1_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG2 */
+#define BITS_DMC_AWQOS_2_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_AWQOS_2_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_AWQOS_2_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_AWQOS_2_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_AWQOS_2_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_AWQOS_2_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_AWQOS_2_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_AWQOS_2_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG3 */
+#define BITS_DMC_AWQOS_3_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_AWQOS_3_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_AWQOS_3_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_AWQOS_3_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_AWQOS_3_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_AWQOS_3_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_AWQOS_3_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_AWQOS_3_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG4 */
+#define BITS_DMC_AWQOS_4_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_AWQOS_4_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_AWQOS_4_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_AWQOS_4_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_AWQOS_4_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_AWQOS_4_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_AWQOS_4_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_AWQOS_4_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG5 */
+#define BITS_DMC_AWQOS_5_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_AWQOS_5_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_AWQOS_5_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_AWQOS_5_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_AWQOS_5_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_AWQOS_5_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_AWQOS_5_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_AWQOS_5_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG6 */
+#define BITS_DMC_AWQOS_6_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_AWQOS_6_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_AWQOS_6_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_AWQOS_6_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_AWQOS_6_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_AWQOS_6_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_AWQOS_6_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_AWQOS_6_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG7 */
+#define BITS_DMC_AWQOS_7_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_AWQOS_7_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_AWQOS_7_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_AWQOS_7_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_AWQOS_7_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_AWQOS_7_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_AWQOS_7_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_AWQOS_7_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG8 */
+#define BITS_DMC_AWQOS_8_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_AWQOS_8_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_AWQOS_8_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_AWQOS_8_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_AWQOS_8_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_AWQOS_8_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_AWQOS_8_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_AWQOS_8_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG9 */
+#define BITS_DMC_AWQOS_9_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_AWQOS_9_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_AWQOS_9_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_AWQOS_9_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_AWQOS_9_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_AWQOS_9_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_AWQOS_9_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_AWQOS_9_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DFI_TIMEOUT_CFG */
+#define BITS_DFI_TIMEOUT_THRESHOLD(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DFI_TIMEOUT_CLR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DFI_TIMEOUT_EN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DFI_TIMEOUT_STATUS */
+#define BITS_DFI_TIMEOUT_STATUS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DFI_TIMEOUT_EN_CNT */
+#define BITS_DFI_TIMEOUT_EN3_CNT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DFI_TIMEOUT_EN2_CNT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DFI_TIMEOUT_EN1_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DFI_TIMEOUT_EN0_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PUB_APB_DFI_TIMEOUT_VALID_CNT */
+#define BITS_DFI_TIMEOUT_VALID3_CNT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DFI_TIMEOUT_VALID2_CNT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DFI_TIMEOUT_VALID1_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DFI_TIMEOUT_VALID0_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT_REMAP_EN */
+#define BITS_DMC_PORTS_REMAP_EN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+
+/* bits definitions for register REG_PUB_APB_DMC_PORTS_MPU_EN */
+#define BITS_DMC_PORTS_MPU_EN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT0_ADDR_REMAP */
+#define BITS_DMC_PORT0_ADDR_REMAP(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT1_ADDR_REMAP */
+#define BITS_DMC_PORT1_ADDR_REMAP(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT2_ADDR_REMAP */
+#define BITS_DMC_PORT2_ADDR_REMAP(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT3_ADDR_REMAP */
+#define BITS_DMC_PORT3_ADDR_REMAP(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT4_ADDR_REMAP */
+#define BITS_DMC_PORT4_ADDR_REMAP(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT5_ADDR_REMAP */
+#define BITS_DMC_PORT5_ADDR_REMAP(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT6_ADDR_REMAP */
+#define BITS_DMC_PORT6_ADDR_REMAP(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT7_ADDR_REMAP */
+#define BITS_DMC_PORT7_ADDR_REMAP(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT8_ADDR_REMAP */
+#define BITS_DMC_PORT8_ADDR_REMAP(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT9_ADDR_REMAP */
+#define BITS_DMC_PORT9_ADDR_REMAP(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT0_MPU_RANGE */
+#define BITS_DMC_PORT0_MPU_RANGE(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT1_MPU_RANGE */
+#define BITS_DMC_PORT1_MPU_RANGE(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT2_MPU_RANGE */
+#define BITS_DMC_PORT2_MPU_RANGE(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT3_MPU_RANGE */
+#define BITS_DMC_PORT3_MPU_RANGE(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT4_MPU_RANGE */
+#define BITS_DMC_PORT4_MPU_RANGE(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT5_MPU_RANGE */
+#define BITS_DMC_PORT5_MPU_RANGE(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT6_MPU_RANGE */
+#define BITS_DMC_PORT6_MPU_RANGE(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT7_MPU_RANGE */
+#define BITS_DMC_PORT7_MPU_RANGE(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT8_MPU_RANGE */
+#define BITS_DMC_PORT8_MPU_RANGE(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT9_MPU_RANGE */
+#define BITS_DMC_PORT9_MPU_RANGE(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT0_DUMP_ADDR */
+#define BITS_DMC_PORT0_DUMP_ADDR(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT1_DUMP_ADDR */
+#define BITS_DMC_PORT1_DUMP_ADDR(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT2_DUMP_ADDR */
+#define BITS_DMC_PORT2_DUMP_ADDR(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT3_DUMP_ADDR */
+#define BITS_DMC_PORT3_DUMP_ADDR(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT4_DUMP_ADDR */
+#define BITS_DMC_PORT4_DUMP_ADDR(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT5_DUMP_ADDR */
+#define BITS_DMC_PORT5_DUMP_ADDR(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT6_DUMP_ADDR */
+#define BITS_DMC_PORT6_DUMP_ADDR(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT7_DUMP_ADDR */
+#define BITS_DMC_PORT7_DUMP_ADDR(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT8_DUMP_ADDR */
+#define BITS_DMC_PORT8_DUMP_ADDR(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT9_DUMP_ADDR */
+#define BITS_DMC_PORT9_DUMP_ADDR(_X_) (_X_)
+
+#endif
diff --git a/include/soc/sprd/chip_x20/__regs_wcdma_ahb_rf.h b/include/soc/sprd/chip_x20/__regs_wcdma_ahb_rf.h new file mode 100644 index 00000000..1be075b6 --- /dev/null +++ b/include/soc/sprd/chip_x20/__regs_wcdma_ahb_rf.h @@ -0,0 +1,136 @@ +/*
+ * Copyright (C) 2014 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+#ifndef __SCI_GLB_REGS_H__
+#error "Don't include this file directly, Pls include sci_glb_regs.h"
+#endif
+
+
+#ifndef __H_REGS_WCDMA_AHB_RF_HEADFILE_H__
+#define __H_REGS_WCDMA_AHB_RF_HEADFILE_H__ __FILE__
+
+#define REGS_WCDMA_AHB_RF
+
+/* registers definitions for WCDMA_AHB_RF */
+#define REG_WCDMA_AHB_RF_AHB_EB0 SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0000)
+#define REG_WCDMA_AHB_RF_AHB_RST0 SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0004)
+#define REG_WCDMA_AHB_RF_ARCH_EB_REG SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0018)
+#define REG_WCDMA_AHB_RF_AHB_REMAP SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x001C)
+#define REG_WCDMA_AHB_RF_AHB_MISC_CTL SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0020)
+#define REG_WCDMA_AHB_RF_AHB_MTX_PRI_SEL0 SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0024)
+#define REG_WCDMA_AHB_RF_AHB_MTX_PRI_SEL1 SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0028)
+#define REG_WCDMA_AHB_RF_AHB1_PAUSE SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x002C)
+#define REG_WCDMA_AHB_RF_AHB2_PAUSE SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0030)
+#define REG_WCDMA_AHB_RF_AHB_SLP_CTL SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0034)
+#define REG_WCDMA_AHB_RF_AHB2_SLP_STS SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0038)
+#define REG_WCDMA_AHB_RF_MCU_CLK_CTL SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x003C)
+#define REG_WCDMA_AHB_RF_CHIP_ID SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x01FC)
+
+
+
+/* bits definitions for register REG_WCDMA_AHB_RF_AHB_EB0 */
+#define BITS_WCDMA_EN(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BIT_BUSMON1_EN ( BIT(2) )
+#define BIT_BUSMON0_EN ( BIT(1) )
+#define BIT_SPINLOCK_EN ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_AHB_RF_AHB_RST0 */
+#define BIT_WCDMA_SOFT_RST ( BIT(3) )
+#define BIT_BUSMON1_SOFT_RST ( BIT(2) )
+#define BIT_BUSMON0_SOFT_RST ( BIT(1) )
+#define BIT_SPINLOCK_SOFT_RST ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_AHB_RF_ARCH_EB_REG */
+#define BIT_AHB_ARCH_EB ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_AHB_RF_AHB_REMAP */
+#define BIT_ARM_JTAG_EN_ARM2 ( BIT(2) )
+#define BIT_ARM_JTAG_EN_ARM1 ( BIT(1) )
+#define BIT_REMAP ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_AHB_RF_AHB_MISC_CTL */
+#define BIT_FORCE_WSYS_ACC_STOP ( BIT(3) )
+#define BIT_W_DMA_LSLP_EN ( BIT(2) )
+#define BIT_BUSMON1_SEL ( BIT(1) )
+#define BIT_BUSMON0_SEL ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_AHB_RF_AHB_MTX_PRI_SEL0 */
+#define BITS_ARMMTX_M3TOS0_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_ARMMTX_M3TOS0_ADJ_EN ( BIT(27) )
+#define BIT_ARMMTX_M3TOS0_RND_EN ( BIT(26) )
+#define BITS_ARMMTX_M3TOS0_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
+#define BITS_ARMMTX_M2TOS0_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BIT_ARMMTX_M2TOS0_ADJ_EN ( BIT(19) )
+#define BIT_ARMMTX_M2TOS0_RND_EN ( BIT(18) )
+#define BITS_ARMMTX_M2TOS0_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_ARMMTX_M1TOS0_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BIT_ARMMTX_M1TOS0_ADJ_EN ( BIT(11) )
+#define BIT_ARMMTX_M1TOS0_RND_EN ( BIT(10) )
+#define BITS_ARMMTX_M1TOS0_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ARMMTX_M0TOS0_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_ARMMTX_M0TOS0_ADJ_EN ( BIT(3) )
+#define BIT_ARMMTX_M0TOS0_RND_EN ( BIT(2) )
+#define BITS_ARMMTX_M0TOS0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_WCDMA_AHB_RF_AHB_MTX_PRI_SEL1 */
+#define BITS_ARMMTX_M6TOS0_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BIT_ARMMTX_M6TOS0_ADJ_EN ( BIT(19) )
+#define BIT_ARMMTX_M6TOS0_RND_EN ( BIT(18) )
+#define BITS_ARMMTX_M6TOS0_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_ARMMTX_M5TOS0_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BIT_ARMMTX_M5TOS0_ADJ_EN ( BIT(11) )
+#define BIT_ARMMTX_M5TOS0_RND_EN ( BIT(10) )
+#define BITS_ARMMTX_M5TOS0_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ARMMTX_M4TOS0_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_ARMMTX_M4TOS0_ADJ_EN ( BIT(3) )
+#define BIT_ARMMTX_M4TOS0_RND_EN ( BIT(2) )
+#define BITS_ARMMTX_M4TOS0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_WCDMA_AHB_RF_AHB1_PAUSE */
+#define BIT_APB1_SLEEP ( BIT(3) )
+#define BIT_MCU1_DEEP_SLEEP_EN ( BIT(2) )
+#define BIT_MCU1_SYS_SLEEP_EN ( BIT(1) )
+#define BIT_MCU1_CORE_SLEEP ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_AHB_RF_AHB2_PAUSE */
+#define BIT_APB2_SLEEP ( BIT(3) )
+#define BIT_MCU2_DEEP_SLEEP_EN ( BIT(2) )
+#define BIT_MCU2_SYS_SLEEP_EN ( BIT(1) )
+#define BIT_MCU2_CORE_SLEEP ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_AHB_RF_AHB_SLP_CTL */
+#define BIT_MCUMTX_AUTO_GATE_EN ( BIT(4) )
+#define BIT_MCU_AUTO_GATE_EN ( BIT(3) )
+#define BIT_AHB_AUTO_GATE_EN ( BIT(2) )
+#define BIT_ARM2_AUTO_GATE_EN ( BIT(1) )
+#define BIT_ARM1_AUTO_GATE_EN ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_AHB_RF_AHB2_SLP_STS */
+#define BIT_APB2_PERI_SLEEP ( BIT(1) )
+#define BIT_APB1_PERI_SLEEP ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_AHB_RF_MCU_CLK_CTL */
+#define BITS_CLK_AHB_DIV(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_CLK_MCU_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) )
+#define BITS_CLK_APB_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_CLK_MCU_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_WCDMA_AHB_RF_CHIP_ID */
+#define BITS_CHIP_ID(_X_) (_X_)
+
+#endif
diff --git a/include/soc/sprd/chip_x20/__regs_wcdma_apb_rf.h b/include/soc/sprd/chip_x20/__regs_wcdma_apb_rf.h new file mode 100644 index 00000000..4249f10d --- /dev/null +++ b/include/soc/sprd/chip_x20/__regs_wcdma_apb_rf.h @@ -0,0 +1,77 @@ +/*
+ * Copyright (C) 2014 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+#ifndef __SCI_GLB_REGS_H__
+#error "Don't include this file directly, Pls include sci_glb_regs.h"
+#endif
+
+
+#ifndef __H_REGS_WCDMA_APB_RF_HEADFILE_H__
+#define __H_REGS_WCDMA_APB_RF_HEADFILE_H__ __FILE__
+
+#define REGS_WCDMA_APB_RF
+
+/* registers definitions for WCDMA_APB_RF */
+#define REG_WCDMA_APB_RF_APB_EB SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0000)
+#define REG_WCDMA_APB_RF_APB_RST SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0004)
+#define REG_WCDMA_APB_RF_APB_SLEEP_ST SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0008)
+#define REG_WCDMA_APB_RF_APB_MCU_RST SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0018)
+#define REG_WCDMA_APB_RF_APB_CLK_SEL0 SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x001C)
+#define REG_WCDMA_APB_RF_APB_CLK_DIV0 SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0020)
+#define REG_WCDMA_APB_RF_APB_ARCH_EB SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0024)
+#define REG_WCDMA_APB_RF_APB_SLP_CTL SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0028)
+
+
+
+/* bits definitions for register REG_WCDMA_APB_RF_APB_EB */
+#define BIT_TMR_RTC_EB ( BIT(6) )
+#define BIT_TMR_EB ( BIT(5) )
+#define BIT_SYSTMR_RTC_EB ( BIT(4) )
+#define BIT_SYSTMR_EB ( BIT(3) )
+#define BIT_UART0_EB ( BIT(2) )
+#define BIT_WDG_RTC_EB ( BIT(1) )
+#define BIT_WDG_EB ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_APB_RF_APB_RST */
+#define BIT_TMR_SOFT_RST ( BIT(3) )
+#define BIT_SYSTMR_SOFT_RST ( BIT(2) )
+#define BIT_UART0_SOFT_RST ( BIT(1) )
+#define BIT_WDG_SOFT_RST ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_APB_RF_APB_SLEEP_ST */
+#define BIT_CHIP_SLEEP_REC_CLR ( BIT(1) )
+#define BIT_CHIP_SLEEP_REC ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_APB_RF_APB_MCU_RST */
+#define BIT_MCU_SOFT_RST_SET ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_APB_RF_APB_CLK_SEL0 */
+#define BITS_CLK_UART0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_WCDMA_APB_RF_APB_CLK_DIV0 */
+#define BITS_CLK_UART0_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
+
+/* bits definitions for register REG_WCDMA_APB_RF_APB_ARCH_EB */
+#define BIT_RTC_ARCH_EB ( BIT(1) )
+#define BIT_APB_ARCH_EB ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_APB_RF_APB_SLP_CTL */
+#define BIT_APB_PERI_FRC_ON ( BIT(1) )
+#define BIT_APB_PERI_FRC_SLP ( BIT(0) )
+
+#endif
diff --git a/include/soc/sprd/chip_x20/__sc2723s_regulator_map.h b/include/soc/sprd/chip_x20/__sc2723s_regulator_map.h new file mode 100755 index 00000000..5ef090a1 --- /dev/null +++ b/include/soc/sprd/chip_x20/__sc2723s_regulator_map.h @@ -0,0 +1,174 @@ +/* + * Copyright (C) 2013 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +/* + * Regulator (0)Name, Regulator (1)Type, Power Off (2)Ctrl and (3)Bit, Power On (4)Ctrl and (5)Bit, Sleep (6)Ctrl and (7)Bit, + * Voltage Trimming (8)Ctrl and (9)Bits, Calibration (10)Ctrl and (11)Bits, + * Voltage (12)Default, Voltage (13)Ctrl and (14)Bits, Voltage Select (15)Count and Voltage (16)List[ ... ...] + */ + +#if 0 + /* BONDOPT6 = 0 --> 45nm process */ + SCI_REGU_REG(vddcore, 2, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(9), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(9), 0, 0, + ANA_REG_GLB_DCDC_CORE_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(16)|BIT(18)|BIT(19), + 1100, ANA_REG_GLB_DCDC_CORE_ADI, BIT(5)|BIT(6)|BIT(7), 8, 1100, 700, 800, 900, 1000, 650, 1200, 1300); + + SCI_REGU_REG(vddarm, 2, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(10), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(10), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(9), + ANA_REG_GLB_DCDC_ARM_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(17)|BIT(18)|BIT(19), + 1100, ANA_REG_GLB_DCDC_ARM_ADI, BIT(5)|BIT(6)|BIT(7), 8, 1100, 700, 800, 900, 1000, 650, 1200, 1300); +#else + /* BONDOPT6 = 1 --> 28nm process */ + SCI_REGU_REG(vddcore, 2, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(9), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(9), 0, 0, + ANA_REG_GLB_DCDC_CORE_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(16)|BIT(18)|BIT(19), + 900, ANA_REG_GLB_MP_MISC_CTRL, BIT(3)|BIT(4)|BIT(5), 8, 1100, 700, 800, 900, 1000, 650, 1200, 1300); + + SCI_REGU_REG(vddarm, 2, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(10), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(10), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(9), + ANA_REG_GLB_DCDC_ARM_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(17)|BIT(18)|BIT(19), + 900, ANA_REG_GLB_MP_MISC_CTRL, BIT(6)|BIT(7)|BIT(8), 8, 1100, 700, 800, 900, 1000, 650, 1200, 1300); +#endif + + SCI_REGU_REG(vddmem, 2, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(11), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(11), 0, 0, + ANA_REG_GLB_DCDC_MEM_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(16)|BIT(17)|BIT(18)|BIT(19), + 1200, ANA_REG_GLB_DCDC_MEM_ADI, BIT(5), 2, 1200, 1250); + + SCI_REGU_REG(vddgen, 2, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(12), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(12), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(12), + ANA_REG_GLB_DCDC_GEN_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(20), + 2400, ANA_REG_GLB_DCDC_GEN_ADI, BIT(5)|BIT(6)|BIT(7), 8, 2200, 1800, 1900, 2000, 2100, 2300, 2400, 2500); + + SCI_REGU_REG(vddwpa, 2, ANA_REG_GLB_LDO_PD_CTRL, BIT(11), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL0, BIT(11), + ANA_REG_GLB_DCDC_WPA_ADI, BIT(0)|BIT(1)|BIT(2), ANA_REG_GLB_LDO_CAL_SEL, BIT(16)|BIT(20), + 0, 0, 0, 0); + +#if 1 + /* BONDOPT4 = 0 */ + SCI_REGU_REG(vddwrf, 2, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(13), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(13), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(10), + ANA_REG_GLB_DCDC_WRF_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(17)|BIT(20), + 1500, ANA_REG_GLB_DCDC_WRF_ADI, BIT(5)|BIT(6), 4, 1300, 1400, 1500, 1600); +#else + /* BONDOPT4 = 1 */ + SCI_REGU_REG(vddwrf, 2, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(13), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(13), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(10), + ANA_REG_GLB_DCDC_WRF_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(17)|BIT(20), + 2800, ANA_REG_GLB_DCDC_WRF_ADI, BIT(5)|BIT(6), 4, 2600, 2700, 2800, 2900); +#endif + + SCI_REGU_REG(vdd18, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(1), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(1), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(0), + ANA_REG_GLB_LDO_CAL_CTRL0, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(6)|BIT(7)|BIT(17)|BIT(18)|BIT(20), + 1800, ANA_REG_GLB_LDO_V_CTRL0, BIT(0)|BIT(1), 4, 1500, 1800, 1300, 1200); + + SCI_REGU_REG(vdd28, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(2), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(2), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(1), + ANA_REG_GLB_LDO_CAL_CTRL0, BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_LDO_CAL_SEL, BIT(8)|BIT(10)|BIT(16)|BIT(18)|BIT(20), + 0, ANA_REG_GLB_LDO_V_CTRL0, BIT(2)|BIT(3), 4, 2800, 3000, 2650, 1800); + +#if 0 + /* BONDOPT6 = 0 --> 45nm process */ + SCI_REGU_REG(vdd25, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(3), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(3), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(2), + ANA_REG_GLB_LDO_CAL_CTRL0, BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_CAL_SEL, BIT(9)|BIT(10)|BIT(16)|BIT(18)|BIT(20), + 2500, ANA_REG_GLB_LDO_V_CTRL0, BIT(4)|BIT(5), 4, 2500, 2750, 3000, 2900); +#else + /* BONDOPT6 = 1 --> 28nm process */ + SCI_REGU_REG(vdd25, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(3), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(3), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(2), + ANA_REG_GLB_LDO_CAL_CTRL0, BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_CAL_SEL, BIT(9)|BIT(10)|BIT(16)|BIT(18)|BIT(20), + 1800, ANA_REG_GLB_MP_MISC_CTRL, BIT(9)|BIT(10), 4, 2500, 2750, 1800, 1900); +#endif + + SCI_REGU_REG(vddrf0, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(4), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(4), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(3), + ANA_REG_GLB_LDO_CAL_CTRL1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(11)|BIT(13)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 2850, ANA_REG_GLB_LDO_V_CTRL0, BIT(6)|BIT(7), 4, 2850, 2950, 2500, 1800); + +#if 1 + /* BONDOPT4 = 0 */ + SCI_REGU_REG(vddrf1, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(5), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(5), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(4), + ANA_REG_GLB_LDO_CAL_CTRL1, BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_LDO_CAL_SEL, BIT(13)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 1200, ANA_REG_GLB_MP_MISC_CTRL, BIT(11)|BIT(12), 4, 2850, 1800, 1500, 1200); +#else + /* BONDOPT4 = 1 */ + SCI_REGU_REG(vddrf1, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(5), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(5), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(4), + ANA_REG_GLB_LDO_CAL_CTRL1, BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_LDO_CAL_SEL, BIT(13)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 2850, ANA_REG_GLB_LDO_V_CTRL0, BIT(8)|BIT(9), 4, 2850, 1800, 1500, 1200); +#endif + + SCI_REGU_REG(vddrf2, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(6), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(6), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(5), + ANA_REG_GLB_LDO_CAL_CTRL1, BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_CAL_SEL, BIT(11)|BIT(12)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 2850, ANA_REG_GLB_LDO_V_CTRL0, BIT(10)|BIT(11), 4, 2850, 1800, 1500, 1200); + + SCI_REGU_REG(vddemmcio, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(7), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(7), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(6), + ANA_REG_GLB_LDO_CAL_CTRL2, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(7)|BIT(17)|BIT(18)|BIT(20), + 1800, ANA_REG_GLB_LDO_V_CTRL0, BIT(12)|BIT(13), 4, 1500, 1800, 1300, 1200); + + SCI_REGU_REG(vddemmccore, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(8), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(8), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(7), + ANA_REG_GLB_LDO_CAL_CTRL2, BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_LDO_CAL_SEL, BIT(10)|BIT(16)|BIT(18)|BIT(20), + 3000, ANA_REG_GLB_LDO_V_CTRL0, BIT(14)|BIT(15), 4, 2800, 3000, 2500, 1800); + + SCI_REGU_REG(avdd18, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(15), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(15), ANA_REG_GLB_LDO_SLP_CTRL1, BIT(0), + ANA_REG_GLB_LDO_CAL_CTRL3, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(5)|BIT(7)|BIT(17)|BIT(18)|BIT(20), + 1800, ANA_REG_GLB_LDO_V_CTRL1, BIT(0)|BIT(1), 4, 1500, 1800, 1300, 1200); + + SCI_REGU_REG(vddsd, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(1), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(1), + ANA_REG_GLB_LDO_CAL_CTRL3, BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_LDO_CAL_SEL, BIT(11)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 2800, ANA_REG_GLB_LDO_V_CTRL1, BIT(2)|BIT(3), 4, 2800, 3000, 2500, 1800); + + SCI_REGU_REG(vddsim0, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(2), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(2), + ANA_REG_GLB_LDO_CAL_CTRL4, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(9)|BIT(16)|BIT(18)|BIT(20), + 1800, ANA_REG_GLB_LDO_V_CTRL1, BIT(4)|BIT(5), 4, 1800, 2900, 3000, 3100); + + SCI_REGU_REG(vddsim1, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(3), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(3), + ANA_REG_GLB_LDO_CAL_CTRL4, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(9)|BIT(16)|BIT(18)|BIT(20), + 1800, ANA_REG_GLB_LDO_V_CTRL1, BIT(6)|BIT(7), 4, 1800, 2900, 3000, 3100); + + SCI_REGU_REG(vddsim2, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(4), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(4), + ANA_REG_GLB_LDO_CAL_CTRL4, BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_LDO_CAL_SEL, BIT(8)|BIT(9)|BIT(16)|BIT(18)|BIT(20), + 1800, ANA_REG_GLB_LDO_V_CTRL1, BIT(8)|BIT(9), 4, 2800, 3000, 2500, 1800); + + SCI_REGU_REG(vddcama, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(5), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(5), + ANA_REG_GLB_LDO_CAL_CTRL4, BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_CAL_SEL, BIT(12)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 2800, ANA_REG_GLB_LDO_V_CTRL2, BIT(0)|BIT(1), 4, 2800, 3000, 2500, 1800); + + SCI_REGU_REG(vddcamd, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(6), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(6), + ANA_REG_GLB_LDO_CAL_CTRL5, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(5)|BIT(6)|BIT(17)|BIT(18)|BIT(20), + 1500, ANA_REG_GLB_LDO_V_CTRL2, BIT(2)|BIT(3), 4, 1500, 1800, 1300, 1200); + +#ifdef CONFIG_REGULATOR_SUPPORT_CAMIO_1200MV + SCI_REGU_REG(vddcamio, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(7), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(7), + ANA_REG_GLB_LDO_CAL_CTRL5, BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_LDO_CAL_SEL, BIT(5)|BIT(17)|BIT(18)|BIT(20), + 1200, ANA_REG_GLB_LDO_V_CTRL2, BIT(4)|BIT(5), 4, 1100, 1200, 1300, 1600); +#else + SCI_REGU_REG(vddcamio, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(7), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(7), + ANA_REG_GLB_LDO_CAL_CTRL5, BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_LDO_CAL_SEL, BIT(5)|BIT(17)|BIT(18)|BIT(20), + 1800, ANA_REG_GLB_LDO_V_CTRL2, BIT(4)|BIT(5), 4, 1500, 1800, 2500, 2800); +#endif + + SCI_REGU_REG(vddcammot, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(8), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(8), + ANA_REG_GLB_LDO_CAL_CTRL5, BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_CAL_SEL, BIT(12)|BIT(13)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 2800, ANA_REG_GLB_LDO_V_CTRL2, BIT(6)|BIT(7), 4, 3000, 3300, 2800, 1800); + + SCI_REGU_REG(vddusb, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(9), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(9), + ANA_REG_GLB_LDO_CAL_CTRL2, BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_CAL_SEL, BIT(8)|BIT(9)|BIT(10)|BIT(16)|BIT(18)|BIT(20), + 3300, ANA_REG_GLB_LDO_V_CTRL2, BIT(8)|BIT(9), 4, 3300, 3400, 3200, 3100); + + SCI_REGU_REG(vddclsg, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(10), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(10), + ANA_REG_GLB_LDO_CAL_CTRL6, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(6)|BIT(17)|BIT(18)|BIT(20), + 0, ANA_REG_GLB_LDO_V_CTRL2, BIT(10)|BIT(11), 4, 1500, 1800, 1300, 1200); + + SCI_REGU_REG(chg_pump, 0, ANA_REG_GLB_CHGR_CTRL2, BIT(8), 0, 0, 0, 0, + ANA_REG_GLB_CHGR_CTRL2, BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13), 0, 0, + 5000, ANA_REG_GLB_CHGR_CTRL0, BIT(2)|BIT(3), 4, 5000, 5200, 5300, 4800); + + SCI_REGU_REG(led_flash, 4, 0, 0, ANA_REG_GLB_FLASH_CTRL, BIT(15), 0, 0, + ANA_REG_GLB_FLASH_CTRL, BIT(4)|BIT(5)|BIT(6), 0, 0, + 4000, ANA_REG_GLB_FLASH_CTRL, BIT(0)|BIT(1)|BIT(2)|BIT(3), 0); + diff --git a/include/soc/sprd/chip_x20/dram_phy_28nm.h b/include/soc/sprd/chip_x20/dram_phy_28nm.h new file mode 100644 index 00000000..8fce6e9f --- /dev/null +++ b/include/soc/sprd/chip_x20/dram_phy_28nm.h @@ -0,0 +1,487 @@ +#ifndef _DRAM_PHY_28NM_H_ +#define _DRAM_PHY_28NM_H_ + +#define __LPDDR2_BL__ 8 /*4,8,16*/ + +#define NS2CLK_T(ns,clk) (((clk)*(ns)+9999)/10000) +#define MAX(x,y) (((x) > (y)) ? (x) : (y)) + +#ifndef BIT +#define BIT(x) (1 << (x)) +#endif + +typedef enum +{ + /*lpddr1 type*/ + DRAM_LPDDR1 = 0x000, + /*lpddr2 type*/ + DRAM_LPDDR2 = 0x100, + /*lpddr3 type*/ + DRAM_LPDDR3 = 0x200, + /*ddr2 type*/ + DRAM_DDR2 = 0x300, + /*ddr3 type*/ + DRAM_DDR3 = 0x400, +}DRAM_TYPE_E; + +typedef enum{ + CLK_24MHZ = 24, + CLK_26MHZ = 26, + CLK_38_4MHZ = 38, + CLK_48MHZ = 48, + CLK_64MHZ = 64, + CLK_76_8MHZ = 77, + CLK_96MHZ = 96, + CLK_100MHZ = 100, + CLK_153_6MHZ = 154, + CLK_150MHZ = 150, + CLK_166MHZ = 166, + CLK_192MHZ = 192, + CLK_200MHZ = 200, + CLK_250MHZ = 250, + CLK_267MHZ = 267, + CLK_300MHZ = 300, + CLK_332MHZ = 332, + CLK_333MHZ = 333, + CLK_384MHZ = 384, + CLK_400MHZ = 400, + CLK_427MHZ = 427, + CLK_450MHZ = 450, + CLK_464MHZ = 464, + CLK_466MHZ = 466, + CLK_467MHZ = 467, + CLK_500MHZ = 500, + CLK_525MHZ = 525, + CLK_533MHZ = 533, + CLK_537MHZ = 537, + CLK_540MHZ = 540, + CLK_550MHZ = 550, + CLK_800MHZ = 800, + CLK_1000MHZ = 1000, + EMC_CLK_400MHZ = 400, + EMC_CLK_450MHZ = 450, + EMC_CLK_500MHZ = 500 +}CLK_TYPE_E; + +typedef enum +{ + CAP_1CS_2G_X32, + CAP_1CS_4G_X32, + CAP_2CS_2G_X32, + CAP_2CS_3G_X32, + CAP_2CS_4G_X32, + CAP_2CS_5G_X32, + CAP_2CS_6G_X32, + CAP_2CS_8G_X32, + CAP_2CS_12G_X32, + CAP_2CS_16G_X32, + CAP_1CS_2G_X8_4P, + CAP_1CS_4G_X16_2P +}DRAM_CAP_SIZE_E; + +typedef enum +{ + DRAM_BT_SEQ = 0, //burst type = sequential(default) + DRAM_BT_INTER= 1 //burst type = interleaved +}DRAM_BURSTTYPE_E; + +typedef enum +{ + DRAM_WRAP = 0, //warp mode + DRAM_NOWRAP = 1 //no warp mode +}DRAM_WC_E; + +typedef enum +{ +/*Driver strength for lpddr1*/ + LPDDR1_DS_FULL, + LPDDR1_DS_HALF, + LPDDR1_DS_QUARTER, + LPDDR1_DS_OCTANT, + LPDDR1_DS_THREE_QUATERS, +/*Driver strength for lpddr2*/ + LPDDR2_DS_34R3 = 0x01, + LPDDR2_DS_40R = 0x02, + LPDDR2_DS_48R = 0x03, + LPDDR2_DS_60R = 0x04, + LPDDR2_DS_68R6 = 0x05, + LPDDR2_DS_80R = 0x06, + LPDDR2_DS_120R = 0x07, +/*Driver strength for ddr3*/ + DDR3_DS_40R = 0x00, + DDR3_DS_34R3 = 0x01 +}MEM_IODS_E; + +typedef enum +{ + UMCTL2_PORT_MIN = 0, + UMCTL2_PORT_AP = 0, + UMCTL2_PORT_MM = 1, + UMCTL2_PORT_GPU = 2, + UMCTL2_PORT_CP2_P0 = 3, + UMCTL2_PORT_CP1 = 4, + UMCTL2_PORT_AP_MTX = 5, + UMCTL2_PORT_CP0 = 6, + UMCTL2_PORT_CP2_P1 = 7, + UMCTL2_PORT_CP0_MTX = 8, + UMCTL2_PORT_DSP = 9, + UMCTL2_PORT_MAX = 10 +}UMCTL2_PORT_ID_E; + +typedef enum +{ + OPERATION_MODE_INIT = 0x0, + OPERATION_MODE_NORMAL = 0x1, + OPERATION_MODE_PD = 0x2, + OPERATION_MODE_SR = 0x3, + OPERATION_MODE_DPD = 0x4 +}OPERATION_MODE_E; + +typedef struct +{ + unsigned int tREFI; /*average refresh interval time between each row normal=7800ns*/ + unsigned int tMRD; /*lpddr1:set lpddr2:sbz ddr3:set*/ + unsigned int tRAS; /*lpddr1:set lpddr2:set ddr3:set*/ + unsigned int tRC; /*lpddr1:set lpddr2:set ddr3:set*/ + unsigned int tRFC; /*lpddr1:set lpddr2:set ddr3:set*/ + unsigned int tRCD; /*lpddr1:set lpddr2:set ddr3:set*/ + unsigned int tRP; /*lpddr1:set lpddr2:set ddr3:set*/ + unsigned int tRRD; /*lpddr1:set lpddr2:set ddr3:set*/ + unsigned int tWR; /*lpddr1:set lpddr2:set ddr3:set*/ + unsigned int tWTR; /*lpddr1:set lpddr2:set ddr3:set*/ + unsigned int tXSR; /*lpddr1:set lpddr2:set ddr3:sbz*/ + unsigned int tXP; /*lpddr1:set lpddr2:set ddr3:set*/ + unsigned int tCKE; /*lpddr1:set lpddr2:set ddr3:set*/ + unsigned int tRFCab; /*lpddr1:sbz lpddr2:set ddr3:sbz*/ + unsigned int tRFCpb; /*lpddr1:sbz lpddr2:set ddr3:sbz*/ + unsigned int tZQINIT; /*lpddr1:sbz lpddr2:set ddr3:set*/ + unsigned int tZQCL; /*lpddr1:sbz lpddr2:set ddr3:sbz*/ + unsigned int tZQCS; /*lpddr1:sbz lpddr2:set ddr3:set*/ + unsigned int tZQreset; /*lpddr1:sbz lpddr2:set ddr3:sbz*/ + unsigned int tZQoper; /*lpddr1:sbz lpddr2:sbz ddr3:set*/ + unsigned int tCKESR; /*lpddr1:sbz lpddr2:set ddr3:sbz*/ + unsigned int tCCD; /*lpddr1:sbz lpddr2:set ddr3:set*/ + unsigned int tRTP; /*lpddr1:sbz lpddr2:set ddr3:set*/ + unsigned int tFAW; /*lpddr1:sbz lpddr2:set ddr3:set*/ + unsigned int tDPD; /*lpddr1:sbz lpddr2:set ddr3:sbz*/ + unsigned int tDQSCK; /*lpddr1:sbz lpddr2:set ddr3:set*/ + unsigned int tDQSCKmax; /*lpddr1:sbz lpddr2:set ddr3:sbz*/ + unsigned int tMRW; /*lpddr1:sbz lpddr2:set ddr3:sbz*/ + unsigned int tMRR; /*lpddr1:sbz lpddr2:set ddr3:sbz*/ + unsigned int tDLLK; /*lpddr1:sbz lpddr2:sbz ddr3:set*/ + unsigned int tMOD; /*lpddr1:sbz lpddr2:sbz ddr3:set*/ + unsigned int tXS; /*lpddr1:sbz lpddr2:sbz ddr3:set*/ + unsigned int tCKSRE; /*lpddr1:sbz lpddr2:sbz ddr3:set*/ + unsigned int tCKSRX; /*lpddr1:sbz lpddr2:sbz ddr3:set*/ + unsigned int cntRDMode; + unsigned int cntRDDLY; + unsigned int cntDQSGX; + unsigned int cntPGWAIT; + unsigned int cntZQDIV; +}DDR_ACTIMING_T; + +typedef struct +{ + DRAM_TYPE_E dram_type; + DRAM_CAP_SIZE_E cap; + unsigned int cs_num; /*ranks number*/ + unsigned int bank_num; /*banks number*/ + unsigned int io_width; /*bus width*/ + unsigned int bt; /*burst type*/ + unsigned int wc; /*wrap control*/ + unsigned int bl; /*burst length*/ + unsigned int rl; /*read cas latency*/ + unsigned int wl; /*write cas latency*/ + unsigned int al; /*ddr2 ddr3 only Posted CAS additive latency*/ + DDR_ACTIMING_T *ac_timing; + DDR_ACTIMING_T *native_ac_timing; +}DRAM_INFO_T; + +typedef struct +{ + volatile unsigned int umctl_mstr; /* 0x0000 master register*/ + volatile unsigned int umctl_stat; /* 0x0004 operating mode status*/ + volatile unsigned int umctl_resv0[2]; /* 0x0008 ~ 0x000c*/ + volatile unsigned int umctl_mrctrl[2]; /* 0x0010 ~ 0x0014 mode register control*/ + volatile unsigned int umctl_mrstat; /* 0x0018 mode register status*/ + volatile unsigned int umctl_resv1; /* 0x001c */ + volatile unsigned int umctl_derateen; /* 0x0020 temperature derate enable*/ + volatile unsigned int umctl_derateint; /* 0x0024 temperature derate interval*/ + volatile unsigned int umctl_resv2[2]; /* 0x0028 ~ 0x002c */ + volatile unsigned int umctl_pwrctl; /* 0x0030 low power control*/ + volatile unsigned int umctl_pwrtmg; /* 0x0034 low power timing*/ + volatile unsigned int umctl_hwlpctl; /* 0x0038 hardware low power control*/ + volatile unsigned int umctl_resv3[5]; /* 0x003c ~ 0x004c */ + volatile unsigned int umctl_rfshctl[3]; /* 0x0050 ~ 0x0058 refresh control*/ + volatile unsigned int umctl_resv4; /* 0x005c */ + volatile unsigned int umctl_rfshctl3; /* 0x0060 refresh control*/ + volatile unsigned int umctl_rfshtmg; /* 0x0064 refresh timing*/ + volatile unsigned int umctl_resv5[2]; /* 0x0068 ~ 0x006c */ + volatile unsigned int umctl_ecccfg[2]; /* 0x0070 ~ 0x0074 ecc configruation*/ + volatile unsigned int umctl_eccstat; /* 0x0078 ecc status*/ + volatile unsigned int umctl_eccclr; /* 0x007c ecc clear*/ + volatile unsigned int umctl_eccerrcnt; /* 0x0080 ecc error count*/ + volatile unsigned int umctl_ecccaddr[2];/* 0x0084 ~ 0x0088 ecc corrected error address*/ + volatile unsigned int umctl_ecccsyn[3]; /* 0x008c ~ 0x0094 ecc corrected syndrome*/ + volatile unsigned int umctl_eccbitmask[3]; /* 0x0098 ~ 0x00a0 ecc corrected data bit mask*/ + volatile unsigned int umctl_eccuaddr[2];/* 0x00a4 ~ 0x00a8 ecc unorrected error address*/ + volatile unsigned int umctl_eccusyn[3]; /* 0x00ac ~ 0x00b4 ecc uncorrected syndrome*/ + volatile unsigned int umctl_eccpoisonaddr[2]; /* 0x00b8 ~ 0x00bc ecc data poisoning address*/ + volatile unsigned int umctl_parctl; /* 0x00c0 parity control*/ + volatile unsigned int umctl_parstat; /* 0x00c4 parity status*/ + volatile unsigned int umctl_resv6[2]; /* 0x00c8 ~ 0x00cc */ + volatile unsigned int umctl_init[8]; /* 0x00d0 ~ 0x00ec sdram initialization*/ + volatile unsigned int umctl_dimmctl; /* 0x00f0 dimm control*/ + volatile unsigned int umctl_rankctl; /* 0x00f4 rank control*/ + volatile unsigned int umctl_resv7[2]; /* 0x00f8 ~ 0x00fc*/ + volatile unsigned int umctl_dramtmg[12];/* 0x0100 ~ 0x012c sdram timing*/ + volatile unsigned int umctl_resv8[20]; /* 0x0130 ~ 0x017c */ + volatile unsigned int umctl_zqctl[3]; /* 0x0180 ~ 0x0188 zq control*/ + volatile unsigned int umctl_zqstat; /* 0x018c zq status*/ + volatile unsigned int umctl_dfitmg[2]; /* 0x0190 ~ 0x0194 dfi timing*/ + volatile unsigned int umctl_dfilpcfg[2];/* 0x0198 ~ 0x019c dfi low power configruation*/ + volatile unsigned int umctl_dfiupd[4]; /* 0x01a0 ~ 0x01ac dfi update*/ + volatile unsigned int umctl_dfimisc; /* 0x01b0 dfi miscellaneous control*/ + volatile unsigned int umctl_resv9[3]; /* 0x01b4 ~ 0x01bc */ + volatile unsigned int umctl_dbictl; /* 0x01c0 dm/dbi control*/ + volatile unsigned int umctl_resv10[3]; /* 0x01c4 ~ 0x01cc */ + volatile unsigned int umctl_trainctl[3];/* 0x01d0 ~ 0x01d8 phy eval training control*/ + volatile unsigned int umctl_trainstat; /* 0x01dc phy eval training status */ + volatile unsigned int umctl_resv11[8]; /* 0x01e0 ~ 0x01fc */ + volatile unsigned int umctl_addrmap[9]; /* 0x0200 ~ 0x0220 address map */ + volatile unsigned int umctl_resv12[7]; /* 0x0224 ~ 0x023c */ + volatile unsigned int umctl_odtcfg; /* 0x0240 odt configruation */ + volatile unsigned int umctl_odtmap; /* 0x0244 odt/rank map */ + volatile unsigned int umctl_resv13[2]; /* 0x0248 ~ 0x024c */ + volatile unsigned int umctl_sched; /* 0x0250 scheduler control */ + volatile unsigned int umctl_resv14; /* 0x0254 */ + volatile unsigned int umctl_perfhpr[2]; /* 0x0258 ~ 0x025c high priority read*/ + volatile unsigned int umctl_perflpr[2]; /* 0x0260 ~ 0x0264 low priority read */ + volatile unsigned int umctl_perfwr[2]; /* 0x0268 ~ 0x026c write cam */ + volatile unsigned int umctl_resv15[36]; /* 0x0270 ~ 0x02fc */ + volatile unsigned int umctl_dbg[2]; /* 0x0300 ~ 0x0304 debug*/ + volatile unsigned int umctl_dbgcam; /* 0x0308 cam debug*/ + volatile unsigned int umctl_dbgcmd; /* 0x030c cam debug*/ + volatile unsigned int umctl_dbgstat; /* 0x0310 cam debug*/ + volatile unsigned int umctl_resv16[58]; /* 0x0314 ~ 0x03f8 */ + volatile unsigned int umctl_pstat; /* 0x03fc */ + volatile unsigned int umctl_pccfg; /* 0x0400 port common configruation*/ + volatile unsigned int umctl_pcfgr0; /* 0x0404 port 0 configruation read */ + volatile unsigned int umctl_pcfgw0; /* 0x0408 port 0 configruation write*/ + volatile unsigned int umctl_pcfgc0; /* 0x040c port 0 common configruation*/ + volatile unsigned int umctl_pcfgidmaskch0_0; /* 0x0410 channel 0 port 0 configruation*/ + volatile unsigned int umctl_pcfgidvaluech0_0; /* 0x0414 channel 0 port 0 configruation*/ + volatile unsigned int umctl_resv17[30]; /* 0x0418 ~ 0x048c */ + volatile unsigned int umctl_pctrl0; /* 0x0490 port control */ +}DMC_UMCTL_REG_INFO_T,*DMC_UMCTL_REG_INFO_PTR_T; + +/* UMCTL STAT [0x0004] */ +#define BIT_STAT_SELFREF_TYPE ( BIT(5) | BIT(4) ) +#define BIT_STAT_OP_MODE ( BIT(2) | BIT(1) | BIT(0) ) + +/* UMCTL low power control [0x0030] */ +#define BIT_PWRCTL_SELFREF_SW ( BIT(5) ) +#define BIT_PWRCTL_MPSM_EN ( BIT(4) ) +#define BIT_PWRCTL_DFICLK_DIS ( BIT(3) ) +#define BIT_PWRCTL_DEEPPD_EN ( BIT(2) ) +#define BIT_PWRCTL_PD_EN ( BIT(1) ) +#define BIT_PWRCTL_SELFREF_EN ( BIT(0) ) + +/* UMCTL DBG1 */ +#define BIT_DBG1_DIS_DQ ( BIT(0) ) + +/* UMCTL DBGCAM [0x0308] */ +#define BIT_DBGCAM_WR_PP_EPTY ( BIT(29) ) +#define BIT_DBGCAM_RD_PP_EPTY ( BIT(28) ) +#define BIT_DBGCAM_WR_Q_EPTY ( BIT(26) ) +#define BIT_DBGCAM_RD_Q_EPTY ( BIT(25) ) +#define BIT_DBGCAM_STALL ( BIT(24) ) + +/* DFI_MISC */ +#define BIT_DFIMISC_PHY_DBI_MODE ( BIT(1) ) +#define BIT_DFIMISC_DFI_COMP_EN ( BIT(0) ) + +/* RFSHCTL3 [0x0060] */ +#define BIT_RFSHCTL3_RF_MODE ( BIT(6) | BIT(5) | BIT(4) ) +#define BIT_RFSHCTL3_RF_LL ( BIT(1) ) +#define BIT_RFSHCTL3_DIS_AUTO_RF ( BIT(0) ) + +typedef struct +{ + volatile unsigned int publ_ridr; /* 0x0000 revision identification*/ + volatile unsigned int publ_pir; /* 0x0004 phy initialization*/ + volatile unsigned int publ_pgcr[4]; /* 0x0008 ~ 0x0014 phy general configruation*/ + volatile unsigned int publ_pgsr[2]; /* 0x0018 ~ 0x001c phy general status*/ + volatile unsigned int publ_pllcr; /* 0x0020 pll control*/ + volatile unsigned int publ_ptr[5]; /* 0x0024 ~ 0x0034 phy timing*/ + volatile unsigned int publ_acmdlr; /* 0x0038 ac master delay line*/ + volatile unsigned int publ_aclcdlr; /* 0x003c ac local calibrated delay line*/ + volatile unsigned int publ_acbdlr[10]; /* 0x0040 ~ 0x0064 ac bit delay line*/ + volatile unsigned int publ_aciocr[6]; /* 0x0068 ~ 0x007c ac i/o configruation*/ + volatile unsigned int publ_dxccr; /* 0x0080 datx8 common configruation*/ + volatile unsigned int publ_dsgcr; /* 0x0084 datx8 system general configruation*/ + volatile unsigned int publ_dcr; /* 0x0088 dram configruation*/ + volatile unsigned int publ_dtpr[4]; /* 0x008c ~ 0x0098 dram timing parameters*/ + volatile unsigned int publ_mr[4]; /* 0x009c ~ 0x00a8 mode register*/ + volatile unsigned int publ_odtcr; /* 0x00ac odt configruation*/ + volatile unsigned int publ_dtcr; /* 0x00b0 data training configruation*/ + volatile unsigned int publ_dtar[4]; /* 0x00b4 ~ 0x00c0 data training address*/ + volatile unsigned int publ_dtdr[2]; /* 0x00c4 ~ 0x00c8 data training data*/ + volatile unsigned int publ_dtedr[2]; /* 0x00cc ~ 0x00d0 data training address */ + volatile unsigned int publ_rdimmgcr[2]; /* 0x00d4 ~ 0x00d8 rdimm general configruation*/ + volatile unsigned int publ_rdimmcr[2]; /* 0x00dc ~ 0x00e0 rdimm control*/ + volatile unsigned int publ_gpr[2]; /* 0x00e4 ~ 0x00e8 general purpose*/ + volatile unsigned int publ_catr[2]; /* 0x00ec ~ 0x00f0 catr*/ + volatile unsigned int publ_dqsdr; /* 0x00f4 dqs drift detection */ + volatile unsigned int publ_dtmr[2]; /* 0x00f8 ~ 0x00fc data training mask*/ + volatile unsigned int publ_resv0[32]; /* 0x0100 ~ 0x017c */ + volatile unsigned int publ_dcuar; /* 0x0180 DCU address*/ + volatile unsigned int publ_dcudr; /* 0x0184 DCU data*/ + volatile unsigned int publ_dcurr; /* 0x0188 DCU run*/ + volatile unsigned int publ_dculr; /* 0x018c DCU loop*/ + volatile unsigned int publ_dcugcr; /* 0x0190 DCU general configruation*/ + volatile unsigned int publ_dcutpr; /* 0x0194 DCU timing parameters*/ + volatile unsigned int publ_dcusr[2]; /* 0x0198 ~ 0x019c DCU status*/ + volatile unsigned int publ_resv1[8]; /* 0x01a0 ~ 0x01bc */ + volatile unsigned int publ_bistrr; /* 0x01c0 BIST run*/ + volatile unsigned int publ_bistwcr; /* 0x01c4 BIST word count*/ + volatile unsigned int publ_bistmskr[3]; /* 0x01c8 ~ 0x01d0 BIST mask*/ + volatile unsigned int publ_bistlsr; /* 0x01d4 BIST LFSR seed*/ + volatile unsigned int publ_bistar[3]; /* 0x01d8 ~ 0x01e0 BIST address*/ + volatile unsigned int publ_bistudpr; /* 0x01e4 BIST User data pattern*/ + volatile unsigned int publ_bistgsr; /* 0x01e8 BIST general status*/ + volatile unsigned int publ_bistwer; /* 0x01ec BIST word error*/ + volatile unsigned int publ_bistber[4]; /* 0x01f0 ~ 0x01fc BIST bit error*/ + volatile unsigned int publ_bistwcsr; /* 0x0200 BIST word count status*/ + volatile unsigned int publ_bistfwr[3]; /* 0x0204 ~ 0x020c BIST fail word*/ + volatile unsigned int publ_resv2[10]; /* 0x0210 ~ 0x0234 catr*/ + volatile unsigned int publ_iovcr[2]; /* 0x0238 ~ 0x023c IO VREF control*/ + volatile unsigned int publ_zqcr; /* 0x0240 zq impedance control*/ + volatile unsigned int publ_zq0pr; /* 0x0244 zq impedance program*/ + volatile unsigned int publ_zq0dr; /* 0x0248 zq impedance data*/ + volatile unsigned int publ_zq0sr; /* 0x024c zq impedance status*/ + volatile unsigned int publ_resv3; /* 0x0250 */ + volatile unsigned int publ_zq1pr; /* 0x0254 zq impedance program*/ + volatile unsigned int publ_zq1dr; /* 0x0258 zq impedance data*/ + volatile unsigned int publ_zq1sr; /* 0x025c zq impedance status*/ + volatile unsigned int publ_resv4; /* 0x0260 */ + volatile unsigned int publ_zq2pr; /* 0x0264 zq impedance program*/ + volatile unsigned int publ_zq2dr; /* 0x0268 zq impedance data*/ + volatile unsigned int publ_zq2sr; /* 0x026c zq impedance status*/ + volatile unsigned int publ_resv5; /* 0x0270 */ + volatile unsigned int publ_zq3pr; /* 0x0274 zq impedance program*/ + volatile unsigned int publ_zq3dr; /* 0x0278 zq impedance data*/ + volatile unsigned int publ_zq3sr; /* 0x027c zq impedance status*/ + volatile unsigned int publ_dx0gcr[4]; /* 0x0280 ~ 0x028c datx8 general config*/ + volatile unsigned int publ_dx0gsr[3]; /* 0x0290 ~ 0x0298 datx8 general status*/ + volatile unsigned int publ_dx0bdlr[7]; /* 0x029c ~ 0x02b4 datx8 bit delay line*/ + volatile unsigned int publ_dx0lcdlr[3]; /* 0x02b8 ~ 0x02c0 datx8 local cal*/ + volatile unsigned int publ_dx0mdlr; /* 0x02c4 datx8 master delay line*/ + volatile unsigned int publ_dx0gtr; /* 0x02c8 datx8 general timing*/ + volatile unsigned int publ_resv6[13]; /* 0x02cc ~ 0x02fc */ + volatile unsigned int publ_dx1gcr[4]; /* 0x0300 ~ 0x030c datx8 general config*/ + volatile unsigned int publ_dx1gsr[3]; /* 0x0310 ~ 0x0318 datx8 general status*/ + volatile unsigned int publ_dx1bdlr[7]; /* 0x031c ~ 0x0334 datx8 bit delay line*/ + volatile unsigned int publ_dx1lcdlr[3]; /* 0x0338 ~ 0x0340 datx8 local cal*/ + volatile unsigned int publ_dx1mdlr; /* 0x0344 datx8 master delay line*/ + volatile unsigned int publ_dx1gtr; /* 0x0348 datx8 general timing*/ + volatile unsigned int publ_resv7[13]; /* 0x034c ~ 0x037c */ + volatile unsigned int publ_dx2gcr[4]; /* 0x0380 ~ 0x038c datx8 general config*/ + volatile unsigned int publ_dx2gsr[3]; /* 0x0390 ~ 0x0398 datx8 general status*/ + volatile unsigned int publ_dx2bdlr[7]; /* 0x039c ~ 0x03b4 datx8 bit delay line*/ + volatile unsigned int publ_dx2lcdlr[3]; /* 0x03b8 ~ 0x03c0 datx8 local cal*/ + volatile unsigned int publ_dx2mdlr; /* 0x03c4 datx8 master delay line*/ + volatile unsigned int publ_dx2gtr; /* 0x03c8 datx8 general timing*/ + volatile unsigned int publ_resv8[13]; /* 0x03cc ~ 0x03fc */ + volatile unsigned int publ_dx3gcr[4]; /* 0x0400 ~ 0x040c datx8 general config*/ + volatile unsigned int publ_dx3gsr[3]; /* 0x0410 ~ 0x0418 datx8 general status*/ + volatile unsigned int publ_dx3bdlr[7]; /* 0x041c ~ 0x0434 datx8 bit delay line*/ + volatile unsigned int publ_dx3lcdlr[3]; /* 0x0438 ~ 0x0440 datx8 local cal*/ + volatile unsigned int publ_dx3mdlr; /* 0x0444 datx8 master delay line*/ + volatile unsigned int publ_dx3gtr; /* 0x0448 datx8 general timing*/ + volatile unsigned int publ_resv9[13]; /* 0x044c ~ 0x047c */ + volatile unsigned int publ_dx4gcr[4]; /* 0x0480 ~ 0x048c datx8 general config*/ + volatile unsigned int publ_dx4gsr[3]; /* 0x0490 ~ 0x0498 datx8 general status*/ + volatile unsigned int publ_dx4bdlr[7]; /* 0x049c ~ 0x04b4 datx8 bit delay line*/ + volatile unsigned int publ_dx4lcdlr[3]; /* 0x04b8 ~ 0x04c0 datx8 local cal*/ + volatile unsigned int publ_dx4mdlr; /* 0x04c4 datx8 master delay line*/ + volatile unsigned int publ_dx4gtr; /* 0x04c8 datx8 general timing*/ + volatile unsigned int publ_resv10[13]; /* 0x04cc ~ 0x04fc */ + volatile unsigned int publ_dx5gcr[4]; /* 0x0500 ~ 0x050c datx8 general config*/ + volatile unsigned int publ_dx5gsr[3]; /* 0x0510 ~ 0x0518 datx8 general status*/ + volatile unsigned int publ_dx5bdlr[7]; /* 0x051c ~ 0x0534 datx8 bit delay line*/ + volatile unsigned int publ_dx5lcdlr[3]; /* 0x0538 ~ 0x0540 datx8 local cal*/ + volatile unsigned int publ_dx5mdlr; /* 0x0544 datx8 master delay line*/ + volatile unsigned int publ_dx5gtr; /* 0x0548 datx8 general timing*/ + volatile unsigned int publ_resv11[13]; /* 0x054c ~ 0x057c */ + volatile unsigned int publ_dx6gcr[4]; /* 0x0580 ~ 0x058c datx8 general config*/ + volatile unsigned int publ_dx6gsr[3]; /* 0x0590 ~ 0x0598 datx8 general status*/ + volatile unsigned int publ_dx6bdlr[7]; /* 0x059c ~ 0x05b4 datx8 bit delay line*/ + volatile unsigned int publ_dx6lcdlr[3]; /* 0x05b8 ~ 0x05c0 datx8 local cal*/ + volatile unsigned int publ_dx6mdlr; /* 0x05c4 datx8 master delay line*/ + volatile unsigned int publ_dx6gtr; /* 0x05c8 datx8 general timing*/ + volatile unsigned int publ_resv12[13]; /* 0x05cc ~ 0x05fc */ + volatile unsigned int publ_dx7gcr[4]; /* 0x0600 ~ 0x060c datx8 general config*/ + volatile unsigned int publ_dx7gsr[3]; /* 0x0610 ~ 0x0618 datx8 general status*/ + volatile unsigned int publ_dx7bdlr[7]; /* 0x061c ~ 0x0634 datx8 bit delay line*/ + volatile unsigned int publ_dx7lcdlr[3]; /* 0x0638 ~ 0x0640 datx8 local cal*/ + volatile unsigned int publ_dx7mdlr; /* 0x0644 datx8 master delay line*/ + volatile unsigned int publ_dx7gtr; /* 0x0648 datx8 general timing*/ + volatile unsigned int publ_resv13[13]; /* 0x064c ~ 0x067c */ + volatile unsigned int publ_dx8gcr[4]; /* 0x0680 ~ 0x068c datx8 general config*/ + volatile unsigned int publ_dx8gsr[3]; /* 0x0690 ~ 0x0698 datx8 general status*/ + volatile unsigned int publ_dx8bdlr[7]; /* 0x069c ~ 0x06b4 datx8 bit delay line*/ + volatile unsigned int publ_dx8lcdlr[3]; /* 0x06b8 ~ 0x06c0 datx8 local cal*/ + volatile unsigned int publ_dx8mdlr; /* 0x06c4 datx8 master delay line*/ + volatile unsigned int publ_dx8gtr; /* 0x06c8 datx8 general timing*/ + volatile unsigned int publ_resv14[13]; /* 0x06cc ~ 0x06fc */ +}DMC_PUBL_REG_INFO_T,*DMC_PUBL_REG_INFO_PTR_T; + +/* PUBL DSGCR */ +#define BIT_DSGCR_PUREN ( BIT(0) ) +#define BIT_DSGCR_BDISEN ( BIT(1) ) +#define BIT_DSGCR_ZUEN ( BIT(2) ) +#define BIT_DSGCR_LPIOPD ( BIT(3) ) +#define BIT_DSGCR_LPPLLPD ( BIT(4) ) +#define BIT_DSGCR_CUAEN ( BIT(5) ) +#define BIT_DSGCR_DQSGX ( BIT(6) | BIT(7) ) +#define BIT_DSGCR_PUAD ( BIT(8) | BIT(9) | BIT(10) | BIT(11) ) +#define BIT_DSGCR_DTOODT ( BIT(12) ) +#define BIT_DSGCR_DTOPDO ( BIT(13) ) +#define BIT_DSGCR_DTOPDR ( BIT(14) ) +#define BIT_DSGCR_DTOIOM ( BIT(15) ) +#define BIT_DSGCR_DTOOE ( BIT(16) ) +#define BIT_DSGCR_ATOAE ( BIT(17) ) +#define BIT_DSGCR_RPMODE ( BIT(18) ) +#define BIT_DSGCR_SDRMODE ( BIT(19) | BIT(20) ) + +/* PUBL PIR [0x0004] */ +#define BIT_PIR_INIT ( BIT(0) ) +#define BIT_PIR_ZCAL ( BIT(1) ) +#define BIT_PIR_CA ( BIT(2) ) +#define BIT_PIR_PLLINIT ( BIT(4) ) +#define BIT_PIR_DCAL ( BIT(5) ) +#define BIT_PIR_PHYRST ( BIT(6) ) +#define BIT_PIR_DRAMRST ( BIT(7) ) +#define BIT_PIR_DRAMINIT ( BIT(8) ) +#define BIT_PIR_WL ( BIT(9) ) +#define BIT_PIR_QSGATE ( BIT(10) ) +#define BIT_PIR_WLADJ ( BIT(11) ) +#define BIT_PIR_RDDSKW ( BIT(12) ) +#define BIT_PIR_WDDSKW ( BIT(13) ) +#define BIT_PIR_RDEYE ( BIT(14) ) +#define BIT_PIR_WDEYE ( BIT(15) ) +#define BIT_PIR_ICPC ( BIT(16) ) +#define BIT_PIR_PLLBYP ( BIT(17) ) +#define BIT_PIR_CTLDINIT ( BIT(18) ) +#define BIT_PIR_RDIMMINIT ( BIT(19) ) +#define BIT_PIR_CLRSR ( BIT(27) ) +#define BIT_PIR_LOOKBYP ( BIT(28) ) +#define BIT_PIR_DCALBYP ( BIT(29) ) +#define BIT_PIR_ZCALBYP ( BIT(30) ) +#define BIT_PIR_INITBYP ( BIT(31) ) + + +//#define EMC_FREQ_AUTO_TEST + +#endif diff --git a/include/soc/sprd/chip_x20l/__clock_tree.h b/include/soc/sprd/chip_x20l/__clock_tree.h new file mode 100644 index 00000000..3c53b809 --- /dev/null +++ b/include/soc/sprd/chip_x20l/__clock_tree.h @@ -0,0 +1,514 @@ +/* + * Copyright (C) 2013 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +/* + * Clock (0)Name, Clock (1)fixed rate, Clock Enable (2)Ctrl and (3)Bit, + * Clock Divisor (4)Ctrl and (5)Bit, Clock Parent (6)Ctrl and (7)Bit, + * and Parent Select (15)Count and (16)Lists[ ... ...] + */ +SCI_CLK_ADD(ext_26m, 26000000, 0, 0, + 0, 0, 0, 0, 0); + +#if 0 +SCI_CLK_ADD(ext_32k, 32768, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_mpll, 0, REG_PMU_APB_CGM_AP_EN, BIT(6), + REG_AON_APB_MPLL_CFG, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_dpll, 0, REG_PMU_APB_CGM_AP_EN, BIT(1), + REG_AON_APB_DPLL_CFG, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_td_sel_i, 0, REG_PMU_APB_TDPLL_REL_CFG, BIT(0), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_w_sel_i, 0, REG_PMU_APB_WPLL_REL_CFG, BIT(0), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_c_sel_i, 0, REG_PMU_APB_CPLL_REL_CFG, BIT(0), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_wifi_sel_i, 0, REG_PMU_APB_WIFIPLL1_REL_CFG, BIT(0), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_tdpll, 768000000, REG_PMU_APB_CGM_AP_EN, BIT(3), + 0, 0, 0, 0, + 1, &clk_td_sel_i); + +SCI_CLK_ADD(clk_wpll, 921600000, REG_PMU_APB_CGM_AP_EN, BIT(5), + 0, 0, 0, 0, + 1, &clk_w_sel_i); + +SCI_CLK_ADD(clk_cpll, 624000000, REG_PMU_APB_CGM_AP_EN, BIT(2), + 0, 0, 0, 0, + 1, &clk_c_sel_i); + +SCI_CLK_ADD(clk_wifipll, 880000000, REG_PMU_APB_CGM_AP_EN, BIT(4), + 0, 0, 0, 0, + 1, &clk_wifi_sel_i); + +SCI_CLK_ADD(clk_300m, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(0), + 3, 0, 0, 0, + 1, &clk_mpll); + +SCI_CLK_ADD(clk_37m5, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(1), + 24, 0, 0, 0, + 1, &clk_mpll); + +SCI_CLK_ADD(clk_66m_d, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(2), + 8, 0, 0, 0, + 1, &clk_dpll); + +SCI_CLK_ADD(clk_51m2_w, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(23), + 18, 0, 0, 0, + 1, &clk_wpll); + +SCI_CLK_ADD(clk_40m_wf1, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(27), + 22, 0, 0, 0, + 1, &clk_wifipll); + +SCI_CLK_ADD(clk_312m, 0, REG_PMU_APB_CGM_AP_EN, BIT(7), + 2, 0, 0, 0, + 1, &clk_cpll); + +SCI_CLK_ADD(clk_208m, 0, REG_PMU_APB_CGM_AP_EN, BIT(20), + 3, 0, 0, 0, + 1, &clk_cpll); + +SCI_CLK_ADD(clk_104m, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(18), + 6, 0, 0, 0, + 1, &clk_cpll); + +SCI_CLK_ADD(clk_52m, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(19), + 12, 0, 0, 0, + 1, &clk_cpll); + +SCI_CLK_ADD(clk_384m, 0, REG_PMU_APB_CGM_AP_EN, BIT(8), + 2, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_256m, 0, REG_PMU_APB_CGM_AP_EN, BIT(9), + 3, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_192m, 0, REG_PMU_APB_CGM_AP_EN, BIT(10), + 4, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_153m6, 0, REG_PMU_APB_CGM_AP_EN, BIT(11), + 5, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_128m, 0, REG_PMU_APB_CGM_AP_EN, BIT(12), + 6, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_96m, 0, REG_PMU_APB_CGM_AP_EN, BIT(13), + 8, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_76m8, 0, REG_PMU_APB_CGM_AP_EN, BIT(14), + 10, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_64m, 0, REG_PMU_APB_CGM_AP_EN, BIT(15), + 12, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_51m2, 0, REG_PMU_APB_CGM_AP_EN, BIT(16), + 15, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_48m, 0, REG_PMU_APB_CGM_AP_EN, BIT(17), + 16, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_38m4, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(15), + 20, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_24m, 0, REG_PMU_APB_CGM_AP_EN, BIT(18), + 32, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_12m, 0, REG_PMU_APB_CGM_AP_EN, BIT(19), + 64, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_mcu, 0, 0, 0, + REG_AP_AHB_CA7_CKG_CFG, BIT(4)|BIT(5)|BIT(6), REG_AP_AHB_CA7_CKG_CFG, BIT(0)|BIT(1)|BIT(2), + 7, &ext_26m, &clk_dpll, &clk_cpll, &clk_tdpll, &clk_wifipll, &clk_wpll, &clk_mpll); + +SCI_CLK_ADD(clk_ca7_core, 0, 0, 0, + 0, 0, 0, 0, + 1, &clk_mcu); + +SCI_CLK_ADD(clk_ca7_axi, 0, 0, 0, + REG_AP_AHB_CA7_CKG_CFG, BIT(8)|BIT(9)|BIT(10), 0, 0, + 1, &clk_mcu); + +SCI_CLK_ADD(clk_ca7_dbg, 0, REG_AP_AHB_MISC_CKG_EN, BIT(8), + REG_AP_AHB_CA7_CKG_CFG, BIT(16)|BIT(17)|BIT(18), 0, 0, + 1, &clk_mcu); + +SCI_CLK_ADD(clk_ap_ahb, 0, 0, 0, + 0, 0, REG_AP_CLK_AP_AHB_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_76m8, &clk_128m, &clk_192m); + +SCI_CLK_ADD(clk_ap_apb, 0, 0, 0, + 0, 0, REG_AP_CLK_AP_APB_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_64m, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_pub_ahb, 0, 0, 0, + 0, 0, REG_AON_CLK_PUB_AHB_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_emc, 0, 0, 0, + REG_AON_CLK_EMC_CFG, BIT(8)|BIT(9), REG_AON_CLK_EMC_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_256m, &clk_384m, &clk_dpll); + +SCI_CLK_ADD(clk_aon_apb, 0, 0, 0, + REG_AON_CLK_AON_APB_CFG, BIT(8)|BIT(9), REG_AON_CLK_AON_APB_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_76m8, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_zip_emc, 0, REG_AON_APB_APB_EB1, BIT(12), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_disp_emc, 0, REG_AON_APB_APB_EB1, BIT(11), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_gsp, 0, REG_AP_AHB_AHB_EB, BIT(3), + 0, 0, REG_AP_CLK_GSP_CFG, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_96m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_disc0, 0, REG_AP_AHB_AHB_EB, BIT(1), + REG_AP_CLK_DISPC0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_DISPC0_CFG, BIT(0), + 2, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_disc0_dbi, 0, REG_AP_AHB_AHB_EB, BIT(1), + REG_AP_CLK_DISPC0_DBI_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_DISPC0_DBI_CFG, BIT(0)|BIT(1), + 4, &clk_128m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_disc0_dpi, 0, REG_AP_AHB_AHB_EB, BIT(1), + REG_AP_CLK_DISPC0_DPI_CFG, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), REG_AP_CLK_DISPC0_DPI_CFG, BIT(0)|BIT(1), + 4, &clk_128m, &clk_153m6, &clk_192m, &clk_384m); + +SCI_CLK_ADD(clk_disc1, 0, REG_AP_AHB_AHB_EB, BIT(2), + REG_AP_CLK_DISPC1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_DISPC1_CFG, BIT(0), + 2, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_disc1_dbi, 0, REG_AP_AHB_AHB_EB, BIT(2), + REG_AP_CLK_DISPC1_DBI_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_DISPC1_DBI_CFG, BIT(0)|BIT(1), + 4, &clk_128m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_disc1_dpi, 0, REG_AP_AHB_AHB_EB, BIT(2), + REG_AP_CLK_DISPC1_DPI_CFG, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), REG_AP_CLK_DISPC1_DPI_CFG, BIT(0)|BIT(1), + 4, &clk_128m, &clk_153m6, &clk_192m, &clk_384m); + +SCI_CLK_ADD(clk_zipdec_emc, 0, REG_AP_AHB_AHB_EB, BIT(21), + 0, 0, REG_AP_CLK_ZIPENC_CFG, BIT(0)|BIT(1), + 4, &clk_96m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_zipenc_emc, 0, REG_AP_AHB_AHB_EB, BIT(20), + 0, 0, REG_AP_CLK_ZIPENC_CFG, BIT(0)|BIT(1), + 4, &clk_96m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_nandc_ecc, 0, REG_AP_AHB_AHB_EB, BIT(19), + 0, 0, REG_AP_CLK_NANDC_ECC_CFG, BIT(0), + 2, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_nfc, 0, REG_AP_AHB_AHB_EB, BIT(6), + REG_AP_CLK_NFC_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_NFC_CFG, BIT(0)|BIT(1), + 3, &clk_64m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_sdio0, 0, REG_AP_AHB_AHB_EB, BIT(8), + REG_AP_CLK_SDIO0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_SDIO0_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_256m, &clk_312m, &clk_384m); + +SCI_CLK_ADD(clk_sdio1, 0, REG_AP_AHB_AHB_EB, BIT(9), + 0, 0, REG_AP_CLK_SDIO1_CFG, BIT(0)|BIT(1), + 4, &clk_48m, &clk_76m8, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_sdio2, 0, REG_AP_AHB_AHB_EB, BIT(10), + 0, 0, REG_AP_CLK_SDIO2_CFG, BIT(0)|BIT(1), + 4, &clk_48m, &clk_76m8, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_emmc, 0, REG_AP_AHB_AHB_EB, BIT(11), + 0, 0, REG_AP_CLK_EMMC_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_256m, &clk_312m, &clk_384m); + +SCI_CLK_ADD(clk_gps_tcxo, 64000000, REG_AP_CLK_GPS_TCXO_CFG, BIT(16), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_gps, 0, REG_AP_AHB_AHB_EB, BIT(12), + 0, 0, REG_AP_CLK_GPS_CFG, BIT(0), + 2, &clk_64m, &clk_76m8); + +SCI_CLK_ADD(clk_usb_ref, 0, REG_AP_AHB_AHB_EB, BIT(4), + 0, 0, REG_AP_CLK_USB_REF_CFG, BIT(0), + 2, &clk_12m, &clk_24m); + +SCI_CLK_ADD(clk_uart0, 0, REG_AP_APB_APB_EB, BIT(13), + REG_AP_CLK_UART0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_UART0_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart1, 0, REG_AP_APB_APB_EB, BIT(14), + REG_AP_CLK_UART1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_UART1_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart2, 0, REG_AP_APB_APB_EB, BIT(15), + REG_AP_CLK_UART2_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_UART2_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart3, 0, REG_AP_APB_APB_EB, BIT(16), + REG_AP_CLK_UART3_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_UART3_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_i2c0, 0, REG_AP_APB_APB_EB, BIT(8), + REG_AP_CLK_I2C0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_I2C0_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_i2c1, 0, REG_AP_APB_APB_EB, BIT(9), + REG_AP_CLK_I2C1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_I2C1_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_i2c2, 0, REG_AP_APB_APB_EB, BIT(10), + REG_AP_CLK_I2C2_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_I2C2_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_i2c3, 0, REG_AP_APB_APB_EB, BIT(11), + REG_AP_CLK_I2C3_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_I2C3_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_spi0, 0, REG_AP_APB_APB_EB, BIT(5), + REG_AP_CLK_SPI0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_SPI0_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_spi1, 0, REG_AP_APB_APB_EB, BIT(6), + REG_AP_CLK_SPI1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_SPI1_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_spi2, 0, REG_AP_APB_APB_EB, BIT(7), + REG_AP_CLK_SPI2_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_SPI2_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_iis0, 0, REG_AP_APB_APB_EB, BIT(1), + REG_AP_CLK_IIS0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_IIS0_CFG, BIT(0)|BIT(1), + 3, &ext_26m, &clk_76m8, &clk_128m); + +SCI_CLK_ADD(clk_iis1, 0, REG_AP_APB_APB_EB, BIT(2), + REG_AP_CLK_IIS1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_IIS1_CFG, BIT(0)|BIT(1), + 3, &ext_26m, &clk_76m8, &clk_128m); + +SCI_CLK_ADD(clk_gpu_top_i, 0, REG_PMU_APB_PD_GPU_TOP_CFG+1, BIT(25), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_gpu_i, 0, REG_AON_APB_APB_EB0, BIT(27), + 0, 0, 0, 0, + 1, &clk_gpu_top_i); + +SCI_CLK_ADD(clk_gpu, 0, &clk_gpu_i, 0, + REG_GPU_APB_APB_CLK_CTRL, BIT(2)|BIT(3), REG_GPU_APB_APB_CLK_CTRL, BIT(0)|BIT(1), + 4, &clk_208m, &clk_256m, &clk_300m, &clk_312m); + +SCI_CLK_ADD(clk_mm_top_i, 0, REG_PMU_APB_PD_MM_TOP_CFG+1, BIT(25), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_mm_i, 0, REG_AON_APB_APB_EB0, BIT(25), + 0, 0, 0, 0, + 1, &clk_mm_top_i); + +SCI_CLK_ADD(clk_mm_ahb, 0, 0, 0, + 0, 0, REG_MM_CLK_MM_AHB_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_mm_mtx_axi, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(8), + 0, 0, 0, 0, + 1, &clk_mm_i); + +SCI_CLK_ADD(clk_mm_axi, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(7), + 0, 0, 0, 0, + 1, &clk_mm_mtx_axi); + +SCI_CLK_ADD(clk_mmu, 0, REG_MM_AHB_AHB_EB, BIT(7), + 0, 0, 0, 0, + 1, &clk_mm_ahb); +SCI_CLK_ADD(clk_mm_ckg_i, 0, REG_MM_AHB_AHB_EB, BIT(6), + 0, 0, 0, 0, + 1, &clk_mm_i); + +SCI_CLK_ADD(clk_jpg_i, 0, REG_MM_AHB_AHB_EB, BIT(5), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_jpg_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(6), + 0, 0, 0, 0, + 1, &clk_jpg_i); + +SCI_CLK_ADD(clk_jpg, 0, &clk_jpg_ckg_i, 0, + 0, 0, REG_MM_CLK_JPG_CFG, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_vsp_i, 0, REG_MM_AHB_AHB_EB, BIT(3), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_vsp_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(5), + 0, 0, 0, 0, + 1, &clk_vsp_i); + +SCI_CLK_ADD(clk_vsp, 0, &clk_vsp_ckg_i, 0, + 0, 0, REG_MM_CLK_VSP_CFG, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_sensor_i, 0, REG_MM_AHB_AHB_EB, BIT(1), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_sensor_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(2), + 0, 0, 0, 0, + 1, &clk_sensor_i); + +SCI_CLK_ADD(clk_sensor, 0, &clk_sensor_ckg_i, 0, + REG_MM_CLK_SENSOR_CFG, BIT(8)|BIT(9)|BIT(10), REG_MM_CLK_SENSOR_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_76m8, &clk_96m); + +SCI_CLK_ADD(clk_ccir_in, 64000000, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_ccir_i, 0, REG_MM_AHB_AHB_EB, BIT(1), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_ccir, 0, &clk_ccir_i, 0, + 0, 0, REG_MM_CLK_CCIR_CFG, BIT(16), + 2, &clk_24m, &clk_ccir_in); + +SCI_CLK_ADD(clk_dcam_i, 0, REG_MM_AHB_AHB_EB, BIT(0), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_dcam_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(3), + 0, 0, 0, 0, + 1, &clk_dcam_i); + +SCI_CLK_ADD(clk_dcam, 0, &clk_dcam_ckg_i, 0, + 0, 0, REG_MM_CLK_DCAM_CFG, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_csi_i, 0, REG_MM_AHB_AHB_EB, BIT(4), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_csi_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(1), + 0, 0, 0, 0, + 1, &clk_csi_i); + +SCI_CLK_ADD(clk_cphy_cfg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(0), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_dcam_mipi, 0, &clk_cphy_cfg_i, 0, + 0, 0, 0, 0, + 1, &clk_csi_ckg_i); + +SCI_CLK_ADD(clk_aud, 0, REG_AON_APB_APB_EB0, BIT(18), + 0, 0, 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_audif, 0, REG_AON_APB_APB_EB0, BIT(17), + 0, 0, REG_AON_CLK_AUDIF_CFG, BIT(0)|BIT(1), + 3, &ext_26m, &clk_38m4, &clk_51m2); + +SCI_CLK_ADD(clk_vbc, 0, REG_AON_APB_APB_EB0, BIT(19), + 0, 0, 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_fm_in, 64000000, REG_AON_CLK_FM_CFG, BIT(16), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_fm, 0, REG_AON_APB_APB_EB0, BIT(1), + 0, 0, 0, 0, + 1, &clk_fm_in); + +SCI_CLK_ADD(clk_adi, 0, REG_AON_APB_APB_EB0, BIT(16), + 0, 0, REG_AON_CLK_ADI_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_38m4, &clk_51m2, &clk_64m); + +SCI_CLK_ADD(clk_aux0, 0, REG_AON_APB_APB_EB1, BIT(2), + REG_AON_APB_AON_CGM_CFG, BIT(16)|BIT(17)|BIT(18)|BIT(19), REG_AON_APB_AON_CGM_CFG, BIT(0)|BIT(1)|BIT(2)|BIT(3), + 9, &ext_32k, &ext_26m, &ext_26m, &clk_48m, &clk_52m, &clk_51m2_w, &clk_37m5, &clk_40m_wf1, &clk_66m_d); + +SCI_CLK_ADD(clk_aux1, 0, REG_AON_APB_APB_EB1, BIT(3), + REG_AON_APB_AON_CGM_CFG, BIT(20)|BIT(21)|BIT(22)|BIT(23), REG_AON_APB_AON_CGM_CFG, BIT(4)|BIT(5)|BIT(6)|BIT(7), + 9, &ext_32k, &ext_26m, &ext_26m, &clk_48m, &clk_52m, &clk_51m2_w, &clk_37m5, &clk_40m_wf1, &clk_66m_d); + +SCI_CLK_ADD(clk_aux2, 0, REG_AON_APB_APB_EB1, BIT(4), + REG_AON_APB_AON_CGM_CFG, BIT(24)|BIT(25)|BIT(26)|BIT(27), REG_AON_APB_AON_CGM_CFG, BIT(8)|BIT(9)|BIT(10)|BIT(11), + 9, &ext_32k, &ext_26m, &ext_26m, &clk_48m, &clk_52m, &clk_51m2_w, &clk_37m5, &clk_40m_wf1, &clk_66m_d); + +SCI_CLK_ADD(clk_pwm0, 0, REG_AON_APB_APB_EB0, BIT(4), + 0, 0, REG_AON_CLK_PWM0_CFG, BIT(0), + 2, &ext_32k, &ext_26m); + +SCI_CLK_ADD(clk_pwm1, 0, REG_AON_APB_APB_EB0, BIT(5), + 0, 0, REG_AON_CLK_PWM1_CFG, BIT(0), + 2, &ext_32k, &ext_26m); + +SCI_CLK_ADD(clk_pwm2, 0, REG_AON_APB_APB_EB0, BIT(6), + 0, 0, REG_AON_CLK_PWM2_CFG, BIT(0), + 2, &ext_32k, &ext_26m); + +SCI_CLK_ADD(clk_pwm3, 0, REG_AON_APB_APB_EB0, BIT(7), + 0, 0, REG_AON_CLK_PWM3_CFG, BIT(0), + 2, &ext_32k, &ext_26m); + +SCI_CLK_ADD(clk_efuse, 0, REG_AON_APB_APB_EB0, BIT(13), + 0, 0, 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_ca7_dap, 0, REG_AON_APB_APB_EB0, BIT(30), + 0, 0, REG_AON_CLK_CA7_DAP_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_76m8, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_ca7_ts, 0, REG_AON_APB_APB_EB0, BIT(28), + 0, 0, REG_AON_CLK_CA7_TS_CFG, BIT(0)|BIT(1), + 4, &ext_32k, &ext_26m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_mspi, 0, REG_AON_APB_APB_EB0, BIT(23), + 0, 0, REG_AON_CLK_MSPI_CFG, BIT(0)|BIT(1), + 3, &clk_52m, &clk_76m8, &clk_96m); + +SCI_CLK_ADD(clk_i2c, 0, REG_AON_APB_APB_EB0, BIT(31), + 0, 0, REG_AON_CLK_I2C_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_avs0, 0, REG_AON_APB_APB_EB0, BIT(6), + 0, 0, REG_AON_CLK_AVS0_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_avs1, 0, REG_AON_APB_APB_EB0, BIT(7), + 0, 0, REG_AON_CLK_AVS1_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); +#endif diff --git a/include/soc/sprd/chip_x20l/__regs_ada_apb_rf.h b/include/soc/sprd/chip_x20l/__regs_ada_apb_rf.h new file mode 100644 index 00000000..fbe0bd89 --- /dev/null +++ b/include/soc/sprd/chip_x20l/__regs_ada_apb_rf.h @@ -0,0 +1,177 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_ADA_APB_RF_HEADFILE_H__ +#define __H_REGS_ADA_APB_RF_HEADFILE_H__ __FILE__ + +#define REGS_ADA_APB_RF + +/* registers definitions for ADA_APB_RF */ +#define REG_ADA_APB_RF_APB_DAC_CTR0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0000) +#define REG_ADA_APB_RF_APB_DAC_CTR1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0004) +#define REG_ADA_APB_RF_APB_DAC_CTR2 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0008) +#define REG_ADA_APB_RF_APB_DAC_CTR3 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x000C) +#define REG_ADA_APB_RF_APB_DAC_CTR4 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0010) +#define REG_ADA_APB_RF_APB_DAC_STS0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0014) +#define REG_ADA_APB_RF_APB_DAC_STS1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0018) +#define REG_ADA_APB_RF_APB_ADC0_CTR0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x001C) +#define REG_ADA_APB_RF_APB_ADC0_CTR1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0020) +#define REG_ADA_APB_RF_APB_ADC0_CTR2 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0024) +#define REG_ADA_APB_RF_APB_ADC0_CTR3 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0028) +#define REG_ADA_APB_RF_APB_CAL_CTR0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0030) +#define REG_ADA_APB_RF_APB_CAL_CTR1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0034) +#define REG_ADA_APB_RF_APB_CAL_CTR3 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x003C) +#define REG_ADA_APB_RF_APB_CAL_STS0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0044) +#define REG_ADA_APB_RF_APB_CAL_STS1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0048) +#define REG_ADA_APB_RF_APB_ADA_CTRL0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0054) +#define REG_ADA_APB_RF_APB_ADA_CTRL1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0058) +#define REG_ADA_APB_RF_APB_RX_GSM_DFT SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x005C) +#define REG_ADA_APB_RF_APB_RX_3G_DFT SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0060) + + + +/* bits definitions for register REG_ADA_APB_RF_APB_DAC_CTR0 */ +#define BITS_DAC_PCTRL_1(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BIT_DAC_OUT_SEL_1 ( BIT(17) ) +#define BIT_DAC_CLK_SEL_1 ( BIT(16) ) +#define BITS_DAC_PCTRL_0(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_DAC_OUT_SEL_0 ( BIT(1) ) +#define BIT_DAC_CLK_SEL_0 ( BIT(0) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_DAC_CTR1 */ +#define BITS_DAC_WD_OVR(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DAC_WADDR_OVR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DAC_WLE_OVR ( BIT(2) ) +#define BIT_DAC_W_OVR_I_QN ( BIT(1) ) +#define BIT_DAC_W_OVR_EN ( BIT(0) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_DAC_CTR2 */ +#define BITS_DAC_RSV(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BIT_DAC_IQ_OUT_MSB_INV ( BIT(21) ) +#define BIT_DAC_IQ_IN_MSB_INV ( BIT(20) ) +#define BIT_DAC_OVR_EN_CAL ( BIT(19) ) +#define BIT_DAC_EN_OOSCAL ( BIT(18) ) +#define BIT_DAC_IQ_SWAP ( BIT(17) ) +#define BIT_DAC_CAL_START ( BIT(16) ) +#define BITS_DAC_OFFSETI(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DAC_OFFSETQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_DAC_CTR3 */ +#define BITS_DAC_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_DAC_CTR4 */ +#define BITS_DAC_I_CAL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC_Q_CAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_DAC_STS0 */ +#define BITS_DAC_WTI(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DAC_WTQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_DAC_STS1 */ +#define BITS_DAC_DA_STATE(_X_) ( (_X_) << 17 & (BIT(17)|BIT(18)) ) +#define BIT_DAC_DONE ( BIT(16) ) +#define BITS_DAC_WQ_OVR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_ADC0_CTR0 */ +#define BITS_ADC0_CALRDOUT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BIT_ADC0_CAL_SOFT_RST ( BIT(10) ) +#define BIT_ADC0_CALRD ( BIT(9) ) +#define BIT_ADC0_CALEN ( BIT(8) ) +#define BITS_ADC0_CALADDR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_ADC0_CTR1 */ +#define BITS_ADC0_DLL_OUT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_ADC0_DLLOOF(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)) ) +#define BIT_ADC0_IQ_SWAP ( BIT(14) ) +#define BITS_ADC0_DLLIN(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_ADC0_IQ_OUT_MSB_INV ( BIT(7) ) +#define BIT_ADC0_IQ_IN_MSB_INV ( BIT(6) ) +#define BIT_ADC0_DLL_SOFT_RST ( BIT(4) ) +#define BIT_ADC0_DLLWR ( BIT(3) ) +#define BIT_ADC0_DLLRD ( BIT(2) ) +#define BIT_ADC0_DLLEN ( BIT(1) ) +#define BIT_ADC0_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_ADC0_CTR2 */ +#define BITS_ADC0_RSV_0(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ADC0_DIG_CLK_SEL_0 ( BIT(11) ) +#define BIT_ADC0_VCM_SEL_0 ( BIT(10) ) +#define BITS_ADC0_DELAY_CAP_0(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ADC0_BIT_SEL_0(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_ADC0_VREF_SEL_0(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_ADC0_VREF_BOOST_0(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_ADC0_QUANT_BOOST_0(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_ADC0_CTR3 */ +#define BITS_ADC0_RSV_1(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ADC0_DIG_CLK_SEL_1 ( BIT(11) ) +#define BIT_ADC0_VCM_SEL_1 ( BIT(10) ) +#define BITS_ADC0_DELAY_CAP_1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ADC0_BIT_SEL_1(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_ADC0_VREF_SEL_1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_ADC0_VREF_BOOST_1(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_ADC0_QUANT_BOOST_1(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_CAL_CTR0 */ +#define BIT_LDO_EN_AUTO_EN ( BIT(27) ) +#define BIT_LDO_EN_FRC ( BIT(26) ) +#define BIT_BG_EN_AUTO_EN ( BIT(25) ) +#define BIT_BG_EN_FRC ( BIT(24) ) +#define BITS_ADC_CLK_CAL_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_ADA_CAL_WAIT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_CLK_ADA_CAL_EN ( BIT(6) ) +#define BIT_DAC_PD_CAL ( BIT(5) ) +#define BIT_ADC0_EN_CAL ( BIT(3) ) +#define BIT_ADC0_CAL ( BIT(1) ) +#define BIT_ADA_MODE_SEL ( BIT(0) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_CAL_CTR1 */ +#define BITS_ADC0_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) ) +#define BITS_ADC0_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_CAL_CTR3 */ +#define BIT_ADA0_CAL_START ( BIT(0) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_CAL_STS0 */ +#define BIT_ADA0_CAL_DONE ( BIT(31) ) +#define BITS_ADC0_I_CAL_RESULT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_CAL_STS1 */ +#define BITS_ADC0_Q_CAL_RESULT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_ADA_CTRL0 */ +#define BITS_ADA_AUTO_CTRL(_X_) (_X_) + +/* bits definitions for register REG_ADA_APB_RF_APB_ADA_CTRL1 */ +#define BITS_ADA_FRC_CTRL(_X_) (_X_) + +/* bits definitions for register REG_ADA_APB_RF_APB_RX_GSM_DFT */ +#define BITS_RX_GSM_DFT_Q(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) ) +#define BITS_RX_GSM_DFT_I(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_RX_3G_DFT */ +#define BITS_RX_3G_DFT_Q(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) ) +#define BITS_RX_3G_DFT_I(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) + +#endif diff --git a/include/soc/sprd/chip_x20l/__regs_ana_glb.h b/include/soc/sprd/chip_x20l/__regs_ana_glb.h new file mode 100644 index 00000000..97d72f38 --- /dev/null +++ b/include/soc/sprd/chip_x20l/__regs_ana_glb.h @@ -0,0 +1,836 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __ANA_REGS_GLB_H__ +#define __ANA_REGS_GLB_H__ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, include <mach/sci_glb_regs.h>" +#endif + +#define ANA_REGS_GLB + +/* registers definitions for controller ANA_REGS_GLB */ +#define ANA_REG_GLB_ARM_MODULE_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0000) +#define ANA_REG_GLB_ARM_CLK_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0004) +#define ANA_REG_GLB_RTC_CLK_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0008) +#define ANA_REG_GLB_ARM_RST SCI_ADDR(ANA_REGS_GLB_BASE, 0x000C) +#define ANA_REG_GLB_LDO_DCDC_PD_RTCSET SCI_ADDR(ANA_REGS_GLB_BASE, 0x0010) +#define ANA_REG_GLB_LDO_DCDC_PD_RTCCLR SCI_ADDR(ANA_REGS_GLB_BASE, 0x0014) +#define ANA_REG_GLB_RTC_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0018) +#define ANA_REG_GLB_LDO_PD_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x001C) +#define ANA_REG_GLB_LDO_V_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0020) +#define ANA_REG_GLB_LDO_V_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0024) +#define ANA_REG_GLB_LDO_V_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0028) +#define ANA_REG_GLB_LDO_CAL_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x002C) +#define ANA_REG_GLB_LDO_CAL_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0030) +#define ANA_REG_GLB_LDO_CAL_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0034) +#define ANA_REG_GLB_LDO_CAL_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0038) +#define ANA_REG_GLB_LDO_CAL_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x003C) +#define ANA_REG_GLB_LDO_CAL_CTRL5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0040) +#define ANA_REG_GLB_LDO_CAL_CTRL6 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0044) +#define ANA_REG_GLB_AUXAD_CTL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0048) +#define ANA_REG_GLB_DCDC_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x004C) +#define ANA_REG_GLB_DCDC_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0050) +#define ANA_REG_GLB_DCDC_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0054) +#define ANA_REG_GLB_DCDC_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0058) +#define ANA_REG_GLB_DCDC_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x005C) +#define ANA_REG_GLB_DCDC_CTRL5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0060) +#define ANA_REG_GLB_DCDC_CTRL6 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0064) +#define ANA_REG_GLB_DDR2_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0068) +#define ANA_REG_GLB_SLP_WAIT_DCDCARM SCI_ADDR(ANA_REGS_GLB_BASE, 0x006C) +#define ANA_REG_GLB_LDO1828_XTL_CTL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0070) +#define ANA_REG_GLB_LDO_SLP_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0074) +#define ANA_REG_GLB_LDO_SLP_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0078) +#define ANA_REG_GLB_LDO_SLP_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x007C) +#define ANA_REG_GLB_LDO_SLP_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0080) +#define ANA_REG_GLB_AUD_SLP_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0084) +#define ANA_REG_GLB_DCDC_SLP_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0088) +#define ANA_REG_GLB_XTL_WAIT_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x008C) +#define ANA_REG_GLB_FLASH_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0090) +#define ANA_REG_GLB_WHTLED_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0094) +#define ANA_REG_GLB_WHTLED_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0098) +#define ANA_REG_GLB_WHTLED_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x009C) +#define ANA_REG_GLB_ANA_DRV_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A0) +#define ANA_REG_GLB_VIBR_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A4) +#define ANA_REG_GLB_VIBR_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A8) +#define ANA_REG_GLB_VIBR_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00AC) +#define ANA_REG_GLB_VIBR_WR_PROT_VALUE SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B0) +#define ANA_REG_GLB_AUDIO_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B4) +#define ANA_REG_GLB_CHGR_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B8) +#define ANA_REG_GLB_CHGR_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00BC) +#define ANA_REG_GLB_CHGR_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C0) +#define ANA_REG_GLB_CHGR_STATUS SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C4) +#define ANA_REG_GLB_ANA_MIXED_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C8) +#define ANA_REG_GLB_PWR_XTL_EN0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00CC) +#define ANA_REG_GLB_PWR_XTL_EN1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D0) +#define ANA_REG_GLB_PWR_XTL_EN2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D4) +#define ANA_REG_GLB_PWR_XTL_EN3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D8) +#define ANA_REG_GLB_PWR_XTL_EN4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00DC) +#define ANA_REG_GLB_PWR_XTL_EN5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E0) +#define ANA_REG_GLB_ANA_STATUS SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E4) +#define ANA_REG_GLB_POR_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E8) +#define ANA_REG_GLB_WDG_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x00EC) +#define ANA_REG_GLB_POR_PIN_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F0) +#define ANA_REG_GLB_POR_SRC_FLAG SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F4) +#define ANA_REG_GLB_POR_7S_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F8) +#define ANA_REG_GLB_INT_DEBUG SCI_ADDR(ANA_REGS_GLB_BASE, 0x00FC) +#define ANA_REG_GLB_GPI_DEBUG SCI_ADDR(ANA_REGS_GLB_BASE, 0x0100) +#define ANA_REG_GLB_HWRST_RTC SCI_ADDR(ANA_REGS_GLB_BASE, 0x0104) +#define ANA_REG_GLB_CHIP_ID_LOW SCI_ADDR(ANA_REGS_GLB_BASE, 0x0108) +#define ANA_REG_GLB_CHIP_ID_HIGH SCI_ADDR(ANA_REGS_GLB_BASE, 0x010C) +#define ANA_REG_GLB_ARM_MF_REG SCI_ADDR(ANA_REGS_GLB_BASE, 0x0110) +#define ANA_REG_GLB_AFUSE_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0114) +#define ANA_REG_GLB_AFUSE_OUT0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0118) +#define ANA_REG_GLB_AFUSE_OUT1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x011C) +#define ANA_REG_GLB_AFUSE_OUT2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0120) +#define ANA_REG_GLB_AFUSE_OUT3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0124) +#define ANA_REG_GLB_ARCH_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0128) +#define ANA_REG_GLB_MCU_WR_PROT_VALUE SCI_ADDR(ANA_REGS_GLB_BASE, 0x012C) +#define ANA_REG_GLB_MP_MISC_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0148) +#define ANA_REG_GLB_DCDC_CORE_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0160) +#define ANA_REG_GLB_DCDC_ARM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0164) +#define ANA_REG_GLB_DCDC_MEM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0168) +#define ANA_REG_GLB_DCDC_GEN_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x016C) +#define ANA_REG_GLB_DCDC_WRF_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0170) +#define ANA_REG_GLB_DCDC_WPA_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0174) +#define ANA_REG_GLB_DCDC_WPA_DCM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x017C) +#define ANA_REG_GLB_LDO_CAL_SEL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0044) + +/* bits definitions for register ANA_REG_GLB_ARM_MODULE_EN */ +#define BIT_ANA_THM_EN ( BIT(12) ) +#define BIT_ANA_BLTC_EN ( BIT(10) ) +#define BIT_ANA_PINREG_EN ( BIT(9) ) +#define BIT_ANA_FGU_EN ( BIT(8) ) +#define BIT_ANA_GPIO_EN ( BIT(7) ) +#define BIT_ANA_ADC_EN ( BIT(6) ) +#define BIT_ANA_HDT_EN ( BIT(5) ) +#define BIT_ANA_AUD_EN ( BIT(4) ) +#define BIT_ANA_EIC_EN ( BIT(3) ) +#define BIT_ANA_WDG_EN ( BIT(2) ) +#define BIT_ANA_RTC_EN ( BIT(1) ) + +/* bits definitions for register ANA_REG_GLB_ARM_CLK_EN */ +#define BIT_CLK_AUXAD_EN ( BIT(9) ) +#define BIT_CLK_AUXADC_EN ( BIT(8) ) +#define BIT_CLK_AUD_HID_EN ( BIT(5) ) +#define BIT_CLK_AUD_HBD_EN ( BIT(4) ) +#define BIT_CLK_AUD_LOOP_EN ( BIT(3) ) +#define BIT_CLK_AUD_6P5M_EN ( BIT(2) ) +#define BIT_CLK_AUDIF_EN ( BIT(1) ) + +/* bits definitions for register ANA_REG_GLB_RTC_CLK_EN */ +#define BIT_RTC_FLASH_EN ( BIT(13) ) +#define BIT_RTC_THMA_AUTO_EN ( BIT(12) ) +#define BIT_RTC_THMA_EN ( BIT(11) ) +#define BIT_RTC_THM_EN ( BIT(10) ) +#define BIT_RTC_BLTC_EN ( BIT(8) ) +#define BIT_RTC_FGU_EN ( BIT(7) ) +#define BIT_RTC_FGUA_EN ( BIT(6) ) +#define BIT_RTC_VIBR_EN ( BIT(5) ) +#define BIT_RTC_AUD_EN ( BIT(4) ) +#define BIT_RTC_EIC_EN ( BIT(3) ) +#define BIT_RTC_WDG_EN ( BIT(2) ) +#define BIT_RTC_RTC_EN ( BIT(1) ) +#define BIT_RTC_ARCH_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_ARM_RST */ +#define BIT_ANA_THMA_SOFT_RST ( BIT(14) ) +#define BIT_ANA_THM_SOFT_RST ( BIT(13) ) +#define BIT_ANA_AUD_32K_SOFT_RST ( BIT(12) ) +#define BIT_ANA_AUDTX_SOFT_RST ( BIT(11) ) +#define BIT_ANA_AUDRX_SOFT_RST ( BIT(10) ) +#define BIT_ANA_AUD_SOFT_RST ( BIT(9) ) +#define BIT_ANA_AUD_HDT_SOFT_RST ( BIT(8) ) +#define BIT_ANA_GPIO_SOFT_RST ( BIT(7) ) +#define BIT_ANA_ADC_SOFT_RST ( BIT(6) ) +#define BIT_ANA_PWM0_SOFT_RST ( BIT(5) ) +#define BIT_ANA_FGU_SOFT_RST ( BIT(4) ) +#define BIT_ANA_EIC_SOFT_RST ( BIT(3) ) +#define BIT_ANA_WDG_SOFT_RST ( BIT(2) ) +#define BIT_ANA_RTC_SOFT_RST ( BIT(1) ) +#define BIT_ANA_BLTC_SOFT_RST ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_DCDC_PD_RTCSET */ +#define BIT_DCDC_OTP_PD_RTCSET ( BIT(14) ) +#define BIT_DCDC_WRF_PD_RTCSET ( BIT(13) ) +#define BIT_DCDC_GEN_PD_RTCSET ( BIT(12) ) +#define BIT_DCDC_MEM_PD_RTCSET ( BIT(11) ) +#define BIT_DCDC_ARM_PD_RTCSET ( BIT(10) ) +#define BIT_DCDC_CORE_PD_RTCSET ( BIT(9) ) +#define BIT_LDO_EMMCCORE_PD_RTCSET ( BIT(8) ) +#define BIT_LDO_EMMCIO_PD_RTCSET ( BIT(7) ) +#define BIT_LDO_RF2_PD_RTCSET ( BIT(6) ) +#define BIT_LDO_RF1_PD_RTCSET ( BIT(5) ) +#define BIT_LDO_RF0_PD_RTCSET ( BIT(4) ) +#define BIT_LDO_VDD25_PD_RTCSET ( BIT(3) ) +#define BIT_LDO_VDD28_PD_RTCSET ( BIT(2) ) +#define BIT_LDO_VDD18_PD_RTCSET ( BIT(1) ) +#define BIT_BG_PD_RTCSET ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_DCDC_PD_RTCCLR */ +#define BIT_DCDC_OTP_PD_RTCCLR ( BIT(14) ) +#define BIT_DCDC_WRF_PD_RTCCLR ( BIT(13) ) +#define BIT_DCDC_GEN_PD_RTCCLR ( BIT(12) ) +#define BIT_DCDC_MEM_PD_RTCCLR ( BIT(11) ) +#define BIT_DCDC_ARM_PD_RTCCLR ( BIT(10) ) +#define BIT_DCDC_CORE_PD_RTCCLR ( BIT(9) ) +#define BIT_LDO_EMMCCORE_PD_RTCCLR ( BIT(8) ) +#define BIT_LDO_EMMCIO_PD_RTCCLR ( BIT(7) ) +#define BIT_LDO_RF2_PD_RTCCLR ( BIT(6) ) +#define BIT_LDO_RF1_PD_RTCCLR ( BIT(5) ) +#define BIT_LDO_RF0_PD_RTCCLR ( BIT(4) ) +#define BIT_LDO_VDD25_PD_RTCCLR ( BIT(3) ) +#define BIT_LDO_VDD28_PD_RTCCLR ( BIT(2) ) +#define BIT_LDO_VDD18_PD_RTCCLR ( BIT(1) ) +#define BIT_BG_PD_RTCCLR ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_RTC_CTRL */ +#define BITS_XOSC32K_CTL_STS(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BIT_XOSC32K_CTL_B3_RTCCLR ( BIT(7) ) +#define BIT_XOSC32K_CTL_B2_RTCCLR ( BIT(6) ) +#define BIT_XOSC32K_CTL_B1_RTCCLR ( BIT(5) ) +#define BIT_XOSC32K_CTL_B0_RTCCLR ( BIT(4) ) +#define BIT_XOSC32K_CTL_B3_RTCSET ( BIT(3) ) +#define BIT_XOSC32K_CTL_B2_RTCSET ( BIT(2) ) +#define BIT_XOSC32K_CTL_B1_RTCSET ( BIT(1) ) +#define BIT_XOSC32K_CTL_B0_RTCSET ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_PD_CTRL */ +#define BIT_LDO_LPREF_PD_SW ( BIT(12) ) +#define BIT_DCDC_WPA_PD ( BIT(11) ) +#define BIT_LDO_CLSG_PD ( BIT(10) ) +#define BIT_LDO_USB_PD ( BIT(9) ) +#define BIT_LDO_CAMMOT_PD ( BIT(8) ) +#define BIT_LDO_CAMIO_PD ( BIT(7) ) +#define BIT_LDO_CAMD_PD ( BIT(6) ) +#define BIT_LDO_CAMA_PD ( BIT(5) ) +#define BIT_LDO_SIM2_PD ( BIT(4) ) +#define BIT_LDO_SIM1_PD ( BIT(3) ) +#define BIT_LDO_SIM0_PD ( BIT(2) ) +#define BIT_LDO_SD_PD ( BIT(1) ) +#define BIT_LDO_AVDD18_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL0 */ +#define BITS_LDO_EMMCCORE_V(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_LDO_EMMCIO_V(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_LDO_RF2_V(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_LDO_RF1_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_LDO_RF0_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_LDO_VDD25_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_LDO_VDD28_V(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_LDO_VDD18_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL1 */ +#define BITS_LDO_SIM2_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_LDO_SIM1_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_LDO_SIM0_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_LDO_SD_V(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_LDO_AVDD18_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL2 */ +#define BITS_VBATBK_RES(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_VBATBK_V(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_LDO_CLSG_V(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_LDO_USB_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_LDO_CAMMOT_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_LDO_CAMIO_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_LDO_CAMD_V(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_LDO_CAMA_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL0 */ +#define BITS_LDO_VDD25_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_VDD28_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_VDD18_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL1 */ +#define BITS_LDO_RF2_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_RF1_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_RF0_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL2 */ +#define BITS_LDO_USB_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_EMMCCORE_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_EMMCIO_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL3 */ +#define BITS_LDO_SD_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_AVDD18_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL4 */ +#define BITS_LDO_CAMA_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_SIM2_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_SIM_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL5 */ +#define BITS_LDO_CAMMOT_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_CAMIO_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_CAMD_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL6 */ +#define BITS_LDOA_CAL_SEL(_x_) ( (_x_) << 11 & (BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_LDOD_CAL_SEL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_LDODCDC_CAL_SEL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_LDO_CLSG_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_AUXAD_CTL */ +#define BIT_AUXAD_CURRENTSEN_EN ( BIT(6) ) +#define BIT_AUXAD_CURRENTSEL ( BIT(5) ) +#define BITS_AUXAD_CURRENT_IBS(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL0 */ +#define BIT_DCDC_CORE_LP_EN ( BIT(15) ) +#define BIT_DCDC_CORE_CL_CTRL ( BIT(14) ) +#define BITS_DCDC_CORE_PDRSLOW(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_DCDC_CORE_PFM ( BIT(9) ) +#define BIT_DCDC_CORE_DCM ( BIT(8) ) +#define BIT_DCDC_ARM_LP_EN ( BIT(7) ) +#define BIT_DCDC_ARM_CL_CTRL ( BIT(6) ) +#define BITS_DCDC_ARM_PDRSLOW(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) +#define BIT_DCDC_ARM_PFM ( BIT(1) ) +#define BIT_DCDC_ARM_DCM ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL1 */ +#define BIT_DCDC_MEM_LP_EN ( BIT(15) ) +#define BIT_DCDC_MEM_CL_CTRL ( BIT(14) ) +#define BITS_DCDC_MEM_PDRSLOW(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_DCDC_MEM_PFM ( BIT(9) ) +#define BIT_DCDC_MEM_DCM ( BIT(8) ) +#define BIT_DCDC_GEN_LP_EN ( BIT(7) ) +#define BIT_DCDC_GEN_CL_CTRL ( BIT(6) ) +#define BITS_DCDC_GEN_PDRSLOW(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) +#define BIT_DCDC_GEN_PFM ( BIT(1) ) +#define BIT_DCDC_GEN_DCM ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL2 */ +#define BIT_DCDC_BG_LP_EN ( BIT(15) ) +#define BIT_DCDC_OTP_CHIP_PD_FLAG_CLR ( BIT(14) ) +#define BIT_DCDC_OTP_CHIP_PD_FLAG ( BIT(13) ) +#define BIT_DCDC_OTP_AUTO_PD_EN ( BIT(12) ) +#define BIT_DCDC_OTP_VBEOP ( BIT(11) ) +#define BITS_DCDC_OTP_S(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BIT_DCDC_WRF_LP_EN ( BIT(7) ) +#define BIT_DCDC_WRF_CL_CTRL ( BIT(6) ) +#define BITS_DCDC_WRF_PDRSLOW(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) +#define BIT_DCDC_WRF_PFM ( BIT(1) ) +#define BIT_DCDC_WRF_DCM ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL3 */ +#define BIT_DCDC_WPA_LP_EN ( BIT(8) ) +#define BIT_DCDC_WPA_CL_CTRL ( BIT(7) ) +#define BIT_DCDC_WPA_ZXOP ( BIT(6) ) +#define BITS_DCDC_WPA_PDRSLOW(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) +#define BIT_DCDC_WPA_PFM ( BIT(1) ) +#define BIT_DCDC_WPA_APTEN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL4 */ +#define BIT_DCDC_CORE_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_CORE_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_CORE_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_CORE_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_ARM_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_ARM_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_ARM_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_ARM_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL5 */ +#define BIT_DCDC_MEM_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_MEM_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_MEM_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_MEM_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_GEN_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_GEN_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_GEN_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_GEN_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL6 */ +#define BIT_DCDC_WPA_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_WPA_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_WPA_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_WPA_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_WRF_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_WRF_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_WRF_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_WRF_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DDR2_CTRL */ +#define BIT_DDR2_BUF_PD_HW ( BIT(9) ) +#define BITS_DDR2_BUF_S_DS(_x_) ( (_x_) << 7 & (BIT(7)|BIT(8)) ) +#define BITS_DDR2_BUF_CHNS_DS(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)) ) +#define BIT_DDR2_BUF_PD ( BIT(4) ) +#define BITS_DDR2_BUF_S(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DDR2_BUF_CHNS(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_SLP_WAIT_DCDCARM */ +#define BITS_SLP_IN_WAIT_DCDCARM(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_SLP_OUT_WAIT_DCDCARM(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO1828_XTL_CTL */ +#define BIT_LDO_VDD18_EXT_XTL2_EN ( BIT(11) ) +#define BIT_LDO_VDD18_EXT_XTL1_EN ( BIT(10) ) +#define BIT_LDO_VDD18_EXT_XTL0_EN ( BIT(9) ) +#define BIT_LDO_VDD18_XTL2_EN ( BIT(8) ) +#define BIT_LDO_VDD18_XTL1_EN ( BIT(7) ) +#define BIT_LDO_VDD18_XTL0_EN ( BIT(6) ) +#define BIT_LDO_VDD28_EXT_XTL2_EN ( BIT(5) ) +#define BIT_LDO_VDD28_EXT_XTL1_EN ( BIT(4) ) +#define BIT_LDO_VDD28_EXT_XTL0_EN ( BIT(3) ) +#define BIT_LDO_VDD28_XTL2_EN ( BIT(2) ) +#define BIT_LDO_VDD28_XTL1_EN ( BIT(1) ) +#define BIT_LDO_VDD28_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SLP_CTRL0 */ +#define BIT_SLP_IO_EN ( BIT(15) ) +#define BIT_SLP_DCDC_OTP_PD_EN ( BIT(13) ) +#define BIT_SLP_DCDCGEN_PD_EN ( BIT(12) ) +#define BIT_SLP_DCDCWPA_PD_EN ( BIT(11) ) +#define BIT_SLP_DCDCWRF_PD_EN ( BIT(10) ) +#define BIT_SLP_DCDCARM_PD_EN ( BIT(9) ) +#define BIT_SLP_LDOEMMCCORE_PD_EN ( BIT(7) ) +#define BIT_SLP_LDOEMMCIO_PD_EN ( BIT(6) ) +#define BIT_SLP_LDORF2_PD_EN ( BIT(5) ) +#define BIT_SLP_LDORF1_PD_EN ( BIT(4) ) +#define BIT_SLP_LDORF0_PD_EN ( BIT(3) ) +#define BIT_SLP_LDOVDD25_PD_EN ( BIT(2) ) +#define BIT_SLP_LDOVDD28_PD_EN ( BIT(1) ) +#define BIT_SLP_LDOVDD18_PD_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SLP_CTRL1 */ +#define BIT_SLP_LDO_PD_EN ( BIT(12) ) +#define BIT_SLP_LDOLPREF_PD_EN ( BIT(11) ) +#define BIT_SLP_LDOCLSG_PD_EN ( BIT(10) ) +#define BIT_SLP_LDOUSB_PD_EN ( BIT(9) ) +#define BIT_SLP_LDOCAMMOT_PD_EN ( BIT(8) ) +#define BIT_SLP_LDOCAMIO_PD_EN ( BIT(7) ) +#define BIT_SLP_LDOCAMD_PD_EN ( BIT(6) ) +#define BIT_SLP_LDOCAMA_PD_EN ( BIT(5) ) +#define BIT_SLP_LDOSIM2_PD_EN ( BIT(4) ) +#define BIT_SLP_LDOSIM1_PD_EN ( BIT(3) ) +#define BIT_SLP_LDOSIM0_PD_EN ( BIT(2) ) +#define BIT_SLP_LDOSD_PD_EN ( BIT(1) ) +#define BIT_SLP_LDOAVDD18_PD_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SLP_CTRL2 */ +#define BIT_SLP_DCDC_BG_LP_EN ( BIT(15) ) +#define BIT_SLP_DCDCCORE_LP_EN ( BIT(11) ) +#define BIT_SLP_DCDCMEM_LP_EN ( BIT(10) ) +#define BIT_SLP_DCDCARM_LP_EN ( BIT(9) ) +#define BIT_SLP_DCDCGEN_LP_EN ( BIT(8) ) +#define BIT_SLP_DCDCWPA_LP_EN ( BIT(6) ) +#define BIT_SLP_DCDCWRF_LP_EN ( BIT(5) ) +#define BIT_SLP_LDOEMMCCORE_LP_EN ( BIT(4) ) +#define BIT_SLP_LDOEMMCIO_LP_EN ( BIT(3) ) +#define BIT_SLP_LDORF2_LP_EN ( BIT(2) ) +#define BIT_SLP_LDORF1_LP_EN ( BIT(1) ) +#define BIT_SLP_LDORF0_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SLP_CTRL3 */ +#define BIT_SLP_BG_LP_EN ( BIT(15) ) +#define BIT_SLP_LDOVDD25_LP_EN ( BIT(13) ) +#define BIT_SLP_LDOVDD28_LP_EN ( BIT(12) ) +#define BIT_SLP_LDOVDD18_LP_EN ( BIT(11) ) +#define BIT_SLP_LDOCLSG_LP_EN ( BIT(10) ) +#define BIT_SLP_LDOUSB_LP_EN ( BIT(9) ) +#define BIT_SLP_LDOCAMMOT_LP_EN ( BIT(8) ) +#define BIT_SLP_LDOCAMIO_LP_EN ( BIT(7) ) +#define BIT_SLP_LDOCAMD_LP_EN ( BIT(6) ) +#define BIT_SLP_LDOCAMA_LP_EN ( BIT(5) ) +#define BIT_SLP_LDOSIM2_LP_EN ( BIT(4) ) +#define BIT_SLP_LDOSIM1_LP_EN ( BIT(3) ) +#define BIT_SLP_LDOSIM0_LP_EN ( BIT(2) ) +#define BIT_SLP_LDOSD_LP_EN ( BIT(1) ) +#define BIT_SLP_LDOAVDD18_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_AUD_SLP_CTRL4 */ +#define BIT_SLP_AUD_PA_SW_PD_EN ( BIT(15) ) +#define BIT_SLP_AUD_PA_LDO_PD_EN ( BIT(14) ) +#define BIT_SLP_AUD_PA_PD_EN ( BIT(13) ) +#define BIT_SLP_AUD_OVP_PD_PD_EN ( BIT(9) ) +#define BIT_SLP_AUD_OVP_LDO_PD_EN ( BIT(8) ) +#define BIT_SLP_AUD_VB_PD_EN ( BIT(7) ) +#define BIT_SLP_AUD_VBO_PD_EN ( BIT(6) ) +#define BIT_SLP_AUD_HEADMICBIAS_PD_EN ( BIT(5) ) +#define BIT_SLP_AUD_MICBIAS_HV_PD_EN ( BIT(2) ) +#define BIT_SLP_AUD_HEADMIC_PD_EN ( BIT(1) ) +#define BIT_SLP_AUD_PMUR1_PD_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL */ +#define BITS_SLP_DCDCCORE_VOL_DROP_CNT(_x_)( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DCDC_CORE_CTL_DS(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register ANA_REG_GLB_XTL_WAIT_CTRL */ +#define BIT_SLP_XTLBUF_PD_EN ( BIT(9) ) +#define BIT_XTL_EN ( BIT(8) ) +#define BITS_XTL_WAIT(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_FLASH_CTRL */ +#define BIT_FLASH_PON ( BIT(15) ) +#define BIT_FLASH_V_HW_EN ( BIT(6) ) +#define BITS_FLASH_V_HW_STEP(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_FLASH_V_SW(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register ANA_REG_GLB_WHTLED_CTRL0 */ +#define BIT_WHTLED_PD_STS ( BIT(15) ) +#define BITS_WHTLED_DC(_x_) ( (_x_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BIT_WHTLED_BOOST_EN ( BIT(8) ) +#define BIT_WHTLED_SERIES_EN ( BIT(7) ) +#define BITS_WHTLED_V(_x_) ( (_x_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_WHTLED_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_WHTLED_CTRL1 */ +#define BIT_LCM_CABC_PWM_SEL ( BIT(15) ) +#define BIT_RTC_PWM0_EN ( BIT(14) ) +#define BIT_PWM0_EN ( BIT(13) ) +#define BITS_WHTLED_ISET(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_WHTLED_FRE_AD(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)) ) +#define BITS_WHTLED_CLMIT_OP(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_WHTLED_CTRL2 */ +#define BIT_WHTLED_DIMMING_SEL ( BIT(15) ) +#define BIT_WHTLED_PD_SEL ( BIT(14) ) +#define BIT_WHTLED_DIS_OVST ( BIT(13) ) +#define BIT_WHTLED_DIM_SEL ( BIT(12) ) +#define BIT_WHTLED_DE_BIAS ( BIT(11) ) +#define BIT_WHTLED_BUFF_SHT ( BIT(10) ) +#define BITS_WHTLED_STB_OP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_WHTLED_CAP_OPTION ( BIT(7) ) +#define BIT_WHTLED_OVP_DIS ( BIT(6) ) +#define BITS_WHTLED_REF_DC(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register ANA_REG_GLB_ANA_DRV_CTRL */ +#define BIT_SLP_RGB_PD_EN ( BIT(14) ) +#define BIT_RGB_PD_HW_EN ( BIT(13) ) +#define BITS_RGB_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BITS_KPLED_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_RGB_PD_SW ( BIT(2) ) +#define BIT_KPLED_PD ( BIT(1) ) +#define BIT_KPLED_PD_STS ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_VIBR_CTRL0 */ +#define BITS_VIBR_STABLE_V_HW(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_VIBR_INIT_V_HW(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_VIBR_V_SW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_VIBR_PON ( BIT(2) ) +#define BIT_VIBR_SW_EN ( BIT(1) ) + +/* bits definitions for register ANA_REG_GLB_VIBR_CTRL1 */ +#define BITS_VIBR_V_CONVERT_CNT_HW(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_VIBR_CTRL2 */ +#define BIT_VIBR_PWR_ON_STS ( BIT(15) ) +#define BIT_VIBR_HW_FLOW_ERR1 ( BIT(14) ) +#define BIT_VIBR_HW_FLOW_ERR1_CLR ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_VIBR_WR_PROT_VALUE */ +#define BIT_VIBR_WR_PROT ( BIT(15) ) +#define BITS_VIBR_WR_PROT_VALUE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_AUDIO_CTRL */ +#define BIT_AUD_SLP_APP_RST_EN ( BIT(10) ) +#define BITS_CLK_AUD_HBD_DIV(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BIT_CLK_AUD_LOOP_INV_EN ( BIT(4) ) +#define BIT_CLK_AUDIF_TX_INV_EN ( BIT(3) ) +#define BIT_CLK_AUDIF_RX_INV_EN ( BIT(2) ) +#define BIT_CLK_AUD_6P5M_TX_INV_EN ( BIT(1) ) +#define BIT_CLK_AUD_6P5M_RX_INV_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL0 */ +#define BIT_CHGR_PD_STS ( BIT(15) ) +#define BITS_CHGR_CV_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CHGR_END_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CHG_PUMP_V(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BIT_CHGR_PD_RTCCLR ( BIT(1) ) +#define BIT_CHGR_PD_RTCSET ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL1 */ +#define BIT_DP_DM_SW_EN ( BIT(15) ) +#define BITS_CHGR_CC_I(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_VBAT_OVP_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_VCHG_OVP_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL2 */ +#define BITS_CHG_PUMP_CAL(_x_) ( (_x_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_CHG_PUMP_PD ( BIT(8) ) +#define BIT_CHGR_CC_EN ( BIT(1) ) +#define BIT_RECHG ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_STATUS */ +#define BIT_CHG_DET_DONE ( BIT(11) ) +#define BIT_DP_LOW ( BIT(10) ) +#define BIT_DCP_DET ( BIT(9) ) +#define BIT_CHG_DET ( BIT(8) ) +#define BIT_SDP_INT ( BIT(7) ) +#define BIT_DCP_INT ( BIT(6) ) +#define BIT_CDP_INT ( BIT(5) ) +#define BIT_CHGR_CV_STATUS ( BIT(4) ) +#define BIT_CHGR_ON ( BIT(3) ) +#define BIT_CHGR_INT ( BIT(2) ) +#define BIT_VBAT_OVI ( BIT(1) ) +#define BIT_VCHG_OVI ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_ANA_MIXED_CTRL */ +#define BIT_PTEST_PD_RTCSET ( BIT(15) ) +#define BIT_THM_CHIP_PD_FLAG ( BIT(8) ) +#define BIT_THM_CHIP_PD_FLAG_CLR ( BIT(7) ) +#define BITS_THM_CAL_SEL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)) ) +#define BIT_THM_AUTO_PD_EN ( BIT(4) ) +#define BIT_BG_LP_EN ( BIT(3) ) +#define BITS_UVHO_T(_x_) ( (_x_) << 1 & (BIT(1)|BIT(2)) ) +#define BIT_UVHO_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN0 */ +#define BIT_LDO_XTL_EN ( BIT(15) ) +#define BIT_LDO_RF1_EXT_XTL2_EN ( BIT(11) ) +#define BIT_LDO_RF1_EXT_XTL1_EN ( BIT(10) ) +#define BIT_LDO_RF1_EXT_XTL0_EN ( BIT(9) ) +#define BIT_LDO_RF1_XTL2_EN ( BIT(8) ) +#define BIT_LDO_RF1_XTL1_EN ( BIT(7) ) +#define BIT_LDO_RF1_XTL0_EN ( BIT(6) ) +#define BIT_LDO_RF0_EXT_XTL2_EN ( BIT(5) ) +#define BIT_LDO_RF0_EXT_XTL1_EN ( BIT(4) ) +#define BIT_LDO_RF0_EXT_XTL0_EN ( BIT(3) ) +#define BIT_LDO_RF0_XTL2_EN ( BIT(2) ) +#define BIT_LDO_RF0_XTL1_EN ( BIT(1) ) +#define BIT_LDO_RF0_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN1 */ +#define BIT_LDO_VDD25_EXT_XTL2_EN ( BIT(11) ) +#define BIT_LDO_VDD25_EXT_XTL1_EN ( BIT(10) ) +#define BIT_LDO_VDD25_EXT_XTL0_EN ( BIT(9) ) +#define BIT_LDO_VDD25_XTL2_EN ( BIT(8) ) +#define BIT_LDO_VDD25_XTL1_EN ( BIT(7) ) +#define BIT_LDO_VDD25_XTL0_EN ( BIT(6) ) +#define BIT_LDO_RF2_EXT_XTL2_EN ( BIT(5) ) +#define BIT_LDO_RF2_EXT_XTL1_EN ( BIT(4) ) +#define BIT_LDO_RF2_EXT_XTL0_EN ( BIT(3) ) +#define BIT_LDO_RF2_XTL2_EN ( BIT(2) ) +#define BIT_LDO_RF2_XTL1_EN ( BIT(1) ) +#define BIT_LDO_RF2_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN2 */ +#define BIT_LDO_AVDD18_EXT_XTL2_EN ( BIT(11) ) +#define BIT_LDO_AVDD18_EXT_XTL1_EN ( BIT(10) ) +#define BIT_LDO_AVDD18_EXT_XTL0_EN ( BIT(9) ) +#define BIT_LDO_AVDD18_XTL2_EN ( BIT(8) ) +#define BIT_LDO_AVDD18_XTL1_EN ( BIT(7) ) +#define BIT_LDO_AVDD18_XTL0_EN ( BIT(6) ) +#define BIT_LDO_SIM2_EXT_XTL2_EN ( BIT(5) ) +#define BIT_LDO_SIM2_EXT_XTL1_EN ( BIT(4) ) +#define BIT_LDO_SIM2_EXT_XTL0_EN ( BIT(3) ) +#define BIT_LDO_SIM2_XTL2_EN ( BIT(2) ) +#define BIT_LDO_SIM2_XTL1_EN ( BIT(1) ) +#define BIT_LDO_SIM2_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN3 */ +#define BIT_DCDC_BG_EXT_XTL2_EN ( BIT(11) ) +#define BIT_DCDC_BG_EXT_XTL1_EN ( BIT(10) ) +#define BIT_DCDC_BG_EXT_XTL0_EN ( BIT(9) ) +#define BIT_DCDC_BG_XTL2_EN ( BIT(8) ) +#define BIT_DCDC_BG_XTL1_EN ( BIT(7) ) +#define BIT_DCDC_BG_XTL0_EN ( BIT(6) ) +#define BIT_BG_EXT_XTL2_EN ( BIT(5) ) +#define BIT_BG_EXT_XTL1_EN ( BIT(4) ) +#define BIT_BG_EXT_XTL0_EN ( BIT(3) ) +#define BIT_BG_XTL2_EN ( BIT(2) ) +#define BIT_BG_XTL1_EN ( BIT(1) ) +#define BIT_BG_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN4 */ +#define BIT_DCDC_WRF_XTL2_EN ( BIT(14) ) +#define BIT_DCDC_WRF_XTL1_EN ( BIT(13) ) +#define BIT_DCDC_WRF_XTL0_EN ( BIT(12) ) +#define BIT_DCDC_WPA_XTL2_EN ( BIT(11) ) +#define BIT_DCDC_WPA_XTL1_EN ( BIT(10) ) +#define BIT_DCDC_WPA_XTL0_EN ( BIT(9) ) +#define BIT_DCDC_MEM_XTL2_EN ( BIT(8) ) +#define BIT_DCDC_MEM_XTL1_EN ( BIT(7) ) +#define BIT_DCDC_MEM_XTL0_EN ( BIT(6) ) +#define BIT_DCDC_GEN_XTL2_EN ( BIT(5) ) +#define BIT_DCDC_GEN_XTL1_EN ( BIT(4) ) +#define BIT_DCDC_GEN_XTL0_EN ( BIT(3) ) +#define BIT_DCDC_CORE_XTL2_EN ( BIT(2) ) +#define BIT_DCDC_CORE_XTL1_EN ( BIT(1) ) +#define BIT_DCDC_CORE_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN5 */ +#define BIT_DCDC_WRF_EXT_XTL2_EN ( BIT(14) ) +#define BIT_DCDC_WRF_EXT_XTL1_EN ( BIT(13) ) +#define BIT_DCDC_WRF_EXT_XTL0_EN ( BIT(12) ) +#define BIT_DCDC_WPA_EXT_XTL2_EN ( BIT(11) ) +#define BIT_DCDC_WPA_EXT_XTL1_EN ( BIT(10) ) +#define BIT_DCDC_WPA_EXT_XTL0_EN ( BIT(9) ) +#define BIT_DCDC_MEM_EXT_XTL2_EN ( BIT(8) ) +#define BIT_DCDC_MEM_EXT_XTL1_EN ( BIT(7) ) +#define BIT_DCDC_MEM_EXT_XTL0_EN ( BIT(6) ) +#define BIT_DCDC_GEN_EXT_XTL2_EN ( BIT(5) ) +#define BIT_DCDC_GEN_EXT_XTL1_EN ( BIT(4) ) +#define BIT_DCDC_GEN_EXT_XTL0_EN ( BIT(3) ) +#define BIT_DCDC_CORE_EXT_XTL2_EN ( BIT(2) ) +#define BIT_DCDC_CORE_EXT_XTL1_EN ( BIT(1) ) +#define BIT_DCDC_CORE_EXT_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_ANA_STATUS */ +#define BIT_BONDOPT5 ( BIT(5) ) +#define BIT_BONDOPT4 ( BIT(4) ) +#define BIT_BONDOPT3 ( BIT(3) ) +#define BIT_BONDOPT2 ( BIT(2) ) +#define BIT_BONDOPT1 ( BIT(1) ) +#define BIT_BONDOPT0 ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_POR_RST_MONITOR */ +#define BITS_POR_RST_MONITOR(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_WDG_RST_MONITOR */ +#define BITS_WDG_RST_MONITOR(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_POR_PIN_RST_MONITOR */ +#define BITS_POR_PIN_RST_MONITOR(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_POR_SRC_FLAG */ +#define BIT_POR_SW_FORCE_ON ( BIT(15) ) +#define BITS_POR_SRC_FLAG(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_POR_7S_CTRL */ +#define BIT_PBINT_7S_FLAG_CLR ( BIT(15) ) +#define BIT_EXT_RSTN_FLAG_CLR ( BIT(14) ) +#define BIT_CHGR_INT_FLAG_CLR ( BIT(13) ) +#define BIT_PBINT2_FLAG_CLR ( BIT(12) ) +#define BIT_PBINT_FLAG_CLR ( BIT(11) ) +#define BIT_PBINT_7S_RST_SWMODE_RTCSTS ( BIT(10) ) +#define BIT_PBINT_7S_RST_SWMODE_RTCCLR ( BIT(9) ) +#define BIT_PBINT_7S_RST_SWMODE_RTCSET ( BIT(8) ) +#define BITS_PBINT_7S_RST_THRESHOLD(_x_)( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_PBINT_7S_RST_DISABLE ( BIT(3) ) +#define BIT_PBINT_7S_RST_MODE_RTCSTS ( BIT(2) ) +#define BIT_PBINT_7S_RST_MODE_RTCCLR ( BIT(1) ) +#define BIT_PBINT_7S_RST_MODE_RTCSET ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_INT_DEBUG */ +#define BIT_OTP_INT_DEB ( BIT(10) ) +#define BIT_THM_INT_DEB ( BIT(9) ) +#define BIT_AUD_PROT_INT_DEB ( BIT(8) ) +#define BIT_AUD_HEADBTN_INT_DEB ( BIT(7) ) +#define BIT_EIC_INT_DEB ( BIT(6) ) +#define BIT_FGU_INT_DEB ( BIT(5) ) +#define BIT_WDG_INT_DEB ( BIT(4) ) +#define BIT_RTC_INT_DEB ( BIT(3) ) +#define BIT_GPIO_INT_DEB ( BIT(2) ) +#define BIT_ADC_INT_DEB ( BIT(1) ) +#define BIT_INT_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_GPI_DEBUG */ +#define BIT_HEAD_INSERT2_DEB ( BIT(9) ) +#define BIT_HEAD_INSERT_DEB ( BIT(8) ) +#define BIT_HEAD_BUTTON_DEB ( BIT(7) ) +#define BIT_PBINT2_DEB ( BIT(6) ) +#define BIT_PBINT_DEB ( BIT(5) ) +#define BIT_VCHG_OVI_DEB ( BIT(4) ) +#define BIT_VBAT_OVI_DEB ( BIT(3) ) +#define BIT_CHGR_INT_DEB ( BIT(2) ) +#define BIT_GPI_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_HWRST_RTC */ +#define BITS_HWRST_RTC_REG_STS(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_HWRST_RTC_REG_SET(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_CHIP_ID_LOW */ +#define BITS_CHIP_ID_LOW(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_CHIP_ID_HIGH */ +#define BITS_CHIP_ID_HIGH(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_ARM_MF_REG */ +#define BITS_ARM_MF_REG(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_AFUSE_CTRL */ +#define BIT_AFUSE_READ_REQ ( BIT(7) ) +#define BITS_AFUSE_READ_DLY(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) + +/* bits definitions for register ANA_REG_GLB_AFUSE_OUT0 */ +#define BITS_AFUSE_OUT0(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_AFUSE_OUT1 */ +#define BITS_AFUSE_OUT1(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_AFUSE_OUT2 */ +#define BITS_AFUSE_OUT2(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_AFUSE_OUT3 */ +#define BITS_AFUSE_OUT3(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_ARCH_EN */ +#define BIT_ARCH_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_MCU_WR_PROT_VALUE */ +#define BIT_MCU_WR_PROT ( BIT(15) ) +#define BITS_MCU_WR_PROT_VALUE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CORE_ADI */ +#define BITS_DCDC_CORE_CTL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DCDC_CORE_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_ARM_ADI */ +#define BITS_DCDC_ARM_CTL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DCDC_ARM_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_MEM_ADI */ +#define BIT_DCDC_MEM_CTL_ADI ( BIT(5) ) +#define BITS_DCDC_MEM_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_GEN_ADI */ +#define BITS_DCDC_GEN_CTL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DCDC_GEN_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_WRF_ADI */ +#define BITS_DCDC_WRF_CTL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)) ) +#define BITS_DCDC_WRF_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_WPA_ADI */ +#define BITS_DCDC_WPA_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_WPA_DCM_ADI */ +#define BIT_DCDC_WPA_DCM_ADI ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_SEL */ +#define BIT_LDO_CAMIO_CAL_EN ( BIT(5) ) +#define BIT_LDO_CLSG_CAL_EN ( BIT(6) ) +#define BITS_LDO_CAMD_CAL_EN(_x_) ( (_x_) & (BIT(5)|BIT(6)) ) +#define BIT_LDO_EMMCIO_CAL_EN ( BIT(7) ) +#define BITS_LDO_AVDD18_CAL_EN(_x_) ( (_x_) & (BIT(5)|BIT(7)) ) +#define BITS_LDO_VDD18_CAL_EN(_x_) ( (_x_) & (BIT(6)|BIT(7)) ) +#define BIT_LDO_SIM0_CAL_EN ( BIT(9) ) +#define BIT_LDO_SIM1_CAL_EN ( BIT(9) ) +#define BITS_LDO_SIM2_CAL_EN(_x_) ( (_x_) & (BIT(8)|BIT(9)) ) +#define BIT_LDO_EMMCCORE_CAL_EN ( BIT(10) ) +#define BITS_LDO_VDD28_CAL_EN(_x_) ( (_x_) & (BIT(8)|BIT(10)) ) +#define BITS_LDO_VDD25_CAL_EN(_x_) ( (_x_) & (BIT(9)|BIT(10)) ) +#define BITS_LDO_USB_CAL_EN(_x_) ( (_x_) & (BIT(8)|BIT(9)|BIT(10)) ) +#define BIT_LDO_SD_CAL_EN ( BIT(11) ) +#define BIT_LDO_CAMA_CAL_EN ( BIT(12) ) +#define BITS_LDO_RF2_CAL_EN(_x_) ( (_x_) & (BIT(11)|BIT(12)) ) +#define BIT_LDO_RF1_CAL_EN ( BIT(13) ) +#define BITS_LDO_RF0_CAL_EN(_x_) ( (_x_) & (BIT(11)|BIT(13)) ) +#define BITS_LDO_CAMMOT_CAL_EN(_x_) ( (_x_) & (BIT(12)|BIT(13)) ) +#define BITS_LDO_CAL_SEL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +#define SHFT_LDO_CAL_SEL ( 5 ) +#define MASK_LDO_CAL_SEL ( BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13) ) + +/* vars definitions for controller ANA_REGS_GLB */ + +#endif //__ANA_REGS_GLB_H__ diff --git a/include/soc/sprd/chip_x20l/__regs_ana_sc2723_glb.h b/include/soc/sprd/chip_x20l/__regs_ana_sc2723_glb.h new file mode 100755 index 00000000..fe9cd745 --- /dev/null +++ b/include/soc/sprd/chip_x20l/__regs_ana_sc2723_glb.h @@ -0,0 +1,952 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __ANA_REGS_GLB_H__ +#define __ANA_REGS_GLB_H__ + +#define ANA_REGS_GLB + +/* registers definitions for controller ANA_REGS_GLB */ +#define ANA_REG_GLB_ARM_MODULE_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0000) +#define ANA_REG_GLB_ARM_CLK_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0004) +#define ANA_REG_GLB_RTC_CLK_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0008) +#define ANA_REG_GLB_ARM_RST SCI_ADDR(ANA_REGS_GLB_BASE, 0x000C) +#define ANA_REG_GLB_LDO_DCDC_PD SCI_ADDR(ANA_REGS_GLB_BASE, 0x0010) +#define ANA_REG_GLB_LDO_PD_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0014) +#define ANA_REG_GLB_LDO_V_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0018) +#define ANA_REG_GLB_LDO_V_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x001C) +#define ANA_REG_GLB_LDO_V_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0020) +#define ANA_REG_GLB_LDO_V_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0024) +#define ANA_REG_GLB_LDO_V_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0028) +#define ANA_REG_GLB_LDO_V_CTRL5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x002C) +#define ANA_REG_GLB_LDO_V_CTRL6 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0030) +#define ANA_REG_GLB_LDO_V_CTRL7 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0034) +#define ANA_REG_GLB_LDO_V_CTRL8 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0038) +#define ANA_REG_GLB_LDO_V_CTRL9 SCI_ADDR(ANA_REGS_GLB_BASE, 0x003C) +#define ANA_REG_GLB_LDO_V_CTRL10 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0040) +#define ANA_REG_GLB_LDO_V_CTRL11 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0044) +#define ANA_REG_GLB_LDO_LP_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0048) +#define ANA_REG_GLB_DCDC_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x004C) +#define ANA_REG_GLB_DCDC_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0050) +#define ANA_REG_GLB_DCDC_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0054) +#define ANA_REG_GLB_DCDC_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0058) +#define ANA_REG_GLB_DCDC_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x005C) +#define ANA_REG_GLB_DCDC_CTRL5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0060) +#define ANA_REG_GLB_DCDC_CTRL6 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0064) +#define ANA_REG_GLB_DCDC_CTRL7 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0068) +#define ANA_REG_GLB_DCDC_CTRL8 SCI_ADDR(ANA_REGS_GLB_BASE, 0x006C) +#define ANA_REG_GLB_DCDC_CTRL9 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0070) +#define ANA_REG_GLB_DCDC_CTRL10 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0074) +#define ANA_REG_GLB_DCDC_CTRL11 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0078) +#define ANA_REG_GLB_DCDC_CTRL12 SCI_ADDR(ANA_REGS_GLB_BASE, 0x007C) +#define ANA_REG_GLB_DCDC_CTRL13 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0080) +#define ANA_REG_GLB_DCDC_CTRL14 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0084) +#define ANA_REG_GLB_DCDC_CTRL15 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0088) +#define ANA_REG_GLB_SLP_WAIT_DCDCARM SCI_ADDR(ANA_REGS_GLB_BASE, 0x008C) +#define ANA_REG_GLB_PWR_SLP_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0090) +#define ANA_REG_GLB_PWR_SLP_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0094) +#define ANA_REG_GLB_PWR_SLP_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0098) +#define ANA_REG_GLB_PWR_SLP_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x009C) +#define ANA_REG_GLB_PWR_SLP_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A0) +#define ANA_REG_GLB_AUD_SLP_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A4) +#define ANA_REG_GLB_DCDC_SLP_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A8) +#define ANA_REG_GLB_DCDC_SLP_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00AC) +#define ANA_REG_GLB_DCDC_SLP_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B0) +#define ANA_REG_GLB_DCDC_SLP_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B4) +#define ANA_REG_GLB_DCDC_SLP_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B8) +#define ANA_REG_GLB_DCDC_SLP_CTRL5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00BC) +#define ANA_REG_GLB_PWR_SEL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C0) +#define ANA_REG_GLB_PWR_XTL_EN0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C4) +#define ANA_REG_GLB_PWR_XTL_EN1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C8) +#define ANA_REG_GLB_PWR_XTL_EN2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00CC) +#define ANA_REG_GLB_PWR_XTL_EN3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D0) +#define ANA_REG_GLB_32KLESS_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D4) +#define ANA_REG_GLB_32KLESS_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D8) +#define ANA_REG_GLB_32KLESS_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00DC) +#define ANA_REG_GLB_32KLESS_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E0) +#define ANA_REG_GLB_AUXAD_CTL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E4) +#define ANA_REG_GLB_XTL_WAIT_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E8) +#define ANA_REG_GLB_RGB_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00EC) +#define ANA_REG_GLB_WHTLED_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F0) +#define ANA_REG_GLB_WHTLED_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0094) +#define ANA_REG_GLB_WHTLED_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0098) +#define ANA_REG_GLB_KPLED_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F4) +#define ANA_REG_GLB_VIBR_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F8) +#define ANA_REG_GLB_AUDIO_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00FC) +#define ANA_REG_GLB_AUDIO_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0100) +#define ANA_REG_GLB_CHGR_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0104) +#define ANA_REG_GLB_CHGR_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0108) +#define ANA_REG_GLB_CHGR_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x010C) +#define ANA_REG_GLB_CHGR_DET_FGU_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0110) +#define ANA_REG_GLB_CHGR_STATUS SCI_ADDR(ANA_REGS_GLB_BASE, 0x0114) +#define ANA_REG_GLB_MIXED_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0118) +#define ANA_REG_GLB_MIXED_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x011C) +#define ANA_REG_GLB_SWRST_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0120) +#define ANA_REG_GLB_POR_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x0124) +#define ANA_REG_GLB_WDG_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x0128) +#define ANA_REG_GLB_POR_PIN_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x012C) +#define ANA_REG_GLB_POR_SRC_FLAG SCI_ADDR(ANA_REGS_GLB_BASE, 0x0130) +#define ANA_REG_GLB_POR_7S_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0134) +#define ANA_REG_GLB_HWRST_RTC SCI_ADDR(ANA_REGS_GLB_BASE, 0x0138) +#define ANA_REG_GLB_CHIP_ID_LOW SCI_ADDR(ANA_REGS_GLB_BASE, 0x013C) +#define ANA_REG_GLB_CHIP_ID_HIGH SCI_ADDR(ANA_REGS_GLB_BASE, 0x0140) +#define ANA_REG_GLB_ARM_MF_REG SCI_ADDR(ANA_REGS_GLB_BASE, 0x0144) +#define ANA_REG_GLB_ARCH_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0148) +#define ANA_REG_GLB_MCU_WR_PROT_VALUE SCI_ADDR(ANA_REGS_GLB_BASE, 0x014C) +#define ANA_REG_GLB_PWR_WR_PROT_VALUE SCI_ADDR(ANA_REGS_GLB_BASE, 0x0150) +#define ANA_REG_GLB_SMPL_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0154) +#define ANA_REG_GLB_SMPL_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0158) +#define ANA_REG_GLB_RTC_RST0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x015C) +#define ANA_REG_GLB_RTC_RST1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0160) +#define ANA_REG_GLB_RTC_RST2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0164) +#define ANA_REG_GLB_LDO_SHPT_PD1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0188) +#define ANA_REG_GLB_LDO_SHPT_PD2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x018C) +#define ANA_REG_GLB_BATDET_CUR_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0190) +#define ANA_REG_GLB_RTC_CLK_STOP SCI_ADDR(ANA_REGS_GLB_BASE, 0x0194) +#define ANA_REG_GLB_VBAT_DROP_CNT SCI_ADDR(ANA_REGS_GLB_BASE, 0x0198) +#define ANA_REG_GLB_DCDC_DISCHRG SCI_ADDR(ANA_REGS_GLB_BASE, 0x019C) +#define ANA_REG_GLB_DCDC_CORE_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0200) +#define ANA_REG_GLB_DCDC_ARM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0204) +#define ANA_REG_GLB_DCDC_MEM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0208) +#define ANA_REG_GLB_DCDC_GEN_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x020C) +#define ANA_REG_GLB_DCDC_WPA_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0210) +#define ANA_REG_GLB_DCDC_WPA_DCM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0214) +#define ANA_REG_GLB_DCDC_CON_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0218) +#define ANA_REG_GLB_DCDC_RF_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x021C) + +/* bits definitions for register ANA_REG_GLB_ARM_MODULE_EN */ +#define BIT_ANA_IMPD_ADC_EN ( BIT(12) ) +#define BIT_ANA_THM_EN ( BIT(11) ) +#define BIT_ANA_BLTC_EN ( BIT(10) ) +#define BIT_ANA_PINREG_EN ( BIT(9) ) +#define BIT_ANA_FGU_EN ( BIT(8) ) +#define BIT_ANA_EFS_EN ( BIT(7) ) +#define BIT_ANA_ADC_EN ( BIT(6) ) +#define BIT_ANA_HDT_EN ( BIT(5) ) +#define BIT_ANA_AUD_EN ( BIT(4) ) +#define BIT_ANA_EIC_EN ( BIT(3) ) +#define BIT_ANA_WDG_EN ( BIT(2) ) +#define BIT_ANA_RTC_EN ( BIT(1) ) +#define BIT_ANA_CAL_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_ARM_CLK_EN */ +#define BIT_CLK_IMPD_ADC_EN ( BIT(10) ) +#define BIT_CLK_AUXAD_EN ( BIT(9) ) +#define BIT_CLK_AUXADC_EN ( BIT(8) ) +#define BITS_CLK_CAL_SRC_SEL(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BIT_CLK_CAL_EN ( BIT(5) ) +#define BIT_CLK_AUD_HID_EN ( BIT(4) ) +#define BIT_CLK_AUD_HBD_EN ( BIT(3) ) +#define BIT_CLK_AUD_LOOP_EN ( BIT(2) ) +#define BIT_CLK_AUD_6P5M_EN ( BIT(1) ) +#define BIT_CLK_AUDIF_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_RTC_CLK_EN */ +#define BIT_RTC_EFS_EN ( BIT(12) ) +#define BIT_RTC_THMA_AUTO_EN ( BIT(11) ) +#define BIT_RTC_THMA_EN ( BIT(10) ) +#define BIT_RTC_THM_EN ( BIT(9) ) +#define BIT_RTC_BLTC_EN ( BIT(8) ) +#define BIT_RTC_FGU_EN ( BIT(7) ) +#define BIT_RTC_FGUA_EN ( BIT(6) ) +#define BIT_RTC_VIBR_EN ( BIT(5) ) +#define BIT_RTC_AUD_EN ( BIT(4) ) +#define BIT_RTC_EIC_EN ( BIT(3) ) +#define BIT_RTC_WDG_EN ( BIT(2) ) +#define BIT_RTC_RTC_EN ( BIT(1) ) +#define BIT_RTC_ARCH_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_ARM_RST */ +#define BIT_ANA_THMA_SOFT_RST ( BIT(15) ) +#define BIT_ANA_THM_SOFT_RST ( BIT(14) ) +#define BIT_ANA_BLTC_SOFT_RST ( BIT(13) ) +#define BIT_ANA_AUD_32K_SOFT_RST ( BIT(12) ) +#define BIT_ANA_AUDTX_SOFT_RST ( BIT(11) ) +#define BIT_ANA_AUDRX_SOFT_RST ( BIT(10) ) +#define BIT_ANA_AUD_SOFT_RST ( BIT(9) ) +#define BIT_ANA_AUD_HDT_SOFT_RST ( BIT(8) ) +#define BIT_ANA_EFS_SOFT_RST ( BIT(7) ) +#define BIT_ANA_ADC_SOFT_RST ( BIT(6) ) +#define BIT_ANA_PWM0_SOFT_RST ( BIT(5) ) +#define BIT_ANA_FGU_SOFT_RST ( BIT(4) ) +#define BIT_ANA_EIC_SOFT_RST ( BIT(3) ) +#define BIT_ANA_WDG_SOFT_RST ( BIT(2) ) +#define BIT_ANA_RTC_SOFT_RST ( BIT(1) ) +#define BIT_ANA_CAL_SOFT_RST ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_DCDC_PD */ +#define BIT_LDO_EMM_PD ( BIT(15) ) +#define BIT_DCDC_TOPCLK6M_PD ( BIT(14) ) +#define BIT_DCDC_RF_PD ( BIT(13) ) +#define BIT_DCDC_GEN_PD ( BIT(12) ) +#define BIT_DCDC_MEM_PD ( BIT(11) ) +#define BIT_DCDC_ARM_PD ( BIT(10) ) +#define BIT_DCDC_CORE_PD ( BIT(9) ) +#define BIT_LDO_RF0_PD ( BIT(8) ) +#define BIT_LDO_EMMCCORE_PD ( BIT(7) ) +#define BIT_LDO_GEN1_PD ( BIT(6) ) +#define BIT_LDO_DCXO_PD ( BIT(5) ) +#define BIT_LDO_GEN0_PD ( BIT(4) ) +#define BIT_LDO_VDD25_PD ( BIT(3) ) +#define BIT_LDO_VDD28_PD ( BIT(2) ) +#define BIT_LDO_VDD18_PD ( BIT(1) ) +#define BIT_BG_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_PD_CTRL */ +#define BIT_LDO_LPREF_PD_SW ( BIT(15) ) +#define BIT_DCDC_WPA_PD ( BIT(14) ) +#define BIT_DCDC_CON_PD ( BIT(13) ) +#define BIT_LDO_WIFIPA_PD ( BIT(11) ) +#define BIT_LDO_SDCORE_PD ( BIT(10) ) +#define BIT_LDO_USB_PD ( BIT(8) ) +#define BIT_LDO_CAMMOT_PD ( BIT(7) ) +#define BIT_LDO_CAMIO_PD ( BIT(6) ) +#define BIT_LDO_CAMD_PD ( BIT(5) ) +#define BIT_LDO_CAMA_PD ( BIT(4) ) +#define BIT_LDO_SIM2_PD ( BIT(3) ) +#define BIT_LDO_SIM1_PD ( BIT(2) ) +#define BIT_LDO_SIM0_PD ( BIT(1) ) +#define BIT_LDO_SDIO_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL0 */ +#define BITS_LDO_RF0_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_WIFIPA_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL1 */ +#define BITS_LDO_CAMIO_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_CAMD_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL2 */ +#define BITS_LDO_GEN0_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL3 */ +#define BITS_LDO_GEN1_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_VDD28_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL4 */ +#define BITS_LDO_SIM0_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_SDIO_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL5 */ +#define BITS_LDO_SIM2_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_SIM1_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL6 */ +#define BITS_LDO_SDCORE_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_CAMA_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL7 */ +#define BITS_LDO_EMMCCORE_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_CAMMOT_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL8 */ +#define BITS_LDO_DCXO_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_DCXO_LP_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL9 */ +#define BITS_LDO_VDD18_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_USB_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL10 */ +#define BITS_LDO_VDD25_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL11 */ +#define BITS_VBATBK_V(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_LDOB_CAL_SEL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_LDOA_CAL_SEL (_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_LDOD_CAL_SEL(_x_) ( (_x_) << 3 & (BIT(3)|BIT(4)) ) +#define BITS_LDODCDC_CAL_SEL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_LP_CTRL */ +#define BITS_LDOB_LP_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDOA_LP_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDODCDC_LP_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL0 */ +#define BITS_DCDC_CORE_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_CORE_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_CORE_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_CORE_QKRSPS ( BIT(3) ) +#define BIT_DCDC_CORE_PFM ( BIT(2) ) +#define BIT_DCDC_CORE_DCM ( BIT(1) ) +#define BIT_DCDC_CORE_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL1 */ +#define BITS_DCDC_MEM_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_MEM_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_MEM_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_MEM_QKRSPS ( BIT(3) ) +#define BIT_DCDC_MEM_PFM ( BIT(2) ) +#define BIT_DCDC_MEM_DCM ( BIT(1) ) +#define BIT_DCDC_MEM_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL2 */ +#define BITS_DCDC_GEN_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_GEN_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_GEN_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_GEN_QKRSPS ( BIT(3) ) +#define BIT_DCDC_GEN_PFM ( BIT(2) ) +#define BIT_DCDC_GEN_DCM ( BIT(1) ) +#define BIT_DCDC_GEN_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL3 */ +#define BITS_DCDC_ARM_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_ARM_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_ARM_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_ARM_QKRSPS ( BIT(3) ) +#define BIT_DCDC_ARM_PFM ( BIT(2) ) +#define BIT_DCDC_ARM_DCM ( BIT(1) ) +#define BIT_DCDC_ARM_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL4 */ +#define BITS_DCDC_WPA_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_WPA_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_WPA_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_WPA_QKRSPS ( BIT(3) ) +#define BIT_DCDC_WPA_PFM ( BIT(2) ) +#define BIT_DCDC_WPA_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL5 */ +#define BITS_DCDC_RF_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_RF_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_RF_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_RF_QKRSPS ( BIT(3) ) +#define BIT_DCDC_RF_PFM ( BIT(2) ) +#define BIT_DCDC_RF_DCM ( BIT(1) ) +#define BIT_DCDC_RF_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL6 */ +#define BITS_DCDC_CON_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_CON_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_CON_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_CON_QKRSPS ( BIT(3) ) +#define BIT_DCDC_CON_PFM ( BIT(2) ) +#define BIT_DCDC_CON_DCM ( BIT(1) ) +#define BIT_DCDC_CON_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL7 */ +#define BITS_DCDC_MEM_CF(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_DCDC_MEM_PFMAD(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_DCDC_MEM_CL_CTRL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_DCDC_CORE_DUALSEL ( BIT(7) ) +#define BIT_DCDC_CORE_MERGEEN ( BIT(6) ) +#define BITS_DCDC_CORE_CF(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_DCDC_CORE_PFMAD(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DCDC_CORE_CL_CTRL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL8 */ +#define BIT_DCDC_ARM_DUALSEL ( BIT(15) ) +#define BIT_DCDC_ARM_MERGEEN ( BIT(14) ) +#define BITS_DCDC_ARM_CF(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_DCDC_ARM_PFMAD(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_DCDC_ARM_CL_CTRL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_DCDC_GEN_CF(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_DCDC_GEN_PFMAD(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DCDC_GEN_CL_CTRL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL9 */ +#define BIT_DCDC_CON_MERGEEN ( BIT(14) ) +#define BITS_DCDC_CON_CF(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_DCDC_CON_PFMAD(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_DCDC_CON_CL_CTRL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_DCDC_RF_MERGEEN ( BIT(6) ) +#define BITS_DCDC_RF_CF(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_DCDC_RF_PFMAD(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DCDC_RF_CL_CTRL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL10 */ +#define BIT_DCDC_WPA_BPOUT_SOFTW ( BIT(15) ) +#define BITS_DCDC_WPA_VBAT_DIV(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BIT_DCDC_WPA_BPEN ( BIT(11) ) +#define BIT_DCDC_WPA_BPMODE ( BIT(10) ) +#define BIT_DCDC_WPA_DEGEN ( BIT(9) ) +#define BIT_DCDC_WPA_APTEN ( BIT(8) ) +#define BITS_DCDC_WPA_DEBC_SEL(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_DCDC_WPA_CF(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_DCDC_WPA_PFMAD(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DCDC_WPA_CL_CTRL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL11 */ +#define BIT_DCDC_3MCLKCAL_EN ( BIT(13) ) +#define BIT_DCDC_2MCLKCAL_EN ( BIT(12) ) +#define BITS_DCDC_6MFRECAL_SW(_x_) ( (_x_) << 7 & (BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DCDC_4MFRECAL_SW(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_DCDC_CLK_SP_SEL ( BIT(1) ) +#define BIT_DCDC_CLK_SP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL12 */ +#define BIT_DCDC_CORE_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_CORE_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_CORE_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_CORE_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_ARM_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_ARM_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_ARM_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_ARM_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL13 */ +#define BIT_DCDC_MEM_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_MEM_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_MEM_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_MEM_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_GEN_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_GEN_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_GEN_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_GEN_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL14 */ +#define BIT_DCDC_WPA_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_WPA_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_WPA_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_WPA_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_RF_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_RF_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_RF_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_RF_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL15 */ +#define BITS_DCDC_CAL_SEL(_x_) ( (_x_) << 13 & (BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_DCDC_CON_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_CON_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_CON_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_CON_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_SLP_WAIT_DCDCARM */ +#define BITS_SLP_IN_WAIT_DCDCARM(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_SLP_OUT_WAIT_DCDCARM(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL0 */ +#define BIT_SLP_IO_EN ( BIT(15) ) +#define BIT_SLP_DCDCRF_PD_EN ( BIT(13) ) +#define BIT_SLP_DCDCCON_PD_EN ( BIT(12) ) +#define BIT_SLP_DCDCGEN_PD_EN ( BIT(11) ) +#define BIT_SLP_DCDCWPA_PD_EN ( BIT(10) ) +#define BIT_SLP_DCDCARM_PD_EN ( BIT(9) ) +#define BIT_SLP_LDOVDD25_PD_EN ( BIT(8) ) +#define BIT_SLP_LDORF0_PD_EN ( BIT(7) ) +#define BIT_SLP_LDOEMMCCORE_PD_EN ( BIT(6) ) +#define BIT_SLP_LDOGEN0_PD_EN ( BIT(5) ) +#define BIT_SLP_LDODCXO_PD_EN ( BIT(4) ) +#define BIT_SLP_LDOGEN1_PD_EN ( BIT(3) ) +#define BIT_SLP_LDOWIFIPA_PD_EN ( BIT(2) ) +#define BIT_SLP_LDOVDD28_PD_EN ( BIT(1) ) +#define BIT_SLP_LDOVDD18_PD_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL1 */ +#define BIT_SLP_LDO_PD_EN ( BIT(15) ) +#define BIT_SLP_LDOLPREF_PD_EN ( BIT(14) ) +#define BIT_SLP_LDOSDCORE_PD_EN ( BIT(9) ) +#define BIT_SLP_LDOUSB_PD_EN ( BIT(8) ) +#define BIT_SLP_LDOCAMMOT_PD_EN ( BIT(7) ) +#define BIT_SLP_LDOCAMIO_PD_EN ( BIT(6) ) +#define BIT_SLP_LDOCAMD_PD_EN ( BIT(5) ) +#define BIT_SLP_LDOCAMA_PD_EN ( BIT(4) ) +#define BIT_SLP_LDOSIM2_PD_EN ( BIT(3) ) +#define BIT_SLP_LDOSIM1_PD_EN ( BIT(2) ) +#define BIT_SLP_LDOSIM0_PD_EN ( BIT(1) ) +#define BIT_SLP_LDOSDIO_PD_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL2 */ +#define BIT_SLP_DCDCRF_LP_EN ( BIT(14) ) +#define BIT_SLP_DCDCCON_LP_EN ( BIT(13) ) +#define BIT_SLP_DCDCCORE_LP_EN ( BIT(12) ) +#define BIT_SLP_DCDCMEM_LP_EN ( BIT(11) ) +#define BIT_SLP_DCDCARM_LP_EN ( BIT(10) ) +#define BIT_SLP_DCDCGEN_LP_EN ( BIT(9) ) +#define BIT_SLP_DCDCWPA_LP_EN ( BIT(8) ) +#define BIT_SLP_LDORF0_LP_EN ( BIT(7) ) +#define BIT_SLP_LDOEMMCCORE_LP_EN ( BIT(6) ) +#define BIT_SLP_LDOGEN0_LP_EN ( BIT(5) ) +#define BIT_SLP_LDODCXO_LP_EN ( BIT(4) ) +#define BIT_SLP_LDOGEN1_LP_EN ( BIT(3) ) +#define BIT_SLP_LDOWIFIPA_LP_EN ( BIT(2) ) +#define BIT_SLP_LDOVDD28_LP_EN ( BIT(1) ) +#define BIT_SLP_LDOVDD18_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL3 */ +#define BIT_SLP_BG_LP_EN ( BIT(15) ) +#define BIT_LDOVDD25_LP_EN_SW ( BIT(14) ) +#define BIT_LDOSDCORE_LP_EN_SW ( BIT(13) ) +#define BIT_LDOUSB_LP_EN_SW ( BIT(12) ) +#define BIT_SLP_LDOVDD25_LP_EN ( BIT(10) ) +#define BIT_SLP_LDOSDCORE_LP_EN ( BIT(9) ) +#define BIT_SLP_LDOUSB_LP_EN ( BIT(8) ) +#define BIT_SLP_LDOCAMMOT_LP_EN ( BIT(7) ) +#define BIT_SLP_LDOCAMIO_LP_EN ( BIT(6) ) +#define BIT_SLP_LDOCAMD_LP_EN ( BIT(5) ) +#define BIT_SLP_LDOCAMA_LP_EN ( BIT(4) ) +#define BIT_SLP_LDOSIM2_LP_EN ( BIT(3) ) +#define BIT_SLP_LDOSIM1_LP_EN ( BIT(2) ) +#define BIT_SLP_LDOSIM0_LP_EN ( BIT(1) ) +#define BIT_SLP_LDOSDIO_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL4 */ +#define BIT_LDOCAMIO_LP_EN_SW ( BIT(15) ) +#define BIT_LDOCAMMOT_LP_EN_SW ( BIT(14) ) +#define BIT_LDOCAMD_LP_EN_SW ( BIT(13) ) +#define BIT_LDOCAMA_LP_EN_SW ( BIT(12) ) +#define BIT_LDOSIM2_LP_EN_SW ( BIT(11) ) +#define BIT_LDOSIM1_LP_EN_SW ( BIT(10) ) +#define BIT_LDOSIM0_LP_EN_SW ( BIT(9) ) +#define BIT_LDOSDIO_LP_EN_SW ( BIT(8) ) +#define BIT_LDORF0_LP_EN_SW ( BIT(7) ) +#define BIT_LDOEMMCCORE_LP_EN_SW ( BIT(6) ) +#define BIT_LDOGEN0_LP_EN_SW ( BIT(5) ) +#define BIT_LDODCXO_LP_EN_SW ( BIT(4) ) +#define BIT_LDOGEN1_LP_EN_SW ( BIT(3) ) +#define BIT_LDOWIFIPA_LP_EN_SW ( BIT(2) ) +#define BIT_LDOVDD28_LP_EN_SW ( BIT(1) ) +#define BIT_LDOVDD18_LP_EN_SW ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_AUD_SLP_CTRL */ +#define BIT_SLP_AUD_PMUR1_PD_EN ( BIT(14) ) +#define BIT_SLP_AUD_PA_SW_PD_EN ( BIT(13) ) +#define BIT_SLP_AUD_PA_LDO_PD_EN ( BIT(12) ) +#define BIT_SLP_AUD_PA_PD_EN ( BIT(11) ) +#define BIT_SLP_AUD_OVP_PD_PD_EN ( BIT(10) ) +#define BIT_SLP_AUD_OVP_LDO_PD_EN ( BIT(9) ) +#define BIT_SLP_AUD_LDOCG_PD_PD_EN ( BIT(8) ) +#define BIT_SLP_AUD_VB_PD_EN ( BIT(7) ) +#define BIT_SLP_AUD_VBO_PD_EN ( BIT(6) ) +#define BIT_SLP_AUD_HEADMICBIAS_PD_EN ( BIT(5) ) +#define BIT_SLP_AUD_HEADMIC_SLEEP_PD_EN ( BIT(4) ) +#define BIT_SLP_AUD_PLGPD_PD_EN ( BIT(3) ) +#define BIT_SLP_AUD_VB_NLEAK_PD ( BIT(2) ) +#define BITS_SLP_AUD_PMUR0_PD_EN(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL0 */ +#define BITS_SLP_DCDCCORE_VOL_DROP_CNT(_x_)( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_PWR_OFF_SEQ_EN ( BIT(2) ) +#define BIT_DCDC_CORE_SLP_OUT_STEP_EN ( BIT(1) ) +#define BIT_DCDC_CORE_SLP_IN_STEP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL1 */ +#define BITS_DCDC_CORE_CAL_DS_SW(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CTRL_DS_SW(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL2 */ +#define BITS_DCDC_CORE_CTRL_SLP_STEP3(_x_)( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_DCDC_CORE_CTRL_SLP_STEP2(_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CTRL_SLP_STEP1(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL3 */ +#define BITS_DCDC_CORE_CTRL_SLP_STEP5(_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CTRL_SLP_STEP4(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL4 */ +#define BITS_DCDC_CORE_CAL_SLP_STEP3(_x_)( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_DCDC_CORE_CAL_SLP_STEP2(_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CAL_SLP_STEP1(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL5 */ +#define BITS_DCDC_CORE_CAL_SLP_STEP5(_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CAL_SLP_STEP4(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SEL */ +#define BIT_LDO_GEN0_SW_SEL ( BIT(13) ) +#define BIT_LDO_GEN1_SW_SEL ( BIT(12) ) +#define BIT_LDO_RF0_SW_SEL ( BIT(11) ) +#define BIT_LDO_VDD18_SW_SEL ( BIT(10) ) +#define BIT_LDO_VDD28_SW_SEL ( BIT(9) ) +#define BIT_LDO_DCXO_SW_SEL ( BIT(8) ) +#define BIT_LDO_EMMCCORE_SW_SEL ( BIT(7) ) +#define BIT_LDO_VDD25_SW_SEL ( BIT(6) ) +#define BIT_DCDC_RF_SW_SEL ( BIT(5) ) +#define BIT_DCDC_GEN_SW_SEL ( BIT(4) ) +#define BIT_DCDC_MEM_SW_SEL ( BIT(3) ) +#define BIT_DCDC_ARM_SW_SEL ( BIT(2) ) +#define BIT_DCDC_CORE_SLP_SW_SEL ( BIT(1) ) +#define BIT_DCDC_CORE_NOR_SW_SEL ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN0 */ +#define BIT_LDO_XTL_EN ( BIT(15) ) +#define BIT_LDO_GEN0_EXT_XTL0_EN ( BIT(14) ) +#define BIT_LDO_GEN0_XTL1_EN ( BIT(13) ) +#define BIT_LDO_GEN0_XTL0_EN ( BIT(12) ) +#define BIT_LDO_GEN1_EXT_XTL0_EN ( BIT(11) ) +#define BIT_LDO_GEN1_XTL1_EN ( BIT(10) ) +#define BIT_LDO_GEN1_XTL0_EN ( BIT(9) ) +#define BIT_LDO_DCXO_EXT_XTL0_EN ( BIT(8) ) +#define BIT_LDO_DCXO_XTL1_EN ( BIT(7) ) +#define BIT_LDO_DCXO_XTL0_EN ( BIT(6) ) +#define BIT_LDO_VDD18_EXT_XTL0_EN ( BIT(5) ) +#define BIT_LDO_VDD18_XTL1_EN ( BIT(4) ) +#define BIT_LDO_VDD18_XTL0_EN ( BIT(3) ) +#define BIT_LDO_VDD28_EXT_XTL0_EN ( BIT(2) ) +#define BIT_LDO_VDD28_XTL1_EN ( BIT(1) ) +#define BIT_LDO_VDD28_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN1 */ +#define BIT_LDO_RF0_EXT_XTL0_EN ( BIT(14) ) +#define BIT_LDO_RF0_XTL1_EN ( BIT(13) ) +#define BIT_LDO_RF0_XTL0_EN ( BIT(12) ) +#define BIT_LDO_WIFIPA_EXT_XTL0_EN ( BIT(11) ) +#define BIT_LDO_WIFIPA_XTL1_EN ( BIT(10) ) +#define BIT_LDO_WIFIPA_XTL0_EN ( BIT(9) ) +#define BIT_LDO_SIM2_EXT_XTL0_EN ( BIT(8) ) +#define BIT_LDO_SIM2_XTL1_EN ( BIT(7) ) +#define BIT_LDO_SIM2_XTL0_EN ( BIT(6) ) +#define BIT_LDO_SIM1_EXT_XTL0_EN ( BIT(5) ) +#define BIT_LDO_SIM1_XTL1_EN ( BIT(4) ) +#define BIT_LDO_SIM1_XTL0_EN ( BIT(3) ) +#define BIT_LDO_SIM0_EXT_XTL0_EN ( BIT(2) ) +#define BIT_LDO_SIM0_XTL1_EN ( BIT(1) ) +#define BIT_LDO_SIM0_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN2 */ +#define BIT_LDO_VDD25_EXT_XTL0_EN ( BIT(11) ) +#define BIT_LDO_VDD25_XTL1_EN ( BIT(10) ) +#define BIT_LDO_VDD25_XTL0_EN ( BIT(9) ) +#define BIT_DCDC_RF_EXT_XTL0_EN ( BIT(8) ) +#define BIT_DCDC_RF_XTL1_EN ( BIT(7) ) +#define BIT_DCDC_RF_XTL0_EN ( BIT(6) ) +#define BIT_XO_EXT_XTL0_EN ( BIT(5) ) +#define BIT_XO_XTL1_EN ( BIT(4) ) +#define BIT_XO_XTL0_EN ( BIT(3) ) +#define BIT_BG_EXT_XTL0_EN ( BIT(2) ) +#define BIT_BG_XTL1_EN ( BIT(1) ) +#define BIT_BG_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN3 */ +#define BIT_DCDC_CON_EXT_XTL0_EN ( BIT(14) ) +#define BIT_DCDC_CON_XTL1_EN ( BIT(13) ) +#define BIT_DCDC_CON_XTL0_EN ( BIT(12) ) +#define BIT_DCDC_WPA_EXT_XTL0_EN ( BIT(11) ) +#define BIT_DCDC_WPA_XTL1_EN ( BIT(10) ) +#define BIT_DCDC_WPA_XTL0_EN ( BIT(9) ) +#define BIT_DCDC_MEM_EXT_XTL0_EN ( BIT(8) ) +#define BIT_DCDC_MEM_XTL1_EN ( BIT(7) ) +#define BIT_DCDC_MEM_XTL0_EN ( BIT(6) ) +#define BIT_DCDC_GEN_EXT_XTL0_EN ( BIT(5) ) +#define BIT_DCDC_GEN_XTL1_EN ( BIT(4) ) +#define BIT_DCDC_GEN_XTL0_EN ( BIT(3) ) +#define BIT_DCDC_CORE_EXT_XTL0_EN ( BIT(2) ) +#define BIT_DCDC_CORE_XTL1_EN ( BIT(1) ) +#define BIT_DCDC_CORE_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_32KLESS_CTRL0 */ +#define BIT_RC_MODE_WR_ACK_FLAG ( BIT(14) ) +#define BIT_XO_LOW_CUR_FLAG ( BIT(13) ) +#define BIT_XO_LOW_CUR_FRC_RTCSET ( BIT(12) ) +#define BIT_XO_LOW_CUR_FRC_RTCCLR ( BIT(11) ) +#define BIT_RC_MODE_WR_ACK_FLAG_CLR ( BIT(10) ) +#define BIT_XO_LOW_CUR_FLAG_CLR ( BIT(9) ) +#define BIT_XO_LOW_CUR_CNT_CLR ( BIT(8) ) +#define BIT_LDO_DCXO_LP_PD_RTCSET ( BIT(7) ) +#define BIT_LDO_DCXO_LP_PD_RTCCLR ( BIT(6) ) +#define BIT_SLP_XO_LOW_CUR_EN ( BIT(5) ) +#define BIT_XO_LOW_CUR_EN ( BIT(3) ) +#define BIT_EXT_32K_PD ( BIT(2) ) +#define BIT_RC_32K_SEL ( BIT(1) ) +#define BIT_RC_32K_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_32KLESS_CTRL1 */ +#define BITS_RC_MODE(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_32KLESS_CTRL2 */ +#define BITS_XO_LOW_CUR_CNT_LOW(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_32KLESS_CTRL3 */ +#define BITS_XO_LOW_CUR_CNT_HIGH(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_AUXAD_CTL */ +#define BIT_AUXAD_CURRENTSEN_EN ( BIT(6) ) +#define BIT_AUXAD_CURRENTSEL ( BIT(5) ) +#define BITS_AUXAD_CURRENT_IBS(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_XTL_WAIT_CTRL */ +#define BIT_SLP_XTLBUF_PD_EN ( BIT(9) ) +#define BIT_XTL_EN ( BIT(8) ) +#define BITS_XTL_WAIT(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_RGB_CTRL */ +#define BIT_RTC_PWM0_EN ( BIT(15) ) +#define BIT_PWM0_EN ( BIT(14) ) +#define BIT_IB_REX_EN ( BIT(12) ) +#define BIT_IB_TRIM_EM_SEL ( BIT(11) ) +#define BITS_RGB_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) ) +#define BIT_SLP_RGB_PD_EN ( BIT(2) ) +#define BIT_RGB_PD_HW_EN ( BIT(1) ) +#define BIT_RGB_PD_SW ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_WHTLED_CTRL */ +#define BITS_IB_TRIM(_x_) ( (_x_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_WHTLED_SERIES_EN ( BIT(8) ) +#define BIT_WHTLED_PD_SEL ( BIT(7) ) +#define BIT_WHTLED_BOOST_EN ( BIT(8) ) +#define BITS_WHTLED_V(_x_) ( (_x_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_WHTLED_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_KPLED_CTRL */ +#define BITS_KPLED_V(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_KPLED_PD ( BIT(11) ) +#define BIT_KPLED_PULLDOWN_EN ( BIT(10) ) +#define BIT_SLP_LDOKPLED_PD_EN ( BIT(9) ) +#define BIT_LDO_KPLED_PD ( BIT(8) ) +#define BITS_LDO_KPLED_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_VIBR_CTRL0 */ +#define BITS_CUR_DRV_CAL_SEL(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BIT_VIBR_PULLDOWN_EN ( BIT(11) ) +#define BIT_VIBR_PULLUP_EN ( BIT(10) ) +#define BIT_SLP_LDOVIBR_PD_EN ( BIT(9) ) +#define BIT_LDO_VIBR_PD ( BIT(8) ) +#define BITS_LDO_VIBR_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_AUDIO_CTRL0 */ +#define BIT_AUD_SLP_APP_RST_EN ( BIT(15) ) +#define BITS_CLK_AUD_HBD_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_CLK_AUD_LOOP_INV_EN ( BIT(4) ) +#define BIT_CLK_AUDIF_TX_INV_EN ( BIT(3) ) +#define BIT_CLK_AUDIF_RX_INV_EN ( BIT(2) ) +#define BIT_CLK_AUD_6P5M_TX_INV_EN ( BIT(1) ) +#define BIT_CLK_AUD_6P5M_RX_INV_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_AUDIO_CTRL1 */ +#define BIT_IMPD_ADC_SOFT_RST ( BIT(7) ) +#define BIT_HEAD_INSERT_EIC_EN ( BIT(6) ) +#define BIT_AUDIO_CHP_CLK_DIV_EN ( BIT(5) ) +#define BITS_AUDIO_CHP_CLK_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL0 */ +#define BIT_CHGLDO_DIS ( BIT(15) ) +#define BITS_CHGR_CV_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CHGR_END_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BIT_CHGR_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL1 */ +#define BITS_CHGR_CC_I(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_VBAT_OVP_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_VCHG_OVP_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL2 */ +#define BIT_CHGR_INT_EN ( BIT(15) ) +#define BIT_CHGR_DRV ( BIT(7) ) +#define BIT_CHGR_OSC ( BIT(6) ) +#define BITS_CHGR_DPM(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CHGR_ITERM(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BIT_CHGR_CC_EN ( BIT(1) ) +#define BIT_RECHG ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_DET_FGU_CTRL */ +#define BIT_FGUA_SOFT_RST ( BIT(13) ) +#define BIT_LDO_FGU_PD ( BIT(12) ) +#define BIT_SD_CHOP_CAP_EN ( BIT(8) ) +#define BITS_SD_CLK_P(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BIT_SD_DCOFFSET_EN ( BIT(5) ) +#define BIT_SD_CHOP_EN ( BIT(4) ) +#define BIT_DP_DM_AUX_EN ( BIT(1) ) +#define BIT_DP_DM_SW_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_STATUS */ +#define BIT_CHG_DET_DONE ( BIT(11) ) +#define BIT_DP_LOW ( BIT(10) ) +#define BIT_DCP_DET ( BIT(9) ) +#define BIT_CHG_DET ( BIT(8) ) +#define BIT_SDP_INT ( BIT(7) ) +#define BIT_DCP_INT ( BIT(6) ) +#define BIT_CDP_INT ( BIT(5) ) +#define BIT_CHGR_CV_STATUS ( BIT(4) ) +#define BIT_CHGR_ON ( BIT(3) ) +#define BIT_CHGR_INT ( BIT(2) ) +#define BIT_VBAT_OVI ( BIT(1) ) +#define BIT_VCHG_OVI ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_MIXED_CTRL0 */ +#define BIT_PTEST_PD_RTCSET ( BIT(15) ) +#define BIT_DCDC_V_CTRL_MODE ( BIT(14) ) +#define BIT_LDO_RAMP_EN ( BIT(13) ) +#define BIT_BG_LP_EN ( BIT(12) ) +#define BITS_VBAT_CRASH_V(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BIT_OVLO_EN ( BIT(9) ) +#define BITS_OVLO_CAL(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_OVLO_V(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_OVLO_T(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_MIXED_CTRL1 */ +#define BITS_XOSC32K_CTL(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_BATON_T(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BIT_BATDET_LDO_SEL ( BIT(9) ) +#define BIT_THM_CHIP_PD_FLAG ( BIT(8) ) +#define BIT_THM_CHIP_PD_FLAG_CLR ( BIT(7) ) +#define BITS_THM_CAL_SEL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)) ) +#define BIT_THM_AUTO_PD_EN ( BIT(4) ) +#define BIT_ALL_GPI_DEB ( BIT(3) ) +#define BIT_GPI_DEBUG_EN ( BIT(2) ) +#define BIT_ALL_INT_DEB ( BIT(1) ) +#define BIT_INT_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_SWRST_CTRL */ +#define BIT_POR_RTC_PD ( BIT(15) ) +#define BITS_POR_RTC_I(_x_) ( (_x_) << 13 & (BIT(13)|BIT(14)) ) +#define BIT_SW_RST_GEN1_PD_EN ( BIT(12) ) +#define BIT_SW_RST_GEN0_PD_EN ( BIT(11) ) +#define BIT_EXT_RSTN_PD_EN ( BIT(10) ) +#define BIT_PB_7S_RST_PD_EN ( BIT(9) ) +#define BIT_SW_RST_EMMCCORE_PD_EN ( BIT(8) ) +#define BIT_KEY2_7S_RST_EN ( BIT(7) ) +#define BIT_WDG_RST_PD_EN ( BIT(6) ) +#define BITS_SW_RST_PD_THRESHOLD(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register ANA_REG_GLB_POR_RST_MONITOR */ +#define BITS_POR_RST_MONITOR(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_WDG_RST_MONITOR */ +#define BITS_WDG_RST_MONITOR(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_POR_PIN_RST_MONITOR */ +#define BITS_POR_PIN_RST_MONITOR(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_POR_SRC_FLAG */ +#define BIT_POR_SW_FORCE_ON ( BIT(15) ) +#define BITS_POR_SRC_FLAG(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_POR_7S_CTRL */ +#define BIT_PBINT_7S_FLAG_CLR ( BIT(15) ) +#define BIT_EXT_RSTN_FLAG_CLR ( BIT(14) ) +#define BIT_CHGR_INT_FLAG_CLR ( BIT(13) ) +#define BIT_PBINT2_FLAG_CLR ( BIT(12) ) +#define BIT_PBINT_FLAG_CLR ( BIT(11) ) +#define BIT_PBINT_7S_RST_SWMODE ( BIT(8) ) +#define BITS_PBINT_7S_RST_THRESHOLD(_x_)( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_PBINT_7S_AUTO_ON_EN ( BIT(2) ) +#define BIT_PBINT_7S_RST_DISABLE ( BIT(1) ) +#define BIT_PBINT_7S_RST_MODE ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_HWRST_RTC */ +#define BITS_HWRST_RTC_REG_STS(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_HWRST_RTC_REG_SET(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_CHIP_ID_LOW */ +#define BITS_CHIP_ID_LOW(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_CHIP_ID_HIGH */ +#define BITS_CHIP_ID_HIGH(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_ARM_MF_REG */ +#define BITS_ARM_MF_REG(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_ARCH_EN */ +#define BIT_ARCH_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_MCU_WR_PROT_VALUE */ +#define BIT_MCU_WR_PROT ( BIT(15) ) +#define BITS_MCU_WR_PROT_VALUE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_PWR_WR_PROT_VALUE */ +#define BIT_PWR_WR_PROT ( BIT(15) ) +#define BITS_PWR_WR_PROT_VALUE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_SMPL_CTRL0 */ +#define BITS_SMPL_MODE(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_SMPL_CTRL1 */ +#define BIT_SMPL_PWR_ON_FLAG ( BIT(15) ) +#define BIT_SMPL_MODE_WR_ACK_FLAG ( BIT(14) ) +#define BIT_SMPL_PWR_ON_FLAG_CLR ( BIT(13) ) +#define BIT_SMPL_MODE_WR_ACK_FLAG_CLR ( BIT(12) ) +#define BIT_SMPL_PWR_ON_SET ( BIT(11) ) +#define BIT_SMPL_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_RTC_RST0 */ +#define BITS_RTC_CLK_FLAG_SET(_x_) ( (_x_) << 15 & (BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_RTC_RST1 */ +#define BITS_RTC_CLK_FLAG_CLR(_x_) ( (_x_) << 15 & (BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_RTC_RST2 */ +#define BITS_RTC_CLK_FLAG_RTC(_x_) ( (_x_) << 15 & (BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SHPT_PD1 */ +#define BIT_LDO_USB_SHPT_PD ( BIT(12) ) +#define BIT_LDO_DCXO_SHPT_PD ( BIT(11) ) +#define BIT_LDO_WIFIPA_SHPT_PD ( BIT(10) ) +#define BIT_LDO_VDD25_SHPT_PD ( BIT(9) ) +#define BIT_LDO_VDD28_SHPT_PD ( BIT(8) ) +#define BIT_LDO_SDIO_SHPT_PD ( BIT(7) ) +#define BIT_LDO_SDCORE_SHPT_PD ( BIT(6) ) +#define BIT_LDO_EMMCCORE_SHPT_PD ( BIT(5) ) +#define BIT_LDO_SIM2_SHPT_PD ( BIT(4) ) +#define BIT_LDO_SIM1_SHPT_PD ( BIT(3) ) +#define BIT_LDO_SIM0_SHPT_PD ( BIT(2) ) +#define BIT_LDO_CAMMOT_SHPT_PD ( BIT(1) ) +#define BIT_LDO_CAMA_SHPT_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SHPT_PD2 */ +#define BIT_LDO_RF0_SHPT_PD ( BIT(7) ) +#define BIT_LDO_GEN1_SHPT_PD ( BIT(6) ) +#define BIT_LDO_GEN0_SHPT_PD ( BIT(5) ) +#define BIT_LDO_CAMD_SHPT_PD ( BIT(4) ) +#define BIT_LDO_VDD18_SHPT_PD ( BIT(3) ) +#define BIT_LDO_CAMIO_SHPT_PD ( BIT(2) ) +#define BIT_LDO_KPLED_SHPT_PD ( BIT(1) ) +#define BIT_LDO_VIBR_SHPT_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_BATDET_CUR_CTRL */ +#define BIT_BATDET_CUR_EN ( BIT(4) ) +#define BITS_BATDET_CUR_I(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register ANA_REG_GLB_RTC_CLK_STOP */ +#define BIT_RTC_CLK_STOP_FLAG ( BIT(7) ) +#define BITS_RTC_CLK_STOP_THRESHOLD(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) + +/* bits definitions for register ANA_REG_GLB_VBAT_DROP_CNT */ +#define BITS_VBAT_DROP_CNT(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_DISCHRG */ +#define BITS_DCDC_ARM_DISCHRG(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_DCDC_CORE_DISCHRG(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_DCDC_MEM_DISCHRG(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_DCDC_GEN_DISCHRG(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_DCDC_RF_DISCHRG(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_DCDC_CON_DISCHRG(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DCDC_WPA_DISCHRG(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CORE_ADI */ +#define BITS_DCDC_CORE_CTL_SW_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CAL_SW_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_ARM_ADI */ +#define BITS_DCDC_ARM_CTL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_ARM_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_MEM_ADI */ +#define BITS_DCDC_MEM_CTRL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_MEM_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_GEN_ADI */ +#define BITS_DCDC_GEN_CTRL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_GEN_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_WPA_ADI */ +#define BITS_DCDC_WPA_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_WPA_DCM_ADI */ +#define BIT_DCDC_WPA_DCM_ADI ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CON_ADI */ +#define BITS_DCDC_CON_CTRL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CON_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_RF_ADI */ +#define BITS_DCDC_RF_CTRL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_RF_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* vars definitions for controller ANA_REGS_GLB */ + +#endif /* __ANA_REGS_GLB_H__ */ diff --git a/include/soc/sprd/chip_x20l/__regs_aon_apb_rf.h b/include/soc/sprd/chip_x20l/__regs_aon_apb_rf.h new file mode 100755 index 00000000..f6214fd3 --- /dev/null +++ b/include/soc/sprd/chip_x20l/__regs_aon_apb_rf.h @@ -0,0 +1,767 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_AON_APB_HEADFILE_H__ +#define __H_REGS_AON_APB_HEADFILE_H__ __FILE__ + +#define REGS_AON_APB_ + +/* registers definitions for AON_APB_ */ +#define REG_AON_APB_APB_EB0 SCI_ADDR(REGS_AON_APB_BASE, 0x0000) +#define REG_AON_APB_APB_EB1 SCI_ADDR(REGS_AON_APB_BASE, 0x0004) +#define REG_AON_APB_APB_RST0 SCI_ADDR(REGS_AON_APB_BASE, 0x0008) +#define REG_AON_APB_APB_RST1 SCI_ADDR(REGS_AON_APB_BASE, 0x000C) +#define REG_AON_APB_APB_RTC_EB SCI_ADDR(REGS_AON_APB_BASE, 0x0010) +#define REG_AON_APB_REC_26MHZ_BUF_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0014) +#define REG_AON_APB_SINDRV_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0018) +#define REG_AON_APB_ADA_SEL_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x001C) +#define REG_AON_APB_VBC_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0020) +#define REG_AON_APB_PWR_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0024) +#define REG_AON_APB_TS_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0028) +#define REG_AON_APB_BOOT_MODE SCI_ADDR(REGS_AON_APB_BASE, 0x002C) +#define REG_AON_APB_BB_BG_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0030) +#define REG_AON_APB_CP_ARM_JTAG_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0034) +#define REG_AON_APB_PLL_SOFT_CNT_DONE SCI_ADDR(REGS_AON_APB_BASE, 0x0038) +#define REG_AON_APB_DCXO_LC_REG0 SCI_ADDR(REGS_AON_APB_BASE, 0x003C) +#define REG_AON_APB_DCXO_LC_REG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0040) +#define REG_AON_APB_MPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0044) +#define REG_AON_APB_MPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0048) +#define REG_AON_APB_DPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x004C) +#define REG_AON_APB_DPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0050) +#define REG_AON_APB_TWPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0054) +#define REG_AON_APB_TWPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0058) +#define REG_AON_APB_LTEPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x005C) +#define REG_AON_APB_LTEPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0060) +#define REG_AON_APB_LVDSDISPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0064) +#define REG_AON_APB_LVDSDISPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0068) +#define REG_AON_APB_AON_REG_PROT SCI_ADDR(REGS_AON_APB_BASE, 0x006C)/*Big endian protect register*/ +#define REG_AON_APB_LDSP_BOOT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x0070)/*DSP boot enable*/ +#define REG_AON_APB_LDSP_BOOT_VEC SCI_ADDR(REGS_AON_APB_BASE, 0x0074)/*DSP boot vector*/ +#define REG_AON_APB_LDSP_RST SCI_ADDR(REGS_AON_APB_BASE, 0x0078)/*DSP reset*/ +#define REG_AON_APB_LDSP_MTX_CTRL1 SCI_ADDR(REGS_AON_APB_BASE, 0x007C) +#define REG_AON_APB_LDSP_MTX_CTRL2 SCI_ADDR(REGS_AON_APB_BASE, 0x0080) +#define REG_AON_APB_LDSP_MTX_CTRL3 SCI_ADDR(REGS_AON_APB_BASE, 0x0084) +#define REG_AON_APB_AON_CGM_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0088) +#define REG_AON_APB_LACC_MTX_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x008C) +#define REG_AON_APB_CORTEX_MTX_CTRL1 SCI_ADDR(REGS_AON_APB_BASE, 0x0090) +#define REG_AON_APB_CORTEX_MTX_CTRL2 SCI_ADDR(REGS_AON_APB_BASE, 0x0094) +#define REG_AON_APB_CORTEX_MTX_CTRL3 SCI_ADDR(REGS_AON_APB_BASE, 0x0098)/*DSP reset*/ +#define REG_AON_APB_CA5_TCLK_DLY_LEN SCI_ADDR(REGS_AON_APB_BASE, 0x009C)/*APB clock control*/ +#define REG_AON_APB_CCIR_RCVR_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0100)/*APB clock control*/ +#define REG_AON_APB_PLL_BG_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0108) +#define REG_AON_APB_LVDSDIS_SEL SCI_ADDR(REGS_AON_APB_BASE, 0x010C) +#define REG_AON_APB_DJTAG_MUX_SEL SCI_ADDR(REGS_AON_APB_BASE, 0x0110) +#define REG_AON_APB_ARM7_SYS_SOFT_RST SCI_ADDR(REGS_AON_APB_BASE, 0x0114) +#define REG_AON_APB_CP1_CP0_ADDR_MSB SCI_ADDR(REGS_AON_APB_BASE, 0x0118) +#define REG_AON_APB_AON_DMA_INT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x011C) +#define REG_AON_APB_EMC_AUTO_GATE_EN SCI_ADDR(REGS_AON_APB_BASE, 0x0120) +#define REG_AON_APB_ARM7_CFG_BUS SCI_ADDR(REGS_AON_APB_BASE, 0x0124) +#define REG_AON_APB_RTC4M_0_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0128) +#define REG_AON_APB_RTC4M_1_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x012C) +#define REG_AON_APB_APB_RST2 SCI_ADDR(REGS_AON_APB_BASE, 0x0130) +#define REG_AON_APB_TGDSP_BOOT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x0134)/*TGDSP_BOOT_EN*/ +#define REG_AON_APB_TGDSP_BOOT_VEC SCI_ADDR(REGS_AON_APB_BASE, 0x0138)/*TGDSP_BOOT_VEC*/ +#define REG_AON_APB_TGDSP_RST SCI_ADDR(REGS_AON_APB_BASE, 0x013C)/*TGDSP_RST*/ +#define REG_AON_APB_RFFE_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0140)/*RFFE_CFG*/ +#define REG_AON_APB_OSC_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0144)/*osc_ctrl*/ +#define REG_AON_APB_OSC_OBS SCI_ADDR(REGS_AON_APB_BASE, 0x0148)/*CA53_OSC_OBS*/ +#define REG_AON_APB_CA7_SDISABLE SCI_ADDR(REGS_AON_APB_BASE, 0x014C)/*CA7_SDISABLE*/ +#define REG_AON_APB_AP_WPROT_EN1 SCI_ADDR(REGS_AON_APB_BASE, 0x3004) +#define REG_AON_APB_CP0_WPROT_EN1 SCI_ADDR(REGS_AON_APB_BASE, 0x3008) +#define REG_AON_APB_CP1_WPROT_EN1 SCI_ADDR(REGS_AON_APB_BASE, 0x300C) +#define REG_AON_APB_IO_DLY_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x3014) +#define REG_AON_APB_AP_WPROT_EN0 SCI_ADDR(REGS_AON_APB_BASE, 0x3018) +#define REG_AON_APB_CP0_WPROT_EN0 SCI_ADDR(REGS_AON_APB_BASE, 0x3020) +#define REG_AON_APB_CP1_WPROT_EN0 SCI_ADDR(REGS_AON_APB_BASE, 0x3024) +#define REG_AON_APB_PMU_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x302C) +#define REG_AON_APB_THM_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3030) +#define REG_AON_APB_AP_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3034) +#define REG_AON_APB_CA7_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3038) +#define REG_AON_APB_BOND_OPT0 SCI_ADDR(REGS_AON_APB_BASE, 0x303C) +#define REG_AON_APB_BOND_OPT1 SCI_ADDR(REGS_AON_APB_BASE, 0x3040) +#define REG_AON_APB_RES_REG0 SCI_ADDR(REGS_AON_APB_BASE, 0x3044) +#define REG_AON_APB_RES_REG1 SCI_ADDR(REGS_AON_APB_BASE, 0x3048) +#define REG_AON_APB_AON_QOS_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x304C) +#define REG_AON_APB_BB_LDO_CAL_START SCI_ADDR(REGS_AON_APB_BASE, 0x3050) +#define REG_AON_APB_AON_MTX_PROT_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3058) +#define REG_AON_APB_LVDS_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3060) +#define REG_AON_APB_PLL_LOCK_OUT_SEL SCI_ADDR(REGS_AON_APB_BASE, 0x3064) +#define REG_AON_APB_RTC4M_RC_VAL SCI_ADDR(REGS_AON_APB_BASE, 0x3068) +#define REG_AON_APB_CP0_MISC_CTL0 SCI_ADDR(REGS_AON_APB_BASE, 0x306C)/*CP0_MISC_CTL0*/ +#define REG_AON_APB_CP0_MCU_C2C_SEMA SCI_ADDR(REGS_AON_APB_BASE, 0x3070)/*CP0_MCU_C2C_SEMA*/ +#define REG_AON_APB_CP0_MCU_CLK_CTL SCI_ADDR(REGS_AON_APB_BASE, 0x3074)/*CP0_MCU_CLK_CTL*/ +#define REG_AON_APB_PROT_BUS_SECURE_EN SCI_ADDR(REGS_AON_APB_BASE, 0x3080)/*PROT_BUS_SECURE_EN*/ +#define REG_AON_APB_PROT_ARM7_SPACE_EN SCI_ADDR(REGS_AON_APB_BASE, 0x3084)/*PROT_ARM7_SPACE_EN*/ +#define REG_AON_APB_APB_ROM_PD_CTL SCI_ADDR(REGS_AON_APB_BASE, 0x3088)/*APB_ROM_PD_CTL*/ +#define REG_AON_APB_CP0_SLP_STS SCI_ADDR(REGS_AON_APB_BASE, 0x308C)/*CP0_SLP_STS*/ +#define REG_AON_APB_CP0_DSP_JTAG_CTL SCI_ADDR(REGS_AON_APB_BASE, 0x3090)/*CP0_DSP_JTAG_CTL*/ +#define REG_AON_APB_ANA_PD_STS SCI_ADDR(REGS_AON_APB_BASE, 0x3094)/*ANA_PD_STS*/ +#define REG_AON_APB_AON_APB_RSV SCI_ADDR(REGS_AON_APB_BASE, 0x30F0) +#define REG_AON_APB_AON_CHIP_ID SCI_ADDR(REGS_AON_APB_BASE, 0x00FC) +#define REG_AON_APB_AON_CHIP_ID_DIG SCI_ADDR(REGS_AON_APB_BASE, 0x00F8)/*AON_DCHIP_ID_DIG*/ + + + +/* bits definitions for register REG_AON_APB_APB_EB0 */ +#define BIT_I2C_EB ( BIT(31) ) +#define BIT_CA7_DAP_EB ( BIT(30) ) +#define BIT_CA7_TS1_EB ( BIT(29) ) +#define BIT_CA7_TS0_EB ( BIT(28) ) +#define BIT_GPU_EB ( BIT(27) ) +#define BIT_AON_CKG_EB ( BIT(26) ) +#define BIT_MM_EB ( BIT(25) ) +#define BIT_AP_WDG_EB ( BIT(24) ) +#define BIT_MSPI_EB ( BIT(23) ) +#define BIT_SPLK_EB ( BIT(22) ) +#define BIT_IPI_EB ( BIT(21) ) +#define BIT_PIN_EB ( BIT(20) ) +#define BIT_VBC_EB ( BIT(19) ) +#define BIT_AUD_EB ( BIT(18) ) +#define BIT_AUDIF_EB ( BIT(17) ) +#define BIT_ADI_EB ( BIT(16) ) +#define BIT_INTC_EB ( BIT(15) ) +#define BIT_EIC_EB ( BIT(14) ) +#define BIT_EFUSE_EB ( BIT(13) ) +#define BIT_AP_TMR0_EB ( BIT(12) ) +#define BIT_AON_TMR_EB ( BIT(11) ) +#define BIT_AP_SYST_EB ( BIT(10) ) +#define BIT_AON_SYST_EB ( BIT(9) ) +#define BIT_KPD_EB ( BIT(8) ) +#define BIT_PWM3_EB ( BIT(7) ) +#define BIT_PWM2_EB ( BIT(6) ) +#define BIT_PWM1_EB ( BIT(5) ) +#define BIT_PWM0_EB ( BIT(4) ) +#define BIT_GPIO_EB ( BIT(3) ) +#define BIT_AON_GPIO_EB (BIT_GPIO_EB) +#define BIT_TPC_EB ( BIT(2) ) +#define BIT_FM_EB ( BIT(1) ) +#define BIT_ADC_EB ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_APB_EB1 */ +#define BIT_MIPI_DSI_TXCLKHSSRC_DIV_EN ( BIT(28) ) +#define BIT_ORP_JTAG_EB ( BIT(27) ) +#define BIT_CA5_TS0_EB ( BIT(26) ) +#define BIT_DEF_EB ( BIT(25) ) +#define BIT_LVDS_PLL_DIV_EN ( BIT(24) ) +#define BIT_ARM7_JTAG_EB ( BIT(23) ) +#define BIT_AON_DMA_EB ( BIT(22) ) +#define BIT_MBOX_EB ( BIT(21) ) +#define BIT_DJTAG_EB ( BIT(20) ) +#define BIT_RTC4M1_CAL_EB ( BIT(19) ) +#define BIT_RTC4M0_CAL_EB ( BIT(18) ) +#define BIT_MDAR_EB ( BIT(17) ) +#define BIT_LVDS_TCXO_EB ( BIT(16) ) +#define BIT_LVDS_TRX_EB ( BIT(15) ) +#define BIT_CA5_DAP_EB ( BIT(14) ) +#define BIT_GSP_EMC_EB ( BIT(13) ) +#define BIT_ZIP_EMC_EB ( BIT(12) ) +#define BIT_DISP_EMC_EB ( BIT(11) ) +#define BIT_AP_TMR2_EB ( BIT(10) ) +#define BIT_AP_TMR1_EB ( BIT(9) ) +#define BIT_CA7_WDG_EB ( BIT(8) ) +#define BIT_AVS_EB ( BIT(6) ) +#define BIT_PROBE_EB ( BIT(5) ) +#define BIT_AUX2_EB ( BIT(4) ) +#define BIT_AUX1_EB ( BIT(3) ) +#define BIT_AUX0_EB ( BIT(2) ) +#define BIT_THM_EB ( BIT(1) ) +#define BIT_PMU_EB ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_APB_RST0 */ +#define BIT_CA5_TS0_SOFT_RST ( BIT(31) ) +#define BIT_I2C_SOFT_RST ( BIT(30) ) +#define BIT_CA7_TS1_SOFT_RST ( BIT(29) ) +#define BIT_CA7_TS0_SOFT_RST ( BIT(28) ) +#define BIT_DAP_MTX_SOFT_RST ( BIT(27) ) +#define BIT_MSPI1_SOFT_RST ( BIT(26) ) +#define BIT_MSPI0_SOFT_RST ( BIT(25) ) +#define BIT_SPLK_SOFT_RST ( BIT(24) ) +#define BIT_IPI_SOFT_RST ( BIT(23) ) +#define BIT_AON_CKG_SOFT_RST ( BIT(22) ) +#define BIT_PIN_SOFT_RST ( BIT(21) ) +#define BIT_VBC_SOFT_RST ( BIT(20) ) +#define BIT_AUD_SOFT_RST ( BIT(19) ) +#define BIT_AUDIF_SOFT_RST ( BIT(18) ) +#define BIT_ADI_SOFT_RST ( BIT(17) ) +#define BIT_INTC_SOFT_RST ( BIT(16) ) +#define BIT_EIC_SOFT_RST ( BIT(15) ) +#define BIT_EFUSE_SOFT_RST ( BIT(14) ) +#define BIT_AP_WDG_SOFT_RST ( BIT(13) ) +#define BIT_AP_TMR0_SOFT_RST ( BIT(12) ) +#define BIT_AON_TMR_SOFT_RST ( BIT(11) ) +#define BIT_AP_SYST_SOFT_RST ( BIT(10) ) +#define BIT_AON_SYST_SOFT_RST ( BIT(9) ) +#define BIT_KPD_SOFT_RST ( BIT(8) ) +#define BIT_PWM3_SOFT_RST ( BIT(7) ) +#define BIT_PWM2_SOFT_RST ( BIT(6) ) +#define BIT_PWM1_SOFT_RST ( BIT(5) ) +#define BIT_PWM0_SOFT_RST ( BIT(4) ) +#define BIT_GPIO_SOFT_RST ( BIT(3) ) +#define BIT_TPC_SOFT_RST ( BIT(2) ) +#define BIT_FM_SOFT_RST ( BIT(1) ) +#define BIT_ADC_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_APB_RST1 */ +#define BIT_RTC4M_ANA_SOFT_RST ( BIT(31) ) +#define BIT_DEF_SLV_INT_SOFT_CLR ( BIT(30) ) +#define BIT_DEF_SOFT_RST ( BIT(29) ) +#define BIT_ADC3_SOFT_RST ( BIT(28) ) +#define BIT_ADC2_SOFT_RST ( BIT(27) ) +#define BIT_ADC1_SOFT_RST ( BIT(26) ) +#define BIT_MBOX_SOFT_RST ( BIT(25) ) +#define BIT_RTC4M1_CAL_SOFT_RST ( BIT(23) ) +#define BIT_RTC4M0_CAL_SOFT_RST ( BIT(22) ) +#define BIT_LDSP_SYS_SOFT_RST ( BIT(21) ) +#define BIT_LCP_SYS_SOFT_RST ( BIT(20) ) +#define BIT_DAC3_SOFT_RST ( BIT(19) ) +#define BIT_DAC2_SOFT_RST ( BIT(18) ) +#define BIT_DAC1_SOFT_RST ( BIT(17) ) +#define BIT_ADC3_CAL_SOFT_RST ( BIT(16) ) +#define BIT_ADC2_CAL_SOFT_RST ( BIT(15) ) +#define BIT_ADC1_CAL_SOFT_RST ( BIT(14) ) +#define BIT_MDAR_SOFT_RST ( BIT(13) ) +#define BIT_LVDSDIS_SOFT_RST ( BIT(12) ) +#define BIT_BB_CAL_SOFT_RST ( BIT(11) ) +#define BIT_DCXO_LC_SOFT_RST ( BIT(10) ) +#define BIT_AP_TMR2_SOFT_RST ( BIT(9) ) +#define BIT_AP_TMR1_SOFT_RST ( BIT(8) ) +#define BIT_CA7_WDG_SOFT_RST ( BIT(7) ) +#define BIT_AON_DMA_SOFT_RST ( BIT(6) ) +#define BIT_AVS_SOFT_RST ( BIT(5) ) +#define BIT_DMC_PHY_SOFT_RST ( BIT(4) ) +#define BIT_GPU_THMA_SOFT_RST ( BIT(3) ) +#define BIT_ARM_THMA_SOFT_RST ( BIT(2) ) +#define BIT_THM_SOFT_RST ( BIT(1) ) +#define BIT_PMU_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_APB_RTC_EB */ +#define BIT_CP0_LTE_EB ( BIT(19) ) +#define BIT_BB_CAL_RTC_EB ( BIT(18) ) +#define BIT_DCXO_LC_RTC_EB ( BIT(17) ) +#define BIT_AP_TMR2_RTC_EB ( BIT(16) ) +#define BIT_AP_TMR1_RTC_EB ( BIT(15) ) +#define BIT_GPU_THMA_RTC_AUTO_EN ( BIT(14) ) +#define BIT_ARM_THMA_RTC_AUTO_EN ( BIT(13) ) +#define BIT_GPU_THMA_RTC_EB ( BIT(12) ) +#define BIT_ARM_THMA_RTC_EB ( BIT(11) ) +#define BIT_THM_RTC_EB ( BIT(10) ) +#define BIT_CA7_WDG_RTC_EB ( BIT(9) ) +#define BIT_AP_WDG_RTC_EB ( BIT(8) ) +#define BIT_EIC_RTCDV5_EB ( BIT(7) ) +#define BIT_EIC_RTC_EB ( BIT(6) ) +#define BIT_AP_TMR0_RTC_EB ( BIT(5) ) +#define BIT_AON_TMR_RTC_EB ( BIT(4) ) +#define BIT_AP_SYST_RTC_EB ( BIT(3) ) +#define BIT_AON_SYST_RTC_EB ( BIT(2) ) +#define BIT_KPD_RTC_EB ( BIT(1) ) +#define BIT_ARCH_RTC_EB ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_REC_26MHZ_BUF_CFG */ +#define BITS_PLL_PROBE_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_REC_26MHZ_1_CUR_SEL ( BIT(4) ) +#define BIT_REC_26MHZ_0_CUR_SEL ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_SINDRV_CTRL */ +#define BITS_SINDRV_LVL(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)) ) +#define BIT_SINDRV_CLIP_MODE ( BIT(2) ) +#define BIT_SINDRV_ENA_SQUARE ( BIT(1) ) +#define BIT_SINDRV_ENA ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_ADA_SEL_CTRL */ + +/* bits definitions for register REG_AON_APB_VBC_CTRL */ +#define BIT_AUDIF_CKG_AUTO_EN ( BIT(20) ) +#define BITS_AUD_INT_SYS_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_VBC_AFIFO_INT_SYS_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_VBC_AD23_INT_SYS_SEL(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_VBC_AD01_INT_SYS_SEL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_VBC_DA01_INT_SYS_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_VBC_AD23_DMA_SYS_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_VBC_AD01_DMA_SYS_SEL(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_VBC_DA01_DMA_SYS_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +//#define BIT_VBC_INT_CP0_ARM_SEL ( BIT(3) ) +//#define BIT_VBC_INT_CP1_ARM_SEL ( BIT(2) ) +//#define BIT_VBC_DMA_CP0_ARM_SEL ( BIT(1) ) +//#define BIT_VBC_DMA_CP1_ARM_SEL ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_PWR_CTRL */ +#define BIT_HSIC_PLL_EN ( BIT(19) ) +#define BIT_HSIC_PHY_PD ( BIT(18) ) +#define BIT_HSIC_PS_PD_S ( BIT(17) ) +#define BIT_HSIC_PS_PD_L ( BIT(16) ) +#define BIT_MIPI_DSI_PS_PD_S ( BIT(15) ) +#define BIT_MIPI_DSI_PS_PD_L ( BIT(14) ) +#define BIT_MIPI_CSI_4LANE_PS_PD_S ( BIT(13) ) +#define BIT_MIPI_CSI_4LANE_PS_PD_L ( BIT(12) ) +#define BIT_MIPI_CSI_2LANE_PS_PD_S ( BIT(11) ) +#define BIT_MIPI_CSI_2LANE_PS_PD_L ( BIT(10) ) +#define BIT_CA7_TS1_STOP ( BIT(9) ) +#define BIT_CA7_TS0_STOP ( BIT(8) ) +#define BIT_EFUSE_BIST_PWR_ON ( BIT(3) ) +#define BIT_FORCE_DSI_PHY_SHUTDOWNZ ( BIT(2) ) +#define BIT_FORCE_CSI_PHY_SHUTDOWNZ ( BIT(1) ) +#define BIT_USB_PHY_PD ( BIT(0) ) + +#define BIT_CSI1_PHY_PD ( BIT(11) ) +#define BIT_CSI0_PHY_PD ( BIT(10) ) + +/* bits definitions for register REG_AON_APB_TS_CFG */ +#define BIT_CSYSACK_TS_LP_2 ( BIT(13) ) +#define BIT_CSYSREQ_TS_LP_2 ( BIT(12) ) +#define BIT_CSYSACK_TS_LP_1 ( BIT(11) ) +#define BIT_CSYSREQ_TS_LP_1 ( BIT(10) ) +#define BIT_CSYSACK_TS_LP_0 ( BIT(9) ) +#define BIT_CSYSREQ_TS_LP_0 ( BIT(8) ) +#define BIT_EVENTACK_RESTARTREQ_TS01 ( BIT(4) ) +#define BIT_EVENT_RESTARTREQ_TS01 ( BIT(1) ) +#define BIT_EVENT_HALTREQ_TS01 ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_BOOT_MODE */ +#define BIT_ARM_JTAG_EN ( BIT(13) ) +#define BIT_WPLL_OVR_FREQ_SEL ( BIT(12) ) +#define BIT_PTEST_FUNC_ATSPEED_SEL ( BIT(8) ) +#define BIT_PTEST_FUNC_MODE ( BIT(7) ) +#define BIT_USB_DLOAD_EN ( BIT(4) ) +#define BIT_ARM_BOOT_MD3 ( BIT(3) ) +#define BIT_ARM_BOOT_MD2 ( BIT(2) ) +#define BIT_ARM_BOOT_MD1 ( BIT(1) ) +#define BIT_ARM_BOOT_MD0 ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_BB_BG_CTRL */ +#define BIT_BB_CON_BG ( BIT(22) ) +#define BITS_BB_BG_RSV(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)) ) +#define BITS_BB_LDO_V(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BIT_BB_BG_RBIAS_EN ( BIT(15) ) +#define BIT_BB_BG_IEXT_IB_EN ( BIT(14) ) +#define BITS_BB_LDO_REFCTRL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) ) +#define BIT_BB_LDO_AUTO_PD_EN ( BIT(11) ) +#define BIT_BB_LDO_SLP_PD_EN ( BIT(10) ) +#define BIT_BB_LDO_FORCE_ON ( BIT(9) ) +#define BIT_BB_LDO_FORCE_PD ( BIT(8) ) +#define BIT_BB_BG_AUTO_PD_EN ( BIT(3) ) +#define BIT_BB_BG_SLP_PD_EN ( BIT(2) ) +#define BIT_BB_BG_FORCE_ON ( BIT(1) ) +#define BIT_BB_BG_FORCE_PD ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_CP_ARM_JTAG_CTRL */ +#define BITS_CP_ARM_JTAG_PIN_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AON_APB_PLL_SOFT_CNT_DONE */ +#define BIT_RC1_SOFT_CNT_DONE ( BIT(13) ) +#define BIT_RC0_SOFT_CNT_DONE ( BIT(12) ) +#define BIT_XTLBUF1_SOFT_CNT_DONE ( BIT(9) ) +#define BIT_XTLBUF0_SOFT_CNT_DONE ( BIT(8) ) +#define BIT_LVDSPLL_SOFT_CNT_DONE ( BIT(4) ) +#define BIT_LPLL_SOFT_CNT_DONE ( BIT(3) ) +#define BIT_TWPLL_SOFT_CNT_DONE ( BIT(2) ) +#define BIT_DPLL_SOFT_CNT_DONE ( BIT(1) ) +#define BIT_MPLL_SOFT_CNT_DONE ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_DCXO_LC_REG0 */ +#define BIT_DCXO_LC_FLAG ( BIT(8) ) +#define BIT_DCXO_LC_FLAG_CLR ( BIT(1) ) +#define BIT_DCXO_LC_CNT_CLR ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_DCXO_LC_REG1 */ +#define BITS_DCXO_LC_CNT(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_MPLL_CFG1 */ +#define BITS_MPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)) ) +#define BIT_MPLL_LOCK_DONE ( BIT(27) ) +#define BIT_MPLL_DIV_S ( BIT(26) ) +#define BIT_MPLL_MOD_EN ( BIT(25) ) +#define BIT_MPLL_SDM_EN ( BIT(24) ) +#define BITS_MPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_MPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_MPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_MPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AON_APB_MPLL_CFG2 */ +#define BITS_MPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_MPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_AON_APB_DPLL_CFG1 */ +#define BITS_DPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)) ) +#define BIT_DPLL_LOCK_DONE ( BIT(27) ) +#define BIT_DPLL_DIV_S ( BIT(26) ) +#define BIT_DPLL_MOD_EN ( BIT(25) ) +#define BIT_DPLL_SDM_EN ( BIT(24) ) +#define BITS_DPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_DPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_DPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_DPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AON_APB_DPLL_CFG2 */ +#define BITS_DPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_DPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_AON_APB_TWPLL_CFG1 */ +#define BITS_TWPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)) ) +#define BIT_TWPLL_LOCK_DONE ( BIT(27) ) +#define BIT_TWPLL_DIV_S ( BIT(26) ) +#define BIT_TWPLL_MOD_EN ( BIT(25) ) +#define BIT_TWPLL_SDM_EN ( BIT(24) ) +#define BITS_TWPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_TWPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_TWPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_TWPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AON_APB_TWPLL_CFG2 */ +#define BITS_TWPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_TWPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_AON_APB_LTEPLL_CFG1 */ +#define BITS_LTEPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)) ) +#define BIT_LTEPLL_LOCK_DONE ( BIT(27) ) +#define BIT_LTEPLL_DIV_S ( BIT(26) ) +#define BIT_LTEPLL_MOD_EN ( BIT(25) ) +#define BIT_LTEPLL_SDM_EN ( BIT(24) ) +#define BITS_LTEPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_LTEPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_LTEPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_LTEPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AON_APB_LTEPLL_CFG2 */ +#define BITS_LTEPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_LTEPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_AON_APB_LVDSDISPLL_CFG1 */ +#define BITS_LVDSDISPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_LVDSDISPLL_LOCK_DONE ( BIT(27) ) +#define BIT_LVDSDISPLL_DIV_S ( BIT(26) ) +#define BIT_LVDSDISPLL_MOD_EN ( BIT(25) ) +#define BIT_LVDSDISPLL_SDM_EN ( BIT(24) ) +#define BITS_LVDSDISPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_LVDSDISPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_LVDSDISPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_LVDSDISPLL_POSTDIV(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LVDSDISPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AON_APB_LVDSDISPLL_CFG2 */ +#define BITS_LVDSDISPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_LVDSDISPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_AON_APB_AON_REG_PROT */ +#define BIT_LDSP_CTRL_PROT ( BIT(31) ) +#define BITS_REG_PROT_VAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AON_APB_LDSP_BOOT_EN */ +#define BIT_FRC_CLK_LDSP_EN ( BIT(1) ) +#define BIT_LDSP_BOOT_EN ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_LDSP_BOOT_VEC */ +#define BITS_LDSP_BOOT_VECTOR(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_LDSP_RST */ +#define BIT_LDSP_SYS_SRST ( BIT(1) ) +#define BIT_LDSP_CORE_SRST_N ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_LDSP_MTX_CTRL1 */ +#define BITS_LDSP_MTX_CTRL1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_LDSP_MTX_CTRL2 */ +#define BITS_LDSP_MTX_CTRL2(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_LDSP_MTX_CTRL3 */ +#define BITS_LDSP_MTX_CTRL3(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_AON_CGM_CFG */ +#define BITS_PROBE_CKG_DIV(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_AUX2_CKG_DIV(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_AUX1_CKG_DIV(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_AUX0_CKG_DIV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_PROBE_CKG_SEL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_AUX2_CKG_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_AUX1_CKG_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_AUX0_CKG_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_LACC_MTX_CTRL */ +#define BITS_LACC_MTX_CTRL(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CORTEX_MTX_CTRL1 */ +#define BITS_CORTEX_MTX_CTRL1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CORTEX_MTX_CTRL2 */ +#define BITS_CORTEX_MTX_CTRL2(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CORTEX_MTX_CTRL3 */ +#define BITS_CORTEX_MTX_CTRL3(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AON_APB_CA5_TCLK_DLY_LEN */ +#define BITS_CA5_TCLK_DLY_LEN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AON_APB_CCIR_RCVR_CFG */ +#define BITS_ANALOG_PLL_RSV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_ANALOG_TESTMUX(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_CCIR_SE ( BIT(1) ) +#define BIT_CCIR_IE ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_PLL_BG_CFG */ +#define BITS_PLL_BG_RSV(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BIT_PLL_BG_RBIAS_EN ( BIT(3) ) +#define BIT_PLL_BG_PD ( BIT(2) ) +#define BIT_PLL_BG_IEXT_IBEN ( BIT(1) ) +#define BIT_PLL_CON_BG ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_LVDSDIS_SEL */ +#define BITS_LVDSDIS_LOG_SEL(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)) ) +#define BIT_LVDSDIS_DBG_SEL ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_DJTAG_MUX_SEL */ +#define BIT_DJTAG_AON_SEL ( BIT(6) ) +#define BIT_DJTAG_PUB_SEL ( BIT(5) ) +#define BIT_DJTAG_CP1_SEL ( BIT(4) ) +#define BIT_DJTAG_CP0_SEL ( BIT(3) ) +#define BIT_DJTAG_GPU_SEL ( BIT(2) ) +#define BIT_DJTAG_MM_SEL ( BIT(1) ) +#define BIT_DJTAG_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_ARM7_SYS_SOFT_RST */ +#define BIT_ARM7_SYS_SOFT_RST ( BIT(4) ) +#define BIT_ARM7_CORE_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_CP1_CP0_ADDR_MSB */ +#define BITS_CP1_CP0_ADDR_MSB(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_AON_DMA_INT_EN */ +#define BIT_AON_DMA_INT_ARM7_EN ( BIT(6) ) +#define BIT_AON_DMA_INT_CP1_DSP_EN ( BIT(5) ) +#define BIT_AON_DMA_INT_CP1_CA5_EN ( BIT(4) ) +#define BIT_AON_DMA_INT_CP0_DSP_1_EN ( BIT(3) ) +#define BIT_AON_DMA_INT_CP0_DSP_0_EN ( BIT(2) ) +#define BIT_AON_DMA_INT_CP0_ARM9_0_EN ( BIT(1) ) +#define BIT_AON_DMA_INT_AP_EN ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_EMC_AUTO_GATE_EN */ +#define BIT_CP1_PUB_AUTO_GATE_EN ( BIT(19) ) +#define BIT_CP0_PUB_AUTO_GATE_EN ( BIT(18) ) +#define BIT_AP_PUB_AUTO_GATE_EN ( BIT(17) ) +#define BIT_AON_APB_PUB_AUTO_GATE_EN ( BIT(16) ) +#define BIT_CP1_EMC_AUTO_GATE_EN ( BIT(3) ) +#define BIT_CP0_EMC_AUTO_GATE_EN ( BIT(2) ) +#define BIT_AP_EMC_AUTO_GATE_EN ( BIT(1) ) +#define BIT_CA7_EMC_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_ARM7_CFG_BUS */ +#define BIT_FUNCTST_DMA_EB ( BIT(2) ) +#define BIT_ARM7_FUNCTST_BUS_SLEEP ( BIT(1) ) +#define BIT_ARM7_CFG_BUS_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_RTC4M_0_CFG */ +#define BITS_RTC4M0_RSV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RTC4M0_I_C(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BIT_RTC4M0_CAL_DONE ( BIT(6) ) +#define BIT_RTC4M0_CAL_START ( BIT(5) ) +#define BIT_RTC4M0_CHOP_EN ( BIT(4) ) +#define BIT_RTC4M0_FORCE_EN ( BIT(1) ) +#define BIT_RTC4M0_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_RTC4M_1_CFG */ +#define BITS_RTC4M1_RSV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RTC4M1_I_C(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BIT_RTC4M1_CAL_DONE ( BIT(6) ) +#define BIT_RTC4M1_CAL_START ( BIT(5) ) +#define BIT_RTC4M1_CHOP_EN ( BIT(4) ) +#define BIT_RTC4M1_FORCE_EN ( BIT(1) ) +#define BIT_RTC4M1_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_APB_RST2 */ +#define BIT_AON_DJTAG_SOFT_RST ( BIT(6) ) +#define BIT_PUB_DJTAG_SOFT_RST ( BIT(5) ) +#define BIT_GPU_DJTAG_SOFT_RST ( BIT(4) ) +#define BIT_MM_DJTAG_SOFT_RST ( BIT(3) ) +#define BIT_CP1_DJTAG_SOFT_RST ( BIT(2) ) +#define BIT_CP0_DJTAG_SOFT_RST ( BIT(1) ) +#define BIT_AP_DJTAG_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_RF_TGDSP_BOOT_EN */ +#define BIT_AHB_VCP1_DEEP_SLEEP_EN ( BIT(4) ) +#define BIT_ASHB_ARMTODSP_EN ( BIT(3) ) +#define BIT_ARM_DAHB_SLEEP_EN ( BIT(2) ) +#define BIT_FRC_CLK_TGDSP_EN ( BIT(1) ) +#define BIT_TGDSP_BOOT_EN ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_RF_TGDSP_BOOT_VEC */ +#define BITS_AON_APB_RF_TGDSP_BOOT_VECTOR(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_RF_TGDSP_RST */ +#define BIT_AON_APB_RF_TGDSP_SYS_SRST ( BIT(1) ) +#define BIT_AON_APB_RF_TGDSP_CORE_SRST_N ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_RF_RFFE_CFG */ +#define BIT_AON_APB_RF_LTE_RFFE_SEL ( BIT(1) ) +#define BIT_AON_APB_RF_TG_RFFE_SEL ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_RF_osc_ctrl */ +#define BITS_AON_APB_RF_OSC_CTRL_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)) ) +#define BIT_AON_APB_RF_OSC_CTRL_EN ( BIT(15) ) +#define BIT_AON_APB_RF_OSC_CTRL_START ( BIT(14) ) +#define BIT_AON_APB_RF_OSC_CTRL_RSTN ( BIT(13) ) +#define BITS_AON_APB_RF_OSC_CTRL_CLK_NUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) + +/* bits definitions for register REG_AON_APB_RF_OSC_OBS */ +#define BIT_AON_APB_RF_OSC_OBS_OVERFLOW ( BIT(15) ) +#define BITS_AON_APB_RF_OSC_OBS_SPEED_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register REG_AON_APB_RF_CA7_SDISABLE */ +#define BIT_AON_APB_RF_CA7_CFGSDISABLE ( BIT(4) ) +#define BITS_AON_APB_RF_CA7_CP15SDISABLE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) +/* bits definitions for register REG_AON_APB_AP_WPROT_EN1 */ +#define BITS_AP_AWADDR_WPROT_EN1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CP0_WPROT_EN1 */ +#define BITS_CP0_AWADDR_WPROT_EN1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CP1_WPROT_EN1 */ +#define BITS_CP1_AWADDR_WPROT_EN1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_IO_DLY_CTRL */ +#define BITS_CLK_CCIR_DLY_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CLK_CP1DSP_DLY_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_CLK_CP0DSP_DLY_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_AP_WPROT_EN0 */ +#define BITS_AP_AWADDR_WPROT_EN0(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CP0_WPROT_EN0 */ +#define BITS_CP0_AWADDR_WPROT_EN0(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CP1_WPROT_EN0 */ +#define BITS_CP1_AWADDR_WPROT_EN0(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_PMU_RST_MONITOR */ +#define BITS_PMU_RST_MONITOR(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_THM_RST_MONITOR */ +#define BITS_THM_RST_MONITOR(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_AP_RST_MONITOR */ +#define BITS_AP_RST_MONITOR(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CA7_RST_MONITOR */ +#define BITS_CA7_RST_MONITOR(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_BOND_OPT0 */ +#define BITS_BOND_OPTION0(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_BOND_OPT1 */ +#define BITS_BOND_OPTION1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_RES_REG0 */ +#define BITS_RES_REG0(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_RES_REG1 */ +#define BITS_RES_REG1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_AON_QOS_CFG */ +#define BITS_QOS_R_GPU(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_QOS_W_GPU(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_QOS_R_GSP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_QOS_W_GSP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_BB_LDO_CAL_START */ +#define BIT_BB_LDO_CAL_START ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_AON_MTX_PROT_CFG */ +#define BITS_HPROT_DMAW(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_HPROT_DMAR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_LVDS_CFG */ +#define BITS_LVDSDIS_TXIMP(_X_) ( (_X_) << 29 & (BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_LVDSDIS_TXPD(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) ) +#define BITS_LVDSDIS_TXCLKDATA(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)) ) +#define BIT_LVDSDIS_OFF_OCT ( BIT(15) ) +#define BIT_LVDSDIS_OFF_CL ( BIT(14) ) +#define BITS_LVDSDIS_TXCOM(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_LVDSDIS_TXSLEW(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_LVDSDIS_TXSW(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_LVDSDIS_CLKOUT_EN ( BIT(7) ) +#define BITS_LVDSDIS_TXRERSER(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) +#define BITS_LVDSDIS_PRE_EMP(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AON_APB_PLL_LOCK_OUT_SEL */ +#define BITS_DPLL_DBG_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_LPLL_DBG_SEL(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_LVDSPLL_DBG_SEL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_MPLL_DBG_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_TWPLL_DBG_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_SLEEP_PLLLOCK_SEL ( BIT(7) ) +#define BITS_PLL_LOCK_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BITS_SLEEP_DBG_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_RTC4M_RC_VAL */ +#define BIT_RTC4M1_RC_SEL ( BIT(31) ) +#define BITS_RTC4M1_RC_VAL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) ) +#define BIT_RTC4M0_RC_SEL ( BIT(15) ) +#define BITS_RTC4M0_RC_VAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) ) + +/* bits definitions for register REG_AON_APB_RF_CP0_MISC_CTL0 */ +#define BITS_ARM_FRC_STOP(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BIT_MCU_FORCE_LIGHT_SLEEP ( BIT(5) ) +#define BIT_MCU_FORCE_DEEP_SLEEP ( BIT(4) ) +#define BIT_CHIP_SLP_ARM_CLR ( BIT(3) ) +#define BIT_ALL_CLK_EN ( BIT(2) ) +#define BIT_WAKEUP_XTL_EN_2G ( BIT(1) ) +#define BIT_WAKEUP_XTL_EN_3G_TD ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_RF_CP0_MCU_C2C_SEMA */ +#define BITS_MCU_C2C_SEMA(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AON_APB_RF_CP0_MCU_CLK_CTL */ +#define BIT_CLK_MCU_DBG_SEL ( BIT(4) ) +#define BITS_CLK_COM_DBG_SEL(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_CLK_SYS_DBG_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_APB_RF_PROT_BUS_SECURE_EN */ +#define BIT_BUS_SECURE_EN ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_RF_PROT_ARM7_SPACE_EN */ +#define BIT_ARM7_SPACE_EN ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_RF_APB_ROM_PD_CTL */ +#define BIT_ROM_FORCE_ON ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_RF_CP0_SLP_STS */ +#define BITS_CP0_SLP_STS(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_RF_CP0_DSP_JTAG_CTL */ +#define BIT_CEVA_SW_JTAG_ENA ( BIT(8) ) +#define BIT_STDO ( BIT(4) ) +#define BIT_STCK ( BIT(3) ) +#define BIT_STMS ( BIT(2) ) +#define BIT_STDI ( BIT(1) ) +#define BIT_STRTCK ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_RF_ANA_PD_STS */ +#define BITS_ANA_PD_STS(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_RF_AON_APB_RSV */ +#define BITS_AON_APB_RSV(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_AON_CHIP_ID */ +#define BITS_AON_CHIP_ID(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_RF_AON_CHIP_ID_DIG */ +#define BITS_AON_CHIP_ID_DIG(_X_) (_X_) + +#endif diff --git a/include/soc/sprd/chip_x20l/__regs_aon_clk.h b/include/soc/sprd/chip_x20l/__regs_aon_clk.h new file mode 100644 index 00000000..3f78be87 --- /dev/null +++ b/include/soc/sprd/chip_x20l/__regs_aon_clk.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __REGS_AON_CLK_H__ +#define __REGS_AON_CLK_H__ + +#define REGS_AON_CLK + +/* registers definitions for controller REGS_AON_CLK */ +#define REG_AON_CLK_PUB_AHB_CFG SCI_ADDR(SPRD_AONCKG_BASE, 0x0020) +#define REG_AON_CLK_AON_APB_CFG SCI_ADDR(SPRD_AONCKG_BASE, 0x0024) +#define REG_AON_CLK_ADI_CFG SCI_ADDR(SPRD_AONCKG_BASE, 0x0028) +#define REG_AON_CLK_PWM0_CFG SCI_ADDR(SPRD_AONCKG_BASE, 0x002c) +#define REG_AON_CLK_PWM1_CFG SCI_ADDR(SPRD_AONCKG_BASE, 0x0030) +#define REG_AON_CLK_PWM2_CFG SCI_ADDR(SPRD_AONCKG_BASE, 0x0034) +#define REG_AON_CLK_PWM3_CFG SCI_ADDR(SPRD_AONCKG_BASE, 0x0038) +#define REG_AON_CLK_ARM7_UART_CFG SCI_ADDR(SPRD_AONCKG_BASE, 0x003c) +#define REG_AON_CLK_THM_CFG SCI_ADDR(SPRD_AONCKG_BASE, 0x0040) +#define REG_AON_CLK_MSPI_CFG SCI_ADDR(SPRD_AONCKG_BASE, 0x0044) +#define REG_AON_CLK_I2C_CFG SCI_ADDR(SPRD_AONCKG_BASE, 0x0048) +#define REG_AON_CLK_AVS_CFG SCI_ADDR(SPRD_AONCKG_BASE, 0x004c) +#define REG_AON_CLK_AUDIF_CFG SCI_ADDR(SPRD_AONCKG_BASE, 0x0050) +#define REG_AON_CLK_CA7_DAP_CFG SCI_ADDR(SPRD_AONCKG_BASE, 0x0054) +#define REG_AON_CLK_EMC_CFG SCI_ADDR(SPRD_AONCKG_BASE, 0x0058) +#define REG_AON_CLK_CA7_TS_CFG SCI_ADDR(SPRD_AONCKG_BASE, 0x005c) +#define REG_AON_CLK_DJTAG_CLK_CFG SCI_ADDR(SPRD_AONCKG_BASE, 0x0060) +#define REG_AON_CLK_ARM7_AHB_CFG SCI_ADDR(SPRD_AONCKG_BASE, 0x0064) +#define REG_AON_CLK_CA5_TS_CFG SCI_ADDR(SPRD_AONCKG_BASE, 0x0068) +/* vars definitions for controller REGS_AON_CLK */ +#define PUB_AHB_CLK_SEL_SHIFT (0x0) +#define PUB_AHB_CLK_SEL_MASK (0x3 << PUB_AHB_CLK_SEL_SHIFT) + +#define PUB_APB_CLK_SEL_SHIFT (0x0) +#define PUB_APB_CLK_SEL_MASK (0x3 << PUB_AHB_CLK_SEL_SHIFT) +#endif //__REGS_AON_CLK_H__ diff --git a/include/soc/sprd/chip_x20l/__regs_ap_ahb_rf.h b/include/soc/sprd/chip_x20l/__regs_ap_ahb_rf.h new file mode 100755 index 00000000..eb40dc11 --- /dev/null +++ b/include/soc/sprd/chip_x20l/__regs_ap_ahb_rf.h @@ -0,0 +1,367 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_AP_AHB_HEADFILE_H__ +#define __H_REGS_AP_AHB_HEADFILE_H__ __FILE__ + +#define REGS_AP_AHB_RF + +/* registers definitions for controller REGS_AP_AHB */ +#define REG_AP_AHB_AHB_EB SCI_ADDR(REGS_AP_AHB_BASE, 0x0000) +#define REG_AP_AHB_AHB_RST SCI_ADDR(REGS_AP_AHB_BASE, 0x0004) +#define REG_AP_AHB_CA7_RST_SET SCI_ADDR(REGS_AP_AHB_BASE, 0x0008) +#define REG_AP_AHB_AP_SYS_FORCE_SLEEP_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x000C) +#define REG_AP_AHB_AP_SYS_AUTO_SLEEP_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x0010) +#define REG_AP_AHB_HOLDING_PEN SCI_ADDR(REGS_AP_AHB_BASE, 0x0014) +#define REG_AP_AHB_JMP_ADDR_CA7_C0 SCI_ADDR(REGS_AP_AHB_BASE, 0x0018) +#define REG_AP_AHB_JMP_ADDR_CA7_C1 SCI_ADDR(REGS_AP_AHB_BASE, 0x001C) +#define REG_AP_AHB_JMP_ADDR_CA7_C2 SCI_ADDR(REGS_AP_AHB_BASE, 0x0020) +#define REG_AP_AHB_JMP_ADDR_CA7_C3 SCI_ADDR(REGS_AP_AHB_BASE, 0x0024) +#define REG_AP_AHB_CA7_C0_PU_LOCK SCI_ADDR(REGS_AP_AHB_BASE, 0x0028) +#define REG_AP_AHB_CA7_C1_PU_LOCK SCI_ADDR(REGS_AP_AHB_BASE, 0x002C) +#define REG_AP_AHB_CA7_C2_PU_LOCK SCI_ADDR(REGS_AP_AHB_BASE, 0x0030) +#define REG_AP_AHB_CA7_C3_PU_LOCK SCI_ADDR(REGS_AP_AHB_BASE, 0x0034) +#define REG_AP_AHB_CA7_CKG_DIV_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x0038) +#define REG_AP_AHB_MCU_PAUSE SCI_ADDR(REGS_AP_AHB_BASE, 0x003C) +#define REG_AP_AHB_MISC_CKG_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x0040) +#define REG_AP_AHB_CA7_C0_AUTO_FORCE_SHUTDOWN_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x0044) +#define REG_AP_AHB_CA7_C1_AUTO_FORCE_SHUTDOWN_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x0048) +#define REG_AP_AHB_CA7_C2_AUTO_FORCE_SHUTDOWN_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x004C) +#define REG_AP_AHB_CA7_C3_AUTO_FORCE_SHUTDOWN_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x0050) +#define REG_AP_AHB_CA7_CKG_SEL_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x0054) +#define REG_AP_AHB_MISC_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x3000) +#define REG_AP_AHB_AP_MAIN_MTX_HPROT_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x3004) +#define REG_AP_AHB_CA7_STANDBY_STATUS SCI_ADDR(REGS_AP_AHB_BASE, 0x3008) +#define REG_AP_AHB_NANC_CLK_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x300C) +#define REG_AP_AHB_LVDS_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x3010) +#define REG_AP_AHB_LVDS_PLL_CFG0 SCI_ADDR(REGS_AP_AHB_BASE, 0x3014) +#define REG_AP_AHB_LVDS_PLL_CFG1 SCI_ADDR(REGS_AP_AHB_BASE, 0x3018) +#define REG_AP_AHB_AP_QOS_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x301C) +#define REG_AP_AHB_OTG_PHY_TUNE SCI_ADDR(REGS_AP_AHB_BASE, 0x3020) +#define REG_AP_AHB_OTG_PHY_TEST SCI_ADDR(REGS_AP_AHB_BASE, 0x3024) +#define REG_AP_AHB_OTG_PHY_CTRL SCI_ADDR(REGS_AP_AHB_BASE, 0x3028) +#define REG_AP_AHB_HSIC_PHY_TUNE SCI_ADDR(REGS_AP_AHB_BASE, 0x302C) +#define REG_AP_AHB_HSIC_PHY_TEST SCI_ADDR(REGS_AP_AHB_BASE, 0x3030) +#define REG_AP_AHB_HSIC_PHY_CTRL SCI_ADDR(REGS_AP_AHB_BASE, 0x3034) +#define REG_AP_AHB_ZIP_MTX_QOS_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x3038) +#define REG_AP_AHB_CHIP_ID SCI_ADDR(REGS_AP_AHB_BASE, 0x30FC) + +/* bits definitions for register REG_AP_AHB_AHB_EB */ +#define BIT_ZIPMTX_EB ( BIT(23) ) +#define BIT_LVDS_EB ( BIT(22) ) +#define BIT_ZIPDEC_EB ( BIT(21) ) +#define BIT_ZIPENC_EB ( BIT(20) ) +#define BIT_NANDC_ECC_EB ( BIT(19) ) +#define BIT_NANDC_2X_EB ( BIT(18) ) +#define BIT_NANDC_EB ( BIT(17) ) +#define BIT_BUSMON2_EB ( BIT(16) ) +#define BIT_BUSMON1_EB ( BIT(15) ) +#define BIT_BUSMON0_EB ( BIT(14) ) +#define BIT_SPINLOCK_EB ( BIT(13) ) +#define BIT_EMMC_EB ( BIT(11) ) +#define BIT_SDIO2_EB ( BIT(10) ) +#define BIT_SDIO1_EB ( BIT(9) ) +#define BIT_SDIO0_EB ( BIT(8) ) +#define BIT_DRM_EB ( BIT(7) ) +#define BIT_NFC_EB ( BIT(6) ) +#define BIT_DMA_EB ( BIT(5) ) +#define BIT_OTG_EB ( BIT(4) ) +#define BIT_USB_EB ( BIT_OTG_EB ) +#define BIT_GSP_EB ( BIT(3) ) +#define BIT_HSIC_EB ( BIT(2) ) +#define BIT_DISPC_EB ( BIT(1) ) +#define BIT_DISPC0_EB ( BIT_DISPC_EB ) +#define BIT_DSI_EB ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_AHB_RST */ +#define BIT_HSIC_PHY_SOFT_RST ( BIT(30) ) +#define BIT_HSIC_UTMI_SOFT_RST ( BIT(29) ) +#define BIT_HSIC_SOFT_RST ( BIT(28) ) +#define BIT_LVDS_SOFT_RST ( BIT(25) ) +#define BIT_ZIP_MTX_SOFT_RST ( BIT(24) ) +#define BIT_ZIPDEC_SOFT_RST ( BIT(23) ) +#define BIT_ZIPENC_SOFT_RST ( BIT(22) ) +#define BIT_NANDC_SOFT_RST ( BIT(20) ) +#define BIT_BUSMON2_SOFT_RST ( BIT(19) ) +#define BIT_BUSMON1_SOFT_RST ( BIT(18) ) +#define BIT_BUSMON0_SOFT_RST ( BIT(17) ) +#define BIT_SPINLOCK_SOFT_RST ( BIT(16) ) +#define BIT_EMMC_SOFT_RST ( BIT(14) ) +#define BIT_SDIO2_SOFT_RST ( BIT(13) ) +#define BIT_SDIO1_SOFT_RST ( BIT(12) ) +#define BIT_SDIO0_SOFT_RST ( BIT(11) ) +#define BIT_DRM_SOFT_RST ( BIT(10) ) +#define BIT_NFC_SOFT_RST ( BIT(9) ) +#define BIT_DMA_SOFT_RST ( BIT(8) ) +#define BIT_OTG_PHY_SOFT_RST ( BIT(6) ) +#define BIT_OTG_UTMI_SOFT_RST ( BIT(5) ) +#define BIT_OTG_SOFT_RST ( BIT(4) ) +#define BIT_GSP_SOFT_RST ( BIT(3) ) +#define BIT_DISP_MTX_SOFT_RST ( BIT(2) ) +#define BIT_DISPC0_SOFT_RST ( BIT(1) ) +#define BIT_DSI_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_CA7_RST_SET */ +#define BIT_CA7_CS_DBG_SOFT_RST ( BIT(14) ) +#define BIT_CA7_L2_SOFT_RST ( BIT(13) ) +#define BIT_CA7_SOCDBG_SOFT_RST ( BIT(12) ) +#define BITS_CA7_ETM_SOFT_RST(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CA7_DBG_SOFT_RST(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_CA7_CORE_SOFT_RST(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AP_AHB_AP_SYS_FORCE_SLEEP_CFG */ +#define BIT_CA7_C3_AUTO_SLP_EN ( BIT(15) ) +#define BIT_CA7_C2_AUTO_SLP_EN ( BIT(14) ) +#define BIT_CA7_C1_AUTO_SLP_EN ( BIT(13) ) +#define BIT_CA7_C0_AUTO_SLP_EN ( BIT(12) ) +#define BIT_CA7_C3_WFI_SHUTDOWN_EN ( BIT(11) ) +#define BIT_CA7_C2_WFI_SHUTDOWN_EN ( BIT(10) ) +#define BIT_CA7_C1_WFI_SHUTDOWN_EN ( BIT(9) ) +#define BIT_CA7_C0_WFI_SHUTDOWN_EN ( BIT(8) ) +#define BIT_MCU_CA7_C3_SLEEP ( BIT(7) ) +#define BIT_MCU_CA7_C2_SLEEP ( BIT(6) ) +#define BIT_MCU_CA7_C1_SLEEP ( BIT(5) ) +#define BIT_MCU_CA7_C0_SLEEP ( BIT(4) ) +#define BIT_AP_PERI_FORCE_ON ( BIT(2) ) +#define BIT_AP_PERI_FORCE_SLP ( BIT(1) ) +#define BIT_AP_APB_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_AP_SYS_AUTO_SLEEP_CFG */ +#define BIT_GSP_CKG_FORCE_EN ( BIT(9) ) +#define BIT_GSP_AUTO_GATE_EN ( BIT(8) ) +#define BIT_AP_AHB_AUTO_GATE_EN ( BIT(5) ) +#define BIT_AP_EMC_AUTO_GATE_EN ( BIT(4) ) +#define BIT_CA7_EMC_AUTO_GATE_EN ( BIT(3) ) +#define BIT_CA7_DBG_FORCE_SLEEP ( BIT(2) ) +#define BIT_CA7_DBG_AUTO_GATE_EN ( BIT(1) ) +#define BIT_CA7_CORE_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_HOLDING_PEN */ +#define BITS_HOLDING_PEN(_x_) ( (_x_) << 0 ) + +/* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C0 */ +#define BITS_JMP_ADDR_CA7_C0(_x_) ( (_x_) << 0 ) + +/* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C1 */ +#define BITS_JMP_ADDR_CA7_C1(_x_) ( (_x_) << 0 ) + +/* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C2 */ +#define BITS_JMP_ADDR_CA7_C2(_x_) ( (_x_) << 0 ) + +/* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C3 */ +#define BITS_JMP_ADDR_CA7_C3(_x_) ( (_x_) << 0 ) + +/* bits definitions for register REG_AP_AHB_CA7_C0_PU_LOCK */ +#define BIT_CA7_C0_PU_LOCK ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_CA7_C1_PU_LOCK */ +#define BIT_CA7_C1_PU_LOCK ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_CA7_C2_PU_LOCK */ +#define BIT_CA7_C2_PU_LOCK ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_CA7_C3_PU_LOCK */ +#define BIT_CA7_C3_PU_LOCK ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_CA7_CKG_DIV_CFG */ +#define BITS_CA7_DBG_CKG_DIV(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)) ) +#define BITS_CA7_AXI_CKG_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CA7_MCU_CKG_DIV(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) + +/* bits definitions for register REG_AP_AHB_MCU_PAUSE */ +#define BIT_DMA_ACT_LIGHT_EN ( BIT(5) ) +#define BIT_MCU_SLEEP_FOLLOW_CA7_EN ( BIT(4) ) +#define BIT_MCU_LIGHT_SLEEP_EN ( BIT(3) ) +#define BIT_MCU_DEEP_SLEEP_EN ( BIT(2) ) +#define BIT_MCU_SYS_SLEEP_EN ( BIT(1) ) +#define BIT_MCU_CORE_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_MISC_CKG_EN */ +#define BIT_ASHB_CA7_DBG_VLD ( BIT(9) ) +#define BIT_ASHB_CA7_DBG_EN ( BIT(8) ) +#define BIT_DISP_TMC_CKG_EN ( BIT(4) ) +#define BIT_DPHY_REF_CKG_EN ( BIT(1) ) +#define BIT_DPHY_CFG_CKG_EN ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_CA7_C0_AUTO_FORCE_SHUTDOWN_EN */ +#define BIT_CA7_C0_AUTO_FORCE_SHUTDOWN_EN ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_CA7_C1_AUTO_FORCE_SHUTDOWN_EN */ +#define BIT_CA7_C1_AUTO_FORCE_SHUTDOWN_EN ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_CA7_C2_AUTO_FORCE_SHUTDOWN_EN */ +#define BIT_CA7_C2_AUTO_FORCE_SHUTDOWN_EN ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_CA7_C3_AUTO_FORCE_SHUTDOWN_EN */ +#define BIT_CA7_C3_AUTO_FORCE_SHUTDOWN_EN ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_CA7_CKG_SEL_CFG */ +#define BITS_CA7_MCU_CKG_SEL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AP_AHB_MISC_CFG */ +#define BITS_EMMC_SLOT_SEL(_x_) ( (_x_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_SDIO0_SLOT_SEL(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_BUSMON2_CHN_SEL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_BUSMON1_CHN_SEL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_BUSMON0_CHN_SEL(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_SDIO2_SLOT_SEL(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_SDIO1_SLOT_SEL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_AHB_AP_MAIN_MTX_HPROT_CFG */ +#define BITS_HPROT_NFC(_x_) ( (_x_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_HPROT_EMMC(_x_) ( (_x_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_HPROT_SDIO2(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_HPROT_SDIO1(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_HPROT_SDIO0(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_HPROT_DMAW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_HPROT_DMAR(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AP_AHB_CA7_STANDBY_STATUS */ +#define BIT_CA7_STANDBYWFIL2 ( BIT(12) ) +#define BITS_CA7_ETMSTANDBYWFX(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CA7_STANDBYWFE(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_CA7_STANDBYWFI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AP_AHB_NANC_CLK_CFG */ +#define BITS_CLK_NANDC_SEL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)) ) +#define BITS_CLK_NANDC2X_DIV(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)) ) +#define BITS_CLK_NANDC2X_SEL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_AHB_LVDS_CFG */ +#define BITS_LVDS_TXCLKDATA(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_LVDS_TXCOM(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_LVDS_TXSLEW(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_LVDS_TXSW(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_LVDS_TXRERSER(_x_) ( (_x_) << 3 & (BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_LVDS_PRE_EMP(_x_) ( (_x_) << 1 & (BIT(1)|BIT(2)) ) +#define BIT_LVDS_TXPD ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_LVDS_PLL_CFG0 */ +#define BIT_LVDS_PLL_LOCK_DET ( BIT(31) ) +#define BITS_LVDS_PLL_REFIN(_x_) ( (_x_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_LVDS_PLL_LPF(_x_) ( (_x_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BIT_LVDS_PLL_DIV_S ( BIT(18) ) +#define BITS_LVDS_PLL_IBIAS(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_LVDS_PLLN(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AP_AHB_LVDS_PLL_CFG1 */ +#define BITS_LVDS_PLL_KINT(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_LVDS_PLL_RSV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_LVDS_PLL_MOD_EN ( BIT(7) ) +#define BIT_LVDS_PLL_SDM_EN ( BIT(6) ) +#define BITS_LVDS_PLL_NINT(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_AP_AHB_AP_QOS_CFG */ +#define BITS_QOS_R_TMC(_x_) ( (_x_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_QOS_W_TMC(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_QOS_R_DISPC(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_QOS_W_DISPC(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AP_AHB_OTG_PHY_TUNE */ +#define BIT_OTG_TXPREEMPPULSETUNE ( BIT(20) ) +#define BITS_OTG_TXRESTUNE(_x_) ( (_x_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_OTG_TXHSXVTUNE(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_OTG_TXVREFTUNE(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_OTG_TXPREEMPAMPTUNE(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_OTG_TXRISETUNE(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_OTG_TXFSLSTUNE(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_OTG_SQRXTUNE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AP_AHB_OTG_PHY_TEST */ +#define BIT_OTG_ATERESET ( BIT(31) ) +#define BIT_OTG_VBUS_VALID_EXT_SEL ( BIT(26) ) +#define BIT_OTG_VBUS_VALID_EXT ( BIT(25) ) +#define BIT_OTG_OTGDISABLE ( BIT(24) ) +#define BIT_OTG_TESTBURNIN ( BIT(21) ) +#define BIT_OTG_LOOPBACKENB ( BIT(20) ) +#define BITS_OTG_TESTDATAOUT(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_OTG_VATESTENB(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BIT_OTG_TESTCLK ( BIT(13) ) +#define BIT_OTG_TESTDATAOUTSEL ( BIT(12) ) +#define BITS_OTG_TESTADDR(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_OTG_TESTDATAIN(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_AP_AHB_OTG_PHY_CTRL */ +#define BITS_OTG_SS_SCALEDOWNMODE(_x_) ( (_x_) << 25 & (BIT(25)|BIT(26)) ) +#define BIT_OTG_TXBITSTUFFENH ( BIT(23) ) +#define BIT_OTG_TXBITSTUFFEN ( BIT(22) ) +#define BIT_OTG_DMPULLDOWN ( BIT(21) ) +#define BIT_OTG_DPPULLDOWN ( BIT(20) ) +#define BIT_OTG_DMPULLUP ( BIT(9) ) +#define BIT_OTG_COMMONONN ( BIT(8) ) +#define BITS_OTG_REFCLKSEL(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_OTG_FSEL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AP_AHB_HSIC_PHY_TUNE */ +#define BITS_HSIC_REFCLK_DIV(_x_) ( (_x_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) ) +#define BIT_HSIC_TXPREEMPPULSETUNE ( BIT(20) ) +#define BITS_HSIC_TXRESTUNE(_x_) ( (_x_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_HSIC_TXHSXVTUNE(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_HSIC_TXVREFTUNE(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_HSIC_TXPREEMPAMPTUNE(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_HSIC_TXRISETUNE(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_HSIC_TXFSLSTUNE(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_HSIC_SQRXTUNE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AP_AHB_HSIC_PHY_TEST */ +#define BIT_HSIC_ATERESET ( BIT(31) ) +#define BIT_HSIC_VBUS_VALID_EXT_SEL ( BIT(26) ) +#define BIT_HSIC_VBUS_VALID_EXT ( BIT(25) ) +#define BIT_HSIC_OTGDISABLE ( BIT(24) ) +#define BIT_HSIC_TESTBURNIN ( BIT(21) ) +#define BIT_HSIC_LOOPBACKENB ( BIT(20) ) +#define BITS_HSIC_TESTDATAOUT(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_HSIC_VATESTENB(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BIT_HSIC_TESTCLK ( BIT(13) ) +#define BIT_HSIC_TESTDATAOUTSEL ( BIT(12) ) +#define BITS_HSIC_TESTADDR(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_HSIC_TESTDATAIN(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_AP_AHB_HSIC_PHY_CTRL */ +#define BITS_HSIC_SS_SCALEDOWNMODE(_x_) ( (_x_) << 25 & (BIT(25)|BIT(26)) ) +#define BIT_HSIC_TXBITSTUFFENH ( BIT(23) ) +#define BIT_HSIC_TXBITSTUFFEN ( BIT(22) ) +#define BIT_HSIC_DMPULLDOWN ( BIT(21) ) +#define BIT_HSIC_DPPULLDOWN ( BIT(20) ) +#define BIT_HSIC_IF_MODE ( BIT(16) ) +#define BIT_IF_SELECT_HSIC ( BIT(13) ) +#define BIT_HSIC_DBNCE_FLTR_BYPASS ( BIT(12) ) +#define BIT_HSIC_DMPULLUP ( BIT(9) ) +#define BIT_HSIC_COMMONONN ( BIT(8) ) +#define BITS_HSIC_REFCLKSEL(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_HSIC_FSEL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AP_AHB_ZIP_MTX_QOS_CFG */ +#define BITS_ZIPMTX_S0_ARQOS(_x_) ( (_x_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_ZIPMTX_S0_AWQOS(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_ZIPDEC_ARQOS(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_ZIPDEC_AWQOS(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_ZIPENC_ARQOS(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_ZIPENC_AWQOS(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AP_AHB_CHIP_ID */ +#define BITS_CHIP_ID(_x_) ( (_x_) << 0 ) + +/* vars definitions for controller REGS_AP_AHB */ + +#endif /* __REGS_AP_AHB_H__ */ diff --git a/include/soc/sprd/chip_x20l/__regs_ap_apb.h b/include/soc/sprd/chip_x20l/__regs_ap_apb.h new file mode 100755 index 00000000..355cbe13 --- /dev/null +++ b/include/soc/sprd/chip_x20l/__regs_ap_apb.h @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_AP_APB_HEADFILE_H__ +#define __H_REGS_AP_APB_HEADFILE_H__ __FILE__ + +#define REGS_AP_APB + +/* registers definitions for AP_APB */ +#define REG_AP_APB_APB_EB SCI_ADDR(REGS_AP_APB_BASE, 0x0000) +#define REG_AP_APB_APB_RST SCI_ADDR(REGS_AP_APB_BASE, 0x0004) +#define REG_AP_APB_APB_MISC_CTRL SCI_ADDR(REGS_AP_APB_BASE, 0x0008) + + + +/* bits definitions for register REG_AP_APB_APB_EB */ +#define BIT_INTC3_EB ( BIT(22) ) +#define BIT_INTC2_EB ( BIT(21) ) +#define BIT_INTC1_EB ( BIT(20) ) +#define BIT_INTC0_EB ( BIT(19) ) +#define BIT_AP_CKG_EB ( BIT(18) ) +#define BIT_UART4_EB ( BIT(17) ) +#define BIT_UART3_EB ( BIT(16) ) +#define BIT_UART2_EB ( BIT(15) ) +#define BIT_UART1_EB ( BIT(14) ) +#define BIT_UART0_EB ( BIT(13) ) +#define BIT_I2C4_EB ( BIT(12) ) +#define BIT_I2C3_EB ( BIT(11) ) +#define BIT_I2C2_EB ( BIT(10) ) +#define BIT_I2C1_EB ( BIT(9) ) +#define BIT_I2C0_EB ( BIT(8) ) +#define BIT_SPI2_EB ( BIT(7) ) +#define BIT_SPI1_EB ( BIT(6) ) +#define BIT_SPI0_EB ( BIT(5) ) +#define BIT_IIS3_EB ( BIT(4) ) +#define BIT_IIS2_EB ( BIT(3) ) +#define BIT_IIS1_EB ( BIT(2) ) +#define BIT_IIS0_EB ( BIT(1) ) +#define BIT_SIM0_EB ( BIT(0) ) + +/* bits definitions for register REG_AP_APB_APB_RST */ +#define BIT_INTC3_SOFT_RST ( BIT(22) ) +#define BIT_INTC2_SOFT_RST ( BIT(21) ) +#define BIT_INTC1_SOFT_RST ( BIT(20) ) +#define BIT_INTC0_SOFT_RST ( BIT(19) ) +#define BIT_AP_CKG_SOFT_RST ( BIT(18) ) +#define BIT_UART4_SOFT_RST ( BIT(17) ) +#define BIT_UART3_SOFT_RST ( BIT(16) ) +#define BIT_UART2_SOFT_RST ( BIT(15) ) +#define BIT_UART1_SOFT_RST ( BIT(14) ) +#define BIT_UART0_SOFT_RST ( BIT(13) ) +#define BIT_I2C4_SOFT_RST ( BIT(12) ) +#define BIT_I2C3_SOFT_RST ( BIT(11) ) +#define BIT_I2C2_SOFT_RST ( BIT(10) ) +#define BIT_I2C1_SOFT_RST ( BIT(9) ) +#define BIT_I2C0_SOFT_RST ( BIT(8) ) +#define BIT_SPI2_SOFT_RST ( BIT(7) ) +#define BIT_SPI1_SOFT_RST ( BIT(6) ) +#define BIT_SPI0_SOFT_RST ( BIT(5) ) +#define BIT_IIS3_SOFT_RST ( BIT(4) ) +#define BIT_IIS2_SOFT_RST ( BIT(3) ) +#define BIT_IIS1_SOFT_RST ( BIT(2) ) +#define BIT_IIS0_SOFT_RST ( BIT(1) ) +#define BIT_SIM0_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_AP_APB_APB_MISC_CTRL */ +#define BIT_SIM_CLK_POLARITY ( BIT(1) ) +#define BIT_FMARK_POLARITY_INV ( BIT(0) ) + +#endif diff --git a/include/soc/sprd/chip_x20l/__regs_ap_clk.h b/include/soc/sprd/chip_x20l/__regs_ap_clk.h new file mode 100644 index 00000000..f3efe02f --- /dev/null +++ b/include/soc/sprd/chip_x20l/__regs_ap_clk.h @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __REGS_AP_CLK_H__ +#define __REGS_AP_CLK_H__ + +#define REGS_AP_CLK + +/* registers definitions for controller REGS_AP_CLK */ +#define REG_AP_CLK_AP_AHB_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0020) +#define REG_AP_CLK_AP_APB_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0024) +#define REG_AP_CLK_GSP_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0028) +#define REG_AP_CLK_DISPC0_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x002c) +#define REG_AP_CLK_DISPC0_DBI_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0030) +#define REG_AP_CLK_DISPC0_DPI_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0034) +#define REG_AP_CLK_NANDC_ECC_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0038) +#define REG_AP_CLK_SDIO0_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x003c) +#define REG_AP_CLK_SDIO1_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0040) +#define REG_AP_CLK_SDIO2_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0044) +#define REG_AP_CLK_EMMC_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0048) +#define REG_AP_CLK_OTG_REF_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x004c) +#define REG_AP_CLK_HSIC_REF_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0050) +#define REG_AP_CLK_UART0_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0054) +#define REG_AP_CLK_UART1_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0058) +#define REG_AP_CLK_UART2_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x005c) +#define REG_AP_CLK_UART3_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0060) +#define REG_AP_CLK_UART4_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0064) +#define REG_AP_CLK_I2C0_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0068) +#define REG_AP_CLK_I2C1_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x006c) +#define REG_AP_CLK_I2C2_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0070) +#define REG_AP_CLK_I2C3_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0074) +#define REG_AP_CLK_I2C4_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0078) +#define REG_AP_CLK_SPI0_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x007c) +#define REG_AP_CLK_SPI1_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0080) +#define REG_AP_CLK_SPI2_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0084) +#define REG_AP_CLK_IIS0_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0088) +#define REG_AP_CLK_IIS1_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x008c) +#define REG_AP_CLK_IIS2_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0090) +#define REG_AP_CLK_IIS3_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0094) +#define REG_AP_CLK_ZIPENC_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0098) +#define REG_AP_CLK_ZIPDEC_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x009c) + + +/* vars definitions for controller REGS_AP_CLK */ + +/* vars definitions for REG_AP_CLK_AP_AHB_CFG */ +#define AP_AHB_CLK_SEL_SHIFT (0) +#define AP_AHB_CLK_SEL_MASK (0x3 << AP_AHB_CLK_SEL_SHIFT) + +#define AP_APB_CLK_SEL_SHIFT (0) +#define AP_APB_CLK_SEL_MASK (0x3 << AP_AHB_CLK_SEL_SHIFT) + +#endif //__REGS_AP_CLK_H__ diff --git a/include/soc/sprd/chip_x20l/__regs_arm7_ahb_rf.h b/include/soc/sprd/chip_x20l/__regs_arm7_ahb_rf.h new file mode 100755 index 00000000..70d20476 --- /dev/null +++ b/include/soc/sprd/chip_x20l/__regs_arm7_ahb_rf.h @@ -0,0 +1,110 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_ARM7_AHB_RF_HEADFILE_H__ +#define __H_REGS_ARM7_AHB_RF_HEADFILE_H__ __FILE__ + +#define REGS_ARM7_AHB_RF + +/* registers definitions for ARM7_AHB_RF */ +#define REG_ARM7_AHB_RF_ARM7_EB SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0000) +#define REG_ARM7_AHB_RF_ARM7_SOFT_RST SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0004) +#define REG_ARM7_AHB_RF_AHB_PAUSE SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0008) +#define REG_ARM7_AHB_RF_ARM7_SLP_CTL SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x000C) +#define REG_ARM7_AHB_RF_AP_PROT_CTL SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0030) +#define REG_ARM7_AHB_RF_AP_COMM_CTL SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0034) +#define REG_ARM7_AHB_RF_CA7_BOOT_VEC SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0038) +#define REG_ARM7_AHB_RF_CA7_SDISABLE SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x003C) +#define REG_ARM7_AHB_RF_ARM7_RES_REG SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0044) + + + +/* bits definitions for register REG_ARM7_AHB_RF_ARM7_EB */ +#define BIT_ARM7_GPIO_EB ( BIT(10) ) +#define BIT_ARM7_UART_EB ( BIT(9) ) +#define BIT_ARM7_TMR_EB ( BIT(8) ) +#define BIT_ARM7_SYST_EB ( BIT(7) ) +#define BIT_ARM7_WDG_EB ( BIT(6) ) +#define BIT_ARM7_EIC_EB ( BIT(5) ) +#define BIT_ARM7_INTC_EB ( BIT(4) ) +#define BIT_ARM7_EFUSE_EB ( BIT(3) ) +#define BIT_ARM7_IMC_EB ( BIT(2) ) +#define BIT_ARM7_TIC_EB ( BIT(1) ) +#define BIT_ARM7_DMA_EB ( BIT(0) ) + +/* bits definitions for register REG_ARM7_AHB_RF_ARM7_SOFT_RST */ +#define BIT_ARM7_GPIO_SOFT_RST ( BIT(10) ) +#define BIT_ARM7_UART_SOFT_RST ( BIT(9) ) +#define BIT_ARM7_TMR_SOFT_RST ( BIT(8) ) +#define BIT_ARM7_SYST_SOFT_RST ( BIT(7) ) +#define BIT_ARM7_WDG_SOFT_RST ( BIT(6) ) +#define BIT_ARM7_EIC_SOFT_RST ( BIT(5) ) +#define BIT_ARM7_INTC_SOFT_RST ( BIT(4) ) +#define BIT_ARM7_EFUSE_SOFT_RST ( BIT(3) ) +#define BIT_ARM7_IMC_SOFT_RST ( BIT(2) ) +#define BIT_ARM7_TIC_SOFT_RST ( BIT(1) ) +#define BIT_ARM7_ARCH_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_ARM7_AHB_RF_AHB_PAUSE */ +#define BIT_ARM7_DEEP_SLEEP_EN ( BIT(2) ) +#define BIT_ARM7_SYS_SLEEP_EN ( BIT(1) ) +#define BIT_ARM7_CORE_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_ARM7_AHB_RF_ARM7_SLP_CTL */ +#define BIT_ARM7_SYS_AUTO_GATE_EN ( BIT(2) ) +#define BIT_ARM7_AHB_AUTO_GATE_EN ( BIT(1) ) +#define BIT_ARM7_CORE_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_ARM7_AHB_RF_AP_PROT_CTL */ +#define BIT_ARM7_CSSYS_SPNIDEN ( BIT(22) ) +#define BIT_ARM7_CSSYS_SPIDEN ( BIT(21) ) +#define BIT_ARM7_CSSYS_NIDEN ( BIT(20) ) +#define BIT_ARM7_CSSYS_DBGEN ( BIT(19) ) +#define BIT_ARM7_CA7_DAP_DBGEN ( BIT(18) ) +#define BIT_ARM7_CA7_DAP_SPIDEN ( BIT(17) ) +#define BIT_ARM7_CA7_DAP_DEVICEEN ( BIT(16) ) +#define BITS_ARM7_CA7_SPNIDEN(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_ARM7_CA7_SPIDEN(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_ARM7_CA7_NIDEN(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_ARM7_CA7_DBGEN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_ARM7_AHB_RF_AP_COMM_CTL */ +#define BIT_ARM7_BOOT_AP_EN ( BIT(21) ) +#define BITS_ARM7_CA7_L1RSTDISABLE(_X_) ( (_X_) << 17 & (BIT(17)|BIT(18)|BIT(19)|BIT(20)) ) +#define BIT_ARM7_CA7_L2RSTDISABLE ( BIT(16) ) +#define BITS_ARM7_CA7_CFGTE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_ARM7_CA7_VINITHI(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_ARM7_AP_AA64NAA32(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_ARM7_AHB_RF_CA7_BOOT_VEC */ +#define BITS_ARM7_BOOT_AP_VEC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_ARM7_AHB_RF_CA7_SDISABLE */ +#define BIT_ARM7_CA7_CFGSDISABLE ( BIT(4) ) +#define BITS_ARM7_CA7_CP15SDISABLE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_ARM7_AHB_RF_ARM7_RES_REG */ +#define BITS_ARM7_RES_REG_H(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ARM7_RES_REG_L(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) + +#endif diff --git a/include/soc/sprd/chip_x20l/__regs_avs_apb_rf.h b/include/soc/sprd/chip_x20l/__regs_avs_apb_rf.h new file mode 100644 index 00000000..aef34590 --- /dev/null +++ b/include/soc/sprd/chip_x20l/__regs_avs_apb_rf.h @@ -0,0 +1,108 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_AVS_APB_RF_HEADFILE_H__ +#define __H_REGS_AVS_APB_RF_HEADFILE_H__ __FILE__ + +#define REGS_AVS_APB_RF + +/* registers definitions for AVS_APB_RF */ +#define REG_AVS_APB_RF_AVS_TUNE_LMT_CFG SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0000) +#define REG_AVS_APB_RF_AVS_TUNE_STATUS SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0004) +#define REG_AVS_APB_RF_AVS_CFG SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0008) +#define REG_AVS_APB_RF_AVS_TUNE_STEP_CFG SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x000C) +#define REG_AVS_APB_RF_AVS_WAIT_CFG SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0010) +#define REG_AVS_APB_RF_AVS_INT_CFG SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0014) +#define REG_AVS_APB_RF_AVS_START_SINGLE_ACT SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0018) +#define REG_AVS_APB_RF_AVS_START_REPEAT_ACT SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x001C) +#define REG_AVS_APB_RF_AVS_HPM_EN SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0020) +#define REG_AVS_APB_RF_AVS_HPM_RPT_ANLS SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0024) +#define REG_AVS_APB_RF_AVS_HPM_RPT_VLD_STATUS_0 SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0028) +#define REG_AVS_APB_RF_AVS_HPM_RPT_VLD_STATUS_1 SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x002C) +#define REG_AVS_APB_RF_FSM_STS SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0030) + + + +/* bits definitions for register REG_AVS_APB_RF_AVS_TUNE_LMT_CFG */ +#define BITS_VOLT_TUNE_VAL_MAX(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_VOLT_TUNE_VAL_MIN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_TUNE_STATUS */ +#define BITS_VOLT_TUNE_VAL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_VOLT_OBS_VAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_CFG */ +#define BIT_HPM3_RPT_CHKSUM_ERR_EN ( BIT(19) ) +#define BIT_HPM2_RPT_CHKSUM_ERR_EN ( BIT(18) ) +#define BIT_HPM1_RPT_CHKSUM_ERR_EN ( BIT(17) ) +#define BIT_HPM0_RPT_CHKSUM_ERR_EN ( BIT(16) ) +#define BIT_PAUSE_OCCUR_ERR_EN ( BIT(8) ) +#define BIT_VOLT_TUNE_FORBID_EN ( BIT(4) ) +#define BIT_VOLT_OBS_FORBID_EN ( BIT(0) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_TUNE_STEP_CFG */ +#define BITS_VOLT_TUNE_DOWN_STEP(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) ) +#define BITS_VOLT_TUNE_UP_STEP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_WAIT_CFG */ +#define BITS_RND_INTVAL_WAIT_NUM(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_VOLT_STB_WAIT_NUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_INT_CFG */ +#define BIT_AVS_TUNE_DONE_INT_MASK_STATUS ( BIT(13) ) +#define BIT_AVS_TUNE_ERR_INT_MASK_STATUS ( BIT(12) ) +#define BIT_AVS_TUNE_DONE_INT_RAW_STATUS ( BIT(9) ) +#define BIT_AVS_TUNE_ERR_INT_RAW_STATUS ( BIT(8) ) +#define BIT_AVS_TUNE_DONE_INT_CLR ( BIT(5) ) +#define BIT_AVS_TUNE_ERR_INT_CLR ( BIT(4) ) +#define BIT_AVS_TUNE_DONE_INT_EN ( BIT(1) ) +#define BIT_AVS_TUNE_ERR_INT_EN ( BIT(0) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_START_SINGLE_ACT */ +#define BIT_AVS_START_SINGLE_ACT ( BIT(0) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_START_REPEAT_ACT */ +#define BIT_AVS_START_REPEAT_ACT ( BIT(0) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_HPM_EN */ +#define BIT_HPM3_EN ( BIT(3) ) +#define BIT_HPM2_EN ( BIT(2) ) +#define BIT_HPM1_EN ( BIT(1) ) +#define BIT_HPM0_EN ( BIT(0) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_HPM_RPT_ANLS */ +#define BITS_HPM_RPT_TUNE_DWN_MARK(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_HPM_RPT_TUNE_UP_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_HPM_RPT_VLD_STATUS_0 */ +#define BITS_HPM1_RPT_VLD(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_HPM0_RPT_VLD(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_HPM_RPT_VLD_STATUS_1 */ +#define BITS_HPM3_RPT_VLD(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_HPM2_RPT_VLD(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AVS_APB_RF_FSM_STS */ +#define BITS_AVS_FSM_STS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +#endif diff --git a/include/soc/sprd/chip_x20l/__regs_cortex_ahb_rf.h b/include/soc/sprd/chip_x20l/__regs_cortex_ahb_rf.h new file mode 100755 index 00000000..e9d8f3c0 --- /dev/null +++ b/include/soc/sprd/chip_x20l/__regs_cortex_ahb_rf.h @@ -0,0 +1,203 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_CORTEX_AHB_RF_HEADFILE_H__ +#define __H_REGS_CORTEX_AHB_RF_HEADFILE_H__ __FILE__ + +#define REGS_CORTEX_AHB_RF + +/* registers definitions for CORTEX_AHB_RF */ +#define REG_CORTEX_AHB_RF_CLK_CORTEX_AXI_CTRL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0000)/*CORTEX_AXI clock control*/ +#define REG_CORTEX_AHB_RF_CLK_CORTEX_AHB_CTRL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0004)/*CORTEX_AHB clock control*/ +#define REG_CORTEX_AHB_RF_CLK_CORTEX_APB_CTRL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0008)/*CORTEX_APB clock control*/ +#define REG_CORTEX_AHB_RF_CLK_SEC0_CTRL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x000C)/*SEC0 clock control*/ +#define REG_CORTEX_AHB_RF_CLK_SEC1_CTRL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0010)/*SEC1 clock control*/ +#define REG_CORTEX_AHB_RF_CA5_CFG SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0030)/* CortexA5 config*/ +#define REG_CORTEX_AHB_RF_AHB_CTRL0 SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0034)/*AHB control 0*/ +#define REG_CORTEX_AHB_RF_AHB_CTRL2 SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x003C)/*AHB control 2*/ +#define REG_CORTEX_AHB_RF_AHB_RST0_STS SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0060)/*AHB software reset*/ +#define REG_CORTEX_AHB_RF_CA5_RST_SET SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0064) +#define REG_CORTEX_AHB_RF_ARCH_EB SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0068) +#define REG_CORTEX_AHB_RF_PTEST_FUNC SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x006C) +#define REG_CORTEX_AHB_RF_AHB_MISC_CTL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0070) +#define REG_CORTEX_AHB_RF_CA5_CTRL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0074)/* Cortex A5 control*/ +#define REG_CORTEX_AHB_RF_AUTO_GATE_CTRL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0078)/*Auto gate control*/ +#define REG_CORTEX_AHB_RF_AHB_PAUSE SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0080)/*AHB sleep control*/ +#define REG_CORTEX_AHB_RF_AHB_SLP_CTL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0084) +#define REG_CORTEX_AHB_RF_AHB_SLP_STS SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0088) +#define REG_CORTEX_AHB_RF_MCU_CLK_CTL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x008C) +#define REG_CORTEX_AHB_RF_RES_REG0 SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x00F4) +#define REG_CORTEX_AHB_RF_CHIP_ID SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0200) + + + +/* bits definitions for register REG_CORTEX_AHB_RF_CLK_CORTEX_AXI_CTRL */ +#define BITS_CLK_CORTEX_AXI_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_CLK_CORTEX_AHB_CTRL */ +#define BITS_CLK_CORTEX_AHB_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_CLK_CORTEX_APB_CTRL */ +#define BITS_CLK_CORTEX_APB_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_CLK_SEC0_CTRL */ +#define BITS_CLK_SEC0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_CLK_SEC1_CTRL */ +#define BITS_CLK_SEC1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_CA5_CFG */ +#define BITS_CA5_DBG_DIV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_CA5_AXI_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CA5_MCU_DIV(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BITS_CA5_MCU_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_AHB_CTRL0 */ +#define BITS_TFT_MST_HPROT(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_PPP1_MST_HPROT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_PPP0_MST_HPROT(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_TFT_EB ( BIT(18) ) +#define BIT_PPP1_EB ( BIT(17) ) +#define BIT_PPP0_EB ( BIT(16) ) +#define BITS_SEC1_MST_HPROT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_SEC0_MST_HPROT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BIT_SEC1_EB ( BIT(5) ) +#define BIT_SEC1_CKG_EN ( BIT(4) ) +#define BIT_SEC0_EB ( BIT(3) ) +#define BIT_SEC0_CKG_EN ( BIT(2) ) +#define BIT_DMA_EB ( BIT(1) ) +#define BIT_DMA_CKG_EN ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_AHB_CTRL2 */ +#define BITS_BUSMON1_CHN_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_AXIBUSMON_CHN_SEL(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_BUSMON0_CHN_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BIT_BUSMON1_EB ( BIT(3) ) +#define BIT_SPINLOCK_EB ( BIT(2) ) +#define BIT_AXIBUSMON_EB ( BIT(1) ) +#define BIT_BUSMON0_EB ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_AHB_RST0_STS */ +#define BIT_TFT_SOFT_RST ( BIT(11) ) +#define BIT_PPP1_SOFT_RST ( BIT(10) ) +#define BIT_PPP0_SOFT_RST ( BIT(9) ) +#define BIT_SEC1_CMD_PARSER_RST ( BIT(8) ) +#define BIT_SEC0_CMD_PARSER_RST ( BIT(7) ) +#define BIT_SPINLOCK_SOFT_RST ( BIT(6) ) +#define BIT_SEC1_SOFT_RST ( BIT(5) ) +#define BIT_SEC0_SOFT_RST ( BIT(4) ) +#define BIT_BUSMON1_SOFT_RST ( BIT(3) ) +#define BIT_AXIBUSMON_SOFT_RST ( BIT(2) ) +#define BIT_BUSMON0_SOFT_RST ( BIT(1) ) +#define BIT_DMA_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_CA5_RST_SET */ +#define BIT_CA5_MTX_SOFT_RST ( BIT(3) ) +#define BIT_CA5_L2_SOFT_RST ( BIT(2) ) +#define BIT_CA5_DBG_SOFT_RST ( BIT(1) ) +#define BIT_CA5_CORE_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_ARCH_EB */ +#define BIT_AHB_ARCH_EB ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_PTEST_FUNC */ +#define BIT_PTEST_FUNC_ATSPEED_SEL ( BIT(2) ) +#define BIT_PTEST_FUNC_MODE ( BIT(1) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_AHB_MISC_CTL */ +#define BITS_DMA_W_PROT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMA_R_PROT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BIT_LCP2PUB_ACCESS_EN ( BIT(4) ) +#define BITS_MCU_SHM_CTRL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_CA5_CTRL */ +#define BIT_CA5_WDRESET_EN ( BIT(18) ) +#define BIT_CA5_TS_EN ( BIT(17) ) +#define BIT_CA5_CFGSDISABLE ( BIT(13) ) +#define BITS_CA5_CLK_AXI_DIV(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)) ) +#define BIT_CA5_CLK_DBG_EN_SEL ( BIT(10) ) +#define BIT_CA5_CLK_DBG_EN ( BIT(9) ) +#define BIT_CA5_DBGEN ( BIT(8) ) +#define BIT_CA5_NIDEN ( BIT(7) ) +#define BIT_CA5_SPIDEN ( BIT(6) ) +#define BIT_CA5_SPNIDEN ( BIT(5) ) +#define BIT_CA5_CP15DISABLE ( BIT(4) ) +#define BIT_CA5_TEINIT ( BIT(3) ) +#define BIT_CA5_L1RSTDISABLE ( BIT(2) ) +#define BIT_CA5_L2CFGEND ( BIT(1) ) +#define BIT_CA5_L2SPNIDEN ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_AUTO_GATE_CTRL */ +#define BIT_CORTEX_AHB_AUTO_GATE_EN ( BIT(5) ) +#define BIT_CA5_DBG_FORCE_SLEEP ( BIT(4) ) +#define BIT_CA5_DBG_AUTO_GATE_EN ( BIT(3) ) +#define BIT_CA5_CORE_AUTO_GATE_EN ( BIT(2) ) +#define BIT_LCPX_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_AHB_PAUSE */ +#define BIT_EMC_LIGHT_SLEEP_EN ( BIT(25) ) +#define BIT_EMC_DEEP_SLEEP_EN ( BIT(24) ) +#define BIT_APB_SLEEP_EN ( BIT(18) ) +#define BIT_APB_PERI_FRC_SLP ( BIT(17) ) +#define BIT_APB_PERI_FRC_ON ( BIT(16) ) +#define BIT_MCU_FORCE_DEEP_SLEEP ( BIT(15) ) +#define BIT_DMA_LSLP_EN ( BIT(4) ) +#define BIT_MCU_LIGHT_SLEEP_EN ( BIT(3) ) +#define BIT_MCU_DEEP_SLEEP_EN ( BIT(2) ) +#define BIT_MCU_SYS_SLEEP_EN ( BIT(1) ) +#define BIT_MCU_CORE_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_AHB_SLP_CTL */ +#define BIT_ARM_DAHB_SLEEP_EN ( BIT(4) ) +#define BIT_MCUMTX_AUTO_GATE_EN ( BIT(3) ) +#define BIT_MCU_AUTO_GATE_EN ( BIT(2) ) +#define BIT_AHB_AUTO_GATE_EN ( BIT(1) ) +#define BIT_ARM_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_AHB_SLP_STS */ +#define BIT_CHIP_SLP_ARM_CLR ( BIT(5) ) +#define BIT_CHIP_SLEEP_REC_ARM ( BIT(4) ) +#define BIT_APB_PERI_SLEEP ( BIT(3) ) +#define BIT_DMA_BUSY ( BIT(1) ) +#define BIT_EMC_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_MCU_CLK_CTL */ +#define BIT_CLK_LCP2LDSP_BRG_EN ( BIT(24) ) +#define BIT_CLK_LCP2PUB_BRG_EN ( BIT(23) ) +#define BIT_CLK_LCP2CP0_BRG_EN ( BIT(22) ) +#define BIT_CLK_CP_DBG_SEL ( BIT(21) ) +#define BIT_CLK_MCU_DBG_SEL ( BIT(20) ) +#define BITS_CLK_COM_DBG_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_CLK_SYS_DBG_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_CLK_AHB_DIV(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_CLK_MCU_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_APB_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CLK_MCU_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_RES_REG0 */ +#define BITS_RES_REG0(_X_) (_X_) + +/* bits definitions for register REG_CORTEX_AHB_RF_CHIP_ID */ +#define BITS_CHIP_ID(_X_) (_X_) + +#endif diff --git a/include/soc/sprd/chip_x20l/__regs_cortex_glb.h b/include/soc/sprd/chip_x20l/__regs_cortex_glb.h new file mode 100755 index 00000000..3f06ccbb --- /dev/null +++ b/include/soc/sprd/chip_x20l/__regs_cortex_glb.h @@ -0,0 +1,138 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_CORTEX_GLB_HEADFILE_H__ +#define __H_REGS_CORTEX_GLB_HEADFILE_H__ __FILE__ + +#define REGS_CORTEX_GLB + +/* registers definitions for CORTEX_GLB */ +#define REG_CORTEX_GLB_APB_EB0_STS SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0008) +#define REG_CORTEX_GLB_APB_RST0_STS SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0014) +#define REG_CORTEX_GLB_APB_MCU_RST SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0018) +#define REG_CORTEX_GLB_APB_CLK_SEL0 SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x001C) +#define REG_CORTEX_GLB_APB_CLK_SEL1 SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0020) +#define REG_CORTEX_GLB_APB_ARCH_EB SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0024) +#define REG_CORTEX_GLB_APB_MISC_CTL0 SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0028) +#define REG_CORTEX_GLB_APB_MISC_CTL1 SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x002C) +#define REG_CORTEX_GLB_APB_CLK_SEL2 SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0030) +#define REG_CORTEX_GLB_APB_BUS_CTL0 SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0058) +#define REG_CORTEX_GLB_APB_MEM_LP_CTRL0 SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x005c) +#define REG_CORTEX_GLB_APB_MEM_LP_CTRL1 SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0060) +#define REG_CORTEX_GLB_APB_DSP_INT_CLR SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0074) +#define REG_CORTEX_GLB_APB_MISC_INT_STS SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0078) +#define REG_CORTEX_GLB_APB_HWRST SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0080) +#define REG_CORTEX_GLB_APB_ARM_BOOT_ADDR SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0084) + + + +/* bits definitions for register REG_CORTEX_GLB_APB_EB0_STS */ +#define BIT_EIC_RTC_EB ( BIT(19) ) +#define BIT_EIC_EB ( BIT(18) ) +#define BIT_RFFE_EB ( BIT(17) ) +#define BIT_EPT_EB ( BIT(16) ) +#define BIT_GPIO_EB ( BIT(15) ) +#define BIT_TMR_RTC_EB ( BIT(14) ) +#define BIT_TMR_EB ( BIT(13) ) +#define BIT_SYSTMR_RTC_EB ( BIT(12) ) +#define BIT_SYSTMR_EB ( BIT(11) ) +#define BIT_IIS0_EB ( BIT(7) ) +#define BIT_SIM2_EB ( BIT(6) ) +#define BIT_SIM1_EB ( BIT(5) ) +#define BIT_SIM0_EB ( BIT(4) ) +#define BIT_UART0_EB ( BIT(2) ) +#define BIT_WDG_RTC_EB ( BIT(1) ) +#define BIT_WDG_EB ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_RST0_STS */ +#define BIT_EIC_SOFT_RST ( BIT(16) ) +#define BIT_RFFE_SOFT_RST ( BIT(15) ) +#define BIT_MCU_DSP_RST ( BIT(14) ) +#define BIT_EPT_SOFT_RST ( BIT(13) ) +#define BIT_GPIO_SOFT_RST ( BIT(12) ) +#define BIT_TMR_SOFT_RST ( BIT(11) ) +#define BIT_SYSTMR_SOFT_RST ( BIT(10) ) +#define BIT_IIS0_SOFT_RST ( BIT(6) ) +#define BIT_SIM2_SOFT_RST ( BIT(5) ) +#define BIT_SIM1_SOFT_RST ( BIT(4) ) +#define BIT_SIM0_SOFT_RST ( BIT(3) ) +#define BIT_UART0_SOFT_RST ( BIT(1) ) +#define BIT_WDG_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_MCU_RST */ +#define BIT_MCU_SOFT_RST_SET ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_CLK_SEL0 */ +#define BITS_CLK_UART0_DIV(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)) ) +#define BITS_CLK_UART0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_CLK_SEL1 */ +#define BIT_CLK_IIS0_PAD_SEL ( BIT(8) ) +#define BITS_CLK_IIS0_DIV(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_CLK_IIS0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_ARCH_EB */ +#define BIT_RTC_ARCH_EB ( BIT(1) ) +#define BIT_APB_ARCH_EB ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_MISC_CTL0 */ +#define BIT_ALL_CLK_EN ( BIT(28) ) +#define BIT_DMA_LSLP_EN ( BIT(27) ) +#define BIT_WAKEUP_XTL_EN_3G ( BIT(26) ) +#define BIT_WAKEUP_XTL_EN_2G ( BIT(25) ) +#define BIT_ARM_JTAG_EN ( BIT(24) ) +#define BITS_ARM_FRC_STOP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_MISC_CTL1 */ +#define BITS_BUFON_CTRL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_SIM2_CLK_POLARITY ( BIT(3) ) +#define BIT_SIM1_CLK_POLARITY ( BIT(2) ) +#define BIT_SIM0_CLK_POLARITY ( BIT(1) ) +#define BIT_ROM_CLK_EN ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_CLK_SEL2 */ + +/* bits definitions for register REG_CORTEX_GLB_APB_BUS_CTL0 */ +#define BIT_RFFE_CTRL_SEL ( BIT(5) ) +#define BIT_IIS0_CTRL_SEL ( BIT(2) ) +#define BIT_UART0_CTRL_SEL ( BIT(1) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_MEM_LP_CTRL0 */ +#define BITS_APB_MEM_LP_CTRL0(_X_) (_X_) + +/* bits definitions for register REG_CORTEX_GLB_APB_MEM_LP_CTRL1 */ +#define BITS_APB_MEM_LP_CTRL1(_X_) (_X_) + +/* bits definitions for register REG_CORTEX_GLB_APB_DSP_INT_CLR */ +#define BIT_RFT_INT_CLR ( BIT(2) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_MISC_INT_STS */ +#define BIT_RFT_INT ( BIT(2) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_HWRST */ +#define BITS_HWRST_REG(_X_) (_X_) + +/* bits definitions for register REG_CORTEX_GLB_APB_ARM_BOOT_ADDR */ +#define BITS_ARMBOOT_ADDR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +#endif diff --git a/include/soc/sprd/chip_x20l/__regs_cp_ahb_rf.h b/include/soc/sprd/chip_x20l/__regs_cp_ahb_rf.h new file mode 100755 index 00000000..26130206 --- /dev/null +++ b/include/soc/sprd/chip_x20l/__regs_cp_ahb_rf.h @@ -0,0 +1,297 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_CP_AHB_RF_HEADFILE_H__ +#define __H_REGS_CP_AHB_RF_HEADFILE_H__ __FILE__ + +#define REGS_CP_AHB_RF + +/* registers definitions for CP_AHB_RF */ +#define REG_CP_AHB_RF_AHB_EB0_STS SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0008) +#define REG_CP_AHB_RF_AHB_RST0_STS SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0014) +#define REG_CP_AHB_RF_ARCH_EB SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0018) +#define REG_CP_AHB_RF_AHB_REMAP SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x001C) +#define REG_CP_AHB_RF_AHB_MISC_CTL SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0020) +#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL0 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0024) +#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL1 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0028) +#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL2 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x002C) +#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL3 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0030) +#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL4 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0034) +#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL5 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0038) +#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL6 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x003C) +#define REG_CP_AHB_RF_AHB_PAUSE SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0040) +#define REG_CP_AHB_RF_AHB_SLP_CTL SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0044) +#define REG_CP_AHB_RF_AHB_SLP_STS SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0048) +#define REG_CP_AHB_RF_MCU_CLK_CTL SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x004C) +#define REG_CP_AHB_RF_DSP_CTL SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0050) +#define REG_CP_AHB_RF_DSP_BOOT_VECTOR SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0054) +#define REG_CP_AHB_RF_DSP_RST SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0058) +#define REG_CP_AHB_RF_DSP_JTAG_CTL SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x005C) +#define REG_CP_AHB_RF_MCU_C2C_SEMA SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0060) +#define REG_CP_AHB_RF_GGE_DSP_BOOT_VECTOR SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0064) +#define REG_CP_AHB_RF_CHIP_ID SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x01FC) + + + +/* bits definitions for register REG_CP_AHB_RF_AHB_EB0_STS */ +#define BIT_LZMA_EN ( BIT(11) ) +#define BIT_WCDMA_EN5 ( BIT(9) ) +#define BIT_WCDMA_EN4 ( BIT(8) ) +#define BIT_WCDMA_EN3 ( BIT(7) ) +#define BIT_WCDMA_EN2 ( BIT(6) ) +#define BIT_WCDMA_EN1 ( BIT(5) ) +#define BIT_WCDMA_EN0 ( BIT(4) ) +#define BIT_BUSMON2_EN ( BIT(3) ) +#define BIT_BUSMON1_EN ( BIT(2) ) +#define BIT_BUSMON0_EN ( BIT(1) ) +#define BIT_DMA_EN ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_RST0_STS */ +#define BIT_LZMA_SOFT_RST ( BIT(8) ) +#define BIT_WSYS_SOFT_RST ( BIT(6) ) +#define BIT_ARM1_SOFT_RST ( BIT(4) ) +#define BIT_BUSMON2_SOFT_RST ( BIT(3) ) +#define BIT_BUSMON1_SOFT_RST ( BIT(2) ) +#define BIT_BUSMON0_SOFT_RST ( BIT(1) ) +#define BIT_DMA_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_ARCH_EB */ +#define BIT_AHB_ARCH_EB ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_REMAP */ +#define BIT_PTEST_FUNC_ATSPEED_SEL ( BIT(2) ) +#define BIT_PTEST_FUNC_MODE ( BIT(1) ) +#define BIT_REMAP ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_MISC_CTL */ +#define BITS_MCU_GGE_SHM_CTRL(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)) ) +#define BITS_LZMA_M_PROT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMA_W_PROT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMA_R_PROT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_MCU_SHM_CTRL(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BIT_RF_SWT_AUTO_EN ( BIT(1) ) +#define BIT_WCDMA_ASHB_EN ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL0 */ +#define BITS_ARMMTX_M3TOS0_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ARMMTX_M3TOS0_ADJ_EN ( BIT(27) ) +#define BIT_ARMMTX_M3TOS0_RND_EN ( BIT(26) ) +#define BITS_ARMMTX_M3TOS0_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_ARMMTX_M2TOS0_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M2TOS0_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M2TOS0_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M2TOS0_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M1TOS0_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M1TOS0_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M1TOS0_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M1TOS0_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M0TOS0_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M0TOS0_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M0TOS0_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M0TOS0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL1 */ +#define BITS_ARMMTX_M3TOS1_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ARMMTX_M3TOS1_ADJ_EN ( BIT(27) ) +#define BIT_ARMMTX_M3TOS1_RND_EN ( BIT(26) ) +#define BITS_ARMMTX_M3TOS1_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_ARMMTX_M2TOS1_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M2TOS1_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M2TOS1_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M2TOS1_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M1TOS1_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M1TOS1_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M1TOS1_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M1TOS1_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M0TOS1_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M0TOS1_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M0TOS1_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M0TOS1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL2 */ +#define BITS_ARMMTX_M1TOS2_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ARMMTX_M1TOS2_ADJ_EN ( BIT(27) ) +#define BIT_ARMMTX_M1TOS2_RND_EN ( BIT(26) ) +#define BITS_ARMMTX_M1TOS2_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_ARMMTX_M0TOS2_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M0TOS2_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M0TOS2_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M0TOS2_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M5TOS1_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M5TOS1_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M5TOS1_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M5TOS1_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M4TOS1_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M4TOS1_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M4TOS1_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M4TOS1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL3 */ +#define BITS_ARMMTX_M5TOS2_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ARMMTX_M5TOS2_ADJ_EN ( BIT(27) ) +#define BIT_ARMMTX_M5TOS2_RND_EN ( BIT(26) ) +#define BITS_ARMMTX_M5TOS2_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_ARMMTX_M5TOS4_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M5TOS4_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M5TOS4_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M5TOS4_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M3TOS2_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M3TOS2_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M3TOS2_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M3TOS2_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M2TOS2_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M2TOS2_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M2TOS2_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M2TOS2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL4 */ +#define BITS_ARMMTX_M4TOS3_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M4TOS3_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M4TOS3_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M4TOS3_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M1TOS3_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M1TOS3_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M1TOS3_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M1TOS3_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M0TOS3_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M0TOS3_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M0TOS3_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M0TOS3_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL5 */ +#define BITS_ARMMTX_M4TOS0_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ARMMTX_M4TOS0_ADJ_EN ( BIT(27) ) +#define BIT_ARMMTX_M4TOS0_RND_EN ( BIT(26) ) +#define BITS_ARMMTX_M4TOS0_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_ARMMTX_M4TOS4_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M4TOS4_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M4TOS4_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M4TOS4_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M1TOS4_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M1TOS4_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M1TOS4_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M1TOS4_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M0TOS4_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M0TOS4_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M0TOS4_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M0TOS4_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL6 */ +#define BITS_ARMMTX_M3TOS5_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ARMMTX_M3TOS5_ADJ_EN ( BIT(27) ) +#define BIT_ARMMTX_M3TOS5_RND_EN ( BIT(26) ) +#define BITS_ARMMTX_M3TOS5_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_ARMMTX_M2TOS5_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M2TOS5_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M2TOS5_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M2TOS5_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M1TOS5_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M1TOS5_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M1TOS5_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M1TOS5_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M0TOS5_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M0TOS5_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M0TOS5_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M0TOS5_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_PAUSE */ +#define BIT_MCU_GGE_DEEP_SLEEP_EN ( BIT(5) ) +#define BIT_MCU_LIGHT_SLEEP_EN ( BIT(4) ) +#define BIT_APB_SLEEP ( BIT(3) ) +#define BIT_MCU_DEEP_SLEEP_EN ( BIT(2) ) +#define BIT_MCU_SYS_SLEEP_EN ( BIT(1) ) +#define BIT_MCU_CORE_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_SLP_CTL */ +#define BIT_AHB_VCP1_DEEP_SLEEP_EN ( BIT(6) ) +#define BIT_GGE_ARM_DAHB_SLEEP_EN ( BIT(5) ) +#define BIT_ARM_DAHB_SLEEP_EN ( BIT(4) ) +#define BIT_MCUMTX_AUTO_GATE_EN ( BIT(3) ) +#define BIT_MCU_AUTO_GATE_EN ( BIT(2) ) +#define BIT_AHB_AUTO_GATE_EN ( BIT(1) ) +#define BIT_ARM_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_SLP_STS */ +#define BIT_GGE_DSP_MAHB_SLEEP_EN ( BIT(4) ) +#define BIT_APB_PERI_SLEEP ( BIT(3) ) +#define BIT_DSP_MAHB_SLEEP_EN ( BIT(2) ) +#define BIT_DMA_BUSY ( BIT(1) ) +#define BIT_EMC_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_MCU_CLK_CTL */ +#define BIT_CLK_CP_DBG_GGE_SEL ( BIT(28) ) +#define BIT_CLK_GGE_DBG_SEL ( BIT(27) ) +#define BITS_CLK_COM_GGE_DBG_SEL(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BIT_CLK_SYS_GGE_DBG_SEL ( BIT(24) ) +#define BITS_CLK_LZMA_SEL(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)) ) +#define BIT_CLK_CP_DBG_SEL ( BIT(21) ) +#define BIT_CLK_MCU_DBG_SEL ( BIT(20) ) +#define BITS_CLK_COM_DBG_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_CLK_SYS_DBG_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_CLK_AHB_DIV(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_CLK_MCU_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_APB_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CLK_MCU_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_CP_AHB_RF_DSP_CTL */ +#define BIT_GGE_ASHB_ARMTODSP_EN ( BIT(5) ) +#define BIT_GGE_FRC_CLK_DSP_EN ( BIT(4) ) +#define BIT_GGE_DSP_BOOT_EN ( BIT(3) ) +#define BIT_ASHB_ARMTODSP_EN ( BIT(2) ) +#define BIT_FRC_CLK_DSP_EN ( BIT(1) ) +#define BIT_DSP_BOOT_EN ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_DSP_BOOT_VECTOR */ +#define BITS_DSP_BOOT_VECTOR(_X_) (_X_) + +/* bits definitions for register REG_CP_AHB_RF_DSP_RST */ +#define BIT_GGE_DSP_SYS_SRST ( BIT(3) ) +#define BIT_GGE_DSP_CORE_SRST_N ( BIT(2) ) +#define BIT_DSP_SYS_SRST ( BIT(1) ) +#define BIT_DSP_CORE_SRST_N ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_DSP_JTAG_CTL */ +#define BIT_GGE_CEVA_SW_JTAG_ENA ( BIT(24) ) +#define BIT_GGE_STDO ( BIT(20) ) +#define BIT_GGE_STCK ( BIT(19) ) +#define BIT_GGE_STMS ( BIT(18) ) +#define BIT_GGE_STDI ( BIT(17) ) +#define BIT_GGE_STRTCK ( BIT(16) ) +#define BIT_CEVA_SW_JTAG_ENA ( BIT(8) ) +#define BIT_STDO ( BIT(4) ) +#define BIT_STCK ( BIT(3) ) +#define BIT_STMS ( BIT(2) ) +#define BIT_STDI ( BIT(1) ) +#define BIT_STRTCK ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_MCU_C2C_SEMA */ +#define BITS_GGE_MCU_C2C_SEMA(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_MCU_C2C_SEMA(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_CP_AHB_RF_GGE_DSP_BOOT_VECTOR */ +#define BITS_GGE_DSP_BOOT_VECTOR(_X_) (_X_) + +/* bits definitions for register REG_CP_AHB_RF_CHIP_ID */ +#define BITS_CHIP_ID(_X_) (_X_) + +#endif diff --git a/include/soc/sprd/chip_x20l/__regs_cp_apb_rf.h b/include/soc/sprd/chip_x20l/__regs_cp_apb_rf.h new file mode 100644 index 00000000..94249dcb --- /dev/null +++ b/include/soc/sprd/chip_x20l/__regs_cp_apb_rf.h @@ -0,0 +1,245 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_CP_APB_RF_HEADFILE_H__ +#define __H_REGS_CP_APB_RF_HEADFILE_H__ __FILE__ + +#define REGS_CP_APB_RF + +/* registers definitions for CP_APB_RF */ +#define REG_CP_APB_RF_APB_EB0_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0008) +#define REG_CP_APB_RF_APB_RST0_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0014) +#define REG_CP_APB_RF_APB_MCU_RST SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0018) +#define REG_CP_APB_RF_APB_CLK_SEL0 SCI_ADDR(REGS_CP_APB_RF_BASE, 0x001C) +#define REG_CP_APB_RF_APB_CLK_DIV0 SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0020) +#define REG_CP_APB_RF_APB_ARCH_EB SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0024) +#define REG_CP_APB_RF_APB_MISC_CTL0 SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0028) +#define REG_CP_APB_RF_APB_MISC_CTL1 SCI_ADDR(REGS_CP_APB_RF_BASE, 0x002C) +#define REG_CP_APB_RF_APB_PIN_SEL SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0040) +#define REG_CP_APB_RF_APB_SLP_CTL SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0044) +#define REG_CP_APB_RF_APB_WSYS_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0048) +#define REG_CP_APB_RF_APB_SLP_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0050) +#define REG_CP_APB_RF_APB_ROM_PD_CTL SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0054) +#define REG_CP_APB_RF_APB_BUS_CTL0 SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0058) +#define REG_CP_APB_RF_APB_DSP_INT_CLR SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0074) +#define REG_CP_APB_RF_APB_MISC_INT_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0078) +#define REG_CP_APB_RF_APB_HWRST SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0080) +#define REG_CP_APB_RF_APB_ARM_BOOT_ADDR SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0084) +#define REG_CP_APB_RF_APB_GGE_SLP_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0088) + + + +/* bits definitions for register REG_CP_APB_RF_APB_EB0_STS */ +#define BIT_UART2_EB ( BIT(20) ) +#define BIT_EIC_RTC_EB ( BIT(19) ) +#define BIT_EIC_EB ( BIT(18) ) +#define BIT_RFFE_EB ( BIT(17) ) +#define BIT_EPT_EB ( BIT(16) ) +#define BIT_GPIO_EB ( BIT(15) ) +#define BIT_TMR_RTC_EB ( BIT(14) ) +#define BIT_TMR_EB ( BIT(13) ) +#define BIT_SYSTMR_RTC_EB ( BIT(12) ) +#define BIT_SYSTMR_EB ( BIT(11) ) +#define BIT_IIS3_EB ( BIT(10) ) +#define BIT_IIS2_EB ( BIT(9) ) +#define BIT_IIS1_EB ( BIT(8) ) +#define BIT_IIS0_EB ( BIT(7) ) +#define BIT_SIM2_EB ( BIT(6) ) +#define BIT_SIM1_EB ( BIT(5) ) +#define BIT_SIM0_EB ( BIT(4) ) +#define BIT_UART1_EB ( BIT(3) ) +#define BIT_UART0_EB ( BIT(2) ) +#define BIT_WDG_RTC_EB ( BIT(1) ) +#define BIT_WDG_EB ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_RST0_STS */ +#define BIT_UART2_SOFT_RST ( BIT(20) ) +#define BIT_GGE_MCU_DSP_RST ( BIT(19) ) +#define BIT_EIC_SOFT_RST ( BIT(16) ) +#define BIT_RFFE_SOFT_RST ( BIT(15) ) +#define BIT_MCU_DSP_RST ( BIT(14) ) +#define BIT_EPT_SOFT_RST ( BIT(13) ) +#define BIT_GPIO_SOFT_RST ( BIT(12) ) +#define BIT_TMR_SOFT_RST ( BIT(11) ) +#define BIT_SYSTMR_SOFT_RST ( BIT(10) ) +#define BIT_IIS3_SOFT_RST ( BIT(9) ) +#define BIT_IIS2_SOFT_RST ( BIT(8) ) +#define BIT_IIS1_SOFT_RST ( BIT(7) ) +#define BIT_IIS0_SOFT_RST ( BIT(6) ) +#define BIT_SIM2_SOFT_RST ( BIT(5) ) +#define BIT_SIM1_SOFT_RST ( BIT(4) ) +#define BIT_SIM0_SOFT_RST ( BIT(3) ) +#define BIT_UART1_SOFT_RST ( BIT(2) ) +#define BIT_UART0_SOFT_RST ( BIT(1) ) +#define BIT_WDG_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_MCU_RST */ +#define BIT_MCU_SOFT_RST_SET ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_CLK_SEL0 */ +#define BIT_CLK_IIS3_PAD_SEL ( BIT(19) ) +#define BIT_CLK_IIS2_PAD_SEL ( BIT(18) ) +#define BIT_CLK_IIS1_PAD_SEL ( BIT(17) ) +#define BIT_CLK_IIS0_PAD_SEL ( BIT(16) ) +#define BITS_CLK_UART2_SEL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_CLK_IIS3_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_CLK_IIS2_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_CLK_IIS1_SEL(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_CLK_IIS0_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CLK_UART1_SEL(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_CLK_UART0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CP_APB_RF_APB_CLK_DIV0 */ +#define BITS_CLK_IIS2_DIV(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_CLK_IIS1_DIV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)) ) +#define BITS_CLK_IIS0_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_CLK_UART1_DIV(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BITS_CLK_UART0_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_CP_APB_RF_APB_ARCH_EB */ +#define BITS_CLK_UART2_DIV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)) ) +#define BITS_CLK_IIS3_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_RTC_ARCH_EB ( BIT(1) ) +#define BIT_APB_ARCH_EB ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_MISC_CTL0 */ +#define BIT_GGE_ALL_CLK_EN ( BIT(29) ) +#define BIT_ALL_CLK_EN ( BIT(28) ) +#define BIT_DMA_LSLP_EN ( BIT(27) ) +#define BIT_WAKEUP_XTL_EN_3G_W ( BIT(26) ) +#define BIT_WAKEUP_XTL_EN_2G ( BIT(25) ) +#define BIT_ARM_JTAG_EN ( BIT(24) ) +#define BIT_WAKEUP_XTL_EN_3G_TD ( BIT(23) ) +#define BIT_GGE_WAKEUP_XTL_EN_2G ( BIT(22) ) +#define BITS_ARM_FRC_STOP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) ) + +/* bits definitions for register REG_CP_APB_RF_APB_MISC_CTL1 */ +#define BITS_BUFON_CTRL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_SIM2_CLK_POLARITY ( BIT(3) ) +#define BIT_SIM1_CLK_POLARITY ( BIT(2) ) +#define BIT_SIM0_CLK_POLARITY ( BIT(1) ) +#define BIT_ROM_CLK_EN ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_PIN_SEL */ +#define BIT_DJTAG_PIN_IN_SEL ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_SLP_CTL */ +#define BITS_GGE_DEEP_SLP_DBG(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_APB_PERI_FRC_ON ( BIT(20) ) +#define BIT_APB_PERI_FRC_SLP ( BIT(16) ) +#define BIT_MCU_XTLEN_AUTOPD_EN ( BIT(12) ) +#define BIT_MCU_FORCE_GGE_LIGHT_SLEEP ( BIT(9) ) +#define BIT_MCU_FORCE_LIGHT_SLEEP ( BIT(8) ) +#define BIT_CHIP_SLP_ARM_CLR ( BIT(4) ) +#define BIT_MCU_FORCE_GGE_DEEP_SLEEP ( BIT(3) ) +#define BIT_MCU_FORCE_WSYS_LT_STOP ( BIT(2) ) +#define BIT_MCU_FORCE_WSYS_STOP ( BIT(1) ) +#define BIT_MCU_FORCE_DEEP_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_WSYS_STS */ +#define BITS_DEEP_SLP_DBG(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_WSYS_STATUS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_CP_APB_RF_APB_SLP_STS */ +#define BIT_DSP_MAHB_SLEEP_EN ( BIT(28) ) +#define BIT_MCU_PERI_STOP ( BIT(27) ) +#define BIT_DSP_PERI_STOP ( BIT(26) ) +#define BIT_ECC_CKG_EN ( BIT(25) ) +#define BIT_QBC_CKG_EN ( BIT(24) ) +#define BIT_DSP_TWPLL_EN ( BIT(21) ) +#define BIT_STC_TMR_AUTOPD_XTL_EN ( BIT(20) ) +#define BIT_RFT_TMR_AUTOPD_XTL_EN ( BIT(19) ) +#define BIT_STC_TMR_AUTOPD_RF_EN ( BIT(18) ) +#define BIT_RFT_TMR_AUTOPD_RF_EN ( BIT(17) ) +#define BIT_CHIP_SLEEP_REC_ARM ( BIT(16) ) +#define BIT_DSP_CORE_STOP ( BIT(15) ) +#define BIT_DSP_MTX_STOP ( BIT(14) ) +#define BIT_DSP_AHB_STOP ( BIT(13) ) +#define BIT_DSP_SYS_STOP ( BIT(12) ) +#define BIT_DSP_DEEP_STOP ( BIT(11) ) +#define BIT_ASHB_DSPTOARM_EN ( BIT(10) ) +#define BIT_ASHB_ARMTODSP_VALID ( BIT(9) ) +#define BIT_EMC_STOP_CH3 ( BIT(8) ) +#define BIT_EMC_STOP_CH4 ( BIT(7) ) +#define BIT_EMC_STOP_CH5 ( BIT(6) ) +#define BIT_FRC_WAKE_EN ( BIT(5) ) +#define BIT_TMR_WAKE_AFC ( BIT(4) ) +#define BIT_SCH_SLEEP ( BIT(3) ) +#define BIT_DSP_STOP ( BIT(2) ) +#define BIT_MCU_STOP ( BIT(1) ) +#define BIT_EMC_STOP ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_ROM_PD_CTL */ +#define BIT_GGE_ROM_FORCE_ON ( BIT(1) ) +#define BIT_ROM_FORCE_ON ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_BUS_CTL0 */ +#define BIT_IIS3_DSP_CTRL_SEL ( BIT(11) ) +#define BIT_IIS2_DSP_CTRL_SEL ( BIT(10) ) +#define BIT_IIS1_DSP_CTRL_SEL ( BIT(9) ) +#define BIT_IIS0_DSP_CTRL_SEL ( BIT(8) ) +#define BIT_UART2_CTRL_SEL ( BIT(7) ) +#define BIT_RFFE_CTRL_SEL ( BIT(5) ) +#define BIT_IIS3_CTRL_SEL ( BIT(4) ) +#define BIT_IIS2_CTRL_SEL ( BIT(3) ) +#define BIT_IIS1_CTRL_SEL ( BIT(2) ) +#define BIT_IIS0_CTRL_SEL ( BIT(1) ) +#define BIT_UART1_CTRL_SEL ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_DSP_INT_CLR */ +#define BIT_RFT_INT_CLR ( BIT(2) ) + +/* bits definitions for register REG_CP_APB_RF_APB_MISC_INT_STS */ +#define BIT_RFT_INT ( BIT(2) ) + +/* bits definitions for register REG_CP_APB_RF_APB_HWRST */ +#define BITS_HWRST_REG(_X_) (_X_) + +/* bits definitions for register REG_CP_APB_RF_APB_ARM_BOOT_ADDR */ +#define BITS_ARMBOOT_ADDR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_CP_APB_RF_APB_GGE_SLP_STS */ +#define BIT_GGE_DSP_MAHB_SLEEP_EN ( BIT(21) ) +#define BIT_GGE_DSP_PERI_STOP ( BIT(20) ) +#define BIT_GGE_QBC_CKG_EN ( BIT(19) ) +#define BIT_GGE_DSP_TWPLL_EN ( BIT(18) ) +#define BIT_GGE_STC_TMR_AUTOPD_XTL_EN ( BIT(17) ) +#define BIT_GGE_STC_TMR_AUTOPD_RF_EN ( BIT(16) ) +#define BIT_GGE_DSP_CORE_STOP ( BIT(15) ) +#define BIT_GGE_DSP_MTX_STOP ( BIT(14) ) +#define BIT_GGE_DSP_AHB_STOP ( BIT(13) ) +#define BIT_GGE_DSP_SYS_STOP ( BIT(12) ) +#define BIT_GGE_DSP_DEEP_STOP ( BIT(11) ) +#define BIT_GGE_ASHB_DSPTOARM_EN ( BIT(10) ) +#define BIT_GGE_ASHB_ARMTODSP_VALID ( BIT(9) ) +#define BIT_GGE_EMC_STOP_CH3 ( BIT(8) ) +#define BIT_GGE_EMC_STOP_CH4 ( BIT(7) ) +#define BIT_GGE_EMC_STOP_CH5 ( BIT(6) ) +#define BIT_GGE_FRC_WAKE_EN ( BIT(5) ) +#define BIT_GGE_TMR_WAKE_AFC ( BIT(4) ) +#define BIT_GGE_SCH_SLEEP ( BIT(3) ) +#define BIT_GGE_DSP_STOP ( BIT(2) ) +#define BIT_GGE_MCU_STOP ( BIT(1) ) +#define BIT_GGE_EMC_STOP ( BIT(0) ) + +#endif diff --git a/include/soc/sprd/chip_x20l/__regs_djtag_apb_rf.h b/include/soc/sprd/chip_x20l/__regs_djtag_apb_rf.h new file mode 100755 index 00000000..7aa4d044 --- /dev/null +++ b/include/soc/sprd/chip_x20l/__regs_djtag_apb_rf.h @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_DJTAG_APB_RF_HEADFILE_H__ +#define __H_REGS_DJTAG_APB_RF_HEADFILE_H__ __FILE__ + +#define REGS_DJTAG_APB_RF + +/* registers definitions for DJTAG_APB_RF */ +#define REG_DJTAG_APB_RF_DJTAG_IR_LEN_CFG SCI_ADDR(REGS_DJTAG_APB_RF_BASE, 0x0000) +#define REG_DJTAG_APB_RF_DJTAG_DR_LEN_CFG SCI_ADDR(REGS_DJTAG_APB_RF_BASE, 0x0004) +#define REG_DJTAG_APB_RF_DJTAG_IR_CFG SCI_ADDR(REGS_DJTAG_APB_RF_BASE, 0x0008) +#define REG_DJTAG_APB_RF_DJTAG_DR_CFG SCI_ADDR(REGS_DJTAG_APB_RF_BASE, 0x000C) +#define REG_DJTAG_APB_RF_DR_PAUSE_RECOV_CFG SCI_ADDR(REGS_DJTAG_APB_RF_BASE, 0x0010) +#define REG_DJTAG_APB_RF_DJTAG_RND_EN_CFG SCI_ADDR(REGS_DJTAG_APB_RF_BASE, 0x0014) +#define REG_DJTAG_APB_RF_DJTAG_UPD_DR_CFG SCI_ADDR(REGS_DJTAG_APB_RF_BASE, 0x0018) + + + +/* bits definitions for register REG_DJTAG_APB_RF_DJTAG_IR_LEN_CFG */ +#define BITS_IR_LEN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_DJTAG_APB_RF_DJTAG_DR_LEN_CFG */ +#define BITS_DR_LEN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_DJTAG_APB_RF_DJTAG_IR_CFG */ +#define BITS_DJTAG_IR(_X_) (_X_) + +/* bits definitions for register REG_DJTAG_APB_RF_DJTAG_DR_CFG */ +#define BITS_DJTAG_DR(_X_) (_X_) + +/* bits definitions for register REG_DJTAG_APB_RF_DR_PAUSE_RECOV_CFG */ +#define BIT_DR_PAUSE_RECOV ( BIT(0) ) + +/* bits definitions for register REG_DJTAG_APB_RF_DJTAG_RND_EN_CFG */ +#define BIT_DJTAG_RND_EN ( BIT(0) ) + +/* bits definitions for register REG_DJTAG_APB_RF_DJTAG_UPD_DR_CFG */ +#define BITS_DJTAG_UPD_DR(_X_) (_X_) + +#endif diff --git a/include/soc/sprd/chip_x20l/__regs_gpu_apb_rf.h b/include/soc/sprd/chip_x20l/__regs_gpu_apb_rf.h new file mode 100755 index 00000000..4144705a --- /dev/null +++ b/include/soc/sprd/chip_x20l/__regs_gpu_apb_rf.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_GPU_APB_HEADFILE_H__ +#define __H_REGS_GPU_APB_HEADFILE_H__ __FILE__ + +#define REGS_GPU_APB_RF + +/* registers definitions for GPU_APB_RF */ +#define REG_GPU_APB_APB_RST SCI_ADDR(REGS_GPU_APB_BASE, 0x0000) +#define REG_GPU_APB_APB_CLK_CTRL SCI_ADDR(REGS_GPU_APB_BASE, 0x0004) + + + +/* bits definitions for register REG_GPU_APB_RF_APB_RST */ +#define BIT_GPU_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_GPU_APB_APB_CLK_CTRL */ +#define BITS_CLK_GPU_DIV(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CLK_GPU_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +#endif diff --git a/include/soc/sprd/chip_x20l/__regs_lte_cevax_pmu.h b/include/soc/sprd/chip_x20l/__regs_lte_cevax_pmu.h new file mode 100755 index 00000000..42b3786d --- /dev/null +++ b/include/soc/sprd/chip_x20l/__regs_lte_cevax_pmu.h @@ -0,0 +1,358 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_LTE_CEVAX_PMU_HEADFILE_H__ +#define __H_REGS_LTE_CEVAX_PMU_HEADFILE_H__ __FILE__ + +#define REGS_LTE_CEVAX_PMU + +/* registers definitions for LTE_CEVAX_PMU */ +#define REG_LTE_CEVAX_PMU_PLL_CFG0 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0000) +#define REG_LTE_CEVAX_PMU_PLL_CFG1 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0004) +#define REG_LTE_CEVAX_PMU_CXCLK_DIV SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0008) +#define REG_LTE_CEVAX_PMU_XHCLK_DIV SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x000C) +#define REG_LTE_CEVAX_PMU_XPCLK_DIV SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0010) +#define REG_LTE_CEVAX_PMU_CXPMOD SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0014) +#define REG_LTE_CEVAX_PMU_XHPMOD SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0018) +#define REG_LTE_CEVAX_PMU_XAPBMOD SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x001C) +#define REG_LTE_CEVAX_PMU_VERSION_CR SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0020) +#define REG_LTE_CEVAX_PMU_SLEEP_STATUS SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0024) +#define REG_LTE_CEVAX_PMU_POW_CTL0 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0028) +#define REG_LTE_CEVAX_PMU_POW_CTL1 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x002C) +#define REG_LTE_CEVAX_PMU_POW_CTL2 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0030) +#define REG_LTE_CEVAX_PMU_ACCCLK_EN0 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0034) +#define REG_LTE_CEVAX_PMU_ACCCLK_EN1 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0038) +#define REG_LTE_CEVAX_PMU_ACCCLK_EN2 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x003C) +#define REG_LTE_CEVAX_PMU_SOFT_RST0 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0040) +#define REG_LTE_CEVAX_PMU_SOFT_RST1 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0044) +#define REG_LTE_CEVAX_PMU_DSP_CKG_SEL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0048) +#define REG_LTE_CEVAX_PMU_CLK_DLCH_SEL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0050) +#define REG_LTE_CEVAX_PMU_CLK_ULCH_SEL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0054) +#define REG_LTE_CEVAX_PMU_CLK_RATEM_SEL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0058) +#define REG_LTE_CEVAX_PMU_CLK_LTE_SPI_DIV_SEL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x005C) +#define REG_LTE_CEVAX_PMU_CX_CKG_DIV SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0078) +#define REG_LTE_CEVAX_PMU_XH_CKG_DIV SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x007C) +#define REG_LTE_CEVAX_PMU_XP_CKG_DIV SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0080) +#define REG_LTE_CEVAX_PMU_LTE_PMU_CKG_EN SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0084) +#define REG_LTE_CEVAX_PMU_LTE_PMU_CLK_EN SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0088) +#define REG_LTE_CEVAX_PMU_APB_CLK_SEL0 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x008C) +#define REG_LTE_CEVAX_PMU_APB_CLK_SEL1 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0090) +#define REG_LTE_CEVAX_PMU_CLK_CXTMR0_SEL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0094) +#define REG_LTE_CEVAX_PMU_CLK_CXTMR1_SEL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0098) +#define REG_LTE_CEVAX_PMU_CLK_CXTMR2_SEL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x009C) +#define REG_LTE_CEVAX_PMU_APB_CLK_SEL2 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x00A0) +#define REG_LTE_CEVAX_PMU_MEM_LP_CTRL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0xA4) +#define REG_LTE_CEVAX_PMU_AXI_MON_CTRL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0xA8) +#define REG_LTE_CEVAX_PMU_RES_REG0 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0140) +#define REG_LTE_CEVAX_PMU_RES_REG1 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0144) +#define REG_LTE_CEVAX_PMU_RES_REG2 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0148) + + + +/* bits definitions for register REG_LTE_CEVAX_PMU_PLL_CFG0 */ +#define BITS_PLL_CFG0_R(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_DSP_DLCH_EN ( BIT(8) ) +#define BIT_DSP_ULCH_EN ( BIT(7) ) +#define BIT_DLCH_AUTO_EN ( BIT(6) ) +#define BIT_ULCH_AUTO_EN ( BIT(5) ) +#define BIT_UART1_EB ( BIT(2) ) +#define BIT_UART0_EB ( BIT(1) ) +#define BIT_RFFE_EB ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_PLL_CFG1 */ +#define BIT_CHIP_SLP_REC_DSP ( BIT(16) ) +#define BIT_LTE_POW_OFF ( BIT(10) ) +#define BIT_LTE_POW_READY ( BIT(9) ) +#define BITS_LTE_POW_WAIT(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) ) +#define BIT_CHIP_SLP_DSP_CLR ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CXCLK_DIV */ +#define BITS_CXREG_AUTO_OFF(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_XHCLK_DIV */ +#define BIT_BUSMON2_CHN_SEL ( BIT(25) ) +#define BIT_BUSMON1_CHN_SEL ( BIT(24) ) +#define BIT_BUSMON0_CHN_SEL ( BIT(23) ) +#define BITS_DSP_SHM_CTRL(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BIT_DSPAPB_DES_AUTO_EN ( BIT(20) ) +#define BIT_DSPAHB_DES_AUTO_EN ( BIT(19) ) +#define BITS_LBUSMON2_CHN_SEL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_LBUSMON1_CHN_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_LBUSMON0_CHN_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_DSPAPB_DIV_DES(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DSPAHB_DIV_DES(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)) ) +#define BITS_CX_DSPPLL_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_XPCLK_DIV */ +#define BIT_PMU_DMA_FRC_EB ( BIT(24) ) +#define BIT_ZBUS_32ACCESS ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CXPMOD */ +#define BIT_MCU_FORCE_DEEP_SLEEP ( BIT(31) ) +#define BIT_LDSP_DEEP_SLP_CTRL ( BIT(30) ) +#define BIT_EMC_LIGHT_SLEEP_EN_M6 ( BIT(29) ) +#define BIT_EMC_DEEP_SLEEP_EN_M6 ( BIT(28) ) +#define BIT_EMC_LIGHT_SLEEP_EN_M7 ( BIT(27) ) +#define BIT_EMC_DEEP_SLEEP_EN_M7 ( BIT(26) ) +#define BIT_EMC_LIGHT_SLEEP_EN_M8 ( BIT(25) ) +#define BIT_EMC_DEEP_SLEEP_EN_M8 ( BIT(24) ) +#define BIT_LDSP2PUB_ACCESS_EN ( BIT(8) ) +#define BIT_LDSP_WAKEUP_XTL_EN ( BIT(7) ) +#define BIT_DMA_LSLP_EN ( BIT(4) ) +#define BIT_DSP_LIGHT_SLEEP_EN ( BIT(3) ) +#define BIT_DSP_DEEP_SLEEP_EN ( BIT(2) ) +#define BIT_DSP_SYS_SLEEP_EN ( BIT(1) ) +#define BIT_DSP_CORE_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_XHPMOD */ +#define BIT_BUSMON2_EB ( BIT(31) ) +#define BIT_BUSMON1_EB ( BIT(30) ) +#define BIT_BUSMON0_EB ( BIT(29) ) +#define BIT_LACCX_AUTO_GATE_EN ( BIT(14) ) +#define BIT_LDSPX_AUTO_GATE_EN ( BIT(13) ) +#define BIT_CXDMA_CLK_AUTO_EN ( BIT(12) ) +#define BIT_CXAPB_AUTO_GATE_EN ( BIT(11) ) +#define BIT_CXAHB_AUTO_GATE_EN ( BIT(10) ) +#define BIT_CXDSP_AUTO_GATE_EN ( BIT(9) ) +#define BIT_CXCORE_AUTO_GATE_EN ( BIT(8) ) +#define BIT_CXMTX_AUTO_GATE_EN ( BIT(7) ) +#define BIT_DSP_MAHB_SLEEP_EN ( BIT(6) ) +#define BIT_ACCZ_ARCH_EB ( BIT(5) ) +#define BIT_CXBUS_ARCH_EB ( BIT(4) ) +#define BIT_LTEPROC_ARCH_EB ( BIT(3) ) +#define BIT_PMU_DLCH_SLEEP_R ( BIT(1) ) +#define BIT_PMU_ULCH_SLEEP_R ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_XAPBMOD */ +#define BITS_HPROTDMAW(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_HPROTDMAR(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_PMU_XPSLEEP_P_R(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_VERSION_CR */ +#define BITS_VERSION_CR(_X_) (_X_) + +/* bits definitions for register REG_LTE_CEVAX_PMU_SLEEP_STATUS */ +#define BITS_PMU_SLEEP_STATUS(_X_) (_X_) + +/* bits definitions for register REG_LTE_CEVAX_PMU_POW_CTL0 */ +#define BITS_LTE_ISO_ON_NUM(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LTE_ISO_OFF_NUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_POW_CTL1 */ +#define BIT_CLK_PWR_LTE_SEL ( BIT(10) ) +#define BIT_LTE_SLP_POWOFF_AUTO_EN ( BIT(9) ) +#define BIT_LTE_POW_FORCE_PD ( BIT(8) ) +#define BITS_DSP_MEM_PD_REG(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_POW_CTL2 */ +#define BITS_DSP_MEM_PD_EN(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)) ) +#define BITS_PD_LTE_STATUS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_ACCCLK_EN0 */ +#define BIT_FFT_OFFLN_HCLKEN ( BIT(30) ) +#define BIT_FFT_OFFLN_CLKEN ( BIT(29) ) +#define BIT_FFT_ONLN_HCLKEN ( BIT(28) ) +#define BIT_FFT_ONLN_CLKEN ( BIT(27) ) +#define BIT_LTE_DRM_CLKEN ( BIT(24) ) +#define BIT_MIMO_HCLKEN ( BIT(23) ) +#define BIT_MIMO_CLKEN ( BIT(22) ) +#define BIT_PBCH_ACLKEN ( BIT(21) ) +#define BIT_PBCH_HCLKEN ( BIT(20) ) +#define BIT_PBCH_CLKEN ( BIT(19) ) +#define BIT_PCFICH_PHICH_HCLKEN ( BIT(18) ) +#define BIT_PCFICH_PHICH_CLKEN ( BIT(17) ) +#define BIT_PDCCH_ACLKEN ( BIT(16) ) +#define BIT_PDCCH_HCLKEN ( BIT(15) ) +#define BIT_PDCCH_CLKEN ( BIT(14) ) +#define BIT_PDSCH_TB_CTL_HCLKEN ( BIT(13) ) +#define BIT_PDSCH_TB_CTL_CLKEN ( BIT(12) ) +#define BIT_RXDFE_HCLKEN ( BIT(11) ) +#define BIT_SYNC_ACLKEN ( BIT(10) ) +#define BIT_SYNC_HCLKEN ( BIT(9) ) +#define BIT_SYNC_CLKEN ( BIT(8) ) +#define BIT_TBUF_ACLKEN ( BIT(7) ) +#define BIT_TBUF_HCLKEN ( BIT(6) ) +#define BIT_TBUF_CLKEN ( BIT(5) ) +#define BIT_VTB_CLKEN ( BIT(4) ) +#define BIT_LTE_PROC_HCLKEN ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_ACCCLK_EN1 */ +#define BIT_LBUSMON2_EB ( BIT(28) ) +#define BIT_LBUSMON1_EB ( BIT(27) ) +#define BIT_LBUSMON0_EB ( BIT(26) ) +#define BIT_HSDL_CLKEN ( BIT(25) ) +#define BIT_ULMAC_HCLKEN ( BIT(24) ) +#define BIT_TBE_HCLKEN ( BIT(23) ) +#define BIT_TBE_CLKEN ( BIT(22) ) +#define BIT_RM_HCLKEN ( BIT(21) ) +#define BIT_RM_CLKEN ( BIT(20) ) +#define BIT_PCM_HCLKEN ( BIT(19) ) +#define BIT_PCM_CLKEN ( BIT(18) ) +#define BIT_UCM_HCLKEN ( BIT(17) ) +#define BIT_UCM_CLKEN ( BIT(16) ) +#define BIT_CHE_ACLKEN ( BIT(15) ) +#define BIT_CHE_HCLKEN ( BIT(14) ) +#define BIT_CHE_SYS_CLKEN ( BIT(13) ) +#define BIT_CHEPP_ACLKEN ( BIT(12) ) +#define BIT_CHEPP_HCLKEN ( BIT(11) ) +#define BIT_CHEPP_SYS_CLKEN ( BIT(10) ) +#define BIT_DBUF_ACLKEN ( BIT(9) ) +#define BIT_DBUF_HCLKEN ( BIT(8) ) +#define BIT_DBUF_CLKEN ( BIT(7) ) +#define BIT_DFE_CLKEN ( BIT(6) ) +#define BIT_FBUF_ACLKEN ( BIT(5) ) +#define BIT_FBUF_HCLKEN ( BIT(4) ) +#define BIT_FBUF_CLKEN ( BIT(3) ) +#define BIT_FEC_ACLKEN ( BIT(2) ) +#define BIT_FEC_HCLKEN ( BIT(1) ) +#define BIT_FEC_CLKEN ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_ACCCLK_EN2 */ + +/* bits definitions for register REG_LTE_CEVAX_PMU_SOFT_RST0 */ +#define BITS_SOFT_RST_R(_X_) (_X_) + +/* bits definitions for register REG_LTE_CEVAX_PMU_SOFT_RST1 */ +#define BIT_LTE_PROC_SOFT_RST_RFT ( BIT(31) ) +#define BIT_HSDL_SOFT_RST ( BIT(30) ) +#define BIT_RFSPI_SOFT_RST ( BIT(29) ) +#define BIT_LTE_PROC_SOFT_RST ( BIT(28) ) +#define BIT_ULMAC_SOFT_RST ( BIT(27) ) +#define BIT_PCM_SOFT_RST ( BIT(26) ) +#define BIT_UCM_SOFT_RST ( BIT(25) ) +#define BIT_TBE_SOFT_RST ( BIT(24) ) +#define BIT_RM_SOFT_RST ( BIT(23) ) +#define BIT_RFT_SOFT_RST ( BIT(22) ) +#define BIT_DFE_SOFT_RST ( BIT(21) ) +#define BIT_MIMO_SOFT_RST ( BIT(20) ) +#define BIT_ON_LINE_FFT_SOFT_RST ( BIT(19) ) +#define BIT_OFF_LINE_FFT_SOFT_RST ( BIT(18) ) +#define BIT_PCFICH_SOFT_RST ( BIT(17) ) +#define BIT_PDSCH_SOFT_RST ( BIT(16) ) +#define BIT_DRM_SOFT_RST ( BIT(15) ) +#define BIT_VTB_SOFT_RST ( BIT(14) ) +#define BIT_FEC_SOFT_RST ( BIT(13) ) +#define BIT_CHE_SOFT_RST ( BIT(12) ) +#define BIT_CHEPP_SOFT_RST ( BIT(11) ) +#define BIT_SYNC_SOFT_RST ( BIT(10) ) +#define BIT_TBUF_SOFT_RST ( BIT(9) ) +#define BIT_DBUF_SOFT_RST ( BIT(8) ) +#define BIT_FBUF_SOFT_RST ( BIT(7) ) +#define BIT_PDCCH_SOFT_RST ( BIT(6) ) +#define BIT_PBCH_SOFT_RST ( BIT(5) ) +#define BIT_RXADC_SOFT_RST ( BIT(4) ) +#define BIT_TXDAC_SOFT_RST ( BIT(3) ) +#define BIT_CAL_SOFT_RST ( BIT(2) ) +#define BIT_RTC_SOFT_RST ( BIT(1) ) +#define BIT_LTE_SPI_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_DSP_CKG_SEL */ +#define BITS_DSP_CKG_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CLK_DLCH_SEL */ +#define BITS_CLK_DLCH_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CLK_ULCH_SEL */ +#define BITS_CLK_ULCH_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CLK_RATEM_SEL */ +#define BITS_CLK_RATEM_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CLK_LTE_SPI_DIV_SEL */ +#define BITS_CLK_LTE_SPI_DIV(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)) ) +#define BITS_CLK_LTE_SPI_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CX_CKG_DIV */ +#define BITS_CX_CKG_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_XH_CKG_DIV */ +#define BITS_XH_CKG_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_XP_CKG_DIV */ +#define BITS_XP_CKG_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_LTE_PMU_CKG_EN */ +#define BIT_DSP_CKG_EN ( BIT(8) ) +#define BIT_CX_CKG_EN ( BIT(6) ) +#define BIT_XH_CKG_EN ( BIT(5) ) +#define BIT_XP_CKG_EN ( BIT(4) ) +#define BIT_DMA_CKG_EN ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_LTE_PMU_CLK_EN */ +#define BIT_LTE_CEVAX_PMU_CLK_LTE_ANA_4X_EN ( BIT(18) ) +#define BIT_CLK_LTE_SA_EN ( BIT(17) ) +#define BIT_CLK_CXTMR2_EN ( BIT(16) ) +#define BIT_CLK_CXTMR1_EN ( BIT(15) ) +#define BIT_CLK_CXTMR0_EN ( BIT(14) ) +#define BIT_CLK_AXI_EN ( BIT(13) ) +#define BIT_CLK_AHB_EN ( BIT(12) ) +#define BIT_CLK_DFE_EN ( BIT(11) ) +#define BIT_CLK_RFT_EN ( BIT(10) ) +#define BIT_CLK_DLCH_EN ( BIT(9) ) +#define BIT_CLK_ULCH_EN ( BIT(8) ) +#define BIT_CLK_RATEM_EN ( BIT(7) ) +#define BIT_CLK_RXADC_EN ( BIT(6) ) +#define BIT_CLK_TXDAC_EN ( BIT(5) ) +#define BIT_CLK_LTE_ANA_2X_EN ( BIT(4) ) +#define BIT_CLK_LTE_ANA_1X_EN ( BIT(3) ) +#define BIT_CLK_CAL_EN ( BIT(2) ) +#define BIT_CLK_RTC_EN ( BIT(1) ) +#define BIT_CLK_LTE_SPI_EN ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_APB_CLK_SEL0 */ +#define BITS_CLK_UART1_DIV(_X_) ( (_X_) << 7 & (BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_CLK_UART1_SEL(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)) ) +#define BITS_CLK_UART0_DIV(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)) ) +#define BITS_CLK_UART0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_APB_CLK_SEL1 */ + +/* bits definitions for register REG_LTE_CEVAX_PMU_CLK_CXTMR0_SEL */ +#define BITS_CLK_CXTMR0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CLK_CXTMR1_SEL */ +#define BITS_CLK_CXTMR1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CLK_CXTMR2_SEL */ +#define BITS_CLK_CXTMR2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_APB_CLK_SEL2 */ + +/* bits definitions for register REG_LTE_CEVAX_PMU_MEM_LP_CTRL */ +#define BITS_MEM_LP_CTRL(_X_) (_X_) + +/* bits definitions for register REG_LTE_CEVAX_PMU_AXI_MON_CTRL */ +#define BIT_AXI_MON_WAIT_EB ( BIT(21) ) +#define BIT_AXI_MON_CLKEN_EB ( BIT(20) ) +#define BITS_AXI_MONITOR_STATUS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_RES_REG0 */ +#define BITS_RES_REG0(_X_) (_X_) + +/* bits definitions for register REG_LTE_CEVAX_PMU_RES_REG1 */ +#define BITS_RES_REG1(_X_) (_X_) + +/* bits definitions for register REG_LTE_CEVAX_PMU_RES_REG2 */ +#define BITS_RES_REG2(_X_) (_X_) + +#endif diff --git a/include/soc/sprd/chip_x20l/__regs_mdar_apb_rf.h b/include/soc/sprd/chip_x20l/__regs_mdar_apb_rf.h new file mode 100755 index 00000000..5416a02f --- /dev/null +++ b/include/soc/sprd/chip_x20l/__regs_mdar_apb_rf.h @@ -0,0 +1,1181 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_MDAR_APB_RF_HEADFILE_H__ +#define __H_REGS_MDAR_APB_RF_HEADFILE_H__ __FILE__ + +#define REGS_MDAR_APB_RF + +/* registers definitions for MDAR_APB_RF */ +#define REG_MDAR_APB_RF_MDAR_CFG0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0000) +#define REG_MDAR_APB_RF_MDAR_CFG1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0004) +#define REG_MDAR_APB_RF_MDAR_CFG3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x000C) +#define REG_MDAR_APB_RF_MDAR_DAC1_CTR1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0010) +#define REG_MDAR_APB_RF_MDAR_DAC1_CTR2 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0014) +#define REG_MDAR_APB_RF_MDAR_DAC1_CTR3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0018) +#define REG_MDAR_APB_RF_MDAR_DAC1_CTR4 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x001C) +#define REG_MDAR_APB_RF_MDAR_DAC1_STS0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0020) +#define REG_MDAR_APB_RF_MDAR_DAC1_STS1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0024) +#define REG_MDAR_APB_RF_MDAR_CAL1_CTR0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0028) +#define REG_MDAR_APB_RF_MDAR_CAL1_CTR1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x002C) +#define REG_MDAR_APB_RF_MDAR_CAL1_CTR3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0030) +#define REG_MDAR_APB_RF_MDAR_CAL1_STS0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0034) +#define REG_MDAR_APB_RF_MDAR_CAL1_STS1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0038) +#define REG_MDAR_APB_RF_MDAR_DAC1_CTR00 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x003C) +#define REG_MDAR_APB_RF_MDAR_DAC1_CTR10 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0040) +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0044) +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR00 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0048) +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR01 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x004C) +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR02 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0050) +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR10 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0054) +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR11 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0058) +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR12 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x005C) +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR20 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0060) +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR21 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0064) +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR22 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0068) +#define REG_MDAR_APB_RF_MDAR_DAC2_CTR1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0070) +#define REG_MDAR_APB_RF_MDAR_DAC2_CTR2 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0074) +#define REG_MDAR_APB_RF_MDAR_DAC2_CTR3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0078) +#define REG_MDAR_APB_RF_MDAR_DAC2_CTR4 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x007C) +#define REG_MDAR_APB_RF_MDAR_DAC2_STS0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0080) +#define REG_MDAR_APB_RF_MDAR_DAC2_STS1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0084) +#define REG_MDAR_APB_RF_MDAR_CAL2_CTR0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0088) +#define REG_MDAR_APB_RF_MDAR_CAL2_CTR1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x008C) +#define REG_MDAR_APB_RF_MDAR_CAL2_CTR3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0090) +#define REG_MDAR_APB_RF_MDAR_CAL2_STS0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0094) +#define REG_MDAR_APB_RF_MDAR_CAL2_STS1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0098) +#define REG_MDAR_APB_RF_MDAR_DAC2_CTR00 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x009C) +#define REG_MDAR_APB_RF_MDAR_DAC2_CTR10 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00A0) +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00A4) +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR00 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00A8) +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR01 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00AC) +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR02 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00B0) +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR10 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00B4) +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR11 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00B8) +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR12 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00BC) +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR20 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00C0) +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR21 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00C4) +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR22 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00C8) +#define REG_MDAR_APB_RF_MDAR_DAC3_CTR1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00D0) +#define REG_MDAR_APB_RF_MDAR_DAC3_CTR2 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00D4) +#define REG_MDAR_APB_RF_MDAR_DAC3_CTR3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00D8) +#define REG_MDAR_APB_RF_MDAR_DAC3_CTR4 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00DC) +#define REG_MDAR_APB_RF_MDAR_DAC3_STS0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00E0) +#define REG_MDAR_APB_RF_MDAR_DAC3_STS1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00E4) +#define REG_MDAR_APB_RF_MDAR_CAL3_CTR0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00E8) +#define REG_MDAR_APB_RF_MDAR_CAL3_CTR1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00EC) +#define REG_MDAR_APB_RF_MDAR_CAL3_CTR3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00F0) +#define REG_MDAR_APB_RF_MDAR_CAL3_STS0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00F4) +#define REG_MDAR_APB_RF_MDAR_CAL3_STS1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00F8) +#define REG_MDAR_APB_RF_MDAR_DAC3_CTR00 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00FC) +#define REG_MDAR_APB_RF_MDAR_DAC3_CTR10 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0100) +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0104) +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR00 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0108) +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR01 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x010C) +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR02 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0110) +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR10 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0114) +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR11 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0118) +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR12 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x011C) +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR20 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0120) +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR21 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0124) +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR22 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0128) +#define REG_MDAR_APB_RF_MDAR_AFCDAC1_CFG SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x012C) +#define REG_MDAR_APB_RF_MDAR_AFCDAC2_CFG SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0130) +#define REG_MDAR_APB_RF_MDAR_APCDAC1_CFG SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0134) +#define REG_MDAR_APB_RF_MDAR_APCDAC2_CFG SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0138) +#define REG_MDAR_APB_RF_MDAR_RFSPI_CFG SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x13C) +#define REG_MDAR_APB_RF_MDAR_RFMIPI_CFG SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x140) +#define REG_MDAR_APB_RF_MDAR_APCDAC_OUTSEL SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x144) +#define REG_MDAR_APB_RF_MDAR_CLASH_CHK SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x148) +#define REG_MDAR_APB_RF_MDAR_CLASH_SNAP SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x14C) +#define REG_MDAR_APB_RF_MDAR_CLASH_STATUS1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x150) +#define REG_MDAR_APB_RF_MDAR_CLASH_STATUS2 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x154) +#define REG_MDAR_APB_RF_MDAR_CLASH_STATUS3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x158) +#define REG_MDAR_APB_RF_MDAR_EXTRA_CFG0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x160) +#define REG_MDAR_APB_RF_MDAR_EXTRA_CFG1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x164) +#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x168) +#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x16C) +#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF2 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x170) +#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x174) +#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF4 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x178) +#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF5 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x17C) +#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF6 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x180) +#define REG_MDAR_APB_RF_MDAR_CFG4 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0184) +#define REG_MDAR_APB_RF_MDAR_CFG5 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0188) +#define REG_MDAR_APB_RF_MDAR_CFG6 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x018C) +#define REG_MDAR_APB_RF_MDAR_CFG7 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0190) +#define REG_MDAR_APB_RF_MDAR_CFG8 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0194) +#define REG_MDAR_APB_RF_MDAR_CFG9 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0198) +#define REG_MDAR_APB_RF_MDAR_CFG10 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x019C) +#define REG_MDAR_APB_RF_MDAR_CFG11 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x01B0) +#define REG_MDAR_APB_RF_MDAR_CFG12 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x01B4) +#define REG_MDAR_APB_RF_MDAR_CFG13 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x01B8) +#define REG_MDAR_APB_RF_MDAR_CFG14 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x01BC) +#define REG_MDAR_APB_RF_MDAR_CFG15 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1C0) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG10 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1C4) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG11 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1C8) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG12 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1CC) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG13 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1D0) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG14 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1D4) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG20 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1D8) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG21 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1DC) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG22 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1E0) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG23 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1E4) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG24 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1E8) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG30 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1EC) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG31 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1F0) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG32 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1F4) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG33 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1F8) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG34 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1FC) + + + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG0 */ +#define BIT_MDAR_ADA_MODE ( BIT(31) ) +#define BITS_ADC3_CHANNEL_SSET(_X_) ( (_X_) << 26 & (BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_ADC2_CHANNEL_SSET(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_ADC1_CHANNEL_SSET(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)) ) +#define BIT_MDAR_WTG_MODE ( BIT(15) ) +#define BITS_ADC3_CHANNEL_MASK(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_ADC2_CHANNEL_MASK(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_ADC1_CHANNEL_MASK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG1 */ +#define BITS_DAC3_CHANNEL_SSET(_X_) ( (_X_) << 26 & (BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_DAC2_CHANNEL_SSET(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC1_CHANNEL_SSET(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_DAC3_CHANNEL_MASK(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_DAC2_CHANNEL_MASK(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DAC1_CHANNEL_MASK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG3 */ +#define BITS_DACX_SBC_SET(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_ADCX_SBC_SET(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_CTR1 */ +#define BITS_DAC1_WD_OVR(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DAC1_WADDR_OVR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DAC1_WLE_OVR ( BIT(2) ) +#define BIT_DAC1_W_OVR_I_QN ( BIT(1) ) +#define BIT_DAC1_W_OVR_EN ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_CTR2 */ +#define BIT_DAC1_AUTO_RST ( BIT(23) ) +#define BIT_DAC1_SOFT_RST ( BIT(22) ) +#define BIT_DAC1_OSBC ( BIT(21) ) +#define BIT_DAC1_ISBC ( BIT(20) ) +#define BIT_DAC1_OVR_EN_CAL ( BIT(19) ) +#define BIT_DAC1_EN_OOSCAL ( BIT(18) ) +#define BIT_DAC1_IQSWAP ( BIT(17) ) +#define BIT_DAC1_CAL_START ( BIT(16) ) +#define BITS_DAC1_OFFSETI(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DAC1_OFFSETQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_CTR3 */ +#define BITS_DAC1_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DAC1_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_CTR4 */ +#define BITS_DAC1_I_CAL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DAC1_Q_CAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_STS0 */ +#define BITS_DAC1_WTI(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DAC1_WTQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_STS1 */ +#define BITS_DAC1_DA_STATE(_X_) ( (_X_) << 17 & (BIT(17)|BIT(18)) ) +#define BIT_DAC1_DONE ( BIT(16) ) +#define BITS_DAC1_WQ_OVR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL1_CTR0 */ +#define BITS_ADC1_CLK_CAL_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_ADA1_CAL_WAIT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_CLK_ADA1_CAL_EN ( BIT(6) ) +#define BIT_DAC1_PD_CAL ( BIT(5) ) +#define BIT_ADC1_EN_CAL ( BIT(3) ) +#define BIT_ADC1_CAL ( BIT(1) ) +#define BIT_ADA1_MODE_SEL ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL1_CTR1 */ +#define BITS_ADC1_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) ) +#define BITS_ADC1_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL1_CTR3 */ +#define BIT_ADA1_CAL_START ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL1_STS0 */ +#define BIT_ADA1_CAL_DONE ( BIT(31) ) +#define BITS_ADC1_CAL_I_SUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL1_STS1 */ +#define BITS_ADC1_CAL_Q_SUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_CTR00 */ +#define BIT_DAC1_OUT_SEL_2 ( BIT(26) ) +#define BITS_DAC1_RSV_2(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC1_PCTRL_2(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)) ) +#define BIT_DAC1_CLK_SEL_2 ( BIT(18) ) +#define BIT_DAC1_OUT_SEL_1 ( BIT(17) ) +#define BITS_DAC1_RSV_1(_X_) ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)) ) +#define BITS_DAC1_PCTRL_1(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DAC1_CLK_SEL_1 ( BIT(9) ) +#define BIT_DAC1_OUT_SEL_0 ( BIT(8) ) +#define BITS_DAC1_RSV_0(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DAC1_PCTRL_0(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)) ) +#define BIT_DAC1_CLK_SEL_0 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_CTR10 */ +#define BIT_DAC1_OUT_SEL_5 ( BIT(26) ) +#define BITS_DAC1_RSV_5(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC1_PCTRL_5(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)) ) +#define BIT_DAC1_CLK_SEL_5 ( BIT(18) ) +#define BIT_DAC1_OUT_SEL_4 ( BIT(17) ) +#define BITS_DAC1_RSV_4(_X_) ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)) ) +#define BITS_DAC1_PCTRL_4(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DAC1_CLK_SEL_4 ( BIT(9) ) +#define BIT_DAC1_OUT_SEL_3 ( BIT(8) ) +#define BITS_DAC1_RSV_3(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DAC1_PCTRL_3(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)) ) +#define BIT_DAC1_CLK_SEL_3 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR0 */ +#define BIT_ADC1_SOFT_RST ( BIT(31) ) +#define BITS_ADC1_DLL_OUT(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_ADC1_CALRDOUT(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) ) +#define BIT_ADC1_DLL_SOFT_RST ( BIT(10) ) +#define BIT_ADC1_CAL_SOFT_RST ( BIT(9) ) +#define BIT_ADC1_CALRD ( BIT(8) ) +#define BIT_ADC1_CALEN ( BIT(7) ) +#define BITS_ADC1_CALADDR(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_ADC1_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR00 */ +#define BITS_ADC1_RSV_1(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC1_RSV_0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR01 */ +#define BIT_ADC1_DIG_CLK_SEL_0 ( BIT(30) ) +#define BIT_ADC1_VCM_SEL_0 ( BIT(29) ) +#define BITS_ADC1_DELAY_CAP_0(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC1_BIT_SEL_0(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC1_VREF_SEL_0(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC1_VREF_BOOST_0(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC1_QUANT_BOOST_0(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC1_DLLRD_0 ( BIT(18) ) +#define BIT_ADC1_DLLWR_0 ( BIT(17) ) +#define BIT_ADC1_DLLEN_0 ( BIT(16) ) +#define BIT_ADC1_CSBC ( BIT(15) ) +#define BIT_ADC1_IQSWAP ( BIT(14) ) +#define BITS_ADC1_DLLOOF_0(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_ADC1_OSBC ( BIT(7) ) +#define BIT_ADC1_ISBC ( BIT(6) ) +#define BITS_ADC1_DLLIN_0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR02 */ +#define BIT_ADC1_DIG_CLK_SEL_1 ( BIT(30) ) +#define BIT_ADC1_VCM_SEL_1 ( BIT(29) ) +#define BITS_ADC1_DELAY_CAP_1(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC1_BIT_SEL_1(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC1_VREF_SEL_1(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC1_VREF_BOOST_1(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC1_QUANT_BOOST_1(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC1_DLLRD_1 ( BIT(18) ) +#define BIT_ADC1_DLLWR_1 ( BIT(17) ) +#define BIT_ADC1_DLLEN_1 ( BIT(16) ) +#define BITS_ADC1_DLLOOF_1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC1_DLLIN_1(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR10 */ +#define BITS_ADC1_RSV_3(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC1_RSV_2(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR11 */ +#define BIT_ADC1_DIG_CLK_SEL_2 ( BIT(30) ) +#define BIT_ADC1_VCM_SEL_2 ( BIT(29) ) +#define BITS_ADC1_DELAY_CAP_2(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC1_BIT_SEL_2(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC1_VREF_SEL_2(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC1_VREF_BOOST_2(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC1_QUANT_BOOST_2(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC1_DLLRD_2 ( BIT(18) ) +#define BIT_ADC1_DLLWR_2 ( BIT(17) ) +#define BIT_ADC1_DLLEN_2 ( BIT(16) ) +#define BITS_ADC1_DLLOOF_2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC1_DLLIN_2(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR12 */ +#define BIT_ADC1_DIG_CLK_SEL_3 ( BIT(30) ) +#define BIT_ADC1_VCM_SEL_3 ( BIT(29) ) +#define BITS_ADC1_DELAY_CAP_3(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC1_BIT_SEL_3(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC1_VREF_SEL_3(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC1_VREF_BOOST_3(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC1_QUANT_BOOST_3(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC1_DLLRD_3 ( BIT(18) ) +#define BIT_ADC1_DLLWR_3 ( BIT(17) ) +#define BIT_ADC1_DLLEN_3 ( BIT(16) ) +#define BITS_ADC1_DLLOOF_3(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC1_DLLIN_3(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR20 */ +#define BITS_ADC1_RSV_5(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC1_RSV_4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR21 */ +#define BIT_ADC1_DIG_CLK_SEL_4 ( BIT(30) ) +#define BIT_ADC1_VCM_SEL_4 ( BIT(29) ) +#define BITS_ADC1_DELAY_CAP_4(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC1_BIT_SEL_4(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC1_VREF_SEL_4(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC1_VREF_BOOST_4(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC1_QUANT_BOOST_4(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC1_DLLRD_4 ( BIT(18) ) +#define BIT_ADC1_DLLWR_4 ( BIT(17) ) +#define BIT_ADC1_DLLEN_4 ( BIT(16) ) +#define BITS_ADC1_DLLOOF_4(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC1_DLLIN_4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR22 */ +#define BIT_ADC1_DIG_CLK_SEL_5 ( BIT(30) ) +#define BIT_ADC1_VCM_SEL_5 ( BIT(29) ) +#define BITS_ADC1_DELAY_CAP_5(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC1_BIT_SEL_5(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC1_VREF_SEL_5(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC1_VREF_BOOST_5(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC1_QUANT_BOOST_5(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC1_DLLRD_5 ( BIT(18) ) +#define BIT_ADC1_DLLWR_5 ( BIT(17) ) +#define BIT_ADC1_DLLEN_5 ( BIT(16) ) +#define BITS_ADC1_DLLOOF_5(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC1_DLLIN_5(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_CTR1 */ +#define BITS_DAC2_WD_OVR(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DAC2_WADDR_OVR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DAC2_WLE_OVR ( BIT(2) ) +#define BIT_DAC2_W_OVR_I_QN ( BIT(1) ) +#define BIT_DAC2_W_OVR_EN ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_CTR2 */ +#define BIT_DAC2_AUTO_RST ( BIT(23) ) +#define BIT_DAC2_SOFT_RST ( BIT(22) ) +#define BIT_DAC2_OSBC ( BIT(21) ) +#define BIT_DAC2_ISBC ( BIT(20) ) +#define BIT_DAC2_OVR_EN_CAL ( BIT(19) ) +#define BIT_DAC2_EN_OOSCAL ( BIT(18) ) +#define BIT_DAC2_IQSWAP ( BIT(17) ) +#define BIT_DAC2_CAL_START ( BIT(16) ) +#define BITS_DAC2_OFFSETI(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DAC2_OFFSETQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_CTR3 */ +#define BITS_DAC2_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DAC2_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_CTR4 */ +#define BITS_DAC2_I_CAL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DAC2_Q_CAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_STS0 */ +#define BITS_DAC2_WTI(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DAC2_WTQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_STS1 */ +#define BITS_DAC2_DA_STATE(_X_) ( (_X_) << 17 & (BIT(17)|BIT(18)) ) +#define BIT_DAC2_DONE ( BIT(16) ) +#define BITS_DAC2_WQ_OVR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL2_CTR0 */ +#define BITS_ADC2_CLK_CAL_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_ADA2_CAL_WAIT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_CLK_ADA2_CAL_EN ( BIT(6) ) +#define BIT_DAC2_PD_CAL ( BIT(5) ) +#define BIT_ADC2_EN_CAL ( BIT(3) ) +#define BIT_ADC2_CAL ( BIT(1) ) +#define BIT_ADA2_MODE_SEL ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL2_CTR1 */ +#define BITS_ADC2_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) ) +#define BITS_ADC2_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL2_CTR3 */ +#define BIT_ADA2_CAL_START ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL2_STS0 */ +#define BIT_ADA2_CAL_DONE ( BIT(31) ) +#define BITS_ADC2_CAL_I_SUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL2_STS1 */ +#define BITS_ADC2_CAL_Q_SUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_CTR00 */ +#define BIT_DAC2_OUT_SEL_2 ( BIT(26) ) +#define BITS_DAC2_RSV_2(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC2_PCTRL_2(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)) ) +#define BIT_DAC2_CLK_SEL_2 ( BIT(18) ) +#define BIT_DAC2_OUT_SEL_1 ( BIT(17) ) +#define BITS_DAC2_RSV_1(_X_) ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)) ) +#define BITS_DAC2_PCTRL_1(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DAC2_CLK_SEL_1 ( BIT(9) ) +#define BIT_DAC2_OUT_SEL_0 ( BIT(8) ) +#define BITS_DAC2_RSV_0(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DAC2_PCTRL_0(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)) ) +#define BIT_DAC2_CLK_SEL_0 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_CTR10 */ +#define BIT_DAC2_OUT_SEL_5 ( BIT(26) ) +#define BITS_DAC2_RSV_5(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC2_PCTRL_5(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)) ) +#define BIT_DAC2_CLK_SEL_5 ( BIT(18) ) +#define BIT_DAC2_OUT_SEL_4 ( BIT(17) ) +#define BITS_DAC2_RSV_4(_X_) ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)) ) +#define BITS_DAC2_PCTRL_4(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DAC2_CLK_SEL_4 ( BIT(9) ) +#define BIT_DAC2_OUT_SEL_3 ( BIT(8) ) +#define BITS_DAC2_RSV_3(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DAC2_PCTRL_3(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)) ) +#define BIT_DAC2_CLK_SEL_3 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR0 */ +#define BIT_ADC2_SOFT_RST ( BIT(31) ) +#define BITS_ADC2_DLL_OUT(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_ADC2_CALRDOUT(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) ) +#define BIT_ADC2_DLL_SOFT_RST ( BIT(10) ) +#define BIT_ADC2_CAL_SOFT_RST ( BIT(9) ) +#define BIT_ADC2_CALRD ( BIT(8) ) +#define BIT_ADC2_CALEN ( BIT(7) ) +#define BITS_ADC2_CALADDR(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_ADC2_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR00 */ +#define BITS_ADC2_RSV_1(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC2_RSV_0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR01 */ +#define BIT_ADC2_DIG_CLK_SEL_0 ( BIT(30) ) +#define BIT_ADC2_VCM_SEL_0 ( BIT(29) ) +#define BITS_ADC2_DELAY_CAP_0(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC2_BIT_SEL_0(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC2_VREF_SEL_0(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC2_VREF_BOOST_0(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC2_QUANT_BOOST_0(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC2_DLLRD_0 ( BIT(18) ) +#define BIT_ADC2_DLLWR_0 ( BIT(17) ) +#define BIT_ADC2_DLLEN_0 ( BIT(16) ) +#define BIT_ADC2_CSBC ( BIT(15) ) +#define BIT_ADC2_IQSWAP ( BIT(14) ) +#define BITS_ADC2_DLLOOF_0(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_ADC2_OSBC ( BIT(7) ) +#define BIT_ADC2_ISBC ( BIT(6) ) +#define BITS_ADC2_DLLIN_0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR02 */ +#define BIT_ADC2_DIG_CLK_SEL_1 ( BIT(30) ) +#define BIT_ADC2_VCM_SEL_1 ( BIT(29) ) +#define BITS_ADC2_DELAY_CAP_1(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC2_BIT_SEL_1(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC2_VREF_SEL_1(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC2_VREF_BOOST_1(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC2_QUANT_BOOST_1(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC2_DLLRD_1 ( BIT(18) ) +#define BIT_ADC2_DLLWR_1 ( BIT(17) ) +#define BIT_ADC2_DLLEN_1 ( BIT(16) ) +#define BITS_ADC2_DLLOOF_1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC2_DLLIN_1(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR10 */ +#define BITS_ADC2_RSV_3(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC2_RSV_2(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR11 */ +#define BIT_ADC2_DIG_CLK_SEL_2 ( BIT(30) ) +#define BIT_ADC2_VCM_SEL_2 ( BIT(29) ) +#define BITS_ADC2_DELAY_CAP_2(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC2_BIT_SEL_2(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC2_VREF_SEL_2(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC2_VREF_BOOST_2(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC2_QUANT_BOOST_2(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC2_DLLRD_2 ( BIT(18) ) +#define BIT_ADC2_DLLWR_2 ( BIT(17) ) +#define BIT_ADC2_DLLEN_2 ( BIT(16) ) +#define BITS_ADC2_DLLOOF_2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC2_DLLIN_2(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR12 */ +#define BIT_ADC2_DIG_CLK_SEL_3 ( BIT(30) ) +#define BIT_ADC2_VCM_SEL_3 ( BIT(29) ) +#define BITS_ADC2_DELAY_CAP_3(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC2_BIT_SEL_3(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC2_VREF_SEL_3(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC2_VREF_BOOST_3(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC2_QUANT_BOOST_3(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC2_DLLRD_3 ( BIT(18) ) +#define BIT_ADC2_DLLWR_3 ( BIT(17) ) +#define BIT_ADC2_DLLEN_3 ( BIT(16) ) +#define BITS_ADC2_DLLOOF_3(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC2_DLLIN_3(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR20 */ +#define BITS_ADC2_RSV_5(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC2_RSV_4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR21 */ +#define BIT_ADC2_DIG_CLK_SEL_4 ( BIT(30) ) +#define BIT_ADC2_VCM_SEL_4 ( BIT(29) ) +#define BITS_ADC2_DELAY_CAP_4(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC2_BIT_SEL_4(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC2_VREF_SEL_4(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC2_VREF_BOOST_4(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC2_QUANT_BOOST_4(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC2_DLLRD_4 ( BIT(18) ) +#define BIT_ADC2_DLLWR_4 ( BIT(17) ) +#define BIT_ADC2_DLLEN_4 ( BIT(16) ) +#define BITS_ADC2_DLLOOF_4(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC2_DLLIN_4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR22 */ +#define BIT_ADC2_DIG_CLK_SEL_5 ( BIT(30) ) +#define BIT_ADC2_VCM_SEL_5 ( BIT(29) ) +#define BITS_ADC2_DELAY_CAP_5(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC2_BIT_SEL_5(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC2_VREF_SEL_5(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC2_VREF_BOOST_5(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC2_QUANT_BOOST_5(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC2_DLLRD_5 ( BIT(18) ) +#define BIT_ADC2_DLLWR_5 ( BIT(17) ) +#define BIT_ADC2_DLLEN_5 ( BIT(16) ) +#define BITS_ADC2_DLLOOF_5(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC2_DLLIN_5(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_CTR1 */ +#define BITS_DAC3_WD_OVR(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DAC3_WADDR_OVR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DAC3_WLE_OVR ( BIT(2) ) +#define BIT_DAC3_W_OVR_I_QN ( BIT(1) ) +#define BIT_DAC3_W_OVR_EN ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_CTR2 */ +#define BIT_DAC3_AUTO_RST ( BIT(23) ) +#define BIT_DAC3_SOFT_RST ( BIT(22) ) +#define BIT_DAC3_OSBC ( BIT(21) ) +#define BIT_DAC3_ISBC ( BIT(20) ) +#define BIT_DAC3_OVR_EN_CAL ( BIT(19) ) +#define BIT_DAC3_EN_OOSCAL ( BIT(18) ) +#define BIT_DAC3_IQSWAP ( BIT(17) ) +#define BIT_DAC3_CAL_START ( BIT(16) ) +#define BITS_DAC3_OFFSETI(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DAC3_OFFSETQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_CTR3 */ +#define BITS_DAC3_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DAC3_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_CTR4 */ +#define BITS_DAC3_I_CAL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DAC3_Q_CAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_STS0 */ +#define BITS_DAC3_WTI(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DAC3_WTQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_STS1 */ +#define BITS_DAC3_DA_STATE(_X_) ( (_X_) << 17 & (BIT(17)|BIT(18)) ) +#define BIT_DAC3_DONE ( BIT(16) ) +#define BITS_DAC3_WQ_OVR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL3_CTR0 */ +#define BITS_ADC3_CLK_CAL_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_ADA3_CAL_WAIT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_CLK_ADA3_CAL_EN ( BIT(6) ) +#define BIT_DAC3_PD_CAL ( BIT(5) ) +#define BIT_ADC3_EN_CAL ( BIT(3) ) +#define BIT_ADC3_CAL ( BIT(1) ) +#define BIT_ADA3_MODE_SEL ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL3_CTR1 */ +#define BITS_ADC3_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) ) +#define BITS_ADC3_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL3_CTR3 */ +#define BIT_ADA3_CAL_START ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL3_STS0 */ +#define BIT_ADA3_CAL_DONE ( BIT(31) ) +#define BITS_ADC3_CAL_I_SUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL3_STS1 */ +#define BITS_ADC3_CAL_Q_SUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_CTR00 */ +#define BIT_DAC3_OUT_SEL_2 ( BIT(26) ) +#define BITS_DAC3_RSV_2(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC3_PCTRL_2(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)) ) +#define BIT_DAC3_CLK_SEL_2 ( BIT(18) ) +#define BIT_DAC3_OUT_SEL_1 ( BIT(17) ) +#define BITS_DAC3_RSV_1(_X_) ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)) ) +#define BITS_DAC3_PCTRL_1(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DAC3_CLK_SEL_1 ( BIT(9) ) +#define BIT_DAC3_OUT_SEL_0 ( BIT(8) ) +#define BITS_DAC3_RSV_0(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DAC3_PCTRL_0(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)) ) +#define BIT_DAC3_CLK_SEL_0 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_CTR10 */ +#define BIT_DAC3_OUT_SEL_5 ( BIT(26) ) +#define BITS_DAC3_RSV_5(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC3_PCTRL_5(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)) ) +#define BIT_DAC3_CLK_SEL_5 ( BIT(18) ) +#define BIT_DAC3_OUT_SEL_4 ( BIT(17) ) +#define BITS_DAC3_RSV_4(_X_) ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)) ) +#define BITS_DAC3_PCTRL_4(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DAC3_CLK_SEL_4 ( BIT(9) ) +#define BIT_DAC3_OUT_SEL_3 ( BIT(8) ) +#define BITS_DAC3_RSV_3(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DAC3_PCTRL_3(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)) ) +#define BIT_DAC3_CLK_SEL_3 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR0 */ +#define BIT_ADC3_SOFT_RST ( BIT(31) ) +#define BITS_ADC3_DLL_OUT(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_ADC3_CALRDOUT(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) ) +#define BIT_ADC3_DLL_SOFT_RST ( BIT(10) ) +#define BIT_ADC3_CAL_SOFT_RST ( BIT(9) ) +#define BIT_ADC3_CALRD ( BIT(8) ) +#define BIT_ADC3_CALEN ( BIT(7) ) +#define BITS_ADC3_CALADDR(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_ADC3_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR00 */ +#define BITS_ADC3_RSV_1(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC3_RSV_0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR01 */ +#define BIT_ADC3_DIG_CLK_SEL_0 ( BIT(30) ) +#define BIT_ADC3_VCM_SEL_0 ( BIT(29) ) +#define BITS_ADC3_DELAY_CAP_0(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC3_BIT_SEL_0(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC3_VREF_SEL_0(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC3_VREF_BOOST_0(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC3_QUANT_BOOST_0(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC3_DLLRD_0 ( BIT(18) ) +#define BIT_ADC3_DLLWR_0 ( BIT(17) ) +#define BIT_ADC3_DLLEN_0 ( BIT(16) ) +#define BIT_ADC3_CSBC ( BIT(15) ) +#define BIT_ADC3_IQSWAP ( BIT(14) ) +#define BITS_ADC3_DLLOOF_0(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_ADC3_OSBC ( BIT(7) ) +#define BIT_ADC3_ISBC ( BIT(6) ) +#define BITS_ADC3_DLLIN_0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR02 */ +#define BIT_ADC3_DIG_CLK_SEL_1 ( BIT(30) ) +#define BIT_ADC3_VCM_SEL_1 ( BIT(29) ) +#define BITS_ADC3_DELAY_CAP_1(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC3_BIT_SEL_1(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC3_VREF_SEL_1(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC3_VREF_BOOST_1(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC3_QUANT_BOOST_1(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC3_DLLRD_1 ( BIT(18) ) +#define BIT_ADC3_DLLWR_1 ( BIT(17) ) +#define BIT_ADC3_DLLEN_1 ( BIT(16) ) +#define BITS_ADC3_DLLOOF_1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC3_DLLIN_1(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR10 */ +#define BITS_ADC3_RSV_3(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC3_RSV_2(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR11 */ +#define BIT_ADC3_DIG_CLK_SEL_2 ( BIT(30) ) +#define BIT_ADC3_VCM_SEL_2 ( BIT(29) ) +#define BITS_ADC3_DELAY_CAP_2(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC3_BIT_SEL_2(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC3_VREF_SEL_2(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC3_VREF_BOOST_2(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC3_QUANT_BOOST_2(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC3_DLLRD_2 ( BIT(18) ) +#define BIT_ADC3_DLLWR_2 ( BIT(17) ) +#define BIT_ADC3_DLLEN_2 ( BIT(16) ) +#define BITS_ADC3_DLLOOF_2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC3_DLLIN_2(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR12 */ +#define BIT_ADC3_DIG_CLK_SEL_3 ( BIT(30) ) +#define BIT_ADC3_VCM_SEL_3 ( BIT(29) ) +#define BITS_ADC3_DELAY_CAP_3(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC3_BIT_SEL_3(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC3_VREF_SEL_3(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC3_VREF_BOOST_3(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC3_QUANT_BOOST_3(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC3_DLLRD_3 ( BIT(18) ) +#define BIT_ADC3_DLLWR_3 ( BIT(17) ) +#define BIT_ADC3_DLLEN_3 ( BIT(16) ) +#define BITS_ADC3_DLLOOF_3(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC3_DLLIN_3(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR20 */ +#define BITS_ADC3_RSV_5(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC3_RSV_4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR21 */ +#define BIT_ADC3_DIG_CLK_SEL_4 ( BIT(30) ) +#define BIT_ADC3_VCM_SEL_4 ( BIT(29) ) +#define BITS_ADC3_DELAY_CAP_4(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC3_BIT_SEL_4(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC3_VREF_SEL_4(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC3_VREF_BOOST_4(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC3_QUANT_BOOST_4(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC3_DLLRD_4 ( BIT(18) ) +#define BIT_ADC3_DLLWR_4 ( BIT(17) ) +#define BIT_ADC3_DLLEN_4 ( BIT(16) ) +#define BITS_ADC3_DLLOOF_4(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC3_DLLIN_4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR22 */ +#define BIT_ADC3_DIG_CLK_SEL_5 ( BIT(30) ) +#define BIT_ADC3_VCM_SEL_5 ( BIT(29) ) +#define BITS_ADC3_DELAY_CAP_5(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC3_BIT_SEL_5(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC3_VREF_SEL_5(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC3_VREF_BOOST_5(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC3_QUANT_BOOST_5(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC3_DLLRD_5 ( BIT(18) ) +#define BIT_ADC3_DLLWR_5 ( BIT(17) ) +#define BIT_ADC3_DLLEN_5 ( BIT(16) ) +#define BITS_ADC3_DLLOOF_5(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC3_DLLIN_5(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_AFCDAC1_CFG */ +#define BITS_AFCDAC1_CHANNEL_MASK(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_AFCDAC1_CHANNEL_SSET(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BIT_AFCDAC1_LOW_V_CON_SST ( BIT(23) ) +#define BIT_AFCDAC1_BP_RES_SST ( BIT(20) ) +#define BITS_AFCDAC1_G_SST(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_AFCDAC1_CTL_SST(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BIT_AFCDAC1_PD_SST ( BIT(15) ) +#define BITS_AFCDAC1_D_SST(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_AFCDAC2_CFG */ +#define BITS_AFCDAC2_CHANNEL_MASK(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_AFCDAC2_CHANNEL_SSET(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BIT_AFCDAC2_LOW_V_CON_SST ( BIT(23) ) +#define BIT_AFCDAC2_BP_RES_SST ( BIT(20) ) +#define BITS_AFCDAC2_G_SST(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_AFCDAC2_CTL_SST(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BIT_AFCDAC2_PD_SST ( BIT(15) ) +#define BITS_AFCDAC2_D_SST(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_APCDAC1_CFG */ +#define BITS_APCDAC1_CHANNEL_MASK(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_APCDAC1_CHANNEL_SSET(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BIT_APCDAC1_LOW_V_CON_SST ( BIT(23) ) +#define BITS_APCDAC1_OUTSEL_SST(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BIT_APCDAC1_BP_RES_SST ( BIT(20) ) +#define BITS_APCDAC1_G_SST(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_APCDAC1_CTL_SST(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BIT_APCDAC1_PD_SST ( BIT(15) ) +#define BIT_APCDAC1_SEL_SST ( BIT(14) ) +#define BITS_APCDAC1_D_SST(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_APCDAC2_CFG */ +#define BITS_APCDAC2_CHANNEL_MASK(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_APCDAC2_CHANNEL_SSET(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BIT_APCDAC2_LOW_V_CON_SST ( BIT(23) ) +#define BITS_APCDAC2_OUTSEL_SST(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BIT_APCDAC2_BP_RES_SST ( BIT(20) ) +#define BITS_APCDAC2_G_SST(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_APCDAC2_CTL_SST(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BIT_APCDAC2_PD_SST ( BIT(15) ) +#define BIT_APCDAC2_SEL_SST ( BIT(14) ) +#define BITS_APCDAC2_D_SST(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFSPI_CFG */ +#define BITS_RFSBI2_CHANNEL_MASK(_X_) ( (_X_) << 29 & (BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_RFSBI2_CHANNEL_SSET(_X_) ( (_X_) << 26 & (BIT(26)|BIT(27)|BIT(28)) ) +#define BIT_RFSBI2_IDATA_SST ( BIT(25) ) +#define BIT_RFSBI2_ODATA_SST ( BIT(24) ) +#define BIT_RFSBI2_DATA_OE_SST ( BIT(23) ) +#define BIT_RFSBI2_DATA_IE_SST ( BIT(22) ) +#define BIT_RFSBI2_CLK_SST ( BIT(21) ) +#define BIT_RFSBI2_CLK_OE_SST ( BIT(20) ) +#define BIT_RFSBI2_EN0_SST ( BIT(19) ) +#define BIT_RFSBI2_EN0_OE_SST ( BIT(18) ) +#define BIT_RFSBI2_EN1_SST ( BIT(17) ) +#define BIT_RFSBI2_EN1_OE_SST ( BIT(16) ) +#define BITS_RFSBI1_CHANNEL_MASK(_X_) ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_RFSBI1_CHANNEL_SSET(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_RFSBI1_IDATA_SST ( BIT(9) ) +#define BIT_RFSBI1_ODATA_SST ( BIT(8) ) +#define BIT_RFSBI1_DATA_OE_SST ( BIT(7) ) +#define BIT_RFSBI1_DATA_IE_SST ( BIT(6) ) +#define BIT_RFSBI1_CLK_SST ( BIT(5) ) +#define BIT_RFSBI1_CLK_OE_SST ( BIT(4) ) +#define BIT_RFSBI1_EN0_SST ( BIT(3) ) +#define BIT_RFSBI1_EN0_OE_SST ( BIT(2) ) +#define BIT_RFSBI1_EN1_SST ( BIT(1) ) +#define BIT_RFSBI1_EN1_OE_SST ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFMIPI_CFG */ +#define BITS_RFMIPI2_CHANNEL_MASK(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_RFMIPI2_CHANNEL_SSET(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BIT_PAD_OUT_RFFE2_CLK_SST ( BIT(20) ) +#define BIT_PAD_OUT_RFFE2_DATA_SST ( BIT(19) ) +#define BIT_PAD_IN_RFFE2_DATA_SST ( BIT(18) ) +#define BIT_PAD_OE_RFFE2_DATA_SST ( BIT(17) ) +#define BIT_PAD_IE_RFFE2_DATA_SST ( BIT(16) ) +#define BITS_RFMIPI1_CHANNEL_MASK(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_RFMIPI1_CHANNEL_SSET(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BIT_PAD_OUT_RFFE1_CLK_SST ( BIT(4) ) +#define BIT_PAD_OUT_RFFE1_DATA_SST ( BIT(3) ) +#define BIT_PAD_IN_RFFE1_DATA_SST ( BIT(2) ) +#define BIT_PAD_OE_RFFE1_DATA_SST ( BIT(1) ) +#define BIT_PAD_IE_RFFE1_DATA_SST ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_APCDAC_OUTSEL */ +#define BIT_AFCDAC_LOW_V_CON_GGE ( BIT(31) ) +#define BIT_AFCDAC_LOW_V_CON_WG ( BIT(30) ) +#define BIT_AFCDAC_LOW_V_CON_WD ( BIT(29) ) +#define BIT_AFCDAC_LOW_V_CON_TG ( BIT(28) ) +#define BIT_AFCDAC_LOW_V_CON_TD ( BIT(27) ) +#define BIT_AFCDAC_LOW_V_CON_LTE ( BIT(26) ) +#define BITS_APCDACX_G3_SST(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_APCDACX_G2_SST(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)) ) +#define BITS_APCDACX_G1_SST(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)) ) +#define BITS_APCDACX_G0_SST(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BIT_APCDAC_LOW_V_CON_GGE ( BIT(17) ) +#define BIT_APCDAC_LOW_V_CON_WG ( BIT(16) ) +#define BIT_APCDAC_LOW_V_CON_WD ( BIT(15) ) +#define BIT_APCDAC_LOW_V_CON_TG ( BIT(14) ) +#define BIT_APCDAC_LOW_V_CON_TD ( BIT(13) ) +#define BIT_APCDAC_LOW_V_CON_LTE ( BIT(12) ) +#define BITS_APCDAC_OUTSEL_GGE(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_APCDAC_OUTSEL_WG(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_APCDAC_OUTSEL_WD(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_APCDAC_OUTSEL_TG(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_APCDAC_OUTSEL_TD(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_APCDAC_OUTSEL_LTE(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CLASH_CHK */ +#define BIT_RFSBI2_CLASH_CHK_INTRP_EN ( BIT(29) ) +#define BIT_RFSBI1_CLASH_CHK_INTRP_EN ( BIT(28) ) +#define BIT_RFMIPI2_CLASH_CHK_INTRP_EN ( BIT(27) ) +#define BIT_RFMIPI1_CLASH_CHK_INTRP_EN ( BIT(26) ) +#define BIT_APCDAC2_CLASH_CHK_INTRP_EN ( BIT(25) ) +#define BIT_APCDAC1_CLASH_CHK_INTRP_EN ( BIT(24) ) +#define BIT_AFCDAC2_CLASH_CHK_INTRP_EN ( BIT(23) ) +#define BIT_AFCDAC1_CLASH_CHK_INTRP_EN ( BIT(22) ) +#define BIT_ADA3_TX_CLASH_CHK_INTRP_EN ( BIT(21) ) +#define BIT_ADA3_RX_CLASH_CHK_INTRP_EN ( BIT(20) ) +#define BIT_ADA2_TX_CLASH_CHK_INTRP_EN ( BIT(19) ) +#define BIT_ADA2_RX_CLASH_CHK_INTRP_EN ( BIT(18) ) +#define BIT_ADA1_TX_CLASH_CHK_INTRP_EN ( BIT(17) ) +#define BIT_ADA1_RX_CLASH_CHK_INTRP_EN ( BIT(16) ) +#define BIT_CHK_CLASH_STFREE ( BIT(8) ) +#define BIT_CHK_CLASH_CLR ( BIT(7) ) +#define BIT_CHK_CLASH_RTC_SNAP_MODE ( BIT(4) ) +#define BIT_CHK_CLASH_RTC_SNAP_EDGE ( BIT(3) ) +#define BIT_CHK_CLASH_RTC_SNAP_INTRP_TYPE ( BIT(2) ) +#define BIT_CHK_CLASH_RTC_SNAP_INTRP_CLR ( BIT(1) ) +#define BIT_CHK_CLASH_RTC_SNAP_INTRP ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CLASH_SNAP */ +#define BITS_CHK_CLASH_RTC_SNAP_TIME(_X_) (_X_) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CLASH_STATUS1 */ +#define BITS_CHK_CLASH_ADA3_TX_CHANNEL_SEL(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_CHK_CLASH_ADA3_RX_CHANNEL_SEL(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) ) +#define BITS_CHK_CLASH_ADA2_TX_CHANNEL_SEL(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_CHK_CLASH_ADA2_RX_CHANNEL_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_CHK_CLASH_ADA1_TX_CHANNEL_SEL(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_CHK_CLASH_ADA1_RX_CHANNEL_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CLASH_STATUS2 */ +#define BITS_CHK_CLASH_APCDAC2_CHANNEL_SEL(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_CHK_CLASH_APCDAC1_CHANNEL_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CHK_CLASH_AFCDAC2_CHANNEL_SEL(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_CHK_CLASH_AFCDAC1_CHANNEL_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CLASH_STATUS3 */ +#define BITS_CHK_CLASH_RFSBI2_CHANNEL_SEL(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_CHK_CLASH_RFSBI1_CHANNEL_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CHK_CLASH_RFMIPI2_CHANNEL_SEL(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_CHK_CLASH_RFMIPI1_CHANNEL_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_EXTRA_CFG0 */ +#define BITS_APT_DCM2_EXTRA_CFG(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_APT_DCM2_ADI_EN ( BIT(23) ) +#define BITS_APT_DCM2_CHANNEL_SSET(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BIT_APT_DCM2_SST ( BIT(19) ) +#define BITS_APT_DCM2_CHANNEL_MASK(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)) ) +#define BITS_APT_DCM1_EXTRA_CFG(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_APT_DCM1_ADI_EN ( BIT(7) ) +#define BITS_APT_DCM1_CHANNEL_SSET(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_APT_DCM1_SST ( BIT(3) ) +#define BITS_APT_DCM1_CHANNEL_MASK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_EXTRA_CFG1 */ +#define BITS_MDAR_EXTRA_CFG1(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_MDAR_EXTRA_CFG1_2 ( BIT(12) ) +#define BIT_MDAR_EXTRA_CFG1_1 ( BIT(11) ) +#define BIT_MDAR_EXTRA_CFG1_0 ( BIT(10) ) +#define BITS_MDAR_BB_LDO_REFCTRL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_MDAR_BB_LDO_SLEEP_PD_EN ( BIT(6) ) +#define BIT_MDAR_BB_LDO_FORCE_ON ( BIT(5) ) +#define BIT_MDAR_BB_LDO_FORCE_PD ( BIT(4) ) +#define BIT_MDAR_BB_BG_SLEEP_PD_EN ( BIT(2) ) +#define BIT_MDAR_BB_BG_FORCE_ON ( BIT(1) ) +#define BIT_MDAR_BB_BG_FORCE_PD ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF0 */ +#define BITS_CHK_CLASH_RFCTRL15_CHX_SEL(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BIT_RFCTRL15_CHK_INTRP_EN ( BIT(16) ) +#define BIT_RFCTRL15_RTC_REFRESH ( BIT(12) ) +#define BIT_RFCTRL15_SNAP_REFRESH ( BIT(8) ) +#define BITS_RFCTRL15_SSET(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BITS_RFCTRL15_MASK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF1 */ +#define BITS_RFCTRL15_CH0_SNAP1_RTC_TIME(_X_) (_X_) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF2 */ +#define BITS_RFCTRL15_CH0_SNAP0_RTC_TIME(_X_) (_X_) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF3 */ +#define BITS_RFCTRL15_CH1_SNAP1_RTC_TIME(_X_) (_X_) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF4 */ +#define BITS_RFCTRL15_CH1_SNAP0_RTC_TIME(_X_) (_X_) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF5 */ +#define BITS_RFCTRL15_CH2_SNAP1_RTC_TIME(_X_) (_X_) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF6 */ +#define BITS_RFCTRL15_CH2_SNAP0_RTC_TIME(_X_) (_X_) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG4 */ +#define BITS_RFCTRL_CHANNEL_MASK3(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_RFCTRL_CHANNEL_MASK2(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BITS_RFCTRL_CHANNEL_MASK1(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RFCTRL_CHANNEL_MASK0(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_RFCTRL150_SST(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG5 */ +#define BITS_RFCTRL_CHANNEL_MASK13(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_RFCTRL_CHANNEL_MASK12(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BITS_RFCTRL_CHANNEL_MASK11(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RFCTRL_CHANNEL_MASK10(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_RFCTRL_CHANNEL_MASK9(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) ) +#define BITS_RFCTRL_CHANNEL_MASK8(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_RFCTRL_CHANNEL_MASK7(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_RFCTRL_CHANNEL_MASK6(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_RFCTRL_CHANNEL_MASK5(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_RFCTRL_CHANNEL_MASK4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG6 */ +#define BITS_RFCTRL_CHANNEL_SSET7(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_RFCTRL_CHANNEL_SSET6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BITS_RFCTRL_CHANNEL_SSET5(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RFCTRL_CHANNEL_SSET4(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_RFCTRL_CHANNEL_SSET3(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) ) +#define BITS_RFCTRL_CHANNEL_SSET2(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_RFCTRL_CHANNEL_SSET1(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_RFCTRL_CHANNEL_SSET0(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_RFCTRL_CHANNEL_MASK15(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_RFCTRL_CHANNEL_MASK14(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG7 */ +#define BITS_RFCTRL_CHANNEL_SSET15(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RFCTRL_CHANNEL_SSET14(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_RFCTRL_CHANNEL_SSET13(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) ) +#define BITS_RFCTRL_CHANNEL_SSET12(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_RFCTRL_CHANNEL_SSET11(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_RFCTRL_CHANNEL_SSET10(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_RFCTRL_CHANNEL_SSET9(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_RFCTRL_CHANNEL_SSET8(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG8 */ +#define BITS_RFCTRL_CHANNEL_MASK19(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_RFCTRL_CHANNEL_MASK18(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BITS_RFCTRL_CHANNEL_MASK17(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RFCTRL_CHANNEL_MASK16(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_RFCTRL3130_SST(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_RFCTRL2916_SST(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG9 */ +#define BITS_RFCTRL_CHANNEL_MASK29(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_RFCTRL_CHANNEL_MASK28(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BITS_RFCTRL_CHANNEL_MASK27(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RFCTRL_CHANNEL_MASK26(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_RFCTRL_CHANNEL_MASK25(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) ) +#define BITS_RFCTRL_CHANNEL_MASK24(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_RFCTRL_CHANNEL_MASK23(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_RFCTRL_CHANNEL_MASK22(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_RFCTRL_CHANNEL_MASK21(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_RFCTRL_CHANNEL_MASK20(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG10 */ +#define BITS_RFCTRL_CHANNEL_SSET23(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_RFCTRL_CHANNEL_SSET22(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BITS_RFCTRL_CHANNEL_SSET21(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RFCTRL_CHANNEL_SSET20(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_RFCTRL_CHANNEL_SSET19(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) ) +#define BITS_RFCTRL_CHANNEL_SSET18(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_RFCTRL_CHANNEL_SSET17(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_RFCTRL_CHANNEL_SSET16(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_RFCTRL_CHANNEL_MASK31(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_RFCTRL_CHANNEL_MASK30(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG11 */ +#define BITS_RFCTRL_CHANNEL_SSET31(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RFCTRL_CHANNEL_SSET30(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_RFCTRL_CHANNEL_SSET29(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) ) +#define BITS_RFCTRL_CHANNEL_SSET28(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_RFCTRL_CHANNEL_SSET27(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_RFCTRL_CHANNEL_SSET26(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_RFCTRL_CHANNEL_SSET25(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_RFCTRL_CHANNEL_SSET24(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG12 */ +#define BITS_RFCTRL_WTGCFGH(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_RFCTRL_WTGCFGL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG13 */ +#define BITS_RFCTRL_GGECFGH(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_RFCTRL_GGECFGL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG14 */ +#define BITS_MDAR_CFG14(_X_) (_X_) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG15 */ +#define BITS_MDAR_ANALOG_BB_RSV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG10 */ +#define BIT_ADC1_IMBP_CLK_SEL_5 ( BIT(21) ) +#define BIT_ADC1_IMBP_CLK_SEL_4 ( BIT(20) ) +#define BIT_ADC1_IMBP_CLK_SEL_3 ( BIT(19) ) +#define BIT_ADC1_IMBP_CLK_SEL_2 ( BIT(18) ) +#define BIT_ADC1_IMBP_CLK_SEL_1 ( BIT(17) ) +#define BIT_ADC1_IMBP_CLK_SEL_0 ( BIT(16) ) +#define BIT_DAC1_IMBP_BYPASS_5 ( BIT(13) ) +#define BIT_DAC1_IMBP_BYPASS_4 ( BIT(12) ) +#define BIT_DAC1_IMBP_BYPASS_3 ( BIT(11) ) +#define BIT_DAC1_IMBP_BYPASS_2 ( BIT(10) ) +#define BIT_DAC1_IMBP_BYPASS_1 ( BIT(9) ) +#define BIT_DAC1_IMBP_BYPASS_0 ( BIT(8) ) +#define BIT_ADC1_IMBP_BYPASS_5 ( BIT(5) ) +#define BIT_ADC1_IMBP_BYPASS_4 ( BIT(4) ) +#define BIT_ADC1_IMBP_BYPASS_3 ( BIT(3) ) +#define BIT_ADC1_IMBP_BYPASS_2 ( BIT(2) ) +#define BIT_ADC1_IMBP_BYPASS_1 ( BIT(1) ) +#define BIT_ADC1_IMBP_BYPASS_0 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG11 */ +#define BITS_ADC1_BAL_B(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_ADC1_BAL_A(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG12 */ +#define BITS_ADC1_BAL_D(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_ADC1_BAL_C(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG13 */ +#define BITS_DAC1_BAL_B(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_DAC1_BAL_A(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG14 */ +#define BITS_DAC1_BAL_D(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_DAC1_BAL_C(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG20 */ +#define BIT_ADC2_IMBP_CLK_SEL_5 ( BIT(21) ) +#define BIT_ADC2_IMBP_CLK_SEL_4 ( BIT(20) ) +#define BIT_ADC2_IMBP_CLK_SEL_3 ( BIT(19) ) +#define BIT_ADC2_IMBP_CLK_SEL_2 ( BIT(18) ) +#define BIT_ADC2_IMBP_CLK_SEL_1 ( BIT(17) ) +#define BIT_ADC2_IMBP_CLK_SEL_0 ( BIT(16) ) +#define BIT_DAC2_IMBP_BYPASS_5 ( BIT(13) ) +#define BIT_DAC2_IMBP_BYPASS_4 ( BIT(12) ) +#define BIT_DAC2_IMBP_BYPASS_3 ( BIT(11) ) +#define BIT_DAC2_IMBP_BYPASS_2 ( BIT(10) ) +#define BIT_DAC2_IMBP_BYPASS_1 ( BIT(9) ) +#define BIT_DAC2_IMBP_BYPASS_0 ( BIT(8) ) +#define BIT_ADC2_IMBP_BYPASS_5 ( BIT(5) ) +#define BIT_ADC2_IMBP_BYPASS_4 ( BIT(4) ) +#define BIT_ADC2_IMBP_BYPASS_3 ( BIT(3) ) +#define BIT_ADC2_IMBP_BYPASS_2 ( BIT(2) ) +#define BIT_ADC2_IMBP_BYPASS_1 ( BIT(1) ) +#define BIT_ADC2_IMBP_BYPASS_0 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG21 */ +#define BITS_ADC2_BAL_B(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_ADC2_BAL_A(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG22 */ +#define BITS_ADC2_BAL_D(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_ADC2_BAL_C(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG23 */ +#define BITS_DAC2_BAL_B(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_DAC2_BAL_A(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG24 */ +#define BITS_DAC2_BAL_D(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_DAC2_BAL_C(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG30 */ +#define BIT_ADC3_IMBP_CLK_SEL_5 ( BIT(21) ) +#define BIT_ADC3_IMBP_CLK_SEL_4 ( BIT(20) ) +#define BIT_ADC3_IMBP_CLK_SEL_3 ( BIT(19) ) +#define BIT_ADC3_IMBP_CLK_SEL_2 ( BIT(18) ) +#define BIT_ADC3_IMBP_CLK_SEL_1 ( BIT(17) ) +#define BIT_ADC3_IMBP_CLK_SEL_0 ( BIT(16) ) +#define BIT_DAC3_IMBP_BYPASS_5 ( BIT(13) ) +#define BIT_DAC3_IMBP_BYPASS_4 ( BIT(12) ) +#define BIT_DAC3_IMBP_BYPASS_3 ( BIT(11) ) +#define BIT_DAC3_IMBP_BYPASS_2 ( BIT(10) ) +#define BIT_DAC3_IMBP_BYPASS_1 ( BIT(9) ) +#define BIT_DAC3_IMBP_BYPASS_0 ( BIT(8) ) +#define BIT_ADC3_IMBP_BYPASS_5 ( BIT(5) ) +#define BIT_ADC3_IMBP_BYPASS_4 ( BIT(4) ) +#define BIT_ADC3_IMBP_BYPASS_3 ( BIT(3) ) +#define BIT_ADC3_IMBP_BYPASS_2 ( BIT(2) ) +#define BIT_ADC3_IMBP_BYPASS_1 ( BIT(1) ) +#define BIT_ADC3_IMBP_BYPASS_0 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG31 */ +#define BITS_ADC3_BAL_B(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_ADC3_BAL_A(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG32 */ +#define BITS_ADC3_BAL_D(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_ADC3_BAL_C(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG33 */ +#define BITS_DAC3_BAL_B(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_DAC3_BAL_A(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG34 */ +#define BITS_DAC3_BAL_D(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_DAC3_BAL_C(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +#endif diff --git a/include/soc/sprd/chip_x20l/__regs_mm_ahb_rf.h b/include/soc/sprd/chip_x20l/__regs_mm_ahb_rf.h new file mode 100755 index 00000000..1fcaa732 --- /dev/null +++ b/include/soc/sprd/chip_x20l/__regs_mm_ahb_rf.h @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_MM_AHB_HEADFILE_H__ +#define __H_REGS_MM_AHB_HEADFILE_H__ __FILE__ + +#define REGS_MM_AHB_RF + +/* registers definitions for MM_AHB_RF */ +#define REG_MM_AHB_AHB_EB SCI_ADDR(REGS_MM_AHB_BASE, 0x0000) +#define REG_MM_AHB_AHB_RST SCI_ADDR(REGS_MM_AHB_BASE, 0x0004) +#define REG_MM_AHB_GEN_CKG_CFG SCI_ADDR(REGS_MM_AHB_BASE, 0x0008) +#define REG_MM_AHB_MIPI_CSI2_CTRL SCI_ADDR(REGS_MM_AHB_BASE, 0x000C) +#define REG_MM_AHB_MM_QOS_CFG SCI_ADDR(REGS_MM_AHB_BASE, 0x0010) + + + +/* bits definitions for register REG_MM_AHB_AHB_EB */ +#define BIT_MMU_EB ( BIT(7) ) +#define BIT_MM_CKG_EB ( BIT(6) ) +#define BIT_JPG_EB ( BIT(5) ) +#define BIT_CSI_EB ( BIT(4) ) +#define BIT_VSP_EB ( BIT(3) ) +#define BIT_ISP_EB ( BIT(2) ) +#define BIT_CCIR_EB ( BIT(1) ) +#define BIT_DCAM_EB ( BIT(0) ) + +/* bits definitions for register REG_MM_AHB_AHB_RST */ +#define BIT_MMU_SOFT_RST ( BIT(14) ) +#define BIT_MM_CKG_SOFT_RST ( BIT(13) ) +#define BIT_MM_MTX_SOFT_RST ( BIT(12) ) +#define BIT_OR1200_SOFT_RST ( BIT(11) ) +#define BIT_ROT_SOFT_RST ( BIT(10) ) +#define BIT_CAM2_SOFT_RST ( BIT(9) ) +#define BIT_CAM1_SOFT_RST ( BIT(8) ) +#define BIT_CAM0_SOFT_RST ( BIT(7) ) +#define BIT_JPG_SOFT_RST ( BIT(6) ) +#define BIT_CSI_SOFT_RST ( BIT(5) ) +#define BIT_VSP_SOFT_RST ( BIT(4) ) +#define BIT_ISP_CFG_SOFT_RST ( BIT(3) ) +#define BIT_ISP_LOG_SOFT_RST ( BIT(2) ) +#define BIT_CCIR_SOFT_RST ( BIT(1) ) +#define BIT_DCAM_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_MM_AHB_GEN_CKG_CFG */ +#define BIT_MM_MTX_AXI_CKG_EN ( BIT(8) ) +#define BIT_MM_AXI_CKG_EN ( BIT(7) ) +#define BIT_JPG_AXI_CKG_EN ( BIT(6) ) +#define BIT_VSP_AXI_CKG_EN ( BIT(5) ) +#define BIT_ISP_AXI_CKG_EN ( BIT(4) ) +#define BIT_DCAM_AXI_CKG_EN ( BIT(3) ) +#define BIT_SENSOR_CKG_EN ( BIT(2) ) +#define BIT_MIPI_CSI_CKG_EN ( BIT(1) ) +#define BIT_CPHY_CFG_CKG_EN ( BIT(0) ) + +/* bits definitions for register REG_MM_AHB_MIPI_CSI2_CTRL */ +#define BITS_MIPI_CPHY_SAMPLE_SEL(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)) ) +#define BIT_MIPI_CPHY_SYNC_MODE ( BIT(2) ) +#define BIT_MIPI_CPHY_TEST_CTL ( BIT(1) ) +#define BIT_MIPI_CPHY_SEL ( BIT(0) ) + +/* bits definitions for register REG_MM_AHB_MM_QOS_CFG */ +#define BITS_QOS_R_DCAM(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_QOS_W_DCAM(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_QOS_R_JPG(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_QOS_W_JPG(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_QOS_R_ISP(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_QOS_W_ISP(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_QOS_R_VSP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_QOS_W_VSP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +#endif diff --git a/include/soc/sprd/chip_x20l/__regs_mm_clk.h b/include/soc/sprd/chip_x20l/__regs_mm_clk.h new file mode 100644 index 00000000..4b73f5ef --- /dev/null +++ b/include/soc/sprd/chip_x20l/__regs_mm_clk.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __REGS_MM_CLK_H__ +#define __REGS_MM_CLK_H__ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, include <mach/sci_glb_regs.h>" +#endif + +#define REGS_MM_CLK + +/* registers definitions for controller REGS_MM_CLK */ +#define REG_MM_CLK_MM_AHB_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0020) +#define REG_MM_CLK_SENSOR_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0024) +#define REG_MM_CLK_CCIR_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0028) +#define REG_MM_CLK_DCAM_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x002c) +#define REG_MM_CLK_VSP_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0030) +#define REG_MM_CLK_ISP_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0034) +#define REG_MM_CLK_JPG_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0038) +#define REG_MM_CLK_MIPI_CSI_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x003c) +#define REG_MM_CLK_CPHY_CFG_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0040) +#define REG_MM_CLK_ORP_TCK_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0044) + +/* vars definitions for controller REGS_MM_CLK */ + +#endif //__REGS_MM_CLK_H__ diff --git a/include/soc/sprd/chip_x20l/__regs_pinmap.h b/include/soc/sprd/chip_x20l/__regs_pinmap.h new file mode 100755 index 00000000..be98c3a0 --- /dev/null +++ b/include/soc/sprd/chip_x20l/__regs_pinmap.h @@ -0,0 +1,283 @@ +#ifndef __ASM_ARM_ARCH_PINMAP_H +#error "Don't include this file directly, Pls include pinmap.h" +#endif + +#ifndef _REGS_PINMAP_H_ +#define _REGS_PINMAP_H_ + +#define CTL_PIN_BASE ( SPRD_PIN_BASE ) + +/* registers definitions for controller CTL_PIN */ +#define REG_PIN_CTRL0 ( 0x0000 ) +#define REG_PIN_CTRL1 ( 0x0004 ) +#define REG_PIN_CTRL2 ( 0x0008 ) +#define REG_PIN_CTRL3 ( 0x000c ) +#define REG_PIN_CTRL4 ( 0x0010 ) +#define REG_PIN_CTRL5 ( 0x0014 ) +#define REG_PIN_SIMCLK0 ( 0x0018 ) +#define REG_PIN_SIMDA0 ( 0x001c ) +#define REG_PIN_SIMRST0 ( 0x0020 ) +#define REG_PIN_SIMCLK1 ( 0x0024 ) +#define REG_PIN_SIMDA1 ( 0x0028 ) +#define REG_PIN_SIMRST1 ( 0x002c ) +#define REG_PIN_SD0_CLK ( 0x0030 ) +#define REG_PIN_SD0_CMD ( 0x0034 ) +#define REG_PIN_SD0_D0 ( 0x0038 ) +#define REG_PIN_SD0_D1 ( 0x003c ) +#define REG_PIN_SD0_D2 ( 0x0040 ) +#define REG_PIN_SD0_D3 ( 0x0044 ) +#define REG_PIN_ANA_INT ( 0x0048 ) +#define REG_PIN_EXT_RST_B ( 0x004c ) +#define REG_PIN_CLK_26M ( 0x0050 ) +#define REG_PIN_CHIP_SLEEP ( 0x0054 ) +#define REG_PIN_XTL_BUF_EN ( 0x0058 ) +#define REG_PIN_CLK_32K ( 0x005c ) +#define REG_PIN_AUD_SCLK ( 0x0060 ) +#define REG_PIN_AUD_ADD0 ( 0x0064 ) +#define REG_PIN_AUD_ADSYNC ( 0x0068 ) +#define REG_PIN_AUD_DAD1 ( 0x006c ) +#define REG_PIN_AUD_DAD0 ( 0x0070 ) +#define REG_PIN_AUD_DASYNC ( 0x0074 ) +#define REG_PIN_TD_TXPD ( 0x0078 ) +#define REG_PIN_TD_RXPD ( 0x007c ) +#define REG_PIN_GSM_TXPD ( 0x0080 ) +#define REG_PIN_GSM_RXPD ( 0x0084 ) +#define REG_PIN_TD_RX_CLK ( 0x0088 ) +#define REG_PIN_ADI_D ( 0x008c ) +#define REG_PIN_ADI_SYNC ( 0x0090 ) +#define REG_PIN_ADI_SCLK ( 0x0094 ) +#define REG_PIN_ANA_INT2 ( 0x0098 ) +#define REG_PIN_COM_TX_APCD ( 0x009c ) +#define REG_PIN_COM_TX_DQ1 ( 0x00a0 ) +#define REG_PIN_COM_TX_DQ0 ( 0x00a4 ) +#define REG_PIN_COM_TX_DI1 ( 0x00a8 ) +#define REG_PIN_COM_TX_DI0 ( 0x00ac ) +#define REG_PIN_COM_TX_SYNC ( 0x00b0 ) +#define REG_PIN_COM_TX_SCLK ( 0x00b4 ) +#define REG_PIN_COM_RX_DQ1 ( 0x00b8 ) +#define REG_PIN_COM_RX_DQ0 ( 0x00bc ) +#define REG_PIN_COM_RX_DI1 ( 0x00c0 ) +#define REG_PIN_COM_RX_DI0 ( 0x00c4 ) +#define REG_PIN_COM_RX_SYNC ( 0x00c8 ) +#define REG_PIN_COM_RX_SCLK ( 0x00cc ) +#define REG_PIN_CCIRCK ( 0x00d0 ) +#define REG_PIN_CCIRMCLK ( 0x00d4 ) +#define REG_PIN_CCIRHS ( 0x00d8 ) +#define REG_PIN_CCIRVS ( 0x00dc ) +#define REG_PIN_CCIRD0 ( 0x00e0 ) +#define REG_PIN_CCIRD1 ( 0x00e4 ) +#define REG_PIN_CCIRD2 ( 0x00e8 ) +#define REG_PIN_CCIRD3 ( 0x00ec ) +#define REG_PIN_CCIRD4 ( 0x00f0 ) +#define REG_PIN_CCIRD5 ( 0x00f4 ) +#define REG_PIN_CCIRD6 ( 0x00f8 ) +#define REG_PIN_CCIRD7 ( 0x00fc ) +#define REG_PIN_CCIRD8 ( 0x0100 ) +#define REG_PIN_CCIRD9 ( 0x0104 ) +#define REG_PIN_CCIRRST ( 0x0108 ) +#define REG_PIN_CCIRPD1 ( 0x010c ) +#define REG_PIN_CCIRPD0 ( 0x0110 ) +#define REG_PIN_SCL1 ( 0x0114 ) +#define REG_PIN_SDA1 ( 0x0118 ) +#define REG_PIN_KEYOUT0 ( 0x011c ) +#define REG_PIN_KEYOUT1 ( 0x0120 ) +#define REG_PIN_KEYOUT2 ( 0x0124 ) +#define REG_PIN_KEYOUT3 ( 0x0128 ) +#define REG_PIN_KEYOUT4 ( 0x012c ) +#define REG_PIN_KEYOUT5 ( 0x0130 ) +#define REG_PIN_GPIO135 ( 0x0134 ) +#define REG_PIN_GPIO136 ( 0x0138 ) +#define REG_PIN_GPIO137 ( 0x013c ) +#define REG_PIN_GPIO138 ( 0x0140 ) +#define REG_PIN_GPIO139 ( 0x0144 ) +#define REG_PIN_GPIO140 ( 0x0148 ) +#define REG_PIN_KEYOUT6 ( 0x014c ) +#define REG_PIN_KEYOUT7 ( 0x0150 ) +#define REG_PIN_KEYIN0 ( 0x0154 ) +#define REG_PIN_KEYIN1 ( 0x0158 ) +#define REG_PIN_KEYIN2 ( 0x015c ) +#define REG_PIN_KEYIN3 ( 0x0160 ) +#define REG_PIN_KEYIN4 ( 0x0164 ) +#define REG_PIN_KEYIN5 ( 0x0168 ) +#define REG_PIN_KEYIN6 ( 0x016c ) +#define REG_PIN_KEYIN7 ( 0x0170 ) +#define REG_PIN_NFWPN ( 0x0174 ) +#define REG_PIN_NFRB ( 0x0178 ) +#define REG_PIN_NFCLE ( 0x017c ) +#define REG_PIN_NFALE ( 0x0180 ) +#define REG_PIN_NFCEN ( 0x0184 ) +#define REG_PIN_NFREN ( 0x0188 ) +#define REG_PIN_NFWEN ( 0x018c ) +#define REG_PIN_NFD0 ( 0x0190 ) +#define REG_PIN_NFD1 ( 0x0194 ) +#define REG_PIN_NFD2 ( 0x0198 ) +#define REG_PIN_NFD3 ( 0x019c ) +#define REG_PIN_NFD4 ( 0x01a0 ) +#define REG_PIN_NFD5 ( 0x01a4 ) +#define REG_PIN_NFD6 ( 0x01a8 ) +#define REG_PIN_NFD7 ( 0x01ac ) +#define REG_PIN_NFD8 ( 0x01b0 ) +#define REG_PIN_NFD9 ( 0x01b4 ) +#define REG_PIN_NFD10 ( 0x01b8 ) +#define REG_PIN_NFD11 ( 0x01bc ) +#define REG_PIN_NFD12 ( 0x01c0 ) +#define REG_PIN_NFD13 ( 0x01c4 ) +#define REG_PIN_NFD14 ( 0x01c8 ) +#define REG_PIN_NFD15 ( 0x01cc ) +#define REG_PIN_SD3_CLK ( 0x01d0 ) +#define REG_PIN_SD3_CMD ( 0x01d4 ) +#define REG_PIN_SD3_D0 ( 0x01d8 ) +#define REG_PIN_SD3_D1 ( 0x01dc ) +#define REG_PIN_SD3_D2 ( 0x01e0 ) +#define REG_PIN_SD3_D3 ( 0x01e4 ) +#define REG_PIN_SD3_D4 ( 0x01e8 ) +#define REG_PIN_SD3_D5 ( 0x01ec ) +#define REG_PIN_SD3_D6 ( 0x01f0 ) +#define REG_PIN_SD3_D7 ( 0x01f4 ) +#define REG_PIN_EMMC_RST ( 0x01f8 ) +#define REG_PIN_SD1_CLK ( 0x01fc ) +#define REG_PIN_SD1_CMD ( 0x0200 ) +#define REG_PIN_SD1_D0 ( 0x0204 ) +#define REG_PIN_SD1_D1 ( 0x0208 ) +#define REG_PIN_SD1_D2 ( 0x020c ) +#define REG_PIN_SD1_D3 ( 0x0210 ) +#define REG_PIN_LCD_CSN1 ( 0x0214 ) +#define REG_PIN_LCD_RSTN ( 0x0218 ) +#define REG_PIN_LCD_CD ( 0x021c ) +#define REG_PIN_LCD_D0 ( 0x0220 ) +#define REG_PIN_LCD_D1 ( 0x0224 ) +#define REG_PIN_LCD_D2 ( 0x0228 ) +#define REG_PIN_LCD_D3 ( 0x022c ) +#define REG_PIN_LCD_D4 ( 0x0230 ) +#define REG_PIN_LCD_D5 ( 0x0234 ) +#define REG_PIN_LCD_D6 ( 0x0238 ) +#define REG_PIN_LCD_D7 ( 0x023c ) +#define REG_PIN_LCD_D8 ( 0x0240 ) +#define REG_PIN_LCD_WRN ( 0x0244 ) +#define REG_PIN_LCD_RDN ( 0x0248 ) +#define REG_PIN_LCD_CSN0 ( 0x024c ) +#define REG_PIN_LCD_D9 ( 0x0250 ) +#define REG_PIN_LCD_D10 ( 0x0254 ) +#define REG_PIN_LCD_D11 ( 0x0258 ) +#define REG_PIN_LCD_D12 ( 0x025c ) +#define REG_PIN_LCD_D13 ( 0x0260 ) +#define REG_PIN_LCD_D14 ( 0x0264 ) +#define REG_PIN_LCD_D15 ( 0x0268 ) +#define REG_PIN_LCD_D16 ( 0x026c ) +#define REG_PIN_LCD_D17 ( 0x0270 ) +#define REG_PIN_LCD_D18 ( 0x0274 ) +#define REG_PIN_LCD_D19 ( 0x0278 ) +#define REG_PIN_LCD_D20 ( 0x027c ) +#define REG_PIN_LCD_D21 ( 0x0280 ) +#define REG_PIN_LCD_D22 ( 0x0284 ) +#define REG_PIN_LCD_D23 ( 0x0288 ) +#define REG_PIN_LCD_FMARK ( 0x028c ) +#define REG_PIN_SPI2_CSN ( 0x0290 ) +#define REG_PIN_SPI2_DO ( 0x0294 ) +#define REG_PIN_SPI2_DI ( 0x0298 ) +#define REG_PIN_SPI2_CLK ( 0x029c ) +#define REG_PIN_SCL0 ( 0x02a0 ) +#define REG_PIN_SDA0 ( 0x02a4 ) +#define REG_PIN_SCL2 ( 0x02a8 ) +#define REG_PIN_SDA2 ( 0x02ac ) +#define REG_PIN_SCL3 ( 0x02b0 ) +#define REG_PIN_SDA3 ( 0x02b4 ) +#define REG_PIN_CLK_AUX0 ( 0x02b8 ) +#define REG_PIN_IIS0DI ( 0x02bc ) +#define REG_PIN_IIS0DO ( 0x02c0 ) +#define REG_PIN_IIS0CLK ( 0x02c4 ) +#define REG_PIN_IIS0LRCK ( 0x02c8 ) +#define REG_PIN_IIS0MCK ( 0x02cc ) +#define REG_PIN_SPI0_CSN ( 0x02d0 ) +#define REG_PIN_SPI0_DO ( 0x02d4 ) +#define REG_PIN_SPI0_DI ( 0x02d8 ) +#define REG_PIN_SPI0_CLK ( 0x02dc ) +#define REG_PIN_GPIO141 ( 0x02e0 ) +#define REG_PIN_GPIO142 ( 0x02e4 ) +#define REG_PIN_MTDO ( 0x02e8 ) + +#define REG_PIN_MTDI ( 0x02ec ) +#define REG_PIN_MTCK ( 0x02f0 ) +#define REG_PIN_MTMS ( 0x02f4 ) +#define REG_PIN_MTRST_N ( 0x02f8 ) +#define REG_PIN_TRACECLK ( 0x02fc ) +#define REG_PIN_TRACECTRL ( 0x0300 ) +#define REG_PIN_TRACEDAT0 ( 0x0304 ) +#define REG_PIN_TRACEDAT1 ( 0x0308 ) +#define REG_PIN_TRACEDAT2 ( 0x030c ) +#define REG_PIN_TRACEDAT3 ( 0x0310 ) +#define REG_PIN_TRACEDAT4 ( 0x0314 ) +#define REG_PIN_TRACEDAT5 ( 0x0318 ) +#define REG_PIN_TRACEDAT6 ( 0x031c ) +#define REG_PIN_TRACEDAT7 ( 0x0320 ) +#define REG_PIN_U0TXD ( 0x0324 ) +#define REG_PIN_U0RXD ( 0x0328 ) +#define REG_PIN_U0CTS ( 0x032c ) +#define REG_PIN_U0RTS ( 0x0330 ) +#define REG_PIN_U1TXD ( 0x0334 ) +#define REG_PIN_U1RXD ( 0x0338 ) +#define REG_PIN_U2TXD ( 0x033c ) +#define REG_PIN_U2RXD ( 0x0340 ) +#define REG_PIN_U2CTS ( 0x0344 ) +#define REG_PIN_U2RTS ( 0x0348 ) +#define REG_PIN_U3TXD ( 0x034c ) +#define REG_PIN_U3RXD ( 0x0350 ) +#define REG_PIN_U3CTS ( 0x0354 ) +#define REG_PIN_U3RTS ( 0x0358 ) +#define REG_PIN_CLK_REQ1 ( 0x035c ) +#define REG_PIN_CLK_REQ2 ( 0x0360 ) +#define REG_PIN_RFSDA0 ( 0x0364 ) +#define REG_PIN_RFSCK0 ( 0x0368 ) +#define REG_PIN_RFSEN0 ( 0x036c ) +#define REG_PIN_RFCTL0 ( 0x0370 ) +#define REG_PIN_RFCTL1 ( 0x0374 ) +#define REG_PIN_RFCTL2 ( 0x0378 ) +#define REG_PIN_RFCTL3 ( 0x037c ) + +#define REG_PIN_RFCTL4 ( 0x0380 ) +#define REG_PIN_RFCTL5 ( 0x0384 ) +#define REG_PIN_RFCTL6 ( 0x0388 ) +#define REG_PIN_RFCTL7 ( 0x038c ) +#define REG_PIN_RFCTL8 ( 0x0390 ) +#define REG_PIN_RFCTL9 ( 0x0394 ) +#define REG_PIN_RFCTL10 ( 0x0398 ) +#define REG_PIN_RFCTL11 ( 0x039c ) +#define REG_PIN_RFCTL12 ( 0x03a0 ) +#define REG_PIN_RFCTL13 ( 0x03a4 ) +#define REG_PIN_RFCTL14 ( 0x03a8 ) +#define REG_PIN_RFCTL15 ( 0x03ac ) +#define REG_PIN_XTL_EN ( 0x03b0 ) +#define REG_PIN_PTEST ( 0x03b4 ) +#define REG_PIN_GPIO143 ( 0x03b8 ) +#define REG_PIN_GPIO144 ( 0x03bc ) + + +/* bits definitions for register REG_PIN_XXX */ +#define BITS_PIN_DS(_x_) ( (_x_) << 19 & (BIT(19)|BIT(20)) ) +#define BITS_PIN_DS_3(_x_) ( (_x_) << 19 & (BIT(19)|BIT(20)|BIT(21)) ) +#define BITS_PIN_DS_4(_x_) ( (_x_) << 19 & (BIT(19)|BIT(20)|BIT(21)|BIT(22)) ) +#define BIT_PIN_SLP_AP ( BIT(13) ) +#define BIT_PIN_WPU ( BIT(7) ) +#define BIT_PIN_WPD ( BIT(6) ) +#define BITS_PIN_AF(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BIT_PIN_SLP_WPU ( BIT(3) ) +#define BIT_PIN_SLP_WPD ( BIT(2) ) +#define BIT_PIN_SLP_IE ( BIT(1) ) +#define BIT_PIN_SLP_OE ( BIT(0) ) + +/* vars definitions for controller CTL_PIN */ +#define BIT_PIN_NUL ( 0 ) +#define BIT_PIN_SLP_NUL ( 0 ) +#define BIT_PIN_SLP_Z ( 0 ) + + + + + + + + + + + +#endif diff --git a/include/soc/sprd/chip_x20l/__regs_pmu_apb_rf.h b/include/soc/sprd/chip_x20l/__regs_pmu_apb_rf.h new file mode 100755 index 00000000..25fd9ced --- /dev/null +++ b/include/soc/sprd/chip_x20l/__regs_pmu_apb_rf.h @@ -0,0 +1,868 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_PMU_APB_HEADFILE_H__ +#define __H_REGS_PMU_APB_HEADFILE_H__ __FILE__ + +#define REGS_PMU_APB_RF + +/* registers definitions for PMU_APB_RF */ +#define REG_PMU_APB_PD_CA7_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0000) +#define REG_PMU_APB_PD_CA7_C0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0004) +#define REG_PMU_APB_PD_CA7_C1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0008) +#define REG_PMU_APB_PD_CA7_C2_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x000C) +#define REG_PMU_APB_PD_CA7_C3_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0010) +#define REG_PMU_APB_PD_AP_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0018) +#define REG_PMU_APB_PD_MM_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x001C) +#define REG_PMU_APB_PD_GPU_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0020) +#define REG_PMU_APB_PD_CP0_ARM9_0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0024) +#define REG_PMU_APB_PD_CP0_ARM9_1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0028) +#define REG_PMU_APB_PD_CP0_HU3GE_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x002C) +#define REG_PMU_APB_PD_CP0_GSM_0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0030) +#define REG_PMU_APB_PD_CP0_GSM_1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0034) +#define REG_PMU_APB_PD_CP0_TD_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0038) +#define REG_PMU_APB_PD_CP0_CEVA_0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x003C) +#define REG_PMU_APB_PD_CP0_CEVA_1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0040) +#define REG_PMU_APB_PD_CP0_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0044) +#define REG_PMU_APB_PD_CP1_CA5_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0048) +#define REG_PMU_APB_PD_CP1_LTE_P1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x004C) +#define REG_PMU_APB_PD_CP1_LTE_P2_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0050) +#define REG_PMU_APB_PD_CP1_CEVA_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0054) +#define REG_PMU_APB_PD_CP1_COMWRAP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0058) +#define REG_PMU_APB_PD_PUB_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x005C) +#define REG_PMU_APB_AP_WAKEUP_POR_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0060) +#define REG_PMU_APB_XTL_WAIT_CNT SCI_ADDR(REGS_PMU_APB_BASE, 0x0070) +#define REG_PMU_APB_XTLBUF_WAIT_CNT SCI_ADDR(REGS_PMU_APB_BASE, 0x0074) +#define REG_PMU_APB_PLL_WAIT_CNT1 SCI_ADDR(REGS_PMU_APB_BASE, 0x0078) +#define REG_PMU_APB_PLL_WAIT_CNT2 SCI_ADDR(REGS_PMU_APB_BASE, 0x007C) +#define REG_PMU_APB_XTL0_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0080) +#define REG_PMU_APB_XTL1_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0084) +#define REG_PMU_APB_XTLBUF0_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x008C) +#define REG_PMU_APB_XTLBUF1_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0090) +#define REG_PMU_APB_MPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0094) +#define REG_PMU_APB_DPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0098) +#define REG_PMU_APB_LTEPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x009C) +#define REG_PMU_APB_TWPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00A0) +#define REG_PMU_APB_LVDSDIS_PLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00A4) +#define REG_PMU_APB_CP_SOFT_RST SCI_ADDR(REGS_PMU_APB_BASE, 0x00B0) +#define REG_PMU_APB_CP_SLP_STATUS_DBG0 SCI_ADDR(REGS_PMU_APB_BASE, 0x00B4) +#define REG_PMU_APB_PWR_STATUS0_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00BC) +#define REG_PMU_APB_PWR_STATUS1_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00C0) +#define REG_PMU_APB_PWR_STATUS2_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00C4) +#define REG_PMU_APB_SLEEP_CTRL SCI_ADDR(REGS_PMU_APB_BASE, 0x00CC) +#define REG_PMU_APB_DDR_SLEEP_CTRL SCI_ADDR(REGS_PMU_APB_BASE, 0x00D0) +#define REG_PMU_APB_SLEEP_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x00D4) +#define REG_PMU_APB_CA7_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00E4) +#define REG_PMU_APB_CA7_C0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00E8) +#define REG_PMU_APB_CA7_C1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00EC) +#define REG_PMU_APB_CA7_C2_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00F0) +#define REG_PMU_APB_CA7_C3_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00F4) +#define REG_PMU_APB_DDR_CHN_SLEEP_CTRL0 SCI_ADDR(REGS_PMU_APB_BASE, 0x00F8) +#define REG_PMU_APB_DDR_CHN_SLEEP_CTRL1 SCI_ADDR(REGS_PMU_APB_BASE, 0x00FC) +#define REG_PMU_APB_DDR_OP_MODE_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x012C) +#define REG_PMU_APB_DDR_PHY_RET_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0130) +#define REG_PMU_APB_26M_SEL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0134) +#define REG_PMU_APB_BISR_DONE_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x0138) +#define REG_PMU_APB_BISR_BUSY_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x013C) +#define REG_PMU_APB_BISR_BYP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0140) +#define REG_PMU_APB_BISR_EN_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0144) +#define REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG0 SCI_ADDR(REGS_PMU_APB_BASE, 0x0148) +#define REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG1 SCI_ADDR(REGS_PMU_APB_BASE, 0x014C) +#define REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG2 SCI_ADDR(REGS_PMU_APB_BASE, 0x0150) +#define REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG3 SCI_ADDR(REGS_PMU_APB_BASE, 0x0154) +#define REG_PMU_APB_CGM_FORCE_EN_CFG0 SCI_ADDR(REGS_PMU_APB_BASE, 0x0158) +#define REG_PMU_APB_CGM_FORCE_EN_CFG1 SCI_ADDR(REGS_PMU_APB_BASE, 0x015C) +#define REG_PMU_APB_CGM_FORCE_EN_CFG2 SCI_ADDR(REGS_PMU_APB_BASE, 0x0160) +#define REG_PMU_APB_CGM_FORCE_EN_CFG3 SCI_ADDR(REGS_PMU_APB_BASE, 0x0164) +#define REG_PMU_APB_SLEEP_XTLON_CTRL SCI_ADDR(REGS_PMU_APB_BASE, 0x0168) +#define REG_PMU_APB_MEM_SLP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x016C) +#define REG_PMU_APB_MEM_SD_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0170) +#define REG_PMU_APB_CA7_CORE_PU_LOCK SCI_ADDR(REGS_PMU_APB_BASE, 0x0174) +#define REG_PMU_APB_ARM7_HOLD_CGM_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0178) +#define REG_PMU_APB_PWR_CNT_WAIT_CFG0 SCI_ADDR(REGS_PMU_APB_BASE, 0x017C) +#define REG_PMU_APB_PWR_CNT_WAIT_CFG1 SCI_ADDR(REGS_PMU_APB_BASE, 0x0180) +#define REG_PMU_APB_RC0_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0184) +#define REG_PMU_APB_RC1_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0188) +#define REG_PMU_APB_RC_CNT_WAIT_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x018C) +#define REG_PMU_APB_MEM_AUTO_SLP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0190) +#define REG_PMU_APB_MEM_AUTO_SD_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0194) +#define REG_PMU_APB_CP0_PD_SHUTDOWN_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0198) +#define REG_PMU_APB_CP1_PD_SHUTDOWN_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x019C) +#define REG_PMU_APB_WAKEUP_LOCK_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x01A0) +#define REG_PMU_APB_PD_CA7_C0_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3000) +#define REG_PMU_APB_PD_CA7_C1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3004) +#define REG_PMU_APB_PD_CA7_C2_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3008) +#define REG_PMU_APB_PD_CA7_C3_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x300C) +#define REG_PMU_APB_PD_CA7_TOP_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3010) +#define REG_PMU_APB_PD_AP_SYS_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3014) +#define REG_PMU_APB_PD_GPU_TOP_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3018) +#define REG_PMU_APB_PD_MM_TOP_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x301C) +#define REG_PMU_APB_PD_CP0_ARM9_0_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3020) +#define REG_PMU_APB_PD_CP0_ARM9_1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3024) +#define REG_PMU_APB_PD_CP0_CEVA_0_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3028) +#define REG_PMU_APB_PD_CP0_CEVA_1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x302C) +#define REG_PMU_APB_PD_CP0_GSM_0_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3030) +#define REG_PMU_APB_PD_CP0_GSM_1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3034) +#define REG_PMU_APB_PD_CP0_TD_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3038) +#define REG_PMU_APB_PD_CP0_HU3GE_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x303C) +#define REG_PMU_APB_PD_CP1_CA5_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3040) +#define REG_PMU_APB_PD_CP1_CEVA_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3044) +#define REG_PMU_APB_PD_CP1_LTE_P1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3048) +#define REG_PMU_APB_PD_CP1_LTE_P2_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x304C) +#define REG_PMU_APB_PD_CP1_COMWRAP_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3050) +#define REG_PMU_APB_PD_PUB_SYS_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3054) + + + +/* bits definitions for register REG_PMU_APB_PD_CA7_TOP_CFG */ +#define BIT_PD_CA7_TOP_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_PD_CA7_TOP_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CA7_TOP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA7_TOP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA7_C0_CFG */ +#define BIT_PD_CA7_C0_WFI_SHUTDOWN_EN ( BIT(29) ) +#define BIT_PD_CA7_C0_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_PD_CA7_C0_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CA7_C0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA7_C0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA7_C1_CFG */ +#define BIT_PD_CA7_C1_WFI_SHUTDOWN_EN ( BIT(29) ) +#define BIT_PD_CA7_C1_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_PD_CA7_C1_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA7_C1_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CA7_C1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA7_C1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA7_C2_CFG */ +#define BIT_PD_CA7_C2_WFI_SHUTDOWN_EN ( BIT(29) ) +#define BIT_PD_CA7_C2_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_PD_CA7_C2_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA7_C2_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CA7_C2_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA7_C2_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA7_C3_CFG */ +#define BIT_PD_CA7_C3_WFI_SHUTDOWN_EN ( BIT(29) ) +#define BIT_PD_CA7_C3_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_PD_CA7_C3_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA7_C3_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CA7_C3_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA7_C3_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_AP_SYS_CFG */ +#define BIT_PD_AP_SYS_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_AP_SYS_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_AP_SYS_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_MM_TOP_CFG */ +#define BIT_PD_MM_TOP_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_MM_TOP_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_MM_TOP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_MM_TOP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_GPU_TOP_CFG */ +#define BIT_PD_GPU_TOP_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_GPU_TOP_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_GPU_TOP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_GPU_TOP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_0_CFG */ +#define BIT_PD_CP0_ARM9_0_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_ARM9_0_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_ARM9_0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_ARM9_0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_ARM9_0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_1_CFG */ +#define BIT_PD_CP0_ARM9_1_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_ARM9_1_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_ARM9_1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_ARM9_1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_ARM9_1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_HU3GE_CFG */ +#define BIT_PD_CP0_HU3GE_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_HU3GE_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_HU3GE_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_HU3GE_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_HU3GE_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_GSM_0_CFG */ +#define BIT_PD_CP0_GSM_0_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_GSM_0_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_GSM_0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_GSM_0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_GSM_0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_GSM_1_CFG */ +#define BIT_PD_CP0_GSM_1_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_GSM_1_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_GSM_1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_GSM_1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_GSM_1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_TD_CFG */ +#define BIT_PD_CP0_TD_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_TD_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_TD_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_TD_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_TD_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_CEVA_0_CFG */ +#define BIT_PD_CP0_CEVA_0_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_CEVA_0_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_CEVA_0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_CEVA_0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_CEVA_0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_CEVA_1_CFG */ +#define BIT_PD_CP0_CEVA_1_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_CEVA_1_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_CEVA_1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_CEVA_1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_CEVA_1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_SYS_CFG */ + +/* bits definitions for register REG_PMU_APB_PD_CP1_CA5_CFG */ +#define BIT_PD_CP1_CA5_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP1_CA5_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP1_CA5_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_CA5_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_CA5_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_LTE_P1_CFG */ +#define BIT_PD_CP1_LTE_P1_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP1_LTE_P1_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP1_LTE_P1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_LTE_P1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_LTE_P1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_LTE_P2_CFG */ +#define BIT_PD_CP1_LTE_P2_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP1_LTE_P2_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP1_LTE_P2_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_LTE_P2_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_LTE_P2_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_CEVA_CFG */ +#define BIT_PD_CP1_CEVA_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP1_CEVA_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP1_CEVA_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_CEVA_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_CEVA_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_COMWRAP_CFG */ +#define BIT_PD_CP1_COMWRAP_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP1_COMWRAP_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP1_COMWRAP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_COMWRAP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_COMWRAP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_PUB_SYS_CFG */ +#define BIT_PD_PUB_SYS_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_PUB_SYS_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_PUB_SYS_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_AP_WAKEUP_POR_CFG */ +#define BIT_AP_WAKEUP_POR_N ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_XTL_WAIT_CNT */ +#define BITS_XTL1_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_XTL0_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_XTLBUF_WAIT_CNT */ +#define BITS_XTLBUF1_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_XTLBUF0_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PLL_WAIT_CNT1 */ +#define BITS_LTEPLL_WAIT_CNT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_TWPLL_WAIT_CNT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DPLL_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_MPLL_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PLL_WAIT_CNT2 */ +#define BITS_LVDSDIS_PLL_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_XTL0_REL_CFG */ +#define BIT_XTL0_ARM7_SEL ( BIT(5) ) +#define BIT_XTL0_VCP1_SEL ( BIT(4) ) +#define BIT_XTL0_VCP0_SEL ( BIT(3) ) +#define BIT_XTL0_CP1_SEL ( BIT(2) ) +#define BIT_XTL0_CP0_SEL ( BIT(1) ) +#define BIT_XTL0_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_XTL1_REL_CFG */ +#define BIT_XTL1_ARM7_SEL ( BIT(5) ) +#define BIT_XTL1_VCP1_SEL ( BIT(4) ) +#define BIT_XTL1_VCP0_SEL ( BIT(3) ) +#define BIT_XTL1_CP1_SEL ( BIT(2) ) +#define BIT_XTL1_CP0_SEL ( BIT(1) ) +#define BIT_XTL1_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_XTLBUF0_REL_CFG */ +#define BIT_XTLBUF0_ARM7_SEL ( BIT(5) ) +#define BIT_XTLBUF0_VCP1_SEL ( BIT(4) ) +#define BIT_XTLBUF0_VCP0_SEL ( BIT(3) ) +#define BIT_XTLBUF0_CP1_SEL ( BIT(2) ) +#define BIT_XTLBUF0_CP0_SEL ( BIT(1) ) +#define BIT_XTLBUF0_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_XTLBUF1_REL_CFG */ +#define BIT_XTLBUF1_ARM7_SEL ( BIT(5) ) +#define BIT_XTLBUF1_VCP1_SEL ( BIT(4) ) +#define BIT_XTLBUF1_VCP0_SEL ( BIT(3) ) +#define BIT_XTLBUF1_CP1_SEL ( BIT(2) ) +#define BIT_XTLBUF1_CP0_SEL ( BIT(1) ) +#define BIT_XTLBUF1_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_MPLL_REL_CFG */ +#define BIT_MPLL_REF_SEL ( BIT(8) ) +#define BIT_MPLL_ARM7_SEL ( BIT(5) ) +#define BIT_MPLL_VCP1_SEL ( BIT(4) ) +#define BIT_MPLL_VCP0_SEL ( BIT(3) ) +#define BIT_MPLL_CP1_SEL ( BIT(2) ) +#define BIT_MPLL_CP0_SEL ( BIT(1) ) +#define BIT_MPLL_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_DPLL_REL_CFG */ +#define BIT_DPLL_REF_SEL ( BIT(8) ) +#define BIT_DPLL_ARM7_SEL ( BIT(5) ) +#define BIT_DPLL_VCP1_SEL ( BIT(4) ) +#define BIT_DPLL_VCP0_SEL ( BIT(3) ) +#define BIT_DPLL_CP1_SEL ( BIT(2) ) +#define BIT_DPLL_CP0_SEL ( BIT(1) ) +#define BIT_DPLL_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_LTEPLL_REL_CFG */ +#define BIT_LTEPLL_REF_SEL ( BIT(8) ) +#define BIT_LTEPLL_ARM7_SEL ( BIT(5) ) +#define BIT_LTEPLL_VCP1_SEL ( BIT(4) ) +#define BIT_LTEPLL_VCP0_SEL ( BIT(3) ) +#define BIT_LTEPLL_CP1_SEL ( BIT(2) ) +#define BIT_LTEPLL_CP0_SEL ( BIT(1) ) +#define BIT_LTEPLL_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_TWPLL_REL_CFG */ +#define BIT_TWPLL_REF_SEL ( BIT(8) ) +#define BIT_TWPLL_ARM7_SEL ( BIT(5) ) +#define BIT_TWPLL_VCP1_SEL ( BIT(4) ) +#define BIT_TWPLL_VCP0_SEL ( BIT(3) ) +#define BIT_TWPLL_CP1_SEL ( BIT(2) ) +#define BIT_TWPLL_CP0_SEL ( BIT(1) ) +#define BIT_TWPLL_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_LVDSDIS_PLL_REL_CFG */ +#define BIT_LVDSDIS_PLL_REF_SEL ( BIT(8) ) +#define BIT_LVDSDIS_PLL_ARM7_SEL ( BIT(5) ) +#define BIT_LVDSDIS_PLL_VCP1_SEL ( BIT(4) ) +#define BIT_LVDSDIS_PLL_VCP0_SEL ( BIT(3) ) +#define BIT_LVDSDIS_PLL_CP1_SEL ( BIT(2) ) +#define BIT_LVDSDIS_PLL_CP0_SEL ( BIT(1) ) +#define BIT_LVDSDIS_PLL_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CP_SOFT_RST */ +#define BIT_ARM7_SOFT_RST ( BIT(8) ) +#define BIT_PUB_SOFT_RST ( BIT(6) ) +#define BIT_AP_SOFT_RST ( BIT(5) ) +#define BIT_GPU_SOFT_RST ( BIT(4) ) +#define BIT_MM_SOFT_RST ( BIT(3) ) +#define BIT_CP1_SOFT_RST ( BIT(1) ) +#define BIT_CP0_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CP_SLP_STATUS_DBG0 */ +#define BITS_CP1_DEEP_SLP_DBG(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_CP0_DEEP_SLP_DBG(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_PMU_APB_PWR_STATUS0_DBG */ +#define BITS_PD_MM_TOP_STATE(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_PD_GPU_TOP_STATE(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_PD_AP_SYS_STATE(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA7_C3_STATE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_PD_CA7_C2_STATE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA7_C1_STATE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_PD_CA7_C0_STATE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_PD_CA7_TOP_STATE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PWR_STATUS1_DBG */ +#define BITS_PD_CP0_CEVA_1_STATE(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_PD_CP0_CEVA_0_STATE(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_PD_CP0_GSM_0_STATE(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_GSM_1_STATE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_PD_CP0_HU3GE_STATE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_ARM9_1_STATE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_PD_CP0_ARM9_0_STATE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_PD_CP0_TD_STATE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PWR_STATUS2_DBG */ +#define BITS_PD_PUB_SYS_STATE(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_PD_CP1_COMWRAP_STATE(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_LTE_P2_STATE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_PD_CP1_LTE_P1_STATE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_CEVA_STATE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_PD_CP1_CA5_STATE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_SLEEP_CTRL */ +#define BIT_VCP1_FORCE_LIGHT_SLEEP ( BIT(28) ) +#define BIT_VCP0_FORCE_LIGHT_SLEEP ( BIT(27) ) +#define BIT_CP1_FORCE_LIGHT_SLEEP ( BIT(26) ) +#define BIT_CP0_FORCE_LIGHT_SLEEP ( BIT(25) ) +#define BIT_AP_FORCE_LIGHT_SLEEP ( BIT(24) ) +#define BIT_ARM7_FORCE_DEEP_SLEEP ( BIT(21) ) +#define BIT_VCP1_FORCE_DEEP_SLEEP ( BIT(20) ) +#define BIT_VCP0_FORCE_DEEP_SLEEP ( BIT(19) ) +#define BIT_CP1_FORCE_DEEP_SLEEP ( BIT(18) ) +#define BIT_CP0_FORCE_DEEP_SLEEP ( BIT(17) ) +#define BIT_AP_FORCE_DEEP_SLEEP ( BIT(16) ) +#define BIT_VCP1_LIGHT_SLEEP ( BIT(12) ) +#define BIT_VCP0_LIGHT_SLEEP ( BIT(11) ) +#define BIT_CP1_LIGHT_SLEEP ( BIT(10) ) +#define BIT_CP0_LIGHT_SLEEP ( BIT(9) ) +#define BIT_AP_LIGHT_SLEEP ( BIT(8) ) +#define BIT_VCP1_DEEP_SLEEP ( BIT(4) ) +#define BIT_VCP0_DEEP_SLEEP ( BIT(3) ) +#define BIT_CP1_DEEP_SLEEP ( BIT(2) ) +#define BIT_CP0_DEEP_SLEEP ( BIT(1) ) +#define BIT_AP_DEEP_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_DDR_SLEEP_CTRL */ +#define BIT_BUSY_TRANSFER_HWDATA_SEL ( BIT(16) ) +#define BIT_DDR_PUBL_APB_SOFT_RST ( BIT(12) ) +#define BIT_DDR_UMCTL_APB_SOFT_RST ( BIT(11) ) +#define BIT_DDR_PUBL_SOFT_RST ( BIT(10) ) +#define BIT_DDR_PHY_SOFT_RST ( BIT(8) ) +#define BIT_DDR_PHY_AUTO_GATE_EN ( BIT(6) ) +#define BIT_DDR_PUBL_AUTO_GATE_EN ( BIT(5) ) +#define BIT_DDR_UMCTL_AUTO_GATE_EN ( BIT(4) ) +#define BIT_DDR_PHY_EB ( BIT(2) ) +#define BIT_DDR_UMCTL_EB ( BIT(1) ) +#define BIT_DDR_PUBL_EB ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_SLEEP_STATUS */ +#define BITS_ARM7_SLP_STATUS(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_VCP1_SLP_STATUS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_VCP0_SLP_STATUS(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_CP1_SLP_STATUS(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CP0_SLP_STATUS(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_AP_SLP_STATUS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_CA7_TOP_CFG */ +#define BIT_CA7_L2RSTDISABLE ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CA7_C0_CFG */ +#define BIT_CA7_VINITHI_C0 ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CA7_C1_CFG */ +#define BIT_CA7_VINITHI_C1 ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CA7_C2_CFG */ +#define BIT_CA7_VINITHI_C2 ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CA7_C3_CFG */ +#define BIT_CA7_VINITHI_C3 ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_DDR_CHN_SLEEP_CTRL0 */ +#define BIT_DDR_CTRL_AXI_LP_EN ( BIT(31) ) +#define BIT_DDR_CTRL_CGM_SEL ( BIT(30) ) +#define BIT_DDR_CHN9_AXI_LP_EN ( BIT(25) ) +#define BIT_DDR_CHN8_AXI_LP_EN ( BIT(24) ) +#define BIT_DDR_CHN7_AXI_LP_EN ( BIT(23) ) +#define BIT_DDR_CHN6_AXI_LP_EN ( BIT(22) ) +#define BIT_DDR_CHN5_AXI_LP_EN ( BIT(21) ) +#define BIT_DDR_CHN4_AXI_LP_EN ( BIT(20) ) +#define BIT_DDR_CHN3_AXI_LP_EN ( BIT(19) ) +#define BIT_DDR_CHN2_AXI_LP_EN ( BIT(18) ) +#define BIT_DDR_CHN1_AXI_LP_EN ( BIT(17) ) +#define BIT_DDR_CHN0_AXI_LP_EN ( BIT(16) ) +#define BIT_DDR_CHN9_CGM_SEL ( BIT(9) ) +#define BIT_DDR_CHN8_CGM_SEL ( BIT(8) ) +#define BIT_DDR_CHN7_CGM_SEL ( BIT(7) ) +#define BIT_DDR_CHN6_CGM_SEL ( BIT(6) ) +#define BIT_DDR_CHN5_CGM_SEL ( BIT(5) ) +#define BIT_DDR_CHN4_CGM_SEL ( BIT(4) ) +#define BIT_DDR_CHN3_CGM_SEL ( BIT(3) ) +#define BIT_DDR_CHN2_CGM_SEL ( BIT(2) ) +#define BIT_DDR_CHN1_CGM_SEL ( BIT(1) ) +#define BIT_DDR_CHN0_CGM_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_DDR_CHN_SLEEP_CTRL1 */ +#define BIT_DDR_CHN9_AXI_STOP_SEL ( BIT(9) ) +#define BIT_DDR_CHN8_AXI_STOP_SEL ( BIT(8) ) +#define BIT_DDR_CHN7_AXI_STOP_SEL ( BIT(7) ) +#define BIT_DDR_CHN6_AXI_STOP_SEL ( BIT(6) ) +#define BIT_DDR_CHN5_AXI_STOP_SEL ( BIT(5) ) +#define BIT_DDR_CHN4_AXI_STOP_SEL ( BIT(4) ) +#define BIT_DDR_CHN3_AXI_STOP_SEL ( BIT(3) ) +#define BIT_DDR_CHN2_AXI_STOP_SEL ( BIT(2) ) +#define BIT_DDR_CHN1_AXI_STOP_SEL ( BIT(1) ) +#define BIT_DDR_CHN0_AXI_STOP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_DDR_OP_MODE_CFG */ +#define BIT_DDR_OPERATE_MODE_BUSY ( BIT(28) ) +#define BIT_DDR_PUBL_RET_EN ( BIT(27) ) +#define BIT_DDR_PHY_ISO_RST_EN ( BIT(26) ) +#define BIT_DDR_UMCTL_RET_EN ( BIT(25) ) +#define BIT_DDR_PHY_AUTO_RET_EN ( BIT(24) ) +#define BITS_DDR_OPERATE_MODE_CNT_LMT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DDR_OPERATE_MODE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_DDR_OPERATE_MODE_IDLE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_PMU_APB_DDR_PHY_RET_CFG */ +#define BIT_DDR_UMCTL_SOFT_RST ( BIT(16) ) +#define BIT_DDR_PHY_CKE_RET_EN ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_26M_SEL_CFG */ +#define BIT_AON_RC_4M_SEL ( BIT(8) ) +#define BIT_GGE_26M_SEL ( BIT(6) ) +#define BIT_PUB_26M_SEL ( BIT(5) ) +#define BIT_AON_26M_SEL ( BIT(4) ) +#define BIT_CP1_26M_SEL ( BIT(2) ) +#define BIT_CP0_26M_SEL ( BIT(1) ) +#define BIT_AP_26M_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_BISR_DONE_STATUS */ +#define BIT_PD_CP1_COMWRAP_BISR_DONE ( BIT(21) ) +#define BIT_PD_CP1_LTE_P2_BISR_DONE ( BIT(20) ) +#define BIT_PD_CP1_LTE_P1_BISR_DONE ( BIT(19) ) +#define BIT_PD_CP1_CEVA_BISR_DONE ( BIT(18) ) +#define BIT_PD_CP1_CA5_BISR_DONE ( BIT(17) ) +#define BIT_PD_CP0_HU3GE_BISR_DONE ( BIT(15) ) +#define BIT_PD_CP0_TD_BISR_DONE ( BIT(14) ) +#define BIT_PD_CP0_GSM_1_BISR_DONE ( BIT(13) ) +#define BIT_PD_CP0_GSM_0_BISR_DONE ( BIT(12) ) +#define BIT_PD_CP0_CEVA_1_BISR_DONE ( BIT(11) ) +#define BIT_PD_CP0_CEVA_0_BISR_DONE ( BIT(10) ) +#define BIT_PD_CP0_ARM9_1_BISR_DONE ( BIT(9) ) +#define BIT_PD_CP0_ARM9_0_BISR_DONE ( BIT(8) ) +#define BIT_PD_MM_TOP_BISR_DONE ( BIT(7) ) +#define BIT_PD_GPU_TOP_BISR_DONE ( BIT(6) ) +#define BIT_PD_AP_SYS_BISR_DONE ( BIT(5) ) +#define BIT_PD_CA7_TOP_BISR_DONE ( BIT(4) ) +#define BIT_PD_CA7_C3_BISR_DONE ( BIT(3) ) +#define BIT_PD_CA7_C2_BISR_DONE ( BIT(2) ) +#define BIT_PD_CA7_C1_BISR_DONE ( BIT(1) ) +#define BIT_PD_CA7_C0_BISR_DONE ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_BISR_BUSY_STATUS */ +#define BIT_PD_CP1_COMWRAP_BISR_BUSY ( BIT(21) ) +#define BIT_PD_CP1_LTE_P2_BISR_BUSY ( BIT(20) ) +#define BIT_PD_CP1_LTE_P1_BISR_BUSY ( BIT(19) ) +#define BIT_PD_CP1_CEVA_BISR_BUSY ( BIT(18) ) +#define BIT_PD_CP1_CA5_BISR_BUSY ( BIT(17) ) +#define BIT_PD_CP0_HU3GE_BISR_BUSY ( BIT(15) ) +#define BIT_PD_CP0_TD_BISR_BUSY ( BIT(14) ) +#define BIT_PD_CP0_GSM_1_BISR_BUSY ( BIT(13) ) +#define BIT_PD_CP0_GSM_0_BISR_BUSY ( BIT(12) ) +#define BIT_PD_CP0_CEVA_1_BISR_BUSY ( BIT(11) ) +#define BIT_PD_CP0_CEVA_0_BISR_BUSY ( BIT(10) ) +#define BIT_PD_CP0_ARM9_1_BISR_BUSY ( BIT(9) ) +#define BIT_PD_CP0_ARM9_0_BISR_BUSY ( BIT(8) ) +#define BIT_PD_MM_TOP_BISR_BUSY ( BIT(7) ) +#define BIT_PD_GPU_TOP_BISR_BUSY ( BIT(6) ) +#define BIT_PD_AP_SYS_BISR_BUSY ( BIT(5) ) +#define BIT_PD_CA7_TOP_BISR_BUSY ( BIT(4) ) +#define BIT_PD_CA7_C3_BISR_BUSY ( BIT(3) ) +#define BIT_PD_CA7_C2_BISR_BUSY ( BIT(2) ) +#define BIT_PD_CA7_C1_BISR_BUSY ( BIT(1) ) +#define BIT_PD_CA7_C0_BISR_BUSY ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_BISR_BYP_CFG */ +#define BIT_PD_CP1_COMWRAP_BISR_FORCE_BYP ( BIT(21) ) +#define BIT_PD_CP1_LTE_P2_BISR_FORCE_BYP ( BIT(20) ) +#define BIT_PD_CP1_LTE_P1_BISR_FORCE_BYP ( BIT(19) ) +#define BIT_PD_CP1_CEVA_BISR_FORCE_BYP ( BIT(18) ) +#define BIT_PD_CP1_CA5_BISR_FORCE_BYP ( BIT(17) ) +#define BIT_PD_CP0_HU3GE_BISR_FORCE_BYP ( BIT(15) ) +#define BIT_PD_CP0_TD_BISR_FORCE_BYP ( BIT(14) ) +#define BIT_PD_CP0_GSM_1_BISR_FORCE_BYP ( BIT(13) ) +#define BIT_PD_CP0_GSM_0_BISR_FORCE_BYP ( BIT(12) ) +#define BIT_PD_CP0_CEVA_1_BISR_FORCE_BYP ( BIT(11) ) +#define BIT_PD_CP0_CEVA_0_BISR_FORCE_BYP ( BIT(10) ) +#define BIT_PD_CP0_ARM9_1_BISR_FORCE_BYP ( BIT(9) ) +#define BIT_PD_CP0_ARM9_0_BISR_FORCE_BYP ( BIT(8) ) +#define BIT_PD_MM_TOP_BISR_FORCE_BYP ( BIT(7) ) +#define BIT_PD_GPU_TOP_BISR_FORCE_BYP ( BIT(6) ) +#define BIT_PD_AP_SYS_BISR_FORCE_BYP ( BIT(5) ) +#define BIT_PD_CA7_TOP_BISR_FORCE_BYP ( BIT(4) ) +#define BIT_PD_CA7_C3_BISR_FORCE_BYP ( BIT(3) ) +#define BIT_PD_CA7_C2_BISR_FORCE_BYP ( BIT(2) ) +#define BIT_PD_CA7_C1_BISR_FORCE_BYP ( BIT(1) ) +#define BIT_PD_CA7_C0_BISR_FORCE_BYP ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_BISR_EN_CFG */ +#define BIT_PD_CP1_COMWRAP_BISR_FORCE_EN ( BIT(21) ) +#define BIT_PD_CP1_LTE_P2_BISR_FORCE_EN ( BIT(20) ) +#define BIT_PD_CP1_LTE_P1_BISR_FORCE_EN ( BIT(19) ) +#define BIT_PD_CP1_CEVA_BISR_FORCE_EN ( BIT(18) ) +#define BIT_PD_CP1_CA5_BISR_FORCE_EN ( BIT(17) ) +#define BIT_PD_CP0_HU3GE_BISR_FORCE_EN ( BIT(15) ) +#define BIT_PD_CP0_TD_BISR_FORCE_EN ( BIT(14) ) +#define BIT_PD_CP0_GSM_1_BISR_FORCE_EN ( BIT(13) ) +#define BIT_PD_CP0_GSM_0_BISR_FORCE_EN ( BIT(12) ) +#define BIT_PD_CP0_CEVA_1_BISR_FORCE_EN ( BIT(11) ) +#define BIT_PD_CP0_CEVA_0_BISR_FORCE_EN ( BIT(10) ) +#define BIT_PD_CP0_ARM9_1_BISR_FORCE_EN ( BIT(9) ) +#define BIT_PD_CP0_ARM9_0_BISR_FORCE_EN ( BIT(8) ) +#define BIT_PD_MM_TOP_BISR_FORCE_EN ( BIT(7) ) +#define BIT_PD_GPU_TOP_BISR_FORCE_EN ( BIT(6) ) +#define BIT_PD_AP_SYS_BISR_FORCE_EN ( BIT(5) ) +#define BIT_PD_CA7_TOP_BISR_FORCE_EN ( BIT(4) ) +#define BIT_PD_CA7_C3_BISR_FORCE_EN ( BIT(3) ) +#define BIT_PD_CA7_C2_BISR_FORCE_EN ( BIT(2) ) +#define BIT_PD_CA7_C1_BISR_FORCE_EN ( BIT(1) ) +#define BIT_PD_CA7_C0_BISR_FORCE_EN ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG0 */ +#define BITS_CGM_AUTO_GATE_SEL_CFG0(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG1 */ +#define BITS_CGM_AUTO_GATE_SEL_CFG1(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG2 */ +#define BITS_CGM_AUTO_GATE_SEL_CFG2(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG3 */ +#define BITS_CGM_AUTO_GATE_SEL_CFG3(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CGM_FORCE_EN_CFG0 */ +#define BITS_CGM_FORCE_EN_CFG0(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CGM_FORCE_EN_CFG1 */ +#define BITS_CGM_FORCE_EN_CFG1(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CGM_FORCE_EN_CFG2 */ +#define BITS_CGM_FORCE_EN_CFG2(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CGM_FORCE_EN_CFG3 */ +#define BITS_CGM_FORCE_EN_CFG3(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_SLEEP_XTLON_CTRL */ +#define BIT_ARM7_SLEEP_XTL_ON ( BIT(5) ) +#define BIT_VCP1_SLEEP_XTL_ON ( BIT(4) ) +#define BIT_VCP0_SLEEP_XTL_ON ( BIT(3) ) +#define BIT_CP1_SLEEP_XTL_ON ( BIT(2) ) +#define BIT_CP0_SLEEP_XTL_ON ( BIT(1) ) +#define BIT_AP_SLEEP_XTL_ON ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_MEM_SLP_CFG */ +#define BITS_MEM_SLP_CFG(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_MEM_SD_CFG */ +#define BITS_MEM_SD_CFG(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CA7_CORE_PU_LOCK */ +#define BIT_CA7_C3_GIC_WAKEUP_EN ( BIT(11) ) +#define BIT_CA7_C2_GIC_WAKEUP_EN ( BIT(10) ) +#define BIT_CA7_C1_GIC_WAKEUP_EN ( BIT(9) ) +#define BIT_CA7_C0_GIC_WAKEUP_EN ( BIT(8) ) +#define BIT_CA7_C3_PU_LOCK ( BIT(3) ) +#define BIT_CA7_C2_PU_LOCK ( BIT(2) ) +#define BIT_CA7_C1_PU_LOCK ( BIT(1) ) +#define BIT_CA7_C0_PU_LOCK ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_ARM7_HOLD_CGM_EN */ +#define BIT_PD_CP1_CEVA_CGM_HOLD_EN ( BIT(10) ) +#define BIT_PD_CP1_CA5_CGM_HOLD_EN ( BIT(9) ) +#define BIT_PD_CP0_CEVA_1_CGM_HOLD_EN ( BIT(8) ) +#define BIT_PD_CP0_CEVA_0_CGM_HOLD_EN ( BIT(7) ) +#define BIT_PD_CP0_ARM9_1_CGM_HOLD_EN ( BIT(6) ) +#define BIT_PD_CP0_ARM9_0_CGM_HOLD_EN ( BIT(5) ) +#define BIT_PD_CA7_TOP_CMG_HOLD_EN ( BIT(4) ) +#define BIT_PD_CA7_C3_CMG_HOLD_EN ( BIT(3) ) +#define BIT_PD_CA7_C2_CMG_HOLD_EN ( BIT(2) ) +#define BIT_PD_CA7_C1_CMG_HOLD_EN ( BIT(1) ) +#define BIT_PD_CA7_C0_CMG_HOLD_EN ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_PWR_CNT_WAIT_CFG0 */ +#define BITS_VCP0_PWR_WAIT_CNT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_CP1_PWR_WAIT_CNT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_CP0_PWR_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_AP_PWR_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PWR_CNT_WAIT_CFG1 */ +#define BITS_ARM7_PWR_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_VCP1_PWR_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_RC0_REL_CFG */ +#define BIT_RC0_ARM7_SEL ( BIT(5) ) +#define BIT_RC0_VCP1_SEL ( BIT(4) ) +#define BIT_RC0_VCP0_SEL ( BIT(3) ) +#define BIT_RC0_CP1_SEL ( BIT(2) ) +#define BIT_RC0_CP0_SEL ( BIT(1) ) +#define BIT_RC0_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_RC1_REL_CFG */ +#define BIT_RC1_ARM7_SEL ( BIT(5) ) +#define BIT_RC1_VCP1_SEL ( BIT(4) ) +#define BIT_RC1_VCP0_SEL ( BIT(3) ) +#define BIT_RC1_CP1_SEL ( BIT(2) ) +#define BIT_RC1_CP0_SEL ( BIT(1) ) +#define BIT_RC1_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_RC_CNT_WAIT_CFG */ +#define BITS_RC1_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_RC0_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_MEM_AUTO_SLP_CFG */ +#define BITS_MEM_AUTO_SLP_EN(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_MEM_AUTO_SD_CFG */ +#define BITS_MEM_AUTO_SD_EN(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CP0_PD_SHUTDOWN_CFG */ +#define BIT_PD_CP0_HU3GE_VCP1_SEL ( BIT(20) ) +#define BIT_PD_CP0_TD_VCP1_SEL ( BIT(19) ) +#define BIT_PD_CP0_GSM_0_VCP1_SEL ( BIT(18) ) +#define BIT_PD_CP0_CEVA_0_VCP1_SEL ( BIT(17) ) +#define BIT_PD_CP0_ARM9_1_VCP1_SEL ( BIT(16) ) +#define BIT_PD_CP0_ARM9_0_VCP0_SEL ( BIT(8) ) +#define BIT_PD_CP0_HU3GE_CP0_SEL ( BIT(5) ) +#define BIT_PD_CP0_TD_CP0_SEL ( BIT(4) ) +#define BIT_PD_CP0_GSM_0_CP0_SEL ( BIT(3) ) +#define BIT_PD_CP0_CEVA_0_CP0_SEL ( BIT(2) ) +#define BIT_PD_CP0_ARM9_1_CP0_SEL ( BIT(1) ) +#define BIT_PD_CP0_ARM9_0_CP0_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CP1_PD_SHUTDOWN_CFG */ +#define BIT_PD_CP1_COMWRAP_VCP1_SEL ( BIT(20) ) +#define BIT_PD_CP1_CEVA_VCP1_SEL ( BIT(19) ) +#define BIT_PD_CP1_LTE_P2_VCP1_SEL ( BIT(18) ) +#define BIT_PD_CP1_LTE_P1_VCP1_SEL ( BIT(17) ) +#define BIT_PD_CP1_CA5_VCP1_SEL ( BIT(16) ) +#define BIT_PD_CP1_COMWRAP_CP1_SEL ( BIT(4) ) +#define BIT_PD_CP1_CEVA_CP1_SEL ( BIT(3) ) +#define BIT_PD_CP1_LTE_P2_CP1_SEL ( BIT(2) ) +#define BIT_PD_CP1_LTE_P1_CP1_SEL ( BIT(1) ) +#define BIT_PD_CP1_CA5_CP1_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_WAKEUP_LOCK_EN */ +#define BIT_VCP1_SYS_WAKEUP_LOCK_EN ( BIT(26) ) +#define BIT_VCP0_SYS_WAKEUP_LOCK_EN ( BIT(25) ) +#define BIT_CP1_SYS_WAKEUP_LOCK_EN ( BIT(24) ) +#define BIT_CP0_SYS_WAKEUP_LOCK_EN ( BIT(23) ) +#define BIT_AP_SYS_WAKEUP_LOCK_EN ( BIT(22) ) +#define BIT_PD_PUB_SYS_WAKEUP_LOCK_EN ( BIT(21) ) +#define BIT_PD_CP1_COMWRAP_WAKEUP_LOCK_EN ( BIT(20) ) +#define BIT_PD_CP1_CEVA_WAKEUP_LOCK_EN ( BIT(19) ) +#define BIT_PD_CP1_LTE_P2_WAKEUP_LOCK_EN ( BIT(18) ) +#define BIT_PD_CP1_LTE_P1_WAKEUP_LOCK_EN ( BIT(17) ) +#define BIT_PD_CP1_CA5_WAKEUP_LOCK_EN ( BIT(16) ) +#define BIT_PD_CP0_CEVA_1_WAKEUP_LOCK_EN ( BIT(15) ) +#define BIT_PD_CP0_CEVA_0_WAKEUP_LOCK_EN ( BIT(14) ) +#define BIT_PD_CP0_TD_WAKEUP_LOCK_EN ( BIT(13) ) +#define BIT_PD_CP0_GSM_1_WAKEUP_LOCK_EN ( BIT(12) ) +#define BIT_PD_CP0_GSM_0_WAKEUP_LOCK_EN ( BIT(11) ) +#define BIT_PD_CP0_HU3GE_WAKEUP_LOCK_EN ( BIT(10) ) +#define BIT_PD_CP0_ARM9_1_WAKEUP_LOCK_EN ( BIT(9) ) +#define BIT_PD_CP0_ARM9_0_WAKEUP_LOCK_EN ( BIT(8) ) +#define BIT_PD_MM_TOP_WAKEUP_LOCK_EN ( BIT(7) ) +#define BIT_PD_GPU_TOP_WAKEUP_LOCK_EN ( BIT(6) ) +#define BIT_PD_AP_SYS_WAKEUP_LOCK_EN ( BIT(5) ) +#define BIT_PD_CA7_TOP_WAKEUP_LOCK_EN ( BIT(4) ) +#define BIT_PD_CA7_C3_WAKEUP_LOCK_EN ( BIT(3) ) +#define BIT_PD_CA7_C2_WAKEUP_LOCK_EN ( BIT(2) ) +#define BIT_PD_CA7_C1_WAKEUP_LOCK_EN ( BIT(1) ) +#define BIT_PD_CA7_C0_WAKEUP_LOCK_EN ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_PD_CA7_C0_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CA7_C0_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA7_C1_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CA7_C1_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA7_C2_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CA7_C2_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA7_C3_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CA7_C3_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA7_TOP_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CA7_TOP_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_AP_SYS_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_AP_SYS_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_GPU_TOP_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_GPU_TOP_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_MM_TOP_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_MM_TOP_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_0_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_ARM9_0_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_1_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_ARM9_1_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_CEVA_0_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_CEVA_0_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_CEVA_1_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_CEVA_1_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_GSM_0_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_GSM_0_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_GSM_1_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_GSM_1_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_TD_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_TD_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_HU3GE_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_HU3GE_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_CA5_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP1_CA5_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_CEVA_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP1_CEVA_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_LTE_P1_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP1_LTE_P1_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_LTE_P2_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP1_LTE_P2_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_COMWRAP_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP1_COMWRAP_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_PUB_SYS_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_PUB_SYS_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +#endif diff --git a/include/soc/sprd/chip_x20l/__regs_pub_apb.h b/include/soc/sprd/chip_x20l/__regs_pub_apb.h new file mode 100644 index 00000000..47462703 --- /dev/null +++ b/include/soc/sprd/chip_x20l/__regs_pub_apb.h @@ -0,0 +1,509 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_PUB_APB_HEADFILE_H__ +#define __H_REGS_PUB_APB_HEADFILE_H__ __FILE__ + +#define REGS_PUB_APB + +/* registers definitions for PUB_APB */ +#define REG_PUB_APB_BUSMON_CNT_START SCI_ADDR(REGS_PUB_APB_BASE, 0x0000) +#define REG_PUB_APB_BUSMON_CFG SCI_ADDR(REGS_PUB_APB_BASE, 0x0004) +#define REG_PUB_APB_DDR_EB SCI_ADDR(REGS_PUB_APB_BASE, 0x0008) +#define REG_PUB_APB_DDR_SOFT_RST SCI_ADDR(REGS_PUB_APB_BASE, 0x000C) +#define REG_PUB_APB_DDR_QOS_CFG1 SCI_ADDR(REGS_PUB_APB_BASE, 0x0010) +#define REG_PUB_APB_DDR_QOS_CFG2 SCI_ADDR(REGS_PUB_APB_BASE, 0x0014) +#define REG_PUB_APB_DDR_QOS_CFG3 SCI_ADDR(REGS_PUB_APB_BASE, 0x0018) +#define REG_PUB_APB_DDR_MRR_STATUS SCI_ADDR(REGS_PUB_APB_BASE, 0x001C) +#define REG_PUB_APB_DDR_ID2QOS_SEL SCI_ADDR(REGS_PUB_APB_BASE, 0x003C) +#define REG_PUB_APB_DDR_ID2QOS_RCFG0 SCI_ADDR(REGS_PUB_APB_BASE, 0x0040) +#define REG_PUB_APB_DDR_ID2QOS_RCFG1 SCI_ADDR(REGS_PUB_APB_BASE, 0x0044) +#define REG_PUB_APB_DDR_ID2QOS_RCFG2 SCI_ADDR(REGS_PUB_APB_BASE, 0x0048) +#define REG_PUB_APB_DDR_ID2QOS_RCFG3 SCI_ADDR(REGS_PUB_APB_BASE, 0x004c) +#define REG_PUB_APB_DDR_ID2QOS_RCFG4 SCI_ADDR(REGS_PUB_APB_BASE, 0x0050) +#define REG_PUB_APB_DDR_ID2QOS_RCFG5 SCI_ADDR(REGS_PUB_APB_BASE, 0x0054) +#define REG_PUB_APB_DDR_ID2QOS_RCFG6 SCI_ADDR(REGS_PUB_APB_BASE, 0x0058) +#define REG_PUB_APB_DDR_ID2QOS_RCFG7 SCI_ADDR(REGS_PUB_APB_BASE, 0x005c) +#define REG_PUB_APB_DDR_ID2QOS_RCFG8 SCI_ADDR(REGS_PUB_APB_BASE, 0x0060) +#define REG_PUB_APB_DDR_ID2QOS_RCFG9 SCI_ADDR(REGS_PUB_APB_BASE, 0x0064) +#define REG_PUB_APB_DDR_ID2QOS_WCFG0 SCI_ADDR(REGS_PUB_APB_BASE, 0x0080) +#define REG_PUB_APB_DDR_ID2QOS_WCFG1 SCI_ADDR(REGS_PUB_APB_BASE, 0x0084) +#define REG_PUB_APB_DDR_ID2QOS_WCFG2 SCI_ADDR(REGS_PUB_APB_BASE, 0x0088) +#define REG_PUB_APB_DDR_ID2QOS_WCFG3 SCI_ADDR(REGS_PUB_APB_BASE, 0x008c) +#define REG_PUB_APB_DDR_ID2QOS_WCFG4 SCI_ADDR(REGS_PUB_APB_BASE, 0x0090) +#define REG_PUB_APB_DDR_ID2QOS_WCFG5 SCI_ADDR(REGS_PUB_APB_BASE, 0x0094) +#define REG_PUB_APB_DDR_ID2QOS_WCFG6 SCI_ADDR(REGS_PUB_APB_BASE, 0x0098) +#define REG_PUB_APB_DDR_ID2QOS_WCFG7 SCI_ADDR(REGS_PUB_APB_BASE, 0x009c) +#define REG_PUB_APB_DDR_ID2QOS_WCFG8 SCI_ADDR(REGS_PUB_APB_BASE, 0x00a0) +#define REG_PUB_APB_DDR_ID2QOS_WCFG9 SCI_ADDR(REGS_PUB_APB_BASE, 0x00a4) +#define REG_PUB_APB_DFI_TIMEOUT_CFG SCI_ADDR(REGS_PUB_APB_BASE, 0x0100) +#define REG_PUB_APB_DFI_TIMEOUT_STATUS SCI_ADDR(REGS_PUB_APB_BASE, 0x0104) +#define REG_PUB_APB_DFI_TIMEOUT_EN_CNT SCI_ADDR(REGS_PUB_APB_BASE, 0x0108) +#define REG_PUB_APB_DFI_TIMEOUT_VALID_CNT SCI_ADDR(REGS_PUB_APB_BASE, 0x010c) +#define REG_PUB_APB_DFI_BW_CTRL SCI_ADDR(REGS_PUB_APB_BASE, 0x0110)/*DFI_BW_CTRL*/ +#define REG_PUB_APB_DFI_BW_STS SCI_ADDR(REGS_PUB_APB_BASE, 0x0114)/*DFI_BW_STS*/ +#define REG_PUB_APB_DFI_BW_THR0 SCI_ADDR(REGS_PUB_APB_BASE, 0x0118)/*DFI_BW_THR0*/ +#define REG_PUB_APB_DFI_BW_THR1 SCI_ADDR(REGS_PUB_APB_BASE, 0x011c)/*DFI_BW_THR1*/ +#define REG_PUB_APB_DFI_BW_THR2 SCI_ADDR(REGS_PUB_APB_BASE, 0x0120)/*DFI_BW_THR2*/ +#define REG_PUB_APB_DFI_BW_THR3 SCI_ADDR(REGS_PUB_APB_BASE, 0x0124)/*DFI_BW_THR3*/ +#define REG_PUB_APB_DFI_BW_TWIN SCI_ADDR(REGS_PUB_APB_BASE, 0x0128)/*DFI_BW_TWIN*/ +#define REG_PUB_APB_DMC_PORT_REMAP_EN SCI_ADDR(REGS_PUB_APB_BASE, 0x3000) +#define REG_PUB_APB_DMC_PORTS_MPU_EN SCI_ADDR(REGS_PUB_APB_BASE, 0x3004) +#define REG_PUB_APB_DMC_PORT0_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3008) +#define REG_PUB_APB_DMC_PORT1_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x300C) +#define REG_PUB_APB_DMC_PORT2_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3010) +#define REG_PUB_APB_DMC_PORT3_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3014) +#define REG_PUB_APB_DMC_PORT4_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3018) +#define REG_PUB_APB_DMC_PORT5_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x301C) +#define REG_PUB_APB_DMC_PORT6_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3020) +#define REG_PUB_APB_DMC_PORT7_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3024) +#define REG_PUB_APB_DMC_PORT8_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3028) +#define REG_PUB_APB_DMC_PORT9_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x302C) +#define REG_PUB_APB_DMC_PORT0_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3030) +#define REG_PUB_APB_DMC_PORT1_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3034) +#define REG_PUB_APB_DMC_PORT2_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3038) +#define REG_PUB_APB_DMC_PORT3_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x303C) +#define REG_PUB_APB_DMC_PORT4_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3040) +#define REG_PUB_APB_DMC_PORT5_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3044) +#define REG_PUB_APB_DMC_PORT6_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3048) +#define REG_PUB_APB_DMC_PORT7_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3050) +#define REG_PUB_APB_DMC_PORT8_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3054) +#define REG_PUB_APB_DMC_PORT9_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3058) +#define REG_PUB_APB_DMC_PORT0_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x305C) +#define REG_PUB_APB_DMC_PORT1_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3060) +#define REG_PUB_APB_DMC_PORT2_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3064) +#define REG_PUB_APB_DMC_PORT3_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3068) +#define REG_PUB_APB_DMC_PORT4_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x306C) +#define REG_PUB_APB_DMC_PORT5_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3070) +#define REG_PUB_APB_DMC_PORT6_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3074) +#define REG_PUB_APB_DMC_PORT7_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3078) +#define REG_PUB_APB_DMC_PORT8_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x307C) +#define REG_PUB_APB_DMC_PORT9_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3080) + + + +/* bits definitions for register REG_PUB_APB_BUSMON_CNT_START */ +#define BIT_PUB_BUSMON_CNT_START ( BIT(0) ) + +/* bits definitions for register REG_PUB_APB_BUSMON_CFG */ +#define BIT_PUB_BUSMON9_EB ( BIT(25) ) +#define BIT_PUB_BUSMON8_EB ( BIT(24) ) +#define BIT_PUB_BUSMON7_EB ( BIT(23) ) +#define BIT_PUB_BUSMON6_EB ( BIT(22) ) +#define BIT_PUB_BUSMON5_EB ( BIT(21) ) +#define BIT_PUB_BUSMON4_EB ( BIT(20) ) +#define BIT_PUB_BUSMON3_EB ( BIT(19) ) +#define BIT_PUB_BUSMON2_EB ( BIT(18) ) +#define BIT_PUB_BUSMON1_EB ( BIT(17) ) +#define BIT_PUB_BUSMON0_EB ( BIT(16) ) +#define BIT_PUB_BUSMON9_SOFT_RST ( BIT(9) ) +#define BIT_PUB_BUSMON8_SOFT_RST ( BIT(8) ) +#define BIT_PUB_BUSMON7_SOFT_RST ( BIT(7) ) +#define BIT_PUB_BUSMON6_SOFT_RST ( BIT(6) ) +#define BIT_PUB_BUSMON5_SOFT_RST ( BIT(5) ) +#define BIT_PUB_BUSMON4_SOFT_RST ( BIT(4) ) +#define BIT_PUB_BUSMON3_SOFT_RST ( BIT(3) ) +#define BIT_PUB_BUSMON2_SOFT_RST ( BIT(2) ) +#define BIT_PUB_BUSMON1_SOFT_RST ( BIT(1) ) +#define BIT_PUB_BUSMON0_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_PUB_APB_DDR_EB */ + +/* bits definitions for register REG_PUB_APB_DDR_SOFT_RST */ + +/* bits definitions for register REG_PUB_APB_DDR_QOS_CFG1 */ +#define BITS_DMC_ARQOS_3(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_3(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_2(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_2(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_1(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_0(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_QOS_CFG2 */ +#define BITS_DMC_ARQOS_7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_7(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_6(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_6(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_5(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_5(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_4(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_QOS_CFG3 */ +#define BITS_DMC_ARQOS_9(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_9(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_8(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_8(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_MRR_STATUS */ +#define BIT_DDRC_CO_RD_MRR_DATA_VALID ( BIT(8) ) +#define BITS_DDRC_CO_RD_MRR_DATA(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_SEL */ +#define BITS_DMC_ID_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DMC_QOS_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG0 */ +#define BITS_DMC_ARQOS_0_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_0_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_0_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_0_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_0_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_0_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_0_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_0_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG1 */ +#define BITS_DMC_ARQOS_1_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_1_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_1_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_1_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_1_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_1_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_1_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_1_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG2 */ +#define BITS_DMC_ARQOS_2_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_2_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_2_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_2_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_2_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_2_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_2_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_2_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG3 */ +#define BITS_DMC_ARQOS_3_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_3_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_3_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_3_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_3_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_3_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_3_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_3_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG4 */ +#define BITS_DMC_ARQOS_4_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_4_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_4_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_4_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_4_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_4_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_4_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_4_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG5 */ +#define BITS_DMC_ARQOS_5_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_5_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_5_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_5_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_5_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_5_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_5_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_5_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG6 */ +#define BITS_DMC_ARQOS_6_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_6_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_6_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_6_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_6_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_6_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_6_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_6_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG7 */ +#define BITS_DMC_ARQOS_7_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_7_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_7_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_7_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_7_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_7_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_7_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_7_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG8 */ +#define BITS_DMC_ARQOS_8_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_8_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_8_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_8_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_8_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_8_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_8_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_8_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG9 */ +#define BITS_DMC_ARQOS_9_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_9_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_9_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_9_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_9_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_9_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_9_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_9_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG0 */ +#define BITS_DMC_AWQOS_0_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_0_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_0_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_0_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_0_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_0_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_0_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_0_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG1 */ +#define BITS_DMC_AWQOS_1_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_1_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_1_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_1_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_1_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_1_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_1_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_1_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG2 */ +#define BITS_DMC_AWQOS_2_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_2_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_2_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_2_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_2_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_2_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_2_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_2_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG3 */ +#define BITS_DMC_AWQOS_3_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_3_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_3_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_3_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_3_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_3_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_3_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_3_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG4 */ +#define BITS_DMC_AWQOS_4_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_4_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_4_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_4_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_4_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_4_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_4_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_4_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG5 */ +#define BITS_DMC_AWQOS_5_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_5_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_5_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_5_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_5_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_5_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_5_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_5_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG6 */ +#define BITS_DMC_AWQOS_6_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_6_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_6_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_6_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_6_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_6_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_6_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_6_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG7 */ +#define BITS_DMC_AWQOS_7_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_7_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_7_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_7_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_7_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_7_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_7_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_7_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG8 */ +#define BITS_DMC_AWQOS_8_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_8_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_8_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_8_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_8_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_8_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_8_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_8_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG9 */ +#define BITS_DMC_AWQOS_9_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_9_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_9_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_9_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_9_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_9_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_9_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_9_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DFI_TIMEOUT_CFG */ +#define BITS_DFI_TIMEOUT_THRESHOLD(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DFI_TIMEOUT_CLR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DFI_TIMEOUT_EN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DFI_TIMEOUT_STATUS */ +#define BITS_DFI_TIMEOUT_STATUS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DFI_TIMEOUT_EN_CNT */ +#define BITS_DFI_TIMEOUT_EN3_CNT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DFI_TIMEOUT_EN2_CNT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DFI_TIMEOUT_EN1_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DFI_TIMEOUT_EN0_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PUB_APB_DFI_TIMEOUT_VALID_CNT */ +#define BITS_DFI_TIMEOUT_VALID3_CNT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DFI_TIMEOUT_VALID2_CNT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DFI_TIMEOUT_VALID1_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DFI_TIMEOUT_VALID0_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PUB_APB_DFI_BW_CTRL */ +#define BITS_PUB_APB_DFI_BW_INT_THR(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_PUB_APB_DFI_BW_INT_EN ( BIT(16) ) +#define BITS_PUB_APB_DFI_BW_THR_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_PUB_APB_DFI_BW_EN ( BIT(0) ) + +/* bits definitions for register REG_PUB_APB_DFI_BW_STS */ +#define BITS_PUB_APB_DFI_BW_THR_SEL_NEW(_X_) ( (_X_) << 30 & (BIT(30)|BIT(31)) ) +#define BITS_PUB_APB_DFI_BW(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) + +/* bits definitions for register REG_PUB_APB_DFI_BW_THR0 */ +#define BITS_PUB_APB_DFI_BW_THR0(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DFI_BW_THR1 */ +#define BITS_PUB_APB_DFI_BW_THR1(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DFI_BW_THR2 */ +#define BITS_PUB_APB_DFI_BW_THR2(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DFI_BW_THR3 */ +#define BITS_PUB_APB_DFI_BW_THR3(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DFI_BW_TWIN */ +#define BITS_PUB_APB_DFI_BW_TWIN(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT_REMAP_EN */ +#define BITS_DMC_PORTS_REMAP_EN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_PUB_APB_DMC_PORTS_MPU_EN */ +#define BITS_DMC_PORTS_MPU_EN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_PUB_APB_DMC_PORT0_ADDR_REMAP */ +#define BITS_DMC_PORT0_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT1_ADDR_REMAP */ +#define BITS_DMC_PORT1_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT2_ADDR_REMAP */ +#define BITS_DMC_PORT2_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT3_ADDR_REMAP */ +#define BITS_DMC_PORT3_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT4_ADDR_REMAP */ +#define BITS_DMC_PORT4_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT5_ADDR_REMAP */ +#define BITS_DMC_PORT5_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT6_ADDR_REMAP */ +#define BITS_DMC_PORT6_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT7_ADDR_REMAP */ +#define BITS_DMC_PORT7_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT8_ADDR_REMAP */ +#define BITS_DMC_PORT8_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT9_ADDR_REMAP */ +#define BITS_DMC_PORT9_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT0_MPU_RANGE */ +#define BITS_DMC_PORT0_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT1_MPU_RANGE */ +#define BITS_DMC_PORT1_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT2_MPU_RANGE */ +#define BITS_DMC_PORT2_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT3_MPU_RANGE */ +#define BITS_DMC_PORT3_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT4_MPU_RANGE */ +#define BITS_DMC_PORT4_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT5_MPU_RANGE */ +#define BITS_DMC_PORT5_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT6_MPU_RANGE */ +#define BITS_DMC_PORT6_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT7_MPU_RANGE */ +#define BITS_DMC_PORT7_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT8_MPU_RANGE */ +#define BITS_DMC_PORT8_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT9_MPU_RANGE */ +#define BITS_DMC_PORT9_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT0_DUMP_ADDR */ +#define BITS_DMC_PORT0_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT1_DUMP_ADDR */ +#define BITS_DMC_PORT1_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT2_DUMP_ADDR */ +#define BITS_DMC_PORT2_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT3_DUMP_ADDR */ +#define BITS_DMC_PORT3_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT4_DUMP_ADDR */ +#define BITS_DMC_PORT4_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT5_DUMP_ADDR */ +#define BITS_DMC_PORT5_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT6_DUMP_ADDR */ +#define BITS_DMC_PORT6_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT7_DUMP_ADDR */ +#define BITS_DMC_PORT7_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT8_DUMP_ADDR */ +#define BITS_DMC_PORT8_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT9_DUMP_ADDR */ +#define BITS_DMC_PORT9_DUMP_ADDR(_X_) (_X_) + +#endif diff --git a/include/soc/sprd/chip_x20l/__regs_wcdma_ahb_rf.h b/include/soc/sprd/chip_x20l/__regs_wcdma_ahb_rf.h new file mode 100644 index 00000000..32d5cbb9 --- /dev/null +++ b/include/soc/sprd/chip_x20l/__regs_wcdma_ahb_rf.h @@ -0,0 +1,123 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_WCDMA_AHB_RF_HEADFILE_H__ +#define __H_REGS_WCDMA_AHB_RF_HEADFILE_H__ __FILE__ + +#define REGS_WCDMA_AHB_RF + +/* registers definitions for WCDMA_AHB_RF */ +#define REG_WCDMA_AHB_RF_AHB_EB0 SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0000) +#define REG_WCDMA_AHB_RF_AHB_RST0 SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0004) +#define REG_WCDMA_AHB_RF_ARCH_EB_REG SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0018) +#define REG_WCDMA_AHB_RF_AHB_REMAP SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x001C) +#define REG_WCDMA_AHB_RF_AHB_MISC_CTL SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0020) +#define REG_WCDMA_AHB_RF_AHB_MTX_PRI_SEL0 SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0024) +#define REG_WCDMA_AHB_RF_AHB_MTX_PRI_SEL1 SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0028) +#define REG_WCDMA_AHB_RF_AHB1_PAUSE SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x002C) +#define REG_WCDMA_AHB_RF_AHB_SLP_CTL SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0034) +#define REG_WCDMA_AHB_RF_AHB2_SLP_STS SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0038) +#define REG_WCDMA_AHB_RF_MCU_CLK_CTL SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x003C) +#define REG_WCDMA_AHB_RF_CHIP_ID SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x01FC) + + + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB_EB0 */ +#define BITS_WCDMA_EN(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BIT_BUSMON0_EN ( BIT(1) ) +#define BIT_SPINLOCK_EN ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB_RST0 */ +#define BIT_WCDMA_SOFT_RST ( BIT(3) ) +#define BIT_BUSMON0_SOFT_RST ( BIT(1) ) +#define BIT_SPINLOCK_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_ARCH_EB_REG */ +#define BIT_AHB_ARCH_EB ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB_REMAP */ +#define BIT_ARM_JTAG_EN_ARM1 ( BIT(1) ) +#define BIT_REMAP ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB_MISC_CTL */ +#define BIT_FORCE_WSYS_ACC_STOP ( BIT(3) ) +#define BIT_W_DMA_LSLP_EN ( BIT(2) ) +#define BIT_BUSMON0_SEL ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB_MTX_PRI_SEL0 */ +#define BITS_ARMMTX_M3TOS0_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ARMMTX_M3TOS0_ADJ_EN ( BIT(27) ) +#define BIT_ARMMTX_M3TOS0_RND_EN ( BIT(26) ) +#define BITS_ARMMTX_M3TOS0_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_ARMMTX_M2TOS0_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M2TOS0_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M2TOS0_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M2TOS0_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M1TOS0_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M1TOS0_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M1TOS0_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M1TOS0_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M0TOS0_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M0TOS0_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M0TOS0_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M0TOS0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB_MTX_PRI_SEL1 */ +#define BITS_ARMMTX_M6TOS0_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M6TOS0_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M6TOS0_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M6TOS0_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M5TOS0_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M5TOS0_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M5TOS0_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M5TOS0_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M4TOS0_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M4TOS0_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M4TOS0_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M4TOS0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB1_PAUSE */ +#define BIT_APB1_SLEEP ( BIT(3) ) +#define BIT_MCU1_DEEP_SLEEP_EN ( BIT(2) ) +#define BIT_MCU1_SYS_SLEEP_EN ( BIT(1) ) +#define BIT_MCU1_CORE_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB_SLP_CTL */ +#define BIT_MCUMTX_AUTO_GATE_EN ( BIT(4) ) +#define BIT_MCU_AUTO_GATE_EN ( BIT(3) ) +#define BIT_AHB_AUTO_GATE_EN ( BIT(2) ) +#define BIT_ARM1_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB2_SLP_STS */ +#define BIT_APB1_PERI_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_MCU_CLK_CTL */ +#define BITS_CLK_AHB_DIV(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_CLK_MCU_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_APB_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CLK_MCU_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_CHIP_ID */ +#define BITS_CHIP_ID(_X_) (_X_) + +#endif diff --git a/include/soc/sprd/chip_x20l/__regs_wcdma_apb_rf.h b/include/soc/sprd/chip_x20l/__regs_wcdma_apb_rf.h new file mode 100644 index 00000000..a5a57b74 --- /dev/null +++ b/include/soc/sprd/chip_x20l/__regs_wcdma_apb_rf.h @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_WCDMA_APB_RF_HEADFILE_H__ +#define __H_REGS_WCDMA_APB_RF_HEADFILE_H__ __FILE__ + +#define REGS_WCDMA_APB_RF + +/* registers definitions for WCDMA_APB_RF */ +#define REG_WCDMA_APB_RF_APB_EB SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0000) +#define REG_WCDMA_APB_RF_APB_RST SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0004) +#define REG_WCDMA_APB_RF_APB_SLEEP_ST SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0008) +#define REG_WCDMA_APB_RF_APB_MCU_RST SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0018) +#define REG_WCDMA_APB_RF_APB_CLK_SEL0 SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x001C) +#define REG_WCDMA_APB_RF_APB_CLK_DIV0 SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0020) +#define REG_WCDMA_APB_RF_APB_ARCH_EB SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0024) +#define REG_WCDMA_APB_RF_APB_SLP_CTL SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0028) + + + +/* bits definitions for register REG_WCDMA_APB_RF_APB_EB */ +#define BIT_TMR_RTC_EB ( BIT(6) ) +#define BIT_TMR_EB ( BIT(5) ) +#define BIT_SYSTMR_RTC_EB ( BIT(4) ) +#define BIT_SYSTMR_EB ( BIT(3) ) +#define BIT_UART0_EB ( BIT(2) ) +#define BIT_WDG_RTC_EB ( BIT(1) ) +#define BIT_WDG_EB ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_APB_RF_APB_RST */ +#define BIT_TMR_SOFT_RST ( BIT(3) ) +#define BIT_SYSTMR_SOFT_RST ( BIT(2) ) +#define BIT_UART0_SOFT_RST ( BIT(1) ) +#define BIT_WDG_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_APB_RF_APB_SLEEP_ST */ +#define BIT_CHIP_SLEEP_REC_CLR ( BIT(1) ) +#define BIT_CHIP_SLEEP_REC ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_APB_RF_APB_MCU_RST */ +#define BIT_MCU_SOFT_RST_SET ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_APB_RF_APB_CLK_SEL0 */ +#define BITS_CLK_UART0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_WCDMA_APB_RF_APB_CLK_DIV0 */ +#define BITS_CLK_UART0_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_WCDMA_APB_RF_APB_ARCH_EB */ +#define BIT_RTC_ARCH_EB ( BIT(1) ) +#define BIT_APB_ARCH_EB ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_APB_RF_APB_SLP_CTL */ +#define BIT_APB_PERI_FRC_ON ( BIT(1) ) +#define BIT_APB_PERI_FRC_SLP ( BIT(0) ) + +#endif diff --git a/include/soc/sprd/chip_x20l/__sc2723_regulator_map.h b/include/soc/sprd/chip_x20l/__sc2723_regulator_map.h new file mode 100644 index 00000000..7879ec63 --- /dev/null +++ b/include/soc/sprd/chip_x20l/__sc2723_regulator_map.h @@ -0,0 +1,128 @@ +/* + * Copyright (C) 2013 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +/* + * Regulator (0)Name, Regulator (1)Type, Power Off (2)Ctrl and (3)Bit, PWR_SEL (4) and (5) Bit, + * Voltage Trimming (6)Ctrl and (7)Bits, Calibration (8)Ctrl and (9)Bits, + * Voltage (10)Default, Voltage (11)Ctrl and (12)Bits, Voltage Select (13)Count and Voltage (14)List[ ... ...] + */ + + SCI_REGU_REG(vddcore, 0x12, ANA_REG_GLB_LDO_DCDC_PD, BIT(9), ANA_REG_GLB_PWR_SEL, BIT(0), + ANA_REG_GLB_DCDC_CORE_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_DCDC_CTRL15, BIT(14)|BIT(16)|BIT(18)|BIT(19), + 900, ANA_REG_GLB_DCDC_CORE_ADI, BIT(5)|BIT(6)|BIT(7), 8, 1100, 700, 800, 900, 1000, 650, 1200, 1300); + + SCI_REGU_REG(vddarm, 0x12, ANA_REG_GLB_LDO_DCDC_PD, BIT(10), ANA_REG_GLB_PWR_SEL, BIT(2), + ANA_REG_GLB_DCDC_ARM_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_DCDC_CTRL15, BIT(13)|BIT(16)|BIT(18)|BIT(19), + 900, ANA_REG_GLB_DCDC_ARM_ADI, BIT(5)|BIT(6)|BIT(7), 8, 1100, 700, 800, 900, 1000, 650, 1200, 1300); + + SCI_REGU_REG(vddmem, 0x12, ANA_REG_GLB_LDO_DCDC_PD, BIT(11), ANA_REG_GLB_PWR_SEL, BIT(3), + ANA_REG_GLB_DCDC_MEM_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_DCDC_CTRL15, BIT(13)|BIT(14)|BIT(16)|BIT(18)|BIT(19), + 1200, 0, 0, 2, 600, 3125); + + SCI_REGU_REG(vddgen, 0x12, ANA_REG_GLB_LDO_DCDC_PD, BIT(12), ANA_REG_GLB_PWR_SEL, BIT(4), + ANA_REG_GLB_DCDC_GEN_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_DCDC_CTRL15, BIT(15)|BIT(16)|BIT(18)|BIT(19), + 2400, 0, 0, 2, 600, 3125); + + SCI_REGU_REG(vddrf, 0x12, ANA_REG_GLB_LDO_DCDC_PD, BIT(13), ANA_REG_GLB_PWR_SEL, BIT(5), + ANA_REG_GLB_DCDC_RF_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_DCDC_CTRL15, BIT(13)|BIT(15)|BIT(16)|BIT(18)|BIT(19), + 1500, 0, 0, 2, 600, 3125); + + SCI_REGU_REG(vddcon, 0x2, ANA_REG_GLB_LDO_PD_CTRL, BIT(13), 0, 0, + ANA_REG_GLB_DCDC_CON_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_DCDC_CTRL15, BIT(14)|BIT(15)|BIT(16)|BIT(18)|BIT(19), + 1600, 0, 0, 2, 600, 3125); + + SCI_REGU_REG(vddwpa, 0x2, ANA_REG_GLB_LDO_PD_CTRL, BIT(14), 0, 0, + ANA_REG_GLB_DCDC_WPA_ADI, BIT(0)|BIT(1)|BIT(2), ANA_REG_GLB_DCDC_CTRL15, BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(18)|BIT(19), + 0, 0, 0, 0); + + SCI_REGU_REG(vddrf0, 0x10, ANA_REG_GLB_LDO_DCDC_PD, BIT(8), ANA_REG_GLB_PWR_SEL, BIT(11), + ANA_REG_GLB_LDO_V_CTRL0, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), ANA_REG_GLB_LDO_V_CTRL11, BIT(2)|BIT(16)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1150, 6250); + + SCI_REGU_REG(vddemmccore, 0x10, ANA_REG_GLB_LDO_DCDC_PD, BIT(7), ANA_REG_GLB_PWR_SEL, BIT(7), + ANA_REG_GLB_LDO_V_CTRL7, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), ANA_REG_GLB_LDO_V_CTRL11, BIT(5)|BIT(6)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 3000, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddgen1, 0x10, ANA_REG_GLB_LDO_DCDC_PD, BIT(6), ANA_REG_GLB_PWR_SEL, BIT(12), + ANA_REG_GLB_LDO_V_CTRL3, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_V_CTRL11, BIT(0)|BIT(2)|BIT(16)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1150, 6250); + + SCI_REGU_REG(vddgen0, 0x10, ANA_REG_GLB_LDO_DCDC_PD, BIT(4), ANA_REG_GLB_PWR_SEL, BIT(13), + ANA_REG_GLB_LDO_V_CTRL2, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6), ANA_REG_GLB_LDO_V_CTRL11, BIT(1)|BIT(2)|BIT(16)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1150, 6250); + + SCI_REGU_REG(vdddcxo, 0x10, ANA_REG_GLB_LDO_DCDC_PD, BIT(5), ANA_REG_GLB_PWR_SEL, BIT(8), + ANA_REG_GLB_LDO_V_CTRL8, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), ANA_REG_GLB_LDO_V_CTRL11, BIT(7)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vdd25, 0x10, ANA_REG_GLB_LDO_DCDC_PD, BIT(3), ANA_REG_GLB_PWR_SEL, BIT(6), + ANA_REG_GLB_LDO_V_CTRL10, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_LDO_V_CTRL11, BIT(8)|BIT(17)|BIT(18)|BIT(20), + 2800, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vdd28, 0x10, ANA_REG_GLB_LDO_DCDC_PD, BIT(2), ANA_REG_GLB_PWR_SEL, BIT(9), + ANA_REG_GLB_LDO_V_CTRL3, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_LDO_V_CTRL11, BIT(6)|BIT(7)|BIT(10)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 2800, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vdd18, 0x10, ANA_REG_GLB_LDO_DCDC_PD, BIT(1), ANA_REG_GLB_PWR_SEL, BIT(10), + ANA_REG_GLB_LDO_V_CTRL9, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_V_CTRL11, BIT(0)|BIT(16)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1150, 6250); + + SCI_REGU_REG(vddwifipa, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(11), 0, 0, + ANA_REG_GLB_LDO_V_CTRL0, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_LDO_V_CTRL11, BIT(5)|BIT(10)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 3300, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddsdcore, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(10), 0, 0, + ANA_REG_GLB_LDO_V_CTRL6, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), ANA_REG_GLB_LDO_V_CTRL11, BIT(5)|BIT(7)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 3000, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddsdio, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(0), 0, 0, + ANA_REG_GLB_LDO_V_CTRL4, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_LDO_V_CTRL11, BIT(3)|BIT(16)|BIT(18)|BIT(19)|BIT(20), + 3000, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddsim0, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(1), 0, 0, + ANA_REG_GLB_LDO_V_CTRL4, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), ANA_REG_GLB_LDO_V_CTRL11, BIT(8)|BIT(10)|BIT(17)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddsim1, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(2), 0, 0, + ANA_REG_GLB_LDO_V_CTRL5, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_LDO_V_CTRL11, BIT(10)|BIT(17)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddsim2, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(3), 0, 0, + ANA_REG_GLB_LDO_V_CTRL5, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), ANA_REG_GLB_LDO_V_CTRL11, BIT(8)|BIT(9)|BIT(17)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddcama, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(4), 0, 0, + ANA_REG_GLB_LDO_V_CTRL6, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_LDO_V_CTRL11, BIT(9)|BIT(17)|BIT(18)|BIT(20), + 2800, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddcamd, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(5), 0, 0, + ANA_REG_GLB_LDO_V_CTRL1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6), ANA_REG_GLB_LDO_V_CTRL11, BIT(1)|BIT(16)|BIT(18)|BIT(20), + 1500, 0, 0, 2, 1150, 6250); + + SCI_REGU_REG(vddcamio, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(6), 0, 0, + ANA_REG_GLB_LDO_V_CTRL1, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_V_CTRL11, BIT(0)|BIT(1)|BIT(16)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1150, 6250); + + SCI_REGU_REG(vddcammot, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(7), 0, 0, + ANA_REG_GLB_LDO_V_CTRL7, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_LDO_V_CTRL11, BIT(6)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 2800, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddusb, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(8), 0, 0, + ANA_REG_GLB_LDO_V_CTRL9, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_LDO_V_CTRL11, BIT(4)|BIT(16)|BIT(18)|BIT(19)|BIT(20), + 3300, 0, 0, 2, 1200, 10000); + diff --git a/include/soc/sprd/chip_x20l/__scx35l_clock_tree.h b/include/soc/sprd/chip_x20l/__scx35l_clock_tree.h new file mode 100644 index 00000000..992ad053 --- /dev/null +++ b/include/soc/sprd/chip_x20l/__scx35l_clock_tree.h @@ -0,0 +1,557 @@ +/* + * Copyright (C) 2013 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#define REG_0X20E0(_o_) SCI_ADDR(SPRD_AHB_BASE, (_o_)) +#define REG_0X2150(_o_) SCI_ADDR(SPRD_APBCKG_BASE, (_o_)) +#define REG_0X402E(_o_) SCI_ADDR(SPRD_AONAPB_BASE, (_o_)) +#define REG_0X402D(_o_) SCI_ADDR(SPRD_AONCKG_BASE, (_o_)) +#define REG_0X6010(_o_) SCI_ADDR(SPRD_GPUAPB_BASE, (_o_)) +#define REG_0X60D0(_o_) SCI_ADDR(SPRD_MMAHB_BASE, (_o_)) +#define REG_0X60E0(_o_) SCI_ADDR(SPRD_MMCKG_BASE, (_o_)) +#define REG_0X7130(_o_) SCI_ADDR(SPRD_APBREG_BASE, (_o_)) + +#define REG_0X402E0044 REG_0X402E(0x0044) +#define REG_0X402E004C REG_0X402E(0x004C) +#define REG_0X402E005C REG_0X402E(0x005C) +#define REG_0X402E0054 REG_0X402E(0x0054) +#define REG_0X402E0064 REG_0X402E(0x0064) +#define REG_0X20E00038 REG_0X20E0(0x0038) +#define REG_0X20E00054 REG_0X20E0(0x0054) +#define REG_0X402D0020 REG_0X402D(0x0020) +#define REG_0X402D002C REG_0X402D(0x002C) +#define REG_0X402D0030 REG_0X402D(0x0030) +#define REG_0X402E0000 REG_0X402E(0x0000) +#define REG_0X402D0034 REG_0X402D(0x0034) +#define REG_0X402E0004 REG_0X402E(0x0004) +#define REG_0X402D0038 REG_0X402D(0x0038) +#define REG_0X402D003C REG_0X402D(0x003C) +#define REG_0X402D0040 REG_0X402D(0x0040) +#define REG_0X402D0044 REG_0X402D(0x0044) +#define REG_0X402D0048 REG_0X402D(0x0048) +#define REG_0X402D004C REG_0X402D(0x004C) +#define REG_0X402D0050 REG_0X402D(0x0050) +#define REG_0X402D0054 REG_0X402D(0x0054) +#define REG_0X402D0058 REG_0X402D(0x0058) +#define REG_0X402D0068 REG_0X402D(0x0068) +#define REG_0X402D006C REG_0X402D(0x006C) +#define REG_0X402D0070 REG_0X402D(0x0070) +#define REG_0X402D0074 REG_0X402D(0x0074) +#define REG_0X402D0078 REG_0X402D(0x0078) +#define REG_0X402D007C REG_0X402D(0x007C) +#define REG_0X402D0080 REG_0X402D(0x0080) +#define REG_0X402D0090 REG_0X402D(0x0090) +#define REG_0X402D0098 REG_0X402D(0x0098) +#define REG_0X402D00C8 REG_0X402D(0x00C8) +#define REG_0X402D00CC REG_0X402D(0x00CC) +#define REG_0X402D00D0 REG_0X402D(0x00D0) +#define REG_0X21500020 REG_0X2150(0x0020) +#define REG_0X21500024 REG_0X2150(0x0024) +#define REG_0X20E00000 REG_0X20E0(0x0000) +#define REG_0X21500028 REG_0X2150(0x0028) +#define REG_0X2150002C REG_0X2150(0x002C) +#define REG_0X21500030 REG_0X2150(0x0030) +#define REG_0X21500034 REG_0X2150(0x0034) +#define REG_0X21500054 REG_0X2150(0x0054) +#define REG_0X21500058 REG_0X2150(0x0058) +#define REG_0X2150005C REG_0X2150(0x005C) +#define REG_0X21500060 REG_0X2150(0x0060) +#define REG_0X21500068 REG_0X2150(0x0068) +#define REG_0X21500070 REG_0X2150(0x0070) +#define REG_0X21500074 REG_0X2150(0x0074) +#define REG_0X2150007C REG_0X2150(0x007C) +#define REG_0X71300000 REG_0X7130(0x0000) +#define REG_0X21500084 REG_0X2150(0x0084) +#define REG_0X21500088 REG_0X2150(0x0088) +#define REG_0X2150008C REG_0X2150(0x008C) +#define REG_0X21500090 REG_0X2150(0x0090) +#define REG_0X21500094 REG_0X2150(0x0094) +#define REG_0X21500098 REG_0X2150(0x0098) +#define REG_0X2150009C REG_0X2150(0x009C) +#define REG_0X215000A0 REG_0X2150(0x00A0) +#define REG_0X215000A4 REG_0X2150(0x00A4) +#define REG_0X215000A8 REG_0X2150(0x00A8) +#define REG_0X215000AC REG_0X2150(0x00AC) +#define REG_0X215000B0 REG_0X2150(0x00B0) +#define REG_0X215000B4 REG_0X2150(0x00B4) +#define REG_0X215000B8 REG_0X2150(0x00B8) +#define REG_0X215000BC REG_0X2150(0x00BC) +#define REG_0X215000C0 REG_0X2150(0x00C0) +#define REG_0X215000C4 REG_0X2150(0x00C4) +#define REG_0X215000C8 REG_0X2150(0x00C8) +#define REG_0X215000CC REG_0X2150(0x00CC) +#define REG_0X60100020 REG_0X6010(0x0020) +#define REG_0X60E00020 REG_0X60E0(0x0020) +#define REG_0X60D00008 REG_0X60D0(0x0008) +#define REG_0X60D00000 REG_0X60D0(0x0000) +#define REG_0X60E00038 REG_0X60E0(0x0038) +#define REG_0X60E00030 REG_0X60E0(0x0030) +#define REG_0X60E00034 REG_0X60E0(0x0034) +#define REG_0X60E00028 REG_0X60E0(0x0028) +#define REG_0X60E00024 REG_0X60E0(0x0024) +#define REG_0X60E0002C REG_0X60E0(0x002C) + +/* + * Clock (0)Name, Clock (1)fixed rate, Clock Enable (2)Ctrl and (3)Bit, + * Clock Divisor (4)Ctrl and (5)Bit, Clock Parent (6)Ctrl and (7)Bit, + * and Parent Select (15)Count and (16)Lists[ ... ...] + */ + +SCI_CLK_ADD(ext_26m, 26000000, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(ext_32k, 32768, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(ext_26m_rf1, 26000000, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(ext_1m, 1000000, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(ext_2m, 2000000, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(ext_4m, 4000000, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_pad, 64000000, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_mpll, 0, 0, 0, + REG_0X402E0044, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, 0); + +SCI_CLK_ADD(clk_dpll, 0, 0, 0, + REG_0X402E004C, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, 0); + +SCI_CLK_ADD(clk_ltepll, 0, 0, 0, + REG_0X402E005C, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, 0); + +SCI_CLK_ADD(clk_twpll, 0, 0, 0, + REG_0X402E0054, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, 0); + +SCI_CLK_ADD(clk_lvdspll, 0, 0, 0, + REG_0X402E0064, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, 0); + +SCI_CLK_ADD(clk_768m, 0, 0, 0, + 2, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_512m, 0, 0, 0, + 3, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_384m, 0, 0, 0, + 4, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_312m, 0, 0, 0, + 5, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_307m2, 0, 0, 0, + 5, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_256m, 0, 0, 0, + 6, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_192m, 0, 0, 0, + 8, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_153m6, 0, 0, 0, + 10, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_128m, 0, 0, 0, + 12, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_96m, 0, 0, 0, + 16, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_76m8, 0, 0, 0, + 20, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_64m, 0, 0, 0, + 24, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_51m2, 0, 0, 0, + 30, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_48m, 0, 0, 0, + 32, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_38m4, 0, 0, 0, + 40, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_24m, 0, 0, 0, + 64, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_12m, 0, 0, 0, + 128, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_42m_d, 0, 0, 0, + 32, 0, 0, 0, + 1, &clk_dpll); + +SCI_CLK_ADD(clk_56m_m, 0, 0, 0, + 32, 0, 0, 0, + 1, &clk_mpll); + +SCI_CLK_ADD(clk_38m4_lte, 0, 0, 0, + 32, 0, 0, 0, + 1, &clk_ltepll); + +SCI_CLK_ADD(clk_44m_lvds, 0, 0, 0, + 32, 0, 0, 0, + 1, &clk_lvdspll); + +SCI_CLK_ADD(clk_614m4, 0, 0, 0, + 2, 0, 0, 0, + 1, &clk_ltepll); + +SCI_CLK_ADD(clk_mcu, 0, 0, 0, + REG_0X20E00038, BIT(4)|BIT(5)|BIT(6), REG_0X20E00054, BIT(0)|BIT(1)|BIT(2), + 7, &ext_26m, &clk_512m, &clk_768m, &clk_dpll, &clk_ltepll, &clk_twpll, &clk_mpll); + +SCI_CLK_ADD(clk_ca7_core, 0, 0, 0, + 0, 0, 0, 0, + 1, &clk_mcu); + +SCI_CLK_ADD(clk_ca7_axi, 0, 0, 0, + REG_0X20E00038, BIT(8)|BIT(9)|BIT(10), 0, 0, + 1, &clk_mcu); + +SCI_CLK_ADD(clk_ca7_dbg, 0, 0, 0, + REG_0X20E00038, BIT(16)|BIT(17)|BIT(18), 0, 0, + 1, &clk_mcu); + +SCI_CLK_ADD(clk_emc_4x, 0, 0, 0, + REG_0X402D0020, BIT(8)|BIT(9), REG_0X402D0020, BIT(0)|BIT(1)|BIT(2), + 8, &ext_26m, &clk_192m, &clk_307m2, &clk_384m, &clk_512m, &clk_614m4, &clk_768m, &clk_dpll); + +SCI_CLK_ADD(clk_pub_ahb, 0, 0, 0, + REG_0X402D002C, BIT(8)|BIT(9), REG_0X402D002C, BIT(0)|BIT(1), + 4, &ext_26m, &ext_4m, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_aon_apb, 0, 0, 0, + REG_0X402D0030, BIT(8)|BIT(9), REG_0X402D0030, BIT(0)|BIT(1), + 4, &ext_4m, &ext_26m, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_adi, 0, REG_0X402E0000, BIT(16), + 0, 0, REG_0X402D0034, BIT(0)|BIT(1), + 4, &ext_26m, &ext_4m, &clk_38m4, &clk_51m2); + +SCI_CLK_ADD(clk_aux0, 0, REG_0X402E0004, BIT(2), + 0, 0, REG_0X402D0038, BIT(0)|BIT(1)|BIT(2), + 7, &ext_32k, &ext_26m, &ext_26m_rf1, &ext_4m, &clk_42m_d, &clk_48m, &clk_56m_m); + +SCI_CLK_ADD(clk_aux1, 0, REG_0X402E0004, BIT(3), + 0, 0, REG_0X402D003C, BIT(0)|BIT(1)|BIT(2)|BIT(3), + 9, &ext_32k, &ext_26m, &ext_26m_rf1, &ext_4m, &clk_42m_d, &clk_48m, &clk_56m_m, &clk_38m4_lte, &clk_44m_lvds); + +SCI_CLK_ADD(clk_aux2, 0, REG_0X402E0004, BIT(4), + 0, 0, REG_0X402D0040, BIT(0)|BIT(1)|BIT(2)|BIT(3), + 9, &ext_32k, &ext_26m, &ext_26m_rf1, &ext_4m, &clk_42m_d, &clk_48m, &clk_56m_m, &clk_38m4_lte, &clk_44m_lvds); + +SCI_CLK_ADD(clk_probe, 0, REG_0X402E0004, BIT(5), + 0, 0, REG_0X402D0044, BIT(0)|BIT(1)|BIT(2)|BIT(3), + 9, &ext_32k, &ext_26m, &ext_26m_rf1, &ext_4m, &clk_42m_d, &clk_48m, &clk_56m_m, &clk_38m4_lte, &clk_44m_lvds); + +SCI_CLK_ADD(clk_pwm0, 0, REG_0X402E0000, BIT(4), + 0, 0, REG_0X402D0048, BIT(0)|BIT(1), + 4, &ext_32k, &ext_26m, &ext_26m_rf1, &clk_48m); + +SCI_CLK_ADD(clk_pwm1, 0, REG_0X402E0000, BIT(5), + 0, 0, REG_0X402D004C, BIT(0)|BIT(1), + 4, &ext_32k, &ext_26m, &ext_26m_rf1, &clk_48m); + +SCI_CLK_ADD(clk_pwm2, 0, REG_0X402E0000, BIT(6), + 0, 0, REG_0X402D0050, BIT(0)|BIT(1), + 4, &ext_32k, &ext_26m, &ext_26m_rf1, &clk_48m); + +SCI_CLK_ADD(clk_pwm3, 0, REG_0X402E0000, BIT(7), + 0, 0, REG_0X402D0054, BIT(0)|BIT(1), + 4, &ext_32k, &ext_26m, &ext_26m_rf1, &clk_48m); + +SCI_CLK_ADD(clk_efuse, 0, REG_0X402E0000, BIT(13), + 0, 0, REG_0X402D0058, BIT(0), + 1, &ext_26m); + +SCI_CLK_ADD(clk_thm, 0, REG_0X402E0004, BIT(1), + 0, 0, REG_0X402D0068, BIT(0), + 2, &ext_32k, &ext_1m); + +SCI_CLK_ADD(clk_mspi, 0, REG_0X402E0000, BIT(23), + 0, 0, REG_0X402D006C, BIT(0), + 4, &ext_26m, &clk_51m2, &clk_76m8, &clk_96m); + +SCI_CLK_ADD(clk_i2c, 0, REG_0X402E0000, BIT(31), + 0, 0, REG_0X402D0070, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_avs, 0, REG_0X402E0004, BIT(6), + 0, 0, REG_0X402D0074, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_aud, 0, REG_0X402E0000, BIT(18), + 0, 0, REG_0X402D0078, BIT(0), + 1, &ext_26m); + +SCI_CLK_ADD(clk_audif, 0, REG_0X402E0000, BIT(17), + 0, 0, REG_0X402D007C, BIT(0)|BIT(1), + 3, &ext_26m, &clk_38m4, &clk_51m2); + +SCI_CLK_ADD(clk_vbc, 0, REG_0X402E0000, BIT(19), + 0, 0, REG_0X402D0080, BIT(0), + 1, &ext_26m); + +SCI_CLK_ADD(clk_ca7_dap, 0, REG_0X402E0000, BIT(30), + 0, 0, REG_0X402D0090, BIT(0)|BIT(1), + 4, &ext_26m, &clk_76m8, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_ca7_ts, 0, REG_0X402E0000, BIT(28), + 0, 0, REG_0X402D0098, BIT(0)|BIT(1), + 4, &ext_32k, &ext_26m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_djtag_tck, 0, 0, 0, + 0, 0, REG_0X402D00C8, BIT(0), + 3, &ext_26m, &ext_4m, &clk_pad); + +SCI_CLK_ADD(clk_arm7_ahb, 0, 0, 0, + REG_0X402D00CC, BIT(8)|BIT(9), REG_0X402D00CC, BIT(0)|BIT(1), + 4, &ext_4m, &ext_26m, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_ca5_ts, 0, REG_0X402E0004, BIT(26), + 0, 0, REG_0X402D00D0, BIT(0)|BIT(1), + 4, &ext_32k, &ext_26m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_disp_emc, 0, REG_0X402E0004, BIT(11), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_gsp_emc, 0, REG_0X402E0004, BIT(13), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_ap_ahb, 0, 0, 0, + 0, 0, REG_0X21500020, BIT(0)|BIT(1), + 4, &ext_26m, &clk_76m8, &clk_128m, &clk_192m); + +SCI_CLK_ADD(clk_ap_apb, 0, 0, 0, + 0, 0, REG_0X21500024, BIT(0)|BIT(1), + 4, &ext_26m, &clk_64m, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_gsp, 0, REG_0X20E00000, BIT(3), + 0, 0, REG_0X21500028, BIT(0)|BIT(1), + 4, &clk_96m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_dispc0, 0, REG_0X20E00000, BIT(1), + REG_0X2150002C, BIT(8)|BIT(9)|BIT(10), REG_0X2150002C, BIT(0)|BIT(1), + 4, &clk_153m6, &clk_192m, &clk_256m, &clk_307m2); + +SCI_CLK_ADD(clk_dispc0_dbi, 0, 0, 0, + REG_0X21500030, BIT(8)|BIT(9)|BIT(10), REG_0X21500030, BIT(0)|BIT(1), + 4, &clk_128m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_dispc0_dpi, 0, 0, 0, + REG_0X21500034, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), REG_0X21500034, BIT(0)|BIT(1), + 5, &clk_128m, &clk_153m6, &clk_192m, &clk_384m, &clk_pad); + +SCI_CLK_ADD(clk_nandc_2x, 0, REG_0X20E00000, BIT(18), + 0, 0, REG_0X21500054, BIT(0)|BIT(1), + 4, &clk_192m, &clk_256m, &clk_307m2, &clk_384m); + +SCI_CLK_ADD(clk_nandc_ecc, 0, REG_0X20E00000, BIT(19), + 0, 0, REG_0X21500058, BIT(0), + 2, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_sdio0, 0, REG_0X20E00000, BIT(8), + REG_0X2150005C, BIT(8)|BIT(9)|BIT(10), REG_0X2150005C, BIT(0)|BIT(1), + 4, &ext_26m, &clk_256m, &clk_307m2, &clk_384m); + +SCI_CLK_ADD(clk_sdio1, 0, REG_0X20E00000, BIT(9), + 0, 0, REG_0X21500060, BIT(0)|BIT(1), + 4, &clk_48m, &clk_76m8, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_sdio2, 0, REG_0X20E00000, BIT(10), + 0, 0, REG_0X21500068, BIT(0)|BIT(1), + 4, &clk_48m, &clk_76m8, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_emmc, 0, REG_0X20E00000, BIT(11), + 0, 0, REG_0X21500070, BIT(0)|BIT(1), + 4, &ext_26m, &clk_256m, &clk_307m2, &clk_384m); + +SCI_CLK_ADD(clk_otg_ref, 0, REG_0X20E00000, BIT(4), + 0, 0, REG_0X21500074, BIT(0), + 2, &clk_12m, &clk_24m); + +SCI_CLK_ADD(clk_hsic_ref, 0, REG_0X20E00000, BIT(2), + 0, 0, REG_0X2150007C, BIT(0), + 2, &clk_12m, &clk_24m); + +SCI_CLK_ADD(clk_uart0, 0, REG_0X71300000, BIT(13), + REG_0X21500084, BIT(8)|BIT(9)|BIT(10), REG_0X21500084, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart1, 0, REG_0X71300000, BIT(14), + REG_0X21500088, BIT(8)|BIT(9)|BIT(10), REG_0X21500088, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart2, 0, REG_0X71300000, BIT(15), + REG_0X2150008C, BIT(8)|BIT(9)|BIT(10), REG_0X2150008C, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart3, 0, REG_0X71300000, BIT(16), + REG_0X21500090, BIT(8)|BIT(9)|BIT(10), REG_0X21500090, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart4, 0, REG_0X71300000, BIT(17), + REG_0X21500094, BIT(8)|BIT(9)|BIT(10), REG_0X21500094, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_i2c0, 0, REG_0X71300000, BIT(8), + REG_0X21500098, BIT(8)|BIT(9)|BIT(10), REG_0X21500098, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_i2c1, 0, REG_0X71300000, BIT(9), + REG_0X2150009C, BIT(8)|BIT(9)|BIT(10), REG_0X2150009C, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_i2c2, 0, REG_0X71300000, BIT(10), + REG_0X215000A0, BIT(8)|BIT(9)|BIT(10), REG_0X215000A0, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_i2c3, 0, REG_0X71300000, BIT(11), + REG_0X215000A4, BIT(8)|BIT(9)|BIT(10), REG_0X215000A4, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_i2c4, 0, REG_0X71300000, BIT(12), + REG_0X215000A8, BIT(8)|BIT(9)|BIT(10), REG_0X215000A8, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_spi0, 0, REG_0X71300000, BIT(5), + REG_0X215000AC, BIT(8)|BIT(9)|BIT(10), REG_0X215000AC, BIT(0)|BIT(1), + 5, &ext_26m, &clk_96m, &clk_153m6, &clk_192m, &clk_pad); + +SCI_CLK_ADD(clk_spi1, 0, REG_0X71300000, BIT(6), + REG_0X215000B0, BIT(8)|BIT(9)|BIT(10), REG_0X215000B0, BIT(0)|BIT(1), + 5, &ext_26m, &clk_96m, &clk_153m6, &clk_192m, &clk_pad); + +SCI_CLK_ADD(clk_spi2, 0, REG_0X71300000, BIT(7), + REG_0X215000B4, BIT(8)|BIT(9)|BIT(10), REG_0X215000B4, BIT(0)|BIT(1), + 5, &ext_26m, &clk_96m, &clk_153m6, &clk_192m, &clk_pad); + +SCI_CLK_ADD(clk_iis0, 0, REG_0X71300000, BIT(1), + REG_0X215000B8, BIT(8)|BIT(9)|BIT(10), REG_0X215000B8, BIT(0)|BIT(1), + 4, &ext_26m, &clk_128m, &clk_153m6, &clk_pad); + +SCI_CLK_ADD(clk_iis1, 0, REG_0X71300000, BIT(2), + REG_0X215000BC, BIT(8)|BIT(9)|BIT(10), REG_0X215000BC, BIT(0)|BIT(1), + 4, &ext_26m, &clk_128m, &clk_153m6, &clk_pad); + +SCI_CLK_ADD(clk_iis2, 0, REG_0X71300000, BIT(3), + REG_0X215000C0, BIT(8)|BIT(9)|BIT(10), REG_0X215000C0, BIT(0)|BIT(1), + 4, &ext_26m, &clk_128m, &clk_153m6, &clk_pad); + +SCI_CLK_ADD(clk_iis3, 0, REG_0X71300000, BIT(4), + REG_0X215000C4, BIT(8)|BIT(9)|BIT(10), REG_0X215000C4, BIT(0)|BIT(1), + 4, &ext_26m, &clk_128m, &clk_153m6, &clk_pad); + +SCI_CLK_ADD(clk_zipenc, 0, REG_0X20E00000, BIT(20), + 0, 0, REG_0X215000C8, BIT(0)|BIT(1), + 4, &clk_96m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_zipdec, 0, REG_0X20E00000, BIT(21), + 0, 0, REG_0X215000CC, BIT(0)|BIT(1), + 4, &clk_96m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_gpu_i, 0, REG_0X402E0000, BIT(27), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_gpu, 0, REG_0X402E0000, BIT(27), + REG_0X60100020, BIT(8)|BIT(9), REG_0X60100020, BIT(0)|BIT(1)|BIT(2), + 6, &clk_153m6, &clk_192m, &clk_256m, &clk_307m2, &clk_384m, &clk_512m); + +SCI_CLK_ADD(clk_mm_i, 0, REG_0X402E0000, BIT(25), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_mm_ahb, 0, 0, 0, + 0, 0, REG_0X60E00020, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_mm_axi, 0, REG_0X60D00008, BIT(7), + 0, 0, 0, 0, + 1, &clk_mm_i); + +SCI_CLK_ADD(clk_mm_mtx_axi, 0, REG_0X60D00008, BIT(8), + 0, 0, 0, 0, + 1, &clk_mm_axi); + +SCI_CLK_ADD(clk_mmu, 0, REG_0X60D00000, BIT(7), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_mm_ckg, 0, REG_0X60D00000, BIT(6), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_jpg, 0, REG_0X60D00008, BIT(6), + 0, 0, REG_0X60E00038, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_256m, &clk_312m); + +SCI_CLK_ADD(clk_csi, 0, REG_0X60D00008, BIT(1), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_dcam_mipi, 0, REG_0X60D00008, BIT(0), + 0, 0, 0, 0, + 1, &clk_csi); + +SCI_CLK_ADD(clk_vsp, 0, REG_0X60D00008, BIT(5), + 0, 0, REG_0X60E00030, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_256m, &clk_312m); + +SCI_CLK_ADD(clk_isp, 0, REG_0X60D00008, BIT(4), + 0, 0, REG_0X60E00034, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_256m, &clk_312m); + +SCI_CLK_ADD(clk_ccir, 0, REG_0X60D00000, BIT(1), + 0, 0, REG_0X60E00028, BIT(16), + 2, &clk_24m, &clk_pad); + +SCI_CLK_ADD(clk_sensor, 0, REG_0X60D00008, BIT(2), + REG_0X60E00024, BIT(8)|BIT(9)|BIT(10), REG_0X60E00024, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_76m8, &clk_96m); + +SCI_CLK_ADD(clk_dcam, 0, REG_0X60D00008, BIT(3), + 0, 0, REG_0X60E0002C, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_256m, &clk_312m); + diff --git a/include/soc/sprd/chip_x30g/__clock_tree.h b/include/soc/sprd/chip_x30g/__clock_tree.h new file mode 100644 index 00000000..23461560 --- /dev/null +++ b/include/soc/sprd/chip_x30g/__clock_tree.h @@ -0,0 +1,548 @@ +/* + * Copyright (C) 2013 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +/* + * Clock (0)Name, Clock (1)fixed rate, Clock Enable (2)Ctrl and (3)Bit, + * Clock Divisor (4)Ctrl and (5)Bit, Clock Parent (6)Ctrl and (7)Bit, + * and Parent Select (15)Count and (16)Lists[ ... ...] + */ + +SCI_CLK_ADD(ext_26m, 26000000, REG_PMU_APB_CGM_AP_EN, BIT(0), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(ext_32k, 32768, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_mpll, 0, REG_PMU_APB_CGM_AP_EN, BIT(6), + REG_AON_APB_MPLL_CFG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_dpll, 0, REG_PMU_APB_CGM_AP_EN, BIT(1), + REG_AON_APB_DPLL_CFG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_td_sel_i, 0, REG_PMU_APB_TDPLL_REL_CFG, BIT(0), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_w_sel_i, 0, REG_PMU_APB_WPLL_REL_CFG, BIT(0), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_c_sel_i, 0, REG_PMU_APB_CPLL_REL_CFG, BIT(0), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_wifi_sel_i, 0, REG_PMU_APB_WIFIPLL1_REL_CFG, BIT(0), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_tdpll, 0, REG_PMU_APB_CGM_AP_EN, BIT(3), + REG_AON_APB_TDPLL_CFG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_wpll, 0, REG_PMU_APB_CGM_AP_EN, BIT(5), + REG_AON_APB_WPLL_CFG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, + 1, &clk_w_sel_i); + +SCI_CLK_ADD(clk_cpll, 0, REG_PMU_APB_CGM_AP_EN, BIT(2), + REG_AON_APB_CPLL_CFG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, + 1, &clk_c_sel_i); + +SCI_CLK_ADD(clk_wifipll, 0, REG_PMU_APB_CGM_AP_EN, BIT(4), + REG_AON_APB_WIFIPLL1_CFG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, + 1, &clk_wifi_sel_i); + +SCI_CLK_ADD(clk_460m8, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(20), + 2, 0, 0, 0, + 1, &clk_wpll); + +SCI_CLK_ADD(clk_300m, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(0), + 3, 0, 0, 0, + 1, &clk_mpll); + +SCI_CLK_ADD(clk_37m5, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(1), + 24, 0, 0, 0, + 1, &clk_mpll); + +SCI_CLK_ADD(clk_66m, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(2), + 16, 0, 0, 0, + 1, &clk_dpll); + +SCI_CLK_ADD(clk_51m2_w, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(23), + 18, 0, 0, 0, + 1, &clk_wpll); + +SCI_CLK_ADD(clk_40m, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(27), + 22, 0, 0, 0, + 1, &clk_wifipll); + +SCI_CLK_ADD(clk_312m, 0, REG_PMU_APB_CGM_AP_EN, BIT(7), + 2, 0, 0, 0, + 1, &clk_cpll); + +SCI_CLK_ADD(clk_208m, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(17), + 3, 0, 0, 0, + 1, &clk_cpll); + +SCI_CLK_ADD(clk_104m, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(18), + 6, 0, 0, 0, + 1, &clk_cpll); + +SCI_CLK_ADD(clk_52m, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(19), + 12, 0, 0, 0, + 1, &clk_cpll); + +SCI_CLK_ADD(clk_384m, 0, REG_PMU_APB_CGM_AP_EN, BIT(8), + 2, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_192m, 0, REG_PMU_APB_CGM_AP_EN, BIT(10), + 4, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_96m, 0, REG_PMU_APB_CGM_AP_EN, BIT(13), + 8, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_48m, 0, REG_PMU_APB_CGM_AP_EN, BIT(17), + 16, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_24m, 0, REG_PMU_APB_CGM_AP_EN, BIT(18), + 32, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_12m, 0, REG_PMU_APB_CGM_AP_EN, BIT(19), + 64, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_256m, 0, REG_PMU_APB_CGM_AP_EN, BIT(9), + 3, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_128m, 0, REG_PMU_APB_CGM_AP_EN, BIT(12), + 6, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_64m, 0, REG_PMU_APB_CGM_AP_EN, BIT(15), + 12, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_153m6, 0, REG_PMU_APB_CGM_AP_EN, BIT(11), + 5, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_51m2, 0, REG_PMU_APB_CGM_AP_EN, BIT(16), + 15, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_76m8, 0, REG_PMU_APB_CGM_AP_EN, BIT(14), + 10, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_38m4, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(15), + 20, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_mcu, 0, 0, 0, + REG_AP_AHB_CA7_CKG_CFG, BIT(4)|BIT(5)|BIT(6), REG_AP_AHB_CA7_CKG_CFG, BIT(0)|BIT(1)|BIT(2), + 7, &ext_26m, &clk_dpll, &clk_cpll, &clk_tdpll, &clk_wifipll, &clk_wpll, &clk_mpll); + +SCI_CLK_ADD(clk_arm, 0, 0, 0, + 0, 0, 0, 0, + 1, &clk_mcu); + +SCI_CLK_ADD(clk_axi, 0, 0, 0, + REG_AP_AHB_CA7_CKG_CFG, BIT(8)|BIT(9)|BIT(10), 0, 0, + 1, &clk_mcu); + +SCI_CLK_ADD(clk_dbg, 0, REG_AP_AHB_MISC_CKG_EN, BIT(8), + REG_AP_AHB_CA7_CKG_CFG, BIT(16)|BIT(17)|BIT(18), 0, 0, + 1, &clk_mcu); + +SCI_CLK_ADD(clk_ap_ahb, 0, 0, 0, + 0, 0, REG_AP_CLK_AP_AHB_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_76m8, &clk_128m, &clk_192m); + +SCI_CLK_ADD(clk_ap_apb, 0, 0, 0, + 0, 0, REG_AP_CLK_AP_APB_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_64m, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_pub_ahb, 0, 0, 0, + 0, 0, REG_AON_CLK_PUB_AHB_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_emc, 0, 0, 0, + REG_AON_CLK_EMC_CFG, BIT(8)|BIT(9), REG_AON_CLK_EMC_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_cpll, &clk_tdpll, &clk_dpll); + +SCI_CLK_ADD(clk_aon_apb, 0, 0, 0, + REG_AON_CLK_AON_APB_CFG, BIT(8)|BIT(9), REG_AON_CLK_AON_APB_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_76m8, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_disp_emc, 0, REG_AON_APB_APB_EB1, BIT(11), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_gsp_emc, 0, REG_AON_APB_APB_EB1, BIT(13), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_gsp, 0, REG_AP_AHB_AHB_EB, BIT(3), + 0, 0, REG_AP_CLK_GSP_CFG, BIT(0)|BIT(1), + 4, &clk_96m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_disc0, 0, REG_AP_AHB_AHB_EB, BIT(1), + REG_AP_CLK_DISPC0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_DISPC0_CFG, BIT(0)|BIT(1), + 4, &clk_153m6, &clk_192m, &clk_256m, &clk_312m); + +SCI_CLK_ADD(clk_disc0_dbi, 0, REG_AP_AHB_AHB_EB, BIT(1), + REG_AP_CLK_DISPC0_DBI_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_DISPC0_DBI_CFG, BIT(0)|BIT(1), + 4, &clk_128m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_disc0_dpi, 0, REG_AP_AHB_AHB_EB, BIT(1), + REG_AP_CLK_DISPC0_DPI_CFG, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), REG_AP_CLK_DISPC0_DPI_CFG, BIT(0)|BIT(1), + 4, &clk_128m, &clk_153m6, &clk_192m, &clk_384m); + +SCI_CLK_ADD(clk_disc1, 0, REG_AP_AHB_AHB_EB, BIT(2), + REG_AP_CLK_DISPC1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_DISPC1_CFG, BIT(0)|BIT(1), + 4, &clk_153m6, &clk_192m, &clk_256m, &clk_312m); + +SCI_CLK_ADD(clk_disc1_dbi, 0, REG_AP_AHB_AHB_EB, BIT(2), + REG_AP_CLK_DISPC1_DBI_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_DISPC1_DBI_CFG, BIT(0)|BIT(1), + 4, &clk_128m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_disc1_dpi, 0, REG_AP_AHB_AHB_EB, BIT(2), + REG_AP_CLK_DISPC1_DPI_CFG, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), REG_AP_CLK_DISPC1_DPI_CFG, BIT(0)|BIT(1), + 4, &clk_128m, &clk_153m6, &clk_192m, &clk_384m); + +/* +SCI_CLK_ADD(clk_zipdec_emc, 0, REG_AP_AHB_AHB_EB, BIT(21), + 0, 0, REG_AP_CLK_ZIPENC_CFG, BIT(0)|BIT(1), + 4, &clk_96m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_zipenc_emc, 0, REG_AP_AHB_AHB_EB, BIT(20), + 0, 0, REG_AP_CLK_ZIPENC_CFG, BIT(0)|BIT(1), + 4, &clk_96m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_nandc_ecc, 0, REG_AP_AHB_AHB_EB, BIT(19), + 0, 0, REG_AP_CLK_NANDC_ECC_CFG, BIT(0), + 2, &clk_153m6, &clk_192m); + +*/ +SCI_CLK_ADD(clk_nfc, 0, REG_AP_AHB_AHB_EB, BIT(6), + REG_AP_CLK_NFC_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_NFC_CFG, BIT(0)|BIT(1), + 3, &clk_64m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_sdio0, 0, REG_AP_AHB_AHB_EB, BIT(8), + REG_AP_CLK_SDIO0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_SDIO0_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_256m, &clk_312m, &clk_384m); + +SCI_CLK_ADD(clk_sdio1, 0, REG_AP_AHB_AHB_EB, BIT(9), + 0, 0, REG_AP_CLK_SDIO1_CFG, BIT(0)|BIT(1), + 4, &clk_48m, &clk_76m8, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_sdio2, 0, REG_AP_AHB_AHB_EB, BIT(10), + 0, 0, REG_AP_CLK_SDIO2_CFG, BIT(0)|BIT(1), + 4, &clk_48m, &clk_76m8, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_emmc, 0, REG_AP_AHB_AHB_EB, BIT(11), + 0, 0, REG_AP_CLK_EMMC_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_256m, &clk_312m, &clk_384m); + +SCI_CLK_ADD(clk_gps_tcxo, 64000000, REG_AP_CLK_GPS_TCXO_CFG, BIT(16), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_gps, 0, REG_AP_AHB_AHB_EB, BIT(12), + 0, 0, REG_AP_CLK_GPS_CFG, BIT(0), + 2, &clk_64m, &clk_76m8); + +SCI_CLK_ADD(clk_usb_ref, 0, REG_AP_AHB_AHB_EB, BIT(4), + 0, 0, REG_AP_CLK_USB_REF_CFG, BIT(0), + 2, &clk_12m, &clk_24m); + +SCI_CLK_ADD(clk_uart0, 0, REG_AP_APB_APB_EB, BIT(13), + REG_AP_CLK_UART0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_UART0_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart1, 0, REG_AP_APB_APB_EB, BIT(14), + REG_AP_CLK_UART1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_UART1_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart2, 0, REG_AP_APB_APB_EB, BIT(15), + REG_AP_CLK_UART2_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_UART2_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart3, 0, REG_AP_APB_APB_EB, BIT(16), + REG_AP_CLK_UART3_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_UART3_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart4, 0, REG_AP_APB_APB_EB, BIT(17), + REG_AP_CLK_UART4_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_UART4_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_i2c0, 0, REG_AP_APB_APB_EB, BIT(8), + REG_AP_CLK_I2C0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_I2C0_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_i2c1, 0, REG_AP_APB_APB_EB, BIT(9), + REG_AP_CLK_I2C1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_I2C1_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_i2c2, 0, REG_AP_APB_APB_EB, BIT(10), + REG_AP_CLK_I2C2_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_I2C2_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_i2c3, 0, REG_AP_APB_APB_EB, BIT(11), + REG_AP_CLK_I2C3_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_I2C3_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_i2c4, 0, REG_AP_APB_APB_EB, BIT(12), + REG_AP_CLK_I2C4_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_I2C4_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_spi0, 0, REG_AP_APB_APB_EB, BIT(5), + REG_AP_CLK_SPI0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_SPI0_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_spi1, 0, REG_AP_APB_APB_EB, BIT(6), + REG_AP_CLK_SPI1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_SPI1_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_spi2, 0, REG_AP_APB_APB_EB, BIT(7), + REG_AP_CLK_SPI2_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_SPI2_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_iis0, 0, REG_AP_APB_APB_EB, BIT(1), + REG_AP_CLK_IIS0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_IIS0_CFG, BIT(0)|BIT(1), + 3, &ext_26m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_iis1, 0, REG_AP_APB_APB_EB, BIT(2), + REG_AP_CLK_IIS1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_IIS1_CFG, BIT(0)|BIT(1), + 3, &ext_26m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_iis2, 0, REG_AP_APB_APB_EB, BIT(3), + REG_AP_CLK_IIS2_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_IIS2_CFG, BIT(0)|BIT(1), + 3, &ext_26m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_iis3, 0, REG_AP_APB_APB_EB, BIT(4), + REG_AP_CLK_IIS3_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_IIS3_CFG, BIT(0)|BIT(1), + 3, &ext_26m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_gpu_top_i, 0, REG_PMU_APB_PD_GPU_TOP_CFG+1, BIT(25), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_gpu_i, 0, REG_AON_APB_APB_EB0, BIT(27), + 0, 0, 0, 0, + 1, &clk_gpu_top_i); + +SCI_CLK_ADD(clk_gpu, 0, &clk_gpu_i, 0, + REG_GPU_APB_APB_CLK_CTRL, BIT(4)|BIT(5), REG_GPU_APB_APB_CLK_CTRL, BIT(0)|BIT(1)|BIT(2), + 7, &clk_153m6, &clk_208m, &clk_256m, &clk_300m, &clk_312m, &clk_384m, &clk_460m8); + +SCI_CLK_ADD(clk_mm_top_i, 0, REG_PMU_APB_PD_MM_TOP_CFG+1, BIT(25), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_mm_i, 0, REG_AON_APB_APB_EB0, BIT(25), + 0, 0, 0, 0, + 1, &clk_mm_top_i); + +SCI_CLK_ADD(clk_mm_ahb, 0, 0, 0, + 0, 0, REG_MM_CLK_MM_AHB_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_mm_mtx_axi, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(8), + 0, 0, 0, 0, + 1, &clk_mm_i); + +SCI_CLK_ADD(clk_mm_axi, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(7), + 0, 0, 0, 0, + 1, &clk_mm_mtx_axi); + +SCI_CLK_ADD(clk_mmu, 0, REG_MM_AHB_AHB_EB, BIT(7), + 0, 0, 0, 0, + 1, &clk_mm_ahb); +SCI_CLK_ADD(clk_mm_ckg_i, 0, REG_MM_AHB_AHB_EB, BIT(6), + 0, 0, 0, 0, + 1, &clk_mm_i); + +SCI_CLK_ADD(clk_jpg_i, 0, REG_MM_AHB_AHB_EB, BIT(5), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_jpg_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(6), + 0, 0, 0, 0, + 1, &clk_jpg_i); + +SCI_CLK_ADD(clk_jpg, 0, &clk_jpg_ckg_i, 0, + 0, 0, REG_MM_CLK_JPG_CFG, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_vsp_i, 0, REG_MM_AHB_AHB_EB, BIT(3), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_vsp_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(5), + 0, 0, 0, 0, + 1, &clk_vsp_i); + +SCI_CLK_ADD(clk_vsp, 0, &clk_vsp_ckg_i, 0, + 0, 0, REG_MM_CLK_VSP_CFG, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_isp_i, 0, REG_MM_AHB_AHB_EB, BIT(2), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_isp_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(4), + 0, 0, 0, 0, + 1, &clk_isp_i); + +SCI_CLK_ADD(clk_isp, 0, &clk_isp_ckg_i, 0, + 0, 0, REG_MM_CLK_ISP_CFG, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_256m, &clk_312m); + +SCI_CLK_ADD(clk_sensor_i, 0, REG_MM_AHB_AHB_EB, BIT(1), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_sensor_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(2), + 0, 0, 0, 0, + 1, &clk_sensor_i); + +SCI_CLK_ADD(clk_sensor, 0, &clk_sensor_ckg_i, 0, + REG_MM_CLK_SENSOR_CFG, BIT(8)|BIT(9)|BIT(10), REG_MM_CLK_SENSOR_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_76m8, &clk_96m); + +SCI_CLK_ADD(clk_ccir_in, 64000000, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_ccir_i, 0, REG_MM_AHB_AHB_EB, BIT(1), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_ccir, 0, &clk_ccir_i, 0, + 0, 0, REG_MM_CLK_CCIR_CFG, BIT(16), + 2, &clk_24m, &clk_ccir_in); + +SCI_CLK_ADD(clk_dcam_i, 0, REG_MM_AHB_AHB_EB, BIT(0), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_dcam_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(3), + 0, 0, 0, 0, + 1, &clk_dcam_i); + +SCI_CLK_ADD(clk_dcam, 0, &clk_dcam_ckg_i, 0, + 0, 0, REG_MM_CLK_DCAM_CFG, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_256m, &clk_312m); + +SCI_CLK_ADD(clk_csi_i, 0, REG_MM_AHB_AHB_EB, BIT(4), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_csi_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(1), + 0, 0, 0, 0, + 1, &clk_csi_i); + +SCI_CLK_ADD(clk_cphy_cfg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(0), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_dcam_mipi, 0, &clk_cphy_cfg_i, 0, + 0, 0, 0, 0, + 1, &clk_csi_ckg_i); + +SCI_CLK_ADD(clk_aud, 0, REG_AON_APB_APB_EB0, BIT(18), + 0, 0, 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_audif, 0, REG_AON_APB_APB_EB0, BIT(17), + 0, 0, REG_AON_CLK_AUDIF_CFG, BIT(0)|BIT(1), + 3, &ext_26m, &clk_38m4, &clk_51m2); + +SCI_CLK_ADD(clk_vbc, 0, REG_AON_APB_APB_EB0, BIT(19), + 0, 0, 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_fm_in, 64000000, REG_AON_CLK_FM_CFG, BIT(16), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_fm, 0, REG_AON_APB_APB_EB0, BIT(1), + 0, 0, 0, 0, + 1, &clk_fm_in); + +SCI_CLK_ADD(clk_adi, 0, REG_AON_APB_APB_EB0, BIT(16), + 0, 0, REG_AON_CLK_ADI_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_38m4, &clk_51m2, &clk_64m); + +SCI_CLK_ADD(clk_aux0, 0, REG_AON_APB_APB_EB1, BIT(2), + REG_AON_APB_AON_CGM_CFG, BIT(16)|BIT(17)|BIT(18)|BIT(19), REG_AON_APB_AON_CGM_CFG, BIT(0)|BIT(1)|BIT(2)|BIT(3), + 10, &ext_32k, &ext_26m, &ext_26m, &clk_48m, &clk_52m, &clk_51m2, &clk_37m5, &clk_40m, &clk_66m, &clk_40m); + +SCI_CLK_ADD(clk_aux1, 0, REG_AON_APB_APB_EB1, BIT(3), + REG_AON_APB_AON_CGM_CFG, BIT(20)|BIT(21)|BIT(22)|BIT(23), REG_AON_APB_AON_CGM_CFG, BIT(4)|BIT(5)|BIT(6)|BIT(7), + 10, &ext_32k, &ext_26m, &ext_26m, &clk_48m, &clk_52m, &clk_51m2, &clk_37m5, &clk_40m, &clk_66m, &clk_40m); + +SCI_CLK_ADD(clk_aux2, 0, REG_AON_APB_APB_EB1, BIT(4), + REG_AON_APB_AON_CGM_CFG, BIT(24)|BIT(25)|BIT(26)|BIT(27), REG_AON_APB_AON_CGM_CFG, BIT(8)|BIT(9)|BIT(10)|BIT(11), + 10, &ext_32k, &ext_26m, &ext_26m, &clk_48m, &clk_52m, &clk_51m2, &clk_37m5, &clk_40m, &clk_66m, &clk_40m); + +SCI_CLK_ADD(clk_pwm0, 0, REG_AON_APB_APB_EB0, BIT(4), + 0, 0, REG_AON_CLK_PWM0_CFG, BIT(0), + 2, &ext_32k, &ext_26m); + +SCI_CLK_ADD(clk_pwm1, 0, REG_AON_APB_APB_EB0, BIT(5), + 0, 0, REG_AON_CLK_PWM1_CFG, BIT(0), + 2, &ext_32k, &ext_26m); + +SCI_CLK_ADD(clk_pwm2, 0, REG_AON_APB_APB_EB0, BIT(6), + 0, 0, REG_AON_CLK_PWM2_CFG, BIT(0), + 2, &ext_32k, &ext_26m); + +SCI_CLK_ADD(clk_pwm3, 0, REG_AON_APB_APB_EB0, BIT(7), + 0, 0, REG_AON_CLK_PWM3_CFG, BIT(0), + 2, &ext_32k, &ext_26m); + +SCI_CLK_ADD(clk_efuse, 0, REG_AON_APB_APB_EB0, BIT(13), + 0, 0, 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_ca7_dap, 0, REG_AON_APB_APB_EB0, BIT(30), + 0, 0, REG_AON_CLK_CA7_DAP_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_76m8, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_ca7_ts, 0, REG_AON_APB_APB_EB0, BIT(28), + 0, 0, REG_AON_CLK_CA7_TS_CFG, BIT(0)|BIT(1), + 4, &ext_32k, &ext_26m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_mspi, 0, REG_AON_APB_APB_EB0, BIT(23), + 0, 0, REG_AON_CLK_MSPI_CFG, BIT(0)|BIT(1), + 3, &ext_26m, &clk_52m, &clk_76m8, &clk_96m); + +SCI_CLK_ADD(clk_i2c, 0, REG_AON_APB_APB_EB0, BIT(31), + 0, 0, REG_AON_CLK_I2C_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_avs0, 0, REG_AON_APB_APB_EB0, BIT(6), + 0, 0, REG_AON_CLK_AVS0_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_avs1, 0, REG_AON_APB_APB_EB0, BIT(7), + 0, 0, REG_AON_CLK_AVS1_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + diff --git a/include/soc/sprd/chip_x30g/__regs_ada_apb_rf.h b/include/soc/sprd/chip_x30g/__regs_ada_apb_rf.h new file mode 100644 index 00000000..0ca65ecf --- /dev/null +++ b/include/soc/sprd/chip_x30g/__regs_ada_apb_rf.h @@ -0,0 +1,177 @@ +/*
+ * Copyright (C) 2014 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+#ifndef __SCI_GLB_REGS_H__
+#error "Don't include this file directly, Pls include sci_glb_regs.h"
+#endif
+
+
+#ifndef __H_REGS_ADA_APB_RF_HEADFILE_H__
+#define __H_REGS_ADA_APB_RF_HEADFILE_H__ __FILE__
+
+#define REGS_ADA_APB_RF
+
+/* registers definitions for ADA_APB_RF */
+#define REG_ADA_APB_RF_APB_DAC_CTR0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0000)
+#define REG_ADA_APB_RF_APB_DAC_CTR1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0004)
+#define REG_ADA_APB_RF_APB_DAC_CTR2 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0008)
+#define REG_ADA_APB_RF_APB_DAC_CTR3 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x000C)
+#define REG_ADA_APB_RF_APB_DAC_CTR4 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0010)
+#define REG_ADA_APB_RF_APB_DAC_STS0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0014)
+#define REG_ADA_APB_RF_APB_DAC_STS1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0018)
+#define REG_ADA_APB_RF_APB_ADC0_CTR0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x001C)
+#define REG_ADA_APB_RF_APB_ADC0_CTR1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0020)
+#define REG_ADA_APB_RF_APB_ADC0_CTR2 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0024)
+#define REG_ADA_APB_RF_APB_ADC0_CTR3 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0028)
+#define REG_ADA_APB_RF_APB_CAL_CTR0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0030)
+#define REG_ADA_APB_RF_APB_CAL_CTR1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0034)
+#define REG_ADA_APB_RF_APB_CAL_CTR3 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x003C)
+#define REG_ADA_APB_RF_APB_CAL_STS0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0044)
+#define REG_ADA_APB_RF_APB_CAL_STS1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0048)
+#define REG_ADA_APB_RF_APB_ADA_CTRL0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0054)
+#define REG_ADA_APB_RF_APB_ADA_CTRL1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0058)
+#define REG_ADA_APB_RF_APB_RX_GSM_DFT SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x005C)
+#define REG_ADA_APB_RF_APB_RX_3G_DFT SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0060)
+
+
+
+/* bits definitions for register REG_ADA_APB_RF_APB_DAC_CTR0 */
+#define BITS_DAC_PCTRL_1(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
+#define BIT_DAC_OUT_SEL_1 ( BIT(17) )
+#define BIT_DAC_CLK_SEL_1 ( BIT(16) )
+#define BITS_DAC_PCTRL_0(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) )
+#define BIT_DAC_OUT_SEL_0 ( BIT(1) )
+#define BIT_DAC_CLK_SEL_0 ( BIT(0) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_DAC_CTR1 */
+#define BITS_DAC_WD_OVR(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DAC_WADDR_OVR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_DAC_WLE_OVR ( BIT(2) )
+#define BIT_DAC_W_OVR_I_QN ( BIT(1) )
+#define BIT_DAC_W_OVR_EN ( BIT(0) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_DAC_CTR2 */
+#define BITS_DAC_RSV(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) )
+#define BIT_DAC_IQ_OUT_MSB_INV ( BIT(21) )
+#define BIT_DAC_IQ_IN_MSB_INV ( BIT(20) )
+#define BIT_DAC_OVR_EN_CAL ( BIT(19) )
+#define BIT_DAC_EN_OOSCAL ( BIT(18) )
+#define BIT_DAC_IQ_SWAP ( BIT(17) )
+#define BIT_DAC_CAL_START ( BIT(16) )
+#define BITS_DAC_OFFSETI(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DAC_OFFSETQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_DAC_CTR3 */
+#define BITS_DAC_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) )
+#define BITS_DAC_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_DAC_CTR4 */
+#define BITS_DAC_I_CAL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) )
+#define BITS_DAC_Q_CAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_DAC_STS0 */
+#define BITS_DAC_WTI(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DAC_WTQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_DAC_STS1 */
+#define BITS_DAC_DA_STATE(_X_) ( (_X_) << 17 & (BIT(17)|BIT(18)) )
+#define BIT_DAC_DONE ( BIT(16) )
+#define BITS_DAC_WQ_OVR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_ADC0_CTR0 */
+#define BITS_ADC0_CALRDOUT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
+#define BIT_ADC0_CAL_SOFT_RST ( BIT(10) )
+#define BIT_ADC0_CALRD ( BIT(9) )
+#define BIT_ADC0_CALEN ( BIT(8) )
+#define BITS_ADC0_CALADDR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_ADC0_CTR1 */
+#define BITS_ADC0_DLL_OUT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
+#define BITS_ADC0_DLLOOF(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)) )
+#define BIT_ADC0_IQ_SWAP ( BIT(14) )
+#define BITS_ADC0_DLLIN(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
+#define BIT_ADC0_IQ_OUT_MSB_INV ( BIT(7) )
+#define BIT_ADC0_IQ_IN_MSB_INV ( BIT(6) )
+#define BIT_ADC0_DLL_SOFT_RST ( BIT(4) )
+#define BIT_ADC0_DLLWR ( BIT(3) )
+#define BIT_ADC0_DLLRD ( BIT(2) )
+#define BIT_ADC0_DLLEN ( BIT(1) )
+#define BIT_ADC0_DEBUG_EN ( BIT(0) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_ADC0_CTR2 */
+#define BITS_ADC0_RSV_0(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_ADC0_DIG_CLK_SEL_0 ( BIT(11) )
+#define BIT_ADC0_VCM_SEL_0 ( BIT(10) )
+#define BITS_ADC0_DELAY_CAP_0(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ADC0_BIT_SEL_0(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) )
+#define BITS_ADC0_VREF_SEL_0(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_ADC0_VREF_BOOST_0(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_ADC0_QUANT_BOOST_0(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_ADC0_CTR3 */
+#define BITS_ADC0_RSV_1(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_ADC0_DIG_CLK_SEL_1 ( BIT(11) )
+#define BIT_ADC0_VCM_SEL_1 ( BIT(10) )
+#define BITS_ADC0_DELAY_CAP_1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ADC0_BIT_SEL_1(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) )
+#define BITS_ADC0_VREF_SEL_1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_ADC0_VREF_BOOST_1(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_ADC0_QUANT_BOOST_1(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_CAL_CTR0 */
+#define BIT_LDO_EN_AUTO_EN ( BIT(27) )
+#define BIT_LDO_EN_FRC ( BIT(26) )
+#define BIT_BG_EN_AUTO_EN ( BIT(25) )
+#define BIT_BG_EN_FRC ( BIT(24) )
+#define BITS_ADC_CLK_CAL_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_ADA_CAL_WAIT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BIT_CLK_ADA_CAL_EN ( BIT(6) )
+#define BIT_DAC_PD_CAL ( BIT(5) )
+#define BIT_ADC0_EN_CAL ( BIT(3) )
+#define BIT_ADC0_CAL ( BIT(1) )
+#define BIT_ADA_MODE_SEL ( BIT(0) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_CAL_CTR1 */
+#define BITS_ADC0_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) )
+#define BITS_ADC0_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_CAL_CTR3 */
+#define BIT_ADA0_CAL_START ( BIT(0) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_CAL_STS0 */
+#define BIT_ADA0_CAL_DONE ( BIT(31) )
+#define BITS_ADC0_I_CAL_RESULT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_CAL_STS1 */
+#define BITS_ADC0_Q_CAL_RESULT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_ADA_CTRL0 */
+#define BITS_ADA_AUTO_CTRL(_X_) (_X_)
+
+/* bits definitions for register REG_ADA_APB_RF_APB_ADA_CTRL1 */
+#define BITS_ADA_FRC_CTRL(_X_) (_X_)
+
+/* bits definitions for register REG_ADA_APB_RF_APB_RX_GSM_DFT */
+#define BITS_RX_GSM_DFT_Q(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) )
+#define BITS_RX_GSM_DFT_I(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_RX_3G_DFT */
+#define BITS_RX_3G_DFT_Q(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) )
+#define BITS_RX_3G_DFT_I(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
+
+#endif
diff --git a/include/soc/sprd/chip_x30g/__regs_ahb_rf_cp2.h b/include/soc/sprd/chip_x30g/__regs_ahb_rf_cp2.h new file mode 100644 index 00000000..d7cf335a --- /dev/null +++ b/include/soc/sprd/chip_x30g/__regs_ahb_rf_cp2.h @@ -0,0 +1,160 @@ +/*
+ * Copyright (C) 2014 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+#ifndef __SCI_GLB_REGS_H__
+#error "Don't include this file directly, Pls include sci_glb_regs.h"
+#endif
+
+
+#ifndef __H_REGS_AHB_RF_CP2_HEADFILE_H__
+#define __H_REGS_AHB_RF_CP2_HEADFILE_H__ __FILE__
+
+#define REGS_AHB_RF_CP2
+
+/* registers definitions for AHB_RF_CP2 */
+#define REG_AHB_RF_CP2_AHB_RST0 SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x0000)
+#define REG_AHB_RF_CP2_AHB_EB0 SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x0004)
+#define REG_AHB_RF_CP2_ARCH_EB_REG SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x0084)
+#define REG_AHB_RF_CP2_AHB_BUS_CTL0 SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x00A0)
+#define REG_AHB_RF_CP2_AHB_BUS_CTL1 SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x00A4)
+#define REG_AHB_RF_CP2_AHB_BUS_CTL2 SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x00A8)
+#define REG_AHB_RF_CP2_AHB_SYS_CTL0 SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x00B0)
+#define REG_AHB_RF_CP2_AHB_SYS_CTL3 SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x00BC)
+#define REG_AHB_RF_CP2_AHB_SLP_CTL0 SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x00D0)
+#define REG_AHB_RF_CP2_AHB_SLP_CTL1 SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x00D4)
+#define REG_AHB_RF_CP2_AHB_SLP_CTL2 SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x00D8)
+#define REG_AHB_RF_CP2_AHB_SYS_CTL6 SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x00E0)
+#define REG_AHB_RF_CP2_AHB_SLP_STS0 SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x0100)
+#define REG_AHB_RF_CP2_AHB_MTX_CTL0 SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x0110)
+#define REG_AHB_RF_CP2_AHB_MTX_CTL1 SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x0114)
+#define REG_AHB_RF_CP2_AHB_MTX_CTL2 SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x0118)
+#define REG_AHB_RF_CP2_AHB_MTX_CTL3 SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x011C)
+#define REG_AHB_RF_CP2_AHB_MTX_CTL4 SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x0120)
+#define REG_AHB_RF_CP2_AHB_MTX_CTL5 SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x0124)
+#define REG_AHB_RF_CP2_AHB_MTX_CTL6 SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x0128)
+#define REG_AHB_RF_CP2_AHB_ARCH_PORT SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x0130)
+#define REG_AHB_RF_CP2_AHB_CHIP_ID SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x03FC)
+
+
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_RST0 */
+#define BIT_VPU_SOFT_RST ( BIT(3) )
+#define BIT_RFSBI_SOFT_RST ( BIT(2) )
+#define BIT_BUSM_SOFT_RST ( BIT(1) )
+#define BIT_DMA_SOFT_RST ( BIT(0) )
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_EB0 */
+#define BIT_WIFI_DBG_EB ( BIT(4) )
+#define BIT_BUSMON1_EB ( BIT(3) )
+#define BIT_BUSMON0_EB ( BIT(2) )
+#define BIT_RFSBI_EB ( BIT(1) )
+#define BIT_DMA_EB ( BIT(0) )
+
+/* bits definitions for register REG_AHB_RF_CP2_ARCH_EB_REG */
+#define BIT_ARCH_EB ( BIT(0) )
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_BUS_CTL0 */
+#define BIT_M5_PAUSE_HW0_EN ( BIT(5) )
+#define BIT_M4_PAUSE_HW0_EN ( BIT(4) )
+#define BIT_M3_PAUSE_HW0_EN ( BIT(3) )
+#define BIT_M2_PAUSE_HW0_EN ( BIT(2) )
+#define BIT_M1_PAUSE_HW0_EN ( BIT(1) )
+#define BIT_M0_PAUSE_HW0_EN ( BIT(0) )
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_BUS_CTL1 */
+#define BIT_M5_PAUSE_HW1_EN ( BIT(5) )
+#define BIT_M4_PAUSE_HW1_EN ( BIT(4) )
+#define BIT_M3_PAUSE_HW1_EN ( BIT(3) )
+#define BIT_M2_PAUSE_HW1_EN ( BIT(2) )
+#define BIT_M1_PAUSE_HW1_EN ( BIT(1) )
+#define BIT_M0_PAUSE_HW1_EN ( BIT(0) )
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_BUS_CTL2 */
+#define BIT_M5_PAUSE_SW ( BIT(5) )
+#define BIT_M4_PAUSE_SW ( BIT(4) )
+#define BIT_M3_PAUSE_SW ( BIT(3) )
+#define BIT_M2_PAUSE_SW ( BIT(2) )
+#define BIT_M1_PAUSE_SW ( BIT(1) )
+#define BIT_M0_PAUSE_SW ( BIT(0) )
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_SYS_CTL0 */
+#define BITS_WIFI_MON_OUT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)) )
+#define BITS_BUSMON1_CHN_SEL(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) )
+#define BITS_BUSMON0_CHN_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_WIFI_MON_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_SYS_CTL3 */
+#define BITS_DMA_REQ_HW_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) )
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_SLP_CTL0 */
+#define BIT_APB_STOP ( BIT(5) )
+#define BIT_MCU_CORE_SLP ( BIT(1) )
+#define BIT_MCU_FORCE_SYS_SLP ( BIT(0) )
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_SLP_CTL1 */
+#define BIT_MCU_LIGHT_SLEEP_EN ( BIT(8) )
+#define BIT_DMA_ACT_LIGHT_EN ( BIT(7) )
+#define BIT_DMA_SLP_MODE ( BIT(6) )
+#define BIT_MCU_DEEP_SLP_EN ( BIT(4) )
+#define BIT_MCU_SYS_SLP_EN ( BIT(3) )
+#define BIT_MCU_DMA_WAKE_UP_EN ( BIT(2) )
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_SLP_CTL2 */
+#define BITS_DMA_REQ_WAKE_EN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) )
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_SYS_CTL6 */
+#define BIT_PTEST ( BIT(0) )
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_SLP_STS0 */
+#define BIT_MTX_M5_STOP ( BIT(5) )
+#define BIT_MTX_M4_STOP ( BIT(4) )
+#define BIT_MTX_M3_STOP ( BIT(3) )
+#define BIT_MTX_M2_STOP ( BIT(2) )
+#define BIT_MTX_M1_STOP ( BIT(1) )
+#define BIT_MTX_M0_STOP ( BIT(0) )
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_MTX_CTL0 */
+#define BITS_MATRIX_CTRL0(_X_) (_X_)
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_MTX_CTL1 */
+#define BITS_MATRIX_CTRL1(_X_) (_X_)
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_MTX_CTL2 */
+#define BITS_MATRIX_CTRL2(_X_) (_X_)
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_MTX_CTL3 */
+#define BITS_MATRIX_CTRL3(_X_) (_X_)
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_MTX_CTL4 */
+#define BITS_MATRIX_CTRL4(_X_) (_X_)
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_MTX_CTL5 */
+#define BITS_MATRIX_CTRL5(_X_) (_X_)
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_MTX_CTL6 */
+#define BITS_MATRIX_CTRL6(_X_) (_X_)
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_ARCH_PORT */
+#define BIT_MCU_PROT ( BIT(16) )
+#define BITS_ARCH_PROT_VAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_CHIP_ID */
+#define BITS_ID_BASE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_MX_REG(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+#endif
diff --git a/include/soc/sprd/chip_x30g/__regs_ana_apb_if.h b/include/soc/sprd/chip_x30g/__regs_ana_apb_if.h new file mode 100644 index 00000000..aac3136d --- /dev/null +++ b/include/soc/sprd/chip_x30g/__regs_ana_apb_if.h @@ -0,0 +1,932 @@ +/*
+ * Copyright (C) 2014 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+#ifndef __SCI_GLB_REGS_H__
+#error "Don't include this file directly, Pls include sci_glb_regs.h"
+#endif
+
+
+#ifndef __H_REGS_ANA_APB_IF_HEADFILE_H__
+#define __H_REGS_ANA_APB_IF_HEADFILE_H__ __FILE__
+
+#define REGS_ANA_APB_IF
+
+/* registers definitions for ANA_APB_IF */
+#define REG_ANA_APB_IF_ARM_MODULE_EN SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0000)
+#define REG_ANA_APB_IF_ARM_CLK_EN SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0004)
+#define REG_ANA_APB_IF_RTC_CLK_EN SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0008)
+#define REG_ANA_APB_IF_ARM_RST SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x000C)
+#define REG_ANA_APB_IF_LDO_DCDC_PD_RTCSET SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0010)
+#define REG_ANA_APB_IF_LDO_DCDC_PD_RTCCLR SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0014)
+#define REG_ANA_APB_IF_RTC_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0018)
+#define REG_ANA_APB_IF_LDO_PD_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x001C)
+#define REG_ANA_APB_IF_LDO_V_CTRL0 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0020)
+#define REG_ANA_APB_IF_LDO_V_CTRL1 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0024)
+#define REG_ANA_APB_IF_LDO_V_CTRL2 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0028)
+#define REG_ANA_APB_IF_LDO_CAL_CTRL0 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x002C)
+#define REG_ANA_APB_IF_LDO_CAL_CTRL1 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0030)
+#define REG_ANA_APB_IF_LDO_CAL_CTRL2 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0034)
+#define REG_ANA_APB_IF_LDO_CAL_CTRL3 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0038)
+#define REG_ANA_APB_IF_LDO_CAL_CTRL4 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x003C)
+#define REG_ANA_APB_IF_LDO_CAL_CTRL5 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0040)
+#define REG_ANA_APB_IF_LDO_CAL_CTRL6 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0044)
+#define REG_ANA_APB_IF_AUXAD_CTL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0048)
+#define REG_ANA_APB_IF_DCDC_CTRL0 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x004C)
+#define REG_ANA_APB_IF_DCDC_CTRL1 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0050)
+#define REG_ANA_APB_IF_DCDC_CTRL2 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0054)
+#define REG_ANA_APB_IF_DCDC_CTRL3 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0058)
+#define REG_ANA_APB_IF_DCDC_CTRL4 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x005C)
+#define REG_ANA_APB_IF_DCDC_CTRL5 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0060)
+#define REG_ANA_APB_IF_DCDC_CTRL6 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0064)
+#define REG_ANA_APB_IF_DDR2_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0068)
+#define REG_ANA_APB_IF_SLP_WAIT_DCDCARM SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x006C)
+#define REG_ANA_APB_IF_LDO1828_XTL_CTL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0070)
+#define REG_ANA_APB_IF_LDO_SLP_CTRL0 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0074)
+#define REG_ANA_APB_IF_LDO_SLP_CTRL1 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0078)
+#define REG_ANA_APB_IF_LDO_SLP_CTRL2 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x007C)
+#define REG_ANA_APB_IF_LDO_SLP_CTRL3 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0080)
+#define REG_ANA_APB_IF_AUD_SLP_CTRL4 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0084)
+#define REG_ANA_APB_IF_DCDC_SLP_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0088)
+#define REG_ANA_APB_IF_XTL_WAIT_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x008C)
+#define REG_ANA_APB_IF_FLASH_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0090)
+#define REG_ANA_APB_IF_WHTLED_CTRL0 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0094)
+#define REG_ANA_APB_IF_WHTLED_CTRL1 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0098)
+#define REG_ANA_APB_IF_WHTLED_CTRL2 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x009C)
+#define REG_ANA_APB_IF_ANA_DRV_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00A0)
+#define REG_ANA_APB_IF_VIBR_CTRL0 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00A4)
+#define REG_ANA_APB_IF_VIBR_CTRL1 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00A8)
+#define REG_ANA_APB_IF_VIBR_CTRL2 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00AC)
+#define REG_ANA_APB_IF_VIBR_WR_PROT_VALUE SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00B0)
+#define REG_ANA_APB_IF_AUDIO_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00B4)
+#define REG_ANA_APB_IF_CHGR_CTRL0 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00B8)
+#define REG_ANA_APB_IF_CHGR_CTRL1 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00BC)
+#define REG_ANA_APB_IF_CHGR_CTRL2 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00C0)
+#define REG_ANA_APB_IF_CHGR_STATUS SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00C4)
+#define REG_ANA_APB_IF_ANA_MIXED_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00C8)
+#define REG_ANA_APB_IF_PWR_XTL_EN0 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00CC)
+#define REG_ANA_APB_IF_PWR_XTL_EN1 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00D0)
+#define REG_ANA_APB_IF_PWR_XTL_EN2 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00D4)
+#define REG_ANA_APB_IF_PWR_XTL_EN3 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00D8)
+#define REG_ANA_APB_IF_PWR_XTL_EN4 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00DC)
+#define REG_ANA_APB_IF_PWR_XTL_EN5 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00E0)
+#define REG_ANA_APB_IF_ANA_STATUS SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00E4)
+#define REG_ANA_APB_IF_POR_RST_MONITOR SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00E8)
+#define REG_ANA_APB_IF_WDG_RST_MONITOR SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00EC)
+#define REG_ANA_APB_IF_POR_PIN_RST_MONITOR SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00F0)
+#define REG_ANA_APB_IF_POR_SRC_FLAG SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00F4)
+#define REG_ANA_APB_IF_POR_7S_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00F8)
+#define REG_ANA_APB_IF_INT_DEBUG SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00FC)
+#define REG_ANA_APB_IF_GPI_DEBUG SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0100)
+#define REG_ANA_APB_IF_HWRST_RTC SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0104)
+#define REG_ANA_APB_IF_CHIP_ID_LOW SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0108)
+#define REG_ANA_APB_IF_CHIP_ID_HIGH SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x010C)
+#define REG_ANA_APB_IF_ARM_MF_REG SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0110)
+#define REG_ANA_APB_IF_AFUSE_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0114)
+#define REG_ANA_APB_IF_AFUSE_OUT0 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0118)
+#define REG_ANA_APB_IF_AFUSE_OUT1 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x011C)
+#define REG_ANA_APB_IF_AFUSE_OUT2 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0120)
+#define REG_ANA_APB_IF_AFUSE_OUT3 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0124)
+#define REG_ANA_APB_IF_CA_CTRL4 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0128)
+#define REG_ANA_APB_IF_MCU_WR_PROT_VALUE SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x012C)
+#define REG_ANA_APB_IF_MP_PWR_CTRL0 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0130 )
+#define REG_ANA_APB_IF_MP_PWR_CTRL1 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0134)
+#define REG_ANA_APB_IF_MP_PWR_CTRL2 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0138)
+#define REG_ANA_APB_IF_MP_PWR_CTRL3 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x013C)
+#define REG_ANA_APB_IF_MP_LDO_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0140)
+#define REG_ANA_APB_IF_MP_CHG_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0144)
+#define REG_ANA_APB_IF_MP_MISC_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0148)
+#define REG_ANA_APB_IF_MP_DCDC_DEDT_CTRL SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x014C)
+#define REG_ANA_APB_IF_CA_CTRL0 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0150)
+#define REG_ANA_APB_IF_CA_CTRL1 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0154)
+#define REG_ANA_APB_IF_CA_CTRL2 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0158)
+#define REG_ANA_APB_IF_CA_CTRL3 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x015C)
+#define REG_ANA_APB_IF_DCDC_CORE_ADI SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0160)
+#define REG_ANA_APB_IF_DCDC_ARM_ADI SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0164)
+#define REG_ANA_APB_IF_DCDC_MEM_ADI SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0168)
+#define REG_ANA_APB_IF_DCDC_GEN_ADI SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x016C)
+#define REG_ANA_APB_IF_DCDC_WRF_ADI SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0170)
+#define REG_ANA_APB_IF_DCDC_WPA_ADI SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0174)
+#define REG_ANA_APB_IF_DCDC_WPA_DCM_ADI SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x017C)
+
+
+
+/* bits definitions for register REG_ANA_APB_IF_ARM_MODULE_EN */
+#define BIT_ANA_THM_EN ( BIT(12) )
+#define BIT_ANA_BLTC_EN ( BIT(10) )
+#define BIT_ANA_PINREG_EN ( BIT(9) )
+#define BIT_ANA_FGU_EN ( BIT(8) )
+#define BIT_ANA_GPIO_EN ( BIT(7) )
+#define BIT_ANA_ADC_EN ( BIT(6) )
+#define BIT_ANA_HDT_EN ( BIT(5) )
+#define BIT_ANA_AUD_EN ( BIT(4) )
+#define BIT_ANA_EIC_EN ( BIT(3) )
+#define BIT_ANA_WDG_EN ( BIT(2) )
+#define BIT_ANA_RTC_EN ( BIT(1) )
+
+/* bits definitions for register REG_ANA_APB_IF_ARM_CLK_EN */
+#define BIT_ANA_CLK_AUXAD_EN ( BIT(9) )
+#define BIT_ANA_CLK_AUXADC_EN ( BIT(8) )
+#define BIT_ANA_CLK_AUD_HID_EN ( BIT(5) )
+#define BIT_ANA_CLK_AUD_HBD_EN ( BIT(4) )
+#define BIT_ANA_CLK_AUD_LOOP_EN ( BIT(3) )
+#define BIT_ANA_CLK_AUD_6P5M_EN ( BIT(2) )
+#define BIT_ANA_CLK_AUDIF_EN ( BIT(1) )
+
+/* bits definitions for register REG_ANA_APB_IF_RTC_CLK_EN */
+#define BIT_ANA_RTC_FLASH_EN ( BIT(13) )
+#define BIT_ANA_RTC_THMA_AUTO_EN ( BIT(12) )
+#define BIT_ANA_RTC_THMA_EN ( BIT(11) )
+#define BIT_ANA_RTC_THM_EN ( BIT(10) )
+#define BIT_ANA_RTC_BLTC_EN ( BIT(8) )
+#define BIT_ANA_RTC_FGU_EN ( BIT(7) )
+#define BIT_ANA_RTC_FGUA_EN ( BIT(6) )
+#define BIT_ANA_RTC_VIBR_EN ( BIT(5) )
+#define BIT_ANA_RTC_AUD_EN ( BIT(4) )
+#define BIT_ANA_RTC_EIC_EN ( BIT(3) )
+#define BIT_ANA_RTC_WDG_EN ( BIT(2) )
+#define BIT_ANA_RTC_RTC_EN ( BIT(1) )
+#define BIT_ANA_RTC_ARCH_EN ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_ARM_RST */
+#define BIT_ANA_THMA_SOFT_RST ( BIT(14) )
+#define BIT_ANA_THM_SOFT_RST ( BIT(13) )
+#define BIT_ANA_AUD_32K_SOFT_RST ( BIT(12) )
+#define BIT_ANA_AUDTX_SOFT_RST ( BIT(11) )
+#define BIT_ANA_AUDRX_SOFT_RST ( BIT(10) )
+#define BIT_ANA_AUD_SOFT_RST ( BIT(9) )
+#define BIT_ANA_AUD_HDT_SOFT_RST ( BIT(8) )
+#define BIT_ANA_GPIO_SOFT_RST ( BIT(7) )
+#define BIT_ANA_ADC_SOFT_RST ( BIT(6) )
+#define BIT_ANA_PWM0_SOFT_RST ( BIT(5) )
+#define BIT_ANA_FGU_SOFT_RST ( BIT(4) )
+#define BIT_ANA_EIC_SOFT_RST ( BIT(3) )
+#define BIT_ANA_WDG_SOFT_RST ( BIT(2) )
+#define BIT_ANA_RTC_SOFT_RST ( BIT(1) )
+#define BIT_ANA_BLTC_SOFT_RST ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_DCDC_PD_RTCSET */
+#define BIT_ANA_LDO_AVDD18_PD_RTCSET ( BIT(15) )
+#define BIT_ANA_DCDC_OTP_PD_RTCSET ( BIT(14) )
+#define BIT_ANA_DCDC_WRF_PD_RTCSET ( BIT(13) )
+#define BIT_ANA_DCDC_GEN_PD_RTCSET ( BIT(12) )
+#define BIT_ANA_DCDC_MEM_PD_RTCSET ( BIT(11) )
+#define BIT_ANA_DCDC_ARM_PD_RTCSET ( BIT(10) )
+#define BIT_ANA_DCDC_CORE_PD_RTCSET ( BIT(9) )
+#define BIT_ANA_LDO_EMMCCORE_PD_RTCSET ( BIT(8) )
+#define BIT_ANA_LDO_EMMCIO_PD_RTCSET ( BIT(7) )
+#define BIT_ANA_LDO_RF2_PD_RTCSET ( BIT(6) )
+#define BIT_ANA_LDO_RF1_PD_RTCSET ( BIT(5) )
+#define BIT_ANA_LDO_RF0_PD_RTCSET ( BIT(4) )
+#define BIT_ANA_LDO_VDD25_PD_RTCSET ( BIT(3) )
+#define BIT_ANA_LDO_VDD28_PD_RTCSET ( BIT(2) )
+#define BIT_ANA_LDO_VDD18_PD_RTCSET ( BIT(1) )
+#define BIT_ANA_BG_PD_RTCSET ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_DCDC_PD_RTCCLR */
+#define BIT_ANA_LDO_AVDD18_PD_RTCCLR ( BIT(15) )
+#define BIT_ANA_DCDC_OTP_PD_RTCCLR ( BIT(14) )
+#define BIT_ANA_DCDC_WRF_PD_RTCCLR ( BIT(13) )
+#define BIT_ANA_DCDC_GEN_PD_RTCCLR ( BIT(12) )
+#define BIT_ANA_DCDC_MEM_PD_RTCCLR ( BIT(11) )
+#define BIT_ANA_DCDC_ARM_PD_RTCCLR ( BIT(10) )
+#define BIT_ANA_DCDC_CORE_PD_RTCCLR ( BIT(9) )
+#define BIT_ANA_LDO_EMMCCORE_PD_RTCCLR ( BIT(8) )
+#define BIT_ANA_LDO_EMMCIO_PD_RTCCLR ( BIT(7) )
+#define BIT_ANA_LDO_RF2_PD_RTCCLR ( BIT(6) )
+#define BIT_ANA_LDO_RF1_PD_RTCCLR ( BIT(5) )
+#define BIT_ANA_LDO_RF0_PD_RTCCLR ( BIT(4) )
+#define BIT_ANA_LDO_VDD25_PD_RTCCLR ( BIT(3) )
+#define BIT_ANA_LDO_VDD28_PD_RTCCLR ( BIT(2) )
+#define BIT_ANA_LDO_VDD18_PD_RTCCLR ( BIT(1) )
+#define BIT_ANA_BG_PD_RTCCLR ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_RTC_CTRL */
+#define BITS_ANA_XOSC32K_CTL_STS(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BIT_ANA_XOSC32K_CTL_B3_RTCCLR ( BIT(7) )
+#define BIT_ANA_XOSC32K_CTL_B2_RTCCLR ( BIT(6) )
+#define BIT_ANA_XOSC32K_CTL_B1_RTCCLR ( BIT(5) )
+#define BIT_ANA_XOSC32K_CTL_B0_RTCCLR ( BIT(4) )
+#define BIT_ANA_XOSC32K_CTL_B3_RTCSET ( BIT(3) )
+#define BIT_ANA_XOSC32K_CTL_B2_RTCSET ( BIT(2) )
+#define BIT_ANA_XOSC32K_CTL_B1_RTCSET ( BIT(1) )
+#define BIT_ANA_XOSC32K_CTL_B0_RTCSET ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_PD_CTRL */
+#define BIT_ANA_LDO_LPREF_PD_SW ( BIT(12) )
+#define BIT_ANA_DCDC_WPA_PD ( BIT(11) )
+#define BIT_ANA_LDO_CLSG_PD ( BIT(10) )
+#define BIT_ANA_LDO_USB_PD ( BIT(9) )
+#define BIT_ANA_LDO_CAMMOT_PD ( BIT(8) )
+#define BIT_ANA_LDO_CAMIO_PD ( BIT(7) )
+#define BIT_ANA_LDO_CAMD_PD ( BIT(6) )
+#define BIT_ANA_LDO_CAMA_PD ( BIT(5) )
+#define BIT_ANA_LDO_SIM2_PD ( BIT(4) )
+#define BIT_ANA_LDO_SIM1_PD ( BIT(3) )
+#define BIT_ANA_LDO_SIM0_PD ( BIT(2) )
+#define BIT_ANA_LDO_SD_PD ( BIT(1) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_V_CTRL0 */
+#define BITS_ANA_LDO_EMMCCORE_V(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) )
+#define BITS_ANA_LDO_EMMCIO_V(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) )
+#define BITS_ANA_LDO_RF2_V(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
+#define BITS_ANA_LDO_RF1_V(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ANA_LDO_RF0_V(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) )
+#define BITS_ANA_LDO_VDD25_V(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_ANA_LDO_VDD28_V(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_ANA_LDO_VDD18_V(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_V_CTRL1 */
+#define BITS_ANA_LDO_SIM2_V(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ANA_LDO_SIM1_V(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) )
+#define BITS_ANA_LDO_SIM0_V(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_ANA_LDO_SD_V(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_ANA_LDO_AVDD18_V(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_V_CTRL2 */
+#define BITS_ANA_VBATBK_RES(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) )
+#define BITS_ANA_VBATBK_V(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) )
+#define BITS_ANA_LDO_CLSG_V(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
+#define BITS_ANA_LDO_USB_V(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ANA_LDO_CAMMOT_V(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) )
+#define BITS_ANA_LDO_CAMIO_V(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_ANA_LDO_CAMD_V(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_ANA_LDO_CAMA_V(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_CAL_CTRL0 */
+#define BITS_ANA_LDO_VDD25_CAL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_ANA_LDO_VDD28_CAL(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_ANA_LDO_VDD18_CAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_CAL_CTRL1 */
+#define BITS_ANA_LDO_RF2_CAL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_ANA_LDO_RF1_CAL(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_ANA_LDO_RF0_CAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_CAL_CTRL2 */
+#define BITS_ANA_LDO_USB_CAL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_ANA_LDO_EMMCCORE_CAL(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_ANA_LDO_EMMCIO_CAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_CAL_CTRL3 */
+#define BITS_ANA_LDO_SD_CAL(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_ANA_LDO_AVDD18_CAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_CAL_CTRL4 */
+#define BITS_ANA_LDO_CAMA_CAL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_ANA_LDO_SIM2_CAL(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_ANA_LDO_SIM_CAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_CAL_CTRL5 */
+#define BITS_ANA_LDO_CAMMOT_CAL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_ANA_LDO_CAMIO_CAL(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_ANA_LDO_CAMD_CAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_CAL_CTRL6 */
+#define BITS_ANA_LDOA_CAL_SEL(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)) )
+#define BITS_ANA_LDOD_CAL_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) )
+#define BITS_ANA_LDODCDC_CAL_SEL(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_ANA_LDO_CLSG_CAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_AUXAD_CTL */
+#define BIT_ANA_AUXAD_CURRENTSEN_EN ( BIT(6) )
+#define BIT_ANA_AUXAD_CURRENTSEL ( BIT(5) )
+#define BITS_ANA_AUXAD_CURRENT_IBS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_CTRL0 */
+#define BIT_ANA_DCDC_CORE_LP_EN ( BIT(15) )
+#define BIT_ANA_DCDC_CORE_CL_CTRL ( BIT(14) )
+#define BITS_ANA_DCDC_CORE_PDRSLOW(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
+#define BIT_ANA_DCDC_CORE_PFM ( BIT(9) )
+#define BIT_ANA_DCDC_CORE_DCM ( BIT(8) )
+#define BIT_ANA_DCDC_ARM_LP_EN ( BIT(7) )
+#define BIT_ANA_DCDC_ARM_CL_CTRL ( BIT(6) )
+#define BITS_ANA_DCDC_ARM_PDRSLOW(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+#define BIT_ANA_DCDC_ARM_PFM ( BIT(1) )
+#define BIT_ANA_DCDC_ARM_DCM ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_CTRL1 */
+#define BIT_ANA_DCDC_MEM_LP_EN ( BIT(15) )
+#define BIT_ANA_DCDC_MEM_CL_CTRL ( BIT(14) )
+#define BITS_ANA_DCDC_MEM_PDRSLOW(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
+#define BIT_ANA_DCDC_MEM_PFM ( BIT(9) )
+#define BIT_ANA_DCDC_MEM_DCM ( BIT(8) )
+#define BIT_ANA_DCDC_GEN_LP_EN ( BIT(7) )
+#define BIT_ANA_DCDC_GEN_CL_CTRL ( BIT(6) )
+#define BITS_ANA_DCDC_GEN_PDRSLOW(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+#define BIT_ANA_DCDC_GEN_PFM ( BIT(1) )
+#define BIT_ANA_DCDC_GEN_DCM ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_CTRL2 */
+#define BIT_ANA_DCDC_BG_LP_EN ( BIT(15) )
+#define BIT_ANA_DCDC_OTP_CHIP_PD_FLAG_CLR ( BIT(14) )
+#define BIT_ANA_DCDC_OTP_CHIP_PD_FLAG ( BIT(13) )
+#define BIT_ANA_DCDC_OTP_AUTO_PD_EN ( BIT(12) )
+#define BIT_ANA_DCDC_OTP_VBEOP ( BIT(11) )
+#define BITS_ANA_DCDC_OTP_S(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) )
+#define BIT_ANA_DCDC_WRF_LP_EN ( BIT(7) )
+#define BIT_ANA_DCDC_WRF_CL_CTRL ( BIT(6) )
+#define BITS_ANA_DCDC_WRF_PDRSLOW(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+#define BIT_ANA_DCDC_WRF_PFM ( BIT(1) )
+#define BIT_ANA_DCDC_WRF_DCM ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_CTRL3 */
+#define BIT_ANA_DCDC_WPA_LP_EN ( BIT(8) )
+#define BIT_ANA_DCDC_WPA_CL_CTRL ( BIT(7) )
+#define BIT_ANA_DCDC_WPA_ZXOP ( BIT(6) )
+#define BITS_ANA_DCDC_WPA_PDRSLOW(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+#define BIT_ANA_DCDC_WPA_PFM ( BIT(1) )
+#define BIT_ANA_DCDC_WPA_APTEN ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_CTRL4 */
+#define BIT_ANA_DCDC_CORE_OSCSYCEN_SW ( BIT(15) )
+#define BIT_ANA_DCDC_CORE_OSCSYCEN_HW_EN ( BIT(14) )
+#define BIT_ANA_DCDC_CORE_OSCSYC_DIV_EN ( BIT(13) )
+#define BITS_ANA_DCDC_CORE_OSCSYC_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
+#define BIT_ANA_DCDC_ARM_OSCSYCEN_SW ( BIT(7) )
+#define BIT_ANA_DCDC_ARM_OSCSYCEN_HW_EN ( BIT(6) )
+#define BIT_ANA_DCDC_ARM_OSCSYC_DIV_EN ( BIT(5) )
+#define BITS_ANA_DCDC_ARM_OSCSYC_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_CTRL5 */
+#define BIT_ANA_DCDC_MEM_OSCSYCEN_SW ( BIT(15) )
+#define BIT_ANA_DCDC_MEM_OSCSYCEN_HW_EN ( BIT(14) )
+#define BIT_ANA_DCDC_MEM_OSCSYC_DIV_EN ( BIT(13) )
+#define BITS_ANA_DCDC_MEM_OSCSYC_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
+#define BIT_ANA_DCDC_GEN_OSCSYCEN_SW ( BIT(7) )
+#define BIT_ANA_DCDC_GEN_OSCSYCEN_HW_EN ( BIT(6) )
+#define BIT_ANA_DCDC_GEN_OSCSYC_DIV_EN ( BIT(5) )
+#define BITS_ANA_DCDC_GEN_OSCSYC_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_CTRL6 */
+#define BIT_ANA_DCDC_WPA_OSCSYCEN_SW ( BIT(15) )
+#define BIT_ANA_DCDC_WPA_OSCSYCEN_HW_EN ( BIT(14) )
+#define BIT_ANA_DCDC_WPA_OSCSYC_DIV_EN ( BIT(13) )
+#define BITS_ANA_DCDC_WPA_OSCSYC_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
+#define BIT_ANA_DCDC_WRF_OSCSYCEN_SW ( BIT(7) )
+#define BIT_ANA_DCDC_WRF_OSCSYCEN_HW_EN ( BIT(6) )
+#define BIT_ANA_DCDC_WRF_OSCSYC_DIV_EN ( BIT(5) )
+#define BITS_ANA_DCDC_WRF_OSCSYC_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_DDR2_CTRL */
+#define BIT_ANA_DDR2_BUF_PD_HW ( BIT(9) )
+#define BITS_ANA_DDR2_BUF_S_DS(_X_) ( (_X_) << 7 & (BIT(7)|BIT(8)) )
+#define BITS_ANA_DDR2_BUF_CHNS_DS(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)) )
+#define BIT_ANA_DDR2_BUF_PD ( BIT(4) )
+#define BITS_ANA_DDR2_BUF_S(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_ANA_DDR2_BUF_CHNS(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_ANA_APB_IF_SLP_WAIT_DCDCARM */
+#define BITS_ANA_SLP_IN_WAIT_DCDCARM(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_ANA_SLP_OUT_WAIT_DCDCARM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO1828_XTL_CTL */
+#define BIT_ANA_LDO_VDD18_EXT_XTL2_EN ( BIT(11) )
+#define BIT_ANA_LDO_VDD18_EXT_XTL1_EN ( BIT(10) )
+#define BIT_ANA_LDO_VDD18_EXT_XTL0_EN ( BIT(9) )
+#define BIT_ANA_LDO_VDD18_XTL2_EN ( BIT(8) )
+#define BIT_ANA_LDO_VDD18_XTL1_EN ( BIT(7) )
+#define BIT_ANA_LDO_VDD18_XTL0_EN ( BIT(6) )
+#define BIT_ANA_LDO_VDD28_EXT_XTL2_EN ( BIT(5) )
+#define BIT_ANA_LDO_VDD28_EXT_XTL1_EN ( BIT(4) )
+#define BIT_ANA_LDO_VDD28_EXT_XTL0_EN ( BIT(3) )
+#define BIT_ANA_LDO_VDD28_XTL2_EN ( BIT(2) )
+#define BIT_ANA_LDO_VDD28_XTL1_EN ( BIT(1) )
+#define BIT_ANA_LDO_VDD28_XTL0_EN ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_SLP_CTRL0 */
+#define BIT_ANA_SLP_IO_EN ( BIT(15) )
+#define BIT_ANA_SLP_DCDC_OTP_PD_EN ( BIT(13) )
+#define BIT_ANA_SLP_DCDCGEN_PD_EN ( BIT(12) )
+#define BIT_ANA_SLP_DCDCWPA_PD_EN ( BIT(11) )
+#define BIT_ANA_SLP_DCDCWRF_PD_EN ( BIT(10) )
+#define BIT_ANA_SLP_DCDCARM_PD_EN ( BIT(9) )
+#define BIT_ANA_SLP_LDOEMMCCORE_PD_EN ( BIT(7) )
+#define BIT_ANA_SLP_LDOEMMCIO_PD_EN ( BIT(6) )
+#define BIT_ANA_SLP_LDORF2_PD_EN ( BIT(5) )
+#define BIT_ANA_SLP_LDORF1_PD_EN ( BIT(4) )
+#define BIT_ANA_SLP_LDORF0_PD_EN ( BIT(3) )
+#define BIT_ANA_SLP_LDOVDD25_PD_EN ( BIT(2) )
+#define BIT_ANA_SLP_LDOVDD28_PD_EN ( BIT(1) )
+#define BIT_ANA_SLP_LDOVDD18_PD_EN ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_SLP_CTRL1 */
+#define BIT_ANA_SLP_LDO_PD_EN ( BIT(12) )
+#define BIT_ANA_SLP_LDOLPREF_PD_EN ( BIT(11) )
+#define BIT_ANA_SLP_LDOCLSG_PD_EN ( BIT(10) )
+#define BIT_ANA_SLP_LDOUSB_PD_EN ( BIT(9) )
+#define BIT_ANA_SLP_LDOCAMMOT_PD_EN ( BIT(8) )
+#define BIT_ANA_SLP_LDOCAMIO_PD_EN ( BIT(7) )
+#define BIT_ANA_SLP_LDOCAMD_PD_EN ( BIT(6) )
+#define BIT_ANA_SLP_LDOCAMA_PD_EN ( BIT(5) )
+#define BIT_ANA_SLP_LDOSIM2_PD_EN ( BIT(4) )
+#define BIT_ANA_SLP_LDOSIM1_PD_EN ( BIT(3) )
+#define BIT_ANA_SLP_LDOSIM0_PD_EN ( BIT(2) )
+#define BIT_ANA_SLP_LDOSD_PD_EN ( BIT(1) )
+#define BIT_ANA_SLP_LDOAVDD18_PD_EN ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_SLP_CTRL2 */
+#define BIT_ANA_SLP_DCDC_BG_LP_EN ( BIT(15) )
+#define BIT_ANA_SLP_DCDCCORE_LP_EN ( BIT(11) )
+#define BIT_ANA_SLP_DCDCMEM_LP_EN ( BIT(10) )
+#define BIT_ANA_SLP_DCDCARM_LP_EN ( BIT(9) )
+#define BIT_ANA_SLP_DCDCGEN_LP_EN ( BIT(8) )
+#define BIT_ANA_SLP_DCDCWPA_LP_EN ( BIT(6) )
+#define BIT_ANA_SLP_DCDCWRF_LP_EN ( BIT(5) )
+#define BIT_ANA_SLP_LDOEMMCCORE_LP_EN ( BIT(4) )
+#define BIT_ANA_SLP_LDOEMMCIO_LP_EN ( BIT(3) )
+#define BIT_ANA_SLP_LDORF2_LP_EN ( BIT(2) )
+#define BIT_ANA_SLP_LDORF1_LP_EN ( BIT(1) )
+#define BIT_ANA_SLP_LDORF0_LP_EN ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_SLP_CTRL3 */
+#define BIT_ANA_SLP_BG_LP_EN ( BIT(15) )
+#define BIT_ANA_SLP_LDOVDD25_LP_EN ( BIT(13) )
+#define BIT_ANA_SLP_LDOVDD28_LP_EN ( BIT(12) )
+#define BIT_ANA_SLP_LDOVDD18_LP_EN ( BIT(11) )
+#define BIT_ANA_SLP_LDOCLSG_LP_EN ( BIT(10) )
+#define BIT_ANA_SLP_LDOUSB_LP_EN ( BIT(9) )
+#define BIT_ANA_SLP_LDOCAMMOT_LP_EN ( BIT(8) )
+#define BIT_ANA_SLP_LDOCAMIO_LP_EN ( BIT(7) )
+#define BIT_ANA_SLP_LDOCAMD_LP_EN ( BIT(6) )
+#define BIT_ANA_SLP_LDOCAMA_LP_EN ( BIT(5) )
+#define BIT_ANA_SLP_LDOSIM2_LP_EN ( BIT(4) )
+#define BIT_ANA_SLP_LDOSIM1_LP_EN ( BIT(3) )
+#define BIT_ANA_SLP_LDOSIM0_LP_EN ( BIT(2) )
+#define BIT_ANA_SLP_LDOSD_LP_EN ( BIT(1) )
+#define BIT_ANA_SLP_LDOAVDD18_LP_EN ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_AUD_SLP_CTRL4 */
+#define BIT_ANA_SLP_AUD_PA_SW_PD_EN ( BIT(15) )
+#define BIT_ANA_SLP_AUD_PA_LDO_PD_EN ( BIT(14) )
+#define BIT_ANA_SLP_AUD_PA_PD_EN ( BIT(13) )
+#define BIT_ANA_SLP_AUD_OVP_PD_PD_EN ( BIT(9) )
+#define BIT_ANA_SLP_AUD_OVP_LDO_PD_EN ( BIT(8) )
+#define BIT_ANA_SLP_AUD_VB_PD_EN ( BIT(7) )
+#define BIT_ANA_SLP_AUD_VBO_PD_EN ( BIT(6) )
+#define BIT_ANA_SLP_AUD_HEADMICBIAS_PD_EN ( BIT(5) )
+#define BIT_ANA_SLP_AUD_MICBIAS_HV_PD_EN ( BIT(2) )
+#define BIT_ANA_SLP_AUD_HEADMIC_PD_EN ( BIT(1) )
+#define BIT_ANA_SLP_AUD_PMUR1_PD_EN ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_SLP_CTRL */
+#define BITS_ANA_SLP_DCDCCORE_VOL_DROP_CNT(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_ANA_DCDC_CORE_CTL_DS_SW(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
+
+/* bits definitions for register REG_ANA_APB_IF_XTL_WAIT_CTRL */
+#define BIT_ANA_SLP_XTLBUF_PD_EN ( BIT(9) )
+#define BIT_ANA_XTL_EN ( BIT(8) )
+#define BITS_ANA_XTL_WAIT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_ANA_APB_IF_FLASH_CTRL */
+#define BIT_ANA_FLASH_PON ( BIT(15) )
+#define BIT_ANA_FLASH_V_HW_EN ( BIT(6) )
+#define BITS_ANA_FLASH_V_HW_STEP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_ANA_FLASH_V_SW(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_ANA_APB_IF_WHTLED_CTRL0 */
+#define BIT_ANA_WHTLED_PD_STS ( BIT(15) )
+#define BITS_ANA_WHTLED_DC(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BIT_ANA_WHTLED_BOOST_EN ( BIT(8) )
+#define BIT_ANA_WHTLED_SERIES_EN ( BIT(7) )
+#define BITS_ANA_WHTLED_V(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) )
+#define BIT_ANA_WHTLED_PD ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_WHTLED_CTRL1 */
+#define BIT_ANA_LCM_CABC_PWM_SEL ( BIT(15) )
+#define BIT_ANA_RTC_PWM0_EN ( BIT(14) )
+#define BIT_ANA_PWM0_EN ( BIT(13) )
+#define BITS_ANA_WHTLED_ISET(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_ANA_WHTLED_FRE_AD(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)) )
+#define BITS_ANA_WHTLED_CLMIT_OP(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_ANA_APB_IF_WHTLED_CTRL2 */
+#define BIT_ANA_WHTLED_DIMMING_SEL ( BIT(15) )
+#define BIT_ANA_WHTLED_PD_SEL ( BIT(14) )
+#define BIT_ANA_WHTLED_DIS_OVST ( BIT(13) )
+#define BIT_ANA_WHTLED_DIM_SEL ( BIT(12) )
+#define BIT_ANA_WHTLED_DE_BIAS ( BIT(11) )
+#define BIT_ANA_WHTLED_BUFF_SHT ( BIT(10) )
+#define BITS_ANA_WHTLED_STB_OP(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BIT_ANA_WHTLED_CAP_OPTION ( BIT(7) )
+#define BIT_ANA_WHTLED_OVP_DIS ( BIT(6) )
+#define BITS_ANA_WHTLED_REF_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+
+/* bits definitions for register REG_ANA_APB_IF_ANA_DRV_CTRL */
+#define BIT_ANA_SLP_RGB_PD_EN ( BIT(14) )
+#define BIT_ANA_RGB_PD_HW_EN ( BIT(13) )
+#define BITS_ANA_RGB_V(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
+#define BITS_ANA_KPLED_V(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_ANA_RGB_PD_SW ( BIT(2) )
+#define BIT_ANA_KPLED_PD ( BIT(1) )
+#define BIT_ANA_KPLED_PD_STS ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_VIBR_CTRL0 */
+#define BITS_ANA_VIBR_STABLE_V_HW(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_ANA_VIBR_INIT_V_HW(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_ANA_VIBR_V_SW(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_ANA_VIBR_PON ( BIT(2) )
+#define BIT_ANA_VIBR_SW_EN ( BIT(1) )
+
+/* bits definitions for register REG_ANA_APB_IF_VIBR_CTRL1 */
+#define BITS_ANA_VIBR_V_CONVERT_CNT_HW(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ANA_APB_IF_VIBR_CTRL2 */
+#define BIT_ANA_VIBR_PWR_ON_STS ( BIT(15) )
+#define BIT_ANA_VIBR_HW_FLOW_ERR1 ( BIT(14) )
+#define BIT_ANA_VIBR_HW_FLOW_ERR1_CLR ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_VIBR_WR_PROT_VALUE */
+#define BIT_ANA_VIBR_WR_PROT ( BIT(15) )
+#define BITS_ANA_VIBR_WR_PROT_VALUE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+
+/* bits definitions for register REG_ANA_APB_IF_AUDIO_CTRL */
+#define BIT_ANA_AUD_SLP_APP_RST_EN ( BIT(10) )
+#define BITS_ANA_CLK_AUD_HBD_DIV(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BIT_ANA_CLK_AUD_LOOP_INV_EN ( BIT(4) )
+#define BIT_ANA_CLK_AUDIF_TX_INV_EN ( BIT(3) )
+#define BIT_ANA_CLK_AUDIF_RX_INV_EN ( BIT(2) )
+#define BIT_ANA_CLK_AUD_6P5M_TX_INV_EN ( BIT(1) )
+#define BIT_ANA_CLK_AUD_6P5M_RX_INV_EN ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_CHGR_CTRL0 */
+#define BIT_ANA_CHGR_PD_STS ( BIT(15) )
+#define BITS_ANA_CHGR_CV_V(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_ANA_CHGR_END_V(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_ANA_CHG_PUMP_V(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BIT_ANA_CHGR_PD_RTCCLR ( BIT(1) )
+#define BIT_ANA_CHGR_PD_RTCSET ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_CHGR_CTRL1 */
+#define BIT_ANA_DP_DM_SW_EN ( BIT(15) )
+#define BITS_ANA_CHGR_CC_I(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_ANA_VBAT_OVP_V(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_ANA_VCHG_OVP_V(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+
+/* bits definitions for register REG_ANA_APB_IF_CHGR_CTRL2 */
+#define BITS_ANA_CHG_PUMP_CAL(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
+#define BIT_ANA_CHG_PUMP_PD ( BIT(8) )
+#define BIT_ANA_CHGR_CC_EN ( BIT(1) )
+#define BIT_ANA_RECHG ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_CHGR_STATUS */
+#define BIT_ANA_CHG_DET_DONE ( BIT(11) )
+#define BIT_ANA_DP_LOW ( BIT(10) )
+#define BIT_ANA_DCP_DET ( BIT(9) )
+#define BIT_ANA_CHG_DET ( BIT(8) )
+#define BIT_ANA_SDP_INT ( BIT(7) )
+#define BIT_ANA_DCP_INT ( BIT(6) )
+#define BIT_ANA_CDP_INT ( BIT(5) )
+#define BIT_ANA_CHGR_CV_STATUS ( BIT(4) )
+#define BIT_ANA_CHGR_ON ( BIT(3) )
+#define BIT_ANA_CHGR_INT ( BIT(2) )
+#define BIT_ANA_VBAT_OVI ( BIT(1) )
+#define BIT_ANA_VCHG_OVI ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_ANA_MIXED_CTRL */
+#define BIT_ANA_PTEST_PD_RTCSET ( BIT(15) )
+#define BIT_ANA_THM_CHIP_PD_FLAG ( BIT(8) )
+#define BIT_ANA_THM_CHIP_PD_FLAG_CLR ( BIT(7) )
+#define BITS_ANA_THM_CAL_SEL(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)) )
+#define BIT_ANA_THM_AUTO_PD_EN ( BIT(4) )
+#define BIT_ANA_BG_LP_EN ( BIT(3) )
+#define BITS_ANA_UVHO_T(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)) )
+#define BIT_ANA_UVHO_EN ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_PWR_XTL_EN0 */
+#define BIT_ANA_LDO_XTL_EN ( BIT(15) )
+#define BIT_ANA_LDO_RF1_EXT_XTL2_EN ( BIT(11) )
+#define BIT_ANA_LDO_RF1_EXT_XTL1_EN ( BIT(10) )
+#define BIT_ANA_LDO_RF1_EXT_XTL0_EN ( BIT(9) )
+#define BIT_ANA_LDO_RF1_XTL2_EN ( BIT(8) )
+#define BIT_ANA_LDO_RF1_XTL1_EN ( BIT(7) )
+#define BIT_ANA_LDO_RF1_XTL0_EN ( BIT(6) )
+#define BIT_ANA_LDO_RF0_EXT_XTL2_EN ( BIT(5) )
+#define BIT_ANA_LDO_RF0_EXT_XTL1_EN ( BIT(4) )
+#define BIT_ANA_LDO_RF0_EXT_XTL0_EN ( BIT(3) )
+#define BIT_ANA_LDO_RF0_XTL2_EN ( BIT(2) )
+#define BIT_ANA_LDO_RF0_XTL1_EN ( BIT(1) )
+#define BIT_ANA_LDO_RF0_XTL0_EN ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_PWR_XTL_EN1 */
+#define BIT_ANA_LDO_VDD25_EXT_XTL2_EN ( BIT(11) )
+#define BIT_ANA_LDO_VDD25_EXT_XTL1_EN ( BIT(10) )
+#define BIT_ANA_LDO_VDD25_EXT_XTL0_EN ( BIT(9) )
+#define BIT_ANA_LDO_VDD25_XTL2_EN ( BIT(8) )
+#define BIT_ANA_LDO_VDD25_XTL1_EN ( BIT(7) )
+#define BIT_ANA_LDO_VDD25_XTL0_EN ( BIT(6) )
+#define BIT_ANA_LDO_RF2_EXT_XTL2_EN ( BIT(5) )
+#define BIT_ANA_LDO_RF2_EXT_XTL1_EN ( BIT(4) )
+#define BIT_ANA_LDO_RF2_EXT_XTL0_EN ( BIT(3) )
+#define BIT_ANA_LDO_RF2_XTL2_EN ( BIT(2) )
+#define BIT_ANA_LDO_RF2_XTL1_EN ( BIT(1) )
+#define BIT_ANA_LDO_RF2_XTL0_EN ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_PWR_XTL_EN2 */
+#define BIT_ANA_LDO_AVDD18_EXT_XTL2_EN ( BIT(11) )
+#define BIT_ANA_LDO_AVDD18_EXT_XTL1_EN ( BIT(10) )
+#define BIT_ANA_LDO_AVDD18_EXT_XTL0_EN ( BIT(9) )
+#define BIT_ANA_LDO_AVDD18_XTL2_EN ( BIT(8) )
+#define BIT_ANA_LDO_AVDD18_XTL1_EN ( BIT(7) )
+#define BIT_ANA_LDO_AVDD18_XTL0_EN ( BIT(6) )
+#define BIT_ANA_LDO_SIM2_EXT_XTL2_EN ( BIT(5) )
+#define BIT_ANA_LDO_SIM2_EXT_XTL1_EN ( BIT(4) )
+#define BIT_ANA_LDO_SIM2_EXT_XTL0_EN ( BIT(3) )
+#define BIT_ANA_LDO_SIM2_XTL2_EN ( BIT(2) )
+#define BIT_ANA_LDO_SIM2_XTL1_EN ( BIT(1) )
+#define BIT_ANA_LDO_SIM2_XTL0_EN ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_PWR_XTL_EN3 */
+#define BIT_ANA_DCDC_BG_EXT_XTL2_EN ( BIT(11) )
+#define BIT_ANA_DCDC_BG_EXT_XTL1_EN ( BIT(10) )
+#define BIT_ANA_DCDC_BG_EXT_XTL0_EN ( BIT(9) )
+#define BIT_ANA_DCDC_BG_XTL2_EN ( BIT(8) )
+#define BIT_ANA_DCDC_BG_XTL1_EN ( BIT(7) )
+#define BIT_ANA_DCDC_BG_XTL0_EN ( BIT(6) )
+#define BIT_ANA_BG_EXT_XTL2_EN ( BIT(5) )
+#define BIT_ANA_BG_EXT_XTL1_EN ( BIT(4) )
+#define BIT_ANA_BG_EXT_XTL0_EN ( BIT(3) )
+#define BIT_ANA_BG_XTL2_EN ( BIT(2) )
+#define BIT_ANA_BG_XTL1_EN ( BIT(1) )
+#define BIT_ANA_BG_XTL0_EN ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_PWR_XTL_EN4 */
+#define BIT_ANA_DCDC_WRF_XTL2_EN ( BIT(14) )
+#define BIT_ANA_DCDC_WRF_XTL1_EN ( BIT(13) )
+#define BIT_ANA_DCDC_WRF_XTL0_EN ( BIT(12) )
+#define BIT_ANA_DCDC_WPA_XTL2_EN ( BIT(11) )
+#define BIT_ANA_DCDC_WPA_XTL1_EN ( BIT(10) )
+#define BIT_ANA_DCDC_WPA_XTL0_EN ( BIT(9) )
+#define BIT_ANA_DCDC_MEM_XTL2_EN ( BIT(8) )
+#define BIT_ANA_DCDC_MEM_XTL1_EN ( BIT(7) )
+#define BIT_ANA_DCDC_MEM_XTL0_EN ( BIT(6) )
+#define BIT_ANA_DCDC_GEN_XTL2_EN ( BIT(5) )
+#define BIT_ANA_DCDC_GEN_XTL1_EN ( BIT(4) )
+#define BIT_ANA_DCDC_GEN_XTL0_EN ( BIT(3) )
+#define BIT_ANA_DCDC_CORE_XTL2_EN ( BIT(2) )
+#define BIT_ANA_DCDC_CORE_XTL1_EN ( BIT(1) )
+#define BIT_ANA_DCDC_CORE_XTL0_EN ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_PWR_XTL_EN5 */
+#define BIT_ANA_DCDC_WRF_EXT_XTL2_EN ( BIT(14) )
+#define BIT_ANA_DCDC_WRF_EXT_XTL1_EN ( BIT(13) )
+#define BIT_ANA_DCDC_WRF_EXT_XTL0_EN ( BIT(12) )
+#define BIT_ANA_DCDC_WPA_EXT_XTL2_EN ( BIT(11) )
+#define BIT_ANA_DCDC_WPA_EXT_XTL1_EN ( BIT(10) )
+#define BIT_ANA_DCDC_WPA_EXT_XTL0_EN ( BIT(9) )
+#define BIT_ANA_DCDC_MEM_EXT_XTL2_EN ( BIT(8) )
+#define BIT_ANA_DCDC_MEM_EXT_XTL1_EN ( BIT(7) )
+#define BIT_ANA_DCDC_MEM_EXT_XTL0_EN ( BIT(6) )
+#define BIT_ANA_DCDC_GEN_EXT_XTL2_EN ( BIT(5) )
+#define BIT_ANA_DCDC_GEN_EXT_XTL1_EN ( BIT(4) )
+#define BIT_ANA_DCDC_GEN_EXT_XTL0_EN ( BIT(3) )
+#define BIT_ANA_DCDC_CORE_EXT_XTL2_EN ( BIT(2) )
+#define BIT_ANA_DCDC_CORE_EXT_XTL1_EN ( BIT(1) )
+#define BIT_ANA_DCDC_CORE_EXT_XTL0_EN ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_ANA_STATUS */
+#define BIT_ANA_BONDOPT6 ( BIT(6) )
+#define BIT_ANA_BONDOPT5 ( BIT(5) )
+#define BIT_ANA_BONDOPT4 ( BIT(4) )
+#define BIT_ANA_BONDOPT3 ( BIT(3) )
+#define BIT_ANA_BONDOPT2 ( BIT(2) )
+#define BIT_ANA_BONDOPT1 ( BIT(1) )
+#define BIT_ANA_BONDOPT0 ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_POR_RST_MONITOR */
+#define BITS_ANA_POR_RST_MONITOR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ANA_APB_IF_WDG_RST_MONITOR */
+#define BITS_ANA_WDG_RST_MONITOR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ANA_APB_IF_POR_PIN_RST_MONITOR */
+#define BITS_ANA_POR_PIN_RST_MONITOR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ANA_APB_IF_POR_SRC_FLAG */
+#define BIT_ANA_POR_SW_FORCE_ON ( BIT(15) )
+#define BITS_ANA_POR_SRC_FLAG(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+
+/* bits definitions for register REG_ANA_APB_IF_POR_7S_CTRL */
+#define BIT_ANA_PBINT_7S_FLAG_CLR ( BIT(15) )
+#define BIT_ANA_EXT_RSTN_FLAG_CLR ( BIT(14) )
+#define BIT_ANA_CHGR_INT_FLAG_CLR ( BIT(13) )
+#define BIT_ANA_PBINT2_FLAG_CLR ( BIT(12) )
+#define BIT_ANA_PBINT_FLAG_CLR ( BIT(11) )
+#define BIT_ANA_PBINT_7S_RST_SWMODE_RTCSTS ( BIT(10) )
+#define BIT_ANA_PBINT_7S_RST_SWMODE_RTCCLR ( BIT(9) )
+#define BIT_ANA_PBINT_7S_RST_SWMODE_RTCSET ( BIT(8) )
+#define BITS_ANA_PBINT_7S_RST_THRESHOLD(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_ANA_PBINT_7S_RST_DISABLE ( BIT(3) )
+#define BIT_ANA_PBINT_7S_RST_MODE_RTCSTS ( BIT(2) )
+#define BIT_ANA_PBINT_7S_RST_MODE_RTCCLR ( BIT(1) )
+#define BIT_ANA_PBINT_7S_RST_MODE_RTCSET ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_INT_DEBUG */
+#define BIT_ANA_OTP_INT_DEB ( BIT(10) )
+#define BIT_ANA_THM_INT_DEB ( BIT(9) )
+#define BIT_ANA_AUD_PROT_INT_DEB ( BIT(8) )
+#define BIT_ANA_AUD_HEADBTN_INT_DEB ( BIT(7) )
+#define BIT_ANA_EIC_INT_DEB ( BIT(6) )
+#define BIT_ANA_FGU_INT_DEB ( BIT(5) )
+#define BIT_ANA_WDG_INT_DEB ( BIT(4) )
+#define BIT_ANA_RTC_INT_DEB ( BIT(3) )
+#define BIT_ANA_GPIO_INT_DEB ( BIT(2) )
+#define BIT_ANA_ADC_INT_DEB ( BIT(1) )
+#define BIT_ANA_INT_DEBUG_EN ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_GPI_DEBUG */
+#define BIT_ANA_HEAD_INSERT2_DEB ( BIT(9) )
+#define BIT_ANA_HEAD_INSERT_DEB ( BIT(8) )
+#define BIT_ANA_HEAD_BUTTON_DEB ( BIT(7) )
+#define BIT_ANA_PBINT2_DEB ( BIT(6) )
+#define BIT_ANA_PBINT_DEB ( BIT(5) )
+#define BIT_ANA_VCHG_OVI_DEB ( BIT(4) )
+#define BIT_ANA_VBAT_OVI_DEB ( BIT(3) )
+#define BIT_ANA_CHGR_INT_DEB ( BIT(2) )
+#define BIT_ANA_GPI_DEBUG_EN ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_HWRST_RTC */
+#define BITS_ANA_HWRST_RTC_REG_STS(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_ANA_HWRST_RTC_REG_SET(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_ANA_APB_IF_CHIP_ID_LOW */
+#define BITS_ANA_CHIP_ID_LOW(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ANA_APB_IF_CHIP_ID_HIGH */
+#define BITS_ANA_CHIP_ID_HIGH(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ANA_APB_IF_ARM_MF_REG */
+#define BITS_ANA_ARM_MF_REG(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ANA_APB_IF_AFUSE_CTRL */
+#define BIT_ANA_AFUSE_READ_REQ ( BIT(7) )
+#define BITS_ANA_AFUSE_READ_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) )
+
+/* bits definitions for register REG_ANA_APB_IF_AFUSE_OUT0 */
+#define BITS_ANA_AFUSE_OUT0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ANA_APB_IF_AFUSE_OUT1 */
+#define BITS_ANA_AFUSE_OUT1(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ANA_APB_IF_AFUSE_OUT2 */
+#define BITS_ANA_AFUSE_OUT2(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ANA_APB_IF_AFUSE_OUT3 */
+#define BITS_ANA_AFUSE_OUT3(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ANA_APB_IF_CA_CTRL4 */
+#define BIT_ANA_EXT_RSTN_PD_EN ( BIT(14) )
+#define BIT_ANA_PB_7S_RST_PD_EN ( BIT(13) )
+#define BIT_ANA_WDG_RST_PD_EN ( BIT(12) )
+#define BIT_ANA_SW_RST_EMMCIO_PD_EN ( BIT(11) )
+#define BIT_ANA_SW_RST_EMMCCORE_PD_EN ( BIT(10) )
+#define BITS_ANA_SW_RST_PD_THRESHOLD(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+
+/* bits definitions for register REG_ANA_APB_IF_MCU_WR_PROT_VALUE */
+#define BIT_ANA_MCU_WR_PROT ( BIT(15) )
+#define BITS_ANA_MCU_WR_PROT_VALUE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+
+/* bits definitions for register REG_ANA_APB_IF_MP_PWR_CTRL0 */
+#define BIT_ANA_LDO_SIM1_EXT_XTL2_EN ( BIT(15) )
+#define BIT_ANA_LDO_SIM1_EXT_XTL1_EN ( BIT(14) )
+#define BIT_ANA_LDO_SIM1_EXT_XTL0_EN ( BIT(13) )
+#define BIT_ANA_LDO_SIM1_XTL2_EN ( BIT(12) )
+#define BIT_ANA_LDO_SIM1_XTL1_EN ( BIT(11) )
+#define BIT_ANA_LDO_SIM1_XTL0_EN ( BIT(10) )
+#define BIT_ANA_LDO_SIM0_EXT_XTL2_EN ( BIT(9) )
+#define BIT_ANA_LDO_SIM0_EXT_XTL1_EN ( BIT(8) )
+#define BIT_ANA_LDO_SIM0_EXT_XTL0_EN ( BIT(7) )
+#define BIT_ANA_LDO_SIM0_XTL2_EN ( BIT(6) )
+#define BIT_ANA_LDO_SIM0_XTL1_EN ( BIT(5) )
+#define BIT_ANA_LDO_SIM0_XTL0_EN ( BIT(4) )
+#define BIT_ANA_PWR_OFF_SEQ_EN ( BIT(3) )
+#define BIT_ANA_DCDC_CORE_SLP_OUT_STEP_EN ( BIT(1) )
+#define BIT_ANA_DCDC_CORE_SLP_IN_STEP_EN ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_MP_PWR_CTRL1 */
+#define BITS_ANA_DCDC_CORE_CTL_SLP_STEP5(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_ANA_DCDC_CORE_CTL_SLP_STEP4(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_ANA_DCDC_CORE_CTL_SLP_STEP3(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) )
+#define BITS_ANA_DCDC_CORE_CTL_SLP_STEP2(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) )
+#define BITS_ANA_DCDC_CORE_CTL_SLP_STEP1(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
+
+/* bits definitions for register REG_ANA_APB_IF_MP_PWR_CTRL2 */
+#define BITS_ANA_DCDC_CORE_CAL_SLP_STEP3(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_ANA_DCDC_CORE_CAL_SLP_STEP2(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_ANA_DCDC_CORE_CAL_SLP_STEP1(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_MP_PWR_CTRL3 */
+#define BITS_ANA_DCDC_ARM_STBOP(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) )
+#define BITS_ANA_DCDC_CORE_STBOP(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
+#define BITS_ANA_DCDC_CORE_CAL_SLP_STEP5(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_ANA_DCDC_CORE_CAL_SLP_STEP4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_MP_LDO_CTRL */
+#define BITS_ANA_LDOD_LP_CAL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_ANA_LDOA_LP_CAL(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_ANA_LDODCDC_LP_CAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_MP_CHG_CTRL */
+#define BIT_ANA_CHGR_INT_EN ( BIT(8) )
+#define BIT_ANA_CHGR_DRV ( BIT(5) )
+#define BIT_ANA_CHGR_OSC ( BIT(4) )
+#define BITS_ANA_CHGR_DPM(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_ANA_CHGR_ITERM(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_ANA_APB_IF_MP_MISC_CTRL */
+#define BITS_ANA_LDO_RF1_V_BOND(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)) )
+#define BITS_ANA_LDO_VDD25_V_BOND(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)) )
+#define BITS_ANA_DCDC_ARM_CTL_BOND(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) )
+#define BITS_ANA_DCDC_CORE_CTL_BOND(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) )
+#define BIT_ANA_DCOFFSET_EN ( BIT(2) )
+#define BIT_ANA_CHOP_EN ( BIT(1) )
+#define BIT_ANA_WHTLED_EXT_RES_CTRL ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_MP_DCDC_DEDT_CTRL */
+#define BITS_ANA_DCDC_WPA_DEDT_EN(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
+#define BITS_ANA_DCDC_WRF_DEDT_EN(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ANA_DCDC_GEN_DEDT_EN(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) )
+#define BITS_ANA_DCDC_MEM_DEDT_EN(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_ANA_DCDC_ARM_DEDT_EN(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_ANA_DCDC_CORE_DEDT_EN(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_ANA_APB_IF_CA_CTRL0 */
+#define BITS_ANA_SD_CLK_P(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) )
+#define BIT_ANA_SD_CHOP_CAP_EN ( BIT(13) )
+#define BIT_ANA_LDO_CAMIO_V_B2 ( BIT(12) )
+#define BIT_ANA_LDO_CAMIO_EXT_XTL2_EN ( BIT(11) )
+#define BIT_ANA_LDO_CAMIO_EXT_XTL1_EN ( BIT(10) )
+#define BIT_ANA_LDO_CAMIO_EXT_XTL0_EN ( BIT(9) )
+#define BIT_ANA_LDO_CAMIO_XTL2_EN ( BIT(8) )
+#define BIT_ANA_LDO_CAMIO_XTL1_EN ( BIT(7) )
+#define BIT_ANA_LDO_CAMIO_XTL0_EN ( BIT(6) )
+#define BIT_ANA_LDO_CAMD_EXT_XTL2_EN ( BIT(5) )
+#define BIT_ANA_LDO_CAMD_EXT_XTL1_EN ( BIT(4) )
+#define BIT_ANA_LDO_CAMD_EXT_XTL0_EN ( BIT(3) )
+#define BIT_ANA_LDO_CAMD_XTL2_EN ( BIT(2) )
+#define BIT_ANA_LDO_CAMD_XTL1_EN ( BIT(1) )
+#define BIT_ANA_LDO_CAMD_XTL0_EN ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_CA_CTRL1 */
+#define BITS_ANA_SMPL_MODE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ANA_APB_IF_CA_CTRL2 */
+#define BIT_ANA_SMPL_PWR_ON_FLAG ( BIT(15) )
+#define BIT_ANA_SMPL_MODE_WR_ACK_FLAG ( BIT(14) )
+#define BIT_ANA_SMPL_PWR_ON_FLAG_CLR ( BIT(13) )
+#define BIT_ANA_SMPL_MODE_WR_ACK_FLAG_CLR ( BIT(12) )
+#define BIT_ANA_SMPL_PWR_ON_SET ( BIT(11) )
+#define BIT_ANA_SLP_LDOKPLED_PD_EN ( BIT(9) )
+#define BIT_ANA_LDO_KPLED_PD ( BIT(8) )
+#define BITS_ANA_LDO_KPLED_V(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_ANA_APB_IF_CA_CTRL3 */
+#define BITS_ANA_VBAT_CRASH_V(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) )
+#define BIT_ANA_PBINT_7S_AUTO_ON_EN_CLR ( BIT(13) )
+#define BIT_ANA_PBINT_7S_AUTO_ON_EN_SET ( BIT(12) )
+#define BIT_ANA_VIBR_LDO_EN ( BIT(10) )
+#define BIT_ANA_SLP_LDOVIBR_PD_EN ( BIT(9) )
+#define BIT_ANA_LDO_VIBR_PD ( BIT(8) )
+#define BITS_ANA_LDO_VIBR_V(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_CORE_ADI */
+#define BITS_ANA_DCDC_CORE_CTL_SW_ADI(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_ANA_DCDC_CORE_CAL_SW_ADI(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_ARM_ADI */
+#define BITS_ANA_DCDC_ARM_CTL_ADI(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_ANA_DCDC_ARM_CAL_ADI(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_MEM_ADI */
+#define BIT_ANA_DCDC_MEM_CTL_ADI ( BIT(5) )
+#define BITS_ANA_DCDC_MEM_CAL_ADI(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_GEN_ADI */
+#define BITS_ANA_DCDC_GEN_CTL_ADI(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_ANA_DCDC_GEN_CAL_ADI(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_WRF_ADI */
+#define BITS_ANA_DCDC_WRF_CTL_ADI(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)) )
+#define BITS_ANA_DCDC_WRF_CAL_ADI(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_WPA_ADI */
+#define BITS_ANA_DCDC_WPA_CAL_ADI(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_WPA_DCM_ADI */
+#define BIT_ANA_DCDC_WPA_DCM_ADI ( BIT(0) )
+
+#endif
diff --git a/include/soc/sprd/chip_x30g/__regs_ana_sc2713s_glb.h b/include/soc/sprd/chip_x30g/__regs_ana_sc2713s_glb.h new file mode 100644 index 00000000..844a48da --- /dev/null +++ b/include/soc/sprd/chip_x30g/__regs_ana_sc2713s_glb.h @@ -0,0 +1,931 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __REGS_ANA_SC2713S_GLB_H__ +#define __REGS_ANA_SC2713S_GLB_H__ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, include <mach/sci_glb_regs.h>" +#endif + +#define ANA_REGS_GLB + +/* registers definitions for controller ANA_REGS_GLB */ +#define ANA_REG_GLB_ARM_MODULE_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0000) +#define ANA_REG_GLB_ARM_CLK_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0004) +#define ANA_REG_GLB_RTC_CLK_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0008) +#define ANA_REG_GLB_ARM_RST SCI_ADDR(ANA_REGS_GLB_BASE, 0x000C) +#define ANA_REG_GLB_LDO_DCDC_PD_RTCSET SCI_ADDR(ANA_REGS_GLB_BASE, 0x0010) +#define ANA_REG_GLB_LDO_DCDC_PD_RTCCLR SCI_ADDR(ANA_REGS_GLB_BASE, 0x0014) +#define ANA_REG_GLB_RTC_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0018) +#define ANA_REG_GLB_LDO_PD_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x001C) +#define ANA_REG_GLB_LDO_V_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0020) +#define ANA_REG_GLB_LDO_V_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0024) +#define ANA_REG_GLB_LDO_V_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0028) +#define ANA_REG_GLB_LDO_CAL_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x002C) +#define ANA_REG_GLB_LDO_CAL_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0030) +#define ANA_REG_GLB_LDO_CAL_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0034) +#define ANA_REG_GLB_LDO_CAL_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0038) +#define ANA_REG_GLB_LDO_CAL_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x003C) +#define ANA_REG_GLB_LDO_CAL_CTRL5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0040) +#define ANA_REG_GLB_LDO_CAL_CTRL6 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0044) +#define ANA_REG_GLB_AUXAD_CTL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0048) +#define ANA_REG_GLB_DCDC_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x004C) +#define ANA_REG_GLB_DCDC_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0050) +#define ANA_REG_GLB_DCDC_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0054) +#define ANA_REG_GLB_DCDC_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0058) +#define ANA_REG_GLB_DCDC_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x005C) +#define ANA_REG_GLB_DCDC_CTRL5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0060) +#define ANA_REG_GLB_DCDC_CTRL6 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0064) +#define ANA_REG_GLB_DDR2_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0068) +#define ANA_REG_GLB_SLP_WAIT_DCDCARM SCI_ADDR(ANA_REGS_GLB_BASE, 0x006C) +#define ANA_REG_GLB_LDO1828_XTL_CTL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0070) +#define ANA_REG_GLB_LDO_SLP_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0074) +#define ANA_REG_GLB_LDO_SLP_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0078) +#define ANA_REG_GLB_LDO_SLP_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x007C) +#define ANA_REG_GLB_LDO_SLP_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0080) +#define ANA_REG_GLB_AUD_SLP_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0084) +#define ANA_REG_GLB_DCDC_SLP_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0088) +#define ANA_REG_GLB_XTL_WAIT_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x008C) +#define ANA_REG_GLB_FLASH_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0090) +#define ANA_REG_GLB_WHTLED_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0094) +#define ANA_REG_GLB_WHTLED_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0098) +#define ANA_REG_GLB_WHTLED_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x009C) +#define ANA_REG_GLB_ANA_DRV_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A0) +#define ANA_REG_GLB_VIBR_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A4) +#define ANA_REG_GLB_VIBR_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A8) +#define ANA_REG_GLB_VIBR_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00AC) +#define ANA_REG_GLB_VIBR_WR_PROT_VALUE SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B0) +#define ANA_REG_GLB_AUDIO_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B4) +#define ANA_REG_GLB_CHGR_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B8) +#define ANA_REG_GLB_CHGR_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00BC) +#define ANA_REG_GLB_CHGR_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C0) +#define ANA_REG_GLB_CHGR_STATUS SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C4) +#define ANA_REG_GLB_ANA_MIXED_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C8) +#define ANA_REG_GLB_PWR_XTL_EN0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00CC) +#define ANA_REG_GLB_PWR_XTL_EN1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D0) +#define ANA_REG_GLB_PWR_XTL_EN2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D4) +#define ANA_REG_GLB_PWR_XTL_EN3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D8) +#define ANA_REG_GLB_PWR_XTL_EN4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00DC) +#define ANA_REG_GLB_PWR_XTL_EN5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E0) +#define ANA_REG_GLB_ANA_STATUS SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E4) +#define ANA_REG_GLB_POR_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E8) +#define ANA_REG_GLB_WDG_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x00EC) +#define ANA_REG_GLB_POR_PIN_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F0) +#define ANA_REG_GLB_POR_SRC_FLAG SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F4) +#define ANA_REG_GLB_POR_7S_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F8) +#define ANA_REG_GLB_INT_DEBUG SCI_ADDR(ANA_REGS_GLB_BASE, 0x00FC) +#define ANA_REG_GLB_GPI_DEBUG SCI_ADDR(ANA_REGS_GLB_BASE, 0x0100) +#define ANA_REG_GLB_HWRST_RTC SCI_ADDR(ANA_REGS_GLB_BASE, 0x0104) +#define ANA_REG_GLB_CHIP_ID_LOW SCI_ADDR(ANA_REGS_GLB_BASE, 0x0108) +#define ANA_REG_GLB_CHIP_ID_HIGH SCI_ADDR(ANA_REGS_GLB_BASE, 0x010C) +#define ANA_REG_GLB_ARM_MF_REG SCI_ADDR(ANA_REGS_GLB_BASE, 0x0110) +#define ANA_REG_GLB_AFUSE_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0114) +#define ANA_REG_GLB_AFUSE_OUT0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0118) +#define ANA_REG_GLB_AFUSE_OUT1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x011C) +#define ANA_REG_GLB_AFUSE_OUT2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0120) +#define ANA_REG_GLB_AFUSE_OUT3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0124) +#define ANA_REG_GLB_CA_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0128) +#define ANA_REG_GLB_MCU_WR_PROT_VALUE SCI_ADDR(ANA_REGS_GLB_BASE, 0x012C) +#define ANA_REG_GLB_MP_PWR_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0130) +#define ANA_REG_GLB_MP_PWR_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0134) +#define ANA_REG_GLB_MP_PWR_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0138) +#define ANA_REG_GLB_MP_PWR_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x013C) +#define ANA_REG_GLB_MP_LDO_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0140) +#define ANA_REG_GLB_MP_CHG_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0144) +#define ANA_REG_GLB_MP_MISC_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0148) +#define ANA_REG_GLB_MP_DCDC_DEDT_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x014C) +#define ANA_REG_GLB_CA_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0150) +#define ANA_REG_GLB_CA_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0154) +#define ANA_REG_GLB_CA_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0158) +#define ANA_REG_GLB_CA_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x015C) +#define ANA_REG_GLB_DCDC_CORE_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0160) +#define ANA_REG_GLB_DCDC_ARM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0164) +#define ANA_REG_GLB_DCDC_MEM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0168) +#define ANA_REG_GLB_DCDC_GEN_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x016C) +#define ANA_REG_GLB_DCDC_WRF_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0170) +#define ANA_REG_GLB_DCDC_WPA_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0174) +#define ANA_REG_GLB_DCDC_WPA_DCM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x017C) + +#define ANA_REG_GLB_LDO_CAL_SEL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0044) + +/* bits definitions for register ANA_REG_GLB_ARM_MODULE_EN */ +#define BIT_ANA_THM_EN ( BIT(12) ) +#define BIT_ANA_BLTC_EN ( BIT(10) ) +#define BIT_ANA_PINREG_EN ( BIT(9) ) +#define BIT_ANA_FGU_EN ( BIT(8) ) +#define BIT_ANA_GPIO_EN ( BIT(7) ) +#define BIT_ANA_ADC_EN ( BIT(6) ) +#define BIT_ANA_HDT_EN ( BIT(5) ) +#define BIT_ANA_AUD_EN ( BIT(4) ) +#define BIT_ANA_EIC_EN ( BIT(3) ) +#define BIT_ANA_WDG_EN ( BIT(2) ) +#define BIT_ANA_RTC_EN ( BIT(1) ) + +/* bits definitions for register ANA_REG_GLB_ARM_CLK_EN */ +#define BIT_CLK_AUXAD_EN ( BIT(9) ) +#define BIT_CLK_AUXADC_EN ( BIT(8) ) +#define BIT_CLK_AUD_HID_EN ( BIT(5) ) +#define BIT_CLK_AUD_HBD_EN ( BIT(4) ) +#define BIT_CLK_AUD_LOOP_EN ( BIT(3) ) +#define BIT_CLK_AUD_6P5M_EN ( BIT(2) ) +#define BIT_CLK_AUDIF_EN ( BIT(1) ) + +/* bits definitions for register ANA_REG_GLB_RTC_CLK_EN */ +#define BIT_RTC_FLASH_EN ( BIT(13) ) +#define BIT_RTC_THMA_AUTO_EN ( BIT(12) ) +#define BIT_RTC_THMA_EN ( BIT(11) ) +#define BIT_RTC_THM_EN ( BIT(10) ) +#define BIT_RTC_BLTC_EN ( BIT(8) ) +#define BIT_RTC_FGU_EN ( BIT(7) ) +#define BIT_RTC_FGUA_EN ( BIT(6) ) +#define BIT_RTC_VIBR_EN ( BIT(5) ) +#define BIT_RTC_AUD_EN ( BIT(4) ) +#define BIT_RTC_EIC_EN ( BIT(3) ) +#define BIT_RTC_WDG_EN ( BIT(2) ) +#define BIT_RTC_RTC_EN ( BIT(1) ) +#define BIT_RTC_ARCH_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_ARM_RST */ +#define BIT_ANA_THMA_SOFT_RST ( BIT(14) ) +#define BIT_ANA_THM_SOFT_RST ( BIT(13) ) +#define BIT_ANA_AUD_32K_SOFT_RST ( BIT(12) ) +#define BIT_ANA_AUDTX_SOFT_RST ( BIT(11) ) +#define BIT_ANA_AUDRX_SOFT_RST ( BIT(10) ) +#define BIT_ANA_AUD_SOFT_RST ( BIT(9) ) +#define BIT_ANA_AUD_HDT_SOFT_RST ( BIT(8) ) +#define BIT_ANA_GPIO_SOFT_RST ( BIT(7) ) +#define BIT_ANA_ADC_SOFT_RST ( BIT(6) ) +#define BIT_ANA_PWM0_SOFT_RST ( BIT(5) ) +#define BIT_ANA_FGU_SOFT_RST ( BIT(4) ) +#define BIT_ANA_EIC_SOFT_RST ( BIT(3) ) +#define BIT_ANA_WDG_SOFT_RST ( BIT(2) ) +#define BIT_ANA_RTC_SOFT_RST ( BIT(1) ) +#define BIT_ANA_BLTC_SOFT_RST ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_DCDC_PD_RTCSET */ +#define BIT_LDO_AVDD18_PD_RTCSET ( BIT(15) ) +#define BIT_DCDC_OTP_PD_RTCSET ( BIT(14) ) +#define BIT_DCDC_WRF_PD_RTCSET ( BIT(13) ) +#define BIT_DCDC_GEN_PD_RTCSET ( BIT(12) ) +#define BIT_DCDC_MEM_PD_RTCSET ( BIT(11) ) +#define BIT_DCDC_ARM_PD_RTCSET ( BIT(10) ) +#define BIT_DCDC_CORE_PD_RTCSET ( BIT(9) ) +#define BIT_LDO_EMMCCORE_PD_RTCSET ( BIT(8) ) +#define BIT_LDO_EMMCIO_PD_RTCSET ( BIT(7) ) +#define BIT_LDO_RF2_PD_RTCSET ( BIT(6) ) +#define BIT_LDO_RF1_PD_RTCSET ( BIT(5) ) +#define BIT_LDO_RF0_PD_RTCSET ( BIT(4) ) +#define BIT_LDO_VDD25_PD_RTCSET ( BIT(3) ) +#define BIT_LDO_VDD28_PD_RTCSET ( BIT(2) ) +#define BIT_LDO_VDD18_PD_RTCSET ( BIT(1) ) +#define BIT_BG_PD_RTCSET ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_DCDC_PD_RTCCLR */ +#define BIT_LDO_AVDD18_PD_RTCCLR ( BIT(15) ) +#define BIT_DCDC_OTP_PD_RTCCLR ( BIT(14) ) +#define BIT_DCDC_WRF_PD_RTCCLR ( BIT(13) ) +#define BIT_DCDC_GEN_PD_RTCCLR ( BIT(12) ) +#define BIT_DCDC_MEM_PD_RTCCLR ( BIT(11) ) +#define BIT_DCDC_ARM_PD_RTCCLR ( BIT(10) ) +#define BIT_DCDC_CORE_PD_RTCCLR ( BIT(9) ) +#define BIT_LDO_EMMCCORE_PD_RTCCLR ( BIT(8) ) +#define BIT_LDO_EMMCIO_PD_RTCCLR ( BIT(7) ) +#define BIT_LDO_RF2_PD_RTCCLR ( BIT(6) ) +#define BIT_LDO_RF1_PD_RTCCLR ( BIT(5) ) +#define BIT_LDO_RF0_PD_RTCCLR ( BIT(4) ) +#define BIT_LDO_VDD25_PD_RTCCLR ( BIT(3) ) +#define BIT_LDO_VDD28_PD_RTCCLR ( BIT(2) ) +#define BIT_LDO_VDD18_PD_RTCCLR ( BIT(1) ) +#define BIT_BG_PD_RTCCLR ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_RTC_CTRL */ +#define BITS_XOSC32K_CTL_STS(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BIT_XOSC32K_CTL_B3_RTCCLR ( BIT(7) ) +#define BIT_XOSC32K_CTL_B2_RTCCLR ( BIT(6) ) +#define BIT_XOSC32K_CTL_B1_RTCCLR ( BIT(5) ) +#define BIT_XOSC32K_CTL_B0_RTCCLR ( BIT(4) ) +#define BIT_XOSC32K_CTL_B3_RTCSET ( BIT(3) ) +#define BIT_XOSC32K_CTL_B2_RTCSET ( BIT(2) ) +#define BIT_XOSC32K_CTL_B1_RTCSET ( BIT(1) ) +#define BIT_XOSC32K_CTL_B0_RTCSET ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_PD_CTRL */ +#define BIT_LDO_LPREF_PD_SW ( BIT(12) ) +#define BIT_DCDC_WPA_PD ( BIT(11) ) +#define BIT_LDO_CLSG_PD ( BIT(10) ) +#define BIT_LDO_USB_PD ( BIT(9) ) +#define BIT_LDO_CAMMOT_PD ( BIT(8) ) +#define BIT_LDO_CAMIO_PD ( BIT(7) ) +#define BIT_LDO_CAMD_PD ( BIT(6) ) +#define BIT_LDO_CAMA_PD ( BIT(5) ) +#define BIT_LDO_SIM2_PD ( BIT(4) ) +#define BIT_LDO_SIM1_PD ( BIT(3) ) +#define BIT_LDO_SIM0_PD ( BIT(2) ) +#define BIT_LDO_SD_PD ( BIT(1) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL0 */ +#define BITS_LDO_EMMCCORE_V(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_LDO_EMMCIO_V(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_LDO_RF2_V(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_LDO_RF1_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_LDO_RF0_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_LDO_VDD25_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_LDO_VDD28_V(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_LDO_VDD18_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL1 */ +#define BITS_LDO_SIM2_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_LDO_SIM1_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_LDO_SIM0_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_LDO_SD_V(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_LDO_AVDD18_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL2 */ +#define BITS_VBATBK_RES(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_VBATBK_V(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_LDO_CLSG_V(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_LDO_USB_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_LDO_CAMMOT_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_LDO_CAMIO_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_LDO_CAMD_V(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_LDO_CAMA_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL0 */ +#define BITS_LDO_VDD25_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_VDD28_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_VDD18_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL1 */ +#define BITS_LDO_RF2_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_RF1_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_RF0_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL2 */ +#define BITS_LDO_USB_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_EMMCCORE_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_EMMCIO_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL3 */ +#define BITS_LDO_SD_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_AVDD18_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL4 */ +#define BITS_LDO_CAMA_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_SIM2_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_SIM_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL5 */ +#define BITS_LDO_CAMMOT_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_CAMIO_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_CAMD_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL6 */ +#define BITS_LDOA_CAL_SEL(_x_) ( (_x_) << 11 & (BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_LDOD_CAL_SEL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_LDODCDC_CAL_SEL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_LDO_CLSG_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_AUXAD_CTL */ +#define BIT_AUXAD_CURRENTSEN_EN ( BIT(6) ) +#define BIT_AUXAD_CURRENTSEL ( BIT(5) ) +#define BITS_AUXAD_CURRENT_IBS(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL0 */ +#define BIT_DCDC_CORE_LP_EN ( BIT(15) ) +#define BIT_DCDC_CORE_CL_CTRL ( BIT(14) ) +#define BITS_DCDC_CORE_PDRSLOW(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_DCDC_CORE_PFM ( BIT(9) ) +#define BIT_DCDC_CORE_DCM ( BIT(8) ) +#define BIT_DCDC_ARM_LP_EN ( BIT(7) ) +#define BIT_DCDC_ARM_CL_CTRL ( BIT(6) ) +#define BITS_DCDC_ARM_PDRSLOW(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) +#define BIT_DCDC_ARM_PFM ( BIT(1) ) +#define BIT_DCDC_ARM_DCM ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL1 */ +#define BIT_DCDC_MEM_LP_EN ( BIT(15) ) +#define BIT_DCDC_MEM_CL_CTRL ( BIT(14) ) +#define BITS_DCDC_MEM_PDRSLOW(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_DCDC_MEM_PFM ( BIT(9) ) +#define BIT_DCDC_MEM_DCM ( BIT(8) ) +#define BIT_DCDC_GEN_LP_EN ( BIT(7) ) +#define BIT_DCDC_GEN_CL_CTRL ( BIT(6) ) +#define BITS_DCDC_GEN_PDRSLOW(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) +#define BIT_DCDC_GEN_PFM ( BIT(1) ) +#define BIT_DCDC_GEN_DCM ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL2 */ +#define BIT_DCDC_BG_LP_EN ( BIT(15) ) +#define BIT_DCDC_OTP_CHIP_PD_FLAG_CLR ( BIT(14) ) +#define BIT_DCDC_OTP_CHIP_PD_FLAG ( BIT(13) ) +#define BIT_DCDC_OTP_AUTO_PD_EN ( BIT(12) ) +#define BIT_DCDC_OTP_VBEOP ( BIT(11) ) +#define BITS_DCDC_OTP_S(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BIT_DCDC_WRF_LP_EN ( BIT(7) ) +#define BIT_DCDC_WRF_CL_CTRL ( BIT(6) ) +#define BITS_DCDC_WRF_PDRSLOW(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) +#define BIT_DCDC_WRF_PFM ( BIT(1) ) +#define BIT_DCDC_WRF_DCM ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL3 */ +#define BIT_DCDC_WPA_LP_EN ( BIT(8) ) +#define BIT_DCDC_WPA_CL_CTRL ( BIT(7) ) +#define BIT_DCDC_WPA_ZXOP ( BIT(6) ) +#define BITS_DCDC_WPA_PDRSLOW(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) +#define BIT_DCDC_WPA_PFM ( BIT(1) ) +#define BIT_DCDC_WPA_APTEN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL4 */ +#define BIT_DCDC_CORE_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_CORE_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_CORE_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_CORE_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_ARM_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_ARM_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_ARM_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_ARM_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL5 */ +#define BIT_DCDC_MEM_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_MEM_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_MEM_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_MEM_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_GEN_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_GEN_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_GEN_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_GEN_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL6 */ +#define BIT_DCDC_WPA_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_WPA_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_WPA_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_WPA_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_WRF_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_WRF_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_WRF_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_WRF_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DDR2_CTRL */ +#define BIT_DDR2_BUF_PD_HW ( BIT(9) ) +#define BITS_DDR2_BUF_S_DS(_x_) ( (_x_) << 7 & (BIT(7)|BIT(8)) ) +#define BITS_DDR2_BUF_CHNS_DS(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)) ) +#define BIT_DDR2_BUF_PD ( BIT(4) ) +#define BITS_DDR2_BUF_S(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DDR2_BUF_CHNS(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_SLP_WAIT_DCDCARM */ +#define BITS_SLP_IN_WAIT_DCDCARM(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_SLP_OUT_WAIT_DCDCARM(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO1828_XTL_CTL */ +#define BIT_LDO_VDD18_EXT_XTL2_EN ( BIT(11) ) +#define BIT_LDO_VDD18_EXT_XTL1_EN ( BIT(10) ) +#define BIT_LDO_VDD18_EXT_XTL0_EN ( BIT(9) ) +#define BIT_LDO_VDD18_XTL2_EN ( BIT(8) ) +#define BIT_LDO_VDD18_XTL1_EN ( BIT(7) ) +#define BIT_LDO_VDD18_XTL0_EN ( BIT(6) ) +#define BIT_LDO_VDD28_EXT_XTL2_EN ( BIT(5) ) +#define BIT_LDO_VDD28_EXT_XTL1_EN ( BIT(4) ) +#define BIT_LDO_VDD28_EXT_XTL0_EN ( BIT(3) ) +#define BIT_LDO_VDD28_XTL2_EN ( BIT(2) ) +#define BIT_LDO_VDD28_XTL1_EN ( BIT(1) ) +#define BIT_LDO_VDD28_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SLP_CTRL0 */ +#define BIT_SLP_IO_EN ( BIT(15) ) +#define BIT_SLP_DCDC_OTP_PD_EN ( BIT(13) ) +#define BIT_SLP_DCDCGEN_PD_EN ( BIT(12) ) +#define BIT_SLP_DCDCWPA_PD_EN ( BIT(11) ) +#define BIT_SLP_DCDCWRF_PD_EN ( BIT(10) ) +#define BIT_SLP_DCDCARM_PD_EN ( BIT(9) ) +#define BIT_SLP_LDOEMMCCORE_PD_EN ( BIT(7) ) +#define BIT_SLP_LDOEMMCIO_PD_EN ( BIT(6) ) +#define BIT_SLP_LDORF2_PD_EN ( BIT(5) ) +#define BIT_SLP_LDORF1_PD_EN ( BIT(4) ) +#define BIT_SLP_LDORF0_PD_EN ( BIT(3) ) +#define BIT_SLP_LDOVDD25_PD_EN ( BIT(2) ) +#define BIT_SLP_LDOVDD28_PD_EN ( BIT(1) ) +#define BIT_SLP_LDOVDD18_PD_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SLP_CTRL1 */ +#define BIT_SLP_LDO_PD_EN ( BIT(12) ) +#define BIT_SLP_LDOLPREF_PD_EN ( BIT(11) ) +#define BIT_SLP_LDOCLSG_PD_EN ( BIT(10) ) +#define BIT_SLP_LDOUSB_PD_EN ( BIT(9) ) +#define BIT_SLP_LDOCAMMOT_PD_EN ( BIT(8) ) +#define BIT_SLP_LDOCAMIO_PD_EN ( BIT(7) ) +#define BIT_SLP_LDOCAMD_PD_EN ( BIT(6) ) +#define BIT_SLP_LDOCAMA_PD_EN ( BIT(5) ) +#define BIT_SLP_LDOSIM2_PD_EN ( BIT(4) ) +#define BIT_SLP_LDOSIM1_PD_EN ( BIT(3) ) +#define BIT_SLP_LDOSIM0_PD_EN ( BIT(2) ) +#define BIT_SLP_LDOSD_PD_EN ( BIT(1) ) +#define BIT_SLP_LDOAVDD18_PD_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SLP_CTRL2 */ +#define BIT_SLP_DCDC_BG_LP_EN ( BIT(15) ) +#define BIT_SLP_DCDCCORE_LP_EN ( BIT(11) ) +#define BIT_SLP_DCDCMEM_LP_EN ( BIT(10) ) +#define BIT_SLP_DCDCARM_LP_EN ( BIT(9) ) +#define BIT_SLP_DCDCGEN_LP_EN ( BIT(8) ) +#define BIT_SLP_DCDCWPA_LP_EN ( BIT(6) ) +#define BIT_SLP_DCDCWRF_LP_EN ( BIT(5) ) +#define BIT_SLP_LDOEMMCCORE_LP_EN ( BIT(4) ) +#define BIT_SLP_LDOEMMCIO_LP_EN ( BIT(3) ) +#define BIT_SLP_LDORF2_LP_EN ( BIT(2) ) +#define BIT_SLP_LDORF1_LP_EN ( BIT(1) ) +#define BIT_SLP_LDORF0_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SLP_CTRL3 */ +#define BIT_SLP_BG_LP_EN ( BIT(15) ) +#define BIT_SLP_LDOVDD25_LP_EN ( BIT(13) ) +#define BIT_SLP_LDOVDD28_LP_EN ( BIT(12) ) +#define BIT_SLP_LDOVDD18_LP_EN ( BIT(11) ) +#define BIT_SLP_LDOCLSG_LP_EN ( BIT(10) ) +#define BIT_SLP_LDOUSB_LP_EN ( BIT(9) ) +#define BIT_SLP_LDOCAMMOT_LP_EN ( BIT(8) ) +#define BIT_SLP_LDOCAMIO_LP_EN ( BIT(7) ) +#define BIT_SLP_LDOCAMD_LP_EN ( BIT(6) ) +#define BIT_SLP_LDOCAMA_LP_EN ( BIT(5) ) +#define BIT_SLP_LDOSIM2_LP_EN ( BIT(4) ) +#define BIT_SLP_LDOSIM1_LP_EN ( BIT(3) ) +#define BIT_SLP_LDOSIM0_LP_EN ( BIT(2) ) +#define BIT_SLP_LDOSD_LP_EN ( BIT(1) ) +#define BIT_SLP_LDOAVDD18_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_AUD_SLP_CTRL4 */ +#define BIT_SLP_AUD_PA_SW_PD_EN ( BIT(15) ) +#define BIT_SLP_AUD_PA_LDO_PD_EN ( BIT(14) ) +#define BIT_SLP_AUD_PA_PD_EN ( BIT(13) ) +#define BIT_SLP_AUD_OVP_PD_PD_EN ( BIT(9) ) +#define BIT_SLP_AUD_OVP_LDO_PD_EN ( BIT(8) ) +#define BIT_SLP_AUD_VB_PD_EN ( BIT(7) ) +#define BIT_SLP_AUD_VBO_PD_EN ( BIT(6) ) +#define BIT_SLP_AUD_HEADMICBIAS_PD_EN ( BIT(5) ) +#define BIT_SLP_AUD_MICBIAS_HV_PD_EN ( BIT(2) ) +#define BIT_SLP_AUD_HEADMIC_PD_EN ( BIT(1) ) +#define BIT_SLP_AUD_PMUR1_PD_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL */ +#define BITS_SLP_DCDCCORE_VOL_DROP_CNT(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DCDC_CORE_CTL_DS(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register ANA_REG_GLB_XTL_WAIT_CTRL */ +#define BIT_SLP_XTLBUF_PD_EN ( BIT(9) ) +#define BIT_XTL_EN ( BIT(8) ) +#define BITS_XTL_WAIT(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_FLASH_CTRL */ +#define BIT_FLASH_PON ( BIT(15) ) +#define BIT_FLASH_V_HW_EN ( BIT(6) ) +#define BITS_FLASH_V_HW_STEP(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_FLASH_V_SW(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register ANA_REG_GLB_WHTLED_CTRL0 */ +#define BIT_WHTLED_PD_STS ( BIT(15) ) +#define BITS_WHTLED_DC(_x_) ( (_x_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BIT_WHTLED_BOOST_EN ( BIT(8) ) +#define BIT_WHTLED_SERIES_EN ( BIT(7) ) +#define BITS_WHTLED_V(_x_) ( (_x_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_WHTLED_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_WHTLED_CTRL1 */ +#define BIT_LCM_CABC_PWM_SEL ( BIT(15) ) +#define BIT_RTC_PWM0_EN ( BIT(14) ) +#define BIT_PWM0_EN ( BIT(13) ) +#define BITS_WHTLED_ISET(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_WHTLED_FRE_AD(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)) ) +#define BITS_WHTLED_CLMIT_OP(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_WHTLED_CTRL2 */ +#define BIT_WHTLED_DIMMING_SEL ( BIT(15) ) +#define BIT_WHTLED_PD_SEL ( BIT(14) ) +#define BIT_WHTLED_DIS_OVST ( BIT(13) ) +#define BIT_WHTLED_DIM_SEL ( BIT(12) ) +#define BIT_WHTLED_DE_BIAS ( BIT(11) ) +#define BIT_WHTLED_BUFF_SHT ( BIT(10) ) +#define BITS_WHTLED_STB_OP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_WHTLED_CAP_OPTION ( BIT(7) ) +#define BIT_WHTLED_OVP_DIS ( BIT(6) ) +#define BITS_WHTLED_REF_DC(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register ANA_REG_GLB_ANA_DRV_CTRL */ +#define BIT_SLP_RGB_PD_EN ( BIT(14) ) +#define BIT_RGB_PD_HW_EN ( BIT(13) ) +#define BITS_RGB_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BITS_KPLED_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_RGB_PD_SW ( BIT(2) ) +#define BIT_KPLED_PD ( BIT(1) ) +#define BIT_KPLED_PD_STS ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_VIBR_CTRL0 */ +#define BITS_VIBR_STABLE_V_HW(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_VIBR_INIT_V_HW(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_VIBR_V_SW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_VIBR_PON ( BIT(2) ) +#define BIT_VIBR_SW_EN ( BIT(1) ) + +/* bits definitions for register ANA_REG_GLB_VIBR_CTRL1 */ +#define BITS_VIBR_V_CONVERT_CNT_HW(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_VIBR_CTRL2 */ +#define BIT_VIBR_PWR_ON_STS ( BIT(15) ) +#define BIT_VIBR_HW_FLOW_ERR1 ( BIT(14) ) +#define BIT_VIBR_HW_FLOW_ERR1_CLR ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_VIBR_WR_PROT_VALUE */ +#define BIT_VIBR_WR_PROT ( BIT(15) ) +#define BITS_VIBR_WR_PROT_VALUE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_AUDIO_CTRL */ +#define BIT_AUD_SLP_APP_RST_EN ( BIT(10) ) +#define BITS_CLK_AUD_HBD_DIV(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BIT_CLK_AUD_LOOP_INV_EN ( BIT(4) ) +#define BIT_CLK_AUDIF_TX_INV_EN ( BIT(3) ) +#define BIT_CLK_AUDIF_RX_INV_EN ( BIT(2) ) +#define BIT_CLK_AUD_6P5M_TX_INV_EN ( BIT(1) ) +#define BIT_CLK_AUD_6P5M_RX_INV_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL0 */ +#define BIT_CHGR_PD_STS ( BIT(15) ) +#define BITS_CHGR_CV_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CHGR_END_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CHG_PUMP_V(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BIT_CHGR_PD_RTCCLR ( BIT(1) ) +#define BIT_CHGR_PD_RTCSET ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL1 */ +#define BIT_DP_DM_SW_EN ( BIT(15) ) +#define BITS_CHGR_CC_I(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_VBAT_OVP_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_VCHG_OVP_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL2 */ +#define BITS_CHG_PUMP_CAL(_x_) ( (_x_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_CHG_PUMP_PD ( BIT(8) ) +#define BIT_CHGR_CC_EN ( BIT(1) ) +#define BIT_RECHG ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_STATUS */ +#define BIT_CHG_DET_DONE ( BIT(11) ) +#define BIT_DP_LOW ( BIT(10) ) +#define BIT_DCP_DET ( BIT(9) ) +#define BIT_CHG_DET ( BIT(8) ) +#define BIT_SDP_INT ( BIT(7) ) +#define BIT_DCP_INT ( BIT(6) ) +#define BIT_CDP_INT ( BIT(5) ) +#define BIT_CHGR_CV_STATUS ( BIT(4) ) +#define BIT_CHGR_ON ( BIT(3) ) +#define BIT_CHGR_INT ( BIT(2) ) +#define BIT_VBAT_OVI ( BIT(1) ) +#define BIT_VCHG_OVI ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_ANA_MIXED_CTRL */ +#define BIT_PTEST_PD_RTCSET ( BIT(15) ) +#define BIT_THM_CHIP_PD_FLAG ( BIT(8) ) +#define BIT_THM_CHIP_PD_FLAG_CLR ( BIT(7) ) +#define BITS_THM_CAL_SEL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)) ) +#define BIT_THM_AUTO_PD_EN ( BIT(4) ) +#define BIT_BG_LP_EN ( BIT(3) ) +#define BITS_UVHO_T(_x_) ( (_x_) << 1 & (BIT(1)|BIT(2)) ) +#define BIT_UVHO_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN0 */ +#define BIT_LDO_XTL_EN ( BIT(15) ) +#define BIT_LDO_RF1_EXT_XTL2_EN ( BIT(11) ) +#define BIT_LDO_RF1_EXT_XTL1_EN ( BIT(10) ) +#define BIT_LDO_RF1_EXT_XTL0_EN ( BIT(9) ) +#define BIT_LDO_RF1_XTL2_EN ( BIT(8) ) +#define BIT_LDO_RF1_XTL1_EN ( BIT(7) ) +#define BIT_LDO_RF1_XTL0_EN ( BIT(6) ) +#define BIT_LDO_RF0_EXT_XTL2_EN ( BIT(5) ) +#define BIT_LDO_RF0_EXT_XTL1_EN ( BIT(4) ) +#define BIT_LDO_RF0_EXT_XTL0_EN ( BIT(3) ) +#define BIT_LDO_RF0_XTL2_EN ( BIT(2) ) +#define BIT_LDO_RF0_XTL1_EN ( BIT(1) ) +#define BIT_LDO_RF0_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN1 */ +#define BIT_LDO_VDD25_EXT_XTL2_EN ( BIT(11) ) +#define BIT_LDO_VDD25_EXT_XTL1_EN ( BIT(10) ) +#define BIT_LDO_VDD25_EXT_XTL0_EN ( BIT(9) ) +#define BIT_LDO_VDD25_XTL2_EN ( BIT(8) ) +#define BIT_LDO_VDD25_XTL1_EN ( BIT(7) ) +#define BIT_LDO_VDD25_XTL0_EN ( BIT(6) ) +#define BIT_LDO_RF2_EXT_XTL2_EN ( BIT(5) ) +#define BIT_LDO_RF2_EXT_XTL1_EN ( BIT(4) ) +#define BIT_LDO_RF2_EXT_XTL0_EN ( BIT(3) ) +#define BIT_LDO_RF2_XTL2_EN ( BIT(2) ) +#define BIT_LDO_RF2_XTL1_EN ( BIT(1) ) +#define BIT_LDO_RF2_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN2 */ +#define BIT_LDO_AVDD18_EXT_XTL2_EN ( BIT(11) ) +#define BIT_LDO_AVDD18_EXT_XTL1_EN ( BIT(10) ) +#define BIT_LDO_AVDD18_EXT_XTL0_EN ( BIT(9) ) +#define BIT_LDO_AVDD18_XTL2_EN ( BIT(8) ) +#define BIT_LDO_AVDD18_XTL1_EN ( BIT(7) ) +#define BIT_LDO_AVDD18_XTL0_EN ( BIT(6) ) +#define BIT_LDO_SIM2_EXT_XTL2_EN ( BIT(5) ) +#define BIT_LDO_SIM2_EXT_XTL1_EN ( BIT(4) ) +#define BIT_LDO_SIM2_EXT_XTL0_EN ( BIT(3) ) +#define BIT_LDO_SIM2_XTL2_EN ( BIT(2) ) +#define BIT_LDO_SIM2_XTL1_EN ( BIT(1) ) +#define BIT_LDO_SIM2_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN3 */ +#define BIT_DCDC_BG_EXT_XTL2_EN ( BIT(11) ) +#define BIT_DCDC_BG_EXT_XTL1_EN ( BIT(10) ) +#define BIT_DCDC_BG_EXT_XTL0_EN ( BIT(9) ) +#define BIT_DCDC_BG_XTL2_EN ( BIT(8) ) +#define BIT_DCDC_BG_XTL1_EN ( BIT(7) ) +#define BIT_DCDC_BG_XTL0_EN ( BIT(6) ) +#define BIT_BG_EXT_XTL2_EN ( BIT(5) ) +#define BIT_BG_EXT_XTL1_EN ( BIT(4) ) +#define BIT_BG_EXT_XTL0_EN ( BIT(3) ) +#define BIT_BG_XTL2_EN ( BIT(2) ) +#define BIT_BG_XTL1_EN ( BIT(1) ) +#define BIT_BG_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN4 */ +#define BIT_DCDC_WRF_XTL2_EN ( BIT(14) ) +#define BIT_DCDC_WRF_XTL1_EN ( BIT(13) ) +#define BIT_DCDC_WRF_XTL0_EN ( BIT(12) ) +#define BIT_DCDC_WPA_XTL2_EN ( BIT(11) ) +#define BIT_DCDC_WPA_XTL1_EN ( BIT(10) ) +#define BIT_DCDC_WPA_XTL0_EN ( BIT(9) ) +#define BIT_DCDC_MEM_XTL2_EN ( BIT(8) ) +#define BIT_DCDC_MEM_XTL1_EN ( BIT(7) ) +#define BIT_DCDC_MEM_XTL0_EN ( BIT(6) ) +#define BIT_DCDC_GEN_XTL2_EN ( BIT(5) ) +#define BIT_DCDC_GEN_XTL1_EN ( BIT(4) ) +#define BIT_DCDC_GEN_XTL0_EN ( BIT(3) ) +#define BIT_DCDC_CORE_XTL2_EN ( BIT(2) ) +#define BIT_DCDC_CORE_XTL1_EN ( BIT(1) ) +#define BIT_DCDC_CORE_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN5 */ +#define BIT_DCDC_WRF_EXT_XTL2_EN ( BIT(14) ) +#define BIT_DCDC_WRF_EXT_XTL1_EN ( BIT(13) ) +#define BIT_DCDC_WRF_EXT_XTL0_EN ( BIT(12) ) +#define BIT_DCDC_WPA_EXT_XTL2_EN ( BIT(11) ) +#define BIT_DCDC_WPA_EXT_XTL1_EN ( BIT(10) ) +#define BIT_DCDC_WPA_EXT_XTL0_EN ( BIT(9) ) +#define BIT_DCDC_MEM_EXT_XTL2_EN ( BIT(8) ) +#define BIT_DCDC_MEM_EXT_XTL1_EN ( BIT(7) ) +#define BIT_DCDC_MEM_EXT_XTL0_EN ( BIT(6) ) +#define BIT_DCDC_GEN_EXT_XTL2_EN ( BIT(5) ) +#define BIT_DCDC_GEN_EXT_XTL1_EN ( BIT(4) ) +#define BIT_DCDC_GEN_EXT_XTL0_EN ( BIT(3) ) +#define BIT_DCDC_CORE_EXT_XTL2_EN ( BIT(2) ) +#define BIT_DCDC_CORE_EXT_XTL1_EN ( BIT(1) ) +#define BIT_DCDC_CORE_EXT_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_ANA_STATUS */ +#define BIT_BONDOPT6 ( BIT(6) ) +#define BIT_BONDOPT5 ( BIT(5) ) +#define BIT_BONDOPT4 ( BIT(4) ) +#define BIT_BONDOPT3 ( BIT(3) ) +#define BIT_BONDOPT2 ( BIT(2) ) +#define BIT_BONDOPT1 ( BIT(1) ) +#define BIT_BONDOPT0 ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_POR_RST_MONITOR */ +#define BITS_POR_RST_MONITOR(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_WDG_RST_MONITOR */ +#define BITS_WDG_RST_MONITOR(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_POR_PIN_RST_MONITOR */ +#define BITS_POR_PIN_RST_MONITOR(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_POR_SRC_FLAG */ +#define BIT_POR_SW_FORCE_ON ( BIT(15) ) +#define BITS_POR_SRC_FLAG(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_POR_7S_CTRL */ +#define BIT_PBINT_7S_FLAG_CLR ( BIT(15) ) +#define BIT_EXT_RSTN_FLAG_CLR ( BIT(14) ) +#define BIT_CHGR_INT_FLAG_CLR ( BIT(13) ) +#define BIT_PBINT2_FLAG_CLR ( BIT(12) ) +#define BIT_PBINT_FLAG_CLR ( BIT(11) ) +#define BIT_PBINT_7S_RST_SWMODE_RTCSTS ( BIT(10) ) +#define BIT_PBINT_7S_RST_SWMODE_RTCCLR ( BIT(9) ) +#define BIT_PBINT_7S_RST_SWMODE_RTCSET ( BIT(8) ) +#define BITS_PBINT_7S_RST_THRESHOLD(_x_)( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_PBINT_7S_RST_DISABLE ( BIT(3) ) +#define BIT_PBINT_7S_RST_MODE_RTCSTS ( BIT(2) ) +#define BIT_PBINT_7S_RST_MODE_RTCCLR ( BIT(1) ) +#define BIT_PBINT_7S_RST_MODE_RTCSET ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_INT_DEBUG */ +#define BIT_OTP_INT_DEB ( BIT(10) ) +#define BIT_THM_INT_DEB ( BIT(9) ) +#define BIT_AUD_PROT_INT_DEB ( BIT(8) ) +#define BIT_AUD_HEADBTN_INT_DEB ( BIT(7) ) +#define BIT_EIC_INT_DEB ( BIT(6) ) +#define BIT_FGU_INT_DEB ( BIT(5) ) +#define BIT_WDG_INT_DEB ( BIT(4) ) +#define BIT_RTC_INT_DEB ( BIT(3) ) +#define BIT_GPIO_INT_DEB ( BIT(2) ) +#define BIT_ADC_INT_DEB ( BIT(1) ) +#define BIT_INT_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_GPI_DEBUG */ +#define BIT_HEAD_INSERT2_DEB ( BIT(9) ) +#define BIT_HEAD_INSERT_DEB ( BIT(8) ) +#define BIT_HEAD_BUTTON_DEB ( BIT(7) ) +#define BIT_PBINT2_DEB ( BIT(6) ) +#define BIT_PBINT_DEB ( BIT(5) ) +#define BIT_VCHG_OVI_DEB ( BIT(4) ) +#define BIT_VBAT_OVI_DEB ( BIT(3) ) +#define BIT_CHGR_INT_DEB ( BIT(2) ) +#define BIT_GPI_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_HWRST_RTC */ +#define BITS_HWRST_RTC_REG_STS(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_HWRST_RTC_REG_SET(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_CHIP_ID_LOW */ +#define BITS_CHIP_ID_LOW(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_CHIP_ID_HIGH */ +#define BITS_CHIP_ID_HIGH(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_ARM_MF_REG */ +#define BITS_ARM_MF_REG(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_AFUSE_CTRL */ +#define BIT_AFUSE_READ_REQ ( BIT(7) ) +#define BITS_AFUSE_READ_DLY(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) + +/* bits definitions for register ANA_REG_GLB_AFUSE_OUT0 */ +#define BITS_AFUSE_OUT0(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_AFUSE_OUT1 */ +#define BITS_AFUSE_OUT1(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_AFUSE_OUT2 */ +#define BITS_AFUSE_OUT2(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_AFUSE_OUT3 */ +#define BITS_AFUSE_OUT3(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_CA_CTRL4 */ +#define BIT_EXT_RSTN_PD_EN ( BIT(14) ) +#define BIT_PB_7S_RST_PD_EN ( BIT(13) ) +#define BIT_WDG_RST_PD_EN ( BIT(12) ) +#define BIT_SW_RST_EMMCIO_PD_EN ( BIT(11) ) +#define BIT_SW_RST_EMMCCORE_PD_EN ( BIT(10) ) +#define BITS_SW_RST_PD_THRESHOLD(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) + +/* bits definitions for register ANA_REG_GLB_MCU_WR_PROT_VALUE */ +#define BIT_MCU_WR_PROT ( BIT(15) ) +#define BITS_MCU_WR_PROT_VALUE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_MP_PWR_CTRL0 */ +#define BIT_LDO_SIM1_EXT_XTL2_EN ( BIT(15) ) +#define BIT_LDO_SIM1_EXT_XTL1_EN ( BIT(14) ) +#define BIT_LDO_SIM1_EXT_XTL0_EN ( BIT(13) ) +#define BIT_LDO_SIM1_XTL2_EN ( BIT(12) ) +#define BIT_LDO_SIM1_XTL1_EN ( BIT(11) ) +#define BIT_LDO_SIM1_XTL0_EN ( BIT(10) ) +#define BIT_LDO_SIM0_EXT_XTL2_EN ( BIT(9) ) +#define BIT_LDO_SIM0_EXT_XTL1_EN ( BIT(8) ) +#define BIT_LDO_SIM0_EXT_XTL0_EN ( BIT(7) ) +#define BIT_LDO_SIM0_XTL2_EN ( BIT(6) ) +#define BIT_LDO_SIM0_XTL1_EN ( BIT(5) ) +#define BIT_LDO_SIM0_XTL0_EN ( BIT(4) ) +#define BIT_PWR_OFF_SEQ_EN ( BIT(3) ) +#define BIT_DCDC_CORE_SLP_OUT_STEP_EN ( BIT(1) ) +#define BIT_DCDC_CORE_SLP_IN_STEP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_MP_PWR_CTRL1 */ +#define BITS_DCDC_CORE_CTL_SLP_STEP5(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_DCDC_CORE_CTL_SLP_STEP4(_x_) ( (_x_) << 9 & (BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DCDC_CORE_CTL_SLP_STEP3(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_DCDC_CORE_CTL_SLP_STEP2(_x_) ( (_x_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_DCDC_CORE_CTL_SLP_STEP1(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register ANA_REG_GLB_MP_PWR_CTRL2 */ +#define BITS_DCDC_CORE_CAL_SLP_STEP3(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_DCDC_CORE_CAL_SLP_STEP2(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CAL_SLP_STEP1(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_MP_PWR_CTRL3 */ +#define BITS_DCDC_ARM_STBOP(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_DCDC_CORE_STBOP(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_DCDC_CORE_CAL_SLP_STEP5(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CAL_SLP_STEP4(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_MP_LDO_CTRL */ +#define BITS_LDOD_LP_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDOA_LP_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDODCDC_LP_CAL(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_MP_CHG_CTRL */ +#define BIT_CHGR_INT_EN ( BIT(8) ) +#define BIT_CHGR_DRV ( BIT(5) ) +#define BIT_CHGR_OSC ( BIT(4) ) +#define BITS_CHGR_DPM(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_CHGR_ITERM(_x_) ( (_x_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_MP_MISC_CTRL */ +#define BITS_LDO_RF1_V_BOND(_x_) ( (_x_) << 11 & (BIT(11)|BIT(12)) ) +#define BITS_LDO_VDD25_V_BOND(_x_) ( (_x_) << 9 & (BIT(9)|BIT(10)) ) +#define BITS_DCDC_ARM_CTL_BOND(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_DCDC_CORE_CTL_BOND(_x_) ( (_x_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BIT_DCOFFSET_EN ( BIT(2) ) +#define BIT_CHOP_EN ( BIT(1) ) +#define BIT_WHTLED_EXT_RES_CTRL ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_MP_DCDC_DEDT_CTRL */ +#define BITS_DCDC_WPA_DEDT_EN(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_DCDC_WRF_DEDT_EN(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_DCDC_GEN_DEDT_EN(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_DCDC_MEM_DEDT_EN(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_DCDC_ARM_DEDT_EN(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DCDC_CORE_DEDT_EN(_x_) ( (_x_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_CA_CTRL0 */ +#define BITS_SD_CLK_P(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BIT_SD_CHOP_CAP_EN ( BIT(13) ) +#define BIT_LDO_CAMIO_V_B2 ( BIT(12) ) +#define BIT_LDO_CAMIO_EXT_XTL2_EN ( BIT(11) ) +#define BIT_LDO_CAMIO_EXT_XTL1_EN ( BIT(10) ) +#define BIT_LDO_CAMIO_EXT_XTL0_EN ( BIT(9) ) +#define BIT_LDO_CAMIO_XTL2_EN ( BIT(8) ) +#define BIT_LDO_CAMIO_XTL1_EN ( BIT(7) ) +#define BIT_LDO_CAMIO_XTL0_EN ( BIT(6) ) +#define BIT_LDO_CAMD_EXT_XTL2_EN ( BIT(5) ) +#define BIT_LDO_CAMD_EXT_XTL1_EN ( BIT(4) ) +#define BIT_LDO_CAMD_EXT_XTL0_EN ( BIT(3) ) +#define BIT_LDO_CAMD_XTL2_EN ( BIT(2) ) +#define BIT_LDO_CAMD_XTL1_EN ( BIT(1) ) +#define BIT_LDO_CAMD_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CA_CTRL1 */ +#define BITS_SMPL_MODE(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_CA_CTRL2 */ +#define BIT_SMPL_PWR_ON_FLAG ( BIT(15) ) +#define BIT_SMPL_MODE_WR_ACK_FLAG ( BIT(14) ) +#define BIT_SMPL_PWR_ON_FLAG_CLR ( BIT(13) ) +#define BIT_SMPL_MODE_WR_ACK_FLAG_CLR ( BIT(12) ) +#define BIT_SMPL_PWR_ON_SET ( BIT(11) ) +#define BIT_SLP_LDOKPLED_PD_EN ( BIT(9) ) +#define BIT_LDO_KPLED_PD ( BIT(8) ) +#define BITS_LDO_KPLED_V(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_CA_CTRL3 */ +#define BITS_VBAT_CRASH_V(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BIT_PBINT_7S_AUTO_ON_EN_CLR ( BIT(13) ) +#define BIT_PBINT_7S_AUTO_ON_EN_SET ( BIT(12) ) +#define BIT_VIBR_LDO_EN ( BIT(10) ) +#define BIT_SLP_LDOVIBR_PD_EN ( BIT(9) ) +#define BIT_LDO_VIBR_PD ( BIT(8) ) +#define BITS_LDO_VIBR_V(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CORE_ADI */ +#define BITS_DCDC_CORE_CTL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DCDC_CORE_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_ARM_ADI */ +#define BITS_DCDC_ARM_CTL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DCDC_ARM_CAL_ADI(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_MEM_ADI */ +#define BIT_DCDC_MEM_CTL_ADI ( BIT(5) ) +#define BITS_DCDC_MEM_CAL_ADI(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_GEN_ADI */ +#define BITS_DCDC_GEN_CTL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DCDC_GEN_CAL_ADI(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_WRF_ADI */ +#define BITS_DCDC_WRF_CTL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)) ) +#define BITS_DCDC_WRF_CAL_ADI(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_WPA_ADI */ +#define BITS_DCDC_WPA_CAL_ADI(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_WPA_DCM_ADI */ +#define BIT_DCDC_WPA_DCM_ADI ( BIT(0) ) + +#endif /* __REGS_ANA_SC2713S_GLB_H__ */ diff --git a/include/soc/sprd/chip_x30g/__regs_ana_sc2723_glb.h b/include/soc/sprd/chip_x30g/__regs_ana_sc2723_glb.h new file mode 100644 index 00000000..fe9cd745 --- /dev/null +++ b/include/soc/sprd/chip_x30g/__regs_ana_sc2723_glb.h @@ -0,0 +1,952 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __ANA_REGS_GLB_H__ +#define __ANA_REGS_GLB_H__ + +#define ANA_REGS_GLB + +/* registers definitions for controller ANA_REGS_GLB */ +#define ANA_REG_GLB_ARM_MODULE_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0000) +#define ANA_REG_GLB_ARM_CLK_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0004) +#define ANA_REG_GLB_RTC_CLK_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0008) +#define ANA_REG_GLB_ARM_RST SCI_ADDR(ANA_REGS_GLB_BASE, 0x000C) +#define ANA_REG_GLB_LDO_DCDC_PD SCI_ADDR(ANA_REGS_GLB_BASE, 0x0010) +#define ANA_REG_GLB_LDO_PD_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0014) +#define ANA_REG_GLB_LDO_V_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0018) +#define ANA_REG_GLB_LDO_V_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x001C) +#define ANA_REG_GLB_LDO_V_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0020) +#define ANA_REG_GLB_LDO_V_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0024) +#define ANA_REG_GLB_LDO_V_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0028) +#define ANA_REG_GLB_LDO_V_CTRL5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x002C) +#define ANA_REG_GLB_LDO_V_CTRL6 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0030) +#define ANA_REG_GLB_LDO_V_CTRL7 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0034) +#define ANA_REG_GLB_LDO_V_CTRL8 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0038) +#define ANA_REG_GLB_LDO_V_CTRL9 SCI_ADDR(ANA_REGS_GLB_BASE, 0x003C) +#define ANA_REG_GLB_LDO_V_CTRL10 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0040) +#define ANA_REG_GLB_LDO_V_CTRL11 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0044) +#define ANA_REG_GLB_LDO_LP_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0048) +#define ANA_REG_GLB_DCDC_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x004C) +#define ANA_REG_GLB_DCDC_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0050) +#define ANA_REG_GLB_DCDC_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0054) +#define ANA_REG_GLB_DCDC_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0058) +#define ANA_REG_GLB_DCDC_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x005C) +#define ANA_REG_GLB_DCDC_CTRL5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0060) +#define ANA_REG_GLB_DCDC_CTRL6 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0064) +#define ANA_REG_GLB_DCDC_CTRL7 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0068) +#define ANA_REG_GLB_DCDC_CTRL8 SCI_ADDR(ANA_REGS_GLB_BASE, 0x006C) +#define ANA_REG_GLB_DCDC_CTRL9 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0070) +#define ANA_REG_GLB_DCDC_CTRL10 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0074) +#define ANA_REG_GLB_DCDC_CTRL11 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0078) +#define ANA_REG_GLB_DCDC_CTRL12 SCI_ADDR(ANA_REGS_GLB_BASE, 0x007C) +#define ANA_REG_GLB_DCDC_CTRL13 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0080) +#define ANA_REG_GLB_DCDC_CTRL14 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0084) +#define ANA_REG_GLB_DCDC_CTRL15 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0088) +#define ANA_REG_GLB_SLP_WAIT_DCDCARM SCI_ADDR(ANA_REGS_GLB_BASE, 0x008C) +#define ANA_REG_GLB_PWR_SLP_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0090) +#define ANA_REG_GLB_PWR_SLP_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0094) +#define ANA_REG_GLB_PWR_SLP_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0098) +#define ANA_REG_GLB_PWR_SLP_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x009C) +#define ANA_REG_GLB_PWR_SLP_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A0) +#define ANA_REG_GLB_AUD_SLP_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A4) +#define ANA_REG_GLB_DCDC_SLP_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A8) +#define ANA_REG_GLB_DCDC_SLP_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00AC) +#define ANA_REG_GLB_DCDC_SLP_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B0) +#define ANA_REG_GLB_DCDC_SLP_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B4) +#define ANA_REG_GLB_DCDC_SLP_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B8) +#define ANA_REG_GLB_DCDC_SLP_CTRL5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00BC) +#define ANA_REG_GLB_PWR_SEL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C0) +#define ANA_REG_GLB_PWR_XTL_EN0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C4) +#define ANA_REG_GLB_PWR_XTL_EN1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C8) +#define ANA_REG_GLB_PWR_XTL_EN2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00CC) +#define ANA_REG_GLB_PWR_XTL_EN3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D0) +#define ANA_REG_GLB_32KLESS_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D4) +#define ANA_REG_GLB_32KLESS_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D8) +#define ANA_REG_GLB_32KLESS_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00DC) +#define ANA_REG_GLB_32KLESS_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E0) +#define ANA_REG_GLB_AUXAD_CTL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E4) +#define ANA_REG_GLB_XTL_WAIT_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E8) +#define ANA_REG_GLB_RGB_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00EC) +#define ANA_REG_GLB_WHTLED_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F0) +#define ANA_REG_GLB_WHTLED_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0094) +#define ANA_REG_GLB_WHTLED_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0098) +#define ANA_REG_GLB_KPLED_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F4) +#define ANA_REG_GLB_VIBR_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F8) +#define ANA_REG_GLB_AUDIO_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00FC) +#define ANA_REG_GLB_AUDIO_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0100) +#define ANA_REG_GLB_CHGR_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0104) +#define ANA_REG_GLB_CHGR_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0108) +#define ANA_REG_GLB_CHGR_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x010C) +#define ANA_REG_GLB_CHGR_DET_FGU_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0110) +#define ANA_REG_GLB_CHGR_STATUS SCI_ADDR(ANA_REGS_GLB_BASE, 0x0114) +#define ANA_REG_GLB_MIXED_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0118) +#define ANA_REG_GLB_MIXED_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x011C) +#define ANA_REG_GLB_SWRST_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0120) +#define ANA_REG_GLB_POR_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x0124) +#define ANA_REG_GLB_WDG_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x0128) +#define ANA_REG_GLB_POR_PIN_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x012C) +#define ANA_REG_GLB_POR_SRC_FLAG SCI_ADDR(ANA_REGS_GLB_BASE, 0x0130) +#define ANA_REG_GLB_POR_7S_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0134) +#define ANA_REG_GLB_HWRST_RTC SCI_ADDR(ANA_REGS_GLB_BASE, 0x0138) +#define ANA_REG_GLB_CHIP_ID_LOW SCI_ADDR(ANA_REGS_GLB_BASE, 0x013C) +#define ANA_REG_GLB_CHIP_ID_HIGH SCI_ADDR(ANA_REGS_GLB_BASE, 0x0140) +#define ANA_REG_GLB_ARM_MF_REG SCI_ADDR(ANA_REGS_GLB_BASE, 0x0144) +#define ANA_REG_GLB_ARCH_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0148) +#define ANA_REG_GLB_MCU_WR_PROT_VALUE SCI_ADDR(ANA_REGS_GLB_BASE, 0x014C) +#define ANA_REG_GLB_PWR_WR_PROT_VALUE SCI_ADDR(ANA_REGS_GLB_BASE, 0x0150) +#define ANA_REG_GLB_SMPL_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0154) +#define ANA_REG_GLB_SMPL_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0158) +#define ANA_REG_GLB_RTC_RST0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x015C) +#define ANA_REG_GLB_RTC_RST1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0160) +#define ANA_REG_GLB_RTC_RST2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0164) +#define ANA_REG_GLB_LDO_SHPT_PD1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0188) +#define ANA_REG_GLB_LDO_SHPT_PD2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x018C) +#define ANA_REG_GLB_BATDET_CUR_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0190) +#define ANA_REG_GLB_RTC_CLK_STOP SCI_ADDR(ANA_REGS_GLB_BASE, 0x0194) +#define ANA_REG_GLB_VBAT_DROP_CNT SCI_ADDR(ANA_REGS_GLB_BASE, 0x0198) +#define ANA_REG_GLB_DCDC_DISCHRG SCI_ADDR(ANA_REGS_GLB_BASE, 0x019C) +#define ANA_REG_GLB_DCDC_CORE_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0200) +#define ANA_REG_GLB_DCDC_ARM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0204) +#define ANA_REG_GLB_DCDC_MEM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0208) +#define ANA_REG_GLB_DCDC_GEN_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x020C) +#define ANA_REG_GLB_DCDC_WPA_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0210) +#define ANA_REG_GLB_DCDC_WPA_DCM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0214) +#define ANA_REG_GLB_DCDC_CON_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0218) +#define ANA_REG_GLB_DCDC_RF_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x021C) + +/* bits definitions for register ANA_REG_GLB_ARM_MODULE_EN */ +#define BIT_ANA_IMPD_ADC_EN ( BIT(12) ) +#define BIT_ANA_THM_EN ( BIT(11) ) +#define BIT_ANA_BLTC_EN ( BIT(10) ) +#define BIT_ANA_PINREG_EN ( BIT(9) ) +#define BIT_ANA_FGU_EN ( BIT(8) ) +#define BIT_ANA_EFS_EN ( BIT(7) ) +#define BIT_ANA_ADC_EN ( BIT(6) ) +#define BIT_ANA_HDT_EN ( BIT(5) ) +#define BIT_ANA_AUD_EN ( BIT(4) ) +#define BIT_ANA_EIC_EN ( BIT(3) ) +#define BIT_ANA_WDG_EN ( BIT(2) ) +#define BIT_ANA_RTC_EN ( BIT(1) ) +#define BIT_ANA_CAL_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_ARM_CLK_EN */ +#define BIT_CLK_IMPD_ADC_EN ( BIT(10) ) +#define BIT_CLK_AUXAD_EN ( BIT(9) ) +#define BIT_CLK_AUXADC_EN ( BIT(8) ) +#define BITS_CLK_CAL_SRC_SEL(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BIT_CLK_CAL_EN ( BIT(5) ) +#define BIT_CLK_AUD_HID_EN ( BIT(4) ) +#define BIT_CLK_AUD_HBD_EN ( BIT(3) ) +#define BIT_CLK_AUD_LOOP_EN ( BIT(2) ) +#define BIT_CLK_AUD_6P5M_EN ( BIT(1) ) +#define BIT_CLK_AUDIF_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_RTC_CLK_EN */ +#define BIT_RTC_EFS_EN ( BIT(12) ) +#define BIT_RTC_THMA_AUTO_EN ( BIT(11) ) +#define BIT_RTC_THMA_EN ( BIT(10) ) +#define BIT_RTC_THM_EN ( BIT(9) ) +#define BIT_RTC_BLTC_EN ( BIT(8) ) +#define BIT_RTC_FGU_EN ( BIT(7) ) +#define BIT_RTC_FGUA_EN ( BIT(6) ) +#define BIT_RTC_VIBR_EN ( BIT(5) ) +#define BIT_RTC_AUD_EN ( BIT(4) ) +#define BIT_RTC_EIC_EN ( BIT(3) ) +#define BIT_RTC_WDG_EN ( BIT(2) ) +#define BIT_RTC_RTC_EN ( BIT(1) ) +#define BIT_RTC_ARCH_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_ARM_RST */ +#define BIT_ANA_THMA_SOFT_RST ( BIT(15) ) +#define BIT_ANA_THM_SOFT_RST ( BIT(14) ) +#define BIT_ANA_BLTC_SOFT_RST ( BIT(13) ) +#define BIT_ANA_AUD_32K_SOFT_RST ( BIT(12) ) +#define BIT_ANA_AUDTX_SOFT_RST ( BIT(11) ) +#define BIT_ANA_AUDRX_SOFT_RST ( BIT(10) ) +#define BIT_ANA_AUD_SOFT_RST ( BIT(9) ) +#define BIT_ANA_AUD_HDT_SOFT_RST ( BIT(8) ) +#define BIT_ANA_EFS_SOFT_RST ( BIT(7) ) +#define BIT_ANA_ADC_SOFT_RST ( BIT(6) ) +#define BIT_ANA_PWM0_SOFT_RST ( BIT(5) ) +#define BIT_ANA_FGU_SOFT_RST ( BIT(4) ) +#define BIT_ANA_EIC_SOFT_RST ( BIT(3) ) +#define BIT_ANA_WDG_SOFT_RST ( BIT(2) ) +#define BIT_ANA_RTC_SOFT_RST ( BIT(1) ) +#define BIT_ANA_CAL_SOFT_RST ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_DCDC_PD */ +#define BIT_LDO_EMM_PD ( BIT(15) ) +#define BIT_DCDC_TOPCLK6M_PD ( BIT(14) ) +#define BIT_DCDC_RF_PD ( BIT(13) ) +#define BIT_DCDC_GEN_PD ( BIT(12) ) +#define BIT_DCDC_MEM_PD ( BIT(11) ) +#define BIT_DCDC_ARM_PD ( BIT(10) ) +#define BIT_DCDC_CORE_PD ( BIT(9) ) +#define BIT_LDO_RF0_PD ( BIT(8) ) +#define BIT_LDO_EMMCCORE_PD ( BIT(7) ) +#define BIT_LDO_GEN1_PD ( BIT(6) ) +#define BIT_LDO_DCXO_PD ( BIT(5) ) +#define BIT_LDO_GEN0_PD ( BIT(4) ) +#define BIT_LDO_VDD25_PD ( BIT(3) ) +#define BIT_LDO_VDD28_PD ( BIT(2) ) +#define BIT_LDO_VDD18_PD ( BIT(1) ) +#define BIT_BG_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_PD_CTRL */ +#define BIT_LDO_LPREF_PD_SW ( BIT(15) ) +#define BIT_DCDC_WPA_PD ( BIT(14) ) +#define BIT_DCDC_CON_PD ( BIT(13) ) +#define BIT_LDO_WIFIPA_PD ( BIT(11) ) +#define BIT_LDO_SDCORE_PD ( BIT(10) ) +#define BIT_LDO_USB_PD ( BIT(8) ) +#define BIT_LDO_CAMMOT_PD ( BIT(7) ) +#define BIT_LDO_CAMIO_PD ( BIT(6) ) +#define BIT_LDO_CAMD_PD ( BIT(5) ) +#define BIT_LDO_CAMA_PD ( BIT(4) ) +#define BIT_LDO_SIM2_PD ( BIT(3) ) +#define BIT_LDO_SIM1_PD ( BIT(2) ) +#define BIT_LDO_SIM0_PD ( BIT(1) ) +#define BIT_LDO_SDIO_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL0 */ +#define BITS_LDO_RF0_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_WIFIPA_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL1 */ +#define BITS_LDO_CAMIO_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_CAMD_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL2 */ +#define BITS_LDO_GEN0_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL3 */ +#define BITS_LDO_GEN1_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_VDD28_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL4 */ +#define BITS_LDO_SIM0_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_SDIO_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL5 */ +#define BITS_LDO_SIM2_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_SIM1_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL6 */ +#define BITS_LDO_SDCORE_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_CAMA_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL7 */ +#define BITS_LDO_EMMCCORE_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_CAMMOT_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL8 */ +#define BITS_LDO_DCXO_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_DCXO_LP_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL9 */ +#define BITS_LDO_VDD18_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_USB_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL10 */ +#define BITS_LDO_VDD25_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL11 */ +#define BITS_VBATBK_V(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_LDOB_CAL_SEL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_LDOA_CAL_SEL (_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_LDOD_CAL_SEL(_x_) ( (_x_) << 3 & (BIT(3)|BIT(4)) ) +#define BITS_LDODCDC_CAL_SEL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_LP_CTRL */ +#define BITS_LDOB_LP_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDOA_LP_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDODCDC_LP_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL0 */ +#define BITS_DCDC_CORE_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_CORE_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_CORE_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_CORE_QKRSPS ( BIT(3) ) +#define BIT_DCDC_CORE_PFM ( BIT(2) ) +#define BIT_DCDC_CORE_DCM ( BIT(1) ) +#define BIT_DCDC_CORE_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL1 */ +#define BITS_DCDC_MEM_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_MEM_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_MEM_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_MEM_QKRSPS ( BIT(3) ) +#define BIT_DCDC_MEM_PFM ( BIT(2) ) +#define BIT_DCDC_MEM_DCM ( BIT(1) ) +#define BIT_DCDC_MEM_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL2 */ +#define BITS_DCDC_GEN_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_GEN_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_GEN_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_GEN_QKRSPS ( BIT(3) ) +#define BIT_DCDC_GEN_PFM ( BIT(2) ) +#define BIT_DCDC_GEN_DCM ( BIT(1) ) +#define BIT_DCDC_GEN_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL3 */ +#define BITS_DCDC_ARM_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_ARM_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_ARM_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_ARM_QKRSPS ( BIT(3) ) +#define BIT_DCDC_ARM_PFM ( BIT(2) ) +#define BIT_DCDC_ARM_DCM ( BIT(1) ) +#define BIT_DCDC_ARM_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL4 */ +#define BITS_DCDC_WPA_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_WPA_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_WPA_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_WPA_QKRSPS ( BIT(3) ) +#define BIT_DCDC_WPA_PFM ( BIT(2) ) +#define BIT_DCDC_WPA_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL5 */ +#define BITS_DCDC_RF_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_RF_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_RF_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_RF_QKRSPS ( BIT(3) ) +#define BIT_DCDC_RF_PFM ( BIT(2) ) +#define BIT_DCDC_RF_DCM ( BIT(1) ) +#define BIT_DCDC_RF_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL6 */ +#define BITS_DCDC_CON_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_CON_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_CON_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_CON_QKRSPS ( BIT(3) ) +#define BIT_DCDC_CON_PFM ( BIT(2) ) +#define BIT_DCDC_CON_DCM ( BIT(1) ) +#define BIT_DCDC_CON_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL7 */ +#define BITS_DCDC_MEM_CF(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_DCDC_MEM_PFMAD(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_DCDC_MEM_CL_CTRL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_DCDC_CORE_DUALSEL ( BIT(7) ) +#define BIT_DCDC_CORE_MERGEEN ( BIT(6) ) +#define BITS_DCDC_CORE_CF(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_DCDC_CORE_PFMAD(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DCDC_CORE_CL_CTRL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL8 */ +#define BIT_DCDC_ARM_DUALSEL ( BIT(15) ) +#define BIT_DCDC_ARM_MERGEEN ( BIT(14) ) +#define BITS_DCDC_ARM_CF(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_DCDC_ARM_PFMAD(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_DCDC_ARM_CL_CTRL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_DCDC_GEN_CF(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_DCDC_GEN_PFMAD(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DCDC_GEN_CL_CTRL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL9 */ +#define BIT_DCDC_CON_MERGEEN ( BIT(14) ) +#define BITS_DCDC_CON_CF(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_DCDC_CON_PFMAD(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_DCDC_CON_CL_CTRL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_DCDC_RF_MERGEEN ( BIT(6) ) +#define BITS_DCDC_RF_CF(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_DCDC_RF_PFMAD(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DCDC_RF_CL_CTRL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL10 */ +#define BIT_DCDC_WPA_BPOUT_SOFTW ( BIT(15) ) +#define BITS_DCDC_WPA_VBAT_DIV(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BIT_DCDC_WPA_BPEN ( BIT(11) ) +#define BIT_DCDC_WPA_BPMODE ( BIT(10) ) +#define BIT_DCDC_WPA_DEGEN ( BIT(9) ) +#define BIT_DCDC_WPA_APTEN ( BIT(8) ) +#define BITS_DCDC_WPA_DEBC_SEL(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_DCDC_WPA_CF(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_DCDC_WPA_PFMAD(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DCDC_WPA_CL_CTRL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL11 */ +#define BIT_DCDC_3MCLKCAL_EN ( BIT(13) ) +#define BIT_DCDC_2MCLKCAL_EN ( BIT(12) ) +#define BITS_DCDC_6MFRECAL_SW(_x_) ( (_x_) << 7 & (BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DCDC_4MFRECAL_SW(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_DCDC_CLK_SP_SEL ( BIT(1) ) +#define BIT_DCDC_CLK_SP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL12 */ +#define BIT_DCDC_CORE_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_CORE_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_CORE_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_CORE_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_ARM_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_ARM_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_ARM_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_ARM_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL13 */ +#define BIT_DCDC_MEM_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_MEM_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_MEM_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_MEM_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_GEN_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_GEN_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_GEN_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_GEN_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL14 */ +#define BIT_DCDC_WPA_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_WPA_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_WPA_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_WPA_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_RF_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_RF_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_RF_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_RF_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL15 */ +#define BITS_DCDC_CAL_SEL(_x_) ( (_x_) << 13 & (BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_DCDC_CON_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_CON_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_CON_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_CON_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_SLP_WAIT_DCDCARM */ +#define BITS_SLP_IN_WAIT_DCDCARM(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_SLP_OUT_WAIT_DCDCARM(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL0 */ +#define BIT_SLP_IO_EN ( BIT(15) ) +#define BIT_SLP_DCDCRF_PD_EN ( BIT(13) ) +#define BIT_SLP_DCDCCON_PD_EN ( BIT(12) ) +#define BIT_SLP_DCDCGEN_PD_EN ( BIT(11) ) +#define BIT_SLP_DCDCWPA_PD_EN ( BIT(10) ) +#define BIT_SLP_DCDCARM_PD_EN ( BIT(9) ) +#define BIT_SLP_LDOVDD25_PD_EN ( BIT(8) ) +#define BIT_SLP_LDORF0_PD_EN ( BIT(7) ) +#define BIT_SLP_LDOEMMCCORE_PD_EN ( BIT(6) ) +#define BIT_SLP_LDOGEN0_PD_EN ( BIT(5) ) +#define BIT_SLP_LDODCXO_PD_EN ( BIT(4) ) +#define BIT_SLP_LDOGEN1_PD_EN ( BIT(3) ) +#define BIT_SLP_LDOWIFIPA_PD_EN ( BIT(2) ) +#define BIT_SLP_LDOVDD28_PD_EN ( BIT(1) ) +#define BIT_SLP_LDOVDD18_PD_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL1 */ +#define BIT_SLP_LDO_PD_EN ( BIT(15) ) +#define BIT_SLP_LDOLPREF_PD_EN ( BIT(14) ) +#define BIT_SLP_LDOSDCORE_PD_EN ( BIT(9) ) +#define BIT_SLP_LDOUSB_PD_EN ( BIT(8) ) +#define BIT_SLP_LDOCAMMOT_PD_EN ( BIT(7) ) +#define BIT_SLP_LDOCAMIO_PD_EN ( BIT(6) ) +#define BIT_SLP_LDOCAMD_PD_EN ( BIT(5) ) +#define BIT_SLP_LDOCAMA_PD_EN ( BIT(4) ) +#define BIT_SLP_LDOSIM2_PD_EN ( BIT(3) ) +#define BIT_SLP_LDOSIM1_PD_EN ( BIT(2) ) +#define BIT_SLP_LDOSIM0_PD_EN ( BIT(1) ) +#define BIT_SLP_LDOSDIO_PD_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL2 */ +#define BIT_SLP_DCDCRF_LP_EN ( BIT(14) ) +#define BIT_SLP_DCDCCON_LP_EN ( BIT(13) ) +#define BIT_SLP_DCDCCORE_LP_EN ( BIT(12) ) +#define BIT_SLP_DCDCMEM_LP_EN ( BIT(11) ) +#define BIT_SLP_DCDCARM_LP_EN ( BIT(10) ) +#define BIT_SLP_DCDCGEN_LP_EN ( BIT(9) ) +#define BIT_SLP_DCDCWPA_LP_EN ( BIT(8) ) +#define BIT_SLP_LDORF0_LP_EN ( BIT(7) ) +#define BIT_SLP_LDOEMMCCORE_LP_EN ( BIT(6) ) +#define BIT_SLP_LDOGEN0_LP_EN ( BIT(5) ) +#define BIT_SLP_LDODCXO_LP_EN ( BIT(4) ) +#define BIT_SLP_LDOGEN1_LP_EN ( BIT(3) ) +#define BIT_SLP_LDOWIFIPA_LP_EN ( BIT(2) ) +#define BIT_SLP_LDOVDD28_LP_EN ( BIT(1) ) +#define BIT_SLP_LDOVDD18_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL3 */ +#define BIT_SLP_BG_LP_EN ( BIT(15) ) +#define BIT_LDOVDD25_LP_EN_SW ( BIT(14) ) +#define BIT_LDOSDCORE_LP_EN_SW ( BIT(13) ) +#define BIT_LDOUSB_LP_EN_SW ( BIT(12) ) +#define BIT_SLP_LDOVDD25_LP_EN ( BIT(10) ) +#define BIT_SLP_LDOSDCORE_LP_EN ( BIT(9) ) +#define BIT_SLP_LDOUSB_LP_EN ( BIT(8) ) +#define BIT_SLP_LDOCAMMOT_LP_EN ( BIT(7) ) +#define BIT_SLP_LDOCAMIO_LP_EN ( BIT(6) ) +#define BIT_SLP_LDOCAMD_LP_EN ( BIT(5) ) +#define BIT_SLP_LDOCAMA_LP_EN ( BIT(4) ) +#define BIT_SLP_LDOSIM2_LP_EN ( BIT(3) ) +#define BIT_SLP_LDOSIM1_LP_EN ( BIT(2) ) +#define BIT_SLP_LDOSIM0_LP_EN ( BIT(1) ) +#define BIT_SLP_LDOSDIO_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL4 */ +#define BIT_LDOCAMIO_LP_EN_SW ( BIT(15) ) +#define BIT_LDOCAMMOT_LP_EN_SW ( BIT(14) ) +#define BIT_LDOCAMD_LP_EN_SW ( BIT(13) ) +#define BIT_LDOCAMA_LP_EN_SW ( BIT(12) ) +#define BIT_LDOSIM2_LP_EN_SW ( BIT(11) ) +#define BIT_LDOSIM1_LP_EN_SW ( BIT(10) ) +#define BIT_LDOSIM0_LP_EN_SW ( BIT(9) ) +#define BIT_LDOSDIO_LP_EN_SW ( BIT(8) ) +#define BIT_LDORF0_LP_EN_SW ( BIT(7) ) +#define BIT_LDOEMMCCORE_LP_EN_SW ( BIT(6) ) +#define BIT_LDOGEN0_LP_EN_SW ( BIT(5) ) +#define BIT_LDODCXO_LP_EN_SW ( BIT(4) ) +#define BIT_LDOGEN1_LP_EN_SW ( BIT(3) ) +#define BIT_LDOWIFIPA_LP_EN_SW ( BIT(2) ) +#define BIT_LDOVDD28_LP_EN_SW ( BIT(1) ) +#define BIT_LDOVDD18_LP_EN_SW ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_AUD_SLP_CTRL */ +#define BIT_SLP_AUD_PMUR1_PD_EN ( BIT(14) ) +#define BIT_SLP_AUD_PA_SW_PD_EN ( BIT(13) ) +#define BIT_SLP_AUD_PA_LDO_PD_EN ( BIT(12) ) +#define BIT_SLP_AUD_PA_PD_EN ( BIT(11) ) +#define BIT_SLP_AUD_OVP_PD_PD_EN ( BIT(10) ) +#define BIT_SLP_AUD_OVP_LDO_PD_EN ( BIT(9) ) +#define BIT_SLP_AUD_LDOCG_PD_PD_EN ( BIT(8) ) +#define BIT_SLP_AUD_VB_PD_EN ( BIT(7) ) +#define BIT_SLP_AUD_VBO_PD_EN ( BIT(6) ) +#define BIT_SLP_AUD_HEADMICBIAS_PD_EN ( BIT(5) ) +#define BIT_SLP_AUD_HEADMIC_SLEEP_PD_EN ( BIT(4) ) +#define BIT_SLP_AUD_PLGPD_PD_EN ( BIT(3) ) +#define BIT_SLP_AUD_VB_NLEAK_PD ( BIT(2) ) +#define BITS_SLP_AUD_PMUR0_PD_EN(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL0 */ +#define BITS_SLP_DCDCCORE_VOL_DROP_CNT(_x_)( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_PWR_OFF_SEQ_EN ( BIT(2) ) +#define BIT_DCDC_CORE_SLP_OUT_STEP_EN ( BIT(1) ) +#define BIT_DCDC_CORE_SLP_IN_STEP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL1 */ +#define BITS_DCDC_CORE_CAL_DS_SW(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CTRL_DS_SW(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL2 */ +#define BITS_DCDC_CORE_CTRL_SLP_STEP3(_x_)( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_DCDC_CORE_CTRL_SLP_STEP2(_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CTRL_SLP_STEP1(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL3 */ +#define BITS_DCDC_CORE_CTRL_SLP_STEP5(_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CTRL_SLP_STEP4(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL4 */ +#define BITS_DCDC_CORE_CAL_SLP_STEP3(_x_)( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_DCDC_CORE_CAL_SLP_STEP2(_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CAL_SLP_STEP1(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL5 */ +#define BITS_DCDC_CORE_CAL_SLP_STEP5(_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CAL_SLP_STEP4(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SEL */ +#define BIT_LDO_GEN0_SW_SEL ( BIT(13) ) +#define BIT_LDO_GEN1_SW_SEL ( BIT(12) ) +#define BIT_LDO_RF0_SW_SEL ( BIT(11) ) +#define BIT_LDO_VDD18_SW_SEL ( BIT(10) ) +#define BIT_LDO_VDD28_SW_SEL ( BIT(9) ) +#define BIT_LDO_DCXO_SW_SEL ( BIT(8) ) +#define BIT_LDO_EMMCCORE_SW_SEL ( BIT(7) ) +#define BIT_LDO_VDD25_SW_SEL ( BIT(6) ) +#define BIT_DCDC_RF_SW_SEL ( BIT(5) ) +#define BIT_DCDC_GEN_SW_SEL ( BIT(4) ) +#define BIT_DCDC_MEM_SW_SEL ( BIT(3) ) +#define BIT_DCDC_ARM_SW_SEL ( BIT(2) ) +#define BIT_DCDC_CORE_SLP_SW_SEL ( BIT(1) ) +#define BIT_DCDC_CORE_NOR_SW_SEL ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN0 */ +#define BIT_LDO_XTL_EN ( BIT(15) ) +#define BIT_LDO_GEN0_EXT_XTL0_EN ( BIT(14) ) +#define BIT_LDO_GEN0_XTL1_EN ( BIT(13) ) +#define BIT_LDO_GEN0_XTL0_EN ( BIT(12) ) +#define BIT_LDO_GEN1_EXT_XTL0_EN ( BIT(11) ) +#define BIT_LDO_GEN1_XTL1_EN ( BIT(10) ) +#define BIT_LDO_GEN1_XTL0_EN ( BIT(9) ) +#define BIT_LDO_DCXO_EXT_XTL0_EN ( BIT(8) ) +#define BIT_LDO_DCXO_XTL1_EN ( BIT(7) ) +#define BIT_LDO_DCXO_XTL0_EN ( BIT(6) ) +#define BIT_LDO_VDD18_EXT_XTL0_EN ( BIT(5) ) +#define BIT_LDO_VDD18_XTL1_EN ( BIT(4) ) +#define BIT_LDO_VDD18_XTL0_EN ( BIT(3) ) +#define BIT_LDO_VDD28_EXT_XTL0_EN ( BIT(2) ) +#define BIT_LDO_VDD28_XTL1_EN ( BIT(1) ) +#define BIT_LDO_VDD28_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN1 */ +#define BIT_LDO_RF0_EXT_XTL0_EN ( BIT(14) ) +#define BIT_LDO_RF0_XTL1_EN ( BIT(13) ) +#define BIT_LDO_RF0_XTL0_EN ( BIT(12) ) +#define BIT_LDO_WIFIPA_EXT_XTL0_EN ( BIT(11) ) +#define BIT_LDO_WIFIPA_XTL1_EN ( BIT(10) ) +#define BIT_LDO_WIFIPA_XTL0_EN ( BIT(9) ) +#define BIT_LDO_SIM2_EXT_XTL0_EN ( BIT(8) ) +#define BIT_LDO_SIM2_XTL1_EN ( BIT(7) ) +#define BIT_LDO_SIM2_XTL0_EN ( BIT(6) ) +#define BIT_LDO_SIM1_EXT_XTL0_EN ( BIT(5) ) +#define BIT_LDO_SIM1_XTL1_EN ( BIT(4) ) +#define BIT_LDO_SIM1_XTL0_EN ( BIT(3) ) +#define BIT_LDO_SIM0_EXT_XTL0_EN ( BIT(2) ) +#define BIT_LDO_SIM0_XTL1_EN ( BIT(1) ) +#define BIT_LDO_SIM0_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN2 */ +#define BIT_LDO_VDD25_EXT_XTL0_EN ( BIT(11) ) +#define BIT_LDO_VDD25_XTL1_EN ( BIT(10) ) +#define BIT_LDO_VDD25_XTL0_EN ( BIT(9) ) +#define BIT_DCDC_RF_EXT_XTL0_EN ( BIT(8) ) +#define BIT_DCDC_RF_XTL1_EN ( BIT(7) ) +#define BIT_DCDC_RF_XTL0_EN ( BIT(6) ) +#define BIT_XO_EXT_XTL0_EN ( BIT(5) ) +#define BIT_XO_XTL1_EN ( BIT(4) ) +#define BIT_XO_XTL0_EN ( BIT(3) ) +#define BIT_BG_EXT_XTL0_EN ( BIT(2) ) +#define BIT_BG_XTL1_EN ( BIT(1) ) +#define BIT_BG_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN3 */ +#define BIT_DCDC_CON_EXT_XTL0_EN ( BIT(14) ) +#define BIT_DCDC_CON_XTL1_EN ( BIT(13) ) +#define BIT_DCDC_CON_XTL0_EN ( BIT(12) ) +#define BIT_DCDC_WPA_EXT_XTL0_EN ( BIT(11) ) +#define BIT_DCDC_WPA_XTL1_EN ( BIT(10) ) +#define BIT_DCDC_WPA_XTL0_EN ( BIT(9) ) +#define BIT_DCDC_MEM_EXT_XTL0_EN ( BIT(8) ) +#define BIT_DCDC_MEM_XTL1_EN ( BIT(7) ) +#define BIT_DCDC_MEM_XTL0_EN ( BIT(6) ) +#define BIT_DCDC_GEN_EXT_XTL0_EN ( BIT(5) ) +#define BIT_DCDC_GEN_XTL1_EN ( BIT(4) ) +#define BIT_DCDC_GEN_XTL0_EN ( BIT(3) ) +#define BIT_DCDC_CORE_EXT_XTL0_EN ( BIT(2) ) +#define BIT_DCDC_CORE_XTL1_EN ( BIT(1) ) +#define BIT_DCDC_CORE_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_32KLESS_CTRL0 */ +#define BIT_RC_MODE_WR_ACK_FLAG ( BIT(14) ) +#define BIT_XO_LOW_CUR_FLAG ( BIT(13) ) +#define BIT_XO_LOW_CUR_FRC_RTCSET ( BIT(12) ) +#define BIT_XO_LOW_CUR_FRC_RTCCLR ( BIT(11) ) +#define BIT_RC_MODE_WR_ACK_FLAG_CLR ( BIT(10) ) +#define BIT_XO_LOW_CUR_FLAG_CLR ( BIT(9) ) +#define BIT_XO_LOW_CUR_CNT_CLR ( BIT(8) ) +#define BIT_LDO_DCXO_LP_PD_RTCSET ( BIT(7) ) +#define BIT_LDO_DCXO_LP_PD_RTCCLR ( BIT(6) ) +#define BIT_SLP_XO_LOW_CUR_EN ( BIT(5) ) +#define BIT_XO_LOW_CUR_EN ( BIT(3) ) +#define BIT_EXT_32K_PD ( BIT(2) ) +#define BIT_RC_32K_SEL ( BIT(1) ) +#define BIT_RC_32K_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_32KLESS_CTRL1 */ +#define BITS_RC_MODE(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_32KLESS_CTRL2 */ +#define BITS_XO_LOW_CUR_CNT_LOW(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_32KLESS_CTRL3 */ +#define BITS_XO_LOW_CUR_CNT_HIGH(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_AUXAD_CTL */ +#define BIT_AUXAD_CURRENTSEN_EN ( BIT(6) ) +#define BIT_AUXAD_CURRENTSEL ( BIT(5) ) +#define BITS_AUXAD_CURRENT_IBS(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_XTL_WAIT_CTRL */ +#define BIT_SLP_XTLBUF_PD_EN ( BIT(9) ) +#define BIT_XTL_EN ( BIT(8) ) +#define BITS_XTL_WAIT(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_RGB_CTRL */ +#define BIT_RTC_PWM0_EN ( BIT(15) ) +#define BIT_PWM0_EN ( BIT(14) ) +#define BIT_IB_REX_EN ( BIT(12) ) +#define BIT_IB_TRIM_EM_SEL ( BIT(11) ) +#define BITS_RGB_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) ) +#define BIT_SLP_RGB_PD_EN ( BIT(2) ) +#define BIT_RGB_PD_HW_EN ( BIT(1) ) +#define BIT_RGB_PD_SW ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_WHTLED_CTRL */ +#define BITS_IB_TRIM(_x_) ( (_x_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_WHTLED_SERIES_EN ( BIT(8) ) +#define BIT_WHTLED_PD_SEL ( BIT(7) ) +#define BIT_WHTLED_BOOST_EN ( BIT(8) ) +#define BITS_WHTLED_V(_x_) ( (_x_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_WHTLED_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_KPLED_CTRL */ +#define BITS_KPLED_V(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_KPLED_PD ( BIT(11) ) +#define BIT_KPLED_PULLDOWN_EN ( BIT(10) ) +#define BIT_SLP_LDOKPLED_PD_EN ( BIT(9) ) +#define BIT_LDO_KPLED_PD ( BIT(8) ) +#define BITS_LDO_KPLED_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_VIBR_CTRL0 */ +#define BITS_CUR_DRV_CAL_SEL(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BIT_VIBR_PULLDOWN_EN ( BIT(11) ) +#define BIT_VIBR_PULLUP_EN ( BIT(10) ) +#define BIT_SLP_LDOVIBR_PD_EN ( BIT(9) ) +#define BIT_LDO_VIBR_PD ( BIT(8) ) +#define BITS_LDO_VIBR_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_AUDIO_CTRL0 */ +#define BIT_AUD_SLP_APP_RST_EN ( BIT(15) ) +#define BITS_CLK_AUD_HBD_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_CLK_AUD_LOOP_INV_EN ( BIT(4) ) +#define BIT_CLK_AUDIF_TX_INV_EN ( BIT(3) ) +#define BIT_CLK_AUDIF_RX_INV_EN ( BIT(2) ) +#define BIT_CLK_AUD_6P5M_TX_INV_EN ( BIT(1) ) +#define BIT_CLK_AUD_6P5M_RX_INV_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_AUDIO_CTRL1 */ +#define BIT_IMPD_ADC_SOFT_RST ( BIT(7) ) +#define BIT_HEAD_INSERT_EIC_EN ( BIT(6) ) +#define BIT_AUDIO_CHP_CLK_DIV_EN ( BIT(5) ) +#define BITS_AUDIO_CHP_CLK_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL0 */ +#define BIT_CHGLDO_DIS ( BIT(15) ) +#define BITS_CHGR_CV_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CHGR_END_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BIT_CHGR_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL1 */ +#define BITS_CHGR_CC_I(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_VBAT_OVP_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_VCHG_OVP_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL2 */ +#define BIT_CHGR_INT_EN ( BIT(15) ) +#define BIT_CHGR_DRV ( BIT(7) ) +#define BIT_CHGR_OSC ( BIT(6) ) +#define BITS_CHGR_DPM(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CHGR_ITERM(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BIT_CHGR_CC_EN ( BIT(1) ) +#define BIT_RECHG ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_DET_FGU_CTRL */ +#define BIT_FGUA_SOFT_RST ( BIT(13) ) +#define BIT_LDO_FGU_PD ( BIT(12) ) +#define BIT_SD_CHOP_CAP_EN ( BIT(8) ) +#define BITS_SD_CLK_P(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BIT_SD_DCOFFSET_EN ( BIT(5) ) +#define BIT_SD_CHOP_EN ( BIT(4) ) +#define BIT_DP_DM_AUX_EN ( BIT(1) ) +#define BIT_DP_DM_SW_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_STATUS */ +#define BIT_CHG_DET_DONE ( BIT(11) ) +#define BIT_DP_LOW ( BIT(10) ) +#define BIT_DCP_DET ( BIT(9) ) +#define BIT_CHG_DET ( BIT(8) ) +#define BIT_SDP_INT ( BIT(7) ) +#define BIT_DCP_INT ( BIT(6) ) +#define BIT_CDP_INT ( BIT(5) ) +#define BIT_CHGR_CV_STATUS ( BIT(4) ) +#define BIT_CHGR_ON ( BIT(3) ) +#define BIT_CHGR_INT ( BIT(2) ) +#define BIT_VBAT_OVI ( BIT(1) ) +#define BIT_VCHG_OVI ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_MIXED_CTRL0 */ +#define BIT_PTEST_PD_RTCSET ( BIT(15) ) +#define BIT_DCDC_V_CTRL_MODE ( BIT(14) ) +#define BIT_LDO_RAMP_EN ( BIT(13) ) +#define BIT_BG_LP_EN ( BIT(12) ) +#define BITS_VBAT_CRASH_V(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BIT_OVLO_EN ( BIT(9) ) +#define BITS_OVLO_CAL(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_OVLO_V(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_OVLO_T(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_MIXED_CTRL1 */ +#define BITS_XOSC32K_CTL(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_BATON_T(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BIT_BATDET_LDO_SEL ( BIT(9) ) +#define BIT_THM_CHIP_PD_FLAG ( BIT(8) ) +#define BIT_THM_CHIP_PD_FLAG_CLR ( BIT(7) ) +#define BITS_THM_CAL_SEL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)) ) +#define BIT_THM_AUTO_PD_EN ( BIT(4) ) +#define BIT_ALL_GPI_DEB ( BIT(3) ) +#define BIT_GPI_DEBUG_EN ( BIT(2) ) +#define BIT_ALL_INT_DEB ( BIT(1) ) +#define BIT_INT_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_SWRST_CTRL */ +#define BIT_POR_RTC_PD ( BIT(15) ) +#define BITS_POR_RTC_I(_x_) ( (_x_) << 13 & (BIT(13)|BIT(14)) ) +#define BIT_SW_RST_GEN1_PD_EN ( BIT(12) ) +#define BIT_SW_RST_GEN0_PD_EN ( BIT(11) ) +#define BIT_EXT_RSTN_PD_EN ( BIT(10) ) +#define BIT_PB_7S_RST_PD_EN ( BIT(9) ) +#define BIT_SW_RST_EMMCCORE_PD_EN ( BIT(8) ) +#define BIT_KEY2_7S_RST_EN ( BIT(7) ) +#define BIT_WDG_RST_PD_EN ( BIT(6) ) +#define BITS_SW_RST_PD_THRESHOLD(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register ANA_REG_GLB_POR_RST_MONITOR */ +#define BITS_POR_RST_MONITOR(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_WDG_RST_MONITOR */ +#define BITS_WDG_RST_MONITOR(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_POR_PIN_RST_MONITOR */ +#define BITS_POR_PIN_RST_MONITOR(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_POR_SRC_FLAG */ +#define BIT_POR_SW_FORCE_ON ( BIT(15) ) +#define BITS_POR_SRC_FLAG(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_POR_7S_CTRL */ +#define BIT_PBINT_7S_FLAG_CLR ( BIT(15) ) +#define BIT_EXT_RSTN_FLAG_CLR ( BIT(14) ) +#define BIT_CHGR_INT_FLAG_CLR ( BIT(13) ) +#define BIT_PBINT2_FLAG_CLR ( BIT(12) ) +#define BIT_PBINT_FLAG_CLR ( BIT(11) ) +#define BIT_PBINT_7S_RST_SWMODE ( BIT(8) ) +#define BITS_PBINT_7S_RST_THRESHOLD(_x_)( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_PBINT_7S_AUTO_ON_EN ( BIT(2) ) +#define BIT_PBINT_7S_RST_DISABLE ( BIT(1) ) +#define BIT_PBINT_7S_RST_MODE ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_HWRST_RTC */ +#define BITS_HWRST_RTC_REG_STS(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_HWRST_RTC_REG_SET(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_CHIP_ID_LOW */ +#define BITS_CHIP_ID_LOW(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_CHIP_ID_HIGH */ +#define BITS_CHIP_ID_HIGH(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_ARM_MF_REG */ +#define BITS_ARM_MF_REG(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_ARCH_EN */ +#define BIT_ARCH_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_MCU_WR_PROT_VALUE */ +#define BIT_MCU_WR_PROT ( BIT(15) ) +#define BITS_MCU_WR_PROT_VALUE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_PWR_WR_PROT_VALUE */ +#define BIT_PWR_WR_PROT ( BIT(15) ) +#define BITS_PWR_WR_PROT_VALUE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_SMPL_CTRL0 */ +#define BITS_SMPL_MODE(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_SMPL_CTRL1 */ +#define BIT_SMPL_PWR_ON_FLAG ( BIT(15) ) +#define BIT_SMPL_MODE_WR_ACK_FLAG ( BIT(14) ) +#define BIT_SMPL_PWR_ON_FLAG_CLR ( BIT(13) ) +#define BIT_SMPL_MODE_WR_ACK_FLAG_CLR ( BIT(12) ) +#define BIT_SMPL_PWR_ON_SET ( BIT(11) ) +#define BIT_SMPL_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_RTC_RST0 */ +#define BITS_RTC_CLK_FLAG_SET(_x_) ( (_x_) << 15 & (BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_RTC_RST1 */ +#define BITS_RTC_CLK_FLAG_CLR(_x_) ( (_x_) << 15 & (BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_RTC_RST2 */ +#define BITS_RTC_CLK_FLAG_RTC(_x_) ( (_x_) << 15 & (BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SHPT_PD1 */ +#define BIT_LDO_USB_SHPT_PD ( BIT(12) ) +#define BIT_LDO_DCXO_SHPT_PD ( BIT(11) ) +#define BIT_LDO_WIFIPA_SHPT_PD ( BIT(10) ) +#define BIT_LDO_VDD25_SHPT_PD ( BIT(9) ) +#define BIT_LDO_VDD28_SHPT_PD ( BIT(8) ) +#define BIT_LDO_SDIO_SHPT_PD ( BIT(7) ) +#define BIT_LDO_SDCORE_SHPT_PD ( BIT(6) ) +#define BIT_LDO_EMMCCORE_SHPT_PD ( BIT(5) ) +#define BIT_LDO_SIM2_SHPT_PD ( BIT(4) ) +#define BIT_LDO_SIM1_SHPT_PD ( BIT(3) ) +#define BIT_LDO_SIM0_SHPT_PD ( BIT(2) ) +#define BIT_LDO_CAMMOT_SHPT_PD ( BIT(1) ) +#define BIT_LDO_CAMA_SHPT_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SHPT_PD2 */ +#define BIT_LDO_RF0_SHPT_PD ( BIT(7) ) +#define BIT_LDO_GEN1_SHPT_PD ( BIT(6) ) +#define BIT_LDO_GEN0_SHPT_PD ( BIT(5) ) +#define BIT_LDO_CAMD_SHPT_PD ( BIT(4) ) +#define BIT_LDO_VDD18_SHPT_PD ( BIT(3) ) +#define BIT_LDO_CAMIO_SHPT_PD ( BIT(2) ) +#define BIT_LDO_KPLED_SHPT_PD ( BIT(1) ) +#define BIT_LDO_VIBR_SHPT_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_BATDET_CUR_CTRL */ +#define BIT_BATDET_CUR_EN ( BIT(4) ) +#define BITS_BATDET_CUR_I(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register ANA_REG_GLB_RTC_CLK_STOP */ +#define BIT_RTC_CLK_STOP_FLAG ( BIT(7) ) +#define BITS_RTC_CLK_STOP_THRESHOLD(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) + +/* bits definitions for register ANA_REG_GLB_VBAT_DROP_CNT */ +#define BITS_VBAT_DROP_CNT(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_DISCHRG */ +#define BITS_DCDC_ARM_DISCHRG(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_DCDC_CORE_DISCHRG(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_DCDC_MEM_DISCHRG(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_DCDC_GEN_DISCHRG(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_DCDC_RF_DISCHRG(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_DCDC_CON_DISCHRG(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DCDC_WPA_DISCHRG(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CORE_ADI */ +#define BITS_DCDC_CORE_CTL_SW_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CAL_SW_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_ARM_ADI */ +#define BITS_DCDC_ARM_CTL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_ARM_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_MEM_ADI */ +#define BITS_DCDC_MEM_CTRL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_MEM_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_GEN_ADI */ +#define BITS_DCDC_GEN_CTRL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_GEN_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_WPA_ADI */ +#define BITS_DCDC_WPA_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_WPA_DCM_ADI */ +#define BIT_DCDC_WPA_DCM_ADI ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CON_ADI */ +#define BITS_DCDC_CON_CTRL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CON_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_RF_ADI */ +#define BITS_DCDC_RF_CTRL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_RF_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* vars definitions for controller ANA_REGS_GLB */ + +#endif /* __ANA_REGS_GLB_H__ */ diff --git a/include/soc/sprd/chip_x30g/__regs_aon_apb.h b/include/soc/sprd/chip_x30g/__regs_aon_apb.h new file mode 100644 index 00000000..026d70e9 --- /dev/null +++ b/include/soc/sprd/chip_x30g/__regs_aon_apb.h @@ -0,0 +1,535 @@ +/*
+ * Copyright (C) 2014 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+#ifndef __SCI_GLB_REGS_H__
+#error "Don't include this file directly, Pls include sci_glb_regs.h"
+#endif
+
+
+#ifndef __H_REGS_AON_APB_HEADFILE_H__
+#define __H_REGS_AON_APB_HEADFILE_H__ __FILE__
+
+#define REGS_AON_APB
+
+/* registers definitions for AON_APB */
+#define REG_AON_APB_APB_EB0 SCI_ADDR(REGS_AON_APB_BASE, 0x0000)
+#define REG_AON_APB_APB_EB1 SCI_ADDR(REGS_AON_APB_BASE, 0x0004)
+#define REG_AON_APB_APB_RST0 SCI_ADDR(REGS_AON_APB_BASE, 0x0008)
+#define REG_AON_APB_APB_RST1 SCI_ADDR(REGS_AON_APB_BASE, 0x000C)
+#define REG_AON_APB_APB_RTC_EB SCI_ADDR(REGS_AON_APB_BASE, 0x0010)
+#define REG_AON_APB_REC_26MHZ_BUF_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0014)
+#define REG_AON_APB_SINDRV_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0018)
+#define REG_AON_APB_ADA_SEL_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x001C)
+#define REG_AON_APB_VBC_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0020)
+#define REG_AON_APB_PWR_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0024)
+#define REG_AON_APB_TS_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0028)
+#define REG_AON_APB_BOOT_MODE SCI_ADDR(REGS_AON_APB_BASE, 0x002C)
+#define REG_AON_APB_BB_BG_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0030)
+#define REG_AON_APB_CP_ARM_JTAG_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0034)
+#define REG_AON_APB_PLL_SOFT_CNT_DONE SCI_ADDR(REGS_AON_APB_BASE, 0x0038)
+#define REG_AON_APB_DCXO_LC_REG0 SCI_ADDR(REGS_AON_APB_BASE, 0x003C)
+#define REG_AON_APB_DCXO_LC_REG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0040)
+#define REG_AON_APB_MPLL_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3000)
+#define REG_AON_APB_DPLL_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3004)
+#define REG_AON_APB_TDPLL_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3008)
+#define REG_AON_APB_CPLL_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x300C)
+#define REG_AON_APB_WIFIPLL0_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3010)
+#define REG_AON_APB_WIFIPLL1_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3014)
+#define REG_AON_APB_WPLL_CFG0 SCI_ADDR(REGS_AON_APB_BASE, 0x3018)
+#define REG_AON_APB_WPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x301C)
+#define REG_AON_APB_AON_CGM_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3020)
+#define REG_AON_APB_CP0_ADDR_REMAP_CTRL0 SCI_ADDR(REGS_AON_APB_BASE, 0x3024)
+#define REG_AON_APB_CP0_ADDR_REMAP_CTRL1 SCI_ADDR(REGS_AON_APB_BASE, 0x3028)
+#define REG_AON_APB_CP1_ADDR_REMAP_CTRL0 SCI_ADDR(REGS_AON_APB_BASE, 0x302C)
+#define REG_AON_APB_CP1_ADDR_REMAP_CTRL1 SCI_ADDR(REGS_AON_APB_BASE, 0x3030)
+#define REG_AON_APB_CP2_ADDR_REMAP_CTRL0 SCI_ADDR(REGS_AON_APB_BASE, 0x3034)
+#define REG_AON_APB_CP2_ADDR_REMAP_CTRL1 SCI_ADDR(REGS_AON_APB_BASE, 0x3038)
+#define REG_AON_APB_IO_DLY_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x303C)
+#define REG_AON_APB_AP_WPROT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x3040)
+#define REG_AON_APB_CP0_WPROT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x3044)
+#define REG_AON_APB_CP1_WPROT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x3048)
+#define REG_AON_APB_CP2_WPROT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x304C)
+#define REG_AON_APB_PMU_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3050)
+#define REG_AON_APB_THM_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3054)
+#define REG_AON_APB_AP_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3058)
+#define REG_AON_APB_CA7_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x305C)
+#define REG_AON_APB_BOND_OPT0 SCI_ADDR(REGS_AON_APB_BASE, 0x3060)
+#define REG_AON_APB_BOND_OPT1 SCI_ADDR(REGS_AON_APB_BASE, 0x3064)
+#define REG_AON_APB_RES_REG0 SCI_ADDR(REGS_AON_APB_BASE, 0x3068)
+#define REG_AON_APB_RES_REG1 SCI_ADDR(REGS_AON_APB_BASE, 0x306C)
+#define REG_AON_APB_MPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x3070)
+#define REG_AON_APB_DPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x3074)
+#define REG_AON_APB_TDPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x3078)
+#define REG_AON_APB_CPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x307C)
+#define REG_AON_APB_WIFIPLL1_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x3080)
+#define REG_AON_APB_WIFIPLL2_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x3084)
+#define REG_AON_APB_AON_QOS_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3088)
+#define REG_AON_APB_BB_LDO_CAL_START SCI_ADDR(REGS_AON_APB_BASE, 0x308C)
+#define REG_AON_APB_AON_CHIP_ID SCI_ADDR(REGS_AON_APB_BASE, 0x00FC)
+
+
+
+/* bits definitions for register REG_AON_APB_APB_EB0 */
+#define BIT_I2C_EB ( BIT(31) )
+#define BIT_CA7_DAP_EB ( BIT(30) )
+#define BIT_CA7_TS1_EB ( BIT(29) )
+#define BIT_CA7_TS0_EB ( BIT(28) )
+#define BIT_GPU_EB ( BIT(27) )
+#define BIT_AON_CKG_EB ( BIT(26) )
+#define BIT_MM_EB ( BIT(25) )
+#define BIT_AP_WDG_EB ( BIT(24) )
+#define BIT_MSPI_EB ( BIT(23) )
+#define BIT_SPLK_EB ( BIT(22) )
+#define BIT_IPI_EB ( BIT(21) )
+#define BIT_PIN_EB ( BIT(20) )
+#define BIT_VBC_EB ( BIT(19) )
+#define BIT_AUD_EB ( BIT(18) )
+#define BIT_AUDIF_EB ( BIT(17) )
+#define BIT_ADI_EB ( BIT(16) )
+#define BIT_INTC_EB ( BIT(15) )
+#define BIT_EIC_EB ( BIT(14) )
+#define BIT_EFUSE_EB ( BIT(13) )
+#define BIT_AP_TMR0_EB ( BIT(12) )
+#define BIT_AON_TMR_EB ( BIT(11) )
+#define BIT_AP_SYST_EB ( BIT(10) )
+#define BIT_AON_SYST_EB ( BIT(9) )
+#define BIT_KPD_EB ( BIT(8) )
+#define BIT_PWM3_EB ( BIT(7) )
+#define BIT_PWM2_EB ( BIT(6) )
+#define BIT_PWM1_EB ( BIT(5) )
+#define BIT_PWM0_EB ( BIT(4) )
+#define BIT_GPIO_EB ( BIT(3) )
+#define BIT_TPC_EB ( BIT(2) )
+#define BIT_FM_EB ( BIT(1) )
+#define BIT_ADC_EB ( BIT(0) )
+
+/* bits definitions for register REG_AON_APB_APB_EB1 */
+#define BIT_GSP_EMC_EB ( BIT(13) )
+#define BIT_ZIP_EMC_EB ( BIT(12) )
+#define BIT_DISP_EMC_EB ( BIT(11) )
+#define BIT_AP_TMR2_EB ( BIT(10) )
+#define BIT_AP_TMR1_EB ( BIT(9) )
+#define BIT_CA7_WDG_EB ( BIT(8) )
+#define BIT_AVS1_EB ( BIT(7) )
+#define BIT_AVS0_EB ( BIT(6) )
+#define BIT_PROBE_EB ( BIT(5) )
+#define BIT_AUX2_EB ( BIT(4) )
+#define BIT_AUX1_EB ( BIT(3) )
+#define BIT_AUX0_EB ( BIT(2) )
+#define BIT_THM_EB ( BIT(1) )
+#define BIT_PMU_EB ( BIT(0) )
+
+/* bits definitions for register REG_AON_APB_APB_RST0 */
+#define BIT_I2C_SOFT_RST ( BIT(30) )
+#define BIT_CA7_TS1_SOFT_RST ( BIT(29) )
+#define BIT_CA7_TS0_SOFT_RST ( BIT(28) )
+#define BIT_DAP_MTX_SOFT_RST ( BIT(27) )
+#define BIT_MSPI1_SOFT_RST ( BIT(26) )
+#define BIT_MSPI0_SOFT_RST ( BIT(25) )
+#define BIT_SPLK_SOFT_RST ( BIT(24) )
+#define BIT_IPI_SOFT_RST ( BIT(23) )
+#define BIT_AON_CKG_SOFT_RST ( BIT(22) )
+#define BIT_PIN_SOFT_RST ( BIT(21) )
+#define BIT_VBC_SOFT_RST ( BIT(20) )
+#define BIT_AUD_SOFT_RST ( BIT(19) )
+#define BIT_AUDIF_SOFT_RST ( BIT(18) )
+#define BIT_ADI_SOFT_RST ( BIT(17) )
+#define BIT_INTC_SOFT_RST ( BIT(16) )
+#define BIT_EIC_SOFT_RST ( BIT(15) )
+#define BIT_EFUSE_SOFT_RST ( BIT(14) )
+#define BIT_AP_WDG_SOFT_RST ( BIT(13) )
+#define BIT_AP_TMR0_SOFT_RST ( BIT(12) )
+#define BIT_AON_TMR_SOFT_RST ( BIT(11) )
+#define BIT_AP_SYST_SOFT_RST ( BIT(10) )
+#define BIT_AON_SYST_SOFT_RST ( BIT(9) )
+#define BIT_KPD_SOFT_RST ( BIT(8) )
+#define BIT_PWM3_SOFT_RST ( BIT(7) )
+#define BIT_PWM2_SOFT_RST ( BIT(6) )
+#define BIT_PWM1_SOFT_RST ( BIT(5) )
+#define BIT_PWM0_SOFT_RST ( BIT(4) )
+#define BIT_GPIO_SOFT_RST ( BIT(3) )
+#define BIT_TPC_SOFT_RST ( BIT(2) )
+#define BIT_FM_SOFT_RST ( BIT(1) )
+#define BIT_ADC_SOFT_RST ( BIT(0) )
+
+/* bits definitions for register REG_AON_APB_APB_RST1 */
+#define BIT_BB_CAL_SOFT_RST ( BIT(11) )
+#define BIT_DCXO_LC_SOFT_RST ( BIT(10) )
+#define BIT_AP_TMR2_SOFT_RST ( BIT(9) )
+#define BIT_AP_TMR1_SOFT_RST ( BIT(8) )
+#define BIT_CA7_WDG_SOFT_RST ( BIT(7) )
+#define BIT_AVS1_SOFT_RST ( BIT(6) )
+#define BIT_AVS0_SOFT_RST ( BIT(5) )
+#define BIT_DMC_PHY_SOFT_RST ( BIT(4) )
+#define BIT_GPU_THMA_SOFT_RST ( BIT(3) )
+#define BIT_ARM_THMA_SOFT_RST ( BIT(2) )
+#define BIT_THM_SOFT_RST ( BIT(1) )
+#define BIT_PMU_SOFT_RST ( BIT(0) )
+
+/* bits definitions for register REG_AON_APB_APB_RTC_EB */
+#define BIT_BB_CAL_RTC_EB ( BIT(18) )
+#define BIT_DCXO_LC_RTC_EB ( BIT(17) )
+#define BIT_AP_TMR2_RTC_EB ( BIT(16) )
+#define BIT_AP_TMR1_RTC_EB ( BIT(15) )
+#define BIT_GPU_THMA_RTC_AUTO_EN ( BIT(14) )
+#define BIT_ARM_THMA_RTC_AUTO_EN ( BIT(13) )
+#define BIT_GPU_THMA_RTC_EB ( BIT(12) )
+#define BIT_ARM_THMA_RTC_EB ( BIT(11) )
+#define BIT_THM_RTC_EB ( BIT(10) )
+#define BIT_CA7_WDG_RTC_EB ( BIT(9) )
+#define BIT_AP_WDG_RTC_EB ( BIT(8) )
+#define BIT_EIC_RTCDV5_EB ( BIT(7) )
+#define BIT_EIC_RTC_EB ( BIT(6) )
+#define BIT_AP_TMR0_RTC_EB ( BIT(5) )
+#define BIT_AON_TMR_RTC_EB ( BIT(4) )
+#define BIT_AP_SYST_RTC_EB ( BIT(3) )
+#define BIT_AON_SYST_RTC_EB ( BIT(2) )
+#define BIT_KPD_RTC_EB ( BIT(1) )
+#define BIT_ARCH_RTC_EB ( BIT(0) )
+
+/* bits definitions for register REG_AON_APB_REC_26MHZ_BUF_CFG */
+#define BITS_PLL_PROBE_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
+#define BIT_REC_26MHZ_1_CUR_SEL ( BIT(4) )
+#define BIT_REC_26MHZ_0_CUR_SEL ( BIT(0) )
+
+/* bits definitions for register REG_AON_APB_SINDRV_CTRL */
+#define BITS_SINDRV_LVL(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)) )
+#define BIT_SINDRV_CLIP_MODE ( BIT(2) )
+#define BIT_SINDRV_ENA_SQUARE ( BIT(1) )
+#define BIT_SINDRV_ENA ( BIT(0) )
+
+/* bits definitions for register REG_AON_APB_ADA_SEL_CTRL */
+#define BIT_TW_MODE_SEL ( BIT(3) )
+#define BIT_WGADC_DIV_EN ( BIT(2) )
+#define BIT_AFCDAC_SYS_SEL ( BIT(1) )
+#define BIT_APCDAC_SYS_SEL ( BIT(0) )
+
+/* bits definitions for register REG_AON_APB_VBC_CTRL */
+#define BIT_AUDIF_CKG_AUTO_EN ( BIT(20) )
+#define BITS_AUD_INT_SYS_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
+#define BITS_VBC_AFIFO_INT_SYS_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_VBC_AD23_INT_SYS_SEL(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) )
+#define BITS_VBC_AD01_INT_SYS_SEL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) )
+#define BITS_VBC_DA01_INT_SYS_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
+#define BITS_VBC_AD23_DMA_SYS_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_VBC_AD01_DMA_SYS_SEL(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) )
+#define BITS_VBC_DA01_DMA_SYS_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BIT_VBC_INT_CP0_ARM_SEL ( BIT(3) )
+#define BIT_VBC_INT_CP1_ARM_SEL ( BIT(2) )
+#define BIT_VBC_DMA_CP0_ARM_SEL ( BIT(1) )
+#define BIT_VBC_DMA_CP1_ARM_SEL ( BIT(0) )
+
+/* bits definitions for register REG_AON_APB_PWR_CTRL */
+#define BIT_DSI_PHY_PD ( BIT(12) )
+#define BIT_CSI1_PHY_PD ( BIT(11) )
+#define BIT_CSI0_PHY_PD ( BIT(10) )
+#define BIT_CA7_TS1_STOP ( BIT(9) )
+#define BIT_CA7_TS0_STOP ( BIT(8) )
+#define BIT_EFUSE1_PWR_ON ( BIT(4) )
+#define BIT_EFUSE0_PWR_ON ( BIT(3) )
+#define BIT_FORCE_DSI_PHY_SHUTDOWNZ ( BIT(2) )
+#define BIT_FORCE_CSI_PHY_SHUTDOWNZ ( BIT(1) )
+#define BIT_USB_PHY_PD ( BIT(0) )
+
+/* bits definitions for register REG_AON_APB_TS_CFG */
+#define BIT_CSYSACK_TS_LP_2 ( BIT(13) )
+#define BIT_CSYSREQ_TS_LP_2 ( BIT(12) )
+#define BIT_CSYSACK_TS_LP_1 ( BIT(11) )
+#define BIT_CSYSREQ_TS_LP_1 ( BIT(10) )
+#define BIT_CSYSACK_TS_LP_0 ( BIT(9) )
+#define BIT_CSYSREQ_TS_LP_0 ( BIT(8) )
+#define BIT_EVENTACK_RESTARTREQ_TS01 ( BIT(4) )
+#define BIT_EVENT_RESTARTREQ_TS01 ( BIT(1) )
+#define BIT_EVENT_HALTREQ_TS01 ( BIT(0) )
+
+/* bits definitions for register REG_AON_APB_BOOT_MODE */
+#define BIT_WPLL_OVR_FREQ_SEL ( BIT(12) )
+#define BIT_PTEST_FUNC_ATSPEED_SEL ( BIT(8) )
+#define BIT_PTEST_FUNC_MODE ( BIT(7) )
+#define BIT_USB_DLOAD_EN ( BIT(4) )
+#define BIT_ARM_BOOT_MD3 ( BIT(3) )
+#define BIT_ARM_BOOT_MD2 ( BIT(2) )
+#define BIT_ARM_BOOT_MD1 ( BIT(1) )
+#define BIT_ARM_BOOT_MD0 ( BIT(0) )
+
+/* bits definitions for register REG_AON_APB_BB_BG_CTRL */
+#define BIT_BB_CON_BG ( BIT(22) )
+#define BITS_BB_BG_RSV(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)) )
+#define BITS_BB_LDO_V(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BIT_BB_BG_RBIAS_EN ( BIT(15) )
+#define BIT_BB_BG_IEXT_IB_EN ( BIT(14) )
+#define BITS_BB_LDO_REFCTRL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) )
+#define BIT_BB_LDO_AUTO_PD_EN ( BIT(11) )
+#define BIT_BB_LDO_SLP_PD_EN ( BIT(10) )
+#define BIT_BB_LDO_FORCE_ON ( BIT(9) )
+#define BIT_BB_LDO_FORCE_PD ( BIT(8) )
+#define BIT_BB_BG_AUTO_PD_EN ( BIT(3) )
+#define BIT_BB_BG_SLP_PD_EN ( BIT(2) )
+#define BIT_BB_BG_FORCE_ON ( BIT(1) )
+#define BIT_BB_BG_FORCE_PD ( BIT(0) )
+
+/* bits definitions for register REG_AON_APB_CP_ARM_JTAG_CTRL */
+#define BITS_CP_ARM_JTAG_PIN_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
+
+/* bits definitions for register REG_AON_APB_PLL_SOFT_CNT_DONE */
+#define BIT_XTLBUF1_SOFT_CNT_DONE ( BIT(9) )
+#define BIT_XTLBUF0_SOFT_CNT_DONE ( BIT(8) )
+#define BIT_WIFIPLL2_SOFT_CNT_DONE ( BIT(6) )
+#define BIT_WIFIPLL1_SOFT_CNT_DONE ( BIT(5) )
+#define BIT_CPLL_SOFT_CNT_DONE ( BIT(4) )
+#define BIT_WPLL_SOFT_CNT_DONE ( BIT(3) )
+#define BIT_TDPLL_SOFT_CNT_DONE ( BIT(2) )
+#define BIT_DPLL_SOFT_CNT_DONE ( BIT(1) )
+#define BIT_MPLL_SOFT_CNT_DONE ( BIT(0) )
+
+/* bits definitions for register REG_AON_APB_DCXO_LC_REG0 */
+#define BIT_DCXO_LC_FLAG ( BIT(8) )
+#define BIT_DCXO_LC_FLAG_CLR ( BIT(1) )
+#define BIT_DCXO_LC_CNT_CLR ( BIT(0) )
+
+/* bits definitions for register REG_AON_APB_DCXO_LC_REG1 */
+#define BITS_DCXO_LC_CNT(_X_) (_X_)
+
+/* bits definitions for register REG_AON_APB_MPLL_CFG */
+#define BITS_MPLL_REFIN(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
+#define BITS_MPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
+#define BITS_MPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_MPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
+
+/* bits definitions for register REG_AON_APB_DPLL_CFG */
+#define BITS_DPLL_REFIN(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
+#define BITS_DPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
+#define BITS_DPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_DPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
+
+/* bits definitions for register REG_AON_APB_TDPLL_CFG */
+#define BITS_TDPLL_REFIN(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
+#define BITS_TDPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
+#define BITS_TDPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_TDPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
+
+/* bits definitions for register REG_AON_APB_CPLL_CFG */
+#define BITS_CPLL_REFIN(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
+#define BITS_CPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
+#define BITS_CPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_CPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
+
+/* bits definitions for register REG_AON_APB_WIFIPLL0_CFG */
+#define BITS_WIFIPLL1_REFIN(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
+#define BITS_WIFIPLL1_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
+#define BITS_WIFIPLL1_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_WIFIPLL1_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
+
+/* bits definitions for register REG_AON_APB_WIFIPLL1_CFG */
+#define BITS_WIFIPLL2_REFIN(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
+#define BITS_WIFIPLL2_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
+#define BITS_WIFIPLL2_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_WIFIPLL2_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
+
+/* bits definitions for register REG_AON_APB_WPLL_CFG0 */
+#define BITS_WPLL_REFIN(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
+#define BITS_WPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
+#define BITS_WPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_WPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
+
+/* bits definitions for register REG_AON_APB_WPLL_CFG1 */
+#define BITS_WPLL_KINT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_WPLL_DIV_S ( BIT(10) )
+#define BITS_WPLL_RSV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BIT_WPLL_MOD_EN ( BIT(7) )
+#define BIT_WPLL_SDM_EN ( BIT(6) )
+#define BITS_WPLL_NINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+
+/* bits definitions for register REG_AON_APB_AON_CGM_CFG */
+#define BITS_PROBE_CKG_DIV(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_AUX2_CKG_DIV(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_AUX1_CKG_DIV(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_AUX0_CKG_DIV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_PROBE_CKG_SEL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_AUX2_CKG_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_AUX1_CKG_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_AUX0_CKG_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_AON_APB_CP0_ADDR_REMAP_CTRL0 */
+#define BITS_CP0_ADDR_B7_REMAP(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_CP0_ADDR_B6_REMAP(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_CP0_ADDR_B5_REMAP(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_CP0_ADDR_B4_REMAP(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_CP0_ADDR_B3_REMAP(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_CP0_ADDR_B2_REMAP(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_CP0_ADDR_B1_REMAP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_CP0_ADDR_B0_REMAP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_AON_APB_CP0_ADDR_REMAP_CTRL1 */
+#define BIT_CP0_PUB_IRAM_B8_PROT_EN ( BIT(12) )
+#define BIT_CP0_PUB_IRAM_B7_PROT_EN ( BIT(11) )
+#define BIT_CP0_PUB_IRAM_B6_PROT_EN ( BIT(10) )
+#define BIT_CP0_PUB_IRAM_B5_PROT_EN ( BIT(9) )
+#define BIT_CP0_PUB_IRAM_B4_PROT_EN ( BIT(8) )
+#define BIT_CP0_PUB_IRAM_B3_PROT_EN ( BIT(7) )
+#define BIT_CP0_PUB_IRAM_B2_PROT_EN ( BIT(6) )
+#define BIT_CP0_PUB_IRAM_B1_PROT_EN ( BIT(5) )
+#define BIT_CP0_PUB_IRAM_B0_PROT_EN ( BIT(4) )
+#define BITS_CP0_ADDR_B8_REMAP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_AON_APB_CP1_ADDR_REMAP_CTRL0 */
+#define BITS_CP1_ADDR_B7_REMAP(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_CP1_ADDR_B6_REMAP(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_CP1_ADDR_B5_REMAP(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_CP1_ADDR_B4_REMAP(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_CP1_ADDR_B3_REMAP(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_CP1_ADDR_B2_REMAP(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_CP1_ADDR_B1_REMAP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_CP1_ADDR_B0_REMAP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_AON_APB_CP1_ADDR_REMAP_CTRL1 */
+#define BIT_CP1_PUB_IRAM_B8_PROT_EN ( BIT(12) )
+#define BIT_CP1_PUB_IRAM_B7_PROT_EN ( BIT(11) )
+#define BIT_CP1_PUB_IRAM_B6_PROT_EN ( BIT(10) )
+#define BIT_CP1_PUB_IRAM_B5_PROT_EN ( BIT(9) )
+#define BIT_CP1_PUB_IRAM_B4_PROT_EN ( BIT(8) )
+#define BIT_CP1_PUB_IRAM_B3_PROT_EN ( BIT(7) )
+#define BIT_CP1_PUB_IRAM_B2_PROT_EN ( BIT(6) )
+#define BIT_CP1_PUB_IRAM_B1_PROT_EN ( BIT(5) )
+#define BIT_CP1_PUB_IRAM_B0_PROT_EN ( BIT(4) )
+#define BITS_CP1_ADDR_B8_REMAP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_AON_APB_CP2_ADDR_REMAP_CTRL0 */
+#define BITS_CP2_ADDR_B7_REMAP(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_CP2_ADDR_B6_REMAP(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_CP2_ADDR_B5_REMAP(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_CP2_ADDR_B4_REMAP(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_CP2_ADDR_B3_REMAP(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_CP2_ADDR_B2_REMAP(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_CP2_ADDR_B1_REMAP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_CP2_ADDR_B0_REMAP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_AON_APB_CP2_ADDR_REMAP_CTRL1 */
+#define BIT_CP2_PUB_IRAM_B8_PROT_EN ( BIT(12) )
+#define BIT_CP2_PUB_IRAM_B7_PROT_EN ( BIT(11) )
+#define BIT_CP2_PUB_IRAM_B6_PROT_EN ( BIT(10) )
+#define BIT_CP2_PUB_IRAM_B5_PROT_EN ( BIT(9) )
+#define BIT_CP2_PUB_IRAM_B4_PROT_EN ( BIT(8) )
+#define BIT_CP2_PUB_IRAM_B3_PROT_EN ( BIT(7) )
+#define BIT_CP2_PUB_IRAM_B2_PROT_EN ( BIT(6) )
+#define BIT_CP2_PUB_IRAM_B1_PROT_EN ( BIT(5) )
+#define BIT_CP2_PUB_IRAM_B0_PROT_EN ( BIT(4) )
+#define BITS_CP2_ADDR_B8_REMAP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_AON_APB_IO_DLY_CTRL */
+#define BITS_CLK_CCIR_DLY_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_CLK_CP1DSP_DLY_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_CLK_CP0DSP_DLY_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_AON_APB_AP_WPROT_EN */
+#define BITS_AP_AWADDR_WPROT_EN(_X_) (_X_)
+
+/* bits definitions for register REG_AON_APB_CP0_WPROT_EN */
+#define BITS_CP0_AWADDR_WPROT_EN(_X_) (_X_)
+
+/* bits definitions for register REG_AON_APB_CP1_WPROT_EN */
+#define BITS_CP1_AWADDR_WPROT_EN(_X_) (_X_)
+
+/* bits definitions for register REG_AON_APB_CP2_WPROT_EN */
+#define BITS_CP2_AWADDR_WPROT_EN(_X_) (_X_)
+
+/* bits definitions for register REG_AON_APB_PMU_RST_MONITOR */
+#define BITS_PMU_RST_MONITOR(_X_) (_X_)
+
+/* bits definitions for register REG_AON_APB_THM_RST_MONITOR */
+#define BITS_THM_RST_MONITOR(_X_) (_X_)
+
+/* bits definitions for register REG_AON_APB_AP_RST_MONITOR */
+#define BITS_AP_RST_MONITOR(_X_) (_X_)
+
+/* bits definitions for register REG_AON_APB_CA7_RST_MONITOR */
+#define BITS_CA7_RST_MONITOR(_X_) (_X_)
+
+/* bits definitions for register REG_AON_APB_BOND_OPT0 */
+#define BITS_BOND_OPTION0(_X_) (_X_)
+
+/* bits definitions for register REG_AON_APB_BOND_OPT1 */
+#define BITS_BOND_OPTION1(_X_) (_X_)
+
+/* bits definitions for register REG_AON_APB_RES_REG0 */
+#define BITS_RES_REG0(_X_) (_X_)
+
+/* bits definitions for register REG_AON_APB_RES_REG1 */
+#define BITS_RES_REG1(_X_) (_X_)
+
+/* bits definitions for register REG_AON_APB_MPLL_CFG1 */
+#define BITS_MPLL_KINT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_MPLL_DIV_S ( BIT(10) )
+#define BITS_MPLL_RSV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BIT_MPLL_MOD_EN ( BIT(7) )
+#define BIT_MPLL_SDM_EN ( BIT(6) )
+#define BITS_MPLL_NINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+
+/* bits definitions for register REG_AON_APB_DPLL_CFG1 */
+#define BITS_DPLL_KINT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_DPLL_DIV_S ( BIT(10) )
+#define BITS_DPLL_RSV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BIT_DPLL_MOD_EN ( BIT(7) )
+#define BIT_DPLL_SDM_EN ( BIT(6) )
+#define BITS_DPLL_NINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+
+/* bits definitions for register REG_AON_APB_TDPLL_CFG1 */
+#define BITS_TDPLL_KINT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_TDPLL_DIV_S ( BIT(10) )
+#define BITS_TDPLL_RSV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BIT_TDPLL_MOD_EN ( BIT(7) )
+#define BIT_TDPLL_SDM_EN ( BIT(6) )
+#define BITS_TDPLL_NINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+
+/* bits definitions for register REG_AON_APB_CPLL_CFG1 */
+#define BITS_CPLL_KINT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_CPLL_DIV_S ( BIT(10) )
+#define BITS_CPLL_RSV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BIT_CPLL_MOD_EN ( BIT(7) )
+#define BIT_CPLL_SDM_EN ( BIT(6) )
+#define BITS_CPLL_NINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+
+/* bits definitions for register REG_AON_APB_WIFIPLL1_CFG1 */
+#define BITS_WIFIPLL1_KINT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_WIFIPLL1_DIV_S ( BIT(10) )
+#define BITS_WIFIPLL1_RSV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BIT_WIFIPLL1_MOD_EN ( BIT(7) )
+#define BIT_WIFIPLL1_SDM_EN ( BIT(6) )
+#define BITS_WIFIPLL1_NINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+
+/* bits definitions for register REG_AON_APB_WIFIPLL2_CFG1 */
+#define BITS_WIFIPLL2_KINT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_WIFIPLL2_DIV_S ( BIT(10) )
+#define BITS_WIFIPLL2_RSV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BIT_WIFIPLL2_MOD_EN ( BIT(7) )
+#define BIT_WIFIPLL2_SDM_EN ( BIT(6) )
+#define BITS_WIFIPLL2_NINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+
+/* bits definitions for register REG_AON_APB_AON_QOS_CFG */
+#define BITS_QOS_R_GPU(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_QOS_W_GPU(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_QOS_R_GSP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_QOS_W_GSP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_AON_APB_BB_LDO_CAL_START */
+#define BIT_BB_LDO_CAL_START ( BIT(0) )
+
+/* bits definitions for register REG_AON_APB_AON_CHIP_ID */
+#define BITS_AON_CHIP_ID(_X_) (_X_)
+
+#endif
diff --git a/include/soc/sprd/chip_x30g/__regs_aon_apb_tshark2.h b/include/soc/sprd/chip_x30g/__regs_aon_apb_tshark2.h new file mode 100644 index 00000000..4cd98124 --- /dev/null +++ b/include/soc/sprd/chip_x30g/__regs_aon_apb_tshark2.h @@ -0,0 +1,562 @@ +/* the head file modifier: ang 2015-01-21 14:32:21*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_AON_APB_HEADFILE_H__ +#define __H_REGS_AON_APB_HEADFILE_H__ __FILE__ + +#define REGS_AON_APB + +/* registers definitions for AON_APB */ +#define REG_AON_APB_APB_EB0 SCI_ADDR(REGS_AON_APB_BASE, 0x0000)/*AHB_EB0*/ +#define REG_AON_APB_APB_EB1 SCI_ADDR(REGS_AON_APB_BASE, 0x0004)/*AHB_EB1*/ +#define REG_AON_APB_APB_RST0 SCI_ADDR(REGS_AON_APB_BASE, 0x0008)/*AHB_RST0*/ +#define REG_AON_APB_APB_RST1 SCI_ADDR(REGS_AON_APB_BASE, 0x000C)/*AHB_RST1*/ +#define REG_AON_APB_APB_RTC_EB SCI_ADDR(REGS_AON_APB_BASE, 0x0010)/*APB_RTC_EB*/ +#define REG_AON_APB_REC_26MHZ_BUF_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0014)/*REC_26MHZ_BUF_CFG*/ +#define REG_AON_APB_SINDRV_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0018)/*SINDRV_CTRL*/ +#define REG_AON_APB_ADA_SEL_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x001C)/*ADA_SEL_CTRL*/ +#define REG_AON_APB_VBC_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0020)/*VBC_CTRL*/ +#define REG_AON_APB_PWR_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0024)/*PWR_CTRL*/ +#define REG_AON_APB_TS_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0028)/*TS_CFG*/ +#define REG_AON_APB_BOOT_MODE SCI_ADDR(REGS_AON_APB_BASE, 0x002C)/*BOOT_MODE*/ +#define REG_AON_APB_BB_BG_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0030)/*BB_BG_CTRL*/ +#define REG_AON_APB_CP_ARM_JTAG_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0034)/*CP_ARM_JTAG_CTRL*/ +#define REG_AON_APB_PLL_SOFT_CNT_DONE SCI_ADDR(REGS_AON_APB_BASE, 0x0038)/*PLL_SOFT_CNT_DONE*/ +#define REG_AON_APB_DCXO_LC_REG0 SCI_ADDR(REGS_AON_APB_BASE, 0x003C)/*DCXO_LC_REG0*/ +#define REG_AON_APB_DCXO_LC_REG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0040)/*DCXO_LC_REG1*/ +#define REG_AON_APB_MPLL_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3000)/*MPLL_CFG*/ +#define REG_AON_APB_DPLL_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3004)/*DPLL_CFG*/ +#define REG_AON_APB_TDPLL_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3008)/*TDPLL_CFG*/ +#define REG_AON_APB_CPLL_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x300C)/*CPLL_CFG*/ +#define REG_AON_APB_WIFIPLL0_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3010)/*WIFIPLL0_CFG*/ +#define REG_AON_APB_WIFIPLL1_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3014)/*WIFIPLL1_CFG*/ +#define REG_AON_APB_WPLL_CFG0 SCI_ADDR(REGS_AON_APB_BASE, 0x3018)/*WPLL_CFG0*/ +#define REG_AON_APB_WPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x301C)/*WPLL_CFG1*/ +#define REG_AON_APB_AON_CGM_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3020)/*AON_CGM_CFG*/ +#define REG_AON_APB_CP0_ADDR_REMAP_CTRL0 SCI_ADDR(REGS_AON_APB_BASE, 0x3024)/*CP0_ADDR_REMAP_CTRL0*/ +#define REG_AON_APB_CP0_ADDR_REMAP_CTRL1 SCI_ADDR(REGS_AON_APB_BASE, 0x3028)/*CP0_ADDR_REMAP_CTRL1*/ +#define REG_AON_APB_CP1_ADDR_REMAP_CTRL0 SCI_ADDR(REGS_AON_APB_BASE, 0x302C)/*CP1_ADDR_REMAP_CTRL0*/ +#define REG_AON_APB_CP1_ADDR_REMAP_CTRL1 SCI_ADDR(REGS_AON_APB_BASE, 0x3030)/*CP1_ADDR_REMAP_CTRL1*/ +#define REG_AON_APB_CP2_ADDR_REMAP_CTRL0 SCI_ADDR(REGS_AON_APB_BASE, 0x3034)/*CP2_ADDR_REMAP_CTRL0*/ +#define REG_AON_APB_CP2_ADDR_REMAP_CTRL1 SCI_ADDR(REGS_AON_APB_BASE, 0x3038)/*CP2_ADDR_REMAP_CTRL1*/ +#define REG_AON_APB_IO_DLY_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x303C)/*IO_DLY_CTRL*/ +#define REG_AON_APB_AP_WPROT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x3040)/*AP_WPROT_EN*/ +#define REG_AON_APB_CP0_WPROT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x3044)/*CP0_WPROT_EN*/ +#define REG_AON_APB_CP1_WPROT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x3048)/*CP1_WPROT_EN*/ +#define REG_AON_APB_CP2_WPROT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x304C)/*CP2_WPROT_EN*/ +#define REG_AON_APB_PMU_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3050)/*PMU_RST_MONITOR*/ +#define REG_AON_APB_THM_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3054)/*THM_RST_MONITOR*/ +#define REG_AON_APB_AP_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3058)/*AP_RST_MONITOR*/ +#define REG_AON_APB_CA7_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x305C)/*CA7_RST_MONITOR*/ +#define REG_AON_APB_BOND_OPT0 SCI_ADDR(REGS_AON_APB_BASE, 0x3060)/*BOND_OPT0*/ +#define REG_AON_APB_BOND_OPT1 SCI_ADDR(REGS_AON_APB_BASE, 0x3064)/*BOND_OPT1*/ +#define REG_AON_APB_RES_REG0 SCI_ADDR(REGS_AON_APB_BASE, 0x3068)/*RES_REG0*/ +#define REG_AON_APB_RES_REG1 SCI_ADDR(REGS_AON_APB_BASE, 0x306C)/*RES_REG1*/ +#define REG_AON_APB_MPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x3070)/*MPLL_CFG1*/ +#define REG_AON_APB_DPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x3074)/*DPLL_CFG1*/ +#define REG_AON_APB_TDPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x3078)/*TDPLL_CFG1*/ +#define REG_AON_APB_CPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x307C)/*CPLL_CFG1*/ +#define REG_AON_APB_WIFIPLL1_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x3080)/*WIFIPLL1_CFG1*/ +#define REG_AON_APB_WIFIPLL2_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x3084)/*WIFIPLL2_CFG1*/ +#define REG_AON_APB_AON_QOS_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3088)/*AON_QOS_CFG*/ +#define REG_AON_APB_BB_LDO_CAL_START SCI_ADDR(REGS_AON_APB_BASE, 0x308C)/*BB_LDO_CAL_START*/ +#define REG_AON_APB_ANALOG_STATUS SCI_ADDR(REGS_AON_APB_BASE, 0x3090)/*ANALOG_STATUS*/ +#define REG_AON_APB_AON_CHIP_ID SCI_ADDR(REGS_AON_APB_BASE, 0x00FC)/*AON_CHIP_ID*/ + + + +/* bits definitions for register REG_AON_APB_APB_EB0 */ +#define BIT_I2C_EB (BIT(31)) +#define BIT_CA7_DAP_EB (BIT(30)) +#define BIT_CA7_TS1_EB (BIT(29)) +#define BIT_CA7_TS0_EB (BIT(28)) +#define BIT_GPU_EB (BIT(27)) +#define BIT_AON_CKG_EB (BIT(26)) +#define BIT_MM_EB (BIT(25)) +#define BIT_AP_WDG_EB (BIT(24)) +#define BIT_MSPI_EB (BIT(23)) +#define BIT_SPLK_EB (BIT(22)) +#define BIT_IPI_EB (BIT(21)) +#define BIT_PIN_EB (BIT(20)) +#define BIT_VBC_EB (BIT(19)) +#define BIT_AUD_EB (BIT(18)) +#define BIT_AUDIF_EB (BIT(17)) +#define BIT_ADI_EB (BIT(16)) +#define BIT_INTC_EB (BIT(15)) +#define BIT_EIC_EB (BIT(14)) +#define BIT_EFUSE_EB (BIT(13)) +#define BIT_AP_TMR0_EB (BIT(12)) +#define BIT_AON_TMR_EB (BIT(11)) +#define BIT_AP_SYST_EB (BIT(10)) +#define BIT_AON_SYST_EB (BIT(9)) +#define BIT_KPD_EB (BIT(8)) +#define BIT_PWM3_EB (BIT(7)) +#define BIT_PWM2_EB (BIT(6)) +#define BIT_PWM1_EB (BIT(5)) +#define BIT_PWM0_EB (BIT(4)) +#define BIT_GPIO_EB (BIT(3)) +#define BIT_TPC_EB (BIT(2)) +#define BIT_FM_EB (BIT(1)) +#define BIT_ADC_EB (BIT(0)) + +/* bits definitions for register REG_AON_APB_APB_EB1 */ +#define BIT_CODEC_EB (BIT(14)) +#define BIT_GSP_EMC_EB (BIT(13)) +#define BIT_ZIP_EMC_EB (BIT(12)) +#define BIT_DISP_EMC_EB (BIT(11)) +#define BIT_AP_TMR2_EB (BIT(10)) +#define BIT_AP_TMR1_EB (BIT(9)) +#define BIT_CA7_WDG_EB (BIT(8)) +#define BIT_AVS1_EB (BIT(7)) +#define BIT_AVS0_EB (BIT(6)) +#define BIT_PROBE_EB (BIT(5)) +#define BIT_AUX2_EB (BIT(4)) +#define BIT_AUX1_EB (BIT(3)) +#define BIT_AUX0_EB (BIT(2)) +#define BIT_THM_EB (BIT(1)) +#define BIT_PMU_EB (BIT(0)) + +/* bits definitions for register REG_AON_APB_APB_RST0 */ +#define BIT_I2C_SOFT_RST (BIT(30)) +#define BIT_CA7_TS1_SOFT_RST (BIT(29)) +#define BIT_CA7_TS0_SOFT_RST (BIT(28)) +#define BIT_DAP_MTX_SOFT_RST (BIT(27)) +#define BIT_MSPI1_SOFT_RST (BIT(26)) +#define BIT_MSPI0_SOFT_RST (BIT(25)) +#define BIT_SPLK_SOFT_RST (BIT(24)) +#define BIT_IPI_SOFT_RST (BIT(23)) +#define BIT_AON_CKG_SOFT_RST (BIT(22)) +#define BIT_PIN_SOFT_RST (BIT(21)) +#define BIT_VBC_SOFT_RST (BIT(20)) +#define BIT_AUD_SOFT_RST (BIT(19)) +#define BIT_AUDIF_SOFT_RST (BIT(18)) +#define BIT_ADI_SOFT_RST (BIT(17)) +#define BIT_INTC_SOFT_RST (BIT(16)) +#define BIT_EIC_SOFT_RST (BIT(15)) +#define BIT_EFUSE_SOFT_RST (BIT(14)) +#define BIT_AP_WDG_SOFT_RST (BIT(13)) +#define BIT_AP_TMR0_SOFT_RST (BIT(12)) +#define BIT_AON_TMR_SOFT_RST (BIT(11)) +#define BIT_AP_SYST_SOFT_RST (BIT(10)) +#define BIT_AON_SYST_SOFT_RST (BIT(9)) +#define BIT_KPD_SOFT_RST (BIT(8)) +#define BIT_PWM3_SOFT_RST (BIT(7)) +#define BIT_PWM2_SOFT_RST (BIT(6)) +#define BIT_PWM1_SOFT_RST (BIT(5)) +#define BIT_PWM0_SOFT_RST (BIT(4)) +#define BIT_GPIO_SOFT_RST (BIT(3)) +#define BIT_TPC_SOFT_RST (BIT(2)) +#define BIT_FM_SOFT_RST (BIT(1)) +#define BIT_ADC_SOFT_RST (BIT(0)) + +/* bits definitions for register REG_AON_APB_APB_RST1 */ +#define BIT_BB_CAL_SOFT_RST (BIT(11)) +#define BIT_DCXO_LC_SOFT_RST (BIT(10)) +#define BIT_AP_TMR2_SOFT_RST (BIT(9)) +#define BIT_AP_TMR1_SOFT_RST (BIT(8)) +#define BIT_CA7_WDG_SOFT_RST (BIT(7)) +#define BIT_AVS1_SOFT_RST (BIT(6)) +#define BIT_AVS0_SOFT_RST (BIT(5)) +#define BIT_DMC_PHY_SOFT_RST (BIT(4)) +#define BIT_GPU_THMA_SOFT_RST (BIT(3)) +#define BIT_ARM_THMA_SOFT_RST (BIT(2)) +#define BIT_THM_SOFT_RST (BIT(1)) +#define BIT_PMU_SOFT_RST (BIT(0)) + +/* bits definitions for register REG_AON_APB_APB_RTC_EB */ +#define BIT_BB_CAL_RTC_EB (BIT(18)) +#define BIT_DCXO_LC_RTC_EB (BIT(17)) +#define BIT_AP_TMR2_RTC_EB (BIT(16)) +#define BIT_AP_TMR1_RTC_EB (BIT(15)) +#define BIT_GPU_THMA_RTC_AUTO_EN (BIT(14)) +#define BIT_ARM_THMA_RTC_AUTO_EN (BIT(13)) +#define BIT_GPU_THMA_RTC_EB (BIT(12)) +#define BIT_ARM_THMA_RTC_EB (BIT(11)) +#define BIT_THM_RTC_EB (BIT(10)) +#define BIT_CA7_WDG_RTC_EB (BIT(9)) +#define BIT_AP_WDG_RTC_EB (BIT(8)) +#define BIT_EIC_RTCDV5_EB (BIT(7)) +#define BIT_EIC_RTC_EB (BIT(6)) +#define BIT_AP_TMR0_RTC_EB (BIT(5)) +#define BIT_AON_TMR_RTC_EB (BIT(4)) +#define BIT_AP_SYST_RTC_EB (BIT(3)) +#define BIT_AON_SYST_RTC_EB (BIT(2)) +#define BIT_KPD_RTC_EB (BIT(1)) +#define BIT_ARCH_RTC_EB (BIT(0)) + +/* bits definitions for register REG_AON_APB_REC_26MHZ_BUF_CFG */ +#define BITS_PLL_PROBE_SEL(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13))) +#define BIT_REC_26MHZ_1_CUR_SEL (BIT(4)) +#define BIT_REC_26MHZ_0_CUR_SEL (BIT(0)) + +/* bits definitions for register REG_AON_APB_SINDRV_CTRL */ +#define BITS_SINDRV_LVL(_X_) ((_X_) << 3 & (BIT(3)|BIT(4))) +#define BIT_SINDRV_CLIP_MODE (BIT(2)) +#define BIT_SINDRV_ENA_SQUARE (BIT(1)) +#define BIT_SINDRV_ENA (BIT(0)) + +/* bits definitions for register REG_AON_APB_ADA_SEL_CTRL */ +#define BIT_TW_MODE_SEL (BIT(3)) +#define BIT_WGADC_DIV_EN (BIT(2)) +#define BIT_AFCDAC_SYS_SEL (BIT(1)) +#define BIT_APCDAC_SYS_SEL (BIT(0)) + +/* bits definitions for register REG_AON_APB_VBC_CTRL */ +#define BIT_AUDIF_CKG_AUTO_EN (BIT(20)) +#define BITS_AUD_INT_SYS_SEL(_X_) ((_X_) << 18 & (BIT(18)|BIT(19))) +#define BITS_VBC_AFIFO_INT_SYS_SEL(_X_) ((_X_) << 16 & (BIT(16)|BIT(17))) +#define BITS_VBC_AD23_INT_SYS_SEL(_X_) ((_X_) << 14 & (BIT(14)|BIT(15))) +#define BITS_VBC_AD01_INT_SYS_SEL(_X_) ((_X_) << 12 & (BIT(12)|BIT(13))) +#define BITS_VBC_DA01_INT_SYS_SEL(_X_) ((_X_) << 10 & (BIT(10)|BIT(11))) +#define BITS_VBC_AD23_DMA_SYS_SEL(_X_) ((_X_) << 8 & (BIT(8)|BIT(9))) +#define BITS_VBC_AD01_DMA_SYS_SEL(_X_) ((_X_) << 6 & (BIT(6)|BIT(7))) +#define BITS_VBC_DA01_DMA_SYS_SEL(_X_) ((_X_) << 4 & (BIT(4)|BIT(5))) +#define BIT_VBC_INT_CP0_ARM_SEL (BIT(3)) +#define BIT_VBC_INT_CP1_ARM_SEL (BIT(2)) +#define BIT_VBC_DMA_CP0_ARM_SEL (BIT(1)) +#define BIT_VBC_DMA_CP1_ARM_SEL (BIT(0)) + +/* bits definitions for register REG_AON_APB_PWR_CTRL */ +#define BIT_DSI_PHY_PD (BIT(12)) +#define BIT_CSI1_PHY_PD (BIT(11)) +#define BIT_CSI0_PHY_PD (BIT(10)) +#define BIT_CA7_TS1_STOP (BIT(9)) +#define BIT_CA7_TS0_STOP (BIT(8)) +#define BIT_EFUSE_BIST_PWR_ON (BIT(3)) +#define BIT_FORCE_DSI_PHY_SHUTDOWNZ (BIT(2)) +#define BIT_FORCE_CSI_PHY_SHUTDOWNZ (BIT(1)) +#define BIT_USB_PHY_PD (BIT(0)) + +/* bits definitions for register REG_AON_APB_TS_CFG */ +#define BIT_CSYSACK_TS_LP_2 (BIT(13)) +#define BIT_CSYSREQ_TS_LP_2 (BIT(12)) +#define BIT_CSYSACK_TS_LP_1 (BIT(11)) +#define BIT_CSYSREQ_TS_LP_1 (BIT(10)) +#define BIT_CSYSACK_TS_LP_0 (BIT(9)) +#define BIT_CSYSREQ_TS_LP_0 (BIT(8)) +#define BIT_EVENTACK_RESTARTREQ_TS01 (BIT(4)) +#define BIT_EVENT_RESTARTREQ_TS01 (BIT(1)) +#define BIT_EVENT_HALTREQ_TS01 (BIT(0)) + +/* bits definitions for register REG_AON_APB_BOOT_MODE */ +#define BIT_WPLL_OVR_FREQ_SEL (BIT(12)) +#define BIT_PTEST_FUNC_ATSPEED_SEL (BIT(8)) +#define BIT_PTEST_FUNC_MODE (BIT(7)) +#define BIT_USB_DLOAD_EN (BIT(4)) +#define BIT_ARM_BOOT_MD3 (BIT(3)) +#define BIT_ARM_BOOT_MD2 (BIT(2)) +#define BIT_ARM_BOOT_MD1 (BIT(1)) +#define BIT_ARM_BOOT_MD0 (BIT(0)) + +/* bits definitions for register REG_AON_APB_BB_BG_CTRL */ +#define BIT_BB_CON_BG (BIT(22)) +#define BITS_BB_BG_RSV(_X_) ((_X_) << 20 & (BIT(20)|BIT(21))) +#define BITS_BB_LDO_V(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19))) +#define BIT_BB_BG_RBIAS_EN (BIT(15)) +#define BIT_BB_BG_IEXT_IB_EN (BIT(14)) +#define BITS_BB_LDO_REFCTRL(_X_) ((_X_) << 12 & (BIT(12)|BIT(13))) +#define BIT_BB_LDO_AUTO_PD_EN (BIT(11)) +#define BIT_BB_LDO_SLP_PD_EN (BIT(10)) +#define BIT_BB_LDO_FORCE_ON (BIT(9)) +#define BIT_BB_LDO_FORCE_PD (BIT(8)) +#define BIT_BB_BG_AUTO_PD_EN (BIT(3)) +#define BIT_BB_BG_SLP_PD_EN (BIT(2)) +#define BIT_BB_BG_FORCE_ON (BIT(1)) +#define BIT_BB_BG_FORCE_PD (BIT(0)) + +/* bits definitions for register REG_AON_APB_CP_ARM_JTAG_CTRL */ +#define BITS_CP_ARM_JTAG_PIN_SEL(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2))) + +/* bits definitions for register REG_AON_APB_PLL_SOFT_CNT_DONE */ +#define BIT_XTLBUF1_SOFT_CNT_DONE (BIT(9)) +#define BIT_XTLBUF0_SOFT_CNT_DONE (BIT(8)) +#define BIT_WIFIPLL2_SOFT_CNT_DONE (BIT(6)) +#define BIT_WIFIPLL1_SOFT_CNT_DONE (BIT(5)) +#define BIT_CPLL_SOFT_CNT_DONE (BIT(4)) +#define BIT_WPLL_SOFT_CNT_DONE (BIT(3)) +#define BIT_TDPLL_SOFT_CNT_DONE (BIT(2)) +#define BIT_DPLL_SOFT_CNT_DONE (BIT(1)) +#define BIT_MPLL_SOFT_CNT_DONE (BIT(0)) + +/* bits definitions for register REG_AON_APB_DCXO_LC_REG0 */ +#define BIT_DCXO_LC_FLAG (BIT(8)) +#define BIT_DCXO_LC_FLAG_CLR (BIT(1)) +#define BIT_DCXO_LC_CNT_CLR (BIT(0)) + +/* bits definitions for register REG_AON_APB_DCXO_LC_REG1 */ +#define BITS_DCXO_LC_CNT(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_MPLL_CFG */ +#define BITS_MPLL_REFIN(_X_) ((_X_) << 24 & (BIT(24)|BIT(25))) +#define BITS_MPLL_LPF(_X_) ((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22))) +#define BITS_MPLL_IBIAS(_X_) ((_X_) << 16 & (BIT(16)|BIT(17))) +#define BITS_MPLL_N(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10))) + +/* bits definitions for register REG_AON_APB_DPLL_CFG */ +#define BITS_DPLL_REFIN(_X_) ((_X_) << 24 & (BIT(24)|BIT(25))) +#define BITS_DPLL_LPF(_X_) ((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22))) +#define BITS_DPLL_IBIAS(_X_) ((_X_) << 16 & (BIT(16)|BIT(17))) +#define BITS_DPLL_N(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10))) + +/* bits definitions for register REG_AON_APB_TDPLL_CFG */ +#define BITS_TDPLL_REFIN(_X_) ((_X_) << 24 & (BIT(24)|BIT(25))) +#define BITS_TDPLL_LPF(_X_) ((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22))) +#define BITS_TDPLL_IBIAS(_X_) ((_X_) << 16 & (BIT(16)|BIT(17))) +#define BITS_TDPLL_N(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10))) + +/* bits definitions for register REG_AON_APB_CPLL_CFG */ +#define BITS_CPLL_REFIN(_X_) ((_X_) << 24 & (BIT(24)|BIT(25))) +#define BITS_CPLL_LPF(_X_) ((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22))) +#define BITS_CPLL_IBIAS(_X_) ((_X_) << 16 & (BIT(16)|BIT(17))) +#define BITS_CPLL_N(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10))) + +/* bits definitions for register REG_AON_APB_WIFIPLL0_CFG */ +#define BITS_WIFIPLL1_REFIN(_X_) ((_X_) << 24 & (BIT(24)|BIT(25))) +#define BITS_WIFIPLL1_LPF(_X_) ((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22))) +#define BITS_WIFIPLL1_IBIAS(_X_) ((_X_) << 16 & (BIT(16)|BIT(17))) +#define BITS_WIFIPLL1_N(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10))) + +/* bits definitions for register REG_AON_APB_WIFIPLL1_CFG */ +#define BITS_WIFIPLL2_REFIN(_X_) ((_X_) << 24 & (BIT(24)|BIT(25))) +#define BITS_WIFIPLL2_LPF(_X_) ((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22))) +#define BITS_WIFIPLL2_IBIAS(_X_) ((_X_) << 16 & (BIT(16)|BIT(17))) +#define BITS_WIFIPLL2_N(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10))) + +/* bits definitions for register REG_AON_APB_WPLL_CFG0 */ +#define BITS_WPLL_REFIN(_X_) ((_X_) << 24 & (BIT(24)|BIT(25))) +#define BITS_WPLL_LPF(_X_) ((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22))) +#define BITS_WPLL_IBIAS(_X_) ((_X_) << 16 & (BIT(16)|BIT(17))) +#define BITS_WPLL_N(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10))) + +/* bits definitions for register REG_AON_APB_WPLL_CFG1 */ +#define BITS_WPLL_KINT(_X_) ((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31))) +#define BIT_WPLL_DIV_S (BIT(10)) +#define BITS_WPLL_RSV(_X_) ((_X_) << 8 & (BIT(8)|BIT(9))) +#define BIT_WPLL_MOD_EN (BIT(7)) +#define BIT_WPLL_SDM_EN (BIT(6)) +#define BITS_WPLL_NINT(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5))) + +/* bits definitions for register REG_AON_APB_AON_CGM_CFG */ +#define BITS_PROBE_CKG_DIV(_X_) ((_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31))) +#define BITS_AUX2_CKG_DIV(_X_) ((_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27))) +#define BITS_AUX1_CKG_DIV(_X_) ((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_AUX0_CKG_DIV(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19))) +#define BITS_PROBE_CKG_SEL(_X_) ((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_AUX2_CKG_SEL(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11))) +#define BITS_AUX1_CKG_SEL(_X_) ((_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7))) +#define BITS_AUX0_CKG_SEL(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3))) + +/* bits definitions for register REG_AON_APB_CP0_ADDR_REMAP_CTRL0 */ +#define BITS_CP0_ADDR_B7_REMAP(_X_) ((_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31))) +#define BITS_CP0_ADDR_B6_REMAP(_X_) ((_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27))) +#define BITS_CP0_ADDR_B5_REMAP(_X_) ((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_CP0_ADDR_B4_REMAP(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19))) +#define BITS_CP0_ADDR_B3_REMAP(_X_) ((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_CP0_ADDR_B2_REMAP(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11))) +#define BITS_CP0_ADDR_B1_REMAP(_X_) ((_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7))) +#define BITS_CP0_ADDR_B0_REMAP(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3))) + +/* bits definitions for register REG_AON_APB_CP0_ADDR_REMAP_CTRL1 */ +#define BIT_CP0_PUB_IRAM_B8_PROT_EN (BIT(12)) +#define BIT_CP0_PUB_IRAM_B7_PROT_EN (BIT(11)) +#define BIT_CP0_PUB_IRAM_B6_PROT_EN (BIT(10)) +#define BIT_CP0_PUB_IRAM_B5_PROT_EN (BIT(9)) +#define BIT_CP0_PUB_IRAM_B4_PROT_EN (BIT(8)) +#define BIT_CP0_PUB_IRAM_B3_PROT_EN (BIT(7)) +#define BIT_CP0_PUB_IRAM_B2_PROT_EN (BIT(6)) +#define BIT_CP0_PUB_IRAM_B1_PROT_EN (BIT(5)) +#define BIT_CP0_PUB_IRAM_B0_PROT_EN (BIT(4)) +#define BITS_CP0_ADDR_B8_REMAP(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3))) + +/* bits definitions for register REG_AON_APB_CP1_ADDR_REMAP_CTRL0 */ +#define BITS_CP1_ADDR_B7_REMAP(_X_) ((_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31))) +#define BITS_CP1_ADDR_B6_REMAP(_X_) ((_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27))) +#define BITS_CP1_ADDR_B5_REMAP(_X_) ((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_CP1_ADDR_B4_REMAP(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19))) +#define BITS_CP1_ADDR_B3_REMAP(_X_) ((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_CP1_ADDR_B2_REMAP(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11))) +#define BITS_CP1_ADDR_B1_REMAP(_X_) ((_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7))) +#define BITS_CP1_ADDR_B0_REMAP(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3))) + +/* bits definitions for register REG_AON_APB_CP1_ADDR_REMAP_CTRL1 */ +#define BIT_CP1_PUB_IRAM_B8_PROT_EN (BIT(12)) +#define BIT_CP1_PUB_IRAM_B7_PROT_EN (BIT(11)) +#define BIT_CP1_PUB_IRAM_B6_PROT_EN (BIT(10)) +#define BIT_CP1_PUB_IRAM_B5_PROT_EN (BIT(9)) +#define BIT_CP1_PUB_IRAM_B4_PROT_EN (BIT(8)) +#define BIT_CP1_PUB_IRAM_B3_PROT_EN (BIT(7)) +#define BIT_CP1_PUB_IRAM_B2_PROT_EN (BIT(6)) +#define BIT_CP1_PUB_IRAM_B1_PROT_EN (BIT(5)) +#define BIT_CP1_PUB_IRAM_B0_PROT_EN (BIT(4)) +#define BITS_CP1_ADDR_B8_REMAP(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3))) + +/* bits definitions for register REG_AON_APB_CP2_ADDR_REMAP_CTRL0 */ +#define BITS_CP2_ADDR_B7_REMAP(_X_) ((_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31))) +#define BITS_CP2_ADDR_B6_REMAP(_X_) ((_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27))) +#define BITS_CP2_ADDR_B5_REMAP(_X_) ((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_CP2_ADDR_B4_REMAP(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19))) +#define BITS_CP2_ADDR_B3_REMAP(_X_) ((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_CP2_ADDR_B2_REMAP(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11))) +#define BITS_CP2_ADDR_B1_REMAP(_X_) ((_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7))) +#define BITS_CP2_ADDR_B0_REMAP(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3))) + +/* bits definitions for register REG_AON_APB_CP2_ADDR_REMAP_CTRL1 */ +#define BIT_CP2_PUB_IRAM_B8_PROT_EN (BIT(12)) +#define BIT_CP2_PUB_IRAM_B7_PROT_EN (BIT(11)) +#define BIT_CP2_PUB_IRAM_B6_PROT_EN (BIT(10)) +#define BIT_CP2_PUB_IRAM_B5_PROT_EN (BIT(9)) +#define BIT_CP2_PUB_IRAM_B4_PROT_EN (BIT(8)) +#define BIT_CP2_PUB_IRAM_B3_PROT_EN (BIT(7)) +#define BIT_CP2_PUB_IRAM_B2_PROT_EN (BIT(6)) +#define BIT_CP2_PUB_IRAM_B1_PROT_EN (BIT(5)) +#define BIT_CP2_PUB_IRAM_B0_PROT_EN (BIT(4)) +#define BITS_CP2_ADDR_B8_REMAP(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3))) + +/* bits definitions for register REG_AON_APB_IO_DLY_CTRL */ +#define BITS_CLK_CCIR_DLY_SEL(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11))) +#define BITS_CLK_CP1DSP_DLY_SEL(_X_) ((_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7))) +#define BITS_CLK_CP0DSP_DLY_SEL(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3))) + +/* bits definitions for register REG_AON_APB_AP_WPROT_EN */ +#define BITS_AP_AWADDR_WPROT_EN(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CP0_WPROT_EN */ +#define BITS_CP0_AWADDR_WPROT_EN(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CP1_WPROT_EN */ +#define BITS_CP1_AWADDR_WPROT_EN(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CP2_WPROT_EN */ +#define BITS_CP2_AWADDR_WPROT_EN(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_PMU_RST_MONITOR */ +#define BITS_PMU_RST_MONITOR(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_THM_RST_MONITOR */ +#define BITS_THM_RST_MONITOR(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_AP_RST_MONITOR */ +#define BITS_AP_RST_MONITOR(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CA7_RST_MONITOR */ +#define BITS_CA7_RST_MONITOR(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_BOND_OPT0 */ +#define BITS_BOND_OPTION0(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_BOND_OPT1 */ +#define BITS_BOND_OPTION1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_RES_REG0 */ +#define BITS_RES_REG0(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_RES_REG1 */ +#define BITS_RES_REG1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_MPLL_CFG1 */ +#define BITS_MPLL_KINT(_X_) ((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31))) +#define BIT_MPLL_DIV_S (BIT(10)) +#define BITS_MPLL_RSV(_X_) ((_X_) << 8 & (BIT(8)|BIT(9))) +#define BIT_MPLL_MOD_EN (BIT(7)) +#define BIT_MPLL_SDM_EN (BIT(6)) +#define BITS_MPLL_NINT(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5))) + +/* bits definitions for register REG_AON_APB_DPLL_CFG1 */ +#define BITS_DPLL_KINT(_X_) ((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31))) +#define BIT_DPLL_DIV_S (BIT(10)) +#define BITS_DPLL_RSV(_X_) ((_X_) << 8 & (BIT(8)|BIT(9))) +#define BIT_DPLL_MOD_EN (BIT(7)) +#define BIT_DPLL_SDM_EN (BIT(6)) +#define BITS_DPLL_NINT(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5))) + +/* bits definitions for register REG_AON_APB_TDPLL_CFG1 */ +#define BITS_TDPLL_KINT(_X_) ((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31))) +#define BIT_TDPLL_DIV_S (BIT(10)) +#define BITS_TDPLL_RSV(_X_) ((_X_) << 8 & (BIT(8)|BIT(9))) +#define BIT_TDPLL_MOD_EN (BIT(7)) +#define BIT_TDPLL_SDM_EN (BIT(6)) +#define BITS_TDPLL_NINT(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5))) + +/* bits definitions for register REG_AON_APB_CPLL_CFG1 */ +#define BITS_CPLL_KINT(_X_) ((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31))) +#define BIT_CPLL_DIV_S (BIT(10)) +#define BITS_CPLL_RSV(_X_) ((_X_) << 8 & (BIT(8)|BIT(9))) +#define BIT_CPLL_MOD_EN (BIT(7)) +#define BIT_CPLL_SDM_EN (BIT(6)) +#define BITS_CPLL_NINT(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5))) + +/* bits definitions for register REG_AON_APB_WIFIPLL1_CFG1 */ +#define BITS_WIFIPLL1_KINT(_X_) ((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31))) +#define BIT_WIFIPLL1_DIV_S (BIT(10)) +#define BITS_WIFIPLL1_RSV(_X_) ((_X_) << 8 & (BIT(8)|BIT(9))) +#define BIT_WIFIPLL1_MOD_EN (BIT(7)) +#define BIT_WIFIPLL1_SDM_EN (BIT(6)) +#define BITS_WIFIPLL1_NINT(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5))) + +/* bits definitions for register REG_AON_APB_WIFIPLL2_CFG1 */ +#define BITS_WIFIPLL2_KINT(_X_) ((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31))) +#define BIT_WIFIPLL2_DIV_S (BIT(10)) +#define BITS_WIFIPLL2_RSV(_X_) ((_X_) << 8 & (BIT(8)|BIT(9))) +#define BIT_WIFIPLL2_MOD_EN (BIT(7)) +#define BIT_WIFIPLL2_SDM_EN (BIT(6)) +#define BITS_WIFIPLL2_NINT(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5))) + +/* bits definitions for register REG_AON_APB_AON_QOS_CFG */ +#define BITS_QOS_R_GPU(_X_) ((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_QOS_W_GPU(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11))) +#define BITS_QOS_R_GSP(_X_) ((_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7))) +#define BITS_QOS_W_GSP(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3))) + +/* bits definitions for register REG_AON_APB_BB_LDO_CAL_START */ +#define BIT_BB_LDO_CAL_START (BIT(0)) + +/* bits definitions for register REG_AON_APB_ANALOG_STATUS */ +#define BIT_EFS0_PD (BIT(21)) +#define BIT_THM_PD (BIT(20)) +#define BIT_LVDS_PLL_PD (BIT(19)) +#define BIT_LVDS_TX_PD (BIT(18)) +#define BIT_CPLL_PD (BIT(17)) +#define BIT_TDPLL_PD (BIT(16)) +#define BIT_WPLL_PD (BIT(15)) +#define BIT_DPLL_PD (BIT(14)) +#define BIT_MPLL_PD (BIT(13)) +#define BIT_REC_26MHZ_1_BUF_PD (BIT(12)) +#define BIT_REC_26MHZ_0_BUF_PD (BIT(11)) +#define BIT_WIFIPLL2_PD (BIT(10)) +#define BIT_WIFIPLL1_PD (BIT(9)) +#define BIT_WBT_DAC_PD (BIT(8)) +#define BIT_BT_SARAD_PD (BIT(7)) +#define BIT_WIFI_SARAD_PD (BIT(6)) +#define BIT_BB_LDO_PD (BIT(5)) +#define BIT_BB_BG_PD (BIT(4)) +#define BIT_WG_AAPC_PD (BIT(3)) +#define BIT_WG_AAFC_PD (BIT(2)) +#define BIT_WG_DAC_PD (BIT(1)) +#define BIT_WG_SARAD_PD (BIT(0)) + +/* bits definitions for register REG_AON_APB_AON_CHIP_ID */ +#define BITS_AON_CHIP_ID(_X_) (_X_) + +#endif diff --git a/include/soc/sprd/chip_x30g/__regs_aon_clk.h b/include/soc/sprd/chip_x30g/__regs_aon_clk.h new file mode 100644 index 00000000..b7ae4228 --- /dev/null +++ b/include/soc/sprd/chip_x30g/__regs_aon_clk.h @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __REGS_AON_CLK_H__ +#define __REGS_AON_CLK_H__ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, include <mach/sci_glb_regs.h>" +#endif + +#define REGS_AON_CLK + +/* registers definitions for controller REGS_AON_CLK */ +#define REG_AON_CLK_PUB_AHB_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0020) +#define REG_AON_CLK_EMC_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0024) +#define REG_AON_CLK_AON_APB_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0028) +#define REG_AON_CLK_AUDIF_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x002c) +#define REG_AON_CLK_FM_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0030) +#define REG_AON_CLK_ADI_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0034) +#define REG_AON_CLK_PWM0_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0038) +#define REG_AON_CLK_PWM1_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x003c) +#define REG_AON_CLK_PWM2_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0040) +#define REG_AON_CLK_PWM3_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0044) +#define REG_AON_CLK_CA7_DAP_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0048) +#define REG_AON_CLK_CA7_TS_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x004c) +#define REG_AON_CLK_MSPI_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0050) +#define REG_AON_CLK_I2C_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0054) +#define REG_AON_CLK_AVS0_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0058) +#define REG_AON_CLK_AVS1_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x005c) + +/* vars definitions for controller REGS_AON_CLK */ + +#endif //__REGS_AON_CLK_H__ diff --git a/include/soc/sprd/chip_x30g/__regs_ap_ahb.h b/include/soc/sprd/chip_x30g/__regs_ap_ahb.h new file mode 100644 index 00000000..5f4a6760 --- /dev/null +++ b/include/soc/sprd/chip_x30g/__regs_ap_ahb.h @@ -0,0 +1,391 @@ +/*
+ * Copyright (C) 2014 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+#ifndef __SCI_GLB_REGS_H__
+#error "Don't include this file directly, Pls include sci_glb_regs.h"
+#endif
+
+
+#ifndef __H_REGS_AP_AHB_HEADFILE_H__
+#define __H_REGS_AP_AHB_HEADFILE_H__ __FILE__
+
+#define REGS_AP_AHB
+
+/* registers definitions for AP_AHB */
+#define REG_AP_AHB_AHB_EB SCI_ADDR(REGS_AP_AHB_BASE, 0x0000)
+#define REG_AP_AHB_AHB_RST SCI_ADDR(REGS_AP_AHB_BASE, 0x0004)
+#define REG_AP_AHB_CA7_RST_SET SCI_ADDR(REGS_AP_AHB_BASE, 0x0008)
+#define REG_AP_AHB_AP_SYS_FORCE_SLEEP_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x000C)
+#define REG_AP_AHB_AP_SYS_AUTO_SLEEP_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x0010)
+#define REG_AP_AHB_HOLDING_PEN SCI_ADDR(REGS_AP_AHB_BASE, 0x0014)
+#define REG_AP_AHB_JMP_ADDR_CA7_C0 SCI_ADDR(REGS_AP_AHB_BASE, 0x0018)
+#define REG_AP_AHB_JMP_ADDR_CA7_C1 SCI_ADDR(REGS_AP_AHB_BASE, 0x001C)
+#define REG_AP_AHB_JMP_ADDR_CA7_C2 SCI_ADDR(REGS_AP_AHB_BASE, 0x0020)
+#define REG_AP_AHB_JMP_ADDR_CA7_C3 SCI_ADDR(REGS_AP_AHB_BASE, 0x0024)
+#define REG_AP_AHB_CA7_C0_PU_LOCK SCI_ADDR(REGS_AP_AHB_BASE, 0x0028)
+#define REG_AP_AHB_CA7_C1_PU_LOCK SCI_ADDR(REGS_AP_AHB_BASE, 0x002C)
+#define REG_AP_AHB_CA7_C2_PU_LOCK SCI_ADDR(REGS_AP_AHB_BASE, 0x0030)
+#define REG_AP_AHB_CA7_C3_PU_LOCK SCI_ADDR(REGS_AP_AHB_BASE, 0x0034)
+#define REG_AP_AHB_CA7_CKG_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x3000)
+#define REG_AP_AHB_MCU_PAUSE SCI_ADDR(REGS_AP_AHB_BASE, 0x3004)
+#define REG_AP_AHB_MISC_CKG_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x3008)
+#define REG_AP_AHB_MISC_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x300C)
+#define REG_AP_AHB_AP_MTX_S3_PRIO0 SCI_ADDR(REGS_AP_AHB_BASE, 0x3010)
+#define REG_AP_AHB_AP_MTX_S3_PRIO1 SCI_ADDR(REGS_AP_AHB_BASE, 0x3014)
+#define REG_AP_AHB_AP_MTX_S3_PRIO2 SCI_ADDR(REGS_AP_AHB_BASE, 0x3018)
+#define REG_AP_AHB_AP_MTX_S2_PRIO0 SCI_ADDR(REGS_AP_AHB_BASE, 0x301C)
+#define REG_AP_AHB_AP_MTX_S1_PRIO0 SCI_ADDR(REGS_AP_AHB_BASE, 0x3020)
+#define REG_AP_AHB_AP_MTX_S0_PRIO0 SCI_ADDR(REGS_AP_AHB_BASE, 0x3024)
+#define REG_AP_AHB_AP_MTX_S0_PRIO1 SCI_ADDR(REGS_AP_AHB_BASE, 0x3028)
+#define REG_AP_AHB_AP_MTX_S0_PRIO2 SCI_ADDR(REGS_AP_AHB_BASE, 0x302C)
+#define REG_AP_AHB_AP_MAIN_MTX_HPROT_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x3030)
+#define REG_AP_AHB_CA7_STANDBY_STATUS SCI_ADDR(REGS_AP_AHB_BASE, 0x3034)
+#define REG_AP_AHB_NANC_CLK_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x3038)
+#define REG_AP_AHB_LVDS_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x303C)
+#define REG_AP_AHB_LVDS_PLL_CFG0 SCI_ADDR(REGS_AP_AHB_BASE, 0x3040)
+#define REG_AP_AHB_LVDS_PLL_CFG1 SCI_ADDR(REGS_AP_AHB_BASE, 0x3044)
+#define REG_AP_AHB_CA7_C0_AUTO_FORCE_SHUTDOWN_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x3048)
+#define REG_AP_AHB_CA7_C1_AUTO_FORCE_SHUTDOWN_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x304C)
+#define REG_AP_AHB_CA7_C2_AUTO_FORCE_SHUTDOWN_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x3050)
+#define REG_AP_AHB_CA7_C3_AUTO_FORCE_SHUTDOWN_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x3054)
+#define REG_AP_AHB_AP_QOS_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x3058)
+#define REG_AP_AHB_CHIP_ID SCI_ADDR(REGS_AP_AHB_BASE, 0x30FC)
+
+
+
+/* bits definitions for register REG_AP_AHB_AHB_EB */
+#define BIT_LVDS_EB ( BIT(22) )
+#define BIT_ZIPDEC_EB ( BIT(21) )
+#define BIT_ZIPENC_EB ( BIT(20) )
+#define BIT_NANDC_ECC_EB ( BIT(19) )
+#define BIT_NANDC_2X_EB ( BIT(18) )
+#define BIT_NANDC_EB ( BIT(17) )
+#define BIT_BUSMON2_EB ( BIT(16) )
+#define BIT_BUSMON1_EB ( BIT(15) )
+#define BIT_BUSMON0_EB ( BIT(14) )
+#define BIT_SPINLOCK_EB ( BIT(13) )
+#define BIT_GPS_EB ( BIT(12) )
+#define BIT_EMMC_EB ( BIT(11) )
+#define BIT_SDIO2_EB ( BIT(10) )
+#define BIT_SDIO1_EB ( BIT(9) )
+#define BIT_SDIO0_EB ( BIT(8) )
+#define BIT_DRM_EB ( BIT(7) )
+#define BIT_NFC_EB ( BIT(6) )
+#define BIT_DMA_EB ( BIT(5) )
+#define BIT_USB_EB ( BIT(4) )
+#define BIT_GSP_EB ( BIT(3) )
+#define BIT_DISPC1_EB ( BIT(2) )
+#define BIT_DISPC0_EB ( BIT(1) )
+#define BIT_DSI_EB ( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_AHB_RST */
+#define BIT_LVDS_SOFT_RST ( BIT(25) )
+#define BIT_ZIP_MTX_SOFT_RST ( BIT(24) )
+#define BIT_ZIPDEC_SOFT_RST ( BIT(23) )
+#define BIT_ZIPENC_SOFT_RST ( BIT(22) )
+#define BIT_NANDC_SOFT_RST ( BIT(20) )
+#define BIT_BUSMON2_SOFT_RST ( BIT(19) )
+#define BIT_BUSMON1_SOFT_RST ( BIT(18) )
+#define BIT_BUSMON0_SOFT_RST ( BIT(17) )
+#define BIT_SPINLOCK_SOFT_RST ( BIT(16) )
+#define BIT_GPS_SOFT_RST ( BIT(15) )
+#define BIT_EMMC_SOFT_RST ( BIT(14) )
+#define BIT_SDIO2_SOFT_RST ( BIT(13) )
+#define BIT_SDIO1_SOFT_RST ( BIT(12) )
+#define BIT_SDIO0_SOFT_RST ( BIT(11) )
+#define BIT_DRM_SOFT_RST ( BIT(10) )
+#define BIT_NFC_SOFT_RST ( BIT(9) )
+#define BIT_DMA_SOFT_RST ( BIT(8) )
+#define BIT_USB_PHY_SOFT_RST ( BIT(7) )
+#define BIT_USB_UTMI_SOFT_RST ( BIT(6) )
+#define BIT_USB_SOFT_RST ( BIT(5) )
+#define BIT_DISP_MTX_SOFT_RST ( BIT(4) )
+#define BIT_GSP_SOFT_RST ( BIT(3) )
+#define BIT_DISPC1_SOFT_RST ( BIT(2) )
+#define BIT_DISPC0_SOFT_RST ( BIT(1) )
+#define BIT_DSI_SOFT_RST ( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_CA7_RST_SET */
+#define BIT_CA7_CS_DBG_SOFT_RST ( BIT(14) )
+#define BIT_CA7_L2_SOFT_RST ( BIT(13) )
+#define BIT_CA7_SOCDBG_SOFT_RST ( BIT(12) )
+#define BITS_CA7_ETM_SOFT_RST(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_CA7_DBG_SOFT_RST(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_CA7_CORE_SOFT_RST(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_AP_AHB_AP_SYS_FORCE_SLEEP_CFG */
+#define BIT_AP_PERI_FORCE_ON ( BIT(2) )
+#define BIT_AP_PERI_FORCE_SLP ( BIT(1) )
+#define BIT_AP_APB_SLEEP ( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_AP_SYS_AUTO_SLEEP_CFG */
+#define BIT_GSP_CKG_FORCE_EN ( BIT(9) )
+#define BIT_GSP_AUTO_GATE_EN ( BIT(8) )
+#define BIT_AP_AHB_AUTO_GATE_EN ( BIT(5) )
+#define BIT_AP_EMC_AUTO_GATE_EN ( BIT(4) )
+#define BIT_CA7_EMC_AUTO_GATE_EN ( BIT(3) )
+#define BIT_CA7_DBG_FORCE_SLEEP ( BIT(2) )
+#define BIT_CA7_DBG_AUTO_GATE_EN ( BIT(1) )
+#define BIT_CA7_CORE_AUTO_GATE_EN ( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_HOLDING_PEN */
+#define BITS_HOLDING_PEN(_X_) (_X_)
+
+/* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C0 */
+#define BITS_JMP_ADDR_CA7_C0(_X_) (_X_)
+
+/* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C1 */
+#define BITS_JMP_ADDR_CA7_C1(_X_) (_X_)
+
+/* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C2 */
+#define BITS_JMP_ADDR_CA7_C2(_X_) (_X_)
+
+/* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C3 */
+#define BITS_JMP_ADDR_CA7_C3(_X_) (_X_)
+
+/* bits definitions for register REG_AP_AHB_CA7_C0_PU_LOCK */
+#define BIT_CA7_C0_PU_LOCK ( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_CA7_C1_PU_LOCK */
+#define BIT_CA7_C1_PU_LOCK ( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_CA7_C2_PU_LOCK */
+#define BIT_CA7_C2_PU_LOCK ( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_CA7_C3_PU_LOCK */
+#define BIT_CA7_C3_PU_LOCK ( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_CA7_CKG_CFG */
+#define BITS_CA7_DBG_CKG_DIV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)) )
+#define BITS_CA7_AXI_CKG_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) )
+#define BITS_CA7_MCU_CKG_DIV(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) )
+#define BITS_CA7_MCU_CKG_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
+
+/* bits definitions for register REG_AP_AHB_MCU_PAUSE */
+#define BIT_DMA_ACT_LIGHT_EN ( BIT(5) )
+#define BIT_MCU_SLEEP_FOLLOW_CA7_EN ( BIT(4) )
+#define BIT_MCU_LIGHT_SLEEP_EN ( BIT(3) )
+#define BIT_MCU_DEEP_SLEEP_EN ( BIT(2) )
+#define BIT_MCU_SYS_SLEEP_EN ( BIT(1) )
+#define BIT_MCU_CORE_SLEEP ( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_MISC_CKG_EN */
+#define BIT_GPS_TCXO_INV_SEL ( BIT(13) )
+#define BIT_GPS_26M_INV_SEL ( BIT(12) )
+#define BIT_ASHB_CA7_DBG_VLD ( BIT(9) )
+#define BIT_ASHB_CA7_DBG_EN ( BIT(8) )
+#define BIT_DISP_TMC_CKG_EN ( BIT(4) )
+#define BIT_DPHY_REF_CKG_EN ( BIT(1) )
+#define BIT_DPHY_CFG_CKG_EN ( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_MISC_CFG */
+#define BITS_EMMC_SLOT_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
+#define BITS_SDIO0_SLOT_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_BUSMON2_CHN_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
+#define BITS_BUSMON1_CHN_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BIT_BUSMON0_CHN_SEL ( BIT(4) )
+#define BITS_SDIO2_SLOT_SEL(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_SDIO1_SLOT_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_AP_AHB_AP_MTX_S3_PRIO0 */
+#define BITS_PRI_M6TOS3_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_PRI_M6TOS3_SEL(_X_) ( (_X_) << 26 & (BIT(26)|BIT(27)) )
+#define BIT_PRI_M6TOS3_RND_EN ( BIT(25) )
+#define BIT_PRI_M6TOS3_ADJ_EN ( BIT(24) )
+#define BITS_PRI_M7TOS3_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PRI_M7TOS3_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
+#define BIT_PRI_M7TOS3_RND_EN ( BIT(17) )
+#define BIT_PRI_M7TOS3_ADJ_EN ( BIT(16) )
+#define BITS_PRI_M8TOS3_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PRI_M8TOS3_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
+#define BIT_PRI_M8TOS3_RND_EN ( BIT(9) )
+#define BIT_PRI_M8TOS3_ADJ_EN ( BIT(8) )
+#define BITS_PRI_M9TOS3_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_PRI_M9TOS3_SEL(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BIT_PRI_M9TOS3_RND_EN ( BIT(1) )
+#define BIT_PRI_M9TOS3_ADJ_EN ( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_AP_MTX_S3_PRIO1 */
+#define BITS_PRI_M2TOS3_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_PRI_M2TOS3_SEL(_X_) ( (_X_) << 26 & (BIT(26)|BIT(27)) )
+#define BIT_PRI_M2TOS3_RND_EN ( BIT(25) )
+#define BIT_PRI_M2TOS3_ADJ_EN ( BIT(24) )
+#define BITS_PRI_M3TOS3_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PRI_M3TOS3_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
+#define BIT_PRI_M3TOS3_RND_EN ( BIT(17) )
+#define BIT_PRI_M3TOS3_ADJ_EN ( BIT(16) )
+#define BITS_PRI_M4TOS3_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PRI_M4TOS3_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
+#define BIT_PRI_M4TOS3_RND_EN ( BIT(9) )
+#define BIT_PRI_M4TOS3_ADJ_EN ( BIT(8) )
+#define BITS_PRI_M5TOS3_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_PRI_M5TOS3_SEL(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BIT_PRI_M5TOS3_RND_EN ( BIT(1) )
+#define BIT_PRI_M5TOS3_ADJ_EN ( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_AP_MTX_S3_PRIO2 */
+#define BITS_PRI_M0TOS3_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_PRI_M0TOS3_SEL(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BIT_PRI_M0TOS3_RND_EN ( BIT(1) )
+#define BIT_PRI_M0TOS3_ADJ_EN ( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_AP_MTX_S2_PRIO0 */
+#define BITS_PRI_M0TOS2_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_PRI_M0TOS2_SEL(_X_) ( (_X_) << 26 & (BIT(26)|BIT(27)) )
+#define BIT_PRI_M0TOS2_RND_EN ( BIT(25) )
+#define BIT_PRI_M0TOS2_ADJ_EN ( BIT(24) )
+#define BITS_PRI_M1TOS2_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PRI_M1TOS2_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
+#define BIT_PRI_M1TOS2_RND_EN ( BIT(17) )
+#define BIT_PRI_M1TOS2_ADJ_EN ( BIT(16) )
+#define BITS_PRI_M2TOS2_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PRI_M2TOS2_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
+#define BIT_PRI_M2TOS2_RND_EN ( BIT(9) )
+#define BIT_PRI_M2TOS2_ADJ_EN ( BIT(8) )
+#define BITS_PRI_M3TOS2_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_PRI_M3TOS2_SEL(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BIT_PRI_M3TOS2_RND_EN ( BIT(1) )
+#define BIT_PRI_M3TOS2_ADJ_EN ( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_AP_MTX_S1_PRIO0 */
+#define BITS_PRI_M0TOS1_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_PRI_M0TOS1_SEL(_X_) ( (_X_) << 26 & (BIT(26)|BIT(27)) )
+#define BIT_PRI_M0TOS1_RND_EN ( BIT(25) )
+#define BIT_PRI_M0TOS1_ADJ_EN ( BIT(24) )
+#define BITS_PRI_M2TOS1_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PRI_M2TOS1_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
+#define BIT_PRI_M2TOS1_RND_EN ( BIT(17) )
+#define BIT_PRI_M2TOS1_ADJ_EN ( BIT(16) )
+#define BITS_PRI_M3TOS1_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PRI_M3TOS1_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
+#define BIT_PRI_M3TOS1_RND_EN ( BIT(9) )
+#define BIT_PRI_M3TOS1_ADJ_EN ( BIT(8) )
+#define BITS_PRI_M8TOS1_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_PRI_M8TOS1_SEL(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BIT_PRI_M8TOS1_RND_EN ( BIT(1) )
+#define BIT_PRI_M8TOS1_ADJ_EN ( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_AP_MTX_S0_PRIO0 */
+#define BITS_PRI_M0TOS0_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_PRI_M0TOS0_SEL(_X_) ( (_X_) << 26 & (BIT(26)|BIT(27)) )
+#define BIT_PRI_M0TOS0_RND_EN ( BIT(25) )
+#define BIT_PRI_M0TOS0_ADJ_EN ( BIT(24) )
+#define BITS_PRI_M1TOS0_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PRI_M1TOS0_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
+#define BIT_PRI_M1TOS0_RND_EN ( BIT(17) )
+#define BIT_PRI_M1TOS0_ADJ_EN ( BIT(16) )
+#define BITS_PRI_M2TOS0_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PRI_M2TOS0_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
+#define BIT_PRI_M2TOS0_RND_EN ( BIT(9) )
+#define BIT_PRI_M2TOS0_ADJ_EN ( BIT(8) )
+#define BITS_PRI_M3TOS0_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_PRI_M3TOS0_SEL(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BIT_PRI_M3TOS0_RND_EN ( BIT(1) )
+#define BIT_PRI_M3TOS0_ADJ_EN ( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_AP_MTX_S0_PRIO1 */
+#define BITS_PRI_M4TOS1_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_PRI_M4TOS1_SEL(_X_) ( (_X_) << 26 & (BIT(26)|BIT(27)) )
+#define BIT_PRI_M4TOS1_RND_EN ( BIT(25) )
+#define BIT_PRI_M4TOS1_ADJ_EN ( BIT(24) )
+#define BITS_PRI_M5TOS1_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PRI_M5TOS1_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
+#define BIT_PRI_M5TOS1_RND_EN ( BIT(17) )
+#define BIT_PRI_M5TOS1_ADJ_EN ( BIT(16) )
+#define BITS_PRI_M6TOS1_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PRI_M6TOS1_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
+#define BIT_PRI_M6TOS1_RND_EN ( BIT(9) )
+#define BIT_PRI_M6TOS1_ADJ_EN ( BIT(8) )
+#define BITS_PRI_M7TOS1_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_PRI_M7TOS1_SEL(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BIT_PRI_M7TOS1_RND_EN ( BIT(1) )
+#define BIT_PRI_M7TOS1_ADJ_EN ( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_AP_MTX_S0_PRIO2 */
+#define BITS_PRI_M9TOS1_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_PRI_M9TOS1_SEL(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BIT_PRI_M9TOS1_RND_EN ( BIT(1) )
+#define BIT_PRI_M9TOS1_ADJ_EN ( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_AP_MAIN_MTX_HPROT_CFG */
+#define BITS_HPROT_NFC(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_HPROT_EMMC(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_HPROT_SDIO2(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_HPROT_SDIO1(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_HPROT_SDIO0(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_HPROT_DMAW(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_HPROT_DMAR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_AP_AHB_CA7_STANDBY_STATUS */
+#define BIT_CA7_STANDBYWFIL2 ( BIT(12) )
+#define BITS_CA7_ETMSTANDBYWFX(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_CA7_STANDBYWFE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_CA7_STANDBYWFI(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_AP_AHB_NANC_CLK_CFG */
+#define BITS_CLK_NANDC2X_DIV(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_CLK_NANDC2X_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_AP_AHB_LVDS_CFG */
+#define BITS_LVDS_TXCLKDATA(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)) )
+#define BITS_LVDS_TXCOM(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) )
+#define BITS_LVDS_TXSLEW(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
+#define BITS_LVDS_TXSW(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_LVDS_TXRERSER(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_LVDS_PRE_EMP(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)) )
+#define BIT_LVDS_TXPD ( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_LVDS_PLL_CFG0 */
+#define BIT_LPLL_LOCK_DET ( BIT(31) )
+#define BITS_LPLL_REFIN(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
+#define BITS_LPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
+#define BIT_LPLL_DIV_S ( BIT(18) )
+#define BITS_LPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_LPLLN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
+
+/* bits definitions for register REG_AP_AHB_LVDS_PLL_CFG1 */
+#define BITS_LPLL_KINT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_LPLL_RSV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BIT_LPLL_MOD_EN ( BIT(7) )
+#define BIT_LPLL_SDM_EN ( BIT(6) )
+#define BITS_LPLL_NINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+
+/* bits definitions for register REG_AP_AHB_CA7_C0_AUTO_FORCE_SHUTDOWN_EN */
+#define BIT_CA7_C0_AUTO_FORCE_SHUTDOWN_EN ( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_CA7_C1_AUTO_FORCE_SHUTDOWN_EN */
+#define BIT_CA7_C1_AUTO_FORCE_SHUTDOWN_EN ( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_CA7_C2_AUTO_FORCE_SHUTDOWN_EN */
+#define BIT_CA7_C2_AUTO_FORCE_SHUTDOWN_EN ( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_CA7_C3_AUTO_FORCE_SHUTDOWN_EN */
+#define BIT_CA7_C3_AUTO_FORCE_SHUTDOWN_EN ( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_AP_QOS_CFG */
+#define BITS_QOS_R_TMC(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_QOS_W_TMC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_QOS_R_DISPC1(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_QOS_W_DISPC1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_QOS_R_DISPC0(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_QOS_W_DISPC0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_AP_AHB_CHIP_ID */
+#define BITS_CHIP_ID(_X_) (_X_)
+
+#endif
diff --git a/include/soc/sprd/chip_x30g/__regs_ap_apb.h b/include/soc/sprd/chip_x30g/__regs_ap_apb.h new file mode 100644 index 00000000..cd0a3c9b --- /dev/null +++ b/include/soc/sprd/chip_x30g/__regs_ap_apb.h @@ -0,0 +1,130 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_AP_APB_HEADFILE_H__ +#define __H_REGS_AP_APB_HEADFILE_H__ __FILE__ + +#define REGS_AP_APB + +/* registers definitions for AP_APB */ +#define REG_AP_APB_APB_EB SCI_ADDR(REGS_AP_APB_BASE, 0x0000) +#define REG_AP_APB_APB_RST SCI_ADDR(REGS_AP_APB_BASE, 0x0004) +#define REG_AP_APB_USB_PHY_TUNE SCI_ADDR(REGS_AP_APB_BASE, 0x3000) +#define REG_AP_APB_USB_PHY_TEST SCI_ADDR(REGS_AP_APB_BASE, 0x3004) +#define REG_AP_APB_USB_PHY_CTRL SCI_ADDR(REGS_AP_APB_BASE, 0x3008) +#define REG_AP_APB_APB_MISC_CTRL SCI_ADDR(REGS_AP_APB_BASE, 0x300C) + + + +/* bits definitions for register REG_AP_APB_APB_EB */ +#define BIT_INTC3_EB ( BIT(22) ) +#define BIT_INTC2_EB ( BIT(21) ) +#define BIT_INTC1_EB ( BIT(20) ) +#define BIT_INTC0_EB ( BIT(19) ) +#define BIT_AP_CKG_EB ( BIT(18) ) +#define BIT_UART4_EB ( BIT(17) ) +#define BIT_UART3_EB ( BIT(16) ) +#define BIT_UART2_EB ( BIT(15) ) +#define BIT_UART1_EB ( BIT(14) ) +#define BIT_UART0_EB ( BIT(13) ) +#define BIT_I2C4_EB ( BIT(12) ) +#define BIT_I2C3_EB ( BIT(11) ) +#define BIT_I2C2_EB ( BIT(10) ) +#define BIT_I2C1_EB ( BIT(9) ) +#define BIT_I2C0_EB ( BIT(8) ) +#define BIT_SPI2_EB ( BIT(7) ) +#define BIT_SPI1_EB ( BIT(6) ) +#define BIT_SPI0_EB ( BIT(5) ) +#define BIT_IIS3_EB ( BIT(4) ) +#define BIT_IIS2_EB ( BIT(3) ) +#define BIT_IIS1_EB ( BIT(2) ) +#define BIT_IIS0_EB ( BIT(1) ) +#define BIT_SIM0_EB ( BIT(0) ) + +/* bits definitions for register REG_AP_APB_APB_RST */ +#define BIT_INTC3_SOFT_RST ( BIT(22) ) +#define BIT_INTC2_SOFT_RST ( BIT(21) ) +#define BIT_INTC1_SOFT_RST ( BIT(20) ) +#define BIT_INTC0_SOFT_RST ( BIT(19) ) +#define BIT_CKG_SOFT_RST ( BIT(18) ) +#define BIT_UART4_SOFT_RST ( BIT(17) ) +#define BIT_UART3_SOFT_RST ( BIT(16) ) +#define BIT_UART2_SOFT_RST ( BIT(15) ) +#define BIT_UART1_SOFT_RST ( BIT(14) ) +#define BIT_UART0_SOFT_RST ( BIT(13) ) +#define BIT_I2C4_SOFT_RST ( BIT(12) ) +#define BIT_I2C3_SOFT_RST ( BIT(11) ) +#define BIT_I2C2_SOFT_RST ( BIT(10) ) +#define BIT_I2C1_SOFT_RST ( BIT(9) ) +#define BIT_I2C0_SOFT_RST ( BIT(8) ) +#define BIT_SPI2_SOFT_RST ( BIT(7) ) +#define BIT_SPI1_SOFT_RST ( BIT(6) ) +#define BIT_SPI0_SOFT_RST ( BIT(5) ) +#define BIT_IIS3_SOFT_RST ( BIT(4) ) +#define BIT_IIS2_SOFT_RST ( BIT(3) ) +#define BIT_IIS1_SOFT_RST ( BIT(2) ) +#define BIT_IIS0_SOFT_RST ( BIT(1) ) +#define BIT_SIM0_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_AP_APB_USB_PHY_TUNE */ +#define BITS_OTGTUNE(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_COMPDISTUNE(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BIT_TXPREEMPPULSETUNE ( BIT(20) ) +#define BITS_TXRESTUNE(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_TXHSXVTUNE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_TXVREFTUNE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_TXPREEMPAMPTUNE(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_TXRISETUNE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_TXFSLSTUNE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_SQRXTUNE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AP_APB_USB_PHY_TEST */ +#define BIT_ATERESET ( BIT(31) ) +#define BIT_VBUS_VALID_EXT_SEL ( BIT(26) ) +#define BIT_VBUS_VALID_EXT ( BIT(25) ) +#define BIT_OTGDISABLE ( BIT(24) ) +#define BIT_TESTBURNIN ( BIT(21) ) +#define BIT_LOOPBACKENB ( BIT(20) ) +#define BITS_TESTDATAOUT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_VATESTENB(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) ) +#define BIT_TESTCLK ( BIT(13) ) +#define BIT_TESTDATAOUTSEL ( BIT(12) ) +#define BITS_TESTADDR(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_TESTDATAIN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_AP_APB_USB_PHY_CTRL */ +#define BITS_SS_SCALEDOWNMODE(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BIT_TXBITSTUFFENH ( BIT(23) ) +#define BIT_TXBITSTUFFEN ( BIT(22) ) +#define BIT_DMPULLDOWN ( BIT(21) ) +#define BIT_DPPULLDOWN ( BIT(20) ) +#define BIT_DMPULLUP ( BIT(9) ) +#define BIT_COMMONONN ( BIT(8) ) +#define BITS_REFCLKSEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_FSEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AP_APB_APB_MISC_CTRL */ +#define BIT_SIM_CLK_POLARITY ( BIT(1) ) +#define BIT_FMARK_POLARITY_INV ( BIT(0) ) + +#endif diff --git a/include/soc/sprd/chip_x30g/__regs_ap_clk.h b/include/soc/sprd/chip_x30g/__regs_ap_clk.h new file mode 100644 index 00000000..4ee29303 --- /dev/null +++ b/include/soc/sprd/chip_x30g/__regs_ap_clk.h @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __REGS_AP_CLK_H__ +#define __REGS_AP_CLK_H__ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, include <mach/sci_glb_regs.h>" +#endif + +#define REGS_AP_CLK + +/* registers definitions for controller REGS_AP_CLK */ +#define REG_AP_CLK_AP_AHB_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0020) +#define REG_AP_CLK_AP_APB_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0024) +#define REG_AP_CLK_GSP_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0028) +#define REG_AP_CLK_DISPC0_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x002c) +#define REG_AP_CLK_DISPC0_DBI_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0030) +#define REG_AP_CLK_DISPC0_DPI_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0034) +#define REG_AP_CLK_DISPC1_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0038) +#define REG_AP_CLK_DISPC1_DBI_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x003c) +#define REG_AP_CLK_DISPC1_DPI_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0040) +#define REG_AP_CLK_NFC_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0044) +#define REG_AP_CLK_SDIO0_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0048) +#define REG_AP_CLK_SDIO1_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x004c) +#define REG_AP_CLK_SDIO2_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0050) +#define REG_AP_CLK_EMMC_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0054) +#define REG_AP_CLK_GPS_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0058) +#define REG_AP_CLK_GPS_TCXO_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x005c) +#define REG_AP_CLK_USB_REF_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0060) +#define REG_AP_CLK_UART0_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0064) +#define REG_AP_CLK_UART1_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0068) +#define REG_AP_CLK_UART2_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x006c) +#define REG_AP_CLK_UART3_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0070) +#define REG_AP_CLK_UART4_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0074) +#define REG_AP_CLK_I2C0_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0078) +#define REG_AP_CLK_I2C1_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x007c) +#define REG_AP_CLK_I2C2_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0080) +#define REG_AP_CLK_I2C3_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0084) +#define REG_AP_CLK_I2C4_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0088) +#define REG_AP_CLK_SPI0_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x008c) +#define REG_AP_CLK_SPI1_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0090) +#define REG_AP_CLK_SPI2_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0094) +#define REG_AP_CLK_IIS0_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0098) +#define REG_AP_CLK_IIS1_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x009c) +#define REG_AP_CLK_IIS2_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x00a0) +#define REG_AP_CLK_IIS3_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x00a4) + +/* vars definitions for controller REGS_AP_CLK */ + +#endif //__REGS_AP_CLK_H__ diff --git a/include/soc/sprd/chip_x30g/__regs_apb_rf_cp2.h b/include/soc/sprd/chip_x30g/__regs_apb_rf_cp2.h new file mode 100644 index 00000000..edddb5f5 --- /dev/null +++ b/include/soc/sprd/chip_x30g/__regs_apb_rf_cp2.h @@ -0,0 +1,454 @@ +/*
+ * Copyright (C) 2014 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+#ifndef __SCI_GLB_REGS_H__
+#error "Don't include this file directly, Pls include sci_glb_regs.h"
+#endif
+
+
+#ifndef __H_REGS_APB_RF_CP2_HEADFILE_H__
+#define __H_REGS_APB_RF_CP2_HEADFILE_H__ __FILE__
+
+#define REGS_APB_RF_CP2
+
+/* registers definitions for APB_RF_CP2 */
+#define REG_APB_RF_CP2_APB_RST SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0000)
+#define REG_APB_RF_CP2_MCU_SOFT_RST SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0004)
+#define REG_APB_RF_CP2_APB_EB SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0018)
+#define REG_APB_RF_CP2_APB_EB1 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x001C)
+#define REG_APB_RF_CP2_APB_CLK_CTL0 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0020)
+#define REG_APB_RF_CP2_APB_CLK_CTL1 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0024)
+#define REG_APB_RF_CP2_APB_SLP_CTL0 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0030)
+#define REG_APB_RF_CP2_APB_INT_STS0 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0034)
+#define REG_APB_RF_CP2_APB_INT_SET_CLR0 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0038)
+#define REG_APB_RF_CP2_WIFI_BUF_BASE SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x003C)
+#define REG_APB_RF_CP2_CLK_TOP_CTRL0 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0040)
+#define REG_APB_RF_CP2_CLK_TOP_CTRL1 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0044)
+#define REG_APB_RF_CP2_FPGADEBUG SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0048)
+#define REG_APB_RF_CP2_APB_BT_DAC_CTR0 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0050)
+#define REG_APB_RF_CP2_APB_BT_DAC_CTR1 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0054)
+#define REG_APB_RF_CP2_APB_BT_DAC_CTR2 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0058)
+#define REG_APB_RF_CP2_APB_BT_DAC_STS0 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x005C)
+#define REG_APB_RF_CP2_APB_BT_DAC_STS1 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0060)
+#define REG_APB_RF_CP2_APB_BT_ADC_CTR0 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0064)
+#define REG_APB_RF_CP2_APB_BT_ADC_CTR1 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0068)
+#define REG_APB_RF_CP2_APB_BT_ADC_CTR2 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x006C)
+#define REG_APB_RF_CP2_WIFI_SYS0 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0070)
+#define REG_APB_RF_CP2_WIFI_SYS1 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0074)
+#define REG_APB_RF_CP2_APB_WIFI_ADC_CTR0 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0078)
+#define REG_APB_RF_CP2_APB_WIFI_ADC_CTR1 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x007C)
+#define REG_APB_RF_CP2_ARM7_RDATA_FROM_ARM9 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0080)
+#define REG_APB_RF_CP2_ARM7_WDATA_TO_ARM9 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0084)
+#define REG_APB_RF_CP2_CP2_BB_CTRL SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0088)
+#define REG_APB_RF_CP2_WIFI_BT_CFG0 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0090)
+#define REG_APB_RF_CP2_WIFI_BT_CFG1 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0094)
+#define REG_APB_RF_CP2_WIFI_BT_CFG2 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0098)
+#define REG_APB_RF_CP2_WIFI_BT_CFG3 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x009C)
+#define REG_APB_RF_CP2_WIFI_DFT_CTRTL0 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00A0)
+#define REG_APB_RF_CP2_WIFI_DFT_CTRTL1 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00A4)
+#define REG_APB_RF_CP2_WIFI_DFT_CTRTL2 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00A8)
+#define REG_APB_RF_CP2_WB_ADA_CTRTL0 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00B0)
+#define REG_APB_RF_CP2_WB_ADA_CTRTL1 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00B4)
+#define REG_APB_RF_CP2_WB_ADA_CTRTL2 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00B8)
+#define REG_APB_RF_CP2_WB_ADA_CTRTL3 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00BC)
+#define REG_APB_RF_CP2_WB_ADA_RESULT0 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00C0)
+#define REG_APB_RF_CP2_WB_ADA_RESULT1 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00C4)
+#define REG_APB_RF_CP2_WB_ADA_RESULT2 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00C8)
+#define REG_APB_RF_CP2_WB_ADA_RESULT3 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00CC)
+#define REG_APB_RF_CP2_WB_DBG_RESULT0 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00D0)
+#define REG_APB_RF_CP2_WB_DBG_RESULT1 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00D4)
+#define REG_APB_RF_CP2_WB_DAC_DBG_DAT SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00D8)
+#define REG_APB_RF_CP2_BT_FUNC_DBG SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00DC)
+#define REG_APB_RF_CP2_APB_ARCH_PORT SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0100)
+#define REG_APB_RF_CP2_IN_AXI_ADDR SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0104)
+#define REG_APB_RF_CP2_IN_CFG_SIZE SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0108)
+#define REG_APB_RF_CP2_APB_MISC_CTL SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0200)
+#define REG_APB_RF_CP2_APB_MISC_CTL1 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0204)
+#define REG_APB_RF_CP2_WIFI_SARADC_CTRL0 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0208)
+#define REG_APB_RF_CP2_WIFI_SARADC_CTRL1 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x020C)
+#define REG_APB_RF_CP2_BT_SARADC_CTRL1 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0210)
+#define REG_APB_RF_CP2_BT_SARADC_CTRL2 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0214)
+#define REG_APB_RF_CP2_WBT_DAC_CTRL0 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0218)
+#define REG_APB_RF_CP2_WBT_ANA_STS0 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x022C)
+#define REG_APB_RF_CP2_WBT_ANA_STS1 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0230)
+#define REG_APB_RF_CP2_WIFI_CTRL0 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0234)
+#define REG_APB_RF_CP2_WIFI_DAC_DFT SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0238)
+#define REG_APB_RF_CP2_WIFI_ADC_DFT SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x023C)
+
+
+
+/* bits definitions for register REG_APB_RF_CP2_APB_RST */
+#define BIT_PHY_SOFT_RST ( BIT(20) )
+#define BIT_MAC_SOFT_RST ( BIT(19) )
+#define BIT_GPIO_SOFT_RST ( BIT(18) )
+#define BIT_ADI_SOFT_RST ( BIT(17) )
+#define BIT_VBC_SOFT_RST ( BIT(16) )
+#define BIT_AUD_SOFT_RST ( BIT(15) )
+#define BIT_VPU_SOFT_RST ( BIT(14) )
+#define BIT_FM_SOFT_RST ( BIT(13) )
+#define BIT_IPI_SOFT_RST ( BIT(12) )
+#define BIT_WIFI_SOFT_RST ( BIT(11) )
+#define BIT_IIS_SOFT_RST ( BIT(10) )
+#define BIT_EIC_SOFT_RST ( BIT(9) )
+#define BIT_BT_SOFT_RST ( BIT(8) )
+#define BIT_WDG_SOFT_RST ( BIT(7) )
+#define BIT_TMR1_SOFT_RST ( BIT(6) )
+#define BIT_TMR0_SOFT_RST ( BIT(5) )
+#define BIT_SYST_SOFT_RST ( BIT(4) )
+#define BIT_UART1_SOFT_RST ( BIT(3) )
+#define BIT_UART0_SOFT_RST ( BIT(2) )
+
+/* bits definitions for register REG_APB_RF_CP2_MCU_SOFT_RST */
+#define BIT_MCU_SOFT_RST_SET ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_EB */
+#define BIT_GPIO_EB ( BIT(24) )
+#define BIT_ADI_EB ( BIT(23) )
+#define BIT_VBC_EB ( BIT(22) )
+#define BIT_AUD_EB ( BIT(21) )
+#define BIT_VPU_EB ( BIT(20) )
+#define BIT_FM_EB ( BIT(19) )
+#define BIT_IPI_EB ( BIT(18) )
+#define BIT_WIFI_EB ( BIT(17) )
+#define BIT_IIS_EB ( BIT(16) )
+#define BIT_EIC_RTCDV5_EB ( BIT(15) )
+#define BIT_EIC_EB ( BIT(14) )
+#define BIT_BT_RTC_EB ( BIT(13) )
+#define BIT_TMR1_RTC_EB ( BIT(12) )
+#define BIT_TMR0_RTC_EB ( BIT(11) )
+#define BIT_SYST_RTC_EB ( BIT(10) )
+#define BIT_WDG_RTC_EB ( BIT(9) )
+#define BIT_BT_EB ( BIT(8) )
+#define BIT_WDG_EB ( BIT(7) )
+#define BIT_TMR1_EB ( BIT(6) )
+#define BIT_TMR0_EB ( BIT(5) )
+#define BIT_SYST_EB ( BIT(4) )
+#define BIT_UART1_EB ( BIT(3) )
+#define BIT_UART0_EB ( BIT(2) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_EB1 */
+#define BIT_APB_ARCH_RTC_EB ( BIT(1) )
+#define BIT_APB_ARCH_EB ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_CLK_CTL0 */
+#define BITS_CLK_WTDAC_CTRL(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_CLK_BT_26M_SRC_SEL ( BIT(19) )
+#define BITS_CLK_BT_DA_SEL(_X_) ( (_X_) << 17 & (BIT(17)|BIT(18)) )
+#define BITS_CLK_BT_AD_SEL(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)) )
+#define BITS_CLK_UART0_SEL(_X_) ( (_X_) << 13 & (BIT(13)|BIT(14)) )
+#define BIT_CLK_BT_26M_SEL ( BIT(12) )
+#define BIT_CLK_BT_24M_SEL ( BIT(11) )
+#define BITS_CLK_IIS_SEL(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)) )
+#define BITS_CLK_VPU_SEL(_X_) ( (_X_) << 7 & (BIT(7)|BIT(8)) )
+#define BITS_CLK_UART1_SEL(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)) )
+#define BIT_CLK_WIFI_120M_EN ( BIT(4) )
+#define BIT_CLK_WIFI_26M_EN ( BIT(3) )
+#define BIT_CLK_WIFI_80M_EN ( BIT(2) )
+#define BIT_CLK_WIFI_44M_EN ( BIT(1) )
+#define BIT_CLK_WIFI_40M_EN ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_CLK_CTL1 */
+#define BITS_CLK_IIS_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_SLP_CTL0 */
+#define BIT_APB_FORCE_ON ( BIT(2) )
+#define BIT_APB_FORCE_SLEEP ( BIT(1) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_INT_STS0 */
+#define BIT_ARM9_FRQ ( BIT(3) )
+#define BIT_ARM9_IRQ ( BIT(2) )
+#define BIT_ARM7_MCU_FRQ ( BIT(1) )
+#define BIT_ARM7_MCU_IRQ ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_INT_SET_CLR0 */
+#define BIT_ARM9_FRQ_CLR ( BIT(3) )
+#define BIT_ARM9_IRQ_CLR ( BIT(2) )
+#define BIT_ARM7_MCU_FRQ_SET ( BIT(1) )
+#define BIT_ARM7_MCU_IRQ_SET ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_BUF_BASE */
+#define BITS_WIFI_BUF_BASE(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_CLK_TOP_CTRL0 */
+#define BITS_CLK_TOP_CTRL0(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_CLK_TOP_CTRL1 */
+#define BITS_CLK_TOP_CTRL1(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_FPGADEBUG */
+#define BITS_FPGADEBUG(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_APB_BT_DAC_CTR0 */
+#define BITS_BT_DAC_BG_CTR(_X_) ( (_X_) << 30 & (BIT(30)|BIT(31)) )
+#define BIT_BT_DAC_EN_ADC ( BIT(26) )
+#define BIT_BT_DAC_CLK_SEL ( BIT(25) )
+#define BIT_BT_DAC_EN_MIDRANGE ( BIT(24) )
+#define BITS_BT_DAC_Q_DC(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_BT_DAC_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_BT_DAC_CTR1 */
+#define BITS_BT_DAC_SEL(_X_) ( (_X_) << 29 & (BIT(29)|BIT(30)) )
+#define BIT_BT_DAC_BOOSTI_EN ( BIT(28) )
+#define BITS_BT_DAC_CFG(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)|BIT(27)) )
+#define BIT_BT_DAC_CAL_CLK_SEL ( BIT(24) )
+#define BIT_BT_DAC_PD ( BIT(23) )
+#define BITS_BT_DAC_WADDR_OVR(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)|BIT(22)) )
+#define BIT_BT_DAC_WLE_OVR ( BIT(18) )
+#define BITS_BT_DAC_WD_OVR(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)) )
+#define BIT_BT_DAC_W_OVR_I_QN ( BIT(1) )
+#define BIT_BT_DAC_W_OVR_EN ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_BT_DAC_CTR2 */
+#define BIT_BB_BG_EN ( BIT(21) )
+#define BIT_BB_LDO_EN ( BIT(20) )
+#define BIT_BT_DAC_OVR_EN_CAL ( BIT(19) )
+#define BIT_BT_DAC_EN_OOSCAL ( BIT(18) )
+#define BIT_BT_DAC_IQ_SWAP ( BIT(17) )
+#define BIT_BT_DAC_CAL_START ( BIT(16) )
+#define BITS_BT_DAC_OFFSETI(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_BT_DAC_OFFSETQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_BT_DAC_STS0 */
+#define BITS_BT_DAC_WTI(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_BT_DAC_WTQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_BT_DAC_STS1 */
+#define BITS_BT_DAC_DA_STATE(_X_) ( (_X_) << 17 & (BIT(17)|BIT(18)) )
+#define BIT_BT_DAC_DONE ( BIT(16) )
+#define BITS_BT_DAC_WQ_OVR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_BT_ADC_CTR0 */
+#define BITS_BT_ADC_SARSPD(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) )
+#define BITS_BT_ADC_CMPSPD(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) )
+#define BITS_BT_ADC_ADJ(_X_) ( (_X_) << 7 & (BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)) )
+#define BITS_BT_ADC_REFBIAS(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) )
+#define BITS_BT_ADC_CMPBIAS(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BIT_BT_ADC_MODE ( BIT(1) )
+#define BIT_BT_ADC_EN ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_BT_ADC_CTR1 */
+#define BIT_BT_ADC_CAL ( BIT(18) )
+#define BITS_BT_ADC_DUTY(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) )
+#define BITS_BT_ADC_DLL_D(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BIT_BT_ADC_DLL_RD ( BIT(8) )
+#define BIT_BT_ADC_DLL_SUG ( BIT(7) )
+#define BITS_BT_ADC_DLL_SET(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) )
+#define BIT_BT_ADC_DLL_OVR ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_BT_ADC_CTR2 */
+#define BITS_BT_PTA_SL(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BIT_BT_CTRL ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_SYS0 */
+#define BITS_WIFIMAB_CTRL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_WIFISAB_CTRL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_SYS1 */
+#define BITS_WIFIMAB_STS(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_WIFISAB_STS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_WIFI_ADC_CTR0 */
+#define BITS_WIFI_ADC_SARSPD(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) )
+#define BITS_WIFI_ADC_CMPSPD(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) )
+#define BITS_WIFI_ADC_ADJ(_X_) ( (_X_) << 7 & (BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)) )
+#define BITS_WIFI_ADC_REFBIAS(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) )
+#define BITS_WIFI_ADC_CMPBIAS(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BIT_WIFI_ADC_MODE ( BIT(1) )
+#define BIT_WIFI_ADC_EN ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_WIFI_ADC_CTR1 */
+#define BIT_WIFI_ADC_CAL ( BIT(18) )
+#define BITS_WIFI_ADC_DUTY(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) )
+#define BITS_WIFI_ADC_DLL_D(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BIT_WIFI_ADC_DLL_RD ( BIT(8) )
+#define BIT_WIFI_ADC_DLL_SUG ( BIT(7) )
+#define BITS_WIFI_ADC_DLL_SET(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) )
+#define BIT_WIFI_ADC_DLL_OVR ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_ARM7_RDATA_FROM_ARM9 */
+#define BITS_ARM7_RDATA_FROM_ARM9(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_ARM7_WDATA_TO_ARM9 */
+#define BITS_ARM7_WDATA_TO_ARM9(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_CP2_BB_CTRL */
+#define BITS_BB_LOCAL_CTRL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_BT_CFG0 */
+#define BITS_WIFI_BT_CFG0(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_BT_CFG1 */
+#define BITS_WIFI_BT_CFG1(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_BT_CFG2 */
+#define BITS_WIFI_BT_CFG2(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_BT_CFG3 */
+#define BITS_WIFI_BT_CFG3(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_DFT_CTRTL0 */
+#define BITS_WIFI_DFT_CTRTL0(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_DFT_CTRTL1 */
+#define BITS_WIFI_DFT_CTRTL1(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_DFT_CTRTL2 */
+#define BITS_WIFI_DFT_CTRTL2(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WB_ADA_CTRTL0 */
+#define BITS_WB_ADA_CTRTL0(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WB_ADA_CTRTL1 */
+#define BITS_WB_ADA_CTRTL1(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WB_ADA_CTRTL2 */
+#define BITS_WB_ADA_CTRTL2(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WB_ADA_CTRTL3 */
+#define BITS_WB_ADA_CTRTL3(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WB_ADA_RESULT0 */
+#define BITS_WB_ADA_RESULT0(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WB_ADA_RESULT1 */
+#define BITS_WB_ADA_RESULT1(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WB_ADA_RESULT2 */
+#define BITS_WB_ADA_RESULT2(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WB_ADA_RESULT3 */
+#define BITS_WB_ADA_RESULT3(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WB_DBG_RESULT0 */
+#define BITS_WB_DBG_RESULT0(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WB_DBG_RESULT1 */
+#define BITS_WB_DBG_RESULT1(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WB_DAC_DBG_DAT */
+#define BITS_WBDAC_IQ_TEST_DAT(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_BT_FUNC_DBG */
+#define BITS_BT_FUNC_DBG(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_APB_ARCH_PORT */
+#define BIT_MCU_PROT_GLB ( BIT(16) )
+#define BITS_MCU_PROT_CHECK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_APB_RF_CP2_IN_AXI_ADDR */
+#define BITS_IN_AXI_ADDR(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_IN_CFG_SIZE */
+#define BITS_IN_CFG_SIZE(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_APB_MISC_CTL */
+#define BIT_FPGA_SPI_SEL ( BIT(16) )
+#define BIT_TEST_DBG_MODE3 ( BIT(10) )
+#define BIT_TEST_DBG_MODE2 ( BIT(9) )
+#define BIT_TEST_DBG_MODE1 ( BIT(8) )
+#define BIT_TEST_DBG_MODE0 ( BIT(7) )
+#define BIT_BT_MAHB_SLEEP_EN ( BIT(6) )
+#define BIT_DSP2BT_IND ( BIT(5) )
+#define BIT_ROM_CLK_FORCE_EN ( BIT(4) )
+#define BIT_ARM7_JTAG_EN ( BIT(3) )
+#define BITS_ARM7_CACHE_SIZE(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)) )
+#define BIT_ARM7_CACHE_EN ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_MISC_CTL1 */
+#define BITS_ARM7_HWRST1_REG(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_SARADC_CTRL0 */
+#define BIT_WIFI_SARAD_CLK_SEL ( BIT(26) )
+#define BIT_WIFI_SARAD_DEBUG_EN ( BIT(25) )
+#define BITS_WIFI_SARAD_CALADDR(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) )
+#define BIT_WIFI_SARAD_CALEN ( BIT(18) )
+#define BIT_WIFI_SARAD_CALRD ( BIT(17) )
+#define BIT_WIFI_SARAD_CAL_RSTN ( BIT(16) )
+#define BIT_WIFI_SARAD_DLLEN ( BIT(15) )
+#define BITS_WIFI_SARAD_DLLIN(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_WIFI_SARAD_DLLOOF(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) )
+#define BIT_WIFI_SARAD_DLLRD ( BIT(2) )
+#define BIT_WIFI_SARAD_DLLWR ( BIT(1) )
+#define BIT_WIFI_SARAD_DLL_RSTN ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_SARADC_CTRL1 */
+#define BITS_WIFI_SARAD_QUANT_BOOST(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) )
+#define BITS_WIFI_SARAD_VREF_BOOST(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) )
+#define BITS_WIFI_SARAD_VREF_SEL(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) )
+#define BITS_WIFI_SARAD_BIT_SEL(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) )
+#define BITS_WIFI_SARAD_DELAY_CAP(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) )
+#define BIT_WIFI_SARAD_VCM_SEL ( BIT(18) )
+#define BIT_WIFI_SARAD_DIG_CLK_SEL ( BIT(17) )
+#define BIT_WIFI_SARAD_CAL ( BIT(16) )
+#define BITS_WIFI_SARAD_RESERVE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_APB_RF_CP2_BT_SARADC_CTRL1 */
+#define BIT_BT_SARAD_PD ( BIT(27) )
+#define BIT_BT_SARAD_ADCS_EN ( BIT(26) )
+#define BIT_BT_SARAD_DEBUG_EN ( BIT(25) )
+#define BITS_BT_SARAD_CALADDR(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) )
+#define BIT_BT_SARAD_CALEN ( BIT(18) )
+#define BIT_BT_SARAD_CALRD ( BIT(17) )
+#define BIT_BT_SARAD_CAL_RSTN ( BIT(16) )
+#define BIT_BT_SARAD_DLLEN ( BIT(15) )
+#define BITS_BT_SARAD_DLLIN(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_BT_SARAD_DLLOOF(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) )
+#define BIT_BT_SARAD_DLLRD ( BIT(2) )
+#define BIT_BT_SARAD_DLLWR ( BIT(1) )
+#define BIT_BT_SARAD_DLL_RSTN ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_BT_SARADC_CTRL2 */
+#define BITS_BT_SARAD_QUANT_BOOST(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) )
+#define BITS_BT_SARAD_VREF_BOOST(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) )
+#define BITS_BT_SARAD_VREF_SEL(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) )
+#define BITS_BT_SARAD_BIT_SEL(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) )
+#define BITS_BT_SARAD_DELAY_CAP(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) )
+#define BIT_BT_SARAD_VCM_SEL ( BIT(18) )
+#define BIT_BT_SARAD_DIG_CLK_SEL ( BIT(17) )
+#define BIT_BT_SARAD_CAL ( BIT(16) )
+#define BITS_BT_SARAD_RESERVE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_APB_RF_CP2_WBT_DAC_CTRL0 */
+#define BIT_WBT_DAC_SOFT_RST ( BIT(8) )
+#define BITS_WBT_DAC_PCTRL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) )
+#define BITS_WBT_DAC_RESERVE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_APB_RF_CP2_WBT_ANA_STS0 */
+#define BITS_WIFI_SARAD_CALRDOUT(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_WIFI_SARAD_DLL_OUT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+
+/* bits definitions for register REG_APB_RF_CP2_WBT_ANA_STS1 */
+#define BIT_WIFIPLL2_LOCK_DONE ( BIT(21) )
+#define BIT_WIFIPLL1_LOCK_DONE ( BIT(20) )
+#define BITS_BT_SARAD_CALRDOUT(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_BT_SARAD_DLL_OUT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_CTRL0 */
+#define BITS_WIFI_IN_CAP_SWT(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) )
+#define BITS_WIFI_SLEEP_CFG(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
+#define BIT_WB_EN_B_RG ( BIT(2) )
+#define BIT_WB_EN_A_RG ( BIT(1) )
+#define BIT_WB_EN_SEL ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_DAC_DFT */
+#define BITS_WIFI_DAC_DFT(_X_) (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_ADC_DFT */
+#define BITS_WIFI_ADC_DFT(_X_) (_X_)
+
+#endif
diff --git a/include/soc/sprd/chip_x30g/__regs_avs_apb.h b/include/soc/sprd/chip_x30g/__regs_avs_apb.h new file mode 100644 index 00000000..e5153c36 --- /dev/null +++ b/include/soc/sprd/chip_x30g/__regs_avs_apb.h @@ -0,0 +1,165 @@ +/*
+ * Copyright (C) 2014 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+#ifndef __SCI_GLB_REGS_H__
+#error "Don't include this file directly, Pls include sci_glb_regs.h"
+#endif
+
+
+#ifndef __H_REGS_AVS_APB_HEADFILE_H__
+#define __H_REGS_AVS_APB_HEADFILE_H__ __FILE__
+
+#define REGS_AVS_APB
+
+/* registers definitions for AVS_APB */
+#define REG_AVS_APB_AVS_TUNE_LMT_CFG SCI_ADDR(REGS_AVS_APB_BASE, 0x0000)
+#define REG_AVS_APB_AVS_TUNE_STATUS SCI_ADDR(REGS_AVS_APB_BASE, 0x0004)
+#define REG_AVS_APB_AVS_CFG SCI_ADDR(REGS_AVS_APB_BASE, 0x0008)
+#define REG_AVS_APB_AVS_TUNE_STEP_CFG SCI_ADDR(REGS_AVS_APB_BASE, 0x000C)
+#define REG_AVS_APB_AVS_WAIT_CFG SCI_ADDR(REGS_AVS_APB_BASE, 0x0010)
+#define REG_AVS_APB_AVS_INT_CFG SCI_ADDR(REGS_AVS_APB_BASE, 0x0014)
+#define REG_AVS_APB_AVS_START_SINGLE_ACT SCI_ADDR(REGS_AVS_APB_BASE, 0x0018)
+#define REG_AVS_APB_AVS_START_REPEAT_ACT SCI_ADDR(REGS_AVS_APB_BASE, 0x001C)
+#define REG_AVS_APB_AVS_HPM_EN SCI_ADDR(REGS_AVS_APB_BASE, 0x0020)
+#define REG_AVS_APB_AVS_HPM_RPT_ANLS SCI_ADDR(REGS_AVS_APB_BASE, 0x0024)
+#define REG_AVS_APB_AVS_HPM_RPT_VLD_STATUS_0 SCI_ADDR(REGS_AVS_APB_BASE, 0x0028)
+#define REG_AVS_APB_AVS_HPM_RPT_VLD_STATUS_1 SCI_ADDR(REGS_AVS_APB_BASE, 0x002C)
+#define REG_AVS_APB_AVS_HPM_RPT_VLD_STATUS_2 SCI_ADDR(REGS_AVS_APB_BASE, 0x0030)
+#define REG_AVS_APB_AVS_HPM_RPT_VLD_STATUS_3 SCI_ADDR(REGS_AVS_APB_BASE, 0x0034)
+#define REG_AVS_APB_AVS_HPM_DLY_WIND_SEL SCI_ADDR(REGS_AVS_APB_BASE, 0x0038)
+#define REG_AVS_APB_FSM_STS SCI_ADDR(REGS_AVS_APB_BASE, 0x0040)
+
+
+
+/* bits definitions for register REG_AVS_APB_AVS_TUNE_LMT_CFG */
+#define BITS_VOLT_TUNE_VAL_MAX(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_VOLT_TUNE_VAL_MIN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_AVS_APB_AVS_TUNE_STATUS */
+#define BITS_VOLT_TUNE_VAL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_VOLT_OBS_VAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_AVS_APB_AVS_CFG */
+#define BIT_HPM15_RPT_CHKSUM_ERR_EN ( BIT(31) )
+#define BIT_HPM14_RPT_CHKSUM_ERR_EN ( BIT(30) )
+#define BIT_HPM13_RPT_CHKSUM_ERR_EN ( BIT(29) )
+#define BIT_HPM12_RPT_CHKSUM_ERR_EN ( BIT(28) )
+#define BIT_HPM11_RPT_CHKSUM_ERR_EN ( BIT(27) )
+#define BIT_HPM10_RPT_CHKSUM_ERR_EN ( BIT(26) )
+#define BIT_HPM9_RPT_CHKSUM_ERR_EN ( BIT(25) )
+#define BIT_HPM8_RPT_CHKSUM_ERR_EN ( BIT(24) )
+#define BIT_HPM7_RPT_CHKSUM_ERR_EN ( BIT(23) )
+#define BIT_HPM6_RPT_CHKSUM_ERR_EN ( BIT(22) )
+#define BIT_HPM5_RPT_CHKSUM_ERR_EN ( BIT(21) )
+#define BIT_HPM4_RPT_CHKSUM_ERR_EN ( BIT(20) )
+#define BIT_HPM3_RPT_CHKSUM_ERR_EN ( BIT(19) )
+#define BIT_HPM2_RPT_CHKSUM_ERR_EN ( BIT(18) )
+#define BIT_HPM1_RPT_CHKSUM_ERR_EN ( BIT(17) )
+#define BIT_HPM0_RPT_CHKSUM_ERR_EN ( BIT(16) )
+#define BIT_PAUSE_OCCUR_ERR_EN ( BIT(8) )
+#define BIT_VOLT_TUNE_FORBIDEN ( BIT(4) )
+#define BIT_VOLT_OBS_FORBIDEN ( BIT(0) )
+
+/* bits definitions for register REG_AVS_APB_AVS_TUNE_STEP_CFG */
+#define BITS_VOLT_TUNE_DOWN_STEP(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) )
+#define BITS_VOLT_TUNE_UP_STEP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) )
+
+/* bits definitions for register REG_AVS_APB_AVS_WAIT_CFG */
+#define BITS_RND_INTVAL_WAIT_NUM(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_VOLT_STB_WAIT_NUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_AVS_APB_AVS_INT_CFG */
+#define BIT_INT_RPT_FORMAT_ERR_CLR ( BIT(14) )
+#define BIT_INT_RPT_ANLS_ERR_CLR ( BIT(13) )
+#define BIT_INT_VOLT_TUNE_ERR_CLR ( BIT(12) )
+#define BIT_INT_RPT_FORMAT_ERR_MASK_STATUS ( BIT(10) )
+#define BIT_INT_RPT_ANLS_ERR_MASK_STATUS ( BIT(9) )
+#define BIT_INT_VOLT_TUNE_ERR_MASK_STATUS ( BIT(8) )
+#define BIT_INT_RPT_FORMAT_ERR_RAW_STATUS ( BIT(6) )
+#define BIT_INT_RPT_ANLS_ERR_RAW_STATUS ( BIT(5) )
+#define BIT_INT_VOLT_TUNE_ERR_RAW_STATUS ( BIT(4) )
+#define BIT_INT_RPT_FORMAT_ERR_EN ( BIT(2) )
+#define BIT_INT_RPT_ANLS_ERR_EN ( BIT(1) )
+#define BIT_INT_VOLT_TUNE_ERR_EN ( BIT(0) )
+
+/* bits definitions for register REG_AVS_APB_AVS_START_SINGLE_ACT */
+#define BIT_AVS_START_SINGLE_ACT ( BIT(0) )
+
+/* bits definitions for register REG_AVS_APB_AVS_START_REPEAT_ACT */
+#define BIT_AVS_START_REPEAT_ACT ( BIT(0) )
+
+/* bits definitions for register REG_AVS_APB_AVS_HPM_EN */
+#define BIT_HPM15_EN ( BIT(15) )
+#define BIT_HPM14_EN ( BIT(14) )
+#define BIT_HPM13_EN ( BIT(13) )
+#define BIT_HPM12_EN ( BIT(12) )
+#define BIT_HPM11_EN ( BIT(11) )
+#define BIT_HPM10_EN ( BIT(10) )
+#define BIT_HPM9_EN ( BIT(9) )
+#define BIT_HPM8_EN ( BIT(8) )
+#define BIT_HPM7_EN ( BIT(7) )
+#define BIT_HPM6_EN ( BIT(6) )
+#define BIT_HPM5_EN ( BIT(5) )
+#define BIT_HPM4_EN ( BIT(4) )
+#define BIT_HPM3_EN ( BIT(3) )
+#define BIT_HPM2_EN ( BIT(2) )
+#define BIT_HPM1_EN ( BIT(1) )
+#define BIT_HPM0_EN ( BIT(0) )
+
+/* bits definitions for register REG_AVS_APB_AVS_HPM_RPT_ANLS */
+#define BITS_HPM_RPT_FF_ANLS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_HPM_RPT_7F_ANLS(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) )
+#define BITS_HPM_RPT_3F_ANLS(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) )
+#define BITS_HPM_RPT_1F_ANLS(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
+#define BITS_HPM_RPT_0F_ANLS(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_HPM_RPT_07_ANLS(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) )
+#define BITS_HPM_RPT_03_ANLS(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_HPM_RPT_01_ANLS(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_HPM_RPT_00_ANLS(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_AVS_APB_AVS_HPM_RPT_VLD_STATUS_0 */
+#define BITS_HPM3_RPT_VLD(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_HPM2_RPT_VLD(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_HPM1_RPT_VLD(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_HPM0_RPT_VLD(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_AVS_APB_AVS_HPM_RPT_VLD_STATUS_1 */
+#define BITS_HPM7_RPT_VLD(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_HPM6_RPT_VLD(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_HPM5_RPT_VLD(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_HPM4_RPT_VLD(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_AVS_APB_AVS_HPM_RPT_VLD_STATUS_2 */
+#define BITS_HPM11_RPT_VLD(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_HPM10_RPT_VLD(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_HPM9_RPT_VLD(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_HPM8_RPT_VLD(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_AVS_APB_AVS_HPM_RPT_VLD_STATUS_3 */
+#define BITS_HPM15_RPT_VLD(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_HPM14_RPT_VLD(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_HPM13_RPT_VLD(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_HPM12_RPT_VLD(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_AVS_APB_AVS_HPM_DLY_WIND_SEL */
+#define BITS_DLY_WIND_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_AVS_APB_FSM_STS */
+#define BITS_AVS_FSM_STS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+#endif
diff --git a/include/soc/sprd/chip_x30g/__regs_codec_ahb.h b/include/soc/sprd/chip_x30g/__regs_codec_ahb.h new file mode 100644 index 00000000..14235fd7 --- /dev/null +++ b/include/soc/sprd/chip_x30g/__regs_codec_ahb.h @@ -0,0 +1,58 @@ +/* the head file modifier: ang 2015-01-21 14:34:02*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_CODEC_AHB_HEADFILE_H__ +#define __H_REGS_CODEC_AHB_HEADFILE_H__ __FILE__ + +#define REGS_CODEC_AHB + +/* registers definitions for CODEC_AHB */ +#define REG_CODEC_AHB_AHB_RST SCI_ADDR(REGS_CODEC_AHB_BASE, 0x0000)/*AHB_RST*/ +#define REG_CODEC_AHB_CKG_ENABLE SCI_ADDR(REGS_CODEC_AHB_BASE, 0x0004)/*CKG_ENABLE*/ +#define REG_CODEC_AHB_CLOCK_SEL SCI_ADDR(REGS_CODEC_AHB_BASE, 0x0008)/*CLOCK_SEL*/ +#define REG_CODEC_AHB_CODA7_STAT SCI_ADDR(REGS_CODEC_AHB_BASE, 0x000C)/*CODA7_STAT*/ + + + +/* bits definitions for register REG_CODEC_AHB_AHB_RST */ +#define BIT_CODA7_APB_SOFT_RST ( BIT(2) ) +#define BIT_CODA7_CC_SOFT_RST ( BIT(1) ) +#define BIT_CODA7_AXI_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_CODEC_AHB_CKG_ENABLE */ +#define BIT_CODA7_CKG_EN ( BIT(4) ) +#define BIT_CODA7_CC_CKG_EN ( BIT(1) ) +#define BIT_CODA7_AXI_CKG_EN ( BIT(0) ) + +/* bits definitions for register REG_CODEC_AHB_CLOCK_SEL */ +#define BITS_CLK_CODA7_AXI_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_CLK_CODA7_CC_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CLK_CODA7_APB_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CODEC_AHB_CODA7_STAT */ +#define BIT_CODA7_RUN ( BIT(1) ) +#define BIT_CODA7_IDLE ( BIT(0) ) + +#endif diff --git a/include/soc/sprd/chip_x30g/__regs_cp_ahb_rf.h b/include/soc/sprd/chip_x30g/__regs_cp_ahb_rf.h new file mode 100644 index 00000000..1ed8bbcd --- /dev/null +++ b/include/soc/sprd/chip_x30g/__regs_cp_ahb_rf.h @@ -0,0 +1,273 @@ +/*
+ * Copyright (C) 2014 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+#ifndef __SCI_GLB_REGS_H__
+#error "Don't include this file directly, Pls include sci_glb_regs.h"
+#endif
+
+
+#ifndef __H_REGS_CP_AHB_RF_HEADFILE_H__
+#define __H_REGS_CP_AHB_RF_HEADFILE_H__ __FILE__
+
+#define REGS_CP_AHB_RF
+
+/* registers definitions for CP_AHB_RF */
+#define REG_CP_AHB_RF_AHB_EB0_STS SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0008)
+#define REG_CP_AHB_RF_AHB_RST0_STS SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0014)
+#define REG_CP_AHB_RF_ARCH_EB SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0018)
+#define REG_CP_AHB_RF_AHB_REMAP SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x001C)
+#define REG_CP_AHB_RF_AHB_MISC_CTL SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0020)
+#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL0 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0024)
+#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL1 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0028)
+#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL2 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x002C)
+#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL3 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0030)
+#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL4 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0034)
+#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL5 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0038)
+#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL6 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x003C)
+#define REG_CP_AHB_RF_AHB_PAUSE SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0040)
+#define REG_CP_AHB_RF_AHB_SLP_CTL SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0044)
+#define REG_CP_AHB_RF_AHB_SLP_STS SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0048)
+#define REG_CP_AHB_RF_MCU_CLK_CTL SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x004C)
+#define REG_CP_AHB_RF_DSP_CTL SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0050)
+#define REG_CP_AHB_RF_DSP_BOOT_VECTOR SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0054)
+#define REG_CP_AHB_RF_DSP_RST SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0058)
+#define REG_CP_AHB_RF_DSP_JTAG_CTL SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x005C)
+#define REG_CP_AHB_RF_MCU_C2C_SEMA SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0060)
+#define REG_CP_AHB_RF_CHIP_ID SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x01FC)
+
+
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_EB0_STS */
+#define BIT_LZMA_EN ( BIT(11) )
+#define BIT_WCDMA_EN5 ( BIT(9) )
+#define BIT_WCDMA_EN4 ( BIT(8) )
+#define BIT_WCDMA_EN3 ( BIT(7) )
+#define BIT_WCDMA_EN2 ( BIT(6) )
+#define BIT_WCDMA_EN1 ( BIT(5) )
+#define BIT_WCDMA_EN0 ( BIT(4) )
+#define BIT_BUSMON2_EN ( BIT(3) )
+#define BIT_BUSMON1_EN ( BIT(2) )
+#define BIT_BUSMON0_EN ( BIT(1) )
+#define BIT_DMA_EN ( BIT(0) )
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_RST0_STS */
+#define BIT_LZMA_SOFT_RST ( BIT(8) )
+#define BIT_WSYS_SOFT_RST ( BIT(6) )
+#define BIT_ARM2_SOFT_RST ( BIT(5) )
+#define BIT_ARM1_SOFT_RST ( BIT(4) )
+#define BIT_BUSMON2_SOFT_RST ( BIT(3) )
+#define BIT_BUSMON1_SOFT_RST ( BIT(2) )
+#define BIT_BUSMON0_SOFT_RST ( BIT(1) )
+#define BIT_DMA_SOFT_RST ( BIT(0) )
+
+/* bits definitions for register REG_CP_AHB_RF_ARCH_EB */
+#define BIT_AHB_ARCH_EB ( BIT(0) )
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_REMAP */
+#define BIT_PTEST_FUNC_ATSPEED_SEL ( BIT(2) )
+#define BIT_PTEST_FUNC_MODE ( BIT(1) )
+#define BIT_REMAP ( BIT(0) )
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_MISC_CTL */
+#define BITS_LZMA_M_PROT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMA_W_PROT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMA_R_PROT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_MCU_SHM_CTRL(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) )
+#define BIT_RF_SWT_AUTO_EN ( BIT(1) )
+#define BIT_WCDMA_ASHB_EN ( BIT(0) )
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL0 */
+#define BITS_ARMMTX_M3TOS0_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_ARMMTX_M3TOS0_ADJ_EN ( BIT(27) )
+#define BIT_ARMMTX_M3TOS0_RND_EN ( BIT(26) )
+#define BITS_ARMMTX_M3TOS0_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
+#define BITS_ARMMTX_M2TOS0_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BIT_ARMMTX_M2TOS0_ADJ_EN ( BIT(19) )
+#define BIT_ARMMTX_M2TOS0_RND_EN ( BIT(18) )
+#define BITS_ARMMTX_M2TOS0_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_ARMMTX_M1TOS0_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BIT_ARMMTX_M1TOS0_ADJ_EN ( BIT(11) )
+#define BIT_ARMMTX_M1TOS0_RND_EN ( BIT(10) )
+#define BITS_ARMMTX_M1TOS0_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ARMMTX_M0TOS0_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_ARMMTX_M0TOS0_ADJ_EN ( BIT(3) )
+#define BIT_ARMMTX_M0TOS0_RND_EN ( BIT(2) )
+#define BITS_ARMMTX_M0TOS0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL1 */
+#define BITS_ARMMTX_M3TOS1_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_ARMMTX_M3TOS1_ADJ_EN ( BIT(27) )
+#define BIT_ARMMTX_M3TOS1_RND_EN ( BIT(26) )
+#define BITS_ARMMTX_M3TOS1_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
+#define BITS_ARMMTX_M2TOS1_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BIT_ARMMTX_M2TOS1_ADJ_EN ( BIT(19) )
+#define BIT_ARMMTX_M2TOS1_RND_EN ( BIT(18) )
+#define BITS_ARMMTX_M2TOS1_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_ARMMTX_M1TOS1_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BIT_ARMMTX_M1TOS1_ADJ_EN ( BIT(11) )
+#define BIT_ARMMTX_M1TOS1_RND_EN ( BIT(10) )
+#define BITS_ARMMTX_M1TOS1_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ARMMTX_M0TOS1_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_ARMMTX_M0TOS1_ADJ_EN ( BIT(3) )
+#define BIT_ARMMTX_M0TOS1_RND_EN ( BIT(2) )
+#define BITS_ARMMTX_M0TOS1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL2 */
+#define BITS_ARMMTX_M1TOS2_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_ARMMTX_M1TOS2_ADJ_EN ( BIT(27) )
+#define BIT_ARMMTX_M1TOS2_RND_EN ( BIT(26) )
+#define BITS_ARMMTX_M1TOS2_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
+#define BITS_ARMMTX_M0TOS2_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BIT_ARMMTX_M0TOS2_ADJ_EN ( BIT(19) )
+#define BIT_ARMMTX_M0TOS2_RND_EN ( BIT(18) )
+#define BITS_ARMMTX_M0TOS2_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_ARMMTX_M5TOS1_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BIT_ARMMTX_M5TOS1_ADJ_EN ( BIT(11) )
+#define BIT_ARMMTX_M5TOS1_RND_EN ( BIT(10) )
+#define BITS_ARMMTX_M5TOS1_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ARMMTX_M4TOS1_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_ARMMTX_M4TOS1_ADJ_EN ( BIT(3) )
+#define BIT_ARMMTX_M4TOS1_RND_EN ( BIT(2) )
+#define BITS_ARMMTX_M4TOS1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL3 */
+#define BITS_ARMMTX_M5TOS2_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_ARMMTX_M5TOS2_ADJ_EN ( BIT(27) )
+#define BIT_ARMMTX_M5TOS2_RND_EN ( BIT(26) )
+#define BITS_ARMMTX_M5TOS2_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
+#define BITS_ARMMTX_M5TOS4_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BIT_ARMMTX_M5TOS4_ADJ_EN ( BIT(19) )
+#define BIT_ARMMTX_M5TOS4_RND_EN ( BIT(18) )
+#define BITS_ARMMTX_M5TOS4_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_ARMMTX_M3TOS2_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BIT_ARMMTX_M3TOS2_ADJ_EN ( BIT(11) )
+#define BIT_ARMMTX_M3TOS2_RND_EN ( BIT(10) )
+#define BITS_ARMMTX_M3TOS2_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ARMMTX_M2TOS2_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_ARMMTX_M2TOS2_ADJ_EN ( BIT(3) )
+#define BIT_ARMMTX_M2TOS2_RND_EN ( BIT(2) )
+#define BITS_ARMMTX_M2TOS2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL4 */
+#define BITS_ARMMTX_M4TOS3_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BIT_ARMMTX_M4TOS3_ADJ_EN ( BIT(19) )
+#define BIT_ARMMTX_M4TOS3_RND_EN ( BIT(18) )
+#define BITS_ARMMTX_M4TOS3_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_ARMMTX_M1TOS3_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BIT_ARMMTX_M1TOS3_ADJ_EN ( BIT(11) )
+#define BIT_ARMMTX_M1TOS3_RND_EN ( BIT(10) )
+#define BITS_ARMMTX_M1TOS3_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ARMMTX_M0TOS3_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_ARMMTX_M0TOS3_ADJ_EN ( BIT(3) )
+#define BIT_ARMMTX_M0TOS3_RND_EN ( BIT(2) )
+#define BITS_ARMMTX_M0TOS3_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL5 */
+#define BITS_ARMMTX_M4TOS0_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_ARMMTX_M4TOS0_ADJ_EN ( BIT(27) )
+#define BIT_ARMMTX_M4TOS0_RND_EN ( BIT(26) )
+#define BITS_ARMMTX_M4TOS0_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
+#define BITS_ARMMTX_M4TOS4_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BIT_ARMMTX_M4TOS4_ADJ_EN ( BIT(19) )
+#define BIT_ARMMTX_M4TOS4_RND_EN ( BIT(18) )
+#define BITS_ARMMTX_M4TOS4_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_ARMMTX_M1TOS4_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BIT_ARMMTX_M1TOS4_ADJ_EN ( BIT(11) )
+#define BIT_ARMMTX_M1TOS4_RND_EN ( BIT(10) )
+#define BITS_ARMMTX_M1TOS4_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ARMMTX_M0TOS4_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_ARMMTX_M0TOS4_ADJ_EN ( BIT(3) )
+#define BIT_ARMMTX_M0TOS4_RND_EN ( BIT(2) )
+#define BITS_ARMMTX_M0TOS4_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL6 */
+#define BITS_ARMMTX_M3TOS5_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_ARMMTX_M3TOS5_ADJ_EN ( BIT(27) )
+#define BIT_ARMMTX_M3TOS5_RND_EN ( BIT(26) )
+#define BITS_ARMMTX_M3TOS5_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
+#define BITS_ARMMTX_M2TOS5_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BIT_ARMMTX_M2TOS5_ADJ_EN ( BIT(19) )
+#define BIT_ARMMTX_M2TOS5_RND_EN ( BIT(18) )
+#define BITS_ARMMTX_M2TOS5_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_ARMMTX_M1TOS5_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BIT_ARMMTX_M1TOS5_ADJ_EN ( BIT(11) )
+#define BIT_ARMMTX_M1TOS5_RND_EN ( BIT(10) )
+#define BITS_ARMMTX_M1TOS5_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ARMMTX_M0TOS5_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_ARMMTX_M0TOS5_ADJ_EN ( BIT(3) )
+#define BIT_ARMMTX_M0TOS5_RND_EN ( BIT(2) )
+#define BITS_ARMMTX_M0TOS5_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_PAUSE */
+#define BIT_MCU_LIGHT_SLEEP_EN ( BIT(4) )
+#define BIT_APB_SLEEP ( BIT(3) )
+#define BIT_MCU_DEEP_SLEEP_EN ( BIT(2) )
+#define BIT_MCU_SYS_SLEEP_EN ( BIT(1) )
+#define BIT_MCU_CORE_SLEEP ( BIT(0) )
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_SLP_CTL */
+#define BIT_ARM_DAHB_SLEEP_EN ( BIT(4) )
+#define BIT_MCUMTX_AUTO_GATE_EN ( BIT(3) )
+#define BIT_MCU_AUTO_GATE_EN ( BIT(2) )
+#define BIT_AHB_AUTO_GATE_EN ( BIT(1) )
+#define BIT_ARM_AUTO_GATE_EN ( BIT(0) )
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_SLP_STS */
+#define BIT_APB_PERI_SLEEP ( BIT(3) )
+#define BIT_DSP_MAHB_SLEEP_EN ( BIT(2) )
+#define BIT_DMA_BUSY ( BIT(1) )
+#define BIT_EMC_SLEEP ( BIT(0) )
+
+/* bits definitions for register REG_CP_AHB_RF_MCU_CLK_CTL */
+#define BITS_CLK_LZMA_SEL(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)) )
+#define BIT_CLK_CP_DBG_SEL ( BIT(21) )
+#define BIT_CLK_MCU_DBG_SEL ( BIT(20) )
+#define BITS_CLK_COM_DBG_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
+#define BITS_CLK_SYS_DBG_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_CLK_AHB_DIV(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_CLK_MCU_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) )
+#define BITS_CLK_APB_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_CLK_MCU_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
+
+/* bits definitions for register REG_CP_AHB_RF_DSP_CTL */
+#define BIT_ASHB_ARMTODSP_EN ( BIT(2) )
+#define BIT_FRC_CLK_DSP_EN ( BIT(1) )
+#define BIT_DSP_BOOT_EN ( BIT(0) )
+
+/* bits definitions for register REG_CP_AHB_RF_DSP_BOOT_VECTOR */
+#define BITS_DSP_BOOT_VECTOR(_X_) (_X_)
+
+/* bits definitions for register REG_CP_AHB_RF_DSP_RST */
+#define BIT_DSP_SYS_SRST ( BIT(1) )
+#define BIT_DSP_CORE_SRST_N ( BIT(0) )
+
+/* bits definitions for register REG_CP_AHB_RF_DSP_JTAG_CTL */
+#define BIT_CEVA_SW_JTAG_ENA ( BIT(8) )
+#define BIT_STDO ( BIT(4) )
+#define BIT_STCK ( BIT(3) )
+#define BIT_STMS ( BIT(2) )
+#define BIT_STDI ( BIT(1) )
+#define BIT_STRTCK ( BIT(0) )
+
+/* bits definitions for register REG_CP_AHB_RF_MCU_C2C_SEMA */
+#define BITS_MCU_C2C_SEMA(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_CP_AHB_RF_CHIP_ID */
+#define BITS_CHIP_ID(_X_) (_X_)
+
+#endif
diff --git a/include/soc/sprd/chip_x30g/__regs_cp_apb_rf.h b/include/soc/sprd/chip_x30g/__regs_cp_apb_rf.h new file mode 100644 index 00000000..37a4d057 --- /dev/null +++ b/include/soc/sprd/chip_x30g/__regs_cp_apb_rf.h @@ -0,0 +1,203 @@ +/*
+ * Copyright (C) 2014 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+#ifndef __SCI_GLB_REGS_H__
+#error "Don't include this file directly, Pls include sci_glb_regs.h"
+#endif
+
+
+#ifndef __H_REGS_CP_APB_RF_HEADFILE_H__
+#define __H_REGS_CP_APB_RF_HEADFILE_H__ __FILE__
+
+#define REGS_CP_APB_RF
+
+/* registers definitions for CP_APB_RF */
+#define REG_CP_APB_RF_APB_EB0_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0008)
+#define REG_CP_APB_RF_APB_RST0_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0014)
+#define REG_CP_APB_RF_APB_MCU_RST SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0018)
+#define REG_CP_APB_RF_APB_CLK_SEL0 SCI_ADDR(REGS_CP_APB_RF_BASE, 0x001C)
+#define REG_CP_APB_RF_APB_CLK_DIV0 SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0020)
+#define REG_CP_APB_RF_APB_ARCH_EB SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0024)
+#define REG_CP_APB_RF_APB_MISC_CTL0 SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0028)
+#define REG_CP_APB_RF_APB_MISC_CTL1 SCI_ADDR(REGS_CP_APB_RF_BASE, 0x002C)
+#define REG_CP_APB_RF_APB_PIN_SEL SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0040)
+#define REG_CP_APB_RF_APB_SLP_CTL SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0044)
+#define REG_CP_APB_RF_APB_WSYS_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0048)
+#define REG_CP_APB_RF_APB_SLP_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0050)
+#define REG_CP_APB_RF_APB_ROM_PD_CTL SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0054)
+#define REG_CP_APB_RF_APB_BUS_CTL0 SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0058)
+#define REG_CP_APB_RF_APB_DSP_INT_CLR SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0074)
+#define REG_CP_APB_RF_APB_MISC_INT_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0078)
+#define REG_CP_APB_RF_APB_HWRST SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0080)
+#define REG_CP_APB_RF_APB_ARM_BOOT_ADDR SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0084)
+
+
+
+/* bits definitions for register REG_CP_APB_RF_APB_EB0_STS */
+#define BIT_ADA_EB ( BIT(18) )
+#define BIT_RFFE_EB ( BIT(17) )
+#define BIT_EPT_EB ( BIT(16) )
+#define BIT_GPIO_EB ( BIT(15) )
+#define BIT_TMR_RTC_EB ( BIT(14) )
+#define BIT_TMR_EB ( BIT(13) )
+#define BIT_SYSTMR_RTC_EB ( BIT(12) )
+#define BIT_SYSTMR_EB ( BIT(11) )
+#define BIT_IIS3_EB ( BIT(10) )
+#define BIT_IIS2_EB ( BIT(9) )
+#define BIT_IIS1_EB ( BIT(8) )
+#define BIT_IIS0_EB ( BIT(7) )
+#define BIT_SIM2_EB ( BIT(6) )
+#define BIT_SIM1_EB ( BIT(5) )
+#define BIT_SIM0_EB ( BIT(4) )
+#define BIT_UART1_EB ( BIT(3) )
+#define BIT_UART0_EB ( BIT(2) )
+#define BIT_WDG_RTC_EB ( BIT(1) )
+#define BIT_WDG_EB ( BIT(0) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_RST0_STS */
+#define BIT_ADA_TX_SOFT_RST ( BIT(18) )
+#define BIT_ADA_RX_SOFT_RST ( BIT(17) )
+#define BIT_ADA_SOFT_RST ( BIT(16) )
+#define BIT_RFFE_SOFT_RST ( BIT(15) )
+#define BIT_MCU_DSP_RST ( BIT(14) )
+#define BIT_EPT_SOFT_RST ( BIT(13) )
+#define BIT_GPIO_SOFT_RST ( BIT(12) )
+#define BIT_TMR_SOFT_RST ( BIT(11) )
+#define BIT_SYSTMR_SOFT_RST ( BIT(10) )
+#define BIT_IIS3_SOFT_RST ( BIT(9) )
+#define BIT_IIS2_SOFT_RST ( BIT(8) )
+#define BIT_IIS1_SOFT_RST ( BIT(7) )
+#define BIT_IIS0_SOFT_RST ( BIT(6) )
+#define BIT_SIM2_SOFT_RST ( BIT(5) )
+#define BIT_SIM1_SOFT_RST ( BIT(4) )
+#define BIT_SIM0_SOFT_RST ( BIT(3) )
+#define BIT_UART1_SOFT_RST ( BIT(2) )
+#define BIT_UART0_SOFT_RST ( BIT(1) )
+#define BIT_WDG_SOFT_RST ( BIT(0) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_MCU_RST */
+#define BIT_MCU_SOFT_RST_SET ( BIT(0) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_CLK_SEL0 */
+#define BITS_CLK_IIS3_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
+#define BITS_CLK_IIS2_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_CLK_IIS1_SEL(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) )
+#define BITS_CLK_IIS0_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_CLK_UART1_SEL(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_CLK_UART0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_CLK_DIV0 */
+#define BITS_CLK_IIS2_DIV(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
+#define BITS_CLK_IIS1_DIV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)) )
+#define BITS_CLK_IIS0_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
+#define BITS_CLK_UART1_DIV(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) )
+#define BITS_CLK_UART0_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_ARCH_EB */
+#define BITS_CLK_IIS3_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
+#define BIT_RTC_ARCH_EB ( BIT(1) )
+#define BIT_APB_ARCH_EB ( BIT(0) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_MISC_CTL0 */
+#define BIT_ALL_CLK_EN ( BIT(28) )
+#define BIT_DMA_LSLP_EN ( BIT(27) )
+#define BIT_WAKEUP_XTL_EN_3G_W ( BIT(26) )
+#define BIT_WAKEUP_XTL_EN_2G ( BIT(25) )
+#define BIT_ARM_JTAG_EN ( BIT(24) )
+#define BIT_WAKEUP_XTL_EN_3G_TD ( BIT(23) )
+#define BITS_ARM_FRC_STOP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_MISC_CTL1 */
+#define BITS_BUFON_CTRL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) )
+#define BIT_SIM2_CLK_POLARITY ( BIT(3) )
+#define BIT_SIM1_CLK_POLARITY ( BIT(2) )
+#define BIT_SIM0_CLK_POLARITY ( BIT(1) )
+#define BIT_ROM_CLK_EN ( BIT(0) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_PIN_SEL */
+#define BIT_DJTAG_PIN_IN_SEL ( BIT(0) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_SLP_CTL */
+#define BIT_APB_PERI_FRC_ON ( BIT(20) )
+#define BIT_APB_PERI_FRC_SLP ( BIT(16) )
+#define BIT_MCU_XTLEN_AUTOPD_EN ( BIT(12) )
+#define BIT_CHIP_SLP_ARM_CLR ( BIT(4) )
+#define BIT_MCU_FORCE_WSYS_LT_STOP ( BIT(2) )
+#define BIT_MCU_FORCE_WSYS_STOP ( BIT(1) )
+#define BIT_MCU_FORCE_DEEP_SLEEP ( BIT(0) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_WSYS_STS */
+#define BITS_DEEP_SLP_DBG(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_WSYS_STATUS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_SLP_STS */
+#define BIT_DSP_MAHB_SLEEP_EN ( BIT(28) )
+#define BIT_MCU_PERI_STOP ( BIT(27) )
+#define BIT_DSP_PERI_STOP ( BIT(26) )
+#define BIT_ECC_CKG_EN ( BIT(25) )
+#define BIT_QBC_CKG_EN ( BIT(24) )
+#define BIT_DSP_DPLL_EN ( BIT(23) )
+#define BIT_DSP_TDPLL_EN ( BIT(22) )
+#define BIT_DSP_MPLL_EN ( BIT(21) )
+#define BIT_STC_TMR_AUTOPD_XTL_EN ( BIT(20) )
+#define BIT_RFT_TMR_AUTOPD_XTL_EN ( BIT(19) )
+#define BIT_STC_TMR_AUTOPD_RF_EN ( BIT(18) )
+#define BIT_RFT_TMR_AUTOPD_RF_EN ( BIT(17) )
+#define BIT_CHIP_SLEEP_REC_ARM ( BIT(16) )
+#define BIT_DSP_CORE_STOP ( BIT(15) )
+#define BIT_DSP_MTX_STOP ( BIT(14) )
+#define BIT_DSP_AHB_STOP ( BIT(13) )
+#define BIT_DSP_SYS_STOP ( BIT(12) )
+#define BIT_DSP_DEEP_STOP ( BIT(11) )
+#define BIT_ASHB_DSPTOARM_EN ( BIT(10) )
+#define BIT_ASHB_ARMTODSP_VALID ( BIT(9) )
+#define BIT_EMC_STOP_CH3 ( BIT(8) )
+#define BIT_EMC_STOP_CH4 ( BIT(7) )
+#define BIT_EMC_STOP_CH5 ( BIT(6) )
+#define BIT_FRC_WAKE_EN ( BIT(5) )
+#define BIT_TMR_WAKE_AFC ( BIT(4) )
+#define BIT_SCH_SLEEP ( BIT(3) )
+#define BIT_DSP_STOP ( BIT(2) )
+#define BIT_MCU_STOP ( BIT(1) )
+#define BIT_EMC_STOP ( BIT(0) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_ROM_PD_CTL */
+#define BIT_ROM_FORCE_ON ( BIT(0) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_BUS_CTL0 */
+#define BIT_ADA_CTRL_SEL ( BIT(6) )
+#define BIT_RFFE_CTRL_SEL ( BIT(5) )
+#define BIT_IIS3_CTRL_SEL ( BIT(4) )
+#define BIT_IIS2_CTRL_SEL ( BIT(3) )
+#define BIT_IIS1_CTRL_SEL ( BIT(2) )
+#define BIT_IIS0_CTRL_SEL ( BIT(1) )
+#define BIT_UART1_CTRL_SEL ( BIT(0) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_DSP_INT_CLR */
+#define BIT_RFT_INT_CLR ( BIT(2) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_MISC_INT_STS */
+#define BIT_RFT_INT ( BIT(2) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_HWRST */
+#define BITS_HWRST_REG(_X_) (_X_)
+
+/* bits definitions for register REG_CP_APB_RF_APB_ARM_BOOT_ADDR */
+#define BITS_ARMBOOT_ADDR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+#endif
diff --git a/include/soc/sprd/chip_x30g/__regs_gpu_apb_rf.h b/include/soc/sprd/chip_x30g/__regs_gpu_apb_rf.h new file mode 100644 index 00000000..81163fdf --- /dev/null +++ b/include/soc/sprd/chip_x30g/__regs_gpu_apb_rf.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_GPU_APB_RF_HEADFILE_H__ +#define __H_REGS_GPU_APB_RF_HEADFILE_H__ __FILE__ + +#define REGS_GPU_APB_RF + +/* registers definitions for GPU_APB_RF */ +#define REG_GPU_APB_APB_RST SCI_ADDR(REGS_GPU_APB_BASE, 0x0000) +#define REG_GPU_APB_APB_CLK_CTRL SCI_ADDR(REGS_GPU_APB_BASE, 0x0004) + + + +/* bits definitions for register REG_GPU_APB_RF_APB_RST */ +#define BIT_GPU_APB_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_GPU_APB_RF_APB_CLK_CTRL */ +#define BITS_CLK_GPU_DIV(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CLK_GPU_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +#endif diff --git a/include/soc/sprd/chip_x30g/__regs_mm_ahb_rf.h b/include/soc/sprd/chip_x30g/__regs_mm_ahb_rf.h new file mode 100644 index 00000000..315cce43 --- /dev/null +++ b/include/soc/sprd/chip_x30g/__regs_mm_ahb_rf.h @@ -0,0 +1,92 @@ +/*
+ * Copyright (C) 2014 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+#ifndef __SCI_GLB_REGS_H__
+#error "Don't include this file directly, Pls include sci_glb_regs.h"
+#endif
+
+
+#ifndef __H_REGS_MM_AHB_RF_HEADFILE_H__
+#define __H_REGS_MM_AHB_RF_HEADFILE_H__ __FILE__
+
+#define REGS_MM_AHB_RF
+
+/* registers definitions for MM_AHB_RF */
+#define REG_MM_AHB_AHB_EB SCI_ADDR(REGS_MM_AHB_BASE, 0x0000)
+#define REG_MM_AHB_AHB_RST SCI_ADDR(REGS_MM_AHB_BASE, 0x0004)
+#define REG_MM_AHB_GEN_CKG_CFG SCI_ADDR(REGS_MM_AHB_BASE, 0x0008)
+#define REG_MM_AHB_MIPI_CSI2_CTRL SCI_ADDR(REGS_MM_AHB_BASE, 0x000C)
+#define REG_MM_AHB_MM_QOS_CFG SCI_ADDR(REGS_MM_AHB_BASE, 0x0010)
+
+
+
+/* bits definitions for register REG_MM_AHB_RF_AHB_EB */
+#define BIT_MMU_EB ( BIT(7) )
+#define BIT_MM_CKG_EB ( BIT(6) )
+#define BIT_JPG_EB ( BIT(5) )
+#define BIT_CSI_EB ( BIT(4) )
+#define BIT_VSP_EB ( BIT(3) )
+#define BIT_ISP_EB ( BIT(2) )
+#define BIT_CCIR_EB ( BIT(1) )
+#define BIT_DCAM_EB ( BIT(0) )
+
+/* bits definitions for register REG_MM_AHB_RF_AHB_RST */
+#define BIT_MMU_SOFT_RST ( BIT(14) )
+#define BIT_MM_CKG_SOFT_RST ( BIT(13) )
+#define BIT_MM_MTX_SOFT_RST ( BIT(12) )
+#define BIT_OR1200_SOFT_RST ( BIT(11) )
+#define BIT_ROT_SOFT_RST ( BIT(10) )
+#define BIT_CAM2_SOFT_RST ( BIT(9) )
+#define BIT_CAM1_SOFT_RST ( BIT(8) )
+#define BIT_CAM0_SOFT_RST ( BIT(7) )
+#define BIT_JPG_SOFT_RST ( BIT(6) )
+#define BIT_CSI_SOFT_RST ( BIT(5) )
+#define BIT_VSP_SOFT_RST ( BIT(4) )
+#define BIT_ISP_CFG_SOFT_RST ( BIT(3) )
+#define BIT_ISP_LOG_SOFT_RST ( BIT(2) )
+#define BIT_CCIR_SOFT_RST ( BIT(1) )
+#define BIT_DCAM_SOFT_RST ( BIT(0) )
+
+/* bits definitions for register REG_MM_AHB_RF_GEN_CKG_CFG */
+#define BIT_MM_MTX_AXI_CKG_EN ( BIT(8) )
+#define BIT_MM_AXI_CKG_EN ( BIT(7) )
+#define BIT_JPG_AXI_CKG_EN ( BIT(6) )
+#define BIT_VSP_AXI_CKG_EN ( BIT(5) )
+#define BIT_ISP_AXI_CKG_EN ( BIT(4) )
+#define BIT_DCAM_AXI_CKG_EN ( BIT(3) )
+#define BIT_SENSOR_CKG_EN ( BIT(2) )
+#define BIT_MIPI_CSI_CKG_EN ( BIT(1) )
+#define BIT_CPHY_CFG_CKG_EN ( BIT(0) )
+
+/* bits definitions for register REG_MM_AHB_RF_MIPI_CSI2_CTRL */
+#define BITS_MIPI_CPHY_SAMPLE_SEL(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)) )
+#define BIT_MIPI_CPHY_SYNC_MODE ( BIT(2) )
+#define BIT_MIPI_CPHY_TEST_CTL ( BIT(1) )
+#define BIT_MIPI_CPHY_SEL ( BIT(0) )
+
+/* bits definitions for register REG_MM_AHB_RF_MM_QOS_CFG */
+#define BITS_QOS_R_DCAM(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_QOS_W_DCAM(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_QOS_R_JPG(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_QOS_W_JPG(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_QOS_R_ISP(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_QOS_W_ISP(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_QOS_R_VSP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_QOS_W_VSP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+#endif
diff --git a/include/soc/sprd/chip_x30g/__regs_mm_ahb_rf_tshark2.h b/include/soc/sprd/chip_x30g/__regs_mm_ahb_rf_tshark2.h new file mode 100644 index 00000000..db3ef54c --- /dev/null +++ b/include/soc/sprd/chip_x30g/__regs_mm_ahb_rf_tshark2.h @@ -0,0 +1,105 @@ +/* the head file modifier: ang 2015-01-21 14:37:26*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_MM_AHB_HEADFILE_H__ +#define __H_REGS_MM_AHB_HEADFILE_H__ __FILE__ + +#define REGS_MM_AHB + +/* registers definitions for MM_AHB */ +#define REG_MM_AHB_AHB_EB SCI_ADDR(REGS_MM_AHB_BASE, 0x0000)/*AHB_EB*/ +#define REG_MM_AHB_AHB_RST SCI_ADDR(REGS_MM_AHB_BASE, 0x0004)/*AHB_RST*/ +#define REG_MM_AHB_GEN_CKG_CFG SCI_ADDR(REGS_MM_AHB_BASE, 0x0008)/*GEN_CKG_CFG*/ +#define REG_MM_AHB_MIPI_CSI2_CTRL SCI_ADDR(REGS_MM_AHB_BASE, 0x000C)/*MIPI_CSI2_CTRL*/ +#define REG_MM_AHB_MM_QOS_CFG SCI_ADDR(REGS_MM_AHB_BASE, 0x0010)/*MM_QOS_CFG*/ +#define REG_MM_AHB_MM_QOS_CFG_1 SCI_ADDR(REGS_MM_AHB_BASE, 0x0014)/*MM_QOS_CFG_1*/ + + + +/* bits definitions for register REG_MM_AHB_AHB_EB */ +#define BIT_VPP_EB (BIT(8)) +#define BIT_MMU_EB (BIT(7)) +#define BIT_MM_CKG_EB (BIT(6)) +#define BIT_JPG_EB (BIT(5)) +#define BIT_CSI_EB (BIT(4)) +#define BIT_VSP_EB (BIT(3)) +#define BIT_ISP_EB (BIT(2)) +#define BIT_CCIR_EB (BIT(1)) +#define BIT_DCAM_EB (BIT(0)) + +/* bits definitions for register REG_MM_AHB_AHB_RST */ +#define BIT_VPP_SOFT_RST (BIT(15)) +#define BIT_MMU_SOFT_RST (BIT(14)) +#define BIT_MM_CKG_SOFT_RST (BIT(13)) +#define BIT_MM_MTX_SOFT_RST (BIT(12)) +#define BIT_OR1200_SOFT_RST (BIT(11)) +#define BIT_ROT_SOFT_RST (BIT(10)) +#define BIT_CAM2_SOFT_RST (BIT(9)) +#define BIT_CAM1_SOFT_RST (BIT(8)) +#define BIT_CAM0_SOFT_RST (BIT(7)) +#define BIT_JPG_SOFT_RST (BIT(6)) +#define BIT_CSI_SOFT_RST (BIT(5)) +#define BIT_VSP_SOFT_RST (BIT(4)) +#define BIT_ISP_CFG_SOFT_RST (BIT(3)) +#define BIT_ISP_LOG_SOFT_RST (BIT(2)) +#define BIT_CCIR_SOFT_RST (BIT(1)) +#define BIT_DCAM_SOFT_RST (BIT(0)) + +/* bits definitions for register REG_MM_AHB_GEN_CKG_CFG */ +#define BIT_VPP_AXI_CKG_EN (BIT(9)) +#define BIT_MM_MTX_AXI_CKG_EN (BIT(8)) +#define BIT_MM_AXI_CKG_EN (BIT(7)) +#define BIT_JPG_AXI_CKG_EN (BIT(6)) +#define BIT_VSP_AXI_CKG_EN (BIT(5)) +#define BIT_ISP_AXI_CKG_EN (BIT(4)) +#define BIT_DCAM_AXI_CKG_EN (BIT(3)) +#define BIT_SENSOR_CKG_EN (BIT(2)) +#define BIT_MIPI_CSI_CKG_EN (BIT(1)) +#define BIT_CPHY_CFG_CKG_EN (BIT(0)) + +/* bits definitions for register REG_MM_AHB_MIPI_CSI2_CTRL */ +#define BIT_MIPI_CPHY_SEL_AB_C (BIT(5)) +#define BITS_MIPI_CPHY_SAMPLE_SEL(_X_) ((_X_) << 3 & (BIT(3)|BIT(4))) +#define BIT_MIPI_CPHY_SYNC_MODE (BIT(2)) +#define BIT_MIPI_CPHY_TEST_CTL (BIT(1)) +#define BIT_MIPI_CPHY_SEL (BIT(0)) + +/* bits definitions for register REG_MM_AHB_MM_QOS_CFG */ +#define BITS_QOS_R_DCAM(_X_) ((_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31))) +#define BITS_QOS_W_DCAM(_X_) ((_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27))) +#define BITS_QOS_R_JPG(_X_) ((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_QOS_W_JPG(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19))) +#define BITS_QOS_R_ISP(_X_) ((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_QOS_W_ISP(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11))) +#define BITS_QOS_R_VSP(_X_) ((_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7))) +#define BITS_QOS_W_VSP(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3))) + +/* bits definitions for register REG_MM_AHB_MM_QOS_CFG_1 */ +#define BITS_QOS_R_VPP(_X_) ((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_QOS_W_VPP(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11))) +#define BITS_QOS_R_CODEC(_X_) ((_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7))) +#define BITS_QOS_W_CODEC(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3))) + +#endif diff --git a/include/soc/sprd/chip_x30g/__regs_mm_clk.h b/include/soc/sprd/chip_x30g/__regs_mm_clk.h new file mode 100644 index 00000000..948502ed --- /dev/null +++ b/include/soc/sprd/chip_x30g/__regs_mm_clk.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __REGS_MM_CLK_H__ +#define __REGS_MM_CLK_H__ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, include <mach/sci_glb_regs.h>" +#endif + +#define REGS_MM_CLK + +/* registers definitions for controller REGS_MM_CLK */ +#define REG_MM_CLK_MM_AHB_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0020) +#define REG_MM_CLK_SENSOR_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0024) +#define REG_MM_CLK_CCIR_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0028) +#define REG_MM_CLK_DCAM_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x002c) +#define REG_MM_CLK_VSP_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0030) +#define REG_MM_CLK_ISP_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0034) +#define REG_MM_CLK_JPG_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0038) + +/* vars definitions for controller REGS_MM_CLK */ + +#endif //__REGS_MM_CLK_H__ diff --git a/include/soc/sprd/chip_x30g/__regs_pinmap.h b/include/soc/sprd/chip_x30g/__regs_pinmap.h new file mode 100755 index 00000000..49ab259a --- /dev/null +++ b/include/soc/sprd/chip_x30g/__regs_pinmap.h @@ -0,0 +1,274 @@ +#ifndef __ASM_ARM_ARCH_PINMAP_H +#error "Don't include this file directly, Pls include pinmap.h" +#endif + +#ifndef _REGS_PINMAP_H_ +#define _REGS_PINMAP_H_ + +#define CTL_PIN_BASE (SPRD_PIN_BASE) + +/* registers definitions for controller CTL_PIN */ +#define REG_PIN_CTRL0 ( 0x0000 ) +#define REG_PIN_CTRL1 ( 0x0004 ) +#define REG_PIN_CTRL2 ( 0x0008 ) +#define REG_PIN_CTRL3 ( 0x000c ) +#define REG_PIN_CTRL4 ( 0x0010 ) +#define REG_PIN_CTRL5 ( 0x0014 ) + +#define REG_PIN_TRACECLK ( 0x0020 ) +#define REG_PIN_TRACECTRL ( 0x0024 ) +#define REG_PIN_TRACEDAT0 ( 0x0028 ) +#define REG_PIN_TRACEDAT1 ( 0x002c ) +#define REG_PIN_TRACEDAT2 ( 0x0030 ) +#define REG_PIN_TRACEDAT3 ( 0x0034 ) +#define REG_PIN_TRACEDAT4 ( 0x0038 ) +#define REG_PIN_TRACEDAT5 ( 0x003c ) +#define REG_PIN_TRACEDAT6 ( 0x0040 ) +#define REG_PIN_TRACEDAT7 ( 0x0044 ) +#define REG_PIN_U0TXD ( 0x0048 ) +#define REG_PIN_U0RXD ( 0x004c ) +#define REG_PIN_U0CTS ( 0x0050 ) +#define REG_PIN_U0RTS ( 0x0054 ) +#define REG_PIN_U1TXD ( 0x0058 ) +#define REG_PIN_U1RXD ( 0x005c ) +#define REG_PIN_U2TXD ( 0x0060 ) +#define REG_PIN_U2RXD ( 0x0064 ) +#define REG_PIN_U3TXD ( 0x0068 ) +#define REG_PIN_U3RXD ( 0x006c ) +#define REG_PIN_U3CTS ( 0x0070 ) +#define REG_PIN_U3RTS ( 0x0074 ) +#define REG_PIN_CP2_RFCTL0 ( 0x0078 ) +#define REG_PIN_CP2_RFCTL1 ( 0x007c ) +#define REG_PIN_CP2_RFCTL2 ( 0x0080 ) +#define REG_PIN_WIFI_AGCGAIN3 ( 0x0084 ) +#define REG_PIN_WIFI_AGCGAIN4 ( 0x0088 ) +#define REG_PIN_WIFI_AGCGAIN5 ( 0x008c ) +#define REG_PIN_WIFI_AGCGAIN6 ( 0x0090 ) +#define REG_PIN_RFSDA0 ( 0x0094 ) +#define REG_PIN_RFSCK0 ( 0x0098 ) +#define REG_PIN_RFSEN0 ( 0x009c ) +#define REG_PIN_RFSDA1 ( 0x00a0 ) +#define REG_PIN_RFSCK1 ( 0x00a4 ) +#define REG_PIN_RFSEN1 ( 0x00a8 ) +#define REG_PIN_CP1_RFCTL0 ( 0x00ac ) +#define REG_PIN_CP1_RFCTL1 ( 0x00b0 ) +#define REG_PIN_CP1_RFCTL2 ( 0x00b4 ) +#define REG_PIN_CP1_RFCTL3 ( 0x00b8 ) +#define REG_PIN_CP1_RFCTL4 ( 0x00bc ) +#define REG_PIN_CP1_RFCTL5 ( 0x00c0 ) +#define REG_PIN_CP1_RFCTL6 ( 0x00c4 ) +#define REG_PIN_CP1_RFCTL7 ( 0x00c8 ) +#define REG_PIN_CP1_RFCTL8 ( 0x00cc ) +#define REG_PIN_CP1_RFCTL9 ( 0x00d0 ) +#define REG_PIN_CP1_RFCTL10 ( 0x00d4 ) +#define REG_PIN_CP1_RFCTL11 ( 0x00d8 ) +#define REG_PIN_CP1_RFCTL12 ( 0x00dc ) +#define REG_PIN_CP1_RFCTL13 ( 0x00e0 ) +#define REG_PIN_CP1_RFCTL14 ( 0x00e4 ) +#define REG_PIN_CP1_RFCTL15 ( 0x00e8 ) +#define REG_PIN_CP0_RFCTL0 ( 0x00ec ) +#define REG_PIN_CP0_RFCTL1 ( 0x00f0 ) +#define REG_PIN_CP0_RFCTL2 ( 0x00f4 ) +#define REG_PIN_CP0_RFCTL3 ( 0x00f8 ) +#define REG_PIN_CP0_RFCTL4 ( 0x00fc ) +#define REG_PIN_CP0_RFCTL5 ( 0x0100 ) +#define REG_PIN_CP0_RFCTL6 ( 0x0104 ) +#define REG_PIN_CP0_RFCTL7 ( 0x0108 ) +#define REG_PIN_XTLEN ( 0x010c ) +#define REG_PIN_SCL3 ( 0x0110 ) +#define REG_PIN_SDA3 ( 0x0114 ) +#define REG_PIN_SPI0_CSN ( 0x0118 ) +#define REG_PIN_SPI0_DO ( 0x011c ) +#define REG_PIN_SPI0_DI ( 0x0120 ) +#define REG_PIN_SPI0_CLK ( 0x0124 ) +#define REG_PIN_EXTINT0 ( 0x0128 ) +#define REG_PIN_EXTINT1 ( 0x012c ) +#define REG_PIN_SCL1 ( 0x0130 ) +#define REG_PIN_SDA1 ( 0x0134 ) +#define REG_PIN_SIMCLK0 ( 0x0138 ) +#define REG_PIN_SIMDA0 ( 0x013c ) +#define REG_PIN_SIMRST0 ( 0x0140 ) +#define REG_PIN_SIMCLK1 ( 0x0144 ) +#define REG_PIN_SIMDA1 ( 0x0148 ) +#define REG_PIN_SIMRST1 ( 0x014c ) +#define REG_PIN_SIMCLK2 ( 0x0150 ) +#define REG_PIN_SIMDA2 ( 0x0154 ) +#define REG_PIN_SIMRST2 ( 0x0158 ) +#define REG_PIN_MEMS_MIC_CLK0 ( 0x015c ) +#define REG_PIN_MEMS_MIC_DATA0 ( 0x0160 ) +#define REG_PIN_MEMS_MIC_CLK1 ( 0x0164 ) +#define REG_PIN_MEMS_MIC_DATA1 ( 0x0168 ) +#define REG_PIN_SD1_CLK ( 0x016c ) +#define REG_PIN_SD1_CMD ( 0x0170 ) +#define REG_PIN_SD1_D0 ( 0x0174 ) +#define REG_PIN_SD1_D1 ( 0x0178 ) +#define REG_PIN_SD1_D2 ( 0x017c ) +#define REG_PIN_SD1_D3 ( 0x0180 ) +#define REG_PIN_SD0_D3 ( 0x0184 ) +#define REG_PIN_SD0_D2 ( 0x0188 ) +#define REG_PIN_SD0_CMD ( 0x018c ) +#define REG_PIN_SD0_D0 ( 0x0190 ) +#define REG_PIN_SD0_D1 ( 0x0194 ) +#define REG_PIN_SD0_CLK1 ( 0x0198 ) +#define REG_PIN_SD0_CLK0 ( 0x019c ) +#define REG_PIN_PTEST ( 0x01a0 ) +#define REG_PIN_ANA_INT ( 0x01a4 ) +#define REG_PIN_EXT_RST_B ( 0x01a8 ) +#define REG_PIN_CHIP_SLEEP ( 0x01ac ) +#define REG_PIN_XTL_BUF_EN0 ( 0x01b0 ) +#define REG_PIN_XTL_BUF_EN1 ( 0x01b4 ) +#define REG_PIN_XTL_BUF_EN2 ( 0x01b8 ) +#define REG_PIN_CLK_32K ( 0x01bc ) +#define REG_PIN_AUD_SCLK ( 0x01c0 ) +#define REG_PIN_AUD_DANGL ( 0x01c4 ) +#define REG_PIN_AUD_DANGR ( 0x01c8 ) +#define REG_PIN_AUD_ADD0 ( 0x01cc ) +#define REG_PIN_AUD_ADSYNC ( 0x01d0 ) +#define REG_PIN_AUD_DAD1 ( 0x01d4 ) +#define REG_PIN_AUD_DAD0 ( 0x01d8 ) +#define REG_PIN_AUD_DASYNC ( 0x01dc ) +#define REG_PIN_ADI_D ( 0x01e0 ) +#define REG_PIN_ADI_SYNC ( 0x01e4 ) +#define REG_PIN_ADI_SCLK ( 0x01e8 ) +#define REG_PIN_LCD_CSN1 ( 0x01ec ) +#define REG_PIN_LCD_CSN0 ( 0x01f0 ) +#define REG_PIN_LCD_RSTN ( 0x01f4 ) +#define REG_PIN_LCD_CD ( 0x01f8 ) +#define REG_PIN_LCD_FMARK ( 0x01fc ) +#define REG_PIN_LCD_WRN ( 0x0200 ) +#define REG_PIN_LCD_RDN ( 0x0204 ) +#define REG_PIN_LCD_D0 ( 0x0208 ) +#define REG_PIN_LCD_D1 ( 0x020c ) +#define REG_PIN_LCD_D2 ( 0x0210 ) +#define REG_PIN_LCD_D3 ( 0x0214 ) +#define REG_PIN_LCD_D4 ( 0x0218 ) +#define REG_PIN_LCD_D5 ( 0x021c ) +#define REG_PIN_LCD_D6 ( 0x0220 ) +#define REG_PIN_LCD_D7 ( 0x0224 ) +#define REG_PIN_LCD_D8 ( 0x0228 ) +#define REG_PIN_LCD_D9 ( 0x022c ) +#define REG_PIN_LCD_D10 ( 0x0230 ) +#define REG_PIN_LCD_D11 ( 0x0234 ) +#define REG_PIN_LCD_D12 ( 0x0238 ) +#define REG_PIN_LCD_D13 ( 0x023c ) +#define REG_PIN_LCD_D14 ( 0x0240 ) +#define REG_PIN_LCD_D15 ( 0x0244 ) +#define REG_PIN_LCD_D16 ( 0x0248 ) +#define REG_PIN_LCD_D17 ( 0x024c ) +#define REG_PIN_LCD_D18 ( 0x0250 ) +#define REG_PIN_LCD_D19 ( 0x0254 ) +#define REG_PIN_LCD_D20 ( 0x0258 ) +#define REG_PIN_LCD_D21 ( 0x025c ) +#define REG_PIN_LCD_D22 ( 0x0260 ) +#define REG_PIN_LCD_D23 ( 0x0264 ) +#define REG_PIN_SPI2_CSN ( 0x0268 ) +#define REG_PIN_SPI2_DO ( 0x026c ) +#define REG_PIN_SPI2_DI ( 0x0270 ) +#define REG_PIN_SPI2_CLK ( 0x0274 ) +#define REG_PIN_EMMC_CLK ( 0x0278 ) +#define REG_PIN_EMMC_CMD ( 0x027c ) +#define REG_PIN_EMMC_D0 ( 0x0280 ) +#define REG_PIN_EMMC_D1 ( 0x0284 ) +#define REG_PIN_EMMC_D2 ( 0x0288 ) +#define REG_PIN_EMMC_D3 ( 0x028c ) +#define REG_PIN_EMMC_D4 ( 0x0290 ) +#define REG_PIN_EMMC_D5 ( 0x0294 ) +#define REG_PIN_EMMC_D6 ( 0x0298 ) +#define REG_PIN_EMMC_D7 ( 0x029c ) +#define REG_PIN_EMMC_RST ( 0x02a0 ) +#define REG_PIN_NFWPN ( 0x02a4 ) +#define REG_PIN_NFRB ( 0x02a8 ) +#define REG_PIN_NFCLE ( 0x02ac ) +#define REG_PIN_NFALE ( 0x02b0 ) +#define REG_PIN_NFCEN0 ( 0x02b4 ) +#define REG_PIN_NFCEN1 ( 0x02b8 ) +#define REG_PIN_NFREN ( 0x02bc ) +#define REG_PIN_NFWEN ( 0x02c0 ) +#define REG_PIN_NFD0 ( 0x02c4 ) +#define REG_PIN_NFD1 ( 0x02c8 ) +#define REG_PIN_NFD2 ( 0x02cc ) +#define REG_PIN_NFD3 ( 0x02d0 ) +#define REG_PIN_NFD4 ( 0x02d4 ) +#define REG_PIN_NFD5 ( 0x02d8 ) +#define REG_PIN_NFD6 ( 0x02dc ) +#define REG_PIN_NFD7 ( 0x02e0 ) +#define REG_PIN_NFD8 ( 0x02e4 ) +#define REG_PIN_NFD9 ( 0x02e8 ) +#define REG_PIN_NFD10 ( 0x02ec ) +#define REG_PIN_NFD11 ( 0x02f0 ) +#define REG_PIN_NFD12 ( 0x02f4 ) +#define REG_PIN_NFD13 ( 0x02f8 ) +#define REG_PIN_NFD14 ( 0x02fc ) +#define REG_PIN_NFD15 ( 0x0300 ) +#define REG_PIN_CCIRCK0 ( 0x0304 ) +#define REG_PIN_CCIRCK1 ( 0x0308 ) +#define REG_PIN_CCIRMCLK ( 0x030c ) +#define REG_PIN_CCIRHS ( 0x0310 ) +#define REG_PIN_CCIRVS ( 0x0314 ) +#define REG_PIN_CCIRD0 ( 0x0318 ) +#define REG_PIN_CCIRD1 ( 0x031c ) +#define REG_PIN_CCIRD2 ( 0x0320 ) +#define REG_PIN_CCIRD3 ( 0x0324 ) +#define REG_PIN_CCIRD4 ( 0x0328 ) +#define REG_PIN_CCIRD5 ( 0x032c ) +#define REG_PIN_CCIRD6 ( 0x0330 ) +#define REG_PIN_CCIRD7 ( 0x0334 ) +#define REG_PIN_CCIRD8 ( 0x0338 ) +#define REG_PIN_CCIRD9 ( 0x033c ) +#define REG_PIN_CCIRRST ( 0x0340 ) +#define REG_PIN_CCIRPD1 ( 0x0344 ) +#define REG_PIN_CCIRPD0 ( 0x0348 ) +#define REG_PIN_SCL0 ( 0x034c ) +#define REG_PIN_SDA0 ( 0x0350 ) +#define REG_PIN_KEYOUT0 ( 0x0354 ) +#define REG_PIN_KEYOUT1 ( 0x0358 ) +#define REG_PIN_KEYOUT2 ( 0x035c ) +#define REG_PIN_KEYIN0 ( 0x0360 ) +#define REG_PIN_KEYIN1 ( 0x0364 ) +#define REG_PIN_KEYIN2 ( 0x0368 ) +#define REG_PIN_SCL2 ( 0x036c ) +#define REG_PIN_SDA2 ( 0x0370 ) +#define REG_PIN_CLK_AUX0 ( 0x0374 ) +#define REG_PIN_IIS0DI ( 0x0378 ) +#define REG_PIN_IIS0DO ( 0x037c ) +#define REG_PIN_IIS0CLK ( 0x0380 ) +#define REG_PIN_IIS0LRCK ( 0x0384 ) +#define REG_PIN_IIS0MCK ( 0x0388 ) +#define REG_PIN_IIS1DI ( 0x038c ) +#define REG_PIN_IIS1DO ( 0x0390 ) +#define REG_PIN_IIS1CLK ( 0x0394 ) +#define REG_PIN_IIS1LRCK ( 0x0398 ) +#define REG_PIN_IIS1MCK ( 0x039c ) +#define REG_PIN_MTDO ( 0x03a0 ) +#define REG_PIN_MTDI ( 0x03a4 ) +#define REG_PIN_MTCK ( 0x03a8 ) +#define REG_PIN_MTMS ( 0x03ac ) +#define REG_PIN_MTRST_N ( 0x03b0 ) + + + +/* bits definitions for register REG_PIN_XXX */ +#define BITS_PIN_DS(_x_) ( ((_x_) << 18) & (BIT_18|BIT_19|BIT_20|BIT_21) ) +#define BIT_PIN_SLP_AP ( BIT_13 ) +#define BIT_PIN_SLP_CP0 ( BIT_14 ) +#define BIT_PIN_SLP_CP1 ( BIT_15 ) +#define BIT_PIN_SLP_CP2 ( BIT_16 ) +#define BITS_PIN_SLP(_x_) ( ((_x_) << 13) & (BIT_13|BIT_14|BIT_15|BIT_16) ) +#define BIT_PIN_WPU_SEL ( BIT_12 ) +#define BIT_PIN_WPU ( BIT_7 ) +#define BIT_PIN_WPD ( BIT_6 ) +#define BITS_PIN_AF(_x_) ( ((_x_) << 4) & (BIT_4|BIT_5) ) +#define BIT_PIN_SLP_WPU ( BIT_3 ) +#define BIT_PIN_SLP_WPD ( BIT_2 ) +#define BIT_PIN_SLP_IE ( BIT_1 ) +#define BIT_PIN_SLP_OE ( BIT_0 ) + +/* vars definitions for controller CTL_PIN */ +#define BIT_PIN_NUL ( 0 ) +#define BIT_PIN_SLP_NUL ( 0 ) +#define BIT_PIN_SLP_Z ( 0 ) +#define BIT_PIN_WPU_SEL ( BIT_12 ) +#define BIT_PIN_WPUS ( BIT_12 ) +#define BIT_PIN_NULL ( 0 ) + +#endif diff --git a/include/soc/sprd/chip_x30g/__regs_pmu_apb.h b/include/soc/sprd/chip_x30g/__regs_pmu_apb.h new file mode 100644 index 00000000..c27c5d08 --- /dev/null +++ b/include/soc/sprd/chip_x30g/__regs_pmu_apb.h @@ -0,0 +1,875 @@ +/*
+ * Copyright (C) 2014 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+#ifndef __SCI_GLB_REGS_H__
+#error "Don't include this file directly, Pls include sci_glb_regs.h"
+#endif
+
+
+#ifndef __H_REGS_PMU_APB_HEADFILE_H__
+#define __H_REGS_PMU_APB_HEADFILE_H__ __FILE__
+
+#define REGS_PMU_APB
+
+/* registers definitions for PMU_APB */
+#define REG_PMU_APB_PD_CA7_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0000)
+#define REG_PMU_APB_PD_CA7_C0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0004)
+#define REG_PMU_APB_PD_CA7_C1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0008)
+#define REG_PMU_APB_PD_CA7_C2_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x000C)
+#define REG_PMU_APB_PD_CA7_C3_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0010)
+#define REG_PMU_APB_PD_AP_DISP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0014)
+#define REG_PMU_APB_PD_AP_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0018)
+#define REG_PMU_APB_PD_MM_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x001C)
+#define REG_PMU_APB_PD_GPU_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0020)
+#define REG_PMU_APB_PD_CP0_ARM9_0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0024)
+#define REG_PMU_APB_PD_CP0_ARM9_1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0028)
+#define REG_PMU_APB_PD_CP0_ARM9_2_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x002C)
+#define REG_PMU_APB_PD_CP0_HU3GE_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0030)
+#define REG_PMU_APB_PD_CP0_GSM_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0034)
+#define REG_PMU_APB_PD_CP0_TD_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0038)
+#define REG_PMU_APB_PD_CP0_CEVA_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x003C)
+#define REG_PMU_APB_PD_CP0_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0044)
+#define REG_PMU_APB_PD_CP1_ARM9_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0048)
+#define REG_PMU_APB_PD_CP1_GSM_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x004C)
+#define REG_PMU_APB_PD_CP1_TD_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0050)
+#define REG_PMU_APB_PD_CP1_L1RAM_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0054)
+#define REG_PMU_APB_PD_CP1_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0058)
+#define REG_PMU_APB_PD_CP2_ARM9_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x005C)
+#define REG_PMU_APB_PD_CP2_WIFI_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0060)
+#define REG_PMU_APB_AP_WAKEUP_POR_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0064)
+#define REG_PMU_APB_PD_CP2_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0068)
+#define REG_PMU_APB_PD_PUB_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x006C)
+#define REG_PMU_APB_XTL_WAIT_CNT SCI_ADDR(REGS_PMU_APB_BASE, 0x0070)
+#define REG_PMU_APB_XTLBUF_WAIT_CNT SCI_ADDR(REGS_PMU_APB_BASE, 0x0074)
+#define REG_PMU_APB_PLL_WAIT_CNT1 SCI_ADDR(REGS_PMU_APB_BASE, 0x0078)
+#define REG_PMU_APB_PLL_WAIT_CNT2 SCI_ADDR(REGS_PMU_APB_BASE, 0x007C)
+#define REG_PMU_APB_XTL0_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0080)
+#define REG_PMU_APB_XTL1_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0084)
+#define REG_PMU_APB_XTL2_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0088)
+#define REG_PMU_APB_XTLBUF0_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x008C)
+#define REG_PMU_APB_XTLBUF1_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0090)
+#define REG_PMU_APB_MPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0094)
+#define REG_PMU_APB_DPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0098)
+#define REG_PMU_APB_TDPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x009C)
+#define REG_PMU_APB_WPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00A0)
+#define REG_PMU_APB_CPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00A4)
+#define REG_PMU_APB_WIFIPLL1_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00A8)
+#define REG_PMU_APB_WIFIPLL2_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00AC)
+#define REG_PMU_APB_CP_SOFT_RST SCI_ADDR(REGS_PMU_APB_BASE, 0x00B0)
+#define REG_PMU_APB_CP_SLP_STATUS_DBG0 SCI_ADDR(REGS_PMU_APB_BASE, 0x00B4)
+#define REG_PMU_APB_CP_SLP_STATUS_DBG1 SCI_ADDR(REGS_PMU_APB_BASE, 0x00B8)
+#define REG_PMU_APB_PWR_STATUS0_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00BC)
+#define REG_PMU_APB_PWR_STATUS1_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00C0)
+#define REG_PMU_APB_PWR_STATUS2_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00C4)
+#define REG_PMU_APB_PWR_STATUS3_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00C8)
+#define REG_PMU_APB_SLEEP_CTRL SCI_ADDR(REGS_PMU_APB_BASE, 0x00CC)
+#define REG_PMU_APB_DDR_SLEEP_CTRL SCI_ADDR(REGS_PMU_APB_BASE, 0x00D0)
+#define REG_PMU_APB_SLEEP_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x00D4)
+#define REG_PMU_APB_PLL_DIV_AUTO_GATE_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x00D8)
+#define REG_PMU_APB_PLL_DIV_EN1 SCI_ADDR(REGS_PMU_APB_BASE, 0x00DC)
+#define REG_PMU_APB_PLL_DIV_EN2 SCI_ADDR(REGS_PMU_APB_BASE, 0x00E0)
+#define REG_PMU_APB_CA7_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00E4)
+#define REG_PMU_APB_CA7_C0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00E8)
+#define REG_PMU_APB_CA7_C1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00EC)
+#define REG_PMU_APB_CA7_C2_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00F0)
+#define REG_PMU_APB_CA7_C3_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00F4)
+#define REG_PMU_APB_DDR_CHN_SLEEP_CTRL0 SCI_ADDR(REGS_PMU_APB_BASE, 0x00F8)
+#define REG_PMU_APB_DDR_CHN_SLEEP_CTRL1 SCI_ADDR(REGS_PMU_APB_BASE, 0x00FC)
+#define REG_PMU_APB_BISR_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0100)
+#define REG_PMU_APB_CGM_AP_AUTO_GATE_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0104)
+#define REG_PMU_APB_CGM_GPU_MM_AUTO_GATE_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0108)
+#define REG_PMU_APB_CGM_CP0_AUTO_GATE_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x010C)
+#define REG_PMU_APB_CGM_CP1_AUTO_GATE_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0110)
+#define REG_PMU_APB_CGM_CP2_AUTO_GATE_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0114)
+#define REG_PMU_APB_CGM_AP_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0118)
+#define REG_PMU_APB_CGM_GPU_MM_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x011C)
+#define REG_PMU_APB_CGM_CP0_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0120)
+#define REG_PMU_APB_CGM_CP1_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0124)
+#define REG_PMU_APB_CGM_CP2_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0128)
+#define REG_PMU_APB_DDR_OP_MODE_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x012C)
+#define REG_PMU_APB_DDR_PHY_RET_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0130)
+#define REG_PMU_APB_26M_SEL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0134)
+#define REG_PMU_APB_MEM_PD_CFG0 SCI_ADDR(REGS_PMU_APB_BASE, 0x0138)
+#define REG_PMU_APB_MEM_PD_CFG1 SCI_ADDR(REGS_PMU_APB_BASE, 0x013C)
+#define REG_PMU_APB_PD_DDR_PUBL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0140)
+#define REG_PMU_APB_PD_DDR_PHY_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0144)
+#define REG_PMU_APB_BISR_CFG2 SCI_ADDR(REGS_PMU_APB_BASE, 0x0148)
+
+
+
+/* bits definitions for register REG_PMU_APB_PD_CA7_TOP_CFG */
+#define BIT_PD_CA7_TOP_DBG_SHUTDOWN_EN ( BIT(28) )
+#define BIT_PD_CA7_TOP_FORCE_SHUTDOWN ( BIT(25) )
+#define BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN ( BIT(24) )
+#define BITS_PD_CA7_TOP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CA7_TOP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_CA7_C0_CFG */
+#define BIT_PD_CA7_C0_DBG_SHUTDOWN_EN ( BIT(28) )
+#define BIT_PD_CA7_C0_FORCE_SHUTDOWN ( BIT(25) )
+#define BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN ( BIT(24) )
+#define BITS_PD_CA7_C0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CA7_C0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_CA7_C1_CFG */
+#define BIT_PD_CA7_C1_DBG_SHUTDOWN_EN ( BIT(28) )
+#define BIT_PD_CA7_C1_FORCE_SHUTDOWN ( BIT(25) )
+#define BIT_PD_CA7_C1_AUTO_SHUTDOWN_EN ( BIT(24) )
+#define BITS_PD_CA7_C1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CA7_C1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_CA7_C2_CFG */
+#define BIT_PD_CA7_C2_DBG_SHUTDOWN_EN ( BIT(28) )
+#define BIT_PD_CA7_C2_FORCE_SHUTDOWN ( BIT(25) )
+#define BIT_PD_CA7_C2_AUTO_SHUTDOWN_EN ( BIT(24) )
+#define BITS_PD_CA7_C2_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CA7_C2_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_CA7_C3_CFG */
+#define BIT_PD_CA7_C3_DBG_SHUTDOWN_EN ( BIT(28) )
+#define BIT_PD_CA7_C3_FORCE_SHUTDOWN ( BIT(25) )
+#define BIT_PD_CA7_C3_AUTO_SHUTDOWN_EN ( BIT(24) )
+#define BITS_PD_CA7_C3_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CA7_C3_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_AP_DISP_CFG */
+
+/* bits definitions for register REG_PMU_APB_PD_AP_SYS_CFG */
+#define BIT_PD_AP_SYS_FORCE_SHUTDOWN ( BIT(25) )
+#define BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN ( BIT(24) )
+#define BITS_PD_AP_SYS_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_AP_SYS_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_MM_TOP_CFG */
+#define BIT_PD_MM_TOP_FORCE_SHUTDOWN ( BIT(25) )
+#define BIT_PD_MM_TOP_AUTO_SHUTDOWN_EN ( BIT(24) )
+#define BITS_PD_MM_TOP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_MM_TOP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_GPU_TOP_CFG */
+#define BIT_PD_GPU_TOP_FORCE_SHUTDOWN ( BIT(25) )
+#define BIT_PD_GPU_TOP_AUTO_SHUTDOWN_EN ( BIT(24) )
+#define BITS_PD_GPU_TOP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_GPU_TOP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_0_CFG */
+#define BIT_PD_CP0_ARM9_0_FORCE_SHUTDOWN ( BIT(25) )
+#define BIT_PD_CP0_ARM9_0_AUTO_SHUTDOWN_EN ( BIT(24) )
+#define BITS_PD_CP0_ARM9_0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CP0_ARM9_0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CP0_ARM9_0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_1_CFG */
+#define BIT_PD_CP0_ARM9_1_FORCE_SHUTDOWN ( BIT(25) )
+#define BIT_PD_CP0_ARM9_1_AUTO_SHUTDOWN_EN ( BIT(24) )
+#define BITS_PD_CP0_ARM9_1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CP0_ARM9_1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CP0_ARM9_1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_2_CFG */
+#define BIT_PD_CP0_ARM9_2_FORCE_SHUTDOWN ( BIT(25) )
+#define BIT_PD_CP0_ARM9_2_AUTO_SHUTDOWN_EN ( BIT(24) )
+#define BITS_PD_CP0_ARM9_2_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CP0_ARM9_2_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CP0_ARM9_2_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_CP0_HU3GE_CFG */
+#define BIT_PD_CP0_HU3GE_FORCE_SHUTDOWN ( BIT(25) )
+#define BIT_PD_CP0_HU3GE_AUTO_SHUTDOWN_EN ( BIT(24) )
+#define BITS_PD_CP0_HU3GE_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CP0_HU3GE_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CP0_HU3GE_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_CP0_GSM_CFG */
+#define BIT_PD_CP0_GSM_FORCE_SHUTDOWN ( BIT(25) )
+#define BIT_PD_CP0_GSM_AUTO_SHUTDOWN_EN ( BIT(24) )
+#define BITS_PD_CP0_GSM_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CP0_GSM_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CP0_GSM_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_CP0_TD_CFG */
+#define BIT_PD_CP0_TD_FORCE_SHUTDOWN ( BIT(25) )
+#define BIT_PD_CP0_TD_AUTO_SHUTDOWN_EN ( BIT(24) )
+#define BITS_PD_CP0_TD_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CP0_TD_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CP0_TD_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_CP0_CEVA_CFG */
+#define BIT_PD_CP0_CEVA_FORCE_SHUTDOWN ( BIT(25) )
+#define BIT_PD_CP0_CEVA_AUTO_SHUTDOWN_EN ( BIT(24) )
+#define BITS_PD_CP0_CEVA_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CP0_CEVA_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CP0_CEVA_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_CP0_SYS_CFG */
+#define BIT_CP0_FORCE_DEEP_SLEEP ( BIT(28) )
+#define BIT_PD_CP0_SYS_FORCE_SHUTDOWN ( BIT(25) )
+#define BITS_PD_CP0_SYS_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CP0_SYS_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CP0_SYS_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_CP1_ARM9_CFG */
+#define BIT_PD_CP1_ARM9_FORCE_SHUTDOWN ( BIT(25) )
+#define BIT_PD_CP1_ARM9_AUTO_SHUTDOWN_EN ( BIT(24) )
+#define BITS_PD_CP1_ARM9_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CP1_ARM9_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CP1_ARM9_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_CP1_GSM_CFG */
+#define BIT_PD_CP1_GSM_FORCE_SHUTDOWN ( BIT(25) )
+#define BIT_PD_CP1_GSM_AUTO_SHUTDOWN_EN ( BIT(24) )
+#define BITS_PD_CP1_GSM_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CP1_GSM_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CP1_GSM_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_CP1_TD_CFG */
+#define BIT_PD_CP1_TD_FORCE_SHUTDOWN ( BIT(25) )
+#define BIT_PD_CP1_TD_AUTO_SHUTDOWN_EN ( BIT(24) )
+#define BITS_PD_CP1_TD_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CP1_TD_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CP1_TD_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_CP1_L1RAM_CFG */
+#define BIT_PD_CP1_L1RAM_FORCE_SHUTDOWN ( BIT(25) )
+#define BIT_PD_CP1_L1RAM_AUTO_SHUTDOWN_EN ( BIT(24) )
+#define BITS_PD_CP1_L1RAM_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CP1_L1RAM_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CP1_L1RAM_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_CP1_SYS_CFG */
+#define BIT_CP1_FORCE_DEEP_SLEEP ( BIT(28) )
+#define BIT_PD_CP1_SYS_FORCE_SHUTDOWN ( BIT(25) )
+#define BITS_PD_CP1_SYS_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CP1_SYS_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CP1_SYS_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_CP2_ARM9_CFG */
+#define BIT_PD_CP2_ARM9_FORCE_SHUTDOWN ( BIT(25) )
+#define BIT_PD_CP2_ARM9_AUTO_SHUTDOWN_EN ( BIT(24) )
+#define BITS_PD_CP2_ARM9_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CP2_ARM9_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CP2_ARM9_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_CP2_WIFI_CFG */
+#define BIT_PD_CP2_WIFI_FORCE_SHUTDOWN ( BIT(25) )
+#define BIT_PD_CP2_WIFI_AUTO_SHUTDOWN_EN ( BIT(24) )
+#define BITS_PD_CP2_WIFI_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CP2_WIFI_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CP2_WIFI_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_AP_WAKEUP_POR_CFG */
+#define BIT_AP_WAKEUP_POR_N ( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_PD_CP2_SYS_CFG */
+#define BIT_CP2_FORCE_DEEP_SLEEP ( BIT(28) )
+#define BIT_PD_CP2_SYS_FORCE_SHUTDOWN ( BIT(25) )
+#define BITS_PD_CP2_SYS_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CP2_SYS_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CP2_SYS_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_PUB_SYS_CFG */
+#define BIT_PD_PUB_SYS_FORCE_SHUTDOWN ( BIT(25) )
+#define BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN ( BIT(24) )
+#define BITS_PD_PUB_SYS_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_PUB_SYS_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_XTL_WAIT_CNT */
+#define BITS_XTL1_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_XTL0_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_XTLBUF_WAIT_CNT */
+#define BITS_XTLBUF1_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_XTLBUF0_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PLL_WAIT_CNT1 */
+#define BITS_WPLL_WAIT_CNT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_TDPLL_WAIT_CNT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DPLL_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_MPLL_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PLL_WAIT_CNT2 */
+#define BITS_WIFIPLL2_WAIT_CNT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_WIFIPLL1_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_CPLL_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_XTL0_REL_CFG */
+#define BIT_XTL0_CP2_SEL ( BIT(3) )
+#define BIT_XTL0_CP1_SEL ( BIT(2) )
+#define BIT_XTL0_CP0_SEL ( BIT(1) )
+#define BIT_XTL0_AP_SEL ( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_XTL1_REL_CFG */
+#define BIT_XTL1_CP2_SEL ( BIT(3) )
+#define BIT_XTL1_CP1_SEL ( BIT(2) )
+#define BIT_XTL1_CP0_SEL ( BIT(1) )
+#define BIT_XTL1_AP_SEL ( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_XTL2_REL_CFG */
+#define BIT_XTL2_CP2_SEL ( BIT(3) )
+#define BIT_XTL2_CP1_SEL ( BIT(2) )
+#define BIT_XTL2_CP0_SEL ( BIT(1) )
+#define BIT_XTL2_AP_SEL ( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_XTLBUF0_REL_CFG */
+#define BIT_XTLBUF0_CP2_SEL ( BIT(3) )
+#define BIT_XTLBUF0_CP1_SEL ( BIT(2) )
+#define BIT_XTLBUF0_CP0_SEL ( BIT(1) )
+#define BIT_XTLBUF0_AP_SEL ( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_XTLBUF1_REL_CFG */
+#define BIT_XTLBUF1_CP2_SEL ( BIT(3) )
+#define BIT_XTLBUF1_CP1_SEL ( BIT(2) )
+#define BIT_XTLBUF1_CP0_SEL ( BIT(1) )
+#define BIT_XTLBUF1_AP_SEL ( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_MPLL_REL_CFG */
+#define BIT_MPLL_REF_SEL ( BIT(4) )
+#define BIT_MPLL_CP2_SEL ( BIT(3) )
+#define BIT_MPLL_CP1_SEL ( BIT(2) )
+#define BIT_MPLL_CP0_SEL ( BIT(1) )
+#define BIT_MPLL_AP_SEL ( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_DPLL_REL_CFG */
+#define BIT_DPLL_REF_SEL ( BIT(4) )
+#define BIT_DPLL_CP2_SEL ( BIT(3) )
+#define BIT_DPLL_CP1_SEL ( BIT(2) )
+#define BIT_DPLL_CP0_SEL ( BIT(1) )
+#define BIT_DPLL_AP_SEL ( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_TDPLL_REL_CFG */
+#define BIT_TDPLL_REF_SEL ( BIT(4) )
+#define BIT_TDPLL_CP2_SEL ( BIT(3) )
+#define BIT_TDPLL_CP1_SEL ( BIT(2) )
+#define BIT_TDPLL_CP0_SEL ( BIT(1) )
+#define BIT_TDPLL_AP_SEL ( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_WPLL_REL_CFG */
+#define BIT_WPLL_REF_SEL ( BIT(4) )
+#define BIT_WPLL_CP2_SEL ( BIT(3) )
+#define BIT_WPLL_CP1_SEL ( BIT(2) )
+#define BIT_WPLL_CP0_SEL ( BIT(1) )
+#define BIT_WPLL_AP_SEL ( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_CPLL_REL_CFG */
+#define BIT_CPLL_REF_SEL ( BIT(4) )
+#define BIT_CPLL_CP2_SEL ( BIT(3) )
+#define BIT_CPLL_CP1_SEL ( BIT(2) )
+#define BIT_CPLL_CP0_SEL ( BIT(1) )
+#define BIT_CPLL_AP_SEL ( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_WIFIPLL1_REL_CFG */
+#define BIT_WIFIPLL1_REF_SEL ( BIT(4) )
+#define BIT_WIFIPLL1_CP2_SEL ( BIT(3) )
+#define BIT_WIFIPLL1_CP1_SEL ( BIT(2) )
+#define BIT_WIFIPLL1_CP0_SEL ( BIT(1) )
+#define BIT_WIFIPLL1_AP_SEL ( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_WIFIPLL2_REL_CFG */
+#define BIT_WIFIPLL2_REF_SEL ( BIT(4) )
+#define BIT_WIFIPLL2_CP2_SEL ( BIT(3) )
+#define BIT_WIFIPLL2_CP1_SEL ( BIT(2) )
+#define BIT_WIFIPLL2_CP0_SEL ( BIT(1) )
+#define BIT_WIFIPLL2_AP_SEL ( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_CP_SOFT_RST */
+#define BIT_PUB_SOFT_RST ( BIT(6) )
+#define BIT_AP_SOFT_RST ( BIT(5) )
+#define BIT_GPU_SOFT_RST ( BIT(4) )
+#define BIT_MM_SOFT_RST ( BIT(3) )
+#define BIT_CP2_SOFT_RST ( BIT(2) )
+#define BIT_CP1_SOFT_RST ( BIT(1) )
+#define BIT_CP0_SOFT_RST ( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_CP_SLP_STATUS_DBG0 */
+#define BITS_CP1_DEEP_SLP_DBG(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_CP0_DEEP_SLP_DBG(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_PMU_APB_CP_SLP_STATUS_DBG1 */
+#define BITS_CP2_DEEP_SLP_DBG(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_PMU_APB_PWR_STATUS0_DBG */
+#define BITS_PD_MM_TOP_STATE(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_PD_GPU_TOP_STATE(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_PD_CA7_C3_STATE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_PD_CA7_C2_STATE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CA7_C1_STATE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_PD_CA7_C0_STATE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_PD_CA7_TOP_STATE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PMU_APB_PWR_STATUS1_DBG */
+#define BITS_PD_CP0_SYS_STATE(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_PD_CP0_GSM_STATE(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CP0_HU3GE_STATE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_PD_CP0_ARM9_2_STATE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CP0_ARM9_1_STATE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_PD_CP0_ARM9_0_STATE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_PD_AP_SYS_STATE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PMU_APB_PWR_STATUS2_DBG */
+#define BITS_PD_CP2_WIFI_STATE(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_PD_CP2_ARM9_STATE(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CP1_SYS_STATE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_PD_CP1_L1RAM_STATE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CP1_TD_STATE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_PD_CP1_GSM_STATE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_PD_CP1_ARM9_STATE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PMU_APB_PWR_STATUS3_DBG */
+#define BITS_PD_CP0_CEVA_STATE(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CP0_TD_STATE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_PD_DDR_PHY_STATE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_DDR_PUBL_STATE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_PD_PUB_SYS_STATE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_PD_CP2_SYS_STATE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PMU_APB_SLEEP_CTRL */
+#define BIT_CP0_FORCE_SLEEP ( BIT(12) )
+#define BIT_CP2_SLEEP_XTL_ON ( BIT(11) )
+#define BIT_CP1_SLEEP_XTL_ON ( BIT(10) )
+#define BIT_CP0_SLEEP_XTL_ON ( BIT(9) )
+#define BIT_AP_SLEEP_XTL_ON ( BIT(8) )
+#define BIT_DISP_DEEP_SLEEP ( BIT(6) )
+#define BIT_GPU_DEEP_SLEEP ( BIT(5) )
+#define BIT_MM_DEEP_SLEEP ( BIT(4) )
+#define BIT_CP2_DEEP_SLEEP ( BIT(3) )
+#define BIT_CP1_DEEP_SLEEP ( BIT(2) )
+#define BIT_CP0_DEEP_SLEEP ( BIT(1) )
+#define BIT_AP_DEEP_SLEEP ( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_DDR_SLEEP_CTRL */
+#define BIT_DDR_PUBL_APB_SOFT_RST ( BIT(12) )
+#define BIT_DDR_UMCTL_APB_SOFT_RST ( BIT(11) )
+#define BIT_DDR_PUBL_SOFT_RST ( BIT(10) )
+#define BIT_DDR_PHY_SOFT_RST ( BIT(8) )
+#define BIT_DDR_PHY_AUTO_GATE_EN ( BIT(6) )
+#define BIT_DDR_PUBL_AUTO_GATE_EN ( BIT(5) )
+#define BIT_DDR_UMCTL_AUTO_GATE_EN ( BIT(4) )
+#define BIT_DDR_PHY_EB ( BIT(2) )
+#define BIT_DDR_UMCTL_EB ( BIT(1) )
+#define BIT_DDR_PUBL_EB ( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_SLEEP_STATUS */
+#define BITS_CP2_SLP_STATUS(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_CP1_SLP_STATUS(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_CP0_SLP_STATUS(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_AP_SLP_STATUS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PMU_APB_PLL_DIV_AUTO_GATE_EN */
+#define BIT_WIFIPLL2_DIV_AUTO_GATE_EN ( BIT(6) )
+#define BIT_WIFIPLL1_DIV_AUTO_GATE_EN ( BIT(5) )
+#define BIT_WPLL_DIV_AUTO_GATE_EN ( BIT(4) )
+#define BIT_TDPLL_DIV_AUTO_GATE_EN ( BIT(3) )
+#define BIT_CPLL_DIV_AUTO_GATE_EN ( BIT(2) )
+#define BIT_DPLL_DIV_AUTO_GATE_EN ( BIT(1) )
+#define BIT_MPLL_DIV_AUTO_GATE_EN ( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_PLL_DIV_EN1 */
+#define BIT_WIFIPLL2_80M_EN ( BIT(31) )
+#define BIT_WIFIPLL2_160M_EN ( BIT(30) )
+#define BIT_WIFIPLL2_120M_EN ( BIT(29) )
+#define BIT_WIFIPLL1_20M_EN ( BIT(28) )
+#define BIT_WIFIPLL1_40M_EN ( BIT(27) )
+#define BIT_WIFIPLL1_80M_EN ( BIT(26) )
+#define BIT_WIFIPLL1_44M_EN ( BIT(25) )
+#define BIT_WPLL_76M8_EN ( BIT(24) )
+#define BIT_WPLL_51M2_EN ( BIT(23) )
+#define BIT_WPLL_102M4_EN ( BIT(22) )
+#define BIT_WPLL_307M2_EN ( BIT(21) )
+#define BIT_WPLL_460M8_EN ( BIT(20) )
+#define BIT_CPLL_52M_EN ( BIT(19) )
+#define BIT_CPLL_104M_EN ( BIT(18) )
+#define BIT_CPLL_208M_EN ( BIT(17) )
+#define BIT_CPLL_312M_EN ( BIT(16) )
+#define BIT_TDPLL_38M4_EN ( BIT(15) )
+#define BIT_TDPLL_76M8_EN ( BIT(14) )
+#define BIT_TDPLL_51M2_EN ( BIT(13) )
+#define BIT_TDPLL_153M6_EN ( BIT(12) )
+#define BIT_TDPLL_64M_EN ( BIT(11) )
+#define BIT_TDPLL_128M_EN ( BIT(10) )
+#define BIT_TDPLL_256M_EN ( BIT(9) )
+#define BIT_TDPLL_12M_EN ( BIT(8) )
+#define BIT_TDPLL_24M_EN ( BIT(7) )
+#define BIT_TDPLL_48M_EN ( BIT(6) )
+#define BIT_TDPLL_96M_EN ( BIT(5) )
+#define BIT_TDPLL_192M_EN ( BIT(4) )
+#define BIT_TDPLL_384M_EN ( BIT(3) )
+#define BIT_DPLL_44M_EN ( BIT(2) )
+#define BIT_MPLL_37M5_EN ( BIT(1) )
+#define BIT_MPLL_300M_EN ( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_PLL_DIV_EN2 */
+#define BIT_DPLL_533M_EN ( BIT(2) )
+#define BIT_WIFIPLL2_20M_EN ( BIT(1) )
+#define BIT_WIFIPLL2_40M_EN ( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_CA7_TOP_CFG */
+#define BIT_CA7_L2RSTDISABLE ( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_CA7_C0_CFG */
+#define BIT_CA7_VINITHI_C0 ( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_CA7_C1_CFG */
+#define BIT_CA7_VINITHI_C1 ( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_CA7_C2_CFG */
+#define BIT_CA7_VINITHI_C2 ( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_CA7_C3_CFG */
+#define BIT_CA7_VINITHI_C3 ( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_DDR_CHN_SLEEP_CTRL0 */
+#define BIT_DDR_CTRL_AXI_LP_EN ( BIT(31) )
+#define BIT_DDR_CTRL_CGM_SEL ( BIT(30) )
+#define BIT_DDR_CHN9_AXI_LP_EN ( BIT(25) )
+#define BIT_DDR_CHN8_AXI_LP_EN ( BIT(24) )
+#define BIT_DDR_CHN7_AXI_LP_EN ( BIT(23) )
+#define BIT_DDR_CHN6_AXI_LP_EN ( BIT(22) )
+#define BIT_DDR_CHN5_AXI_LP_EN ( BIT(21) )
+#define BIT_DDR_CHN4_AXI_LP_EN ( BIT(20) )
+#define BIT_DDR_CHN3_AXI_LP_EN ( BIT(19) )
+#define BIT_DDR_CHN2_AXI_LP_EN ( BIT(18) )
+#define BIT_DDR_CHN1_AXI_LP_EN ( BIT(17) )
+#define BIT_DDR_CHN0_AXI_LP_EN ( BIT(16) )
+#define BIT_DDR_CHN9_CGM_SEL ( BIT(9) )
+#define BIT_DDR_CHN8_CGM_SEL ( BIT(8) )
+#define BIT_DDR_CHN7_CGM_SEL ( BIT(7) )
+#define BIT_DDR_CHN6_CGM_SEL ( BIT(6) )
+#define BIT_DDR_CHN5_CGM_SEL ( BIT(5) )
+#define BIT_DDR_CHN4_CGM_SEL ( BIT(4) )
+#define BIT_DDR_CHN3_CGM_SEL ( BIT(3) )
+#define BIT_DDR_CHN2_CGM_SEL ( BIT(2) )
+#define BIT_DDR_CHN1_CGM_SEL ( BIT(1) )
+#define BIT_DDR_CHN0_CGM_SEL ( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_DDR_CHN_SLEEP_CTRL1 */
+#define BIT_DDR_CHN9_AXI_STOP_SEL ( BIT(9) )
+#define BIT_DDR_CHN8_AXI_STOP_SEL ( BIT(8) )
+#define BIT_DDR_CHN7_AXI_STOP_SEL ( BIT(7) )
+#define BIT_DDR_CHN6_AXI_STOP_SEL ( BIT(6) )
+#define BIT_DDR_CHN5_AXI_STOP_SEL ( BIT(5) )
+#define BIT_DDR_CHN4_AXI_STOP_SEL ( BIT(4) )
+#define BIT_DDR_CHN3_AXI_STOP_SEL ( BIT(3) )
+#define BIT_DDR_CHN2_AXI_STOP_SEL ( BIT(2) )
+#define BIT_DDR_CHN1_AXI_STOP_SEL ( BIT(1) )
+#define BIT_DDR_CHN0_AXI_STOP_SEL ( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_BISR_CFG */
+#define BIT_PD_CP0_CEVA_BISR_DONE ( BIT(31) )
+#define BIT_PD_CP0_TD_BISR_DONE ( BIT(30) )
+#define BIT_PD_CP1_TD_BISR_DONE ( BIT(29) )
+#define BIT_PD_CP1_SYS_BISR_DONE ( BIT(28) )
+#define BIT_PD_CP0_HU3GE_BISR_DONE ( BIT(27) )
+#define BIT_PD_CP0_SYS_BISR_DONE ( BIT(26) )
+#define BIT_PD_MM_TOP_BISR_DONE ( BIT(25) )
+#define BIT_PD_GPU_TOP_BISR_DONE ( BIT(24) )
+#define BIT_PD_CP0_CEVA_BISR_BUSY ( BIT(23) )
+#define BIT_PD_CP0_TD_BISR_BUSY ( BIT(22) )
+#define BIT_PD_CP1_TD_BISR_BUSY ( BIT(21) )
+#define BIT_PD_CP1_SYS_BISR_BUSY ( BIT(20) )
+#define BIT_PD_CP0_HU3GE_BISR_BUSY ( BIT(19) )
+#define BIT_PD_CP0_SYS_BISR_BUSY ( BIT(18) )
+#define BIT_PD_MM_TOP_BISR_BUSY ( BIT(17) )
+#define BIT_PD_GPU_TOP_BISR_BUSY ( BIT(16) )
+#define BIT_PD_CP0_CEVA_BISR_FORCE_EN ( BIT(15) )
+#define BIT_PD_CP0_TD_BISR_FORCE_EN ( BIT(14) )
+#define BIT_PD_CP1_TD_BISR_FORCE_EN ( BIT(13) )
+#define BIT_PD_CP1_SYS_BISR_FORCE_EN ( BIT(12) )
+#define BIT_PD_CP0_HU3GE_BISR_FORCE_EN ( BIT(11) )
+#define BIT_PD_CP0_SYS_BISR_FORCE_EN ( BIT(10) )
+#define BIT_PD_MM_TOP_BISR_FORCE_EN ( BIT(9) )
+#define BIT_PD_GPU_TOP_BISR_FORCE_EN ( BIT(8) )
+#define BIT_PD_CP1_TD_BISR_FORCE_BYP ( BIT(7) )
+#define BIT_PD_CP0_CEVA_BISR_FORCE_BYP ( BIT(6) )
+#define BIT_PD_CP0_TD_BISR_FORCE_BYP ( BIT(5) )
+#define BIT_PD_CP1_SYS_BISR_FORCE_BYP ( BIT(4) )
+#define BIT_PD_CP0_HU3GE_BISR_FORCE_BYP ( BIT(3) )
+#define BIT_PD_CP0_SYS_BISR_FORCE_BYP ( BIT(2) )
+#define BIT_PD_MM_TOP_BISR_FORCE_BYP ( BIT(1) )
+#define BIT_PD_GPU_TOP_BISR_FORCE_BYP ( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_CGM_AP_AUTO_GATE_EN */
+#define BIT_CGM_208M_AP_AUTO_GATE_EN ( BIT(20) )
+#define BIT_CGM_12M_AP_AUTO_GATE_EN ( BIT(19) )
+#define BIT_CGM_24M_AP_AUTO_GATE_EN ( BIT(18) )
+#define BIT_CGM_48M_AP_AUTO_GATE_EN ( BIT(17) )
+#define BIT_CGM_51M2_AP_AUTO_GATE_EN ( BIT(16) )
+#define BIT_CGM_64M_AP_AUTO_GATE_EN ( BIT(15) )
+#define BIT_CGM_76M8_AP_AUTO_GATE_EN ( BIT(14) )
+#define BIT_CGM_96M_AP_AUTO_GATE_EN ( BIT(13) )
+#define BIT_CGM_128M_AP_AUTO_GATE_EN ( BIT(12) )
+#define BIT_CGM_153M6_AP_AUTO_GATE_EN ( BIT(11) )
+#define BIT_CGM_192M_AP_AUTO_GATE_EN ( BIT(10) )
+#define BIT_CGM_256M_AP_AUTO_GATE_EN ( BIT(9) )
+#define BIT_CGM_384M_AP_AUTO_GATE_EN ( BIT(8) )
+#define BIT_CGM_312M_AP_AUTO_GATE_EN ( BIT(7) )
+#define BIT_CGM_MPLL_AP_AUTO_GATE_EN ( BIT(6) )
+#define BIT_CGM_WPLL_AP_AUTO_GATE_EN ( BIT(5) )
+#define BIT_CGM_WIFIPLL1_AP_AUTO_GATE_EN ( BIT(4) )
+#define BIT_CGM_TDPLL_AP_AUTO_GATE_EN ( BIT(3) )
+#define BIT_CGM_CPLL_AP_AUTO_GATE_EN ( BIT(2) )
+#define BIT_CGM_DPLL_AP_AUTO_GATE_EN ( BIT(1) )
+#define BIT_CGM_26M_AP_AUTO_GATE_EN ( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_CGM_GPU_MM_AUTO_GATE_EN */
+#define BIT_CGM_312M_MM_AUTO_GATE_EN ( BIT(27) )
+#define BIT_CGM_12M_MM_AUTO_GATE_EN ( BIT(26) )
+#define BIT_CGM_24M_MM_AUTO_GATE_EN ( BIT(25) )
+#define BIT_CGM_48M_MM_AUTO_GATE_EN ( BIT(24) )
+#define BIT_CGM_64M_MM_AUTO_GATE_EN ( BIT(23) )
+#define BIT_CGM_76M8_MM_AUTO_GATE_EN ( BIT(22) )
+#define BIT_CGM_96M_MM_AUTO_GATE_EN ( BIT(21) )
+#define BIT_CGM_128M_MM_AUTO_GATE_EN ( BIT(20) )
+#define BIT_CGM_153M6_MM_AUTO_GATE_EN ( BIT(19) )
+#define BIT_CGM_192M_MM_AUTO_GATE_EN ( BIT(18) )
+#define BIT_CGM_256M_MM_AUTO_GATE_EN ( BIT(17) )
+#define BIT_CGM_26M_MM_AUTO_GATE_EN ( BIT(16) )
+#define BIT_CGM_153_6M_GPU_AUTO_GATE_EN ( BIT(6) )
+#define BIT_CGM_384M_GPU_AUTO_GATE_EN ( BIT(5) )
+#define BIT_CGM_460_8M_GPU_AUTO_GATE_EN ( BIT(4) )
+#define BIT_CGM_256M_GPU_AUTO_GATE_EN ( BIT(3) )
+#define BIT_CGM_208M_GPU_AUTO_GATE_EN ( BIT(2) )
+#define BIT_CGM_312M_GPU_AUTO_GATE_EN ( BIT(1) )
+#define BIT_CGM_300M_GPU_AUTO_GATE_EN ( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_CGM_CP0_AUTO_GATE_EN */
+#define BIT_CGM_312M_CP0_AUTO_GATE_EN ( BIT(16) )
+#define BIT_CGM_208M_CP0_AUTO_GATE_EN ( BIT(15) )
+#define BIT_CGM_256M_CP0_AUTO_GATE_EN ( BIT(14) )
+#define BIT_CGM_460M8_CP0W_AUTO_GATE_EN ( BIT(13) )
+#define BIT_CGM_307M2_CP0W_AUTO_GATE_EN ( BIT(12) )
+#define BIT_CGM_51M2_CP0W_AUTO_GATE_EN ( BIT(11) )
+#define BIT_CGM_76M8_CP0W_AUTO_GATE_EN ( BIT(10) )
+#define BIT_CGM_102M4_CP0W_AUTO_GATE_EN ( BIT(9) )
+#define BIT_CGM_192M_CP0_AUTO_GATE_EN ( BIT(8) )
+#define BIT_CGM_51M2_CP0_AUTO_GATE_EN ( BIT(7) )
+#define BIT_CGM_76M8_CP0_AUTO_GATE_EN ( BIT(6) )
+#define BIT_CGM_153M6_CP0_AUTO_GATE_EN ( BIT(5) )
+#define BIT_CGM_48M_CP0_AUTO_GATE_EN ( BIT(4) )
+#define BIT_CGM_64M_CP0_AUTO_GATE_EN ( BIT(3) )
+#define BIT_CGM_96M_CP0_AUTO_GATE_EN ( BIT(2) )
+#define BIT_CGM_128M_CP0_AUTO_GATE_EN ( BIT(1) )
+#define BIT_CGM_26M_CP0_AUTO_GATE_EN ( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_CGM_CP1_AUTO_GATE_EN */
+#define BIT_CGM_312M_CP1_AUTO_GATE_EN ( BIT(10) )
+#define BIT_CGM_256M_CP1_AUTO_GATE_EN ( BIT(9) )
+#define BIT_CGM_192M_CP1_AUTO_GATE_EN ( BIT(8) )
+#define BIT_CGM_51M2_CP1_AUTO_GATE_EN ( BIT(7) )
+#define BIT_CGM_76M8_CP1_AUTO_GATE_EN ( BIT(6) )
+#define BIT_CGM_153M6_CP1_AUTO_GATE_EN ( BIT(5) )
+#define BIT_CGM_48M_CP1_AUTO_GATE_EN ( BIT(4) )
+#define BIT_CGM_96M_CP1_AUTO_GATE_EN ( BIT(3) )
+#define BIT_CGM_64M_CP1_AUTO_GATE_EN ( BIT(2) )
+#define BIT_CGM_128M_CP1_AUTO_GATE_EN ( BIT(1) )
+#define BIT_CGM_26M_CP1_AUTO_GATE_EN ( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_CGM_CP2_AUTO_GATE_EN */
+#define BIT_CGM_153M6_CP2_AUTO_GATE_EN ( BIT(12) )
+#define BIT_CGM_20M_CP2WF2_AUTO_GATE_EN ( BIT(11) )
+#define BIT_CGM_80M_CP2WF2_AUTO_GATE_EN ( BIT(10) )
+#define BIT_CGM_120M_CP2WF2_AUTO_GATE_EN ( BIT(9) )
+#define BIT_CGM_160M_CP2WF2_AUTO_GATE_EN ( BIT(8) )
+#define BIT_CGM_20M_CP2WF1_AUTO_GATE_EN ( BIT(7) )
+#define BIT_CGM_44M_CP2WF1_AUTO_GATE_EN ( BIT(6) )
+#define BIT_CGM_80M_CP2WF1_AUTO_GATE_EN ( BIT(5) )
+#define BIT_CGM_256M_CP2_AUTO_GATE_EN ( BIT(4) )
+#define BIT_CGM_104M_CP2_AUTO_GATE_EN ( BIT(3) )
+#define BIT_CGM_208M_CP2_AUTO_GATE_EN ( BIT(2) )
+#define BIT_CGM_312M_CP2_AUTO_GATE_EN ( BIT(1) )
+#define BIT_CGM_26M_CP2_AUTO_GATE_EN ( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_CGM_AP_EN */
+#define BIT_CGM_208M_AP_EN ( BIT(20) )
+#define BIT_CGM_12M_AP_EN ( BIT(19) )
+#define BIT_CGM_24M_AP_EN ( BIT(18) )
+#define BIT_CGM_48M_AP_EN ( BIT(17) )
+#define BIT_CGM_51M2_AP_EN ( BIT(16) )
+#define BIT_CGM_64M_AP_EN ( BIT(15) )
+#define BIT_CGM_76M8_AP_EN ( BIT(14) )
+#define BIT_CGM_96M_AP_EN ( BIT(13) )
+#define BIT_CGM_128M_AP_EN ( BIT(12) )
+#define BIT_CGM_153M6_AP_EN ( BIT(11) )
+#define BIT_CGM_192M_AP_EN ( BIT(10) )
+#define BIT_CGM_256M_AP_EN ( BIT(9) )
+#define BIT_CGM_384M_AP_EN ( BIT(8) )
+#define BIT_CGM_312M_AP_EN ( BIT(7) )
+#define BIT_CGM_MPLL_AP_EN ( BIT(6) )
+#define BIT_CGM_WPLL_AP_EN ( BIT(5) )
+#define BIT_CGM_WIFIPLL1_AP_EN ( BIT(4) )
+#define BIT_CGM_TDPLL_AP_EN ( BIT(3) )
+#define BIT_CGM_CPLL_AP_EN ( BIT(2) )
+#define BIT_CGM_DPLL_AP_EN ( BIT(1) )
+#define BIT_CGM_26M_AP_EN ( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_CGM_GPU_MM_EN */
+#define BIT_CGM_312M_MM_EN ( BIT(27) )
+#define BIT_CGM_12M_MM_EN ( BIT(26) )
+#define BIT_CGM_24M_MM_EN ( BIT(25) )
+#define BIT_CGM_48M_MM_EN ( BIT(24) )
+#define BIT_CGM_64M_MM_EN ( BIT(23) )
+#define BIT_CGM_76M8_MM_EN ( BIT(22) )
+#define BIT_CGM_96M_MM_EN ( BIT(21) )
+#define BIT_CGM_128M_MM_EN ( BIT(20) )
+#define BIT_CGM_153M6_MM_EN ( BIT(19) )
+#define BIT_CGM_192M_MM_EN ( BIT(18) )
+#define BIT_CGM_256M_MM_EN ( BIT(17) )
+#define BIT_CGM_26M_MM_EN ( BIT(16) )
+#define BIT_CGM_153_6M_GPU_EN ( BIT(6) )
+#define BIT_CGM_384M_GPU_EN ( BIT(5) )
+#define BIT_CGM_460_8M_GPU_EN ( BIT(4) )
+#define BIT_CGM_256M_GPU_EN ( BIT(3) )
+#define BIT_CGM_208M_GPU_EN ( BIT(2) )
+#define BIT_CGM_312M_GPU_EN ( BIT(1) )
+#define BIT_CGM_300M_GPU_EN ( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_CGM_CP0_EN */
+#define BIT_CGM_312M_CP0_EN ( BIT(16) )
+#define BIT_CGM_208M_CP0_EN ( BIT(15) )
+#define BIT_CGM_256M_CP0_EN ( BIT(14) )
+#define BIT_CGM_460M8_CP0W_EN ( BIT(13) )
+#define BIT_CGM_307M2_CP0W_EN ( BIT(12) )
+#define BIT_CGM_51M2_CP0W_EN ( BIT(11) )
+#define BIT_CGM_76M8_CP0W_EN ( BIT(10) )
+#define BIT_CGM_102M4_CP0W_EN ( BIT(9) )
+#define BIT_CGM_192M_CP0_EN ( BIT(8) )
+#define BIT_CGM_51M2_CP0_EN ( BIT(7) )
+#define BIT_CGM_76M8_CP0_EN ( BIT(6) )
+#define BIT_CGM_153M6_CP0_EN ( BIT(5) )
+#define BIT_CGM_48M_CP0_EN ( BIT(4) )
+#define BIT_CGM_64M_CP0_EN ( BIT(3) )
+#define BIT_CGM_96M_CP0_EN ( BIT(2) )
+#define BIT_CGM_128M_CP0_EN ( BIT(1) )
+#define BIT_CGM_26M_CP0_EN ( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_CGM_CP1_EN */
+#define BIT_CGM_312M_CP1_EN ( BIT(10) )
+#define BIT_CGM_256M_CP1_EN ( BIT(9) )
+#define BIT_CGM_192M_CP1_EN ( BIT(8) )
+#define BIT_CGM_51M2_CP1_EN ( BIT(7) )
+#define BIT_CGM_76M8_CP1_EN ( BIT(6) )
+#define BIT_CGM_153M6_CP1_EN ( BIT(5) )
+#define BIT_CGM_48M_CP1_EN ( BIT(4) )
+#define BIT_CGM_96M_CP1_EN ( BIT(3) )
+#define BIT_CGM_64M_CP1_EN ( BIT(2) )
+#define BIT_CGM_128M_CP1_EN ( BIT(1) )
+#define BIT_CGM_26M_CP1_EN ( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_CGM_CP2_EN */
+#define BIT_CGM_153M6_CP2_EN ( BIT(12) )
+#define BIT_CGM_20M_CP2WF2_EN ( BIT(11) )
+#define BIT_CGM_80M_CP2WF2_EN ( BIT(10) )
+#define BIT_CGM_120M_CP2WF2_EN ( BIT(9) )
+#define BIT_CGM_160M_CP2WF2_EN ( BIT(8) )
+#define BIT_CGM_20M_CP2WF1_EN ( BIT(7) )
+#define BIT_CGM_44M_CP2WF1_EN ( BIT(6) )
+#define BIT_CGM_80M_CP2WF1_EN ( BIT(5) )
+#define BIT_CGM_256M_CP2_EN ( BIT(4) )
+#define BIT_CGM_104M_CP2_EN ( BIT(3) )
+#define BIT_CGM_208M_CP2_EN ( BIT(2) )
+#define BIT_CGM_312M_CP2_EN ( BIT(1) )
+#define BIT_CGM_26M_CP2_EN ( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_DDR_OP_MODE_CFG */
+#define BIT_DDR_PHY_RET_EN ( BIT(28) )
+#define BIT_DDR_PUBL_RET_EN ( BIT(27) )
+#define BIT_DDR_PHY_ISO_RST_EN ( BIT(26) )
+#define BIT_DDR_UMCTL_RET_EN ( BIT(25) )
+#define BIT_DDR_PHY_AUTO_RET_EN ( BIT(24) )
+#define BITS_DDR_OPERATE_MODE_CNT_LMT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DDR_OPERATE_MODE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) )
+#define BITS_DDR_OPERATE_MODE_IDLE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
+
+/* bits definitions for register REG_PMU_APB_DDR_PHY_RET_CFG */
+#define BIT_DDR_UMCTL_SOFT_RST ( BIT(16) )
+#define BIT_DDR_PHY_CKE_RET_EN ( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_26M_SEL_CFG */
+#define BIT_AON_MEM_PD_EN_CP2 ( BIT(9) )
+#define BIT_AON_MEM_PD_EN_CP0 ( BIT(8) )
+#define BIT_AON_MEM_PD_EN_AP ( BIT(7) )
+#define BIT_LPLL_REF_SEL ( BIT(6) )
+#define BIT_PUB_26M_SEL ( BIT(5) )
+#define BIT_AON_26M_SEL ( BIT(4) )
+#define BIT_CP2_26M_SEL ( BIT(3) )
+#define BIT_CP1_26M_SEL ( BIT(2) )
+#define BIT_CP0_26M_SEL ( BIT(1) )
+#define BIT_AP_26M_SEL ( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_MEM_PD_CFG0 */
+#define BITS_CP0_W_MEM_PD_CFG_UART1(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)) )
+#define BITS_CP0_W_MEM_PD_CFG_UART0(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)) )
+#define BITS_CP0_W_MEM_PD_CFG_IRAM(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
+#define BITS_CP0_W_MEM_PD_CFG_PERIF(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_AON_MEM_PD_CFG_IRAM(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) )
+#define BITS_AON_MEM_PD_CFG_IMC3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) )
+#define BITS_AON_MEM_PD_CFG_IMC2(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
+#define BITS_AON_MEM_PD_CFG_IMC1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_AON_MEM_PD_CFG_IMC0(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) )
+#define BITS_AON_MEM_PD_CFG_VBC(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_AON_MEM_PD_CFG_AUD(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_AON_MEM_PD_CFG_FM(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_PMU_APB_MEM_PD_CFG1 */
+#define BITS_CP0_DSP_MEM_PD_CFG_DMA(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
+#define BITS_CP0_DSP_MEM_PD_CFG_SHM(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)) )
+#define BITS_CP0_DSP_MEM_PD_CFG_RFT(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)) )
+#define BITS_CP0_DSP_MEM_PD_CFG_STC(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
+#define BITS_CP0_ARM_MEM_PD_CFG_IIS3(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_CP0_ARM_MEM_PD_CFG_IIS2(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) )
+#define BITS_CP0_ARM_MEM_PD_CFG_IIS1(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) )
+#define BITS_CP0_ARM_MEM_PD_CFG_IIS0(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
+#define BITS_CP0_ARM_MEM_PD_CFG_UART1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_CP0_ARM_MEM_PD_CFG_UART0(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) )
+#define BITS_CP0_ARM_MEM_PD_CFG_EPT(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_CP0_ARM_MEM_PD_CFG_LZMA(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_CP0_ARM_MEM_PD_CFG_DMA(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_PMU_APB_PD_DDR_PUBL_CFG */
+#define BIT_PD_DDR_PUBL_FORCE_SHUTDOWN ( BIT(25) )
+#define BIT_PD_DDR_PUBL_AUTO_SHUTDOWN_EN ( BIT(24) )
+#define BITS_PD_DDR_PUBL_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_DDR_PUBL_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_DDR_PUBL_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_DDR_PHY_CFG */
+#define BIT_PD_DDR_PHY_FORCE_SHUTDOWN ( BIT(25) )
+#define BIT_PD_DDR_PHY_AUTO_SHUTDOWN_EN ( BIT(24) )
+#define BITS_PD_DDR_PHY_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_DDR_PHY_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_DDR_PHY_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_BISR_CFG2 */
+#define BIT_PD_CP2_WIFI_BISR_DONE ( BIT(7) )
+#define BIT_PD_AP_SYS_BISR_DONE ( BIT(6) )
+#define BIT_PD_CP2_WIFI_BISR_BUSY ( BIT(5) )
+#define BIT_PD_AP_SYS_BISR_BUSY ( BIT(4) )
+#define BIT_PD_CP2_WIFI_BISR_FORCE_EN ( BIT(3) )
+#define BIT_PD_AP_SYS_BISR_FORCE_EN ( BIT(2) )
+#define BIT_PD_CP2_WIFI_BISR_FORCE_BYP ( BIT(1) )
+#define BIT_PD_AP_SYS_BISR_FORCE_BYP ( BIT(0) )
+
+#endif
diff --git a/include/soc/sprd/chip_x30g/__regs_pmu_apb_tshark2.h b/include/soc/sprd/chip_x30g/__regs_pmu_apb_tshark2.h new file mode 100644 index 00000000..6866f9d6 --- /dev/null +++ b/include/soc/sprd/chip_x30g/__regs_pmu_apb_tshark2.h @@ -0,0 +1,914 @@ +/* the head file modifier: ang 2015-01-21 14:39:32*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_PMU_APB_HEADFILE_H__ +#define __H_REGS_PMU_APB_HEADFILE_H__ __FILE__ + +#define REGS_PMU_APB + +/* registers definitions for PMU_APB */ +#define REG_PMU_APB_PD_CA7_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0000)/*PD_CA7_TOP_CFG*/ +#define REG_PMU_APB_PD_CA7_C0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0004)/*PD_CA7_C0_CFG*/ +#define REG_PMU_APB_PD_CA7_C1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0008)/*PD_CA7_C1_CFG*/ +#define REG_PMU_APB_PD_CA7_C2_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x000C)/*PD_CA7_C2_CFG*/ +#define REG_PMU_APB_PD_CA7_C3_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0010)/*PD_CA7_C3_CFG*/ +#define REG_PMU_APB_PD_AP_DISP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0014)/*PD_AP_DISP_CFG*/ +#define REG_PMU_APB_PD_AP_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0018)/*PD_AP_SYS_CFG*/ +#define REG_PMU_APB_PD_MM_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x001C)/*PD_MM_TOP_CFG*/ +#define REG_PMU_APB_PD_GPU_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0020)/*PD_GPU_TOP_CFG*/ +#define REG_PMU_APB_PD_CP0_ARM9_0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0024)/*PD_CP0_ARM9_0_CFG*/ +#define REG_PMU_APB_PD_CP0_ARM9_1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0028)/*PD_CP0_ARM9_1_CFG*/ +#define REG_PMU_APB_PD_CP0_ARM9_2_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x002C)/*PD_CP0_ARM9_2_CFG*/ +#define REG_PMU_APB_PD_CP0_HU3GE_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0030)/*PD_CP0_HU3GE_CFG*/ +#define REG_PMU_APB_PD_CP0_GSM_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0034)/*PD_CP0_GSM_CFG*/ +#define REG_PMU_APB_PD_CP0_TD_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0038)/*PD_CP0_TD_CFG*/ +#define REG_PMU_APB_PD_CP0_CEVA_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x003C)/*PD_CP0_CEVA_CFG*/ +#define REG_PMU_APB_PD_CP0_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0044)/*PD_CP0_SYS_CFG*/ +#define REG_PMU_APB_PD_CP1_ARM9_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0048)/*PD_CP1_ARM9_CFG*/ +#define REG_PMU_APB_PD_CP1_GSM_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x004C)/*PD_CP1_GSM_CFG*/ +#define REG_PMU_APB_PD_CP1_TD_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0050)/*PD_CP1_TD_CFG*/ +#define REG_PMU_APB_PD_CP1_L1RAM_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0054)/*PD_CP1_L1RAM_CFG*/ +#define REG_PMU_APB_PD_CP1_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0058)/*PD_CP1_SYS_CFG*/ +#define REG_PMU_APB_PD_CP2_ARM9_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x005C)/*PD_CP2_ARM9_CFG*/ +#define REG_PMU_APB_PD_CP2_WIFI_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0060)/*PD_CP2_WIFI_CFG*/ +#define REG_PMU_APB_AP_WAKEUP_POR_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0064)/*AP_WAKEUP_POR_CFG*/ +#define REG_PMU_APB_PD_CP2_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0068)/*PD_CP2_SYS_CFG*/ +#define REG_PMU_APB_PD_PUB_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x006C)/*PD_PUB_SYS_CFG*/ +#define REG_PMU_APB_XTL_WAIT_CNT SCI_ADDR(REGS_PMU_APB_BASE, 0x0070)/*XTL_WAIT_CNT*/ +#define REG_PMU_APB_XTLBUF_WAIT_CNT SCI_ADDR(REGS_PMU_APB_BASE, 0x0074)/*XTLBUF_WAIT_CNT*/ +#define REG_PMU_APB_PLL_WAIT_CNT1 SCI_ADDR(REGS_PMU_APB_BASE, 0x0078)/*PLL_WAIT_CNT1*/ +#define REG_PMU_APB_PLL_WAIT_CNT2 SCI_ADDR(REGS_PMU_APB_BASE, 0x007C)/*PLL_WAIT_CNT2*/ +#define REG_PMU_APB_XTL0_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0080)/*XTL0_REL_CFG*/ +#define REG_PMU_APB_XTL1_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0084)/*XTL1_REL_CFG*/ +#define REG_PMU_APB_XTL2_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0088)/*XTL1_REL_CFG*/ +#define REG_PMU_APB_XTLBUF0_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x008C)/*XTLBUF0_REL_CFG*/ +#define REG_PMU_APB_XTLBUF1_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0090)/*XTLBUF1_REL_CFG*/ +#define REG_PMU_APB_MPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0094)/*MPLL_REL_CFG*/ +#define REG_PMU_APB_DPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0098)/*DPLL_REL_CFG*/ +#define REG_PMU_APB_TDPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x009C)/*TDPLL_REL_CFG*/ +#define REG_PMU_APB_WPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00A0)/*WPLL_REL_CFG*/ +#define REG_PMU_APB_CPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00A4)/*CPLL_REL_CFG*/ +#define REG_PMU_APB_WIFIPLL1_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00A8)/*WIFIPLL1_REL_CFG*/ +#define REG_PMU_APB_WIFIPLL2_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00AC)/*WIFIPLL2_REL_CFG*/ +#define REG_PMU_APB_CP_SOFT_RST SCI_ADDR(REGS_PMU_APB_BASE, 0x00B0)/*CP_SOFT_RST*/ +#define REG_PMU_APB_CP_SLP_STATUS_DBG0 SCI_ADDR(REGS_PMU_APB_BASE, 0x00B4)/*CP_SLP_STATUS_DBG0*/ +#define REG_PMU_APB_CP_SLP_STATUS_DBG1 SCI_ADDR(REGS_PMU_APB_BASE, 0x00B8)/*CP_SLP_STATUS_DBG1*/ +#define REG_PMU_APB_PWR_STATUS0_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00BC)/*PWR_STATUS0_DBG*/ +#define REG_PMU_APB_PWR_STATUS1_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00C0)/*PWR_STATUS1_DBG*/ +#define REG_PMU_APB_PWR_STATUS2_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00C4)/*PWR_STATUS2_DBG*/ +#define REG_PMU_APB_PWR_STATUS3_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00C8)/*PWR_STATUS3_DBG*/ +#define REG_PMU_APB_SLEEP_CTRL SCI_ADDR(REGS_PMU_APB_BASE, 0x00CC)/*SLEEP_CTRL*/ +#define REG_PMU_APB_DDR_SLEEP_CTRL SCI_ADDR(REGS_PMU_APB_BASE, 0x00D0)/*DDR_SLEEP_CTRL*/ +#define REG_PMU_APB_SLEEP_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x00D4)/*SLEEP_STATUS*/ +#define REG_PMU_APB_PLL_DIV_AUTO_GATE_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x00D8)/*PLL_DIV_AUTO_GATE_EN*/ +#define REG_PMU_APB_PLL_DIV_EN1 SCI_ADDR(REGS_PMU_APB_BASE, 0x00DC)/*PLL_DIV_EN1*/ +#define REG_PMU_APB_PLL_DIV_EN2 SCI_ADDR(REGS_PMU_APB_BASE, 0x00E0)/*PLL_DIV_EN2*/ +#define REG_PMU_APB_CA7_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00E4)/*CA7_TOP_CFG*/ +#define REG_PMU_APB_CA7_C0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00E8)/*CA7_C0_CFG*/ +#define REG_PMU_APB_CA7_C1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00EC)/*CA7_C1_CFG*/ +#define REG_PMU_APB_CA7_C2_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00F0)/*CA7_C2_CFG*/ +#define REG_PMU_APB_CA7_C3_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00F4)/*CA7_C3_CFG*/ +#define REG_PMU_APB_DDR_CHN_SLEEP_CTRL0 SCI_ADDR(REGS_PMU_APB_BASE, 0x00F8)/*DDR_CHN_SLEEP_CTRL0*/ +#define REG_PMU_APB_DDR_CHN_SLEEP_CTRL1 SCI_ADDR(REGS_PMU_APB_BASE, 0x00FC)/*DDR_CHN_SLEEP_CTRL1*/ +#define REG_PMU_APB_BISR_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0100)/*BISR_CFG*/ +#define REG_PMU_APB_CGM_AP_AUTO_GATE_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0104)/*CGM_AP_AUTO_GATE_EN*/ +#define REG_PMU_APB_CGM_GPU_MM_AUTO_GATE_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0108)/*CGM_GPU_MM_AUTO_GATE_EN*/ +#define REG_PMU_APB_CGM_CP0_AUTO_GATE_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x010C)/*CGM_CP0_AUTO_GATE_EN*/ +#define REG_PMU_APB_CGM_CP1_AUTO_GATE_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0110)/*CGM_CP1_AUTO_GATE_EN*/ +#define REG_PMU_APB_CGM_CP2_AUTO_GATE_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0114)/*CGM_CP2_AUTO_GATE_EN*/ +#define REG_PMU_APB_CGM_AP_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0118)/*CGM_AP_EN*/ +#define REG_PMU_APB_CGM_GPU_MM_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x011C)/*CGM_GPU_MM_EN*/ +#define REG_PMU_APB_CGM_CP0_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0120)/*CGM_CP0_EN*/ +#define REG_PMU_APB_CGM_CP1_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0124)/*CGM_CP1_EN*/ +#define REG_PMU_APB_CGM_CP2_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0128)/*CGM_CP2_EN*/ +#define REG_PMU_APB_DDR_OP_MODE_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x012C)/*DDR_OP_MODE_CFG*/ +#define REG_PMU_APB_DDR_PHY_RET_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0130)/*DDR_PHY_RET_CFG*/ +#define REG_PMU_APB_26M_SEL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0134)/*26M_SEL_CFG*/ +#define REG_PMU_APB_MEM_PD_CFG0 SCI_ADDR(REGS_PMU_APB_BASE, 0x0138)/*MEM_PD_CFG0*/ +#define REG_PMU_APB_MEM_PD_CFG1 SCI_ADDR(REGS_PMU_APB_BASE, 0x013C)/*MEM_PD_CFG1*/ +#define REG_PMU_APB_PD_DDR_PUBL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0140)/*PD_DDR_PUBL_CFG*/ +#define REG_PMU_APB_PD_DDR_PHY_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0144)/*PD_DDR_PHY_CFG*/ +#define REG_PMU_APB_BISR_CFG2 SCI_ADDR(REGS_PMU_APB_BASE, 0x0148)/*BISR_CFG2*/ +#define REG_PMU_APB_CGM_CODEC_AUTO_GATE_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x014C)/*CGM_GPU_CODEC_AUTO_GATE_EN*/ +#define REG_PMU_APB_CGM_CODEC_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0150)/*CGM_GPU_CODEC_EN*/ +#define REG_PMU_APB_PD_CODEC_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0154)/*PD_CODEC_TOP_CFG*/ +#define REG_PMU_APB_PUB_SYS_PD_FLAG SCI_ADDR(REGS_PMU_APB_BASE, 0x0158)/*PUB_SYS_PD_FLAG*/ +#define REG_PMU_APB_DDR_PHY_PD_FLAG SCI_ADDR(REGS_PMU_APB_BASE, 0x015C)/*DDR_PHY_PD_FLAG*/ + + + +/* bits definitions for register REG_PMU_APB_PD_CA7_TOP_CFG */ +#define BIT_PD_CA7_TOP_DBG_SHUTDOWN_EN (BIT(28)) +#define BIT_PD_CA7_TOP_FORCE_SHUTDOWN (BIT(25)) +#define BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN (BIT(24)) +#define BITS_PD_CA7_TOP_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_PD_CA7_TOP_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7))) + +/* bits definitions for register REG_PMU_APB_PD_CA7_C0_CFG */ +#define BIT_PD_CA7_C0_DBG_SHUTDOWN_EN (BIT(28)) +#define BIT_PD_CA7_C0_FORCE_SHUTDOWN (BIT(25)) +#define BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN (BIT(24)) +#define BITS_PD_CA7_C0_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_PD_CA7_C0_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7))) + +/* bits definitions for register REG_PMU_APB_PD_CA7_C1_CFG */ +#define BIT_PD_CA7_C1_DBG_SHUTDOWN_EN (BIT(28)) +#define BIT_PD_CA7_C1_FORCE_SHUTDOWN (BIT(25)) +#define BIT_PD_CA7_C1_AUTO_SHUTDOWN_EN (BIT(24)) +#define BITS_PD_CA7_C1_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_PD_CA7_C1_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7))) + +/* bits definitions for register REG_PMU_APB_PD_CA7_C2_CFG */ +#define BIT_PD_CA7_C2_DBG_SHUTDOWN_EN (BIT(28)) +#define BIT_PD_CA7_C2_FORCE_SHUTDOWN (BIT(25)) +#define BIT_PD_CA7_C2_AUTO_SHUTDOWN_EN (BIT(24)) +#define BITS_PD_CA7_C2_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_PD_CA7_C2_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7))) + +/* bits definitions for register REG_PMU_APB_PD_CA7_C3_CFG */ +#define BIT_PD_CA7_C3_DBG_SHUTDOWN_EN (BIT(28)) +#define BIT_PD_CA7_C3_FORCE_SHUTDOWN (BIT(25)) +#define BIT_PD_CA7_C3_AUTO_SHUTDOWN_EN (BIT(24)) +#define BITS_PD_CA7_C3_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_PD_CA7_C3_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7))) + +/* bits definitions for register REG_PMU_APB_PD_AP_DISP_CFG */ + +/* bits definitions for register REG_PMU_APB_PD_AP_SYS_CFG */ +#define BIT_PD_AP_SYS_FORCE_SHUTDOWN (BIT(25)) +#define BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN (BIT(24)) +#define BITS_PD_AP_SYS_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_PD_AP_SYS_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7))) + +/* bits definitions for register REG_PMU_APB_PD_MM_TOP_CFG */ +#define BIT_PD_MM_TOP_FORCE_SHUTDOWN (BIT(25)) +#define BIT_PD_MM_TOP_AUTO_SHUTDOWN_EN (BIT(24)) +#define BITS_PD_MM_TOP_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_PD_MM_TOP_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7))) + +/* bits definitions for register REG_PMU_APB_PD_GPU_TOP_CFG */ +#define BIT_PD_GPU_TOP_FORCE_SHUTDOWN (BIT(25)) +#define BIT_PD_GPU_TOP_AUTO_SHUTDOWN_EN (BIT(24)) +#define BITS_PD_GPU_TOP_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_PD_GPU_TOP_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7))) + +/* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_0_CFG */ +#define BIT_PD_CP0_ARM9_0_FORCE_SHUTDOWN (BIT(25)) +#define BIT_PD_CP0_ARM9_0_AUTO_SHUTDOWN_EN (BIT(24)) +#define BITS_PD_CP0_ARM9_0_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_PD_CP0_ARM9_0_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_PD_CP0_ARM9_0_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7))) + +/* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_1_CFG */ +#define BIT_PD_CP0_ARM9_1_FORCE_SHUTDOWN (BIT(25)) +#define BIT_PD_CP0_ARM9_1_AUTO_SHUTDOWN_EN (BIT(24)) +#define BITS_PD_CP0_ARM9_1_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_PD_CP0_ARM9_1_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_PD_CP0_ARM9_1_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7))) + +/* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_2_CFG */ +#define BIT_PD_CP0_ARM9_2_FORCE_SHUTDOWN (BIT(25)) +#define BIT_PD_CP0_ARM9_2_AUTO_SHUTDOWN_EN (BIT(24)) +#define BITS_PD_CP0_ARM9_2_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_PD_CP0_ARM9_2_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_PD_CP0_ARM9_2_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7))) + +/* bits definitions for register REG_PMU_APB_PD_CP0_HU3GE_CFG */ +#define BIT_PD_CP0_HU3GE_FORCE_SHUTDOWN (BIT(25)) +#define BIT_PD_CP0_HU3GE_AUTO_SHUTDOWN_EN (BIT(24)) +#define BITS_PD_CP0_HU3GE_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_PD_CP0_HU3GE_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_PD_CP0_HU3GE_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7))) + +/* bits definitions for register REG_PMU_APB_PD_CP0_GSM_CFG */ +#define BIT_PD_CP0_GSM_FORCE_SHUTDOWN (BIT(25)) +#define BIT_PD_CP0_GSM_AUTO_SHUTDOWN_EN (BIT(24)) +#define BITS_PD_CP0_GSM_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_PD_CP0_GSM_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_PD_CP0_GSM_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7))) + +/* bits definitions for register REG_PMU_APB_PD_CP0_TD_CFG */ +#define BIT_PD_CP0_TD_FORCE_SHUTDOWN (BIT(25)) +#define BIT_PD_CP0_TD_AUTO_SHUTDOWN_EN (BIT(24)) +#define BITS_PD_CP0_TD_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_PD_CP0_TD_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_PD_CP0_TD_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7))) + +/* bits definitions for register REG_PMU_APB_PD_CP0_CEVA_CFG */ +#define BIT_PD_CP0_CEVA_FORCE_SHUTDOWN (BIT(25)) +#define BIT_PD_CP0_CEVA_AUTO_SHUTDOWN_EN (BIT(24)) +#define BITS_PD_CP0_CEVA_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_PD_CP0_CEVA_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_PD_CP0_CEVA_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7))) + +/* bits definitions for register REG_PMU_APB_PD_CP0_SYS_CFG */ +#define BIT_CP0_FORCE_DEEP_SLEEP (BIT(28)) +#define BIT_PD_CP0_SYS_FORCE_SHUTDOWN (BIT(25)) +#define BITS_PD_CP0_SYS_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_PD_CP0_SYS_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_PD_CP0_SYS_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7))) + +/* bits definitions for register REG_PMU_APB_PD_CP1_ARM9_CFG */ +#define BIT_PD_CP1_ARM9_FORCE_SHUTDOWN (BIT(25)) +#define BIT_PD_CP1_ARM9_AUTO_SHUTDOWN_EN (BIT(24)) +#define BITS_PD_CP1_ARM9_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_PD_CP1_ARM9_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_PD_CP1_ARM9_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7))) + +/* bits definitions for register REG_PMU_APB_PD_CP1_GSM_CFG */ +#define BIT_PD_CP1_GSM_FORCE_SHUTDOWN (BIT(25)) +#define BIT_PD_CP1_GSM_AUTO_SHUTDOWN_EN (BIT(24)) +#define BITS_PD_CP1_GSM_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_PD_CP1_GSM_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_PD_CP1_GSM_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7))) + +/* bits definitions for register REG_PMU_APB_PD_CP1_TD_CFG */ +#define BIT_PD_CP1_TD_FORCE_SHUTDOWN (BIT(25)) +#define BIT_PD_CP1_TD_AUTO_SHUTDOWN_EN (BIT(24)) +#define BITS_PD_CP1_TD_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_PD_CP1_TD_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_PD_CP1_TD_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7))) + +/* bits definitions for register REG_PMU_APB_PD_CP1_L1RAM_CFG */ +#define BIT_PD_CP1_L1RAM_FORCE_SHUTDOWN (BIT(25)) +#define BIT_PD_CP1_L1RAM_AUTO_SHUTDOWN_EN (BIT(24)) +#define BITS_PD_CP1_L1RAM_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_PD_CP1_L1RAM_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_PD_CP1_L1RAM_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7))) + +/* bits definitions for register REG_PMU_APB_PD_CP1_SYS_CFG */ +#define BIT_CP1_FORCE_DEEP_SLEEP (BIT(28)) +#define BIT_PD_CP1_SYS_FORCE_SHUTDOWN (BIT(25)) +#define BITS_PD_CP1_SYS_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_PD_CP1_SYS_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_PD_CP1_SYS_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7))) + +/* bits definitions for register REG_PMU_APB_PD_CP2_ARM9_CFG */ +#define BIT_PD_CP2_ARM9_FORCE_SHUTDOWN (BIT(25)) +#define BIT_PD_CP2_ARM9_AUTO_SHUTDOWN_EN (BIT(24)) +#define BITS_PD_CP2_ARM9_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_PD_CP2_ARM9_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_PD_CP2_ARM9_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7))) + +/* bits definitions for register REG_PMU_APB_PD_CP2_WIFI_CFG */ +#define BIT_PD_CP2_WIFI_FORCE_SHUTDOWN (BIT(25)) +#define BIT_PD_CP2_WIFI_AUTO_SHUTDOWN_EN (BIT(24)) +#define BITS_PD_CP2_WIFI_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_PD_CP2_WIFI_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_PD_CP2_WIFI_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7))) + +/* bits definitions for register REG_PMU_APB_AP_WAKEUP_POR_CFG */ +#define BIT_AP_WAKEUP_POR_N (BIT(0)) + +/* bits definitions for register REG_PMU_APB_PD_CP2_SYS_CFG */ +#define BIT_CP2_FORCE_DEEP_SLEEP (BIT(28)) +#define BIT_PD_CP2_SYS_FORCE_SHUTDOWN (BIT(25)) +#define BITS_PD_CP2_SYS_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_PD_CP2_SYS_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_PD_CP2_SYS_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7))) + +/* bits definitions for register REG_PMU_APB_PD_PUB_SYS_CFG */ +#define BIT_PD_PUB_SYS_FORCE_SHUTDOWN (BIT(25)) +#define BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN (BIT(24)) +#define BITS_PD_PUB_SYS_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_PD_PUB_SYS_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7))) + +/* bits definitions for register REG_PMU_APB_XTL_WAIT_CNT */ +#define BITS_XTL1_WAIT_CNT(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_XTL0_WAIT_CNT(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7))) + +/* bits definitions for register REG_PMU_APB_XTLBUF_WAIT_CNT */ +#define BITS_XTLBUF1_WAIT_CNT(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_XTLBUF0_WAIT_CNT(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7))) + +/* bits definitions for register REG_PMU_APB_PLL_WAIT_CNT1 */ +#define BITS_WPLL_WAIT_CNT(_X_) ((_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31))) +#define BITS_TDPLL_WAIT_CNT(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_DPLL_WAIT_CNT(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_MPLL_WAIT_CNT(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7))) + +/* bits definitions for register REG_PMU_APB_PLL_WAIT_CNT2 */ +#define BITS_WIFIPLL2_WAIT_CNT(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_WIFIPLL1_WAIT_CNT(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_CPLL_WAIT_CNT(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7))) + +/* bits definitions for register REG_PMU_APB_XTL0_REL_CFG */ +#define BIT_XTL0_CP2_SEL (BIT(3)) +#define BIT_XTL0_CP1_SEL (BIT(2)) +#define BIT_XTL0_CP0_SEL (BIT(1)) +#define BIT_XTL0_AP_SEL (BIT(0)) + +/* bits definitions for register REG_PMU_APB_XTL1_REL_CFG */ +#define BIT_XTL1_CP2_SEL (BIT(3)) +#define BIT_XTL1_CP1_SEL (BIT(2)) +#define BIT_XTL1_CP0_SEL (BIT(1)) +#define BIT_XTL1_AP_SEL (BIT(0)) + +/* bits definitions for register REG_PMU_APB_XTL2_REL_CFG */ +#define BIT_XTL2_CP2_SEL (BIT(3)) +#define BIT_XTL2_CP1_SEL (BIT(2)) +#define BIT_XTL2_CP0_SEL (BIT(1)) +#define BIT_XTL2_AP_SEL (BIT(0)) + +/* bits definitions for register REG_PMU_APB_XTLBUF0_REL_CFG */ +#define BIT_XTLBUF0_CP2_SEL (BIT(3)) +#define BIT_XTLBUF0_CP1_SEL (BIT(2)) +#define BIT_XTLBUF0_CP0_SEL (BIT(1)) +#define BIT_XTLBUF0_AP_SEL (BIT(0)) + +/* bits definitions for register REG_PMU_APB_XTLBUF1_REL_CFG */ +#define BIT_XTLBUF1_CP2_SEL (BIT(3)) +#define BIT_XTLBUF1_CP1_SEL (BIT(2)) +#define BIT_XTLBUF1_CP0_SEL (BIT(1)) +#define BIT_XTLBUF1_AP_SEL (BIT(0)) + +/* bits definitions for register REG_PMU_APB_MPLL_REL_CFG */ +#define BIT_MPLL_REF_SEL (BIT(4)) +#define BIT_MPLL_CP2_SEL (BIT(3)) +#define BIT_MPLL_CP1_SEL (BIT(2)) +#define BIT_MPLL_CP0_SEL (BIT(1)) +#define BIT_MPLL_AP_SEL (BIT(0)) + +/* bits definitions for register REG_PMU_APB_DPLL_REL_CFG */ +#define BIT_DPLL_REF_SEL (BIT(4)) +#define BIT_DPLL_CP2_SEL (BIT(3)) +#define BIT_DPLL_CP1_SEL (BIT(2)) +#define BIT_DPLL_CP0_SEL (BIT(1)) +#define BIT_DPLL_AP_SEL (BIT(0)) + +/* bits definitions for register REG_PMU_APB_TDPLL_REL_CFG */ +#define BIT_TDPLL_REF_SEL (BIT(4)) +#define BIT_TDPLL_CP2_SEL (BIT(3)) +#define BIT_TDPLL_CP1_SEL (BIT(2)) +#define BIT_TDPLL_CP0_SEL (BIT(1)) +#define BIT_TDPLL_AP_SEL (BIT(0)) + +/* bits definitions for register REG_PMU_APB_WPLL_REL_CFG */ +#define BIT_WPLL_REF_SEL (BIT(4)) +#define BIT_WPLL_CP2_SEL (BIT(3)) +#define BIT_WPLL_CP1_SEL (BIT(2)) +#define BIT_WPLL_CP0_SEL (BIT(1)) +#define BIT_WPLL_AP_SEL (BIT(0)) + +/* bits definitions for register REG_PMU_APB_CPLL_REL_CFG */ +#define BIT_CPLL_REF_SEL (BIT(4)) +#define BIT_CPLL_CP2_SEL (BIT(3)) +#define BIT_CPLL_CP1_SEL (BIT(2)) +#define BIT_CPLL_CP0_SEL (BIT(1)) +#define BIT_CPLL_AP_SEL (BIT(0)) + +/* bits definitions for register REG_PMU_APB_WIFIPLL1_REL_CFG */ +#define BIT_WIFIPLL1_REF_SEL (BIT(4)) +#define BIT_WIFIPLL1_CP2_SEL (BIT(3)) +#define BIT_WIFIPLL1_CP1_SEL (BIT(2)) +#define BIT_WIFIPLL1_CP0_SEL (BIT(1)) +#define BIT_WIFIPLL1_AP_SEL (BIT(0)) + +/* bits definitions for register REG_PMU_APB_WIFIPLL2_REL_CFG */ +#define BIT_WIFIPLL2_REF_SEL (BIT(4)) +#define BIT_WIFIPLL2_CP2_SEL (BIT(3)) +#define BIT_WIFIPLL2_CP1_SEL (BIT(2)) +#define BIT_WIFIPLL2_CP0_SEL (BIT(1)) +#define BIT_WIFIPLL2_AP_SEL (BIT(0)) + +/* bits definitions for register REG_PMU_APB_CP_SOFT_RST */ +#define BIT_CODEC_SOFT_RST (BIT(7)) +#define BIT_PUB_SOFT_RST (BIT(6)) +#define BIT_AP_SOFT_RST (BIT(5)) +#define BIT_GPU_SOFT_RST (BIT(4)) +#define BIT_MM_SOFT_RST (BIT(3)) +#define BIT_CP2_SOFT_RST (BIT(2)) +#define BIT_CP1_SOFT_RST (BIT(1)) +#define BIT_CP0_SOFT_RST (BIT(0)) + +/* bits definitions for register REG_PMU_APB_CP_SLP_STATUS_DBG0 */ +#define BITS_CP1_DEEP_SLP_DBG(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31))) +#define BITS_CP0_DEEP_SLP_DBG(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15))) + +/* bits definitions for register REG_PMU_APB_CP_SLP_STATUS_DBG1 */ +#define BITS_CP2_DEEP_SLP_DBG(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15))) + +/* bits definitions for register REG_PMU_APB_PWR_STATUS0_DBG */ +#define BITS_PD_MM_TOP_STATE(_X_) ((_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31))) +#define BITS_PD_GPU_TOP_STATE(_X_) ((_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27))) +#define BITS_PD_CODEC_TOP_STATE(_X_) ((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_PD_CA7_C3_STATE(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19))) +#define BITS_PD_CA7_C2_STATE(_X_) ((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_PD_CA7_C1_STATE(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11))) +#define BITS_PD_CA7_C0_STATE(_X_) ((_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7))) +#define BITS_PD_CA7_TOP_STATE(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3))) + +/* bits definitions for register REG_PMU_APB_PWR_STATUS1_DBG */ +#define BITS_PD_CP0_SYS_STATE(_X_) ((_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31))) +#define BITS_PD_CP0_GSM_STATE(_X_) ((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_PD_CP0_HU3GE_STATE(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19))) +#define BITS_PD_CP0_ARM9_2_STATE(_X_) ((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_PD_CP0_ARM9_1_STATE(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11))) +#define BITS_PD_CP0_ARM9_0_STATE(_X_) ((_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7))) +#define BITS_PD_AP_SYS_STATE(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3))) + +/* bits definitions for register REG_PMU_APB_PWR_STATUS2_DBG */ +#define BITS_PD_CP2_WIFI_STATE(_X_) ((_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27))) +#define BITS_PD_CP2_ARM9_STATE(_X_) ((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_PD_CP1_SYS_STATE(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19))) +#define BITS_PD_CP1_L1RAM_STATE(_X_) ((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_PD_CP1_TD_STATE(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11))) +#define BITS_PD_CP1_GSM_STATE(_X_) ((_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7))) +#define BITS_PD_CP1_ARM9_STATE(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3))) + +/* bits definitions for register REG_PMU_APB_PWR_STATUS3_DBG */ +#define BITS_PD_CP0_CEVA_STATE(_X_) ((_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_PD_CP0_TD_STATE(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19))) +#define BITS_PD_DDR_PHY_STATE(_X_) ((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_PD_DDR_PUBL_STATE(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11))) +#define BITS_PD_PUB_SYS_STATE(_X_) ((_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7))) +#define BITS_PD_CP2_SYS_STATE(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3))) + +/* bits definitions for register REG_PMU_APB_SLEEP_CTRL */ +#define BIT_CP0_FORCE_SLEEP (BIT(12)) +#define BIT_CP2_SLEEP_XTL_ON (BIT(11)) +#define BIT_CP1_SLEEP_XTL_ON (BIT(10)) +#define BIT_CP0_SLEEP_XTL_ON (BIT(9)) +#define BIT_AP_SLEEP_XTL_ON (BIT(8)) +#define BIT_DISP_DEEP_SLEEP (BIT(6)) +#define BIT_GPU_DEEP_SLEEP (BIT(5)) +#define BIT_MM_DEEP_SLEEP (BIT(4)) +#define BIT_CP2_DEEP_SLEEP (BIT(3)) +#define BIT_CP1_DEEP_SLEEP (BIT(2)) +#define BIT_CP0_DEEP_SLEEP (BIT(1)) +#define BIT_AP_DEEP_SLEEP (BIT(0)) + +/* bits definitions for register REG_PMU_APB_DDR_SLEEP_CTRL */ +#define BIT_DDR_PUBL_APB_SOFT_RST (BIT(12)) +#define BIT_DDR_UMCTL_APB_SOFT_RST (BIT(11)) +#define BIT_DDR_PUBL_SOFT_RST (BIT(10)) +#define BIT_DDR_PHY_SOFT_RST (BIT(8)) +#define BIT_DDR_PHY_AUTO_GATE_EN (BIT(6)) +#define BIT_DDR_PUBL_AUTO_GATE_EN (BIT(5)) +#define BIT_DDR_UMCTL_AUTO_GATE_EN (BIT(4)) +#define BIT_DDR_PHY_EB (BIT(2)) +#define BIT_DDR_UMCTL_EB (BIT(1)) +#define BIT_DDR_PUBL_EB (BIT(0)) + +/* bits definitions for register REG_PMU_APB_SLEEP_STATUS */ +#define BITS_CP2_SLP_STATUS(_X_) ((_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_CP1_SLP_STATUS(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11))) +#define BITS_CP0_SLP_STATUS(_X_) ((_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7))) +#define BITS_AP_SLP_STATUS(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3))) + +/* bits definitions for register REG_PMU_APB_PLL_DIV_AUTO_GATE_EN */ +#define BIT_WIFIPLL2_DIV_AUTO_GATE_EN (BIT(6)) +#define BIT_WIFIPLL1_DIV_AUTO_GATE_EN (BIT(5)) +#define BIT_WPLL_DIV_AUTO_GATE_EN (BIT(4)) +#define BIT_TDPLL_DIV_AUTO_GATE_EN (BIT(3)) +#define BIT_CPLL_DIV_AUTO_GATE_EN (BIT(2)) +#define BIT_DPLL_DIV_AUTO_GATE_EN (BIT(1)) +#define BIT_MPLL_DIV_AUTO_GATE_EN (BIT(0)) + +/* bits definitions for register REG_PMU_APB_PLL_DIV_EN1 */ +#define BIT_WIFIPLL2_80M_EN (BIT(31)) +#define BIT_WIFIPLL2_160M_EN (BIT(30)) +#define BIT_WIFIPLL2_120M_EN (BIT(29)) +#define BIT_WIFIPLL1_20M_EN (BIT(28)) +#define BIT_WIFIPLL1_40M_EN (BIT(27)) +#define BIT_WIFIPLL1_80M_EN (BIT(26)) +#define BIT_WIFIPLL1_44M_EN (BIT(25)) +#define BIT_WPLL_76M8_EN (BIT(24)) +#define BIT_WPLL_51M2_EN (BIT(23)) +#define BIT_WPLL_102M4_EN (BIT(22)) +#define BIT_WPLL_307M2_EN (BIT(21)) +#define BIT_WPLL_460M8_EN (BIT(20)) +#define BIT_CPLL_52M_EN (BIT(19)) +#define BIT_CPLL_104M_EN (BIT(18)) +#define BIT_CPLL_208M_EN (BIT(17)) +#define BIT_CPLL_312M_EN (BIT(16)) +#define BIT_TDPLL_38M4_EN (BIT(15)) +#define BIT_TDPLL_76M8_EN (BIT(14)) +#define BIT_TDPLL_51M2_EN (BIT(13)) +#define BIT_TDPLL_153M6_EN (BIT(12)) +#define BIT_TDPLL_64M_EN (BIT(11)) +#define BIT_TDPLL_128M_EN (BIT(10)) +#define BIT_TDPLL_256M_EN (BIT(9)) +#define BIT_TDPLL_12M_EN (BIT(8)) +#define BIT_TDPLL_24M_EN (BIT(7)) +#define BIT_TDPLL_48M_EN (BIT(6)) +#define BIT_TDPLL_96M_EN (BIT(5)) +#define BIT_TDPLL_192M_EN (BIT(4)) +#define BIT_TDPLL_384M_EN (BIT(3)) +#define BIT_DPLL_44M_EN (BIT(2)) +#define BIT_MPLL_37M5_EN (BIT(1)) +#define BIT_MPLL_300M_EN (BIT(0)) + +/* bits definitions for register REG_PMU_APB_PLL_DIV_EN2 */ +#define BITS_MPLL_300M_DIV(_X_) ((_X_) << 3 & (BIT(3)|BIT(4))) +#define BIT_DPLL_533M_EN (BIT(2)) +#define BIT_WIFIPLL2_20M_EN (BIT(1)) +#define BIT_WIFIPLL2_40M_EN (BIT(0)) + +/* bits definitions for register REG_PMU_APB_CA7_TOP_CFG */ +#define BIT_CA7_L2RSTDISABLE (BIT(0)) + +/* bits definitions for register REG_PMU_APB_CA7_C0_CFG */ +#define BIT_CA7_VINITHI_C0 (BIT(0)) + +/* bits definitions for register REG_PMU_APB_CA7_C1_CFG */ +#define BIT_CA7_VINITHI_C1 (BIT(0)) + +/* bits definitions for register REG_PMU_APB_CA7_C2_CFG */ +#define BIT_CA7_VINITHI_C2 (BIT(0)) + +/* bits definitions for register REG_PMU_APB_CA7_C3_CFG */ +#define BIT_CA7_VINITHI_C3 (BIT(0)) + +/* bits definitions for register REG_PMU_APB_DDR_CHN_SLEEP_CTRL0 */ +#define BIT_DDR_CTRL_AXI_LP_EN (BIT(31)) +#define BIT_DDR_CTRL_CGM_SEL (BIT(30)) +#define BIT_DDR_CHN9_AXI_LP_EN (BIT(25)) +#define BIT_DDR_CHN8_AXI_LP_EN (BIT(24)) +#define BIT_DDR_CHN7_AXI_LP_EN (BIT(23)) +#define BIT_DDR_CHN6_AXI_LP_EN (BIT(22)) +#define BIT_DDR_CHN5_AXI_LP_EN (BIT(21)) +#define BIT_DDR_CHN4_AXI_LP_EN (BIT(20)) +#define BIT_DDR_CHN3_AXI_LP_EN (BIT(19)) +#define BIT_DDR_CHN2_AXI_LP_EN (BIT(18)) +#define BIT_DDR_CHN1_AXI_LP_EN (BIT(17)) +#define BIT_DDR_CHN0_AXI_LP_EN (BIT(16)) +#define BIT_DDR_CHN9_CGM_SEL (BIT(9)) +#define BIT_DDR_CHN8_CGM_SEL (BIT(8)) +#define BIT_DDR_CHN7_CGM_SEL (BIT(7)) +#define BIT_DDR_CHN6_CGM_SEL (BIT(6)) +#define BIT_DDR_CHN5_CGM_SEL (BIT(5)) +#define BIT_DDR_CHN4_CGM_SEL (BIT(4)) +#define BIT_DDR_CHN3_CGM_SEL (BIT(3)) +#define BIT_DDR_CHN2_CGM_SEL (BIT(2)) +#define BIT_DDR_CHN1_CGM_SEL (BIT(1)) +#define BIT_DDR_CHN0_CGM_SEL (BIT(0)) + +/* bits definitions for register REG_PMU_APB_DDR_CHN_SLEEP_CTRL1 */ +#define BIT_DDR_CHN9_AXI_STOP_SEL (BIT(9)) +#define BIT_DDR_CHN8_AXI_STOP_SEL (BIT(8)) +#define BIT_DDR_CHN7_AXI_STOP_SEL (BIT(7)) +#define BIT_DDR_CHN6_AXI_STOP_SEL (BIT(6)) +#define BIT_DDR_CHN5_AXI_STOP_SEL (BIT(5)) +#define BIT_DDR_CHN4_AXI_STOP_SEL (BIT(4)) +#define BIT_DDR_CHN3_AXI_STOP_SEL (BIT(3)) +#define BIT_DDR_CHN2_AXI_STOP_SEL (BIT(2)) +#define BIT_DDR_CHN1_AXI_STOP_SEL (BIT(1)) +#define BIT_DDR_CHN0_AXI_STOP_SEL (BIT(0)) + +/* bits definitions for register REG_PMU_APB_BISR_CFG */ +#define BIT_PD_CP0_CEVA_BISR_DONE (BIT(31)) +#define BIT_PD_CP0_TD_BISR_DONE (BIT(30)) +#define BIT_PD_CP1_TD_BISR_DONE (BIT(29)) +#define BIT_PD_CP1_SYS_BISR_DONE (BIT(28)) +#define BIT_PD_CP0_HU3GE_BISR_DONE (BIT(27)) +#define BIT_PD_CP0_SYS_BISR_DONE (BIT(26)) +#define BIT_PD_MM_TOP_BISR_DONE (BIT(25)) +#define BIT_PD_GPU_TOP_BISR_DONE (BIT(24)) +#define BIT_PD_CP0_CEVA_BISR_BUSY (BIT(23)) +#define BIT_PD_CP0_TD_BISR_BUSY (BIT(22)) +#define BIT_PD_CP1_TD_BISR_BUSY (BIT(21)) +#define BIT_PD_CP1_SYS_BISR_BUSY (BIT(20)) +#define BIT_PD_CP0_HU3GE_BISR_BUSY (BIT(19)) +#define BIT_PD_CP0_SYS_BISR_BUSY (BIT(18)) +#define BIT_PD_MM_TOP_BISR_BUSY (BIT(17)) +#define BIT_PD_GPU_TOP_BISR_BUSY (BIT(16)) +#define BIT_PD_CP0_CEVA_BISR_FORCE_EN (BIT(15)) +#define BIT_PD_CP0_TD_BISR_FORCE_EN (BIT(14)) +#define BIT_PD_CP1_TD_BISR_FORCE_EN (BIT(13)) +#define BIT_PD_CP1_SYS_BISR_FORCE_EN (BIT(12)) +#define BIT_PD_CP0_HU3GE_BISR_FORCE_EN (BIT(11)) +#define BIT_PD_CP0_SYS_BISR_FORCE_EN (BIT(10)) +#define BIT_PD_MM_TOP_BISR_FORCE_EN (BIT(9)) +#define BIT_PD_GPU_TOP_BISR_FORCE_EN (BIT(8)) +#define BIT_PD_CP1_TD_BISR_FORCE_BYP (BIT(7)) +#define BIT_PD_CP0_CEVA_BISR_FORCE_BYP (BIT(6)) +#define BIT_PD_CP0_TD_BISR_FORCE_BYP (BIT(5)) +#define BIT_PD_CP1_SYS_BISR_FORCE_BYP (BIT(4)) +#define BIT_PD_CP0_HU3GE_BISR_FORCE_BYP (BIT(3)) +#define BIT_PD_CP0_SYS_BISR_FORCE_BYP (BIT(2)) +#define BIT_PD_MM_TOP_BISR_FORCE_BYP (BIT(1)) +#define BIT_PD_GPU_TOP_BISR_FORCE_BYP (BIT(0)) + +/* bits definitions for register REG_PMU_APB_CGM_AP_AUTO_GATE_EN */ +#define BIT_CGM_208M_AP_AUTO_GATE_EN (BIT(20)) +#define BIT_CGM_12M_AP_AUTO_GATE_EN (BIT(19)) +#define BIT_CGM_24M_AP_AUTO_GATE_EN (BIT(18)) +#define BIT_CGM_48M_AP_AUTO_GATE_EN (BIT(17)) +#define BIT_CGM_51M2_AP_AUTO_GATE_EN (BIT(16)) +#define BIT_CGM_64M_AP_AUTO_GATE_EN (BIT(15)) +#define BIT_CGM_76M8_AP_AUTO_GATE_EN (BIT(14)) +#define BIT_CGM_96M_AP_AUTO_GATE_EN (BIT(13)) +#define BIT_CGM_128M_AP_AUTO_GATE_EN (BIT(12)) +#define BIT_CGM_153M6_AP_AUTO_GATE_EN (BIT(11)) +#define BIT_CGM_192M_AP_AUTO_GATE_EN (BIT(10)) +#define BIT_CGM_256M_AP_AUTO_GATE_EN (BIT(9)) +#define BIT_CGM_384M_AP_AUTO_GATE_EN (BIT(8)) +#define BIT_CGM_312M_AP_AUTO_GATE_EN (BIT(7)) +#define BIT_CGM_MPLL_AP_AUTO_GATE_EN (BIT(6)) +#define BIT_CGM_WPLL_AP_AUTO_GATE_EN (BIT(5)) +#define BIT_CGM_WIFIPLL1_AP_AUTO_GATE_EN (BIT(4)) +#define BIT_CGM_TDPLL_AP_AUTO_GATE_EN (BIT(3)) +#define BIT_CGM_CPLL_AP_AUTO_GATE_EN (BIT(2)) +#define BIT_CGM_DPLL_AP_AUTO_GATE_EN (BIT(1)) +#define BIT_CGM_26M_AP_AUTO_GATE_EN (BIT(0)) + +/* bits definitions for register REG_PMU_APB_CGM_GPU_MM_AUTO_GATE_EN */ +#define BIT_CGM_312M_MM_AUTO_GATE_EN (BIT(27)) +#define BIT_CGM_12M_MM_AUTO_GATE_EN (BIT(26)) +#define BIT_CGM_24M_MM_AUTO_GATE_EN (BIT(25)) +#define BIT_CGM_48M_MM_AUTO_GATE_EN (BIT(24)) +#define BIT_CGM_64M_MM_AUTO_GATE_EN (BIT(23)) +#define BIT_CGM_76M8_MM_AUTO_GATE_EN (BIT(22)) +#define BIT_CGM_96M_MM_AUTO_GATE_EN (BIT(21)) +#define BIT_CGM_128M_MM_AUTO_GATE_EN (BIT(20)) +#define BIT_CGM_153M6_MM_AUTO_GATE_EN (BIT(19)) +#define BIT_CGM_192M_MM_AUTO_GATE_EN (BIT(18)) +#define BIT_CGM_256M_MM_AUTO_GATE_EN (BIT(17)) +#define BIT_CGM_26M_MM_AUTO_GATE_EN (BIT(16)) +#define BIT_CGM_153_6M_GPU_AUTO_GATE_EN (BIT(6)) +#define BIT_CGM_384M_GPU_AUTO_GATE_EN (BIT(5)) +#define BIT_CGM_460_8M_GPU_AUTO_GATE_EN (BIT(4)) +#define BIT_CGM_256M_GPU_AUTO_GATE_EN (BIT(3)) +#define BIT_CGM_208M_GPU_AUTO_GATE_EN (BIT(2)) +#define BIT_CGM_312M_GPU_AUTO_GATE_EN (BIT(1)) +#define BIT_CGM_300M_GPU_AUTO_GATE_EN (BIT(0)) + +/* bits definitions for register REG_PMU_APB_CGM_CP0_AUTO_GATE_EN */ +#define BIT_CGM_312M_CP0_AUTO_GATE_EN (BIT(16)) +#define BIT_CGM_208M_CP0_AUTO_GATE_EN (BIT(15)) +#define BIT_CGM_256M_CP0_AUTO_GATE_EN (BIT(14)) +#define BIT_CGM_460M8_CP0W_AUTO_GATE_EN (BIT(13)) +#define BIT_CGM_307M2_CP0W_AUTO_GATE_EN (BIT(12)) +#define BIT_CGM_51M2_CP0W_AUTO_GATE_EN (BIT(11)) +#define BIT_CGM_76M8_CP0W_AUTO_GATE_EN (BIT(10)) +#define BIT_CGM_102M4_CP0W_AUTO_GATE_EN (BIT(9)) +#define BIT_CGM_192M_CP0_AUTO_GATE_EN (BIT(8)) +#define BIT_CGM_51M2_CP0_AUTO_GATE_EN (BIT(7)) +#define BIT_CGM_76M8_CP0_AUTO_GATE_EN (BIT(6)) +#define BIT_CGM_153M6_CP0_AUTO_GATE_EN (BIT(5)) +#define BIT_CGM_48M_CP0_AUTO_GATE_EN (BIT(4)) +#define BIT_CGM_64M_CP0_AUTO_GATE_EN (BIT(3)) +#define BIT_CGM_96M_CP0_AUTO_GATE_EN (BIT(2)) +#define BIT_CGM_128M_CP0_AUTO_GATE_EN (BIT(1)) +#define BIT_CGM_26M_CP0_AUTO_GATE_EN (BIT(0)) + +/* bits definitions for register REG_PMU_APB_CGM_CP1_AUTO_GATE_EN */ +#define BIT_CGM_312M_CP1_AUTO_GATE_EN (BIT(10)) +#define BIT_CGM_256M_CP1_AUTO_GATE_EN (BIT(9)) +#define BIT_CGM_192M_CP1_AUTO_GATE_EN (BIT(8)) +#define BIT_CGM_51M2_CP1_AUTO_GATE_EN (BIT(7)) +#define BIT_CGM_76M8_CP1_AUTO_GATE_EN (BIT(6)) +#define BIT_CGM_153M6_CP1_AUTO_GATE_EN (BIT(5)) +#define BIT_CGM_48M_CP1_AUTO_GATE_EN (BIT(4)) +#define BIT_CGM_96M_CP1_AUTO_GATE_EN (BIT(3)) +#define BIT_CGM_64M_CP1_AUTO_GATE_EN (BIT(2)) +#define BIT_CGM_128M_CP1_AUTO_GATE_EN (BIT(1)) +#define BIT_CGM_26M_CP1_AUTO_GATE_EN (BIT(0)) + +/* bits definitions for register REG_PMU_APB_CGM_CP2_AUTO_GATE_EN */ +#define BIT_CGM_153M6_CP2_AUTO_GATE_EN (BIT(12)) +#define BIT_CGM_20M_CP2WF2_AUTO_GATE_EN (BIT(11)) +#define BIT_CGM_80M_CP2WF2_AUTO_GATE_EN (BIT(10)) +#define BIT_CGM_120M_CP2WF2_AUTO_GATE_EN (BIT(9)) +#define BIT_CGM_160M_CP2WF2_AUTO_GATE_EN (BIT(8)) +#define BIT_CGM_20M_CP2WF1_AUTO_GATE_EN (BIT(7)) +#define BIT_CGM_44M_CP2WF1_AUTO_GATE_EN (BIT(6)) +#define BIT_CGM_80M_CP2WF1_AUTO_GATE_EN (BIT(5)) +#define BIT_CGM_256M_CP2_AUTO_GATE_EN (BIT(4)) +#define BIT_CGM_104M_CP2_AUTO_GATE_EN (BIT(3)) +#define BIT_CGM_208M_CP2_AUTO_GATE_EN (BIT(2)) +#define BIT_CGM_312M_CP2_AUTO_GATE_EN (BIT(1)) +#define BIT_CGM_26M_CP2_AUTO_GATE_EN (BIT(0)) + +/* bits definitions for register REG_PMU_APB_CGM_AP_EN */ +#define BIT_CGM_208M_AP_EN (BIT(20)) +#define BIT_CGM_12M_AP_EN (BIT(19)) +#define BIT_CGM_24M_AP_EN (BIT(18)) +#define BIT_CGM_48M_AP_EN (BIT(17)) +#define BIT_CGM_51M2_AP_EN (BIT(16)) +#define BIT_CGM_64M_AP_EN (BIT(15)) +#define BIT_CGM_76M8_AP_EN (BIT(14)) +#define BIT_CGM_96M_AP_EN (BIT(13)) +#define BIT_CGM_128M_AP_EN (BIT(12)) +#define BIT_CGM_153M6_AP_EN (BIT(11)) +#define BIT_CGM_192M_AP_EN (BIT(10)) +#define BIT_CGM_256M_AP_EN (BIT(9)) +#define BIT_CGM_384M_AP_EN (BIT(8)) +#define BIT_CGM_312M_AP_EN (BIT(7)) +#define BIT_CGM_MPLL_AP_EN (BIT(6)) +#define BIT_CGM_WPLL_AP_EN (BIT(5)) +#define BIT_CGM_WIFIPLL1_AP_EN (BIT(4)) +#define BIT_CGM_TDPLL_AP_EN (BIT(3)) +#define BIT_CGM_CPLL_AP_EN (BIT(2)) +#define BIT_CGM_DPLL_AP_EN (BIT(1)) +#define BIT_CGM_26M_AP_EN (BIT(0)) + +/* bits definitions for register REG_PMU_APB_CGM_GPU_MM_EN */ +#define BIT_CGM_312M_MM_EN (BIT(27)) +#define BIT_CGM_12M_MM_EN (BIT(26)) +#define BIT_CGM_24M_MM_EN (BIT(25)) +#define BIT_CGM_48M_MM_EN (BIT(24)) +#define BIT_CGM_64M_MM_EN (BIT(23)) +#define BIT_CGM_76M8_MM_EN (BIT(22)) +#define BIT_CGM_96M_MM_EN (BIT(21)) +#define BIT_CGM_128M_MM_EN (BIT(20)) +#define BIT_CGM_153M6_MM_EN (BIT(19)) +#define BIT_CGM_192M_MM_EN (BIT(18)) +#define BIT_CGM_256M_MM_EN (BIT(17)) +#define BIT_CGM_26M_MM_EN (BIT(16)) +#define BIT_CGM_153_6M_GPU_EN (BIT(6)) +#define BIT_CGM_384M_GPU_EN (BIT(5)) +#define BIT_CGM_460_8M_GPU_EN (BIT(4)) +#define BIT_CGM_256M_GPU_EN (BIT(3)) +#define BIT_CGM_208M_GPU_EN (BIT(2)) +#define BIT_CGM_312M_GPU_EN (BIT(1)) +#define BIT_CGM_300M_GPU_EN (BIT(0)) + +/* bits definitions for register REG_PMU_APB_CGM_CP0_EN */ +#define BIT_CGM_312M_CP0_EN (BIT(16)) +#define BIT_CGM_208M_CP0_EN (BIT(15)) +#define BIT_CGM_256M_CP0_EN (BIT(14)) +#define BIT_CGM_460M8_CP0W_EN (BIT(13)) +#define BIT_CGM_307M2_CP0W_EN (BIT(12)) +#define BIT_CGM_51M2_CP0W_EN (BIT(11)) +#define BIT_CGM_76M8_CP0W_EN (BIT(10)) +#define BIT_CGM_102M4_CP0W_EN (BIT(9)) +#define BIT_CGM_192M_CP0_EN (BIT(8)) +#define BIT_CGM_51M2_CP0_EN (BIT(7)) +#define BIT_CGM_76M8_CP0_EN (BIT(6)) +#define BIT_CGM_153M6_CP0_EN (BIT(5)) +#define BIT_CGM_48M_CP0_EN (BIT(4)) +#define BIT_CGM_64M_CP0_EN (BIT(3)) +#define BIT_CGM_96M_CP0_EN (BIT(2)) +#define BIT_CGM_128M_CP0_EN (BIT(1)) +#define BIT_CGM_26M_CP0_EN (BIT(0)) + +/* bits definitions for register REG_PMU_APB_CGM_CP1_EN */ +#define BIT_CGM_312M_CP1_EN (BIT(10)) +#define BIT_CGM_256M_CP1_EN (BIT(9)) +#define BIT_CGM_192M_CP1_EN (BIT(8)) +#define BIT_CGM_51M2_CP1_EN (BIT(7)) +#define BIT_CGM_76M8_CP1_EN (BIT(6)) +#define BIT_CGM_153M6_CP1_EN (BIT(5)) +#define BIT_CGM_48M_CP1_EN (BIT(4)) +#define BIT_CGM_96M_CP1_EN (BIT(3)) +#define BIT_CGM_64M_CP1_EN (BIT(2)) +#define BIT_CGM_128M_CP1_EN (BIT(1)) +#define BIT_CGM_26M_CP1_EN (BIT(0)) + +/* bits definitions for register REG_PMU_APB_CGM_CP2_EN */ +#define BIT_CGM_153M6_CP2_EN (BIT(12)) +#define BIT_CGM_20M_CP2WF2_EN (BIT(11)) +#define BIT_CGM_80M_CP2WF2_EN (BIT(10)) +#define BIT_CGM_120M_CP2WF2_EN (BIT(9)) +#define BIT_CGM_160M_CP2WF2_EN (BIT(8)) +#define BIT_CGM_20M_CP2WF1_EN (BIT(7)) +#define BIT_CGM_44M_CP2WF1_EN (BIT(6)) +#define BIT_CGM_80M_CP2WF1_EN (BIT(5)) +#define BIT_CGM_256M_CP2_EN (BIT(4)) +#define BIT_CGM_104M_CP2_EN (BIT(3)) +#define BIT_CGM_208M_CP2_EN (BIT(2)) +#define BIT_CGM_312M_CP2_EN (BIT(1)) +#define BIT_CGM_26M_CP2_EN (BIT(0)) + +/* bits definitions for register REG_PMU_APB_DDR_OP_MODE_CFG */ +#define BIT_DDR_PHY_RET_EN (BIT(28)) +#define BIT_DDR_PUBL_RET_EN (BIT(27)) +#define BIT_DDR_PHY_ISO_RST_EN (BIT(26)) +#define BIT_DDR_UMCTL_RET_EN (BIT(25)) +#define BIT_DDR_PHY_AUTO_RET_EN (BIT(24)) +#define BITS_DDR_OPERATE_MODE_CNT_LMT(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_DDR_OPERATE_MODE(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10))) +#define BITS_DDR_OPERATE_MODE_IDLE(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2))) + +/* bits definitions for register REG_PMU_APB_DDR_PHY_RET_CFG */ +#define BIT_DDR_UMCTL_SOFT_RST (BIT(16)) +#define BIT_DDR_PHY_CKE_RET_EN (BIT(0)) + +/* bits definitions for register REG_PMU_APB_26M_SEL_CFG */ +#define BIT_AON_MEM_PD_EN_CP2 (BIT(9)) +#define BIT_AON_MEM_PD_EN_CP0 (BIT(8)) +#define BIT_AON_MEM_PD_EN_AP (BIT(7)) +#define BIT_LPLL_REF_SEL (BIT(6)) +#define BIT_PUB_26M_SEL (BIT(5)) +#define BIT_AON_26M_SEL (BIT(4)) +#define BIT_CP2_26M_SEL (BIT(3)) +#define BIT_CP1_26M_SEL (BIT(2)) +#define BIT_CP0_26M_SEL (BIT(1)) +#define BIT_AP_26M_SEL (BIT(0)) + +/* bits definitions for register REG_PMU_APB_MEM_PD_CFG0 */ +#define BITS_CP0_W_MEM_PD_CFG_UART1(_X_) ((_X_) << 22 & (BIT(22)|BIT(23))) +#define BITS_CP0_W_MEM_PD_CFG_UART0(_X_) ((_X_) << 20 & (BIT(20)|BIT(21))) +#define BITS_CP0_W_MEM_PD_CFG_IRAM(_X_) ((_X_) << 18 & (BIT(18)|BIT(19))) +#define BITS_CP0_W_MEM_PD_CFG_PERIF(_X_) ((_X_) << 16 & (BIT(16)|BIT(17))) +#define BITS_AON_MEM_PD_CFG_IRAM(_X_) ((_X_) << 14 & (BIT(14)|BIT(15))) +#define BITS_AON_MEM_PD_CFG_IMC3(_X_) ((_X_) << 12 & (BIT(12)|BIT(13))) +#define BITS_AON_MEM_PD_CFG_IMC2(_X_) ((_X_) << 10 & (BIT(10)|BIT(11))) +#define BITS_AON_MEM_PD_CFG_IMC1(_X_) ((_X_) << 8 & (BIT(8)|BIT(9))) +#define BITS_AON_MEM_PD_CFG_IMC0(_X_) ((_X_) << 6 & (BIT(6)|BIT(7))) +#define BITS_AON_MEM_PD_CFG_VBC(_X_) ((_X_) << 4 & (BIT(4)|BIT(5))) +#define BITS_AON_MEM_PD_CFG_AUD(_X_) ((_X_) << 2 & (BIT(2)|BIT(3))) +#define BITS_AON_MEM_PD_CFG_FM(_X_) ((_X_) & (BIT(0)|BIT(1))) + +/* bits definitions for register REG_PMU_APB_MEM_PD_CFG1 */ +#define BITS_CP0_DSP_MEM_PD_CFG_DMA(_X_) ((_X_) << 24 & (BIT(24)|BIT(25))) +#define BITS_CP0_DSP_MEM_PD_CFG_SHM(_X_) ((_X_) << 22 & (BIT(22)|BIT(23))) +#define BITS_CP0_DSP_MEM_PD_CFG_RFT(_X_) ((_X_) << 20 & (BIT(20)|BIT(21))) +#define BITS_CP0_DSP_MEM_PD_CFG_STC(_X_) ((_X_) << 18 & (BIT(18)|BIT(19))) +#define BITS_CP0_ARM_MEM_PD_CFG_IIS3(_X_) ((_X_) << 16 & (BIT(16)|BIT(17))) +#define BITS_CP0_ARM_MEM_PD_CFG_IIS2(_X_) ((_X_) << 14 & (BIT(14)|BIT(15))) +#define BITS_CP0_ARM_MEM_PD_CFG_IIS1(_X_) ((_X_) << 12 & (BIT(12)|BIT(13))) +#define BITS_CP0_ARM_MEM_PD_CFG_IIS0(_X_) ((_X_) << 10 & (BIT(10)|BIT(11))) +#define BITS_CP0_ARM_MEM_PD_CFG_UART1(_X_) ((_X_) << 8 & (BIT(8)|BIT(9))) +#define BITS_CP0_ARM_MEM_PD_CFG_UART0(_X_) ((_X_) << 6 & (BIT(6)|BIT(7))) +#define BITS_CP0_ARM_MEM_PD_CFG_EPT(_X_) ((_X_) << 4 & (BIT(4)|BIT(5))) +#define BITS_CP0_ARM_MEM_PD_CFG_LZMA(_X_) ((_X_) << 2 & (BIT(2)|BIT(3))) +#define BITS_CP0_ARM_MEM_PD_CFG_DMA(_X_) ((_X_) & (BIT(0)|BIT(1))) + +/* bits definitions for register REG_PMU_APB_PD_DDR_PUBL_CFG */ +#define BIT_PD_DDR_PUBL_FORCE_SHUTDOWN (BIT(25)) +#define BIT_PD_DDR_PUBL_AUTO_SHUTDOWN_EN (BIT(24)) +#define BITS_PD_DDR_PUBL_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_PD_DDR_PUBL_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_PD_DDR_PUBL_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7))) + +/* bits definitions for register REG_PMU_APB_PD_DDR_PHY_CFG */ +#define BIT_PD_DDR_PHY_FORCE_SHUTDOWN (BIT(25)) +#define BIT_PD_DDR_PHY_AUTO_SHUTDOWN_EN (BIT(24)) +#define BITS_PD_DDR_PHY_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_PD_DDR_PHY_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_PD_DDR_PHY_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7))) + +/* bits definitions for register REG_PMU_APB_BISR_CFG2 */ +#define BIT_PD_CP2_WIFI_BISR_DONE (BIT(7)) +#define BIT_PD_AP_SYS_BISR_DONE (BIT(6)) +#define BIT_PD_CP2_WIFI_BISR_BUSY (BIT(5)) +#define BIT_PD_AP_SYS_BISR_BUSY (BIT(4)) +#define BIT_PD_CP2_WIFI_BISR_FORCE_EN (BIT(3)) +#define BIT_PD_AP_SYS_BISR_FORCE_EN (BIT(2)) +#define BIT_PD_CP2_WIFI_BISR_FORCE_BYP (BIT(1)) +#define BIT_PD_AP_SYS_BISR_FORCE_BYP (BIT(0)) + +/* bits definitions for register REG_PMU_APB_CGM_CODEC_AUTO_GATE_EN */ +#define BIT_CGM_76M8_CODEC_AUTO_GATE_EN (BIT(5)) +#define BIT_CGM_96M_CODEC_AUTO_GATE_EN (BIT(4)) +#define BIT_CGM_128M_CODEC_AUTO_GATE_EN (BIT(3)) +#define BIT_CGM_153M6_CODEC_AUTO_GATE_EN (BIT(2)) +#define BIT_CGM_192M_CODEC_AUTO_GATE_EN (BIT(1)) +#define BIT_CGM_26M_CODEC_AUTO_GATE_EN (BIT(0)) + +/* bits definitions for register REG_PMU_APB_CGM_CODEC_EN */ +#define BIT_CGM_76M8_CODEC_EN (BIT(5)) +#define BIT_CGM_96M_CODEC_EN (BIT(4)) +#define BIT_CGM_128M_CODEC_EN (BIT(3)) +#define BIT_CGM_153M6_CODEC_EN (BIT(2)) +#define BIT_CGM_192M_CODEC_EN (BIT(1)) +#define BIT_CGM_26M_CODEC_EN (BIT(0)) + +/* bits definitions for register REG_PMU_APB_PD_CODEC_TOP_CFG */ +#define BIT_PD_CODEC_TOP_FORCE_SHUTDOWN (BIT(25)) +#define BIT_PD_CODEC_TOP_AUTO_SHUTDOWN_EN (BIT(24)) +#define BITS_PD_CODEC_TOP_PWR_ON_DLY(_X_) ((_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_PD_CODEC_TOP_PWR_ON_SEQ_DLY(_X_) ((_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_PD_CODEC_TOP_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7))) + +/* bits definitions for register REG_PMU_APB_PUB_SYS_PD_FLAG */ +#define BIT_PUB_SYS_PD_FLAG (BIT(0)) + +/* bits definitions for register REG_PMU_APB_DDR_PHY_PD_FLAG */ +#define BIT_DDR_PHY_PD_FLAG (BIT(0)) + +#endif diff --git a/include/soc/sprd/chip_x30g/__regs_pub_apb.h b/include/soc/sprd/chip_x30g/__regs_pub_apb.h new file mode 100644 index 00000000..be6df61d --- /dev/null +++ b/include/soc/sprd/chip_x30g/__regs_pub_apb.h @@ -0,0 +1,477 @@ +/*
+ * Copyright (C) 2014 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+#ifndef __SCI_GLB_REGS_H__
+#error "Don't include this file directly, Pls include sci_glb_regs.h"
+#endif
+
+
+#ifndef __H_REGS_PUB_APB_HEADFILE_H__
+#define __H_REGS_PUB_APB_HEADFILE_H__ __FILE__
+
+#define REGS_PUB_APB
+
+/* registers definitions for PUB_APB */
+#define REG_PUB_APB_BUSMON_CNT_START SCI_ADDR(REGS_PUB_APB_BASE, 0x0000)
+#define REG_PUB_APB_BUSMON_CFG SCI_ADDR(REGS_PUB_APB_BASE, 0x0004)
+#define REG_PUB_APB_DDR_EB SCI_ADDR(REGS_PUB_APB_BASE, 0x0008)
+#define REG_PUB_APB_DDR_SOFT_RST SCI_ADDR(REGS_PUB_APB_BASE, 0x000C)
+#define REG_PUB_APB_DDR_QOS_CFG1 SCI_ADDR(REGS_PUB_APB_BASE, 0x0010)
+#define REG_PUB_APB_DDR_QOS_CFG2 SCI_ADDR(REGS_PUB_APB_BASE, 0x0014)
+#define REG_PUB_APB_DDR_QOS_CFG3 SCI_ADDR(REGS_PUB_APB_BASE, 0x0018)
+#define REG_PUB_APB_DDR_MRR_STATUS SCI_ADDR(REGS_PUB_APB_BASE, 0x001C)
+#define REG_PUB_APB_DDR_ID2QOS_SEL SCI_ADDR(REGS_PUB_APB_BASE, 0x003C)
+#define REG_PUB_APB_DDR_ID2QOS_RCFG0 SCI_ADDR(REGS_PUB_APB_BASE, 0x0040)
+#define REG_PUB_APB_DDR_ID2QOS_RCFG1 SCI_ADDR(REGS_PUB_APB_BASE, 0x0044)
+#define REG_PUB_APB_DDR_ID2QOS_RCFG2 SCI_ADDR(REGS_PUB_APB_BASE, 0x0048)
+#define REG_PUB_APB_DDR_ID2QOS_RCFG3 SCI_ADDR(REGS_PUB_APB_BASE, 0x004c)
+#define REG_PUB_APB_DDR_ID2QOS_RCFG4 SCI_ADDR(REGS_PUB_APB_BASE, 0x0050)
+#define REG_PUB_APB_DDR_ID2QOS_RCFG5 SCI_ADDR(REGS_PUB_APB_BASE, 0x0054)
+#define REG_PUB_APB_DDR_ID2QOS_RCFG6 SCI_ADDR(REGS_PUB_APB_BASE, 0x0058)
+#define REG_PUB_APB_DDR_ID2QOS_RCFG7 SCI_ADDR(REGS_PUB_APB_BASE, 0x005c)
+#define REG_PUB_APB_DDR_ID2QOS_RCFG8 SCI_ADDR(REGS_PUB_APB_BASE, 0x0060)
+#define REG_PUB_APB_DDR_ID2QOS_RCFG9 SCI_ADDR(REGS_PUB_APB_BASE, 0x0064)
+#define REG_PUB_APB_DDR_ID2QOS_WCFG0 SCI_ADDR(REGS_PUB_APB_BASE, 0x0080)
+#define REG_PUB_APB_DDR_ID2QOS_WCFG1 SCI_ADDR(REGS_PUB_APB_BASE, 0x0084)
+#define REG_PUB_APB_DDR_ID2QOS_WCFG2 SCI_ADDR(REGS_PUB_APB_BASE, 0x0088)
+#define REG_PUB_APB_DDR_ID2QOS_WCFG3 SCI_ADDR(REGS_PUB_APB_BASE, 0x008c)
+#define REG_PUB_APB_DDR_ID2QOS_WCFG4 SCI_ADDR(REGS_PUB_APB_BASE, 0x0090)
+#define REG_PUB_APB_DDR_ID2QOS_WCFG5 SCI_ADDR(REGS_PUB_APB_BASE, 0x0094)
+#define REG_PUB_APB_DDR_ID2QOS_WCFG6 SCI_ADDR(REGS_PUB_APB_BASE, 0x0098)
+#define REG_PUB_APB_DDR_ID2QOS_WCFG7 SCI_ADDR(REGS_PUB_APB_BASE, 0x009c)
+#define REG_PUB_APB_DDR_ID2QOS_WCFG8 SCI_ADDR(REGS_PUB_APB_BASE, 0x00a0)
+#define REG_PUB_APB_DDR_ID2QOS_WCFG9 SCI_ADDR(REGS_PUB_APB_BASE, 0x00a4)
+#define REG_PUB_APB_DFI_TIMEOUT_CFG SCI_ADDR(REGS_PUB_APB_BASE, 0x0100)
+#define REG_PUB_APB_DFI_TIMEOUT_STATUS SCI_ADDR(REGS_PUB_APB_BASE, 0x0104)
+#define REG_PUB_APB_DFI_TIMEOUT_EN_CNT SCI_ADDR(REGS_PUB_APB_BASE, 0x0108)
+#define REG_PUB_APB_DFI_TIMEOUT_VALID_CNT SCI_ADDR(REGS_PUB_APB_BASE, 0x010c)
+#define REG_PUB_APB_DMC_PORT_REMAP_EN SCI_ADDR(REGS_PUB_APB_BASE, 0x3000)
+#define REG_PUB_APB_DMC_PORTS_MPU_EN SCI_ADDR(REGS_PUB_APB_BASE, 0x3004)
+#define REG_PUB_APB_DMC_PORT0_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3008)
+#define REG_PUB_APB_DMC_PORT1_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x300C)
+#define REG_PUB_APB_DMC_PORT2_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3010)
+#define REG_PUB_APB_DMC_PORT3_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3014)
+#define REG_PUB_APB_DMC_PORT4_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3018)
+#define REG_PUB_APB_DMC_PORT5_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x301C)
+#define REG_PUB_APB_DMC_PORT6_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3020)
+#define REG_PUB_APB_DMC_PORT7_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3024)
+#define REG_PUB_APB_DMC_PORT8_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3028)
+#define REG_PUB_APB_DMC_PORT9_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x302C)
+#define REG_PUB_APB_DMC_PORT0_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3030)
+#define REG_PUB_APB_DMC_PORT1_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3034)
+#define REG_PUB_APB_DMC_PORT2_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3038)
+#define REG_PUB_APB_DMC_PORT3_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x303C)
+#define REG_PUB_APB_DMC_PORT4_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3040)
+#define REG_PUB_APB_DMC_PORT5_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3044)
+#define REG_PUB_APB_DMC_PORT6_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3048)
+#define REG_PUB_APB_DMC_PORT7_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3050)
+#define REG_PUB_APB_DMC_PORT8_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3054)
+#define REG_PUB_APB_DMC_PORT9_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3058)
+#define REG_PUB_APB_DMC_PORT0_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x305C)
+#define REG_PUB_APB_DMC_PORT1_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3060)
+#define REG_PUB_APB_DMC_PORT2_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3064)
+#define REG_PUB_APB_DMC_PORT3_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3068)
+#define REG_PUB_APB_DMC_PORT4_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x306C)
+#define REG_PUB_APB_DMC_PORT5_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3070)
+#define REG_PUB_APB_DMC_PORT6_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3074)
+#define REG_PUB_APB_DMC_PORT7_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3078)
+#define REG_PUB_APB_DMC_PORT8_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x307C)
+#define REG_PUB_APB_DMC_PORT9_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3080)
+
+
+
+/* bits definitions for register REG_PUB_APB_BUSMON_CNT_START */
+#define BIT_PUB_BUSMON_CNT_START ( BIT(0) )
+
+/* bits definitions for register REG_PUB_APB_BUSMON_CFG */
+#define BIT_PUB_BUSMON9_EB ( BIT(25) )
+#define BIT_PUB_BUSMON8_EB ( BIT(24) )
+#define BIT_PUB_BUSMON7_EB ( BIT(23) )
+#define BIT_PUB_BUSMON6_EB ( BIT(22) )
+#define BIT_PUB_BUSMON5_EB ( BIT(21) )
+#define BIT_PUB_BUSMON4_EB ( BIT(20) )
+#define BIT_PUB_BUSMON3_EB ( BIT(19) )
+#define BIT_PUB_BUSMON2_EB ( BIT(18) )
+#define BIT_PUB_BUSMON1_EB ( BIT(17) )
+#define BIT_PUB_BUSMON0_EB ( BIT(16) )
+#define BIT_PUB_BUSMON9_SOFT_RST ( BIT(9) )
+#define BIT_PUB_BUSMON8_SOFT_RST ( BIT(8) )
+#define BIT_PUB_BUSMON7_SOFT_RST ( BIT(7) )
+#define BIT_PUB_BUSMON6_SOFT_RST ( BIT(6) )
+#define BIT_PUB_BUSMON5_SOFT_RST ( BIT(5) )
+#define BIT_PUB_BUSMON4_SOFT_RST ( BIT(4) )
+#define BIT_PUB_BUSMON3_SOFT_RST ( BIT(3) )
+#define BIT_PUB_BUSMON2_SOFT_RST ( BIT(2) )
+#define BIT_PUB_BUSMON1_SOFT_RST ( BIT(1) )
+#define BIT_PUB_BUSMON0_SOFT_RST ( BIT(0) )
+
+/* bits definitions for register REG_PUB_APB_DDR_EB */
+
+/* bits definitions for register REG_PUB_APB_DDR_SOFT_RST */
+
+/* bits definitions for register REG_PUB_APB_DDR_QOS_CFG1 */
+#define BITS_DMC_ARQOS_3(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_AWQOS_3(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_ARQOS_2(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_AWQOS_2(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_ARQOS_1(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_AWQOS_1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_ARQOS_0(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_AWQOS_0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_QOS_CFG2 */
+#define BITS_DMC_ARQOS_7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_AWQOS_7(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_ARQOS_6(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_AWQOS_6(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_ARQOS_5(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_AWQOS_5(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_ARQOS_4(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_AWQOS_4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_QOS_CFG3 */
+#define BITS_DMC_ARQOS_9(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_AWQOS_9(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_ARQOS_8(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_AWQOS_8(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_MRR_STATUS */
+#define BIT_DDRC_CO_RD_MRR_DATA_VALID ( BIT(8) )
+#define BITS_DDRC_CO_RD_MRR_DATA(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_SEL */
+#define BITS_DMC_ID_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) )
+#define BITS_DMC_QOS_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG0 */
+#define BITS_DMC_ARQOS_0_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_ARQOS_0_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_ARQOS_0_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_ARQOS_0_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_ARQOS_0_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_ARQOS_0_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_ARQOS_0_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_ARQOS_0_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG1 */
+#define BITS_DMC_ARQOS_1_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_ARQOS_1_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_ARQOS_1_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_ARQOS_1_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_ARQOS_1_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_ARQOS_1_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_ARQOS_1_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_ARQOS_1_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG2 */
+#define BITS_DMC_ARQOS_2_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_ARQOS_2_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_ARQOS_2_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_ARQOS_2_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_ARQOS_2_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_ARQOS_2_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_ARQOS_2_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_ARQOS_2_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG3 */
+#define BITS_DMC_ARQOS_3_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_ARQOS_3_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_ARQOS_3_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_ARQOS_3_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_ARQOS_3_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_ARQOS_3_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_ARQOS_3_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_ARQOS_3_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG4 */
+#define BITS_DMC_ARQOS_4_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_ARQOS_4_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_ARQOS_4_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_ARQOS_4_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_ARQOS_4_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_ARQOS_4_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_ARQOS_4_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_ARQOS_4_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG5 */
+#define BITS_DMC_ARQOS_5_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_ARQOS_5_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_ARQOS_5_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_ARQOS_5_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_ARQOS_5_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_ARQOS_5_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_ARQOS_5_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_ARQOS_5_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG6 */
+#define BITS_DMC_ARQOS_6_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_ARQOS_6_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_ARQOS_6_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_ARQOS_6_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_ARQOS_6_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_ARQOS_6_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_ARQOS_6_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_ARQOS_6_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG7 */
+#define BITS_DMC_ARQOS_7_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_ARQOS_7_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_ARQOS_7_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_ARQOS_7_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_ARQOS_7_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_ARQOS_7_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_ARQOS_7_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_ARQOS_7_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG8 */
+#define BITS_DMC_ARQOS_8_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_ARQOS_8_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_ARQOS_8_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_ARQOS_8_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_ARQOS_8_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_ARQOS_8_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_ARQOS_8_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_ARQOS_8_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG9 */
+#define BITS_DMC_ARQOS_9_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_ARQOS_9_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_ARQOS_9_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_ARQOS_9_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_ARQOS_9_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_ARQOS_9_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_ARQOS_9_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_ARQOS_9_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG0 */
+#define BITS_DMC_AWQOS_0_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_AWQOS_0_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_AWQOS_0_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_AWQOS_0_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_AWQOS_0_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_AWQOS_0_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_AWQOS_0_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_AWQOS_0_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG1 */
+#define BITS_DMC_AWQOS_1_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_AWQOS_1_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_AWQOS_1_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_AWQOS_1_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_AWQOS_1_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_AWQOS_1_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_AWQOS_1_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_AWQOS_1_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG2 */
+#define BITS_DMC_AWQOS_2_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_AWQOS_2_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_AWQOS_2_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_AWQOS_2_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_AWQOS_2_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_AWQOS_2_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_AWQOS_2_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_AWQOS_2_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG3 */
+#define BITS_DMC_AWQOS_3_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_AWQOS_3_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_AWQOS_3_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_AWQOS_3_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_AWQOS_3_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_AWQOS_3_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_AWQOS_3_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_AWQOS_3_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG4 */
+#define BITS_DMC_AWQOS_4_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_AWQOS_4_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_AWQOS_4_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_AWQOS_4_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_AWQOS_4_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_AWQOS_4_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_AWQOS_4_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_AWQOS_4_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG5 */
+#define BITS_DMC_AWQOS_5_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_AWQOS_5_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_AWQOS_5_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_AWQOS_5_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_AWQOS_5_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_AWQOS_5_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_AWQOS_5_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_AWQOS_5_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG6 */
+#define BITS_DMC_AWQOS_6_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_AWQOS_6_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_AWQOS_6_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_AWQOS_6_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_AWQOS_6_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_AWQOS_6_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_AWQOS_6_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_AWQOS_6_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG7 */
+#define BITS_DMC_AWQOS_7_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_AWQOS_7_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_AWQOS_7_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_AWQOS_7_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_AWQOS_7_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_AWQOS_7_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_AWQOS_7_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_AWQOS_7_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG8 */
+#define BITS_DMC_AWQOS_8_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_AWQOS_8_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_AWQOS_8_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_AWQOS_8_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_AWQOS_8_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_AWQOS_8_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_AWQOS_8_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_AWQOS_8_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG9 */
+#define BITS_DMC_AWQOS_9_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_AWQOS_9_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_AWQOS_9_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_AWQOS_9_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_AWQOS_9_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_AWQOS_9_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_AWQOS_9_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_AWQOS_9_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DFI_TIMEOUT_CFG */
+#define BITS_DFI_TIMEOUT_THRESHOLD(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DFI_TIMEOUT_CLR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DFI_TIMEOUT_EN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DFI_TIMEOUT_STATUS */
+#define BITS_DFI_TIMEOUT_STATUS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DFI_TIMEOUT_EN_CNT */
+#define BITS_DFI_TIMEOUT_EN3_CNT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DFI_TIMEOUT_EN2_CNT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DFI_TIMEOUT_EN1_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DFI_TIMEOUT_EN0_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PUB_APB_DFI_TIMEOUT_VALID_CNT */
+#define BITS_DFI_TIMEOUT_VALID3_CNT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DFI_TIMEOUT_VALID2_CNT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DFI_TIMEOUT_VALID1_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DFI_TIMEOUT_VALID0_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT_REMAP_EN */
+#define BITS_DMC_PORTS_REMAP_EN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+
+/* bits definitions for register REG_PUB_APB_DMC_PORTS_MPU_EN */
+#define BITS_DMC_PORTS_MPU_EN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT0_ADDR_REMAP */
+#define BITS_DMC_PORT0_ADDR_REMAP(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT1_ADDR_REMAP */
+#define BITS_DMC_PORT1_ADDR_REMAP(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT2_ADDR_REMAP */
+#define BITS_DMC_PORT2_ADDR_REMAP(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT3_ADDR_REMAP */
+#define BITS_DMC_PORT3_ADDR_REMAP(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT4_ADDR_REMAP */
+#define BITS_DMC_PORT4_ADDR_REMAP(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT5_ADDR_REMAP */
+#define BITS_DMC_PORT5_ADDR_REMAP(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT6_ADDR_REMAP */
+#define BITS_DMC_PORT6_ADDR_REMAP(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT7_ADDR_REMAP */
+#define BITS_DMC_PORT7_ADDR_REMAP(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT8_ADDR_REMAP */
+#define BITS_DMC_PORT8_ADDR_REMAP(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT9_ADDR_REMAP */
+#define BITS_DMC_PORT9_ADDR_REMAP(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT0_MPU_RANGE */
+#define BITS_DMC_PORT0_MPU_RANGE(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT1_MPU_RANGE */
+#define BITS_DMC_PORT1_MPU_RANGE(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT2_MPU_RANGE */
+#define BITS_DMC_PORT2_MPU_RANGE(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT3_MPU_RANGE */
+#define BITS_DMC_PORT3_MPU_RANGE(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT4_MPU_RANGE */
+#define BITS_DMC_PORT4_MPU_RANGE(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT5_MPU_RANGE */
+#define BITS_DMC_PORT5_MPU_RANGE(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT6_MPU_RANGE */
+#define BITS_DMC_PORT6_MPU_RANGE(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT7_MPU_RANGE */
+#define BITS_DMC_PORT7_MPU_RANGE(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT8_MPU_RANGE */
+#define BITS_DMC_PORT8_MPU_RANGE(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT9_MPU_RANGE */
+#define BITS_DMC_PORT9_MPU_RANGE(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT0_DUMP_ADDR */
+#define BITS_DMC_PORT0_DUMP_ADDR(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT1_DUMP_ADDR */
+#define BITS_DMC_PORT1_DUMP_ADDR(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT2_DUMP_ADDR */
+#define BITS_DMC_PORT2_DUMP_ADDR(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT3_DUMP_ADDR */
+#define BITS_DMC_PORT3_DUMP_ADDR(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT4_DUMP_ADDR */
+#define BITS_DMC_PORT4_DUMP_ADDR(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT5_DUMP_ADDR */
+#define BITS_DMC_PORT5_DUMP_ADDR(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT6_DUMP_ADDR */
+#define BITS_DMC_PORT6_DUMP_ADDR(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT7_DUMP_ADDR */
+#define BITS_DMC_PORT7_DUMP_ADDR(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT8_DUMP_ADDR */
+#define BITS_DMC_PORT8_DUMP_ADDR(_X_) (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT9_DUMP_ADDR */
+#define BITS_DMC_PORT9_DUMP_ADDR(_X_) (_X_)
+
+#endif
diff --git a/include/soc/sprd/chip_x30g/__regs_wcdma_ahb_rf.h b/include/soc/sprd/chip_x30g/__regs_wcdma_ahb_rf.h new file mode 100644 index 00000000..1be075b6 --- /dev/null +++ b/include/soc/sprd/chip_x30g/__regs_wcdma_ahb_rf.h @@ -0,0 +1,136 @@ +/*
+ * Copyright (C) 2014 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+#ifndef __SCI_GLB_REGS_H__
+#error "Don't include this file directly, Pls include sci_glb_regs.h"
+#endif
+
+
+#ifndef __H_REGS_WCDMA_AHB_RF_HEADFILE_H__
+#define __H_REGS_WCDMA_AHB_RF_HEADFILE_H__ __FILE__
+
+#define REGS_WCDMA_AHB_RF
+
+/* registers definitions for WCDMA_AHB_RF */
+#define REG_WCDMA_AHB_RF_AHB_EB0 SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0000)
+#define REG_WCDMA_AHB_RF_AHB_RST0 SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0004)
+#define REG_WCDMA_AHB_RF_ARCH_EB_REG SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0018)
+#define REG_WCDMA_AHB_RF_AHB_REMAP SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x001C)
+#define REG_WCDMA_AHB_RF_AHB_MISC_CTL SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0020)
+#define REG_WCDMA_AHB_RF_AHB_MTX_PRI_SEL0 SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0024)
+#define REG_WCDMA_AHB_RF_AHB_MTX_PRI_SEL1 SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0028)
+#define REG_WCDMA_AHB_RF_AHB1_PAUSE SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x002C)
+#define REG_WCDMA_AHB_RF_AHB2_PAUSE SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0030)
+#define REG_WCDMA_AHB_RF_AHB_SLP_CTL SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0034)
+#define REG_WCDMA_AHB_RF_AHB2_SLP_STS SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0038)
+#define REG_WCDMA_AHB_RF_MCU_CLK_CTL SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x003C)
+#define REG_WCDMA_AHB_RF_CHIP_ID SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x01FC)
+
+
+
+/* bits definitions for register REG_WCDMA_AHB_RF_AHB_EB0 */
+#define BITS_WCDMA_EN(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BIT_BUSMON1_EN ( BIT(2) )
+#define BIT_BUSMON0_EN ( BIT(1) )
+#define BIT_SPINLOCK_EN ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_AHB_RF_AHB_RST0 */
+#define BIT_WCDMA_SOFT_RST ( BIT(3) )
+#define BIT_BUSMON1_SOFT_RST ( BIT(2) )
+#define BIT_BUSMON0_SOFT_RST ( BIT(1) )
+#define BIT_SPINLOCK_SOFT_RST ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_AHB_RF_ARCH_EB_REG */
+#define BIT_AHB_ARCH_EB ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_AHB_RF_AHB_REMAP */
+#define BIT_ARM_JTAG_EN_ARM2 ( BIT(2) )
+#define BIT_ARM_JTAG_EN_ARM1 ( BIT(1) )
+#define BIT_REMAP ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_AHB_RF_AHB_MISC_CTL */
+#define BIT_FORCE_WSYS_ACC_STOP ( BIT(3) )
+#define BIT_W_DMA_LSLP_EN ( BIT(2) )
+#define BIT_BUSMON1_SEL ( BIT(1) )
+#define BIT_BUSMON0_SEL ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_AHB_RF_AHB_MTX_PRI_SEL0 */
+#define BITS_ARMMTX_M3TOS0_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_ARMMTX_M3TOS0_ADJ_EN ( BIT(27) )
+#define BIT_ARMMTX_M3TOS0_RND_EN ( BIT(26) )
+#define BITS_ARMMTX_M3TOS0_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) )
+#define BITS_ARMMTX_M2TOS0_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BIT_ARMMTX_M2TOS0_ADJ_EN ( BIT(19) )
+#define BIT_ARMMTX_M2TOS0_RND_EN ( BIT(18) )
+#define BITS_ARMMTX_M2TOS0_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_ARMMTX_M1TOS0_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BIT_ARMMTX_M1TOS0_ADJ_EN ( BIT(11) )
+#define BIT_ARMMTX_M1TOS0_RND_EN ( BIT(10) )
+#define BITS_ARMMTX_M1TOS0_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ARMMTX_M0TOS0_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_ARMMTX_M0TOS0_ADJ_EN ( BIT(3) )
+#define BIT_ARMMTX_M0TOS0_RND_EN ( BIT(2) )
+#define BITS_ARMMTX_M0TOS0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_WCDMA_AHB_RF_AHB_MTX_PRI_SEL1 */
+#define BITS_ARMMTX_M6TOS0_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BIT_ARMMTX_M6TOS0_ADJ_EN ( BIT(19) )
+#define BIT_ARMMTX_M6TOS0_RND_EN ( BIT(18) )
+#define BITS_ARMMTX_M6TOS0_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_ARMMTX_M5TOS0_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BIT_ARMMTX_M5TOS0_ADJ_EN ( BIT(11) )
+#define BIT_ARMMTX_M5TOS0_RND_EN ( BIT(10) )
+#define BITS_ARMMTX_M5TOS0_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ARMMTX_M4TOS0_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_ARMMTX_M4TOS0_ADJ_EN ( BIT(3) )
+#define BIT_ARMMTX_M4TOS0_RND_EN ( BIT(2) )
+#define BITS_ARMMTX_M4TOS0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_WCDMA_AHB_RF_AHB1_PAUSE */
+#define BIT_APB1_SLEEP ( BIT(3) )
+#define BIT_MCU1_DEEP_SLEEP_EN ( BIT(2) )
+#define BIT_MCU1_SYS_SLEEP_EN ( BIT(1) )
+#define BIT_MCU1_CORE_SLEEP ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_AHB_RF_AHB2_PAUSE */
+#define BIT_APB2_SLEEP ( BIT(3) )
+#define BIT_MCU2_DEEP_SLEEP_EN ( BIT(2) )
+#define BIT_MCU2_SYS_SLEEP_EN ( BIT(1) )
+#define BIT_MCU2_CORE_SLEEP ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_AHB_RF_AHB_SLP_CTL */
+#define BIT_MCUMTX_AUTO_GATE_EN ( BIT(4) )
+#define BIT_MCU_AUTO_GATE_EN ( BIT(3) )
+#define BIT_AHB_AUTO_GATE_EN ( BIT(2) )
+#define BIT_ARM2_AUTO_GATE_EN ( BIT(1) )
+#define BIT_ARM1_AUTO_GATE_EN ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_AHB_RF_AHB2_SLP_STS */
+#define BIT_APB2_PERI_SLEEP ( BIT(1) )
+#define BIT_APB1_PERI_SLEEP ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_AHB_RF_MCU_CLK_CTL */
+#define BITS_CLK_AHB_DIV(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_CLK_MCU_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) )
+#define BITS_CLK_APB_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_CLK_MCU_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_WCDMA_AHB_RF_CHIP_ID */
+#define BITS_CHIP_ID(_X_) (_X_)
+
+#endif
diff --git a/include/soc/sprd/chip_x30g/__regs_wcdma_apb_rf.h b/include/soc/sprd/chip_x30g/__regs_wcdma_apb_rf.h new file mode 100644 index 00000000..4249f10d --- /dev/null +++ b/include/soc/sprd/chip_x30g/__regs_wcdma_apb_rf.h @@ -0,0 +1,77 @@ +/*
+ * Copyright (C) 2014 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+#ifndef __SCI_GLB_REGS_H__
+#error "Don't include this file directly, Pls include sci_glb_regs.h"
+#endif
+
+
+#ifndef __H_REGS_WCDMA_APB_RF_HEADFILE_H__
+#define __H_REGS_WCDMA_APB_RF_HEADFILE_H__ __FILE__
+
+#define REGS_WCDMA_APB_RF
+
+/* registers definitions for WCDMA_APB_RF */
+#define REG_WCDMA_APB_RF_APB_EB SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0000)
+#define REG_WCDMA_APB_RF_APB_RST SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0004)
+#define REG_WCDMA_APB_RF_APB_SLEEP_ST SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0008)
+#define REG_WCDMA_APB_RF_APB_MCU_RST SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0018)
+#define REG_WCDMA_APB_RF_APB_CLK_SEL0 SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x001C)
+#define REG_WCDMA_APB_RF_APB_CLK_DIV0 SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0020)
+#define REG_WCDMA_APB_RF_APB_ARCH_EB SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0024)
+#define REG_WCDMA_APB_RF_APB_SLP_CTL SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0028)
+
+
+
+/* bits definitions for register REG_WCDMA_APB_RF_APB_EB */
+#define BIT_TMR_RTC_EB ( BIT(6) )
+#define BIT_TMR_EB ( BIT(5) )
+#define BIT_SYSTMR_RTC_EB ( BIT(4) )
+#define BIT_SYSTMR_EB ( BIT(3) )
+#define BIT_UART0_EB ( BIT(2) )
+#define BIT_WDG_RTC_EB ( BIT(1) )
+#define BIT_WDG_EB ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_APB_RF_APB_RST */
+#define BIT_TMR_SOFT_RST ( BIT(3) )
+#define BIT_SYSTMR_SOFT_RST ( BIT(2) )
+#define BIT_UART0_SOFT_RST ( BIT(1) )
+#define BIT_WDG_SOFT_RST ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_APB_RF_APB_SLEEP_ST */
+#define BIT_CHIP_SLEEP_REC_CLR ( BIT(1) )
+#define BIT_CHIP_SLEEP_REC ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_APB_RF_APB_MCU_RST */
+#define BIT_MCU_SOFT_RST_SET ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_APB_RF_APB_CLK_SEL0 */
+#define BITS_CLK_UART0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_WCDMA_APB_RF_APB_CLK_DIV0 */
+#define BITS_CLK_UART0_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
+
+/* bits definitions for register REG_WCDMA_APB_RF_APB_ARCH_EB */
+#define BIT_RTC_ARCH_EB ( BIT(1) )
+#define BIT_APB_ARCH_EB ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_APB_RF_APB_SLP_CTL */
+#define BIT_APB_PERI_FRC_ON ( BIT(1) )
+#define BIT_APB_PERI_FRC_SLP ( BIT(0) )
+
+#endif
diff --git a/include/soc/sprd/chip_x30g/__sc2713s_regulator_map.h b/include/soc/sprd/chip_x30g/__sc2713s_regulator_map.h new file mode 100644 index 00000000..5ef090a1 --- /dev/null +++ b/include/soc/sprd/chip_x30g/__sc2713s_regulator_map.h @@ -0,0 +1,174 @@ +/* + * Copyright (C) 2013 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +/* + * Regulator (0)Name, Regulator (1)Type, Power Off (2)Ctrl and (3)Bit, Power On (4)Ctrl and (5)Bit, Sleep (6)Ctrl and (7)Bit, + * Voltage Trimming (8)Ctrl and (9)Bits, Calibration (10)Ctrl and (11)Bits, + * Voltage (12)Default, Voltage (13)Ctrl and (14)Bits, Voltage Select (15)Count and Voltage (16)List[ ... ...] + */ + +#if 0 + /* BONDOPT6 = 0 --> 45nm process */ + SCI_REGU_REG(vddcore, 2, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(9), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(9), 0, 0, + ANA_REG_GLB_DCDC_CORE_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(16)|BIT(18)|BIT(19), + 1100, ANA_REG_GLB_DCDC_CORE_ADI, BIT(5)|BIT(6)|BIT(7), 8, 1100, 700, 800, 900, 1000, 650, 1200, 1300); + + SCI_REGU_REG(vddarm, 2, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(10), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(10), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(9), + ANA_REG_GLB_DCDC_ARM_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(17)|BIT(18)|BIT(19), + 1100, ANA_REG_GLB_DCDC_ARM_ADI, BIT(5)|BIT(6)|BIT(7), 8, 1100, 700, 800, 900, 1000, 650, 1200, 1300); +#else + /* BONDOPT6 = 1 --> 28nm process */ + SCI_REGU_REG(vddcore, 2, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(9), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(9), 0, 0, + ANA_REG_GLB_DCDC_CORE_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(16)|BIT(18)|BIT(19), + 900, ANA_REG_GLB_MP_MISC_CTRL, BIT(3)|BIT(4)|BIT(5), 8, 1100, 700, 800, 900, 1000, 650, 1200, 1300); + + SCI_REGU_REG(vddarm, 2, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(10), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(10), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(9), + ANA_REG_GLB_DCDC_ARM_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(17)|BIT(18)|BIT(19), + 900, ANA_REG_GLB_MP_MISC_CTRL, BIT(6)|BIT(7)|BIT(8), 8, 1100, 700, 800, 900, 1000, 650, 1200, 1300); +#endif + + SCI_REGU_REG(vddmem, 2, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(11), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(11), 0, 0, + ANA_REG_GLB_DCDC_MEM_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(16)|BIT(17)|BIT(18)|BIT(19), + 1200, ANA_REG_GLB_DCDC_MEM_ADI, BIT(5), 2, 1200, 1250); + + SCI_REGU_REG(vddgen, 2, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(12), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(12), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(12), + ANA_REG_GLB_DCDC_GEN_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(20), + 2400, ANA_REG_GLB_DCDC_GEN_ADI, BIT(5)|BIT(6)|BIT(7), 8, 2200, 1800, 1900, 2000, 2100, 2300, 2400, 2500); + + SCI_REGU_REG(vddwpa, 2, ANA_REG_GLB_LDO_PD_CTRL, BIT(11), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL0, BIT(11), + ANA_REG_GLB_DCDC_WPA_ADI, BIT(0)|BIT(1)|BIT(2), ANA_REG_GLB_LDO_CAL_SEL, BIT(16)|BIT(20), + 0, 0, 0, 0); + +#if 1 + /* BONDOPT4 = 0 */ + SCI_REGU_REG(vddwrf, 2, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(13), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(13), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(10), + ANA_REG_GLB_DCDC_WRF_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(17)|BIT(20), + 1500, ANA_REG_GLB_DCDC_WRF_ADI, BIT(5)|BIT(6), 4, 1300, 1400, 1500, 1600); +#else + /* BONDOPT4 = 1 */ + SCI_REGU_REG(vddwrf, 2, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(13), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(13), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(10), + ANA_REG_GLB_DCDC_WRF_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(17)|BIT(20), + 2800, ANA_REG_GLB_DCDC_WRF_ADI, BIT(5)|BIT(6), 4, 2600, 2700, 2800, 2900); +#endif + + SCI_REGU_REG(vdd18, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(1), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(1), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(0), + ANA_REG_GLB_LDO_CAL_CTRL0, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(6)|BIT(7)|BIT(17)|BIT(18)|BIT(20), + 1800, ANA_REG_GLB_LDO_V_CTRL0, BIT(0)|BIT(1), 4, 1500, 1800, 1300, 1200); + + SCI_REGU_REG(vdd28, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(2), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(2), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(1), + ANA_REG_GLB_LDO_CAL_CTRL0, BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_LDO_CAL_SEL, BIT(8)|BIT(10)|BIT(16)|BIT(18)|BIT(20), + 0, ANA_REG_GLB_LDO_V_CTRL0, BIT(2)|BIT(3), 4, 2800, 3000, 2650, 1800); + +#if 0 + /* BONDOPT6 = 0 --> 45nm process */ + SCI_REGU_REG(vdd25, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(3), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(3), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(2), + ANA_REG_GLB_LDO_CAL_CTRL0, BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_CAL_SEL, BIT(9)|BIT(10)|BIT(16)|BIT(18)|BIT(20), + 2500, ANA_REG_GLB_LDO_V_CTRL0, BIT(4)|BIT(5), 4, 2500, 2750, 3000, 2900); +#else + /* BONDOPT6 = 1 --> 28nm process */ + SCI_REGU_REG(vdd25, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(3), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(3), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(2), + ANA_REG_GLB_LDO_CAL_CTRL0, BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_CAL_SEL, BIT(9)|BIT(10)|BIT(16)|BIT(18)|BIT(20), + 1800, ANA_REG_GLB_MP_MISC_CTRL, BIT(9)|BIT(10), 4, 2500, 2750, 1800, 1900); +#endif + + SCI_REGU_REG(vddrf0, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(4), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(4), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(3), + ANA_REG_GLB_LDO_CAL_CTRL1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(11)|BIT(13)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 2850, ANA_REG_GLB_LDO_V_CTRL0, BIT(6)|BIT(7), 4, 2850, 2950, 2500, 1800); + +#if 1 + /* BONDOPT4 = 0 */ + SCI_REGU_REG(vddrf1, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(5), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(5), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(4), + ANA_REG_GLB_LDO_CAL_CTRL1, BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_LDO_CAL_SEL, BIT(13)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 1200, ANA_REG_GLB_MP_MISC_CTRL, BIT(11)|BIT(12), 4, 2850, 1800, 1500, 1200); +#else + /* BONDOPT4 = 1 */ + SCI_REGU_REG(vddrf1, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(5), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(5), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(4), + ANA_REG_GLB_LDO_CAL_CTRL1, BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_LDO_CAL_SEL, BIT(13)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 2850, ANA_REG_GLB_LDO_V_CTRL0, BIT(8)|BIT(9), 4, 2850, 1800, 1500, 1200); +#endif + + SCI_REGU_REG(vddrf2, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(6), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(6), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(5), + ANA_REG_GLB_LDO_CAL_CTRL1, BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_CAL_SEL, BIT(11)|BIT(12)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 2850, ANA_REG_GLB_LDO_V_CTRL0, BIT(10)|BIT(11), 4, 2850, 1800, 1500, 1200); + + SCI_REGU_REG(vddemmcio, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(7), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(7), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(6), + ANA_REG_GLB_LDO_CAL_CTRL2, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(7)|BIT(17)|BIT(18)|BIT(20), + 1800, ANA_REG_GLB_LDO_V_CTRL0, BIT(12)|BIT(13), 4, 1500, 1800, 1300, 1200); + + SCI_REGU_REG(vddemmccore, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(8), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(8), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(7), + ANA_REG_GLB_LDO_CAL_CTRL2, BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_LDO_CAL_SEL, BIT(10)|BIT(16)|BIT(18)|BIT(20), + 3000, ANA_REG_GLB_LDO_V_CTRL0, BIT(14)|BIT(15), 4, 2800, 3000, 2500, 1800); + + SCI_REGU_REG(avdd18, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(15), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(15), ANA_REG_GLB_LDO_SLP_CTRL1, BIT(0), + ANA_REG_GLB_LDO_CAL_CTRL3, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(5)|BIT(7)|BIT(17)|BIT(18)|BIT(20), + 1800, ANA_REG_GLB_LDO_V_CTRL1, BIT(0)|BIT(1), 4, 1500, 1800, 1300, 1200); + + SCI_REGU_REG(vddsd, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(1), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(1), + ANA_REG_GLB_LDO_CAL_CTRL3, BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_LDO_CAL_SEL, BIT(11)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 2800, ANA_REG_GLB_LDO_V_CTRL1, BIT(2)|BIT(3), 4, 2800, 3000, 2500, 1800); + + SCI_REGU_REG(vddsim0, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(2), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(2), + ANA_REG_GLB_LDO_CAL_CTRL4, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(9)|BIT(16)|BIT(18)|BIT(20), + 1800, ANA_REG_GLB_LDO_V_CTRL1, BIT(4)|BIT(5), 4, 1800, 2900, 3000, 3100); + + SCI_REGU_REG(vddsim1, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(3), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(3), + ANA_REG_GLB_LDO_CAL_CTRL4, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(9)|BIT(16)|BIT(18)|BIT(20), + 1800, ANA_REG_GLB_LDO_V_CTRL1, BIT(6)|BIT(7), 4, 1800, 2900, 3000, 3100); + + SCI_REGU_REG(vddsim2, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(4), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(4), + ANA_REG_GLB_LDO_CAL_CTRL4, BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_LDO_CAL_SEL, BIT(8)|BIT(9)|BIT(16)|BIT(18)|BIT(20), + 1800, ANA_REG_GLB_LDO_V_CTRL1, BIT(8)|BIT(9), 4, 2800, 3000, 2500, 1800); + + SCI_REGU_REG(vddcama, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(5), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(5), + ANA_REG_GLB_LDO_CAL_CTRL4, BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_CAL_SEL, BIT(12)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 2800, ANA_REG_GLB_LDO_V_CTRL2, BIT(0)|BIT(1), 4, 2800, 3000, 2500, 1800); + + SCI_REGU_REG(vddcamd, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(6), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(6), + ANA_REG_GLB_LDO_CAL_CTRL5, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(5)|BIT(6)|BIT(17)|BIT(18)|BIT(20), + 1500, ANA_REG_GLB_LDO_V_CTRL2, BIT(2)|BIT(3), 4, 1500, 1800, 1300, 1200); + +#ifdef CONFIG_REGULATOR_SUPPORT_CAMIO_1200MV + SCI_REGU_REG(vddcamio, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(7), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(7), + ANA_REG_GLB_LDO_CAL_CTRL5, BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_LDO_CAL_SEL, BIT(5)|BIT(17)|BIT(18)|BIT(20), + 1200, ANA_REG_GLB_LDO_V_CTRL2, BIT(4)|BIT(5), 4, 1100, 1200, 1300, 1600); +#else + SCI_REGU_REG(vddcamio, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(7), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(7), + ANA_REG_GLB_LDO_CAL_CTRL5, BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_LDO_CAL_SEL, BIT(5)|BIT(17)|BIT(18)|BIT(20), + 1800, ANA_REG_GLB_LDO_V_CTRL2, BIT(4)|BIT(5), 4, 1500, 1800, 2500, 2800); +#endif + + SCI_REGU_REG(vddcammot, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(8), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(8), + ANA_REG_GLB_LDO_CAL_CTRL5, BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_CAL_SEL, BIT(12)|BIT(13)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 2800, ANA_REG_GLB_LDO_V_CTRL2, BIT(6)|BIT(7), 4, 3000, 3300, 2800, 1800); + + SCI_REGU_REG(vddusb, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(9), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(9), + ANA_REG_GLB_LDO_CAL_CTRL2, BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_CAL_SEL, BIT(8)|BIT(9)|BIT(10)|BIT(16)|BIT(18)|BIT(20), + 3300, ANA_REG_GLB_LDO_V_CTRL2, BIT(8)|BIT(9), 4, 3300, 3400, 3200, 3100); + + SCI_REGU_REG(vddclsg, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(10), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(10), + ANA_REG_GLB_LDO_CAL_CTRL6, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(6)|BIT(17)|BIT(18)|BIT(20), + 0, ANA_REG_GLB_LDO_V_CTRL2, BIT(10)|BIT(11), 4, 1500, 1800, 1300, 1200); + + SCI_REGU_REG(chg_pump, 0, ANA_REG_GLB_CHGR_CTRL2, BIT(8), 0, 0, 0, 0, + ANA_REG_GLB_CHGR_CTRL2, BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13), 0, 0, + 5000, ANA_REG_GLB_CHGR_CTRL0, BIT(2)|BIT(3), 4, 5000, 5200, 5300, 4800); + + SCI_REGU_REG(led_flash, 4, 0, 0, ANA_REG_GLB_FLASH_CTRL, BIT(15), 0, 0, + ANA_REG_GLB_FLASH_CTRL, BIT(4)|BIT(5)|BIT(6), 0, 0, + 4000, ANA_REG_GLB_FLASH_CTRL, BIT(0)|BIT(1)|BIT(2)|BIT(3), 0); + diff --git a/include/soc/sprd/chip_x30g/dram_phy_28nm.h b/include/soc/sprd/chip_x30g/dram_phy_28nm.h new file mode 100644 index 00000000..8fce6e9f --- /dev/null +++ b/include/soc/sprd/chip_x30g/dram_phy_28nm.h @@ -0,0 +1,487 @@ +#ifndef _DRAM_PHY_28NM_H_ +#define _DRAM_PHY_28NM_H_ + +#define __LPDDR2_BL__ 8 /*4,8,16*/ + +#define NS2CLK_T(ns,clk) (((clk)*(ns)+9999)/10000) +#define MAX(x,y) (((x) > (y)) ? (x) : (y)) + +#ifndef BIT +#define BIT(x) (1 << (x)) +#endif + +typedef enum +{ + /*lpddr1 type*/ + DRAM_LPDDR1 = 0x000, + /*lpddr2 type*/ + DRAM_LPDDR2 = 0x100, + /*lpddr3 type*/ + DRAM_LPDDR3 = 0x200, + /*ddr2 type*/ + DRAM_DDR2 = 0x300, + /*ddr3 type*/ + DRAM_DDR3 = 0x400, +}DRAM_TYPE_E; + +typedef enum{ + CLK_24MHZ = 24, + CLK_26MHZ = 26, + CLK_38_4MHZ = 38, + CLK_48MHZ = 48, + CLK_64MHZ = 64, + CLK_76_8MHZ = 77, + CLK_96MHZ = 96, + CLK_100MHZ = 100, + CLK_153_6MHZ = 154, + CLK_150MHZ = 150, + CLK_166MHZ = 166, + CLK_192MHZ = 192, + CLK_200MHZ = 200, + CLK_250MHZ = 250, + CLK_267MHZ = 267, + CLK_300MHZ = 300, + CLK_332MHZ = 332, + CLK_333MHZ = 333, + CLK_384MHZ = 384, + CLK_400MHZ = 400, + CLK_427MHZ = 427, + CLK_450MHZ = 450, + CLK_464MHZ = 464, + CLK_466MHZ = 466, + CLK_467MHZ = 467, + CLK_500MHZ = 500, + CLK_525MHZ = 525, + CLK_533MHZ = 533, + CLK_537MHZ = 537, + CLK_540MHZ = 540, + CLK_550MHZ = 550, + CLK_800MHZ = 800, + CLK_1000MHZ = 1000, + EMC_CLK_400MHZ = 400, + EMC_CLK_450MHZ = 450, + EMC_CLK_500MHZ = 500 +}CLK_TYPE_E; + +typedef enum +{ + CAP_1CS_2G_X32, + CAP_1CS_4G_X32, + CAP_2CS_2G_X32, + CAP_2CS_3G_X32, + CAP_2CS_4G_X32, + CAP_2CS_5G_X32, + CAP_2CS_6G_X32, + CAP_2CS_8G_X32, + CAP_2CS_12G_X32, + CAP_2CS_16G_X32, + CAP_1CS_2G_X8_4P, + CAP_1CS_4G_X16_2P +}DRAM_CAP_SIZE_E; + +typedef enum +{ + DRAM_BT_SEQ = 0, //burst type = sequential(default) + DRAM_BT_INTER= 1 //burst type = interleaved +}DRAM_BURSTTYPE_E; + +typedef enum +{ + DRAM_WRAP = 0, //warp mode + DRAM_NOWRAP = 1 //no warp mode +}DRAM_WC_E; + +typedef enum +{ +/*Driver strength for lpddr1*/ + LPDDR1_DS_FULL, + LPDDR1_DS_HALF, + LPDDR1_DS_QUARTER, + LPDDR1_DS_OCTANT, + LPDDR1_DS_THREE_QUATERS, +/*Driver strength for lpddr2*/ + LPDDR2_DS_34R3 = 0x01, + LPDDR2_DS_40R = 0x02, + LPDDR2_DS_48R = 0x03, + LPDDR2_DS_60R = 0x04, + LPDDR2_DS_68R6 = 0x05, + LPDDR2_DS_80R = 0x06, + LPDDR2_DS_120R = 0x07, +/*Driver strength for ddr3*/ + DDR3_DS_40R = 0x00, + DDR3_DS_34R3 = 0x01 +}MEM_IODS_E; + +typedef enum +{ + UMCTL2_PORT_MIN = 0, + UMCTL2_PORT_AP = 0, + UMCTL2_PORT_MM = 1, + UMCTL2_PORT_GPU = 2, + UMCTL2_PORT_CP2_P0 = 3, + UMCTL2_PORT_CP1 = 4, + UMCTL2_PORT_AP_MTX = 5, + UMCTL2_PORT_CP0 = 6, + UMCTL2_PORT_CP2_P1 = 7, + UMCTL2_PORT_CP0_MTX = 8, + UMCTL2_PORT_DSP = 9, + UMCTL2_PORT_MAX = 10 +}UMCTL2_PORT_ID_E; + +typedef enum +{ + OPERATION_MODE_INIT = 0x0, + OPERATION_MODE_NORMAL = 0x1, + OPERATION_MODE_PD = 0x2, + OPERATION_MODE_SR = 0x3, + OPERATION_MODE_DPD = 0x4 +}OPERATION_MODE_E; + +typedef struct +{ + unsigned int tREFI; /*average refresh interval time between each row normal=7800ns*/ + unsigned int tMRD; /*lpddr1:set lpddr2:sbz ddr3:set*/ + unsigned int tRAS; /*lpddr1:set lpddr2:set ddr3:set*/ + unsigned int tRC; /*lpddr1:set lpddr2:set ddr3:set*/ + unsigned int tRFC; /*lpddr1:set lpddr2:set ddr3:set*/ + unsigned int tRCD; /*lpddr1:set lpddr2:set ddr3:set*/ + unsigned int tRP; /*lpddr1:set lpddr2:set ddr3:set*/ + unsigned int tRRD; /*lpddr1:set lpddr2:set ddr3:set*/ + unsigned int tWR; /*lpddr1:set lpddr2:set ddr3:set*/ + unsigned int tWTR; /*lpddr1:set lpddr2:set ddr3:set*/ + unsigned int tXSR; /*lpddr1:set lpddr2:set ddr3:sbz*/ + unsigned int tXP; /*lpddr1:set lpddr2:set ddr3:set*/ + unsigned int tCKE; /*lpddr1:set lpddr2:set ddr3:set*/ + unsigned int tRFCab; /*lpddr1:sbz lpddr2:set ddr3:sbz*/ + unsigned int tRFCpb; /*lpddr1:sbz lpddr2:set ddr3:sbz*/ + unsigned int tZQINIT; /*lpddr1:sbz lpddr2:set ddr3:set*/ + unsigned int tZQCL; /*lpddr1:sbz lpddr2:set ddr3:sbz*/ + unsigned int tZQCS; /*lpddr1:sbz lpddr2:set ddr3:set*/ + unsigned int tZQreset; /*lpddr1:sbz lpddr2:set ddr3:sbz*/ + unsigned int tZQoper; /*lpddr1:sbz lpddr2:sbz ddr3:set*/ + unsigned int tCKESR; /*lpddr1:sbz lpddr2:set ddr3:sbz*/ + unsigned int tCCD; /*lpddr1:sbz lpddr2:set ddr3:set*/ + unsigned int tRTP; /*lpddr1:sbz lpddr2:set ddr3:set*/ + unsigned int tFAW; /*lpddr1:sbz lpddr2:set ddr3:set*/ + unsigned int tDPD; /*lpddr1:sbz lpddr2:set ddr3:sbz*/ + unsigned int tDQSCK; /*lpddr1:sbz lpddr2:set ddr3:set*/ + unsigned int tDQSCKmax; /*lpddr1:sbz lpddr2:set ddr3:sbz*/ + unsigned int tMRW; /*lpddr1:sbz lpddr2:set ddr3:sbz*/ + unsigned int tMRR; /*lpddr1:sbz lpddr2:set ddr3:sbz*/ + unsigned int tDLLK; /*lpddr1:sbz lpddr2:sbz ddr3:set*/ + unsigned int tMOD; /*lpddr1:sbz lpddr2:sbz ddr3:set*/ + unsigned int tXS; /*lpddr1:sbz lpddr2:sbz ddr3:set*/ + unsigned int tCKSRE; /*lpddr1:sbz lpddr2:sbz ddr3:set*/ + unsigned int tCKSRX; /*lpddr1:sbz lpddr2:sbz ddr3:set*/ + unsigned int cntRDMode; + unsigned int cntRDDLY; + unsigned int cntDQSGX; + unsigned int cntPGWAIT; + unsigned int cntZQDIV; +}DDR_ACTIMING_T; + +typedef struct +{ + DRAM_TYPE_E dram_type; + DRAM_CAP_SIZE_E cap; + unsigned int cs_num; /*ranks number*/ + unsigned int bank_num; /*banks number*/ + unsigned int io_width; /*bus width*/ + unsigned int bt; /*burst type*/ + unsigned int wc; /*wrap control*/ + unsigned int bl; /*burst length*/ + unsigned int rl; /*read cas latency*/ + unsigned int wl; /*write cas latency*/ + unsigned int al; /*ddr2 ddr3 only Posted CAS additive latency*/ + DDR_ACTIMING_T *ac_timing; + DDR_ACTIMING_T *native_ac_timing; +}DRAM_INFO_T; + +typedef struct +{ + volatile unsigned int umctl_mstr; /* 0x0000 master register*/ + volatile unsigned int umctl_stat; /* 0x0004 operating mode status*/ + volatile unsigned int umctl_resv0[2]; /* 0x0008 ~ 0x000c*/ + volatile unsigned int umctl_mrctrl[2]; /* 0x0010 ~ 0x0014 mode register control*/ + volatile unsigned int umctl_mrstat; /* 0x0018 mode register status*/ + volatile unsigned int umctl_resv1; /* 0x001c */ + volatile unsigned int umctl_derateen; /* 0x0020 temperature derate enable*/ + volatile unsigned int umctl_derateint; /* 0x0024 temperature derate interval*/ + volatile unsigned int umctl_resv2[2]; /* 0x0028 ~ 0x002c */ + volatile unsigned int umctl_pwrctl; /* 0x0030 low power control*/ + volatile unsigned int umctl_pwrtmg; /* 0x0034 low power timing*/ + volatile unsigned int umctl_hwlpctl; /* 0x0038 hardware low power control*/ + volatile unsigned int umctl_resv3[5]; /* 0x003c ~ 0x004c */ + volatile unsigned int umctl_rfshctl[3]; /* 0x0050 ~ 0x0058 refresh control*/ + volatile unsigned int umctl_resv4; /* 0x005c */ + volatile unsigned int umctl_rfshctl3; /* 0x0060 refresh control*/ + volatile unsigned int umctl_rfshtmg; /* 0x0064 refresh timing*/ + volatile unsigned int umctl_resv5[2]; /* 0x0068 ~ 0x006c */ + volatile unsigned int umctl_ecccfg[2]; /* 0x0070 ~ 0x0074 ecc configruation*/ + volatile unsigned int umctl_eccstat; /* 0x0078 ecc status*/ + volatile unsigned int umctl_eccclr; /* 0x007c ecc clear*/ + volatile unsigned int umctl_eccerrcnt; /* 0x0080 ecc error count*/ + volatile unsigned int umctl_ecccaddr[2];/* 0x0084 ~ 0x0088 ecc corrected error address*/ + volatile unsigned int umctl_ecccsyn[3]; /* 0x008c ~ 0x0094 ecc corrected syndrome*/ + volatile unsigned int umctl_eccbitmask[3]; /* 0x0098 ~ 0x00a0 ecc corrected data bit mask*/ + volatile unsigned int umctl_eccuaddr[2];/* 0x00a4 ~ 0x00a8 ecc unorrected error address*/ + volatile unsigned int umctl_eccusyn[3]; /* 0x00ac ~ 0x00b4 ecc uncorrected syndrome*/ + volatile unsigned int umctl_eccpoisonaddr[2]; /* 0x00b8 ~ 0x00bc ecc data poisoning address*/ + volatile unsigned int umctl_parctl; /* 0x00c0 parity control*/ + volatile unsigned int umctl_parstat; /* 0x00c4 parity status*/ + volatile unsigned int umctl_resv6[2]; /* 0x00c8 ~ 0x00cc */ + volatile unsigned int umctl_init[8]; /* 0x00d0 ~ 0x00ec sdram initialization*/ + volatile unsigned int umctl_dimmctl; /* 0x00f0 dimm control*/ + volatile unsigned int umctl_rankctl; /* 0x00f4 rank control*/ + volatile unsigned int umctl_resv7[2]; /* 0x00f8 ~ 0x00fc*/ + volatile unsigned int umctl_dramtmg[12];/* 0x0100 ~ 0x012c sdram timing*/ + volatile unsigned int umctl_resv8[20]; /* 0x0130 ~ 0x017c */ + volatile unsigned int umctl_zqctl[3]; /* 0x0180 ~ 0x0188 zq control*/ + volatile unsigned int umctl_zqstat; /* 0x018c zq status*/ + volatile unsigned int umctl_dfitmg[2]; /* 0x0190 ~ 0x0194 dfi timing*/ + volatile unsigned int umctl_dfilpcfg[2];/* 0x0198 ~ 0x019c dfi low power configruation*/ + volatile unsigned int umctl_dfiupd[4]; /* 0x01a0 ~ 0x01ac dfi update*/ + volatile unsigned int umctl_dfimisc; /* 0x01b0 dfi miscellaneous control*/ + volatile unsigned int umctl_resv9[3]; /* 0x01b4 ~ 0x01bc */ + volatile unsigned int umctl_dbictl; /* 0x01c0 dm/dbi control*/ + volatile unsigned int umctl_resv10[3]; /* 0x01c4 ~ 0x01cc */ + volatile unsigned int umctl_trainctl[3];/* 0x01d0 ~ 0x01d8 phy eval training control*/ + volatile unsigned int umctl_trainstat; /* 0x01dc phy eval training status */ + volatile unsigned int umctl_resv11[8]; /* 0x01e0 ~ 0x01fc */ + volatile unsigned int umctl_addrmap[9]; /* 0x0200 ~ 0x0220 address map */ + volatile unsigned int umctl_resv12[7]; /* 0x0224 ~ 0x023c */ + volatile unsigned int umctl_odtcfg; /* 0x0240 odt configruation */ + volatile unsigned int umctl_odtmap; /* 0x0244 odt/rank map */ + volatile unsigned int umctl_resv13[2]; /* 0x0248 ~ 0x024c */ + volatile unsigned int umctl_sched; /* 0x0250 scheduler control */ + volatile unsigned int umctl_resv14; /* 0x0254 */ + volatile unsigned int umctl_perfhpr[2]; /* 0x0258 ~ 0x025c high priority read*/ + volatile unsigned int umctl_perflpr[2]; /* 0x0260 ~ 0x0264 low priority read */ + volatile unsigned int umctl_perfwr[2]; /* 0x0268 ~ 0x026c write cam */ + volatile unsigned int umctl_resv15[36]; /* 0x0270 ~ 0x02fc */ + volatile unsigned int umctl_dbg[2]; /* 0x0300 ~ 0x0304 debug*/ + volatile unsigned int umctl_dbgcam; /* 0x0308 cam debug*/ + volatile unsigned int umctl_dbgcmd; /* 0x030c cam debug*/ + volatile unsigned int umctl_dbgstat; /* 0x0310 cam debug*/ + volatile unsigned int umctl_resv16[58]; /* 0x0314 ~ 0x03f8 */ + volatile unsigned int umctl_pstat; /* 0x03fc */ + volatile unsigned int umctl_pccfg; /* 0x0400 port common configruation*/ + volatile unsigned int umctl_pcfgr0; /* 0x0404 port 0 configruation read */ + volatile unsigned int umctl_pcfgw0; /* 0x0408 port 0 configruation write*/ + volatile unsigned int umctl_pcfgc0; /* 0x040c port 0 common configruation*/ + volatile unsigned int umctl_pcfgidmaskch0_0; /* 0x0410 channel 0 port 0 configruation*/ + volatile unsigned int umctl_pcfgidvaluech0_0; /* 0x0414 channel 0 port 0 configruation*/ + volatile unsigned int umctl_resv17[30]; /* 0x0418 ~ 0x048c */ + volatile unsigned int umctl_pctrl0; /* 0x0490 port control */ +}DMC_UMCTL_REG_INFO_T,*DMC_UMCTL_REG_INFO_PTR_T; + +/* UMCTL STAT [0x0004] */ +#define BIT_STAT_SELFREF_TYPE ( BIT(5) | BIT(4) ) +#define BIT_STAT_OP_MODE ( BIT(2) | BIT(1) | BIT(0) ) + +/* UMCTL low power control [0x0030] */ +#define BIT_PWRCTL_SELFREF_SW ( BIT(5) ) +#define BIT_PWRCTL_MPSM_EN ( BIT(4) ) +#define BIT_PWRCTL_DFICLK_DIS ( BIT(3) ) +#define BIT_PWRCTL_DEEPPD_EN ( BIT(2) ) +#define BIT_PWRCTL_PD_EN ( BIT(1) ) +#define BIT_PWRCTL_SELFREF_EN ( BIT(0) ) + +/* UMCTL DBG1 */ +#define BIT_DBG1_DIS_DQ ( BIT(0) ) + +/* UMCTL DBGCAM [0x0308] */ +#define BIT_DBGCAM_WR_PP_EPTY ( BIT(29) ) +#define BIT_DBGCAM_RD_PP_EPTY ( BIT(28) ) +#define BIT_DBGCAM_WR_Q_EPTY ( BIT(26) ) +#define BIT_DBGCAM_RD_Q_EPTY ( BIT(25) ) +#define BIT_DBGCAM_STALL ( BIT(24) ) + +/* DFI_MISC */ +#define BIT_DFIMISC_PHY_DBI_MODE ( BIT(1) ) +#define BIT_DFIMISC_DFI_COMP_EN ( BIT(0) ) + +/* RFSHCTL3 [0x0060] */ +#define BIT_RFSHCTL3_RF_MODE ( BIT(6) | BIT(5) | BIT(4) ) +#define BIT_RFSHCTL3_RF_LL ( BIT(1) ) +#define BIT_RFSHCTL3_DIS_AUTO_RF ( BIT(0) ) + +typedef struct +{ + volatile unsigned int publ_ridr; /* 0x0000 revision identification*/ + volatile unsigned int publ_pir; /* 0x0004 phy initialization*/ + volatile unsigned int publ_pgcr[4]; /* 0x0008 ~ 0x0014 phy general configruation*/ + volatile unsigned int publ_pgsr[2]; /* 0x0018 ~ 0x001c phy general status*/ + volatile unsigned int publ_pllcr; /* 0x0020 pll control*/ + volatile unsigned int publ_ptr[5]; /* 0x0024 ~ 0x0034 phy timing*/ + volatile unsigned int publ_acmdlr; /* 0x0038 ac master delay line*/ + volatile unsigned int publ_aclcdlr; /* 0x003c ac local calibrated delay line*/ + volatile unsigned int publ_acbdlr[10]; /* 0x0040 ~ 0x0064 ac bit delay line*/ + volatile unsigned int publ_aciocr[6]; /* 0x0068 ~ 0x007c ac i/o configruation*/ + volatile unsigned int publ_dxccr; /* 0x0080 datx8 common configruation*/ + volatile unsigned int publ_dsgcr; /* 0x0084 datx8 system general configruation*/ + volatile unsigned int publ_dcr; /* 0x0088 dram configruation*/ + volatile unsigned int publ_dtpr[4]; /* 0x008c ~ 0x0098 dram timing parameters*/ + volatile unsigned int publ_mr[4]; /* 0x009c ~ 0x00a8 mode register*/ + volatile unsigned int publ_odtcr; /* 0x00ac odt configruation*/ + volatile unsigned int publ_dtcr; /* 0x00b0 data training configruation*/ + volatile unsigned int publ_dtar[4]; /* 0x00b4 ~ 0x00c0 data training address*/ + volatile unsigned int publ_dtdr[2]; /* 0x00c4 ~ 0x00c8 data training data*/ + volatile unsigned int publ_dtedr[2]; /* 0x00cc ~ 0x00d0 data training address */ + volatile unsigned int publ_rdimmgcr[2]; /* 0x00d4 ~ 0x00d8 rdimm general configruation*/ + volatile unsigned int publ_rdimmcr[2]; /* 0x00dc ~ 0x00e0 rdimm control*/ + volatile unsigned int publ_gpr[2]; /* 0x00e4 ~ 0x00e8 general purpose*/ + volatile unsigned int publ_catr[2]; /* 0x00ec ~ 0x00f0 catr*/ + volatile unsigned int publ_dqsdr; /* 0x00f4 dqs drift detection */ + volatile unsigned int publ_dtmr[2]; /* 0x00f8 ~ 0x00fc data training mask*/ + volatile unsigned int publ_resv0[32]; /* 0x0100 ~ 0x017c */ + volatile unsigned int publ_dcuar; /* 0x0180 DCU address*/ + volatile unsigned int publ_dcudr; /* 0x0184 DCU data*/ + volatile unsigned int publ_dcurr; /* 0x0188 DCU run*/ + volatile unsigned int publ_dculr; /* 0x018c DCU loop*/ + volatile unsigned int publ_dcugcr; /* 0x0190 DCU general configruation*/ + volatile unsigned int publ_dcutpr; /* 0x0194 DCU timing parameters*/ + volatile unsigned int publ_dcusr[2]; /* 0x0198 ~ 0x019c DCU status*/ + volatile unsigned int publ_resv1[8]; /* 0x01a0 ~ 0x01bc */ + volatile unsigned int publ_bistrr; /* 0x01c0 BIST run*/ + volatile unsigned int publ_bistwcr; /* 0x01c4 BIST word count*/ + volatile unsigned int publ_bistmskr[3]; /* 0x01c8 ~ 0x01d0 BIST mask*/ + volatile unsigned int publ_bistlsr; /* 0x01d4 BIST LFSR seed*/ + volatile unsigned int publ_bistar[3]; /* 0x01d8 ~ 0x01e0 BIST address*/ + volatile unsigned int publ_bistudpr; /* 0x01e4 BIST User data pattern*/ + volatile unsigned int publ_bistgsr; /* 0x01e8 BIST general status*/ + volatile unsigned int publ_bistwer; /* 0x01ec BIST word error*/ + volatile unsigned int publ_bistber[4]; /* 0x01f0 ~ 0x01fc BIST bit error*/ + volatile unsigned int publ_bistwcsr; /* 0x0200 BIST word count status*/ + volatile unsigned int publ_bistfwr[3]; /* 0x0204 ~ 0x020c BIST fail word*/ + volatile unsigned int publ_resv2[10]; /* 0x0210 ~ 0x0234 catr*/ + volatile unsigned int publ_iovcr[2]; /* 0x0238 ~ 0x023c IO VREF control*/ + volatile unsigned int publ_zqcr; /* 0x0240 zq impedance control*/ + volatile unsigned int publ_zq0pr; /* 0x0244 zq impedance program*/ + volatile unsigned int publ_zq0dr; /* 0x0248 zq impedance data*/ + volatile unsigned int publ_zq0sr; /* 0x024c zq impedance status*/ + volatile unsigned int publ_resv3; /* 0x0250 */ + volatile unsigned int publ_zq1pr; /* 0x0254 zq impedance program*/ + volatile unsigned int publ_zq1dr; /* 0x0258 zq impedance data*/ + volatile unsigned int publ_zq1sr; /* 0x025c zq impedance status*/ + volatile unsigned int publ_resv4; /* 0x0260 */ + volatile unsigned int publ_zq2pr; /* 0x0264 zq impedance program*/ + volatile unsigned int publ_zq2dr; /* 0x0268 zq impedance data*/ + volatile unsigned int publ_zq2sr; /* 0x026c zq impedance status*/ + volatile unsigned int publ_resv5; /* 0x0270 */ + volatile unsigned int publ_zq3pr; /* 0x0274 zq impedance program*/ + volatile unsigned int publ_zq3dr; /* 0x0278 zq impedance data*/ + volatile unsigned int publ_zq3sr; /* 0x027c zq impedance status*/ + volatile unsigned int publ_dx0gcr[4]; /* 0x0280 ~ 0x028c datx8 general config*/ + volatile unsigned int publ_dx0gsr[3]; /* 0x0290 ~ 0x0298 datx8 general status*/ + volatile unsigned int publ_dx0bdlr[7]; /* 0x029c ~ 0x02b4 datx8 bit delay line*/ + volatile unsigned int publ_dx0lcdlr[3]; /* 0x02b8 ~ 0x02c0 datx8 local cal*/ + volatile unsigned int publ_dx0mdlr; /* 0x02c4 datx8 master delay line*/ + volatile unsigned int publ_dx0gtr; /* 0x02c8 datx8 general timing*/ + volatile unsigned int publ_resv6[13]; /* 0x02cc ~ 0x02fc */ + volatile unsigned int publ_dx1gcr[4]; /* 0x0300 ~ 0x030c datx8 general config*/ + volatile unsigned int publ_dx1gsr[3]; /* 0x0310 ~ 0x0318 datx8 general status*/ + volatile unsigned int publ_dx1bdlr[7]; /* 0x031c ~ 0x0334 datx8 bit delay line*/ + volatile unsigned int publ_dx1lcdlr[3]; /* 0x0338 ~ 0x0340 datx8 local cal*/ + volatile unsigned int publ_dx1mdlr; /* 0x0344 datx8 master delay line*/ + volatile unsigned int publ_dx1gtr; /* 0x0348 datx8 general timing*/ + volatile unsigned int publ_resv7[13]; /* 0x034c ~ 0x037c */ + volatile unsigned int publ_dx2gcr[4]; /* 0x0380 ~ 0x038c datx8 general config*/ + volatile unsigned int publ_dx2gsr[3]; /* 0x0390 ~ 0x0398 datx8 general status*/ + volatile unsigned int publ_dx2bdlr[7]; /* 0x039c ~ 0x03b4 datx8 bit delay line*/ + volatile unsigned int publ_dx2lcdlr[3]; /* 0x03b8 ~ 0x03c0 datx8 local cal*/ + volatile unsigned int publ_dx2mdlr; /* 0x03c4 datx8 master delay line*/ + volatile unsigned int publ_dx2gtr; /* 0x03c8 datx8 general timing*/ + volatile unsigned int publ_resv8[13]; /* 0x03cc ~ 0x03fc */ + volatile unsigned int publ_dx3gcr[4]; /* 0x0400 ~ 0x040c datx8 general config*/ + volatile unsigned int publ_dx3gsr[3]; /* 0x0410 ~ 0x0418 datx8 general status*/ + volatile unsigned int publ_dx3bdlr[7]; /* 0x041c ~ 0x0434 datx8 bit delay line*/ + volatile unsigned int publ_dx3lcdlr[3]; /* 0x0438 ~ 0x0440 datx8 local cal*/ + volatile unsigned int publ_dx3mdlr; /* 0x0444 datx8 master delay line*/ + volatile unsigned int publ_dx3gtr; /* 0x0448 datx8 general timing*/ + volatile unsigned int publ_resv9[13]; /* 0x044c ~ 0x047c */ + volatile unsigned int publ_dx4gcr[4]; /* 0x0480 ~ 0x048c datx8 general config*/ + volatile unsigned int publ_dx4gsr[3]; /* 0x0490 ~ 0x0498 datx8 general status*/ + volatile unsigned int publ_dx4bdlr[7]; /* 0x049c ~ 0x04b4 datx8 bit delay line*/ + volatile unsigned int publ_dx4lcdlr[3]; /* 0x04b8 ~ 0x04c0 datx8 local cal*/ + volatile unsigned int publ_dx4mdlr; /* 0x04c4 datx8 master delay line*/ + volatile unsigned int publ_dx4gtr; /* 0x04c8 datx8 general timing*/ + volatile unsigned int publ_resv10[13]; /* 0x04cc ~ 0x04fc */ + volatile unsigned int publ_dx5gcr[4]; /* 0x0500 ~ 0x050c datx8 general config*/ + volatile unsigned int publ_dx5gsr[3]; /* 0x0510 ~ 0x0518 datx8 general status*/ + volatile unsigned int publ_dx5bdlr[7]; /* 0x051c ~ 0x0534 datx8 bit delay line*/ + volatile unsigned int publ_dx5lcdlr[3]; /* 0x0538 ~ 0x0540 datx8 local cal*/ + volatile unsigned int publ_dx5mdlr; /* 0x0544 datx8 master delay line*/ + volatile unsigned int publ_dx5gtr; /* 0x0548 datx8 general timing*/ + volatile unsigned int publ_resv11[13]; /* 0x054c ~ 0x057c */ + volatile unsigned int publ_dx6gcr[4]; /* 0x0580 ~ 0x058c datx8 general config*/ + volatile unsigned int publ_dx6gsr[3]; /* 0x0590 ~ 0x0598 datx8 general status*/ + volatile unsigned int publ_dx6bdlr[7]; /* 0x059c ~ 0x05b4 datx8 bit delay line*/ + volatile unsigned int publ_dx6lcdlr[3]; /* 0x05b8 ~ 0x05c0 datx8 local cal*/ + volatile unsigned int publ_dx6mdlr; /* 0x05c4 datx8 master delay line*/ + volatile unsigned int publ_dx6gtr; /* 0x05c8 datx8 general timing*/ + volatile unsigned int publ_resv12[13]; /* 0x05cc ~ 0x05fc */ + volatile unsigned int publ_dx7gcr[4]; /* 0x0600 ~ 0x060c datx8 general config*/ + volatile unsigned int publ_dx7gsr[3]; /* 0x0610 ~ 0x0618 datx8 general status*/ + volatile unsigned int publ_dx7bdlr[7]; /* 0x061c ~ 0x0634 datx8 bit delay line*/ + volatile unsigned int publ_dx7lcdlr[3]; /* 0x0638 ~ 0x0640 datx8 local cal*/ + volatile unsigned int publ_dx7mdlr; /* 0x0644 datx8 master delay line*/ + volatile unsigned int publ_dx7gtr; /* 0x0648 datx8 general timing*/ + volatile unsigned int publ_resv13[13]; /* 0x064c ~ 0x067c */ + volatile unsigned int publ_dx8gcr[4]; /* 0x0680 ~ 0x068c datx8 general config*/ + volatile unsigned int publ_dx8gsr[3]; /* 0x0690 ~ 0x0698 datx8 general status*/ + volatile unsigned int publ_dx8bdlr[7]; /* 0x069c ~ 0x06b4 datx8 bit delay line*/ + volatile unsigned int publ_dx8lcdlr[3]; /* 0x06b8 ~ 0x06c0 datx8 local cal*/ + volatile unsigned int publ_dx8mdlr; /* 0x06c4 datx8 master delay line*/ + volatile unsigned int publ_dx8gtr; /* 0x06c8 datx8 general timing*/ + volatile unsigned int publ_resv14[13]; /* 0x06cc ~ 0x06fc */ +}DMC_PUBL_REG_INFO_T,*DMC_PUBL_REG_INFO_PTR_T; + +/* PUBL DSGCR */ +#define BIT_DSGCR_PUREN ( BIT(0) ) +#define BIT_DSGCR_BDISEN ( BIT(1) ) +#define BIT_DSGCR_ZUEN ( BIT(2) ) +#define BIT_DSGCR_LPIOPD ( BIT(3) ) +#define BIT_DSGCR_LPPLLPD ( BIT(4) ) +#define BIT_DSGCR_CUAEN ( BIT(5) ) +#define BIT_DSGCR_DQSGX ( BIT(6) | BIT(7) ) +#define BIT_DSGCR_PUAD ( BIT(8) | BIT(9) | BIT(10) | BIT(11) ) +#define BIT_DSGCR_DTOODT ( BIT(12) ) +#define BIT_DSGCR_DTOPDO ( BIT(13) ) +#define BIT_DSGCR_DTOPDR ( BIT(14) ) +#define BIT_DSGCR_DTOIOM ( BIT(15) ) +#define BIT_DSGCR_DTOOE ( BIT(16) ) +#define BIT_DSGCR_ATOAE ( BIT(17) ) +#define BIT_DSGCR_RPMODE ( BIT(18) ) +#define BIT_DSGCR_SDRMODE ( BIT(19) | BIT(20) ) + +/* PUBL PIR [0x0004] */ +#define BIT_PIR_INIT ( BIT(0) ) +#define BIT_PIR_ZCAL ( BIT(1) ) +#define BIT_PIR_CA ( BIT(2) ) +#define BIT_PIR_PLLINIT ( BIT(4) ) +#define BIT_PIR_DCAL ( BIT(5) ) +#define BIT_PIR_PHYRST ( BIT(6) ) +#define BIT_PIR_DRAMRST ( BIT(7) ) +#define BIT_PIR_DRAMINIT ( BIT(8) ) +#define BIT_PIR_WL ( BIT(9) ) +#define BIT_PIR_QSGATE ( BIT(10) ) +#define BIT_PIR_WLADJ ( BIT(11) ) +#define BIT_PIR_RDDSKW ( BIT(12) ) +#define BIT_PIR_WDDSKW ( BIT(13) ) +#define BIT_PIR_RDEYE ( BIT(14) ) +#define BIT_PIR_WDEYE ( BIT(15) ) +#define BIT_PIR_ICPC ( BIT(16) ) +#define BIT_PIR_PLLBYP ( BIT(17) ) +#define BIT_PIR_CTLDINIT ( BIT(18) ) +#define BIT_PIR_RDIMMINIT ( BIT(19) ) +#define BIT_PIR_CLRSR ( BIT(27) ) +#define BIT_PIR_LOOKBYP ( BIT(28) ) +#define BIT_PIR_DCALBYP ( BIT(29) ) +#define BIT_PIR_ZCALBYP ( BIT(30) ) +#define BIT_PIR_INITBYP ( BIT(31) ) + + +//#define EMC_FREQ_AUTO_TEST + +#endif diff --git a/include/soc/sprd/chip_x35l/__clock_tree.h b/include/soc/sprd/chip_x35l/__clock_tree.h new file mode 100644 index 00000000..3c53b809 --- /dev/null +++ b/include/soc/sprd/chip_x35l/__clock_tree.h @@ -0,0 +1,514 @@ +/* + * Copyright (C) 2013 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +/* + * Clock (0)Name, Clock (1)fixed rate, Clock Enable (2)Ctrl and (3)Bit, + * Clock Divisor (4)Ctrl and (5)Bit, Clock Parent (6)Ctrl and (7)Bit, + * and Parent Select (15)Count and (16)Lists[ ... ...] + */ +SCI_CLK_ADD(ext_26m, 26000000, 0, 0, + 0, 0, 0, 0, 0); + +#if 0 +SCI_CLK_ADD(ext_32k, 32768, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_mpll, 0, REG_PMU_APB_CGM_AP_EN, BIT(6), + REG_AON_APB_MPLL_CFG, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_dpll, 0, REG_PMU_APB_CGM_AP_EN, BIT(1), + REG_AON_APB_DPLL_CFG, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_td_sel_i, 0, REG_PMU_APB_TDPLL_REL_CFG, BIT(0), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_w_sel_i, 0, REG_PMU_APB_WPLL_REL_CFG, BIT(0), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_c_sel_i, 0, REG_PMU_APB_CPLL_REL_CFG, BIT(0), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_wifi_sel_i, 0, REG_PMU_APB_WIFIPLL1_REL_CFG, BIT(0), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_tdpll, 768000000, REG_PMU_APB_CGM_AP_EN, BIT(3), + 0, 0, 0, 0, + 1, &clk_td_sel_i); + +SCI_CLK_ADD(clk_wpll, 921600000, REG_PMU_APB_CGM_AP_EN, BIT(5), + 0, 0, 0, 0, + 1, &clk_w_sel_i); + +SCI_CLK_ADD(clk_cpll, 624000000, REG_PMU_APB_CGM_AP_EN, BIT(2), + 0, 0, 0, 0, + 1, &clk_c_sel_i); + +SCI_CLK_ADD(clk_wifipll, 880000000, REG_PMU_APB_CGM_AP_EN, BIT(4), + 0, 0, 0, 0, + 1, &clk_wifi_sel_i); + +SCI_CLK_ADD(clk_300m, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(0), + 3, 0, 0, 0, + 1, &clk_mpll); + +SCI_CLK_ADD(clk_37m5, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(1), + 24, 0, 0, 0, + 1, &clk_mpll); + +SCI_CLK_ADD(clk_66m_d, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(2), + 8, 0, 0, 0, + 1, &clk_dpll); + +SCI_CLK_ADD(clk_51m2_w, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(23), + 18, 0, 0, 0, + 1, &clk_wpll); + +SCI_CLK_ADD(clk_40m_wf1, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(27), + 22, 0, 0, 0, + 1, &clk_wifipll); + +SCI_CLK_ADD(clk_312m, 0, REG_PMU_APB_CGM_AP_EN, BIT(7), + 2, 0, 0, 0, + 1, &clk_cpll); + +SCI_CLK_ADD(clk_208m, 0, REG_PMU_APB_CGM_AP_EN, BIT(20), + 3, 0, 0, 0, + 1, &clk_cpll); + +SCI_CLK_ADD(clk_104m, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(18), + 6, 0, 0, 0, + 1, &clk_cpll); + +SCI_CLK_ADD(clk_52m, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(19), + 12, 0, 0, 0, + 1, &clk_cpll); + +SCI_CLK_ADD(clk_384m, 0, REG_PMU_APB_CGM_AP_EN, BIT(8), + 2, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_256m, 0, REG_PMU_APB_CGM_AP_EN, BIT(9), + 3, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_192m, 0, REG_PMU_APB_CGM_AP_EN, BIT(10), + 4, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_153m6, 0, REG_PMU_APB_CGM_AP_EN, BIT(11), + 5, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_128m, 0, REG_PMU_APB_CGM_AP_EN, BIT(12), + 6, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_96m, 0, REG_PMU_APB_CGM_AP_EN, BIT(13), + 8, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_76m8, 0, REG_PMU_APB_CGM_AP_EN, BIT(14), + 10, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_64m, 0, REG_PMU_APB_CGM_AP_EN, BIT(15), + 12, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_51m2, 0, REG_PMU_APB_CGM_AP_EN, BIT(16), + 15, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_48m, 0, REG_PMU_APB_CGM_AP_EN, BIT(17), + 16, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_38m4, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(15), + 20, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_24m, 0, REG_PMU_APB_CGM_AP_EN, BIT(18), + 32, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_12m, 0, REG_PMU_APB_CGM_AP_EN, BIT(19), + 64, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_mcu, 0, 0, 0, + REG_AP_AHB_CA7_CKG_CFG, BIT(4)|BIT(5)|BIT(6), REG_AP_AHB_CA7_CKG_CFG, BIT(0)|BIT(1)|BIT(2), + 7, &ext_26m, &clk_dpll, &clk_cpll, &clk_tdpll, &clk_wifipll, &clk_wpll, &clk_mpll); + +SCI_CLK_ADD(clk_ca7_core, 0, 0, 0, + 0, 0, 0, 0, + 1, &clk_mcu); + +SCI_CLK_ADD(clk_ca7_axi, 0, 0, 0, + REG_AP_AHB_CA7_CKG_CFG, BIT(8)|BIT(9)|BIT(10), 0, 0, + 1, &clk_mcu); + +SCI_CLK_ADD(clk_ca7_dbg, 0, REG_AP_AHB_MISC_CKG_EN, BIT(8), + REG_AP_AHB_CA7_CKG_CFG, BIT(16)|BIT(17)|BIT(18), 0, 0, + 1, &clk_mcu); + +SCI_CLK_ADD(clk_ap_ahb, 0, 0, 0, + 0, 0, REG_AP_CLK_AP_AHB_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_76m8, &clk_128m, &clk_192m); + +SCI_CLK_ADD(clk_ap_apb, 0, 0, 0, + 0, 0, REG_AP_CLK_AP_APB_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_64m, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_pub_ahb, 0, 0, 0, + 0, 0, REG_AON_CLK_PUB_AHB_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_emc, 0, 0, 0, + REG_AON_CLK_EMC_CFG, BIT(8)|BIT(9), REG_AON_CLK_EMC_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_256m, &clk_384m, &clk_dpll); + +SCI_CLK_ADD(clk_aon_apb, 0, 0, 0, + REG_AON_CLK_AON_APB_CFG, BIT(8)|BIT(9), REG_AON_CLK_AON_APB_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_76m8, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_zip_emc, 0, REG_AON_APB_APB_EB1, BIT(12), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_disp_emc, 0, REG_AON_APB_APB_EB1, BIT(11), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_gsp, 0, REG_AP_AHB_AHB_EB, BIT(3), + 0, 0, REG_AP_CLK_GSP_CFG, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_96m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_disc0, 0, REG_AP_AHB_AHB_EB, BIT(1), + REG_AP_CLK_DISPC0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_DISPC0_CFG, BIT(0), + 2, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_disc0_dbi, 0, REG_AP_AHB_AHB_EB, BIT(1), + REG_AP_CLK_DISPC0_DBI_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_DISPC0_DBI_CFG, BIT(0)|BIT(1), + 4, &clk_128m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_disc0_dpi, 0, REG_AP_AHB_AHB_EB, BIT(1), + REG_AP_CLK_DISPC0_DPI_CFG, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), REG_AP_CLK_DISPC0_DPI_CFG, BIT(0)|BIT(1), + 4, &clk_128m, &clk_153m6, &clk_192m, &clk_384m); + +SCI_CLK_ADD(clk_disc1, 0, REG_AP_AHB_AHB_EB, BIT(2), + REG_AP_CLK_DISPC1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_DISPC1_CFG, BIT(0), + 2, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_disc1_dbi, 0, REG_AP_AHB_AHB_EB, BIT(2), + REG_AP_CLK_DISPC1_DBI_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_DISPC1_DBI_CFG, BIT(0)|BIT(1), + 4, &clk_128m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_disc1_dpi, 0, REG_AP_AHB_AHB_EB, BIT(2), + REG_AP_CLK_DISPC1_DPI_CFG, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), REG_AP_CLK_DISPC1_DPI_CFG, BIT(0)|BIT(1), + 4, &clk_128m, &clk_153m6, &clk_192m, &clk_384m); + +SCI_CLK_ADD(clk_zipdec_emc, 0, REG_AP_AHB_AHB_EB, BIT(21), + 0, 0, REG_AP_CLK_ZIPENC_CFG, BIT(0)|BIT(1), + 4, &clk_96m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_zipenc_emc, 0, REG_AP_AHB_AHB_EB, BIT(20), + 0, 0, REG_AP_CLK_ZIPENC_CFG, BIT(0)|BIT(1), + 4, &clk_96m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_nandc_ecc, 0, REG_AP_AHB_AHB_EB, BIT(19), + 0, 0, REG_AP_CLK_NANDC_ECC_CFG, BIT(0), + 2, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_nfc, 0, REG_AP_AHB_AHB_EB, BIT(6), + REG_AP_CLK_NFC_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_NFC_CFG, BIT(0)|BIT(1), + 3, &clk_64m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_sdio0, 0, REG_AP_AHB_AHB_EB, BIT(8), + REG_AP_CLK_SDIO0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_SDIO0_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_256m, &clk_312m, &clk_384m); + +SCI_CLK_ADD(clk_sdio1, 0, REG_AP_AHB_AHB_EB, BIT(9), + 0, 0, REG_AP_CLK_SDIO1_CFG, BIT(0)|BIT(1), + 4, &clk_48m, &clk_76m8, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_sdio2, 0, REG_AP_AHB_AHB_EB, BIT(10), + 0, 0, REG_AP_CLK_SDIO2_CFG, BIT(0)|BIT(1), + 4, &clk_48m, &clk_76m8, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_emmc, 0, REG_AP_AHB_AHB_EB, BIT(11), + 0, 0, REG_AP_CLK_EMMC_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_256m, &clk_312m, &clk_384m); + +SCI_CLK_ADD(clk_gps_tcxo, 64000000, REG_AP_CLK_GPS_TCXO_CFG, BIT(16), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_gps, 0, REG_AP_AHB_AHB_EB, BIT(12), + 0, 0, REG_AP_CLK_GPS_CFG, BIT(0), + 2, &clk_64m, &clk_76m8); + +SCI_CLK_ADD(clk_usb_ref, 0, REG_AP_AHB_AHB_EB, BIT(4), + 0, 0, REG_AP_CLK_USB_REF_CFG, BIT(0), + 2, &clk_12m, &clk_24m); + +SCI_CLK_ADD(clk_uart0, 0, REG_AP_APB_APB_EB, BIT(13), + REG_AP_CLK_UART0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_UART0_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart1, 0, REG_AP_APB_APB_EB, BIT(14), + REG_AP_CLK_UART1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_UART1_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart2, 0, REG_AP_APB_APB_EB, BIT(15), + REG_AP_CLK_UART2_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_UART2_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart3, 0, REG_AP_APB_APB_EB, BIT(16), + REG_AP_CLK_UART3_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_UART3_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_i2c0, 0, REG_AP_APB_APB_EB, BIT(8), + REG_AP_CLK_I2C0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_I2C0_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_i2c1, 0, REG_AP_APB_APB_EB, BIT(9), + REG_AP_CLK_I2C1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_I2C1_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_i2c2, 0, REG_AP_APB_APB_EB, BIT(10), + REG_AP_CLK_I2C2_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_I2C2_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_i2c3, 0, REG_AP_APB_APB_EB, BIT(11), + REG_AP_CLK_I2C3_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_I2C3_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_spi0, 0, REG_AP_APB_APB_EB, BIT(5), + REG_AP_CLK_SPI0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_SPI0_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_spi1, 0, REG_AP_APB_APB_EB, BIT(6), + REG_AP_CLK_SPI1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_SPI1_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_spi2, 0, REG_AP_APB_APB_EB, BIT(7), + REG_AP_CLK_SPI2_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_SPI2_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_iis0, 0, REG_AP_APB_APB_EB, BIT(1), + REG_AP_CLK_IIS0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_IIS0_CFG, BIT(0)|BIT(1), + 3, &ext_26m, &clk_76m8, &clk_128m); + +SCI_CLK_ADD(clk_iis1, 0, REG_AP_APB_APB_EB, BIT(2), + REG_AP_CLK_IIS1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_IIS1_CFG, BIT(0)|BIT(1), + 3, &ext_26m, &clk_76m8, &clk_128m); + +SCI_CLK_ADD(clk_gpu_top_i, 0, REG_PMU_APB_PD_GPU_TOP_CFG+1, BIT(25), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_gpu_i, 0, REG_AON_APB_APB_EB0, BIT(27), + 0, 0, 0, 0, + 1, &clk_gpu_top_i); + +SCI_CLK_ADD(clk_gpu, 0, &clk_gpu_i, 0, + REG_GPU_APB_APB_CLK_CTRL, BIT(2)|BIT(3), REG_GPU_APB_APB_CLK_CTRL, BIT(0)|BIT(1), + 4, &clk_208m, &clk_256m, &clk_300m, &clk_312m); + +SCI_CLK_ADD(clk_mm_top_i, 0, REG_PMU_APB_PD_MM_TOP_CFG+1, BIT(25), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_mm_i, 0, REG_AON_APB_APB_EB0, BIT(25), + 0, 0, 0, 0, + 1, &clk_mm_top_i); + +SCI_CLK_ADD(clk_mm_ahb, 0, 0, 0, + 0, 0, REG_MM_CLK_MM_AHB_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_mm_mtx_axi, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(8), + 0, 0, 0, 0, + 1, &clk_mm_i); + +SCI_CLK_ADD(clk_mm_axi, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(7), + 0, 0, 0, 0, + 1, &clk_mm_mtx_axi); + +SCI_CLK_ADD(clk_mmu, 0, REG_MM_AHB_AHB_EB, BIT(7), + 0, 0, 0, 0, + 1, &clk_mm_ahb); +SCI_CLK_ADD(clk_mm_ckg_i, 0, REG_MM_AHB_AHB_EB, BIT(6), + 0, 0, 0, 0, + 1, &clk_mm_i); + +SCI_CLK_ADD(clk_jpg_i, 0, REG_MM_AHB_AHB_EB, BIT(5), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_jpg_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(6), + 0, 0, 0, 0, + 1, &clk_jpg_i); + +SCI_CLK_ADD(clk_jpg, 0, &clk_jpg_ckg_i, 0, + 0, 0, REG_MM_CLK_JPG_CFG, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_vsp_i, 0, REG_MM_AHB_AHB_EB, BIT(3), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_vsp_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(5), + 0, 0, 0, 0, + 1, &clk_vsp_i); + +SCI_CLK_ADD(clk_vsp, 0, &clk_vsp_ckg_i, 0, + 0, 0, REG_MM_CLK_VSP_CFG, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_sensor_i, 0, REG_MM_AHB_AHB_EB, BIT(1), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_sensor_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(2), + 0, 0, 0, 0, + 1, &clk_sensor_i); + +SCI_CLK_ADD(clk_sensor, 0, &clk_sensor_ckg_i, 0, + REG_MM_CLK_SENSOR_CFG, BIT(8)|BIT(9)|BIT(10), REG_MM_CLK_SENSOR_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_76m8, &clk_96m); + +SCI_CLK_ADD(clk_ccir_in, 64000000, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_ccir_i, 0, REG_MM_AHB_AHB_EB, BIT(1), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_ccir, 0, &clk_ccir_i, 0, + 0, 0, REG_MM_CLK_CCIR_CFG, BIT(16), + 2, &clk_24m, &clk_ccir_in); + +SCI_CLK_ADD(clk_dcam_i, 0, REG_MM_AHB_AHB_EB, BIT(0), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_dcam_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(3), + 0, 0, 0, 0, + 1, &clk_dcam_i); + +SCI_CLK_ADD(clk_dcam, 0, &clk_dcam_ckg_i, 0, + 0, 0, REG_MM_CLK_DCAM_CFG, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_csi_i, 0, REG_MM_AHB_AHB_EB, BIT(4), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_csi_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(1), + 0, 0, 0, 0, + 1, &clk_csi_i); + +SCI_CLK_ADD(clk_cphy_cfg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(0), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_dcam_mipi, 0, &clk_cphy_cfg_i, 0, + 0, 0, 0, 0, + 1, &clk_csi_ckg_i); + +SCI_CLK_ADD(clk_aud, 0, REG_AON_APB_APB_EB0, BIT(18), + 0, 0, 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_audif, 0, REG_AON_APB_APB_EB0, BIT(17), + 0, 0, REG_AON_CLK_AUDIF_CFG, BIT(0)|BIT(1), + 3, &ext_26m, &clk_38m4, &clk_51m2); + +SCI_CLK_ADD(clk_vbc, 0, REG_AON_APB_APB_EB0, BIT(19), + 0, 0, 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_fm_in, 64000000, REG_AON_CLK_FM_CFG, BIT(16), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_fm, 0, REG_AON_APB_APB_EB0, BIT(1), + 0, 0, 0, 0, + 1, &clk_fm_in); + +SCI_CLK_ADD(clk_adi, 0, REG_AON_APB_APB_EB0, BIT(16), + 0, 0, REG_AON_CLK_ADI_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_38m4, &clk_51m2, &clk_64m); + +SCI_CLK_ADD(clk_aux0, 0, REG_AON_APB_APB_EB1, BIT(2), + REG_AON_APB_AON_CGM_CFG, BIT(16)|BIT(17)|BIT(18)|BIT(19), REG_AON_APB_AON_CGM_CFG, BIT(0)|BIT(1)|BIT(2)|BIT(3), + 9, &ext_32k, &ext_26m, &ext_26m, &clk_48m, &clk_52m, &clk_51m2_w, &clk_37m5, &clk_40m_wf1, &clk_66m_d); + +SCI_CLK_ADD(clk_aux1, 0, REG_AON_APB_APB_EB1, BIT(3), + REG_AON_APB_AON_CGM_CFG, BIT(20)|BIT(21)|BIT(22)|BIT(23), REG_AON_APB_AON_CGM_CFG, BIT(4)|BIT(5)|BIT(6)|BIT(7), + 9, &ext_32k, &ext_26m, &ext_26m, &clk_48m, &clk_52m, &clk_51m2_w, &clk_37m5, &clk_40m_wf1, &clk_66m_d); + +SCI_CLK_ADD(clk_aux2, 0, REG_AON_APB_APB_EB1, BIT(4), + REG_AON_APB_AON_CGM_CFG, BIT(24)|BIT(25)|BIT(26)|BIT(27), REG_AON_APB_AON_CGM_CFG, BIT(8)|BIT(9)|BIT(10)|BIT(11), + 9, &ext_32k, &ext_26m, &ext_26m, &clk_48m, &clk_52m, &clk_51m2_w, &clk_37m5, &clk_40m_wf1, &clk_66m_d); + +SCI_CLK_ADD(clk_pwm0, 0, REG_AON_APB_APB_EB0, BIT(4), + 0, 0, REG_AON_CLK_PWM0_CFG, BIT(0), + 2, &ext_32k, &ext_26m); + +SCI_CLK_ADD(clk_pwm1, 0, REG_AON_APB_APB_EB0, BIT(5), + 0, 0, REG_AON_CLK_PWM1_CFG, BIT(0), + 2, &ext_32k, &ext_26m); + +SCI_CLK_ADD(clk_pwm2, 0, REG_AON_APB_APB_EB0, BIT(6), + 0, 0, REG_AON_CLK_PWM2_CFG, BIT(0), + 2, &ext_32k, &ext_26m); + +SCI_CLK_ADD(clk_pwm3, 0, REG_AON_APB_APB_EB0, BIT(7), + 0, 0, REG_AON_CLK_PWM3_CFG, BIT(0), + 2, &ext_32k, &ext_26m); + +SCI_CLK_ADD(clk_efuse, 0, REG_AON_APB_APB_EB0, BIT(13), + 0, 0, 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_ca7_dap, 0, REG_AON_APB_APB_EB0, BIT(30), + 0, 0, REG_AON_CLK_CA7_DAP_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_76m8, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_ca7_ts, 0, REG_AON_APB_APB_EB0, BIT(28), + 0, 0, REG_AON_CLK_CA7_TS_CFG, BIT(0)|BIT(1), + 4, &ext_32k, &ext_26m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_mspi, 0, REG_AON_APB_APB_EB0, BIT(23), + 0, 0, REG_AON_CLK_MSPI_CFG, BIT(0)|BIT(1), + 3, &clk_52m, &clk_76m8, &clk_96m); + +SCI_CLK_ADD(clk_i2c, 0, REG_AON_APB_APB_EB0, BIT(31), + 0, 0, REG_AON_CLK_I2C_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_avs0, 0, REG_AON_APB_APB_EB0, BIT(6), + 0, 0, REG_AON_CLK_AVS0_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_avs1, 0, REG_AON_APB_APB_EB0, BIT(7), + 0, 0, REG_AON_CLK_AVS1_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); +#endif diff --git a/include/soc/sprd/chip_x35l/__regs_ada_apb_rf.h b/include/soc/sprd/chip_x35l/__regs_ada_apb_rf.h new file mode 100644 index 00000000..fbe0bd89 --- /dev/null +++ b/include/soc/sprd/chip_x35l/__regs_ada_apb_rf.h @@ -0,0 +1,177 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_ADA_APB_RF_HEADFILE_H__ +#define __H_REGS_ADA_APB_RF_HEADFILE_H__ __FILE__ + +#define REGS_ADA_APB_RF + +/* registers definitions for ADA_APB_RF */ +#define REG_ADA_APB_RF_APB_DAC_CTR0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0000) +#define REG_ADA_APB_RF_APB_DAC_CTR1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0004) +#define REG_ADA_APB_RF_APB_DAC_CTR2 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0008) +#define REG_ADA_APB_RF_APB_DAC_CTR3 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x000C) +#define REG_ADA_APB_RF_APB_DAC_CTR4 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0010) +#define REG_ADA_APB_RF_APB_DAC_STS0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0014) +#define REG_ADA_APB_RF_APB_DAC_STS1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0018) +#define REG_ADA_APB_RF_APB_ADC0_CTR0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x001C) +#define REG_ADA_APB_RF_APB_ADC0_CTR1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0020) +#define REG_ADA_APB_RF_APB_ADC0_CTR2 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0024) +#define REG_ADA_APB_RF_APB_ADC0_CTR3 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0028) +#define REG_ADA_APB_RF_APB_CAL_CTR0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0030) +#define REG_ADA_APB_RF_APB_CAL_CTR1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0034) +#define REG_ADA_APB_RF_APB_CAL_CTR3 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x003C) +#define REG_ADA_APB_RF_APB_CAL_STS0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0044) +#define REG_ADA_APB_RF_APB_CAL_STS1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0048) +#define REG_ADA_APB_RF_APB_ADA_CTRL0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0054) +#define REG_ADA_APB_RF_APB_ADA_CTRL1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0058) +#define REG_ADA_APB_RF_APB_RX_GSM_DFT SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x005C) +#define REG_ADA_APB_RF_APB_RX_3G_DFT SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0060) + + + +/* bits definitions for register REG_ADA_APB_RF_APB_DAC_CTR0 */ +#define BITS_DAC_PCTRL_1(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BIT_DAC_OUT_SEL_1 ( BIT(17) ) +#define BIT_DAC_CLK_SEL_1 ( BIT(16) ) +#define BITS_DAC_PCTRL_0(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_DAC_OUT_SEL_0 ( BIT(1) ) +#define BIT_DAC_CLK_SEL_0 ( BIT(0) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_DAC_CTR1 */ +#define BITS_DAC_WD_OVR(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DAC_WADDR_OVR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DAC_WLE_OVR ( BIT(2) ) +#define BIT_DAC_W_OVR_I_QN ( BIT(1) ) +#define BIT_DAC_W_OVR_EN ( BIT(0) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_DAC_CTR2 */ +#define BITS_DAC_RSV(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BIT_DAC_IQ_OUT_MSB_INV ( BIT(21) ) +#define BIT_DAC_IQ_IN_MSB_INV ( BIT(20) ) +#define BIT_DAC_OVR_EN_CAL ( BIT(19) ) +#define BIT_DAC_EN_OOSCAL ( BIT(18) ) +#define BIT_DAC_IQ_SWAP ( BIT(17) ) +#define BIT_DAC_CAL_START ( BIT(16) ) +#define BITS_DAC_OFFSETI(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DAC_OFFSETQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_DAC_CTR3 */ +#define BITS_DAC_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_DAC_CTR4 */ +#define BITS_DAC_I_CAL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC_Q_CAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_DAC_STS0 */ +#define BITS_DAC_WTI(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DAC_WTQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_DAC_STS1 */ +#define BITS_DAC_DA_STATE(_X_) ( (_X_) << 17 & (BIT(17)|BIT(18)) ) +#define BIT_DAC_DONE ( BIT(16) ) +#define BITS_DAC_WQ_OVR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_ADC0_CTR0 */ +#define BITS_ADC0_CALRDOUT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BIT_ADC0_CAL_SOFT_RST ( BIT(10) ) +#define BIT_ADC0_CALRD ( BIT(9) ) +#define BIT_ADC0_CALEN ( BIT(8) ) +#define BITS_ADC0_CALADDR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_ADC0_CTR1 */ +#define BITS_ADC0_DLL_OUT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_ADC0_DLLOOF(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)) ) +#define BIT_ADC0_IQ_SWAP ( BIT(14) ) +#define BITS_ADC0_DLLIN(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_ADC0_IQ_OUT_MSB_INV ( BIT(7) ) +#define BIT_ADC0_IQ_IN_MSB_INV ( BIT(6) ) +#define BIT_ADC0_DLL_SOFT_RST ( BIT(4) ) +#define BIT_ADC0_DLLWR ( BIT(3) ) +#define BIT_ADC0_DLLRD ( BIT(2) ) +#define BIT_ADC0_DLLEN ( BIT(1) ) +#define BIT_ADC0_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_ADC0_CTR2 */ +#define BITS_ADC0_RSV_0(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ADC0_DIG_CLK_SEL_0 ( BIT(11) ) +#define BIT_ADC0_VCM_SEL_0 ( BIT(10) ) +#define BITS_ADC0_DELAY_CAP_0(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ADC0_BIT_SEL_0(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_ADC0_VREF_SEL_0(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_ADC0_VREF_BOOST_0(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_ADC0_QUANT_BOOST_0(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_ADC0_CTR3 */ +#define BITS_ADC0_RSV_1(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ADC0_DIG_CLK_SEL_1 ( BIT(11) ) +#define BIT_ADC0_VCM_SEL_1 ( BIT(10) ) +#define BITS_ADC0_DELAY_CAP_1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ADC0_BIT_SEL_1(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_ADC0_VREF_SEL_1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_ADC0_VREF_BOOST_1(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_ADC0_QUANT_BOOST_1(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_CAL_CTR0 */ +#define BIT_LDO_EN_AUTO_EN ( BIT(27) ) +#define BIT_LDO_EN_FRC ( BIT(26) ) +#define BIT_BG_EN_AUTO_EN ( BIT(25) ) +#define BIT_BG_EN_FRC ( BIT(24) ) +#define BITS_ADC_CLK_CAL_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_ADA_CAL_WAIT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_CLK_ADA_CAL_EN ( BIT(6) ) +#define BIT_DAC_PD_CAL ( BIT(5) ) +#define BIT_ADC0_EN_CAL ( BIT(3) ) +#define BIT_ADC0_CAL ( BIT(1) ) +#define BIT_ADA_MODE_SEL ( BIT(0) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_CAL_CTR1 */ +#define BITS_ADC0_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) ) +#define BITS_ADC0_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_CAL_CTR3 */ +#define BIT_ADA0_CAL_START ( BIT(0) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_CAL_STS0 */ +#define BIT_ADA0_CAL_DONE ( BIT(31) ) +#define BITS_ADC0_I_CAL_RESULT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_CAL_STS1 */ +#define BITS_ADC0_Q_CAL_RESULT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_ADA_CTRL0 */ +#define BITS_ADA_AUTO_CTRL(_X_) (_X_) + +/* bits definitions for register REG_ADA_APB_RF_APB_ADA_CTRL1 */ +#define BITS_ADA_FRC_CTRL(_X_) (_X_) + +/* bits definitions for register REG_ADA_APB_RF_APB_RX_GSM_DFT */ +#define BITS_RX_GSM_DFT_Q(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) ) +#define BITS_RX_GSM_DFT_I(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_RX_3G_DFT */ +#define BITS_RX_3G_DFT_Q(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) ) +#define BITS_RX_3G_DFT_I(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) + +#endif diff --git a/include/soc/sprd/chip_x35l/__regs_ana_glb.h b/include/soc/sprd/chip_x35l/__regs_ana_glb.h new file mode 100644 index 00000000..97d72f38 --- /dev/null +++ b/include/soc/sprd/chip_x35l/__regs_ana_glb.h @@ -0,0 +1,836 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __ANA_REGS_GLB_H__ +#define __ANA_REGS_GLB_H__ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, include <mach/sci_glb_regs.h>" +#endif + +#define ANA_REGS_GLB + +/* registers definitions for controller ANA_REGS_GLB */ +#define ANA_REG_GLB_ARM_MODULE_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0000) +#define ANA_REG_GLB_ARM_CLK_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0004) +#define ANA_REG_GLB_RTC_CLK_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0008) +#define ANA_REG_GLB_ARM_RST SCI_ADDR(ANA_REGS_GLB_BASE, 0x000C) +#define ANA_REG_GLB_LDO_DCDC_PD_RTCSET SCI_ADDR(ANA_REGS_GLB_BASE, 0x0010) +#define ANA_REG_GLB_LDO_DCDC_PD_RTCCLR SCI_ADDR(ANA_REGS_GLB_BASE, 0x0014) +#define ANA_REG_GLB_RTC_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0018) +#define ANA_REG_GLB_LDO_PD_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x001C) +#define ANA_REG_GLB_LDO_V_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0020) +#define ANA_REG_GLB_LDO_V_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0024) +#define ANA_REG_GLB_LDO_V_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0028) +#define ANA_REG_GLB_LDO_CAL_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x002C) +#define ANA_REG_GLB_LDO_CAL_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0030) +#define ANA_REG_GLB_LDO_CAL_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0034) +#define ANA_REG_GLB_LDO_CAL_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0038) +#define ANA_REG_GLB_LDO_CAL_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x003C) +#define ANA_REG_GLB_LDO_CAL_CTRL5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0040) +#define ANA_REG_GLB_LDO_CAL_CTRL6 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0044) +#define ANA_REG_GLB_AUXAD_CTL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0048) +#define ANA_REG_GLB_DCDC_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x004C) +#define ANA_REG_GLB_DCDC_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0050) +#define ANA_REG_GLB_DCDC_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0054) +#define ANA_REG_GLB_DCDC_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0058) +#define ANA_REG_GLB_DCDC_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x005C) +#define ANA_REG_GLB_DCDC_CTRL5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0060) +#define ANA_REG_GLB_DCDC_CTRL6 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0064) +#define ANA_REG_GLB_DDR2_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0068) +#define ANA_REG_GLB_SLP_WAIT_DCDCARM SCI_ADDR(ANA_REGS_GLB_BASE, 0x006C) +#define ANA_REG_GLB_LDO1828_XTL_CTL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0070) +#define ANA_REG_GLB_LDO_SLP_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0074) +#define ANA_REG_GLB_LDO_SLP_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0078) +#define ANA_REG_GLB_LDO_SLP_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x007C) +#define ANA_REG_GLB_LDO_SLP_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0080) +#define ANA_REG_GLB_AUD_SLP_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0084) +#define ANA_REG_GLB_DCDC_SLP_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0088) +#define ANA_REG_GLB_XTL_WAIT_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x008C) +#define ANA_REG_GLB_FLASH_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0090) +#define ANA_REG_GLB_WHTLED_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0094) +#define ANA_REG_GLB_WHTLED_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0098) +#define ANA_REG_GLB_WHTLED_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x009C) +#define ANA_REG_GLB_ANA_DRV_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A0) +#define ANA_REG_GLB_VIBR_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A4) +#define ANA_REG_GLB_VIBR_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A8) +#define ANA_REG_GLB_VIBR_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00AC) +#define ANA_REG_GLB_VIBR_WR_PROT_VALUE SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B0) +#define ANA_REG_GLB_AUDIO_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B4) +#define ANA_REG_GLB_CHGR_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B8) +#define ANA_REG_GLB_CHGR_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00BC) +#define ANA_REG_GLB_CHGR_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C0) +#define ANA_REG_GLB_CHGR_STATUS SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C4) +#define ANA_REG_GLB_ANA_MIXED_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C8) +#define ANA_REG_GLB_PWR_XTL_EN0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00CC) +#define ANA_REG_GLB_PWR_XTL_EN1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D0) +#define ANA_REG_GLB_PWR_XTL_EN2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D4) +#define ANA_REG_GLB_PWR_XTL_EN3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D8) +#define ANA_REG_GLB_PWR_XTL_EN4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00DC) +#define ANA_REG_GLB_PWR_XTL_EN5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E0) +#define ANA_REG_GLB_ANA_STATUS SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E4) +#define ANA_REG_GLB_POR_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E8) +#define ANA_REG_GLB_WDG_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x00EC) +#define ANA_REG_GLB_POR_PIN_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F0) +#define ANA_REG_GLB_POR_SRC_FLAG SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F4) +#define ANA_REG_GLB_POR_7S_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F8) +#define ANA_REG_GLB_INT_DEBUG SCI_ADDR(ANA_REGS_GLB_BASE, 0x00FC) +#define ANA_REG_GLB_GPI_DEBUG SCI_ADDR(ANA_REGS_GLB_BASE, 0x0100) +#define ANA_REG_GLB_HWRST_RTC SCI_ADDR(ANA_REGS_GLB_BASE, 0x0104) +#define ANA_REG_GLB_CHIP_ID_LOW SCI_ADDR(ANA_REGS_GLB_BASE, 0x0108) +#define ANA_REG_GLB_CHIP_ID_HIGH SCI_ADDR(ANA_REGS_GLB_BASE, 0x010C) +#define ANA_REG_GLB_ARM_MF_REG SCI_ADDR(ANA_REGS_GLB_BASE, 0x0110) +#define ANA_REG_GLB_AFUSE_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0114) +#define ANA_REG_GLB_AFUSE_OUT0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0118) +#define ANA_REG_GLB_AFUSE_OUT1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x011C) +#define ANA_REG_GLB_AFUSE_OUT2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0120) +#define ANA_REG_GLB_AFUSE_OUT3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0124) +#define ANA_REG_GLB_ARCH_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0128) +#define ANA_REG_GLB_MCU_WR_PROT_VALUE SCI_ADDR(ANA_REGS_GLB_BASE, 0x012C) +#define ANA_REG_GLB_MP_MISC_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0148) +#define ANA_REG_GLB_DCDC_CORE_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0160) +#define ANA_REG_GLB_DCDC_ARM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0164) +#define ANA_REG_GLB_DCDC_MEM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0168) +#define ANA_REG_GLB_DCDC_GEN_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x016C) +#define ANA_REG_GLB_DCDC_WRF_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0170) +#define ANA_REG_GLB_DCDC_WPA_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0174) +#define ANA_REG_GLB_DCDC_WPA_DCM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x017C) +#define ANA_REG_GLB_LDO_CAL_SEL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0044) + +/* bits definitions for register ANA_REG_GLB_ARM_MODULE_EN */ +#define BIT_ANA_THM_EN ( BIT(12) ) +#define BIT_ANA_BLTC_EN ( BIT(10) ) +#define BIT_ANA_PINREG_EN ( BIT(9) ) +#define BIT_ANA_FGU_EN ( BIT(8) ) +#define BIT_ANA_GPIO_EN ( BIT(7) ) +#define BIT_ANA_ADC_EN ( BIT(6) ) +#define BIT_ANA_HDT_EN ( BIT(5) ) +#define BIT_ANA_AUD_EN ( BIT(4) ) +#define BIT_ANA_EIC_EN ( BIT(3) ) +#define BIT_ANA_WDG_EN ( BIT(2) ) +#define BIT_ANA_RTC_EN ( BIT(1) ) + +/* bits definitions for register ANA_REG_GLB_ARM_CLK_EN */ +#define BIT_CLK_AUXAD_EN ( BIT(9) ) +#define BIT_CLK_AUXADC_EN ( BIT(8) ) +#define BIT_CLK_AUD_HID_EN ( BIT(5) ) +#define BIT_CLK_AUD_HBD_EN ( BIT(4) ) +#define BIT_CLK_AUD_LOOP_EN ( BIT(3) ) +#define BIT_CLK_AUD_6P5M_EN ( BIT(2) ) +#define BIT_CLK_AUDIF_EN ( BIT(1) ) + +/* bits definitions for register ANA_REG_GLB_RTC_CLK_EN */ +#define BIT_RTC_FLASH_EN ( BIT(13) ) +#define BIT_RTC_THMA_AUTO_EN ( BIT(12) ) +#define BIT_RTC_THMA_EN ( BIT(11) ) +#define BIT_RTC_THM_EN ( BIT(10) ) +#define BIT_RTC_BLTC_EN ( BIT(8) ) +#define BIT_RTC_FGU_EN ( BIT(7) ) +#define BIT_RTC_FGUA_EN ( BIT(6) ) +#define BIT_RTC_VIBR_EN ( BIT(5) ) +#define BIT_RTC_AUD_EN ( BIT(4) ) +#define BIT_RTC_EIC_EN ( BIT(3) ) +#define BIT_RTC_WDG_EN ( BIT(2) ) +#define BIT_RTC_RTC_EN ( BIT(1) ) +#define BIT_RTC_ARCH_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_ARM_RST */ +#define BIT_ANA_THMA_SOFT_RST ( BIT(14) ) +#define BIT_ANA_THM_SOFT_RST ( BIT(13) ) +#define BIT_ANA_AUD_32K_SOFT_RST ( BIT(12) ) +#define BIT_ANA_AUDTX_SOFT_RST ( BIT(11) ) +#define BIT_ANA_AUDRX_SOFT_RST ( BIT(10) ) +#define BIT_ANA_AUD_SOFT_RST ( BIT(9) ) +#define BIT_ANA_AUD_HDT_SOFT_RST ( BIT(8) ) +#define BIT_ANA_GPIO_SOFT_RST ( BIT(7) ) +#define BIT_ANA_ADC_SOFT_RST ( BIT(6) ) +#define BIT_ANA_PWM0_SOFT_RST ( BIT(5) ) +#define BIT_ANA_FGU_SOFT_RST ( BIT(4) ) +#define BIT_ANA_EIC_SOFT_RST ( BIT(3) ) +#define BIT_ANA_WDG_SOFT_RST ( BIT(2) ) +#define BIT_ANA_RTC_SOFT_RST ( BIT(1) ) +#define BIT_ANA_BLTC_SOFT_RST ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_DCDC_PD_RTCSET */ +#define BIT_DCDC_OTP_PD_RTCSET ( BIT(14) ) +#define BIT_DCDC_WRF_PD_RTCSET ( BIT(13) ) +#define BIT_DCDC_GEN_PD_RTCSET ( BIT(12) ) +#define BIT_DCDC_MEM_PD_RTCSET ( BIT(11) ) +#define BIT_DCDC_ARM_PD_RTCSET ( BIT(10) ) +#define BIT_DCDC_CORE_PD_RTCSET ( BIT(9) ) +#define BIT_LDO_EMMCCORE_PD_RTCSET ( BIT(8) ) +#define BIT_LDO_EMMCIO_PD_RTCSET ( BIT(7) ) +#define BIT_LDO_RF2_PD_RTCSET ( BIT(6) ) +#define BIT_LDO_RF1_PD_RTCSET ( BIT(5) ) +#define BIT_LDO_RF0_PD_RTCSET ( BIT(4) ) +#define BIT_LDO_VDD25_PD_RTCSET ( BIT(3) ) +#define BIT_LDO_VDD28_PD_RTCSET ( BIT(2) ) +#define BIT_LDO_VDD18_PD_RTCSET ( BIT(1) ) +#define BIT_BG_PD_RTCSET ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_DCDC_PD_RTCCLR */ +#define BIT_DCDC_OTP_PD_RTCCLR ( BIT(14) ) +#define BIT_DCDC_WRF_PD_RTCCLR ( BIT(13) ) +#define BIT_DCDC_GEN_PD_RTCCLR ( BIT(12) ) +#define BIT_DCDC_MEM_PD_RTCCLR ( BIT(11) ) +#define BIT_DCDC_ARM_PD_RTCCLR ( BIT(10) ) +#define BIT_DCDC_CORE_PD_RTCCLR ( BIT(9) ) +#define BIT_LDO_EMMCCORE_PD_RTCCLR ( BIT(8) ) +#define BIT_LDO_EMMCIO_PD_RTCCLR ( BIT(7) ) +#define BIT_LDO_RF2_PD_RTCCLR ( BIT(6) ) +#define BIT_LDO_RF1_PD_RTCCLR ( BIT(5) ) +#define BIT_LDO_RF0_PD_RTCCLR ( BIT(4) ) +#define BIT_LDO_VDD25_PD_RTCCLR ( BIT(3) ) +#define BIT_LDO_VDD28_PD_RTCCLR ( BIT(2) ) +#define BIT_LDO_VDD18_PD_RTCCLR ( BIT(1) ) +#define BIT_BG_PD_RTCCLR ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_RTC_CTRL */ +#define BITS_XOSC32K_CTL_STS(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BIT_XOSC32K_CTL_B3_RTCCLR ( BIT(7) ) +#define BIT_XOSC32K_CTL_B2_RTCCLR ( BIT(6) ) +#define BIT_XOSC32K_CTL_B1_RTCCLR ( BIT(5) ) +#define BIT_XOSC32K_CTL_B0_RTCCLR ( BIT(4) ) +#define BIT_XOSC32K_CTL_B3_RTCSET ( BIT(3) ) +#define BIT_XOSC32K_CTL_B2_RTCSET ( BIT(2) ) +#define BIT_XOSC32K_CTL_B1_RTCSET ( BIT(1) ) +#define BIT_XOSC32K_CTL_B0_RTCSET ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_PD_CTRL */ +#define BIT_LDO_LPREF_PD_SW ( BIT(12) ) +#define BIT_DCDC_WPA_PD ( BIT(11) ) +#define BIT_LDO_CLSG_PD ( BIT(10) ) +#define BIT_LDO_USB_PD ( BIT(9) ) +#define BIT_LDO_CAMMOT_PD ( BIT(8) ) +#define BIT_LDO_CAMIO_PD ( BIT(7) ) +#define BIT_LDO_CAMD_PD ( BIT(6) ) +#define BIT_LDO_CAMA_PD ( BIT(5) ) +#define BIT_LDO_SIM2_PD ( BIT(4) ) +#define BIT_LDO_SIM1_PD ( BIT(3) ) +#define BIT_LDO_SIM0_PD ( BIT(2) ) +#define BIT_LDO_SD_PD ( BIT(1) ) +#define BIT_LDO_AVDD18_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL0 */ +#define BITS_LDO_EMMCCORE_V(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_LDO_EMMCIO_V(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_LDO_RF2_V(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_LDO_RF1_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_LDO_RF0_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_LDO_VDD25_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_LDO_VDD28_V(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_LDO_VDD18_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL1 */ +#define BITS_LDO_SIM2_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_LDO_SIM1_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_LDO_SIM0_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_LDO_SD_V(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_LDO_AVDD18_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL2 */ +#define BITS_VBATBK_RES(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_VBATBK_V(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_LDO_CLSG_V(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_LDO_USB_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_LDO_CAMMOT_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_LDO_CAMIO_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_LDO_CAMD_V(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_LDO_CAMA_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL0 */ +#define BITS_LDO_VDD25_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_VDD28_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_VDD18_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL1 */ +#define BITS_LDO_RF2_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_RF1_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_RF0_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL2 */ +#define BITS_LDO_USB_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_EMMCCORE_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_EMMCIO_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL3 */ +#define BITS_LDO_SD_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_AVDD18_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL4 */ +#define BITS_LDO_CAMA_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_SIM2_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_SIM_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL5 */ +#define BITS_LDO_CAMMOT_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_CAMIO_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_CAMD_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL6 */ +#define BITS_LDOA_CAL_SEL(_x_) ( (_x_) << 11 & (BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_LDOD_CAL_SEL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_LDODCDC_CAL_SEL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_LDO_CLSG_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_AUXAD_CTL */ +#define BIT_AUXAD_CURRENTSEN_EN ( BIT(6) ) +#define BIT_AUXAD_CURRENTSEL ( BIT(5) ) +#define BITS_AUXAD_CURRENT_IBS(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL0 */ +#define BIT_DCDC_CORE_LP_EN ( BIT(15) ) +#define BIT_DCDC_CORE_CL_CTRL ( BIT(14) ) +#define BITS_DCDC_CORE_PDRSLOW(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_DCDC_CORE_PFM ( BIT(9) ) +#define BIT_DCDC_CORE_DCM ( BIT(8) ) +#define BIT_DCDC_ARM_LP_EN ( BIT(7) ) +#define BIT_DCDC_ARM_CL_CTRL ( BIT(6) ) +#define BITS_DCDC_ARM_PDRSLOW(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) +#define BIT_DCDC_ARM_PFM ( BIT(1) ) +#define BIT_DCDC_ARM_DCM ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL1 */ +#define BIT_DCDC_MEM_LP_EN ( BIT(15) ) +#define BIT_DCDC_MEM_CL_CTRL ( BIT(14) ) +#define BITS_DCDC_MEM_PDRSLOW(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_DCDC_MEM_PFM ( BIT(9) ) +#define BIT_DCDC_MEM_DCM ( BIT(8) ) +#define BIT_DCDC_GEN_LP_EN ( BIT(7) ) +#define BIT_DCDC_GEN_CL_CTRL ( BIT(6) ) +#define BITS_DCDC_GEN_PDRSLOW(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) +#define BIT_DCDC_GEN_PFM ( BIT(1) ) +#define BIT_DCDC_GEN_DCM ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL2 */ +#define BIT_DCDC_BG_LP_EN ( BIT(15) ) +#define BIT_DCDC_OTP_CHIP_PD_FLAG_CLR ( BIT(14) ) +#define BIT_DCDC_OTP_CHIP_PD_FLAG ( BIT(13) ) +#define BIT_DCDC_OTP_AUTO_PD_EN ( BIT(12) ) +#define BIT_DCDC_OTP_VBEOP ( BIT(11) ) +#define BITS_DCDC_OTP_S(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BIT_DCDC_WRF_LP_EN ( BIT(7) ) +#define BIT_DCDC_WRF_CL_CTRL ( BIT(6) ) +#define BITS_DCDC_WRF_PDRSLOW(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) +#define BIT_DCDC_WRF_PFM ( BIT(1) ) +#define BIT_DCDC_WRF_DCM ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL3 */ +#define BIT_DCDC_WPA_LP_EN ( BIT(8) ) +#define BIT_DCDC_WPA_CL_CTRL ( BIT(7) ) +#define BIT_DCDC_WPA_ZXOP ( BIT(6) ) +#define BITS_DCDC_WPA_PDRSLOW(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) +#define BIT_DCDC_WPA_PFM ( BIT(1) ) +#define BIT_DCDC_WPA_APTEN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL4 */ +#define BIT_DCDC_CORE_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_CORE_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_CORE_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_CORE_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_ARM_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_ARM_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_ARM_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_ARM_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL5 */ +#define BIT_DCDC_MEM_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_MEM_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_MEM_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_MEM_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_GEN_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_GEN_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_GEN_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_GEN_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL6 */ +#define BIT_DCDC_WPA_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_WPA_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_WPA_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_WPA_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_WRF_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_WRF_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_WRF_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_WRF_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DDR2_CTRL */ +#define BIT_DDR2_BUF_PD_HW ( BIT(9) ) +#define BITS_DDR2_BUF_S_DS(_x_) ( (_x_) << 7 & (BIT(7)|BIT(8)) ) +#define BITS_DDR2_BUF_CHNS_DS(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)) ) +#define BIT_DDR2_BUF_PD ( BIT(4) ) +#define BITS_DDR2_BUF_S(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DDR2_BUF_CHNS(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_SLP_WAIT_DCDCARM */ +#define BITS_SLP_IN_WAIT_DCDCARM(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_SLP_OUT_WAIT_DCDCARM(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO1828_XTL_CTL */ +#define BIT_LDO_VDD18_EXT_XTL2_EN ( BIT(11) ) +#define BIT_LDO_VDD18_EXT_XTL1_EN ( BIT(10) ) +#define BIT_LDO_VDD18_EXT_XTL0_EN ( BIT(9) ) +#define BIT_LDO_VDD18_XTL2_EN ( BIT(8) ) +#define BIT_LDO_VDD18_XTL1_EN ( BIT(7) ) +#define BIT_LDO_VDD18_XTL0_EN ( BIT(6) ) +#define BIT_LDO_VDD28_EXT_XTL2_EN ( BIT(5) ) +#define BIT_LDO_VDD28_EXT_XTL1_EN ( BIT(4) ) +#define BIT_LDO_VDD28_EXT_XTL0_EN ( BIT(3) ) +#define BIT_LDO_VDD28_XTL2_EN ( BIT(2) ) +#define BIT_LDO_VDD28_XTL1_EN ( BIT(1) ) +#define BIT_LDO_VDD28_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SLP_CTRL0 */ +#define BIT_SLP_IO_EN ( BIT(15) ) +#define BIT_SLP_DCDC_OTP_PD_EN ( BIT(13) ) +#define BIT_SLP_DCDCGEN_PD_EN ( BIT(12) ) +#define BIT_SLP_DCDCWPA_PD_EN ( BIT(11) ) +#define BIT_SLP_DCDCWRF_PD_EN ( BIT(10) ) +#define BIT_SLP_DCDCARM_PD_EN ( BIT(9) ) +#define BIT_SLP_LDOEMMCCORE_PD_EN ( BIT(7) ) +#define BIT_SLP_LDOEMMCIO_PD_EN ( BIT(6) ) +#define BIT_SLP_LDORF2_PD_EN ( BIT(5) ) +#define BIT_SLP_LDORF1_PD_EN ( BIT(4) ) +#define BIT_SLP_LDORF0_PD_EN ( BIT(3) ) +#define BIT_SLP_LDOVDD25_PD_EN ( BIT(2) ) +#define BIT_SLP_LDOVDD28_PD_EN ( BIT(1) ) +#define BIT_SLP_LDOVDD18_PD_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SLP_CTRL1 */ +#define BIT_SLP_LDO_PD_EN ( BIT(12) ) +#define BIT_SLP_LDOLPREF_PD_EN ( BIT(11) ) +#define BIT_SLP_LDOCLSG_PD_EN ( BIT(10) ) +#define BIT_SLP_LDOUSB_PD_EN ( BIT(9) ) +#define BIT_SLP_LDOCAMMOT_PD_EN ( BIT(8) ) +#define BIT_SLP_LDOCAMIO_PD_EN ( BIT(7) ) +#define BIT_SLP_LDOCAMD_PD_EN ( BIT(6) ) +#define BIT_SLP_LDOCAMA_PD_EN ( BIT(5) ) +#define BIT_SLP_LDOSIM2_PD_EN ( BIT(4) ) +#define BIT_SLP_LDOSIM1_PD_EN ( BIT(3) ) +#define BIT_SLP_LDOSIM0_PD_EN ( BIT(2) ) +#define BIT_SLP_LDOSD_PD_EN ( BIT(1) ) +#define BIT_SLP_LDOAVDD18_PD_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SLP_CTRL2 */ +#define BIT_SLP_DCDC_BG_LP_EN ( BIT(15) ) +#define BIT_SLP_DCDCCORE_LP_EN ( BIT(11) ) +#define BIT_SLP_DCDCMEM_LP_EN ( BIT(10) ) +#define BIT_SLP_DCDCARM_LP_EN ( BIT(9) ) +#define BIT_SLP_DCDCGEN_LP_EN ( BIT(8) ) +#define BIT_SLP_DCDCWPA_LP_EN ( BIT(6) ) +#define BIT_SLP_DCDCWRF_LP_EN ( BIT(5) ) +#define BIT_SLP_LDOEMMCCORE_LP_EN ( BIT(4) ) +#define BIT_SLP_LDOEMMCIO_LP_EN ( BIT(3) ) +#define BIT_SLP_LDORF2_LP_EN ( BIT(2) ) +#define BIT_SLP_LDORF1_LP_EN ( BIT(1) ) +#define BIT_SLP_LDORF0_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SLP_CTRL3 */ +#define BIT_SLP_BG_LP_EN ( BIT(15) ) +#define BIT_SLP_LDOVDD25_LP_EN ( BIT(13) ) +#define BIT_SLP_LDOVDD28_LP_EN ( BIT(12) ) +#define BIT_SLP_LDOVDD18_LP_EN ( BIT(11) ) +#define BIT_SLP_LDOCLSG_LP_EN ( BIT(10) ) +#define BIT_SLP_LDOUSB_LP_EN ( BIT(9) ) +#define BIT_SLP_LDOCAMMOT_LP_EN ( BIT(8) ) +#define BIT_SLP_LDOCAMIO_LP_EN ( BIT(7) ) +#define BIT_SLP_LDOCAMD_LP_EN ( BIT(6) ) +#define BIT_SLP_LDOCAMA_LP_EN ( BIT(5) ) +#define BIT_SLP_LDOSIM2_LP_EN ( BIT(4) ) +#define BIT_SLP_LDOSIM1_LP_EN ( BIT(3) ) +#define BIT_SLP_LDOSIM0_LP_EN ( BIT(2) ) +#define BIT_SLP_LDOSD_LP_EN ( BIT(1) ) +#define BIT_SLP_LDOAVDD18_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_AUD_SLP_CTRL4 */ +#define BIT_SLP_AUD_PA_SW_PD_EN ( BIT(15) ) +#define BIT_SLP_AUD_PA_LDO_PD_EN ( BIT(14) ) +#define BIT_SLP_AUD_PA_PD_EN ( BIT(13) ) +#define BIT_SLP_AUD_OVP_PD_PD_EN ( BIT(9) ) +#define BIT_SLP_AUD_OVP_LDO_PD_EN ( BIT(8) ) +#define BIT_SLP_AUD_VB_PD_EN ( BIT(7) ) +#define BIT_SLP_AUD_VBO_PD_EN ( BIT(6) ) +#define BIT_SLP_AUD_HEADMICBIAS_PD_EN ( BIT(5) ) +#define BIT_SLP_AUD_MICBIAS_HV_PD_EN ( BIT(2) ) +#define BIT_SLP_AUD_HEADMIC_PD_EN ( BIT(1) ) +#define BIT_SLP_AUD_PMUR1_PD_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL */ +#define BITS_SLP_DCDCCORE_VOL_DROP_CNT(_x_)( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DCDC_CORE_CTL_DS(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register ANA_REG_GLB_XTL_WAIT_CTRL */ +#define BIT_SLP_XTLBUF_PD_EN ( BIT(9) ) +#define BIT_XTL_EN ( BIT(8) ) +#define BITS_XTL_WAIT(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_FLASH_CTRL */ +#define BIT_FLASH_PON ( BIT(15) ) +#define BIT_FLASH_V_HW_EN ( BIT(6) ) +#define BITS_FLASH_V_HW_STEP(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_FLASH_V_SW(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register ANA_REG_GLB_WHTLED_CTRL0 */ +#define BIT_WHTLED_PD_STS ( BIT(15) ) +#define BITS_WHTLED_DC(_x_) ( (_x_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BIT_WHTLED_BOOST_EN ( BIT(8) ) +#define BIT_WHTLED_SERIES_EN ( BIT(7) ) +#define BITS_WHTLED_V(_x_) ( (_x_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_WHTLED_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_WHTLED_CTRL1 */ +#define BIT_LCM_CABC_PWM_SEL ( BIT(15) ) +#define BIT_RTC_PWM0_EN ( BIT(14) ) +#define BIT_PWM0_EN ( BIT(13) ) +#define BITS_WHTLED_ISET(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_WHTLED_FRE_AD(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)) ) +#define BITS_WHTLED_CLMIT_OP(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_WHTLED_CTRL2 */ +#define BIT_WHTLED_DIMMING_SEL ( BIT(15) ) +#define BIT_WHTLED_PD_SEL ( BIT(14) ) +#define BIT_WHTLED_DIS_OVST ( BIT(13) ) +#define BIT_WHTLED_DIM_SEL ( BIT(12) ) +#define BIT_WHTLED_DE_BIAS ( BIT(11) ) +#define BIT_WHTLED_BUFF_SHT ( BIT(10) ) +#define BITS_WHTLED_STB_OP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_WHTLED_CAP_OPTION ( BIT(7) ) +#define BIT_WHTLED_OVP_DIS ( BIT(6) ) +#define BITS_WHTLED_REF_DC(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register ANA_REG_GLB_ANA_DRV_CTRL */ +#define BIT_SLP_RGB_PD_EN ( BIT(14) ) +#define BIT_RGB_PD_HW_EN ( BIT(13) ) +#define BITS_RGB_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BITS_KPLED_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_RGB_PD_SW ( BIT(2) ) +#define BIT_KPLED_PD ( BIT(1) ) +#define BIT_KPLED_PD_STS ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_VIBR_CTRL0 */ +#define BITS_VIBR_STABLE_V_HW(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_VIBR_INIT_V_HW(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_VIBR_V_SW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_VIBR_PON ( BIT(2) ) +#define BIT_VIBR_SW_EN ( BIT(1) ) + +/* bits definitions for register ANA_REG_GLB_VIBR_CTRL1 */ +#define BITS_VIBR_V_CONVERT_CNT_HW(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_VIBR_CTRL2 */ +#define BIT_VIBR_PWR_ON_STS ( BIT(15) ) +#define BIT_VIBR_HW_FLOW_ERR1 ( BIT(14) ) +#define BIT_VIBR_HW_FLOW_ERR1_CLR ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_VIBR_WR_PROT_VALUE */ +#define BIT_VIBR_WR_PROT ( BIT(15) ) +#define BITS_VIBR_WR_PROT_VALUE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_AUDIO_CTRL */ +#define BIT_AUD_SLP_APP_RST_EN ( BIT(10) ) +#define BITS_CLK_AUD_HBD_DIV(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BIT_CLK_AUD_LOOP_INV_EN ( BIT(4) ) +#define BIT_CLK_AUDIF_TX_INV_EN ( BIT(3) ) +#define BIT_CLK_AUDIF_RX_INV_EN ( BIT(2) ) +#define BIT_CLK_AUD_6P5M_TX_INV_EN ( BIT(1) ) +#define BIT_CLK_AUD_6P5M_RX_INV_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL0 */ +#define BIT_CHGR_PD_STS ( BIT(15) ) +#define BITS_CHGR_CV_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CHGR_END_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CHG_PUMP_V(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BIT_CHGR_PD_RTCCLR ( BIT(1) ) +#define BIT_CHGR_PD_RTCSET ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL1 */ +#define BIT_DP_DM_SW_EN ( BIT(15) ) +#define BITS_CHGR_CC_I(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_VBAT_OVP_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_VCHG_OVP_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL2 */ +#define BITS_CHG_PUMP_CAL(_x_) ( (_x_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_CHG_PUMP_PD ( BIT(8) ) +#define BIT_CHGR_CC_EN ( BIT(1) ) +#define BIT_RECHG ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_STATUS */ +#define BIT_CHG_DET_DONE ( BIT(11) ) +#define BIT_DP_LOW ( BIT(10) ) +#define BIT_DCP_DET ( BIT(9) ) +#define BIT_CHG_DET ( BIT(8) ) +#define BIT_SDP_INT ( BIT(7) ) +#define BIT_DCP_INT ( BIT(6) ) +#define BIT_CDP_INT ( BIT(5) ) +#define BIT_CHGR_CV_STATUS ( BIT(4) ) +#define BIT_CHGR_ON ( BIT(3) ) +#define BIT_CHGR_INT ( BIT(2) ) +#define BIT_VBAT_OVI ( BIT(1) ) +#define BIT_VCHG_OVI ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_ANA_MIXED_CTRL */ +#define BIT_PTEST_PD_RTCSET ( BIT(15) ) +#define BIT_THM_CHIP_PD_FLAG ( BIT(8) ) +#define BIT_THM_CHIP_PD_FLAG_CLR ( BIT(7) ) +#define BITS_THM_CAL_SEL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)) ) +#define BIT_THM_AUTO_PD_EN ( BIT(4) ) +#define BIT_BG_LP_EN ( BIT(3) ) +#define BITS_UVHO_T(_x_) ( (_x_) << 1 & (BIT(1)|BIT(2)) ) +#define BIT_UVHO_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN0 */ +#define BIT_LDO_XTL_EN ( BIT(15) ) +#define BIT_LDO_RF1_EXT_XTL2_EN ( BIT(11) ) +#define BIT_LDO_RF1_EXT_XTL1_EN ( BIT(10) ) +#define BIT_LDO_RF1_EXT_XTL0_EN ( BIT(9) ) +#define BIT_LDO_RF1_XTL2_EN ( BIT(8) ) +#define BIT_LDO_RF1_XTL1_EN ( BIT(7) ) +#define BIT_LDO_RF1_XTL0_EN ( BIT(6) ) +#define BIT_LDO_RF0_EXT_XTL2_EN ( BIT(5) ) +#define BIT_LDO_RF0_EXT_XTL1_EN ( BIT(4) ) +#define BIT_LDO_RF0_EXT_XTL0_EN ( BIT(3) ) +#define BIT_LDO_RF0_XTL2_EN ( BIT(2) ) +#define BIT_LDO_RF0_XTL1_EN ( BIT(1) ) +#define BIT_LDO_RF0_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN1 */ +#define BIT_LDO_VDD25_EXT_XTL2_EN ( BIT(11) ) +#define BIT_LDO_VDD25_EXT_XTL1_EN ( BIT(10) ) +#define BIT_LDO_VDD25_EXT_XTL0_EN ( BIT(9) ) +#define BIT_LDO_VDD25_XTL2_EN ( BIT(8) ) +#define BIT_LDO_VDD25_XTL1_EN ( BIT(7) ) +#define BIT_LDO_VDD25_XTL0_EN ( BIT(6) ) +#define BIT_LDO_RF2_EXT_XTL2_EN ( BIT(5) ) +#define BIT_LDO_RF2_EXT_XTL1_EN ( BIT(4) ) +#define BIT_LDO_RF2_EXT_XTL0_EN ( BIT(3) ) +#define BIT_LDO_RF2_XTL2_EN ( BIT(2) ) +#define BIT_LDO_RF2_XTL1_EN ( BIT(1) ) +#define BIT_LDO_RF2_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN2 */ +#define BIT_LDO_AVDD18_EXT_XTL2_EN ( BIT(11) ) +#define BIT_LDO_AVDD18_EXT_XTL1_EN ( BIT(10) ) +#define BIT_LDO_AVDD18_EXT_XTL0_EN ( BIT(9) ) +#define BIT_LDO_AVDD18_XTL2_EN ( BIT(8) ) +#define BIT_LDO_AVDD18_XTL1_EN ( BIT(7) ) +#define BIT_LDO_AVDD18_XTL0_EN ( BIT(6) ) +#define BIT_LDO_SIM2_EXT_XTL2_EN ( BIT(5) ) +#define BIT_LDO_SIM2_EXT_XTL1_EN ( BIT(4) ) +#define BIT_LDO_SIM2_EXT_XTL0_EN ( BIT(3) ) +#define BIT_LDO_SIM2_XTL2_EN ( BIT(2) ) +#define BIT_LDO_SIM2_XTL1_EN ( BIT(1) ) +#define BIT_LDO_SIM2_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN3 */ +#define BIT_DCDC_BG_EXT_XTL2_EN ( BIT(11) ) +#define BIT_DCDC_BG_EXT_XTL1_EN ( BIT(10) ) +#define BIT_DCDC_BG_EXT_XTL0_EN ( BIT(9) ) +#define BIT_DCDC_BG_XTL2_EN ( BIT(8) ) +#define BIT_DCDC_BG_XTL1_EN ( BIT(7) ) +#define BIT_DCDC_BG_XTL0_EN ( BIT(6) ) +#define BIT_BG_EXT_XTL2_EN ( BIT(5) ) +#define BIT_BG_EXT_XTL1_EN ( BIT(4) ) +#define BIT_BG_EXT_XTL0_EN ( BIT(3) ) +#define BIT_BG_XTL2_EN ( BIT(2) ) +#define BIT_BG_XTL1_EN ( BIT(1) ) +#define BIT_BG_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN4 */ +#define BIT_DCDC_WRF_XTL2_EN ( BIT(14) ) +#define BIT_DCDC_WRF_XTL1_EN ( BIT(13) ) +#define BIT_DCDC_WRF_XTL0_EN ( BIT(12) ) +#define BIT_DCDC_WPA_XTL2_EN ( BIT(11) ) +#define BIT_DCDC_WPA_XTL1_EN ( BIT(10) ) +#define BIT_DCDC_WPA_XTL0_EN ( BIT(9) ) +#define BIT_DCDC_MEM_XTL2_EN ( BIT(8) ) +#define BIT_DCDC_MEM_XTL1_EN ( BIT(7) ) +#define BIT_DCDC_MEM_XTL0_EN ( BIT(6) ) +#define BIT_DCDC_GEN_XTL2_EN ( BIT(5) ) +#define BIT_DCDC_GEN_XTL1_EN ( BIT(4) ) +#define BIT_DCDC_GEN_XTL0_EN ( BIT(3) ) +#define BIT_DCDC_CORE_XTL2_EN ( BIT(2) ) +#define BIT_DCDC_CORE_XTL1_EN ( BIT(1) ) +#define BIT_DCDC_CORE_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN5 */ +#define BIT_DCDC_WRF_EXT_XTL2_EN ( BIT(14) ) +#define BIT_DCDC_WRF_EXT_XTL1_EN ( BIT(13) ) +#define BIT_DCDC_WRF_EXT_XTL0_EN ( BIT(12) ) +#define BIT_DCDC_WPA_EXT_XTL2_EN ( BIT(11) ) +#define BIT_DCDC_WPA_EXT_XTL1_EN ( BIT(10) ) +#define BIT_DCDC_WPA_EXT_XTL0_EN ( BIT(9) ) +#define BIT_DCDC_MEM_EXT_XTL2_EN ( BIT(8) ) +#define BIT_DCDC_MEM_EXT_XTL1_EN ( BIT(7) ) +#define BIT_DCDC_MEM_EXT_XTL0_EN ( BIT(6) ) +#define BIT_DCDC_GEN_EXT_XTL2_EN ( BIT(5) ) +#define BIT_DCDC_GEN_EXT_XTL1_EN ( BIT(4) ) +#define BIT_DCDC_GEN_EXT_XTL0_EN ( BIT(3) ) +#define BIT_DCDC_CORE_EXT_XTL2_EN ( BIT(2) ) +#define BIT_DCDC_CORE_EXT_XTL1_EN ( BIT(1) ) +#define BIT_DCDC_CORE_EXT_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_ANA_STATUS */ +#define BIT_BONDOPT5 ( BIT(5) ) +#define BIT_BONDOPT4 ( BIT(4) ) +#define BIT_BONDOPT3 ( BIT(3) ) +#define BIT_BONDOPT2 ( BIT(2) ) +#define BIT_BONDOPT1 ( BIT(1) ) +#define BIT_BONDOPT0 ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_POR_RST_MONITOR */ +#define BITS_POR_RST_MONITOR(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_WDG_RST_MONITOR */ +#define BITS_WDG_RST_MONITOR(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_POR_PIN_RST_MONITOR */ +#define BITS_POR_PIN_RST_MONITOR(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_POR_SRC_FLAG */ +#define BIT_POR_SW_FORCE_ON ( BIT(15) ) +#define BITS_POR_SRC_FLAG(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_POR_7S_CTRL */ +#define BIT_PBINT_7S_FLAG_CLR ( BIT(15) ) +#define BIT_EXT_RSTN_FLAG_CLR ( BIT(14) ) +#define BIT_CHGR_INT_FLAG_CLR ( BIT(13) ) +#define BIT_PBINT2_FLAG_CLR ( BIT(12) ) +#define BIT_PBINT_FLAG_CLR ( BIT(11) ) +#define BIT_PBINT_7S_RST_SWMODE_RTCSTS ( BIT(10) ) +#define BIT_PBINT_7S_RST_SWMODE_RTCCLR ( BIT(9) ) +#define BIT_PBINT_7S_RST_SWMODE_RTCSET ( BIT(8) ) +#define BITS_PBINT_7S_RST_THRESHOLD(_x_)( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_PBINT_7S_RST_DISABLE ( BIT(3) ) +#define BIT_PBINT_7S_RST_MODE_RTCSTS ( BIT(2) ) +#define BIT_PBINT_7S_RST_MODE_RTCCLR ( BIT(1) ) +#define BIT_PBINT_7S_RST_MODE_RTCSET ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_INT_DEBUG */ +#define BIT_OTP_INT_DEB ( BIT(10) ) +#define BIT_THM_INT_DEB ( BIT(9) ) +#define BIT_AUD_PROT_INT_DEB ( BIT(8) ) +#define BIT_AUD_HEADBTN_INT_DEB ( BIT(7) ) +#define BIT_EIC_INT_DEB ( BIT(6) ) +#define BIT_FGU_INT_DEB ( BIT(5) ) +#define BIT_WDG_INT_DEB ( BIT(4) ) +#define BIT_RTC_INT_DEB ( BIT(3) ) +#define BIT_GPIO_INT_DEB ( BIT(2) ) +#define BIT_ADC_INT_DEB ( BIT(1) ) +#define BIT_INT_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_GPI_DEBUG */ +#define BIT_HEAD_INSERT2_DEB ( BIT(9) ) +#define BIT_HEAD_INSERT_DEB ( BIT(8) ) +#define BIT_HEAD_BUTTON_DEB ( BIT(7) ) +#define BIT_PBINT2_DEB ( BIT(6) ) +#define BIT_PBINT_DEB ( BIT(5) ) +#define BIT_VCHG_OVI_DEB ( BIT(4) ) +#define BIT_VBAT_OVI_DEB ( BIT(3) ) +#define BIT_CHGR_INT_DEB ( BIT(2) ) +#define BIT_GPI_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_HWRST_RTC */ +#define BITS_HWRST_RTC_REG_STS(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_HWRST_RTC_REG_SET(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_CHIP_ID_LOW */ +#define BITS_CHIP_ID_LOW(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_CHIP_ID_HIGH */ +#define BITS_CHIP_ID_HIGH(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_ARM_MF_REG */ +#define BITS_ARM_MF_REG(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_AFUSE_CTRL */ +#define BIT_AFUSE_READ_REQ ( BIT(7) ) +#define BITS_AFUSE_READ_DLY(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) + +/* bits definitions for register ANA_REG_GLB_AFUSE_OUT0 */ +#define BITS_AFUSE_OUT0(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_AFUSE_OUT1 */ +#define BITS_AFUSE_OUT1(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_AFUSE_OUT2 */ +#define BITS_AFUSE_OUT2(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_AFUSE_OUT3 */ +#define BITS_AFUSE_OUT3(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_ARCH_EN */ +#define BIT_ARCH_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_MCU_WR_PROT_VALUE */ +#define BIT_MCU_WR_PROT ( BIT(15) ) +#define BITS_MCU_WR_PROT_VALUE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CORE_ADI */ +#define BITS_DCDC_CORE_CTL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DCDC_CORE_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_ARM_ADI */ +#define BITS_DCDC_ARM_CTL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DCDC_ARM_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_MEM_ADI */ +#define BIT_DCDC_MEM_CTL_ADI ( BIT(5) ) +#define BITS_DCDC_MEM_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_GEN_ADI */ +#define BITS_DCDC_GEN_CTL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DCDC_GEN_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_WRF_ADI */ +#define BITS_DCDC_WRF_CTL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)) ) +#define BITS_DCDC_WRF_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_WPA_ADI */ +#define BITS_DCDC_WPA_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_WPA_DCM_ADI */ +#define BIT_DCDC_WPA_DCM_ADI ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_SEL */ +#define BIT_LDO_CAMIO_CAL_EN ( BIT(5) ) +#define BIT_LDO_CLSG_CAL_EN ( BIT(6) ) +#define BITS_LDO_CAMD_CAL_EN(_x_) ( (_x_) & (BIT(5)|BIT(6)) ) +#define BIT_LDO_EMMCIO_CAL_EN ( BIT(7) ) +#define BITS_LDO_AVDD18_CAL_EN(_x_) ( (_x_) & (BIT(5)|BIT(7)) ) +#define BITS_LDO_VDD18_CAL_EN(_x_) ( (_x_) & (BIT(6)|BIT(7)) ) +#define BIT_LDO_SIM0_CAL_EN ( BIT(9) ) +#define BIT_LDO_SIM1_CAL_EN ( BIT(9) ) +#define BITS_LDO_SIM2_CAL_EN(_x_) ( (_x_) & (BIT(8)|BIT(9)) ) +#define BIT_LDO_EMMCCORE_CAL_EN ( BIT(10) ) +#define BITS_LDO_VDD28_CAL_EN(_x_) ( (_x_) & (BIT(8)|BIT(10)) ) +#define BITS_LDO_VDD25_CAL_EN(_x_) ( (_x_) & (BIT(9)|BIT(10)) ) +#define BITS_LDO_USB_CAL_EN(_x_) ( (_x_) & (BIT(8)|BIT(9)|BIT(10)) ) +#define BIT_LDO_SD_CAL_EN ( BIT(11) ) +#define BIT_LDO_CAMA_CAL_EN ( BIT(12) ) +#define BITS_LDO_RF2_CAL_EN(_x_) ( (_x_) & (BIT(11)|BIT(12)) ) +#define BIT_LDO_RF1_CAL_EN ( BIT(13) ) +#define BITS_LDO_RF0_CAL_EN(_x_) ( (_x_) & (BIT(11)|BIT(13)) ) +#define BITS_LDO_CAMMOT_CAL_EN(_x_) ( (_x_) & (BIT(12)|BIT(13)) ) +#define BITS_LDO_CAL_SEL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +#define SHFT_LDO_CAL_SEL ( 5 ) +#define MASK_LDO_CAL_SEL ( BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13) ) + +/* vars definitions for controller ANA_REGS_GLB */ + +#endif //__ANA_REGS_GLB_H__ diff --git a/include/soc/sprd/chip_x35l/__regs_ana_sc2723_glb.h b/include/soc/sprd/chip_x35l/__regs_ana_sc2723_glb.h new file mode 100755 index 00000000..fe9cd745 --- /dev/null +++ b/include/soc/sprd/chip_x35l/__regs_ana_sc2723_glb.h @@ -0,0 +1,952 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __ANA_REGS_GLB_H__ +#define __ANA_REGS_GLB_H__ + +#define ANA_REGS_GLB + +/* registers definitions for controller ANA_REGS_GLB */ +#define ANA_REG_GLB_ARM_MODULE_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0000) +#define ANA_REG_GLB_ARM_CLK_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0004) +#define ANA_REG_GLB_RTC_CLK_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0008) +#define ANA_REG_GLB_ARM_RST SCI_ADDR(ANA_REGS_GLB_BASE, 0x000C) +#define ANA_REG_GLB_LDO_DCDC_PD SCI_ADDR(ANA_REGS_GLB_BASE, 0x0010) +#define ANA_REG_GLB_LDO_PD_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0014) +#define ANA_REG_GLB_LDO_V_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0018) +#define ANA_REG_GLB_LDO_V_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x001C) +#define ANA_REG_GLB_LDO_V_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0020) +#define ANA_REG_GLB_LDO_V_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0024) +#define ANA_REG_GLB_LDO_V_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0028) +#define ANA_REG_GLB_LDO_V_CTRL5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x002C) +#define ANA_REG_GLB_LDO_V_CTRL6 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0030) +#define ANA_REG_GLB_LDO_V_CTRL7 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0034) +#define ANA_REG_GLB_LDO_V_CTRL8 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0038) +#define ANA_REG_GLB_LDO_V_CTRL9 SCI_ADDR(ANA_REGS_GLB_BASE, 0x003C) +#define ANA_REG_GLB_LDO_V_CTRL10 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0040) +#define ANA_REG_GLB_LDO_V_CTRL11 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0044) +#define ANA_REG_GLB_LDO_LP_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0048) +#define ANA_REG_GLB_DCDC_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x004C) +#define ANA_REG_GLB_DCDC_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0050) +#define ANA_REG_GLB_DCDC_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0054) +#define ANA_REG_GLB_DCDC_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0058) +#define ANA_REG_GLB_DCDC_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x005C) +#define ANA_REG_GLB_DCDC_CTRL5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0060) +#define ANA_REG_GLB_DCDC_CTRL6 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0064) +#define ANA_REG_GLB_DCDC_CTRL7 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0068) +#define ANA_REG_GLB_DCDC_CTRL8 SCI_ADDR(ANA_REGS_GLB_BASE, 0x006C) +#define ANA_REG_GLB_DCDC_CTRL9 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0070) +#define ANA_REG_GLB_DCDC_CTRL10 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0074) +#define ANA_REG_GLB_DCDC_CTRL11 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0078) +#define ANA_REG_GLB_DCDC_CTRL12 SCI_ADDR(ANA_REGS_GLB_BASE, 0x007C) +#define ANA_REG_GLB_DCDC_CTRL13 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0080) +#define ANA_REG_GLB_DCDC_CTRL14 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0084) +#define ANA_REG_GLB_DCDC_CTRL15 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0088) +#define ANA_REG_GLB_SLP_WAIT_DCDCARM SCI_ADDR(ANA_REGS_GLB_BASE, 0x008C) +#define ANA_REG_GLB_PWR_SLP_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0090) +#define ANA_REG_GLB_PWR_SLP_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0094) +#define ANA_REG_GLB_PWR_SLP_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0098) +#define ANA_REG_GLB_PWR_SLP_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x009C) +#define ANA_REG_GLB_PWR_SLP_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A0) +#define ANA_REG_GLB_AUD_SLP_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A4) +#define ANA_REG_GLB_DCDC_SLP_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A8) +#define ANA_REG_GLB_DCDC_SLP_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00AC) +#define ANA_REG_GLB_DCDC_SLP_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B0) +#define ANA_REG_GLB_DCDC_SLP_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B4) +#define ANA_REG_GLB_DCDC_SLP_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B8) +#define ANA_REG_GLB_DCDC_SLP_CTRL5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00BC) +#define ANA_REG_GLB_PWR_SEL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C0) +#define ANA_REG_GLB_PWR_XTL_EN0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C4) +#define ANA_REG_GLB_PWR_XTL_EN1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C8) +#define ANA_REG_GLB_PWR_XTL_EN2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00CC) +#define ANA_REG_GLB_PWR_XTL_EN3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D0) +#define ANA_REG_GLB_32KLESS_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D4) +#define ANA_REG_GLB_32KLESS_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D8) +#define ANA_REG_GLB_32KLESS_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00DC) +#define ANA_REG_GLB_32KLESS_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E0) +#define ANA_REG_GLB_AUXAD_CTL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E4) +#define ANA_REG_GLB_XTL_WAIT_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E8) +#define ANA_REG_GLB_RGB_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00EC) +#define ANA_REG_GLB_WHTLED_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F0) +#define ANA_REG_GLB_WHTLED_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0094) +#define ANA_REG_GLB_WHTLED_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0098) +#define ANA_REG_GLB_KPLED_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F4) +#define ANA_REG_GLB_VIBR_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F8) +#define ANA_REG_GLB_AUDIO_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00FC) +#define ANA_REG_GLB_AUDIO_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0100) +#define ANA_REG_GLB_CHGR_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0104) +#define ANA_REG_GLB_CHGR_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0108) +#define ANA_REG_GLB_CHGR_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x010C) +#define ANA_REG_GLB_CHGR_DET_FGU_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0110) +#define ANA_REG_GLB_CHGR_STATUS SCI_ADDR(ANA_REGS_GLB_BASE, 0x0114) +#define ANA_REG_GLB_MIXED_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0118) +#define ANA_REG_GLB_MIXED_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x011C) +#define ANA_REG_GLB_SWRST_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0120) +#define ANA_REG_GLB_POR_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x0124) +#define ANA_REG_GLB_WDG_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x0128) +#define ANA_REG_GLB_POR_PIN_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x012C) +#define ANA_REG_GLB_POR_SRC_FLAG SCI_ADDR(ANA_REGS_GLB_BASE, 0x0130) +#define ANA_REG_GLB_POR_7S_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0134) +#define ANA_REG_GLB_HWRST_RTC SCI_ADDR(ANA_REGS_GLB_BASE, 0x0138) +#define ANA_REG_GLB_CHIP_ID_LOW SCI_ADDR(ANA_REGS_GLB_BASE, 0x013C) +#define ANA_REG_GLB_CHIP_ID_HIGH SCI_ADDR(ANA_REGS_GLB_BASE, 0x0140) +#define ANA_REG_GLB_ARM_MF_REG SCI_ADDR(ANA_REGS_GLB_BASE, 0x0144) +#define ANA_REG_GLB_ARCH_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0148) +#define ANA_REG_GLB_MCU_WR_PROT_VALUE SCI_ADDR(ANA_REGS_GLB_BASE, 0x014C) +#define ANA_REG_GLB_PWR_WR_PROT_VALUE SCI_ADDR(ANA_REGS_GLB_BASE, 0x0150) +#define ANA_REG_GLB_SMPL_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0154) +#define ANA_REG_GLB_SMPL_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0158) +#define ANA_REG_GLB_RTC_RST0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x015C) +#define ANA_REG_GLB_RTC_RST1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0160) +#define ANA_REG_GLB_RTC_RST2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0164) +#define ANA_REG_GLB_LDO_SHPT_PD1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0188) +#define ANA_REG_GLB_LDO_SHPT_PD2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x018C) +#define ANA_REG_GLB_BATDET_CUR_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0190) +#define ANA_REG_GLB_RTC_CLK_STOP SCI_ADDR(ANA_REGS_GLB_BASE, 0x0194) +#define ANA_REG_GLB_VBAT_DROP_CNT SCI_ADDR(ANA_REGS_GLB_BASE, 0x0198) +#define ANA_REG_GLB_DCDC_DISCHRG SCI_ADDR(ANA_REGS_GLB_BASE, 0x019C) +#define ANA_REG_GLB_DCDC_CORE_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0200) +#define ANA_REG_GLB_DCDC_ARM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0204) +#define ANA_REG_GLB_DCDC_MEM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0208) +#define ANA_REG_GLB_DCDC_GEN_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x020C) +#define ANA_REG_GLB_DCDC_WPA_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0210) +#define ANA_REG_GLB_DCDC_WPA_DCM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0214) +#define ANA_REG_GLB_DCDC_CON_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0218) +#define ANA_REG_GLB_DCDC_RF_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x021C) + +/* bits definitions for register ANA_REG_GLB_ARM_MODULE_EN */ +#define BIT_ANA_IMPD_ADC_EN ( BIT(12) ) +#define BIT_ANA_THM_EN ( BIT(11) ) +#define BIT_ANA_BLTC_EN ( BIT(10) ) +#define BIT_ANA_PINREG_EN ( BIT(9) ) +#define BIT_ANA_FGU_EN ( BIT(8) ) +#define BIT_ANA_EFS_EN ( BIT(7) ) +#define BIT_ANA_ADC_EN ( BIT(6) ) +#define BIT_ANA_HDT_EN ( BIT(5) ) +#define BIT_ANA_AUD_EN ( BIT(4) ) +#define BIT_ANA_EIC_EN ( BIT(3) ) +#define BIT_ANA_WDG_EN ( BIT(2) ) +#define BIT_ANA_RTC_EN ( BIT(1) ) +#define BIT_ANA_CAL_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_ARM_CLK_EN */ +#define BIT_CLK_IMPD_ADC_EN ( BIT(10) ) +#define BIT_CLK_AUXAD_EN ( BIT(9) ) +#define BIT_CLK_AUXADC_EN ( BIT(8) ) +#define BITS_CLK_CAL_SRC_SEL(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BIT_CLK_CAL_EN ( BIT(5) ) +#define BIT_CLK_AUD_HID_EN ( BIT(4) ) +#define BIT_CLK_AUD_HBD_EN ( BIT(3) ) +#define BIT_CLK_AUD_LOOP_EN ( BIT(2) ) +#define BIT_CLK_AUD_6P5M_EN ( BIT(1) ) +#define BIT_CLK_AUDIF_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_RTC_CLK_EN */ +#define BIT_RTC_EFS_EN ( BIT(12) ) +#define BIT_RTC_THMA_AUTO_EN ( BIT(11) ) +#define BIT_RTC_THMA_EN ( BIT(10) ) +#define BIT_RTC_THM_EN ( BIT(9) ) +#define BIT_RTC_BLTC_EN ( BIT(8) ) +#define BIT_RTC_FGU_EN ( BIT(7) ) +#define BIT_RTC_FGUA_EN ( BIT(6) ) +#define BIT_RTC_VIBR_EN ( BIT(5) ) +#define BIT_RTC_AUD_EN ( BIT(4) ) +#define BIT_RTC_EIC_EN ( BIT(3) ) +#define BIT_RTC_WDG_EN ( BIT(2) ) +#define BIT_RTC_RTC_EN ( BIT(1) ) +#define BIT_RTC_ARCH_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_ARM_RST */ +#define BIT_ANA_THMA_SOFT_RST ( BIT(15) ) +#define BIT_ANA_THM_SOFT_RST ( BIT(14) ) +#define BIT_ANA_BLTC_SOFT_RST ( BIT(13) ) +#define BIT_ANA_AUD_32K_SOFT_RST ( BIT(12) ) +#define BIT_ANA_AUDTX_SOFT_RST ( BIT(11) ) +#define BIT_ANA_AUDRX_SOFT_RST ( BIT(10) ) +#define BIT_ANA_AUD_SOFT_RST ( BIT(9) ) +#define BIT_ANA_AUD_HDT_SOFT_RST ( BIT(8) ) +#define BIT_ANA_EFS_SOFT_RST ( BIT(7) ) +#define BIT_ANA_ADC_SOFT_RST ( BIT(6) ) +#define BIT_ANA_PWM0_SOFT_RST ( BIT(5) ) +#define BIT_ANA_FGU_SOFT_RST ( BIT(4) ) +#define BIT_ANA_EIC_SOFT_RST ( BIT(3) ) +#define BIT_ANA_WDG_SOFT_RST ( BIT(2) ) +#define BIT_ANA_RTC_SOFT_RST ( BIT(1) ) +#define BIT_ANA_CAL_SOFT_RST ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_DCDC_PD */ +#define BIT_LDO_EMM_PD ( BIT(15) ) +#define BIT_DCDC_TOPCLK6M_PD ( BIT(14) ) +#define BIT_DCDC_RF_PD ( BIT(13) ) +#define BIT_DCDC_GEN_PD ( BIT(12) ) +#define BIT_DCDC_MEM_PD ( BIT(11) ) +#define BIT_DCDC_ARM_PD ( BIT(10) ) +#define BIT_DCDC_CORE_PD ( BIT(9) ) +#define BIT_LDO_RF0_PD ( BIT(8) ) +#define BIT_LDO_EMMCCORE_PD ( BIT(7) ) +#define BIT_LDO_GEN1_PD ( BIT(6) ) +#define BIT_LDO_DCXO_PD ( BIT(5) ) +#define BIT_LDO_GEN0_PD ( BIT(4) ) +#define BIT_LDO_VDD25_PD ( BIT(3) ) +#define BIT_LDO_VDD28_PD ( BIT(2) ) +#define BIT_LDO_VDD18_PD ( BIT(1) ) +#define BIT_BG_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_PD_CTRL */ +#define BIT_LDO_LPREF_PD_SW ( BIT(15) ) +#define BIT_DCDC_WPA_PD ( BIT(14) ) +#define BIT_DCDC_CON_PD ( BIT(13) ) +#define BIT_LDO_WIFIPA_PD ( BIT(11) ) +#define BIT_LDO_SDCORE_PD ( BIT(10) ) +#define BIT_LDO_USB_PD ( BIT(8) ) +#define BIT_LDO_CAMMOT_PD ( BIT(7) ) +#define BIT_LDO_CAMIO_PD ( BIT(6) ) +#define BIT_LDO_CAMD_PD ( BIT(5) ) +#define BIT_LDO_CAMA_PD ( BIT(4) ) +#define BIT_LDO_SIM2_PD ( BIT(3) ) +#define BIT_LDO_SIM1_PD ( BIT(2) ) +#define BIT_LDO_SIM0_PD ( BIT(1) ) +#define BIT_LDO_SDIO_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL0 */ +#define BITS_LDO_RF0_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_WIFIPA_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL1 */ +#define BITS_LDO_CAMIO_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_CAMD_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL2 */ +#define BITS_LDO_GEN0_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL3 */ +#define BITS_LDO_GEN1_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_VDD28_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL4 */ +#define BITS_LDO_SIM0_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_SDIO_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL5 */ +#define BITS_LDO_SIM2_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_SIM1_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL6 */ +#define BITS_LDO_SDCORE_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_CAMA_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL7 */ +#define BITS_LDO_EMMCCORE_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_CAMMOT_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL8 */ +#define BITS_LDO_DCXO_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_DCXO_LP_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL9 */ +#define BITS_LDO_VDD18_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_USB_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL10 */ +#define BITS_LDO_VDD25_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL11 */ +#define BITS_VBATBK_V(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_LDOB_CAL_SEL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_LDOA_CAL_SEL (_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_LDOD_CAL_SEL(_x_) ( (_x_) << 3 & (BIT(3)|BIT(4)) ) +#define BITS_LDODCDC_CAL_SEL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_LP_CTRL */ +#define BITS_LDOB_LP_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDOA_LP_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDODCDC_LP_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL0 */ +#define BITS_DCDC_CORE_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_CORE_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_CORE_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_CORE_QKRSPS ( BIT(3) ) +#define BIT_DCDC_CORE_PFM ( BIT(2) ) +#define BIT_DCDC_CORE_DCM ( BIT(1) ) +#define BIT_DCDC_CORE_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL1 */ +#define BITS_DCDC_MEM_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_MEM_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_MEM_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_MEM_QKRSPS ( BIT(3) ) +#define BIT_DCDC_MEM_PFM ( BIT(2) ) +#define BIT_DCDC_MEM_DCM ( BIT(1) ) +#define BIT_DCDC_MEM_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL2 */ +#define BITS_DCDC_GEN_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_GEN_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_GEN_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_GEN_QKRSPS ( BIT(3) ) +#define BIT_DCDC_GEN_PFM ( BIT(2) ) +#define BIT_DCDC_GEN_DCM ( BIT(1) ) +#define BIT_DCDC_GEN_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL3 */ +#define BITS_DCDC_ARM_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_ARM_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_ARM_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_ARM_QKRSPS ( BIT(3) ) +#define BIT_DCDC_ARM_PFM ( BIT(2) ) +#define BIT_DCDC_ARM_DCM ( BIT(1) ) +#define BIT_DCDC_ARM_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL4 */ +#define BITS_DCDC_WPA_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_WPA_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_WPA_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_WPA_QKRSPS ( BIT(3) ) +#define BIT_DCDC_WPA_PFM ( BIT(2) ) +#define BIT_DCDC_WPA_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL5 */ +#define BITS_DCDC_RF_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_RF_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_RF_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_RF_QKRSPS ( BIT(3) ) +#define BIT_DCDC_RF_PFM ( BIT(2) ) +#define BIT_DCDC_RF_DCM ( BIT(1) ) +#define BIT_DCDC_RF_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL6 */ +#define BITS_DCDC_CON_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_CON_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_CON_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_CON_QKRSPS ( BIT(3) ) +#define BIT_DCDC_CON_PFM ( BIT(2) ) +#define BIT_DCDC_CON_DCM ( BIT(1) ) +#define BIT_DCDC_CON_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL7 */ +#define BITS_DCDC_MEM_CF(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_DCDC_MEM_PFMAD(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_DCDC_MEM_CL_CTRL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_DCDC_CORE_DUALSEL ( BIT(7) ) +#define BIT_DCDC_CORE_MERGEEN ( BIT(6) ) +#define BITS_DCDC_CORE_CF(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_DCDC_CORE_PFMAD(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DCDC_CORE_CL_CTRL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL8 */ +#define BIT_DCDC_ARM_DUALSEL ( BIT(15) ) +#define BIT_DCDC_ARM_MERGEEN ( BIT(14) ) +#define BITS_DCDC_ARM_CF(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_DCDC_ARM_PFMAD(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_DCDC_ARM_CL_CTRL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_DCDC_GEN_CF(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_DCDC_GEN_PFMAD(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DCDC_GEN_CL_CTRL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL9 */ +#define BIT_DCDC_CON_MERGEEN ( BIT(14) ) +#define BITS_DCDC_CON_CF(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_DCDC_CON_PFMAD(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_DCDC_CON_CL_CTRL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_DCDC_RF_MERGEEN ( BIT(6) ) +#define BITS_DCDC_RF_CF(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_DCDC_RF_PFMAD(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DCDC_RF_CL_CTRL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL10 */ +#define BIT_DCDC_WPA_BPOUT_SOFTW ( BIT(15) ) +#define BITS_DCDC_WPA_VBAT_DIV(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BIT_DCDC_WPA_BPEN ( BIT(11) ) +#define BIT_DCDC_WPA_BPMODE ( BIT(10) ) +#define BIT_DCDC_WPA_DEGEN ( BIT(9) ) +#define BIT_DCDC_WPA_APTEN ( BIT(8) ) +#define BITS_DCDC_WPA_DEBC_SEL(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_DCDC_WPA_CF(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_DCDC_WPA_PFMAD(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DCDC_WPA_CL_CTRL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL11 */ +#define BIT_DCDC_3MCLKCAL_EN ( BIT(13) ) +#define BIT_DCDC_2MCLKCAL_EN ( BIT(12) ) +#define BITS_DCDC_6MFRECAL_SW(_x_) ( (_x_) << 7 & (BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DCDC_4MFRECAL_SW(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_DCDC_CLK_SP_SEL ( BIT(1) ) +#define BIT_DCDC_CLK_SP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL12 */ +#define BIT_DCDC_CORE_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_CORE_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_CORE_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_CORE_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_ARM_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_ARM_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_ARM_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_ARM_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL13 */ +#define BIT_DCDC_MEM_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_MEM_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_MEM_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_MEM_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_GEN_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_GEN_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_GEN_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_GEN_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL14 */ +#define BIT_DCDC_WPA_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_WPA_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_WPA_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_WPA_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_RF_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_RF_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_RF_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_RF_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL15 */ +#define BITS_DCDC_CAL_SEL(_x_) ( (_x_) << 13 & (BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_DCDC_CON_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_CON_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_CON_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_CON_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_SLP_WAIT_DCDCARM */ +#define BITS_SLP_IN_WAIT_DCDCARM(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_SLP_OUT_WAIT_DCDCARM(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL0 */ +#define BIT_SLP_IO_EN ( BIT(15) ) +#define BIT_SLP_DCDCRF_PD_EN ( BIT(13) ) +#define BIT_SLP_DCDCCON_PD_EN ( BIT(12) ) +#define BIT_SLP_DCDCGEN_PD_EN ( BIT(11) ) +#define BIT_SLP_DCDCWPA_PD_EN ( BIT(10) ) +#define BIT_SLP_DCDCARM_PD_EN ( BIT(9) ) +#define BIT_SLP_LDOVDD25_PD_EN ( BIT(8) ) +#define BIT_SLP_LDORF0_PD_EN ( BIT(7) ) +#define BIT_SLP_LDOEMMCCORE_PD_EN ( BIT(6) ) +#define BIT_SLP_LDOGEN0_PD_EN ( BIT(5) ) +#define BIT_SLP_LDODCXO_PD_EN ( BIT(4) ) +#define BIT_SLP_LDOGEN1_PD_EN ( BIT(3) ) +#define BIT_SLP_LDOWIFIPA_PD_EN ( BIT(2) ) +#define BIT_SLP_LDOVDD28_PD_EN ( BIT(1) ) +#define BIT_SLP_LDOVDD18_PD_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL1 */ +#define BIT_SLP_LDO_PD_EN ( BIT(15) ) +#define BIT_SLP_LDOLPREF_PD_EN ( BIT(14) ) +#define BIT_SLP_LDOSDCORE_PD_EN ( BIT(9) ) +#define BIT_SLP_LDOUSB_PD_EN ( BIT(8) ) +#define BIT_SLP_LDOCAMMOT_PD_EN ( BIT(7) ) +#define BIT_SLP_LDOCAMIO_PD_EN ( BIT(6) ) +#define BIT_SLP_LDOCAMD_PD_EN ( BIT(5) ) +#define BIT_SLP_LDOCAMA_PD_EN ( BIT(4) ) +#define BIT_SLP_LDOSIM2_PD_EN ( BIT(3) ) +#define BIT_SLP_LDOSIM1_PD_EN ( BIT(2) ) +#define BIT_SLP_LDOSIM0_PD_EN ( BIT(1) ) +#define BIT_SLP_LDOSDIO_PD_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL2 */ +#define BIT_SLP_DCDCRF_LP_EN ( BIT(14) ) +#define BIT_SLP_DCDCCON_LP_EN ( BIT(13) ) +#define BIT_SLP_DCDCCORE_LP_EN ( BIT(12) ) +#define BIT_SLP_DCDCMEM_LP_EN ( BIT(11) ) +#define BIT_SLP_DCDCARM_LP_EN ( BIT(10) ) +#define BIT_SLP_DCDCGEN_LP_EN ( BIT(9) ) +#define BIT_SLP_DCDCWPA_LP_EN ( BIT(8) ) +#define BIT_SLP_LDORF0_LP_EN ( BIT(7) ) +#define BIT_SLP_LDOEMMCCORE_LP_EN ( BIT(6) ) +#define BIT_SLP_LDOGEN0_LP_EN ( BIT(5) ) +#define BIT_SLP_LDODCXO_LP_EN ( BIT(4) ) +#define BIT_SLP_LDOGEN1_LP_EN ( BIT(3) ) +#define BIT_SLP_LDOWIFIPA_LP_EN ( BIT(2) ) +#define BIT_SLP_LDOVDD28_LP_EN ( BIT(1) ) +#define BIT_SLP_LDOVDD18_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL3 */ +#define BIT_SLP_BG_LP_EN ( BIT(15) ) +#define BIT_LDOVDD25_LP_EN_SW ( BIT(14) ) +#define BIT_LDOSDCORE_LP_EN_SW ( BIT(13) ) +#define BIT_LDOUSB_LP_EN_SW ( BIT(12) ) +#define BIT_SLP_LDOVDD25_LP_EN ( BIT(10) ) +#define BIT_SLP_LDOSDCORE_LP_EN ( BIT(9) ) +#define BIT_SLP_LDOUSB_LP_EN ( BIT(8) ) +#define BIT_SLP_LDOCAMMOT_LP_EN ( BIT(7) ) +#define BIT_SLP_LDOCAMIO_LP_EN ( BIT(6) ) +#define BIT_SLP_LDOCAMD_LP_EN ( BIT(5) ) +#define BIT_SLP_LDOCAMA_LP_EN ( BIT(4) ) +#define BIT_SLP_LDOSIM2_LP_EN ( BIT(3) ) +#define BIT_SLP_LDOSIM1_LP_EN ( BIT(2) ) +#define BIT_SLP_LDOSIM0_LP_EN ( BIT(1) ) +#define BIT_SLP_LDOSDIO_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL4 */ +#define BIT_LDOCAMIO_LP_EN_SW ( BIT(15) ) +#define BIT_LDOCAMMOT_LP_EN_SW ( BIT(14) ) +#define BIT_LDOCAMD_LP_EN_SW ( BIT(13) ) +#define BIT_LDOCAMA_LP_EN_SW ( BIT(12) ) +#define BIT_LDOSIM2_LP_EN_SW ( BIT(11) ) +#define BIT_LDOSIM1_LP_EN_SW ( BIT(10) ) +#define BIT_LDOSIM0_LP_EN_SW ( BIT(9) ) +#define BIT_LDOSDIO_LP_EN_SW ( BIT(8) ) +#define BIT_LDORF0_LP_EN_SW ( BIT(7) ) +#define BIT_LDOEMMCCORE_LP_EN_SW ( BIT(6) ) +#define BIT_LDOGEN0_LP_EN_SW ( BIT(5) ) +#define BIT_LDODCXO_LP_EN_SW ( BIT(4) ) +#define BIT_LDOGEN1_LP_EN_SW ( BIT(3) ) +#define BIT_LDOWIFIPA_LP_EN_SW ( BIT(2) ) +#define BIT_LDOVDD28_LP_EN_SW ( BIT(1) ) +#define BIT_LDOVDD18_LP_EN_SW ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_AUD_SLP_CTRL */ +#define BIT_SLP_AUD_PMUR1_PD_EN ( BIT(14) ) +#define BIT_SLP_AUD_PA_SW_PD_EN ( BIT(13) ) +#define BIT_SLP_AUD_PA_LDO_PD_EN ( BIT(12) ) +#define BIT_SLP_AUD_PA_PD_EN ( BIT(11) ) +#define BIT_SLP_AUD_OVP_PD_PD_EN ( BIT(10) ) +#define BIT_SLP_AUD_OVP_LDO_PD_EN ( BIT(9) ) +#define BIT_SLP_AUD_LDOCG_PD_PD_EN ( BIT(8) ) +#define BIT_SLP_AUD_VB_PD_EN ( BIT(7) ) +#define BIT_SLP_AUD_VBO_PD_EN ( BIT(6) ) +#define BIT_SLP_AUD_HEADMICBIAS_PD_EN ( BIT(5) ) +#define BIT_SLP_AUD_HEADMIC_SLEEP_PD_EN ( BIT(4) ) +#define BIT_SLP_AUD_PLGPD_PD_EN ( BIT(3) ) +#define BIT_SLP_AUD_VB_NLEAK_PD ( BIT(2) ) +#define BITS_SLP_AUD_PMUR0_PD_EN(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL0 */ +#define BITS_SLP_DCDCCORE_VOL_DROP_CNT(_x_)( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_PWR_OFF_SEQ_EN ( BIT(2) ) +#define BIT_DCDC_CORE_SLP_OUT_STEP_EN ( BIT(1) ) +#define BIT_DCDC_CORE_SLP_IN_STEP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL1 */ +#define BITS_DCDC_CORE_CAL_DS_SW(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CTRL_DS_SW(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL2 */ +#define BITS_DCDC_CORE_CTRL_SLP_STEP3(_x_)( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_DCDC_CORE_CTRL_SLP_STEP2(_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CTRL_SLP_STEP1(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL3 */ +#define BITS_DCDC_CORE_CTRL_SLP_STEP5(_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CTRL_SLP_STEP4(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL4 */ +#define BITS_DCDC_CORE_CAL_SLP_STEP3(_x_)( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_DCDC_CORE_CAL_SLP_STEP2(_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CAL_SLP_STEP1(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL5 */ +#define BITS_DCDC_CORE_CAL_SLP_STEP5(_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CAL_SLP_STEP4(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SEL */ +#define BIT_LDO_GEN0_SW_SEL ( BIT(13) ) +#define BIT_LDO_GEN1_SW_SEL ( BIT(12) ) +#define BIT_LDO_RF0_SW_SEL ( BIT(11) ) +#define BIT_LDO_VDD18_SW_SEL ( BIT(10) ) +#define BIT_LDO_VDD28_SW_SEL ( BIT(9) ) +#define BIT_LDO_DCXO_SW_SEL ( BIT(8) ) +#define BIT_LDO_EMMCCORE_SW_SEL ( BIT(7) ) +#define BIT_LDO_VDD25_SW_SEL ( BIT(6) ) +#define BIT_DCDC_RF_SW_SEL ( BIT(5) ) +#define BIT_DCDC_GEN_SW_SEL ( BIT(4) ) +#define BIT_DCDC_MEM_SW_SEL ( BIT(3) ) +#define BIT_DCDC_ARM_SW_SEL ( BIT(2) ) +#define BIT_DCDC_CORE_SLP_SW_SEL ( BIT(1) ) +#define BIT_DCDC_CORE_NOR_SW_SEL ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN0 */ +#define BIT_LDO_XTL_EN ( BIT(15) ) +#define BIT_LDO_GEN0_EXT_XTL0_EN ( BIT(14) ) +#define BIT_LDO_GEN0_XTL1_EN ( BIT(13) ) +#define BIT_LDO_GEN0_XTL0_EN ( BIT(12) ) +#define BIT_LDO_GEN1_EXT_XTL0_EN ( BIT(11) ) +#define BIT_LDO_GEN1_XTL1_EN ( BIT(10) ) +#define BIT_LDO_GEN1_XTL0_EN ( BIT(9) ) +#define BIT_LDO_DCXO_EXT_XTL0_EN ( BIT(8) ) +#define BIT_LDO_DCXO_XTL1_EN ( BIT(7) ) +#define BIT_LDO_DCXO_XTL0_EN ( BIT(6) ) +#define BIT_LDO_VDD18_EXT_XTL0_EN ( BIT(5) ) +#define BIT_LDO_VDD18_XTL1_EN ( BIT(4) ) +#define BIT_LDO_VDD18_XTL0_EN ( BIT(3) ) +#define BIT_LDO_VDD28_EXT_XTL0_EN ( BIT(2) ) +#define BIT_LDO_VDD28_XTL1_EN ( BIT(1) ) +#define BIT_LDO_VDD28_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN1 */ +#define BIT_LDO_RF0_EXT_XTL0_EN ( BIT(14) ) +#define BIT_LDO_RF0_XTL1_EN ( BIT(13) ) +#define BIT_LDO_RF0_XTL0_EN ( BIT(12) ) +#define BIT_LDO_WIFIPA_EXT_XTL0_EN ( BIT(11) ) +#define BIT_LDO_WIFIPA_XTL1_EN ( BIT(10) ) +#define BIT_LDO_WIFIPA_XTL0_EN ( BIT(9) ) +#define BIT_LDO_SIM2_EXT_XTL0_EN ( BIT(8) ) +#define BIT_LDO_SIM2_XTL1_EN ( BIT(7) ) +#define BIT_LDO_SIM2_XTL0_EN ( BIT(6) ) +#define BIT_LDO_SIM1_EXT_XTL0_EN ( BIT(5) ) +#define BIT_LDO_SIM1_XTL1_EN ( BIT(4) ) +#define BIT_LDO_SIM1_XTL0_EN ( BIT(3) ) +#define BIT_LDO_SIM0_EXT_XTL0_EN ( BIT(2) ) +#define BIT_LDO_SIM0_XTL1_EN ( BIT(1) ) +#define BIT_LDO_SIM0_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN2 */ +#define BIT_LDO_VDD25_EXT_XTL0_EN ( BIT(11) ) +#define BIT_LDO_VDD25_XTL1_EN ( BIT(10) ) +#define BIT_LDO_VDD25_XTL0_EN ( BIT(9) ) +#define BIT_DCDC_RF_EXT_XTL0_EN ( BIT(8) ) +#define BIT_DCDC_RF_XTL1_EN ( BIT(7) ) +#define BIT_DCDC_RF_XTL0_EN ( BIT(6) ) +#define BIT_XO_EXT_XTL0_EN ( BIT(5) ) +#define BIT_XO_XTL1_EN ( BIT(4) ) +#define BIT_XO_XTL0_EN ( BIT(3) ) +#define BIT_BG_EXT_XTL0_EN ( BIT(2) ) +#define BIT_BG_XTL1_EN ( BIT(1) ) +#define BIT_BG_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN3 */ +#define BIT_DCDC_CON_EXT_XTL0_EN ( BIT(14) ) +#define BIT_DCDC_CON_XTL1_EN ( BIT(13) ) +#define BIT_DCDC_CON_XTL0_EN ( BIT(12) ) +#define BIT_DCDC_WPA_EXT_XTL0_EN ( BIT(11) ) +#define BIT_DCDC_WPA_XTL1_EN ( BIT(10) ) +#define BIT_DCDC_WPA_XTL0_EN ( BIT(9) ) +#define BIT_DCDC_MEM_EXT_XTL0_EN ( BIT(8) ) +#define BIT_DCDC_MEM_XTL1_EN ( BIT(7) ) +#define BIT_DCDC_MEM_XTL0_EN ( BIT(6) ) +#define BIT_DCDC_GEN_EXT_XTL0_EN ( BIT(5) ) +#define BIT_DCDC_GEN_XTL1_EN ( BIT(4) ) +#define BIT_DCDC_GEN_XTL0_EN ( BIT(3) ) +#define BIT_DCDC_CORE_EXT_XTL0_EN ( BIT(2) ) +#define BIT_DCDC_CORE_XTL1_EN ( BIT(1) ) +#define BIT_DCDC_CORE_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_32KLESS_CTRL0 */ +#define BIT_RC_MODE_WR_ACK_FLAG ( BIT(14) ) +#define BIT_XO_LOW_CUR_FLAG ( BIT(13) ) +#define BIT_XO_LOW_CUR_FRC_RTCSET ( BIT(12) ) +#define BIT_XO_LOW_CUR_FRC_RTCCLR ( BIT(11) ) +#define BIT_RC_MODE_WR_ACK_FLAG_CLR ( BIT(10) ) +#define BIT_XO_LOW_CUR_FLAG_CLR ( BIT(9) ) +#define BIT_XO_LOW_CUR_CNT_CLR ( BIT(8) ) +#define BIT_LDO_DCXO_LP_PD_RTCSET ( BIT(7) ) +#define BIT_LDO_DCXO_LP_PD_RTCCLR ( BIT(6) ) +#define BIT_SLP_XO_LOW_CUR_EN ( BIT(5) ) +#define BIT_XO_LOW_CUR_EN ( BIT(3) ) +#define BIT_EXT_32K_PD ( BIT(2) ) +#define BIT_RC_32K_SEL ( BIT(1) ) +#define BIT_RC_32K_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_32KLESS_CTRL1 */ +#define BITS_RC_MODE(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_32KLESS_CTRL2 */ +#define BITS_XO_LOW_CUR_CNT_LOW(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_32KLESS_CTRL3 */ +#define BITS_XO_LOW_CUR_CNT_HIGH(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_AUXAD_CTL */ +#define BIT_AUXAD_CURRENTSEN_EN ( BIT(6) ) +#define BIT_AUXAD_CURRENTSEL ( BIT(5) ) +#define BITS_AUXAD_CURRENT_IBS(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_XTL_WAIT_CTRL */ +#define BIT_SLP_XTLBUF_PD_EN ( BIT(9) ) +#define BIT_XTL_EN ( BIT(8) ) +#define BITS_XTL_WAIT(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_RGB_CTRL */ +#define BIT_RTC_PWM0_EN ( BIT(15) ) +#define BIT_PWM0_EN ( BIT(14) ) +#define BIT_IB_REX_EN ( BIT(12) ) +#define BIT_IB_TRIM_EM_SEL ( BIT(11) ) +#define BITS_RGB_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) ) +#define BIT_SLP_RGB_PD_EN ( BIT(2) ) +#define BIT_RGB_PD_HW_EN ( BIT(1) ) +#define BIT_RGB_PD_SW ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_WHTLED_CTRL */ +#define BITS_IB_TRIM(_x_) ( (_x_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_WHTLED_SERIES_EN ( BIT(8) ) +#define BIT_WHTLED_PD_SEL ( BIT(7) ) +#define BIT_WHTLED_BOOST_EN ( BIT(8) ) +#define BITS_WHTLED_V(_x_) ( (_x_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_WHTLED_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_KPLED_CTRL */ +#define BITS_KPLED_V(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_KPLED_PD ( BIT(11) ) +#define BIT_KPLED_PULLDOWN_EN ( BIT(10) ) +#define BIT_SLP_LDOKPLED_PD_EN ( BIT(9) ) +#define BIT_LDO_KPLED_PD ( BIT(8) ) +#define BITS_LDO_KPLED_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_VIBR_CTRL0 */ +#define BITS_CUR_DRV_CAL_SEL(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BIT_VIBR_PULLDOWN_EN ( BIT(11) ) +#define BIT_VIBR_PULLUP_EN ( BIT(10) ) +#define BIT_SLP_LDOVIBR_PD_EN ( BIT(9) ) +#define BIT_LDO_VIBR_PD ( BIT(8) ) +#define BITS_LDO_VIBR_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_AUDIO_CTRL0 */ +#define BIT_AUD_SLP_APP_RST_EN ( BIT(15) ) +#define BITS_CLK_AUD_HBD_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_CLK_AUD_LOOP_INV_EN ( BIT(4) ) +#define BIT_CLK_AUDIF_TX_INV_EN ( BIT(3) ) +#define BIT_CLK_AUDIF_RX_INV_EN ( BIT(2) ) +#define BIT_CLK_AUD_6P5M_TX_INV_EN ( BIT(1) ) +#define BIT_CLK_AUD_6P5M_RX_INV_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_AUDIO_CTRL1 */ +#define BIT_IMPD_ADC_SOFT_RST ( BIT(7) ) +#define BIT_HEAD_INSERT_EIC_EN ( BIT(6) ) +#define BIT_AUDIO_CHP_CLK_DIV_EN ( BIT(5) ) +#define BITS_AUDIO_CHP_CLK_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL0 */ +#define BIT_CHGLDO_DIS ( BIT(15) ) +#define BITS_CHGR_CV_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CHGR_END_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BIT_CHGR_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL1 */ +#define BITS_CHGR_CC_I(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_VBAT_OVP_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_VCHG_OVP_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL2 */ +#define BIT_CHGR_INT_EN ( BIT(15) ) +#define BIT_CHGR_DRV ( BIT(7) ) +#define BIT_CHGR_OSC ( BIT(6) ) +#define BITS_CHGR_DPM(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CHGR_ITERM(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BIT_CHGR_CC_EN ( BIT(1) ) +#define BIT_RECHG ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_DET_FGU_CTRL */ +#define BIT_FGUA_SOFT_RST ( BIT(13) ) +#define BIT_LDO_FGU_PD ( BIT(12) ) +#define BIT_SD_CHOP_CAP_EN ( BIT(8) ) +#define BITS_SD_CLK_P(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BIT_SD_DCOFFSET_EN ( BIT(5) ) +#define BIT_SD_CHOP_EN ( BIT(4) ) +#define BIT_DP_DM_AUX_EN ( BIT(1) ) +#define BIT_DP_DM_SW_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_STATUS */ +#define BIT_CHG_DET_DONE ( BIT(11) ) +#define BIT_DP_LOW ( BIT(10) ) +#define BIT_DCP_DET ( BIT(9) ) +#define BIT_CHG_DET ( BIT(8) ) +#define BIT_SDP_INT ( BIT(7) ) +#define BIT_DCP_INT ( BIT(6) ) +#define BIT_CDP_INT ( BIT(5) ) +#define BIT_CHGR_CV_STATUS ( BIT(4) ) +#define BIT_CHGR_ON ( BIT(3) ) +#define BIT_CHGR_INT ( BIT(2) ) +#define BIT_VBAT_OVI ( BIT(1) ) +#define BIT_VCHG_OVI ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_MIXED_CTRL0 */ +#define BIT_PTEST_PD_RTCSET ( BIT(15) ) +#define BIT_DCDC_V_CTRL_MODE ( BIT(14) ) +#define BIT_LDO_RAMP_EN ( BIT(13) ) +#define BIT_BG_LP_EN ( BIT(12) ) +#define BITS_VBAT_CRASH_V(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BIT_OVLO_EN ( BIT(9) ) +#define BITS_OVLO_CAL(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_OVLO_V(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_OVLO_T(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_MIXED_CTRL1 */ +#define BITS_XOSC32K_CTL(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_BATON_T(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BIT_BATDET_LDO_SEL ( BIT(9) ) +#define BIT_THM_CHIP_PD_FLAG ( BIT(8) ) +#define BIT_THM_CHIP_PD_FLAG_CLR ( BIT(7) ) +#define BITS_THM_CAL_SEL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)) ) +#define BIT_THM_AUTO_PD_EN ( BIT(4) ) +#define BIT_ALL_GPI_DEB ( BIT(3) ) +#define BIT_GPI_DEBUG_EN ( BIT(2) ) +#define BIT_ALL_INT_DEB ( BIT(1) ) +#define BIT_INT_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_SWRST_CTRL */ +#define BIT_POR_RTC_PD ( BIT(15) ) +#define BITS_POR_RTC_I(_x_) ( (_x_) << 13 & (BIT(13)|BIT(14)) ) +#define BIT_SW_RST_GEN1_PD_EN ( BIT(12) ) +#define BIT_SW_RST_GEN0_PD_EN ( BIT(11) ) +#define BIT_EXT_RSTN_PD_EN ( BIT(10) ) +#define BIT_PB_7S_RST_PD_EN ( BIT(9) ) +#define BIT_SW_RST_EMMCCORE_PD_EN ( BIT(8) ) +#define BIT_KEY2_7S_RST_EN ( BIT(7) ) +#define BIT_WDG_RST_PD_EN ( BIT(6) ) +#define BITS_SW_RST_PD_THRESHOLD(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register ANA_REG_GLB_POR_RST_MONITOR */ +#define BITS_POR_RST_MONITOR(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_WDG_RST_MONITOR */ +#define BITS_WDG_RST_MONITOR(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_POR_PIN_RST_MONITOR */ +#define BITS_POR_PIN_RST_MONITOR(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_POR_SRC_FLAG */ +#define BIT_POR_SW_FORCE_ON ( BIT(15) ) +#define BITS_POR_SRC_FLAG(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_POR_7S_CTRL */ +#define BIT_PBINT_7S_FLAG_CLR ( BIT(15) ) +#define BIT_EXT_RSTN_FLAG_CLR ( BIT(14) ) +#define BIT_CHGR_INT_FLAG_CLR ( BIT(13) ) +#define BIT_PBINT2_FLAG_CLR ( BIT(12) ) +#define BIT_PBINT_FLAG_CLR ( BIT(11) ) +#define BIT_PBINT_7S_RST_SWMODE ( BIT(8) ) +#define BITS_PBINT_7S_RST_THRESHOLD(_x_)( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_PBINT_7S_AUTO_ON_EN ( BIT(2) ) +#define BIT_PBINT_7S_RST_DISABLE ( BIT(1) ) +#define BIT_PBINT_7S_RST_MODE ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_HWRST_RTC */ +#define BITS_HWRST_RTC_REG_STS(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_HWRST_RTC_REG_SET(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_CHIP_ID_LOW */ +#define BITS_CHIP_ID_LOW(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_CHIP_ID_HIGH */ +#define BITS_CHIP_ID_HIGH(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_ARM_MF_REG */ +#define BITS_ARM_MF_REG(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_ARCH_EN */ +#define BIT_ARCH_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_MCU_WR_PROT_VALUE */ +#define BIT_MCU_WR_PROT ( BIT(15) ) +#define BITS_MCU_WR_PROT_VALUE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_PWR_WR_PROT_VALUE */ +#define BIT_PWR_WR_PROT ( BIT(15) ) +#define BITS_PWR_WR_PROT_VALUE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_SMPL_CTRL0 */ +#define BITS_SMPL_MODE(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_SMPL_CTRL1 */ +#define BIT_SMPL_PWR_ON_FLAG ( BIT(15) ) +#define BIT_SMPL_MODE_WR_ACK_FLAG ( BIT(14) ) +#define BIT_SMPL_PWR_ON_FLAG_CLR ( BIT(13) ) +#define BIT_SMPL_MODE_WR_ACK_FLAG_CLR ( BIT(12) ) +#define BIT_SMPL_PWR_ON_SET ( BIT(11) ) +#define BIT_SMPL_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_RTC_RST0 */ +#define BITS_RTC_CLK_FLAG_SET(_x_) ( (_x_) << 15 & (BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_RTC_RST1 */ +#define BITS_RTC_CLK_FLAG_CLR(_x_) ( (_x_) << 15 & (BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_RTC_RST2 */ +#define BITS_RTC_CLK_FLAG_RTC(_x_) ( (_x_) << 15 & (BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SHPT_PD1 */ +#define BIT_LDO_USB_SHPT_PD ( BIT(12) ) +#define BIT_LDO_DCXO_SHPT_PD ( BIT(11) ) +#define BIT_LDO_WIFIPA_SHPT_PD ( BIT(10) ) +#define BIT_LDO_VDD25_SHPT_PD ( BIT(9) ) +#define BIT_LDO_VDD28_SHPT_PD ( BIT(8) ) +#define BIT_LDO_SDIO_SHPT_PD ( BIT(7) ) +#define BIT_LDO_SDCORE_SHPT_PD ( BIT(6) ) +#define BIT_LDO_EMMCCORE_SHPT_PD ( BIT(5) ) +#define BIT_LDO_SIM2_SHPT_PD ( BIT(4) ) +#define BIT_LDO_SIM1_SHPT_PD ( BIT(3) ) +#define BIT_LDO_SIM0_SHPT_PD ( BIT(2) ) +#define BIT_LDO_CAMMOT_SHPT_PD ( BIT(1) ) +#define BIT_LDO_CAMA_SHPT_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SHPT_PD2 */ +#define BIT_LDO_RF0_SHPT_PD ( BIT(7) ) +#define BIT_LDO_GEN1_SHPT_PD ( BIT(6) ) +#define BIT_LDO_GEN0_SHPT_PD ( BIT(5) ) +#define BIT_LDO_CAMD_SHPT_PD ( BIT(4) ) +#define BIT_LDO_VDD18_SHPT_PD ( BIT(3) ) +#define BIT_LDO_CAMIO_SHPT_PD ( BIT(2) ) +#define BIT_LDO_KPLED_SHPT_PD ( BIT(1) ) +#define BIT_LDO_VIBR_SHPT_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_BATDET_CUR_CTRL */ +#define BIT_BATDET_CUR_EN ( BIT(4) ) +#define BITS_BATDET_CUR_I(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register ANA_REG_GLB_RTC_CLK_STOP */ +#define BIT_RTC_CLK_STOP_FLAG ( BIT(7) ) +#define BITS_RTC_CLK_STOP_THRESHOLD(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) + +/* bits definitions for register ANA_REG_GLB_VBAT_DROP_CNT */ +#define BITS_VBAT_DROP_CNT(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_DISCHRG */ +#define BITS_DCDC_ARM_DISCHRG(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_DCDC_CORE_DISCHRG(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_DCDC_MEM_DISCHRG(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_DCDC_GEN_DISCHRG(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_DCDC_RF_DISCHRG(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_DCDC_CON_DISCHRG(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DCDC_WPA_DISCHRG(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CORE_ADI */ +#define BITS_DCDC_CORE_CTL_SW_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CAL_SW_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_ARM_ADI */ +#define BITS_DCDC_ARM_CTL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_ARM_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_MEM_ADI */ +#define BITS_DCDC_MEM_CTRL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_MEM_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_GEN_ADI */ +#define BITS_DCDC_GEN_CTRL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_GEN_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_WPA_ADI */ +#define BITS_DCDC_WPA_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_WPA_DCM_ADI */ +#define BIT_DCDC_WPA_DCM_ADI ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CON_ADI */ +#define BITS_DCDC_CON_CTRL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CON_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_RF_ADI */ +#define BITS_DCDC_RF_CTRL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_RF_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* vars definitions for controller ANA_REGS_GLB */ + +#endif /* __ANA_REGS_GLB_H__ */ diff --git a/include/soc/sprd/chip_x35l/__regs_aon_apb_rf.h b/include/soc/sprd/chip_x35l/__regs_aon_apb_rf.h new file mode 100755 index 00000000..776e4ab1 --- /dev/null +++ b/include/soc/sprd/chip_x35l/__regs_aon_apb_rf.h @@ -0,0 +1,674 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_AON_APB_HEADFILE_H__ +#define __H_REGS_AON_APB_HEADFILE_H__ __FILE__ + +#define REGS_AON_APB_ + +/* registers definitions for AON_APB_ */ +#define REG_AON_APB_APB_EB0 SCI_ADDR(REGS_AON_APB_BASE, 0x0000) +#define REG_AON_APB_APB_EB1 SCI_ADDR(REGS_AON_APB_BASE, 0x0004) +#define REG_AON_APB_APB_RST0 SCI_ADDR(REGS_AON_APB_BASE, 0x0008) +#define REG_AON_APB_APB_RST1 SCI_ADDR(REGS_AON_APB_BASE, 0x000C) +#define REG_AON_APB_APB_RTC_EB SCI_ADDR(REGS_AON_APB_BASE, 0x0010) +#define REG_AON_APB_REC_26MHZ_BUF_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0014) +#define REG_AON_APB_SINDRV_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0018) +#define REG_AON_APB_ADA_SEL_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x001C) +#define REG_AON_APB_VBC_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0020) +#define REG_AON_APB_PWR_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0024) +#define REG_AON_APB_TS_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0028) +#define REG_AON_APB_BOOT_MODE SCI_ADDR(REGS_AON_APB_BASE, 0x002C) +#define REG_AON_APB_BB_BG_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0030) +#define REG_AON_APB_CP_ARM_JTAG_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0034) +#define REG_AON_APB_PLL_SOFT_CNT_DONE SCI_ADDR(REGS_AON_APB_BASE, 0x0038) +#define REG_AON_APB_DCXO_LC_REG0 SCI_ADDR(REGS_AON_APB_BASE, 0x003C) +#define REG_AON_APB_DCXO_LC_REG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0040) +#define REG_AON_APB_MPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0044) +#define REG_AON_APB_MPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0048) +#define REG_AON_APB_DPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x004C) +#define REG_AON_APB_DPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0050) +#define REG_AON_APB_TWPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0054) +#define REG_AON_APB_TWPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0058) +#define REG_AON_APB_LTEPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x005C) +#define REG_AON_APB_LTEPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0060) +#define REG_AON_APB_LVDSDISPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0064) +#define REG_AON_APB_LVDSDISPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0068) +#define REG_AON_APB_AON_REG_PROT SCI_ADDR(REGS_AON_APB_BASE, 0x006C)/*Big endian protect register*/ +#define REG_AON_APB_LDSP_BOOT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x0070)/*DSP boot enable*/ +#define REG_AON_APB_LDSP_BOOT_VEC SCI_ADDR(REGS_AON_APB_BASE, 0x0074)/*DSP boot vector*/ +#define REG_AON_APB_LDSP_RST SCI_ADDR(REGS_AON_APB_BASE, 0x0078)/*DSP reset*/ +#define REG_AON_APB_LDSP_MTX_CTRL1 SCI_ADDR(REGS_AON_APB_BASE, 0x007C) +#define REG_AON_APB_LDSP_MTX_CTRL2 SCI_ADDR(REGS_AON_APB_BASE, 0x0080) +#define REG_AON_APB_LDSP_MTX_CTRL3 SCI_ADDR(REGS_AON_APB_BASE, 0x0084) +#define REG_AON_APB_AON_CGM_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0088) +#define REG_AON_APB_LACC_MTX_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x008C) +#define REG_AON_APB_CORTEX_MTX_CTRL1 SCI_ADDR(REGS_AON_APB_BASE, 0x0090) +#define REG_AON_APB_CORTEX_MTX_CTRL2 SCI_ADDR(REGS_AON_APB_BASE, 0x0094) +#define REG_AON_APB_CORTEX_MTX_CTRL3 SCI_ADDR(REGS_AON_APB_BASE, 0x0098)/*DSP reset*/ +#define REG_AON_APB_CA5_TCLK_DLY_LEN SCI_ADDR(REGS_AON_APB_BASE, 0x009C)/*APB clock control*/ +#define REG_AON_APB_CCIR_RCVR_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0100)/*APB clock control*/ +#define REG_AON_APB_AON_CHIP_ID_H SCI_ADDR(REGS_AON_APB_BASE, 0x00F8) +#define REG_AON_APB_AON_CHIP_ID SCI_ADDR(REGS_AON_APB_BASE, 0x00FC) +#define REG_AON_APB_AON_CHIP_ID_L REG_AON_APB_AON_CHIP_ID +#define REG_AON_APB_PLL_BG_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0108) +#define REG_AON_APB_LVDSDIS_SEL SCI_ADDR(REGS_AON_APB_BASE, 0x010C) +#define REG_AON_APB_DJTAG_MUX_SEL SCI_ADDR(REGS_AON_APB_BASE, 0x0110) +#define REG_AON_APB_ARM7_SYS_SOFT_RST SCI_ADDR(REGS_AON_APB_BASE, 0x0114) +#define REG_AON_APB_CP1_CP0_ADDR_MSB SCI_ADDR(REGS_AON_APB_BASE, 0x0118) +#define REG_AON_APB_AON_DMA_INT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x011C) +#define REG_AON_APB_EMC_AUTO_GATE_EN SCI_ADDR(REGS_AON_APB_BASE, 0x0120) +#define REG_AON_APB_ARM7_CFG_BUS SCI_ADDR(REGS_AON_APB_BASE, 0x0124) +#define REG_AON_APB_RTC4M_0_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0128) +#define REG_AON_APB_RTC4M_1_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x012C) +#define REG_AON_APB_APB_RST2 SCI_ADDR(REGS_AON_APB_BASE, 0x0130) +#define REG_AON_APB_AP_WPROT_EN1 SCI_ADDR(REGS_AON_APB_BASE, 0x3004) +#define REG_AON_APB_CP0_WPROT_EN1 SCI_ADDR(REGS_AON_APB_BASE, 0x3008) +#define REG_AON_APB_CP1_WPROT_EN1 SCI_ADDR(REGS_AON_APB_BASE, 0x300C) +#define REG_AON_APB_IO_DLY_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x3014) +#define REG_AON_APB_AP_WPROT_EN0 SCI_ADDR(REGS_AON_APB_BASE, 0x3018) +#define REG_AON_APB_CP0_WPROT_EN0 SCI_ADDR(REGS_AON_APB_BASE, 0x3020) +#define REG_AON_APB_CP1_WPROT_EN0 SCI_ADDR(REGS_AON_APB_BASE, 0x3024) +#define REG_AON_APB_PMU_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x302C) +#define REG_AON_APB_THM_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3030) +#define REG_AON_APB_AP_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3034) +#define REG_AON_APB_CA7_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3038) +#define REG_AON_APB_BOND_OPT0 SCI_ADDR(REGS_AON_APB_BASE, 0x303C) +#define REG_AON_APB_BOND_OPT1 SCI_ADDR(REGS_AON_APB_BASE, 0x3040) +#define REG_AON_APB_RES_REG0 SCI_ADDR(REGS_AON_APB_BASE, 0x3044) +#define REG_AON_APB_RES_REG1 SCI_ADDR(REGS_AON_APB_BASE, 0x3048) +#define REG_AON_APB_AON_QOS_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x304C) +#define REG_AON_APB_BB_LDO_CAL_START SCI_ADDR(REGS_AON_APB_BASE, 0x3050) +#define REG_AON_APB_AON_MTX_PROT_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3058) +#define REG_AON_APB_LVDS_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3060) +#define REG_AON_APB_PLL_LOCK_OUT_SEL SCI_ADDR(REGS_AON_APB_BASE, 0x3064) +#define REG_AON_APB_RTC4M_RC_VAL SCI_ADDR(REGS_AON_APB_BASE, 0x3068) +#define REG_AON_APB_AON_APB_RSV SCI_ADDR(REGS_AON_APB_BASE, 0x30F0) + +/* bits definitions for register REG_AON_APB_APB_EB0 */ +#define BIT_I2C_EB ( BIT(31) ) +#define BIT_CA7_DAP_EB ( BIT(30) ) +#define BIT_CA7_TS1_EB ( BIT(29) ) +#define BIT_CA7_TS0_EB ( BIT(28) ) +#define BIT_GPU_EB ( BIT(27) ) +#define BIT_AON_CKG_EB ( BIT(26) ) +#define BIT_MM_EB ( BIT(25) ) +#define BIT_AP_WDG_EB ( BIT(24) ) +#define BIT_MSPI_EB ( BIT(23) ) +#define BIT_SPLK_EB ( BIT(22) ) +#define BIT_IPI_EB ( BIT(21) ) +#define BIT_PIN_EB ( BIT(20) ) +#define BIT_VBC_EB ( BIT(19) ) +#define BIT_AUD_EB ( BIT(18) ) +#define BIT_AUDIF_EB ( BIT(17) ) +#define BIT_ADI_EB ( BIT(16) ) +#define BIT_INTC_EB ( BIT(15) ) +#define BIT_EIC_EB ( BIT(14) ) +#define BIT_EFUSE_EB ( BIT(13) ) +#define BIT_AP_TMR0_EB ( BIT(12) ) +#define BIT_AON_TMR_EB ( BIT(11) ) +#define BIT_AP_SYST_EB ( BIT(10) ) +#define BIT_AON_SYST_EB ( BIT(9) ) +#define BIT_KPD_EB ( BIT(8) ) +#define BIT_PWM3_EB ( BIT(7) ) +#define BIT_PWM2_EB ( BIT(6) ) +#define BIT_PWM1_EB ( BIT(5) ) +#define BIT_PWM0_EB ( BIT(4) ) +#define BIT_GPIO_EB ( BIT(3) ) +#define BIT_TPC_EB ( BIT(2) ) +#define BIT_FM_EB ( BIT(1) ) +#define BIT_ADC_EB ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_APB_EB1 */ +#if defined(CONFIG_MACH_SP9830I) +#define BIT_CODEC_EB (BIT(28)) +#endif +#define BIT_ORP_JTAG_EB ( BIT(27) ) +#define BIT_CA5_TS0_EB ( BIT(26) ) +#define BIT_DEF_EB ( BIT(25) ) +#define BIT_LVDS_PLL_DIV_EN ( BIT(24) ) +#define BIT_ARM7_JTAG_EB ( BIT(23) ) +#define BIT_AON_DMA_EB ( BIT(22) ) +#define BIT_MBOX_EB ( BIT(21) ) +#define BIT_DJTAG_EB ( BIT(20) ) +#define BIT_RTC4M1_CAL_EB ( BIT(19) ) +#define BIT_RTC4M0_CAL_EB ( BIT(18) ) +#define BIT_MDAR_EB ( BIT(17) ) +#define BIT_LVDS_TCXO_EB ( BIT(16) ) +#define BIT_LVDS_TRX_EB ( BIT(15) ) +#define BIT_CA5_DAP_EB ( BIT(14) ) +#define BIT_GSP_EMC_EB ( BIT(13) ) +#define BIT_ZIP_EMC_EB ( BIT(12) ) +#define BIT_DISP_EMC_EB ( BIT(11) ) +#define BIT_AP_TMR2_EB ( BIT(10) ) +#define BIT_AP_TMR1_EB ( BIT(9) ) +#define BIT_CA7_WDG_EB ( BIT(8) ) +#define BIT_AVS_EB ( BIT(6) ) +#define BIT_PROBE_EB ( BIT(5) ) +#define BIT_AUX2_EB ( BIT(4) ) +#define BIT_AUX1_EB ( BIT(3) ) +#define BIT_AUX0_EB ( BIT(2) ) +#define BIT_THM_EB ( BIT(1) ) +#define BIT_PMU_EB ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_APB_RST0 */ +#define BIT_CA5_TS0_SOFT_RST ( BIT(31) ) +#define BIT_I2C_SOFT_RST ( BIT(30) ) +#define BIT_CA7_TS1_SOFT_RST ( BIT(29) ) +#define BIT_CA7_TS0_SOFT_RST ( BIT(28) ) +#define BIT_DAP_MTX_SOFT_RST ( BIT(27) ) +#define BIT_MSPI1_SOFT_RST ( BIT(26) ) +#define BIT_MSPI0_SOFT_RST ( BIT(25) ) +#define BIT_SPLK_SOFT_RST ( BIT(24) ) +#define BIT_IPI_SOFT_RST ( BIT(23) ) +#define BIT_AON_CKG_SOFT_RST ( BIT(22) ) +#define BIT_PIN_SOFT_RST ( BIT(21) ) +#define BIT_VBC_SOFT_RST ( BIT(20) ) +#define BIT_AUD_SOFT_RST ( BIT(19) ) +#define BIT_AUDIF_SOFT_RST ( BIT(18) ) +#define BIT_ADI_SOFT_RST ( BIT(17) ) +#define BIT_INTC_SOFT_RST ( BIT(16) ) +#define BIT_EIC_SOFT_RST ( BIT(15) ) +#define BIT_EFUSE_SOFT_RST ( BIT(14) ) +#define BIT_AP_WDG_SOFT_RST ( BIT(13) ) +#define BIT_AP_TMR0_SOFT_RST ( BIT(12) ) +#define BIT_AON_TMR_SOFT_RST ( BIT(11) ) +#define BIT_AP_SYST_SOFT_RST ( BIT(10) ) +#define BIT_AON_SYST_SOFT_RST ( BIT(9) ) +#define BIT_KPD_SOFT_RST ( BIT(8) ) +#define BIT_PWM3_SOFT_RST ( BIT(7) ) +#define BIT_PWM2_SOFT_RST ( BIT(6) ) +#define BIT_PWM1_SOFT_RST ( BIT(5) ) +#define BIT_PWM0_SOFT_RST ( BIT(4) ) +#define BIT_GPIO_SOFT_RST ( BIT(3) ) +#define BIT_TPC_SOFT_RST ( BIT(2) ) +#define BIT_FM_SOFT_RST ( BIT(1) ) +#define BIT_ADC_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_APB_RST1 */ +#define BIT_RTC4M_ANA_SOFT_RST ( BIT(31) ) +#define BIT_DEF_SLV_INT_SOFT_CLR ( BIT(30) ) +#define BIT_DEF_SOFT_RST ( BIT(29) ) +#define BIT_ADC3_SOFT_RST ( BIT(28) ) +#define BIT_ADC2_SOFT_RST ( BIT(27) ) +#define BIT_ADC1_SOFT_RST ( BIT(26) ) +#define BIT_MBOX_SOFT_RST ( BIT(25) ) +#define BIT_RTC4M1_CAL_SOFT_RST ( BIT(23) ) +#define BIT_RTC4M0_CAL_SOFT_RST ( BIT(22) ) +#define BIT_LDSP_SYS_SOFT_RST ( BIT(21) ) +#define BIT_LCP_SYS_SOFT_RST ( BIT(20) ) +#define BIT_DAC3_SOFT_RST ( BIT(19) ) +#define BIT_DAC2_SOFT_RST ( BIT(18) ) +#define BIT_DAC1_SOFT_RST ( BIT(17) ) +#define BIT_ADC3_CAL_SOFT_RST ( BIT(16) ) +#define BIT_ADC2_CAL_SOFT_RST ( BIT(15) ) +#define BIT_ADC1_CAL_SOFT_RST ( BIT(14) ) +#define BIT_MDAR_SOFT_RST ( BIT(13) ) +#define BIT_LVDSDIS_SOFT_RST ( BIT(12) ) +#define BIT_BB_CAL_SOFT_RST ( BIT(11) ) +#define BIT_DCXO_LC_SOFT_RST ( BIT(10) ) +#define BIT_AP_TMR2_SOFT_RST ( BIT(9) ) +#define BIT_AP_TMR1_SOFT_RST ( BIT(8) ) +#define BIT_CA7_WDG_SOFT_RST ( BIT(7) ) +#define BIT_AON_DMA_SOFT_RST ( BIT(6) ) +#define BIT_AVS_SOFT_RST ( BIT(5) ) +#define BIT_DMC_PHY_SOFT_RST ( BIT(4) ) +#define BIT_GPU_THMA_SOFT_RST ( BIT(3) ) +#define BIT_ARM_THMA_SOFT_RST ( BIT(2) ) +#define BIT_THM_SOFT_RST ( BIT(1) ) +#define BIT_PMU_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_APB_RTC_EB */ +#define BIT_CP0_LTE_EB ( BIT(19) ) +#define BIT_BB_CAL_RTC_EB ( BIT(18) ) +#define BIT_DCXO_LC_RTC_EB ( BIT(17) ) +#define BIT_AP_TMR2_RTC_EB ( BIT(16) ) +#define BIT_AP_TMR1_RTC_EB ( BIT(15) ) +#define BIT_GPU_THMA_RTC_AUTO_EN ( BIT(14) ) +#define BIT_ARM_THMA_RTC_AUTO_EN ( BIT(13) ) +#define BIT_GPU_THMA_RTC_EB ( BIT(12) ) +#define BIT_ARM_THMA_RTC_EB ( BIT(11) ) +#define BIT_THM_RTC_EB ( BIT(10) ) +#define BIT_CA7_WDG_RTC_EB ( BIT(9) ) +#define BIT_AP_WDG_RTC_EB ( BIT(8) ) +#define BIT_EIC_RTCDV5_EB ( BIT(7) ) +#define BIT_EIC_RTC_EB ( BIT(6) ) +#define BIT_AP_TMR0_RTC_EB ( BIT(5) ) +#define BIT_AON_TMR_RTC_EB ( BIT(4) ) +#define BIT_AP_SYST_RTC_EB ( BIT(3) ) +#define BIT_AON_SYST_RTC_EB ( BIT(2) ) +#define BIT_KPD_RTC_EB ( BIT(1) ) +#define BIT_ARCH_RTC_EB ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_REC_26MHZ_BUF_CFG */ +#define BITS_PLL_PROBE_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_REC_26MHZ_1_CUR_SEL ( BIT(4) ) +#define BIT_REC_26MHZ_0_CUR_SEL ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_SINDRV_CTRL */ +#define BITS_SINDRV_LVL(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)) ) +#define BIT_SINDRV_CLIP_MODE ( BIT(2) ) +#define BIT_SINDRV_ENA_SQUARE ( BIT(1) ) +#define BIT_SINDRV_ENA ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_ADA_SEL_CTRL */ +#define BIT_TW_MODE_SEL ( BIT(3) ) +#define BIT_WGADC_DIV_EN ( BIT(2) ) +#define BIT_AFCDAC_SYS_SEL ( BIT(1) ) +#define BIT_APCDAC_SYS_SEL ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_VBC_CTRL */ +#define BIT_AUDIF_CKG_AUTO_EN ( BIT(20) ) +#define BITS_AUD_INT_SYS_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_VBC_AFIFO_INT_SYS_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_VBC_AD23_INT_SYS_SEL(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_VBC_AD01_INT_SYS_SEL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_VBC_DA01_INT_SYS_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_VBC_AD23_DMA_SYS_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_VBC_AD01_DMA_SYS_SEL(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_VBC_DA01_DMA_SYS_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BIT_VBC_INT_CP0_ARM_SEL ( BIT(3) ) +#define BIT_VBC_INT_CP1_ARM_SEL ( BIT(2) ) +#define BIT_VBC_DMA_CP0_ARM_SEL ( BIT(1) ) +#define BIT_VBC_DMA_CP1_ARM_SEL ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_PWR_CTRL */ +#define BIT_HSIC_PLL_EN ( BIT(19) ) +#define BIT_HSIC_PHY_PD ( BIT(18) ) +#define BIT_HSIC_PS_PD_S ( BIT(17) ) +#define BIT_HSIC_PS_PD_L ( BIT(16) ) +#define BIT_MIPI_DSI_PS_PD_S ( BIT(15) ) +#define BIT_MIPI_DSI_PS_PD_L ( BIT(14) ) +#define BIT_MIPI_CSI_4LANE_PS_PD_S ( BIT(13) ) +#define BIT_MIPI_CSI_4LANE_PS_PD_L ( BIT(12) ) +#define BIT_MIPI_CSI_2LANE_PS_PD_S ( BIT(11) ) +#define BIT_MIPI_CSI_2LANE_PS_PD_L ( BIT(10) ) +#define BIT_CA7_TS1_STOP ( BIT(9) ) +#define BIT_CA7_TS0_STOP ( BIT(8) ) +#define BIT_EFUSE_BIST_PWR_ON ( BIT(3) ) +#define BIT_FORCE_DSI_PHY_SHUTDOWNZ ( BIT(2) ) +#define BIT_FORCE_CSI_PHY_SHUTDOWNZ ( BIT(1) ) +#define BIT_USB_PHY_PD ( BIT(0) ) + +#define BIT_CSI1_PHY_PD ( BIT(11) ) +#define BIT_CSI0_PHY_PD ( BIT(10) ) + +/* bits definitions for register REG_AON_APB_TS_CFG */ +#define BIT_CSYSACK_TS_LP_2 ( BIT(13) ) +#define BIT_CSYSREQ_TS_LP_2 ( BIT(12) ) +#define BIT_CSYSACK_TS_LP_1 ( BIT(11) ) +#define BIT_CSYSREQ_TS_LP_1 ( BIT(10) ) +#define BIT_CSYSACK_TS_LP_0 ( BIT(9) ) +#define BIT_CSYSREQ_TS_LP_0 ( BIT(8) ) +#define BIT_EVENTACK_RESTARTREQ_TS01 ( BIT(4) ) +#define BIT_EVENT_RESTARTREQ_TS01 ( BIT(1) ) +#define BIT_EVENT_HALTREQ_TS01 ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_BOOT_MODE */ +#define BIT_ARM_JTAG_EN ( BIT(13) ) +#define BIT_WPLL_OVR_FREQ_SEL ( BIT(12) ) +#define BIT_PTEST_FUNC_ATSPEED_SEL ( BIT(8) ) +#define BIT_PTEST_FUNC_MODE ( BIT(7) ) +#define BIT_USB_DLOAD_EN ( BIT(4) ) +#define BIT_ARM_BOOT_MD3 ( BIT(3) ) +#define BIT_ARM_BOOT_MD2 ( BIT(2) ) +#define BIT_ARM_BOOT_MD1 ( BIT(1) ) +#define BIT_ARM_BOOT_MD0 ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_BB_BG_CTRL */ +#define BIT_BB_CON_BG ( BIT(22) ) +#define BITS_BB_BG_RSV(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)) ) +#define BITS_BB_LDO_V(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BIT_BB_BG_RBIAS_EN ( BIT(15) ) +#define BIT_BB_BG_IEXT_IB_EN ( BIT(14) ) +#define BITS_BB_LDO_REFCTRL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) ) +#define BIT_BB_LDO_AUTO_PD_EN ( BIT(11) ) +#define BIT_BB_LDO_SLP_PD_EN ( BIT(10) ) +#define BIT_BB_LDO_FORCE_ON ( BIT(9) ) +#define BIT_BB_LDO_FORCE_PD ( BIT(8) ) +#define BIT_BB_BG_AUTO_PD_EN ( BIT(3) ) +#define BIT_BB_BG_SLP_PD_EN ( BIT(2) ) +#define BIT_BB_BG_FORCE_ON ( BIT(1) ) +#define BIT_BB_BG_FORCE_PD ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_CP_ARM_JTAG_CTRL */ +#define BITS_CP_ARM_JTAG_PIN_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AON_APB_PLL_SOFT_CNT_DONE */ +#define BIT_RC1_SOFT_CNT_DONE ( BIT(13) ) +#define BIT_RC0_SOFT_CNT_DONE ( BIT(12) ) +#define BIT_XTLBUF1_SOFT_CNT_DONE ( BIT(9) ) +#define BIT_XTLBUF0_SOFT_CNT_DONE ( BIT(8) ) +#define BIT_LVDSPLL_SOFT_CNT_DONE ( BIT(4) ) +#define BIT_LPLL_SOFT_CNT_DONE ( BIT(3) ) +#define BIT_TWPLL_SOFT_CNT_DONE ( BIT(2) ) +#define BIT_DPLL_SOFT_CNT_DONE ( BIT(1) ) +#define BIT_MPLL_SOFT_CNT_DONE ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_DCXO_LC_REG0 */ +#define BIT_DCXO_LC_FLAG ( BIT(8) ) +#define BIT_DCXO_LC_FLAG_CLR ( BIT(1) ) +#define BIT_DCXO_LC_CNT_CLR ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_DCXO_LC_REG1 */ +#define BITS_DCXO_LC_CNT(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_MPLL_CFG1 */ +#define BITS_MPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)) ) +#define BIT_MPLL_LOCK_DONE ( BIT(27) ) +#define BIT_MPLL_DIV_S ( BIT(26) ) +#define BIT_MPLL_MOD_EN ( BIT(25) ) +#define BIT_MPLL_SDM_EN ( BIT(24) ) +#define BITS_MPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_MPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_MPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_MPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AON_APB_MPLL_CFG2 */ +#define BITS_MPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_MPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_AON_APB_DPLL_CFG1 */ +#define BITS_DPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)) ) +#define BIT_DPLL_LOCK_DONE ( BIT(27) ) +#define BIT_DPLL_DIV_S ( BIT(26) ) +#define BIT_DPLL_MOD_EN ( BIT(25) ) +#define BIT_DPLL_SDM_EN ( BIT(24) ) +#define BITS_DPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_DPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_DPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_DPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AON_APB_DPLL_CFG2 */ +#define BITS_DPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_DPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_AON_APB_TWPLL_CFG1 */ +#define BITS_TWPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)) ) +#define BIT_TWPLL_LOCK_DONE ( BIT(27) ) +#define BIT_TWPLL_DIV_S ( BIT(26) ) +#define BIT_TWPLL_MOD_EN ( BIT(25) ) +#define BIT_TWPLL_SDM_EN ( BIT(24) ) +#define BITS_TWPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_TWPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_TWPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_TWPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AON_APB_TWPLL_CFG2 */ +#define BITS_TWPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_TWPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_AON_APB_LTEPLL_CFG1 */ +#define BITS_LTEPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)) ) +#define BIT_LTEPLL_LOCK_DONE ( BIT(27) ) +#define BIT_LTEPLL_DIV_S ( BIT(26) ) +#define BIT_LTEPLL_MOD_EN ( BIT(25) ) +#define BIT_LTEPLL_SDM_EN ( BIT(24) ) +#define BITS_LTEPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_LTEPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_LTEPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_LTEPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AON_APB_LTEPLL_CFG2 */ +#define BITS_LTEPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_LTEPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_AON_APB_LVDSDISPLL_CFG1 */ +#define BITS_LVDSDISPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_LVDSDISPLL_LOCK_DONE ( BIT(27) ) +#define BIT_LVDSDISPLL_DIV_S ( BIT(26) ) +#define BIT_LVDSDISPLL_MOD_EN ( BIT(25) ) +#define BIT_LVDSDISPLL_SDM_EN ( BIT(24) ) +#define BITS_LVDSDISPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_LVDSDISPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_LVDSDISPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_LVDSDISPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AON_APB_LVDSDISPLL_CFG2 */ +#define BITS_LVDSDISPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_LVDSDISPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_AON_APB_AON_REG_PROT */ +#define BIT_LDSP_CTRL_PROT ( BIT(31) ) +#define BITS_REG_PROT_VAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AON_APB_LDSP_BOOT_EN */ +#define BIT_FRC_CLK_LDSP_EN ( BIT(1) ) +#define BIT_LDSP_BOOT_EN ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_LDSP_BOOT_VEC */ +#define BITS_LDSP_BOOT_VECTOR(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_LDSP_RST */ +#define BIT_LDSP_SYS_SRST ( BIT(1) ) +#define BIT_LDSP_CORE_SRST_N ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_LDSP_MTX_CTRL1 */ +#define BITS_LDSP_MTX_CTRL1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_LDSP_MTX_CTRL2 */ +#define BITS_LDSP_MTX_CTRL2(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_LDSP_MTX_CTRL3 */ +#define BITS_LDSP_MTX_CTRL3(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_AON_CGM_CFG */ +#define BITS_PROBE_CKG_DIV(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_AUX2_CKG_DIV(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_AUX1_CKG_DIV(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_AUX0_CKG_DIV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_PROBE_CKG_SEL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_AUX2_CKG_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_AUX1_CKG_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_AUX0_CKG_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_LACC_MTX_CTRL */ +#define BITS_LACC_MTX_CTRL(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CORTEX_MTX_CTRL1 */ +#define BITS_CORTEX_MTX_CTRL1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CORTEX_MTX_CTRL2 */ +#define BITS_CORTEX_MTX_CTRL2(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CORTEX_MTX_CTRL3 */ +#define BITS_CORTEX_MTX_CTRL3(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AON_APB_CA5_TCLK_DLY_LEN */ +#define BITS_CA5_TCLK_DLY_LEN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AON_APB_CCIR_RCVR_CFG */ +#define BITS_ANALOG_PLL_RSV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_ANALOG_TESTMUX(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_CCIR_SE ( BIT(1) ) +#define BIT_CCIR_IE ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_PLL_BG_CFG */ +#define BITS_PLL_BG_RSV(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BIT_PLL_BG_RBIAS_EN ( BIT(3) ) +#define BIT_PLL_BG_PD ( BIT(2) ) +#define BIT_PLL_BG_IEXT_IBEN ( BIT(1) ) +#define BIT_PLL_CON_BG ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_LVDSDIS_SEL */ +#define BITS_LVDSDIS_LOG_SEL(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)) ) +#define BIT_LVDSDIS_DBG_SEL ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_DJTAG_MUX_SEL */ +#if defined(CONFIG_MACH_SP9830I) +#define BIT_DjTAG_CODEC_SEL (BIT(7)) +#endif +#define BIT_DJTAG_AON_SEL ( BIT(6) ) +#define BIT_DJTAG_PUB_SEL ( BIT(5) ) +#define BIT_DJTAG_CP1_SEL ( BIT(4) ) +#define BIT_DJTAG_CP0_SEL ( BIT(3) ) +#define BIT_DJTAG_GPU_SEL ( BIT(2) ) +#define BIT_DJTAG_MM_SEL ( BIT(1) ) +#define BIT_DJTAG_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_ARM7_SYS_SOFT_RST */ +#define BIT_ARM7_SYS_SOFT_RST ( BIT(4) ) +#define BIT_ARM7_CORE_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_CP1_CP0_ADDR_MSB */ +#define BITS_CP1_CP0_ADDR_MSB(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_AON_DMA_INT_EN */ +#define BIT_AON_DMA_INT_ARM7_EN ( BIT(6) ) +#define BIT_AON_DMA_INT_CP1_DSP_EN ( BIT(5) ) +#define BIT_AON_DMA_INT_CP1_CA5_EN ( BIT(4) ) +#define BIT_AON_DMA_INT_CP0_DSP_1_EN ( BIT(3) ) +#define BIT_AON_DMA_INT_CP0_DSP_0_EN ( BIT(2) ) +#define BIT_AON_DMA_INT_CP0_ARM9_0_EN ( BIT(1) ) +#define BIT_AON_DMA_INT_AP_EN ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_EMC_AUTO_GATE_EN */ +#define BIT_CP1_PUB_AUTO_GATE_EN ( BIT(19) ) +#define BIT_CP0_PUB_AUTO_GATE_EN ( BIT(18) ) +#define BIT_AP_PUB_AUTO_GATE_EN ( BIT(17) ) +#define BIT_AON_APB_PUB_AUTO_GATE_EN ( BIT(16) ) +#define BIT_CP1_EMC_AUTO_GATE_EN ( BIT(3) ) +#define BIT_CP0_EMC_AUTO_GATE_EN ( BIT(2) ) +#define BIT_AP_EMC_AUTO_GATE_EN ( BIT(1) ) +#define BIT_CA7_EMC_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_ARM7_CFG_BUS */ +#define BIT_ARM7_CFG_BUS_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_RTC4M_0_CFG */ +#define BITS_RTC4M0_RSV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RTC4M0_I_C(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BIT_RTC4M0_CAL_DONE ( BIT(6) ) +#define BIT_RTC4M0_CAL_START ( BIT(5) ) +#define BIT_RTC4M0_CHOP_EN ( BIT(4) ) +#define BIT_RTC4M0_FORCE_EN ( BIT(1) ) +#define BIT_RTC4M0_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_RTC4M_1_CFG */ +#define BITS_RTC4M1_RSV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RTC4M1_I_C(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BIT_RTC4M1_CAL_DONE ( BIT(6) ) +#define BIT_RTC4M1_CAL_START ( BIT(5) ) +#define BIT_RTC4M1_CHOP_EN ( BIT(4) ) +#define BIT_RTC4M1_FORCE_EN ( BIT(1) ) +#define BIT_RTC4M1_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_APB_RST2 */ +#if defined(CONFIG_MACH_SP9830I) +#define BIT_CODEC_DJTAG_SOFT_RST (BIT(7)) +#endif +#define BIT_AON_DJTAG_SOFT_RST ( BIT(6) ) +#define BIT_PUB_DJTAG_SOFT_RST ( BIT(5) ) +#define BIT_GPU_DJTAG_SOFT_RST ( BIT(4) ) +#define BIT_MM_DJTAG_SOFT_RST ( BIT(3) ) +#define BIT_CP1_DJTAG_SOFT_RST ( BIT(2) ) +#define BIT_CP0_DJTAG_SOFT_RST ( BIT(1) ) +#define BIT_AP_DJTAG_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_AP_WPROT_EN1 */ +#define BITS_AP_AWADDR_WPROT_EN1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CP0_WPROT_EN1 */ +#define BITS_CP0_AWADDR_WPROT_EN1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CP1_WPROT_EN1 */ +#define BITS_CP1_AWADDR_WPROT_EN1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_IO_DLY_CTRL */ +#define BITS_CLK_CCIR_DLY_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CLK_CP1DSP_DLY_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_CLK_CP0DSP_DLY_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_AP_WPROT_EN0 */ +#define BITS_AP_AWADDR_WPROT_EN0(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CP0_WPROT_EN0 */ +#define BITS_CP0_AWADDR_WPROT_EN0(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CP1_WPROT_EN0 */ +#define BITS_CP1_AWADDR_WPROT_EN0(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_PMU_RST_MONITOR */ +#define BITS_PMU_RST_MONITOR(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_THM_RST_MONITOR */ +#define BITS_THM_RST_MONITOR(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_AP_RST_MONITOR */ +#define BITS_AP_RST_MONITOR(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CA7_RST_MONITOR */ +#define BITS_CA7_RST_MONITOR(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_BOND_OPT0 */ +#define BITS_BOND_OPTION0(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_BOND_OPT1 */ +#define BITS_BOND_OPTION1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_RES_REG0 */ +#define BITS_RES_REG0(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_RES_REG1 */ +#define BITS_RES_REG1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_AON_QOS_CFG */ +#define BITS_QOS_R_GPU(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_QOS_W_GPU(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_QOS_R_GSP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_QOS_W_GSP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_BB_LDO_CAL_START */ +#define BIT_BB_LDO_CAL_START ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_AON_MTX_PROT_CFG */ +#define BITS_HPROT_DMAW(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_HPROT_DMAR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_LVDS_CFG */ +#define BITS_LVDSDIS_TXCLKDATA(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_LVDSDIS_TXCOM(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_LVDSDIS_TXSLEW(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_LVDSDIS_TXSW(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_LVDSDIS_TXRERSER(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_LVDSDIS_PRE_EMP(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)) ) +#define BIT_LVDSDIS_TXPD ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_PLL_LOCK_OUT_SEL */ +#define BIT_SLEEP_PLLLOCK_SEL ( BIT(7) ) +#define BITS_PLL_LOCK_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BITS_SLEEP_DBG_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_RTC4M_RC_VAL */ +#define BIT_RTC4M1_RC_SEL ( BIT(31) ) +#define BITS_RTC4M1_RC_VAL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) ) +#define BIT_RTC4M0_RC_SEL ( BIT(15) ) +#define BITS_RTC4M0_RC_VAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) ) + +/* bits definitions for register REG_AON_APB_AON_APB_RSV */ +#define BITS_AON_APB_RSV(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_AON_CHIP_ID */ +#define BITS_AON_CHIP_ID(_X_) (_X_) + +#endif diff --git a/include/soc/sprd/chip_x35l/__regs_aon_clk.h b/include/soc/sprd/chip_x35l/__regs_aon_clk.h new file mode 100644 index 00000000..3f78be87 --- /dev/null +++ b/include/soc/sprd/chip_x35l/__regs_aon_clk.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __REGS_AON_CLK_H__ +#define __REGS_AON_CLK_H__ + +#define REGS_AON_CLK + +/* registers definitions for controller REGS_AON_CLK */ +#define REG_AON_CLK_PUB_AHB_CFG SCI_ADDR(SPRD_AONCKG_BASE, 0x0020) +#define REG_AON_CLK_AON_APB_CFG SCI_ADDR(SPRD_AONCKG_BASE, 0x0024) +#define REG_AON_CLK_ADI_CFG SCI_ADDR(SPRD_AONCKG_BASE, 0x0028) +#define REG_AON_CLK_PWM0_CFG SCI_ADDR(SPRD_AONCKG_BASE, 0x002c) +#define REG_AON_CLK_PWM1_CFG SCI_ADDR(SPRD_AONCKG_BASE, 0x0030) +#define REG_AON_CLK_PWM2_CFG SCI_ADDR(SPRD_AONCKG_BASE, 0x0034) +#define REG_AON_CLK_PWM3_CFG SCI_ADDR(SPRD_AONCKG_BASE, 0x0038) +#define REG_AON_CLK_ARM7_UART_CFG SCI_ADDR(SPRD_AONCKG_BASE, 0x003c) +#define REG_AON_CLK_THM_CFG SCI_ADDR(SPRD_AONCKG_BASE, 0x0040) +#define REG_AON_CLK_MSPI_CFG SCI_ADDR(SPRD_AONCKG_BASE, 0x0044) +#define REG_AON_CLK_I2C_CFG SCI_ADDR(SPRD_AONCKG_BASE, 0x0048) +#define REG_AON_CLK_AVS_CFG SCI_ADDR(SPRD_AONCKG_BASE, 0x004c) +#define REG_AON_CLK_AUDIF_CFG SCI_ADDR(SPRD_AONCKG_BASE, 0x0050) +#define REG_AON_CLK_CA7_DAP_CFG SCI_ADDR(SPRD_AONCKG_BASE, 0x0054) +#define REG_AON_CLK_EMC_CFG SCI_ADDR(SPRD_AONCKG_BASE, 0x0058) +#define REG_AON_CLK_CA7_TS_CFG SCI_ADDR(SPRD_AONCKG_BASE, 0x005c) +#define REG_AON_CLK_DJTAG_CLK_CFG SCI_ADDR(SPRD_AONCKG_BASE, 0x0060) +#define REG_AON_CLK_ARM7_AHB_CFG SCI_ADDR(SPRD_AONCKG_BASE, 0x0064) +#define REG_AON_CLK_CA5_TS_CFG SCI_ADDR(SPRD_AONCKG_BASE, 0x0068) +/* vars definitions for controller REGS_AON_CLK */ +#define PUB_AHB_CLK_SEL_SHIFT (0x0) +#define PUB_AHB_CLK_SEL_MASK (0x3 << PUB_AHB_CLK_SEL_SHIFT) + +#define PUB_APB_CLK_SEL_SHIFT (0x0) +#define PUB_APB_CLK_SEL_MASK (0x3 << PUB_AHB_CLK_SEL_SHIFT) +#endif //__REGS_AON_CLK_H__ diff --git a/include/soc/sprd/chip_x35l/__regs_ap_ahb_rf.h b/include/soc/sprd/chip_x35l/__regs_ap_ahb_rf.h new file mode 100755 index 00000000..9619a74f --- /dev/null +++ b/include/soc/sprd/chip_x35l/__regs_ap_ahb_rf.h @@ -0,0 +1,366 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_AP_AHB_HEADFILE_H__ +#define __H_REGS_AP_AHB_HEADFILE_H__ __FILE__ + +#define REGS_AP_AHB_RF + +/* registers definitions for controller REGS_AP_AHB */ +#define REG_AP_AHB_AHB_EB SCI_ADDR(REGS_AP_AHB_BASE, 0x0000) +#define REG_AP_AHB_AHB_RST SCI_ADDR(REGS_AP_AHB_BASE, 0x0004) +#define REG_AP_AHB_CA7_RST_SET SCI_ADDR(REGS_AP_AHB_BASE, 0x0008) +#define REG_AP_AHB_AP_SYS_FORCE_SLEEP_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x000C) +#define REG_AP_AHB_AP_SYS_AUTO_SLEEP_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x0010) +#define REG_AP_AHB_HOLDING_PEN SCI_ADDR(REGS_AP_AHB_BASE, 0x0014) +#define REG_AP_AHB_JMP_ADDR_CA7_C0 SCI_ADDR(REGS_AP_AHB_BASE, 0x0018) +#define REG_AP_AHB_JMP_ADDR_CA7_C1 SCI_ADDR(REGS_AP_AHB_BASE, 0x001C) +#define REG_AP_AHB_JMP_ADDR_CA7_C2 SCI_ADDR(REGS_AP_AHB_BASE, 0x0020) +#define REG_AP_AHB_JMP_ADDR_CA7_C3 SCI_ADDR(REGS_AP_AHB_BASE, 0x0024) +#define REG_AP_AHB_CA7_C0_PU_LOCK SCI_ADDR(REGS_AP_AHB_BASE, 0x0028) +#define REG_AP_AHB_CA7_C1_PU_LOCK SCI_ADDR(REGS_AP_AHB_BASE, 0x002C) +#define REG_AP_AHB_CA7_C2_PU_LOCK SCI_ADDR(REGS_AP_AHB_BASE, 0x0030) +#define REG_AP_AHB_CA7_C3_PU_LOCK SCI_ADDR(REGS_AP_AHB_BASE, 0x0034) +#define REG_AP_AHB_CA7_CKG_DIV_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x0038) +#define REG_AP_AHB_MCU_PAUSE SCI_ADDR(REGS_AP_AHB_BASE, 0x003C) +#define REG_AP_AHB_MISC_CKG_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x0040) +#define REG_AP_AHB_CA7_C0_AUTO_FORCE_SHUTDOWN_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x0044) +#define REG_AP_AHB_CA7_C1_AUTO_FORCE_SHUTDOWN_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x0048) +#define REG_AP_AHB_CA7_C2_AUTO_FORCE_SHUTDOWN_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x004C) +#define REG_AP_AHB_CA7_C3_AUTO_FORCE_SHUTDOWN_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x0050) +#define REG_AP_AHB_CA7_CKG_SEL_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x0054) +#define REG_AP_AHB_MISC_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x3000) +#define REG_AP_AHB_AP_MAIN_MTX_HPROT_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x3004) +#define REG_AP_AHB_CA7_STANDBY_STATUS SCI_ADDR(REGS_AP_AHB_BASE, 0x3008) +#define REG_AP_AHB_NANC_CLK_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x300C) +#define REG_AP_AHB_LVDS_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x3010) +#define REG_AP_AHB_LVDS_PLL_CFG0 SCI_ADDR(REGS_AP_AHB_BASE, 0x3014) +#define REG_AP_AHB_LVDS_PLL_CFG1 SCI_ADDR(REGS_AP_AHB_BASE, 0x3018) +#define REG_AP_AHB_AP_QOS_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x301C) +#define REG_AP_AHB_OTG_PHY_TUNE SCI_ADDR(REGS_AP_AHB_BASE, 0x3020) +#define REG_AP_AHB_OTG_PHY_TEST SCI_ADDR(REGS_AP_AHB_BASE, 0x3024) +#define REG_AP_AHB_OTG_PHY_CTRL SCI_ADDR(REGS_AP_AHB_BASE, 0x3028) +#define REG_AP_AHB_HSIC_PHY_TUNE SCI_ADDR(REGS_AP_AHB_BASE, 0x302C) +#define REG_AP_AHB_HSIC_PHY_TEST SCI_ADDR(REGS_AP_AHB_BASE, 0x3030) +#define REG_AP_AHB_HSIC_PHY_CTRL SCI_ADDR(REGS_AP_AHB_BASE, 0x3034) +#define REG_AP_AHB_ZIP_MTX_QOS_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x3038) +#define REG_AP_AHB_CHIP_ID SCI_ADDR(REGS_AP_AHB_BASE, 0x30FC) + +/* bits definitions for register REG_AP_AHB_AHB_EB */ +#define BIT_ZIPMTX_EB ( BIT(23) ) +#define BIT_LVDS_EB ( BIT(22) ) +#define BIT_ZIPDEC_EB ( BIT(21) ) +#define BIT_ZIPENC_EB ( BIT(20) ) +#define BIT_NANDC_ECC_EB ( BIT(19) ) +#define BIT_NANDC_2X_EB ( BIT(18) ) +#define BIT_NANDC_EB ( BIT(17) ) +#define BIT_BUSMON2_EB ( BIT(16) ) +#define BIT_BUSMON1_EB ( BIT(15) ) +#define BIT_BUSMON0_EB ( BIT(14) ) +#define BIT_SPINLOCK_EB ( BIT(13) ) +#define BIT_EMMC_EB ( BIT(11) ) +#define BIT_SDIO2_EB ( BIT(10) ) +#define BIT_SDIO1_EB ( BIT(9) ) +#define BIT_SDIO0_EB ( BIT(8) ) +#define BIT_DRM_EB ( BIT(7) ) +#define BIT_NFC_EB ( BIT(6) ) +#define BIT_DMA_EB ( BIT(5) ) +#define BIT_OTG_EB ( BIT(4) ) +#define BIT_USB_EB (BIT_OTG_EB) +#define BIT_GSP_EB ( BIT(3) ) +#define BIT_HSIC_EB ( BIT(2) ) +#define BIT_DISPC_EB ( BIT(1) ) +#define BIT_DISPC0_EB (BIT_DISPC_EB) +#define BIT_DSI_EB ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_AHB_RST */ +#define BIT_HSIC_PHY_SOFT_RST ( BIT(30) ) +#define BIT_HSIC_UTMI_SOFT_RST ( BIT(29) ) +#define BIT_HSIC_SOFT_RST ( BIT(28) ) +#define BIT_LVDS_SOFT_RST ( BIT(25) ) +#define BIT_ZIP_MTX_SOFT_RST ( BIT(24) ) +#define BIT_ZIPDEC_SOFT_RST ( BIT(23) ) +#define BIT_ZIPENC_SOFT_RST ( BIT(22) ) +#define BIT_NANDC_SOFT_RST ( BIT(20) ) +#define BIT_BUSMON2_SOFT_RST ( BIT(19) ) +#define BIT_BUSMON1_SOFT_RST ( BIT(18) ) +#define BIT_BUSMON0_SOFT_RST ( BIT(17) ) +#define BIT_SPINLOCK_SOFT_RST ( BIT(16) ) +#define BIT_EMMC_SOFT_RST ( BIT(14) ) +#define BIT_SDIO2_SOFT_RST ( BIT(13) ) +#define BIT_SDIO1_SOFT_RST ( BIT(12) ) +#define BIT_SDIO0_SOFT_RST ( BIT(11) ) +#define BIT_DRM_SOFT_RST ( BIT(10) ) +#define BIT_NFC_SOFT_RST ( BIT(9) ) +#define BIT_DMA_SOFT_RST ( BIT(8) ) +#define BIT_OTG_PHY_SOFT_RST ( BIT(6) ) +#define BIT_OTG_UTMI_SOFT_RST ( BIT(5) ) +#define BIT_OTG_SOFT_RST ( BIT(4) ) +#define BIT_GSP_SOFT_RST ( BIT(3) ) +#define BIT_DISP_MTX_SOFT_RST ( BIT(2) ) +#define BIT_DISPC0_SOFT_RST ( BIT(1) ) +#define BIT_DSI_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_CA7_RST_SET */ +#define BIT_CA7_CS_DBG_SOFT_RST ( BIT(14) ) +#define BIT_CA7_L2_SOFT_RST ( BIT(13) ) +#define BIT_CA7_SOCDBG_SOFT_RST ( BIT(12) ) +#define BITS_CA7_ETM_SOFT_RST(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CA7_DBG_SOFT_RST(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_CA7_CORE_SOFT_RST(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AP_AHB_AP_SYS_FORCE_SLEEP_CFG */ +#define BIT_CA7_C3_AUTO_SLP_EN ( BIT(15) ) +#define BIT_CA7_C2_AUTO_SLP_EN ( BIT(14) ) +#define BIT_CA7_C1_AUTO_SLP_EN ( BIT(13) ) +#define BIT_CA7_C0_AUTO_SLP_EN ( BIT(12) ) +#define BIT_CA7_C3_WFI_SHUTDOWN_EN ( BIT(11) ) +#define BIT_CA7_C2_WFI_SHUTDOWN_EN ( BIT(10) ) +#define BIT_CA7_C1_WFI_SHUTDOWN_EN ( BIT(9) ) +#define BIT_CA7_C0_WFI_SHUTDOWN_EN ( BIT(8) ) +#define BIT_MCU_CA7_C3_SLEEP ( BIT(7) ) +#define BIT_MCU_CA7_C2_SLEEP ( BIT(6) ) +#define BIT_MCU_CA7_C1_SLEEP ( BIT(5) ) +#define BIT_MCU_CA7_C0_SLEEP ( BIT(4) ) +#define BIT_AP_PERI_FORCE_ON ( BIT(2) ) +#define BIT_AP_PERI_FORCE_SLP ( BIT(1) ) +#define BIT_AP_APB_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_AP_SYS_AUTO_SLEEP_CFG */ +#define BIT_GSP_CKG_FORCE_EN ( BIT(9) ) +#define BIT_GSP_AUTO_GATE_EN ( BIT(8) ) +#define BIT_AP_AHB_AUTO_GATE_EN ( BIT(5) ) +#define BIT_AP_EMC_AUTO_GATE_EN ( BIT(4) ) +#define BIT_CA7_EMC_AUTO_GATE_EN ( BIT(3) ) +#define BIT_CA7_DBG_FORCE_SLEEP ( BIT(2) ) +#define BIT_CA7_DBG_AUTO_GATE_EN ( BIT(1) ) +#define BIT_CA7_CORE_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_HOLDING_PEN */ +#define BITS_HOLDING_PEN(_x_) ( (_x_) << 0 ) + +/* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C0 */ +#define BITS_JMP_ADDR_CA7_C0(_x_) ( (_x_) << 0 ) + +/* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C1 */ +#define BITS_JMP_ADDR_CA7_C1(_x_) ( (_x_) << 0 ) + +/* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C2 */ +#define BITS_JMP_ADDR_CA7_C2(_x_) ( (_x_) << 0 ) + +/* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C3 */ +#define BITS_JMP_ADDR_CA7_C3(_x_) ( (_x_) << 0 ) + +/* bits definitions for register REG_AP_AHB_CA7_C0_PU_LOCK */ +#define BIT_CA7_C0_PU_LOCK ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_CA7_C1_PU_LOCK */ +#define BIT_CA7_C1_PU_LOCK ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_CA7_C2_PU_LOCK */ +#define BIT_CA7_C2_PU_LOCK ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_CA7_C3_PU_LOCK */ +#define BIT_CA7_C3_PU_LOCK ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_CA7_CKG_DIV_CFG */ +#define BITS_CA7_DBG_CKG_DIV(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)) ) +#define BITS_CA7_AXI_CKG_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CA7_MCU_CKG_DIV(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) + +/* bits definitions for register REG_AP_AHB_MCU_PAUSE */ +#define BIT_DMA_ACT_LIGHT_EN ( BIT(5) ) +#define BIT_MCU_SLEEP_FOLLOW_CA7_EN ( BIT(4) ) +#define BIT_MCU_LIGHT_SLEEP_EN ( BIT(3) ) +#define BIT_MCU_DEEP_SLEEP_EN ( BIT(2) ) +#define BIT_MCU_SYS_SLEEP_EN ( BIT(1) ) +#define BIT_MCU_CORE_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_MISC_CKG_EN */ +#define BIT_ASHB_CA7_DBG_VLD ( BIT(9) ) +#define BIT_ASHB_CA7_DBG_EN ( BIT(8) ) +#define BIT_DISP_TMC_CKG_EN ( BIT(4) ) +#define BIT_DPHY_REF_CKG_EN ( BIT(1) ) +#define BIT_DPHY_CFG_CKG_EN ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_CA7_C0_AUTO_FORCE_SHUTDOWN_EN */ +#define BIT_CA7_C0_AUTO_FORCE_SHUTDOWN_EN ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_CA7_C1_AUTO_FORCE_SHUTDOWN_EN */ +#define BIT_CA7_C1_AUTO_FORCE_SHUTDOWN_EN ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_CA7_C2_AUTO_FORCE_SHUTDOWN_EN */ +#define BIT_CA7_C2_AUTO_FORCE_SHUTDOWN_EN ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_CA7_C3_AUTO_FORCE_SHUTDOWN_EN */ +#define BIT_CA7_C3_AUTO_FORCE_SHUTDOWN_EN ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_CA7_CKG_SEL_CFG */ +#define BITS_CA7_MCU_CKG_SEL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AP_AHB_MISC_CFG */ +#define BITS_EMMC_SLOT_SEL(_x_) ( (_x_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_SDIO0_SLOT_SEL(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_BUSMON2_CHN_SEL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_BUSMON1_CHN_SEL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_BUSMON0_CHN_SEL(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_SDIO2_SLOT_SEL(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_SDIO1_SLOT_SEL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_AHB_AP_MAIN_MTX_HPROT_CFG */ +#define BITS_HPROT_NFC(_x_) ( (_x_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_HPROT_EMMC(_x_) ( (_x_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_HPROT_SDIO2(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_HPROT_SDIO1(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_HPROT_SDIO0(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_HPROT_DMAW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_HPROT_DMAR(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AP_AHB_CA7_STANDBY_STATUS */ +#define BIT_CA7_STANDBYWFIL2 ( BIT(12) ) +#define BITS_CA7_ETMSTANDBYWFX(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CA7_STANDBYWFE(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_CA7_STANDBYWFI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AP_AHB_NANC_CLK_CFG */ +#define BITS_CLK_NANDC2X_DIV(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_CLK_NANDC2X_SEL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_AHB_LVDS_CFG */ +#define BITS_LVDS_TXCLKDATA(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_LVDS_TXCOM(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_LVDS_TXSLEW(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_LVDS_TXSW(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_LVDS_TXRERSER(_x_) ( (_x_) << 3 & (BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_LVDS_PRE_EMP(_x_) ( (_x_) << 1 & (BIT(1)|BIT(2)) ) +#define BIT_LVDS_TXPD ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_LVDS_PLL_CFG0 */ +#define BIT_LVDS_PLL_LOCK_DET ( BIT(31) ) +#define BITS_LVDS_PLL_REFIN(_x_) ( (_x_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_LVDS_PLL_LPF(_x_) ( (_x_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BIT_LVDS_PLL_DIV_S ( BIT(18) ) +#define BITS_LVDS_PLL_IBIAS(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_LVDS_PLLN(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AP_AHB_LVDS_PLL_CFG1 */ +#define BITS_LVDS_PLL_KINT(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_LVDS_PLL_RSV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_LVDS_PLL_MOD_EN ( BIT(7) ) +#define BIT_LVDS_PLL_SDM_EN ( BIT(6) ) +#define BITS_LVDS_PLL_NINT(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_AP_AHB_AP_QOS_CFG */ +#define BITS_QOS_R_TMC(_x_) ( (_x_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_QOS_W_TMC(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_QOS_R_DISPC(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_QOS_W_DISPC(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AP_AHB_OTG_PHY_TUNE */ +#define BIT_OTG_TXPREEMPPULSETUNE ( BIT(20) ) +#define BITS_OTG_TXRESTUNE(_x_) ( (_x_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_OTG_TXHSXVTUNE(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_OTG_TXVREFTUNE(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_OTG_TXPREEMPAMPTUNE(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_OTG_TXRISETUNE(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_OTG_TXFSLSTUNE(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_OTG_SQRXTUNE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AP_AHB_OTG_PHY_TEST */ +#define BIT_OTG_ATERESET ( BIT(31) ) +#define BIT_OTG_VBUS_VALID_EXT_SEL ( BIT(26) ) +#define BIT_OTG_VBUS_VALID_EXT ( BIT(25) ) +#define BIT_OTG_OTGDISABLE ( BIT(24) ) +#define BIT_OTG_TESTBURNIN ( BIT(21) ) +#define BIT_OTG_LOOPBACKENB ( BIT(20) ) +#define BITS_OTG_TESTDATAOUT(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_OTG_VATESTENB(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BIT_OTG_TESTCLK ( BIT(13) ) +#define BIT_OTG_TESTDATAOUTSEL ( BIT(12) ) +#define BITS_OTG_TESTADDR(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_OTG_TESTDATAIN(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_AP_AHB_OTG_PHY_CTRL */ +#define BITS_OTG_SS_SCALEDOWNMODE(_x_) ( (_x_) << 25 & (BIT(25)|BIT(26)) ) +#define BIT_OTG_TXBITSTUFFENH ( BIT(23) ) +#define BIT_OTG_TXBITSTUFFEN ( BIT(22) ) +#define BIT_OTG_DMPULLDOWN ( BIT(21) ) +#define BIT_OTG_DPPULLDOWN ( BIT(20) ) +#define BIT_OTG_DMPULLUP ( BIT(9) ) +#define BIT_OTG_COMMONONN ( BIT(8) ) +#define BITS_OTG_REFCLKSEL(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_OTG_FSEL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AP_AHB_HSIC_PHY_TUNE */ +#define BITS_HSIC_REFCLK_DIV(_x_) ( (_x_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) ) +#define BIT_HSIC_TXPREEMPPULSETUNE ( BIT(20) ) +#define BITS_HSIC_TXRESTUNE(_x_) ( (_x_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_HSIC_TXHSXVTUNE(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_HSIC_TXVREFTUNE(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_HSIC_TXPREEMPAMPTUNE(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_HSIC_TXRISETUNE(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_HSIC_TXFSLSTUNE(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_HSIC_SQRXTUNE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AP_AHB_HSIC_PHY_TEST */ +#define BIT_HSIC_ATERESET ( BIT(31) ) +#define BIT_HSIC_VBUS_VALID_EXT_SEL ( BIT(26) ) +#define BIT_HSIC_VBUS_VALID_EXT ( BIT(25) ) +#define BIT_HSIC_OTGDISABLE ( BIT(24) ) +#define BIT_HSIC_TESTBURNIN ( BIT(21) ) +#define BIT_HSIC_LOOPBACKENB ( BIT(20) ) +#define BITS_HSIC_TESTDATAOUT(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_HSIC_VATESTENB(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BIT_HSIC_TESTCLK ( BIT(13) ) +#define BIT_HSIC_TESTDATAOUTSEL ( BIT(12) ) +#define BITS_HSIC_TESTADDR(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_HSIC_TESTDATAIN(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_AP_AHB_HSIC_PHY_CTRL */ +#define BITS_HSIC_SS_SCALEDOWNMODE(_x_) ( (_x_) << 25 & (BIT(25)|BIT(26)) ) +#define BIT_HSIC_TXBITSTUFFENH ( BIT(23) ) +#define BIT_HSIC_TXBITSTUFFEN ( BIT(22) ) +#define BIT_HSIC_DMPULLDOWN ( BIT(21) ) +#define BIT_HSIC_DPPULLDOWN ( BIT(20) ) +#define BIT_HSIC_IF_MODE ( BIT(16) ) +#define BIT_IF_SELECT_HSIC ( BIT(13) ) +#define BIT_HSIC_DBNCE_FLTR_BYPASS ( BIT(12) ) +#define BIT_HSIC_DMPULLUP ( BIT(9) ) +#define BIT_HSIC_COMMONONN ( BIT(8) ) +#define BITS_HSIC_REFCLKSEL(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_HSIC_FSEL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AP_AHB_ZIP_MTX_QOS_CFG */ +#define BITS_ZIPMTX_S0_ARQOS(_x_) ( (_x_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_ZIPMTX_S0_AWQOS(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_ZIPDEC_ARQOS(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_ZIPDEC_AWQOS(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_ZIPENC_ARQOS(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_ZIPENC_AWQOS(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AP_AHB_CHIP_ID */ +#define BITS_CHIP_ID(_x_) ( (_x_) << 0 ) + +/* vars definitions for controller REGS_AP_AHB */ + +#endif /* __REGS_AP_AHB_H__ */ diff --git a/include/soc/sprd/chip_x35l/__regs_ap_apb.h b/include/soc/sprd/chip_x35l/__regs_ap_apb.h new file mode 100755 index 00000000..355cbe13 --- /dev/null +++ b/include/soc/sprd/chip_x35l/__regs_ap_apb.h @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_AP_APB_HEADFILE_H__ +#define __H_REGS_AP_APB_HEADFILE_H__ __FILE__ + +#define REGS_AP_APB + +/* registers definitions for AP_APB */ +#define REG_AP_APB_APB_EB SCI_ADDR(REGS_AP_APB_BASE, 0x0000) +#define REG_AP_APB_APB_RST SCI_ADDR(REGS_AP_APB_BASE, 0x0004) +#define REG_AP_APB_APB_MISC_CTRL SCI_ADDR(REGS_AP_APB_BASE, 0x0008) + + + +/* bits definitions for register REG_AP_APB_APB_EB */ +#define BIT_INTC3_EB ( BIT(22) ) +#define BIT_INTC2_EB ( BIT(21) ) +#define BIT_INTC1_EB ( BIT(20) ) +#define BIT_INTC0_EB ( BIT(19) ) +#define BIT_AP_CKG_EB ( BIT(18) ) +#define BIT_UART4_EB ( BIT(17) ) +#define BIT_UART3_EB ( BIT(16) ) +#define BIT_UART2_EB ( BIT(15) ) +#define BIT_UART1_EB ( BIT(14) ) +#define BIT_UART0_EB ( BIT(13) ) +#define BIT_I2C4_EB ( BIT(12) ) +#define BIT_I2C3_EB ( BIT(11) ) +#define BIT_I2C2_EB ( BIT(10) ) +#define BIT_I2C1_EB ( BIT(9) ) +#define BIT_I2C0_EB ( BIT(8) ) +#define BIT_SPI2_EB ( BIT(7) ) +#define BIT_SPI1_EB ( BIT(6) ) +#define BIT_SPI0_EB ( BIT(5) ) +#define BIT_IIS3_EB ( BIT(4) ) +#define BIT_IIS2_EB ( BIT(3) ) +#define BIT_IIS1_EB ( BIT(2) ) +#define BIT_IIS0_EB ( BIT(1) ) +#define BIT_SIM0_EB ( BIT(0) ) + +/* bits definitions for register REG_AP_APB_APB_RST */ +#define BIT_INTC3_SOFT_RST ( BIT(22) ) +#define BIT_INTC2_SOFT_RST ( BIT(21) ) +#define BIT_INTC1_SOFT_RST ( BIT(20) ) +#define BIT_INTC0_SOFT_RST ( BIT(19) ) +#define BIT_AP_CKG_SOFT_RST ( BIT(18) ) +#define BIT_UART4_SOFT_RST ( BIT(17) ) +#define BIT_UART3_SOFT_RST ( BIT(16) ) +#define BIT_UART2_SOFT_RST ( BIT(15) ) +#define BIT_UART1_SOFT_RST ( BIT(14) ) +#define BIT_UART0_SOFT_RST ( BIT(13) ) +#define BIT_I2C4_SOFT_RST ( BIT(12) ) +#define BIT_I2C3_SOFT_RST ( BIT(11) ) +#define BIT_I2C2_SOFT_RST ( BIT(10) ) +#define BIT_I2C1_SOFT_RST ( BIT(9) ) +#define BIT_I2C0_SOFT_RST ( BIT(8) ) +#define BIT_SPI2_SOFT_RST ( BIT(7) ) +#define BIT_SPI1_SOFT_RST ( BIT(6) ) +#define BIT_SPI0_SOFT_RST ( BIT(5) ) +#define BIT_IIS3_SOFT_RST ( BIT(4) ) +#define BIT_IIS2_SOFT_RST ( BIT(3) ) +#define BIT_IIS1_SOFT_RST ( BIT(2) ) +#define BIT_IIS0_SOFT_RST ( BIT(1) ) +#define BIT_SIM0_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_AP_APB_APB_MISC_CTRL */ +#define BIT_SIM_CLK_POLARITY ( BIT(1) ) +#define BIT_FMARK_POLARITY_INV ( BIT(0) ) + +#endif diff --git a/include/soc/sprd/chip_x35l/__regs_ap_clk.h b/include/soc/sprd/chip_x35l/__regs_ap_clk.h new file mode 100644 index 00000000..f3efe02f --- /dev/null +++ b/include/soc/sprd/chip_x35l/__regs_ap_clk.h @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __REGS_AP_CLK_H__ +#define __REGS_AP_CLK_H__ + +#define REGS_AP_CLK + +/* registers definitions for controller REGS_AP_CLK */ +#define REG_AP_CLK_AP_AHB_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0020) +#define REG_AP_CLK_AP_APB_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0024) +#define REG_AP_CLK_GSP_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0028) +#define REG_AP_CLK_DISPC0_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x002c) +#define REG_AP_CLK_DISPC0_DBI_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0030) +#define REG_AP_CLK_DISPC0_DPI_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0034) +#define REG_AP_CLK_NANDC_ECC_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0038) +#define REG_AP_CLK_SDIO0_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x003c) +#define REG_AP_CLK_SDIO1_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0040) +#define REG_AP_CLK_SDIO2_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0044) +#define REG_AP_CLK_EMMC_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0048) +#define REG_AP_CLK_OTG_REF_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x004c) +#define REG_AP_CLK_HSIC_REF_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0050) +#define REG_AP_CLK_UART0_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0054) +#define REG_AP_CLK_UART1_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0058) +#define REG_AP_CLK_UART2_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x005c) +#define REG_AP_CLK_UART3_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0060) +#define REG_AP_CLK_UART4_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0064) +#define REG_AP_CLK_I2C0_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0068) +#define REG_AP_CLK_I2C1_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x006c) +#define REG_AP_CLK_I2C2_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0070) +#define REG_AP_CLK_I2C3_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0074) +#define REG_AP_CLK_I2C4_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0078) +#define REG_AP_CLK_SPI0_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x007c) +#define REG_AP_CLK_SPI1_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0080) +#define REG_AP_CLK_SPI2_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0084) +#define REG_AP_CLK_IIS0_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0088) +#define REG_AP_CLK_IIS1_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x008c) +#define REG_AP_CLK_IIS2_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0090) +#define REG_AP_CLK_IIS3_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0094) +#define REG_AP_CLK_ZIPENC_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x0098) +#define REG_AP_CLK_ZIPDEC_CFG SCI_ADDR(REGS_AP_CLK_BASE, 0x009c) + + +/* vars definitions for controller REGS_AP_CLK */ + +/* vars definitions for REG_AP_CLK_AP_AHB_CFG */ +#define AP_AHB_CLK_SEL_SHIFT (0) +#define AP_AHB_CLK_SEL_MASK (0x3 << AP_AHB_CLK_SEL_SHIFT) + +#define AP_APB_CLK_SEL_SHIFT (0) +#define AP_APB_CLK_SEL_MASK (0x3 << AP_AHB_CLK_SEL_SHIFT) + +#endif //__REGS_AP_CLK_H__ diff --git a/include/soc/sprd/chip_x35l/__regs_arm7_ahb_rf.h b/include/soc/sprd/chip_x35l/__regs_arm7_ahb_rf.h new file mode 100755 index 00000000..784081ab --- /dev/null +++ b/include/soc/sprd/chip_x35l/__regs_arm7_ahb_rf.h @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_ARM7_AHB_RF_HEADFILE_H__ +#define __H_REGS_ARM7_AHB_RF_HEADFILE_H__ __FILE__ + +#define REGS_ARM7_AHB_RF + +/* registers definitions for ARM7_AHB_RF */ +#define REG_ARM7_AHB_RF_ARM7_EB SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0000) +#define REG_ARM7_AHB_RF_ARM7_SOFT_RST SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0004) +#define REG_ARM7_AHB_RF_AHB_PAUSE SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0008) +#define REG_ARM7_AHB_RF_ARM7_SLP_CTL SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x000C) + + + +/* bits definitions for register REG_ARM7_AHB_RF_ARM7_EB */ +#define BIT_ARM7_GPIO_EB ( BIT(10) ) +#define BIT_ARM7_UART_EB ( BIT(9) ) +#define BIT_ARM7_TMR_EB ( BIT(8) ) +#define BIT_ARM7_SYST_EB ( BIT(7) ) +#define BIT_ARM7_WDG_EB ( BIT(6) ) +#define BIT_ARM7_EIC_EB ( BIT(5) ) +#define BIT_ARM7_INTC_EB ( BIT(4) ) +#define BIT_ARM7_IMC_EB ( BIT(2) ) +#define BIT_ARM7_TIC_EB ( BIT(1) ) +#define BIT_ARM7_DMA_EB ( BIT(0) ) + +/* bits definitions for register REG_ARM7_AHB_RF_ARM7_SOFT_RST */ +#define BIT_ARM7_GPIO_SOFT_RST ( BIT(10) ) +#define BIT_ARM7_UART_SOFT_RST ( BIT(9) ) +#define BIT_ARM7_TMR_SOFT_RST ( BIT(8) ) +#define BIT_ARM7_SYST_SOFT_RST ( BIT(7) ) +#define BIT_ARM7_WDG_SOFT_RST ( BIT(6) ) +#define BIT_ARM7_EIC_SOFT_RST ( BIT(5) ) +#define BIT_ARM7_INTC_SOFT_RST ( BIT(4) ) +#define BIT_ARM7_IMC_SOFT_RST ( BIT(2) ) +#define BIT_ARM7_TIC_SOFT_RST ( BIT(1) ) +#define BIT_ARM7_ARCH_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_ARM7_AHB_RF_AHB_PAUSE */ +#define BIT_ARM7_DEEP_SLEEP_EN ( BIT(2) ) +#define BIT_ARM7_SYS_SLEEP_EN ( BIT(1) ) +#define BIT_ARM7_CORE_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_ARM7_AHB_RF_ARM7_SLP_CTL */ +#define BIT_ARM7_SYS_AUTO_GATE_EN ( BIT(2) ) +#define BIT_ARM7_AHB_AUTO_GATE_EN ( BIT(1) ) +#define BIT_ARM7_CORE_AUTO_GATE_EN ( BIT(0) ) + +#endif diff --git a/include/soc/sprd/chip_x35l/__regs_avs_apb_rf.h b/include/soc/sprd/chip_x35l/__regs_avs_apb_rf.h new file mode 100644 index 00000000..aef34590 --- /dev/null +++ b/include/soc/sprd/chip_x35l/__regs_avs_apb_rf.h @@ -0,0 +1,108 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_AVS_APB_RF_HEADFILE_H__ +#define __H_REGS_AVS_APB_RF_HEADFILE_H__ __FILE__ + +#define REGS_AVS_APB_RF + +/* registers definitions for AVS_APB_RF */ +#define REG_AVS_APB_RF_AVS_TUNE_LMT_CFG SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0000) +#define REG_AVS_APB_RF_AVS_TUNE_STATUS SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0004) +#define REG_AVS_APB_RF_AVS_CFG SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0008) +#define REG_AVS_APB_RF_AVS_TUNE_STEP_CFG SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x000C) +#define REG_AVS_APB_RF_AVS_WAIT_CFG SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0010) +#define REG_AVS_APB_RF_AVS_INT_CFG SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0014) +#define REG_AVS_APB_RF_AVS_START_SINGLE_ACT SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0018) +#define REG_AVS_APB_RF_AVS_START_REPEAT_ACT SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x001C) +#define REG_AVS_APB_RF_AVS_HPM_EN SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0020) +#define REG_AVS_APB_RF_AVS_HPM_RPT_ANLS SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0024) +#define REG_AVS_APB_RF_AVS_HPM_RPT_VLD_STATUS_0 SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0028) +#define REG_AVS_APB_RF_AVS_HPM_RPT_VLD_STATUS_1 SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x002C) +#define REG_AVS_APB_RF_FSM_STS SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0030) + + + +/* bits definitions for register REG_AVS_APB_RF_AVS_TUNE_LMT_CFG */ +#define BITS_VOLT_TUNE_VAL_MAX(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_VOLT_TUNE_VAL_MIN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_TUNE_STATUS */ +#define BITS_VOLT_TUNE_VAL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_VOLT_OBS_VAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_CFG */ +#define BIT_HPM3_RPT_CHKSUM_ERR_EN ( BIT(19) ) +#define BIT_HPM2_RPT_CHKSUM_ERR_EN ( BIT(18) ) +#define BIT_HPM1_RPT_CHKSUM_ERR_EN ( BIT(17) ) +#define BIT_HPM0_RPT_CHKSUM_ERR_EN ( BIT(16) ) +#define BIT_PAUSE_OCCUR_ERR_EN ( BIT(8) ) +#define BIT_VOLT_TUNE_FORBID_EN ( BIT(4) ) +#define BIT_VOLT_OBS_FORBID_EN ( BIT(0) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_TUNE_STEP_CFG */ +#define BITS_VOLT_TUNE_DOWN_STEP(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) ) +#define BITS_VOLT_TUNE_UP_STEP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_WAIT_CFG */ +#define BITS_RND_INTVAL_WAIT_NUM(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_VOLT_STB_WAIT_NUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_INT_CFG */ +#define BIT_AVS_TUNE_DONE_INT_MASK_STATUS ( BIT(13) ) +#define BIT_AVS_TUNE_ERR_INT_MASK_STATUS ( BIT(12) ) +#define BIT_AVS_TUNE_DONE_INT_RAW_STATUS ( BIT(9) ) +#define BIT_AVS_TUNE_ERR_INT_RAW_STATUS ( BIT(8) ) +#define BIT_AVS_TUNE_DONE_INT_CLR ( BIT(5) ) +#define BIT_AVS_TUNE_ERR_INT_CLR ( BIT(4) ) +#define BIT_AVS_TUNE_DONE_INT_EN ( BIT(1) ) +#define BIT_AVS_TUNE_ERR_INT_EN ( BIT(0) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_START_SINGLE_ACT */ +#define BIT_AVS_START_SINGLE_ACT ( BIT(0) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_START_REPEAT_ACT */ +#define BIT_AVS_START_REPEAT_ACT ( BIT(0) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_HPM_EN */ +#define BIT_HPM3_EN ( BIT(3) ) +#define BIT_HPM2_EN ( BIT(2) ) +#define BIT_HPM1_EN ( BIT(1) ) +#define BIT_HPM0_EN ( BIT(0) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_HPM_RPT_ANLS */ +#define BITS_HPM_RPT_TUNE_DWN_MARK(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_HPM_RPT_TUNE_UP_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_HPM_RPT_VLD_STATUS_0 */ +#define BITS_HPM1_RPT_VLD(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_HPM0_RPT_VLD(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_HPM_RPT_VLD_STATUS_1 */ +#define BITS_HPM3_RPT_VLD(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_HPM2_RPT_VLD(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AVS_APB_RF_FSM_STS */ +#define BITS_AVS_FSM_STS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +#endif diff --git a/include/soc/sprd/chip_x35l/__regs_codec_ahb.h b/include/soc/sprd/chip_x35l/__regs_codec_ahb.h new file mode 100644 index 00000000..b072b219 --- /dev/null +++ b/include/soc/sprd/chip_x35l/__regs_codec_ahb.h @@ -0,0 +1,58 @@ +/* the head file modifier: ang 2015-01-21 14:34:02*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_CODEC_AHB_HEADFILE_H__ +#define __H_REGS_CODEC_AHB_HEADFILE_H__ __FILE__ + +#define REGS_CODEC_AHB + +/* registers definitions for CODEC_AHB */ +#define REG_CODEC_AHB_AHB_RST SCI_ADDR(REGS_CODEC_AHB_BASE, 0x0000)/*AHB_RST*/ +#define REG_CODEC_AHB_CKG_ENABLE SCI_ADDR(REGS_CODEC_AHB_BASE, 0x0004)/*CKG_ENABLE*/ +#define REG_CODEC_AHB_CLOCK_SEL SCI_ADDR(REGS_CODEC_AHB_BASE, 0x0008)/*CLOCK_SEL*/ +#define REG_CODEC_AHB_CODA7_STAT SCI_ADDR(REGS_CODEC_AHB_BASE, 0x000C)/*CODA7_STAT*/ + + + +/* bits definitions for register REG_CODEC_AHB_AHB_RST */ +#define BIT_CODA7_APB_SOFT_RST (BIT(2)) +#define BIT_CODA7_CC_SOFT_RST (BIT(1)) +#define BIT_CODA7_AXI_SOFT_RST (BIT(0)) + +/* bits definitions for register REG_CODEC_AHB_CKG_ENABLE */ +#define BIT_CODA7_CKG_EN (BIT(4)) +#define BIT_CODA7_CC_CKG_EN (BIT(1)) +#define BIT_CODA7_AXI_CKG_EN (BIT(0)) + +/* bits definitions for register REG_CODEC_AHB_CLOCK_SEL */ +#define BITS_CLK_CODA7_AXI_SEL(_X_) ((_X_) << 8 & (BIT(8)|BIT(9))) +#define BITS_CLK_CODA7_CC_SEL(_X_) ((_X_) << 4 & (BIT(4)|BIT(5))) +#define BITS_CLK_CODA7_APB_SEL(_X_) ((_X_) & (BIT(0)|BIT(1))) + +/* bits definitions for register REG_CODEC_AHB_CODA7_STAT */ +#define BIT_CODA7_RUN (BIT(1)) +#define BIT_CODA7_IDLE (BIT(0)) + +#endif diff --git a/include/soc/sprd/chip_x35l/__regs_cortex_ahb_rf.h b/include/soc/sprd/chip_x35l/__regs_cortex_ahb_rf.h new file mode 100755 index 00000000..e9d8f3c0 --- /dev/null +++ b/include/soc/sprd/chip_x35l/__regs_cortex_ahb_rf.h @@ -0,0 +1,203 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_CORTEX_AHB_RF_HEADFILE_H__ +#define __H_REGS_CORTEX_AHB_RF_HEADFILE_H__ __FILE__ + +#define REGS_CORTEX_AHB_RF + +/* registers definitions for CORTEX_AHB_RF */ +#define REG_CORTEX_AHB_RF_CLK_CORTEX_AXI_CTRL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0000)/*CORTEX_AXI clock control*/ +#define REG_CORTEX_AHB_RF_CLK_CORTEX_AHB_CTRL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0004)/*CORTEX_AHB clock control*/ +#define REG_CORTEX_AHB_RF_CLK_CORTEX_APB_CTRL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0008)/*CORTEX_APB clock control*/ +#define REG_CORTEX_AHB_RF_CLK_SEC0_CTRL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x000C)/*SEC0 clock control*/ +#define REG_CORTEX_AHB_RF_CLK_SEC1_CTRL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0010)/*SEC1 clock control*/ +#define REG_CORTEX_AHB_RF_CA5_CFG SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0030)/* CortexA5 config*/ +#define REG_CORTEX_AHB_RF_AHB_CTRL0 SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0034)/*AHB control 0*/ +#define REG_CORTEX_AHB_RF_AHB_CTRL2 SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x003C)/*AHB control 2*/ +#define REG_CORTEX_AHB_RF_AHB_RST0_STS SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0060)/*AHB software reset*/ +#define REG_CORTEX_AHB_RF_CA5_RST_SET SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0064) +#define REG_CORTEX_AHB_RF_ARCH_EB SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0068) +#define REG_CORTEX_AHB_RF_PTEST_FUNC SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x006C) +#define REG_CORTEX_AHB_RF_AHB_MISC_CTL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0070) +#define REG_CORTEX_AHB_RF_CA5_CTRL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0074)/* Cortex A5 control*/ +#define REG_CORTEX_AHB_RF_AUTO_GATE_CTRL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0078)/*Auto gate control*/ +#define REG_CORTEX_AHB_RF_AHB_PAUSE SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0080)/*AHB sleep control*/ +#define REG_CORTEX_AHB_RF_AHB_SLP_CTL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0084) +#define REG_CORTEX_AHB_RF_AHB_SLP_STS SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0088) +#define REG_CORTEX_AHB_RF_MCU_CLK_CTL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x008C) +#define REG_CORTEX_AHB_RF_RES_REG0 SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x00F4) +#define REG_CORTEX_AHB_RF_CHIP_ID SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0200) + + + +/* bits definitions for register REG_CORTEX_AHB_RF_CLK_CORTEX_AXI_CTRL */ +#define BITS_CLK_CORTEX_AXI_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_CLK_CORTEX_AHB_CTRL */ +#define BITS_CLK_CORTEX_AHB_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_CLK_CORTEX_APB_CTRL */ +#define BITS_CLK_CORTEX_APB_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_CLK_SEC0_CTRL */ +#define BITS_CLK_SEC0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_CLK_SEC1_CTRL */ +#define BITS_CLK_SEC1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_CA5_CFG */ +#define BITS_CA5_DBG_DIV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_CA5_AXI_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CA5_MCU_DIV(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BITS_CA5_MCU_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_AHB_CTRL0 */ +#define BITS_TFT_MST_HPROT(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_PPP1_MST_HPROT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_PPP0_MST_HPROT(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_TFT_EB ( BIT(18) ) +#define BIT_PPP1_EB ( BIT(17) ) +#define BIT_PPP0_EB ( BIT(16) ) +#define BITS_SEC1_MST_HPROT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_SEC0_MST_HPROT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BIT_SEC1_EB ( BIT(5) ) +#define BIT_SEC1_CKG_EN ( BIT(4) ) +#define BIT_SEC0_EB ( BIT(3) ) +#define BIT_SEC0_CKG_EN ( BIT(2) ) +#define BIT_DMA_EB ( BIT(1) ) +#define BIT_DMA_CKG_EN ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_AHB_CTRL2 */ +#define BITS_BUSMON1_CHN_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_AXIBUSMON_CHN_SEL(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_BUSMON0_CHN_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BIT_BUSMON1_EB ( BIT(3) ) +#define BIT_SPINLOCK_EB ( BIT(2) ) +#define BIT_AXIBUSMON_EB ( BIT(1) ) +#define BIT_BUSMON0_EB ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_AHB_RST0_STS */ +#define BIT_TFT_SOFT_RST ( BIT(11) ) +#define BIT_PPP1_SOFT_RST ( BIT(10) ) +#define BIT_PPP0_SOFT_RST ( BIT(9) ) +#define BIT_SEC1_CMD_PARSER_RST ( BIT(8) ) +#define BIT_SEC0_CMD_PARSER_RST ( BIT(7) ) +#define BIT_SPINLOCK_SOFT_RST ( BIT(6) ) +#define BIT_SEC1_SOFT_RST ( BIT(5) ) +#define BIT_SEC0_SOFT_RST ( BIT(4) ) +#define BIT_BUSMON1_SOFT_RST ( BIT(3) ) +#define BIT_AXIBUSMON_SOFT_RST ( BIT(2) ) +#define BIT_BUSMON0_SOFT_RST ( BIT(1) ) +#define BIT_DMA_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_CA5_RST_SET */ +#define BIT_CA5_MTX_SOFT_RST ( BIT(3) ) +#define BIT_CA5_L2_SOFT_RST ( BIT(2) ) +#define BIT_CA5_DBG_SOFT_RST ( BIT(1) ) +#define BIT_CA5_CORE_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_ARCH_EB */ +#define BIT_AHB_ARCH_EB ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_PTEST_FUNC */ +#define BIT_PTEST_FUNC_ATSPEED_SEL ( BIT(2) ) +#define BIT_PTEST_FUNC_MODE ( BIT(1) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_AHB_MISC_CTL */ +#define BITS_DMA_W_PROT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMA_R_PROT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BIT_LCP2PUB_ACCESS_EN ( BIT(4) ) +#define BITS_MCU_SHM_CTRL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_CA5_CTRL */ +#define BIT_CA5_WDRESET_EN ( BIT(18) ) +#define BIT_CA5_TS_EN ( BIT(17) ) +#define BIT_CA5_CFGSDISABLE ( BIT(13) ) +#define BITS_CA5_CLK_AXI_DIV(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)) ) +#define BIT_CA5_CLK_DBG_EN_SEL ( BIT(10) ) +#define BIT_CA5_CLK_DBG_EN ( BIT(9) ) +#define BIT_CA5_DBGEN ( BIT(8) ) +#define BIT_CA5_NIDEN ( BIT(7) ) +#define BIT_CA5_SPIDEN ( BIT(6) ) +#define BIT_CA5_SPNIDEN ( BIT(5) ) +#define BIT_CA5_CP15DISABLE ( BIT(4) ) +#define BIT_CA5_TEINIT ( BIT(3) ) +#define BIT_CA5_L1RSTDISABLE ( BIT(2) ) +#define BIT_CA5_L2CFGEND ( BIT(1) ) +#define BIT_CA5_L2SPNIDEN ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_AUTO_GATE_CTRL */ +#define BIT_CORTEX_AHB_AUTO_GATE_EN ( BIT(5) ) +#define BIT_CA5_DBG_FORCE_SLEEP ( BIT(4) ) +#define BIT_CA5_DBG_AUTO_GATE_EN ( BIT(3) ) +#define BIT_CA5_CORE_AUTO_GATE_EN ( BIT(2) ) +#define BIT_LCPX_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_AHB_PAUSE */ +#define BIT_EMC_LIGHT_SLEEP_EN ( BIT(25) ) +#define BIT_EMC_DEEP_SLEEP_EN ( BIT(24) ) +#define BIT_APB_SLEEP_EN ( BIT(18) ) +#define BIT_APB_PERI_FRC_SLP ( BIT(17) ) +#define BIT_APB_PERI_FRC_ON ( BIT(16) ) +#define BIT_MCU_FORCE_DEEP_SLEEP ( BIT(15) ) +#define BIT_DMA_LSLP_EN ( BIT(4) ) +#define BIT_MCU_LIGHT_SLEEP_EN ( BIT(3) ) +#define BIT_MCU_DEEP_SLEEP_EN ( BIT(2) ) +#define BIT_MCU_SYS_SLEEP_EN ( BIT(1) ) +#define BIT_MCU_CORE_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_AHB_SLP_CTL */ +#define BIT_ARM_DAHB_SLEEP_EN ( BIT(4) ) +#define BIT_MCUMTX_AUTO_GATE_EN ( BIT(3) ) +#define BIT_MCU_AUTO_GATE_EN ( BIT(2) ) +#define BIT_AHB_AUTO_GATE_EN ( BIT(1) ) +#define BIT_ARM_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_AHB_SLP_STS */ +#define BIT_CHIP_SLP_ARM_CLR ( BIT(5) ) +#define BIT_CHIP_SLEEP_REC_ARM ( BIT(4) ) +#define BIT_APB_PERI_SLEEP ( BIT(3) ) +#define BIT_DMA_BUSY ( BIT(1) ) +#define BIT_EMC_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_MCU_CLK_CTL */ +#define BIT_CLK_LCP2LDSP_BRG_EN ( BIT(24) ) +#define BIT_CLK_LCP2PUB_BRG_EN ( BIT(23) ) +#define BIT_CLK_LCP2CP0_BRG_EN ( BIT(22) ) +#define BIT_CLK_CP_DBG_SEL ( BIT(21) ) +#define BIT_CLK_MCU_DBG_SEL ( BIT(20) ) +#define BITS_CLK_COM_DBG_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_CLK_SYS_DBG_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_CLK_AHB_DIV(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_CLK_MCU_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_APB_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CLK_MCU_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_RES_REG0 */ +#define BITS_RES_REG0(_X_) (_X_) + +/* bits definitions for register REG_CORTEX_AHB_RF_CHIP_ID */ +#define BITS_CHIP_ID(_X_) (_X_) + +#endif diff --git a/include/soc/sprd/chip_x35l/__regs_cortex_glb.h b/include/soc/sprd/chip_x35l/__regs_cortex_glb.h new file mode 100755 index 00000000..9c2abe91 --- /dev/null +++ b/include/soc/sprd/chip_x35l/__regs_cortex_glb.h @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_CORTEX_GLB_HEADFILE_H__ +#define __H_REGS_CORTEX_GLB_HEADFILE_H__ __FILE__ + +#define REGS_CORTEX_GLB + +/* registers definitions for CORTEX_GLB */ +#define REG_CORTEX_GLB_APB_EB0_STS SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0008) +#define REG_CORTEX_GLB_APB_RST0_STS SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0014) +#define REG_CORTEX_GLB_APB_MCU_RST SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0018) +#define REG_CORTEX_GLB_APB_CLK_SEL0 SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x001C) +#define REG_CORTEX_GLB_APB_CLK_SEL1 SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0020) +#define REG_CORTEX_GLB_APB_ARCH_EB SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0024) +#define REG_CORTEX_GLB_APB_MISC_CTL0 SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0028) +#define REG_CORTEX_GLB_APB_MISC_CTL1 SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x002C) +#define REG_CORTEX_GLB_APB_CLK_SEL2 SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0030) +#define REG_CORTEX_GLB_APB_BUS_CTL0 SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0058) +#define REG_CORTEX_GLB_APB_MEM_LP_CTRL0 SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x005c) +#define REG_CORTEX_GLB_APB_MEM_LP_CTRL1 SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0060) +#define REG_CORTEX_GLB_APB_DSP_INT_CLR SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0074) +#define REG_CORTEX_GLB_APB_MISC_INT_STS SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0078) +#define REG_CORTEX_GLB_APB_HWRST SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0080) +#define REG_CORTEX_GLB_APB_ARM_BOOT_ADDR SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0084) + + + +/* bits definitions for register REG_CORTEX_GLB_APB_EB0_STS */ +#define BIT_EIC_RTC_EB ( BIT(19) ) +#define BIT_EIC_EB ( BIT(18) ) +#define BIT_RFFE_EB ( BIT(17) ) +#define BIT_EPT_EB ( BIT(16) ) +#define BIT_GPIO_EB ( BIT(15) ) +#define BIT_TMR_RTC_EB ( BIT(14) ) +#define BIT_TMR_EB ( BIT(13) ) +#define BIT_SYSTMR_RTC_EB ( BIT(12) ) +#define BIT_SYSTMR_EB ( BIT(11) ) +#define BIT_IIS3_EB ( BIT(10) ) +#define BIT_IIS2_EB ( BIT(9) ) +#define BIT_IIS1_EB ( BIT(8) ) +#define BIT_IIS0_EB ( BIT(7) ) +#define BIT_SIM2_EB ( BIT(6) ) +#define BIT_SIM1_EB ( BIT(5) ) +#define BIT_SIM0_EB ( BIT(4) ) +#define BIT_UART1_EB ( BIT(3) ) +#define BIT_UART0_EB ( BIT(2) ) +#define BIT_WDG_RTC_EB ( BIT(1) ) +#define BIT_WDG_EB ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_RST0_STS */ +#define BIT_EIC_SOFT_RST ( BIT(16) ) +#define BIT_RFFE_SOFT_RST ( BIT(15) ) +#define BIT_MCU_DSP_RST ( BIT(14) ) +#define BIT_EPT_SOFT_RST ( BIT(13) ) +#define BIT_GPIO_SOFT_RST ( BIT(12) ) +#define BIT_TMR_SOFT_RST ( BIT(11) ) +#define BIT_SYSTMR_SOFT_RST ( BIT(10) ) +#define BIT_IIS3_SOFT_RST ( BIT(9) ) +#define BIT_IIS2_SOFT_RST ( BIT(8) ) +#define BIT_IIS1_SOFT_RST ( BIT(7) ) +#define BIT_IIS0_SOFT_RST ( BIT(6) ) +#define BIT_SIM2_SOFT_RST ( BIT(5) ) +#define BIT_SIM1_SOFT_RST ( BIT(4) ) +#define BIT_SIM0_SOFT_RST ( BIT(3) ) +#define BIT_UART1_SOFT_RST ( BIT(2) ) +#define BIT_UART0_SOFT_RST ( BIT(1) ) +#define BIT_WDG_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_MCU_RST */ +#define BIT_MCU_SOFT_RST_SET ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_CLK_SEL0 */ +#define BITS_CLK_UART1_DIV(_X_) ( (_X_) << 7 & (BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_CLK_UART1_SEL(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)) ) +#define BITS_CLK_UART0_DIV(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)) ) +#define BITS_CLK_UART0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_CLK_SEL1 */ +#define BIT_CLK_IIS1_PAD_SEL ( BIT(24) ) +#define BITS_CLK_IIS1_DIV(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_CLK_IIS1_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BIT_CLK_IIS0_PAD_SEL ( BIT(8) ) +#define BITS_CLK_IIS0_DIV(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_CLK_IIS0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_ARCH_EB */ +#define BIT_RTC_ARCH_EB ( BIT(1) ) +#define BIT_APB_ARCH_EB ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_MISC_CTL0 */ +#define BIT_ALL_CLK_EN ( BIT(28) ) +#define BIT_DMA_LSLP_EN ( BIT(27) ) +#define BIT_WAKEUP_XTL_EN_3G ( BIT(26) ) +#define BIT_WAKEUP_XTL_EN_2G ( BIT(25) ) +#define BIT_ARM_JTAG_EN ( BIT(24) ) +#define BITS_ARM_FRC_STOP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_MISC_CTL1 */ +#define BITS_BUFON_CTRL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_SIM2_CLK_POLARITY ( BIT(3) ) +#define BIT_SIM1_CLK_POLARITY ( BIT(2) ) +#define BIT_SIM0_CLK_POLARITY ( BIT(1) ) +#define BIT_ROM_CLK_EN ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_CLK_SEL2 */ +#define BIT_CLK_IIS3_PAD_SEL ( BIT(24) ) +#define BITS_CLK_IIS3_DIV(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_CLK_IIS3_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BIT_CLK_IIS2_PAD_SEL ( BIT(8) ) +#define BITS_CLK_IIS2_DIV(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_CLK_IIS2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_BUS_CTL0 */ +#define BIT_IIS3_CTRL_SEL ( BIT(7) ) +#define BIT_IIS2_CTRL_SEL ( BIT(6) ) +#define BIT_RFFE_CTRL_SEL ( BIT(5) ) +#define BIT_IIS1_CTRL_SEL ( BIT(3) ) +#define BIT_IIS0_CTRL_SEL ( BIT(2) ) +#define BIT_UART0_CTRL_SEL ( BIT(1) ) +#define BIT_UART1_CTRL_SEL ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_MEM_LP_CTRL0 */ +#define BITS_APB_MEM_LP_CTRL0(_X_) (_X_) + +/* bits definitions for register REG_CORTEX_GLB_APB_MEM_LP_CTRL1 */ +#define BITS_APB_MEM_LP_CTRL1(_X_) (_X_) + +/* bits definitions for register REG_CORTEX_GLB_APB_DSP_INT_CLR */ +#define BIT_RFT_INT_CLR ( BIT(2) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_MISC_INT_STS */ +#define BIT_RFT_INT ( BIT(2) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_HWRST */ +#define BITS_HWRST_REG(_X_) (_X_) + +/* bits definitions for register REG_CORTEX_GLB_APB_ARM_BOOT_ADDR */ +#define BITS_ARMBOOT_ADDR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +#endif diff --git a/include/soc/sprd/chip_x35l/__regs_cp_ahb_rf.h b/include/soc/sprd/chip_x35l/__regs_cp_ahb_rf.h new file mode 100755 index 00000000..26130206 --- /dev/null +++ b/include/soc/sprd/chip_x35l/__regs_cp_ahb_rf.h @@ -0,0 +1,297 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_CP_AHB_RF_HEADFILE_H__ +#define __H_REGS_CP_AHB_RF_HEADFILE_H__ __FILE__ + +#define REGS_CP_AHB_RF + +/* registers definitions for CP_AHB_RF */ +#define REG_CP_AHB_RF_AHB_EB0_STS SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0008) +#define REG_CP_AHB_RF_AHB_RST0_STS SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0014) +#define REG_CP_AHB_RF_ARCH_EB SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0018) +#define REG_CP_AHB_RF_AHB_REMAP SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x001C) +#define REG_CP_AHB_RF_AHB_MISC_CTL SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0020) +#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL0 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0024) +#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL1 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0028) +#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL2 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x002C) +#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL3 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0030) +#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL4 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0034) +#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL5 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0038) +#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL6 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x003C) +#define REG_CP_AHB_RF_AHB_PAUSE SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0040) +#define REG_CP_AHB_RF_AHB_SLP_CTL SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0044) +#define REG_CP_AHB_RF_AHB_SLP_STS SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0048) +#define REG_CP_AHB_RF_MCU_CLK_CTL SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x004C) +#define REG_CP_AHB_RF_DSP_CTL SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0050) +#define REG_CP_AHB_RF_DSP_BOOT_VECTOR SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0054) +#define REG_CP_AHB_RF_DSP_RST SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0058) +#define REG_CP_AHB_RF_DSP_JTAG_CTL SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x005C) +#define REG_CP_AHB_RF_MCU_C2C_SEMA SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0060) +#define REG_CP_AHB_RF_GGE_DSP_BOOT_VECTOR SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0064) +#define REG_CP_AHB_RF_CHIP_ID SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x01FC) + + + +/* bits definitions for register REG_CP_AHB_RF_AHB_EB0_STS */ +#define BIT_LZMA_EN ( BIT(11) ) +#define BIT_WCDMA_EN5 ( BIT(9) ) +#define BIT_WCDMA_EN4 ( BIT(8) ) +#define BIT_WCDMA_EN3 ( BIT(7) ) +#define BIT_WCDMA_EN2 ( BIT(6) ) +#define BIT_WCDMA_EN1 ( BIT(5) ) +#define BIT_WCDMA_EN0 ( BIT(4) ) +#define BIT_BUSMON2_EN ( BIT(3) ) +#define BIT_BUSMON1_EN ( BIT(2) ) +#define BIT_BUSMON0_EN ( BIT(1) ) +#define BIT_DMA_EN ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_RST0_STS */ +#define BIT_LZMA_SOFT_RST ( BIT(8) ) +#define BIT_WSYS_SOFT_RST ( BIT(6) ) +#define BIT_ARM1_SOFT_RST ( BIT(4) ) +#define BIT_BUSMON2_SOFT_RST ( BIT(3) ) +#define BIT_BUSMON1_SOFT_RST ( BIT(2) ) +#define BIT_BUSMON0_SOFT_RST ( BIT(1) ) +#define BIT_DMA_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_ARCH_EB */ +#define BIT_AHB_ARCH_EB ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_REMAP */ +#define BIT_PTEST_FUNC_ATSPEED_SEL ( BIT(2) ) +#define BIT_PTEST_FUNC_MODE ( BIT(1) ) +#define BIT_REMAP ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_MISC_CTL */ +#define BITS_MCU_GGE_SHM_CTRL(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)) ) +#define BITS_LZMA_M_PROT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMA_W_PROT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMA_R_PROT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_MCU_SHM_CTRL(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BIT_RF_SWT_AUTO_EN ( BIT(1) ) +#define BIT_WCDMA_ASHB_EN ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL0 */ +#define BITS_ARMMTX_M3TOS0_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ARMMTX_M3TOS0_ADJ_EN ( BIT(27) ) +#define BIT_ARMMTX_M3TOS0_RND_EN ( BIT(26) ) +#define BITS_ARMMTX_M3TOS0_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_ARMMTX_M2TOS0_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M2TOS0_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M2TOS0_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M2TOS0_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M1TOS0_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M1TOS0_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M1TOS0_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M1TOS0_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M0TOS0_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M0TOS0_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M0TOS0_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M0TOS0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL1 */ +#define BITS_ARMMTX_M3TOS1_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ARMMTX_M3TOS1_ADJ_EN ( BIT(27) ) +#define BIT_ARMMTX_M3TOS1_RND_EN ( BIT(26) ) +#define BITS_ARMMTX_M3TOS1_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_ARMMTX_M2TOS1_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M2TOS1_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M2TOS1_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M2TOS1_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M1TOS1_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M1TOS1_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M1TOS1_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M1TOS1_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M0TOS1_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M0TOS1_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M0TOS1_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M0TOS1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL2 */ +#define BITS_ARMMTX_M1TOS2_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ARMMTX_M1TOS2_ADJ_EN ( BIT(27) ) +#define BIT_ARMMTX_M1TOS2_RND_EN ( BIT(26) ) +#define BITS_ARMMTX_M1TOS2_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_ARMMTX_M0TOS2_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M0TOS2_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M0TOS2_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M0TOS2_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M5TOS1_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M5TOS1_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M5TOS1_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M5TOS1_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M4TOS1_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M4TOS1_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M4TOS1_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M4TOS1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL3 */ +#define BITS_ARMMTX_M5TOS2_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ARMMTX_M5TOS2_ADJ_EN ( BIT(27) ) +#define BIT_ARMMTX_M5TOS2_RND_EN ( BIT(26) ) +#define BITS_ARMMTX_M5TOS2_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_ARMMTX_M5TOS4_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M5TOS4_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M5TOS4_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M5TOS4_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M3TOS2_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M3TOS2_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M3TOS2_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M3TOS2_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M2TOS2_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M2TOS2_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M2TOS2_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M2TOS2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL4 */ +#define BITS_ARMMTX_M4TOS3_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M4TOS3_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M4TOS3_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M4TOS3_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M1TOS3_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M1TOS3_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M1TOS3_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M1TOS3_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M0TOS3_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M0TOS3_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M0TOS3_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M0TOS3_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL5 */ +#define BITS_ARMMTX_M4TOS0_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ARMMTX_M4TOS0_ADJ_EN ( BIT(27) ) +#define BIT_ARMMTX_M4TOS0_RND_EN ( BIT(26) ) +#define BITS_ARMMTX_M4TOS0_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_ARMMTX_M4TOS4_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M4TOS4_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M4TOS4_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M4TOS4_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M1TOS4_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M1TOS4_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M1TOS4_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M1TOS4_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M0TOS4_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M0TOS4_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M0TOS4_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M0TOS4_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL6 */ +#define BITS_ARMMTX_M3TOS5_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ARMMTX_M3TOS5_ADJ_EN ( BIT(27) ) +#define BIT_ARMMTX_M3TOS5_RND_EN ( BIT(26) ) +#define BITS_ARMMTX_M3TOS5_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_ARMMTX_M2TOS5_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M2TOS5_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M2TOS5_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M2TOS5_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M1TOS5_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M1TOS5_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M1TOS5_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M1TOS5_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M0TOS5_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M0TOS5_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M0TOS5_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M0TOS5_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_PAUSE */ +#define BIT_MCU_GGE_DEEP_SLEEP_EN ( BIT(5) ) +#define BIT_MCU_LIGHT_SLEEP_EN ( BIT(4) ) +#define BIT_APB_SLEEP ( BIT(3) ) +#define BIT_MCU_DEEP_SLEEP_EN ( BIT(2) ) +#define BIT_MCU_SYS_SLEEP_EN ( BIT(1) ) +#define BIT_MCU_CORE_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_SLP_CTL */ +#define BIT_AHB_VCP1_DEEP_SLEEP_EN ( BIT(6) ) +#define BIT_GGE_ARM_DAHB_SLEEP_EN ( BIT(5) ) +#define BIT_ARM_DAHB_SLEEP_EN ( BIT(4) ) +#define BIT_MCUMTX_AUTO_GATE_EN ( BIT(3) ) +#define BIT_MCU_AUTO_GATE_EN ( BIT(2) ) +#define BIT_AHB_AUTO_GATE_EN ( BIT(1) ) +#define BIT_ARM_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_SLP_STS */ +#define BIT_GGE_DSP_MAHB_SLEEP_EN ( BIT(4) ) +#define BIT_APB_PERI_SLEEP ( BIT(3) ) +#define BIT_DSP_MAHB_SLEEP_EN ( BIT(2) ) +#define BIT_DMA_BUSY ( BIT(1) ) +#define BIT_EMC_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_MCU_CLK_CTL */ +#define BIT_CLK_CP_DBG_GGE_SEL ( BIT(28) ) +#define BIT_CLK_GGE_DBG_SEL ( BIT(27) ) +#define BITS_CLK_COM_GGE_DBG_SEL(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BIT_CLK_SYS_GGE_DBG_SEL ( BIT(24) ) +#define BITS_CLK_LZMA_SEL(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)) ) +#define BIT_CLK_CP_DBG_SEL ( BIT(21) ) +#define BIT_CLK_MCU_DBG_SEL ( BIT(20) ) +#define BITS_CLK_COM_DBG_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_CLK_SYS_DBG_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_CLK_AHB_DIV(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_CLK_MCU_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_APB_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CLK_MCU_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_CP_AHB_RF_DSP_CTL */ +#define BIT_GGE_ASHB_ARMTODSP_EN ( BIT(5) ) +#define BIT_GGE_FRC_CLK_DSP_EN ( BIT(4) ) +#define BIT_GGE_DSP_BOOT_EN ( BIT(3) ) +#define BIT_ASHB_ARMTODSP_EN ( BIT(2) ) +#define BIT_FRC_CLK_DSP_EN ( BIT(1) ) +#define BIT_DSP_BOOT_EN ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_DSP_BOOT_VECTOR */ +#define BITS_DSP_BOOT_VECTOR(_X_) (_X_) + +/* bits definitions for register REG_CP_AHB_RF_DSP_RST */ +#define BIT_GGE_DSP_SYS_SRST ( BIT(3) ) +#define BIT_GGE_DSP_CORE_SRST_N ( BIT(2) ) +#define BIT_DSP_SYS_SRST ( BIT(1) ) +#define BIT_DSP_CORE_SRST_N ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_DSP_JTAG_CTL */ +#define BIT_GGE_CEVA_SW_JTAG_ENA ( BIT(24) ) +#define BIT_GGE_STDO ( BIT(20) ) +#define BIT_GGE_STCK ( BIT(19) ) +#define BIT_GGE_STMS ( BIT(18) ) +#define BIT_GGE_STDI ( BIT(17) ) +#define BIT_GGE_STRTCK ( BIT(16) ) +#define BIT_CEVA_SW_JTAG_ENA ( BIT(8) ) +#define BIT_STDO ( BIT(4) ) +#define BIT_STCK ( BIT(3) ) +#define BIT_STMS ( BIT(2) ) +#define BIT_STDI ( BIT(1) ) +#define BIT_STRTCK ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_MCU_C2C_SEMA */ +#define BITS_GGE_MCU_C2C_SEMA(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_MCU_C2C_SEMA(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_CP_AHB_RF_GGE_DSP_BOOT_VECTOR */ +#define BITS_GGE_DSP_BOOT_VECTOR(_X_) (_X_) + +/* bits definitions for register REG_CP_AHB_RF_CHIP_ID */ +#define BITS_CHIP_ID(_X_) (_X_) + +#endif diff --git a/include/soc/sprd/chip_x35l/__regs_cp_apb_rf.h b/include/soc/sprd/chip_x35l/__regs_cp_apb_rf.h new file mode 100644 index 00000000..94249dcb --- /dev/null +++ b/include/soc/sprd/chip_x35l/__regs_cp_apb_rf.h @@ -0,0 +1,245 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_CP_APB_RF_HEADFILE_H__ +#define __H_REGS_CP_APB_RF_HEADFILE_H__ __FILE__ + +#define REGS_CP_APB_RF + +/* registers definitions for CP_APB_RF */ +#define REG_CP_APB_RF_APB_EB0_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0008) +#define REG_CP_APB_RF_APB_RST0_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0014) +#define REG_CP_APB_RF_APB_MCU_RST SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0018) +#define REG_CP_APB_RF_APB_CLK_SEL0 SCI_ADDR(REGS_CP_APB_RF_BASE, 0x001C) +#define REG_CP_APB_RF_APB_CLK_DIV0 SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0020) +#define REG_CP_APB_RF_APB_ARCH_EB SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0024) +#define REG_CP_APB_RF_APB_MISC_CTL0 SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0028) +#define REG_CP_APB_RF_APB_MISC_CTL1 SCI_ADDR(REGS_CP_APB_RF_BASE, 0x002C) +#define REG_CP_APB_RF_APB_PIN_SEL SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0040) +#define REG_CP_APB_RF_APB_SLP_CTL SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0044) +#define REG_CP_APB_RF_APB_WSYS_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0048) +#define REG_CP_APB_RF_APB_SLP_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0050) +#define REG_CP_APB_RF_APB_ROM_PD_CTL SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0054) +#define REG_CP_APB_RF_APB_BUS_CTL0 SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0058) +#define REG_CP_APB_RF_APB_DSP_INT_CLR SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0074) +#define REG_CP_APB_RF_APB_MISC_INT_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0078) +#define REG_CP_APB_RF_APB_HWRST SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0080) +#define REG_CP_APB_RF_APB_ARM_BOOT_ADDR SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0084) +#define REG_CP_APB_RF_APB_GGE_SLP_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0088) + + + +/* bits definitions for register REG_CP_APB_RF_APB_EB0_STS */ +#define BIT_UART2_EB ( BIT(20) ) +#define BIT_EIC_RTC_EB ( BIT(19) ) +#define BIT_EIC_EB ( BIT(18) ) +#define BIT_RFFE_EB ( BIT(17) ) +#define BIT_EPT_EB ( BIT(16) ) +#define BIT_GPIO_EB ( BIT(15) ) +#define BIT_TMR_RTC_EB ( BIT(14) ) +#define BIT_TMR_EB ( BIT(13) ) +#define BIT_SYSTMR_RTC_EB ( BIT(12) ) +#define BIT_SYSTMR_EB ( BIT(11) ) +#define BIT_IIS3_EB ( BIT(10) ) +#define BIT_IIS2_EB ( BIT(9) ) +#define BIT_IIS1_EB ( BIT(8) ) +#define BIT_IIS0_EB ( BIT(7) ) +#define BIT_SIM2_EB ( BIT(6) ) +#define BIT_SIM1_EB ( BIT(5) ) +#define BIT_SIM0_EB ( BIT(4) ) +#define BIT_UART1_EB ( BIT(3) ) +#define BIT_UART0_EB ( BIT(2) ) +#define BIT_WDG_RTC_EB ( BIT(1) ) +#define BIT_WDG_EB ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_RST0_STS */ +#define BIT_UART2_SOFT_RST ( BIT(20) ) +#define BIT_GGE_MCU_DSP_RST ( BIT(19) ) +#define BIT_EIC_SOFT_RST ( BIT(16) ) +#define BIT_RFFE_SOFT_RST ( BIT(15) ) +#define BIT_MCU_DSP_RST ( BIT(14) ) +#define BIT_EPT_SOFT_RST ( BIT(13) ) +#define BIT_GPIO_SOFT_RST ( BIT(12) ) +#define BIT_TMR_SOFT_RST ( BIT(11) ) +#define BIT_SYSTMR_SOFT_RST ( BIT(10) ) +#define BIT_IIS3_SOFT_RST ( BIT(9) ) +#define BIT_IIS2_SOFT_RST ( BIT(8) ) +#define BIT_IIS1_SOFT_RST ( BIT(7) ) +#define BIT_IIS0_SOFT_RST ( BIT(6) ) +#define BIT_SIM2_SOFT_RST ( BIT(5) ) +#define BIT_SIM1_SOFT_RST ( BIT(4) ) +#define BIT_SIM0_SOFT_RST ( BIT(3) ) +#define BIT_UART1_SOFT_RST ( BIT(2) ) +#define BIT_UART0_SOFT_RST ( BIT(1) ) +#define BIT_WDG_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_MCU_RST */ +#define BIT_MCU_SOFT_RST_SET ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_CLK_SEL0 */ +#define BIT_CLK_IIS3_PAD_SEL ( BIT(19) ) +#define BIT_CLK_IIS2_PAD_SEL ( BIT(18) ) +#define BIT_CLK_IIS1_PAD_SEL ( BIT(17) ) +#define BIT_CLK_IIS0_PAD_SEL ( BIT(16) ) +#define BITS_CLK_UART2_SEL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_CLK_IIS3_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_CLK_IIS2_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_CLK_IIS1_SEL(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_CLK_IIS0_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CLK_UART1_SEL(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_CLK_UART0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CP_APB_RF_APB_CLK_DIV0 */ +#define BITS_CLK_IIS2_DIV(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_CLK_IIS1_DIV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)) ) +#define BITS_CLK_IIS0_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_CLK_UART1_DIV(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BITS_CLK_UART0_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_CP_APB_RF_APB_ARCH_EB */ +#define BITS_CLK_UART2_DIV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)) ) +#define BITS_CLK_IIS3_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_RTC_ARCH_EB ( BIT(1) ) +#define BIT_APB_ARCH_EB ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_MISC_CTL0 */ +#define BIT_GGE_ALL_CLK_EN ( BIT(29) ) +#define BIT_ALL_CLK_EN ( BIT(28) ) +#define BIT_DMA_LSLP_EN ( BIT(27) ) +#define BIT_WAKEUP_XTL_EN_3G_W ( BIT(26) ) +#define BIT_WAKEUP_XTL_EN_2G ( BIT(25) ) +#define BIT_ARM_JTAG_EN ( BIT(24) ) +#define BIT_WAKEUP_XTL_EN_3G_TD ( BIT(23) ) +#define BIT_GGE_WAKEUP_XTL_EN_2G ( BIT(22) ) +#define BITS_ARM_FRC_STOP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) ) + +/* bits definitions for register REG_CP_APB_RF_APB_MISC_CTL1 */ +#define BITS_BUFON_CTRL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_SIM2_CLK_POLARITY ( BIT(3) ) +#define BIT_SIM1_CLK_POLARITY ( BIT(2) ) +#define BIT_SIM0_CLK_POLARITY ( BIT(1) ) +#define BIT_ROM_CLK_EN ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_PIN_SEL */ +#define BIT_DJTAG_PIN_IN_SEL ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_SLP_CTL */ +#define BITS_GGE_DEEP_SLP_DBG(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_APB_PERI_FRC_ON ( BIT(20) ) +#define BIT_APB_PERI_FRC_SLP ( BIT(16) ) +#define BIT_MCU_XTLEN_AUTOPD_EN ( BIT(12) ) +#define BIT_MCU_FORCE_GGE_LIGHT_SLEEP ( BIT(9) ) +#define BIT_MCU_FORCE_LIGHT_SLEEP ( BIT(8) ) +#define BIT_CHIP_SLP_ARM_CLR ( BIT(4) ) +#define BIT_MCU_FORCE_GGE_DEEP_SLEEP ( BIT(3) ) +#define BIT_MCU_FORCE_WSYS_LT_STOP ( BIT(2) ) +#define BIT_MCU_FORCE_WSYS_STOP ( BIT(1) ) +#define BIT_MCU_FORCE_DEEP_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_WSYS_STS */ +#define BITS_DEEP_SLP_DBG(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_WSYS_STATUS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_CP_APB_RF_APB_SLP_STS */ +#define BIT_DSP_MAHB_SLEEP_EN ( BIT(28) ) +#define BIT_MCU_PERI_STOP ( BIT(27) ) +#define BIT_DSP_PERI_STOP ( BIT(26) ) +#define BIT_ECC_CKG_EN ( BIT(25) ) +#define BIT_QBC_CKG_EN ( BIT(24) ) +#define BIT_DSP_TWPLL_EN ( BIT(21) ) +#define BIT_STC_TMR_AUTOPD_XTL_EN ( BIT(20) ) +#define BIT_RFT_TMR_AUTOPD_XTL_EN ( BIT(19) ) +#define BIT_STC_TMR_AUTOPD_RF_EN ( BIT(18) ) +#define BIT_RFT_TMR_AUTOPD_RF_EN ( BIT(17) ) +#define BIT_CHIP_SLEEP_REC_ARM ( BIT(16) ) +#define BIT_DSP_CORE_STOP ( BIT(15) ) +#define BIT_DSP_MTX_STOP ( BIT(14) ) +#define BIT_DSP_AHB_STOP ( BIT(13) ) +#define BIT_DSP_SYS_STOP ( BIT(12) ) +#define BIT_DSP_DEEP_STOP ( BIT(11) ) +#define BIT_ASHB_DSPTOARM_EN ( BIT(10) ) +#define BIT_ASHB_ARMTODSP_VALID ( BIT(9) ) +#define BIT_EMC_STOP_CH3 ( BIT(8) ) +#define BIT_EMC_STOP_CH4 ( BIT(7) ) +#define BIT_EMC_STOP_CH5 ( BIT(6) ) +#define BIT_FRC_WAKE_EN ( BIT(5) ) +#define BIT_TMR_WAKE_AFC ( BIT(4) ) +#define BIT_SCH_SLEEP ( BIT(3) ) +#define BIT_DSP_STOP ( BIT(2) ) +#define BIT_MCU_STOP ( BIT(1) ) +#define BIT_EMC_STOP ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_ROM_PD_CTL */ +#define BIT_GGE_ROM_FORCE_ON ( BIT(1) ) +#define BIT_ROM_FORCE_ON ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_BUS_CTL0 */ +#define BIT_IIS3_DSP_CTRL_SEL ( BIT(11) ) +#define BIT_IIS2_DSP_CTRL_SEL ( BIT(10) ) +#define BIT_IIS1_DSP_CTRL_SEL ( BIT(9) ) +#define BIT_IIS0_DSP_CTRL_SEL ( BIT(8) ) +#define BIT_UART2_CTRL_SEL ( BIT(7) ) +#define BIT_RFFE_CTRL_SEL ( BIT(5) ) +#define BIT_IIS3_CTRL_SEL ( BIT(4) ) +#define BIT_IIS2_CTRL_SEL ( BIT(3) ) +#define BIT_IIS1_CTRL_SEL ( BIT(2) ) +#define BIT_IIS0_CTRL_SEL ( BIT(1) ) +#define BIT_UART1_CTRL_SEL ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_DSP_INT_CLR */ +#define BIT_RFT_INT_CLR ( BIT(2) ) + +/* bits definitions for register REG_CP_APB_RF_APB_MISC_INT_STS */ +#define BIT_RFT_INT ( BIT(2) ) + +/* bits definitions for register REG_CP_APB_RF_APB_HWRST */ +#define BITS_HWRST_REG(_X_) (_X_) + +/* bits definitions for register REG_CP_APB_RF_APB_ARM_BOOT_ADDR */ +#define BITS_ARMBOOT_ADDR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_CP_APB_RF_APB_GGE_SLP_STS */ +#define BIT_GGE_DSP_MAHB_SLEEP_EN ( BIT(21) ) +#define BIT_GGE_DSP_PERI_STOP ( BIT(20) ) +#define BIT_GGE_QBC_CKG_EN ( BIT(19) ) +#define BIT_GGE_DSP_TWPLL_EN ( BIT(18) ) +#define BIT_GGE_STC_TMR_AUTOPD_XTL_EN ( BIT(17) ) +#define BIT_GGE_STC_TMR_AUTOPD_RF_EN ( BIT(16) ) +#define BIT_GGE_DSP_CORE_STOP ( BIT(15) ) +#define BIT_GGE_DSP_MTX_STOP ( BIT(14) ) +#define BIT_GGE_DSP_AHB_STOP ( BIT(13) ) +#define BIT_GGE_DSP_SYS_STOP ( BIT(12) ) +#define BIT_GGE_DSP_DEEP_STOP ( BIT(11) ) +#define BIT_GGE_ASHB_DSPTOARM_EN ( BIT(10) ) +#define BIT_GGE_ASHB_ARMTODSP_VALID ( BIT(9) ) +#define BIT_GGE_EMC_STOP_CH3 ( BIT(8) ) +#define BIT_GGE_EMC_STOP_CH4 ( BIT(7) ) +#define BIT_GGE_EMC_STOP_CH5 ( BIT(6) ) +#define BIT_GGE_FRC_WAKE_EN ( BIT(5) ) +#define BIT_GGE_TMR_WAKE_AFC ( BIT(4) ) +#define BIT_GGE_SCH_SLEEP ( BIT(3) ) +#define BIT_GGE_DSP_STOP ( BIT(2) ) +#define BIT_GGE_MCU_STOP ( BIT(1) ) +#define BIT_GGE_EMC_STOP ( BIT(0) ) + +#endif diff --git a/include/soc/sprd/chip_x35l/__regs_djtag_apb_rf.h b/include/soc/sprd/chip_x35l/__regs_djtag_apb_rf.h new file mode 100755 index 00000000..7aa4d044 --- /dev/null +++ b/include/soc/sprd/chip_x35l/__regs_djtag_apb_rf.h @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_DJTAG_APB_RF_HEADFILE_H__ +#define __H_REGS_DJTAG_APB_RF_HEADFILE_H__ __FILE__ + +#define REGS_DJTAG_APB_RF + +/* registers definitions for DJTAG_APB_RF */ +#define REG_DJTAG_APB_RF_DJTAG_IR_LEN_CFG SCI_ADDR(REGS_DJTAG_APB_RF_BASE, 0x0000) +#define REG_DJTAG_APB_RF_DJTAG_DR_LEN_CFG SCI_ADDR(REGS_DJTAG_APB_RF_BASE, 0x0004) +#define REG_DJTAG_APB_RF_DJTAG_IR_CFG SCI_ADDR(REGS_DJTAG_APB_RF_BASE, 0x0008) +#define REG_DJTAG_APB_RF_DJTAG_DR_CFG SCI_ADDR(REGS_DJTAG_APB_RF_BASE, 0x000C) +#define REG_DJTAG_APB_RF_DR_PAUSE_RECOV_CFG SCI_ADDR(REGS_DJTAG_APB_RF_BASE, 0x0010) +#define REG_DJTAG_APB_RF_DJTAG_RND_EN_CFG SCI_ADDR(REGS_DJTAG_APB_RF_BASE, 0x0014) +#define REG_DJTAG_APB_RF_DJTAG_UPD_DR_CFG SCI_ADDR(REGS_DJTAG_APB_RF_BASE, 0x0018) + + + +/* bits definitions for register REG_DJTAG_APB_RF_DJTAG_IR_LEN_CFG */ +#define BITS_IR_LEN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_DJTAG_APB_RF_DJTAG_DR_LEN_CFG */ +#define BITS_DR_LEN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_DJTAG_APB_RF_DJTAG_IR_CFG */ +#define BITS_DJTAG_IR(_X_) (_X_) + +/* bits definitions for register REG_DJTAG_APB_RF_DJTAG_DR_CFG */ +#define BITS_DJTAG_DR(_X_) (_X_) + +/* bits definitions for register REG_DJTAG_APB_RF_DR_PAUSE_RECOV_CFG */ +#define BIT_DR_PAUSE_RECOV ( BIT(0) ) + +/* bits definitions for register REG_DJTAG_APB_RF_DJTAG_RND_EN_CFG */ +#define BIT_DJTAG_RND_EN ( BIT(0) ) + +/* bits definitions for register REG_DJTAG_APB_RF_DJTAG_UPD_DR_CFG */ +#define BITS_DJTAG_UPD_DR(_X_) (_X_) + +#endif diff --git a/include/soc/sprd/chip_x35l/__regs_gpu_apb_rf.h b/include/soc/sprd/chip_x35l/__regs_gpu_apb_rf.h new file mode 100755 index 00000000..4144705a --- /dev/null +++ b/include/soc/sprd/chip_x35l/__regs_gpu_apb_rf.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_GPU_APB_HEADFILE_H__ +#define __H_REGS_GPU_APB_HEADFILE_H__ __FILE__ + +#define REGS_GPU_APB_RF + +/* registers definitions for GPU_APB_RF */ +#define REG_GPU_APB_APB_RST SCI_ADDR(REGS_GPU_APB_BASE, 0x0000) +#define REG_GPU_APB_APB_CLK_CTRL SCI_ADDR(REGS_GPU_APB_BASE, 0x0004) + + + +/* bits definitions for register REG_GPU_APB_RF_APB_RST */ +#define BIT_GPU_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_GPU_APB_APB_CLK_CTRL */ +#define BITS_CLK_GPU_DIV(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CLK_GPU_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +#endif diff --git a/include/soc/sprd/chip_x35l/__regs_lte_cevax_pmu.h b/include/soc/sprd/chip_x35l/__regs_lte_cevax_pmu.h new file mode 100755 index 00000000..dd8f631a --- /dev/null +++ b/include/soc/sprd/chip_x35l/__regs_lte_cevax_pmu.h @@ -0,0 +1,376 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_LTE_CEVAX_PMU_HEADFILE_H__ +#define __H_REGS_LTE_CEVAX_PMU_HEADFILE_H__ __FILE__ + +#define REGS_LTE_CEVAX_PMU + +/* registers definitions for LTE_CEVAX_PMU */ +#define REG_LTE_CEVAX_PMU_PLL_CFG0 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0000) +#define REG_LTE_CEVAX_PMU_PLL_CFG1 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0004) +#define REG_LTE_CEVAX_PMU_CXCLK_DIV SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0008) +#define REG_LTE_CEVAX_PMU_XHCLK_DIV SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x000C) +#define REG_LTE_CEVAX_PMU_XPCLK_DIV SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0010) +#define REG_LTE_CEVAX_PMU_CXPMOD SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0014) +#define REG_LTE_CEVAX_PMU_XHPMOD SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0018) +#define REG_LTE_CEVAX_PMU_XAPBMOD SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x001C) +#define REG_LTE_CEVAX_PMU_VERSION_CR SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0020) +#define REG_LTE_CEVAX_PMU_SLEEP_STATUS SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0024) +#define REG_LTE_CEVAX_PMU_POW_CTL0 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0028) +#define REG_LTE_CEVAX_PMU_POW_CTL1 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x002C) +#define REG_LTE_CEVAX_PMU_POW_CTL2 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0030) +#define REG_LTE_CEVAX_PMU_ACCCLK_EN0 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0034) +#define REG_LTE_CEVAX_PMU_ACCCLK_EN1 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0038) +#define REG_LTE_CEVAX_PMU_ACCCLK_EN2 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x003C) +#define REG_LTE_CEVAX_PMU_SOFT_RST0 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0040) +#define REG_LTE_CEVAX_PMU_SOFT_RST1 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0044) +#define REG_LTE_CEVAX_PMU_DSP_CKG_SEL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0048) +#define REG_LTE_CEVAX_PMU_CLK_DLCH_SEL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0050) +#define REG_LTE_CEVAX_PMU_CLK_ULCH_SEL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0054) +#define REG_LTE_CEVAX_PMU_CLK_RATEM_SEL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0058) +#define REG_LTE_CEVAX_PMU_CLK_LTE_SPI_DIV_SEL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x005C) +#define REG_LTE_CEVAX_PMU_CX_CKG_DIV SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0078) +#define REG_LTE_CEVAX_PMU_XH_CKG_DIV SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x007C) +#define REG_LTE_CEVAX_PMU_XP_CKG_DIV SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0080) +#define REG_LTE_CEVAX_PMU_LTE_PMU_CKG_EN SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0084) +#define REG_LTE_CEVAX_PMU_LTE_PMU_CLK_EN SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0088) +#define REG_LTE_CEVAX_PMU_APB_CLK_SEL0 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x008C) +#define REG_LTE_CEVAX_PMU_APB_CLK_SEL1 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0090) +#define REG_LTE_CEVAX_PMU_CLK_CXTMR0_SEL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0094) +#define REG_LTE_CEVAX_PMU_CLK_CXTMR1_SEL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0098) +#define REG_LTE_CEVAX_PMU_CLK_CXTMR2_SEL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x009C) +#define REG_LTE_CEVAX_PMU_APB_CLK_SEL2 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x00A0) +#define REG_LTE_CEVAX_PMU_MEM_LP_CTRL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0xA4) +#define REG_LTE_CEVAX_PMU_XC321_BOOT SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0120) +#define REG_LTE_CEVAX_PMU_XC321_CORE_RST SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0124) +#define REG_LTE_CEVAX_PMU_XC321_BVECTOR SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0128) +#define REG_LTE_CEVAX_PMU_RES_REG0 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0140) +#define REG_LTE_CEVAX_PMU_RES_REG1 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0144) +#define REG_LTE_CEVAX_PMU_RES_REG2 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0148) + + + +/* bits definitions for register REG_LTE_CEVAX_PMU_PLL_CFG0 */ +#define BITS_PLL_CFG0_R(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_IIS3_EB ( BIT(10) ) +#define BIT_IIS2_EB ( BIT(9) ) +#define BIT_DSP_DLCH_EN ( BIT(8) ) +#define BIT_DSP_ULCH_EN ( BIT(7) ) +#define BIT_DLCH_AUTO_EN ( BIT(6) ) +#define BIT_ULCH_AUTO_EN ( BIT(5) ) +#define BIT_IIS1_EB ( BIT(4) ) +#define BIT_IIS0_EB ( BIT(3) ) +#define BIT_UART1_EB ( BIT(2) ) +#define BIT_UART0_EB ( BIT(1) ) +#define BIT_RFFE_EB ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_PLL_CFG1 */ +#define BIT_CHIP_SLP_REC_DSP ( BIT(16) ) +#define BIT_LTE_POW_OFF ( BIT(10) ) +#define BIT_LTE_POW_READY ( BIT(9) ) +#define BITS_LTE_POW_WAIT(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) ) +#define BIT_CHIP_SLP_DSP_CLR ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CXCLK_DIV */ +#define BITS_CXREG_AUTO_OFF(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_XHCLK_DIV */ +#define BIT_BUSMON2_CHN_SEL ( BIT(25) ) +#define BIT_BUSMON1_CHN_SEL ( BIT(24) ) +#define BIT_BUSMON0_CHN_SEL ( BIT(23) ) +#define BITS_DSP_SHM_CTRL(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BIT_DSPAPB_DES_AUTO_EN ( BIT(20) ) +#define BIT_DSPAHB_DES_AUTO_EN ( BIT(19) ) +#define BITS_LBUSMON2_CHN_SEL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_LBUSMON1_CHN_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_LBUSMON0_CHN_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_DSPAPB_DIV_DES(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DSPAHB_DIV_DES(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)) ) +#define BITS_CX_DSPPLL_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_XPCLK_DIV */ +#define BIT_PMU_DMA_FRC_EB ( BIT(24) ) +#define BIT_ZBUS_32ACCESS ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CXPMOD */ +#define BIT_MCU_FORCE_DEEP_SLEEP ( BIT(31) ) +#define BIT_LDSP_DEEP_SLP_CTRL ( BIT(30) ) +#define BIT_EMC_LIGHT_SLEEP_EN_M6 ( BIT(29) ) +#define BIT_EMC_DEEP_SLEEP_EN_M6 ( BIT(28) ) +#define BIT_EMC_LIGHT_SLEEP_EN_M7 ( BIT(27) ) +#define BIT_EMC_DEEP_SLEEP_EN_M7 ( BIT(26) ) +#define BIT_EMC_LIGHT_SLEEP_EN_M8 ( BIT(25) ) +#define BIT_EMC_DEEP_SLEEP_EN_M8 ( BIT(24) ) +#define BIT_LDSP2PUB_ACCESS_EN ( BIT(8) ) +#define BIT_LDSP_WAKEUP_XTL_EN ( BIT(7) ) +#define BIT_DMA_LSLP_EN ( BIT(4) ) +#define BIT_DSP_LIGHT_SLEEP_EN ( BIT(3) ) +#define BIT_DSP_DEEP_SLEEP_EN ( BIT(2) ) +#define BIT_DSP_SYS_SLEEP_EN ( BIT(1) ) +#define BIT_DSP_CORE_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_XHPMOD */ +#define BIT_BUSMON2_EB ( BIT(31) ) +#define BIT_BUSMON1_EB ( BIT(30) ) +#define BIT_BUSMON0_EB ( BIT(29) ) +#define BIT_LACCX_AUTO_GATE_EN ( BIT(14) ) +#define BIT_LDSPX_AUTO_GATE_EN ( BIT(13) ) +#define BIT_CXDMA_CLK_AUTO_EN ( BIT(12) ) +#define BIT_CXAPB_AUTO_GATE_EN ( BIT(11) ) +#define BIT_CXAHB_AUTO_GATE_EN ( BIT(10) ) +#define BIT_CXDSP_AUTO_GATE_EN ( BIT(9) ) +#define BIT_CXCORE_AUTO_GATE_EN ( BIT(8) ) +#define BIT_CXMTX_AUTO_GATE_EN ( BIT(7) ) +#define BIT_DSP_MAHB_SLEEP_EN ( BIT(6) ) +#define BIT_ACCZ_ARCH_EB ( BIT(5) ) +#define BIT_CXBUS_ARCH_EB ( BIT(4) ) +#define BIT_LTEPROC_ARCH_EB ( BIT(3) ) +#define BIT_PMU_DLCH_SLEEP_R ( BIT(1) ) +#define BIT_PMU_ULCH_SLEEP_R ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_XAPBMOD */ +#define BITS_HPROTDMAW(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_HPROTDMAR(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_PMU_XPSLEEP_P_R(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_VERSION_CR */ +#define BITS_VERSION_CR(_X_) (_X_) + +/* bits definitions for register REG_LTE_CEVAX_PMU_SLEEP_STATUS */ +#define BITS_PMU_SLEEP_STATUS(_X_) (_X_) + +/* bits definitions for register REG_LTE_CEVAX_PMU_POW_CTL0 */ +#define BITS_LTE_ISO_ON_NUM(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LTE_ISO_OFF_NUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_POW_CTL1 */ +#define BIT_CLK_PWR_LTE_SEL ( BIT(10) ) +#define BIT_LTE_SLP_POWOFF_AUTO_EN ( BIT(9) ) +#define BIT_LTE_POW_FORCE_PD ( BIT(8) ) +#define BITS_DSP_MEM_PD_REG(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_POW_CTL2 */ +#define BITS_DSP_MEM_PD_EN(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)) ) +#define BITS_PD_LTE_STATUS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_ACCCLK_EN0 */ +#define BIT_FFT_OFFLN_HCLKEN ( BIT(30) ) +#define BIT_FFT_OFFLN_CLKEN ( BIT(29) ) +#define BIT_FFT_ONLN_HCLKEN ( BIT(28) ) +#define BIT_FFT_ONLN_CLKEN ( BIT(27) ) +#define BIT_LTE_DRM_CLKEN ( BIT(24) ) +#define BIT_MIMO_HCLKEN ( BIT(23) ) +#define BIT_MIMO_CLKEN ( BIT(22) ) +#define BIT_PBCH_ACLKEN ( BIT(21) ) +#define BIT_PBCH_HCLKEN ( BIT(20) ) +#define BIT_PBCH_CLKEN ( BIT(19) ) +#define BIT_PCFICH_PHICH_HCLKEN ( BIT(18) ) +#define BIT_PCFICH_PHICH_CLKEN ( BIT(17) ) +#define BIT_PDCCH_ACLKEN ( BIT(16) ) +#define BIT_PDCCH_HCLKEN ( BIT(15) ) +#define BIT_PDCCH_CLKEN ( BIT(14) ) +#define BIT_PDSCH_TB_CTL_HCLKEN ( BIT(13) ) +#define BIT_PDSCH_TB_CTL_CLKEN ( BIT(12) ) +#define BIT_RXDFE_HCLKEN ( BIT(11) ) +#define BIT_SYNC_ACLKEN ( BIT(10) ) +#define BIT_SYNC_HCLKEN ( BIT(9) ) +#define BIT_SYNC_CLKEN ( BIT(8) ) +#define BIT_TBUF_ACLKEN ( BIT(7) ) +#define BIT_TBUF_HCLKEN ( BIT(6) ) +#define BIT_TBUF_CLKEN ( BIT(5) ) +#define BIT_VTB_CLKEN ( BIT(4) ) +#define BIT_LTE_PROC_HCLKEN ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_ACCCLK_EN1 */ +#define BIT_LBUSMON2_EB ( BIT(28) ) +#define BIT_LBUSMON1_EB ( BIT(27) ) +#define BIT_LBUSMON0_EB ( BIT(26) ) +#define BIT_HSDL_CLKEN ( BIT(25) ) +#define BIT_ULMAC_HCLKEN ( BIT(24) ) +#define BIT_TBE_HCLKEN ( BIT(23) ) +#define BIT_TBE_CLKEN ( BIT(22) ) +#define BIT_RM_HCLKEN ( BIT(21) ) +#define BIT_RM_CLKEN ( BIT(20) ) +#define BIT_PCM_HCLKEN ( BIT(19) ) +#define BIT_PCM_CLKEN ( BIT(18) ) +#define BIT_UCM_HCLKEN ( BIT(17) ) +#define BIT_UCM_CLKEN ( BIT(16) ) +#define BIT_CHE_ACLKEN ( BIT(15) ) +#define BIT_CHE_HCLKEN ( BIT(14) ) +#define BIT_CHE_SYS_CLKEN ( BIT(13) ) +#define BIT_CHEPP_ACLKEN ( BIT(12) ) +#define BIT_CHEPP_HCLKEN ( BIT(11) ) +#define BIT_CHEPP_SYS_CLKEN ( BIT(10) ) +#define BIT_DBUF_ACLKEN ( BIT(9) ) +#define BIT_DBUF_HCLKEN ( BIT(8) ) +#define BIT_DBUF_CLKEN ( BIT(7) ) +#define BIT_DFE_CLKEN ( BIT(6) ) +#define BIT_FBUF_ACLKEN ( BIT(5) ) +#define BIT_FBUF_HCLKEN ( BIT(4) ) +#define BIT_FBUF_CLKEN ( BIT(3) ) +#define BIT_FEC_ACLKEN ( BIT(2) ) +#define BIT_FEC_HCLKEN ( BIT(1) ) +#define BIT_FEC_CLKEN ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_ACCCLK_EN2 */ + +/* bits definitions for register REG_LTE_CEVAX_PMU_SOFT_RST0 */ +#define BITS_SOFT_RST_R(_X_) (_X_) + +/* bits definitions for register REG_LTE_CEVAX_PMU_SOFT_RST1 */ +#define BIT_LTE_PROC_SOFT_RST_RFT ( BIT(31) ) +#define BIT_HSDL_SOFT_RST ( BIT(30) ) +#define BIT_RFSPI_SOFT_RST ( BIT(29) ) +#define BIT_LTE_PROC_SOFT_RST ( BIT(28) ) +#define BIT_ULMAC_SOFT_RST ( BIT(27) ) +#define BIT_PCM_SOFT_RST ( BIT(26) ) +#define BIT_UCM_SOFT_RST ( BIT(25) ) +#define BIT_TBE_SOFT_RST ( BIT(24) ) +#define BIT_RM_SOFT_RST ( BIT(23) ) +#define BIT_RFT_SOFT_RST ( BIT(22) ) +#define BIT_DFE_SOFT_RST ( BIT(21) ) +#define BIT_MIMO_SOFT_RST ( BIT(20) ) +#define BIT_ON_LINE_FFT_SOFT_RST ( BIT(19) ) +#define BIT_OFF_LINE_FFT_SOFT_RST ( BIT(18) ) +#define BIT_PCFICH_SOFT_RST ( BIT(17) ) +#define BIT_PDSCH_SOFT_RST ( BIT(16) ) +#define BIT_DRM_SOFT_RST ( BIT(15) ) +#define BIT_VTB_SOFT_RST ( BIT(14) ) +#define BIT_FEC_SOFT_RST ( BIT(13) ) +#define BIT_CHE_SOFT_RST ( BIT(12) ) +#define BIT_CHEPP_SOFT_RST ( BIT(11) ) +#define BIT_SYNC_SOFT_RST ( BIT(10) ) +#define BIT_TBUF_SOFT_RST ( BIT(9) ) +#define BIT_DBUF_SOFT_RST ( BIT(8) ) +#define BIT_FBUF_SOFT_RST ( BIT(7) ) +#define BIT_PDCCH_SOFT_RST ( BIT(6) ) +#define BIT_PBCH_SOFT_RST ( BIT(5) ) +#define BIT_RXADC_SOFT_RST ( BIT(4) ) +#define BIT_TXDAC_SOFT_RST ( BIT(3) ) +#define BIT_CAL_SOFT_RST ( BIT(2) ) +#define BIT_RTC_SOFT_RST ( BIT(1) ) +#define BIT_LTE_SPI_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_DSP_CKG_SEL */ +#define BITS_DSP_CKG_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CLK_DLCH_SEL */ +#define BITS_CLK_DLCH_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CLK_ULCH_SEL */ +#define BITS_CLK_ULCH_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CLK_RATEM_SEL */ +#define BITS_CLK_RATEM_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CLK_LTE_SPI_DIV_SEL */ +#define BITS_CLK_LTE_SPI_DIV(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)) ) +#define BITS_CLK_LTE_SPI_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CX_CKG_DIV */ +#define BITS_CX_CKG_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_XH_CKG_DIV */ +#define BITS_XH_CKG_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_XP_CKG_DIV */ +#define BITS_XP_CKG_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_LTE_PMU_CKG_EN */ +#define BIT_DSP_CKG_EN ( BIT(8) ) +#define BIT_CX_CKG_EN ( BIT(6) ) +#define BIT_XH_CKG_EN ( BIT(5) ) +#define BIT_XP_CKG_EN ( BIT(4) ) +#define BIT_DMA_CKG_EN ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_LTE_PMU_CLK_EN */ +#define BIT_CLK_LTE_SA_EN ( BIT(17) ) +#define BIT_CLK_CXTMR2_EN ( BIT(16) ) +#define BIT_CLK_CXTMR1_EN ( BIT(15) ) +#define BIT_CLK_CXTMR0_EN ( BIT(14) ) +#define BIT_CLK_AXI_EN ( BIT(13) ) +#define BIT_CLK_AHB_EN ( BIT(12) ) +#define BIT_CLK_DFE_EN ( BIT(11) ) +#define BIT_CLK_RFT_EN ( BIT(10) ) +#define BIT_CLK_DLCH_EN ( BIT(9) ) +#define BIT_CLK_ULCH_EN ( BIT(8) ) +#define BIT_CLK_RATEM_EN ( BIT(7) ) +#define BIT_CLK_RXADC_EN ( BIT(6) ) +#define BIT_CLK_TXDAC_EN ( BIT(5) ) +#define BIT_CLK_LTE_ANA_2X_EN ( BIT(4) ) +#define BIT_CLK_LTE_ANA_1X_EN ( BIT(3) ) +#define BIT_CLK_CAL_EN ( BIT(2) ) +#define BIT_CLK_RTC_EN ( BIT(1) ) +#define BIT_CLK_LTE_SPI_EN ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_APB_CLK_SEL0 */ +#define BITS_CLK_UART1_DIV(_X_) ( (_X_) << 7 & (BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_CLK_UART1_SEL(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)) ) +#define BITS_CLK_UART0_DIV(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)) ) +#define BITS_CLK_UART0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_APB_CLK_SEL1 */ +#define BITS_CLK_IIS1_DIV(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_CLK_IIS1_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_CLK_IIS0_DIV(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_CLK_IIS0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CLK_CXTMR0_SEL */ +#define BITS_CLK_CXTMR0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CLK_CXTMR1_SEL */ +#define BITS_CLK_CXTMR1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CLK_CXTMR2_SEL */ +#define BITS_CLK_CXTMR2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_APB_CLK_SEL2 */ +#define BITS_CLK_IIS3_DIV(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_CLK_IIS3_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_CLK_IIS2_DIV(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_CLK_IIS2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_MEM_LP_CTRL */ +#define BITS_MEM_LP_CTRL(_X_) (_X_) +/* bits definitions for register REG_LTE_CEVAX_PMU_XC321_BOOT */ +#define BIT_FRC_CLK_XC321_EN ( BIT(1) ) +#define BIT_XC321_BOOT ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_XC321_CORE_RST */ +#define BIT_XC321_SYS_SRST ( BIT(1) ) +#define BIT_XC321_CORE_SRST_N ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_XC321_BVECTOR */ +#define BITS_XC321_BOOT_VECTOR(_X_) (_X_) + +/* bits definitions for register REG_LTE_CEVAX_PMU_RES_REG0 */ +#define BITS_RES_REG0(_X_) (_X_) + +/* bits definitions for register REG_LTE_CEVAX_PMU_RES_REG1 */ +#define BITS_RES_REG1(_X_) (_X_) + +/* bits definitions for register REG_LTE_CEVAX_PMU_RES_REG2 */ +#define BITS_RES_REG2(_X_) (_X_) + +#endif diff --git a/include/soc/sprd/chip_x35l/__regs_mdar_apb_rf.h b/include/soc/sprd/chip_x35l/__regs_mdar_apb_rf.h new file mode 100755 index 00000000..5416a02f --- /dev/null +++ b/include/soc/sprd/chip_x35l/__regs_mdar_apb_rf.h @@ -0,0 +1,1181 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_MDAR_APB_RF_HEADFILE_H__ +#define __H_REGS_MDAR_APB_RF_HEADFILE_H__ __FILE__ + +#define REGS_MDAR_APB_RF + +/* registers definitions for MDAR_APB_RF */ +#define REG_MDAR_APB_RF_MDAR_CFG0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0000) +#define REG_MDAR_APB_RF_MDAR_CFG1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0004) +#define REG_MDAR_APB_RF_MDAR_CFG3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x000C) +#define REG_MDAR_APB_RF_MDAR_DAC1_CTR1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0010) +#define REG_MDAR_APB_RF_MDAR_DAC1_CTR2 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0014) +#define REG_MDAR_APB_RF_MDAR_DAC1_CTR3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0018) +#define REG_MDAR_APB_RF_MDAR_DAC1_CTR4 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x001C) +#define REG_MDAR_APB_RF_MDAR_DAC1_STS0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0020) +#define REG_MDAR_APB_RF_MDAR_DAC1_STS1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0024) +#define REG_MDAR_APB_RF_MDAR_CAL1_CTR0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0028) +#define REG_MDAR_APB_RF_MDAR_CAL1_CTR1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x002C) +#define REG_MDAR_APB_RF_MDAR_CAL1_CTR3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0030) +#define REG_MDAR_APB_RF_MDAR_CAL1_STS0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0034) +#define REG_MDAR_APB_RF_MDAR_CAL1_STS1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0038) +#define REG_MDAR_APB_RF_MDAR_DAC1_CTR00 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x003C) +#define REG_MDAR_APB_RF_MDAR_DAC1_CTR10 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0040) +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0044) +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR00 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0048) +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR01 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x004C) +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR02 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0050) +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR10 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0054) +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR11 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0058) +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR12 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x005C) +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR20 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0060) +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR21 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0064) +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR22 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0068) +#define REG_MDAR_APB_RF_MDAR_DAC2_CTR1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0070) +#define REG_MDAR_APB_RF_MDAR_DAC2_CTR2 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0074) +#define REG_MDAR_APB_RF_MDAR_DAC2_CTR3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0078) +#define REG_MDAR_APB_RF_MDAR_DAC2_CTR4 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x007C) +#define REG_MDAR_APB_RF_MDAR_DAC2_STS0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0080) +#define REG_MDAR_APB_RF_MDAR_DAC2_STS1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0084) +#define REG_MDAR_APB_RF_MDAR_CAL2_CTR0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0088) +#define REG_MDAR_APB_RF_MDAR_CAL2_CTR1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x008C) +#define REG_MDAR_APB_RF_MDAR_CAL2_CTR3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0090) +#define REG_MDAR_APB_RF_MDAR_CAL2_STS0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0094) +#define REG_MDAR_APB_RF_MDAR_CAL2_STS1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0098) +#define REG_MDAR_APB_RF_MDAR_DAC2_CTR00 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x009C) +#define REG_MDAR_APB_RF_MDAR_DAC2_CTR10 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00A0) +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00A4) +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR00 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00A8) +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR01 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00AC) +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR02 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00B0) +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR10 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00B4) +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR11 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00B8) +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR12 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00BC) +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR20 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00C0) +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR21 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00C4) +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR22 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00C8) +#define REG_MDAR_APB_RF_MDAR_DAC3_CTR1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00D0) +#define REG_MDAR_APB_RF_MDAR_DAC3_CTR2 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00D4) +#define REG_MDAR_APB_RF_MDAR_DAC3_CTR3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00D8) +#define REG_MDAR_APB_RF_MDAR_DAC3_CTR4 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00DC) +#define REG_MDAR_APB_RF_MDAR_DAC3_STS0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00E0) +#define REG_MDAR_APB_RF_MDAR_DAC3_STS1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00E4) +#define REG_MDAR_APB_RF_MDAR_CAL3_CTR0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00E8) +#define REG_MDAR_APB_RF_MDAR_CAL3_CTR1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00EC) +#define REG_MDAR_APB_RF_MDAR_CAL3_CTR3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00F0) +#define REG_MDAR_APB_RF_MDAR_CAL3_STS0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00F4) +#define REG_MDAR_APB_RF_MDAR_CAL3_STS1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00F8) +#define REG_MDAR_APB_RF_MDAR_DAC3_CTR00 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00FC) +#define REG_MDAR_APB_RF_MDAR_DAC3_CTR10 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0100) +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0104) +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR00 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0108) +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR01 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x010C) +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR02 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0110) +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR10 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0114) +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR11 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0118) +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR12 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x011C) +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR20 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0120) +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR21 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0124) +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR22 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0128) +#define REG_MDAR_APB_RF_MDAR_AFCDAC1_CFG SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x012C) +#define REG_MDAR_APB_RF_MDAR_AFCDAC2_CFG SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0130) +#define REG_MDAR_APB_RF_MDAR_APCDAC1_CFG SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0134) +#define REG_MDAR_APB_RF_MDAR_APCDAC2_CFG SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0138) +#define REG_MDAR_APB_RF_MDAR_RFSPI_CFG SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x13C) +#define REG_MDAR_APB_RF_MDAR_RFMIPI_CFG SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x140) +#define REG_MDAR_APB_RF_MDAR_APCDAC_OUTSEL SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x144) +#define REG_MDAR_APB_RF_MDAR_CLASH_CHK SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x148) +#define REG_MDAR_APB_RF_MDAR_CLASH_SNAP SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x14C) +#define REG_MDAR_APB_RF_MDAR_CLASH_STATUS1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x150) +#define REG_MDAR_APB_RF_MDAR_CLASH_STATUS2 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x154) +#define REG_MDAR_APB_RF_MDAR_CLASH_STATUS3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x158) +#define REG_MDAR_APB_RF_MDAR_EXTRA_CFG0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x160) +#define REG_MDAR_APB_RF_MDAR_EXTRA_CFG1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x164) +#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x168) +#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x16C) +#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF2 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x170) +#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x174) +#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF4 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x178) +#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF5 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x17C) +#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF6 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x180) +#define REG_MDAR_APB_RF_MDAR_CFG4 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0184) +#define REG_MDAR_APB_RF_MDAR_CFG5 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0188) +#define REG_MDAR_APB_RF_MDAR_CFG6 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x018C) +#define REG_MDAR_APB_RF_MDAR_CFG7 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0190) +#define REG_MDAR_APB_RF_MDAR_CFG8 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0194) +#define REG_MDAR_APB_RF_MDAR_CFG9 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0198) +#define REG_MDAR_APB_RF_MDAR_CFG10 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x019C) +#define REG_MDAR_APB_RF_MDAR_CFG11 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x01B0) +#define REG_MDAR_APB_RF_MDAR_CFG12 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x01B4) +#define REG_MDAR_APB_RF_MDAR_CFG13 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x01B8) +#define REG_MDAR_APB_RF_MDAR_CFG14 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x01BC) +#define REG_MDAR_APB_RF_MDAR_CFG15 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1C0) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG10 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1C4) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG11 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1C8) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG12 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1CC) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG13 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1D0) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG14 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1D4) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG20 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1D8) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG21 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1DC) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG22 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1E0) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG23 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1E4) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG24 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1E8) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG30 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1EC) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG31 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1F0) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG32 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1F4) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG33 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1F8) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG34 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1FC) + + + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG0 */ +#define BIT_MDAR_ADA_MODE ( BIT(31) ) +#define BITS_ADC3_CHANNEL_SSET(_X_) ( (_X_) << 26 & (BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_ADC2_CHANNEL_SSET(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_ADC1_CHANNEL_SSET(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)) ) +#define BIT_MDAR_WTG_MODE ( BIT(15) ) +#define BITS_ADC3_CHANNEL_MASK(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_ADC2_CHANNEL_MASK(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_ADC1_CHANNEL_MASK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG1 */ +#define BITS_DAC3_CHANNEL_SSET(_X_) ( (_X_) << 26 & (BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_DAC2_CHANNEL_SSET(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC1_CHANNEL_SSET(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_DAC3_CHANNEL_MASK(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_DAC2_CHANNEL_MASK(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DAC1_CHANNEL_MASK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG3 */ +#define BITS_DACX_SBC_SET(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_ADCX_SBC_SET(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_CTR1 */ +#define BITS_DAC1_WD_OVR(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DAC1_WADDR_OVR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DAC1_WLE_OVR ( BIT(2) ) +#define BIT_DAC1_W_OVR_I_QN ( BIT(1) ) +#define BIT_DAC1_W_OVR_EN ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_CTR2 */ +#define BIT_DAC1_AUTO_RST ( BIT(23) ) +#define BIT_DAC1_SOFT_RST ( BIT(22) ) +#define BIT_DAC1_OSBC ( BIT(21) ) +#define BIT_DAC1_ISBC ( BIT(20) ) +#define BIT_DAC1_OVR_EN_CAL ( BIT(19) ) +#define BIT_DAC1_EN_OOSCAL ( BIT(18) ) +#define BIT_DAC1_IQSWAP ( BIT(17) ) +#define BIT_DAC1_CAL_START ( BIT(16) ) +#define BITS_DAC1_OFFSETI(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DAC1_OFFSETQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_CTR3 */ +#define BITS_DAC1_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DAC1_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_CTR4 */ +#define BITS_DAC1_I_CAL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DAC1_Q_CAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_STS0 */ +#define BITS_DAC1_WTI(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DAC1_WTQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_STS1 */ +#define BITS_DAC1_DA_STATE(_X_) ( (_X_) << 17 & (BIT(17)|BIT(18)) ) +#define BIT_DAC1_DONE ( BIT(16) ) +#define BITS_DAC1_WQ_OVR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL1_CTR0 */ +#define BITS_ADC1_CLK_CAL_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_ADA1_CAL_WAIT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_CLK_ADA1_CAL_EN ( BIT(6) ) +#define BIT_DAC1_PD_CAL ( BIT(5) ) +#define BIT_ADC1_EN_CAL ( BIT(3) ) +#define BIT_ADC1_CAL ( BIT(1) ) +#define BIT_ADA1_MODE_SEL ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL1_CTR1 */ +#define BITS_ADC1_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) ) +#define BITS_ADC1_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL1_CTR3 */ +#define BIT_ADA1_CAL_START ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL1_STS0 */ +#define BIT_ADA1_CAL_DONE ( BIT(31) ) +#define BITS_ADC1_CAL_I_SUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL1_STS1 */ +#define BITS_ADC1_CAL_Q_SUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_CTR00 */ +#define BIT_DAC1_OUT_SEL_2 ( BIT(26) ) +#define BITS_DAC1_RSV_2(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC1_PCTRL_2(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)) ) +#define BIT_DAC1_CLK_SEL_2 ( BIT(18) ) +#define BIT_DAC1_OUT_SEL_1 ( BIT(17) ) +#define BITS_DAC1_RSV_1(_X_) ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)) ) +#define BITS_DAC1_PCTRL_1(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DAC1_CLK_SEL_1 ( BIT(9) ) +#define BIT_DAC1_OUT_SEL_0 ( BIT(8) ) +#define BITS_DAC1_RSV_0(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DAC1_PCTRL_0(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)) ) +#define BIT_DAC1_CLK_SEL_0 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_CTR10 */ +#define BIT_DAC1_OUT_SEL_5 ( BIT(26) ) +#define BITS_DAC1_RSV_5(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC1_PCTRL_5(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)) ) +#define BIT_DAC1_CLK_SEL_5 ( BIT(18) ) +#define BIT_DAC1_OUT_SEL_4 ( BIT(17) ) +#define BITS_DAC1_RSV_4(_X_) ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)) ) +#define BITS_DAC1_PCTRL_4(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DAC1_CLK_SEL_4 ( BIT(9) ) +#define BIT_DAC1_OUT_SEL_3 ( BIT(8) ) +#define BITS_DAC1_RSV_3(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DAC1_PCTRL_3(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)) ) +#define BIT_DAC1_CLK_SEL_3 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR0 */ +#define BIT_ADC1_SOFT_RST ( BIT(31) ) +#define BITS_ADC1_DLL_OUT(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_ADC1_CALRDOUT(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) ) +#define BIT_ADC1_DLL_SOFT_RST ( BIT(10) ) +#define BIT_ADC1_CAL_SOFT_RST ( BIT(9) ) +#define BIT_ADC1_CALRD ( BIT(8) ) +#define BIT_ADC1_CALEN ( BIT(7) ) +#define BITS_ADC1_CALADDR(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_ADC1_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR00 */ +#define BITS_ADC1_RSV_1(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC1_RSV_0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR01 */ +#define BIT_ADC1_DIG_CLK_SEL_0 ( BIT(30) ) +#define BIT_ADC1_VCM_SEL_0 ( BIT(29) ) +#define BITS_ADC1_DELAY_CAP_0(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC1_BIT_SEL_0(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC1_VREF_SEL_0(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC1_VREF_BOOST_0(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC1_QUANT_BOOST_0(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC1_DLLRD_0 ( BIT(18) ) +#define BIT_ADC1_DLLWR_0 ( BIT(17) ) +#define BIT_ADC1_DLLEN_0 ( BIT(16) ) +#define BIT_ADC1_CSBC ( BIT(15) ) +#define BIT_ADC1_IQSWAP ( BIT(14) ) +#define BITS_ADC1_DLLOOF_0(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_ADC1_OSBC ( BIT(7) ) +#define BIT_ADC1_ISBC ( BIT(6) ) +#define BITS_ADC1_DLLIN_0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR02 */ +#define BIT_ADC1_DIG_CLK_SEL_1 ( BIT(30) ) +#define BIT_ADC1_VCM_SEL_1 ( BIT(29) ) +#define BITS_ADC1_DELAY_CAP_1(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC1_BIT_SEL_1(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC1_VREF_SEL_1(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC1_VREF_BOOST_1(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC1_QUANT_BOOST_1(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC1_DLLRD_1 ( BIT(18) ) +#define BIT_ADC1_DLLWR_1 ( BIT(17) ) +#define BIT_ADC1_DLLEN_1 ( BIT(16) ) +#define BITS_ADC1_DLLOOF_1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC1_DLLIN_1(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR10 */ +#define BITS_ADC1_RSV_3(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC1_RSV_2(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR11 */ +#define BIT_ADC1_DIG_CLK_SEL_2 ( BIT(30) ) +#define BIT_ADC1_VCM_SEL_2 ( BIT(29) ) +#define BITS_ADC1_DELAY_CAP_2(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC1_BIT_SEL_2(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC1_VREF_SEL_2(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC1_VREF_BOOST_2(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC1_QUANT_BOOST_2(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC1_DLLRD_2 ( BIT(18) ) +#define BIT_ADC1_DLLWR_2 ( BIT(17) ) +#define BIT_ADC1_DLLEN_2 ( BIT(16) ) +#define BITS_ADC1_DLLOOF_2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC1_DLLIN_2(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR12 */ +#define BIT_ADC1_DIG_CLK_SEL_3 ( BIT(30) ) +#define BIT_ADC1_VCM_SEL_3 ( BIT(29) ) +#define BITS_ADC1_DELAY_CAP_3(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC1_BIT_SEL_3(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC1_VREF_SEL_3(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC1_VREF_BOOST_3(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC1_QUANT_BOOST_3(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC1_DLLRD_3 ( BIT(18) ) +#define BIT_ADC1_DLLWR_3 ( BIT(17) ) +#define BIT_ADC1_DLLEN_3 ( BIT(16) ) +#define BITS_ADC1_DLLOOF_3(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC1_DLLIN_3(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR20 */ +#define BITS_ADC1_RSV_5(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC1_RSV_4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR21 */ +#define BIT_ADC1_DIG_CLK_SEL_4 ( BIT(30) ) +#define BIT_ADC1_VCM_SEL_4 ( BIT(29) ) +#define BITS_ADC1_DELAY_CAP_4(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC1_BIT_SEL_4(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC1_VREF_SEL_4(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC1_VREF_BOOST_4(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC1_QUANT_BOOST_4(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC1_DLLRD_4 ( BIT(18) ) +#define BIT_ADC1_DLLWR_4 ( BIT(17) ) +#define BIT_ADC1_DLLEN_4 ( BIT(16) ) +#define BITS_ADC1_DLLOOF_4(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC1_DLLIN_4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR22 */ +#define BIT_ADC1_DIG_CLK_SEL_5 ( BIT(30) ) +#define BIT_ADC1_VCM_SEL_5 ( BIT(29) ) +#define BITS_ADC1_DELAY_CAP_5(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC1_BIT_SEL_5(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC1_VREF_SEL_5(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC1_VREF_BOOST_5(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC1_QUANT_BOOST_5(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC1_DLLRD_5 ( BIT(18) ) +#define BIT_ADC1_DLLWR_5 ( BIT(17) ) +#define BIT_ADC1_DLLEN_5 ( BIT(16) ) +#define BITS_ADC1_DLLOOF_5(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC1_DLLIN_5(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_CTR1 */ +#define BITS_DAC2_WD_OVR(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DAC2_WADDR_OVR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DAC2_WLE_OVR ( BIT(2) ) +#define BIT_DAC2_W_OVR_I_QN ( BIT(1) ) +#define BIT_DAC2_W_OVR_EN ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_CTR2 */ +#define BIT_DAC2_AUTO_RST ( BIT(23) ) +#define BIT_DAC2_SOFT_RST ( BIT(22) ) +#define BIT_DAC2_OSBC ( BIT(21) ) +#define BIT_DAC2_ISBC ( BIT(20) ) +#define BIT_DAC2_OVR_EN_CAL ( BIT(19) ) +#define BIT_DAC2_EN_OOSCAL ( BIT(18) ) +#define BIT_DAC2_IQSWAP ( BIT(17) ) +#define BIT_DAC2_CAL_START ( BIT(16) ) +#define BITS_DAC2_OFFSETI(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DAC2_OFFSETQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_CTR3 */ +#define BITS_DAC2_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DAC2_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_CTR4 */ +#define BITS_DAC2_I_CAL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DAC2_Q_CAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_STS0 */ +#define BITS_DAC2_WTI(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DAC2_WTQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_STS1 */ +#define BITS_DAC2_DA_STATE(_X_) ( (_X_) << 17 & (BIT(17)|BIT(18)) ) +#define BIT_DAC2_DONE ( BIT(16) ) +#define BITS_DAC2_WQ_OVR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL2_CTR0 */ +#define BITS_ADC2_CLK_CAL_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_ADA2_CAL_WAIT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_CLK_ADA2_CAL_EN ( BIT(6) ) +#define BIT_DAC2_PD_CAL ( BIT(5) ) +#define BIT_ADC2_EN_CAL ( BIT(3) ) +#define BIT_ADC2_CAL ( BIT(1) ) +#define BIT_ADA2_MODE_SEL ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL2_CTR1 */ +#define BITS_ADC2_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) ) +#define BITS_ADC2_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL2_CTR3 */ +#define BIT_ADA2_CAL_START ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL2_STS0 */ +#define BIT_ADA2_CAL_DONE ( BIT(31) ) +#define BITS_ADC2_CAL_I_SUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL2_STS1 */ +#define BITS_ADC2_CAL_Q_SUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_CTR00 */ +#define BIT_DAC2_OUT_SEL_2 ( BIT(26) ) +#define BITS_DAC2_RSV_2(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC2_PCTRL_2(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)) ) +#define BIT_DAC2_CLK_SEL_2 ( BIT(18) ) +#define BIT_DAC2_OUT_SEL_1 ( BIT(17) ) +#define BITS_DAC2_RSV_1(_X_) ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)) ) +#define BITS_DAC2_PCTRL_1(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DAC2_CLK_SEL_1 ( BIT(9) ) +#define BIT_DAC2_OUT_SEL_0 ( BIT(8) ) +#define BITS_DAC2_RSV_0(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DAC2_PCTRL_0(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)) ) +#define BIT_DAC2_CLK_SEL_0 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_CTR10 */ +#define BIT_DAC2_OUT_SEL_5 ( BIT(26) ) +#define BITS_DAC2_RSV_5(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC2_PCTRL_5(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)) ) +#define BIT_DAC2_CLK_SEL_5 ( BIT(18) ) +#define BIT_DAC2_OUT_SEL_4 ( BIT(17) ) +#define BITS_DAC2_RSV_4(_X_) ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)) ) +#define BITS_DAC2_PCTRL_4(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DAC2_CLK_SEL_4 ( BIT(9) ) +#define BIT_DAC2_OUT_SEL_3 ( BIT(8) ) +#define BITS_DAC2_RSV_3(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DAC2_PCTRL_3(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)) ) +#define BIT_DAC2_CLK_SEL_3 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR0 */ +#define BIT_ADC2_SOFT_RST ( BIT(31) ) +#define BITS_ADC2_DLL_OUT(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_ADC2_CALRDOUT(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) ) +#define BIT_ADC2_DLL_SOFT_RST ( BIT(10) ) +#define BIT_ADC2_CAL_SOFT_RST ( BIT(9) ) +#define BIT_ADC2_CALRD ( BIT(8) ) +#define BIT_ADC2_CALEN ( BIT(7) ) +#define BITS_ADC2_CALADDR(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_ADC2_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR00 */ +#define BITS_ADC2_RSV_1(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC2_RSV_0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR01 */ +#define BIT_ADC2_DIG_CLK_SEL_0 ( BIT(30) ) +#define BIT_ADC2_VCM_SEL_0 ( BIT(29) ) +#define BITS_ADC2_DELAY_CAP_0(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC2_BIT_SEL_0(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC2_VREF_SEL_0(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC2_VREF_BOOST_0(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC2_QUANT_BOOST_0(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC2_DLLRD_0 ( BIT(18) ) +#define BIT_ADC2_DLLWR_0 ( BIT(17) ) +#define BIT_ADC2_DLLEN_0 ( BIT(16) ) +#define BIT_ADC2_CSBC ( BIT(15) ) +#define BIT_ADC2_IQSWAP ( BIT(14) ) +#define BITS_ADC2_DLLOOF_0(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_ADC2_OSBC ( BIT(7) ) +#define BIT_ADC2_ISBC ( BIT(6) ) +#define BITS_ADC2_DLLIN_0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR02 */ +#define BIT_ADC2_DIG_CLK_SEL_1 ( BIT(30) ) +#define BIT_ADC2_VCM_SEL_1 ( BIT(29) ) +#define BITS_ADC2_DELAY_CAP_1(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC2_BIT_SEL_1(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC2_VREF_SEL_1(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC2_VREF_BOOST_1(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC2_QUANT_BOOST_1(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC2_DLLRD_1 ( BIT(18) ) +#define BIT_ADC2_DLLWR_1 ( BIT(17) ) +#define BIT_ADC2_DLLEN_1 ( BIT(16) ) +#define BITS_ADC2_DLLOOF_1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC2_DLLIN_1(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR10 */ +#define BITS_ADC2_RSV_3(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC2_RSV_2(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR11 */ +#define BIT_ADC2_DIG_CLK_SEL_2 ( BIT(30) ) +#define BIT_ADC2_VCM_SEL_2 ( BIT(29) ) +#define BITS_ADC2_DELAY_CAP_2(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC2_BIT_SEL_2(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC2_VREF_SEL_2(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC2_VREF_BOOST_2(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC2_QUANT_BOOST_2(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC2_DLLRD_2 ( BIT(18) ) +#define BIT_ADC2_DLLWR_2 ( BIT(17) ) +#define BIT_ADC2_DLLEN_2 ( BIT(16) ) +#define BITS_ADC2_DLLOOF_2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC2_DLLIN_2(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR12 */ +#define BIT_ADC2_DIG_CLK_SEL_3 ( BIT(30) ) +#define BIT_ADC2_VCM_SEL_3 ( BIT(29) ) +#define BITS_ADC2_DELAY_CAP_3(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC2_BIT_SEL_3(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC2_VREF_SEL_3(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC2_VREF_BOOST_3(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC2_QUANT_BOOST_3(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC2_DLLRD_3 ( BIT(18) ) +#define BIT_ADC2_DLLWR_3 ( BIT(17) ) +#define BIT_ADC2_DLLEN_3 ( BIT(16) ) +#define BITS_ADC2_DLLOOF_3(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC2_DLLIN_3(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR20 */ +#define BITS_ADC2_RSV_5(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC2_RSV_4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR21 */ +#define BIT_ADC2_DIG_CLK_SEL_4 ( BIT(30) ) +#define BIT_ADC2_VCM_SEL_4 ( BIT(29) ) +#define BITS_ADC2_DELAY_CAP_4(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC2_BIT_SEL_4(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC2_VREF_SEL_4(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC2_VREF_BOOST_4(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC2_QUANT_BOOST_4(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC2_DLLRD_4 ( BIT(18) ) +#define BIT_ADC2_DLLWR_4 ( BIT(17) ) +#define BIT_ADC2_DLLEN_4 ( BIT(16) ) +#define BITS_ADC2_DLLOOF_4(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC2_DLLIN_4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR22 */ +#define BIT_ADC2_DIG_CLK_SEL_5 ( BIT(30) ) +#define BIT_ADC2_VCM_SEL_5 ( BIT(29) ) +#define BITS_ADC2_DELAY_CAP_5(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC2_BIT_SEL_5(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC2_VREF_SEL_5(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC2_VREF_BOOST_5(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC2_QUANT_BOOST_5(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC2_DLLRD_5 ( BIT(18) ) +#define BIT_ADC2_DLLWR_5 ( BIT(17) ) +#define BIT_ADC2_DLLEN_5 ( BIT(16) ) +#define BITS_ADC2_DLLOOF_5(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC2_DLLIN_5(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_CTR1 */ +#define BITS_DAC3_WD_OVR(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DAC3_WADDR_OVR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DAC3_WLE_OVR ( BIT(2) ) +#define BIT_DAC3_W_OVR_I_QN ( BIT(1) ) +#define BIT_DAC3_W_OVR_EN ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_CTR2 */ +#define BIT_DAC3_AUTO_RST ( BIT(23) ) +#define BIT_DAC3_SOFT_RST ( BIT(22) ) +#define BIT_DAC3_OSBC ( BIT(21) ) +#define BIT_DAC3_ISBC ( BIT(20) ) +#define BIT_DAC3_OVR_EN_CAL ( BIT(19) ) +#define BIT_DAC3_EN_OOSCAL ( BIT(18) ) +#define BIT_DAC3_IQSWAP ( BIT(17) ) +#define BIT_DAC3_CAL_START ( BIT(16) ) +#define BITS_DAC3_OFFSETI(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DAC3_OFFSETQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_CTR3 */ +#define BITS_DAC3_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DAC3_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_CTR4 */ +#define BITS_DAC3_I_CAL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DAC3_Q_CAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_STS0 */ +#define BITS_DAC3_WTI(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DAC3_WTQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_STS1 */ +#define BITS_DAC3_DA_STATE(_X_) ( (_X_) << 17 & (BIT(17)|BIT(18)) ) +#define BIT_DAC3_DONE ( BIT(16) ) +#define BITS_DAC3_WQ_OVR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL3_CTR0 */ +#define BITS_ADC3_CLK_CAL_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_ADA3_CAL_WAIT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_CLK_ADA3_CAL_EN ( BIT(6) ) +#define BIT_DAC3_PD_CAL ( BIT(5) ) +#define BIT_ADC3_EN_CAL ( BIT(3) ) +#define BIT_ADC3_CAL ( BIT(1) ) +#define BIT_ADA3_MODE_SEL ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL3_CTR1 */ +#define BITS_ADC3_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) ) +#define BITS_ADC3_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL3_CTR3 */ +#define BIT_ADA3_CAL_START ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL3_STS0 */ +#define BIT_ADA3_CAL_DONE ( BIT(31) ) +#define BITS_ADC3_CAL_I_SUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL3_STS1 */ +#define BITS_ADC3_CAL_Q_SUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_CTR00 */ +#define BIT_DAC3_OUT_SEL_2 ( BIT(26) ) +#define BITS_DAC3_RSV_2(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC3_PCTRL_2(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)) ) +#define BIT_DAC3_CLK_SEL_2 ( BIT(18) ) +#define BIT_DAC3_OUT_SEL_1 ( BIT(17) ) +#define BITS_DAC3_RSV_1(_X_) ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)) ) +#define BITS_DAC3_PCTRL_1(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DAC3_CLK_SEL_1 ( BIT(9) ) +#define BIT_DAC3_OUT_SEL_0 ( BIT(8) ) +#define BITS_DAC3_RSV_0(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DAC3_PCTRL_0(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)) ) +#define BIT_DAC3_CLK_SEL_0 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_CTR10 */ +#define BIT_DAC3_OUT_SEL_5 ( BIT(26) ) +#define BITS_DAC3_RSV_5(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC3_PCTRL_5(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)) ) +#define BIT_DAC3_CLK_SEL_5 ( BIT(18) ) +#define BIT_DAC3_OUT_SEL_4 ( BIT(17) ) +#define BITS_DAC3_RSV_4(_X_) ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)) ) +#define BITS_DAC3_PCTRL_4(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DAC3_CLK_SEL_4 ( BIT(9) ) +#define BIT_DAC3_OUT_SEL_3 ( BIT(8) ) +#define BITS_DAC3_RSV_3(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DAC3_PCTRL_3(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)) ) +#define BIT_DAC3_CLK_SEL_3 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR0 */ +#define BIT_ADC3_SOFT_RST ( BIT(31) ) +#define BITS_ADC3_DLL_OUT(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_ADC3_CALRDOUT(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) ) +#define BIT_ADC3_DLL_SOFT_RST ( BIT(10) ) +#define BIT_ADC3_CAL_SOFT_RST ( BIT(9) ) +#define BIT_ADC3_CALRD ( BIT(8) ) +#define BIT_ADC3_CALEN ( BIT(7) ) +#define BITS_ADC3_CALADDR(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_ADC3_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR00 */ +#define BITS_ADC3_RSV_1(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC3_RSV_0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR01 */ +#define BIT_ADC3_DIG_CLK_SEL_0 ( BIT(30) ) +#define BIT_ADC3_VCM_SEL_0 ( BIT(29) ) +#define BITS_ADC3_DELAY_CAP_0(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC3_BIT_SEL_0(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC3_VREF_SEL_0(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC3_VREF_BOOST_0(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC3_QUANT_BOOST_0(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC3_DLLRD_0 ( BIT(18) ) +#define BIT_ADC3_DLLWR_0 ( BIT(17) ) +#define BIT_ADC3_DLLEN_0 ( BIT(16) ) +#define BIT_ADC3_CSBC ( BIT(15) ) +#define BIT_ADC3_IQSWAP ( BIT(14) ) +#define BITS_ADC3_DLLOOF_0(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_ADC3_OSBC ( BIT(7) ) +#define BIT_ADC3_ISBC ( BIT(6) ) +#define BITS_ADC3_DLLIN_0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR02 */ +#define BIT_ADC3_DIG_CLK_SEL_1 ( BIT(30) ) +#define BIT_ADC3_VCM_SEL_1 ( BIT(29) ) +#define BITS_ADC3_DELAY_CAP_1(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC3_BIT_SEL_1(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC3_VREF_SEL_1(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC3_VREF_BOOST_1(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC3_QUANT_BOOST_1(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC3_DLLRD_1 ( BIT(18) ) +#define BIT_ADC3_DLLWR_1 ( BIT(17) ) +#define BIT_ADC3_DLLEN_1 ( BIT(16) ) +#define BITS_ADC3_DLLOOF_1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC3_DLLIN_1(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR10 */ +#define BITS_ADC3_RSV_3(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC3_RSV_2(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR11 */ +#define BIT_ADC3_DIG_CLK_SEL_2 ( BIT(30) ) +#define BIT_ADC3_VCM_SEL_2 ( BIT(29) ) +#define BITS_ADC3_DELAY_CAP_2(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC3_BIT_SEL_2(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC3_VREF_SEL_2(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC3_VREF_BOOST_2(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC3_QUANT_BOOST_2(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC3_DLLRD_2 ( BIT(18) ) +#define BIT_ADC3_DLLWR_2 ( BIT(17) ) +#define BIT_ADC3_DLLEN_2 ( BIT(16) ) +#define BITS_ADC3_DLLOOF_2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC3_DLLIN_2(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR12 */ +#define BIT_ADC3_DIG_CLK_SEL_3 ( BIT(30) ) +#define BIT_ADC3_VCM_SEL_3 ( BIT(29) ) +#define BITS_ADC3_DELAY_CAP_3(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC3_BIT_SEL_3(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC3_VREF_SEL_3(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC3_VREF_BOOST_3(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC3_QUANT_BOOST_3(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC3_DLLRD_3 ( BIT(18) ) +#define BIT_ADC3_DLLWR_3 ( BIT(17) ) +#define BIT_ADC3_DLLEN_3 ( BIT(16) ) +#define BITS_ADC3_DLLOOF_3(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC3_DLLIN_3(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR20 */ +#define BITS_ADC3_RSV_5(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC3_RSV_4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR21 */ +#define BIT_ADC3_DIG_CLK_SEL_4 ( BIT(30) ) +#define BIT_ADC3_VCM_SEL_4 ( BIT(29) ) +#define BITS_ADC3_DELAY_CAP_4(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC3_BIT_SEL_4(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC3_VREF_SEL_4(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC3_VREF_BOOST_4(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC3_QUANT_BOOST_4(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC3_DLLRD_4 ( BIT(18) ) +#define BIT_ADC3_DLLWR_4 ( BIT(17) ) +#define BIT_ADC3_DLLEN_4 ( BIT(16) ) +#define BITS_ADC3_DLLOOF_4(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC3_DLLIN_4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR22 */ +#define BIT_ADC3_DIG_CLK_SEL_5 ( BIT(30) ) +#define BIT_ADC3_VCM_SEL_5 ( BIT(29) ) +#define BITS_ADC3_DELAY_CAP_5(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC3_BIT_SEL_5(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC3_VREF_SEL_5(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC3_VREF_BOOST_5(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC3_QUANT_BOOST_5(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC3_DLLRD_5 ( BIT(18) ) +#define BIT_ADC3_DLLWR_5 ( BIT(17) ) +#define BIT_ADC3_DLLEN_5 ( BIT(16) ) +#define BITS_ADC3_DLLOOF_5(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC3_DLLIN_5(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_AFCDAC1_CFG */ +#define BITS_AFCDAC1_CHANNEL_MASK(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_AFCDAC1_CHANNEL_SSET(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BIT_AFCDAC1_LOW_V_CON_SST ( BIT(23) ) +#define BIT_AFCDAC1_BP_RES_SST ( BIT(20) ) +#define BITS_AFCDAC1_G_SST(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_AFCDAC1_CTL_SST(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BIT_AFCDAC1_PD_SST ( BIT(15) ) +#define BITS_AFCDAC1_D_SST(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_AFCDAC2_CFG */ +#define BITS_AFCDAC2_CHANNEL_MASK(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_AFCDAC2_CHANNEL_SSET(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BIT_AFCDAC2_LOW_V_CON_SST ( BIT(23) ) +#define BIT_AFCDAC2_BP_RES_SST ( BIT(20) ) +#define BITS_AFCDAC2_G_SST(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_AFCDAC2_CTL_SST(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BIT_AFCDAC2_PD_SST ( BIT(15) ) +#define BITS_AFCDAC2_D_SST(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_APCDAC1_CFG */ +#define BITS_APCDAC1_CHANNEL_MASK(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_APCDAC1_CHANNEL_SSET(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BIT_APCDAC1_LOW_V_CON_SST ( BIT(23) ) +#define BITS_APCDAC1_OUTSEL_SST(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BIT_APCDAC1_BP_RES_SST ( BIT(20) ) +#define BITS_APCDAC1_G_SST(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_APCDAC1_CTL_SST(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BIT_APCDAC1_PD_SST ( BIT(15) ) +#define BIT_APCDAC1_SEL_SST ( BIT(14) ) +#define BITS_APCDAC1_D_SST(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_APCDAC2_CFG */ +#define BITS_APCDAC2_CHANNEL_MASK(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_APCDAC2_CHANNEL_SSET(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BIT_APCDAC2_LOW_V_CON_SST ( BIT(23) ) +#define BITS_APCDAC2_OUTSEL_SST(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BIT_APCDAC2_BP_RES_SST ( BIT(20) ) +#define BITS_APCDAC2_G_SST(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_APCDAC2_CTL_SST(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BIT_APCDAC2_PD_SST ( BIT(15) ) +#define BIT_APCDAC2_SEL_SST ( BIT(14) ) +#define BITS_APCDAC2_D_SST(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFSPI_CFG */ +#define BITS_RFSBI2_CHANNEL_MASK(_X_) ( (_X_) << 29 & (BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_RFSBI2_CHANNEL_SSET(_X_) ( (_X_) << 26 & (BIT(26)|BIT(27)|BIT(28)) ) +#define BIT_RFSBI2_IDATA_SST ( BIT(25) ) +#define BIT_RFSBI2_ODATA_SST ( BIT(24) ) +#define BIT_RFSBI2_DATA_OE_SST ( BIT(23) ) +#define BIT_RFSBI2_DATA_IE_SST ( BIT(22) ) +#define BIT_RFSBI2_CLK_SST ( BIT(21) ) +#define BIT_RFSBI2_CLK_OE_SST ( BIT(20) ) +#define BIT_RFSBI2_EN0_SST ( BIT(19) ) +#define BIT_RFSBI2_EN0_OE_SST ( BIT(18) ) +#define BIT_RFSBI2_EN1_SST ( BIT(17) ) +#define BIT_RFSBI2_EN1_OE_SST ( BIT(16) ) +#define BITS_RFSBI1_CHANNEL_MASK(_X_) ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_RFSBI1_CHANNEL_SSET(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_RFSBI1_IDATA_SST ( BIT(9) ) +#define BIT_RFSBI1_ODATA_SST ( BIT(8) ) +#define BIT_RFSBI1_DATA_OE_SST ( BIT(7) ) +#define BIT_RFSBI1_DATA_IE_SST ( BIT(6) ) +#define BIT_RFSBI1_CLK_SST ( BIT(5) ) +#define BIT_RFSBI1_CLK_OE_SST ( BIT(4) ) +#define BIT_RFSBI1_EN0_SST ( BIT(3) ) +#define BIT_RFSBI1_EN0_OE_SST ( BIT(2) ) +#define BIT_RFSBI1_EN1_SST ( BIT(1) ) +#define BIT_RFSBI1_EN1_OE_SST ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFMIPI_CFG */ +#define BITS_RFMIPI2_CHANNEL_MASK(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_RFMIPI2_CHANNEL_SSET(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BIT_PAD_OUT_RFFE2_CLK_SST ( BIT(20) ) +#define BIT_PAD_OUT_RFFE2_DATA_SST ( BIT(19) ) +#define BIT_PAD_IN_RFFE2_DATA_SST ( BIT(18) ) +#define BIT_PAD_OE_RFFE2_DATA_SST ( BIT(17) ) +#define BIT_PAD_IE_RFFE2_DATA_SST ( BIT(16) ) +#define BITS_RFMIPI1_CHANNEL_MASK(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_RFMIPI1_CHANNEL_SSET(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BIT_PAD_OUT_RFFE1_CLK_SST ( BIT(4) ) +#define BIT_PAD_OUT_RFFE1_DATA_SST ( BIT(3) ) +#define BIT_PAD_IN_RFFE1_DATA_SST ( BIT(2) ) +#define BIT_PAD_OE_RFFE1_DATA_SST ( BIT(1) ) +#define BIT_PAD_IE_RFFE1_DATA_SST ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_APCDAC_OUTSEL */ +#define BIT_AFCDAC_LOW_V_CON_GGE ( BIT(31) ) +#define BIT_AFCDAC_LOW_V_CON_WG ( BIT(30) ) +#define BIT_AFCDAC_LOW_V_CON_WD ( BIT(29) ) +#define BIT_AFCDAC_LOW_V_CON_TG ( BIT(28) ) +#define BIT_AFCDAC_LOW_V_CON_TD ( BIT(27) ) +#define BIT_AFCDAC_LOW_V_CON_LTE ( BIT(26) ) +#define BITS_APCDACX_G3_SST(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_APCDACX_G2_SST(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)) ) +#define BITS_APCDACX_G1_SST(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)) ) +#define BITS_APCDACX_G0_SST(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BIT_APCDAC_LOW_V_CON_GGE ( BIT(17) ) +#define BIT_APCDAC_LOW_V_CON_WG ( BIT(16) ) +#define BIT_APCDAC_LOW_V_CON_WD ( BIT(15) ) +#define BIT_APCDAC_LOW_V_CON_TG ( BIT(14) ) +#define BIT_APCDAC_LOW_V_CON_TD ( BIT(13) ) +#define BIT_APCDAC_LOW_V_CON_LTE ( BIT(12) ) +#define BITS_APCDAC_OUTSEL_GGE(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_APCDAC_OUTSEL_WG(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_APCDAC_OUTSEL_WD(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_APCDAC_OUTSEL_TG(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_APCDAC_OUTSEL_TD(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_APCDAC_OUTSEL_LTE(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CLASH_CHK */ +#define BIT_RFSBI2_CLASH_CHK_INTRP_EN ( BIT(29) ) +#define BIT_RFSBI1_CLASH_CHK_INTRP_EN ( BIT(28) ) +#define BIT_RFMIPI2_CLASH_CHK_INTRP_EN ( BIT(27) ) +#define BIT_RFMIPI1_CLASH_CHK_INTRP_EN ( BIT(26) ) +#define BIT_APCDAC2_CLASH_CHK_INTRP_EN ( BIT(25) ) +#define BIT_APCDAC1_CLASH_CHK_INTRP_EN ( BIT(24) ) +#define BIT_AFCDAC2_CLASH_CHK_INTRP_EN ( BIT(23) ) +#define BIT_AFCDAC1_CLASH_CHK_INTRP_EN ( BIT(22) ) +#define BIT_ADA3_TX_CLASH_CHK_INTRP_EN ( BIT(21) ) +#define BIT_ADA3_RX_CLASH_CHK_INTRP_EN ( BIT(20) ) +#define BIT_ADA2_TX_CLASH_CHK_INTRP_EN ( BIT(19) ) +#define BIT_ADA2_RX_CLASH_CHK_INTRP_EN ( BIT(18) ) +#define BIT_ADA1_TX_CLASH_CHK_INTRP_EN ( BIT(17) ) +#define BIT_ADA1_RX_CLASH_CHK_INTRP_EN ( BIT(16) ) +#define BIT_CHK_CLASH_STFREE ( BIT(8) ) +#define BIT_CHK_CLASH_CLR ( BIT(7) ) +#define BIT_CHK_CLASH_RTC_SNAP_MODE ( BIT(4) ) +#define BIT_CHK_CLASH_RTC_SNAP_EDGE ( BIT(3) ) +#define BIT_CHK_CLASH_RTC_SNAP_INTRP_TYPE ( BIT(2) ) +#define BIT_CHK_CLASH_RTC_SNAP_INTRP_CLR ( BIT(1) ) +#define BIT_CHK_CLASH_RTC_SNAP_INTRP ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CLASH_SNAP */ +#define BITS_CHK_CLASH_RTC_SNAP_TIME(_X_) (_X_) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CLASH_STATUS1 */ +#define BITS_CHK_CLASH_ADA3_TX_CHANNEL_SEL(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_CHK_CLASH_ADA3_RX_CHANNEL_SEL(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) ) +#define BITS_CHK_CLASH_ADA2_TX_CHANNEL_SEL(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_CHK_CLASH_ADA2_RX_CHANNEL_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_CHK_CLASH_ADA1_TX_CHANNEL_SEL(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_CHK_CLASH_ADA1_RX_CHANNEL_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CLASH_STATUS2 */ +#define BITS_CHK_CLASH_APCDAC2_CHANNEL_SEL(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_CHK_CLASH_APCDAC1_CHANNEL_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CHK_CLASH_AFCDAC2_CHANNEL_SEL(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_CHK_CLASH_AFCDAC1_CHANNEL_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CLASH_STATUS3 */ +#define BITS_CHK_CLASH_RFSBI2_CHANNEL_SEL(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_CHK_CLASH_RFSBI1_CHANNEL_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CHK_CLASH_RFMIPI2_CHANNEL_SEL(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_CHK_CLASH_RFMIPI1_CHANNEL_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_EXTRA_CFG0 */ +#define BITS_APT_DCM2_EXTRA_CFG(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_APT_DCM2_ADI_EN ( BIT(23) ) +#define BITS_APT_DCM2_CHANNEL_SSET(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BIT_APT_DCM2_SST ( BIT(19) ) +#define BITS_APT_DCM2_CHANNEL_MASK(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)) ) +#define BITS_APT_DCM1_EXTRA_CFG(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_APT_DCM1_ADI_EN ( BIT(7) ) +#define BITS_APT_DCM1_CHANNEL_SSET(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_APT_DCM1_SST ( BIT(3) ) +#define BITS_APT_DCM1_CHANNEL_MASK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_EXTRA_CFG1 */ +#define BITS_MDAR_EXTRA_CFG1(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_MDAR_EXTRA_CFG1_2 ( BIT(12) ) +#define BIT_MDAR_EXTRA_CFG1_1 ( BIT(11) ) +#define BIT_MDAR_EXTRA_CFG1_0 ( BIT(10) ) +#define BITS_MDAR_BB_LDO_REFCTRL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_MDAR_BB_LDO_SLEEP_PD_EN ( BIT(6) ) +#define BIT_MDAR_BB_LDO_FORCE_ON ( BIT(5) ) +#define BIT_MDAR_BB_LDO_FORCE_PD ( BIT(4) ) +#define BIT_MDAR_BB_BG_SLEEP_PD_EN ( BIT(2) ) +#define BIT_MDAR_BB_BG_FORCE_ON ( BIT(1) ) +#define BIT_MDAR_BB_BG_FORCE_PD ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF0 */ +#define BITS_CHK_CLASH_RFCTRL15_CHX_SEL(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BIT_RFCTRL15_CHK_INTRP_EN ( BIT(16) ) +#define BIT_RFCTRL15_RTC_REFRESH ( BIT(12) ) +#define BIT_RFCTRL15_SNAP_REFRESH ( BIT(8) ) +#define BITS_RFCTRL15_SSET(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BITS_RFCTRL15_MASK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF1 */ +#define BITS_RFCTRL15_CH0_SNAP1_RTC_TIME(_X_) (_X_) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF2 */ +#define BITS_RFCTRL15_CH0_SNAP0_RTC_TIME(_X_) (_X_) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF3 */ +#define BITS_RFCTRL15_CH1_SNAP1_RTC_TIME(_X_) (_X_) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF4 */ +#define BITS_RFCTRL15_CH1_SNAP0_RTC_TIME(_X_) (_X_) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF5 */ +#define BITS_RFCTRL15_CH2_SNAP1_RTC_TIME(_X_) (_X_) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF6 */ +#define BITS_RFCTRL15_CH2_SNAP0_RTC_TIME(_X_) (_X_) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG4 */ +#define BITS_RFCTRL_CHANNEL_MASK3(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_RFCTRL_CHANNEL_MASK2(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BITS_RFCTRL_CHANNEL_MASK1(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RFCTRL_CHANNEL_MASK0(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_RFCTRL150_SST(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG5 */ +#define BITS_RFCTRL_CHANNEL_MASK13(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_RFCTRL_CHANNEL_MASK12(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BITS_RFCTRL_CHANNEL_MASK11(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RFCTRL_CHANNEL_MASK10(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_RFCTRL_CHANNEL_MASK9(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) ) +#define BITS_RFCTRL_CHANNEL_MASK8(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_RFCTRL_CHANNEL_MASK7(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_RFCTRL_CHANNEL_MASK6(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_RFCTRL_CHANNEL_MASK5(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_RFCTRL_CHANNEL_MASK4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG6 */ +#define BITS_RFCTRL_CHANNEL_SSET7(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_RFCTRL_CHANNEL_SSET6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BITS_RFCTRL_CHANNEL_SSET5(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RFCTRL_CHANNEL_SSET4(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_RFCTRL_CHANNEL_SSET3(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) ) +#define BITS_RFCTRL_CHANNEL_SSET2(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_RFCTRL_CHANNEL_SSET1(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_RFCTRL_CHANNEL_SSET0(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_RFCTRL_CHANNEL_MASK15(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_RFCTRL_CHANNEL_MASK14(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG7 */ +#define BITS_RFCTRL_CHANNEL_SSET15(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RFCTRL_CHANNEL_SSET14(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_RFCTRL_CHANNEL_SSET13(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) ) +#define BITS_RFCTRL_CHANNEL_SSET12(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_RFCTRL_CHANNEL_SSET11(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_RFCTRL_CHANNEL_SSET10(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_RFCTRL_CHANNEL_SSET9(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_RFCTRL_CHANNEL_SSET8(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG8 */ +#define BITS_RFCTRL_CHANNEL_MASK19(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_RFCTRL_CHANNEL_MASK18(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BITS_RFCTRL_CHANNEL_MASK17(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RFCTRL_CHANNEL_MASK16(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_RFCTRL3130_SST(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_RFCTRL2916_SST(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG9 */ +#define BITS_RFCTRL_CHANNEL_MASK29(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_RFCTRL_CHANNEL_MASK28(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BITS_RFCTRL_CHANNEL_MASK27(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RFCTRL_CHANNEL_MASK26(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_RFCTRL_CHANNEL_MASK25(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) ) +#define BITS_RFCTRL_CHANNEL_MASK24(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_RFCTRL_CHANNEL_MASK23(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_RFCTRL_CHANNEL_MASK22(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_RFCTRL_CHANNEL_MASK21(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_RFCTRL_CHANNEL_MASK20(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG10 */ +#define BITS_RFCTRL_CHANNEL_SSET23(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_RFCTRL_CHANNEL_SSET22(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BITS_RFCTRL_CHANNEL_SSET21(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RFCTRL_CHANNEL_SSET20(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_RFCTRL_CHANNEL_SSET19(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) ) +#define BITS_RFCTRL_CHANNEL_SSET18(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_RFCTRL_CHANNEL_SSET17(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_RFCTRL_CHANNEL_SSET16(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_RFCTRL_CHANNEL_MASK31(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_RFCTRL_CHANNEL_MASK30(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG11 */ +#define BITS_RFCTRL_CHANNEL_SSET31(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RFCTRL_CHANNEL_SSET30(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_RFCTRL_CHANNEL_SSET29(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) ) +#define BITS_RFCTRL_CHANNEL_SSET28(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_RFCTRL_CHANNEL_SSET27(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_RFCTRL_CHANNEL_SSET26(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_RFCTRL_CHANNEL_SSET25(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_RFCTRL_CHANNEL_SSET24(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG12 */ +#define BITS_RFCTRL_WTGCFGH(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_RFCTRL_WTGCFGL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG13 */ +#define BITS_RFCTRL_GGECFGH(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_RFCTRL_GGECFGL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG14 */ +#define BITS_MDAR_CFG14(_X_) (_X_) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG15 */ +#define BITS_MDAR_ANALOG_BB_RSV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG10 */ +#define BIT_ADC1_IMBP_CLK_SEL_5 ( BIT(21) ) +#define BIT_ADC1_IMBP_CLK_SEL_4 ( BIT(20) ) +#define BIT_ADC1_IMBP_CLK_SEL_3 ( BIT(19) ) +#define BIT_ADC1_IMBP_CLK_SEL_2 ( BIT(18) ) +#define BIT_ADC1_IMBP_CLK_SEL_1 ( BIT(17) ) +#define BIT_ADC1_IMBP_CLK_SEL_0 ( BIT(16) ) +#define BIT_DAC1_IMBP_BYPASS_5 ( BIT(13) ) +#define BIT_DAC1_IMBP_BYPASS_4 ( BIT(12) ) +#define BIT_DAC1_IMBP_BYPASS_3 ( BIT(11) ) +#define BIT_DAC1_IMBP_BYPASS_2 ( BIT(10) ) +#define BIT_DAC1_IMBP_BYPASS_1 ( BIT(9) ) +#define BIT_DAC1_IMBP_BYPASS_0 ( BIT(8) ) +#define BIT_ADC1_IMBP_BYPASS_5 ( BIT(5) ) +#define BIT_ADC1_IMBP_BYPASS_4 ( BIT(4) ) +#define BIT_ADC1_IMBP_BYPASS_3 ( BIT(3) ) +#define BIT_ADC1_IMBP_BYPASS_2 ( BIT(2) ) +#define BIT_ADC1_IMBP_BYPASS_1 ( BIT(1) ) +#define BIT_ADC1_IMBP_BYPASS_0 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG11 */ +#define BITS_ADC1_BAL_B(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_ADC1_BAL_A(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG12 */ +#define BITS_ADC1_BAL_D(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_ADC1_BAL_C(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG13 */ +#define BITS_DAC1_BAL_B(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_DAC1_BAL_A(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG14 */ +#define BITS_DAC1_BAL_D(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_DAC1_BAL_C(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG20 */ +#define BIT_ADC2_IMBP_CLK_SEL_5 ( BIT(21) ) +#define BIT_ADC2_IMBP_CLK_SEL_4 ( BIT(20) ) +#define BIT_ADC2_IMBP_CLK_SEL_3 ( BIT(19) ) +#define BIT_ADC2_IMBP_CLK_SEL_2 ( BIT(18) ) +#define BIT_ADC2_IMBP_CLK_SEL_1 ( BIT(17) ) +#define BIT_ADC2_IMBP_CLK_SEL_0 ( BIT(16) ) +#define BIT_DAC2_IMBP_BYPASS_5 ( BIT(13) ) +#define BIT_DAC2_IMBP_BYPASS_4 ( BIT(12) ) +#define BIT_DAC2_IMBP_BYPASS_3 ( BIT(11) ) +#define BIT_DAC2_IMBP_BYPASS_2 ( BIT(10) ) +#define BIT_DAC2_IMBP_BYPASS_1 ( BIT(9) ) +#define BIT_DAC2_IMBP_BYPASS_0 ( BIT(8) ) +#define BIT_ADC2_IMBP_BYPASS_5 ( BIT(5) ) +#define BIT_ADC2_IMBP_BYPASS_4 ( BIT(4) ) +#define BIT_ADC2_IMBP_BYPASS_3 ( BIT(3) ) +#define BIT_ADC2_IMBP_BYPASS_2 ( BIT(2) ) +#define BIT_ADC2_IMBP_BYPASS_1 ( BIT(1) ) +#define BIT_ADC2_IMBP_BYPASS_0 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG21 */ +#define BITS_ADC2_BAL_B(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_ADC2_BAL_A(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG22 */ +#define BITS_ADC2_BAL_D(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_ADC2_BAL_C(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG23 */ +#define BITS_DAC2_BAL_B(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_DAC2_BAL_A(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG24 */ +#define BITS_DAC2_BAL_D(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_DAC2_BAL_C(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG30 */ +#define BIT_ADC3_IMBP_CLK_SEL_5 ( BIT(21) ) +#define BIT_ADC3_IMBP_CLK_SEL_4 ( BIT(20) ) +#define BIT_ADC3_IMBP_CLK_SEL_3 ( BIT(19) ) +#define BIT_ADC3_IMBP_CLK_SEL_2 ( BIT(18) ) +#define BIT_ADC3_IMBP_CLK_SEL_1 ( BIT(17) ) +#define BIT_ADC3_IMBP_CLK_SEL_0 ( BIT(16) ) +#define BIT_DAC3_IMBP_BYPASS_5 ( BIT(13) ) +#define BIT_DAC3_IMBP_BYPASS_4 ( BIT(12) ) +#define BIT_DAC3_IMBP_BYPASS_3 ( BIT(11) ) +#define BIT_DAC3_IMBP_BYPASS_2 ( BIT(10) ) +#define BIT_DAC3_IMBP_BYPASS_1 ( BIT(9) ) +#define BIT_DAC3_IMBP_BYPASS_0 ( BIT(8) ) +#define BIT_ADC3_IMBP_BYPASS_5 ( BIT(5) ) +#define BIT_ADC3_IMBP_BYPASS_4 ( BIT(4) ) +#define BIT_ADC3_IMBP_BYPASS_3 ( BIT(3) ) +#define BIT_ADC3_IMBP_BYPASS_2 ( BIT(2) ) +#define BIT_ADC3_IMBP_BYPASS_1 ( BIT(1) ) +#define BIT_ADC3_IMBP_BYPASS_0 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG31 */ +#define BITS_ADC3_BAL_B(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_ADC3_BAL_A(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG32 */ +#define BITS_ADC3_BAL_D(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_ADC3_BAL_C(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG33 */ +#define BITS_DAC3_BAL_B(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_DAC3_BAL_A(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG34 */ +#define BITS_DAC3_BAL_D(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_DAC3_BAL_C(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +#endif diff --git a/include/soc/sprd/chip_x35l/__regs_mm_ahb_rf.h b/include/soc/sprd/chip_x35l/__regs_mm_ahb_rf.h new file mode 100755 index 00000000..1fcaa732 --- /dev/null +++ b/include/soc/sprd/chip_x35l/__regs_mm_ahb_rf.h @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_MM_AHB_HEADFILE_H__ +#define __H_REGS_MM_AHB_HEADFILE_H__ __FILE__ + +#define REGS_MM_AHB_RF + +/* registers definitions for MM_AHB_RF */ +#define REG_MM_AHB_AHB_EB SCI_ADDR(REGS_MM_AHB_BASE, 0x0000) +#define REG_MM_AHB_AHB_RST SCI_ADDR(REGS_MM_AHB_BASE, 0x0004) +#define REG_MM_AHB_GEN_CKG_CFG SCI_ADDR(REGS_MM_AHB_BASE, 0x0008) +#define REG_MM_AHB_MIPI_CSI2_CTRL SCI_ADDR(REGS_MM_AHB_BASE, 0x000C) +#define REG_MM_AHB_MM_QOS_CFG SCI_ADDR(REGS_MM_AHB_BASE, 0x0010) + + + +/* bits definitions for register REG_MM_AHB_AHB_EB */ +#define BIT_MMU_EB ( BIT(7) ) +#define BIT_MM_CKG_EB ( BIT(6) ) +#define BIT_JPG_EB ( BIT(5) ) +#define BIT_CSI_EB ( BIT(4) ) +#define BIT_VSP_EB ( BIT(3) ) +#define BIT_ISP_EB ( BIT(2) ) +#define BIT_CCIR_EB ( BIT(1) ) +#define BIT_DCAM_EB ( BIT(0) ) + +/* bits definitions for register REG_MM_AHB_AHB_RST */ +#define BIT_MMU_SOFT_RST ( BIT(14) ) +#define BIT_MM_CKG_SOFT_RST ( BIT(13) ) +#define BIT_MM_MTX_SOFT_RST ( BIT(12) ) +#define BIT_OR1200_SOFT_RST ( BIT(11) ) +#define BIT_ROT_SOFT_RST ( BIT(10) ) +#define BIT_CAM2_SOFT_RST ( BIT(9) ) +#define BIT_CAM1_SOFT_RST ( BIT(8) ) +#define BIT_CAM0_SOFT_RST ( BIT(7) ) +#define BIT_JPG_SOFT_RST ( BIT(6) ) +#define BIT_CSI_SOFT_RST ( BIT(5) ) +#define BIT_VSP_SOFT_RST ( BIT(4) ) +#define BIT_ISP_CFG_SOFT_RST ( BIT(3) ) +#define BIT_ISP_LOG_SOFT_RST ( BIT(2) ) +#define BIT_CCIR_SOFT_RST ( BIT(1) ) +#define BIT_DCAM_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_MM_AHB_GEN_CKG_CFG */ +#define BIT_MM_MTX_AXI_CKG_EN ( BIT(8) ) +#define BIT_MM_AXI_CKG_EN ( BIT(7) ) +#define BIT_JPG_AXI_CKG_EN ( BIT(6) ) +#define BIT_VSP_AXI_CKG_EN ( BIT(5) ) +#define BIT_ISP_AXI_CKG_EN ( BIT(4) ) +#define BIT_DCAM_AXI_CKG_EN ( BIT(3) ) +#define BIT_SENSOR_CKG_EN ( BIT(2) ) +#define BIT_MIPI_CSI_CKG_EN ( BIT(1) ) +#define BIT_CPHY_CFG_CKG_EN ( BIT(0) ) + +/* bits definitions for register REG_MM_AHB_MIPI_CSI2_CTRL */ +#define BITS_MIPI_CPHY_SAMPLE_SEL(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)) ) +#define BIT_MIPI_CPHY_SYNC_MODE ( BIT(2) ) +#define BIT_MIPI_CPHY_TEST_CTL ( BIT(1) ) +#define BIT_MIPI_CPHY_SEL ( BIT(0) ) + +/* bits definitions for register REG_MM_AHB_MM_QOS_CFG */ +#define BITS_QOS_R_DCAM(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_QOS_W_DCAM(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_QOS_R_JPG(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_QOS_W_JPG(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_QOS_R_ISP(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_QOS_W_ISP(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_QOS_R_VSP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_QOS_W_VSP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +#endif diff --git a/include/soc/sprd/chip_x35l/__regs_mm_clk.h b/include/soc/sprd/chip_x35l/__regs_mm_clk.h new file mode 100644 index 00000000..4b73f5ef --- /dev/null +++ b/include/soc/sprd/chip_x35l/__regs_mm_clk.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __REGS_MM_CLK_H__ +#define __REGS_MM_CLK_H__ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, include <mach/sci_glb_regs.h>" +#endif + +#define REGS_MM_CLK + +/* registers definitions for controller REGS_MM_CLK */ +#define REG_MM_CLK_MM_AHB_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0020) +#define REG_MM_CLK_SENSOR_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0024) +#define REG_MM_CLK_CCIR_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0028) +#define REG_MM_CLK_DCAM_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x002c) +#define REG_MM_CLK_VSP_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0030) +#define REG_MM_CLK_ISP_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0034) +#define REG_MM_CLK_JPG_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0038) +#define REG_MM_CLK_MIPI_CSI_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x003c) +#define REG_MM_CLK_CPHY_CFG_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0040) +#define REG_MM_CLK_ORP_TCK_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0044) + +/* vars definitions for controller REGS_MM_CLK */ + +#endif //__REGS_MM_CLK_H__ diff --git a/include/soc/sprd/chip_x35l/__regs_pinmap.h b/include/soc/sprd/chip_x35l/__regs_pinmap.h new file mode 100755 index 00000000..be98c3a0 --- /dev/null +++ b/include/soc/sprd/chip_x35l/__regs_pinmap.h @@ -0,0 +1,283 @@ +#ifndef __ASM_ARM_ARCH_PINMAP_H +#error "Don't include this file directly, Pls include pinmap.h" +#endif + +#ifndef _REGS_PINMAP_H_ +#define _REGS_PINMAP_H_ + +#define CTL_PIN_BASE ( SPRD_PIN_BASE ) + +/* registers definitions for controller CTL_PIN */ +#define REG_PIN_CTRL0 ( 0x0000 ) +#define REG_PIN_CTRL1 ( 0x0004 ) +#define REG_PIN_CTRL2 ( 0x0008 ) +#define REG_PIN_CTRL3 ( 0x000c ) +#define REG_PIN_CTRL4 ( 0x0010 ) +#define REG_PIN_CTRL5 ( 0x0014 ) +#define REG_PIN_SIMCLK0 ( 0x0018 ) +#define REG_PIN_SIMDA0 ( 0x001c ) +#define REG_PIN_SIMRST0 ( 0x0020 ) +#define REG_PIN_SIMCLK1 ( 0x0024 ) +#define REG_PIN_SIMDA1 ( 0x0028 ) +#define REG_PIN_SIMRST1 ( 0x002c ) +#define REG_PIN_SD0_CLK ( 0x0030 ) +#define REG_PIN_SD0_CMD ( 0x0034 ) +#define REG_PIN_SD0_D0 ( 0x0038 ) +#define REG_PIN_SD0_D1 ( 0x003c ) +#define REG_PIN_SD0_D2 ( 0x0040 ) +#define REG_PIN_SD0_D3 ( 0x0044 ) +#define REG_PIN_ANA_INT ( 0x0048 ) +#define REG_PIN_EXT_RST_B ( 0x004c ) +#define REG_PIN_CLK_26M ( 0x0050 ) +#define REG_PIN_CHIP_SLEEP ( 0x0054 ) +#define REG_PIN_XTL_BUF_EN ( 0x0058 ) +#define REG_PIN_CLK_32K ( 0x005c ) +#define REG_PIN_AUD_SCLK ( 0x0060 ) +#define REG_PIN_AUD_ADD0 ( 0x0064 ) +#define REG_PIN_AUD_ADSYNC ( 0x0068 ) +#define REG_PIN_AUD_DAD1 ( 0x006c ) +#define REG_PIN_AUD_DAD0 ( 0x0070 ) +#define REG_PIN_AUD_DASYNC ( 0x0074 ) +#define REG_PIN_TD_TXPD ( 0x0078 ) +#define REG_PIN_TD_RXPD ( 0x007c ) +#define REG_PIN_GSM_TXPD ( 0x0080 ) +#define REG_PIN_GSM_RXPD ( 0x0084 ) +#define REG_PIN_TD_RX_CLK ( 0x0088 ) +#define REG_PIN_ADI_D ( 0x008c ) +#define REG_PIN_ADI_SYNC ( 0x0090 ) +#define REG_PIN_ADI_SCLK ( 0x0094 ) +#define REG_PIN_ANA_INT2 ( 0x0098 ) +#define REG_PIN_COM_TX_APCD ( 0x009c ) +#define REG_PIN_COM_TX_DQ1 ( 0x00a0 ) +#define REG_PIN_COM_TX_DQ0 ( 0x00a4 ) +#define REG_PIN_COM_TX_DI1 ( 0x00a8 ) +#define REG_PIN_COM_TX_DI0 ( 0x00ac ) +#define REG_PIN_COM_TX_SYNC ( 0x00b0 ) +#define REG_PIN_COM_TX_SCLK ( 0x00b4 ) +#define REG_PIN_COM_RX_DQ1 ( 0x00b8 ) +#define REG_PIN_COM_RX_DQ0 ( 0x00bc ) +#define REG_PIN_COM_RX_DI1 ( 0x00c0 ) +#define REG_PIN_COM_RX_DI0 ( 0x00c4 ) +#define REG_PIN_COM_RX_SYNC ( 0x00c8 ) +#define REG_PIN_COM_RX_SCLK ( 0x00cc ) +#define REG_PIN_CCIRCK ( 0x00d0 ) +#define REG_PIN_CCIRMCLK ( 0x00d4 ) +#define REG_PIN_CCIRHS ( 0x00d8 ) +#define REG_PIN_CCIRVS ( 0x00dc ) +#define REG_PIN_CCIRD0 ( 0x00e0 ) +#define REG_PIN_CCIRD1 ( 0x00e4 ) +#define REG_PIN_CCIRD2 ( 0x00e8 ) +#define REG_PIN_CCIRD3 ( 0x00ec ) +#define REG_PIN_CCIRD4 ( 0x00f0 ) +#define REG_PIN_CCIRD5 ( 0x00f4 ) +#define REG_PIN_CCIRD6 ( 0x00f8 ) +#define REG_PIN_CCIRD7 ( 0x00fc ) +#define REG_PIN_CCIRD8 ( 0x0100 ) +#define REG_PIN_CCIRD9 ( 0x0104 ) +#define REG_PIN_CCIRRST ( 0x0108 ) +#define REG_PIN_CCIRPD1 ( 0x010c ) +#define REG_PIN_CCIRPD0 ( 0x0110 ) +#define REG_PIN_SCL1 ( 0x0114 ) +#define REG_PIN_SDA1 ( 0x0118 ) +#define REG_PIN_KEYOUT0 ( 0x011c ) +#define REG_PIN_KEYOUT1 ( 0x0120 ) +#define REG_PIN_KEYOUT2 ( 0x0124 ) +#define REG_PIN_KEYOUT3 ( 0x0128 ) +#define REG_PIN_KEYOUT4 ( 0x012c ) +#define REG_PIN_KEYOUT5 ( 0x0130 ) +#define REG_PIN_GPIO135 ( 0x0134 ) +#define REG_PIN_GPIO136 ( 0x0138 ) +#define REG_PIN_GPIO137 ( 0x013c ) +#define REG_PIN_GPIO138 ( 0x0140 ) +#define REG_PIN_GPIO139 ( 0x0144 ) +#define REG_PIN_GPIO140 ( 0x0148 ) +#define REG_PIN_KEYOUT6 ( 0x014c ) +#define REG_PIN_KEYOUT7 ( 0x0150 ) +#define REG_PIN_KEYIN0 ( 0x0154 ) +#define REG_PIN_KEYIN1 ( 0x0158 ) +#define REG_PIN_KEYIN2 ( 0x015c ) +#define REG_PIN_KEYIN3 ( 0x0160 ) +#define REG_PIN_KEYIN4 ( 0x0164 ) +#define REG_PIN_KEYIN5 ( 0x0168 ) +#define REG_PIN_KEYIN6 ( 0x016c ) +#define REG_PIN_KEYIN7 ( 0x0170 ) +#define REG_PIN_NFWPN ( 0x0174 ) +#define REG_PIN_NFRB ( 0x0178 ) +#define REG_PIN_NFCLE ( 0x017c ) +#define REG_PIN_NFALE ( 0x0180 ) +#define REG_PIN_NFCEN ( 0x0184 ) +#define REG_PIN_NFREN ( 0x0188 ) +#define REG_PIN_NFWEN ( 0x018c ) +#define REG_PIN_NFD0 ( 0x0190 ) +#define REG_PIN_NFD1 ( 0x0194 ) +#define REG_PIN_NFD2 ( 0x0198 ) +#define REG_PIN_NFD3 ( 0x019c ) +#define REG_PIN_NFD4 ( 0x01a0 ) +#define REG_PIN_NFD5 ( 0x01a4 ) +#define REG_PIN_NFD6 ( 0x01a8 ) +#define REG_PIN_NFD7 ( 0x01ac ) +#define REG_PIN_NFD8 ( 0x01b0 ) +#define REG_PIN_NFD9 ( 0x01b4 ) +#define REG_PIN_NFD10 ( 0x01b8 ) +#define REG_PIN_NFD11 ( 0x01bc ) +#define REG_PIN_NFD12 ( 0x01c0 ) +#define REG_PIN_NFD13 ( 0x01c4 ) +#define REG_PIN_NFD14 ( 0x01c8 ) +#define REG_PIN_NFD15 ( 0x01cc ) +#define REG_PIN_SD3_CLK ( 0x01d0 ) +#define REG_PIN_SD3_CMD ( 0x01d4 ) +#define REG_PIN_SD3_D0 ( 0x01d8 ) +#define REG_PIN_SD3_D1 ( 0x01dc ) +#define REG_PIN_SD3_D2 ( 0x01e0 ) +#define REG_PIN_SD3_D3 ( 0x01e4 ) +#define REG_PIN_SD3_D4 ( 0x01e8 ) +#define REG_PIN_SD3_D5 ( 0x01ec ) +#define REG_PIN_SD3_D6 ( 0x01f0 ) +#define REG_PIN_SD3_D7 ( 0x01f4 ) +#define REG_PIN_EMMC_RST ( 0x01f8 ) +#define REG_PIN_SD1_CLK ( 0x01fc ) +#define REG_PIN_SD1_CMD ( 0x0200 ) +#define REG_PIN_SD1_D0 ( 0x0204 ) +#define REG_PIN_SD1_D1 ( 0x0208 ) +#define REG_PIN_SD1_D2 ( 0x020c ) +#define REG_PIN_SD1_D3 ( 0x0210 ) +#define REG_PIN_LCD_CSN1 ( 0x0214 ) +#define REG_PIN_LCD_RSTN ( 0x0218 ) +#define REG_PIN_LCD_CD ( 0x021c ) +#define REG_PIN_LCD_D0 ( 0x0220 ) +#define REG_PIN_LCD_D1 ( 0x0224 ) +#define REG_PIN_LCD_D2 ( 0x0228 ) +#define REG_PIN_LCD_D3 ( 0x022c ) +#define REG_PIN_LCD_D4 ( 0x0230 ) +#define REG_PIN_LCD_D5 ( 0x0234 ) +#define REG_PIN_LCD_D6 ( 0x0238 ) +#define REG_PIN_LCD_D7 ( 0x023c ) +#define REG_PIN_LCD_D8 ( 0x0240 ) +#define REG_PIN_LCD_WRN ( 0x0244 ) +#define REG_PIN_LCD_RDN ( 0x0248 ) +#define REG_PIN_LCD_CSN0 ( 0x024c ) +#define REG_PIN_LCD_D9 ( 0x0250 ) +#define REG_PIN_LCD_D10 ( 0x0254 ) +#define REG_PIN_LCD_D11 ( 0x0258 ) +#define REG_PIN_LCD_D12 ( 0x025c ) +#define REG_PIN_LCD_D13 ( 0x0260 ) +#define REG_PIN_LCD_D14 ( 0x0264 ) +#define REG_PIN_LCD_D15 ( 0x0268 ) +#define REG_PIN_LCD_D16 ( 0x026c ) +#define REG_PIN_LCD_D17 ( 0x0270 ) +#define REG_PIN_LCD_D18 ( 0x0274 ) +#define REG_PIN_LCD_D19 ( 0x0278 ) +#define REG_PIN_LCD_D20 ( 0x027c ) +#define REG_PIN_LCD_D21 ( 0x0280 ) +#define REG_PIN_LCD_D22 ( 0x0284 ) +#define REG_PIN_LCD_D23 ( 0x0288 ) +#define REG_PIN_LCD_FMARK ( 0x028c ) +#define REG_PIN_SPI2_CSN ( 0x0290 ) +#define REG_PIN_SPI2_DO ( 0x0294 ) +#define REG_PIN_SPI2_DI ( 0x0298 ) +#define REG_PIN_SPI2_CLK ( 0x029c ) +#define REG_PIN_SCL0 ( 0x02a0 ) +#define REG_PIN_SDA0 ( 0x02a4 ) +#define REG_PIN_SCL2 ( 0x02a8 ) +#define REG_PIN_SDA2 ( 0x02ac ) +#define REG_PIN_SCL3 ( 0x02b0 ) +#define REG_PIN_SDA3 ( 0x02b4 ) +#define REG_PIN_CLK_AUX0 ( 0x02b8 ) +#define REG_PIN_IIS0DI ( 0x02bc ) +#define REG_PIN_IIS0DO ( 0x02c0 ) +#define REG_PIN_IIS0CLK ( 0x02c4 ) +#define REG_PIN_IIS0LRCK ( 0x02c8 ) +#define REG_PIN_IIS0MCK ( 0x02cc ) +#define REG_PIN_SPI0_CSN ( 0x02d0 ) +#define REG_PIN_SPI0_DO ( 0x02d4 ) +#define REG_PIN_SPI0_DI ( 0x02d8 ) +#define REG_PIN_SPI0_CLK ( 0x02dc ) +#define REG_PIN_GPIO141 ( 0x02e0 ) +#define REG_PIN_GPIO142 ( 0x02e4 ) +#define REG_PIN_MTDO ( 0x02e8 ) + +#define REG_PIN_MTDI ( 0x02ec ) +#define REG_PIN_MTCK ( 0x02f0 ) +#define REG_PIN_MTMS ( 0x02f4 ) +#define REG_PIN_MTRST_N ( 0x02f8 ) +#define REG_PIN_TRACECLK ( 0x02fc ) +#define REG_PIN_TRACECTRL ( 0x0300 ) +#define REG_PIN_TRACEDAT0 ( 0x0304 ) +#define REG_PIN_TRACEDAT1 ( 0x0308 ) +#define REG_PIN_TRACEDAT2 ( 0x030c ) +#define REG_PIN_TRACEDAT3 ( 0x0310 ) +#define REG_PIN_TRACEDAT4 ( 0x0314 ) +#define REG_PIN_TRACEDAT5 ( 0x0318 ) +#define REG_PIN_TRACEDAT6 ( 0x031c ) +#define REG_PIN_TRACEDAT7 ( 0x0320 ) +#define REG_PIN_U0TXD ( 0x0324 ) +#define REG_PIN_U0RXD ( 0x0328 ) +#define REG_PIN_U0CTS ( 0x032c ) +#define REG_PIN_U0RTS ( 0x0330 ) +#define REG_PIN_U1TXD ( 0x0334 ) +#define REG_PIN_U1RXD ( 0x0338 ) +#define REG_PIN_U2TXD ( 0x033c ) +#define REG_PIN_U2RXD ( 0x0340 ) +#define REG_PIN_U2CTS ( 0x0344 ) +#define REG_PIN_U2RTS ( 0x0348 ) +#define REG_PIN_U3TXD ( 0x034c ) +#define REG_PIN_U3RXD ( 0x0350 ) +#define REG_PIN_U3CTS ( 0x0354 ) +#define REG_PIN_U3RTS ( 0x0358 ) +#define REG_PIN_CLK_REQ1 ( 0x035c ) +#define REG_PIN_CLK_REQ2 ( 0x0360 ) +#define REG_PIN_RFSDA0 ( 0x0364 ) +#define REG_PIN_RFSCK0 ( 0x0368 ) +#define REG_PIN_RFSEN0 ( 0x036c ) +#define REG_PIN_RFCTL0 ( 0x0370 ) +#define REG_PIN_RFCTL1 ( 0x0374 ) +#define REG_PIN_RFCTL2 ( 0x0378 ) +#define REG_PIN_RFCTL3 ( 0x037c ) + +#define REG_PIN_RFCTL4 ( 0x0380 ) +#define REG_PIN_RFCTL5 ( 0x0384 ) +#define REG_PIN_RFCTL6 ( 0x0388 ) +#define REG_PIN_RFCTL7 ( 0x038c ) +#define REG_PIN_RFCTL8 ( 0x0390 ) +#define REG_PIN_RFCTL9 ( 0x0394 ) +#define REG_PIN_RFCTL10 ( 0x0398 ) +#define REG_PIN_RFCTL11 ( 0x039c ) +#define REG_PIN_RFCTL12 ( 0x03a0 ) +#define REG_PIN_RFCTL13 ( 0x03a4 ) +#define REG_PIN_RFCTL14 ( 0x03a8 ) +#define REG_PIN_RFCTL15 ( 0x03ac ) +#define REG_PIN_XTL_EN ( 0x03b0 ) +#define REG_PIN_PTEST ( 0x03b4 ) +#define REG_PIN_GPIO143 ( 0x03b8 ) +#define REG_PIN_GPIO144 ( 0x03bc ) + + +/* bits definitions for register REG_PIN_XXX */ +#define BITS_PIN_DS(_x_) ( (_x_) << 19 & (BIT(19)|BIT(20)) ) +#define BITS_PIN_DS_3(_x_) ( (_x_) << 19 & (BIT(19)|BIT(20)|BIT(21)) ) +#define BITS_PIN_DS_4(_x_) ( (_x_) << 19 & (BIT(19)|BIT(20)|BIT(21)|BIT(22)) ) +#define BIT_PIN_SLP_AP ( BIT(13) ) +#define BIT_PIN_WPU ( BIT(7) ) +#define BIT_PIN_WPD ( BIT(6) ) +#define BITS_PIN_AF(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BIT_PIN_SLP_WPU ( BIT(3) ) +#define BIT_PIN_SLP_WPD ( BIT(2) ) +#define BIT_PIN_SLP_IE ( BIT(1) ) +#define BIT_PIN_SLP_OE ( BIT(0) ) + +/* vars definitions for controller CTL_PIN */ +#define BIT_PIN_NUL ( 0 ) +#define BIT_PIN_SLP_NUL ( 0 ) +#define BIT_PIN_SLP_Z ( 0 ) + + + + + + + + + + + +#endif diff --git a/include/soc/sprd/chip_x35l/__regs_pmu_apb_rf.h b/include/soc/sprd/chip_x35l/__regs_pmu_apb_rf.h new file mode 100755 index 00000000..790fe771 --- /dev/null +++ b/include/soc/sprd/chip_x35l/__regs_pmu_apb_rf.h @@ -0,0 +1,893 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_PMU_APB_HEADFILE_H__ +#define __H_REGS_PMU_APB_HEADFILE_H__ __FILE__ + +#define REGS_PMU_APB_RF + +/* registers definitions for PMU_APB_RF */ +#define REG_PMU_APB_PD_CA7_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0000) +#define REG_PMU_APB_PD_CA7_C0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0004) +#define REG_PMU_APB_PD_CA7_C1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0008) +#define REG_PMU_APB_PD_CA7_C2_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x000C) +#define REG_PMU_APB_PD_CA7_C3_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0010) +#define REG_PMU_APB_PD_AP_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0018) +#define REG_PMU_APB_PD_MM_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x001C) +#define REG_PMU_APB_PD_GPU_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0020) +#define REG_PMU_APB_PD_CP0_ARM9_0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0024) +#define REG_PMU_APB_PD_CP0_ARM9_1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0028) +#define REG_PMU_APB_PD_CP0_HU3GE_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x002C) +#define REG_PMU_APB_PD_CP0_GSM_0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0030) +#define REG_PMU_APB_PD_CP0_GSM_1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0034) +#define REG_PMU_APB_PD_CP0_TD_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0038) +#define REG_PMU_APB_PD_CP0_CEVA_0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x003C) +#define REG_PMU_APB_PD_CP0_CEVA_1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0040) +#define REG_PMU_APB_PD_CP0_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0044) +#define REG_PMU_APB_PD_CP1_CA5_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0048) +#define REG_PMU_APB_PD_CP1_LTE_P1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x004C) +#define REG_PMU_APB_PD_CP1_LTE_P2_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0050) +#define REG_PMU_APB_PD_CP1_CEVA_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0054) +#define REG_PMU_APB_PD_CP1_COMWRAP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0058) +#define REG_PMU_APB_PD_PUB_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x005C) +#define REG_PMU_APB_AP_WAKEUP_POR_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0060) +#define REG_PMU_APB_XTL_WAIT_CNT SCI_ADDR(REGS_PMU_APB_BASE, 0x0070) +#define REG_PMU_APB_XTLBUF_WAIT_CNT SCI_ADDR(REGS_PMU_APB_BASE, 0x0074) +#define REG_PMU_APB_PLL_WAIT_CNT1 SCI_ADDR(REGS_PMU_APB_BASE, 0x0078) +#define REG_PMU_APB_PLL_WAIT_CNT2 SCI_ADDR(REGS_PMU_APB_BASE, 0x007C) +#define REG_PMU_APB_XTL0_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0080) +#define REG_PMU_APB_XTL1_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0084) +#define REG_PMU_APB_XTLBUF0_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x008C) +#define REG_PMU_APB_XTLBUF1_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0090) +#define REG_PMU_APB_MPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0094) +#define REG_PMU_APB_DPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0098) +#define REG_PMU_APB_LTEPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x009C) +#define REG_PMU_APB_TWPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00A0) +#define REG_PMU_APB_LVDSDIS_PLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00A4) +#define REG_PMU_APB_CP_SOFT_RST SCI_ADDR(REGS_PMU_APB_BASE, 0x00B0) +#define REG_PMU_APB_CP_SLP_STATUS_DBG0 SCI_ADDR(REGS_PMU_APB_BASE, 0x00B4) +#define REG_PMU_APB_PWR_STATUS0_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00BC) +#define REG_PMU_APB_PWR_STATUS1_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00C0) +#define REG_PMU_APB_PWR_STATUS2_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00C4) +#define REG_PMU_APB_SLEEP_CTRL SCI_ADDR(REGS_PMU_APB_BASE, 0x00CC) +#define REG_PMU_APB_DDR_SLEEP_CTRL SCI_ADDR(REGS_PMU_APB_BASE, 0x00D0) +#define REG_PMU_APB_SLEEP_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x00D4) +#define REG_PMU_APB_CA7_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00E4) +#define REG_PMU_APB_CA7_C0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00E8) +#define REG_PMU_APB_CA7_C1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00EC) +#define REG_PMU_APB_CA7_C2_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00F0) +#define REG_PMU_APB_CA7_C3_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00F4) +#define REG_PMU_APB_DDR_CHN_SLEEP_CTRL0 SCI_ADDR(REGS_PMU_APB_BASE, 0x00F8) +#define REG_PMU_APB_DDR_CHN_SLEEP_CTRL1 SCI_ADDR(REGS_PMU_APB_BASE, 0x00FC) +#define REG_PMU_APB_DDR_OP_MODE_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x012C) +#define REG_PMU_APB_DDR_PHY_RET_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0130) +#define REG_PMU_APB_26M_SEL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0134) +#define REG_PMU_APB_BISR_DONE_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x0138) +#define REG_PMU_APB_BISR_BUSY_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x013C) +#define REG_PMU_APB_BISR_BYP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0140) +#define REG_PMU_APB_BISR_EN_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0144) +#define REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG0 SCI_ADDR(REGS_PMU_APB_BASE, 0x0148) +#define REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG1 SCI_ADDR(REGS_PMU_APB_BASE, 0x014C) +#define REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG2 SCI_ADDR(REGS_PMU_APB_BASE, 0x0150) +#define REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG3 SCI_ADDR(REGS_PMU_APB_BASE, 0x0154) +#define REG_PMU_APB_CGM_FORCE_EN_CFG0 SCI_ADDR(REGS_PMU_APB_BASE, 0x0158) +#define REG_PMU_APB_CGM_FORCE_EN_CFG1 SCI_ADDR(REGS_PMU_APB_BASE, 0x015C) +#define REG_PMU_APB_CGM_FORCE_EN_CFG2 SCI_ADDR(REGS_PMU_APB_BASE, 0x0160) +#define REG_PMU_APB_CGM_FORCE_EN_CFG3 SCI_ADDR(REGS_PMU_APB_BASE, 0x0164) +#define REG_PMU_APB_SLEEP_XTLON_CTRL SCI_ADDR(REGS_PMU_APB_BASE, 0x0168) +#define REG_PMU_APB_MEM_SLP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x016C) +#define REG_PMU_APB_MEM_SD_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0170) +#define REG_PMU_APB_CA7_CORE_PU_LOCK SCI_ADDR(REGS_PMU_APB_BASE, 0x0174) +#define REG_PMU_APB_ARM7_HOLD_CGM_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0178) +#define REG_PMU_APB_PWR_CNT_WAIT_CFG0 SCI_ADDR(REGS_PMU_APB_BASE, 0x017C) +#define REG_PMU_APB_PWR_CNT_WAIT_CFG1 SCI_ADDR(REGS_PMU_APB_BASE, 0x0180) +#define REG_PMU_APB_RC0_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0184) +#define REG_PMU_APB_RC1_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0188) +#define REG_PMU_APB_RC_CNT_WAIT_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x018C) +#define REG_PMU_APB_MEM_AUTO_SLP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0190) +#define REG_PMU_APB_MEM_AUTO_SD_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0194) +#define REG_PMU_APB_CP0_PD_SHUTDOWN_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0198) +#define REG_PMU_APB_CP1_PD_SHUTDOWN_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x019C) +#define REG_PMU_APB_WAKEUP_LOCK_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x01A0) +#if defined(CONFIG_MACH_SP9830I) +#define REG_PMU_APB_PD_CODEC_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0X01A4) +#endif +#define REG_PMU_APB_PD_CA7_C0_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3000) +#define REG_PMU_APB_PD_CA7_C1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3004) +#define REG_PMU_APB_PD_CA7_C2_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3008) +#define REG_PMU_APB_PD_CA7_C3_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x300C) +#define REG_PMU_APB_PD_CA7_TOP_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3010) +#define REG_PMU_APB_PD_AP_SYS_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3014) +#define REG_PMU_APB_PD_GPU_TOP_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3018) +#define REG_PMU_APB_PD_MM_TOP_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x301C) +#define REG_PMU_APB_PD_CP0_ARM9_0_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3020) +#define REG_PMU_APB_PD_CP0_ARM9_1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3024) +#define REG_PMU_APB_PD_CP0_CEVA_0_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3028) +#define REG_PMU_APB_PD_CP0_CEVA_1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x302C) +#define REG_PMU_APB_PD_CP0_GSM_0_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3030) +#define REG_PMU_APB_PD_CP0_GSM_1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3034) +#define REG_PMU_APB_PD_CP0_TD_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3038) +#define REG_PMU_APB_PD_CP0_HU3GE_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x303C) +#define REG_PMU_APB_PD_CP1_CA5_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3040) +#define REG_PMU_APB_PD_CP1_CEVA_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3044) +#define REG_PMU_APB_PD_CP1_LTE_P1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3048) +#define REG_PMU_APB_PD_CP1_LTE_P2_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x304C) +#define REG_PMU_APB_PD_CP1_COMWRAP_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3050) +#define REG_PMU_APB_PD_PUB_SYS_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3054) +#if defined(CONFIG_MACH_SP9830I) +#define REG_PMU_APB_PD_CODEC_TOP_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3058) +#endif + +/* bits definitions for register REG_PMU_APB_PD_CA7_TOP_CFG */ +#define BIT_PD_CA7_TOP_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_PD_CA7_TOP_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CA7_TOP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA7_TOP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA7_C0_CFG */ +#define BIT_PD_CA7_C0_WFI_SHUTDOWN_EN ( BIT(29) ) +#define BIT_PD_CA7_C0_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_PD_CA7_C0_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CA7_C0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA7_C0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA7_C1_CFG */ +#define BIT_PD_CA7_C1_WFI_SHUTDOWN_EN ( BIT(29) ) +#define BIT_PD_CA7_C1_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_PD_CA7_C1_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA7_C1_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CA7_C1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA7_C1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA7_C2_CFG */ +#define BIT_PD_CA7_C2_WFI_SHUTDOWN_EN ( BIT(29) ) +#define BIT_PD_CA7_C2_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_PD_CA7_C2_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA7_C2_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CA7_C2_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA7_C2_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA7_C3_CFG */ +#define BIT_PD_CA7_C3_WFI_SHUTDOWN_EN ( BIT(29) ) +#define BIT_PD_CA7_C3_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_PD_CA7_C3_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA7_C3_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CA7_C3_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA7_C3_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_AP_SYS_CFG */ +#define BIT_PD_AP_SYS_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_AP_SYS_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_AP_SYS_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_MM_TOP_CFG */ +#define BIT_PD_MM_TOP_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_MM_TOP_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_MM_TOP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_MM_TOP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_GPU_TOP_CFG */ +#define BIT_PD_GPU_TOP_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_GPU_TOP_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_GPU_TOP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_GPU_TOP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_0_CFG */ +#define BIT_PD_CP0_ARM9_0_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_ARM9_0_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_ARM9_0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_ARM9_0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_ARM9_0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_1_CFG */ +#define BIT_PD_CP0_ARM9_1_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_ARM9_1_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_ARM9_1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_ARM9_1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_ARM9_1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_HU3GE_CFG */ +#define BIT_PD_CP0_HU3GE_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_HU3GE_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_HU3GE_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_HU3GE_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_HU3GE_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_GSM_0_CFG */ +#define BIT_PD_CP0_GSM_0_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_GSM_0_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_GSM_0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_GSM_0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_GSM_0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_GSM_1_CFG */ +#define BIT_PD_CP0_GSM_1_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_GSM_1_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_GSM_1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_GSM_1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_GSM_1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_TD_CFG */ +#define BIT_PD_CP0_TD_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_TD_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_TD_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_TD_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_TD_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_CEVA_0_CFG */ +#define BIT_PD_CP0_CEVA_0_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_CEVA_0_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_CEVA_0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_CEVA_0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_CEVA_0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_CEVA_1_CFG */ +#define BIT_PD_CP0_CEVA_1_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_CEVA_1_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_CEVA_1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_CEVA_1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_CEVA_1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_SYS_CFG */ + +/* bits definitions for register REG_PMU_APB_PD_CP1_CA5_CFG */ +#define BIT_PD_CP1_CA5_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP1_CA5_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP1_CA5_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_CA5_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_CA5_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_LTE_P1_CFG */ +#define BIT_PD_CP1_LTE_P1_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP1_LTE_P1_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP1_LTE_P1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_LTE_P1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_LTE_P1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_LTE_P2_CFG */ +#define BIT_PD_CP1_LTE_P2_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP1_LTE_P2_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP1_LTE_P2_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_LTE_P2_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_LTE_P2_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_CEVA_CFG */ +#define BIT_PD_CP1_CEVA_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP1_CEVA_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP1_CEVA_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_CEVA_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_CEVA_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_COMWRAP_CFG */ +#define BIT_PD_CP1_COMWRAP_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP1_COMWRAP_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP1_COMWRAP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_COMWRAP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_COMWRAP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_PUB_SYS_CFG */ +#define BIT_PD_PUB_SYS_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_PUB_SYS_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_PUB_SYS_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_AP_WAKEUP_POR_CFG */ +#define BIT_AP_WAKEUP_POR_N ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_XTL_WAIT_CNT */ +#define BITS_XTL1_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_XTL0_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_XTLBUF_WAIT_CNT */ +#define BITS_XTLBUF1_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_XTLBUF0_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PLL_WAIT_CNT1 */ +#define BITS_LTEPLL_WAIT_CNT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_TWPLL_WAIT_CNT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DPLL_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_MPLL_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PLL_WAIT_CNT2 */ +#define BITS_LVDSDIS_PLL_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_XTL0_REL_CFG */ +#define BIT_XTL0_ARM7_SEL ( BIT(5) ) +#define BIT_XTL0_VCP1_SEL ( BIT(4) ) +#define BIT_XTL0_VCP0_SEL ( BIT(3) ) +#define BIT_XTL0_CP1_SEL ( BIT(2) ) +#define BIT_XTL0_CP0_SEL ( BIT(1) ) +#define BIT_XTL0_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_XTL1_REL_CFG */ +#define BIT_XTL1_ARM7_SEL ( BIT(5) ) +#define BIT_XTL1_VCP1_SEL ( BIT(4) ) +#define BIT_XTL1_VCP0_SEL ( BIT(3) ) +#define BIT_XTL1_CP1_SEL ( BIT(2) ) +#define BIT_XTL1_CP0_SEL ( BIT(1) ) +#define BIT_XTL1_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_XTLBUF0_REL_CFG */ +#define BIT_XTLBUF0_ARM7_SEL ( BIT(5) ) +#define BIT_XTLBUF0_VCP1_SEL ( BIT(4) ) +#define BIT_XTLBUF0_VCP0_SEL ( BIT(3) ) +#define BIT_XTLBUF0_CP1_SEL ( BIT(2) ) +#define BIT_XTLBUF0_CP0_SEL ( BIT(1) ) +#define BIT_XTLBUF0_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_XTLBUF1_REL_CFG */ +#define BIT_XTLBUF1_ARM7_SEL ( BIT(5) ) +#define BIT_XTLBUF1_VCP1_SEL ( BIT(4) ) +#define BIT_XTLBUF1_VCP0_SEL ( BIT(3) ) +#define BIT_XTLBUF1_CP1_SEL ( BIT(2) ) +#define BIT_XTLBUF1_CP0_SEL ( BIT(1) ) +#define BIT_XTLBUF1_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_MPLL_REL_CFG */ +#define BIT_MPLL_REF_SEL ( BIT(8) ) +#define BIT_MPLL_ARM7_SEL ( BIT(5) ) +#define BIT_MPLL_VCP1_SEL ( BIT(4) ) +#define BIT_MPLL_VCP0_SEL ( BIT(3) ) +#define BIT_MPLL_CP1_SEL ( BIT(2) ) +#define BIT_MPLL_CP0_SEL ( BIT(1) ) +#define BIT_MPLL_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_DPLL_REL_CFG */ +#define BIT_DPLL_REF_SEL ( BIT(8) ) +#define BIT_DPLL_ARM7_SEL ( BIT(5) ) +#define BIT_DPLL_VCP1_SEL ( BIT(4) ) +#define BIT_DPLL_VCP0_SEL ( BIT(3) ) +#define BIT_DPLL_CP1_SEL ( BIT(2) ) +#define BIT_DPLL_CP0_SEL ( BIT(1) ) +#define BIT_DPLL_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_LTEPLL_REL_CFG */ +#define BIT_LTEPLL_REF_SEL ( BIT(8) ) +#define BIT_LTEPLL_ARM7_SEL ( BIT(5) ) +#define BIT_LTEPLL_VCP1_SEL ( BIT(4) ) +#define BIT_LTEPLL_VCP0_SEL ( BIT(3) ) +#define BIT_LTEPLL_CP1_SEL ( BIT(2) ) +#define BIT_LTEPLL_CP0_SEL ( BIT(1) ) +#define BIT_LTEPLL_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_TWPLL_REL_CFG */ +#define BIT_TWPLL_REF_SEL ( BIT(8) ) +#define BIT_TWPLL_ARM7_SEL ( BIT(5) ) +#define BIT_TWPLL_VCP1_SEL ( BIT(4) ) +#define BIT_TWPLL_VCP0_SEL ( BIT(3) ) +#define BIT_TWPLL_CP1_SEL ( BIT(2) ) +#define BIT_TWPLL_CP0_SEL ( BIT(1) ) +#define BIT_TWPLL_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_LVDSDIS_PLL_REL_CFG */ +#define BIT_LVDSDIS_PLL_REF_SEL ( BIT(8) ) +#define BIT_LVDSDIS_PLL_ARM7_SEL ( BIT(5) ) +#define BIT_LVDSDIS_PLL_VCP1_SEL ( BIT(4) ) +#define BIT_LVDSDIS_PLL_VCP0_SEL ( BIT(3) ) +#define BIT_LVDSDIS_PLL_CP1_SEL ( BIT(2) ) +#define BIT_LVDSDIS_PLL_CP0_SEL ( BIT(1) ) +#define BIT_LVDSDIS_PLL_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CP_SOFT_RST */ +#define BIT_ARM7_SOFT_RST ( BIT(8) ) +#define BIT_PUB_SOFT_RST ( BIT(6) ) +#define BIT_AP_SOFT_RST ( BIT(5) ) +#define BIT_GPU_SOFT_RST ( BIT(4) ) +#define BIT_MM_SOFT_RST ( BIT(3) ) +#if defined(CONFIG_MACH_SP9830I) +#define BIT_CODEC_SOFT_RST (bit(2)) +#endif +#define BIT_CP1_SOFT_RST ( BIT(1) ) +#define BIT_CP0_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CP_SLP_STATUS_DBG0 */ +#define BITS_CP1_DEEP_SLP_DBG(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_CP0_DEEP_SLP_DBG(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_PMU_APB_PWR_STATUS0_DBG */ +#define BITS_PD_MM_TOP_STATE(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_PD_GPU_TOP_STATE(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_PD_AP_SYS_STATE(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA7_C3_STATE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_PD_CA7_C2_STATE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA7_C1_STATE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_PD_CA7_C0_STATE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_PD_CA7_TOP_STATE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PWR_STATUS1_DBG */ +#define BITS_PD_CP0_CEVA_1_STATE(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_PD_CP0_CEVA_0_STATE(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_PD_CP0_GSM_0_STATE(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_GSM_1_STATE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_PD_CP0_HU3GE_STATE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_ARM9_1_STATE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_PD_CP0_ARM9_0_STATE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_PD_CP0_TD_STATE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PWR_STATUS2_DBG */ +#define BITS_PD_PUB_SYS_STATE(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_PD_CP1_COMWRAP_STATE(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_LTE_P2_STATE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_PD_CP1_LTE_P1_STATE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_CEVA_STATE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_PD_CP1_CA5_STATE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_SLEEP_CTRL */ +#define BIT_VCP1_FORCE_LIGHT_SLEEP ( BIT(28) ) +#define BIT_VCP0_FORCE_LIGHT_SLEEP ( BIT(27) ) +#define BIT_CP1_FORCE_LIGHT_SLEEP ( BIT(26) ) +#define BIT_CP0_FORCE_LIGHT_SLEEP ( BIT(25) ) +#define BIT_AP_FORCE_LIGHT_SLEEP ( BIT(24) ) +#define BIT_ARM7_FORCE_DEEP_SLEEP ( BIT(21) ) +#define BIT_VCP1_FORCE_DEEP_SLEEP ( BIT(20) ) +#define BIT_VCP0_FORCE_DEEP_SLEEP ( BIT(19) ) +#define BIT_CP1_FORCE_DEEP_SLEEP ( BIT(18) ) +#define BIT_CP0_FORCE_DEEP_SLEEP ( BIT(17) ) +#define BIT_AP_FORCE_DEEP_SLEEP ( BIT(16) ) +#define BIT_VCP1_LIGHT_SLEEP ( BIT(12) ) +#define BIT_VCP0_LIGHT_SLEEP ( BIT(11) ) +#define BIT_CP1_LIGHT_SLEEP ( BIT(10) ) +#define BIT_CP0_LIGHT_SLEEP ( BIT(9) ) +#define BIT_AP_LIGHT_SLEEP ( BIT(8) ) +#define BIT_VCP1_DEEP_SLEEP ( BIT(4) ) +#define BIT_VCP0_DEEP_SLEEP ( BIT(3) ) +#define BIT_CP1_DEEP_SLEEP ( BIT(2) ) +#define BIT_CP0_DEEP_SLEEP ( BIT(1) ) +#define BIT_AP_DEEP_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_DDR_SLEEP_CTRL */ +#define BIT_BUSY_TRANSFER_HWDATA_SEL ( BIT(16) ) +#define BIT_DDR_PUBL_APB_SOFT_RST ( BIT(12) ) +#define BIT_DDR_UMCTL_APB_SOFT_RST ( BIT(11) ) +#define BIT_DDR_PUBL_SOFT_RST ( BIT(10) ) +#define BIT_DDR_PHY_SOFT_RST ( BIT(8) ) +#define BIT_DDR_PHY_AUTO_GATE_EN ( BIT(6) ) +#define BIT_DDR_PUBL_AUTO_GATE_EN ( BIT(5) ) +#define BIT_DDR_UMCTL_AUTO_GATE_EN ( BIT(4) ) +#define BIT_DDR_PHY_EB ( BIT(2) ) +#define BIT_DDR_UMCTL_EB ( BIT(1) ) +#define BIT_DDR_PUBL_EB ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_SLEEP_STATUS */ +#define BITS_ARM7_SLP_STATUS(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_VCP1_SLP_STATUS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_VCP0_SLP_STATUS(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_CP1_SLP_STATUS(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CP0_SLP_STATUS(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_AP_SLP_STATUS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_CA7_TOP_CFG */ +#define BIT_CA7_L2RSTDISABLE ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CA7_C0_CFG */ +#define BIT_CA7_VINITHI_C0 ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CA7_C1_CFG */ +#define BIT_CA7_VINITHI_C1 ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CA7_C2_CFG */ +#define BIT_CA7_VINITHI_C2 ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CA7_C3_CFG */ +#define BIT_CA7_VINITHI_C3 ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_DDR_CHN_SLEEP_CTRL0 */ +#define BIT_DDR_CTRL_AXI_LP_EN ( BIT(31) ) +#define BIT_DDR_CTRL_CGM_SEL ( BIT(30) ) +#define BIT_DDR_CHN9_AXI_LP_EN ( BIT(25) ) +#define BIT_DDR_CHN8_AXI_LP_EN ( BIT(24) ) +#define BIT_DDR_CHN7_AXI_LP_EN ( BIT(23) ) +#define BIT_DDR_CHN6_AXI_LP_EN ( BIT(22) ) +#define BIT_DDR_CHN5_AXI_LP_EN ( BIT(21) ) +#define BIT_DDR_CHN4_AXI_LP_EN ( BIT(20) ) +#define BIT_DDR_CHN3_AXI_LP_EN ( BIT(19) ) +#define BIT_DDR_CHN2_AXI_LP_EN ( BIT(18) ) +#define BIT_DDR_CHN1_AXI_LP_EN ( BIT(17) ) +#define BIT_DDR_CHN0_AXI_LP_EN ( BIT(16) ) +#define BIT_DDR_CHN9_CGM_SEL ( BIT(9) ) +#define BIT_DDR_CHN8_CGM_SEL ( BIT(8) ) +#define BIT_DDR_CHN7_CGM_SEL ( BIT(7) ) +#define BIT_DDR_CHN6_CGM_SEL ( BIT(6) ) +#define BIT_DDR_CHN5_CGM_SEL ( BIT(5) ) +#define BIT_DDR_CHN4_CGM_SEL ( BIT(4) ) +#define BIT_DDR_CHN3_CGM_SEL ( BIT(3) ) +#define BIT_DDR_CHN2_CGM_SEL ( BIT(2) ) +#define BIT_DDR_CHN1_CGM_SEL ( BIT(1) ) +#define BIT_DDR_CHN0_CGM_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_DDR_CHN_SLEEP_CTRL1 */ +#define BIT_DDR_CHN9_AXI_STOP_SEL ( BIT(9) ) +#define BIT_DDR_CHN8_AXI_STOP_SEL ( BIT(8) ) +#define BIT_DDR_CHN7_AXI_STOP_SEL ( BIT(7) ) +#define BIT_DDR_CHN6_AXI_STOP_SEL ( BIT(6) ) +#define BIT_DDR_CHN5_AXI_STOP_SEL ( BIT(5) ) +#define BIT_DDR_CHN4_AXI_STOP_SEL ( BIT(4) ) +#define BIT_DDR_CHN3_AXI_STOP_SEL ( BIT(3) ) +#define BIT_DDR_CHN2_AXI_STOP_SEL ( BIT(2) ) +#define BIT_DDR_CHN1_AXI_STOP_SEL ( BIT(1) ) +#define BIT_DDR_CHN0_AXI_STOP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_DDR_OP_MODE_CFG */ +#define BIT_DDR_OPERATE_MODE_BUSY ( BIT(28) ) +#define BIT_DDR_PUBL_RET_EN ( BIT(27) ) +#define BIT_DDR_PHY_ISO_RST_EN ( BIT(26) ) +#define BIT_DDR_UMCTL_RET_EN ( BIT(25) ) +#define BIT_DDR_PHY_AUTO_RET_EN ( BIT(24) ) +#define BITS_DDR_OPERATE_MODE_CNT_LMT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DDR_OPERATE_MODE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_DDR_OPERATE_MODE_IDLE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_PMU_APB_DDR_PHY_RET_CFG */ +#define BIT_DDR_UMCTL_SOFT_RST ( BIT(16) ) +#define BIT_DDR_PHY_CKE_RET_EN ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_26M_SEL_CFG */ +#define BIT_AON_RC_4M_SEL ( BIT(8) ) +#define BIT_GGE_26M_SEL ( BIT(6) ) +#define BIT_PUB_26M_SEL ( BIT(5) ) +#define BIT_AON_26M_SEL ( BIT(4) ) +#define BIT_CP1_26M_SEL ( BIT(2) ) +#define BIT_CP0_26M_SEL ( BIT(1) ) +#define BIT_AP_26M_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_BISR_DONE_STATUS */ +#define BIT_PD_CP1_COMWRAP_BISR_DONE ( BIT(21) ) +#define BIT_PD_CP1_LTE_P2_BISR_DONE ( BIT(20) ) +#define BIT_PD_CP1_LTE_P1_BISR_DONE ( BIT(19) ) +#define BIT_PD_CP1_CEVA_BISR_DONE ( BIT(18) ) +#define BIT_PD_CP1_CA5_BISR_DONE ( BIT(17) ) +#define BIT_PD_CP0_HU3GE_BISR_DONE ( BIT(15) ) +#define BIT_PD_CP0_TD_BISR_DONE ( BIT(14) ) +#define BIT_PD_CP0_GSM_1_BISR_DONE ( BIT(13) ) +#define BIT_PD_CP0_GSM_0_BISR_DONE ( BIT(12) ) +#define BIT_PD_CP0_CEVA_1_BISR_DONE ( BIT(11) ) +#define BIT_PD_CP0_CEVA_0_BISR_DONE ( BIT(10) ) +#define BIT_PD_CP0_ARM9_1_BISR_DONE ( BIT(9) ) +#define BIT_PD_CP0_ARM9_0_BISR_DONE ( BIT(8) ) +#define BIT_PD_MM_TOP_BISR_DONE ( BIT(7) ) +#define BIT_PD_GPU_TOP_BISR_DONE ( BIT(6) ) +#define BIT_PD_AP_SYS_BISR_DONE ( BIT(5) ) +#define BIT_PD_CA7_TOP_BISR_DONE ( BIT(4) ) +#define BIT_PD_CA7_C3_BISR_DONE ( BIT(3) ) +#define BIT_PD_CA7_C2_BISR_DONE ( BIT(2) ) +#define BIT_PD_CA7_C1_BISR_DONE ( BIT(1) ) +#define BIT_PD_CA7_C0_BISR_DONE ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_BISR_BUSY_STATUS */ +#define BIT_PD_CP1_COMWRAP_BISR_BUSY ( BIT(21) ) +#define BIT_PD_CP1_LTE_P2_BISR_BUSY ( BIT(20) ) +#define BIT_PD_CP1_LTE_P1_BISR_BUSY ( BIT(19) ) +#define BIT_PD_CP1_CEVA_BISR_BUSY ( BIT(18) ) +#define BIT_PD_CP1_CA5_BISR_BUSY ( BIT(17) ) +#define BIT_PD_CP0_HU3GE_BISR_BUSY ( BIT(15) ) +#define BIT_PD_CP0_TD_BISR_BUSY ( BIT(14) ) +#define BIT_PD_CP0_GSM_1_BISR_BUSY ( BIT(13) ) +#define BIT_PD_CP0_GSM_0_BISR_BUSY ( BIT(12) ) +#define BIT_PD_CP0_CEVA_1_BISR_BUSY ( BIT(11) ) +#define BIT_PD_CP0_CEVA_0_BISR_BUSY ( BIT(10) ) +#define BIT_PD_CP0_ARM9_1_BISR_BUSY ( BIT(9) ) +#define BIT_PD_CP0_ARM9_0_BISR_BUSY ( BIT(8) ) +#define BIT_PD_MM_TOP_BISR_BUSY ( BIT(7) ) +#define BIT_PD_GPU_TOP_BISR_BUSY ( BIT(6) ) +#define BIT_PD_AP_SYS_BISR_BUSY ( BIT(5) ) +#define BIT_PD_CA7_TOP_BISR_BUSY ( BIT(4) ) +#define BIT_PD_CA7_C3_BISR_BUSY ( BIT(3) ) +#define BIT_PD_CA7_C2_BISR_BUSY ( BIT(2) ) +#define BIT_PD_CA7_C1_BISR_BUSY ( BIT(1) ) +#define BIT_PD_CA7_C0_BISR_BUSY ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_BISR_BYP_CFG */ +#define BIT_PD_CP1_COMWRAP_BISR_FORCE_BYP ( BIT(21) ) +#define BIT_PD_CP1_LTE_P2_BISR_FORCE_BYP ( BIT(20) ) +#define BIT_PD_CP1_LTE_P1_BISR_FORCE_BYP ( BIT(19) ) +#define BIT_PD_CP1_CEVA_BISR_FORCE_BYP ( BIT(18) ) +#define BIT_PD_CP1_CA5_BISR_FORCE_BYP ( BIT(17) ) +#if defined(CONFIG_MACH_SP9830I) +#define BIT_PD_CODEC_TOP_BISR_FORCE_BYP (BIT(16)) +#endif +#define BIT_PD_CP0_HU3GE_BISR_FORCE_BYP ( BIT(15) ) +#define BIT_PD_CP0_TD_BISR_FORCE_BYP ( BIT(14) ) +#define BIT_PD_CP0_GSM_1_BISR_FORCE_BYP ( BIT(13) ) +#define BIT_PD_CP0_GSM_0_BISR_FORCE_BYP ( BIT(12) ) +#define BIT_PD_CP0_CEVA_1_BISR_FORCE_BYP ( BIT(11) ) +#define BIT_PD_CP0_CEVA_0_BISR_FORCE_BYP ( BIT(10) ) +#define BIT_PD_CP0_ARM9_1_BISR_FORCE_BYP ( BIT(9) ) +#define BIT_PD_CP0_ARM9_0_BISR_FORCE_BYP ( BIT(8) ) +#define BIT_PD_MM_TOP_BISR_FORCE_BYP ( BIT(7) ) +#define BIT_PD_GPU_TOP_BISR_FORCE_BYP ( BIT(6) ) +#define BIT_PD_AP_SYS_BISR_FORCE_BYP ( BIT(5) ) +#define BIT_PD_CA7_TOP_BISR_FORCE_BYP ( BIT(4) ) +#define BIT_PD_CA7_C3_BISR_FORCE_BYP ( BIT(3) ) +#define BIT_PD_CA7_C2_BISR_FORCE_BYP ( BIT(2) ) +#define BIT_PD_CA7_C1_BISR_FORCE_BYP ( BIT(1) ) +#define BIT_PD_CA7_C0_BISR_FORCE_BYP ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_BISR_EN_CFG */ +#define BIT_PD_CP1_COMWRAP_BISR_FORCE_EN ( BIT(21) ) +#define BIT_PD_CP1_LTE_P2_BISR_FORCE_EN ( BIT(20) ) +#define BIT_PD_CP1_LTE_P1_BISR_FORCE_EN ( BIT(19) ) +#define BIT_PD_CP1_CEVA_BISR_FORCE_EN ( BIT(18) ) +#define BIT_PD_CP1_CA5_BISR_FORCE_EN ( BIT(17) ) +#if defined(CONFIG_MACH_SP9830I) +#define BIT_CODEC_TOP_BISR_FORCE_EN (BIT(16)) +#endif +#define BIT_PD_CP0_HU3GE_BISR_FORCE_EN ( BIT(15) ) +#define BIT_PD_CP0_TD_BISR_FORCE_EN ( BIT(14) ) +#define BIT_PD_CP0_GSM_1_BISR_FORCE_EN ( BIT(13) ) +#define BIT_PD_CP0_GSM_0_BISR_FORCE_EN ( BIT(12) ) +#define BIT_PD_CP0_CEVA_1_BISR_FORCE_EN ( BIT(11) ) +#define BIT_PD_CP0_CEVA_0_BISR_FORCE_EN ( BIT(10) ) +#define BIT_PD_CP0_ARM9_1_BISR_FORCE_EN ( BIT(9) ) +#define BIT_PD_CP0_ARM9_0_BISR_FORCE_EN ( BIT(8) ) +#define BIT_PD_MM_TOP_BISR_FORCE_EN ( BIT(7) ) +#define BIT_PD_GPU_TOP_BISR_FORCE_EN ( BIT(6) ) +#define BIT_PD_AP_SYS_BISR_FORCE_EN ( BIT(5) ) +#define BIT_PD_CA7_TOP_BISR_FORCE_EN ( BIT(4) ) +#define BIT_PD_CA7_C3_BISR_FORCE_EN ( BIT(3) ) +#define BIT_PD_CA7_C2_BISR_FORCE_EN ( BIT(2) ) +#define BIT_PD_CA7_C1_BISR_FORCE_EN ( BIT(1) ) +#define BIT_PD_CA7_C0_BISR_FORCE_EN ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG0 */ +#define BITS_CGM_AUTO_GATE_SEL_CFG0(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG1 */ +#define BITS_CGM_AUTO_GATE_SEL_CFG1(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG2 */ +#define BITS_CGM_AUTO_GATE_SEL_CFG2(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG3 */ +#define BITS_CGM_AUTO_GATE_SEL_CFG3(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CGM_FORCE_EN_CFG0 */ +#define BITS_CGM_FORCE_EN_CFG0(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CGM_FORCE_EN_CFG1 */ +#define BITS_CGM_FORCE_EN_CFG1(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CGM_FORCE_EN_CFG2 */ +#define BITS_CGM_FORCE_EN_CFG2(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CGM_FORCE_EN_CFG3 */ +#define BITS_CGM_FORCE_EN_CFG3(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_SLEEP_XTLON_CTRL */ +#define BIT_ARM7_SLEEP_XTL_ON ( BIT(5) ) +#define BIT_VCP1_SLEEP_XTL_ON ( BIT(4) ) +#define BIT_VCP0_SLEEP_XTL_ON ( BIT(3) ) +#define BIT_CP1_SLEEP_XTL_ON ( BIT(2) ) +#define BIT_CP0_SLEEP_XTL_ON ( BIT(1) ) +#define BIT_AP_SLEEP_XTL_ON ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_MEM_SLP_CFG */ +#define BITS_MEM_SLP_CFG(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_MEM_SD_CFG */ +#define BITS_MEM_SD_CFG(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CA7_CORE_PU_LOCK */ +#define BIT_CA7_C3_GIC_WAKEUP_EN ( BIT(11) ) +#define BIT_CA7_C2_GIC_WAKEUP_EN ( BIT(10) ) +#define BIT_CA7_C1_GIC_WAKEUP_EN ( BIT(9) ) +#define BIT_CA7_C0_GIC_WAKEUP_EN ( BIT(8) ) +#define BIT_CA7_C3_PU_LOCK ( BIT(3) ) +#define BIT_CA7_C2_PU_LOCK ( BIT(2) ) +#define BIT_CA7_C1_PU_LOCK ( BIT(1) ) +#define BIT_CA7_C0_PU_LOCK ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_ARM7_HOLD_CGM_EN */ +#define BIT_PD_CP1_CEVA_CGM_HOLD_EN ( BIT(10) ) +#define BIT_PD_CP1_CA5_CGM_HOLD_EN ( BIT(9) ) +#define BIT_PD_CP0_CEVA_1_CGM_HOLD_EN ( BIT(8) ) +#define BIT_PD_CP0_CEVA_0_CGM_HOLD_EN ( BIT(7) ) +#define BIT_PD_CP0_ARM9_1_CGM_HOLD_EN ( BIT(6) ) +#define BIT_PD_CP0_ARM9_0_CGM_HOLD_EN ( BIT(5) ) +#define BIT_PD_CA7_TOP_CMG_HOLD_EN ( BIT(4) ) +#define BIT_PD_CA7_C3_CMG_HOLD_EN ( BIT(3) ) +#define BIT_PD_CA7_C2_CMG_HOLD_EN ( BIT(2) ) +#define BIT_PD_CA7_C1_CMG_HOLD_EN ( BIT(1) ) +#define BIT_PD_CA7_C0_CMG_HOLD_EN ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_PWR_CNT_WAIT_CFG0 */ +#define BITS_VCP0_PWR_WAIT_CNT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_CP1_PWR_WAIT_CNT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_CP0_PWR_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_AP_PWR_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PWR_CNT_WAIT_CFG1 */ +#define BITS_ARM7_PWR_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_VCP1_PWR_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_RC0_REL_CFG */ +#define BIT_RC0_ARM7_SEL ( BIT(5) ) +#define BIT_RC0_VCP1_SEL ( BIT(4) ) +#define BIT_RC0_VCP0_SEL ( BIT(3) ) +#define BIT_RC0_CP1_SEL ( BIT(2) ) +#define BIT_RC0_CP0_SEL ( BIT(1) ) +#define BIT_RC0_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_RC1_REL_CFG */ +#define BIT_RC1_ARM7_SEL ( BIT(5) ) +#define BIT_RC1_VCP1_SEL ( BIT(4) ) +#define BIT_RC1_VCP0_SEL ( BIT(3) ) +#define BIT_RC1_CP1_SEL ( BIT(2) ) +#define BIT_RC1_CP0_SEL ( BIT(1) ) +#define BIT_RC1_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_RC_CNT_WAIT_CFG */ +#define BITS_RC1_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_RC0_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_MEM_AUTO_SLP_CFG */ +#define BITS_MEM_AUTO_SLP_EN(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_MEM_AUTO_SD_CFG */ +#define BITS_MEM_AUTO_SD_EN(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CP0_PD_SHUTDOWN_CFG */ +#define BIT_PD_CP0_HU3GE_VCP1_SEL ( BIT(20) ) +#define BIT_PD_CP0_TD_VCP1_SEL ( BIT(19) ) +#define BIT_PD_CP0_GSM_0_VCP1_SEL ( BIT(18) ) +#define BIT_PD_CP0_CEVA_0_VCP1_SEL ( BIT(17) ) +#define BIT_PD_CP0_ARM9_1_VCP1_SEL ( BIT(16) ) +#define BIT_PD_CP0_ARM9_0_VCP0_SEL ( BIT(8) ) +#define BIT_PD_CP0_HU3GE_CP0_SEL ( BIT(5) ) +#define BIT_PD_CP0_TD_CP0_SEL ( BIT(4) ) +#define BIT_PD_CP0_GSM_0_CP0_SEL ( BIT(3) ) +#define BIT_PD_CP0_CEVA_0_CP0_SEL ( BIT(2) ) +#define BIT_PD_CP0_ARM9_1_CP0_SEL ( BIT(1) ) +#define BIT_PD_CP0_ARM9_0_CP0_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CP1_PD_SHUTDOWN_CFG */ +#define BIT_PD_CP1_COMWRAP_VCP1_SEL ( BIT(20) ) +#define BIT_PD_CP1_CEVA_VCP1_SEL ( BIT(19) ) +#define BIT_PD_CP1_LTE_P2_VCP1_SEL ( BIT(18) ) +#define BIT_PD_CP1_LTE_P1_VCP1_SEL ( BIT(17) ) +#define BIT_PD_CP1_CA5_VCP1_SEL ( BIT(16) ) +#define BIT_PD_CP1_COMWRAP_CP1_SEL ( BIT(4) ) +#define BIT_PD_CP1_CEVA_CP1_SEL ( BIT(3) ) +#define BIT_PD_CP1_LTE_P2_CP1_SEL ( BIT(2) ) +#define BIT_PD_CP1_LTE_P1_CP1_SEL ( BIT(1) ) +#define BIT_PD_CP1_CA5_CP1_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_WAKEUP_LOCK_EN */ +#define BIT_VCP1_SYS_WAKEUP_LOCK_EN ( BIT(26) ) +#define BIT_VCP0_SYS_WAKEUP_LOCK_EN ( BIT(25) ) +#define BIT_CP1_SYS_WAKEUP_LOCK_EN ( BIT(24) ) +#define BIT_CP0_SYS_WAKEUP_LOCK_EN ( BIT(23) ) +#define BIT_AP_SYS_WAKEUP_LOCK_EN ( BIT(22) ) +#define BIT_PD_PUB_SYS_WAKEUP_LOCK_EN ( BIT(21) ) +#define BIT_PD_CP1_COMWRAP_WAKEUP_LOCK_EN ( BIT(20) ) +#define BIT_PD_CP1_CEVA_WAKEUP_LOCK_EN ( BIT(19) ) +#define BIT_PD_CP1_LTE_P2_WAKEUP_LOCK_EN ( BIT(18) ) +#define BIT_PD_CP1_LTE_P1_WAKEUP_LOCK_EN ( BIT(17) ) +#define BIT_PD_CP1_CA5_WAKEUP_LOCK_EN ( BIT(16) ) +#define BIT_PD_CP0_CEVA_1_WAKEUP_LOCK_EN ( BIT(15) ) +#define BIT_PD_CP0_CEVA_0_WAKEUP_LOCK_EN ( BIT(14) ) +#define BIT_PD_CP0_TD_WAKEUP_LOCK_EN ( BIT(13) ) +#define BIT_PD_CP0_GSM_1_WAKEUP_LOCK_EN ( BIT(12) ) +#define BIT_PD_CP0_GSM_0_WAKEUP_LOCK_EN ( BIT(11) ) +#define BIT_PD_CP0_HU3GE_WAKEUP_LOCK_EN ( BIT(10) ) +#define BIT_PD_CP0_ARM9_1_WAKEUP_LOCK_EN ( BIT(9) ) +#define BIT_PD_CP0_ARM9_0_WAKEUP_LOCK_EN ( BIT(8) ) +#define BIT_PD_MM_TOP_WAKEUP_LOCK_EN ( BIT(7) ) +#define BIT_PD_GPU_TOP_WAKEUP_LOCK_EN ( BIT(6) ) +#define BIT_PD_AP_SYS_WAKEUP_LOCK_EN ( BIT(5) ) +#define BIT_PD_CA7_TOP_WAKEUP_LOCK_EN ( BIT(4) ) +#define BIT_PD_CA7_C3_WAKEUP_LOCK_EN ( BIT(3) ) +#define BIT_PD_CA7_C2_WAKEUP_LOCK_EN ( BIT(2) ) +#define BIT_PD_CA7_C1_WAKEUP_LOCK_EN ( BIT(1) ) +#define BIT_PD_CA7_C0_WAKEUP_LOCK_EN ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_PD_CODEC_TOP_CFG */ +#define BIT_PD_CODEC_TOP_FORCE_SHUTDOWN (BIT(25)) +#define BIT_PD_CODEC_TOP_AUTO_SHUTDOWN_EN (BIT(24)) +#define BITS_PD_CODEC_TOP_PWR_ON_DLY(_X_) ((_X_) & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23))) +#define BITS_PD_CODEC_TOP_PWR_ON_SEQ_DLY(_X_) ((_X_) & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15))) +#define BITS_PD_CODEC_TOP_ISO_ON_DLY(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7))) + +/* bits definitions for register REG_PMU_APB_PD_CA7_C0_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CA7_C0_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA7_C1_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CA7_C1_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA7_C2_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CA7_C2_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA7_C3_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CA7_C3_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA7_TOP_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CA7_TOP_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_AP_SYS_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_AP_SYS_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_GPU_TOP_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_GPU_TOP_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_MM_TOP_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_MM_TOP_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_0_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_ARM9_0_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_1_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_ARM9_1_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_CEVA_0_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_CEVA_0_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_CEVA_1_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_CEVA_1_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_GSM_0_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_GSM_0_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_GSM_1_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_GSM_1_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_TD_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_TD_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_HU3GE_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_HU3GE_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_CA5_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP1_CA5_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_CEVA_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP1_CEVA_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_LTE_P1_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP1_LTE_P1_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_LTE_P2_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP1_LTE_P2_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_COMWRAP_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP1_COMWRAP_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_PUB_SYS_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_PUB_SYS_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +#if defined(CONFIG_MACH_SP9830I) +/* bits definitions for register REG_PMU_APB_PD_CODEC_TOP_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CODEC_TOP_SHUTDOWN_MARK(_X_) ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3))) +#endif + +#endif diff --git a/include/soc/sprd/chip_x35l/__regs_pub_apb.h b/include/soc/sprd/chip_x35l/__regs_pub_apb.h new file mode 100644 index 00000000..3f0109f2 --- /dev/null +++ b/include/soc/sprd/chip_x35l/__regs_pub_apb.h @@ -0,0 +1,477 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_PUB_APB_HEADFILE_H__ +#define __H_REGS_PUB_APB_HEADFILE_H__ __FILE__ + +#define REGS_PUB_APB + +/* registers definitions for PUB_APB */ +#define REG_PUB_APB_BUSMON_CNT_START SCI_ADDR(REGS_PUB_APB_BASE, 0x0000) +#define REG_PUB_APB_BUSMON_CFG SCI_ADDR(REGS_PUB_APB_BASE, 0x0004) +#define REG_PUB_APB_DDR_EB SCI_ADDR(REGS_PUB_APB_BASE, 0x0008) +#define REG_PUB_APB_DDR_SOFT_RST SCI_ADDR(REGS_PUB_APB_BASE, 0x000C) +#define REG_PUB_APB_DDR_QOS_CFG1 SCI_ADDR(REGS_PUB_APB_BASE, 0x0010) +#define REG_PUB_APB_DDR_QOS_CFG2 SCI_ADDR(REGS_PUB_APB_BASE, 0x0014) +#define REG_PUB_APB_DDR_QOS_CFG3 SCI_ADDR(REGS_PUB_APB_BASE, 0x0018) +#define REG_PUB_APB_DDR_MRR_STATUS SCI_ADDR(REGS_PUB_APB_BASE, 0x001C) +#define REG_PUB_APB_DDR_ID2QOS_SEL SCI_ADDR(REGS_PUB_APB_BASE, 0x003C) +#define REG_PUB_APB_DDR_ID2QOS_RCFG0 SCI_ADDR(REGS_PUB_APB_BASE, 0x0040) +#define REG_PUB_APB_DDR_ID2QOS_RCFG1 SCI_ADDR(REGS_PUB_APB_BASE, 0x0044) +#define REG_PUB_APB_DDR_ID2QOS_RCFG2 SCI_ADDR(REGS_PUB_APB_BASE, 0x0048) +#define REG_PUB_APB_DDR_ID2QOS_RCFG3 SCI_ADDR(REGS_PUB_APB_BASE, 0x004c) +#define REG_PUB_APB_DDR_ID2QOS_RCFG4 SCI_ADDR(REGS_PUB_APB_BASE, 0x0050) +#define REG_PUB_APB_DDR_ID2QOS_RCFG5 SCI_ADDR(REGS_PUB_APB_BASE, 0x0054) +#define REG_PUB_APB_DDR_ID2QOS_RCFG6 SCI_ADDR(REGS_PUB_APB_BASE, 0x0058) +#define REG_PUB_APB_DDR_ID2QOS_RCFG7 SCI_ADDR(REGS_PUB_APB_BASE, 0x005c) +#define REG_PUB_APB_DDR_ID2QOS_RCFG8 SCI_ADDR(REGS_PUB_APB_BASE, 0x0060) +#define REG_PUB_APB_DDR_ID2QOS_RCFG9 SCI_ADDR(REGS_PUB_APB_BASE, 0x0064) +#define REG_PUB_APB_DDR_ID2QOS_WCFG0 SCI_ADDR(REGS_PUB_APB_BASE, 0x0080) +#define REG_PUB_APB_DDR_ID2QOS_WCFG1 SCI_ADDR(REGS_PUB_APB_BASE, 0x0084) +#define REG_PUB_APB_DDR_ID2QOS_WCFG2 SCI_ADDR(REGS_PUB_APB_BASE, 0x0088) +#define REG_PUB_APB_DDR_ID2QOS_WCFG3 SCI_ADDR(REGS_PUB_APB_BASE, 0x008c) +#define REG_PUB_APB_DDR_ID2QOS_WCFG4 SCI_ADDR(REGS_PUB_APB_BASE, 0x0090) +#define REG_PUB_APB_DDR_ID2QOS_WCFG5 SCI_ADDR(REGS_PUB_APB_BASE, 0x0094) +#define REG_PUB_APB_DDR_ID2QOS_WCFG6 SCI_ADDR(REGS_PUB_APB_BASE, 0x0098) +#define REG_PUB_APB_DDR_ID2QOS_WCFG7 SCI_ADDR(REGS_PUB_APB_BASE, 0x009c) +#define REG_PUB_APB_DDR_ID2QOS_WCFG8 SCI_ADDR(REGS_PUB_APB_BASE, 0x00a0) +#define REG_PUB_APB_DDR_ID2QOS_WCFG9 SCI_ADDR(REGS_PUB_APB_BASE, 0x00a4) +#define REG_PUB_APB_DFI_TIMEOUT_CFG SCI_ADDR(REGS_PUB_APB_BASE, 0x0100) +#define REG_PUB_APB_DFI_TIMEOUT_STATUS SCI_ADDR(REGS_PUB_APB_BASE, 0x0104) +#define REG_PUB_APB_DFI_TIMEOUT_EN_CNT SCI_ADDR(REGS_PUB_APB_BASE, 0x0108) +#define REG_PUB_APB_DFI_TIMEOUT_VALID_CNT SCI_ADDR(REGS_PUB_APB_BASE, 0x010c) +#define REG_PUB_APB_DMC_PORT_REMAP_EN SCI_ADDR(REGS_PUB_APB_BASE, 0x3000) +#define REG_PUB_APB_DMC_PORTS_MPU_EN SCI_ADDR(REGS_PUB_APB_BASE, 0x3004) +#define REG_PUB_APB_DMC_PORT0_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3008) +#define REG_PUB_APB_DMC_PORT1_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x300C) +#define REG_PUB_APB_DMC_PORT2_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3010) +#define REG_PUB_APB_DMC_PORT3_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3014) +#define REG_PUB_APB_DMC_PORT4_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3018) +#define REG_PUB_APB_DMC_PORT5_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x301C) +#define REG_PUB_APB_DMC_PORT6_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3020) +#define REG_PUB_APB_DMC_PORT7_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3024) +#define REG_PUB_APB_DMC_PORT8_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3028) +#define REG_PUB_APB_DMC_PORT9_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x302C) +#define REG_PUB_APB_DMC_PORT0_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3030) +#define REG_PUB_APB_DMC_PORT1_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3034) +#define REG_PUB_APB_DMC_PORT2_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3038) +#define REG_PUB_APB_DMC_PORT3_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x303C) +#define REG_PUB_APB_DMC_PORT4_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3040) +#define REG_PUB_APB_DMC_PORT5_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3044) +#define REG_PUB_APB_DMC_PORT6_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3048) +#define REG_PUB_APB_DMC_PORT7_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3050) +#define REG_PUB_APB_DMC_PORT8_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3054) +#define REG_PUB_APB_DMC_PORT9_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3058) +#define REG_PUB_APB_DMC_PORT0_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x305C) +#define REG_PUB_APB_DMC_PORT1_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3060) +#define REG_PUB_APB_DMC_PORT2_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3064) +#define REG_PUB_APB_DMC_PORT3_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3068) +#define REG_PUB_APB_DMC_PORT4_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x306C) +#define REG_PUB_APB_DMC_PORT5_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3070) +#define REG_PUB_APB_DMC_PORT6_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3074) +#define REG_PUB_APB_DMC_PORT7_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3078) +#define REG_PUB_APB_DMC_PORT8_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x307C) +#define REG_PUB_APB_DMC_PORT9_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3080) + + + +/* bits definitions for register REG_PUB_APB_BUSMON_CNT_START */ +#define BIT_PUB_BUSMON_CNT_START ( BIT(0) ) + +/* bits definitions for register REG_PUB_APB_BUSMON_CFG */ +#define BIT_PUB_BUSMON9_EB ( BIT(25) ) +#define BIT_PUB_BUSMON8_EB ( BIT(24) ) +#define BIT_PUB_BUSMON7_EB ( BIT(23) ) +#define BIT_PUB_BUSMON6_EB ( BIT(22) ) +#define BIT_PUB_BUSMON5_EB ( BIT(21) ) +#define BIT_PUB_BUSMON4_EB ( BIT(20) ) +#define BIT_PUB_BUSMON3_EB ( BIT(19) ) +#define BIT_PUB_BUSMON2_EB ( BIT(18) ) +#define BIT_PUB_BUSMON1_EB ( BIT(17) ) +#define BIT_PUB_BUSMON0_EB ( BIT(16) ) +#define BIT_PUB_BUSMON9_SOFT_RST ( BIT(9) ) +#define BIT_PUB_BUSMON8_SOFT_RST ( BIT(8) ) +#define BIT_PUB_BUSMON7_SOFT_RST ( BIT(7) ) +#define BIT_PUB_BUSMON6_SOFT_RST ( BIT(6) ) +#define BIT_PUB_BUSMON5_SOFT_RST ( BIT(5) ) +#define BIT_PUB_BUSMON4_SOFT_RST ( BIT(4) ) +#define BIT_PUB_BUSMON3_SOFT_RST ( BIT(3) ) +#define BIT_PUB_BUSMON2_SOFT_RST ( BIT(2) ) +#define BIT_PUB_BUSMON1_SOFT_RST ( BIT(1) ) +#define BIT_PUB_BUSMON0_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_PUB_APB_DDR_EB */ + +/* bits definitions for register REG_PUB_APB_DDR_SOFT_RST */ + +/* bits definitions for register REG_PUB_APB_DDR_QOS_CFG1 */ +#define BITS_DMC_ARQOS_3(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_3(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_2(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_2(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_1(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_0(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_QOS_CFG2 */ +#define BITS_DMC_ARQOS_7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_7(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_6(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_6(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_5(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_5(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_4(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_QOS_CFG3 */ +#define BITS_DMC_ARQOS_9(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_9(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_8(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_8(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_MRR_STATUS */ +#define BIT_DDRC_CO_RD_MRR_DATA_VALID ( BIT(8) ) +#define BITS_DDRC_CO_RD_MRR_DATA(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_SEL */ +#define BITS_DMC_ID_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DMC_QOS_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG0 */ +#define BITS_DMC_ARQOS_0_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_0_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_0_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_0_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_0_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_0_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_0_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_0_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG1 */ +#define BITS_DMC_ARQOS_1_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_1_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_1_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_1_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_1_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_1_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_1_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_1_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG2 */ +#define BITS_DMC_ARQOS_2_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_2_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_2_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_2_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_2_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_2_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_2_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_2_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG3 */ +#define BITS_DMC_ARQOS_3_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_3_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_3_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_3_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_3_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_3_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_3_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_3_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG4 */ +#define BITS_DMC_ARQOS_4_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_4_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_4_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_4_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_4_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_4_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_4_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_4_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG5 */ +#define BITS_DMC_ARQOS_5_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_5_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_5_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_5_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_5_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_5_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_5_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_5_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG6 */ +#define BITS_DMC_ARQOS_6_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_6_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_6_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_6_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_6_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_6_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_6_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_6_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG7 */ +#define BITS_DMC_ARQOS_7_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_7_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_7_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_7_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_7_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_7_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_7_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_7_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG8 */ +#define BITS_DMC_ARQOS_8_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_8_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_8_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_8_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_8_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_8_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_8_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_8_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG9 */ +#define BITS_DMC_ARQOS_9_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_9_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_9_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_9_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_9_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_9_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_9_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_9_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG0 */ +#define BITS_DMC_AWQOS_0_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_0_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_0_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_0_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_0_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_0_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_0_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_0_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG1 */ +#define BITS_DMC_AWQOS_1_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_1_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_1_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_1_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_1_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_1_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_1_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_1_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG2 */ +#define BITS_DMC_AWQOS_2_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_2_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_2_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_2_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_2_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_2_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_2_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_2_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG3 */ +#define BITS_DMC_AWQOS_3_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_3_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_3_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_3_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_3_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_3_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_3_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_3_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG4 */ +#define BITS_DMC_AWQOS_4_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_4_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_4_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_4_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_4_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_4_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_4_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_4_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG5 */ +#define BITS_DMC_AWQOS_5_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_5_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_5_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_5_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_5_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_5_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_5_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_5_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG6 */ +#define BITS_DMC_AWQOS_6_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_6_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_6_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_6_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_6_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_6_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_6_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_6_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG7 */ +#define BITS_DMC_AWQOS_7_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_7_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_7_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_7_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_7_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_7_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_7_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_7_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG8 */ +#define BITS_DMC_AWQOS_8_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_8_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_8_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_8_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_8_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_8_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_8_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_8_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG9 */ +#define BITS_DMC_AWQOS_9_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_9_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_9_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_9_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_9_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_9_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_9_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_9_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DFI_TIMEOUT_CFG */ +#define BITS_DFI_TIMEOUT_THRESHOLD(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DFI_TIMEOUT_CLR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DFI_TIMEOUT_EN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DFI_TIMEOUT_STATUS */ +#define BITS_DFI_TIMEOUT_STATUS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DFI_TIMEOUT_EN_CNT */ +#define BITS_DFI_TIMEOUT_EN3_CNT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DFI_TIMEOUT_EN2_CNT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DFI_TIMEOUT_EN1_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DFI_TIMEOUT_EN0_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PUB_APB_DFI_TIMEOUT_VALID_CNT */ +#define BITS_DFI_TIMEOUT_VALID3_CNT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DFI_TIMEOUT_VALID2_CNT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DFI_TIMEOUT_VALID1_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DFI_TIMEOUT_VALID0_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PUB_APB_DMC_PORT_REMAP_EN */ +#define BITS_DMC_PORTS_REMAP_EN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_PUB_APB_DMC_PORTS_MPU_EN */ +#define BITS_DMC_PORTS_MPU_EN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_PUB_APB_DMC_PORT0_ADDR_REMAP */ +#define BITS_DMC_PORT0_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT1_ADDR_REMAP */ +#define BITS_DMC_PORT1_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT2_ADDR_REMAP */ +#define BITS_DMC_PORT2_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT3_ADDR_REMAP */ +#define BITS_DMC_PORT3_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT4_ADDR_REMAP */ +#define BITS_DMC_PORT4_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT5_ADDR_REMAP */ +#define BITS_DMC_PORT5_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT6_ADDR_REMAP */ +#define BITS_DMC_PORT6_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT7_ADDR_REMAP */ +#define BITS_DMC_PORT7_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT8_ADDR_REMAP */ +#define BITS_DMC_PORT8_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT9_ADDR_REMAP */ +#define BITS_DMC_PORT9_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT0_MPU_RANGE */ +#define BITS_DMC_PORT0_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT1_MPU_RANGE */ +#define BITS_DMC_PORT1_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT2_MPU_RANGE */ +#define BITS_DMC_PORT2_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT3_MPU_RANGE */ +#define BITS_DMC_PORT3_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT4_MPU_RANGE */ +#define BITS_DMC_PORT4_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT5_MPU_RANGE */ +#define BITS_DMC_PORT5_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT6_MPU_RANGE */ +#define BITS_DMC_PORT6_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT7_MPU_RANGE */ +#define BITS_DMC_PORT7_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT8_MPU_RANGE */ +#define BITS_DMC_PORT8_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT9_MPU_RANGE */ +#define BITS_DMC_PORT9_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT0_DUMP_ADDR */ +#define BITS_DMC_PORT0_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT1_DUMP_ADDR */ +#define BITS_DMC_PORT1_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT2_DUMP_ADDR */ +#define BITS_DMC_PORT2_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT3_DUMP_ADDR */ +#define BITS_DMC_PORT3_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT4_DUMP_ADDR */ +#define BITS_DMC_PORT4_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT5_DUMP_ADDR */ +#define BITS_DMC_PORT5_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT6_DUMP_ADDR */ +#define BITS_DMC_PORT6_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT7_DUMP_ADDR */ +#define BITS_DMC_PORT7_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT8_DUMP_ADDR */ +#define BITS_DMC_PORT8_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT9_DUMP_ADDR */ +#define BITS_DMC_PORT9_DUMP_ADDR(_X_) (_X_) + +#endif diff --git a/include/soc/sprd/chip_x35l/__regs_wcdma_ahb_rf.h b/include/soc/sprd/chip_x35l/__regs_wcdma_ahb_rf.h new file mode 100644 index 00000000..32d5cbb9 --- /dev/null +++ b/include/soc/sprd/chip_x35l/__regs_wcdma_ahb_rf.h @@ -0,0 +1,123 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_WCDMA_AHB_RF_HEADFILE_H__ +#define __H_REGS_WCDMA_AHB_RF_HEADFILE_H__ __FILE__ + +#define REGS_WCDMA_AHB_RF + +/* registers definitions for WCDMA_AHB_RF */ +#define REG_WCDMA_AHB_RF_AHB_EB0 SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0000) +#define REG_WCDMA_AHB_RF_AHB_RST0 SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0004) +#define REG_WCDMA_AHB_RF_ARCH_EB_REG SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0018) +#define REG_WCDMA_AHB_RF_AHB_REMAP SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x001C) +#define REG_WCDMA_AHB_RF_AHB_MISC_CTL SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0020) +#define REG_WCDMA_AHB_RF_AHB_MTX_PRI_SEL0 SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0024) +#define REG_WCDMA_AHB_RF_AHB_MTX_PRI_SEL1 SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0028) +#define REG_WCDMA_AHB_RF_AHB1_PAUSE SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x002C) +#define REG_WCDMA_AHB_RF_AHB_SLP_CTL SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0034) +#define REG_WCDMA_AHB_RF_AHB2_SLP_STS SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0038) +#define REG_WCDMA_AHB_RF_MCU_CLK_CTL SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x003C) +#define REG_WCDMA_AHB_RF_CHIP_ID SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x01FC) + + + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB_EB0 */ +#define BITS_WCDMA_EN(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BIT_BUSMON0_EN ( BIT(1) ) +#define BIT_SPINLOCK_EN ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB_RST0 */ +#define BIT_WCDMA_SOFT_RST ( BIT(3) ) +#define BIT_BUSMON0_SOFT_RST ( BIT(1) ) +#define BIT_SPINLOCK_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_ARCH_EB_REG */ +#define BIT_AHB_ARCH_EB ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB_REMAP */ +#define BIT_ARM_JTAG_EN_ARM1 ( BIT(1) ) +#define BIT_REMAP ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB_MISC_CTL */ +#define BIT_FORCE_WSYS_ACC_STOP ( BIT(3) ) +#define BIT_W_DMA_LSLP_EN ( BIT(2) ) +#define BIT_BUSMON0_SEL ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB_MTX_PRI_SEL0 */ +#define BITS_ARMMTX_M3TOS0_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ARMMTX_M3TOS0_ADJ_EN ( BIT(27) ) +#define BIT_ARMMTX_M3TOS0_RND_EN ( BIT(26) ) +#define BITS_ARMMTX_M3TOS0_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_ARMMTX_M2TOS0_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M2TOS0_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M2TOS0_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M2TOS0_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M1TOS0_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M1TOS0_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M1TOS0_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M1TOS0_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M0TOS0_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M0TOS0_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M0TOS0_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M0TOS0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB_MTX_PRI_SEL1 */ +#define BITS_ARMMTX_M6TOS0_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M6TOS0_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M6TOS0_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M6TOS0_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M5TOS0_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M5TOS0_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M5TOS0_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M5TOS0_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M4TOS0_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M4TOS0_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M4TOS0_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M4TOS0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB1_PAUSE */ +#define BIT_APB1_SLEEP ( BIT(3) ) +#define BIT_MCU1_DEEP_SLEEP_EN ( BIT(2) ) +#define BIT_MCU1_SYS_SLEEP_EN ( BIT(1) ) +#define BIT_MCU1_CORE_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB_SLP_CTL */ +#define BIT_MCUMTX_AUTO_GATE_EN ( BIT(4) ) +#define BIT_MCU_AUTO_GATE_EN ( BIT(3) ) +#define BIT_AHB_AUTO_GATE_EN ( BIT(2) ) +#define BIT_ARM1_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB2_SLP_STS */ +#define BIT_APB1_PERI_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_MCU_CLK_CTL */ +#define BITS_CLK_AHB_DIV(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_CLK_MCU_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_APB_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CLK_MCU_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_CHIP_ID */ +#define BITS_CHIP_ID(_X_) (_X_) + +#endif diff --git a/include/soc/sprd/chip_x35l/__regs_wcdma_apb_rf.h b/include/soc/sprd/chip_x35l/__regs_wcdma_apb_rf.h new file mode 100644 index 00000000..a5a57b74 --- /dev/null +++ b/include/soc/sprd/chip_x35l/__regs_wcdma_apb_rf.h @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_WCDMA_APB_RF_HEADFILE_H__ +#define __H_REGS_WCDMA_APB_RF_HEADFILE_H__ __FILE__ + +#define REGS_WCDMA_APB_RF + +/* registers definitions for WCDMA_APB_RF */ +#define REG_WCDMA_APB_RF_APB_EB SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0000) +#define REG_WCDMA_APB_RF_APB_RST SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0004) +#define REG_WCDMA_APB_RF_APB_SLEEP_ST SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0008) +#define REG_WCDMA_APB_RF_APB_MCU_RST SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0018) +#define REG_WCDMA_APB_RF_APB_CLK_SEL0 SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x001C) +#define REG_WCDMA_APB_RF_APB_CLK_DIV0 SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0020) +#define REG_WCDMA_APB_RF_APB_ARCH_EB SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0024) +#define REG_WCDMA_APB_RF_APB_SLP_CTL SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0028) + + + +/* bits definitions for register REG_WCDMA_APB_RF_APB_EB */ +#define BIT_TMR_RTC_EB ( BIT(6) ) +#define BIT_TMR_EB ( BIT(5) ) +#define BIT_SYSTMR_RTC_EB ( BIT(4) ) +#define BIT_SYSTMR_EB ( BIT(3) ) +#define BIT_UART0_EB ( BIT(2) ) +#define BIT_WDG_RTC_EB ( BIT(1) ) +#define BIT_WDG_EB ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_APB_RF_APB_RST */ +#define BIT_TMR_SOFT_RST ( BIT(3) ) +#define BIT_SYSTMR_SOFT_RST ( BIT(2) ) +#define BIT_UART0_SOFT_RST ( BIT(1) ) +#define BIT_WDG_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_APB_RF_APB_SLEEP_ST */ +#define BIT_CHIP_SLEEP_REC_CLR ( BIT(1) ) +#define BIT_CHIP_SLEEP_REC ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_APB_RF_APB_MCU_RST */ +#define BIT_MCU_SOFT_RST_SET ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_APB_RF_APB_CLK_SEL0 */ +#define BITS_CLK_UART0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_WCDMA_APB_RF_APB_CLK_DIV0 */ +#define BITS_CLK_UART0_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_WCDMA_APB_RF_APB_ARCH_EB */ +#define BIT_RTC_ARCH_EB ( BIT(1) ) +#define BIT_APB_ARCH_EB ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_APB_RF_APB_SLP_CTL */ +#define BIT_APB_PERI_FRC_ON ( BIT(1) ) +#define BIT_APB_PERI_FRC_SLP ( BIT(0) ) + +#endif diff --git a/include/soc/sprd/chip_x35l/__sc2723_regulator_map.h b/include/soc/sprd/chip_x35l/__sc2723_regulator_map.h new file mode 100644 index 00000000..7879ec63 --- /dev/null +++ b/include/soc/sprd/chip_x35l/__sc2723_regulator_map.h @@ -0,0 +1,128 @@ +/* + * Copyright (C) 2013 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +/* + * Regulator (0)Name, Regulator (1)Type, Power Off (2)Ctrl and (3)Bit, PWR_SEL (4) and (5) Bit, + * Voltage Trimming (6)Ctrl and (7)Bits, Calibration (8)Ctrl and (9)Bits, + * Voltage (10)Default, Voltage (11)Ctrl and (12)Bits, Voltage Select (13)Count and Voltage (14)List[ ... ...] + */ + + SCI_REGU_REG(vddcore, 0x12, ANA_REG_GLB_LDO_DCDC_PD, BIT(9), ANA_REG_GLB_PWR_SEL, BIT(0), + ANA_REG_GLB_DCDC_CORE_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_DCDC_CTRL15, BIT(14)|BIT(16)|BIT(18)|BIT(19), + 900, ANA_REG_GLB_DCDC_CORE_ADI, BIT(5)|BIT(6)|BIT(7), 8, 1100, 700, 800, 900, 1000, 650, 1200, 1300); + + SCI_REGU_REG(vddarm, 0x12, ANA_REG_GLB_LDO_DCDC_PD, BIT(10), ANA_REG_GLB_PWR_SEL, BIT(2), + ANA_REG_GLB_DCDC_ARM_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_DCDC_CTRL15, BIT(13)|BIT(16)|BIT(18)|BIT(19), + 900, ANA_REG_GLB_DCDC_ARM_ADI, BIT(5)|BIT(6)|BIT(7), 8, 1100, 700, 800, 900, 1000, 650, 1200, 1300); + + SCI_REGU_REG(vddmem, 0x12, ANA_REG_GLB_LDO_DCDC_PD, BIT(11), ANA_REG_GLB_PWR_SEL, BIT(3), + ANA_REG_GLB_DCDC_MEM_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_DCDC_CTRL15, BIT(13)|BIT(14)|BIT(16)|BIT(18)|BIT(19), + 1200, 0, 0, 2, 600, 3125); + + SCI_REGU_REG(vddgen, 0x12, ANA_REG_GLB_LDO_DCDC_PD, BIT(12), ANA_REG_GLB_PWR_SEL, BIT(4), + ANA_REG_GLB_DCDC_GEN_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_DCDC_CTRL15, BIT(15)|BIT(16)|BIT(18)|BIT(19), + 2400, 0, 0, 2, 600, 3125); + + SCI_REGU_REG(vddrf, 0x12, ANA_REG_GLB_LDO_DCDC_PD, BIT(13), ANA_REG_GLB_PWR_SEL, BIT(5), + ANA_REG_GLB_DCDC_RF_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_DCDC_CTRL15, BIT(13)|BIT(15)|BIT(16)|BIT(18)|BIT(19), + 1500, 0, 0, 2, 600, 3125); + + SCI_REGU_REG(vddcon, 0x2, ANA_REG_GLB_LDO_PD_CTRL, BIT(13), 0, 0, + ANA_REG_GLB_DCDC_CON_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_DCDC_CTRL15, BIT(14)|BIT(15)|BIT(16)|BIT(18)|BIT(19), + 1600, 0, 0, 2, 600, 3125); + + SCI_REGU_REG(vddwpa, 0x2, ANA_REG_GLB_LDO_PD_CTRL, BIT(14), 0, 0, + ANA_REG_GLB_DCDC_WPA_ADI, BIT(0)|BIT(1)|BIT(2), ANA_REG_GLB_DCDC_CTRL15, BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(18)|BIT(19), + 0, 0, 0, 0); + + SCI_REGU_REG(vddrf0, 0x10, ANA_REG_GLB_LDO_DCDC_PD, BIT(8), ANA_REG_GLB_PWR_SEL, BIT(11), + ANA_REG_GLB_LDO_V_CTRL0, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), ANA_REG_GLB_LDO_V_CTRL11, BIT(2)|BIT(16)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1150, 6250); + + SCI_REGU_REG(vddemmccore, 0x10, ANA_REG_GLB_LDO_DCDC_PD, BIT(7), ANA_REG_GLB_PWR_SEL, BIT(7), + ANA_REG_GLB_LDO_V_CTRL7, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), ANA_REG_GLB_LDO_V_CTRL11, BIT(5)|BIT(6)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 3000, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddgen1, 0x10, ANA_REG_GLB_LDO_DCDC_PD, BIT(6), ANA_REG_GLB_PWR_SEL, BIT(12), + ANA_REG_GLB_LDO_V_CTRL3, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_V_CTRL11, BIT(0)|BIT(2)|BIT(16)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1150, 6250); + + SCI_REGU_REG(vddgen0, 0x10, ANA_REG_GLB_LDO_DCDC_PD, BIT(4), ANA_REG_GLB_PWR_SEL, BIT(13), + ANA_REG_GLB_LDO_V_CTRL2, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6), ANA_REG_GLB_LDO_V_CTRL11, BIT(1)|BIT(2)|BIT(16)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1150, 6250); + + SCI_REGU_REG(vdddcxo, 0x10, ANA_REG_GLB_LDO_DCDC_PD, BIT(5), ANA_REG_GLB_PWR_SEL, BIT(8), + ANA_REG_GLB_LDO_V_CTRL8, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), ANA_REG_GLB_LDO_V_CTRL11, BIT(7)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vdd25, 0x10, ANA_REG_GLB_LDO_DCDC_PD, BIT(3), ANA_REG_GLB_PWR_SEL, BIT(6), + ANA_REG_GLB_LDO_V_CTRL10, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_LDO_V_CTRL11, BIT(8)|BIT(17)|BIT(18)|BIT(20), + 2800, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vdd28, 0x10, ANA_REG_GLB_LDO_DCDC_PD, BIT(2), ANA_REG_GLB_PWR_SEL, BIT(9), + ANA_REG_GLB_LDO_V_CTRL3, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_LDO_V_CTRL11, BIT(6)|BIT(7)|BIT(10)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 2800, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vdd18, 0x10, ANA_REG_GLB_LDO_DCDC_PD, BIT(1), ANA_REG_GLB_PWR_SEL, BIT(10), + ANA_REG_GLB_LDO_V_CTRL9, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_V_CTRL11, BIT(0)|BIT(16)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1150, 6250); + + SCI_REGU_REG(vddwifipa, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(11), 0, 0, + ANA_REG_GLB_LDO_V_CTRL0, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_LDO_V_CTRL11, BIT(5)|BIT(10)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 3300, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddsdcore, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(10), 0, 0, + ANA_REG_GLB_LDO_V_CTRL6, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), ANA_REG_GLB_LDO_V_CTRL11, BIT(5)|BIT(7)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 3000, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddsdio, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(0), 0, 0, + ANA_REG_GLB_LDO_V_CTRL4, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_LDO_V_CTRL11, BIT(3)|BIT(16)|BIT(18)|BIT(19)|BIT(20), + 3000, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddsim0, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(1), 0, 0, + ANA_REG_GLB_LDO_V_CTRL4, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), ANA_REG_GLB_LDO_V_CTRL11, BIT(8)|BIT(10)|BIT(17)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddsim1, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(2), 0, 0, + ANA_REG_GLB_LDO_V_CTRL5, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_LDO_V_CTRL11, BIT(10)|BIT(17)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddsim2, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(3), 0, 0, + ANA_REG_GLB_LDO_V_CTRL5, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), ANA_REG_GLB_LDO_V_CTRL11, BIT(8)|BIT(9)|BIT(17)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddcama, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(4), 0, 0, + ANA_REG_GLB_LDO_V_CTRL6, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_LDO_V_CTRL11, BIT(9)|BIT(17)|BIT(18)|BIT(20), + 2800, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddcamd, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(5), 0, 0, + ANA_REG_GLB_LDO_V_CTRL1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6), ANA_REG_GLB_LDO_V_CTRL11, BIT(1)|BIT(16)|BIT(18)|BIT(20), + 1500, 0, 0, 2, 1150, 6250); + + SCI_REGU_REG(vddcamio, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(6), 0, 0, + ANA_REG_GLB_LDO_V_CTRL1, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_V_CTRL11, BIT(0)|BIT(1)|BIT(16)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1150, 6250); + + SCI_REGU_REG(vddcammot, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(7), 0, 0, + ANA_REG_GLB_LDO_V_CTRL7, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_LDO_V_CTRL11, BIT(6)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 2800, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddusb, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(8), 0, 0, + ANA_REG_GLB_LDO_V_CTRL9, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_LDO_V_CTRL11, BIT(4)|BIT(16)|BIT(18)|BIT(19)|BIT(20), + 3300, 0, 0, 2, 1200, 10000); + diff --git a/include/soc/sprd/chip_x35l/__scx35l_clock_tree.h b/include/soc/sprd/chip_x35l/__scx35l_clock_tree.h new file mode 100644 index 00000000..992ad053 --- /dev/null +++ b/include/soc/sprd/chip_x35l/__scx35l_clock_tree.h @@ -0,0 +1,557 @@ +/* + * Copyright (C) 2013 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#define REG_0X20E0(_o_) SCI_ADDR(SPRD_AHB_BASE, (_o_)) +#define REG_0X2150(_o_) SCI_ADDR(SPRD_APBCKG_BASE, (_o_)) +#define REG_0X402E(_o_) SCI_ADDR(SPRD_AONAPB_BASE, (_o_)) +#define REG_0X402D(_o_) SCI_ADDR(SPRD_AONCKG_BASE, (_o_)) +#define REG_0X6010(_o_) SCI_ADDR(SPRD_GPUAPB_BASE, (_o_)) +#define REG_0X60D0(_o_) SCI_ADDR(SPRD_MMAHB_BASE, (_o_)) +#define REG_0X60E0(_o_) SCI_ADDR(SPRD_MMCKG_BASE, (_o_)) +#define REG_0X7130(_o_) SCI_ADDR(SPRD_APBREG_BASE, (_o_)) + +#define REG_0X402E0044 REG_0X402E(0x0044) +#define REG_0X402E004C REG_0X402E(0x004C) +#define REG_0X402E005C REG_0X402E(0x005C) +#define REG_0X402E0054 REG_0X402E(0x0054) +#define REG_0X402E0064 REG_0X402E(0x0064) +#define REG_0X20E00038 REG_0X20E0(0x0038) +#define REG_0X20E00054 REG_0X20E0(0x0054) +#define REG_0X402D0020 REG_0X402D(0x0020) +#define REG_0X402D002C REG_0X402D(0x002C) +#define REG_0X402D0030 REG_0X402D(0x0030) +#define REG_0X402E0000 REG_0X402E(0x0000) +#define REG_0X402D0034 REG_0X402D(0x0034) +#define REG_0X402E0004 REG_0X402E(0x0004) +#define REG_0X402D0038 REG_0X402D(0x0038) +#define REG_0X402D003C REG_0X402D(0x003C) +#define REG_0X402D0040 REG_0X402D(0x0040) +#define REG_0X402D0044 REG_0X402D(0x0044) +#define REG_0X402D0048 REG_0X402D(0x0048) +#define REG_0X402D004C REG_0X402D(0x004C) +#define REG_0X402D0050 REG_0X402D(0x0050) +#define REG_0X402D0054 REG_0X402D(0x0054) +#define REG_0X402D0058 REG_0X402D(0x0058) +#define REG_0X402D0068 REG_0X402D(0x0068) +#define REG_0X402D006C REG_0X402D(0x006C) +#define REG_0X402D0070 REG_0X402D(0x0070) +#define REG_0X402D0074 REG_0X402D(0x0074) +#define REG_0X402D0078 REG_0X402D(0x0078) +#define REG_0X402D007C REG_0X402D(0x007C) +#define REG_0X402D0080 REG_0X402D(0x0080) +#define REG_0X402D0090 REG_0X402D(0x0090) +#define REG_0X402D0098 REG_0X402D(0x0098) +#define REG_0X402D00C8 REG_0X402D(0x00C8) +#define REG_0X402D00CC REG_0X402D(0x00CC) +#define REG_0X402D00D0 REG_0X402D(0x00D0) +#define REG_0X21500020 REG_0X2150(0x0020) +#define REG_0X21500024 REG_0X2150(0x0024) +#define REG_0X20E00000 REG_0X20E0(0x0000) +#define REG_0X21500028 REG_0X2150(0x0028) +#define REG_0X2150002C REG_0X2150(0x002C) +#define REG_0X21500030 REG_0X2150(0x0030) +#define REG_0X21500034 REG_0X2150(0x0034) +#define REG_0X21500054 REG_0X2150(0x0054) +#define REG_0X21500058 REG_0X2150(0x0058) +#define REG_0X2150005C REG_0X2150(0x005C) +#define REG_0X21500060 REG_0X2150(0x0060) +#define REG_0X21500068 REG_0X2150(0x0068) +#define REG_0X21500070 REG_0X2150(0x0070) +#define REG_0X21500074 REG_0X2150(0x0074) +#define REG_0X2150007C REG_0X2150(0x007C) +#define REG_0X71300000 REG_0X7130(0x0000) +#define REG_0X21500084 REG_0X2150(0x0084) +#define REG_0X21500088 REG_0X2150(0x0088) +#define REG_0X2150008C REG_0X2150(0x008C) +#define REG_0X21500090 REG_0X2150(0x0090) +#define REG_0X21500094 REG_0X2150(0x0094) +#define REG_0X21500098 REG_0X2150(0x0098) +#define REG_0X2150009C REG_0X2150(0x009C) +#define REG_0X215000A0 REG_0X2150(0x00A0) +#define REG_0X215000A4 REG_0X2150(0x00A4) +#define REG_0X215000A8 REG_0X2150(0x00A8) +#define REG_0X215000AC REG_0X2150(0x00AC) +#define REG_0X215000B0 REG_0X2150(0x00B0) +#define REG_0X215000B4 REG_0X2150(0x00B4) +#define REG_0X215000B8 REG_0X2150(0x00B8) +#define REG_0X215000BC REG_0X2150(0x00BC) +#define REG_0X215000C0 REG_0X2150(0x00C0) +#define REG_0X215000C4 REG_0X2150(0x00C4) +#define REG_0X215000C8 REG_0X2150(0x00C8) +#define REG_0X215000CC REG_0X2150(0x00CC) +#define REG_0X60100020 REG_0X6010(0x0020) +#define REG_0X60E00020 REG_0X60E0(0x0020) +#define REG_0X60D00008 REG_0X60D0(0x0008) +#define REG_0X60D00000 REG_0X60D0(0x0000) +#define REG_0X60E00038 REG_0X60E0(0x0038) +#define REG_0X60E00030 REG_0X60E0(0x0030) +#define REG_0X60E00034 REG_0X60E0(0x0034) +#define REG_0X60E00028 REG_0X60E0(0x0028) +#define REG_0X60E00024 REG_0X60E0(0x0024) +#define REG_0X60E0002C REG_0X60E0(0x002C) + +/* + * Clock (0)Name, Clock (1)fixed rate, Clock Enable (2)Ctrl and (3)Bit, + * Clock Divisor (4)Ctrl and (5)Bit, Clock Parent (6)Ctrl and (7)Bit, + * and Parent Select (15)Count and (16)Lists[ ... ...] + */ + +SCI_CLK_ADD(ext_26m, 26000000, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(ext_32k, 32768, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(ext_26m_rf1, 26000000, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(ext_1m, 1000000, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(ext_2m, 2000000, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(ext_4m, 4000000, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_pad, 64000000, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_mpll, 0, 0, 0, + REG_0X402E0044, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, 0); + +SCI_CLK_ADD(clk_dpll, 0, 0, 0, + REG_0X402E004C, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, 0); + +SCI_CLK_ADD(clk_ltepll, 0, 0, 0, + REG_0X402E005C, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, 0); + +SCI_CLK_ADD(clk_twpll, 0, 0, 0, + REG_0X402E0054, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, 0); + +SCI_CLK_ADD(clk_lvdspll, 0, 0, 0, + REG_0X402E0064, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, 0); + +SCI_CLK_ADD(clk_768m, 0, 0, 0, + 2, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_512m, 0, 0, 0, + 3, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_384m, 0, 0, 0, + 4, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_312m, 0, 0, 0, + 5, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_307m2, 0, 0, 0, + 5, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_256m, 0, 0, 0, + 6, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_192m, 0, 0, 0, + 8, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_153m6, 0, 0, 0, + 10, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_128m, 0, 0, 0, + 12, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_96m, 0, 0, 0, + 16, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_76m8, 0, 0, 0, + 20, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_64m, 0, 0, 0, + 24, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_51m2, 0, 0, 0, + 30, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_48m, 0, 0, 0, + 32, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_38m4, 0, 0, 0, + 40, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_24m, 0, 0, 0, + 64, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_12m, 0, 0, 0, + 128, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_42m_d, 0, 0, 0, + 32, 0, 0, 0, + 1, &clk_dpll); + +SCI_CLK_ADD(clk_56m_m, 0, 0, 0, + 32, 0, 0, 0, + 1, &clk_mpll); + +SCI_CLK_ADD(clk_38m4_lte, 0, 0, 0, + 32, 0, 0, 0, + 1, &clk_ltepll); + +SCI_CLK_ADD(clk_44m_lvds, 0, 0, 0, + 32, 0, 0, 0, + 1, &clk_lvdspll); + +SCI_CLK_ADD(clk_614m4, 0, 0, 0, + 2, 0, 0, 0, + 1, &clk_ltepll); + +SCI_CLK_ADD(clk_mcu, 0, 0, 0, + REG_0X20E00038, BIT(4)|BIT(5)|BIT(6), REG_0X20E00054, BIT(0)|BIT(1)|BIT(2), + 7, &ext_26m, &clk_512m, &clk_768m, &clk_dpll, &clk_ltepll, &clk_twpll, &clk_mpll); + +SCI_CLK_ADD(clk_ca7_core, 0, 0, 0, + 0, 0, 0, 0, + 1, &clk_mcu); + +SCI_CLK_ADD(clk_ca7_axi, 0, 0, 0, + REG_0X20E00038, BIT(8)|BIT(9)|BIT(10), 0, 0, + 1, &clk_mcu); + +SCI_CLK_ADD(clk_ca7_dbg, 0, 0, 0, + REG_0X20E00038, BIT(16)|BIT(17)|BIT(18), 0, 0, + 1, &clk_mcu); + +SCI_CLK_ADD(clk_emc_4x, 0, 0, 0, + REG_0X402D0020, BIT(8)|BIT(9), REG_0X402D0020, BIT(0)|BIT(1)|BIT(2), + 8, &ext_26m, &clk_192m, &clk_307m2, &clk_384m, &clk_512m, &clk_614m4, &clk_768m, &clk_dpll); + +SCI_CLK_ADD(clk_pub_ahb, 0, 0, 0, + REG_0X402D002C, BIT(8)|BIT(9), REG_0X402D002C, BIT(0)|BIT(1), + 4, &ext_26m, &ext_4m, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_aon_apb, 0, 0, 0, + REG_0X402D0030, BIT(8)|BIT(9), REG_0X402D0030, BIT(0)|BIT(1), + 4, &ext_4m, &ext_26m, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_adi, 0, REG_0X402E0000, BIT(16), + 0, 0, REG_0X402D0034, BIT(0)|BIT(1), + 4, &ext_26m, &ext_4m, &clk_38m4, &clk_51m2); + +SCI_CLK_ADD(clk_aux0, 0, REG_0X402E0004, BIT(2), + 0, 0, REG_0X402D0038, BIT(0)|BIT(1)|BIT(2), + 7, &ext_32k, &ext_26m, &ext_26m_rf1, &ext_4m, &clk_42m_d, &clk_48m, &clk_56m_m); + +SCI_CLK_ADD(clk_aux1, 0, REG_0X402E0004, BIT(3), + 0, 0, REG_0X402D003C, BIT(0)|BIT(1)|BIT(2)|BIT(3), + 9, &ext_32k, &ext_26m, &ext_26m_rf1, &ext_4m, &clk_42m_d, &clk_48m, &clk_56m_m, &clk_38m4_lte, &clk_44m_lvds); + +SCI_CLK_ADD(clk_aux2, 0, REG_0X402E0004, BIT(4), + 0, 0, REG_0X402D0040, BIT(0)|BIT(1)|BIT(2)|BIT(3), + 9, &ext_32k, &ext_26m, &ext_26m_rf1, &ext_4m, &clk_42m_d, &clk_48m, &clk_56m_m, &clk_38m4_lte, &clk_44m_lvds); + +SCI_CLK_ADD(clk_probe, 0, REG_0X402E0004, BIT(5), + 0, 0, REG_0X402D0044, BIT(0)|BIT(1)|BIT(2)|BIT(3), + 9, &ext_32k, &ext_26m, &ext_26m_rf1, &ext_4m, &clk_42m_d, &clk_48m, &clk_56m_m, &clk_38m4_lte, &clk_44m_lvds); + +SCI_CLK_ADD(clk_pwm0, 0, REG_0X402E0000, BIT(4), + 0, 0, REG_0X402D0048, BIT(0)|BIT(1), + 4, &ext_32k, &ext_26m, &ext_26m_rf1, &clk_48m); + +SCI_CLK_ADD(clk_pwm1, 0, REG_0X402E0000, BIT(5), + 0, 0, REG_0X402D004C, BIT(0)|BIT(1), + 4, &ext_32k, &ext_26m, &ext_26m_rf1, &clk_48m); + +SCI_CLK_ADD(clk_pwm2, 0, REG_0X402E0000, BIT(6), + 0, 0, REG_0X402D0050, BIT(0)|BIT(1), + 4, &ext_32k, &ext_26m, &ext_26m_rf1, &clk_48m); + +SCI_CLK_ADD(clk_pwm3, 0, REG_0X402E0000, BIT(7), + 0, 0, REG_0X402D0054, BIT(0)|BIT(1), + 4, &ext_32k, &ext_26m, &ext_26m_rf1, &clk_48m); + +SCI_CLK_ADD(clk_efuse, 0, REG_0X402E0000, BIT(13), + 0, 0, REG_0X402D0058, BIT(0), + 1, &ext_26m); + +SCI_CLK_ADD(clk_thm, 0, REG_0X402E0004, BIT(1), + 0, 0, REG_0X402D0068, BIT(0), + 2, &ext_32k, &ext_1m); + +SCI_CLK_ADD(clk_mspi, 0, REG_0X402E0000, BIT(23), + 0, 0, REG_0X402D006C, BIT(0), + 4, &ext_26m, &clk_51m2, &clk_76m8, &clk_96m); + +SCI_CLK_ADD(clk_i2c, 0, REG_0X402E0000, BIT(31), + 0, 0, REG_0X402D0070, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_avs, 0, REG_0X402E0004, BIT(6), + 0, 0, REG_0X402D0074, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_aud, 0, REG_0X402E0000, BIT(18), + 0, 0, REG_0X402D0078, BIT(0), + 1, &ext_26m); + +SCI_CLK_ADD(clk_audif, 0, REG_0X402E0000, BIT(17), + 0, 0, REG_0X402D007C, BIT(0)|BIT(1), + 3, &ext_26m, &clk_38m4, &clk_51m2); + +SCI_CLK_ADD(clk_vbc, 0, REG_0X402E0000, BIT(19), + 0, 0, REG_0X402D0080, BIT(0), + 1, &ext_26m); + +SCI_CLK_ADD(clk_ca7_dap, 0, REG_0X402E0000, BIT(30), + 0, 0, REG_0X402D0090, BIT(0)|BIT(1), + 4, &ext_26m, &clk_76m8, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_ca7_ts, 0, REG_0X402E0000, BIT(28), + 0, 0, REG_0X402D0098, BIT(0)|BIT(1), + 4, &ext_32k, &ext_26m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_djtag_tck, 0, 0, 0, + 0, 0, REG_0X402D00C8, BIT(0), + 3, &ext_26m, &ext_4m, &clk_pad); + +SCI_CLK_ADD(clk_arm7_ahb, 0, 0, 0, + REG_0X402D00CC, BIT(8)|BIT(9), REG_0X402D00CC, BIT(0)|BIT(1), + 4, &ext_4m, &ext_26m, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_ca5_ts, 0, REG_0X402E0004, BIT(26), + 0, 0, REG_0X402D00D0, BIT(0)|BIT(1), + 4, &ext_32k, &ext_26m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_disp_emc, 0, REG_0X402E0004, BIT(11), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_gsp_emc, 0, REG_0X402E0004, BIT(13), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_ap_ahb, 0, 0, 0, + 0, 0, REG_0X21500020, BIT(0)|BIT(1), + 4, &ext_26m, &clk_76m8, &clk_128m, &clk_192m); + +SCI_CLK_ADD(clk_ap_apb, 0, 0, 0, + 0, 0, REG_0X21500024, BIT(0)|BIT(1), + 4, &ext_26m, &clk_64m, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_gsp, 0, REG_0X20E00000, BIT(3), + 0, 0, REG_0X21500028, BIT(0)|BIT(1), + 4, &clk_96m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_dispc0, 0, REG_0X20E00000, BIT(1), + REG_0X2150002C, BIT(8)|BIT(9)|BIT(10), REG_0X2150002C, BIT(0)|BIT(1), + 4, &clk_153m6, &clk_192m, &clk_256m, &clk_307m2); + +SCI_CLK_ADD(clk_dispc0_dbi, 0, 0, 0, + REG_0X21500030, BIT(8)|BIT(9)|BIT(10), REG_0X21500030, BIT(0)|BIT(1), + 4, &clk_128m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_dispc0_dpi, 0, 0, 0, + REG_0X21500034, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), REG_0X21500034, BIT(0)|BIT(1), + 5, &clk_128m, &clk_153m6, &clk_192m, &clk_384m, &clk_pad); + +SCI_CLK_ADD(clk_nandc_2x, 0, REG_0X20E00000, BIT(18), + 0, 0, REG_0X21500054, BIT(0)|BIT(1), + 4, &clk_192m, &clk_256m, &clk_307m2, &clk_384m); + +SCI_CLK_ADD(clk_nandc_ecc, 0, REG_0X20E00000, BIT(19), + 0, 0, REG_0X21500058, BIT(0), + 2, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_sdio0, 0, REG_0X20E00000, BIT(8), + REG_0X2150005C, BIT(8)|BIT(9)|BIT(10), REG_0X2150005C, BIT(0)|BIT(1), + 4, &ext_26m, &clk_256m, &clk_307m2, &clk_384m); + +SCI_CLK_ADD(clk_sdio1, 0, REG_0X20E00000, BIT(9), + 0, 0, REG_0X21500060, BIT(0)|BIT(1), + 4, &clk_48m, &clk_76m8, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_sdio2, 0, REG_0X20E00000, BIT(10), + 0, 0, REG_0X21500068, BIT(0)|BIT(1), + 4, &clk_48m, &clk_76m8, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_emmc, 0, REG_0X20E00000, BIT(11), + 0, 0, REG_0X21500070, BIT(0)|BIT(1), + 4, &ext_26m, &clk_256m, &clk_307m2, &clk_384m); + +SCI_CLK_ADD(clk_otg_ref, 0, REG_0X20E00000, BIT(4), + 0, 0, REG_0X21500074, BIT(0), + 2, &clk_12m, &clk_24m); + +SCI_CLK_ADD(clk_hsic_ref, 0, REG_0X20E00000, BIT(2), + 0, 0, REG_0X2150007C, BIT(0), + 2, &clk_12m, &clk_24m); + +SCI_CLK_ADD(clk_uart0, 0, REG_0X71300000, BIT(13), + REG_0X21500084, BIT(8)|BIT(9)|BIT(10), REG_0X21500084, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart1, 0, REG_0X71300000, BIT(14), + REG_0X21500088, BIT(8)|BIT(9)|BIT(10), REG_0X21500088, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart2, 0, REG_0X71300000, BIT(15), + REG_0X2150008C, BIT(8)|BIT(9)|BIT(10), REG_0X2150008C, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart3, 0, REG_0X71300000, BIT(16), + REG_0X21500090, BIT(8)|BIT(9)|BIT(10), REG_0X21500090, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart4, 0, REG_0X71300000, BIT(17), + REG_0X21500094, BIT(8)|BIT(9)|BIT(10), REG_0X21500094, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_i2c0, 0, REG_0X71300000, BIT(8), + REG_0X21500098, BIT(8)|BIT(9)|BIT(10), REG_0X21500098, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_i2c1, 0, REG_0X71300000, BIT(9), + REG_0X2150009C, BIT(8)|BIT(9)|BIT(10), REG_0X2150009C, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_i2c2, 0, REG_0X71300000, BIT(10), + REG_0X215000A0, BIT(8)|BIT(9)|BIT(10), REG_0X215000A0, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_i2c3, 0, REG_0X71300000, BIT(11), + REG_0X215000A4, BIT(8)|BIT(9)|BIT(10), REG_0X215000A4, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_i2c4, 0, REG_0X71300000, BIT(12), + REG_0X215000A8, BIT(8)|BIT(9)|BIT(10), REG_0X215000A8, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_spi0, 0, REG_0X71300000, BIT(5), + REG_0X215000AC, BIT(8)|BIT(9)|BIT(10), REG_0X215000AC, BIT(0)|BIT(1), + 5, &ext_26m, &clk_96m, &clk_153m6, &clk_192m, &clk_pad); + +SCI_CLK_ADD(clk_spi1, 0, REG_0X71300000, BIT(6), + REG_0X215000B0, BIT(8)|BIT(9)|BIT(10), REG_0X215000B0, BIT(0)|BIT(1), + 5, &ext_26m, &clk_96m, &clk_153m6, &clk_192m, &clk_pad); + +SCI_CLK_ADD(clk_spi2, 0, REG_0X71300000, BIT(7), + REG_0X215000B4, BIT(8)|BIT(9)|BIT(10), REG_0X215000B4, BIT(0)|BIT(1), + 5, &ext_26m, &clk_96m, &clk_153m6, &clk_192m, &clk_pad); + +SCI_CLK_ADD(clk_iis0, 0, REG_0X71300000, BIT(1), + REG_0X215000B8, BIT(8)|BIT(9)|BIT(10), REG_0X215000B8, BIT(0)|BIT(1), + 4, &ext_26m, &clk_128m, &clk_153m6, &clk_pad); + +SCI_CLK_ADD(clk_iis1, 0, REG_0X71300000, BIT(2), + REG_0X215000BC, BIT(8)|BIT(9)|BIT(10), REG_0X215000BC, BIT(0)|BIT(1), + 4, &ext_26m, &clk_128m, &clk_153m6, &clk_pad); + +SCI_CLK_ADD(clk_iis2, 0, REG_0X71300000, BIT(3), + REG_0X215000C0, BIT(8)|BIT(9)|BIT(10), REG_0X215000C0, BIT(0)|BIT(1), + 4, &ext_26m, &clk_128m, &clk_153m6, &clk_pad); + +SCI_CLK_ADD(clk_iis3, 0, REG_0X71300000, BIT(4), + REG_0X215000C4, BIT(8)|BIT(9)|BIT(10), REG_0X215000C4, BIT(0)|BIT(1), + 4, &ext_26m, &clk_128m, &clk_153m6, &clk_pad); + +SCI_CLK_ADD(clk_zipenc, 0, REG_0X20E00000, BIT(20), + 0, 0, REG_0X215000C8, BIT(0)|BIT(1), + 4, &clk_96m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_zipdec, 0, REG_0X20E00000, BIT(21), + 0, 0, REG_0X215000CC, BIT(0)|BIT(1), + 4, &clk_96m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_gpu_i, 0, REG_0X402E0000, BIT(27), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_gpu, 0, REG_0X402E0000, BIT(27), + REG_0X60100020, BIT(8)|BIT(9), REG_0X60100020, BIT(0)|BIT(1)|BIT(2), + 6, &clk_153m6, &clk_192m, &clk_256m, &clk_307m2, &clk_384m, &clk_512m); + +SCI_CLK_ADD(clk_mm_i, 0, REG_0X402E0000, BIT(25), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_mm_ahb, 0, 0, 0, + 0, 0, REG_0X60E00020, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_mm_axi, 0, REG_0X60D00008, BIT(7), + 0, 0, 0, 0, + 1, &clk_mm_i); + +SCI_CLK_ADD(clk_mm_mtx_axi, 0, REG_0X60D00008, BIT(8), + 0, 0, 0, 0, + 1, &clk_mm_axi); + +SCI_CLK_ADD(clk_mmu, 0, REG_0X60D00000, BIT(7), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_mm_ckg, 0, REG_0X60D00000, BIT(6), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_jpg, 0, REG_0X60D00008, BIT(6), + 0, 0, REG_0X60E00038, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_256m, &clk_312m); + +SCI_CLK_ADD(clk_csi, 0, REG_0X60D00008, BIT(1), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_dcam_mipi, 0, REG_0X60D00008, BIT(0), + 0, 0, 0, 0, + 1, &clk_csi); + +SCI_CLK_ADD(clk_vsp, 0, REG_0X60D00008, BIT(5), + 0, 0, REG_0X60E00030, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_256m, &clk_312m); + +SCI_CLK_ADD(clk_isp, 0, REG_0X60D00008, BIT(4), + 0, 0, REG_0X60E00034, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_256m, &clk_312m); + +SCI_CLK_ADD(clk_ccir, 0, REG_0X60D00000, BIT(1), + 0, 0, REG_0X60E00028, BIT(16), + 2, &clk_24m, &clk_pad); + +SCI_CLK_ADD(clk_sensor, 0, REG_0X60D00008, BIT(2), + REG_0X60E00024, BIT(8)|BIT(9)|BIT(10), REG_0X60E00024, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_76m8, &clk_96m); + +SCI_CLK_ADD(clk_dcam, 0, REG_0X60D00008, BIT(3), + 0, 0, REG_0X60E0002C, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_256m, &clk_312m); + diff --git a/include/soc/sprd/chip_x35l64/__clock_tree.h b/include/soc/sprd/chip_x35l64/__clock_tree.h new file mode 100644 index 00000000..3c53b809 --- /dev/null +++ b/include/soc/sprd/chip_x35l64/__clock_tree.h @@ -0,0 +1,514 @@ +/* + * Copyright (C) 2013 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +/* + * Clock (0)Name, Clock (1)fixed rate, Clock Enable (2)Ctrl and (3)Bit, + * Clock Divisor (4)Ctrl and (5)Bit, Clock Parent (6)Ctrl and (7)Bit, + * and Parent Select (15)Count and (16)Lists[ ... ...] + */ +SCI_CLK_ADD(ext_26m, 26000000, 0, 0, + 0, 0, 0, 0, 0); + +#if 0 +SCI_CLK_ADD(ext_32k, 32768, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_mpll, 0, REG_PMU_APB_CGM_AP_EN, BIT(6), + REG_AON_APB_MPLL_CFG, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_dpll, 0, REG_PMU_APB_CGM_AP_EN, BIT(1), + REG_AON_APB_DPLL_CFG, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_td_sel_i, 0, REG_PMU_APB_TDPLL_REL_CFG, BIT(0), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_w_sel_i, 0, REG_PMU_APB_WPLL_REL_CFG, BIT(0), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_c_sel_i, 0, REG_PMU_APB_CPLL_REL_CFG, BIT(0), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_wifi_sel_i, 0, REG_PMU_APB_WIFIPLL1_REL_CFG, BIT(0), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_tdpll, 768000000, REG_PMU_APB_CGM_AP_EN, BIT(3), + 0, 0, 0, 0, + 1, &clk_td_sel_i); + +SCI_CLK_ADD(clk_wpll, 921600000, REG_PMU_APB_CGM_AP_EN, BIT(5), + 0, 0, 0, 0, + 1, &clk_w_sel_i); + +SCI_CLK_ADD(clk_cpll, 624000000, REG_PMU_APB_CGM_AP_EN, BIT(2), + 0, 0, 0, 0, + 1, &clk_c_sel_i); + +SCI_CLK_ADD(clk_wifipll, 880000000, REG_PMU_APB_CGM_AP_EN, BIT(4), + 0, 0, 0, 0, + 1, &clk_wifi_sel_i); + +SCI_CLK_ADD(clk_300m, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(0), + 3, 0, 0, 0, + 1, &clk_mpll); + +SCI_CLK_ADD(clk_37m5, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(1), + 24, 0, 0, 0, + 1, &clk_mpll); + +SCI_CLK_ADD(clk_66m_d, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(2), + 8, 0, 0, 0, + 1, &clk_dpll); + +SCI_CLK_ADD(clk_51m2_w, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(23), + 18, 0, 0, 0, + 1, &clk_wpll); + +SCI_CLK_ADD(clk_40m_wf1, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(27), + 22, 0, 0, 0, + 1, &clk_wifipll); + +SCI_CLK_ADD(clk_312m, 0, REG_PMU_APB_CGM_AP_EN, BIT(7), + 2, 0, 0, 0, + 1, &clk_cpll); + +SCI_CLK_ADD(clk_208m, 0, REG_PMU_APB_CGM_AP_EN, BIT(20), + 3, 0, 0, 0, + 1, &clk_cpll); + +SCI_CLK_ADD(clk_104m, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(18), + 6, 0, 0, 0, + 1, &clk_cpll); + +SCI_CLK_ADD(clk_52m, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(19), + 12, 0, 0, 0, + 1, &clk_cpll); + +SCI_CLK_ADD(clk_384m, 0, REG_PMU_APB_CGM_AP_EN, BIT(8), + 2, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_256m, 0, REG_PMU_APB_CGM_AP_EN, BIT(9), + 3, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_192m, 0, REG_PMU_APB_CGM_AP_EN, BIT(10), + 4, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_153m6, 0, REG_PMU_APB_CGM_AP_EN, BIT(11), + 5, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_128m, 0, REG_PMU_APB_CGM_AP_EN, BIT(12), + 6, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_96m, 0, REG_PMU_APB_CGM_AP_EN, BIT(13), + 8, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_76m8, 0, REG_PMU_APB_CGM_AP_EN, BIT(14), + 10, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_64m, 0, REG_PMU_APB_CGM_AP_EN, BIT(15), + 12, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_51m2, 0, REG_PMU_APB_CGM_AP_EN, BIT(16), + 15, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_48m, 0, REG_PMU_APB_CGM_AP_EN, BIT(17), + 16, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_38m4, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(15), + 20, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_24m, 0, REG_PMU_APB_CGM_AP_EN, BIT(18), + 32, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_12m, 0, REG_PMU_APB_CGM_AP_EN, BIT(19), + 64, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_mcu, 0, 0, 0, + REG_AP_AHB_CA7_CKG_CFG, BIT(4)|BIT(5)|BIT(6), REG_AP_AHB_CA7_CKG_CFG, BIT(0)|BIT(1)|BIT(2), + 7, &ext_26m, &clk_dpll, &clk_cpll, &clk_tdpll, &clk_wifipll, &clk_wpll, &clk_mpll); + +SCI_CLK_ADD(clk_ca7_core, 0, 0, 0, + 0, 0, 0, 0, + 1, &clk_mcu); + +SCI_CLK_ADD(clk_ca7_axi, 0, 0, 0, + REG_AP_AHB_CA7_CKG_CFG, BIT(8)|BIT(9)|BIT(10), 0, 0, + 1, &clk_mcu); + +SCI_CLK_ADD(clk_ca7_dbg, 0, REG_AP_AHB_MISC_CKG_EN, BIT(8), + REG_AP_AHB_CA7_CKG_CFG, BIT(16)|BIT(17)|BIT(18), 0, 0, + 1, &clk_mcu); + +SCI_CLK_ADD(clk_ap_ahb, 0, 0, 0, + 0, 0, REG_AP_CLK_AP_AHB_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_76m8, &clk_128m, &clk_192m); + +SCI_CLK_ADD(clk_ap_apb, 0, 0, 0, + 0, 0, REG_AP_CLK_AP_APB_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_64m, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_pub_ahb, 0, 0, 0, + 0, 0, REG_AON_CLK_PUB_AHB_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_emc, 0, 0, 0, + REG_AON_CLK_EMC_CFG, BIT(8)|BIT(9), REG_AON_CLK_EMC_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_256m, &clk_384m, &clk_dpll); + +SCI_CLK_ADD(clk_aon_apb, 0, 0, 0, + REG_AON_CLK_AON_APB_CFG, BIT(8)|BIT(9), REG_AON_CLK_AON_APB_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_76m8, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_zip_emc, 0, REG_AON_APB_APB_EB1, BIT(12), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_disp_emc, 0, REG_AON_APB_APB_EB1, BIT(11), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_gsp, 0, REG_AP_AHB_AHB_EB, BIT(3), + 0, 0, REG_AP_CLK_GSP_CFG, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_96m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_disc0, 0, REG_AP_AHB_AHB_EB, BIT(1), + REG_AP_CLK_DISPC0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_DISPC0_CFG, BIT(0), + 2, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_disc0_dbi, 0, REG_AP_AHB_AHB_EB, BIT(1), + REG_AP_CLK_DISPC0_DBI_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_DISPC0_DBI_CFG, BIT(0)|BIT(1), + 4, &clk_128m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_disc0_dpi, 0, REG_AP_AHB_AHB_EB, BIT(1), + REG_AP_CLK_DISPC0_DPI_CFG, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), REG_AP_CLK_DISPC0_DPI_CFG, BIT(0)|BIT(1), + 4, &clk_128m, &clk_153m6, &clk_192m, &clk_384m); + +SCI_CLK_ADD(clk_disc1, 0, REG_AP_AHB_AHB_EB, BIT(2), + REG_AP_CLK_DISPC1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_DISPC1_CFG, BIT(0), + 2, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_disc1_dbi, 0, REG_AP_AHB_AHB_EB, BIT(2), + REG_AP_CLK_DISPC1_DBI_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_DISPC1_DBI_CFG, BIT(0)|BIT(1), + 4, &clk_128m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_disc1_dpi, 0, REG_AP_AHB_AHB_EB, BIT(2), + REG_AP_CLK_DISPC1_DPI_CFG, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), REG_AP_CLK_DISPC1_DPI_CFG, BIT(0)|BIT(1), + 4, &clk_128m, &clk_153m6, &clk_192m, &clk_384m); + +SCI_CLK_ADD(clk_zipdec_emc, 0, REG_AP_AHB_AHB_EB, BIT(21), + 0, 0, REG_AP_CLK_ZIPENC_CFG, BIT(0)|BIT(1), + 4, &clk_96m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_zipenc_emc, 0, REG_AP_AHB_AHB_EB, BIT(20), + 0, 0, REG_AP_CLK_ZIPENC_CFG, BIT(0)|BIT(1), + 4, &clk_96m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_nandc_ecc, 0, REG_AP_AHB_AHB_EB, BIT(19), + 0, 0, REG_AP_CLK_NANDC_ECC_CFG, BIT(0), + 2, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_nfc, 0, REG_AP_AHB_AHB_EB, BIT(6), + REG_AP_CLK_NFC_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_NFC_CFG, BIT(0)|BIT(1), + 3, &clk_64m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_sdio0, 0, REG_AP_AHB_AHB_EB, BIT(8), + REG_AP_CLK_SDIO0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_SDIO0_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_256m, &clk_312m, &clk_384m); + +SCI_CLK_ADD(clk_sdio1, 0, REG_AP_AHB_AHB_EB, BIT(9), + 0, 0, REG_AP_CLK_SDIO1_CFG, BIT(0)|BIT(1), + 4, &clk_48m, &clk_76m8, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_sdio2, 0, REG_AP_AHB_AHB_EB, BIT(10), + 0, 0, REG_AP_CLK_SDIO2_CFG, BIT(0)|BIT(1), + 4, &clk_48m, &clk_76m8, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_emmc, 0, REG_AP_AHB_AHB_EB, BIT(11), + 0, 0, REG_AP_CLK_EMMC_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_256m, &clk_312m, &clk_384m); + +SCI_CLK_ADD(clk_gps_tcxo, 64000000, REG_AP_CLK_GPS_TCXO_CFG, BIT(16), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_gps, 0, REG_AP_AHB_AHB_EB, BIT(12), + 0, 0, REG_AP_CLK_GPS_CFG, BIT(0), + 2, &clk_64m, &clk_76m8); + +SCI_CLK_ADD(clk_usb_ref, 0, REG_AP_AHB_AHB_EB, BIT(4), + 0, 0, REG_AP_CLK_USB_REF_CFG, BIT(0), + 2, &clk_12m, &clk_24m); + +SCI_CLK_ADD(clk_uart0, 0, REG_AP_APB_APB_EB, BIT(13), + REG_AP_CLK_UART0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_UART0_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart1, 0, REG_AP_APB_APB_EB, BIT(14), + REG_AP_CLK_UART1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_UART1_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart2, 0, REG_AP_APB_APB_EB, BIT(15), + REG_AP_CLK_UART2_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_UART2_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart3, 0, REG_AP_APB_APB_EB, BIT(16), + REG_AP_CLK_UART3_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_UART3_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_i2c0, 0, REG_AP_APB_APB_EB, BIT(8), + REG_AP_CLK_I2C0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_I2C0_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_i2c1, 0, REG_AP_APB_APB_EB, BIT(9), + REG_AP_CLK_I2C1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_I2C1_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_i2c2, 0, REG_AP_APB_APB_EB, BIT(10), + REG_AP_CLK_I2C2_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_I2C2_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_i2c3, 0, REG_AP_APB_APB_EB, BIT(11), + REG_AP_CLK_I2C3_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_I2C3_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_spi0, 0, REG_AP_APB_APB_EB, BIT(5), + REG_AP_CLK_SPI0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_SPI0_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_spi1, 0, REG_AP_APB_APB_EB, BIT(6), + REG_AP_CLK_SPI1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_SPI1_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_spi2, 0, REG_AP_APB_APB_EB, BIT(7), + REG_AP_CLK_SPI2_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_SPI2_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_iis0, 0, REG_AP_APB_APB_EB, BIT(1), + REG_AP_CLK_IIS0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_IIS0_CFG, BIT(0)|BIT(1), + 3, &ext_26m, &clk_76m8, &clk_128m); + +SCI_CLK_ADD(clk_iis1, 0, REG_AP_APB_APB_EB, BIT(2), + REG_AP_CLK_IIS1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_IIS1_CFG, BIT(0)|BIT(1), + 3, &ext_26m, &clk_76m8, &clk_128m); + +SCI_CLK_ADD(clk_gpu_top_i, 0, REG_PMU_APB_PD_GPU_TOP_CFG+1, BIT(25), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_gpu_i, 0, REG_AON_APB_APB_EB0, BIT(27), + 0, 0, 0, 0, + 1, &clk_gpu_top_i); + +SCI_CLK_ADD(clk_gpu, 0, &clk_gpu_i, 0, + REG_GPU_APB_APB_CLK_CTRL, BIT(2)|BIT(3), REG_GPU_APB_APB_CLK_CTRL, BIT(0)|BIT(1), + 4, &clk_208m, &clk_256m, &clk_300m, &clk_312m); + +SCI_CLK_ADD(clk_mm_top_i, 0, REG_PMU_APB_PD_MM_TOP_CFG+1, BIT(25), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_mm_i, 0, REG_AON_APB_APB_EB0, BIT(25), + 0, 0, 0, 0, + 1, &clk_mm_top_i); + +SCI_CLK_ADD(clk_mm_ahb, 0, 0, 0, + 0, 0, REG_MM_CLK_MM_AHB_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_mm_mtx_axi, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(8), + 0, 0, 0, 0, + 1, &clk_mm_i); + +SCI_CLK_ADD(clk_mm_axi, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(7), + 0, 0, 0, 0, + 1, &clk_mm_mtx_axi); + +SCI_CLK_ADD(clk_mmu, 0, REG_MM_AHB_AHB_EB, BIT(7), + 0, 0, 0, 0, + 1, &clk_mm_ahb); +SCI_CLK_ADD(clk_mm_ckg_i, 0, REG_MM_AHB_AHB_EB, BIT(6), + 0, 0, 0, 0, + 1, &clk_mm_i); + +SCI_CLK_ADD(clk_jpg_i, 0, REG_MM_AHB_AHB_EB, BIT(5), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_jpg_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(6), + 0, 0, 0, 0, + 1, &clk_jpg_i); + +SCI_CLK_ADD(clk_jpg, 0, &clk_jpg_ckg_i, 0, + 0, 0, REG_MM_CLK_JPG_CFG, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_vsp_i, 0, REG_MM_AHB_AHB_EB, BIT(3), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_vsp_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(5), + 0, 0, 0, 0, + 1, &clk_vsp_i); + +SCI_CLK_ADD(clk_vsp, 0, &clk_vsp_ckg_i, 0, + 0, 0, REG_MM_CLK_VSP_CFG, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_sensor_i, 0, REG_MM_AHB_AHB_EB, BIT(1), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_sensor_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(2), + 0, 0, 0, 0, + 1, &clk_sensor_i); + +SCI_CLK_ADD(clk_sensor, 0, &clk_sensor_ckg_i, 0, + REG_MM_CLK_SENSOR_CFG, BIT(8)|BIT(9)|BIT(10), REG_MM_CLK_SENSOR_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_76m8, &clk_96m); + +SCI_CLK_ADD(clk_ccir_in, 64000000, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_ccir_i, 0, REG_MM_AHB_AHB_EB, BIT(1), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_ccir, 0, &clk_ccir_i, 0, + 0, 0, REG_MM_CLK_CCIR_CFG, BIT(16), + 2, &clk_24m, &clk_ccir_in); + +SCI_CLK_ADD(clk_dcam_i, 0, REG_MM_AHB_AHB_EB, BIT(0), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_dcam_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(3), + 0, 0, 0, 0, + 1, &clk_dcam_i); + +SCI_CLK_ADD(clk_dcam, 0, &clk_dcam_ckg_i, 0, + 0, 0, REG_MM_CLK_DCAM_CFG, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_csi_i, 0, REG_MM_AHB_AHB_EB, BIT(4), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_csi_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(1), + 0, 0, 0, 0, + 1, &clk_csi_i); + +SCI_CLK_ADD(clk_cphy_cfg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(0), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_dcam_mipi, 0, &clk_cphy_cfg_i, 0, + 0, 0, 0, 0, + 1, &clk_csi_ckg_i); + +SCI_CLK_ADD(clk_aud, 0, REG_AON_APB_APB_EB0, BIT(18), + 0, 0, 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_audif, 0, REG_AON_APB_APB_EB0, BIT(17), + 0, 0, REG_AON_CLK_AUDIF_CFG, BIT(0)|BIT(1), + 3, &ext_26m, &clk_38m4, &clk_51m2); + +SCI_CLK_ADD(clk_vbc, 0, REG_AON_APB_APB_EB0, BIT(19), + 0, 0, 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_fm_in, 64000000, REG_AON_CLK_FM_CFG, BIT(16), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_fm, 0, REG_AON_APB_APB_EB0, BIT(1), + 0, 0, 0, 0, + 1, &clk_fm_in); + +SCI_CLK_ADD(clk_adi, 0, REG_AON_APB_APB_EB0, BIT(16), + 0, 0, REG_AON_CLK_ADI_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_38m4, &clk_51m2, &clk_64m); + +SCI_CLK_ADD(clk_aux0, 0, REG_AON_APB_APB_EB1, BIT(2), + REG_AON_APB_AON_CGM_CFG, BIT(16)|BIT(17)|BIT(18)|BIT(19), REG_AON_APB_AON_CGM_CFG, BIT(0)|BIT(1)|BIT(2)|BIT(3), + 9, &ext_32k, &ext_26m, &ext_26m, &clk_48m, &clk_52m, &clk_51m2_w, &clk_37m5, &clk_40m_wf1, &clk_66m_d); + +SCI_CLK_ADD(clk_aux1, 0, REG_AON_APB_APB_EB1, BIT(3), + REG_AON_APB_AON_CGM_CFG, BIT(20)|BIT(21)|BIT(22)|BIT(23), REG_AON_APB_AON_CGM_CFG, BIT(4)|BIT(5)|BIT(6)|BIT(7), + 9, &ext_32k, &ext_26m, &ext_26m, &clk_48m, &clk_52m, &clk_51m2_w, &clk_37m5, &clk_40m_wf1, &clk_66m_d); + +SCI_CLK_ADD(clk_aux2, 0, REG_AON_APB_APB_EB1, BIT(4), + REG_AON_APB_AON_CGM_CFG, BIT(24)|BIT(25)|BIT(26)|BIT(27), REG_AON_APB_AON_CGM_CFG, BIT(8)|BIT(9)|BIT(10)|BIT(11), + 9, &ext_32k, &ext_26m, &ext_26m, &clk_48m, &clk_52m, &clk_51m2_w, &clk_37m5, &clk_40m_wf1, &clk_66m_d); + +SCI_CLK_ADD(clk_pwm0, 0, REG_AON_APB_APB_EB0, BIT(4), + 0, 0, REG_AON_CLK_PWM0_CFG, BIT(0), + 2, &ext_32k, &ext_26m); + +SCI_CLK_ADD(clk_pwm1, 0, REG_AON_APB_APB_EB0, BIT(5), + 0, 0, REG_AON_CLK_PWM1_CFG, BIT(0), + 2, &ext_32k, &ext_26m); + +SCI_CLK_ADD(clk_pwm2, 0, REG_AON_APB_APB_EB0, BIT(6), + 0, 0, REG_AON_CLK_PWM2_CFG, BIT(0), + 2, &ext_32k, &ext_26m); + +SCI_CLK_ADD(clk_pwm3, 0, REG_AON_APB_APB_EB0, BIT(7), + 0, 0, REG_AON_CLK_PWM3_CFG, BIT(0), + 2, &ext_32k, &ext_26m); + +SCI_CLK_ADD(clk_efuse, 0, REG_AON_APB_APB_EB0, BIT(13), + 0, 0, 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_ca7_dap, 0, REG_AON_APB_APB_EB0, BIT(30), + 0, 0, REG_AON_CLK_CA7_DAP_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_76m8, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_ca7_ts, 0, REG_AON_APB_APB_EB0, BIT(28), + 0, 0, REG_AON_CLK_CA7_TS_CFG, BIT(0)|BIT(1), + 4, &ext_32k, &ext_26m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_mspi, 0, REG_AON_APB_APB_EB0, BIT(23), + 0, 0, REG_AON_CLK_MSPI_CFG, BIT(0)|BIT(1), + 3, &clk_52m, &clk_76m8, &clk_96m); + +SCI_CLK_ADD(clk_i2c, 0, REG_AON_APB_APB_EB0, BIT(31), + 0, 0, REG_AON_CLK_I2C_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_avs0, 0, REG_AON_APB_APB_EB0, BIT(6), + 0, 0, REG_AON_CLK_AVS0_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_avs1, 0, REG_AON_APB_APB_EB0, BIT(7), + 0, 0, REG_AON_CLK_AVS1_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); +#endif diff --git a/include/soc/sprd/chip_x35l64/__regs_ada_apb_rf.h b/include/soc/sprd/chip_x35l64/__regs_ada_apb_rf.h new file mode 100644 index 00000000..fbe0bd89 --- /dev/null +++ b/include/soc/sprd/chip_x35l64/__regs_ada_apb_rf.h @@ -0,0 +1,177 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_ADA_APB_RF_HEADFILE_H__ +#define __H_REGS_ADA_APB_RF_HEADFILE_H__ __FILE__ + +#define REGS_ADA_APB_RF + +/* registers definitions for ADA_APB_RF */ +#define REG_ADA_APB_RF_APB_DAC_CTR0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0000) +#define REG_ADA_APB_RF_APB_DAC_CTR1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0004) +#define REG_ADA_APB_RF_APB_DAC_CTR2 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0008) +#define REG_ADA_APB_RF_APB_DAC_CTR3 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x000C) +#define REG_ADA_APB_RF_APB_DAC_CTR4 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0010) +#define REG_ADA_APB_RF_APB_DAC_STS0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0014) +#define REG_ADA_APB_RF_APB_DAC_STS1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0018) +#define REG_ADA_APB_RF_APB_ADC0_CTR0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x001C) +#define REG_ADA_APB_RF_APB_ADC0_CTR1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0020) +#define REG_ADA_APB_RF_APB_ADC0_CTR2 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0024) +#define REG_ADA_APB_RF_APB_ADC0_CTR3 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0028) +#define REG_ADA_APB_RF_APB_CAL_CTR0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0030) +#define REG_ADA_APB_RF_APB_CAL_CTR1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0034) +#define REG_ADA_APB_RF_APB_CAL_CTR3 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x003C) +#define REG_ADA_APB_RF_APB_CAL_STS0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0044) +#define REG_ADA_APB_RF_APB_CAL_STS1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0048) +#define REG_ADA_APB_RF_APB_ADA_CTRL0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0054) +#define REG_ADA_APB_RF_APB_ADA_CTRL1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0058) +#define REG_ADA_APB_RF_APB_RX_GSM_DFT SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x005C) +#define REG_ADA_APB_RF_APB_RX_3G_DFT SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0060) + + + +/* bits definitions for register REG_ADA_APB_RF_APB_DAC_CTR0 */ +#define BITS_DAC_PCTRL_1(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BIT_DAC_OUT_SEL_1 ( BIT(17) ) +#define BIT_DAC_CLK_SEL_1 ( BIT(16) ) +#define BITS_DAC_PCTRL_0(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_DAC_OUT_SEL_0 ( BIT(1) ) +#define BIT_DAC_CLK_SEL_0 ( BIT(0) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_DAC_CTR1 */ +#define BITS_DAC_WD_OVR(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DAC_WADDR_OVR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DAC_WLE_OVR ( BIT(2) ) +#define BIT_DAC_W_OVR_I_QN ( BIT(1) ) +#define BIT_DAC_W_OVR_EN ( BIT(0) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_DAC_CTR2 */ +#define BITS_DAC_RSV(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BIT_DAC_IQ_OUT_MSB_INV ( BIT(21) ) +#define BIT_DAC_IQ_IN_MSB_INV ( BIT(20) ) +#define BIT_DAC_OVR_EN_CAL ( BIT(19) ) +#define BIT_DAC_EN_OOSCAL ( BIT(18) ) +#define BIT_DAC_IQ_SWAP ( BIT(17) ) +#define BIT_DAC_CAL_START ( BIT(16) ) +#define BITS_DAC_OFFSETI(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DAC_OFFSETQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_DAC_CTR3 */ +#define BITS_DAC_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_DAC_CTR4 */ +#define BITS_DAC_I_CAL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC_Q_CAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_DAC_STS0 */ +#define BITS_DAC_WTI(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DAC_WTQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_DAC_STS1 */ +#define BITS_DAC_DA_STATE(_X_) ( (_X_) << 17 & (BIT(17)|BIT(18)) ) +#define BIT_DAC_DONE ( BIT(16) ) +#define BITS_DAC_WQ_OVR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_ADC0_CTR0 */ +#define BITS_ADC0_CALRDOUT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BIT_ADC0_CAL_SOFT_RST ( BIT(10) ) +#define BIT_ADC0_CALRD ( BIT(9) ) +#define BIT_ADC0_CALEN ( BIT(8) ) +#define BITS_ADC0_CALADDR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_ADC0_CTR1 */ +#define BITS_ADC0_DLL_OUT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_ADC0_DLLOOF(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)) ) +#define BIT_ADC0_IQ_SWAP ( BIT(14) ) +#define BITS_ADC0_DLLIN(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_ADC0_IQ_OUT_MSB_INV ( BIT(7) ) +#define BIT_ADC0_IQ_IN_MSB_INV ( BIT(6) ) +#define BIT_ADC0_DLL_SOFT_RST ( BIT(4) ) +#define BIT_ADC0_DLLWR ( BIT(3) ) +#define BIT_ADC0_DLLRD ( BIT(2) ) +#define BIT_ADC0_DLLEN ( BIT(1) ) +#define BIT_ADC0_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_ADC0_CTR2 */ +#define BITS_ADC0_RSV_0(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ADC0_DIG_CLK_SEL_0 ( BIT(11) ) +#define BIT_ADC0_VCM_SEL_0 ( BIT(10) ) +#define BITS_ADC0_DELAY_CAP_0(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ADC0_BIT_SEL_0(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_ADC0_VREF_SEL_0(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_ADC0_VREF_BOOST_0(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_ADC0_QUANT_BOOST_0(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_ADC0_CTR3 */ +#define BITS_ADC0_RSV_1(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ADC0_DIG_CLK_SEL_1 ( BIT(11) ) +#define BIT_ADC0_VCM_SEL_1 ( BIT(10) ) +#define BITS_ADC0_DELAY_CAP_1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ADC0_BIT_SEL_1(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_ADC0_VREF_SEL_1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_ADC0_VREF_BOOST_1(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_ADC0_QUANT_BOOST_1(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_CAL_CTR0 */ +#define BIT_LDO_EN_AUTO_EN ( BIT(27) ) +#define BIT_LDO_EN_FRC ( BIT(26) ) +#define BIT_BG_EN_AUTO_EN ( BIT(25) ) +#define BIT_BG_EN_FRC ( BIT(24) ) +#define BITS_ADC_CLK_CAL_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_ADA_CAL_WAIT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_CLK_ADA_CAL_EN ( BIT(6) ) +#define BIT_DAC_PD_CAL ( BIT(5) ) +#define BIT_ADC0_EN_CAL ( BIT(3) ) +#define BIT_ADC0_CAL ( BIT(1) ) +#define BIT_ADA_MODE_SEL ( BIT(0) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_CAL_CTR1 */ +#define BITS_ADC0_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) ) +#define BITS_ADC0_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_CAL_CTR3 */ +#define BIT_ADA0_CAL_START ( BIT(0) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_CAL_STS0 */ +#define BIT_ADA0_CAL_DONE ( BIT(31) ) +#define BITS_ADC0_I_CAL_RESULT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_CAL_STS1 */ +#define BITS_ADC0_Q_CAL_RESULT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_ADA_CTRL0 */ +#define BITS_ADA_AUTO_CTRL(_X_) (_X_) + +/* bits definitions for register REG_ADA_APB_RF_APB_ADA_CTRL1 */ +#define BITS_ADA_FRC_CTRL(_X_) (_X_) + +/* bits definitions for register REG_ADA_APB_RF_APB_RX_GSM_DFT */ +#define BITS_RX_GSM_DFT_Q(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) ) +#define BITS_RX_GSM_DFT_I(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_RX_3G_DFT */ +#define BITS_RX_3G_DFT_Q(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) ) +#define BITS_RX_3G_DFT_I(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) + +#endif diff --git a/include/soc/sprd/chip_x35l64/__regs_ana_glb.h b/include/soc/sprd/chip_x35l64/__regs_ana_glb.h new file mode 100644 index 00000000..97d72f38 --- /dev/null +++ b/include/soc/sprd/chip_x35l64/__regs_ana_glb.h @@ -0,0 +1,836 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __ANA_REGS_GLB_H__ +#define __ANA_REGS_GLB_H__ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, include <mach/sci_glb_regs.h>" +#endif + +#define ANA_REGS_GLB + +/* registers definitions for controller ANA_REGS_GLB */ +#define ANA_REG_GLB_ARM_MODULE_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0000) +#define ANA_REG_GLB_ARM_CLK_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0004) +#define ANA_REG_GLB_RTC_CLK_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0008) +#define ANA_REG_GLB_ARM_RST SCI_ADDR(ANA_REGS_GLB_BASE, 0x000C) +#define ANA_REG_GLB_LDO_DCDC_PD_RTCSET SCI_ADDR(ANA_REGS_GLB_BASE, 0x0010) +#define ANA_REG_GLB_LDO_DCDC_PD_RTCCLR SCI_ADDR(ANA_REGS_GLB_BASE, 0x0014) +#define ANA_REG_GLB_RTC_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0018) +#define ANA_REG_GLB_LDO_PD_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x001C) +#define ANA_REG_GLB_LDO_V_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0020) +#define ANA_REG_GLB_LDO_V_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0024) +#define ANA_REG_GLB_LDO_V_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0028) +#define ANA_REG_GLB_LDO_CAL_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x002C) +#define ANA_REG_GLB_LDO_CAL_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0030) +#define ANA_REG_GLB_LDO_CAL_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0034) +#define ANA_REG_GLB_LDO_CAL_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0038) +#define ANA_REG_GLB_LDO_CAL_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x003C) +#define ANA_REG_GLB_LDO_CAL_CTRL5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0040) +#define ANA_REG_GLB_LDO_CAL_CTRL6 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0044) +#define ANA_REG_GLB_AUXAD_CTL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0048) +#define ANA_REG_GLB_DCDC_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x004C) +#define ANA_REG_GLB_DCDC_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0050) +#define ANA_REG_GLB_DCDC_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0054) +#define ANA_REG_GLB_DCDC_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0058) +#define ANA_REG_GLB_DCDC_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x005C) +#define ANA_REG_GLB_DCDC_CTRL5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0060) +#define ANA_REG_GLB_DCDC_CTRL6 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0064) +#define ANA_REG_GLB_DDR2_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0068) +#define ANA_REG_GLB_SLP_WAIT_DCDCARM SCI_ADDR(ANA_REGS_GLB_BASE, 0x006C) +#define ANA_REG_GLB_LDO1828_XTL_CTL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0070) +#define ANA_REG_GLB_LDO_SLP_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0074) +#define ANA_REG_GLB_LDO_SLP_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0078) +#define ANA_REG_GLB_LDO_SLP_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x007C) +#define ANA_REG_GLB_LDO_SLP_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0080) +#define ANA_REG_GLB_AUD_SLP_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0084) +#define ANA_REG_GLB_DCDC_SLP_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0088) +#define ANA_REG_GLB_XTL_WAIT_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x008C) +#define ANA_REG_GLB_FLASH_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0090) +#define ANA_REG_GLB_WHTLED_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0094) +#define ANA_REG_GLB_WHTLED_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0098) +#define ANA_REG_GLB_WHTLED_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x009C) +#define ANA_REG_GLB_ANA_DRV_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A0) +#define ANA_REG_GLB_VIBR_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A4) +#define ANA_REG_GLB_VIBR_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A8) +#define ANA_REG_GLB_VIBR_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00AC) +#define ANA_REG_GLB_VIBR_WR_PROT_VALUE SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B0) +#define ANA_REG_GLB_AUDIO_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B4) +#define ANA_REG_GLB_CHGR_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B8) +#define ANA_REG_GLB_CHGR_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00BC) +#define ANA_REG_GLB_CHGR_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C0) +#define ANA_REG_GLB_CHGR_STATUS SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C4) +#define ANA_REG_GLB_ANA_MIXED_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C8) +#define ANA_REG_GLB_PWR_XTL_EN0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00CC) +#define ANA_REG_GLB_PWR_XTL_EN1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D0) +#define ANA_REG_GLB_PWR_XTL_EN2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D4) +#define ANA_REG_GLB_PWR_XTL_EN3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D8) +#define ANA_REG_GLB_PWR_XTL_EN4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00DC) +#define ANA_REG_GLB_PWR_XTL_EN5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E0) +#define ANA_REG_GLB_ANA_STATUS SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E4) +#define ANA_REG_GLB_POR_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E8) +#define ANA_REG_GLB_WDG_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x00EC) +#define ANA_REG_GLB_POR_PIN_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F0) +#define ANA_REG_GLB_POR_SRC_FLAG SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F4) +#define ANA_REG_GLB_POR_7S_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F8) +#define ANA_REG_GLB_INT_DEBUG SCI_ADDR(ANA_REGS_GLB_BASE, 0x00FC) +#define ANA_REG_GLB_GPI_DEBUG SCI_ADDR(ANA_REGS_GLB_BASE, 0x0100) +#define ANA_REG_GLB_HWRST_RTC SCI_ADDR(ANA_REGS_GLB_BASE, 0x0104) +#define ANA_REG_GLB_CHIP_ID_LOW SCI_ADDR(ANA_REGS_GLB_BASE, 0x0108) +#define ANA_REG_GLB_CHIP_ID_HIGH SCI_ADDR(ANA_REGS_GLB_BASE, 0x010C) +#define ANA_REG_GLB_ARM_MF_REG SCI_ADDR(ANA_REGS_GLB_BASE, 0x0110) +#define ANA_REG_GLB_AFUSE_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0114) +#define ANA_REG_GLB_AFUSE_OUT0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0118) +#define ANA_REG_GLB_AFUSE_OUT1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x011C) +#define ANA_REG_GLB_AFUSE_OUT2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0120) +#define ANA_REG_GLB_AFUSE_OUT3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0124) +#define ANA_REG_GLB_ARCH_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0128) +#define ANA_REG_GLB_MCU_WR_PROT_VALUE SCI_ADDR(ANA_REGS_GLB_BASE, 0x012C) +#define ANA_REG_GLB_MP_MISC_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0148) +#define ANA_REG_GLB_DCDC_CORE_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0160) +#define ANA_REG_GLB_DCDC_ARM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0164) +#define ANA_REG_GLB_DCDC_MEM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0168) +#define ANA_REG_GLB_DCDC_GEN_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x016C) +#define ANA_REG_GLB_DCDC_WRF_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0170) +#define ANA_REG_GLB_DCDC_WPA_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0174) +#define ANA_REG_GLB_DCDC_WPA_DCM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x017C) +#define ANA_REG_GLB_LDO_CAL_SEL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0044) + +/* bits definitions for register ANA_REG_GLB_ARM_MODULE_EN */ +#define BIT_ANA_THM_EN ( BIT(12) ) +#define BIT_ANA_BLTC_EN ( BIT(10) ) +#define BIT_ANA_PINREG_EN ( BIT(9) ) +#define BIT_ANA_FGU_EN ( BIT(8) ) +#define BIT_ANA_GPIO_EN ( BIT(7) ) +#define BIT_ANA_ADC_EN ( BIT(6) ) +#define BIT_ANA_HDT_EN ( BIT(5) ) +#define BIT_ANA_AUD_EN ( BIT(4) ) +#define BIT_ANA_EIC_EN ( BIT(3) ) +#define BIT_ANA_WDG_EN ( BIT(2) ) +#define BIT_ANA_RTC_EN ( BIT(1) ) + +/* bits definitions for register ANA_REG_GLB_ARM_CLK_EN */ +#define BIT_CLK_AUXAD_EN ( BIT(9) ) +#define BIT_CLK_AUXADC_EN ( BIT(8) ) +#define BIT_CLK_AUD_HID_EN ( BIT(5) ) +#define BIT_CLK_AUD_HBD_EN ( BIT(4) ) +#define BIT_CLK_AUD_LOOP_EN ( BIT(3) ) +#define BIT_CLK_AUD_6P5M_EN ( BIT(2) ) +#define BIT_CLK_AUDIF_EN ( BIT(1) ) + +/* bits definitions for register ANA_REG_GLB_RTC_CLK_EN */ +#define BIT_RTC_FLASH_EN ( BIT(13) ) +#define BIT_RTC_THMA_AUTO_EN ( BIT(12) ) +#define BIT_RTC_THMA_EN ( BIT(11) ) +#define BIT_RTC_THM_EN ( BIT(10) ) +#define BIT_RTC_BLTC_EN ( BIT(8) ) +#define BIT_RTC_FGU_EN ( BIT(7) ) +#define BIT_RTC_FGUA_EN ( BIT(6) ) +#define BIT_RTC_VIBR_EN ( BIT(5) ) +#define BIT_RTC_AUD_EN ( BIT(4) ) +#define BIT_RTC_EIC_EN ( BIT(3) ) +#define BIT_RTC_WDG_EN ( BIT(2) ) +#define BIT_RTC_RTC_EN ( BIT(1) ) +#define BIT_RTC_ARCH_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_ARM_RST */ +#define BIT_ANA_THMA_SOFT_RST ( BIT(14) ) +#define BIT_ANA_THM_SOFT_RST ( BIT(13) ) +#define BIT_ANA_AUD_32K_SOFT_RST ( BIT(12) ) +#define BIT_ANA_AUDTX_SOFT_RST ( BIT(11) ) +#define BIT_ANA_AUDRX_SOFT_RST ( BIT(10) ) +#define BIT_ANA_AUD_SOFT_RST ( BIT(9) ) +#define BIT_ANA_AUD_HDT_SOFT_RST ( BIT(8) ) +#define BIT_ANA_GPIO_SOFT_RST ( BIT(7) ) +#define BIT_ANA_ADC_SOFT_RST ( BIT(6) ) +#define BIT_ANA_PWM0_SOFT_RST ( BIT(5) ) +#define BIT_ANA_FGU_SOFT_RST ( BIT(4) ) +#define BIT_ANA_EIC_SOFT_RST ( BIT(3) ) +#define BIT_ANA_WDG_SOFT_RST ( BIT(2) ) +#define BIT_ANA_RTC_SOFT_RST ( BIT(1) ) +#define BIT_ANA_BLTC_SOFT_RST ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_DCDC_PD_RTCSET */ +#define BIT_DCDC_OTP_PD_RTCSET ( BIT(14) ) +#define BIT_DCDC_WRF_PD_RTCSET ( BIT(13) ) +#define BIT_DCDC_GEN_PD_RTCSET ( BIT(12) ) +#define BIT_DCDC_MEM_PD_RTCSET ( BIT(11) ) +#define BIT_DCDC_ARM_PD_RTCSET ( BIT(10) ) +#define BIT_DCDC_CORE_PD_RTCSET ( BIT(9) ) +#define BIT_LDO_EMMCCORE_PD_RTCSET ( BIT(8) ) +#define BIT_LDO_EMMCIO_PD_RTCSET ( BIT(7) ) +#define BIT_LDO_RF2_PD_RTCSET ( BIT(6) ) +#define BIT_LDO_RF1_PD_RTCSET ( BIT(5) ) +#define BIT_LDO_RF0_PD_RTCSET ( BIT(4) ) +#define BIT_LDO_VDD25_PD_RTCSET ( BIT(3) ) +#define BIT_LDO_VDD28_PD_RTCSET ( BIT(2) ) +#define BIT_LDO_VDD18_PD_RTCSET ( BIT(1) ) +#define BIT_BG_PD_RTCSET ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_DCDC_PD_RTCCLR */ +#define BIT_DCDC_OTP_PD_RTCCLR ( BIT(14) ) +#define BIT_DCDC_WRF_PD_RTCCLR ( BIT(13) ) +#define BIT_DCDC_GEN_PD_RTCCLR ( BIT(12) ) +#define BIT_DCDC_MEM_PD_RTCCLR ( BIT(11) ) +#define BIT_DCDC_ARM_PD_RTCCLR ( BIT(10) ) +#define BIT_DCDC_CORE_PD_RTCCLR ( BIT(9) ) +#define BIT_LDO_EMMCCORE_PD_RTCCLR ( BIT(8) ) +#define BIT_LDO_EMMCIO_PD_RTCCLR ( BIT(7) ) +#define BIT_LDO_RF2_PD_RTCCLR ( BIT(6) ) +#define BIT_LDO_RF1_PD_RTCCLR ( BIT(5) ) +#define BIT_LDO_RF0_PD_RTCCLR ( BIT(4) ) +#define BIT_LDO_VDD25_PD_RTCCLR ( BIT(3) ) +#define BIT_LDO_VDD28_PD_RTCCLR ( BIT(2) ) +#define BIT_LDO_VDD18_PD_RTCCLR ( BIT(1) ) +#define BIT_BG_PD_RTCCLR ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_RTC_CTRL */ +#define BITS_XOSC32K_CTL_STS(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BIT_XOSC32K_CTL_B3_RTCCLR ( BIT(7) ) +#define BIT_XOSC32K_CTL_B2_RTCCLR ( BIT(6) ) +#define BIT_XOSC32K_CTL_B1_RTCCLR ( BIT(5) ) +#define BIT_XOSC32K_CTL_B0_RTCCLR ( BIT(4) ) +#define BIT_XOSC32K_CTL_B3_RTCSET ( BIT(3) ) +#define BIT_XOSC32K_CTL_B2_RTCSET ( BIT(2) ) +#define BIT_XOSC32K_CTL_B1_RTCSET ( BIT(1) ) +#define BIT_XOSC32K_CTL_B0_RTCSET ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_PD_CTRL */ +#define BIT_LDO_LPREF_PD_SW ( BIT(12) ) +#define BIT_DCDC_WPA_PD ( BIT(11) ) +#define BIT_LDO_CLSG_PD ( BIT(10) ) +#define BIT_LDO_USB_PD ( BIT(9) ) +#define BIT_LDO_CAMMOT_PD ( BIT(8) ) +#define BIT_LDO_CAMIO_PD ( BIT(7) ) +#define BIT_LDO_CAMD_PD ( BIT(6) ) +#define BIT_LDO_CAMA_PD ( BIT(5) ) +#define BIT_LDO_SIM2_PD ( BIT(4) ) +#define BIT_LDO_SIM1_PD ( BIT(3) ) +#define BIT_LDO_SIM0_PD ( BIT(2) ) +#define BIT_LDO_SD_PD ( BIT(1) ) +#define BIT_LDO_AVDD18_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL0 */ +#define BITS_LDO_EMMCCORE_V(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_LDO_EMMCIO_V(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_LDO_RF2_V(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_LDO_RF1_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_LDO_RF0_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_LDO_VDD25_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_LDO_VDD28_V(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_LDO_VDD18_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL1 */ +#define BITS_LDO_SIM2_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_LDO_SIM1_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_LDO_SIM0_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_LDO_SD_V(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_LDO_AVDD18_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL2 */ +#define BITS_VBATBK_RES(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_VBATBK_V(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_LDO_CLSG_V(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_LDO_USB_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_LDO_CAMMOT_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_LDO_CAMIO_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_LDO_CAMD_V(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_LDO_CAMA_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL0 */ +#define BITS_LDO_VDD25_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_VDD28_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_VDD18_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL1 */ +#define BITS_LDO_RF2_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_RF1_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_RF0_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL2 */ +#define BITS_LDO_USB_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_EMMCCORE_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_EMMCIO_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL3 */ +#define BITS_LDO_SD_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_AVDD18_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL4 */ +#define BITS_LDO_CAMA_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_SIM2_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_SIM_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL5 */ +#define BITS_LDO_CAMMOT_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_CAMIO_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_CAMD_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL6 */ +#define BITS_LDOA_CAL_SEL(_x_) ( (_x_) << 11 & (BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_LDOD_CAL_SEL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_LDODCDC_CAL_SEL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_LDO_CLSG_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_AUXAD_CTL */ +#define BIT_AUXAD_CURRENTSEN_EN ( BIT(6) ) +#define BIT_AUXAD_CURRENTSEL ( BIT(5) ) +#define BITS_AUXAD_CURRENT_IBS(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL0 */ +#define BIT_DCDC_CORE_LP_EN ( BIT(15) ) +#define BIT_DCDC_CORE_CL_CTRL ( BIT(14) ) +#define BITS_DCDC_CORE_PDRSLOW(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_DCDC_CORE_PFM ( BIT(9) ) +#define BIT_DCDC_CORE_DCM ( BIT(8) ) +#define BIT_DCDC_ARM_LP_EN ( BIT(7) ) +#define BIT_DCDC_ARM_CL_CTRL ( BIT(6) ) +#define BITS_DCDC_ARM_PDRSLOW(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) +#define BIT_DCDC_ARM_PFM ( BIT(1) ) +#define BIT_DCDC_ARM_DCM ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL1 */ +#define BIT_DCDC_MEM_LP_EN ( BIT(15) ) +#define BIT_DCDC_MEM_CL_CTRL ( BIT(14) ) +#define BITS_DCDC_MEM_PDRSLOW(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_DCDC_MEM_PFM ( BIT(9) ) +#define BIT_DCDC_MEM_DCM ( BIT(8) ) +#define BIT_DCDC_GEN_LP_EN ( BIT(7) ) +#define BIT_DCDC_GEN_CL_CTRL ( BIT(6) ) +#define BITS_DCDC_GEN_PDRSLOW(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) +#define BIT_DCDC_GEN_PFM ( BIT(1) ) +#define BIT_DCDC_GEN_DCM ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL2 */ +#define BIT_DCDC_BG_LP_EN ( BIT(15) ) +#define BIT_DCDC_OTP_CHIP_PD_FLAG_CLR ( BIT(14) ) +#define BIT_DCDC_OTP_CHIP_PD_FLAG ( BIT(13) ) +#define BIT_DCDC_OTP_AUTO_PD_EN ( BIT(12) ) +#define BIT_DCDC_OTP_VBEOP ( BIT(11) ) +#define BITS_DCDC_OTP_S(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BIT_DCDC_WRF_LP_EN ( BIT(7) ) +#define BIT_DCDC_WRF_CL_CTRL ( BIT(6) ) +#define BITS_DCDC_WRF_PDRSLOW(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) +#define BIT_DCDC_WRF_PFM ( BIT(1) ) +#define BIT_DCDC_WRF_DCM ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL3 */ +#define BIT_DCDC_WPA_LP_EN ( BIT(8) ) +#define BIT_DCDC_WPA_CL_CTRL ( BIT(7) ) +#define BIT_DCDC_WPA_ZXOP ( BIT(6) ) +#define BITS_DCDC_WPA_PDRSLOW(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) +#define BIT_DCDC_WPA_PFM ( BIT(1) ) +#define BIT_DCDC_WPA_APTEN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL4 */ +#define BIT_DCDC_CORE_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_CORE_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_CORE_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_CORE_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_ARM_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_ARM_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_ARM_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_ARM_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL5 */ +#define BIT_DCDC_MEM_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_MEM_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_MEM_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_MEM_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_GEN_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_GEN_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_GEN_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_GEN_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL6 */ +#define BIT_DCDC_WPA_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_WPA_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_WPA_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_WPA_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_WRF_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_WRF_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_WRF_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_WRF_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DDR2_CTRL */ +#define BIT_DDR2_BUF_PD_HW ( BIT(9) ) +#define BITS_DDR2_BUF_S_DS(_x_) ( (_x_) << 7 & (BIT(7)|BIT(8)) ) +#define BITS_DDR2_BUF_CHNS_DS(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)) ) +#define BIT_DDR2_BUF_PD ( BIT(4) ) +#define BITS_DDR2_BUF_S(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DDR2_BUF_CHNS(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_SLP_WAIT_DCDCARM */ +#define BITS_SLP_IN_WAIT_DCDCARM(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_SLP_OUT_WAIT_DCDCARM(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO1828_XTL_CTL */ +#define BIT_LDO_VDD18_EXT_XTL2_EN ( BIT(11) ) +#define BIT_LDO_VDD18_EXT_XTL1_EN ( BIT(10) ) +#define BIT_LDO_VDD18_EXT_XTL0_EN ( BIT(9) ) +#define BIT_LDO_VDD18_XTL2_EN ( BIT(8) ) +#define BIT_LDO_VDD18_XTL1_EN ( BIT(7) ) +#define BIT_LDO_VDD18_XTL0_EN ( BIT(6) ) +#define BIT_LDO_VDD28_EXT_XTL2_EN ( BIT(5) ) +#define BIT_LDO_VDD28_EXT_XTL1_EN ( BIT(4) ) +#define BIT_LDO_VDD28_EXT_XTL0_EN ( BIT(3) ) +#define BIT_LDO_VDD28_XTL2_EN ( BIT(2) ) +#define BIT_LDO_VDD28_XTL1_EN ( BIT(1) ) +#define BIT_LDO_VDD28_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SLP_CTRL0 */ +#define BIT_SLP_IO_EN ( BIT(15) ) +#define BIT_SLP_DCDC_OTP_PD_EN ( BIT(13) ) +#define BIT_SLP_DCDCGEN_PD_EN ( BIT(12) ) +#define BIT_SLP_DCDCWPA_PD_EN ( BIT(11) ) +#define BIT_SLP_DCDCWRF_PD_EN ( BIT(10) ) +#define BIT_SLP_DCDCARM_PD_EN ( BIT(9) ) +#define BIT_SLP_LDOEMMCCORE_PD_EN ( BIT(7) ) +#define BIT_SLP_LDOEMMCIO_PD_EN ( BIT(6) ) +#define BIT_SLP_LDORF2_PD_EN ( BIT(5) ) +#define BIT_SLP_LDORF1_PD_EN ( BIT(4) ) +#define BIT_SLP_LDORF0_PD_EN ( BIT(3) ) +#define BIT_SLP_LDOVDD25_PD_EN ( BIT(2) ) +#define BIT_SLP_LDOVDD28_PD_EN ( BIT(1) ) +#define BIT_SLP_LDOVDD18_PD_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SLP_CTRL1 */ +#define BIT_SLP_LDO_PD_EN ( BIT(12) ) +#define BIT_SLP_LDOLPREF_PD_EN ( BIT(11) ) +#define BIT_SLP_LDOCLSG_PD_EN ( BIT(10) ) +#define BIT_SLP_LDOUSB_PD_EN ( BIT(9) ) +#define BIT_SLP_LDOCAMMOT_PD_EN ( BIT(8) ) +#define BIT_SLP_LDOCAMIO_PD_EN ( BIT(7) ) +#define BIT_SLP_LDOCAMD_PD_EN ( BIT(6) ) +#define BIT_SLP_LDOCAMA_PD_EN ( BIT(5) ) +#define BIT_SLP_LDOSIM2_PD_EN ( BIT(4) ) +#define BIT_SLP_LDOSIM1_PD_EN ( BIT(3) ) +#define BIT_SLP_LDOSIM0_PD_EN ( BIT(2) ) +#define BIT_SLP_LDOSD_PD_EN ( BIT(1) ) +#define BIT_SLP_LDOAVDD18_PD_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SLP_CTRL2 */ +#define BIT_SLP_DCDC_BG_LP_EN ( BIT(15) ) +#define BIT_SLP_DCDCCORE_LP_EN ( BIT(11) ) +#define BIT_SLP_DCDCMEM_LP_EN ( BIT(10) ) +#define BIT_SLP_DCDCARM_LP_EN ( BIT(9) ) +#define BIT_SLP_DCDCGEN_LP_EN ( BIT(8) ) +#define BIT_SLP_DCDCWPA_LP_EN ( BIT(6) ) +#define BIT_SLP_DCDCWRF_LP_EN ( BIT(5) ) +#define BIT_SLP_LDOEMMCCORE_LP_EN ( BIT(4) ) +#define BIT_SLP_LDOEMMCIO_LP_EN ( BIT(3) ) +#define BIT_SLP_LDORF2_LP_EN ( BIT(2) ) +#define BIT_SLP_LDORF1_LP_EN ( BIT(1) ) +#define BIT_SLP_LDORF0_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SLP_CTRL3 */ +#define BIT_SLP_BG_LP_EN ( BIT(15) ) +#define BIT_SLP_LDOVDD25_LP_EN ( BIT(13) ) +#define BIT_SLP_LDOVDD28_LP_EN ( BIT(12) ) +#define BIT_SLP_LDOVDD18_LP_EN ( BIT(11) ) +#define BIT_SLP_LDOCLSG_LP_EN ( BIT(10) ) +#define BIT_SLP_LDOUSB_LP_EN ( BIT(9) ) +#define BIT_SLP_LDOCAMMOT_LP_EN ( BIT(8) ) +#define BIT_SLP_LDOCAMIO_LP_EN ( BIT(7) ) +#define BIT_SLP_LDOCAMD_LP_EN ( BIT(6) ) +#define BIT_SLP_LDOCAMA_LP_EN ( BIT(5) ) +#define BIT_SLP_LDOSIM2_LP_EN ( BIT(4) ) +#define BIT_SLP_LDOSIM1_LP_EN ( BIT(3) ) +#define BIT_SLP_LDOSIM0_LP_EN ( BIT(2) ) +#define BIT_SLP_LDOSD_LP_EN ( BIT(1) ) +#define BIT_SLP_LDOAVDD18_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_AUD_SLP_CTRL4 */ +#define BIT_SLP_AUD_PA_SW_PD_EN ( BIT(15) ) +#define BIT_SLP_AUD_PA_LDO_PD_EN ( BIT(14) ) +#define BIT_SLP_AUD_PA_PD_EN ( BIT(13) ) +#define BIT_SLP_AUD_OVP_PD_PD_EN ( BIT(9) ) +#define BIT_SLP_AUD_OVP_LDO_PD_EN ( BIT(8) ) +#define BIT_SLP_AUD_VB_PD_EN ( BIT(7) ) +#define BIT_SLP_AUD_VBO_PD_EN ( BIT(6) ) +#define BIT_SLP_AUD_HEADMICBIAS_PD_EN ( BIT(5) ) +#define BIT_SLP_AUD_MICBIAS_HV_PD_EN ( BIT(2) ) +#define BIT_SLP_AUD_HEADMIC_PD_EN ( BIT(1) ) +#define BIT_SLP_AUD_PMUR1_PD_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL */ +#define BITS_SLP_DCDCCORE_VOL_DROP_CNT(_x_)( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DCDC_CORE_CTL_DS(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register ANA_REG_GLB_XTL_WAIT_CTRL */ +#define BIT_SLP_XTLBUF_PD_EN ( BIT(9) ) +#define BIT_XTL_EN ( BIT(8) ) +#define BITS_XTL_WAIT(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_FLASH_CTRL */ +#define BIT_FLASH_PON ( BIT(15) ) +#define BIT_FLASH_V_HW_EN ( BIT(6) ) +#define BITS_FLASH_V_HW_STEP(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_FLASH_V_SW(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register ANA_REG_GLB_WHTLED_CTRL0 */ +#define BIT_WHTLED_PD_STS ( BIT(15) ) +#define BITS_WHTLED_DC(_x_) ( (_x_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BIT_WHTLED_BOOST_EN ( BIT(8) ) +#define BIT_WHTLED_SERIES_EN ( BIT(7) ) +#define BITS_WHTLED_V(_x_) ( (_x_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_WHTLED_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_WHTLED_CTRL1 */ +#define BIT_LCM_CABC_PWM_SEL ( BIT(15) ) +#define BIT_RTC_PWM0_EN ( BIT(14) ) +#define BIT_PWM0_EN ( BIT(13) ) +#define BITS_WHTLED_ISET(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_WHTLED_FRE_AD(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)) ) +#define BITS_WHTLED_CLMIT_OP(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_WHTLED_CTRL2 */ +#define BIT_WHTLED_DIMMING_SEL ( BIT(15) ) +#define BIT_WHTLED_PD_SEL ( BIT(14) ) +#define BIT_WHTLED_DIS_OVST ( BIT(13) ) +#define BIT_WHTLED_DIM_SEL ( BIT(12) ) +#define BIT_WHTLED_DE_BIAS ( BIT(11) ) +#define BIT_WHTLED_BUFF_SHT ( BIT(10) ) +#define BITS_WHTLED_STB_OP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_WHTLED_CAP_OPTION ( BIT(7) ) +#define BIT_WHTLED_OVP_DIS ( BIT(6) ) +#define BITS_WHTLED_REF_DC(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register ANA_REG_GLB_ANA_DRV_CTRL */ +#define BIT_SLP_RGB_PD_EN ( BIT(14) ) +#define BIT_RGB_PD_HW_EN ( BIT(13) ) +#define BITS_RGB_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BITS_KPLED_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_RGB_PD_SW ( BIT(2) ) +#define BIT_KPLED_PD ( BIT(1) ) +#define BIT_KPLED_PD_STS ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_VIBR_CTRL0 */ +#define BITS_VIBR_STABLE_V_HW(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_VIBR_INIT_V_HW(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_VIBR_V_SW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_VIBR_PON ( BIT(2) ) +#define BIT_VIBR_SW_EN ( BIT(1) ) + +/* bits definitions for register ANA_REG_GLB_VIBR_CTRL1 */ +#define BITS_VIBR_V_CONVERT_CNT_HW(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_VIBR_CTRL2 */ +#define BIT_VIBR_PWR_ON_STS ( BIT(15) ) +#define BIT_VIBR_HW_FLOW_ERR1 ( BIT(14) ) +#define BIT_VIBR_HW_FLOW_ERR1_CLR ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_VIBR_WR_PROT_VALUE */ +#define BIT_VIBR_WR_PROT ( BIT(15) ) +#define BITS_VIBR_WR_PROT_VALUE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_AUDIO_CTRL */ +#define BIT_AUD_SLP_APP_RST_EN ( BIT(10) ) +#define BITS_CLK_AUD_HBD_DIV(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BIT_CLK_AUD_LOOP_INV_EN ( BIT(4) ) +#define BIT_CLK_AUDIF_TX_INV_EN ( BIT(3) ) +#define BIT_CLK_AUDIF_RX_INV_EN ( BIT(2) ) +#define BIT_CLK_AUD_6P5M_TX_INV_EN ( BIT(1) ) +#define BIT_CLK_AUD_6P5M_RX_INV_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL0 */ +#define BIT_CHGR_PD_STS ( BIT(15) ) +#define BITS_CHGR_CV_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CHGR_END_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CHG_PUMP_V(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BIT_CHGR_PD_RTCCLR ( BIT(1) ) +#define BIT_CHGR_PD_RTCSET ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL1 */ +#define BIT_DP_DM_SW_EN ( BIT(15) ) +#define BITS_CHGR_CC_I(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_VBAT_OVP_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_VCHG_OVP_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL2 */ +#define BITS_CHG_PUMP_CAL(_x_) ( (_x_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_CHG_PUMP_PD ( BIT(8) ) +#define BIT_CHGR_CC_EN ( BIT(1) ) +#define BIT_RECHG ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_STATUS */ +#define BIT_CHG_DET_DONE ( BIT(11) ) +#define BIT_DP_LOW ( BIT(10) ) +#define BIT_DCP_DET ( BIT(9) ) +#define BIT_CHG_DET ( BIT(8) ) +#define BIT_SDP_INT ( BIT(7) ) +#define BIT_DCP_INT ( BIT(6) ) +#define BIT_CDP_INT ( BIT(5) ) +#define BIT_CHGR_CV_STATUS ( BIT(4) ) +#define BIT_CHGR_ON ( BIT(3) ) +#define BIT_CHGR_INT ( BIT(2) ) +#define BIT_VBAT_OVI ( BIT(1) ) +#define BIT_VCHG_OVI ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_ANA_MIXED_CTRL */ +#define BIT_PTEST_PD_RTCSET ( BIT(15) ) +#define BIT_THM_CHIP_PD_FLAG ( BIT(8) ) +#define BIT_THM_CHIP_PD_FLAG_CLR ( BIT(7) ) +#define BITS_THM_CAL_SEL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)) ) +#define BIT_THM_AUTO_PD_EN ( BIT(4) ) +#define BIT_BG_LP_EN ( BIT(3) ) +#define BITS_UVHO_T(_x_) ( (_x_) << 1 & (BIT(1)|BIT(2)) ) +#define BIT_UVHO_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN0 */ +#define BIT_LDO_XTL_EN ( BIT(15) ) +#define BIT_LDO_RF1_EXT_XTL2_EN ( BIT(11) ) +#define BIT_LDO_RF1_EXT_XTL1_EN ( BIT(10) ) +#define BIT_LDO_RF1_EXT_XTL0_EN ( BIT(9) ) +#define BIT_LDO_RF1_XTL2_EN ( BIT(8) ) +#define BIT_LDO_RF1_XTL1_EN ( BIT(7) ) +#define BIT_LDO_RF1_XTL0_EN ( BIT(6) ) +#define BIT_LDO_RF0_EXT_XTL2_EN ( BIT(5) ) +#define BIT_LDO_RF0_EXT_XTL1_EN ( BIT(4) ) +#define BIT_LDO_RF0_EXT_XTL0_EN ( BIT(3) ) +#define BIT_LDO_RF0_XTL2_EN ( BIT(2) ) +#define BIT_LDO_RF0_XTL1_EN ( BIT(1) ) +#define BIT_LDO_RF0_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN1 */ +#define BIT_LDO_VDD25_EXT_XTL2_EN ( BIT(11) ) +#define BIT_LDO_VDD25_EXT_XTL1_EN ( BIT(10) ) +#define BIT_LDO_VDD25_EXT_XTL0_EN ( BIT(9) ) +#define BIT_LDO_VDD25_XTL2_EN ( BIT(8) ) +#define BIT_LDO_VDD25_XTL1_EN ( BIT(7) ) +#define BIT_LDO_VDD25_XTL0_EN ( BIT(6) ) +#define BIT_LDO_RF2_EXT_XTL2_EN ( BIT(5) ) +#define BIT_LDO_RF2_EXT_XTL1_EN ( BIT(4) ) +#define BIT_LDO_RF2_EXT_XTL0_EN ( BIT(3) ) +#define BIT_LDO_RF2_XTL2_EN ( BIT(2) ) +#define BIT_LDO_RF2_XTL1_EN ( BIT(1) ) +#define BIT_LDO_RF2_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN2 */ +#define BIT_LDO_AVDD18_EXT_XTL2_EN ( BIT(11) ) +#define BIT_LDO_AVDD18_EXT_XTL1_EN ( BIT(10) ) +#define BIT_LDO_AVDD18_EXT_XTL0_EN ( BIT(9) ) +#define BIT_LDO_AVDD18_XTL2_EN ( BIT(8) ) +#define BIT_LDO_AVDD18_XTL1_EN ( BIT(7) ) +#define BIT_LDO_AVDD18_XTL0_EN ( BIT(6) ) +#define BIT_LDO_SIM2_EXT_XTL2_EN ( BIT(5) ) +#define BIT_LDO_SIM2_EXT_XTL1_EN ( BIT(4) ) +#define BIT_LDO_SIM2_EXT_XTL0_EN ( BIT(3) ) +#define BIT_LDO_SIM2_XTL2_EN ( BIT(2) ) +#define BIT_LDO_SIM2_XTL1_EN ( BIT(1) ) +#define BIT_LDO_SIM2_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN3 */ +#define BIT_DCDC_BG_EXT_XTL2_EN ( BIT(11) ) +#define BIT_DCDC_BG_EXT_XTL1_EN ( BIT(10) ) +#define BIT_DCDC_BG_EXT_XTL0_EN ( BIT(9) ) +#define BIT_DCDC_BG_XTL2_EN ( BIT(8) ) +#define BIT_DCDC_BG_XTL1_EN ( BIT(7) ) +#define BIT_DCDC_BG_XTL0_EN ( BIT(6) ) +#define BIT_BG_EXT_XTL2_EN ( BIT(5) ) +#define BIT_BG_EXT_XTL1_EN ( BIT(4) ) +#define BIT_BG_EXT_XTL0_EN ( BIT(3) ) +#define BIT_BG_XTL2_EN ( BIT(2) ) +#define BIT_BG_XTL1_EN ( BIT(1) ) +#define BIT_BG_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN4 */ +#define BIT_DCDC_WRF_XTL2_EN ( BIT(14) ) +#define BIT_DCDC_WRF_XTL1_EN ( BIT(13) ) +#define BIT_DCDC_WRF_XTL0_EN ( BIT(12) ) +#define BIT_DCDC_WPA_XTL2_EN ( BIT(11) ) +#define BIT_DCDC_WPA_XTL1_EN ( BIT(10) ) +#define BIT_DCDC_WPA_XTL0_EN ( BIT(9) ) +#define BIT_DCDC_MEM_XTL2_EN ( BIT(8) ) +#define BIT_DCDC_MEM_XTL1_EN ( BIT(7) ) +#define BIT_DCDC_MEM_XTL0_EN ( BIT(6) ) +#define BIT_DCDC_GEN_XTL2_EN ( BIT(5) ) +#define BIT_DCDC_GEN_XTL1_EN ( BIT(4) ) +#define BIT_DCDC_GEN_XTL0_EN ( BIT(3) ) +#define BIT_DCDC_CORE_XTL2_EN ( BIT(2) ) +#define BIT_DCDC_CORE_XTL1_EN ( BIT(1) ) +#define BIT_DCDC_CORE_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN5 */ +#define BIT_DCDC_WRF_EXT_XTL2_EN ( BIT(14) ) +#define BIT_DCDC_WRF_EXT_XTL1_EN ( BIT(13) ) +#define BIT_DCDC_WRF_EXT_XTL0_EN ( BIT(12) ) +#define BIT_DCDC_WPA_EXT_XTL2_EN ( BIT(11) ) +#define BIT_DCDC_WPA_EXT_XTL1_EN ( BIT(10) ) +#define BIT_DCDC_WPA_EXT_XTL0_EN ( BIT(9) ) +#define BIT_DCDC_MEM_EXT_XTL2_EN ( BIT(8) ) +#define BIT_DCDC_MEM_EXT_XTL1_EN ( BIT(7) ) +#define BIT_DCDC_MEM_EXT_XTL0_EN ( BIT(6) ) +#define BIT_DCDC_GEN_EXT_XTL2_EN ( BIT(5) ) +#define BIT_DCDC_GEN_EXT_XTL1_EN ( BIT(4) ) +#define BIT_DCDC_GEN_EXT_XTL0_EN ( BIT(3) ) +#define BIT_DCDC_CORE_EXT_XTL2_EN ( BIT(2) ) +#define BIT_DCDC_CORE_EXT_XTL1_EN ( BIT(1) ) +#define BIT_DCDC_CORE_EXT_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_ANA_STATUS */ +#define BIT_BONDOPT5 ( BIT(5) ) +#define BIT_BONDOPT4 ( BIT(4) ) +#define BIT_BONDOPT3 ( BIT(3) ) +#define BIT_BONDOPT2 ( BIT(2) ) +#define BIT_BONDOPT1 ( BIT(1) ) +#define BIT_BONDOPT0 ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_POR_RST_MONITOR */ +#define BITS_POR_RST_MONITOR(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_WDG_RST_MONITOR */ +#define BITS_WDG_RST_MONITOR(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_POR_PIN_RST_MONITOR */ +#define BITS_POR_PIN_RST_MONITOR(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_POR_SRC_FLAG */ +#define BIT_POR_SW_FORCE_ON ( BIT(15) ) +#define BITS_POR_SRC_FLAG(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_POR_7S_CTRL */ +#define BIT_PBINT_7S_FLAG_CLR ( BIT(15) ) +#define BIT_EXT_RSTN_FLAG_CLR ( BIT(14) ) +#define BIT_CHGR_INT_FLAG_CLR ( BIT(13) ) +#define BIT_PBINT2_FLAG_CLR ( BIT(12) ) +#define BIT_PBINT_FLAG_CLR ( BIT(11) ) +#define BIT_PBINT_7S_RST_SWMODE_RTCSTS ( BIT(10) ) +#define BIT_PBINT_7S_RST_SWMODE_RTCCLR ( BIT(9) ) +#define BIT_PBINT_7S_RST_SWMODE_RTCSET ( BIT(8) ) +#define BITS_PBINT_7S_RST_THRESHOLD(_x_)( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_PBINT_7S_RST_DISABLE ( BIT(3) ) +#define BIT_PBINT_7S_RST_MODE_RTCSTS ( BIT(2) ) +#define BIT_PBINT_7S_RST_MODE_RTCCLR ( BIT(1) ) +#define BIT_PBINT_7S_RST_MODE_RTCSET ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_INT_DEBUG */ +#define BIT_OTP_INT_DEB ( BIT(10) ) +#define BIT_THM_INT_DEB ( BIT(9) ) +#define BIT_AUD_PROT_INT_DEB ( BIT(8) ) +#define BIT_AUD_HEADBTN_INT_DEB ( BIT(7) ) +#define BIT_EIC_INT_DEB ( BIT(6) ) +#define BIT_FGU_INT_DEB ( BIT(5) ) +#define BIT_WDG_INT_DEB ( BIT(4) ) +#define BIT_RTC_INT_DEB ( BIT(3) ) +#define BIT_GPIO_INT_DEB ( BIT(2) ) +#define BIT_ADC_INT_DEB ( BIT(1) ) +#define BIT_INT_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_GPI_DEBUG */ +#define BIT_HEAD_INSERT2_DEB ( BIT(9) ) +#define BIT_HEAD_INSERT_DEB ( BIT(8) ) +#define BIT_HEAD_BUTTON_DEB ( BIT(7) ) +#define BIT_PBINT2_DEB ( BIT(6) ) +#define BIT_PBINT_DEB ( BIT(5) ) +#define BIT_VCHG_OVI_DEB ( BIT(4) ) +#define BIT_VBAT_OVI_DEB ( BIT(3) ) +#define BIT_CHGR_INT_DEB ( BIT(2) ) +#define BIT_GPI_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_HWRST_RTC */ +#define BITS_HWRST_RTC_REG_STS(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_HWRST_RTC_REG_SET(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_CHIP_ID_LOW */ +#define BITS_CHIP_ID_LOW(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_CHIP_ID_HIGH */ +#define BITS_CHIP_ID_HIGH(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_ARM_MF_REG */ +#define BITS_ARM_MF_REG(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_AFUSE_CTRL */ +#define BIT_AFUSE_READ_REQ ( BIT(7) ) +#define BITS_AFUSE_READ_DLY(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) + +/* bits definitions for register ANA_REG_GLB_AFUSE_OUT0 */ +#define BITS_AFUSE_OUT0(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_AFUSE_OUT1 */ +#define BITS_AFUSE_OUT1(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_AFUSE_OUT2 */ +#define BITS_AFUSE_OUT2(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_AFUSE_OUT3 */ +#define BITS_AFUSE_OUT3(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_ARCH_EN */ +#define BIT_ARCH_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_MCU_WR_PROT_VALUE */ +#define BIT_MCU_WR_PROT ( BIT(15) ) +#define BITS_MCU_WR_PROT_VALUE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CORE_ADI */ +#define BITS_DCDC_CORE_CTL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DCDC_CORE_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_ARM_ADI */ +#define BITS_DCDC_ARM_CTL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DCDC_ARM_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_MEM_ADI */ +#define BIT_DCDC_MEM_CTL_ADI ( BIT(5) ) +#define BITS_DCDC_MEM_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_GEN_ADI */ +#define BITS_DCDC_GEN_CTL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DCDC_GEN_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_WRF_ADI */ +#define BITS_DCDC_WRF_CTL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)) ) +#define BITS_DCDC_WRF_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_WPA_ADI */ +#define BITS_DCDC_WPA_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_WPA_DCM_ADI */ +#define BIT_DCDC_WPA_DCM_ADI ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_SEL */ +#define BIT_LDO_CAMIO_CAL_EN ( BIT(5) ) +#define BIT_LDO_CLSG_CAL_EN ( BIT(6) ) +#define BITS_LDO_CAMD_CAL_EN(_x_) ( (_x_) & (BIT(5)|BIT(6)) ) +#define BIT_LDO_EMMCIO_CAL_EN ( BIT(7) ) +#define BITS_LDO_AVDD18_CAL_EN(_x_) ( (_x_) & (BIT(5)|BIT(7)) ) +#define BITS_LDO_VDD18_CAL_EN(_x_) ( (_x_) & (BIT(6)|BIT(7)) ) +#define BIT_LDO_SIM0_CAL_EN ( BIT(9) ) +#define BIT_LDO_SIM1_CAL_EN ( BIT(9) ) +#define BITS_LDO_SIM2_CAL_EN(_x_) ( (_x_) & (BIT(8)|BIT(9)) ) +#define BIT_LDO_EMMCCORE_CAL_EN ( BIT(10) ) +#define BITS_LDO_VDD28_CAL_EN(_x_) ( (_x_) & (BIT(8)|BIT(10)) ) +#define BITS_LDO_VDD25_CAL_EN(_x_) ( (_x_) & (BIT(9)|BIT(10)) ) +#define BITS_LDO_USB_CAL_EN(_x_) ( (_x_) & (BIT(8)|BIT(9)|BIT(10)) ) +#define BIT_LDO_SD_CAL_EN ( BIT(11) ) +#define BIT_LDO_CAMA_CAL_EN ( BIT(12) ) +#define BITS_LDO_RF2_CAL_EN(_x_) ( (_x_) & (BIT(11)|BIT(12)) ) +#define BIT_LDO_RF1_CAL_EN ( BIT(13) ) +#define BITS_LDO_RF0_CAL_EN(_x_) ( (_x_) & (BIT(11)|BIT(13)) ) +#define BITS_LDO_CAMMOT_CAL_EN(_x_) ( (_x_) & (BIT(12)|BIT(13)) ) +#define BITS_LDO_CAL_SEL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +#define SHFT_LDO_CAL_SEL ( 5 ) +#define MASK_LDO_CAL_SEL ( BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13) ) + +/* vars definitions for controller ANA_REGS_GLB */ + +#endif //__ANA_REGS_GLB_H__ diff --git a/include/soc/sprd/chip_x35l64/__regs_ana_sc2723_glb.h b/include/soc/sprd/chip_x35l64/__regs_ana_sc2723_glb.h new file mode 100755 index 00000000..fe9cd745 --- /dev/null +++ b/include/soc/sprd/chip_x35l64/__regs_ana_sc2723_glb.h @@ -0,0 +1,952 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __ANA_REGS_GLB_H__ +#define __ANA_REGS_GLB_H__ + +#define ANA_REGS_GLB + +/* registers definitions for controller ANA_REGS_GLB */ +#define ANA_REG_GLB_ARM_MODULE_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0000) +#define ANA_REG_GLB_ARM_CLK_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0004) +#define ANA_REG_GLB_RTC_CLK_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0008) +#define ANA_REG_GLB_ARM_RST SCI_ADDR(ANA_REGS_GLB_BASE, 0x000C) +#define ANA_REG_GLB_LDO_DCDC_PD SCI_ADDR(ANA_REGS_GLB_BASE, 0x0010) +#define ANA_REG_GLB_LDO_PD_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0014) +#define ANA_REG_GLB_LDO_V_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0018) +#define ANA_REG_GLB_LDO_V_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x001C) +#define ANA_REG_GLB_LDO_V_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0020) +#define ANA_REG_GLB_LDO_V_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0024) +#define ANA_REG_GLB_LDO_V_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0028) +#define ANA_REG_GLB_LDO_V_CTRL5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x002C) +#define ANA_REG_GLB_LDO_V_CTRL6 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0030) +#define ANA_REG_GLB_LDO_V_CTRL7 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0034) +#define ANA_REG_GLB_LDO_V_CTRL8 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0038) +#define ANA_REG_GLB_LDO_V_CTRL9 SCI_ADDR(ANA_REGS_GLB_BASE, 0x003C) +#define ANA_REG_GLB_LDO_V_CTRL10 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0040) +#define ANA_REG_GLB_LDO_V_CTRL11 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0044) +#define ANA_REG_GLB_LDO_LP_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0048) +#define ANA_REG_GLB_DCDC_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x004C) +#define ANA_REG_GLB_DCDC_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0050) +#define ANA_REG_GLB_DCDC_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0054) +#define ANA_REG_GLB_DCDC_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0058) +#define ANA_REG_GLB_DCDC_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x005C) +#define ANA_REG_GLB_DCDC_CTRL5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0060) +#define ANA_REG_GLB_DCDC_CTRL6 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0064) +#define ANA_REG_GLB_DCDC_CTRL7 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0068) +#define ANA_REG_GLB_DCDC_CTRL8 SCI_ADDR(ANA_REGS_GLB_BASE, 0x006C) +#define ANA_REG_GLB_DCDC_CTRL9 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0070) +#define ANA_REG_GLB_DCDC_CTRL10 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0074) +#define ANA_REG_GLB_DCDC_CTRL11 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0078) +#define ANA_REG_GLB_DCDC_CTRL12 SCI_ADDR(ANA_REGS_GLB_BASE, 0x007C) +#define ANA_REG_GLB_DCDC_CTRL13 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0080) +#define ANA_REG_GLB_DCDC_CTRL14 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0084) +#define ANA_REG_GLB_DCDC_CTRL15 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0088) +#define ANA_REG_GLB_SLP_WAIT_DCDCARM SCI_ADDR(ANA_REGS_GLB_BASE, 0x008C) +#define ANA_REG_GLB_PWR_SLP_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0090) +#define ANA_REG_GLB_PWR_SLP_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0094) +#define ANA_REG_GLB_PWR_SLP_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0098) +#define ANA_REG_GLB_PWR_SLP_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x009C) +#define ANA_REG_GLB_PWR_SLP_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A0) +#define ANA_REG_GLB_AUD_SLP_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A4) +#define ANA_REG_GLB_DCDC_SLP_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A8) +#define ANA_REG_GLB_DCDC_SLP_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00AC) +#define ANA_REG_GLB_DCDC_SLP_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B0) +#define ANA_REG_GLB_DCDC_SLP_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B4) +#define ANA_REG_GLB_DCDC_SLP_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B8) +#define ANA_REG_GLB_DCDC_SLP_CTRL5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00BC) +#define ANA_REG_GLB_PWR_SEL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C0) +#define ANA_REG_GLB_PWR_XTL_EN0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C4) +#define ANA_REG_GLB_PWR_XTL_EN1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C8) +#define ANA_REG_GLB_PWR_XTL_EN2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00CC) +#define ANA_REG_GLB_PWR_XTL_EN3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D0) +#define ANA_REG_GLB_32KLESS_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D4) +#define ANA_REG_GLB_32KLESS_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D8) +#define ANA_REG_GLB_32KLESS_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00DC) +#define ANA_REG_GLB_32KLESS_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E0) +#define ANA_REG_GLB_AUXAD_CTL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E4) +#define ANA_REG_GLB_XTL_WAIT_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E8) +#define ANA_REG_GLB_RGB_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00EC) +#define ANA_REG_GLB_WHTLED_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F0) +#define ANA_REG_GLB_WHTLED_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0094) +#define ANA_REG_GLB_WHTLED_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0098) +#define ANA_REG_GLB_KPLED_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F4) +#define ANA_REG_GLB_VIBR_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F8) +#define ANA_REG_GLB_AUDIO_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00FC) +#define ANA_REG_GLB_AUDIO_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0100) +#define ANA_REG_GLB_CHGR_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0104) +#define ANA_REG_GLB_CHGR_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0108) +#define ANA_REG_GLB_CHGR_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x010C) +#define ANA_REG_GLB_CHGR_DET_FGU_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0110) +#define ANA_REG_GLB_CHGR_STATUS SCI_ADDR(ANA_REGS_GLB_BASE, 0x0114) +#define ANA_REG_GLB_MIXED_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0118) +#define ANA_REG_GLB_MIXED_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x011C) +#define ANA_REG_GLB_SWRST_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0120) +#define ANA_REG_GLB_POR_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x0124) +#define ANA_REG_GLB_WDG_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x0128) +#define ANA_REG_GLB_POR_PIN_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x012C) +#define ANA_REG_GLB_POR_SRC_FLAG SCI_ADDR(ANA_REGS_GLB_BASE, 0x0130) +#define ANA_REG_GLB_POR_7S_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0134) +#define ANA_REG_GLB_HWRST_RTC SCI_ADDR(ANA_REGS_GLB_BASE, 0x0138) +#define ANA_REG_GLB_CHIP_ID_LOW SCI_ADDR(ANA_REGS_GLB_BASE, 0x013C) +#define ANA_REG_GLB_CHIP_ID_HIGH SCI_ADDR(ANA_REGS_GLB_BASE, 0x0140) +#define ANA_REG_GLB_ARM_MF_REG SCI_ADDR(ANA_REGS_GLB_BASE, 0x0144) +#define ANA_REG_GLB_ARCH_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0148) +#define ANA_REG_GLB_MCU_WR_PROT_VALUE SCI_ADDR(ANA_REGS_GLB_BASE, 0x014C) +#define ANA_REG_GLB_PWR_WR_PROT_VALUE SCI_ADDR(ANA_REGS_GLB_BASE, 0x0150) +#define ANA_REG_GLB_SMPL_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0154) +#define ANA_REG_GLB_SMPL_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0158) +#define ANA_REG_GLB_RTC_RST0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x015C) +#define ANA_REG_GLB_RTC_RST1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0160) +#define ANA_REG_GLB_RTC_RST2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0164) +#define ANA_REG_GLB_LDO_SHPT_PD1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0188) +#define ANA_REG_GLB_LDO_SHPT_PD2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x018C) +#define ANA_REG_GLB_BATDET_CUR_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0190) +#define ANA_REG_GLB_RTC_CLK_STOP SCI_ADDR(ANA_REGS_GLB_BASE, 0x0194) +#define ANA_REG_GLB_VBAT_DROP_CNT SCI_ADDR(ANA_REGS_GLB_BASE, 0x0198) +#define ANA_REG_GLB_DCDC_DISCHRG SCI_ADDR(ANA_REGS_GLB_BASE, 0x019C) +#define ANA_REG_GLB_DCDC_CORE_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0200) +#define ANA_REG_GLB_DCDC_ARM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0204) +#define ANA_REG_GLB_DCDC_MEM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0208) +#define ANA_REG_GLB_DCDC_GEN_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x020C) +#define ANA_REG_GLB_DCDC_WPA_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0210) +#define ANA_REG_GLB_DCDC_WPA_DCM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0214) +#define ANA_REG_GLB_DCDC_CON_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0218) +#define ANA_REG_GLB_DCDC_RF_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x021C) + +/* bits definitions for register ANA_REG_GLB_ARM_MODULE_EN */ +#define BIT_ANA_IMPD_ADC_EN ( BIT(12) ) +#define BIT_ANA_THM_EN ( BIT(11) ) +#define BIT_ANA_BLTC_EN ( BIT(10) ) +#define BIT_ANA_PINREG_EN ( BIT(9) ) +#define BIT_ANA_FGU_EN ( BIT(8) ) +#define BIT_ANA_EFS_EN ( BIT(7) ) +#define BIT_ANA_ADC_EN ( BIT(6) ) +#define BIT_ANA_HDT_EN ( BIT(5) ) +#define BIT_ANA_AUD_EN ( BIT(4) ) +#define BIT_ANA_EIC_EN ( BIT(3) ) +#define BIT_ANA_WDG_EN ( BIT(2) ) +#define BIT_ANA_RTC_EN ( BIT(1) ) +#define BIT_ANA_CAL_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_ARM_CLK_EN */ +#define BIT_CLK_IMPD_ADC_EN ( BIT(10) ) +#define BIT_CLK_AUXAD_EN ( BIT(9) ) +#define BIT_CLK_AUXADC_EN ( BIT(8) ) +#define BITS_CLK_CAL_SRC_SEL(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BIT_CLK_CAL_EN ( BIT(5) ) +#define BIT_CLK_AUD_HID_EN ( BIT(4) ) +#define BIT_CLK_AUD_HBD_EN ( BIT(3) ) +#define BIT_CLK_AUD_LOOP_EN ( BIT(2) ) +#define BIT_CLK_AUD_6P5M_EN ( BIT(1) ) +#define BIT_CLK_AUDIF_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_RTC_CLK_EN */ +#define BIT_RTC_EFS_EN ( BIT(12) ) +#define BIT_RTC_THMA_AUTO_EN ( BIT(11) ) +#define BIT_RTC_THMA_EN ( BIT(10) ) +#define BIT_RTC_THM_EN ( BIT(9) ) +#define BIT_RTC_BLTC_EN ( BIT(8) ) +#define BIT_RTC_FGU_EN ( BIT(7) ) +#define BIT_RTC_FGUA_EN ( BIT(6) ) +#define BIT_RTC_VIBR_EN ( BIT(5) ) +#define BIT_RTC_AUD_EN ( BIT(4) ) +#define BIT_RTC_EIC_EN ( BIT(3) ) +#define BIT_RTC_WDG_EN ( BIT(2) ) +#define BIT_RTC_RTC_EN ( BIT(1) ) +#define BIT_RTC_ARCH_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_ARM_RST */ +#define BIT_ANA_THMA_SOFT_RST ( BIT(15) ) +#define BIT_ANA_THM_SOFT_RST ( BIT(14) ) +#define BIT_ANA_BLTC_SOFT_RST ( BIT(13) ) +#define BIT_ANA_AUD_32K_SOFT_RST ( BIT(12) ) +#define BIT_ANA_AUDTX_SOFT_RST ( BIT(11) ) +#define BIT_ANA_AUDRX_SOFT_RST ( BIT(10) ) +#define BIT_ANA_AUD_SOFT_RST ( BIT(9) ) +#define BIT_ANA_AUD_HDT_SOFT_RST ( BIT(8) ) +#define BIT_ANA_EFS_SOFT_RST ( BIT(7) ) +#define BIT_ANA_ADC_SOFT_RST ( BIT(6) ) +#define BIT_ANA_PWM0_SOFT_RST ( BIT(5) ) +#define BIT_ANA_FGU_SOFT_RST ( BIT(4) ) +#define BIT_ANA_EIC_SOFT_RST ( BIT(3) ) +#define BIT_ANA_WDG_SOFT_RST ( BIT(2) ) +#define BIT_ANA_RTC_SOFT_RST ( BIT(1) ) +#define BIT_ANA_CAL_SOFT_RST ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_DCDC_PD */ +#define BIT_LDO_EMM_PD ( BIT(15) ) +#define BIT_DCDC_TOPCLK6M_PD ( BIT(14) ) +#define BIT_DCDC_RF_PD ( BIT(13) ) +#define BIT_DCDC_GEN_PD ( BIT(12) ) +#define BIT_DCDC_MEM_PD ( BIT(11) ) +#define BIT_DCDC_ARM_PD ( BIT(10) ) +#define BIT_DCDC_CORE_PD ( BIT(9) ) +#define BIT_LDO_RF0_PD ( BIT(8) ) +#define BIT_LDO_EMMCCORE_PD ( BIT(7) ) +#define BIT_LDO_GEN1_PD ( BIT(6) ) +#define BIT_LDO_DCXO_PD ( BIT(5) ) +#define BIT_LDO_GEN0_PD ( BIT(4) ) +#define BIT_LDO_VDD25_PD ( BIT(3) ) +#define BIT_LDO_VDD28_PD ( BIT(2) ) +#define BIT_LDO_VDD18_PD ( BIT(1) ) +#define BIT_BG_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_PD_CTRL */ +#define BIT_LDO_LPREF_PD_SW ( BIT(15) ) +#define BIT_DCDC_WPA_PD ( BIT(14) ) +#define BIT_DCDC_CON_PD ( BIT(13) ) +#define BIT_LDO_WIFIPA_PD ( BIT(11) ) +#define BIT_LDO_SDCORE_PD ( BIT(10) ) +#define BIT_LDO_USB_PD ( BIT(8) ) +#define BIT_LDO_CAMMOT_PD ( BIT(7) ) +#define BIT_LDO_CAMIO_PD ( BIT(6) ) +#define BIT_LDO_CAMD_PD ( BIT(5) ) +#define BIT_LDO_CAMA_PD ( BIT(4) ) +#define BIT_LDO_SIM2_PD ( BIT(3) ) +#define BIT_LDO_SIM1_PD ( BIT(2) ) +#define BIT_LDO_SIM0_PD ( BIT(1) ) +#define BIT_LDO_SDIO_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL0 */ +#define BITS_LDO_RF0_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_WIFIPA_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL1 */ +#define BITS_LDO_CAMIO_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_CAMD_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL2 */ +#define BITS_LDO_GEN0_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL3 */ +#define BITS_LDO_GEN1_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_VDD28_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL4 */ +#define BITS_LDO_SIM0_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_SDIO_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL5 */ +#define BITS_LDO_SIM2_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_SIM1_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL6 */ +#define BITS_LDO_SDCORE_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_CAMA_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL7 */ +#define BITS_LDO_EMMCCORE_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_CAMMOT_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL8 */ +#define BITS_LDO_DCXO_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_DCXO_LP_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL9 */ +#define BITS_LDO_VDD18_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_USB_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL10 */ +#define BITS_LDO_VDD25_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL11 */ +#define BITS_VBATBK_V(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_LDOB_CAL_SEL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_LDOA_CAL_SEL (_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_LDOD_CAL_SEL(_x_) ( (_x_) << 3 & (BIT(3)|BIT(4)) ) +#define BITS_LDODCDC_CAL_SEL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_LP_CTRL */ +#define BITS_LDOB_LP_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDOA_LP_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDODCDC_LP_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL0 */ +#define BITS_DCDC_CORE_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_CORE_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_CORE_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_CORE_QKRSPS ( BIT(3) ) +#define BIT_DCDC_CORE_PFM ( BIT(2) ) +#define BIT_DCDC_CORE_DCM ( BIT(1) ) +#define BIT_DCDC_CORE_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL1 */ +#define BITS_DCDC_MEM_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_MEM_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_MEM_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_MEM_QKRSPS ( BIT(3) ) +#define BIT_DCDC_MEM_PFM ( BIT(2) ) +#define BIT_DCDC_MEM_DCM ( BIT(1) ) +#define BIT_DCDC_MEM_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL2 */ +#define BITS_DCDC_GEN_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_GEN_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_GEN_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_GEN_QKRSPS ( BIT(3) ) +#define BIT_DCDC_GEN_PFM ( BIT(2) ) +#define BIT_DCDC_GEN_DCM ( BIT(1) ) +#define BIT_DCDC_GEN_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL3 */ +#define BITS_DCDC_ARM_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_ARM_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_ARM_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_ARM_QKRSPS ( BIT(3) ) +#define BIT_DCDC_ARM_PFM ( BIT(2) ) +#define BIT_DCDC_ARM_DCM ( BIT(1) ) +#define BIT_DCDC_ARM_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL4 */ +#define BITS_DCDC_WPA_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_WPA_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_WPA_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_WPA_QKRSPS ( BIT(3) ) +#define BIT_DCDC_WPA_PFM ( BIT(2) ) +#define BIT_DCDC_WPA_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL5 */ +#define BITS_DCDC_RF_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_RF_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_RF_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_RF_QKRSPS ( BIT(3) ) +#define BIT_DCDC_RF_PFM ( BIT(2) ) +#define BIT_DCDC_RF_DCM ( BIT(1) ) +#define BIT_DCDC_RF_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL6 */ +#define BITS_DCDC_CON_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_CON_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_CON_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_CON_QKRSPS ( BIT(3) ) +#define BIT_DCDC_CON_PFM ( BIT(2) ) +#define BIT_DCDC_CON_DCM ( BIT(1) ) +#define BIT_DCDC_CON_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL7 */ +#define BITS_DCDC_MEM_CF(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_DCDC_MEM_PFMAD(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_DCDC_MEM_CL_CTRL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_DCDC_CORE_DUALSEL ( BIT(7) ) +#define BIT_DCDC_CORE_MERGEEN ( BIT(6) ) +#define BITS_DCDC_CORE_CF(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_DCDC_CORE_PFMAD(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DCDC_CORE_CL_CTRL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL8 */ +#define BIT_DCDC_ARM_DUALSEL ( BIT(15) ) +#define BIT_DCDC_ARM_MERGEEN ( BIT(14) ) +#define BITS_DCDC_ARM_CF(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_DCDC_ARM_PFMAD(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_DCDC_ARM_CL_CTRL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_DCDC_GEN_CF(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_DCDC_GEN_PFMAD(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DCDC_GEN_CL_CTRL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL9 */ +#define BIT_DCDC_CON_MERGEEN ( BIT(14) ) +#define BITS_DCDC_CON_CF(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_DCDC_CON_PFMAD(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_DCDC_CON_CL_CTRL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_DCDC_RF_MERGEEN ( BIT(6) ) +#define BITS_DCDC_RF_CF(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_DCDC_RF_PFMAD(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DCDC_RF_CL_CTRL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL10 */ +#define BIT_DCDC_WPA_BPOUT_SOFTW ( BIT(15) ) +#define BITS_DCDC_WPA_VBAT_DIV(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BIT_DCDC_WPA_BPEN ( BIT(11) ) +#define BIT_DCDC_WPA_BPMODE ( BIT(10) ) +#define BIT_DCDC_WPA_DEGEN ( BIT(9) ) +#define BIT_DCDC_WPA_APTEN ( BIT(8) ) +#define BITS_DCDC_WPA_DEBC_SEL(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_DCDC_WPA_CF(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_DCDC_WPA_PFMAD(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DCDC_WPA_CL_CTRL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL11 */ +#define BIT_DCDC_3MCLKCAL_EN ( BIT(13) ) +#define BIT_DCDC_2MCLKCAL_EN ( BIT(12) ) +#define BITS_DCDC_6MFRECAL_SW(_x_) ( (_x_) << 7 & (BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DCDC_4MFRECAL_SW(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_DCDC_CLK_SP_SEL ( BIT(1) ) +#define BIT_DCDC_CLK_SP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL12 */ +#define BIT_DCDC_CORE_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_CORE_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_CORE_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_CORE_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_ARM_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_ARM_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_ARM_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_ARM_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL13 */ +#define BIT_DCDC_MEM_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_MEM_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_MEM_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_MEM_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_GEN_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_GEN_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_GEN_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_GEN_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL14 */ +#define BIT_DCDC_WPA_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_WPA_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_WPA_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_WPA_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_RF_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_RF_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_RF_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_RF_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL15 */ +#define BITS_DCDC_CAL_SEL(_x_) ( (_x_) << 13 & (BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_DCDC_CON_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_CON_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_CON_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_CON_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_SLP_WAIT_DCDCARM */ +#define BITS_SLP_IN_WAIT_DCDCARM(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_SLP_OUT_WAIT_DCDCARM(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL0 */ +#define BIT_SLP_IO_EN ( BIT(15) ) +#define BIT_SLP_DCDCRF_PD_EN ( BIT(13) ) +#define BIT_SLP_DCDCCON_PD_EN ( BIT(12) ) +#define BIT_SLP_DCDCGEN_PD_EN ( BIT(11) ) +#define BIT_SLP_DCDCWPA_PD_EN ( BIT(10) ) +#define BIT_SLP_DCDCARM_PD_EN ( BIT(9) ) +#define BIT_SLP_LDOVDD25_PD_EN ( BIT(8) ) +#define BIT_SLP_LDORF0_PD_EN ( BIT(7) ) +#define BIT_SLP_LDOEMMCCORE_PD_EN ( BIT(6) ) +#define BIT_SLP_LDOGEN0_PD_EN ( BIT(5) ) +#define BIT_SLP_LDODCXO_PD_EN ( BIT(4) ) +#define BIT_SLP_LDOGEN1_PD_EN ( BIT(3) ) +#define BIT_SLP_LDOWIFIPA_PD_EN ( BIT(2) ) +#define BIT_SLP_LDOVDD28_PD_EN ( BIT(1) ) +#define BIT_SLP_LDOVDD18_PD_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL1 */ +#define BIT_SLP_LDO_PD_EN ( BIT(15) ) +#define BIT_SLP_LDOLPREF_PD_EN ( BIT(14) ) +#define BIT_SLP_LDOSDCORE_PD_EN ( BIT(9) ) +#define BIT_SLP_LDOUSB_PD_EN ( BIT(8) ) +#define BIT_SLP_LDOCAMMOT_PD_EN ( BIT(7) ) +#define BIT_SLP_LDOCAMIO_PD_EN ( BIT(6) ) +#define BIT_SLP_LDOCAMD_PD_EN ( BIT(5) ) +#define BIT_SLP_LDOCAMA_PD_EN ( BIT(4) ) +#define BIT_SLP_LDOSIM2_PD_EN ( BIT(3) ) +#define BIT_SLP_LDOSIM1_PD_EN ( BIT(2) ) +#define BIT_SLP_LDOSIM0_PD_EN ( BIT(1) ) +#define BIT_SLP_LDOSDIO_PD_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL2 */ +#define BIT_SLP_DCDCRF_LP_EN ( BIT(14) ) +#define BIT_SLP_DCDCCON_LP_EN ( BIT(13) ) +#define BIT_SLP_DCDCCORE_LP_EN ( BIT(12) ) +#define BIT_SLP_DCDCMEM_LP_EN ( BIT(11) ) +#define BIT_SLP_DCDCARM_LP_EN ( BIT(10) ) +#define BIT_SLP_DCDCGEN_LP_EN ( BIT(9) ) +#define BIT_SLP_DCDCWPA_LP_EN ( BIT(8) ) +#define BIT_SLP_LDORF0_LP_EN ( BIT(7) ) +#define BIT_SLP_LDOEMMCCORE_LP_EN ( BIT(6) ) +#define BIT_SLP_LDOGEN0_LP_EN ( BIT(5) ) +#define BIT_SLP_LDODCXO_LP_EN ( BIT(4) ) +#define BIT_SLP_LDOGEN1_LP_EN ( BIT(3) ) +#define BIT_SLP_LDOWIFIPA_LP_EN ( BIT(2) ) +#define BIT_SLP_LDOVDD28_LP_EN ( BIT(1) ) +#define BIT_SLP_LDOVDD18_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL3 */ +#define BIT_SLP_BG_LP_EN ( BIT(15) ) +#define BIT_LDOVDD25_LP_EN_SW ( BIT(14) ) +#define BIT_LDOSDCORE_LP_EN_SW ( BIT(13) ) +#define BIT_LDOUSB_LP_EN_SW ( BIT(12) ) +#define BIT_SLP_LDOVDD25_LP_EN ( BIT(10) ) +#define BIT_SLP_LDOSDCORE_LP_EN ( BIT(9) ) +#define BIT_SLP_LDOUSB_LP_EN ( BIT(8) ) +#define BIT_SLP_LDOCAMMOT_LP_EN ( BIT(7) ) +#define BIT_SLP_LDOCAMIO_LP_EN ( BIT(6) ) +#define BIT_SLP_LDOCAMD_LP_EN ( BIT(5) ) +#define BIT_SLP_LDOCAMA_LP_EN ( BIT(4) ) +#define BIT_SLP_LDOSIM2_LP_EN ( BIT(3) ) +#define BIT_SLP_LDOSIM1_LP_EN ( BIT(2) ) +#define BIT_SLP_LDOSIM0_LP_EN ( BIT(1) ) +#define BIT_SLP_LDOSDIO_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL4 */ +#define BIT_LDOCAMIO_LP_EN_SW ( BIT(15) ) +#define BIT_LDOCAMMOT_LP_EN_SW ( BIT(14) ) +#define BIT_LDOCAMD_LP_EN_SW ( BIT(13) ) +#define BIT_LDOCAMA_LP_EN_SW ( BIT(12) ) +#define BIT_LDOSIM2_LP_EN_SW ( BIT(11) ) +#define BIT_LDOSIM1_LP_EN_SW ( BIT(10) ) +#define BIT_LDOSIM0_LP_EN_SW ( BIT(9) ) +#define BIT_LDOSDIO_LP_EN_SW ( BIT(8) ) +#define BIT_LDORF0_LP_EN_SW ( BIT(7) ) +#define BIT_LDOEMMCCORE_LP_EN_SW ( BIT(6) ) +#define BIT_LDOGEN0_LP_EN_SW ( BIT(5) ) +#define BIT_LDODCXO_LP_EN_SW ( BIT(4) ) +#define BIT_LDOGEN1_LP_EN_SW ( BIT(3) ) +#define BIT_LDOWIFIPA_LP_EN_SW ( BIT(2) ) +#define BIT_LDOVDD28_LP_EN_SW ( BIT(1) ) +#define BIT_LDOVDD18_LP_EN_SW ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_AUD_SLP_CTRL */ +#define BIT_SLP_AUD_PMUR1_PD_EN ( BIT(14) ) +#define BIT_SLP_AUD_PA_SW_PD_EN ( BIT(13) ) +#define BIT_SLP_AUD_PA_LDO_PD_EN ( BIT(12) ) +#define BIT_SLP_AUD_PA_PD_EN ( BIT(11) ) +#define BIT_SLP_AUD_OVP_PD_PD_EN ( BIT(10) ) +#define BIT_SLP_AUD_OVP_LDO_PD_EN ( BIT(9) ) +#define BIT_SLP_AUD_LDOCG_PD_PD_EN ( BIT(8) ) +#define BIT_SLP_AUD_VB_PD_EN ( BIT(7) ) +#define BIT_SLP_AUD_VBO_PD_EN ( BIT(6) ) +#define BIT_SLP_AUD_HEADMICBIAS_PD_EN ( BIT(5) ) +#define BIT_SLP_AUD_HEADMIC_SLEEP_PD_EN ( BIT(4) ) +#define BIT_SLP_AUD_PLGPD_PD_EN ( BIT(3) ) +#define BIT_SLP_AUD_VB_NLEAK_PD ( BIT(2) ) +#define BITS_SLP_AUD_PMUR0_PD_EN(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL0 */ +#define BITS_SLP_DCDCCORE_VOL_DROP_CNT(_x_)( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_PWR_OFF_SEQ_EN ( BIT(2) ) +#define BIT_DCDC_CORE_SLP_OUT_STEP_EN ( BIT(1) ) +#define BIT_DCDC_CORE_SLP_IN_STEP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL1 */ +#define BITS_DCDC_CORE_CAL_DS_SW(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CTRL_DS_SW(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL2 */ +#define BITS_DCDC_CORE_CTRL_SLP_STEP3(_x_)( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_DCDC_CORE_CTRL_SLP_STEP2(_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CTRL_SLP_STEP1(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL3 */ +#define BITS_DCDC_CORE_CTRL_SLP_STEP5(_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CTRL_SLP_STEP4(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL4 */ +#define BITS_DCDC_CORE_CAL_SLP_STEP3(_x_)( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_DCDC_CORE_CAL_SLP_STEP2(_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CAL_SLP_STEP1(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL5 */ +#define BITS_DCDC_CORE_CAL_SLP_STEP5(_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CAL_SLP_STEP4(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SEL */ +#define BIT_LDO_GEN0_SW_SEL ( BIT(13) ) +#define BIT_LDO_GEN1_SW_SEL ( BIT(12) ) +#define BIT_LDO_RF0_SW_SEL ( BIT(11) ) +#define BIT_LDO_VDD18_SW_SEL ( BIT(10) ) +#define BIT_LDO_VDD28_SW_SEL ( BIT(9) ) +#define BIT_LDO_DCXO_SW_SEL ( BIT(8) ) +#define BIT_LDO_EMMCCORE_SW_SEL ( BIT(7) ) +#define BIT_LDO_VDD25_SW_SEL ( BIT(6) ) +#define BIT_DCDC_RF_SW_SEL ( BIT(5) ) +#define BIT_DCDC_GEN_SW_SEL ( BIT(4) ) +#define BIT_DCDC_MEM_SW_SEL ( BIT(3) ) +#define BIT_DCDC_ARM_SW_SEL ( BIT(2) ) +#define BIT_DCDC_CORE_SLP_SW_SEL ( BIT(1) ) +#define BIT_DCDC_CORE_NOR_SW_SEL ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN0 */ +#define BIT_LDO_XTL_EN ( BIT(15) ) +#define BIT_LDO_GEN0_EXT_XTL0_EN ( BIT(14) ) +#define BIT_LDO_GEN0_XTL1_EN ( BIT(13) ) +#define BIT_LDO_GEN0_XTL0_EN ( BIT(12) ) +#define BIT_LDO_GEN1_EXT_XTL0_EN ( BIT(11) ) +#define BIT_LDO_GEN1_XTL1_EN ( BIT(10) ) +#define BIT_LDO_GEN1_XTL0_EN ( BIT(9) ) +#define BIT_LDO_DCXO_EXT_XTL0_EN ( BIT(8) ) +#define BIT_LDO_DCXO_XTL1_EN ( BIT(7) ) +#define BIT_LDO_DCXO_XTL0_EN ( BIT(6) ) +#define BIT_LDO_VDD18_EXT_XTL0_EN ( BIT(5) ) +#define BIT_LDO_VDD18_XTL1_EN ( BIT(4) ) +#define BIT_LDO_VDD18_XTL0_EN ( BIT(3) ) +#define BIT_LDO_VDD28_EXT_XTL0_EN ( BIT(2) ) +#define BIT_LDO_VDD28_XTL1_EN ( BIT(1) ) +#define BIT_LDO_VDD28_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN1 */ +#define BIT_LDO_RF0_EXT_XTL0_EN ( BIT(14) ) +#define BIT_LDO_RF0_XTL1_EN ( BIT(13) ) +#define BIT_LDO_RF0_XTL0_EN ( BIT(12) ) +#define BIT_LDO_WIFIPA_EXT_XTL0_EN ( BIT(11) ) +#define BIT_LDO_WIFIPA_XTL1_EN ( BIT(10) ) +#define BIT_LDO_WIFIPA_XTL0_EN ( BIT(9) ) +#define BIT_LDO_SIM2_EXT_XTL0_EN ( BIT(8) ) +#define BIT_LDO_SIM2_XTL1_EN ( BIT(7) ) +#define BIT_LDO_SIM2_XTL0_EN ( BIT(6) ) +#define BIT_LDO_SIM1_EXT_XTL0_EN ( BIT(5) ) +#define BIT_LDO_SIM1_XTL1_EN ( BIT(4) ) +#define BIT_LDO_SIM1_XTL0_EN ( BIT(3) ) +#define BIT_LDO_SIM0_EXT_XTL0_EN ( BIT(2) ) +#define BIT_LDO_SIM0_XTL1_EN ( BIT(1) ) +#define BIT_LDO_SIM0_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN2 */ +#define BIT_LDO_VDD25_EXT_XTL0_EN ( BIT(11) ) +#define BIT_LDO_VDD25_XTL1_EN ( BIT(10) ) +#define BIT_LDO_VDD25_XTL0_EN ( BIT(9) ) +#define BIT_DCDC_RF_EXT_XTL0_EN ( BIT(8) ) +#define BIT_DCDC_RF_XTL1_EN ( BIT(7) ) +#define BIT_DCDC_RF_XTL0_EN ( BIT(6) ) +#define BIT_XO_EXT_XTL0_EN ( BIT(5) ) +#define BIT_XO_XTL1_EN ( BIT(4) ) +#define BIT_XO_XTL0_EN ( BIT(3) ) +#define BIT_BG_EXT_XTL0_EN ( BIT(2) ) +#define BIT_BG_XTL1_EN ( BIT(1) ) +#define BIT_BG_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN3 */ +#define BIT_DCDC_CON_EXT_XTL0_EN ( BIT(14) ) +#define BIT_DCDC_CON_XTL1_EN ( BIT(13) ) +#define BIT_DCDC_CON_XTL0_EN ( BIT(12) ) +#define BIT_DCDC_WPA_EXT_XTL0_EN ( BIT(11) ) +#define BIT_DCDC_WPA_XTL1_EN ( BIT(10) ) +#define BIT_DCDC_WPA_XTL0_EN ( BIT(9) ) +#define BIT_DCDC_MEM_EXT_XTL0_EN ( BIT(8) ) +#define BIT_DCDC_MEM_XTL1_EN ( BIT(7) ) +#define BIT_DCDC_MEM_XTL0_EN ( BIT(6) ) +#define BIT_DCDC_GEN_EXT_XTL0_EN ( BIT(5) ) +#define BIT_DCDC_GEN_XTL1_EN ( BIT(4) ) +#define BIT_DCDC_GEN_XTL0_EN ( BIT(3) ) +#define BIT_DCDC_CORE_EXT_XTL0_EN ( BIT(2) ) +#define BIT_DCDC_CORE_XTL1_EN ( BIT(1) ) +#define BIT_DCDC_CORE_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_32KLESS_CTRL0 */ +#define BIT_RC_MODE_WR_ACK_FLAG ( BIT(14) ) +#define BIT_XO_LOW_CUR_FLAG ( BIT(13) ) +#define BIT_XO_LOW_CUR_FRC_RTCSET ( BIT(12) ) +#define BIT_XO_LOW_CUR_FRC_RTCCLR ( BIT(11) ) +#define BIT_RC_MODE_WR_ACK_FLAG_CLR ( BIT(10) ) +#define BIT_XO_LOW_CUR_FLAG_CLR ( BIT(9) ) +#define BIT_XO_LOW_CUR_CNT_CLR ( BIT(8) ) +#define BIT_LDO_DCXO_LP_PD_RTCSET ( BIT(7) ) +#define BIT_LDO_DCXO_LP_PD_RTCCLR ( BIT(6) ) +#define BIT_SLP_XO_LOW_CUR_EN ( BIT(5) ) +#define BIT_XO_LOW_CUR_EN ( BIT(3) ) +#define BIT_EXT_32K_PD ( BIT(2) ) +#define BIT_RC_32K_SEL ( BIT(1) ) +#define BIT_RC_32K_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_32KLESS_CTRL1 */ +#define BITS_RC_MODE(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_32KLESS_CTRL2 */ +#define BITS_XO_LOW_CUR_CNT_LOW(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_32KLESS_CTRL3 */ +#define BITS_XO_LOW_CUR_CNT_HIGH(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_AUXAD_CTL */ +#define BIT_AUXAD_CURRENTSEN_EN ( BIT(6) ) +#define BIT_AUXAD_CURRENTSEL ( BIT(5) ) +#define BITS_AUXAD_CURRENT_IBS(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_XTL_WAIT_CTRL */ +#define BIT_SLP_XTLBUF_PD_EN ( BIT(9) ) +#define BIT_XTL_EN ( BIT(8) ) +#define BITS_XTL_WAIT(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_RGB_CTRL */ +#define BIT_RTC_PWM0_EN ( BIT(15) ) +#define BIT_PWM0_EN ( BIT(14) ) +#define BIT_IB_REX_EN ( BIT(12) ) +#define BIT_IB_TRIM_EM_SEL ( BIT(11) ) +#define BITS_RGB_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) ) +#define BIT_SLP_RGB_PD_EN ( BIT(2) ) +#define BIT_RGB_PD_HW_EN ( BIT(1) ) +#define BIT_RGB_PD_SW ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_WHTLED_CTRL */ +#define BITS_IB_TRIM(_x_) ( (_x_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_WHTLED_SERIES_EN ( BIT(8) ) +#define BIT_WHTLED_PD_SEL ( BIT(7) ) +#define BIT_WHTLED_BOOST_EN ( BIT(8) ) +#define BITS_WHTLED_V(_x_) ( (_x_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_WHTLED_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_KPLED_CTRL */ +#define BITS_KPLED_V(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_KPLED_PD ( BIT(11) ) +#define BIT_KPLED_PULLDOWN_EN ( BIT(10) ) +#define BIT_SLP_LDOKPLED_PD_EN ( BIT(9) ) +#define BIT_LDO_KPLED_PD ( BIT(8) ) +#define BITS_LDO_KPLED_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_VIBR_CTRL0 */ +#define BITS_CUR_DRV_CAL_SEL(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BIT_VIBR_PULLDOWN_EN ( BIT(11) ) +#define BIT_VIBR_PULLUP_EN ( BIT(10) ) +#define BIT_SLP_LDOVIBR_PD_EN ( BIT(9) ) +#define BIT_LDO_VIBR_PD ( BIT(8) ) +#define BITS_LDO_VIBR_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_AUDIO_CTRL0 */ +#define BIT_AUD_SLP_APP_RST_EN ( BIT(15) ) +#define BITS_CLK_AUD_HBD_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_CLK_AUD_LOOP_INV_EN ( BIT(4) ) +#define BIT_CLK_AUDIF_TX_INV_EN ( BIT(3) ) +#define BIT_CLK_AUDIF_RX_INV_EN ( BIT(2) ) +#define BIT_CLK_AUD_6P5M_TX_INV_EN ( BIT(1) ) +#define BIT_CLK_AUD_6P5M_RX_INV_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_AUDIO_CTRL1 */ +#define BIT_IMPD_ADC_SOFT_RST ( BIT(7) ) +#define BIT_HEAD_INSERT_EIC_EN ( BIT(6) ) +#define BIT_AUDIO_CHP_CLK_DIV_EN ( BIT(5) ) +#define BITS_AUDIO_CHP_CLK_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL0 */ +#define BIT_CHGLDO_DIS ( BIT(15) ) +#define BITS_CHGR_CV_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CHGR_END_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BIT_CHGR_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL1 */ +#define BITS_CHGR_CC_I(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_VBAT_OVP_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_VCHG_OVP_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL2 */ +#define BIT_CHGR_INT_EN ( BIT(15) ) +#define BIT_CHGR_DRV ( BIT(7) ) +#define BIT_CHGR_OSC ( BIT(6) ) +#define BITS_CHGR_DPM(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CHGR_ITERM(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BIT_CHGR_CC_EN ( BIT(1) ) +#define BIT_RECHG ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_DET_FGU_CTRL */ +#define BIT_FGUA_SOFT_RST ( BIT(13) ) +#define BIT_LDO_FGU_PD ( BIT(12) ) +#define BIT_SD_CHOP_CAP_EN ( BIT(8) ) +#define BITS_SD_CLK_P(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BIT_SD_DCOFFSET_EN ( BIT(5) ) +#define BIT_SD_CHOP_EN ( BIT(4) ) +#define BIT_DP_DM_AUX_EN ( BIT(1) ) +#define BIT_DP_DM_SW_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_STATUS */ +#define BIT_CHG_DET_DONE ( BIT(11) ) +#define BIT_DP_LOW ( BIT(10) ) +#define BIT_DCP_DET ( BIT(9) ) +#define BIT_CHG_DET ( BIT(8) ) +#define BIT_SDP_INT ( BIT(7) ) +#define BIT_DCP_INT ( BIT(6) ) +#define BIT_CDP_INT ( BIT(5) ) +#define BIT_CHGR_CV_STATUS ( BIT(4) ) +#define BIT_CHGR_ON ( BIT(3) ) +#define BIT_CHGR_INT ( BIT(2) ) +#define BIT_VBAT_OVI ( BIT(1) ) +#define BIT_VCHG_OVI ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_MIXED_CTRL0 */ +#define BIT_PTEST_PD_RTCSET ( BIT(15) ) +#define BIT_DCDC_V_CTRL_MODE ( BIT(14) ) +#define BIT_LDO_RAMP_EN ( BIT(13) ) +#define BIT_BG_LP_EN ( BIT(12) ) +#define BITS_VBAT_CRASH_V(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BIT_OVLO_EN ( BIT(9) ) +#define BITS_OVLO_CAL(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_OVLO_V(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_OVLO_T(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_MIXED_CTRL1 */ +#define BITS_XOSC32K_CTL(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_BATON_T(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BIT_BATDET_LDO_SEL ( BIT(9) ) +#define BIT_THM_CHIP_PD_FLAG ( BIT(8) ) +#define BIT_THM_CHIP_PD_FLAG_CLR ( BIT(7) ) +#define BITS_THM_CAL_SEL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)) ) +#define BIT_THM_AUTO_PD_EN ( BIT(4) ) +#define BIT_ALL_GPI_DEB ( BIT(3) ) +#define BIT_GPI_DEBUG_EN ( BIT(2) ) +#define BIT_ALL_INT_DEB ( BIT(1) ) +#define BIT_INT_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_SWRST_CTRL */ +#define BIT_POR_RTC_PD ( BIT(15) ) +#define BITS_POR_RTC_I(_x_) ( (_x_) << 13 & (BIT(13)|BIT(14)) ) +#define BIT_SW_RST_GEN1_PD_EN ( BIT(12) ) +#define BIT_SW_RST_GEN0_PD_EN ( BIT(11) ) +#define BIT_EXT_RSTN_PD_EN ( BIT(10) ) +#define BIT_PB_7S_RST_PD_EN ( BIT(9) ) +#define BIT_SW_RST_EMMCCORE_PD_EN ( BIT(8) ) +#define BIT_KEY2_7S_RST_EN ( BIT(7) ) +#define BIT_WDG_RST_PD_EN ( BIT(6) ) +#define BITS_SW_RST_PD_THRESHOLD(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register ANA_REG_GLB_POR_RST_MONITOR */ +#define BITS_POR_RST_MONITOR(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_WDG_RST_MONITOR */ +#define BITS_WDG_RST_MONITOR(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_POR_PIN_RST_MONITOR */ +#define BITS_POR_PIN_RST_MONITOR(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_POR_SRC_FLAG */ +#define BIT_POR_SW_FORCE_ON ( BIT(15) ) +#define BITS_POR_SRC_FLAG(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_POR_7S_CTRL */ +#define BIT_PBINT_7S_FLAG_CLR ( BIT(15) ) +#define BIT_EXT_RSTN_FLAG_CLR ( BIT(14) ) +#define BIT_CHGR_INT_FLAG_CLR ( BIT(13) ) +#define BIT_PBINT2_FLAG_CLR ( BIT(12) ) +#define BIT_PBINT_FLAG_CLR ( BIT(11) ) +#define BIT_PBINT_7S_RST_SWMODE ( BIT(8) ) +#define BITS_PBINT_7S_RST_THRESHOLD(_x_)( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_PBINT_7S_AUTO_ON_EN ( BIT(2) ) +#define BIT_PBINT_7S_RST_DISABLE ( BIT(1) ) +#define BIT_PBINT_7S_RST_MODE ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_HWRST_RTC */ +#define BITS_HWRST_RTC_REG_STS(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_HWRST_RTC_REG_SET(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_CHIP_ID_LOW */ +#define BITS_CHIP_ID_LOW(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_CHIP_ID_HIGH */ +#define BITS_CHIP_ID_HIGH(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_ARM_MF_REG */ +#define BITS_ARM_MF_REG(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_ARCH_EN */ +#define BIT_ARCH_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_MCU_WR_PROT_VALUE */ +#define BIT_MCU_WR_PROT ( BIT(15) ) +#define BITS_MCU_WR_PROT_VALUE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_PWR_WR_PROT_VALUE */ +#define BIT_PWR_WR_PROT ( BIT(15) ) +#define BITS_PWR_WR_PROT_VALUE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_SMPL_CTRL0 */ +#define BITS_SMPL_MODE(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_SMPL_CTRL1 */ +#define BIT_SMPL_PWR_ON_FLAG ( BIT(15) ) +#define BIT_SMPL_MODE_WR_ACK_FLAG ( BIT(14) ) +#define BIT_SMPL_PWR_ON_FLAG_CLR ( BIT(13) ) +#define BIT_SMPL_MODE_WR_ACK_FLAG_CLR ( BIT(12) ) +#define BIT_SMPL_PWR_ON_SET ( BIT(11) ) +#define BIT_SMPL_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_RTC_RST0 */ +#define BITS_RTC_CLK_FLAG_SET(_x_) ( (_x_) << 15 & (BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_RTC_RST1 */ +#define BITS_RTC_CLK_FLAG_CLR(_x_) ( (_x_) << 15 & (BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_RTC_RST2 */ +#define BITS_RTC_CLK_FLAG_RTC(_x_) ( (_x_) << 15 & (BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SHPT_PD1 */ +#define BIT_LDO_USB_SHPT_PD ( BIT(12) ) +#define BIT_LDO_DCXO_SHPT_PD ( BIT(11) ) +#define BIT_LDO_WIFIPA_SHPT_PD ( BIT(10) ) +#define BIT_LDO_VDD25_SHPT_PD ( BIT(9) ) +#define BIT_LDO_VDD28_SHPT_PD ( BIT(8) ) +#define BIT_LDO_SDIO_SHPT_PD ( BIT(7) ) +#define BIT_LDO_SDCORE_SHPT_PD ( BIT(6) ) +#define BIT_LDO_EMMCCORE_SHPT_PD ( BIT(5) ) +#define BIT_LDO_SIM2_SHPT_PD ( BIT(4) ) +#define BIT_LDO_SIM1_SHPT_PD ( BIT(3) ) +#define BIT_LDO_SIM0_SHPT_PD ( BIT(2) ) +#define BIT_LDO_CAMMOT_SHPT_PD ( BIT(1) ) +#define BIT_LDO_CAMA_SHPT_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SHPT_PD2 */ +#define BIT_LDO_RF0_SHPT_PD ( BIT(7) ) +#define BIT_LDO_GEN1_SHPT_PD ( BIT(6) ) +#define BIT_LDO_GEN0_SHPT_PD ( BIT(5) ) +#define BIT_LDO_CAMD_SHPT_PD ( BIT(4) ) +#define BIT_LDO_VDD18_SHPT_PD ( BIT(3) ) +#define BIT_LDO_CAMIO_SHPT_PD ( BIT(2) ) +#define BIT_LDO_KPLED_SHPT_PD ( BIT(1) ) +#define BIT_LDO_VIBR_SHPT_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_BATDET_CUR_CTRL */ +#define BIT_BATDET_CUR_EN ( BIT(4) ) +#define BITS_BATDET_CUR_I(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register ANA_REG_GLB_RTC_CLK_STOP */ +#define BIT_RTC_CLK_STOP_FLAG ( BIT(7) ) +#define BITS_RTC_CLK_STOP_THRESHOLD(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) + +/* bits definitions for register ANA_REG_GLB_VBAT_DROP_CNT */ +#define BITS_VBAT_DROP_CNT(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_DISCHRG */ +#define BITS_DCDC_ARM_DISCHRG(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_DCDC_CORE_DISCHRG(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_DCDC_MEM_DISCHRG(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_DCDC_GEN_DISCHRG(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_DCDC_RF_DISCHRG(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_DCDC_CON_DISCHRG(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DCDC_WPA_DISCHRG(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CORE_ADI */ +#define BITS_DCDC_CORE_CTL_SW_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CAL_SW_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_ARM_ADI */ +#define BITS_DCDC_ARM_CTL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_ARM_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_MEM_ADI */ +#define BITS_DCDC_MEM_CTRL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_MEM_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_GEN_ADI */ +#define BITS_DCDC_GEN_CTRL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_GEN_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_WPA_ADI */ +#define BITS_DCDC_WPA_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_WPA_DCM_ADI */ +#define BIT_DCDC_WPA_DCM_ADI ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CON_ADI */ +#define BITS_DCDC_CON_CTRL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CON_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_RF_ADI */ +#define BITS_DCDC_RF_CTRL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_RF_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* vars definitions for controller ANA_REGS_GLB */ + +#endif /* __ANA_REGS_GLB_H__ */ diff --git a/include/soc/sprd/chip_x35l64/__regs_aon_apb_rf.h b/include/soc/sprd/chip_x35l64/__regs_aon_apb_rf.h new file mode 100755 index 00000000..4c397d55 --- /dev/null +++ b/include/soc/sprd/chip_x35l64/__regs_aon_apb_rf.h @@ -0,0 +1,708 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + + + +#ifndef __H_REGS_AON_APB_RF_HEADFILE_H__ +#define __H_REGS_AON_APB_RF_HEADFILE_H__ __FILE__ + +#define REGS_AON_APB_RF + +/* registers definitions for AON_APB_RF */ +#define REG_AON_APB_APB_EB0 SCI_ADDR(REGS_AON_APB_BASE, 0x0000)/*AHB_EB0*/ +#define REG_AON_APB_APB_EB1 SCI_ADDR(REGS_AON_APB_BASE, 0x0004)/*AHB_EB1*/ +#define REG_AON_APB_APB_RST0 SCI_ADDR(REGS_AON_APB_BASE, 0x0008)/*AHB_RST0*/ +#define REG_AON_APB_APB_RST1 SCI_ADDR(REGS_AON_APB_BASE, 0x000C)/*AHB_RST1*/ +#define REG_AON_APB_APB_RTC_EB SCI_ADDR(REGS_AON_APB_BASE, 0x0010)/*APB_RTC_EB*/ +#define REG_AON_APB_REC_26MHZ_BUF_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0014)/*REC_26MHZ_BUF_CFG*/ +#define REG_AON_APB_SINDRV_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0018)/*SINDRV_CTRL*/ +#define REG_AON_APB_ADA_SEL_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x001C)/*ADA_SEL_CTRL*/ +#define REG_AON_APB_VBC_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0020)/*VBC_CTRL*/ +#define REG_AON_APB_PWR_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0024)/*PWR_CTRL*/ +#define REG_AON_APB_TS_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0028)/*TS_CFG*/ +#define REG_AON_APB_BOOT_MODE SCI_ADDR(REGS_AON_APB_BASE, 0x002C)/*BOOT_MODE*/ +#define REG_AON_APB_BB_BG_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0030)/*BB_BG_CTRL*/ +#define REG_AON_APB_CP_ARM_JTAG_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0034)/*CP_ARM_JTAG_CTRL*/ +#define REG_AON_APB_PLL_SOFT_CNT_DONE SCI_ADDR(REGS_AON_APB_BASE, 0x0038)/*PLL_SOFT_CNT_DONE*/ +#define REG_AON_APB_DCXO_LC_REG0 SCI_ADDR(REGS_AON_APB_BASE, 0x003C)/*DCXO_LC_REG0*/ +#define REG_AON_APB_DCXO_LC_REG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0040)/*DCXO_LC_REG1*/ +#define REG_AON_APB_MPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0044)/*MPLL_CFG1*/ +#define REG_AON_APB_MPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0048)/*MPLL_CFG2*/ +#define REG_AON_APB_DPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x004C)/*DPLL_CFG1*/ +#define REG_AON_APB_DPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0050)/*DPLL_CFG2*/ +#define REG_AON_APB_TWPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0054)/*TWPLL_CFG1*/ +#define REG_AON_APB_TWPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0058)/*TWPLL_CFG2*/ +#define REG_AON_APB_LTEPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x005C)/*LTEPLL_CFG1*/ +#define REG_AON_APB_LTEPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0060)/*LTEPLL_CFG2*/ +#define REG_AON_APB_LVDSDISPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0064)/*LVDSDISPLL_CFG1*/ +#define REG_AON_APB_LVDSDISPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0068)/*LVDSDISPLL_CFG2*/ +#define REG_AON_APB_AON_REG_PROT SCI_ADDR(REGS_AON_APB_BASE, 0x006C)/*AON_REG_PROT*/ +#define REG_AON_APB_LDSP_BOOT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x0070)/*LDSP_BOOT_EN*/ +#define REG_AON_APB_LDSP_BOOT_VEC SCI_ADDR(REGS_AON_APB_BASE, 0x0074)/*LDSP_BOOT_VEC*/ +#define REG_AON_APB_LDSP_RST SCI_ADDR(REGS_AON_APB_BASE, 0x0078)/*LDSP_RST*/ +#define REG_AON_APB_LDSP_MTX_CTRL1 SCI_ADDR(REGS_AON_APB_BASE, 0x007C)/*LDSP_MTX_CT1RL1*/ +#define REG_AON_APB_LDSP_MTX_CTRL2 SCI_ADDR(REGS_AON_APB_BASE, 0x0080)/*LDSP_MTX_CTRL2*/ +#define REG_AON_APB_LDSP_MTX_CTRL3 SCI_ADDR(REGS_AON_APB_BASE, 0x0084)/*LDSP_MTX_CTRL3*/ +#define REG_AON_APB_AON_CGM_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0088)/*AON_CGM_CFG*/ +#define REG_AON_APB_LACC_MTX_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x008C)/*LACC_MTX_CTRL*/ +#define REG_AON_APB_CORTEX_MTX_CTRL1 SCI_ADDR(REGS_AON_APB_BASE, 0x0090)/*CORTEX_MTX_CTRL1*/ +#define REG_AON_APB_CORTEX_MTX_CTRL2 SCI_ADDR(REGS_AON_APB_BASE, 0x0094)/*CORTEX_MTX_CTRL2*/ +#define REG_AON_APB_CORTEX_MTX_CTRL3 SCI_ADDR(REGS_AON_APB_BASE, 0x0098)/*CORTEX_MTX_CTRL3*/ +#define REG_AON_APB_CA5_TCLK_DLY_LEN SCI_ADDR(REGS_AON_APB_BASE, 0x009C)/*CA5_TCLK_DLY_LEN*/ +#define REG_AON_APB_AON_CHIP_ID SCI_ADDR(REGS_AON_APB_BASE, 0x00FC)/*AON_CHIP_ID*/ +#define REG_AON_APB_CCIR_RCVR_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0100)/*CCIR_RCVR_CFG*/ +#define REG_AON_APB_PLL_BG_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0108)/*PLL_BG_CFG*/ +#define REG_AON_APB_LVDSDIS_SEL SCI_ADDR(REGS_AON_APB_BASE, 0x010C)/*LVDSDIS_SEL*/ +#define REG_AON_APB_DJTAG_MUX_SEL SCI_ADDR(REGS_AON_APB_BASE, 0x0110)/*DJTAG_MUX_SEL*/ +#define REG_AON_APB_ARM7_SYS_SOFT_RST SCI_ADDR(REGS_AON_APB_BASE, 0x0114)/*ARM7_SYS_SOFT_RST*/ +#define REG_AON_APB_CP1_CP0_ADDR_MSB SCI_ADDR(REGS_AON_APB_BASE, 0x0118)/*CP1_CP0_ADDR_MSB*/ +#define REG_AON_APB_AON_DMA_INT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x011C)/*AON_DMA_INT_EN*/ +#define REG_AON_APB_EMC_AUTO_GATE_EN SCI_ADDR(REGS_AON_APB_BASE, 0x0120)/*EMC_AUTO_GATE_EN*/ +#define REG_AON_APB_ARM7_CFG_BUS SCI_ADDR(REGS_AON_APB_BASE, 0x0124)/*ARM7_CFG_BUS*/ +#define REG_AON_APB_RTC4M_0_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0128)/*RTC4M_0_CFG*/ +#define REG_AON_APB_RTC4M_1_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x012C)/*RTC4M_1_CFG*/ +#define REG_AON_APB_APB_RST2 SCI_ADDR(REGS_AON_APB_BASE, 0x0130)/*AHB_RST2*/ +#define REG_AON_APB_OSC_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0134)/*CA53_OSC_CTRL*/ +#define REG_AON_APB_OSC_OBS SCI_ADDR(REGS_AON_APB_BASE, 0x0138)/*CA53_OSC_OBS*/ +#define REG_AON_APB_AP_SDISABLE SCI_ADDR(REGS_AON_APB_BASE, 0x013C)/*AP_SDISABLE*/ +#define REG_AON_APB_AP_WPROT_EN1 SCI_ADDR(REGS_AON_APB_BASE, 0x3004)/*AP_WPROT_EN1*/ +#define REG_AON_APB_CP0_WPROT_EN1 SCI_ADDR(REGS_AON_APB_BASE, 0x3008)/*CP0_WPROT_EN1*/ +#define REG_AON_APB_CP1_WPROT_EN1 SCI_ADDR(REGS_AON_APB_BASE, 0x300C)/*CP1_WPROT_EN1*/ +#define REG_AON_APB_IO_DLY_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x3014)/*IO_DLY_CTRL*/ +#define REG_AON_APB_AP_WPROT_EN0 SCI_ADDR(REGS_AON_APB_BASE, 0x3018)/*AP_WPROT_EN0*/ +#define REG_AON_APB_CP0_WPROT_EN0 SCI_ADDR(REGS_AON_APB_BASE, 0x3020)/*CP0_WPROT_EN0*/ +#define REG_AON_APB_CP1_WPROT_EN0 SCI_ADDR(REGS_AON_APB_BASE, 0x3024)/*CP1_WPROT_EN0*/ +#define REG_AON_APB_PMU_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x302C)/*PMU_RST_MONITOR*/ +#define REG_AON_APB_THM_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3030)/*THM_RST_MONITOR*/ +#define REG_AON_APB_AP_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3034)/*AP_RST_MONITOR*/ +#define REG_AON_APB_APCPU_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3038)/*APCPU_RST_MONITOR*/ +#define REG_AON_APB_BOND_OPT0 SCI_ADDR(REGS_AON_APB_BASE, 0x303C)/*BOND_OPT0*/ +#define REG_AON_APB_BOND_OPT1 SCI_ADDR(REGS_AON_APB_BASE, 0x3040)/*BOND_OPT1*/ +#define REG_AON_APB_RES_REG0 SCI_ADDR(REGS_AON_APB_BASE, 0x3044)/*RES_REG0*/ +#define REG_AON_APB_RES_REG1 SCI_ADDR(REGS_AON_APB_BASE, 0x3048)/*RES_REG1*/ +#define REG_AON_APB_AON_QOS_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x304C)/*AON_QOS_CFG*/ +#define REG_AON_APB_BB_LDO_CAL_START SCI_ADDR(REGS_AON_APB_BASE, 0x3050)/*BB_LDO_CAL_START*/ +#define REG_AON_APB_AON_MTX_PROT_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3058)/*AON_MTX_PROT_CFG*/ +#define REG_AON_APB_LVDS_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3060)/*LVDS_CFG*/ +#define REG_AON_APB_PLL_LOCK_OUT_SEL SCI_ADDR(REGS_AON_APB_BASE, 0x3064)/*PLL_LOCK_OUT_SEL*/ +#define REG_AON_APB_RTC4M_RC_VAL SCI_ADDR(REGS_AON_APB_BASE, 0x3068)/*RTC4M_RC_VAL*/ +#define REG_AON_APB_PROT_BUS_SECURE_EN SCI_ADDR(REGS_AON_APB_BASE, 0x3080)/*PROT_BUS_SECURE_EN*/ +#define REG_AON_APB_PROT_ARM7_SPACE_EN SCI_ADDR(REGS_AON_APB_BASE, 0x3084)/*PROT_ARM7_SPACE_EN*/ +#define REG_AON_APB_AON_APB_RSV SCI_ADDR(REGS_AON_APB_BASE, 0x30F0)/*AON_APB_RSV*/ + + + +/* bits definitions for register REG_AON_APB_APB_EB0 */ +#define BIT_I2C_EB ( BIT(31) ) +#define BIT_APCPU_DAP_EB ( BIT(30) ) +#define BIT_APCPU_TS1_EB ( BIT(29) ) +#define BIT_APCPU_TS0_EB ( BIT(28) ) +#define BIT_CA7_DAP_EB BIT_APCPU_DAP_EB +#define BIT_CA7_TS1_EB BIT_APCPU_TS1_EB +#define BIT_CA7_TS0_EB BIT_APCPU_TS0_EB +#define BIT_GPU_EB ( BIT(27) ) +#define BIT_CKG_EB ( BIT(26) ) +#define BIT_AON_CKG_EB BIT_CKG_EB +#define BIT_MM_EB ( BIT(25) ) +#define BIT_AP_WDG_EB ( BIT(24) ) +#define BIT_MSPI_EB ( BIT(23) ) +#define BIT_SPLK_EB ( BIT(22) ) +#define BIT_IPI_EB ( BIT(21) ) +#define BIT_PIN_EB ( BIT(20) ) +#define BIT_VBC_EB ( BIT(19) ) +#define BIT_AUD_EB ( BIT(18) ) +#define BIT_AUDIF_EB ( BIT(17) ) +#define BIT_ADI_EB ( BIT(16) ) +#define BIT_INTC_EB ( BIT(15) ) +#define BIT_EIC_EB ( BIT(14) ) +#define BIT_EFUSE_EB ( BIT(13) ) +#define BIT_AP_TMR0_EB ( BIT(12) ) +#define BIT_AON_TMR_EB ( BIT(11) ) +#define BIT_AP_SYST_EB ( BIT(10) ) +#define BIT_AON_SYST_EB ( BIT(9) ) +#define BIT_KPD_EB ( BIT(8) ) +#define BIT_PWM3_EB ( BIT(7) ) +#define BIT_PWM2_EB ( BIT(6) ) +#define BIT_PWM1_EB ( BIT(5) ) +#define BIT_PWM0_EB ( BIT(4) ) +#define BIT_GPIO_EB ( BIT(3) ) +#define BIT_AON_GPIO_EB ( BIT_GPIO_EB ) +#define BIT_TPC_EB ( BIT(2) ) +#define BIT_FM_EB ( BIT(1) ) +#define BIT_ADC_EB ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_APB_EB1 */ +#define BIT_ORP_JTAG_EB ( BIT(27) ) +#define BIT_CA5_TS0_EB ( BIT(26) ) +#define BIT_DEF_EB ( BIT(25) ) +#define BIT_LVDS_PLL_DIV_EN ( BIT(24) ) +#define BIT_ARM7_JTAG_EB ( BIT(23) ) +#define BIT_AON_DMA_EB ( BIT(22) ) +#define BIT_MBOX_EB ( BIT(21) ) +#define BIT_DJTAG_EB ( BIT(20) ) +#define BIT_RTC4M1_CAL_EB ( BIT(19) ) +#define BIT_RTC4M0_CAL_EB ( BIT(18) ) +#define BIT_MDAR_EB ( BIT(17) ) +#define BIT_LVDS_TCXO_EB ( BIT(16) ) +#define BIT_LVDS_TRX_EB ( BIT(15) ) +#define BIT_CA5_DAP_EB ( BIT(14) ) +#define BIT_GSP_EMC_EB ( BIT(13) ) +#define BIT_ZIP_EMC_EB ( BIT(12) ) +#define BIT_DISP_EMC_EB ( BIT(11) ) +#define BIT_AP_TMR2_EB ( BIT(10) ) +#define BIT_AP_TMR1_EB ( BIT(9) ) +#define BIT_APCPU_WDG_EB ( BIT(8) ) +#define BIT_CA7_WDG_EB BIT_APCPU_WDG_EB +#define BIT_AVS_EB ( BIT(6) ) +#define BIT_PROBE_EB ( BIT(5) ) +#define BIT_AUX2_EB ( BIT(4) ) +#define BIT_AUX1_EB ( BIT(3) ) +#define BIT_AUX0_EB ( BIT(2) ) +#define BIT_THM_EB ( BIT(1) ) +#define BIT_PMU_EB ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_APB_RST0 */ +#define BIT_CA5_TS0_SOFT_RST ( BIT(31) ) +#define BIT_I2C_SOFT_RST ( BIT(30) ) +#define BIT_APCPU_TS1_SOFT_RST ( BIT(29) ) +#define BIT_APCPU_TS0_SOFT_RST ( BIT(28) ) +#define BIT_CA7_TS1_SOFT_RST BIT_APCPU_TS1_SOFT_RST +#define BIT_CA7_TS0_SOFT_RST BIT_APCPU_TS0_SOFT_RST +#define BIT_DAP_MTX_SOFT_RST ( BIT(27) ) +#define BIT_MSPI1_SOFT_RST ( BIT(26) ) +#define BIT_MSPI0_SOFT_RST ( BIT(25) ) +#define BIT_SPLK_SOFT_RST ( BIT(24) ) +#define BIT_IPI_SOFT_RST ( BIT(23) ) +#define BIT_CKG_SOFT_RST ( BIT(22) ) +#define BIT_AON_CKG_SOFT_RST BIT_CKG_SOFT_RST +#define BIT_PIN_SOFT_RST ( BIT(21) ) +#define BIT_VBC_SOFT_RST ( BIT(20) ) +#define BIT_AUD_SOFT_RST ( BIT(19) ) +#define BIT_AUDIF_SOFT_RST ( BIT(18) ) +#define BIT_ADI_SOFT_RST ( BIT(17) ) +#define BIT_INTC_SOFT_RST ( BIT(16) ) +#define BIT_EIC_SOFT_RST ( BIT(15) ) +#define BIT_EFUSE_SOFT_RST ( BIT(14) ) +#define BIT_AP_WDG_SOFT_RST ( BIT(13) ) +#define BIT_AP_TMR0_SOFT_RST ( BIT(12) ) +#define BIT_AON_TMR_SOFT_RST ( BIT(11) ) +#define BIT_AP_SYST_SOFT_RST ( BIT(10) ) +#define BIT_AON_SYST_SOFT_RST ( BIT(9) ) +#define BIT_KPD_SOFT_RST ( BIT(8) ) +#define BIT_PWM3_SOFT_RST ( BIT(7) ) +#define BIT_PWM2_SOFT_RST ( BIT(6) ) +#define BIT_PWM1_SOFT_RST ( BIT(5) ) +#define BIT_PWM0_SOFT_RST ( BIT(4) ) +#define BIT_GPIO_SOFT_RST ( BIT(3) ) +#define BIT_TPC_SOFT_RST ( BIT(2) ) +#define BIT_FM_SOFT_RST ( BIT(1) ) +#define BIT_ADC_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_APB_RST1 */ +#define BIT_RTC4M_ANA_SOFT_RST ( BIT(31) ) +#define BIT_DEF_SLV_INT_SOFT_CLR ( BIT(30) ) +#define BIT_DEF_SOFT_RST ( BIT(29) ) +#define BIT_ADC3_SOFT_RST ( BIT(28) ) +#define BIT_ADC2_SOFT_RST ( BIT(27) ) +#define BIT_ADC1_SOFT_RST ( BIT(26) ) +#define BIT_MBOX_SOFT_RST ( BIT(25) ) +#define BIT_RTC4M1_CAL_SOFT_RST ( BIT(23) ) +#define BIT_RTC4M0_CAL_SOFT_RST ( BIT(22) ) +#define BIT_LDSP_SYS_SOFT_RST ( BIT(21) ) +#define BIT_LCP_SYS_SOFT_RST ( BIT(20) ) +#define BIT_DAC3_SOFT_RST ( BIT(19) ) +#define BIT_DAC2_SOFT_RST ( BIT(18) ) +#define BIT_DAC1_SOFT_RST ( BIT(17) ) +#define BIT_ADC3_CAL_SOFT_RST ( BIT(16) ) +#define BIT_ADC2_CAL_SOFT_RST ( BIT(15) ) +#define BIT_ADC1_CAL_SOFT_RST ( BIT(14) ) +#define BIT_MDAR_SOFT_RST ( BIT(13) ) +#define BIT_LVDSDIS_SOFT_RST ( BIT(12) ) +#define BIT_BB_CAL_SOFT_RST ( BIT(11) ) +#define BIT_DCXO_LC_SOFT_RST ( BIT(10) ) +#define BIT_AP_TMR2_SOFT_RST ( BIT(9) ) +#define BIT_AP_TMR1_SOFT_RST ( BIT(8) ) +#define BIT_APCPU_WDG_SOFT_RST ( BIT(7) ) +#define BIT_CA7_WDG_SOFT_RST BIT_APCPU_WDG_SOFT_RST +#define BIT_AON_DMA_SOFT_RST ( BIT(6) ) +#define BIT_AVS_SOFT_RST ( BIT(5) ) +#define BIT_DMC_PHY_SOFT_RST ( BIT(4) ) +#define BIT_GPU_THMA_SOFT_RST ( BIT(3) ) +#define BIT_ARM_THMA_SOFT_RST ( BIT(2) ) +#define BIT_THM_SOFT_RST ( BIT(1) ) +#define BIT_PMU_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_APB_RTC_EB */ +#define BIT_CP0_LTE_EB ( BIT(19) ) +#define BIT_BB_CAL_RTC_EB ( BIT(18) ) +#define BIT_DCXO_LC_RTC_EB ( BIT(17) ) +#define BIT_AP_TMR2_RTC_EB ( BIT(16) ) +#define BIT_AP_TMR1_RTC_EB ( BIT(15) ) +#define BIT_GPU_THMA_RTC_AUTO_EN ( BIT(14) ) +#define BIT_ARM_THMA_RTC_AUTO_EN ( BIT(13) ) +#define BIT_GPU_THMA_RTC_EB ( BIT(12) ) +#define BIT_ARM_THMA_RTC_EB ( BIT(11) ) +#define BIT_THM_RTC_EB ( BIT(10) ) +#define BIT_APCPU_WDG_RTC_EB ( BIT(9) ) +#define BIT_CA7_WDG_RTC_EB BIT_APCPU_WDG_RTC_EB +#define BIT_AP_WDG_RTC_EB ( BIT(8) ) +#define BIT_EIC_RTCDV5_EB ( BIT(7) ) +#define BIT_EIC_RTC_EB ( BIT(6) ) +#define BIT_AP_TMR0_RTC_EB ( BIT(5) ) +#define BIT_AON_TMR_RTC_EB ( BIT(4) ) +#define BIT_AP_SYST_RTC_EB ( BIT(3) ) +#define BIT_AON_SYST_RTC_EB ( BIT(2) ) +#define BIT_KPD_RTC_EB ( BIT(1) ) +#define BIT_ARCH_RTC_EB ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_REC_26MHZ_BUF_CFG */ +#define BITS_PLL_PROBE_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_REC_26MHZ_1_CUR_SEL ( BIT(4) ) +#define BIT_REC_26MHZ_0_CUR_SEL ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_SINDRV_CTRL */ +#define BITS_SINDRV_LVL(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)) ) +#define BIT_SINDRV_CLIP_MODE ( BIT(2) ) +#define BIT_SINDRV_ENA_SQUARE ( BIT(1) ) +#define BIT_SINDRV_ENA ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_ADA_SEL_CTRL */ +#define BIT_TW_MODE_SEL ( BIT(3) ) +#define BIT_WGADC_DIV_EN ( BIT(2) ) +#define BIT_AFCDAC_SYS_SEL ( BIT(1) ) +#define BIT_APCDAC_SYS_SEL ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_VBC_CTRL */ +#define BIT_AUDIF_CKG_AUTO_EN ( BIT(20) ) +#define BITS_AUD_INT_SYS_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_VBC_AFIFO_INT_SYS_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_VBC_AD23_INT_SYS_SEL(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_VBC_AD01_INT_SYS_SEL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_VBC_DA01_INT_SYS_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_VBC_AD23_DMA_SYS_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_VBC_AD01_DMA_SYS_SEL(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_VBC_DA01_DMA_SYS_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BIT_VBC_INT_CP0_ARM_SEL ( BIT(3) ) +#define BIT_VBC_INT_CP1_ARM_SEL ( BIT(2) ) +#define BIT_VBC_DMA_CP0_ARM_SEL ( BIT(1) ) +#define BIT_VBC_DMA_CP1_ARM_SEL ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_PWR_CTRL */ +#define BIT_HSIC_PLL_EN ( BIT(19) ) +#define BIT_HSIC_PHY_PD ( BIT(18) ) +#define BIT_HSIC_PS_PD_S ( BIT(17) ) +#define BIT_HSIC_PS_PD_L ( BIT(16) ) +#define BIT_MIPI_DSI_PS_PD_S ( BIT(15) ) +#define BIT_MIPI_DSI_PS_PD_L ( BIT(14) ) +#define BIT_MIPI_CSI_4LANE_PS_PD_S ( BIT(13) ) +#define BIT_MIPI_CSI_4LANE_PS_PD_L ( BIT(12) ) +#define BIT_MIPI_CSI_2LANE_PS_PD_S ( BIT(11) ) +#define BIT_MIPI_CSI_2LANE_PS_PD_L ( BIT(10) ) +#define BIT_APCPU_TS1_STOP ( BIT(9) ) +#define BIT_APCPU_TS0_STOP ( BIT(8) ) +#define BIT_CA7_TS1_STOP BIT_APCPU_TS1_STOP +#define BIT_CA7_TS0_STOP BIT_APCPU_TS0_STOP +#define BIT_EFUSE_BIST_PWR_ON ( BIT(3) ) +#define BIT_FORCE_DSI_PHY_SHUTDOWNZ ( BIT(2) ) +#define BIT_FORCE_CSI_PHY_SHUTDOWNZ ( BIT(1) ) +#define BIT_USB_PHY_PD ( BIT(0) ) + + + +/* bits definitions for register REG_AON_APB_TS_CFG */ +#define BIT_CSYSACK_TS_LP_2 ( BIT(13) ) +#define BIT_CSYSREQ_TS_LP_2 ( BIT(12) ) +#define BIT_CSYSACK_TS_LP_1 ( BIT(11) ) +#define BIT_CSYSREQ_TS_LP_1 ( BIT(10) ) +#define BIT_CSYSACK_TS_LP_0 ( BIT(9) ) +#define BIT_CSYSREQ_TS_LP_0 ( BIT(8) ) +#define BIT_EVENTACK_RESTARTREQ_TS01 ( BIT(4) ) +#define BIT_EVENT_RESTARTREQ_TS01 ( BIT(1) ) +#define BIT_EVENT_HALTREQ_TS01 ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_BOOT_MODE */ +#define BIT_ARM_JTAG_EN ( BIT(13) ) +#define BIT_WPLL_OVR_FREQ_SEL ( BIT(12) ) +#define BIT_PTEST_FUNC_ATSPEED_SEL ( BIT(8) ) +#define BIT_PTEST_FUNC_MODE ( BIT(7) ) +#define BIT_USB_DLOAD_EN ( BIT(4) ) +#define BIT_ARM_BOOT_MD3 ( BIT(3) ) +#define BIT_ARM_BOOT_MD2 ( BIT(2) ) +#define BIT_ARM_BOOT_MD1 ( BIT(1) ) +#define BIT_ARM_BOOT_MD0 ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_BB_BG_CTRL */ +#define BIT_BB_CON_BG ( BIT(22) ) +#define BITS_BB_BG_RSV(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)) ) +#define BITS_BB_LDO_V(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BIT_BB_BG_RBIAS_EN ( BIT(15) ) +#define BIT_BB_BG_IEXT_IB_EN ( BIT(14) ) +#define BITS_BB_LDO_REFCTRL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) ) +#define BIT_BB_LDO_AUTO_PD_EN ( BIT(11) ) +#define BIT_BB_LDO_SLP_PD_EN ( BIT(10) ) +#define BIT_BB_LDO_FORCE_ON ( BIT(9) ) +#define BIT_BB_LDO_FORCE_PD ( BIT(8) ) +#define BIT_BB_BG_AUTO_PD_EN ( BIT(3) ) +#define BIT_BB_BG_SLP_PD_EN ( BIT(2) ) +#define BIT_BB_BG_FORCE_ON ( BIT(1) ) +#define BIT_BB_BG_FORCE_PD ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_CP_ARM_JTAG_CTRL */ +#define BIT_AON_ETM_PIN_SEL ( BIT(3) ) +#define BITS_CP_ARM_JTAG_PIN_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AON_APB_PLL_SOFT_CNT_DONE */ +#define BIT_RC1_SOFT_CNT_DONE ( BIT(13) ) +#define BIT_RC0_SOFT_CNT_DONE ( BIT(12) ) +#define BIT_XTLBUF1_SOFT_CNT_DONE ( BIT(9) ) +#define BIT_XTLBUF0_SOFT_CNT_DONE ( BIT(8) ) +#define BIT_LVDSPLL_SOFT_CNT_DONE ( BIT(4) ) +#define BIT_LPLL_SOFT_CNT_DONE ( BIT(3) ) +#define BIT_TWPLL_SOFT_CNT_DONE ( BIT(2) ) +#define BIT_DPLL_SOFT_CNT_DONE ( BIT(1) ) +#define BIT_MPLL_SOFT_CNT_DONE ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_DCXO_LC_REG0 */ +#define BIT_DCXO_LC_FLAG ( BIT(8) ) +#define BIT_DCXO_LC_FLAG_CLR ( BIT(1) ) +#define BIT_DCXO_LC_CNT_CLR ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_DCXO_LC_REG1 */ +#define BITS_DCXO_LC_CNT(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_MPLL_CFG1 */ +#define BITS_MPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)) ) +#define BIT_MPLL_LOCK_DONE ( BIT(27) ) +#define BIT_MPLL_DIV_S ( BIT(26) ) +#define BIT_MPLL_MOD_EN ( BIT(25) ) +#define BIT_MPLL_SDM_EN ( BIT(24) ) +#define BITS_MPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_MPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_MPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_MPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AON_APB_MPLL_CFG2 */ +#define BITS_MPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_MPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_AON_APB_DPLL_CFG1 */ +#define BITS_DPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)) ) +#define BIT_DPLL_LOCK_DONE ( BIT(27) ) +#define BIT_DPLL_DIV_S ( BIT(26) ) +#define BIT_DPLL_MOD_EN ( BIT(25) ) +#define BIT_DPLL_SDM_EN ( BIT(24) ) +#define BITS_DPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_DPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_DPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_DPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AON_APB_DPLL_CFG2 */ +#define BITS_DPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_DPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_AON_APB_TWPLL_CFG1 */ +#define BITS_TWPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)) ) +#define BIT_TWPLL_LOCK_DONE ( BIT(27) ) +#define BIT_TWPLL_DIV_S ( BIT(26) ) +#define BIT_TWPLL_MOD_EN ( BIT(25) ) +#define BIT_TWPLL_SDM_EN ( BIT(24) ) +#define BITS_TWPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_TWPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_TWPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_TWPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AON_APB_TWPLL_CFG2 */ +#define BITS_TWPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_TWPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_AON_APB_LTEPLL_CFG1 */ +#define BITS_LTEPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)) ) +#define BIT_LTEPLL_LOCK_DONE ( BIT(27) ) +#define BIT_LTEPLL_DIV_S ( BIT(26) ) +#define BIT_LTEPLL_MOD_EN ( BIT(25) ) +#define BIT_LTEPLL_SDM_EN ( BIT(24) ) +#define BITS_LTEPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_LTEPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_LTEPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_LTEPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AON_APB_LTEPLL_CFG2 */ +#define BITS_LTEPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_LTEPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_AON_APB_LVDSDISPLL_CFG1 */ +#define BITS_LVDSDISPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_LVDSDISPLL_LOCK_DONE ( BIT(27) ) +#define BIT_LVDSDISPLL_DIV_S ( BIT(26) ) +#define BIT_LVDSDISPLL_MOD_EN ( BIT(25) ) +#define BIT_LVDSDISPLL_SDM_EN ( BIT(24) ) +#define BITS_LVDSDISPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_LVDSDISPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_LVDSDISPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_LVDSDISPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AON_APB_LVDSDISPLL_CFG2 */ +#define BITS_LVDSDISPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_LVDSDISPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_AON_APB_AON_REG_PROT */ +#define BIT_LDSP_CTRL_PROT ( BIT(31) ) +#define BITS_REG_PROT_VAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AON_APB_LDSP_BOOT_EN */ +#define BIT_FRC_CLK_LDSP_EN ( BIT(1) ) +#define BIT_LDSP_BOOT_EN ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_LDSP_BOOT_VEC */ +#define BITS_LDSP_BOOT_VECTOR(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_LDSP_RST */ +#define BIT_LDSP_SYS_SRST ( BIT(1) ) +#define BIT_LDSP_CORE_SRST_N ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_LDSP_MTX_CTRL1 */ +#define BITS_LDSP_MTX_CTRL1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_LDSP_MTX_CTRL2 */ +#define BITS_LDSP_MTX_CTRL2(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_LDSP_MTX_CTRL3 */ +#define BITS_LDSP_MTX_CTRL3(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_AON_CGM_CFG */ +#define BITS_PROBE_CKG_DIV(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_AUX2_CKG_DIV(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_AUX1_CKG_DIV(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_AUX0_CKG_DIV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_PROBE_CKG_SEL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_AUX2_CKG_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_AUX1_CKG_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_AUX0_CKG_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_LACC_MTX_CTRL */ +#define BITS_LACC_MTX_CTRL(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CORTEX_MTX_CTRL1 */ +#define BITS_CORTEX_MTX_CTRL1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CORTEX_MTX_CTRL2 */ +#define BITS_CORTEX_MTX_CTRL2(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CORTEX_MTX_CTRL3 */ +#define BITS_CORTEX_MTX_CTRL3(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AON_APB_CA5_TCLK_DLY_LEN */ +#define BITS_CA5_TCLK_DLY_LEN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AON_APB_AON_CHIP_ID */ +#define BITS_AON_CHIP_ID(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CCIR_RCVR_CFG */ +#define BITS_ANALOG_PLL_RSV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_ANALOG_TESTMUX(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_CCIR_SE ( BIT(1) ) +#define BIT_CCIR_IE ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_PLL_BG_CFG */ +#define BITS_PLL_BG_RSV(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BIT_PLL_BG_RBIAS_EN ( BIT(3) ) +#define BIT_PLL_BG_PD ( BIT(2) ) +#define BIT_PLL_BG_IEXT_IBEN ( BIT(1) ) +#define BIT_PLL_CON_BG ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_LVDSDIS_SEL */ +#define BITS_LVDSDIS_LOG_SEL(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)) ) +#define BIT_LVDSDIS_DBG_SEL ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_DJTAG_MUX_SEL */ +#define BIT_DJTAG_AON_SEL ( BIT(6) ) +#define BIT_DJTAG_PUB_SEL ( BIT(5) ) +#define BIT_DJTAG_CP1_SEL ( BIT(4) ) +#define BIT_DJTAG_CP0_SEL ( BIT(3) ) +#define BIT_DJTAG_GPU_SEL ( BIT(2) ) +#define BIT_DJTAG_MM_SEL ( BIT(1) ) +#define BIT_DJTAG_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_ARM7_SYS_SOFT_RST */ +#define BIT_ARM7_SYS_SOFT_RST ( BIT(4) ) +#define BIT_ARM7_CORE_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_CP1_CP0_ADDR_MSB */ +#define BITS_CP1_CP0_ADDR_MSB(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_AON_DMA_INT_EN */ +#define BIT_AON_DMA_INT_ARM7_EN ( BIT(6) ) +#define BIT_AON_DMA_INT_CP1_DSP_EN ( BIT(5) ) +#define BIT_AON_DMA_INT_CP1_CA5_EN ( BIT(4) ) +#define BIT_AON_DMA_INT_CP0_DSP_1_EN ( BIT(3) ) +#define BIT_AON_DMA_INT_CP0_DSP_0_EN ( BIT(2) ) +#define BIT_AON_DMA_INT_CP0_ARM9_0_EN ( BIT(1) ) +#define BIT_AON_DMA_INT_AP_EN ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_EMC_AUTO_GATE_EN */ +#define BIT_CP1_PUB_AUTO_GATE_EN ( BIT(19) ) +#define BIT_CP0_PUB_AUTO_GATE_EN ( BIT(18) ) +#define BIT_AP_PUB_AUTO_GATE_EN ( BIT(17) ) +#define BIT_AON_APB_PUB_AUTO_GATE_EN ( BIT(16) ) +#define BIT_CP1_EMC_AUTO_GATE_EN ( BIT(3) ) +#define BIT_CP0_EMC_AUTO_GATE_EN ( BIT(2) ) +#define BIT_AON_AP_EMC_AUTO_GATE_EN ( BIT(1) ) +#define BIT_AON_APCPU_EMC_AUTO_GATE_EN ( BIT(0) ) +#define BIT_AON_CA7_EMC_AUTO_GATE_EN ( BIT_AON_APCPU_EMC_AUTO_GATE_EN ) + +/* bits definitions for register REG_AON_APB_ARM7_CFG_BUS */ +#define BIT_ARM7_CFG_BUS_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_RTC4M_0_CFG */ +#define BITS_RTC4M0_RSV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RTC4M0_I_C(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BIT_RTC4M0_CAL_DONE ( BIT(6) ) +#define BIT_RTC4M0_CAL_START ( BIT(5) ) +#define BIT_RTC4M0_CHOP_EN ( BIT(4) ) +#define BIT_RTC4M0_FORCE_EN ( BIT(1) ) +#define BIT_RTC4M0_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_RTC4M_1_CFG */ +#define BITS_RTC4M1_RSV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RTC4M1_I_C(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BIT_RTC4M1_CAL_DONE ( BIT(6) ) +#define BIT_RTC4M1_CAL_START ( BIT(5) ) +#define BIT_RTC4M1_CHOP_EN ( BIT(4) ) +#define BIT_RTC4M1_FORCE_EN ( BIT(1) ) +#define BIT_RTC4M1_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_APB_RST2 */ +#define BIT_AON_DJTAG_SOFT_RST ( BIT(6) ) +#define BIT_PUB_DJTAG_SOFT_RST ( BIT(5) ) +#define BIT_GPU_DJTAG_SOFT_RST ( BIT(4) ) +#define BIT_MM_DJTAG_SOFT_RST ( BIT(3) ) +#define BIT_CP1_DJTAG_SOFT_RST ( BIT(2) ) +#define BIT_CP0_DJTAG_SOFT_RST ( BIT(1) ) +#define BIT_AP_DJTAG_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_OSC_CTRL */ +#define BITS_OSC_CTRL_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)) ) +#define BIT_OSC_CTRL_EN ( BIT(15) ) +#define BIT_OSC_CTRL_START ( BIT(14) ) +#define BIT_OSC_CTRL_RSTN ( BIT(13) ) +#define BITS_OSC_CTRL_CLK_NUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) + +/* bits definitions for register REG_AON_APB_OSC_OBS */ +#define BIT_OSC_OBS_OVERFLOW ( BIT(15) ) +#define BITS_OSC_OBS_SPEED_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register REG_AON_APB_AP_SDISABLE */ +#define BIT_AP_CFGSDISABLE ( BIT(4) ) +#define BITS_AP_CP15SDISABLE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_AP_WPROT_EN1 */ +#define BITS_AP_AWADDR_WPROT_EN1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CP0_WPROT_EN1 */ +#define BITS_CP0_AWADDR_WPROT_EN1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CP1_WPROT_EN1 */ +#define BITS_CP1_AWADDR_WPROT_EN1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_IO_DLY_CTRL */ +#define BITS_CLK_CCIR_DLY_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CLK_CP1DSP_DLY_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_CLK_CP0DSP_DLY_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_AP_WPROT_EN0 */ +#define BITS_AP_AWADDR_WPROT_EN0(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CP0_WPROT_EN0 */ +#define BITS_CP0_AWADDR_WPROT_EN0(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CP1_WPROT_EN0 */ +#define BITS_CP1_AWADDR_WPROT_EN0(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_PMU_RST_MONITOR */ +#define BITS_PMU_RST_MONITOR(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_THM_RST_MONITOR */ +#define BITS_THM_RST_MONITOR(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_AP_RST_MONITOR */ +#define BITS_AP_RST_MONITOR(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CA7_RST_MONITOR */ +#define BITS_APCPU_RST_MONITOR(_X_) (_X_) +#define BITS_CA7_RST_MONITOR(_X_) BITS_APCPU_RST_MONITOR + +/* bits definitions for register REG_AON_APB_BOND_OPT0 */ +#define BITS_BOND_OPTION0(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_BOND_OPT1 */ +#define BITS_BOND_OPTION1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_RES_REG0 */ +#define BITS_RES_REG0(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_RES_REG1 */ +#define BITS_RES_REG1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_AON_QOS_CFG */ +#define BITS_QOS_R_GPU(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_QOS_W_GPU(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_QOS_R_GSP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_QOS_W_GSP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_BB_LDO_CAL_START */ +#define BIT_BB_LDO_CAL_START ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_AON_MTX_PROT_CFG */ +#define BITS_AON_HPROT_DMAW(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_AON_HPROT_DMAR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_LVDS_CFG */ +#define BITS_LVDSDIS_TXCLKDATA(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_LVDSDIS_TXCOM(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_LVDSDIS_TXSLEW(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_LVDSDIS_TXSW(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_LVDSDIS_TXRERSER(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_LVDSDIS_PRE_EMP(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)) ) +#define BIT_LVDSDIS_TXPD ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_PLL_LOCK_OUT_SEL */ +#define BIT_SLEEP_PLLLOCK_SEL ( BIT(7) ) +#define BITS_PLL_LOCK_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BITS_SLEEP_DBG_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_RTC4M_RC_VAL */ +#define BIT_RTC4M1_RC_SEL ( BIT(31) ) +#define BITS_RTC4M1_RC_VAL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) ) +#define BIT_RTC4M0_RC_SEL ( BIT(15) ) +#define BITS_RTC4M0_RC_VAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) ) + +/* bits definitions for register REG_AON_APB_PROT_BUS_SECURE_EN */ +#define BIT_BUS_SECURE_EN ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_PROT_ARM7_SPACE_EN */ +#define BIT_ARM7_SPACE_EN ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_AON_APB_RSV */ +#define BITS_AON_APB_RSV(_X_) (_X_) + +#endif diff --git a/include/soc/sprd/chip_x35l64/__regs_aon_clk.h b/include/soc/sprd/chip_x35l64/__regs_aon_clk.h new file mode 100644 index 00000000..d92de360 --- /dev/null +++ b/include/soc/sprd/chip_x35l64/__regs_aon_clk.h @@ -0,0 +1,134 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + + + + +#ifndef __H_REGS_AON_CLK_CORE_HEADFILE_H__ +#define __H_REGS_AON_CLK_CORE_HEADFILE_H__ __FILE__ + +#define REGS_AON_CLK_CORE + +/* registers definitions for AON_CLK_CORE */ +#define REG_AON_CLK_CORE_clk_pub_ahb_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x20)/*clk_pub_ahb_cfg*/ +#define REG_AON_CLK_CORE_clk_aon_apb_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x24)/*clk_aon_apb_cfg*/ +#define REG_AON_CLK_CORE_clk_adi_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x28)/*clk_adi_cfg*/ +#define REG_AON_CLK_CORE_clk_pwm0_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x2c)/*clk_pwm0_cfg*/ +#define REG_AON_CLK_CORE_clk_pwm1_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x30)/*clk_pwm1_cfg*/ +#define REG_AON_CLK_CORE_clk_pwm2_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x34)/*clk_pwm2_cfg*/ +#define REG_AON_CLK_CORE_clk_pwm3_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x38)/*clk_pwm3_cfg*/ +#define REG_AON_CLK_CORE_clk_arm7_uart_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x3c)/*clk_arm7_uart_cfg*/ +#define REG_AON_CLK_CORE_clk_thm_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x40)/*clk_thm_cfg*/ +#define REG_AON_CLK_CORE_clk_mspi_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x44)/*clk_mspi_cfg*/ +#define REG_AON_CLK_CORE_clk_i2c_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x48)/*clk_i2c_cfg*/ +#define REG_AON_CLK_CORE_clk_avs_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x4c)/*clk_avs_cfg*/ +#define REG_AON_CLK_CORE_clk_audif_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x50)/*clk_audif_cfg*/ +#define REG_AON_CLK_CORE_clk_apcpu_dap_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x54)/*clk_apcpu_dap_cfg*/ +#define REG_AON_CLK_CORE_clk_emc_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x58)/*clk_emc_cfg*/ +#define REG_AON_CLK_CORE_clk_apcpu_ts_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x5c)/*clk_apcpu_ts_cfg*/ +#define REG_AON_CLK_CORE_clk_djtag_tck_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x60)/*clk_djtag_tck_cfg*/ +#define REG_AON_CLK_CORE_clk_arm7_ahb_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x64)/*clk_arm7_ahb_cfg*/ +#define REG_AON_CLK_CORE_clk_ca5_ts_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x68)/*clk_ca5_ts_cfg*/ + +/* registers definitions for controller REGS_AON_CLK */ +#define REG_AON_CLK_PUB_AHB_CFG REG_AON_CLK_CORE_clk_pub_ahb_cfg +#define REG_AON_CLK_AON_APB_CFG REG_AON_CLK_CORE_clk_aon_apb_cfg +#define REG_AON_CLK_ADI_CFG REG_AON_CLK_CORE_clk_adi_cfg +#define REG_AON_CLK_PWM0_CFG REG_AON_CLK_CORE_clk_pwm0_cfg +#define REG_AON_CLK_PWM1_CFG REG_AON_CLK_CORE_clk_pwm1_cfg +#define REG_AON_CLK_PWM2_CFG REG_AON_CLK_CORE_clk_pwm2_cfg +#define REG_AON_CLK_PWM3_CFG REG_AON_CLK_CORE_clk_pwm3_cfg +#define REG_AON_CLK_ARM7_UART_CFG REG_AON_CLK_CORE_clk_arm7_uart_cfg +#define REG_AON_CLK_THM_CFG REG_AON_CLK_CORE_clk_thm_cfg +#define REG_AON_CLK_MSPI_CFG REG_AON_CLK_CORE_clk_mspi_cfg +#define REG_AON_CLK_I2C_CFG REG_AON_CLK_CORE_clk_i2c_cfg +#define REG_AON_CLK_AVS_CFG REG_AON_CLK_CORE_clk_avs_cfg +#define REG_AON_CLK_AUDIF_CFG REG_AON_CLK_CORE_clk_audif_cfg +#define REG_AON_CLK_CA7_DAP_CFG REG_AON_CLK_CORE_clk_apcpu_dap_cfg +#define REG_AON_CLK_EMC_CFG REG_AON_CLK_CORE_clk_emc_cfg +#define REG_AON_CLK_CA7_TS_CFG REG_AON_CLK_CORE_clk_apcpu_ts_cfg +#define REG_AON_CLK_DJTAG_CLK_CFG REG_AON_CLK_CORE_clk_djtag_tck_cfg +#define REG_AON_CLK_ARM7_AHB_CFG REG_AON_CLK_CORE_clk_arm7_ahb_cfg +#define REG_AON_CLK_CA5_TS_CFG REG_AON_CLK_CORE_clk_ca5_ts_cfg +/* vars definitions for controller REGS_AON_CLK */ +#define PUB_AHB_CLK_SEL_SHIFT (0x0) +#define PUB_AHB_CLK_SEL_MASK (0x3 << PUB_AHB_CLK_SEL_SHIFT) + +/* bits definitions for register REG_AON_CLK_CORE_clk_pub_ahb_cfg */ +#define BITS_CLK_PUB_AHB_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_CLK_PUB_AHB_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_aon_apb_cfg */ +#define BITS_CLK_AON_APB_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_CLK_AON_APB_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_adi_cfg */ +#define BITS_CLK_ADI_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_pwm0_cfg */ +#define BITS_CLK_PWM0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_pwm1_cfg */ +#define BITS_CLK_PWM1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_pwm2_cfg */ +#define BITS_CLK_PWM2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_pwm3_cfg */ +#define BITS_CLK_PWM3_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_arm7_uart_cfg */ +#define BITS_CLK_ARM7_UART_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_thm_cfg */ +#define BIT_CLK_THM_SEL ( BIT(0) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_mspi_cfg */ +#define BITS_CLK_MSPI_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_i2c_cfg */ +#define BITS_CLK_I2C_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_avs_cfg */ +#define BITS_CLK_AVS_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_audif_cfg */ +#define BITS_CLK_AUDIF_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_apcpu_dap_cfg */ +#define BITS_CLK_APCPU_DAP_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_emc_cfg */ +#define BITS_CLK_EMC_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_CLK_EMC_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_apcpu_ts_cfg */ +#define BITS_CLK_APCPU_TS_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_djtag_tck_cfg */ +#define BIT_CLK_DJTAG_TCK_PAD_SEL ( BIT(16) ) +#define BIT_CLK_DJTAG_TCK_SEL ( BIT(0) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_arm7_ahb_cfg */ +#define BITS_CLK_ARM7_AHB_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_CLK_ARM7_AHB_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_ca5_ts_cfg */ +#define BITS_CLK_CA5_TS_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +#endif diff --git a/include/soc/sprd/chip_x35l64/__regs_ap_ahb_rf.h b/include/soc/sprd/chip_x35l64/__regs_ap_ahb_rf.h new file mode 100644 index 00000000..69a0f1d5 --- /dev/null +++ b/include/soc/sprd/chip_x35l64/__regs_ap_ahb_rf.h @@ -0,0 +1,454 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + + +#ifndef __H_REGS_AP_AHB_RF_HEADFILE_H__ +#define __H_REGS_AP_AHB_RF_HEADFILE_H__ __FILE__ + +#define REGS_AP_AHB_RF +/* registers definitions for controller REGS_AP_AHB */ +#define REG_AP_AHB_AHB_EB SCI_ADDR(REGS_AP_AHB_BASE, 0x0000) +#define REG_AP_AHB_AHB_RST SCI_ADDR(REGS_AP_AHB_BASE, 0x0004) +#define REG_AP_AHB_APCPU_RST_SET SCI_ADDR(REGS_AP_AHB_BASE, 0x0008)/*APCPU_RST_SET*/ +#define REG_AP_AHB_CA7_RST_SET REG_AP_AHB_APCPU_RST_SET +#define REG_AP_AHB_AP_SYS_FORCE_SLEEP_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x000C) +#define REG_AP_AHB_AP_SYS_AUTO_SLEEP_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x0010) +#define REG_AP_AHB_HOLDING_PEN SCI_ADDR(REGS_AP_AHB_BASE, 0x0014) +#define REG_AP_AHB_JMP_ADDR_APCPU_C0 SCI_ADDR(REGS_AP_AHB_BASE, 0x0018)/*JMP_ADDR_APCPU_C0*/ +#define REG_AP_AHB_JMP_ADDR_APCPU_C1 SCI_ADDR(REGS_AP_AHB_BASE, 0x001C)/*JMP_ADDR_APCPU_C1*/ +#define REG_AP_AHB_JMP_ADDR_APCPU_C2 SCI_ADDR(REGS_AP_AHB_BASE, 0x0020)/*JMP_ADDR_APCPU_C2*/ +#define REG_AP_AHB_JMP_ADDR_APCPU_C3 SCI_ADDR(REGS_AP_AHB_BASE, 0x0024)/*JMP_ADDR_APCPU_C3*/ +#define REG_AP_AHB_APCPU_C0_PU_LOCK SCI_ADDR(REGS_AP_AHB_BASE, 0x0028)/*APCPU_C0_PU_LOCK*/ +#define REG_AP_AHB_APCPU_C1_PU_LOCK SCI_ADDR(REGS_AP_AHB_BASE, 0x002C)/*APCPU_C1_PU_LOCK*/ +#define REG_AP_AHB_APCPU_C2_PU_LOCK SCI_ADDR(REGS_AP_AHB_BASE, 0x0030)/*APCPU_C2_PU_LOCK*/ +#define REG_AP_AHB_APCPU_C3_PU_LOCK SCI_ADDR(REGS_AP_AHB_BASE, 0x0034)/*APCPU_C3_PU_LOCK*/ +#define REG_AP_AHB_APCPU_CKG_DIV_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x0038)/*APCPU_CKG_DIV_CFG*/ +#define REG_AP_AHB_JMP_ADDR_CA7_C0 REG_AP_AHB_JMP_ADDR_APCPU_C0 +#define REG_AP_AHB_JMP_ADDR_CA7_C1 REG_AP_AHB_JMP_ADDR_APCPU_C1 +#define REG_AP_AHB_JMP_ADDR_CA7_C2 REG_AP_AHB_JMP_ADDR_APCPU_C2 +#define REG_AP_AHB_JMP_ADDR_CA7_C3 REG_AP_AHB_JMP_ADDR_APCPU_C3 +#define REG_AP_AHB_CA7_C0_PU_LOCK REG_AP_AHB_APCPU_C0_PU_LOCK +#define REG_AP_AHB_CA7_C1_PU_LOCK REG_AP_AHB_APCPU_C1_PU_LOCK +#define REG_AP_AHB_CA7_C2_PU_LOCK REG_AP_AHB_APCPU_C2_PU_LOCK +#define REG_AP_AHB_CA7_C3_PU_LOCK REG_AP_AHB_APCPU_C3_PU_LOCK +#define REG_AP_AHB_CA7_CKG_DIV_CFG REG_AP_AHB_APCPU_CKG_DIV_CFG +#define REG_AP_AHB_MCU_PAUSE SCI_ADDR(REGS_AP_AHB_BASE, 0x003C) +#define REG_AP_AHB_MISC_CKG_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x0040) +#define REG_AP_AHB_APCPU_C0_AUTO_FORCE_SHUTDOWN_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x0044)/*APCPU_C0_AUTO_FORCE_SHUTDOWN_EN*/ +#define REG_AP_AHB_APCPU_C1_AUTO_FORCE_SHUTDOWN_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x0048)/*APCPU_C1_AUTO_FORCE_SHUTDOWN_EN*/ +#define REG_AP_AHB_APCPU_C2_AUTO_FORCE_SHUTDOWN_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x004C)/*APCPU_C2_AUTO_FORCE_SHUTDOWN_EN*/ +#define REG_AP_AHB_APCPU_C3_AUTO_FORCE_SHUTDOWN_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x0050)/*APCPU_C3_AUTO_FORCE_SHUTDOWN_EN*/ +#define REG_AP_AHB_APCPU_CKG_SEL_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x0054)/*APCPU_CKG_SEL_CFG*/ +#define REG_AP_AHB_APCPU_AUTO_GATE_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x0058)/*APCPU_AUTO_GATE_EN*/ +#define REG_AP_AHB_CA7_C0_AUTO_FORCE_SHUTDOWN_EN REG_AP_AHB_APCPU_C0_AUTO_FORCE_SHUTDOWN_EN +#define REG_AP_AHB_CA7_C1_AUTO_FORCE_SHUTDOWN_EN REG_AP_AHB_APCPU_C1_AUTO_FORCE_SHUTDOWN_EN +#define REG_AP_AHB_CA7_C2_AUTO_FORCE_SHUTDOWN_EN REG_AP_AHB_APCPU_C2_AUTO_FORCE_SHUTDOWN_EN +#define REG_AP_AHB_CA7_C3_AUTO_FORCE_SHUTDOWN_EN REG_AP_AHB_APCPU_C3_AUTO_FORCE_SHUTDOWN_EN +#define REG_AP_AHB_CA7_CKG_SEL_CFG REG_AP_AHB_APCPU_CKG_SEL_CFG +#define REG_AP_AHB_MISC_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x3000) +#define REG_AP_AHB_AP_MAIN_MTX_HPROT_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x3004) +#define REG_AP_AHB_CA7_STANDBY_STATUS SCI_ADDR(REGS_AP_AHB_BASE, 0x3008) +#define REG_AP_AHB_NANC_CLK_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x300C) +#define REG_AP_AHB_LVDS_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x3010) +#define REG_AP_AHB_LVDS_PLL_CFG0 SCI_ADDR(REGS_AP_AHB_BASE, 0x3014) +#define REG_AP_AHB_LVDS_PLL_CFG1 SCI_ADDR(REGS_AP_AHB_BASE, 0x3018) +#define REG_AP_AHB_AP_QOS_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x301C) +#define REG_AP_AHB_OTG_PHY_TUNE SCI_ADDR(REGS_AP_AHB_BASE, 0x3020) +#define REG_AP_AHB_OTG_PHY_TEST SCI_ADDR(REGS_AP_AHB_BASE, 0x3024) +#define REG_AP_AHB_OTG_PHY_CTRL SCI_ADDR(REGS_AP_AHB_BASE, 0x3028) +#define REG_AP_AHB_HSIC_PHY_TUNE SCI_ADDR(REGS_AP_AHB_BASE, 0x302C) +#define REG_AP_AHB_HSIC_PHY_TEST SCI_ADDR(REGS_AP_AHB_BASE, 0x3030) +#define REG_AP_AHB_HSIC_PHY_CTRL SCI_ADDR(REGS_AP_AHB_BASE, 0x3034) +#define REG_AP_AHB_ZIP_MTX_QOS_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x3038) +#define REG_AP_AHB_APCPU_QCHN_STA SCI_ADDR(REGS_AP_AHB_BASE, 0x3040)/*APCPU_QCHN_STA*/ +#define REG_AP_AHB_RES_REG SCI_ADDR(REGS_AP_AHB_BASE, 0x30F0)/*RES_REG*/ +#define REG_AP_AHB_CHIP_ID SCI_ADDR(REGS_AP_AHB_BASE, 0x30FC) + +/* bits definitions for register REG_AP_AHB_AHB_EB */ +#define BIT_ZIPMTX_EB ( BIT(23) ) +#define BIT_LVDS_EB ( BIT(22) ) +#define BIT_ZIPDEC_EB ( BIT(21) ) +#define BIT_ZIPENC_EB ( BIT(20) ) +#define BIT_NANDC_ECC_EB ( BIT(19) ) +#define BIT_NANDC_2X_EB ( BIT(18) ) +#define BIT_NANDC_EB ( BIT(17) ) +#define BIT_BUSMON2_EB ( BIT(16) ) +#define BIT_BUSMON1_EB ( BIT(15) ) +#define BIT_BUSMON0_EB ( BIT(14) ) +#define BIT_SPINLOCK_EB ( BIT(13) ) +#define BIT_EMMC_EB ( BIT(11) ) +#define BIT_SDIO2_EB ( BIT(10) ) +#define BIT_SDIO1_EB ( BIT(9) ) +#define BIT_SDIO0_EB ( BIT(8) ) +#define BIT_DRM_EB ( BIT(7) ) +#define BIT_NFC_EB ( BIT(6) ) +#define BIT_DMA_EB ( BIT(5) ) +#define BIT_OTG_EB ( BIT(4) ) +#define BIT_USB_EB (BIT_OTG_EB) +#define BIT_GSP_EB ( BIT(3) ) +#define BIT_HSIC_EB ( BIT(2) ) +#define BIT_DISPC_EB ( BIT(1) ) +#define BIT_DISPC0_EB (BIT_DISPC_EB) +#define BIT_DSI_EB ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_AHB_RST */ +#define BIT_HSIC_PHY_SOFT_RST ( BIT(30) ) +#define BIT_HSIC_UTMI_SOFT_RST ( BIT(29) ) +#define BIT_HSIC_SOFT_RST ( BIT(28) ) +#define BIT_LVDS_SOFT_RST ( BIT(25) ) +#define BIT_ZIP_MTX_SOFT_RST ( BIT(24) ) +#define BIT_ZIPDEC_SOFT_RST ( BIT(23) ) +#define BIT_ZIPENC_SOFT_RST ( BIT(22) ) +#define BIT_NANDC_SOFT_RST ( BIT(20) ) +#define BIT_BUSMON2_SOFT_RST ( BIT(19) ) +#define BIT_BUSMON1_SOFT_RST ( BIT(18) ) +#define BIT_BUSMON0_SOFT_RST ( BIT(17) ) +#define BIT_SPINLOCK_SOFT_RST ( BIT(16) ) +#define BIT_EMMC_SOFT_RST ( BIT(14) ) +#define BIT_SDIO2_SOFT_RST ( BIT(13) ) +#define BIT_SDIO1_SOFT_RST ( BIT(12) ) +#define BIT_SDIO0_SOFT_RST ( BIT(11) ) +#define BIT_DRM_SOFT_RST ( BIT(10) ) +#define BIT_NFC_SOFT_RST ( BIT(9) ) +#define BIT_DMA_SOFT_RST ( BIT(8) ) +#define BIT_OTG_PHY_SOFT_RST ( BIT(6) ) +#define BIT_OTG_UTMI_SOFT_RST ( BIT(5) ) +#define BIT_OTG_SOFT_RST ( BIT(4) ) +#define BIT_GSP_SOFT_RST ( BIT(3) ) +#define BIT_DISP_MTX_SOFT_RST ( BIT(2) ) +#define BIT_DISPC_SOFT_RST ( BIT(1) ) +#define BIT_DISPC0_SOFT_RST (BIT_DISPC_SOFT_RST) +#define BIT_DSI_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_CA7_RST_SET */ +#define BIT_AP_QCHN_SOFT_RST ( BIT(17) ) +#define BIT_APCPU_TRACE_SOFT_RST ( BIT(16) ) +#define BIT_APCPU_GIC_SOFT_RST ( BIT(15) ) +#define BIT_APCPU_CS_DBG_SOFT_RST ( BIT(14) ) +#define BIT_APCPU_L2_SOFT_RST ( BIT(13) ) +#define BIT_APCPU_SOCDBG_SOFT_RST ( BIT(12) ) +#define BITS_APCPU_ETM_SOFT_RST(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_APCPU_DBG_SOFT_RST(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_APCPU_CORE_SOFT_RST(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) +#define BIT_CA7_CS_DBG_SOFT_RST BIT_APCPU_CS_DBG_SOFT_RST +#define BIT_CA7_L2_SOFT_RST BIT_APCPU_L2_SOFT_RST +#define BIT_CA7_SOCDBG_SOFT_RST BIT_APCPU_SOCDBG_SOFT_RST +#define BITS_CA7_ETM_SOFT_RST(_x_) BITS_APCPU_ETM_SOFT_RST(_x_) +#define BITS_CA7_DBG_SOFT_RST(_x_) BITS_APCPU_DBG_SOFT_RST(_x_) +#define BITS_CA7_CORE_SOFT_RST(_x_) BITS_APCPU_CORE_SOFT_RST(_x_) + +/* bits definitions for register REG_AP_AHB_AP_SYS_FORCE_SLEEP_CFG */ +#define BIT_APCPU_C3_AUTO_SLP_EN ( BIT(15) ) +#define BIT_APCPU_C2_AUTO_SLP_EN ( BIT(14) ) +#define BIT_APCPU_C1_AUTO_SLP_EN ( BIT(13) ) +#define BIT_APCPU_C0_AUTO_SLP_EN ( BIT(12) ) +#define BIT_APCPU_C3_WFI_SHUTDOWN_EN ( BIT(11) ) +#define BIT_APCPU_C2_WFI_SHUTDOWN_EN ( BIT(10) ) +#define BIT_APCPU_C1_WFI_SHUTDOWN_EN ( BIT(9) ) +#define BIT_APCPU_C0_WFI_SHUTDOWN_EN ( BIT(8) ) +#define BIT_MCU_APCPU_C3_SLEEP ( BIT(7) ) +#define BIT_MCU_APCPU_C2_SLEEP ( BIT(6) ) +#define BIT_MCU_APCPU_C1_SLEEP ( BIT(5) ) +#define BIT_MCU_APCPU_C0_SLEEP ( BIT(4) ) +#define BIT_CA7_C3_AUTO_SLP_EN BIT_APCPU_C3_AUTO_SLP_EN +#define BIT_CA7_C2_AUTO_SLP_EN BIT_APCPU_C2_AUTO_SLP_EN +#define BIT_CA7_C1_AUTO_SLP_EN BIT_APCPU_C1_AUTO_SLP_EN +#define BIT_CA7_C0_AUTO_SLP_EN BIT_APCPU_C0_AUTO_SLP_EN +#define BIT_CA7_C3_WFI_SHUTDOWN_EN BIT_APCPU_C3_WFI_SHUTDOWN_EN +#define BIT_CA7_C2_WFI_SHUTDOWN_EN BIT_APCPU_C2_WFI_SHUTDOWN_EN +#define BIT_CA7_C1_WFI_SHUTDOWN_EN BIT_APCPU_C1_WFI_SHUTDOWN_EN +#define BIT_CA7_C0_WFI_SHUTDOWN_EN BIT_APCPU_C0_WFI_SHUTDOWN_EN +#define BIT_MCU_CA7_C3_SLEEP BIT_MCU_APCPU_C3_SLEEP +#define BIT_MCU_CA7_C2_SLEEP BIT_MCU_APCPU_C2_SLEEP +#define BIT_MCU_CA7_C1_SLEEP BIT_MCU_APCPU_C1_SLEEP +#define BIT_MCU_CA7_C0_SLEEP BIT_MCU_APCPU_C0_SLEEP +#define BIT_AP_PERI_FORCE_ON ( BIT(2) ) +#define BIT_AP_PERI_FORCE_SLP ( BIT(1) ) +#define BIT_AP_APB_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_AP_SYS_AUTO_SLEEP_CFG */ +#define BIT_GSP_CKG_FORCE_EN ( BIT(9) ) +#define BIT_GSP_AUTO_GATE_EN ( BIT(8) ) +#define BIT_APCPU_TRACE_FORCE_SLEEP ( BIT(7) ) +#define BIT_APCPU_TRACE_AUTO_GATE_EN ( BIT(6) ) +#define BIT_AP_AHB_AUTO_GATE_EN ( BIT(5) ) +#define BIT_AP_EMC_AUTO_GATE_EN ( BIT(4) ) +#define BIT_APCPU_EMC_AUTO_GATE_EN ( BIT(3) ) +#define BIT_APCPU_DBG_FORCE_SLEEP ( BIT(2) ) +#define BIT_APCPU_DBG_AUTO_GATE_EN ( BIT(1) ) +#define BIT_APCPU_CORE_AUTO_GATE_EN ( BIT(0) ) +#define BIT_CA7_EMC_AUTO_GATE_EN BIT_APCPU_EMC_AUTO_GATE_EN +#define BIT_CA7_DBG_FORCE_SLEEP BIT_APCPU_DBG_FORCE_SLEEP +#define BIT_CA7_DBG_AUTO_GATE_EN BIT_APCPU_DBG_AUTO_GATE_EN +#define BIT_CA7_CORE_AUTO_GATE_EN BIT_APCPU_CORE_AUTO_GATE_EN + +/* bits definitions for register REG_AP_AHB_HOLDING_PEN */ +#define BITS_HOLDING_PEN(_x_) ( (_x_) << 0 ) + +/* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C0 */ +#define BITS_JMP_ADDR_APCPU_C0(_x_) (_x_) +#define BITS_JMP_ADDR_CA7_C0(_x_) BITS_JMP_ADDR_APCPU_C0 + +/* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C1 */ +#define BITS_JMP_ADDR_APCPU_C1(_x_) (_x_) +#define BITS_JMP_ADDR_CA7_C1(_x_) BITS_JMP_ADDR_APCPU_C1(_x_) + +/* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C2 */ +#define BITS_JMP_ADDR_APCPU_C2(_x_) (_x_) +#define BITS_JMP_ADDR_CA7_C2(_x_) BITS_JMP_ADDR_APCPU_C2(_x_) + +/* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C3 */ +#define BITS_JMP_ADDR_APCPU_C3(_x_) (_x_) +#define BITS_JMP_ADDR_CA7_C3(_x_) BITS_JMP_ADDR_APCPU_C3(_x_) + +/* bits definitions for register REG_AP_AHB_CA7_C0_PU_LOCK */ +#define BIT_APCPU_C0_PU_LOCK ( BIT(0) ) +#define BIT_CA7_C0_PU_LOCK BIT_APCPU_C0_PU_LOCK + +/* bits definitions for register REG_AP_AHB_CA7_C1_PU_LOCK */ +#define BIT_APCPU_C1_PU_LOCK ( BIT(0) ) +#define BIT_CA7_C1_PU_LOCK BIT_APCPU_C1_PU_LOCK + +/* bits definitions for register REG_AP_AHB_CA7_C2_PU_LOCK */ +#define BIT_APCPU_C2_PU_LOCK ( BIT(0) ) +#define BIT_CA7_C2_PU_LOCK BIT_APCPU_C2_PU_LOCK + +/* bits definitions for register REG_AP_AHB_CA7_C3_PU_LOCK */ +#define BIT_APCPU_C3_PU_LOCK ( BIT(0) ) +#define BIT_CA7_C3_PU_LOCK BIT_APCPU_C3_PU_LOCK + +/* bits definitions for register REG_AP_AHB_CA7_CKG_DIV_CFG */ +#define BITS_APCPU_TRACE_CKG_DIV(_x_) ( (_x_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_APCPU_DBG_CKG_DIV(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)) ) +#define BITS_APCPU_AXI_CKG_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_APCPU_MCU_CKG_DIV(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BITS_CA7_DBG_CKG_DIV(_x_) BITS_APCPU_DBG_CKG_DIV(_x_) +#define BITS_CA7_AXI_CKG_DIV(_x_) BITS_APCPU_AXI_CKG_DIV(_x_) +#define BITS_CA7_MCU_CKG_DIV(_x_) BITS_APCPU_MCU_CKG_DIV(_x_) + +/* bits definitions for register REG_AP_AHB_MCU_PAUSE */ +#define BIT_DMA_ACT_LIGHT_EN ( BIT(5) ) +#define BIT_MCU_SLEEP_FOLLOW_APCPU_EN ( BIT(4) ) +#define BIT_MCU_SLEEP_FOLLOW_CA7_EN BIT_MCU_SLEEP_FOLLOW_APCPU_EN +#define BIT_MCU_LIGHT_SLEEP_EN ( BIT(3) ) +#define BIT_MCU_DEEP_SLEEP_EN ( BIT(2) ) +#define BIT_MCU_SYS_SLEEP_EN ( BIT(1) ) +#define BIT_MCU_CORE_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_MISC_CKG_EN */ +#define BIT_ASHB_APCPU_DBG_VLD ( BIT(9) ) +#define BIT_ASHB_APCPU_DBG_EN ( BIT(8) ) +#define BIT_ASHB_CA7_DBG_VLD BIT_ASHB_APCPU_DBG_VLD +#define BIT_ASHB_CA7_DBG_EN BIT_ASHB_APCPU_DBG_EN +#define BIT_DISP_TMC_CKG_EN ( BIT(4) ) +#define BIT_DPHY_REF_CKG_EN ( BIT(1) ) +#define BIT_DPHY_CFG_CKG_EN ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_CA7_C0_AUTO_FORCE_SHUTDOWN_EN */ +#define BIT_APCPU_C0_AUTO_FORCE_SHUTDOWN_EN ( BIT(0) ) +#define BIT_CA7_C0_AUTO_FORCE_SHUTDOWN_EN BIT_APCPU_C0_AUTO_FORCE_SHUTDOWN_EN + +/* bits definitions for register REG_AP_AHB_CA7_C1_AUTO_FORCE_SHUTDOWN_EN */ +#define BIT_APCPU_C1_AUTO_FORCE_SHUTDOWN_EN ( BIT(0) ) +#define BIT_CA7_C1_AUTO_FORCE_SHUTDOWN_EN BIT_APCPU_C1_AUTO_FORCE_SHUTDOWN_EN + +/* bits definitions for register REG_AP_AHB_CA7_C2_AUTO_FORCE_SHUTDOWN_EN */ +#define BIT_APCPU_C2_AUTO_FORCE_SHUTDOWN_EN ( BIT(0) ) +#define BIT_CA7_C2_AUTO_FORCE_SHUTDOWN_EN BIT_APCPU_C2_AUTO_FORCE_SHUTDOWN_EN + +/* bits definitions for register REG_AP_AHB_CA7_C3_AUTO_FORCE_SHUTDOWN_EN */ +#define BIT_APCPU_C3_AUTO_FORCE_SHUTDOWN_EN ( BIT(0) ) +#define BIT_CA7_C3_AUTO_FORCE_SHUTDOWN_EN BIT_APCPU_C3_AUTO_FORCE_SHUTDOWN_EN + +/* bits definitions for register REG_AP_AHB_CA7_CKG_SEL_CFG */ +#define BITS_APCPU_MCU_CKG_SEL(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)) ) +#define BITS_CA7_MCU_CKG_SEL(_x_) BITS_APCPU_MCU_CKG_SEL(_x_) +/* bits definitions for register REG_AP_AHB_APCPU_AUTO_GATE_EN */ +#define BIT_APCPU_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_MISC_CFG */ +#define BIT_APCPU_L2RAM_LIGHT_SLEEP_EN ( BIT(22) ) +#define BIT_APCPU_AUTO_REG_SAVE_TRIG_SEL ( BIT(21) ) +#define BIT_APCPU_AUTO_REG_SAVE_EN ( BIT(20) ) +#define BITS_EMMC_SLOT_SEL(_x_) ( (_x_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_SDIO0_SLOT_SEL(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_BUSMON2_CHN_SEL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_BUSMON1_CHN_SEL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_BUSMON0_CHN_SEL(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_SDIO2_SLOT_SEL(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_SDIO1_SLOT_SEL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_AHB_AP_MAIN_MTX_HPROT_CFG */ +#define BITS_HPROT_NFC(_x_) ( (_x_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_HPROT_EMMC(_x_) ( (_x_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_HPROT_SDIO2(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_HPROT_SDIO1(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_HPROT_SDIO0(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_HPROT_DMAW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_HPROT_DMAR(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AP_AHB_CA7_STANDBY_STATUS */ +#define BIT_APCPU_STANDBYWFIL2 ( BIT(12) ) +#define BITS_APCPU_ETMSTANDBYWFX(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_APCPU_STANDBYWFE(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_APCPU_STANDBYWFI(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) +#define BIT_CA7_STANDBYWFIL2 BIT_APCPU_STANDBYWFIL2 +#define BITS_CA7_ETMSTANDBYWFX(_x_) BITS_APCPU_ETMSTANDBYWFX(_x_) +#define BITS_CA7_STANDBYWFE(_x_) BITS_APCPU_STANDBYWFE(_x_) +#define BITS_CA7_STANDBYWFI(_x_) BITS_APCPU_STANDBYWFI(_x_) +/* bits definitions for register REG_AP_AHB_NANC_CLK_CFG */ +#define BITS_CLK_NANDC2X_DIV(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_CLK_NANDC2X_SEL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_AHB_LVDS_CFG */ +#define BITS_LVDS_TXCLKDATA(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_LVDS_TXCOM(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_LVDS_TXSLEW(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_LVDS_TXSW(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_LVDS_TXRERSER(_x_) ( (_x_) << 3 & (BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_LVDS_PRE_EMP(_x_) ( (_x_) << 1 & (BIT(1)|BIT(2)) ) +#define BIT_LVDS_TXPD ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_LVDS_PLL_CFG0 */ +#define BIT_LVDS_PLL_LOCK_DET ( BIT(31) ) +#define BITS_LVDS_PLL_REFIN(_x_) ( (_x_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_LVDS_PLL_LPF(_x_) ( (_x_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BIT_LVDS_PLL_DIV_S ( BIT(18) ) +#define BITS_LVDS_PLL_IBIAS(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_LVDS_PLLN(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AP_AHB_LVDS_PLL_CFG1 */ +#define BITS_LVDS_PLL_KINT(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_LVDS_PLL_RSV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_LVDS_PLL_MOD_EN ( BIT(7) ) +#define BIT_LVDS_PLL_SDM_EN ( BIT(6) ) +#define BITS_LVDS_PLL_NINT(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_AP_AHB_AP_QOS_CFG */ +#define BITS_QOS_R_TMC(_x_) ( (_x_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_QOS_W_TMC(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_QOS_R_DISPC(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_QOS_W_DISPC(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AP_AHB_OTG_PHY_TUNE */ +#define BIT_OTG_TXPREEMPPULSETUNE ( BIT(20) ) +#define BITS_OTG_TXRESTUNE(_x_) ( (_x_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_OTG_TXHSXVTUNE(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_OTG_TXVREFTUNE(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_OTG_TXPREEMPAMPTUNE(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_OTG_TXRISETUNE(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_OTG_TXFSLSTUNE(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_OTG_SQRXTUNE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AP_AHB_OTG_PHY_TEST */ +#define BIT_OTG_ATERESET ( BIT(31) ) +#define BIT_OTG_VBUS_VALID_EXT_SEL ( BIT(26) ) +#define BIT_OTG_VBUS_VALID_EXT ( BIT(25) ) +#define BIT_OTG_OTGDISABLE ( BIT(24) ) +#define BIT_OTG_TESTBURNIN ( BIT(21) ) +#define BIT_OTG_LOOPBACKENB ( BIT(20) ) +#define BITS_OTG_TESTDATAOUT(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_OTG_VATESTENB(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BIT_OTG_TESTCLK ( BIT(13) ) +#define BIT_OTG_TESTDATAOUTSEL ( BIT(12) ) +#define BITS_OTG_TESTADDR(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_OTG_TESTDATAIN(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_AP_AHB_OTG_PHY_CTRL */ +#define BITS_OTG_SS_SCALEDOWNMODE(_x_) ( (_x_) << 25 & (BIT(25)|BIT(26)) ) +#define BIT_OTG_TXBITSTUFFENH ( BIT(23) ) +#define BIT_OTG_TXBITSTUFFEN ( BIT(22) ) +#define BIT_OTG_DMPULLDOWN ( BIT(21) ) +#define BIT_OTG_DPPULLDOWN ( BIT(20) ) +#define BIT_OTG_DMPULLUP ( BIT(9) ) +#define BIT_OTG_COMMONONN ( BIT(8) ) +#define BITS_OTG_REFCLKSEL(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_OTG_FSEL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AP_AHB_HSIC_PHY_TUNE */ +#define BITS_HSIC_REFCLK_DIV(_x_) ( (_x_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) ) +#define BIT_HSIC_TXPREEMPPULSETUNE ( BIT(20) ) +#define BITS_HSIC_TXRESTUNE(_x_) ( (_x_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_HSIC_TXHSXVTUNE(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_HSIC_TXVREFTUNE(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_HSIC_TXPREEMPAMPTUNE(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_HSIC_TXRISETUNE(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_HSIC_TXFSLSTUNE(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_HSIC_SQRXTUNE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AP_AHB_HSIC_PHY_TEST */ +#define BIT_HSIC_ATERESET ( BIT(31) ) +#define BIT_HSIC_VBUS_VALID_EXT_SEL ( BIT(26) ) +#define BIT_HSIC_VBUS_VALID_EXT ( BIT(25) ) +#define BIT_HSIC_OTGDISABLE ( BIT(24) ) +#define BIT_HSIC_TESTBURNIN ( BIT(21) ) +#define BIT_HSIC_LOOPBACKENB ( BIT(20) ) +#define BITS_HSIC_TESTDATAOUT(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_HSIC_VATESTENB(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BIT_HSIC_TESTCLK ( BIT(13) ) +#define BIT_HSIC_TESTDATAOUTSEL ( BIT(12) ) +#define BITS_HSIC_TESTADDR(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_HSIC_TESTDATAIN(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_AP_AHB_HSIC_PHY_CTRL */ +#define BITS_HSIC_SS_SCALEDOWNMODE(_x_) ( (_x_) << 25 & (BIT(25)|BIT(26)) ) +#define BIT_HSIC_TXBITSTUFFENH ( BIT(23) ) +#define BIT_HSIC_TXBITSTUFFEN ( BIT(22) ) +#define BIT_HSIC_DMPULLDOWN ( BIT(21) ) +#define BIT_HSIC_DPPULLDOWN ( BIT(20) ) +#define BIT_HSIC_IF_MODE ( BIT(16) ) +#define BIT_IF_SELECT_HSIC ( BIT(13) ) +#define BIT_HSIC_DBNCE_FLTR_BYPASS ( BIT(12) ) +#define BIT_HSIC_DMPULLUP ( BIT(9) ) +#define BIT_HSIC_COMMONONN ( BIT(8) ) +#define BITS_HSIC_REFCLKSEL(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_HSIC_FSEL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AP_AHB_ZIP_MTX_QOS_CFG */ +#define BITS_ZIPMTX_S0_ARQOS(_x_) ( (_x_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_ZIPMTX_S0_AWQOS(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_ZIPDEC_ARQOS(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_ZIPDEC_AWQOS(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_ZIPENC_ARQOS(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_ZIPENC_AWQOS(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) +/* bits definitions for register REG_AP_AHB_APCPU_QCHN_CTL */ +#define BITS_APCPU_Q_NEG_THD(_x_) ( (_x_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_APCPU_Q_WAIT_GAP(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_APCPU_Q_PGEN_DUR(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_APCPU_Q_WAIT_REQ(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_APCPU_Q_RETN_BYP ( BIT(2) ) +#define BIT_APCPU_Q_RETN_SEL ( BIT(1) ) +#define BIT_APCPU_Q_LP_EN ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_APCPU_QCHN_STA */ +#define BITS_APCPU_Q_STATUS(_x_) (_x_) + +/* bits definitions for register REG_AP_AHB_RES_REG */ +#define BITS_RES_REG(_x_) (_x_) + +/* bits definitions for register REG_AP_AHB_CHIP_ID */ +#define BITS_CHIP_ID(_x_) ( (_x_) << 0 ) + +/* vars definitions for controller REGS_AP_AHB */ + +#endif /* __REGS_AP_AHB_H__ */ diff --git a/include/soc/sprd/chip_x35l64/__regs_ap_apb.h b/include/soc/sprd/chip_x35l64/__regs_ap_apb.h new file mode 100755 index 00000000..36a3d4d6 --- /dev/null +++ b/include/soc/sprd/chip_x35l64/__regs_ap_apb.h @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_AP_APB_HEADFILE_H__ +#define __H_REGS_AP_APB_HEADFILE_H__ __FILE__ + +#define REGS_AP_APB + +/* registers definitions for AP_APB */ +#define REG_AP_APB_APB_EB SCI_ADDR(REGS_AP_APB_BASE, 0x0000) +#define REG_AP_APB_APB_RST SCI_ADDR(REGS_AP_APB_BASE, 0x0004) +#define REG_AP_APB_APB_MISC_CTRL SCI_ADDR(REGS_AP_APB_BASE, 0x0008) + + + +/* bits definitions for register REG_AP_APB_APB_EB */ +#define BIT_INTC3_EB ( BIT(22) ) +#define BIT_INTC2_EB ( BIT(21) ) +#define BIT_INTC1_EB ( BIT(20) ) +#define BIT_INTC0_EB ( BIT(19) ) +#define BIT_AP_APB_CKG_EB ( BIT(18) ) +#define BIT_AP_CKG_EB ( BIT_AP_APB_CKG_EB ) +#define BIT_UART4_EB ( BIT(17) ) +#define BIT_UART3_EB ( BIT(16) ) +#define BIT_UART2_EB ( BIT(15) ) +#define BIT_UART1_EB ( BIT(14) ) +#define BIT_UART0_EB ( BIT(13) ) +#define BIT_I2C4_EB ( BIT(12) ) +#define BIT_I2C3_EB ( BIT(11) ) +#define BIT_I2C2_EB ( BIT(10) ) +#define BIT_I2C1_EB ( BIT(9) ) +#define BIT_I2C0_EB ( BIT(8) ) +#define BIT_SPI2_EB ( BIT(7) ) +#define BIT_SPI1_EB ( BIT(6) ) +#define BIT_SPI0_EB ( BIT(5) ) +#define BIT_IIS3_EB ( BIT(4) ) +#define BIT_IIS2_EB ( BIT(3) ) +#define BIT_IIS1_EB ( BIT(2) ) +#define BIT_IIS0_EB ( BIT(1) ) +#define BIT_SIM0_EB ( BIT(0) ) + +/* bits definitions for register REG_AP_APB_APB_RST */ +#define BIT_INTC3_SOFT_RST ( BIT(22) ) +#define BIT_INTC2_SOFT_RST ( BIT(21) ) +#define BIT_INTC1_SOFT_RST ( BIT(20) ) +#define BIT_INTC0_SOFT_RST ( BIT(19) ) +#define BIT_AP_APB_CKG_SOFT_RST ( BIT(18) ) +#define BIT_AP_CKG_SOFT_RST BIT_AP_APB_CKG_SOFT_RST +#define BIT_UART4_SOFT_RST ( BIT(17) ) +#define BIT_UART3_SOFT_RST ( BIT(16) ) +#define BIT_UART2_SOFT_RST ( BIT(15) ) +#define BIT_UART1_SOFT_RST ( BIT(14) ) +#define BIT_UART0_SOFT_RST ( BIT(13) ) +#define BIT_I2C4_SOFT_RST ( BIT(12) ) +#define BIT_I2C3_SOFT_RST ( BIT(11) ) +#define BIT_I2C2_SOFT_RST ( BIT(10) ) +#define BIT_I2C1_SOFT_RST ( BIT(9) ) +#define BIT_I2C0_SOFT_RST ( BIT(8) ) +#define BIT_SPI2_SOFT_RST ( BIT(7) ) +#define BIT_SPI1_SOFT_RST ( BIT(6) ) +#define BIT_SPI0_SOFT_RST ( BIT(5) ) +#define BIT_IIS3_SOFT_RST ( BIT(4) ) +#define BIT_IIS2_SOFT_RST ( BIT(3) ) +#define BIT_IIS1_SOFT_RST ( BIT(2) ) +#define BIT_IIS0_SOFT_RST ( BIT(1) ) +#define BIT_SIM0_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_AP_APB_APB_MISC_CTRL */ +#define BIT_SIM_CLK_POLARITY ( BIT(1) ) +#define BIT_FMARK_POLARITY_INV ( BIT(0) ) + +#endif diff --git a/include/soc/sprd/chip_x35l64/__regs_ap_clk.h b/include/soc/sprd/chip_x35l64/__regs_ap_clk.h new file mode 100644 index 00000000..00f0e67c --- /dev/null +++ b/include/soc/sprd/chip_x35l64/__regs_ap_clk.h @@ -0,0 +1,223 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __H_REGS_AP_CLK_CORE_HEADFILE_H__ +#define __H_REGS_AP_CLK_CORE_HEADFILE_H__ __FILE__ + +/* registers definitions for AP_CLK_CORE */ +#define REG_AP_CLK_CORE_clk_ap_ahb_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x20)/*clk_ap_ahb_cfg*/ +#define REG_AP_CLK_CORE_clk_ap_apb_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x24)/*clk_ap_apb_cfg*/ +#define REG_AP_CLK_CORE_clk_gsp_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x28)/*clk_gsp_cfg*/ +#define REG_AP_CLK_CORE_clk_dispc0_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x2c)/*clk_dispc0_cfg*/ +#define REG_AP_CLK_CORE_clk_dispc0_dbi_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x30)/*clk_dispc0_dbi_cfg*/ +#define REG_AP_CLK_CORE_clk_dispc0_dpi_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x34)/*clk_dispc0_dpi_cfg*/ +#define REG_AP_CLK_CORE_clk_nandc_ecc_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x38)/*clk_nandc_ecc_cfg*/ +#define REG_AP_CLK_CORE_clk_sdio0_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x3c)/*clk_sdio0_cfg*/ +#define REG_AP_CLK_CORE_clk_sdio1_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x40)/*clk_sdio1_cfg*/ +#define REG_AP_CLK_CORE_clk_sdio2_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x44)/*clk_sdio2_cfg*/ +#define REG_AP_CLK_CORE_clk_emmc_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x48)/*clk_emmc_cfg*/ +#define REG_AP_CLK_CORE_clk_otg_ref_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x4c)/*clk_otg_ref_cfg*/ +#define REG_AP_CLK_CORE_clk_hsic_ref_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x50)/*clk_hsic_ref_cfg*/ +#define REG_AP_CLK_CORE_clk_uart0_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x54)/*clk_uart0_cfg*/ +#define REG_AP_CLK_CORE_clk_uart1_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x58)/*clk_uart1_cfg*/ +#define REG_AP_CLK_CORE_clk_uart2_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x5c)/*clk_uart2_cfg*/ +#define REG_AP_CLK_CORE_clk_uart3_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x60)/*clk_uart3_cfg*/ +#define REG_AP_CLK_CORE_clk_uart4_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x64)/*clk_uart4_cfg*/ +#define REG_AP_CLK_CORE_clk_i2c0_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x68)/*clk_i2c0_cfg*/ +#define REG_AP_CLK_CORE_clk_i2c1_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x6c)/*clk_i2c1_cfg*/ +#define REG_AP_CLK_CORE_clk_i2c2_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x70)/*clk_i2c2_cfg*/ +#define REG_AP_CLK_CORE_clk_i2c3_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x74)/*clk_i2c3_cfg*/ +#define REG_AP_CLK_CORE_clk_i2c4_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x78)/*clk_i2c4_cfg*/ +#define REG_AP_CLK_CORE_clk_spi0_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x7c)/*clk_spi0_cfg*/ +#define REG_AP_CLK_CORE_clk_spi1_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x80)/*clk_spi1_cfg*/ +#define REG_AP_CLK_CORE_clk_spi2_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x84)/*clk_spi2_cfg*/ +#define REG_AP_CLK_CORE_clk_iis0_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x88)/*clk_iis0_cfg*/ +#define REG_AP_CLK_CORE_clk_iis1_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x8c)/*clk_iis1_cfg*/ +#define REG_AP_CLK_CORE_clk_iis2_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x90)/*clk_iis2_cfg*/ +#define REG_AP_CLK_CORE_clk_iis3_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x94)/*clk_iis3_cfg*/ +#define REG_AP_CLK_CORE_clk_zipenc_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x98)/*clk_zipenc_cfg*/ +#define REG_AP_CLK_CORE_clk_zipdec_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x9c)/*clk_zipdec_cfg*/ + +#define REG_AP_CLK_AP_AHB_CFG REG_AP_CLK_CORE_clk_ap_ahb_cfg +#define REG_AP_CLK_AP_APB_CFG REG_AP_CLK_CORE_clk_ap_apb_cfg +#define REG_AP_CLK_GSP_CFG REG_AP_CLK_CORE_clk_gsp_cfg +#define REG_AP_CLK_DISPC0_CFG REG_AP_CLK_CORE_clk_dispc0_cfg +#define REG_AP_CLK_DISPC0_DBI_CFG REG_AP_CLK_CORE_clk_dispc0_dbi_cfg +#define REG_AP_CLK_DISPC0_DPI_CFG REG_AP_CLK_CORE_clk_dispc0_dpi_cfg +#define REG_AP_CLK_NANDC_ECC_CFG REG_AP_CLK_CORE_clk_nandc_ecc_cfg +#define REG_AP_CLK_SDIO0_CFG REG_AP_CLK_CORE_clk_sdio0_cfg +#define REG_AP_CLK_SDIO1_CFG REG_AP_CLK_CORE_clk_sdio1_cfg +#define REG_AP_CLK_SDIO2_CFG REG_AP_CLK_CORE_clk_sdio2_cfg +#define REG_AP_CLK_EMMC_CFG REG_AP_CLK_CORE_clk_emmc_cfg +#define REG_AP_CLK_OTG_REF_CFG REG_AP_CLK_CORE_clk_otg_ref_cfg +#define REG_AP_CLK_HSIC_REF_CFG REG_AP_CLK_CORE_clk_hsic_ref_cfg +#define REG_AP_CLK_UART0_CFG REG_AP_CLK_CORE_clk_uart0_cfg +#define REG_AP_CLK_UART1_CFG REG_AP_CLK_CORE_clk_uart1_cfg +#define REG_AP_CLK_UART2_CFG REG_AP_CLK_CORE_clk_uart2_cfg +#define REG_AP_CLK_UART3_CFG REG_AP_CLK_CORE_clk_uart3_cfg +#define REG_AP_CLK_UART4_CFG REG_AP_CLK_CORE_clk_uart4_cfg +#define REG_AP_CLK_I2C0_CFG REG_AP_CLK_CORE_clk_i2c0_cfg +#define REG_AP_CLK_I2C1_CFG REG_AP_CLK_CORE_clk_i2c1_cfg +#define REG_AP_CLK_I2C2_CFG REG_AP_CLK_CORE_clk_i2c2_cfg +#define REG_AP_CLK_I2C3_CFG REG_AP_CLK_CORE_clk_i2c3_cfg +#define REG_AP_CLK_I2C4_CFG REG_AP_CLK_CORE_clk_i2c4_cfg +#define REG_AP_CLK_SPI0_CFG REG_AP_CLK_CORE_clk_spi0_cfg +#define REG_AP_CLK_SPI1_CFG REG_AP_CLK_CORE_clk_spi1_cfg +#define REG_AP_CLK_SPI2_CFG REG_AP_CLK_CORE_clk_spi2_cfg +#define REG_AP_CLK_IIS0_CFG REG_AP_CLK_CORE_clk_iis0_cfg +#define REG_AP_CLK_IIS1_CFG REG_AP_CLK_CORE_clk_iis1_cfg +#define REG_AP_CLK_IIS2_CFG REG_AP_CLK_CORE_clk_iis2_cfg +#define REG_AP_CLK_IIS3_CFG REG_AP_CLK_CORE_clk_iis3_cfg +#define REG_AP_CLK_ZIPENC_CFG REG_AP_CLK_CORE_clk_zipenc_cfg +#define REG_AP_CLK_ZIPDEC_CFG REG_AP_CLK_CORE_clk_zipdec_cfg + + +/* bits definitions for register REG_AP_CLK_CORE_clk_ap_ahb_cfg */ +#define BITS_CLK_AP_AHB_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_ap_apb_cfg */ +#define BITS_CLK_AP_APB_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_gsp_cfg */ +#define BITS_CLK_GSP_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_dispc0_cfg */ +#define BITS_CLK_DISPC0_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_DISPC0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_dispc0_dbi_cfg */ +#define BITS_CLK_DISPC0_DBI_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_DISPC0_DBI_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_dispc0_dpi_cfg */ +#define BIT_CLK_DISPC0_DPI_PAD_SEL ( BIT(16) ) +#define BITS_CLK_DISPC0_DPI_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_CLK_DISPC0_DPI_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_nandc_ecc_cfg */ +#define BIT_CLK_NANDC_ECC_SEL ( BIT(0) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_sdio0_cfg */ +#define BITS_CLK_SDIO0_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_SDIO0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_sdio1_cfg */ +#define BITS_CLK_SDIO1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_sdio2_cfg */ +#define BITS_CLK_SDIO2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_emmc_cfg */ +#define BITS_CLK_EMMC_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_otg_ref_cfg */ +#define BIT_CLK_OTG_REF_SEL ( BIT(0) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_hsic_ref_cfg */ +#define BIT_CLK_HSIC_REF_SEL ( BIT(0) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_uart0_cfg */ +#define BITS_CLK_UART0_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_UART0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_uart1_cfg */ +#define BITS_CLK_UART1_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_UART1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_uart2_cfg */ +#define BITS_CLK_UART2_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_UART2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_uart3_cfg */ +#define BITS_CLK_UART3_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_UART3_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_uart4_cfg */ +#define BITS_CLK_UART4_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_UART4_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_i2c0_cfg */ +#define BITS_CLK_I2C0_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_I2C0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_i2c1_cfg */ +#define BITS_CLK_I2C1_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_I2C1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_i2c2_cfg */ +#define BITS_CLK_I2C2_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_I2C2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_i2c3_cfg */ +#define BITS_CLK_I2C3_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_I2C3_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_i2c4_cfg */ +#define BITS_CLK_I2C4_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_I2C4_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_spi0_cfg */ +#define BIT_CLK_SPI0_PAD_SEL ( BIT(16) ) +#define BITS_CLK_SPI0_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_SPI0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_spi1_cfg */ +#define BIT_CLK_SPI1_PAD_SEL ( BIT(16) ) +#define BITS_CLK_SPI1_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_SPI1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_spi2_cfg */ +#define BIT_CLK_SPI2_PAD_SEL ( BIT(16) ) +#define BITS_CLK_SPI2_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_SPI2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_iis0_cfg */ +#define BIT_CLK_IIS0_PAD_SEL ( BIT(16) ) +#define BITS_CLK_IIS0_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_IIS0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_iis1_cfg */ +#define BIT_CLK_IIS1_PAD_SEL ( BIT(16) ) +#define BITS_CLK_IIS1_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_IIS1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_iis2_cfg */ +#define BIT_CLK_IIS2_PAD_SEL ( BIT(16) ) +#define BITS_CLK_IIS2_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_IIS2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_iis3_cfg */ +#define BIT_CLK_IIS3_PAD_SEL ( BIT(16) ) +#define BITS_CLK_IIS3_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_IIS3_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_zipenc_cfg */ +#define BITS_CLK_ZIPENC_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_zipdec_cfg */ +#define BITS_CLK_ZIPDEC_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) +/* vars definitions for controller REGS_AP_CLK */ + +/* vars definitions for REG_AP_CLK_AP_AHB_CFG */ +#define AP_AHB_CLK_SEL_SHIFT (0) +#define AP_AHB_CLK_SEL_MASK (0x3 << AP_AHB_CLK_SEL_SHIFT) + +#define AP_APB_CLK_SEL_SHIFT (0) +#define AP_APB_CLK_SEL_MASK (0x3 << AP_AHB_CLK_SEL_SHIFT) + +#endif //__REGS_AP_CLK_H__ diff --git a/include/soc/sprd/chip_x35l64/__regs_arm7_ahb_rf.h b/include/soc/sprd/chip_x35l64/__regs_arm7_ahb_rf.h new file mode 100755 index 00000000..784081ab --- /dev/null +++ b/include/soc/sprd/chip_x35l64/__regs_arm7_ahb_rf.h @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_ARM7_AHB_RF_HEADFILE_H__ +#define __H_REGS_ARM7_AHB_RF_HEADFILE_H__ __FILE__ + +#define REGS_ARM7_AHB_RF + +/* registers definitions for ARM7_AHB_RF */ +#define REG_ARM7_AHB_RF_ARM7_EB SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0000) +#define REG_ARM7_AHB_RF_ARM7_SOFT_RST SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0004) +#define REG_ARM7_AHB_RF_AHB_PAUSE SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0008) +#define REG_ARM7_AHB_RF_ARM7_SLP_CTL SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x000C) + + + +/* bits definitions for register REG_ARM7_AHB_RF_ARM7_EB */ +#define BIT_ARM7_GPIO_EB ( BIT(10) ) +#define BIT_ARM7_UART_EB ( BIT(9) ) +#define BIT_ARM7_TMR_EB ( BIT(8) ) +#define BIT_ARM7_SYST_EB ( BIT(7) ) +#define BIT_ARM7_WDG_EB ( BIT(6) ) +#define BIT_ARM7_EIC_EB ( BIT(5) ) +#define BIT_ARM7_INTC_EB ( BIT(4) ) +#define BIT_ARM7_IMC_EB ( BIT(2) ) +#define BIT_ARM7_TIC_EB ( BIT(1) ) +#define BIT_ARM7_DMA_EB ( BIT(0) ) + +/* bits definitions for register REG_ARM7_AHB_RF_ARM7_SOFT_RST */ +#define BIT_ARM7_GPIO_SOFT_RST ( BIT(10) ) +#define BIT_ARM7_UART_SOFT_RST ( BIT(9) ) +#define BIT_ARM7_TMR_SOFT_RST ( BIT(8) ) +#define BIT_ARM7_SYST_SOFT_RST ( BIT(7) ) +#define BIT_ARM7_WDG_SOFT_RST ( BIT(6) ) +#define BIT_ARM7_EIC_SOFT_RST ( BIT(5) ) +#define BIT_ARM7_INTC_SOFT_RST ( BIT(4) ) +#define BIT_ARM7_IMC_SOFT_RST ( BIT(2) ) +#define BIT_ARM7_TIC_SOFT_RST ( BIT(1) ) +#define BIT_ARM7_ARCH_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_ARM7_AHB_RF_AHB_PAUSE */ +#define BIT_ARM7_DEEP_SLEEP_EN ( BIT(2) ) +#define BIT_ARM7_SYS_SLEEP_EN ( BIT(1) ) +#define BIT_ARM7_CORE_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_ARM7_AHB_RF_ARM7_SLP_CTL */ +#define BIT_ARM7_SYS_AUTO_GATE_EN ( BIT(2) ) +#define BIT_ARM7_AHB_AUTO_GATE_EN ( BIT(1) ) +#define BIT_ARM7_CORE_AUTO_GATE_EN ( BIT(0) ) + +#endif diff --git a/include/soc/sprd/chip_x35l64/__regs_avs_apb_rf.h b/include/soc/sprd/chip_x35l64/__regs_avs_apb_rf.h new file mode 100644 index 00000000..aef34590 --- /dev/null +++ b/include/soc/sprd/chip_x35l64/__regs_avs_apb_rf.h @@ -0,0 +1,108 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_AVS_APB_RF_HEADFILE_H__ +#define __H_REGS_AVS_APB_RF_HEADFILE_H__ __FILE__ + +#define REGS_AVS_APB_RF + +/* registers definitions for AVS_APB_RF */ +#define REG_AVS_APB_RF_AVS_TUNE_LMT_CFG SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0000) +#define REG_AVS_APB_RF_AVS_TUNE_STATUS SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0004) +#define REG_AVS_APB_RF_AVS_CFG SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0008) +#define REG_AVS_APB_RF_AVS_TUNE_STEP_CFG SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x000C) +#define REG_AVS_APB_RF_AVS_WAIT_CFG SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0010) +#define REG_AVS_APB_RF_AVS_INT_CFG SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0014) +#define REG_AVS_APB_RF_AVS_START_SINGLE_ACT SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0018) +#define REG_AVS_APB_RF_AVS_START_REPEAT_ACT SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x001C) +#define REG_AVS_APB_RF_AVS_HPM_EN SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0020) +#define REG_AVS_APB_RF_AVS_HPM_RPT_ANLS SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0024) +#define REG_AVS_APB_RF_AVS_HPM_RPT_VLD_STATUS_0 SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0028) +#define REG_AVS_APB_RF_AVS_HPM_RPT_VLD_STATUS_1 SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x002C) +#define REG_AVS_APB_RF_FSM_STS SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0030) + + + +/* bits definitions for register REG_AVS_APB_RF_AVS_TUNE_LMT_CFG */ +#define BITS_VOLT_TUNE_VAL_MAX(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_VOLT_TUNE_VAL_MIN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_TUNE_STATUS */ +#define BITS_VOLT_TUNE_VAL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_VOLT_OBS_VAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_CFG */ +#define BIT_HPM3_RPT_CHKSUM_ERR_EN ( BIT(19) ) +#define BIT_HPM2_RPT_CHKSUM_ERR_EN ( BIT(18) ) +#define BIT_HPM1_RPT_CHKSUM_ERR_EN ( BIT(17) ) +#define BIT_HPM0_RPT_CHKSUM_ERR_EN ( BIT(16) ) +#define BIT_PAUSE_OCCUR_ERR_EN ( BIT(8) ) +#define BIT_VOLT_TUNE_FORBID_EN ( BIT(4) ) +#define BIT_VOLT_OBS_FORBID_EN ( BIT(0) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_TUNE_STEP_CFG */ +#define BITS_VOLT_TUNE_DOWN_STEP(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) ) +#define BITS_VOLT_TUNE_UP_STEP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_WAIT_CFG */ +#define BITS_RND_INTVAL_WAIT_NUM(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_VOLT_STB_WAIT_NUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_INT_CFG */ +#define BIT_AVS_TUNE_DONE_INT_MASK_STATUS ( BIT(13) ) +#define BIT_AVS_TUNE_ERR_INT_MASK_STATUS ( BIT(12) ) +#define BIT_AVS_TUNE_DONE_INT_RAW_STATUS ( BIT(9) ) +#define BIT_AVS_TUNE_ERR_INT_RAW_STATUS ( BIT(8) ) +#define BIT_AVS_TUNE_DONE_INT_CLR ( BIT(5) ) +#define BIT_AVS_TUNE_ERR_INT_CLR ( BIT(4) ) +#define BIT_AVS_TUNE_DONE_INT_EN ( BIT(1) ) +#define BIT_AVS_TUNE_ERR_INT_EN ( BIT(0) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_START_SINGLE_ACT */ +#define BIT_AVS_START_SINGLE_ACT ( BIT(0) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_START_REPEAT_ACT */ +#define BIT_AVS_START_REPEAT_ACT ( BIT(0) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_HPM_EN */ +#define BIT_HPM3_EN ( BIT(3) ) +#define BIT_HPM2_EN ( BIT(2) ) +#define BIT_HPM1_EN ( BIT(1) ) +#define BIT_HPM0_EN ( BIT(0) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_HPM_RPT_ANLS */ +#define BITS_HPM_RPT_TUNE_DWN_MARK(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_HPM_RPT_TUNE_UP_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_HPM_RPT_VLD_STATUS_0 */ +#define BITS_HPM1_RPT_VLD(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_HPM0_RPT_VLD(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_HPM_RPT_VLD_STATUS_1 */ +#define BITS_HPM3_RPT_VLD(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_HPM2_RPT_VLD(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AVS_APB_RF_FSM_STS */ +#define BITS_AVS_FSM_STS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +#endif diff --git a/include/soc/sprd/chip_x35l64/__regs_cortex_ahb_rf.h b/include/soc/sprd/chip_x35l64/__regs_cortex_ahb_rf.h new file mode 100755 index 00000000..e9d8f3c0 --- /dev/null +++ b/include/soc/sprd/chip_x35l64/__regs_cortex_ahb_rf.h @@ -0,0 +1,203 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_CORTEX_AHB_RF_HEADFILE_H__ +#define __H_REGS_CORTEX_AHB_RF_HEADFILE_H__ __FILE__ + +#define REGS_CORTEX_AHB_RF + +/* registers definitions for CORTEX_AHB_RF */ +#define REG_CORTEX_AHB_RF_CLK_CORTEX_AXI_CTRL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0000)/*CORTEX_AXI clock control*/ +#define REG_CORTEX_AHB_RF_CLK_CORTEX_AHB_CTRL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0004)/*CORTEX_AHB clock control*/ +#define REG_CORTEX_AHB_RF_CLK_CORTEX_APB_CTRL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0008)/*CORTEX_APB clock control*/ +#define REG_CORTEX_AHB_RF_CLK_SEC0_CTRL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x000C)/*SEC0 clock control*/ +#define REG_CORTEX_AHB_RF_CLK_SEC1_CTRL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0010)/*SEC1 clock control*/ +#define REG_CORTEX_AHB_RF_CA5_CFG SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0030)/* CortexA5 config*/ +#define REG_CORTEX_AHB_RF_AHB_CTRL0 SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0034)/*AHB control 0*/ +#define REG_CORTEX_AHB_RF_AHB_CTRL2 SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x003C)/*AHB control 2*/ +#define REG_CORTEX_AHB_RF_AHB_RST0_STS SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0060)/*AHB software reset*/ +#define REG_CORTEX_AHB_RF_CA5_RST_SET SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0064) +#define REG_CORTEX_AHB_RF_ARCH_EB SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0068) +#define REG_CORTEX_AHB_RF_PTEST_FUNC SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x006C) +#define REG_CORTEX_AHB_RF_AHB_MISC_CTL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0070) +#define REG_CORTEX_AHB_RF_CA5_CTRL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0074)/* Cortex A5 control*/ +#define REG_CORTEX_AHB_RF_AUTO_GATE_CTRL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0078)/*Auto gate control*/ +#define REG_CORTEX_AHB_RF_AHB_PAUSE SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0080)/*AHB sleep control*/ +#define REG_CORTEX_AHB_RF_AHB_SLP_CTL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0084) +#define REG_CORTEX_AHB_RF_AHB_SLP_STS SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0088) +#define REG_CORTEX_AHB_RF_MCU_CLK_CTL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x008C) +#define REG_CORTEX_AHB_RF_RES_REG0 SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x00F4) +#define REG_CORTEX_AHB_RF_CHIP_ID SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0200) + + + +/* bits definitions for register REG_CORTEX_AHB_RF_CLK_CORTEX_AXI_CTRL */ +#define BITS_CLK_CORTEX_AXI_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_CLK_CORTEX_AHB_CTRL */ +#define BITS_CLK_CORTEX_AHB_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_CLK_CORTEX_APB_CTRL */ +#define BITS_CLK_CORTEX_APB_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_CLK_SEC0_CTRL */ +#define BITS_CLK_SEC0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_CLK_SEC1_CTRL */ +#define BITS_CLK_SEC1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_CA5_CFG */ +#define BITS_CA5_DBG_DIV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_CA5_AXI_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CA5_MCU_DIV(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BITS_CA5_MCU_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_AHB_CTRL0 */ +#define BITS_TFT_MST_HPROT(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_PPP1_MST_HPROT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_PPP0_MST_HPROT(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_TFT_EB ( BIT(18) ) +#define BIT_PPP1_EB ( BIT(17) ) +#define BIT_PPP0_EB ( BIT(16) ) +#define BITS_SEC1_MST_HPROT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_SEC0_MST_HPROT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BIT_SEC1_EB ( BIT(5) ) +#define BIT_SEC1_CKG_EN ( BIT(4) ) +#define BIT_SEC0_EB ( BIT(3) ) +#define BIT_SEC0_CKG_EN ( BIT(2) ) +#define BIT_DMA_EB ( BIT(1) ) +#define BIT_DMA_CKG_EN ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_AHB_CTRL2 */ +#define BITS_BUSMON1_CHN_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_AXIBUSMON_CHN_SEL(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_BUSMON0_CHN_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BIT_BUSMON1_EB ( BIT(3) ) +#define BIT_SPINLOCK_EB ( BIT(2) ) +#define BIT_AXIBUSMON_EB ( BIT(1) ) +#define BIT_BUSMON0_EB ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_AHB_RST0_STS */ +#define BIT_TFT_SOFT_RST ( BIT(11) ) +#define BIT_PPP1_SOFT_RST ( BIT(10) ) +#define BIT_PPP0_SOFT_RST ( BIT(9) ) +#define BIT_SEC1_CMD_PARSER_RST ( BIT(8) ) +#define BIT_SEC0_CMD_PARSER_RST ( BIT(7) ) +#define BIT_SPINLOCK_SOFT_RST ( BIT(6) ) +#define BIT_SEC1_SOFT_RST ( BIT(5) ) +#define BIT_SEC0_SOFT_RST ( BIT(4) ) +#define BIT_BUSMON1_SOFT_RST ( BIT(3) ) +#define BIT_AXIBUSMON_SOFT_RST ( BIT(2) ) +#define BIT_BUSMON0_SOFT_RST ( BIT(1) ) +#define BIT_DMA_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_CA5_RST_SET */ +#define BIT_CA5_MTX_SOFT_RST ( BIT(3) ) +#define BIT_CA5_L2_SOFT_RST ( BIT(2) ) +#define BIT_CA5_DBG_SOFT_RST ( BIT(1) ) +#define BIT_CA5_CORE_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_ARCH_EB */ +#define BIT_AHB_ARCH_EB ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_PTEST_FUNC */ +#define BIT_PTEST_FUNC_ATSPEED_SEL ( BIT(2) ) +#define BIT_PTEST_FUNC_MODE ( BIT(1) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_AHB_MISC_CTL */ +#define BITS_DMA_W_PROT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMA_R_PROT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BIT_LCP2PUB_ACCESS_EN ( BIT(4) ) +#define BITS_MCU_SHM_CTRL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_CA5_CTRL */ +#define BIT_CA5_WDRESET_EN ( BIT(18) ) +#define BIT_CA5_TS_EN ( BIT(17) ) +#define BIT_CA5_CFGSDISABLE ( BIT(13) ) +#define BITS_CA5_CLK_AXI_DIV(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)) ) +#define BIT_CA5_CLK_DBG_EN_SEL ( BIT(10) ) +#define BIT_CA5_CLK_DBG_EN ( BIT(9) ) +#define BIT_CA5_DBGEN ( BIT(8) ) +#define BIT_CA5_NIDEN ( BIT(7) ) +#define BIT_CA5_SPIDEN ( BIT(6) ) +#define BIT_CA5_SPNIDEN ( BIT(5) ) +#define BIT_CA5_CP15DISABLE ( BIT(4) ) +#define BIT_CA5_TEINIT ( BIT(3) ) +#define BIT_CA5_L1RSTDISABLE ( BIT(2) ) +#define BIT_CA5_L2CFGEND ( BIT(1) ) +#define BIT_CA5_L2SPNIDEN ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_AUTO_GATE_CTRL */ +#define BIT_CORTEX_AHB_AUTO_GATE_EN ( BIT(5) ) +#define BIT_CA5_DBG_FORCE_SLEEP ( BIT(4) ) +#define BIT_CA5_DBG_AUTO_GATE_EN ( BIT(3) ) +#define BIT_CA5_CORE_AUTO_GATE_EN ( BIT(2) ) +#define BIT_LCPX_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_AHB_PAUSE */ +#define BIT_EMC_LIGHT_SLEEP_EN ( BIT(25) ) +#define BIT_EMC_DEEP_SLEEP_EN ( BIT(24) ) +#define BIT_APB_SLEEP_EN ( BIT(18) ) +#define BIT_APB_PERI_FRC_SLP ( BIT(17) ) +#define BIT_APB_PERI_FRC_ON ( BIT(16) ) +#define BIT_MCU_FORCE_DEEP_SLEEP ( BIT(15) ) +#define BIT_DMA_LSLP_EN ( BIT(4) ) +#define BIT_MCU_LIGHT_SLEEP_EN ( BIT(3) ) +#define BIT_MCU_DEEP_SLEEP_EN ( BIT(2) ) +#define BIT_MCU_SYS_SLEEP_EN ( BIT(1) ) +#define BIT_MCU_CORE_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_AHB_SLP_CTL */ +#define BIT_ARM_DAHB_SLEEP_EN ( BIT(4) ) +#define BIT_MCUMTX_AUTO_GATE_EN ( BIT(3) ) +#define BIT_MCU_AUTO_GATE_EN ( BIT(2) ) +#define BIT_AHB_AUTO_GATE_EN ( BIT(1) ) +#define BIT_ARM_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_AHB_SLP_STS */ +#define BIT_CHIP_SLP_ARM_CLR ( BIT(5) ) +#define BIT_CHIP_SLEEP_REC_ARM ( BIT(4) ) +#define BIT_APB_PERI_SLEEP ( BIT(3) ) +#define BIT_DMA_BUSY ( BIT(1) ) +#define BIT_EMC_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_MCU_CLK_CTL */ +#define BIT_CLK_LCP2LDSP_BRG_EN ( BIT(24) ) +#define BIT_CLK_LCP2PUB_BRG_EN ( BIT(23) ) +#define BIT_CLK_LCP2CP0_BRG_EN ( BIT(22) ) +#define BIT_CLK_CP_DBG_SEL ( BIT(21) ) +#define BIT_CLK_MCU_DBG_SEL ( BIT(20) ) +#define BITS_CLK_COM_DBG_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_CLK_SYS_DBG_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_CLK_AHB_DIV(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_CLK_MCU_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_APB_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CLK_MCU_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_RES_REG0 */ +#define BITS_RES_REG0(_X_) (_X_) + +/* bits definitions for register REG_CORTEX_AHB_RF_CHIP_ID */ +#define BITS_CHIP_ID(_X_) (_X_) + +#endif diff --git a/include/soc/sprd/chip_x35l64/__regs_cortex_glb.h b/include/soc/sprd/chip_x35l64/__regs_cortex_glb.h new file mode 100755 index 00000000..9c2abe91 --- /dev/null +++ b/include/soc/sprd/chip_x35l64/__regs_cortex_glb.h @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_CORTEX_GLB_HEADFILE_H__ +#define __H_REGS_CORTEX_GLB_HEADFILE_H__ __FILE__ + +#define REGS_CORTEX_GLB + +/* registers definitions for CORTEX_GLB */ +#define REG_CORTEX_GLB_APB_EB0_STS SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0008) +#define REG_CORTEX_GLB_APB_RST0_STS SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0014) +#define REG_CORTEX_GLB_APB_MCU_RST SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0018) +#define REG_CORTEX_GLB_APB_CLK_SEL0 SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x001C) +#define REG_CORTEX_GLB_APB_CLK_SEL1 SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0020) +#define REG_CORTEX_GLB_APB_ARCH_EB SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0024) +#define REG_CORTEX_GLB_APB_MISC_CTL0 SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0028) +#define REG_CORTEX_GLB_APB_MISC_CTL1 SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x002C) +#define REG_CORTEX_GLB_APB_CLK_SEL2 SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0030) +#define REG_CORTEX_GLB_APB_BUS_CTL0 SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0058) +#define REG_CORTEX_GLB_APB_MEM_LP_CTRL0 SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x005c) +#define REG_CORTEX_GLB_APB_MEM_LP_CTRL1 SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0060) +#define REG_CORTEX_GLB_APB_DSP_INT_CLR SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0074) +#define REG_CORTEX_GLB_APB_MISC_INT_STS SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0078) +#define REG_CORTEX_GLB_APB_HWRST SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0080) +#define REG_CORTEX_GLB_APB_ARM_BOOT_ADDR SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0084) + + + +/* bits definitions for register REG_CORTEX_GLB_APB_EB0_STS */ +#define BIT_EIC_RTC_EB ( BIT(19) ) +#define BIT_EIC_EB ( BIT(18) ) +#define BIT_RFFE_EB ( BIT(17) ) +#define BIT_EPT_EB ( BIT(16) ) +#define BIT_GPIO_EB ( BIT(15) ) +#define BIT_TMR_RTC_EB ( BIT(14) ) +#define BIT_TMR_EB ( BIT(13) ) +#define BIT_SYSTMR_RTC_EB ( BIT(12) ) +#define BIT_SYSTMR_EB ( BIT(11) ) +#define BIT_IIS3_EB ( BIT(10) ) +#define BIT_IIS2_EB ( BIT(9) ) +#define BIT_IIS1_EB ( BIT(8) ) +#define BIT_IIS0_EB ( BIT(7) ) +#define BIT_SIM2_EB ( BIT(6) ) +#define BIT_SIM1_EB ( BIT(5) ) +#define BIT_SIM0_EB ( BIT(4) ) +#define BIT_UART1_EB ( BIT(3) ) +#define BIT_UART0_EB ( BIT(2) ) +#define BIT_WDG_RTC_EB ( BIT(1) ) +#define BIT_WDG_EB ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_RST0_STS */ +#define BIT_EIC_SOFT_RST ( BIT(16) ) +#define BIT_RFFE_SOFT_RST ( BIT(15) ) +#define BIT_MCU_DSP_RST ( BIT(14) ) +#define BIT_EPT_SOFT_RST ( BIT(13) ) +#define BIT_GPIO_SOFT_RST ( BIT(12) ) +#define BIT_TMR_SOFT_RST ( BIT(11) ) +#define BIT_SYSTMR_SOFT_RST ( BIT(10) ) +#define BIT_IIS3_SOFT_RST ( BIT(9) ) +#define BIT_IIS2_SOFT_RST ( BIT(8) ) +#define BIT_IIS1_SOFT_RST ( BIT(7) ) +#define BIT_IIS0_SOFT_RST ( BIT(6) ) +#define BIT_SIM2_SOFT_RST ( BIT(5) ) +#define BIT_SIM1_SOFT_RST ( BIT(4) ) +#define BIT_SIM0_SOFT_RST ( BIT(3) ) +#define BIT_UART1_SOFT_RST ( BIT(2) ) +#define BIT_UART0_SOFT_RST ( BIT(1) ) +#define BIT_WDG_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_MCU_RST */ +#define BIT_MCU_SOFT_RST_SET ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_CLK_SEL0 */ +#define BITS_CLK_UART1_DIV(_X_) ( (_X_) << 7 & (BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_CLK_UART1_SEL(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)) ) +#define BITS_CLK_UART0_DIV(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)) ) +#define BITS_CLK_UART0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_CLK_SEL1 */ +#define BIT_CLK_IIS1_PAD_SEL ( BIT(24) ) +#define BITS_CLK_IIS1_DIV(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_CLK_IIS1_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BIT_CLK_IIS0_PAD_SEL ( BIT(8) ) +#define BITS_CLK_IIS0_DIV(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_CLK_IIS0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_ARCH_EB */ +#define BIT_RTC_ARCH_EB ( BIT(1) ) +#define BIT_APB_ARCH_EB ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_MISC_CTL0 */ +#define BIT_ALL_CLK_EN ( BIT(28) ) +#define BIT_DMA_LSLP_EN ( BIT(27) ) +#define BIT_WAKEUP_XTL_EN_3G ( BIT(26) ) +#define BIT_WAKEUP_XTL_EN_2G ( BIT(25) ) +#define BIT_ARM_JTAG_EN ( BIT(24) ) +#define BITS_ARM_FRC_STOP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_MISC_CTL1 */ +#define BITS_BUFON_CTRL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_SIM2_CLK_POLARITY ( BIT(3) ) +#define BIT_SIM1_CLK_POLARITY ( BIT(2) ) +#define BIT_SIM0_CLK_POLARITY ( BIT(1) ) +#define BIT_ROM_CLK_EN ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_CLK_SEL2 */ +#define BIT_CLK_IIS3_PAD_SEL ( BIT(24) ) +#define BITS_CLK_IIS3_DIV(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_CLK_IIS3_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BIT_CLK_IIS2_PAD_SEL ( BIT(8) ) +#define BITS_CLK_IIS2_DIV(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_CLK_IIS2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_BUS_CTL0 */ +#define BIT_IIS3_CTRL_SEL ( BIT(7) ) +#define BIT_IIS2_CTRL_SEL ( BIT(6) ) +#define BIT_RFFE_CTRL_SEL ( BIT(5) ) +#define BIT_IIS1_CTRL_SEL ( BIT(3) ) +#define BIT_IIS0_CTRL_SEL ( BIT(2) ) +#define BIT_UART0_CTRL_SEL ( BIT(1) ) +#define BIT_UART1_CTRL_SEL ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_MEM_LP_CTRL0 */ +#define BITS_APB_MEM_LP_CTRL0(_X_) (_X_) + +/* bits definitions for register REG_CORTEX_GLB_APB_MEM_LP_CTRL1 */ +#define BITS_APB_MEM_LP_CTRL1(_X_) (_X_) + +/* bits definitions for register REG_CORTEX_GLB_APB_DSP_INT_CLR */ +#define BIT_RFT_INT_CLR ( BIT(2) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_MISC_INT_STS */ +#define BIT_RFT_INT ( BIT(2) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_HWRST */ +#define BITS_HWRST_REG(_X_) (_X_) + +/* bits definitions for register REG_CORTEX_GLB_APB_ARM_BOOT_ADDR */ +#define BITS_ARMBOOT_ADDR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +#endif diff --git a/include/soc/sprd/chip_x35l64/__regs_cp_ahb_rf.h b/include/soc/sprd/chip_x35l64/__regs_cp_ahb_rf.h new file mode 100755 index 00000000..26130206 --- /dev/null +++ b/include/soc/sprd/chip_x35l64/__regs_cp_ahb_rf.h @@ -0,0 +1,297 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_CP_AHB_RF_HEADFILE_H__ +#define __H_REGS_CP_AHB_RF_HEADFILE_H__ __FILE__ + +#define REGS_CP_AHB_RF + +/* registers definitions for CP_AHB_RF */ +#define REG_CP_AHB_RF_AHB_EB0_STS SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0008) +#define REG_CP_AHB_RF_AHB_RST0_STS SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0014) +#define REG_CP_AHB_RF_ARCH_EB SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0018) +#define REG_CP_AHB_RF_AHB_REMAP SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x001C) +#define REG_CP_AHB_RF_AHB_MISC_CTL SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0020) +#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL0 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0024) +#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL1 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0028) +#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL2 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x002C) +#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL3 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0030) +#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL4 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0034) +#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL5 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0038) +#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL6 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x003C) +#define REG_CP_AHB_RF_AHB_PAUSE SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0040) +#define REG_CP_AHB_RF_AHB_SLP_CTL SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0044) +#define REG_CP_AHB_RF_AHB_SLP_STS SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0048) +#define REG_CP_AHB_RF_MCU_CLK_CTL SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x004C) +#define REG_CP_AHB_RF_DSP_CTL SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0050) +#define REG_CP_AHB_RF_DSP_BOOT_VECTOR SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0054) +#define REG_CP_AHB_RF_DSP_RST SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0058) +#define REG_CP_AHB_RF_DSP_JTAG_CTL SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x005C) +#define REG_CP_AHB_RF_MCU_C2C_SEMA SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0060) +#define REG_CP_AHB_RF_GGE_DSP_BOOT_VECTOR SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0064) +#define REG_CP_AHB_RF_CHIP_ID SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x01FC) + + + +/* bits definitions for register REG_CP_AHB_RF_AHB_EB0_STS */ +#define BIT_LZMA_EN ( BIT(11) ) +#define BIT_WCDMA_EN5 ( BIT(9) ) +#define BIT_WCDMA_EN4 ( BIT(8) ) +#define BIT_WCDMA_EN3 ( BIT(7) ) +#define BIT_WCDMA_EN2 ( BIT(6) ) +#define BIT_WCDMA_EN1 ( BIT(5) ) +#define BIT_WCDMA_EN0 ( BIT(4) ) +#define BIT_BUSMON2_EN ( BIT(3) ) +#define BIT_BUSMON1_EN ( BIT(2) ) +#define BIT_BUSMON0_EN ( BIT(1) ) +#define BIT_DMA_EN ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_RST0_STS */ +#define BIT_LZMA_SOFT_RST ( BIT(8) ) +#define BIT_WSYS_SOFT_RST ( BIT(6) ) +#define BIT_ARM1_SOFT_RST ( BIT(4) ) +#define BIT_BUSMON2_SOFT_RST ( BIT(3) ) +#define BIT_BUSMON1_SOFT_RST ( BIT(2) ) +#define BIT_BUSMON0_SOFT_RST ( BIT(1) ) +#define BIT_DMA_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_ARCH_EB */ +#define BIT_AHB_ARCH_EB ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_REMAP */ +#define BIT_PTEST_FUNC_ATSPEED_SEL ( BIT(2) ) +#define BIT_PTEST_FUNC_MODE ( BIT(1) ) +#define BIT_REMAP ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_MISC_CTL */ +#define BITS_MCU_GGE_SHM_CTRL(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)) ) +#define BITS_LZMA_M_PROT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMA_W_PROT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMA_R_PROT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_MCU_SHM_CTRL(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BIT_RF_SWT_AUTO_EN ( BIT(1) ) +#define BIT_WCDMA_ASHB_EN ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL0 */ +#define BITS_ARMMTX_M3TOS0_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ARMMTX_M3TOS0_ADJ_EN ( BIT(27) ) +#define BIT_ARMMTX_M3TOS0_RND_EN ( BIT(26) ) +#define BITS_ARMMTX_M3TOS0_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_ARMMTX_M2TOS0_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M2TOS0_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M2TOS0_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M2TOS0_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M1TOS0_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M1TOS0_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M1TOS0_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M1TOS0_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M0TOS0_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M0TOS0_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M0TOS0_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M0TOS0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL1 */ +#define BITS_ARMMTX_M3TOS1_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ARMMTX_M3TOS1_ADJ_EN ( BIT(27) ) +#define BIT_ARMMTX_M3TOS1_RND_EN ( BIT(26) ) +#define BITS_ARMMTX_M3TOS1_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_ARMMTX_M2TOS1_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M2TOS1_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M2TOS1_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M2TOS1_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M1TOS1_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M1TOS1_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M1TOS1_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M1TOS1_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M0TOS1_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M0TOS1_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M0TOS1_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M0TOS1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL2 */ +#define BITS_ARMMTX_M1TOS2_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ARMMTX_M1TOS2_ADJ_EN ( BIT(27) ) +#define BIT_ARMMTX_M1TOS2_RND_EN ( BIT(26) ) +#define BITS_ARMMTX_M1TOS2_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_ARMMTX_M0TOS2_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M0TOS2_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M0TOS2_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M0TOS2_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M5TOS1_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M5TOS1_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M5TOS1_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M5TOS1_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M4TOS1_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M4TOS1_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M4TOS1_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M4TOS1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL3 */ +#define BITS_ARMMTX_M5TOS2_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ARMMTX_M5TOS2_ADJ_EN ( BIT(27) ) +#define BIT_ARMMTX_M5TOS2_RND_EN ( BIT(26) ) +#define BITS_ARMMTX_M5TOS2_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_ARMMTX_M5TOS4_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M5TOS4_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M5TOS4_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M5TOS4_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M3TOS2_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M3TOS2_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M3TOS2_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M3TOS2_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M2TOS2_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M2TOS2_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M2TOS2_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M2TOS2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL4 */ +#define BITS_ARMMTX_M4TOS3_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M4TOS3_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M4TOS3_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M4TOS3_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M1TOS3_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M1TOS3_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M1TOS3_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M1TOS3_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M0TOS3_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M0TOS3_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M0TOS3_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M0TOS3_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL5 */ +#define BITS_ARMMTX_M4TOS0_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ARMMTX_M4TOS0_ADJ_EN ( BIT(27) ) +#define BIT_ARMMTX_M4TOS0_RND_EN ( BIT(26) ) +#define BITS_ARMMTX_M4TOS0_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_ARMMTX_M4TOS4_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M4TOS4_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M4TOS4_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M4TOS4_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M1TOS4_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M1TOS4_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M1TOS4_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M1TOS4_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M0TOS4_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M0TOS4_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M0TOS4_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M0TOS4_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL6 */ +#define BITS_ARMMTX_M3TOS5_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ARMMTX_M3TOS5_ADJ_EN ( BIT(27) ) +#define BIT_ARMMTX_M3TOS5_RND_EN ( BIT(26) ) +#define BITS_ARMMTX_M3TOS5_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_ARMMTX_M2TOS5_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M2TOS5_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M2TOS5_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M2TOS5_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M1TOS5_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M1TOS5_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M1TOS5_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M1TOS5_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M0TOS5_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M0TOS5_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M0TOS5_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M0TOS5_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_PAUSE */ +#define BIT_MCU_GGE_DEEP_SLEEP_EN ( BIT(5) ) +#define BIT_MCU_LIGHT_SLEEP_EN ( BIT(4) ) +#define BIT_APB_SLEEP ( BIT(3) ) +#define BIT_MCU_DEEP_SLEEP_EN ( BIT(2) ) +#define BIT_MCU_SYS_SLEEP_EN ( BIT(1) ) +#define BIT_MCU_CORE_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_SLP_CTL */ +#define BIT_AHB_VCP1_DEEP_SLEEP_EN ( BIT(6) ) +#define BIT_GGE_ARM_DAHB_SLEEP_EN ( BIT(5) ) +#define BIT_ARM_DAHB_SLEEP_EN ( BIT(4) ) +#define BIT_MCUMTX_AUTO_GATE_EN ( BIT(3) ) +#define BIT_MCU_AUTO_GATE_EN ( BIT(2) ) +#define BIT_AHB_AUTO_GATE_EN ( BIT(1) ) +#define BIT_ARM_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_SLP_STS */ +#define BIT_GGE_DSP_MAHB_SLEEP_EN ( BIT(4) ) +#define BIT_APB_PERI_SLEEP ( BIT(3) ) +#define BIT_DSP_MAHB_SLEEP_EN ( BIT(2) ) +#define BIT_DMA_BUSY ( BIT(1) ) +#define BIT_EMC_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_MCU_CLK_CTL */ +#define BIT_CLK_CP_DBG_GGE_SEL ( BIT(28) ) +#define BIT_CLK_GGE_DBG_SEL ( BIT(27) ) +#define BITS_CLK_COM_GGE_DBG_SEL(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BIT_CLK_SYS_GGE_DBG_SEL ( BIT(24) ) +#define BITS_CLK_LZMA_SEL(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)) ) +#define BIT_CLK_CP_DBG_SEL ( BIT(21) ) +#define BIT_CLK_MCU_DBG_SEL ( BIT(20) ) +#define BITS_CLK_COM_DBG_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_CLK_SYS_DBG_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_CLK_AHB_DIV(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_CLK_MCU_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_APB_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CLK_MCU_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_CP_AHB_RF_DSP_CTL */ +#define BIT_GGE_ASHB_ARMTODSP_EN ( BIT(5) ) +#define BIT_GGE_FRC_CLK_DSP_EN ( BIT(4) ) +#define BIT_GGE_DSP_BOOT_EN ( BIT(3) ) +#define BIT_ASHB_ARMTODSP_EN ( BIT(2) ) +#define BIT_FRC_CLK_DSP_EN ( BIT(1) ) +#define BIT_DSP_BOOT_EN ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_DSP_BOOT_VECTOR */ +#define BITS_DSP_BOOT_VECTOR(_X_) (_X_) + +/* bits definitions for register REG_CP_AHB_RF_DSP_RST */ +#define BIT_GGE_DSP_SYS_SRST ( BIT(3) ) +#define BIT_GGE_DSP_CORE_SRST_N ( BIT(2) ) +#define BIT_DSP_SYS_SRST ( BIT(1) ) +#define BIT_DSP_CORE_SRST_N ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_DSP_JTAG_CTL */ +#define BIT_GGE_CEVA_SW_JTAG_ENA ( BIT(24) ) +#define BIT_GGE_STDO ( BIT(20) ) +#define BIT_GGE_STCK ( BIT(19) ) +#define BIT_GGE_STMS ( BIT(18) ) +#define BIT_GGE_STDI ( BIT(17) ) +#define BIT_GGE_STRTCK ( BIT(16) ) +#define BIT_CEVA_SW_JTAG_ENA ( BIT(8) ) +#define BIT_STDO ( BIT(4) ) +#define BIT_STCK ( BIT(3) ) +#define BIT_STMS ( BIT(2) ) +#define BIT_STDI ( BIT(1) ) +#define BIT_STRTCK ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_MCU_C2C_SEMA */ +#define BITS_GGE_MCU_C2C_SEMA(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_MCU_C2C_SEMA(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_CP_AHB_RF_GGE_DSP_BOOT_VECTOR */ +#define BITS_GGE_DSP_BOOT_VECTOR(_X_) (_X_) + +/* bits definitions for register REG_CP_AHB_RF_CHIP_ID */ +#define BITS_CHIP_ID(_X_) (_X_) + +#endif diff --git a/include/soc/sprd/chip_x35l64/__regs_cp_apb_rf.h b/include/soc/sprd/chip_x35l64/__regs_cp_apb_rf.h new file mode 100644 index 00000000..94249dcb --- /dev/null +++ b/include/soc/sprd/chip_x35l64/__regs_cp_apb_rf.h @@ -0,0 +1,245 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_CP_APB_RF_HEADFILE_H__ +#define __H_REGS_CP_APB_RF_HEADFILE_H__ __FILE__ + +#define REGS_CP_APB_RF + +/* registers definitions for CP_APB_RF */ +#define REG_CP_APB_RF_APB_EB0_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0008) +#define REG_CP_APB_RF_APB_RST0_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0014) +#define REG_CP_APB_RF_APB_MCU_RST SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0018) +#define REG_CP_APB_RF_APB_CLK_SEL0 SCI_ADDR(REGS_CP_APB_RF_BASE, 0x001C) +#define REG_CP_APB_RF_APB_CLK_DIV0 SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0020) +#define REG_CP_APB_RF_APB_ARCH_EB SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0024) +#define REG_CP_APB_RF_APB_MISC_CTL0 SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0028) +#define REG_CP_APB_RF_APB_MISC_CTL1 SCI_ADDR(REGS_CP_APB_RF_BASE, 0x002C) +#define REG_CP_APB_RF_APB_PIN_SEL SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0040) +#define REG_CP_APB_RF_APB_SLP_CTL SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0044) +#define REG_CP_APB_RF_APB_WSYS_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0048) +#define REG_CP_APB_RF_APB_SLP_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0050) +#define REG_CP_APB_RF_APB_ROM_PD_CTL SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0054) +#define REG_CP_APB_RF_APB_BUS_CTL0 SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0058) +#define REG_CP_APB_RF_APB_DSP_INT_CLR SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0074) +#define REG_CP_APB_RF_APB_MISC_INT_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0078) +#define REG_CP_APB_RF_APB_HWRST SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0080) +#define REG_CP_APB_RF_APB_ARM_BOOT_ADDR SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0084) +#define REG_CP_APB_RF_APB_GGE_SLP_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0088) + + + +/* bits definitions for register REG_CP_APB_RF_APB_EB0_STS */ +#define BIT_UART2_EB ( BIT(20) ) +#define BIT_EIC_RTC_EB ( BIT(19) ) +#define BIT_EIC_EB ( BIT(18) ) +#define BIT_RFFE_EB ( BIT(17) ) +#define BIT_EPT_EB ( BIT(16) ) +#define BIT_GPIO_EB ( BIT(15) ) +#define BIT_TMR_RTC_EB ( BIT(14) ) +#define BIT_TMR_EB ( BIT(13) ) +#define BIT_SYSTMR_RTC_EB ( BIT(12) ) +#define BIT_SYSTMR_EB ( BIT(11) ) +#define BIT_IIS3_EB ( BIT(10) ) +#define BIT_IIS2_EB ( BIT(9) ) +#define BIT_IIS1_EB ( BIT(8) ) +#define BIT_IIS0_EB ( BIT(7) ) +#define BIT_SIM2_EB ( BIT(6) ) +#define BIT_SIM1_EB ( BIT(5) ) +#define BIT_SIM0_EB ( BIT(4) ) +#define BIT_UART1_EB ( BIT(3) ) +#define BIT_UART0_EB ( BIT(2) ) +#define BIT_WDG_RTC_EB ( BIT(1) ) +#define BIT_WDG_EB ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_RST0_STS */ +#define BIT_UART2_SOFT_RST ( BIT(20) ) +#define BIT_GGE_MCU_DSP_RST ( BIT(19) ) +#define BIT_EIC_SOFT_RST ( BIT(16) ) +#define BIT_RFFE_SOFT_RST ( BIT(15) ) +#define BIT_MCU_DSP_RST ( BIT(14) ) +#define BIT_EPT_SOFT_RST ( BIT(13) ) +#define BIT_GPIO_SOFT_RST ( BIT(12) ) +#define BIT_TMR_SOFT_RST ( BIT(11) ) +#define BIT_SYSTMR_SOFT_RST ( BIT(10) ) +#define BIT_IIS3_SOFT_RST ( BIT(9) ) +#define BIT_IIS2_SOFT_RST ( BIT(8) ) +#define BIT_IIS1_SOFT_RST ( BIT(7) ) +#define BIT_IIS0_SOFT_RST ( BIT(6) ) +#define BIT_SIM2_SOFT_RST ( BIT(5) ) +#define BIT_SIM1_SOFT_RST ( BIT(4) ) +#define BIT_SIM0_SOFT_RST ( BIT(3) ) +#define BIT_UART1_SOFT_RST ( BIT(2) ) +#define BIT_UART0_SOFT_RST ( BIT(1) ) +#define BIT_WDG_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_MCU_RST */ +#define BIT_MCU_SOFT_RST_SET ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_CLK_SEL0 */ +#define BIT_CLK_IIS3_PAD_SEL ( BIT(19) ) +#define BIT_CLK_IIS2_PAD_SEL ( BIT(18) ) +#define BIT_CLK_IIS1_PAD_SEL ( BIT(17) ) +#define BIT_CLK_IIS0_PAD_SEL ( BIT(16) ) +#define BITS_CLK_UART2_SEL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_CLK_IIS3_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_CLK_IIS2_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_CLK_IIS1_SEL(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_CLK_IIS0_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CLK_UART1_SEL(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_CLK_UART0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CP_APB_RF_APB_CLK_DIV0 */ +#define BITS_CLK_IIS2_DIV(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_CLK_IIS1_DIV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)) ) +#define BITS_CLK_IIS0_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_CLK_UART1_DIV(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BITS_CLK_UART0_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_CP_APB_RF_APB_ARCH_EB */ +#define BITS_CLK_UART2_DIV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)) ) +#define BITS_CLK_IIS3_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_RTC_ARCH_EB ( BIT(1) ) +#define BIT_APB_ARCH_EB ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_MISC_CTL0 */ +#define BIT_GGE_ALL_CLK_EN ( BIT(29) ) +#define BIT_ALL_CLK_EN ( BIT(28) ) +#define BIT_DMA_LSLP_EN ( BIT(27) ) +#define BIT_WAKEUP_XTL_EN_3G_W ( BIT(26) ) +#define BIT_WAKEUP_XTL_EN_2G ( BIT(25) ) +#define BIT_ARM_JTAG_EN ( BIT(24) ) +#define BIT_WAKEUP_XTL_EN_3G_TD ( BIT(23) ) +#define BIT_GGE_WAKEUP_XTL_EN_2G ( BIT(22) ) +#define BITS_ARM_FRC_STOP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) ) + +/* bits definitions for register REG_CP_APB_RF_APB_MISC_CTL1 */ +#define BITS_BUFON_CTRL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_SIM2_CLK_POLARITY ( BIT(3) ) +#define BIT_SIM1_CLK_POLARITY ( BIT(2) ) +#define BIT_SIM0_CLK_POLARITY ( BIT(1) ) +#define BIT_ROM_CLK_EN ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_PIN_SEL */ +#define BIT_DJTAG_PIN_IN_SEL ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_SLP_CTL */ +#define BITS_GGE_DEEP_SLP_DBG(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_APB_PERI_FRC_ON ( BIT(20) ) +#define BIT_APB_PERI_FRC_SLP ( BIT(16) ) +#define BIT_MCU_XTLEN_AUTOPD_EN ( BIT(12) ) +#define BIT_MCU_FORCE_GGE_LIGHT_SLEEP ( BIT(9) ) +#define BIT_MCU_FORCE_LIGHT_SLEEP ( BIT(8) ) +#define BIT_CHIP_SLP_ARM_CLR ( BIT(4) ) +#define BIT_MCU_FORCE_GGE_DEEP_SLEEP ( BIT(3) ) +#define BIT_MCU_FORCE_WSYS_LT_STOP ( BIT(2) ) +#define BIT_MCU_FORCE_WSYS_STOP ( BIT(1) ) +#define BIT_MCU_FORCE_DEEP_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_WSYS_STS */ +#define BITS_DEEP_SLP_DBG(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_WSYS_STATUS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_CP_APB_RF_APB_SLP_STS */ +#define BIT_DSP_MAHB_SLEEP_EN ( BIT(28) ) +#define BIT_MCU_PERI_STOP ( BIT(27) ) +#define BIT_DSP_PERI_STOP ( BIT(26) ) +#define BIT_ECC_CKG_EN ( BIT(25) ) +#define BIT_QBC_CKG_EN ( BIT(24) ) +#define BIT_DSP_TWPLL_EN ( BIT(21) ) +#define BIT_STC_TMR_AUTOPD_XTL_EN ( BIT(20) ) +#define BIT_RFT_TMR_AUTOPD_XTL_EN ( BIT(19) ) +#define BIT_STC_TMR_AUTOPD_RF_EN ( BIT(18) ) +#define BIT_RFT_TMR_AUTOPD_RF_EN ( BIT(17) ) +#define BIT_CHIP_SLEEP_REC_ARM ( BIT(16) ) +#define BIT_DSP_CORE_STOP ( BIT(15) ) +#define BIT_DSP_MTX_STOP ( BIT(14) ) +#define BIT_DSP_AHB_STOP ( BIT(13) ) +#define BIT_DSP_SYS_STOP ( BIT(12) ) +#define BIT_DSP_DEEP_STOP ( BIT(11) ) +#define BIT_ASHB_DSPTOARM_EN ( BIT(10) ) +#define BIT_ASHB_ARMTODSP_VALID ( BIT(9) ) +#define BIT_EMC_STOP_CH3 ( BIT(8) ) +#define BIT_EMC_STOP_CH4 ( BIT(7) ) +#define BIT_EMC_STOP_CH5 ( BIT(6) ) +#define BIT_FRC_WAKE_EN ( BIT(5) ) +#define BIT_TMR_WAKE_AFC ( BIT(4) ) +#define BIT_SCH_SLEEP ( BIT(3) ) +#define BIT_DSP_STOP ( BIT(2) ) +#define BIT_MCU_STOP ( BIT(1) ) +#define BIT_EMC_STOP ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_ROM_PD_CTL */ +#define BIT_GGE_ROM_FORCE_ON ( BIT(1) ) +#define BIT_ROM_FORCE_ON ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_BUS_CTL0 */ +#define BIT_IIS3_DSP_CTRL_SEL ( BIT(11) ) +#define BIT_IIS2_DSP_CTRL_SEL ( BIT(10) ) +#define BIT_IIS1_DSP_CTRL_SEL ( BIT(9) ) +#define BIT_IIS0_DSP_CTRL_SEL ( BIT(8) ) +#define BIT_UART2_CTRL_SEL ( BIT(7) ) +#define BIT_RFFE_CTRL_SEL ( BIT(5) ) +#define BIT_IIS3_CTRL_SEL ( BIT(4) ) +#define BIT_IIS2_CTRL_SEL ( BIT(3) ) +#define BIT_IIS1_CTRL_SEL ( BIT(2) ) +#define BIT_IIS0_CTRL_SEL ( BIT(1) ) +#define BIT_UART1_CTRL_SEL ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_DSP_INT_CLR */ +#define BIT_RFT_INT_CLR ( BIT(2) ) + +/* bits definitions for register REG_CP_APB_RF_APB_MISC_INT_STS */ +#define BIT_RFT_INT ( BIT(2) ) + +/* bits definitions for register REG_CP_APB_RF_APB_HWRST */ +#define BITS_HWRST_REG(_X_) (_X_) + +/* bits definitions for register REG_CP_APB_RF_APB_ARM_BOOT_ADDR */ +#define BITS_ARMBOOT_ADDR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_CP_APB_RF_APB_GGE_SLP_STS */ +#define BIT_GGE_DSP_MAHB_SLEEP_EN ( BIT(21) ) +#define BIT_GGE_DSP_PERI_STOP ( BIT(20) ) +#define BIT_GGE_QBC_CKG_EN ( BIT(19) ) +#define BIT_GGE_DSP_TWPLL_EN ( BIT(18) ) +#define BIT_GGE_STC_TMR_AUTOPD_XTL_EN ( BIT(17) ) +#define BIT_GGE_STC_TMR_AUTOPD_RF_EN ( BIT(16) ) +#define BIT_GGE_DSP_CORE_STOP ( BIT(15) ) +#define BIT_GGE_DSP_MTX_STOP ( BIT(14) ) +#define BIT_GGE_DSP_AHB_STOP ( BIT(13) ) +#define BIT_GGE_DSP_SYS_STOP ( BIT(12) ) +#define BIT_GGE_DSP_DEEP_STOP ( BIT(11) ) +#define BIT_GGE_ASHB_DSPTOARM_EN ( BIT(10) ) +#define BIT_GGE_ASHB_ARMTODSP_VALID ( BIT(9) ) +#define BIT_GGE_EMC_STOP_CH3 ( BIT(8) ) +#define BIT_GGE_EMC_STOP_CH4 ( BIT(7) ) +#define BIT_GGE_EMC_STOP_CH5 ( BIT(6) ) +#define BIT_GGE_FRC_WAKE_EN ( BIT(5) ) +#define BIT_GGE_TMR_WAKE_AFC ( BIT(4) ) +#define BIT_GGE_SCH_SLEEP ( BIT(3) ) +#define BIT_GGE_DSP_STOP ( BIT(2) ) +#define BIT_GGE_MCU_STOP ( BIT(1) ) +#define BIT_GGE_EMC_STOP ( BIT(0) ) + +#endif diff --git a/include/soc/sprd/chip_x35l64/__regs_djtag_apb_rf.h b/include/soc/sprd/chip_x35l64/__regs_djtag_apb_rf.h new file mode 100755 index 00000000..7aa4d044 --- /dev/null +++ b/include/soc/sprd/chip_x35l64/__regs_djtag_apb_rf.h @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_DJTAG_APB_RF_HEADFILE_H__ +#define __H_REGS_DJTAG_APB_RF_HEADFILE_H__ __FILE__ + +#define REGS_DJTAG_APB_RF + +/* registers definitions for DJTAG_APB_RF */ +#define REG_DJTAG_APB_RF_DJTAG_IR_LEN_CFG SCI_ADDR(REGS_DJTAG_APB_RF_BASE, 0x0000) +#define REG_DJTAG_APB_RF_DJTAG_DR_LEN_CFG SCI_ADDR(REGS_DJTAG_APB_RF_BASE, 0x0004) +#define REG_DJTAG_APB_RF_DJTAG_IR_CFG SCI_ADDR(REGS_DJTAG_APB_RF_BASE, 0x0008) +#define REG_DJTAG_APB_RF_DJTAG_DR_CFG SCI_ADDR(REGS_DJTAG_APB_RF_BASE, 0x000C) +#define REG_DJTAG_APB_RF_DR_PAUSE_RECOV_CFG SCI_ADDR(REGS_DJTAG_APB_RF_BASE, 0x0010) +#define REG_DJTAG_APB_RF_DJTAG_RND_EN_CFG SCI_ADDR(REGS_DJTAG_APB_RF_BASE, 0x0014) +#define REG_DJTAG_APB_RF_DJTAG_UPD_DR_CFG SCI_ADDR(REGS_DJTAG_APB_RF_BASE, 0x0018) + + + +/* bits definitions for register REG_DJTAG_APB_RF_DJTAG_IR_LEN_CFG */ +#define BITS_IR_LEN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_DJTAG_APB_RF_DJTAG_DR_LEN_CFG */ +#define BITS_DR_LEN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_DJTAG_APB_RF_DJTAG_IR_CFG */ +#define BITS_DJTAG_IR(_X_) (_X_) + +/* bits definitions for register REG_DJTAG_APB_RF_DJTAG_DR_CFG */ +#define BITS_DJTAG_DR(_X_) (_X_) + +/* bits definitions for register REG_DJTAG_APB_RF_DR_PAUSE_RECOV_CFG */ +#define BIT_DR_PAUSE_RECOV ( BIT(0) ) + +/* bits definitions for register REG_DJTAG_APB_RF_DJTAG_RND_EN_CFG */ +#define BIT_DJTAG_RND_EN ( BIT(0) ) + +/* bits definitions for register REG_DJTAG_APB_RF_DJTAG_UPD_DR_CFG */ +#define BITS_DJTAG_UPD_DR(_X_) (_X_) + +#endif diff --git a/include/soc/sprd/chip_x35l64/__regs_gpu_apb_rf.h b/include/soc/sprd/chip_x35l64/__regs_gpu_apb_rf.h new file mode 100755 index 00000000..46b49cfa --- /dev/null +++ b/include/soc/sprd/chip_x35l64/__regs_gpu_apb_rf.h @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + + + +#ifndef __H_REGS_GPU_APB_RF_HEADFILE_H__ +#define __H_REGS_GPU_APB_RF_HEADFILE_H__ __FILE__ + +#define REGS_GPU_APB_RF + +/* registers definitions for GPU_APB_RF */ +#define REG_GPU_APB_APB_RST SCI_ADDR(REGS_GPU_APB_BASE, 0x0000) +#define REG_GPU_APB_APB_CLK_CTRL SCI_ADDR(REGS_GPU_APB_BASE, 0x0004) + + + +/* bits definitions for register REG_GPU_APB_RF_APB_RST */ +#define BIT_GPU_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_GPU_APB_APB_CLK_CTRL */ +#define BITS_CLK_GPU_DIV(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CLK_GPU_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +#endif diff --git a/include/soc/sprd/chip_x35l64/__regs_lte_cevax_pmu.h b/include/soc/sprd/chip_x35l64/__regs_lte_cevax_pmu.h new file mode 100755 index 00000000..dd8f631a --- /dev/null +++ b/include/soc/sprd/chip_x35l64/__regs_lte_cevax_pmu.h @@ -0,0 +1,376 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_LTE_CEVAX_PMU_HEADFILE_H__ +#define __H_REGS_LTE_CEVAX_PMU_HEADFILE_H__ __FILE__ + +#define REGS_LTE_CEVAX_PMU + +/* registers definitions for LTE_CEVAX_PMU */ +#define REG_LTE_CEVAX_PMU_PLL_CFG0 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0000) +#define REG_LTE_CEVAX_PMU_PLL_CFG1 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0004) +#define REG_LTE_CEVAX_PMU_CXCLK_DIV SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0008) +#define REG_LTE_CEVAX_PMU_XHCLK_DIV SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x000C) +#define REG_LTE_CEVAX_PMU_XPCLK_DIV SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0010) +#define REG_LTE_CEVAX_PMU_CXPMOD SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0014) +#define REG_LTE_CEVAX_PMU_XHPMOD SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0018) +#define REG_LTE_CEVAX_PMU_XAPBMOD SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x001C) +#define REG_LTE_CEVAX_PMU_VERSION_CR SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0020) +#define REG_LTE_CEVAX_PMU_SLEEP_STATUS SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0024) +#define REG_LTE_CEVAX_PMU_POW_CTL0 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0028) +#define REG_LTE_CEVAX_PMU_POW_CTL1 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x002C) +#define REG_LTE_CEVAX_PMU_POW_CTL2 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0030) +#define REG_LTE_CEVAX_PMU_ACCCLK_EN0 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0034) +#define REG_LTE_CEVAX_PMU_ACCCLK_EN1 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0038) +#define REG_LTE_CEVAX_PMU_ACCCLK_EN2 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x003C) +#define REG_LTE_CEVAX_PMU_SOFT_RST0 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0040) +#define REG_LTE_CEVAX_PMU_SOFT_RST1 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0044) +#define REG_LTE_CEVAX_PMU_DSP_CKG_SEL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0048) +#define REG_LTE_CEVAX_PMU_CLK_DLCH_SEL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0050) +#define REG_LTE_CEVAX_PMU_CLK_ULCH_SEL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0054) +#define REG_LTE_CEVAX_PMU_CLK_RATEM_SEL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0058) +#define REG_LTE_CEVAX_PMU_CLK_LTE_SPI_DIV_SEL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x005C) +#define REG_LTE_CEVAX_PMU_CX_CKG_DIV SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0078) +#define REG_LTE_CEVAX_PMU_XH_CKG_DIV SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x007C) +#define REG_LTE_CEVAX_PMU_XP_CKG_DIV SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0080) +#define REG_LTE_CEVAX_PMU_LTE_PMU_CKG_EN SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0084) +#define REG_LTE_CEVAX_PMU_LTE_PMU_CLK_EN SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0088) +#define REG_LTE_CEVAX_PMU_APB_CLK_SEL0 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x008C) +#define REG_LTE_CEVAX_PMU_APB_CLK_SEL1 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0090) +#define REG_LTE_CEVAX_PMU_CLK_CXTMR0_SEL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0094) +#define REG_LTE_CEVAX_PMU_CLK_CXTMR1_SEL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0098) +#define REG_LTE_CEVAX_PMU_CLK_CXTMR2_SEL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x009C) +#define REG_LTE_CEVAX_PMU_APB_CLK_SEL2 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x00A0) +#define REG_LTE_CEVAX_PMU_MEM_LP_CTRL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0xA4) +#define REG_LTE_CEVAX_PMU_XC321_BOOT SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0120) +#define REG_LTE_CEVAX_PMU_XC321_CORE_RST SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0124) +#define REG_LTE_CEVAX_PMU_XC321_BVECTOR SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0128) +#define REG_LTE_CEVAX_PMU_RES_REG0 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0140) +#define REG_LTE_CEVAX_PMU_RES_REG1 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0144) +#define REG_LTE_CEVAX_PMU_RES_REG2 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0148) + + + +/* bits definitions for register REG_LTE_CEVAX_PMU_PLL_CFG0 */ +#define BITS_PLL_CFG0_R(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_IIS3_EB ( BIT(10) ) +#define BIT_IIS2_EB ( BIT(9) ) +#define BIT_DSP_DLCH_EN ( BIT(8) ) +#define BIT_DSP_ULCH_EN ( BIT(7) ) +#define BIT_DLCH_AUTO_EN ( BIT(6) ) +#define BIT_ULCH_AUTO_EN ( BIT(5) ) +#define BIT_IIS1_EB ( BIT(4) ) +#define BIT_IIS0_EB ( BIT(3) ) +#define BIT_UART1_EB ( BIT(2) ) +#define BIT_UART0_EB ( BIT(1) ) +#define BIT_RFFE_EB ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_PLL_CFG1 */ +#define BIT_CHIP_SLP_REC_DSP ( BIT(16) ) +#define BIT_LTE_POW_OFF ( BIT(10) ) +#define BIT_LTE_POW_READY ( BIT(9) ) +#define BITS_LTE_POW_WAIT(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) ) +#define BIT_CHIP_SLP_DSP_CLR ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CXCLK_DIV */ +#define BITS_CXREG_AUTO_OFF(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_XHCLK_DIV */ +#define BIT_BUSMON2_CHN_SEL ( BIT(25) ) +#define BIT_BUSMON1_CHN_SEL ( BIT(24) ) +#define BIT_BUSMON0_CHN_SEL ( BIT(23) ) +#define BITS_DSP_SHM_CTRL(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BIT_DSPAPB_DES_AUTO_EN ( BIT(20) ) +#define BIT_DSPAHB_DES_AUTO_EN ( BIT(19) ) +#define BITS_LBUSMON2_CHN_SEL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_LBUSMON1_CHN_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_LBUSMON0_CHN_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_DSPAPB_DIV_DES(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DSPAHB_DIV_DES(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)) ) +#define BITS_CX_DSPPLL_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_XPCLK_DIV */ +#define BIT_PMU_DMA_FRC_EB ( BIT(24) ) +#define BIT_ZBUS_32ACCESS ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CXPMOD */ +#define BIT_MCU_FORCE_DEEP_SLEEP ( BIT(31) ) +#define BIT_LDSP_DEEP_SLP_CTRL ( BIT(30) ) +#define BIT_EMC_LIGHT_SLEEP_EN_M6 ( BIT(29) ) +#define BIT_EMC_DEEP_SLEEP_EN_M6 ( BIT(28) ) +#define BIT_EMC_LIGHT_SLEEP_EN_M7 ( BIT(27) ) +#define BIT_EMC_DEEP_SLEEP_EN_M7 ( BIT(26) ) +#define BIT_EMC_LIGHT_SLEEP_EN_M8 ( BIT(25) ) +#define BIT_EMC_DEEP_SLEEP_EN_M8 ( BIT(24) ) +#define BIT_LDSP2PUB_ACCESS_EN ( BIT(8) ) +#define BIT_LDSP_WAKEUP_XTL_EN ( BIT(7) ) +#define BIT_DMA_LSLP_EN ( BIT(4) ) +#define BIT_DSP_LIGHT_SLEEP_EN ( BIT(3) ) +#define BIT_DSP_DEEP_SLEEP_EN ( BIT(2) ) +#define BIT_DSP_SYS_SLEEP_EN ( BIT(1) ) +#define BIT_DSP_CORE_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_XHPMOD */ +#define BIT_BUSMON2_EB ( BIT(31) ) +#define BIT_BUSMON1_EB ( BIT(30) ) +#define BIT_BUSMON0_EB ( BIT(29) ) +#define BIT_LACCX_AUTO_GATE_EN ( BIT(14) ) +#define BIT_LDSPX_AUTO_GATE_EN ( BIT(13) ) +#define BIT_CXDMA_CLK_AUTO_EN ( BIT(12) ) +#define BIT_CXAPB_AUTO_GATE_EN ( BIT(11) ) +#define BIT_CXAHB_AUTO_GATE_EN ( BIT(10) ) +#define BIT_CXDSP_AUTO_GATE_EN ( BIT(9) ) +#define BIT_CXCORE_AUTO_GATE_EN ( BIT(8) ) +#define BIT_CXMTX_AUTO_GATE_EN ( BIT(7) ) +#define BIT_DSP_MAHB_SLEEP_EN ( BIT(6) ) +#define BIT_ACCZ_ARCH_EB ( BIT(5) ) +#define BIT_CXBUS_ARCH_EB ( BIT(4) ) +#define BIT_LTEPROC_ARCH_EB ( BIT(3) ) +#define BIT_PMU_DLCH_SLEEP_R ( BIT(1) ) +#define BIT_PMU_ULCH_SLEEP_R ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_XAPBMOD */ +#define BITS_HPROTDMAW(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_HPROTDMAR(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_PMU_XPSLEEP_P_R(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_VERSION_CR */ +#define BITS_VERSION_CR(_X_) (_X_) + +/* bits definitions for register REG_LTE_CEVAX_PMU_SLEEP_STATUS */ +#define BITS_PMU_SLEEP_STATUS(_X_) (_X_) + +/* bits definitions for register REG_LTE_CEVAX_PMU_POW_CTL0 */ +#define BITS_LTE_ISO_ON_NUM(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LTE_ISO_OFF_NUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_POW_CTL1 */ +#define BIT_CLK_PWR_LTE_SEL ( BIT(10) ) +#define BIT_LTE_SLP_POWOFF_AUTO_EN ( BIT(9) ) +#define BIT_LTE_POW_FORCE_PD ( BIT(8) ) +#define BITS_DSP_MEM_PD_REG(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_POW_CTL2 */ +#define BITS_DSP_MEM_PD_EN(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)) ) +#define BITS_PD_LTE_STATUS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_ACCCLK_EN0 */ +#define BIT_FFT_OFFLN_HCLKEN ( BIT(30) ) +#define BIT_FFT_OFFLN_CLKEN ( BIT(29) ) +#define BIT_FFT_ONLN_HCLKEN ( BIT(28) ) +#define BIT_FFT_ONLN_CLKEN ( BIT(27) ) +#define BIT_LTE_DRM_CLKEN ( BIT(24) ) +#define BIT_MIMO_HCLKEN ( BIT(23) ) +#define BIT_MIMO_CLKEN ( BIT(22) ) +#define BIT_PBCH_ACLKEN ( BIT(21) ) +#define BIT_PBCH_HCLKEN ( BIT(20) ) +#define BIT_PBCH_CLKEN ( BIT(19) ) +#define BIT_PCFICH_PHICH_HCLKEN ( BIT(18) ) +#define BIT_PCFICH_PHICH_CLKEN ( BIT(17) ) +#define BIT_PDCCH_ACLKEN ( BIT(16) ) +#define BIT_PDCCH_HCLKEN ( BIT(15) ) +#define BIT_PDCCH_CLKEN ( BIT(14) ) +#define BIT_PDSCH_TB_CTL_HCLKEN ( BIT(13) ) +#define BIT_PDSCH_TB_CTL_CLKEN ( BIT(12) ) +#define BIT_RXDFE_HCLKEN ( BIT(11) ) +#define BIT_SYNC_ACLKEN ( BIT(10) ) +#define BIT_SYNC_HCLKEN ( BIT(9) ) +#define BIT_SYNC_CLKEN ( BIT(8) ) +#define BIT_TBUF_ACLKEN ( BIT(7) ) +#define BIT_TBUF_HCLKEN ( BIT(6) ) +#define BIT_TBUF_CLKEN ( BIT(5) ) +#define BIT_VTB_CLKEN ( BIT(4) ) +#define BIT_LTE_PROC_HCLKEN ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_ACCCLK_EN1 */ +#define BIT_LBUSMON2_EB ( BIT(28) ) +#define BIT_LBUSMON1_EB ( BIT(27) ) +#define BIT_LBUSMON0_EB ( BIT(26) ) +#define BIT_HSDL_CLKEN ( BIT(25) ) +#define BIT_ULMAC_HCLKEN ( BIT(24) ) +#define BIT_TBE_HCLKEN ( BIT(23) ) +#define BIT_TBE_CLKEN ( BIT(22) ) +#define BIT_RM_HCLKEN ( BIT(21) ) +#define BIT_RM_CLKEN ( BIT(20) ) +#define BIT_PCM_HCLKEN ( BIT(19) ) +#define BIT_PCM_CLKEN ( BIT(18) ) +#define BIT_UCM_HCLKEN ( BIT(17) ) +#define BIT_UCM_CLKEN ( BIT(16) ) +#define BIT_CHE_ACLKEN ( BIT(15) ) +#define BIT_CHE_HCLKEN ( BIT(14) ) +#define BIT_CHE_SYS_CLKEN ( BIT(13) ) +#define BIT_CHEPP_ACLKEN ( BIT(12) ) +#define BIT_CHEPP_HCLKEN ( BIT(11) ) +#define BIT_CHEPP_SYS_CLKEN ( BIT(10) ) +#define BIT_DBUF_ACLKEN ( BIT(9) ) +#define BIT_DBUF_HCLKEN ( BIT(8) ) +#define BIT_DBUF_CLKEN ( BIT(7) ) +#define BIT_DFE_CLKEN ( BIT(6) ) +#define BIT_FBUF_ACLKEN ( BIT(5) ) +#define BIT_FBUF_HCLKEN ( BIT(4) ) +#define BIT_FBUF_CLKEN ( BIT(3) ) +#define BIT_FEC_ACLKEN ( BIT(2) ) +#define BIT_FEC_HCLKEN ( BIT(1) ) +#define BIT_FEC_CLKEN ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_ACCCLK_EN2 */ + +/* bits definitions for register REG_LTE_CEVAX_PMU_SOFT_RST0 */ +#define BITS_SOFT_RST_R(_X_) (_X_) + +/* bits definitions for register REG_LTE_CEVAX_PMU_SOFT_RST1 */ +#define BIT_LTE_PROC_SOFT_RST_RFT ( BIT(31) ) +#define BIT_HSDL_SOFT_RST ( BIT(30) ) +#define BIT_RFSPI_SOFT_RST ( BIT(29) ) +#define BIT_LTE_PROC_SOFT_RST ( BIT(28) ) +#define BIT_ULMAC_SOFT_RST ( BIT(27) ) +#define BIT_PCM_SOFT_RST ( BIT(26) ) +#define BIT_UCM_SOFT_RST ( BIT(25) ) +#define BIT_TBE_SOFT_RST ( BIT(24) ) +#define BIT_RM_SOFT_RST ( BIT(23) ) +#define BIT_RFT_SOFT_RST ( BIT(22) ) +#define BIT_DFE_SOFT_RST ( BIT(21) ) +#define BIT_MIMO_SOFT_RST ( BIT(20) ) +#define BIT_ON_LINE_FFT_SOFT_RST ( BIT(19) ) +#define BIT_OFF_LINE_FFT_SOFT_RST ( BIT(18) ) +#define BIT_PCFICH_SOFT_RST ( BIT(17) ) +#define BIT_PDSCH_SOFT_RST ( BIT(16) ) +#define BIT_DRM_SOFT_RST ( BIT(15) ) +#define BIT_VTB_SOFT_RST ( BIT(14) ) +#define BIT_FEC_SOFT_RST ( BIT(13) ) +#define BIT_CHE_SOFT_RST ( BIT(12) ) +#define BIT_CHEPP_SOFT_RST ( BIT(11) ) +#define BIT_SYNC_SOFT_RST ( BIT(10) ) +#define BIT_TBUF_SOFT_RST ( BIT(9) ) +#define BIT_DBUF_SOFT_RST ( BIT(8) ) +#define BIT_FBUF_SOFT_RST ( BIT(7) ) +#define BIT_PDCCH_SOFT_RST ( BIT(6) ) +#define BIT_PBCH_SOFT_RST ( BIT(5) ) +#define BIT_RXADC_SOFT_RST ( BIT(4) ) +#define BIT_TXDAC_SOFT_RST ( BIT(3) ) +#define BIT_CAL_SOFT_RST ( BIT(2) ) +#define BIT_RTC_SOFT_RST ( BIT(1) ) +#define BIT_LTE_SPI_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_DSP_CKG_SEL */ +#define BITS_DSP_CKG_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CLK_DLCH_SEL */ +#define BITS_CLK_DLCH_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CLK_ULCH_SEL */ +#define BITS_CLK_ULCH_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CLK_RATEM_SEL */ +#define BITS_CLK_RATEM_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CLK_LTE_SPI_DIV_SEL */ +#define BITS_CLK_LTE_SPI_DIV(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)) ) +#define BITS_CLK_LTE_SPI_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CX_CKG_DIV */ +#define BITS_CX_CKG_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_XH_CKG_DIV */ +#define BITS_XH_CKG_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_XP_CKG_DIV */ +#define BITS_XP_CKG_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_LTE_PMU_CKG_EN */ +#define BIT_DSP_CKG_EN ( BIT(8) ) +#define BIT_CX_CKG_EN ( BIT(6) ) +#define BIT_XH_CKG_EN ( BIT(5) ) +#define BIT_XP_CKG_EN ( BIT(4) ) +#define BIT_DMA_CKG_EN ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_LTE_PMU_CLK_EN */ +#define BIT_CLK_LTE_SA_EN ( BIT(17) ) +#define BIT_CLK_CXTMR2_EN ( BIT(16) ) +#define BIT_CLK_CXTMR1_EN ( BIT(15) ) +#define BIT_CLK_CXTMR0_EN ( BIT(14) ) +#define BIT_CLK_AXI_EN ( BIT(13) ) +#define BIT_CLK_AHB_EN ( BIT(12) ) +#define BIT_CLK_DFE_EN ( BIT(11) ) +#define BIT_CLK_RFT_EN ( BIT(10) ) +#define BIT_CLK_DLCH_EN ( BIT(9) ) +#define BIT_CLK_ULCH_EN ( BIT(8) ) +#define BIT_CLK_RATEM_EN ( BIT(7) ) +#define BIT_CLK_RXADC_EN ( BIT(6) ) +#define BIT_CLK_TXDAC_EN ( BIT(5) ) +#define BIT_CLK_LTE_ANA_2X_EN ( BIT(4) ) +#define BIT_CLK_LTE_ANA_1X_EN ( BIT(3) ) +#define BIT_CLK_CAL_EN ( BIT(2) ) +#define BIT_CLK_RTC_EN ( BIT(1) ) +#define BIT_CLK_LTE_SPI_EN ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_APB_CLK_SEL0 */ +#define BITS_CLK_UART1_DIV(_X_) ( (_X_) << 7 & (BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_CLK_UART1_SEL(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)) ) +#define BITS_CLK_UART0_DIV(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)) ) +#define BITS_CLK_UART0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_APB_CLK_SEL1 */ +#define BITS_CLK_IIS1_DIV(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_CLK_IIS1_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_CLK_IIS0_DIV(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_CLK_IIS0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CLK_CXTMR0_SEL */ +#define BITS_CLK_CXTMR0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CLK_CXTMR1_SEL */ +#define BITS_CLK_CXTMR1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CLK_CXTMR2_SEL */ +#define BITS_CLK_CXTMR2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_APB_CLK_SEL2 */ +#define BITS_CLK_IIS3_DIV(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_CLK_IIS3_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_CLK_IIS2_DIV(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_CLK_IIS2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_MEM_LP_CTRL */ +#define BITS_MEM_LP_CTRL(_X_) (_X_) +/* bits definitions for register REG_LTE_CEVAX_PMU_XC321_BOOT */ +#define BIT_FRC_CLK_XC321_EN ( BIT(1) ) +#define BIT_XC321_BOOT ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_XC321_CORE_RST */ +#define BIT_XC321_SYS_SRST ( BIT(1) ) +#define BIT_XC321_CORE_SRST_N ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_XC321_BVECTOR */ +#define BITS_XC321_BOOT_VECTOR(_X_) (_X_) + +/* bits definitions for register REG_LTE_CEVAX_PMU_RES_REG0 */ +#define BITS_RES_REG0(_X_) (_X_) + +/* bits definitions for register REG_LTE_CEVAX_PMU_RES_REG1 */ +#define BITS_RES_REG1(_X_) (_X_) + +/* bits definitions for register REG_LTE_CEVAX_PMU_RES_REG2 */ +#define BITS_RES_REG2(_X_) (_X_) + +#endif diff --git a/include/soc/sprd/chip_x35l64/__regs_mdar_apb_rf.h b/include/soc/sprd/chip_x35l64/__regs_mdar_apb_rf.h new file mode 100755 index 00000000..5416a02f --- /dev/null +++ b/include/soc/sprd/chip_x35l64/__regs_mdar_apb_rf.h @@ -0,0 +1,1181 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_MDAR_APB_RF_HEADFILE_H__ +#define __H_REGS_MDAR_APB_RF_HEADFILE_H__ __FILE__ + +#define REGS_MDAR_APB_RF + +/* registers definitions for MDAR_APB_RF */ +#define REG_MDAR_APB_RF_MDAR_CFG0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0000) +#define REG_MDAR_APB_RF_MDAR_CFG1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0004) +#define REG_MDAR_APB_RF_MDAR_CFG3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x000C) +#define REG_MDAR_APB_RF_MDAR_DAC1_CTR1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0010) +#define REG_MDAR_APB_RF_MDAR_DAC1_CTR2 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0014) +#define REG_MDAR_APB_RF_MDAR_DAC1_CTR3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0018) +#define REG_MDAR_APB_RF_MDAR_DAC1_CTR4 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x001C) +#define REG_MDAR_APB_RF_MDAR_DAC1_STS0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0020) +#define REG_MDAR_APB_RF_MDAR_DAC1_STS1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0024) +#define REG_MDAR_APB_RF_MDAR_CAL1_CTR0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0028) +#define REG_MDAR_APB_RF_MDAR_CAL1_CTR1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x002C) +#define REG_MDAR_APB_RF_MDAR_CAL1_CTR3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0030) +#define REG_MDAR_APB_RF_MDAR_CAL1_STS0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0034) +#define REG_MDAR_APB_RF_MDAR_CAL1_STS1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0038) +#define REG_MDAR_APB_RF_MDAR_DAC1_CTR00 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x003C) +#define REG_MDAR_APB_RF_MDAR_DAC1_CTR10 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0040) +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0044) +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR00 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0048) +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR01 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x004C) +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR02 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0050) +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR10 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0054) +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR11 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0058) +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR12 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x005C) +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR20 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0060) +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR21 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0064) +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR22 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0068) +#define REG_MDAR_APB_RF_MDAR_DAC2_CTR1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0070) +#define REG_MDAR_APB_RF_MDAR_DAC2_CTR2 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0074) +#define REG_MDAR_APB_RF_MDAR_DAC2_CTR3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0078) +#define REG_MDAR_APB_RF_MDAR_DAC2_CTR4 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x007C) +#define REG_MDAR_APB_RF_MDAR_DAC2_STS0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0080) +#define REG_MDAR_APB_RF_MDAR_DAC2_STS1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0084) +#define REG_MDAR_APB_RF_MDAR_CAL2_CTR0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0088) +#define REG_MDAR_APB_RF_MDAR_CAL2_CTR1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x008C) +#define REG_MDAR_APB_RF_MDAR_CAL2_CTR3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0090) +#define REG_MDAR_APB_RF_MDAR_CAL2_STS0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0094) +#define REG_MDAR_APB_RF_MDAR_CAL2_STS1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0098) +#define REG_MDAR_APB_RF_MDAR_DAC2_CTR00 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x009C) +#define REG_MDAR_APB_RF_MDAR_DAC2_CTR10 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00A0) +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00A4) +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR00 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00A8) +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR01 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00AC) +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR02 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00B0) +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR10 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00B4) +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR11 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00B8) +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR12 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00BC) +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR20 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00C0) +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR21 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00C4) +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR22 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00C8) +#define REG_MDAR_APB_RF_MDAR_DAC3_CTR1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00D0) +#define REG_MDAR_APB_RF_MDAR_DAC3_CTR2 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00D4) +#define REG_MDAR_APB_RF_MDAR_DAC3_CTR3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00D8) +#define REG_MDAR_APB_RF_MDAR_DAC3_CTR4 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00DC) +#define REG_MDAR_APB_RF_MDAR_DAC3_STS0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00E0) +#define REG_MDAR_APB_RF_MDAR_DAC3_STS1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00E4) +#define REG_MDAR_APB_RF_MDAR_CAL3_CTR0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00E8) +#define REG_MDAR_APB_RF_MDAR_CAL3_CTR1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00EC) +#define REG_MDAR_APB_RF_MDAR_CAL3_CTR3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00F0) +#define REG_MDAR_APB_RF_MDAR_CAL3_STS0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00F4) +#define REG_MDAR_APB_RF_MDAR_CAL3_STS1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00F8) +#define REG_MDAR_APB_RF_MDAR_DAC3_CTR00 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00FC) +#define REG_MDAR_APB_RF_MDAR_DAC3_CTR10 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0100) +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0104) +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR00 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0108) +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR01 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x010C) +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR02 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0110) +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR10 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0114) +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR11 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0118) +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR12 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x011C) +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR20 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0120) +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR21 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0124) +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR22 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0128) +#define REG_MDAR_APB_RF_MDAR_AFCDAC1_CFG SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x012C) +#define REG_MDAR_APB_RF_MDAR_AFCDAC2_CFG SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0130) +#define REG_MDAR_APB_RF_MDAR_APCDAC1_CFG SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0134) +#define REG_MDAR_APB_RF_MDAR_APCDAC2_CFG SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0138) +#define REG_MDAR_APB_RF_MDAR_RFSPI_CFG SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x13C) +#define REG_MDAR_APB_RF_MDAR_RFMIPI_CFG SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x140) +#define REG_MDAR_APB_RF_MDAR_APCDAC_OUTSEL SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x144) +#define REG_MDAR_APB_RF_MDAR_CLASH_CHK SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x148) +#define REG_MDAR_APB_RF_MDAR_CLASH_SNAP SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x14C) +#define REG_MDAR_APB_RF_MDAR_CLASH_STATUS1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x150) +#define REG_MDAR_APB_RF_MDAR_CLASH_STATUS2 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x154) +#define REG_MDAR_APB_RF_MDAR_CLASH_STATUS3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x158) +#define REG_MDAR_APB_RF_MDAR_EXTRA_CFG0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x160) +#define REG_MDAR_APB_RF_MDAR_EXTRA_CFG1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x164) +#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x168) +#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x16C) +#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF2 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x170) +#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x174) +#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF4 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x178) +#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF5 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x17C) +#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF6 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x180) +#define REG_MDAR_APB_RF_MDAR_CFG4 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0184) +#define REG_MDAR_APB_RF_MDAR_CFG5 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0188) +#define REG_MDAR_APB_RF_MDAR_CFG6 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x018C) +#define REG_MDAR_APB_RF_MDAR_CFG7 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0190) +#define REG_MDAR_APB_RF_MDAR_CFG8 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0194) +#define REG_MDAR_APB_RF_MDAR_CFG9 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0198) +#define REG_MDAR_APB_RF_MDAR_CFG10 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x019C) +#define REG_MDAR_APB_RF_MDAR_CFG11 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x01B0) +#define REG_MDAR_APB_RF_MDAR_CFG12 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x01B4) +#define REG_MDAR_APB_RF_MDAR_CFG13 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x01B8) +#define REG_MDAR_APB_RF_MDAR_CFG14 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x01BC) +#define REG_MDAR_APB_RF_MDAR_CFG15 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1C0) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG10 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1C4) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG11 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1C8) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG12 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1CC) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG13 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1D0) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG14 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1D4) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG20 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1D8) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG21 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1DC) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG22 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1E0) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG23 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1E4) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG24 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1E8) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG30 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1EC) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG31 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1F0) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG32 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1F4) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG33 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1F8) +#define REG_MDAR_APB_RF_MDAR_IMB_CFG34 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1FC) + + + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG0 */ +#define BIT_MDAR_ADA_MODE ( BIT(31) ) +#define BITS_ADC3_CHANNEL_SSET(_X_) ( (_X_) << 26 & (BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_ADC2_CHANNEL_SSET(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_ADC1_CHANNEL_SSET(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)) ) +#define BIT_MDAR_WTG_MODE ( BIT(15) ) +#define BITS_ADC3_CHANNEL_MASK(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_ADC2_CHANNEL_MASK(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_ADC1_CHANNEL_MASK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG1 */ +#define BITS_DAC3_CHANNEL_SSET(_X_) ( (_X_) << 26 & (BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_DAC2_CHANNEL_SSET(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC1_CHANNEL_SSET(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_DAC3_CHANNEL_MASK(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_DAC2_CHANNEL_MASK(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DAC1_CHANNEL_MASK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG3 */ +#define BITS_DACX_SBC_SET(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_ADCX_SBC_SET(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_CTR1 */ +#define BITS_DAC1_WD_OVR(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DAC1_WADDR_OVR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DAC1_WLE_OVR ( BIT(2) ) +#define BIT_DAC1_W_OVR_I_QN ( BIT(1) ) +#define BIT_DAC1_W_OVR_EN ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_CTR2 */ +#define BIT_DAC1_AUTO_RST ( BIT(23) ) +#define BIT_DAC1_SOFT_RST ( BIT(22) ) +#define BIT_DAC1_OSBC ( BIT(21) ) +#define BIT_DAC1_ISBC ( BIT(20) ) +#define BIT_DAC1_OVR_EN_CAL ( BIT(19) ) +#define BIT_DAC1_EN_OOSCAL ( BIT(18) ) +#define BIT_DAC1_IQSWAP ( BIT(17) ) +#define BIT_DAC1_CAL_START ( BIT(16) ) +#define BITS_DAC1_OFFSETI(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DAC1_OFFSETQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_CTR3 */ +#define BITS_DAC1_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DAC1_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_CTR4 */ +#define BITS_DAC1_I_CAL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DAC1_Q_CAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_STS0 */ +#define BITS_DAC1_WTI(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DAC1_WTQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_STS1 */ +#define BITS_DAC1_DA_STATE(_X_) ( (_X_) << 17 & (BIT(17)|BIT(18)) ) +#define BIT_DAC1_DONE ( BIT(16) ) +#define BITS_DAC1_WQ_OVR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL1_CTR0 */ +#define BITS_ADC1_CLK_CAL_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_ADA1_CAL_WAIT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_CLK_ADA1_CAL_EN ( BIT(6) ) +#define BIT_DAC1_PD_CAL ( BIT(5) ) +#define BIT_ADC1_EN_CAL ( BIT(3) ) +#define BIT_ADC1_CAL ( BIT(1) ) +#define BIT_ADA1_MODE_SEL ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL1_CTR1 */ +#define BITS_ADC1_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) ) +#define BITS_ADC1_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL1_CTR3 */ +#define BIT_ADA1_CAL_START ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL1_STS0 */ +#define BIT_ADA1_CAL_DONE ( BIT(31) ) +#define BITS_ADC1_CAL_I_SUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL1_STS1 */ +#define BITS_ADC1_CAL_Q_SUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_CTR00 */ +#define BIT_DAC1_OUT_SEL_2 ( BIT(26) ) +#define BITS_DAC1_RSV_2(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC1_PCTRL_2(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)) ) +#define BIT_DAC1_CLK_SEL_2 ( BIT(18) ) +#define BIT_DAC1_OUT_SEL_1 ( BIT(17) ) +#define BITS_DAC1_RSV_1(_X_) ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)) ) +#define BITS_DAC1_PCTRL_1(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DAC1_CLK_SEL_1 ( BIT(9) ) +#define BIT_DAC1_OUT_SEL_0 ( BIT(8) ) +#define BITS_DAC1_RSV_0(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DAC1_PCTRL_0(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)) ) +#define BIT_DAC1_CLK_SEL_0 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_CTR10 */ +#define BIT_DAC1_OUT_SEL_5 ( BIT(26) ) +#define BITS_DAC1_RSV_5(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC1_PCTRL_5(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)) ) +#define BIT_DAC1_CLK_SEL_5 ( BIT(18) ) +#define BIT_DAC1_OUT_SEL_4 ( BIT(17) ) +#define BITS_DAC1_RSV_4(_X_) ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)) ) +#define BITS_DAC1_PCTRL_4(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DAC1_CLK_SEL_4 ( BIT(9) ) +#define BIT_DAC1_OUT_SEL_3 ( BIT(8) ) +#define BITS_DAC1_RSV_3(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DAC1_PCTRL_3(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)) ) +#define BIT_DAC1_CLK_SEL_3 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR0 */ +#define BIT_ADC1_SOFT_RST ( BIT(31) ) +#define BITS_ADC1_DLL_OUT(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_ADC1_CALRDOUT(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) ) +#define BIT_ADC1_DLL_SOFT_RST ( BIT(10) ) +#define BIT_ADC1_CAL_SOFT_RST ( BIT(9) ) +#define BIT_ADC1_CALRD ( BIT(8) ) +#define BIT_ADC1_CALEN ( BIT(7) ) +#define BITS_ADC1_CALADDR(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_ADC1_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR00 */ +#define BITS_ADC1_RSV_1(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC1_RSV_0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR01 */ +#define BIT_ADC1_DIG_CLK_SEL_0 ( BIT(30) ) +#define BIT_ADC1_VCM_SEL_0 ( BIT(29) ) +#define BITS_ADC1_DELAY_CAP_0(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC1_BIT_SEL_0(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC1_VREF_SEL_0(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC1_VREF_BOOST_0(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC1_QUANT_BOOST_0(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC1_DLLRD_0 ( BIT(18) ) +#define BIT_ADC1_DLLWR_0 ( BIT(17) ) +#define BIT_ADC1_DLLEN_0 ( BIT(16) ) +#define BIT_ADC1_CSBC ( BIT(15) ) +#define BIT_ADC1_IQSWAP ( BIT(14) ) +#define BITS_ADC1_DLLOOF_0(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_ADC1_OSBC ( BIT(7) ) +#define BIT_ADC1_ISBC ( BIT(6) ) +#define BITS_ADC1_DLLIN_0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR02 */ +#define BIT_ADC1_DIG_CLK_SEL_1 ( BIT(30) ) +#define BIT_ADC1_VCM_SEL_1 ( BIT(29) ) +#define BITS_ADC1_DELAY_CAP_1(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC1_BIT_SEL_1(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC1_VREF_SEL_1(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC1_VREF_BOOST_1(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC1_QUANT_BOOST_1(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC1_DLLRD_1 ( BIT(18) ) +#define BIT_ADC1_DLLWR_1 ( BIT(17) ) +#define BIT_ADC1_DLLEN_1 ( BIT(16) ) +#define BITS_ADC1_DLLOOF_1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC1_DLLIN_1(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR10 */ +#define BITS_ADC1_RSV_3(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC1_RSV_2(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR11 */ +#define BIT_ADC1_DIG_CLK_SEL_2 ( BIT(30) ) +#define BIT_ADC1_VCM_SEL_2 ( BIT(29) ) +#define BITS_ADC1_DELAY_CAP_2(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC1_BIT_SEL_2(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC1_VREF_SEL_2(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC1_VREF_BOOST_2(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC1_QUANT_BOOST_2(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC1_DLLRD_2 ( BIT(18) ) +#define BIT_ADC1_DLLWR_2 ( BIT(17) ) +#define BIT_ADC1_DLLEN_2 ( BIT(16) ) +#define BITS_ADC1_DLLOOF_2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC1_DLLIN_2(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR12 */ +#define BIT_ADC1_DIG_CLK_SEL_3 ( BIT(30) ) +#define BIT_ADC1_VCM_SEL_3 ( BIT(29) ) +#define BITS_ADC1_DELAY_CAP_3(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC1_BIT_SEL_3(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC1_VREF_SEL_3(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC1_VREF_BOOST_3(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC1_QUANT_BOOST_3(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC1_DLLRD_3 ( BIT(18) ) +#define BIT_ADC1_DLLWR_3 ( BIT(17) ) +#define BIT_ADC1_DLLEN_3 ( BIT(16) ) +#define BITS_ADC1_DLLOOF_3(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC1_DLLIN_3(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR20 */ +#define BITS_ADC1_RSV_5(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC1_RSV_4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR21 */ +#define BIT_ADC1_DIG_CLK_SEL_4 ( BIT(30) ) +#define BIT_ADC1_VCM_SEL_4 ( BIT(29) ) +#define BITS_ADC1_DELAY_CAP_4(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC1_BIT_SEL_4(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC1_VREF_SEL_4(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC1_VREF_BOOST_4(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC1_QUANT_BOOST_4(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC1_DLLRD_4 ( BIT(18) ) +#define BIT_ADC1_DLLWR_4 ( BIT(17) ) +#define BIT_ADC1_DLLEN_4 ( BIT(16) ) +#define BITS_ADC1_DLLOOF_4(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC1_DLLIN_4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR22 */ +#define BIT_ADC1_DIG_CLK_SEL_5 ( BIT(30) ) +#define BIT_ADC1_VCM_SEL_5 ( BIT(29) ) +#define BITS_ADC1_DELAY_CAP_5(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC1_BIT_SEL_5(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC1_VREF_SEL_5(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC1_VREF_BOOST_5(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC1_QUANT_BOOST_5(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC1_DLLRD_5 ( BIT(18) ) +#define BIT_ADC1_DLLWR_5 ( BIT(17) ) +#define BIT_ADC1_DLLEN_5 ( BIT(16) ) +#define BITS_ADC1_DLLOOF_5(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC1_DLLIN_5(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_CTR1 */ +#define BITS_DAC2_WD_OVR(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DAC2_WADDR_OVR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DAC2_WLE_OVR ( BIT(2) ) +#define BIT_DAC2_W_OVR_I_QN ( BIT(1) ) +#define BIT_DAC2_W_OVR_EN ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_CTR2 */ +#define BIT_DAC2_AUTO_RST ( BIT(23) ) +#define BIT_DAC2_SOFT_RST ( BIT(22) ) +#define BIT_DAC2_OSBC ( BIT(21) ) +#define BIT_DAC2_ISBC ( BIT(20) ) +#define BIT_DAC2_OVR_EN_CAL ( BIT(19) ) +#define BIT_DAC2_EN_OOSCAL ( BIT(18) ) +#define BIT_DAC2_IQSWAP ( BIT(17) ) +#define BIT_DAC2_CAL_START ( BIT(16) ) +#define BITS_DAC2_OFFSETI(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DAC2_OFFSETQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_CTR3 */ +#define BITS_DAC2_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DAC2_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_CTR4 */ +#define BITS_DAC2_I_CAL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DAC2_Q_CAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_STS0 */ +#define BITS_DAC2_WTI(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DAC2_WTQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_STS1 */ +#define BITS_DAC2_DA_STATE(_X_) ( (_X_) << 17 & (BIT(17)|BIT(18)) ) +#define BIT_DAC2_DONE ( BIT(16) ) +#define BITS_DAC2_WQ_OVR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL2_CTR0 */ +#define BITS_ADC2_CLK_CAL_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_ADA2_CAL_WAIT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_CLK_ADA2_CAL_EN ( BIT(6) ) +#define BIT_DAC2_PD_CAL ( BIT(5) ) +#define BIT_ADC2_EN_CAL ( BIT(3) ) +#define BIT_ADC2_CAL ( BIT(1) ) +#define BIT_ADA2_MODE_SEL ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL2_CTR1 */ +#define BITS_ADC2_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) ) +#define BITS_ADC2_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL2_CTR3 */ +#define BIT_ADA2_CAL_START ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL2_STS0 */ +#define BIT_ADA2_CAL_DONE ( BIT(31) ) +#define BITS_ADC2_CAL_I_SUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL2_STS1 */ +#define BITS_ADC2_CAL_Q_SUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_CTR00 */ +#define BIT_DAC2_OUT_SEL_2 ( BIT(26) ) +#define BITS_DAC2_RSV_2(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC2_PCTRL_2(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)) ) +#define BIT_DAC2_CLK_SEL_2 ( BIT(18) ) +#define BIT_DAC2_OUT_SEL_1 ( BIT(17) ) +#define BITS_DAC2_RSV_1(_X_) ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)) ) +#define BITS_DAC2_PCTRL_1(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DAC2_CLK_SEL_1 ( BIT(9) ) +#define BIT_DAC2_OUT_SEL_0 ( BIT(8) ) +#define BITS_DAC2_RSV_0(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DAC2_PCTRL_0(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)) ) +#define BIT_DAC2_CLK_SEL_0 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_CTR10 */ +#define BIT_DAC2_OUT_SEL_5 ( BIT(26) ) +#define BITS_DAC2_RSV_5(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC2_PCTRL_5(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)) ) +#define BIT_DAC2_CLK_SEL_5 ( BIT(18) ) +#define BIT_DAC2_OUT_SEL_4 ( BIT(17) ) +#define BITS_DAC2_RSV_4(_X_) ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)) ) +#define BITS_DAC2_PCTRL_4(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DAC2_CLK_SEL_4 ( BIT(9) ) +#define BIT_DAC2_OUT_SEL_3 ( BIT(8) ) +#define BITS_DAC2_RSV_3(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DAC2_PCTRL_3(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)) ) +#define BIT_DAC2_CLK_SEL_3 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR0 */ +#define BIT_ADC2_SOFT_RST ( BIT(31) ) +#define BITS_ADC2_DLL_OUT(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_ADC2_CALRDOUT(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) ) +#define BIT_ADC2_DLL_SOFT_RST ( BIT(10) ) +#define BIT_ADC2_CAL_SOFT_RST ( BIT(9) ) +#define BIT_ADC2_CALRD ( BIT(8) ) +#define BIT_ADC2_CALEN ( BIT(7) ) +#define BITS_ADC2_CALADDR(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_ADC2_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR00 */ +#define BITS_ADC2_RSV_1(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC2_RSV_0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR01 */ +#define BIT_ADC2_DIG_CLK_SEL_0 ( BIT(30) ) +#define BIT_ADC2_VCM_SEL_0 ( BIT(29) ) +#define BITS_ADC2_DELAY_CAP_0(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC2_BIT_SEL_0(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC2_VREF_SEL_0(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC2_VREF_BOOST_0(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC2_QUANT_BOOST_0(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC2_DLLRD_0 ( BIT(18) ) +#define BIT_ADC2_DLLWR_0 ( BIT(17) ) +#define BIT_ADC2_DLLEN_0 ( BIT(16) ) +#define BIT_ADC2_CSBC ( BIT(15) ) +#define BIT_ADC2_IQSWAP ( BIT(14) ) +#define BITS_ADC2_DLLOOF_0(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_ADC2_OSBC ( BIT(7) ) +#define BIT_ADC2_ISBC ( BIT(6) ) +#define BITS_ADC2_DLLIN_0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR02 */ +#define BIT_ADC2_DIG_CLK_SEL_1 ( BIT(30) ) +#define BIT_ADC2_VCM_SEL_1 ( BIT(29) ) +#define BITS_ADC2_DELAY_CAP_1(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC2_BIT_SEL_1(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC2_VREF_SEL_1(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC2_VREF_BOOST_1(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC2_QUANT_BOOST_1(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC2_DLLRD_1 ( BIT(18) ) +#define BIT_ADC2_DLLWR_1 ( BIT(17) ) +#define BIT_ADC2_DLLEN_1 ( BIT(16) ) +#define BITS_ADC2_DLLOOF_1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC2_DLLIN_1(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR10 */ +#define BITS_ADC2_RSV_3(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC2_RSV_2(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR11 */ +#define BIT_ADC2_DIG_CLK_SEL_2 ( BIT(30) ) +#define BIT_ADC2_VCM_SEL_2 ( BIT(29) ) +#define BITS_ADC2_DELAY_CAP_2(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC2_BIT_SEL_2(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC2_VREF_SEL_2(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC2_VREF_BOOST_2(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC2_QUANT_BOOST_2(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC2_DLLRD_2 ( BIT(18) ) +#define BIT_ADC2_DLLWR_2 ( BIT(17) ) +#define BIT_ADC2_DLLEN_2 ( BIT(16) ) +#define BITS_ADC2_DLLOOF_2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC2_DLLIN_2(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR12 */ +#define BIT_ADC2_DIG_CLK_SEL_3 ( BIT(30) ) +#define BIT_ADC2_VCM_SEL_3 ( BIT(29) ) +#define BITS_ADC2_DELAY_CAP_3(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC2_BIT_SEL_3(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC2_VREF_SEL_3(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC2_VREF_BOOST_3(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC2_QUANT_BOOST_3(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC2_DLLRD_3 ( BIT(18) ) +#define BIT_ADC2_DLLWR_3 ( BIT(17) ) +#define BIT_ADC2_DLLEN_3 ( BIT(16) ) +#define BITS_ADC2_DLLOOF_3(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC2_DLLIN_3(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR20 */ +#define BITS_ADC2_RSV_5(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC2_RSV_4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR21 */ +#define BIT_ADC2_DIG_CLK_SEL_4 ( BIT(30) ) +#define BIT_ADC2_VCM_SEL_4 ( BIT(29) ) +#define BITS_ADC2_DELAY_CAP_4(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC2_BIT_SEL_4(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC2_VREF_SEL_4(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC2_VREF_BOOST_4(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC2_QUANT_BOOST_4(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC2_DLLRD_4 ( BIT(18) ) +#define BIT_ADC2_DLLWR_4 ( BIT(17) ) +#define BIT_ADC2_DLLEN_4 ( BIT(16) ) +#define BITS_ADC2_DLLOOF_4(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC2_DLLIN_4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR22 */ +#define BIT_ADC2_DIG_CLK_SEL_5 ( BIT(30) ) +#define BIT_ADC2_VCM_SEL_5 ( BIT(29) ) +#define BITS_ADC2_DELAY_CAP_5(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC2_BIT_SEL_5(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC2_VREF_SEL_5(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC2_VREF_BOOST_5(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC2_QUANT_BOOST_5(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC2_DLLRD_5 ( BIT(18) ) +#define BIT_ADC2_DLLWR_5 ( BIT(17) ) +#define BIT_ADC2_DLLEN_5 ( BIT(16) ) +#define BITS_ADC2_DLLOOF_5(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC2_DLLIN_5(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_CTR1 */ +#define BITS_DAC3_WD_OVR(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DAC3_WADDR_OVR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DAC3_WLE_OVR ( BIT(2) ) +#define BIT_DAC3_W_OVR_I_QN ( BIT(1) ) +#define BIT_DAC3_W_OVR_EN ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_CTR2 */ +#define BIT_DAC3_AUTO_RST ( BIT(23) ) +#define BIT_DAC3_SOFT_RST ( BIT(22) ) +#define BIT_DAC3_OSBC ( BIT(21) ) +#define BIT_DAC3_ISBC ( BIT(20) ) +#define BIT_DAC3_OVR_EN_CAL ( BIT(19) ) +#define BIT_DAC3_EN_OOSCAL ( BIT(18) ) +#define BIT_DAC3_IQSWAP ( BIT(17) ) +#define BIT_DAC3_CAL_START ( BIT(16) ) +#define BITS_DAC3_OFFSETI(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DAC3_OFFSETQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_CTR3 */ +#define BITS_DAC3_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DAC3_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_CTR4 */ +#define BITS_DAC3_I_CAL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DAC3_Q_CAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_STS0 */ +#define BITS_DAC3_WTI(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DAC3_WTQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_STS1 */ +#define BITS_DAC3_DA_STATE(_X_) ( (_X_) << 17 & (BIT(17)|BIT(18)) ) +#define BIT_DAC3_DONE ( BIT(16) ) +#define BITS_DAC3_WQ_OVR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL3_CTR0 */ +#define BITS_ADC3_CLK_CAL_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_ADA3_CAL_WAIT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_CLK_ADA3_CAL_EN ( BIT(6) ) +#define BIT_DAC3_PD_CAL ( BIT(5) ) +#define BIT_ADC3_EN_CAL ( BIT(3) ) +#define BIT_ADC3_CAL ( BIT(1) ) +#define BIT_ADA3_MODE_SEL ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL3_CTR1 */ +#define BITS_ADC3_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) ) +#define BITS_ADC3_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL3_CTR3 */ +#define BIT_ADA3_CAL_START ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL3_STS0 */ +#define BIT_ADA3_CAL_DONE ( BIT(31) ) +#define BITS_ADC3_CAL_I_SUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL3_STS1 */ +#define BITS_ADC3_CAL_Q_SUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_CTR00 */ +#define BIT_DAC3_OUT_SEL_2 ( BIT(26) ) +#define BITS_DAC3_RSV_2(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC3_PCTRL_2(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)) ) +#define BIT_DAC3_CLK_SEL_2 ( BIT(18) ) +#define BIT_DAC3_OUT_SEL_1 ( BIT(17) ) +#define BITS_DAC3_RSV_1(_X_) ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)) ) +#define BITS_DAC3_PCTRL_1(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DAC3_CLK_SEL_1 ( BIT(9) ) +#define BIT_DAC3_OUT_SEL_0 ( BIT(8) ) +#define BITS_DAC3_RSV_0(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DAC3_PCTRL_0(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)) ) +#define BIT_DAC3_CLK_SEL_0 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_CTR10 */ +#define BIT_DAC3_OUT_SEL_5 ( BIT(26) ) +#define BITS_DAC3_RSV_5(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC3_PCTRL_5(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)) ) +#define BIT_DAC3_CLK_SEL_5 ( BIT(18) ) +#define BIT_DAC3_OUT_SEL_4 ( BIT(17) ) +#define BITS_DAC3_RSV_4(_X_) ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)) ) +#define BITS_DAC3_PCTRL_4(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DAC3_CLK_SEL_4 ( BIT(9) ) +#define BIT_DAC3_OUT_SEL_3 ( BIT(8) ) +#define BITS_DAC3_RSV_3(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DAC3_PCTRL_3(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)) ) +#define BIT_DAC3_CLK_SEL_3 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR0 */ +#define BIT_ADC3_SOFT_RST ( BIT(31) ) +#define BITS_ADC3_DLL_OUT(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_ADC3_CALRDOUT(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) ) +#define BIT_ADC3_DLL_SOFT_RST ( BIT(10) ) +#define BIT_ADC3_CAL_SOFT_RST ( BIT(9) ) +#define BIT_ADC3_CALRD ( BIT(8) ) +#define BIT_ADC3_CALEN ( BIT(7) ) +#define BITS_ADC3_CALADDR(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_ADC3_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR00 */ +#define BITS_ADC3_RSV_1(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC3_RSV_0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR01 */ +#define BIT_ADC3_DIG_CLK_SEL_0 ( BIT(30) ) +#define BIT_ADC3_VCM_SEL_0 ( BIT(29) ) +#define BITS_ADC3_DELAY_CAP_0(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC3_BIT_SEL_0(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC3_VREF_SEL_0(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC3_VREF_BOOST_0(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC3_QUANT_BOOST_0(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC3_DLLRD_0 ( BIT(18) ) +#define BIT_ADC3_DLLWR_0 ( BIT(17) ) +#define BIT_ADC3_DLLEN_0 ( BIT(16) ) +#define BIT_ADC3_CSBC ( BIT(15) ) +#define BIT_ADC3_IQSWAP ( BIT(14) ) +#define BITS_ADC3_DLLOOF_0(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_ADC3_OSBC ( BIT(7) ) +#define BIT_ADC3_ISBC ( BIT(6) ) +#define BITS_ADC3_DLLIN_0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR02 */ +#define BIT_ADC3_DIG_CLK_SEL_1 ( BIT(30) ) +#define BIT_ADC3_VCM_SEL_1 ( BIT(29) ) +#define BITS_ADC3_DELAY_CAP_1(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC3_BIT_SEL_1(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC3_VREF_SEL_1(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC3_VREF_BOOST_1(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC3_QUANT_BOOST_1(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC3_DLLRD_1 ( BIT(18) ) +#define BIT_ADC3_DLLWR_1 ( BIT(17) ) +#define BIT_ADC3_DLLEN_1 ( BIT(16) ) +#define BITS_ADC3_DLLOOF_1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC3_DLLIN_1(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR10 */ +#define BITS_ADC3_RSV_3(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC3_RSV_2(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR11 */ +#define BIT_ADC3_DIG_CLK_SEL_2 ( BIT(30) ) +#define BIT_ADC3_VCM_SEL_2 ( BIT(29) ) +#define BITS_ADC3_DELAY_CAP_2(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC3_BIT_SEL_2(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC3_VREF_SEL_2(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC3_VREF_BOOST_2(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC3_QUANT_BOOST_2(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC3_DLLRD_2 ( BIT(18) ) +#define BIT_ADC3_DLLWR_2 ( BIT(17) ) +#define BIT_ADC3_DLLEN_2 ( BIT(16) ) +#define BITS_ADC3_DLLOOF_2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC3_DLLIN_2(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR12 */ +#define BIT_ADC3_DIG_CLK_SEL_3 ( BIT(30) ) +#define BIT_ADC3_VCM_SEL_3 ( BIT(29) ) +#define BITS_ADC3_DELAY_CAP_3(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC3_BIT_SEL_3(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC3_VREF_SEL_3(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC3_VREF_BOOST_3(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC3_QUANT_BOOST_3(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC3_DLLRD_3 ( BIT(18) ) +#define BIT_ADC3_DLLWR_3 ( BIT(17) ) +#define BIT_ADC3_DLLEN_3 ( BIT(16) ) +#define BITS_ADC3_DLLOOF_3(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC3_DLLIN_3(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR20 */ +#define BITS_ADC3_RSV_5(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC3_RSV_4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR21 */ +#define BIT_ADC3_DIG_CLK_SEL_4 ( BIT(30) ) +#define BIT_ADC3_VCM_SEL_4 ( BIT(29) ) +#define BITS_ADC3_DELAY_CAP_4(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC3_BIT_SEL_4(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC3_VREF_SEL_4(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC3_VREF_BOOST_4(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC3_QUANT_BOOST_4(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC3_DLLRD_4 ( BIT(18) ) +#define BIT_ADC3_DLLWR_4 ( BIT(17) ) +#define BIT_ADC3_DLLEN_4 ( BIT(16) ) +#define BITS_ADC3_DLLOOF_4(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC3_DLLIN_4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR22 */ +#define BIT_ADC3_DIG_CLK_SEL_5 ( BIT(30) ) +#define BIT_ADC3_VCM_SEL_5 ( BIT(29) ) +#define BITS_ADC3_DELAY_CAP_5(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC3_BIT_SEL_5(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC3_VREF_SEL_5(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC3_VREF_BOOST_5(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC3_QUANT_BOOST_5(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC3_DLLRD_5 ( BIT(18) ) +#define BIT_ADC3_DLLWR_5 ( BIT(17) ) +#define BIT_ADC3_DLLEN_5 ( BIT(16) ) +#define BITS_ADC3_DLLOOF_5(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC3_DLLIN_5(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_AFCDAC1_CFG */ +#define BITS_AFCDAC1_CHANNEL_MASK(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_AFCDAC1_CHANNEL_SSET(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BIT_AFCDAC1_LOW_V_CON_SST ( BIT(23) ) +#define BIT_AFCDAC1_BP_RES_SST ( BIT(20) ) +#define BITS_AFCDAC1_G_SST(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_AFCDAC1_CTL_SST(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BIT_AFCDAC1_PD_SST ( BIT(15) ) +#define BITS_AFCDAC1_D_SST(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_AFCDAC2_CFG */ +#define BITS_AFCDAC2_CHANNEL_MASK(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_AFCDAC2_CHANNEL_SSET(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BIT_AFCDAC2_LOW_V_CON_SST ( BIT(23) ) +#define BIT_AFCDAC2_BP_RES_SST ( BIT(20) ) +#define BITS_AFCDAC2_G_SST(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_AFCDAC2_CTL_SST(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BIT_AFCDAC2_PD_SST ( BIT(15) ) +#define BITS_AFCDAC2_D_SST(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_APCDAC1_CFG */ +#define BITS_APCDAC1_CHANNEL_MASK(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_APCDAC1_CHANNEL_SSET(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BIT_APCDAC1_LOW_V_CON_SST ( BIT(23) ) +#define BITS_APCDAC1_OUTSEL_SST(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BIT_APCDAC1_BP_RES_SST ( BIT(20) ) +#define BITS_APCDAC1_G_SST(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_APCDAC1_CTL_SST(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BIT_APCDAC1_PD_SST ( BIT(15) ) +#define BIT_APCDAC1_SEL_SST ( BIT(14) ) +#define BITS_APCDAC1_D_SST(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_APCDAC2_CFG */ +#define BITS_APCDAC2_CHANNEL_MASK(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_APCDAC2_CHANNEL_SSET(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BIT_APCDAC2_LOW_V_CON_SST ( BIT(23) ) +#define BITS_APCDAC2_OUTSEL_SST(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BIT_APCDAC2_BP_RES_SST ( BIT(20) ) +#define BITS_APCDAC2_G_SST(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_APCDAC2_CTL_SST(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BIT_APCDAC2_PD_SST ( BIT(15) ) +#define BIT_APCDAC2_SEL_SST ( BIT(14) ) +#define BITS_APCDAC2_D_SST(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFSPI_CFG */ +#define BITS_RFSBI2_CHANNEL_MASK(_X_) ( (_X_) << 29 & (BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_RFSBI2_CHANNEL_SSET(_X_) ( (_X_) << 26 & (BIT(26)|BIT(27)|BIT(28)) ) +#define BIT_RFSBI2_IDATA_SST ( BIT(25) ) +#define BIT_RFSBI2_ODATA_SST ( BIT(24) ) +#define BIT_RFSBI2_DATA_OE_SST ( BIT(23) ) +#define BIT_RFSBI2_DATA_IE_SST ( BIT(22) ) +#define BIT_RFSBI2_CLK_SST ( BIT(21) ) +#define BIT_RFSBI2_CLK_OE_SST ( BIT(20) ) +#define BIT_RFSBI2_EN0_SST ( BIT(19) ) +#define BIT_RFSBI2_EN0_OE_SST ( BIT(18) ) +#define BIT_RFSBI2_EN1_SST ( BIT(17) ) +#define BIT_RFSBI2_EN1_OE_SST ( BIT(16) ) +#define BITS_RFSBI1_CHANNEL_MASK(_X_) ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_RFSBI1_CHANNEL_SSET(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_RFSBI1_IDATA_SST ( BIT(9) ) +#define BIT_RFSBI1_ODATA_SST ( BIT(8) ) +#define BIT_RFSBI1_DATA_OE_SST ( BIT(7) ) +#define BIT_RFSBI1_DATA_IE_SST ( BIT(6) ) +#define BIT_RFSBI1_CLK_SST ( BIT(5) ) +#define BIT_RFSBI1_CLK_OE_SST ( BIT(4) ) +#define BIT_RFSBI1_EN0_SST ( BIT(3) ) +#define BIT_RFSBI1_EN0_OE_SST ( BIT(2) ) +#define BIT_RFSBI1_EN1_SST ( BIT(1) ) +#define BIT_RFSBI1_EN1_OE_SST ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFMIPI_CFG */ +#define BITS_RFMIPI2_CHANNEL_MASK(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_RFMIPI2_CHANNEL_SSET(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BIT_PAD_OUT_RFFE2_CLK_SST ( BIT(20) ) +#define BIT_PAD_OUT_RFFE2_DATA_SST ( BIT(19) ) +#define BIT_PAD_IN_RFFE2_DATA_SST ( BIT(18) ) +#define BIT_PAD_OE_RFFE2_DATA_SST ( BIT(17) ) +#define BIT_PAD_IE_RFFE2_DATA_SST ( BIT(16) ) +#define BITS_RFMIPI1_CHANNEL_MASK(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_RFMIPI1_CHANNEL_SSET(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BIT_PAD_OUT_RFFE1_CLK_SST ( BIT(4) ) +#define BIT_PAD_OUT_RFFE1_DATA_SST ( BIT(3) ) +#define BIT_PAD_IN_RFFE1_DATA_SST ( BIT(2) ) +#define BIT_PAD_OE_RFFE1_DATA_SST ( BIT(1) ) +#define BIT_PAD_IE_RFFE1_DATA_SST ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_APCDAC_OUTSEL */ +#define BIT_AFCDAC_LOW_V_CON_GGE ( BIT(31) ) +#define BIT_AFCDAC_LOW_V_CON_WG ( BIT(30) ) +#define BIT_AFCDAC_LOW_V_CON_WD ( BIT(29) ) +#define BIT_AFCDAC_LOW_V_CON_TG ( BIT(28) ) +#define BIT_AFCDAC_LOW_V_CON_TD ( BIT(27) ) +#define BIT_AFCDAC_LOW_V_CON_LTE ( BIT(26) ) +#define BITS_APCDACX_G3_SST(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_APCDACX_G2_SST(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)) ) +#define BITS_APCDACX_G1_SST(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)) ) +#define BITS_APCDACX_G0_SST(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BIT_APCDAC_LOW_V_CON_GGE ( BIT(17) ) +#define BIT_APCDAC_LOW_V_CON_WG ( BIT(16) ) +#define BIT_APCDAC_LOW_V_CON_WD ( BIT(15) ) +#define BIT_APCDAC_LOW_V_CON_TG ( BIT(14) ) +#define BIT_APCDAC_LOW_V_CON_TD ( BIT(13) ) +#define BIT_APCDAC_LOW_V_CON_LTE ( BIT(12) ) +#define BITS_APCDAC_OUTSEL_GGE(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_APCDAC_OUTSEL_WG(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_APCDAC_OUTSEL_WD(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_APCDAC_OUTSEL_TG(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_APCDAC_OUTSEL_TD(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_APCDAC_OUTSEL_LTE(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CLASH_CHK */ +#define BIT_RFSBI2_CLASH_CHK_INTRP_EN ( BIT(29) ) +#define BIT_RFSBI1_CLASH_CHK_INTRP_EN ( BIT(28) ) +#define BIT_RFMIPI2_CLASH_CHK_INTRP_EN ( BIT(27) ) +#define BIT_RFMIPI1_CLASH_CHK_INTRP_EN ( BIT(26) ) +#define BIT_APCDAC2_CLASH_CHK_INTRP_EN ( BIT(25) ) +#define BIT_APCDAC1_CLASH_CHK_INTRP_EN ( BIT(24) ) +#define BIT_AFCDAC2_CLASH_CHK_INTRP_EN ( BIT(23) ) +#define BIT_AFCDAC1_CLASH_CHK_INTRP_EN ( BIT(22) ) +#define BIT_ADA3_TX_CLASH_CHK_INTRP_EN ( BIT(21) ) +#define BIT_ADA3_RX_CLASH_CHK_INTRP_EN ( BIT(20) ) +#define BIT_ADA2_TX_CLASH_CHK_INTRP_EN ( BIT(19) ) +#define BIT_ADA2_RX_CLASH_CHK_INTRP_EN ( BIT(18) ) +#define BIT_ADA1_TX_CLASH_CHK_INTRP_EN ( BIT(17) ) +#define BIT_ADA1_RX_CLASH_CHK_INTRP_EN ( BIT(16) ) +#define BIT_CHK_CLASH_STFREE ( BIT(8) ) +#define BIT_CHK_CLASH_CLR ( BIT(7) ) +#define BIT_CHK_CLASH_RTC_SNAP_MODE ( BIT(4) ) +#define BIT_CHK_CLASH_RTC_SNAP_EDGE ( BIT(3) ) +#define BIT_CHK_CLASH_RTC_SNAP_INTRP_TYPE ( BIT(2) ) +#define BIT_CHK_CLASH_RTC_SNAP_INTRP_CLR ( BIT(1) ) +#define BIT_CHK_CLASH_RTC_SNAP_INTRP ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CLASH_SNAP */ +#define BITS_CHK_CLASH_RTC_SNAP_TIME(_X_) (_X_) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CLASH_STATUS1 */ +#define BITS_CHK_CLASH_ADA3_TX_CHANNEL_SEL(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_CHK_CLASH_ADA3_RX_CHANNEL_SEL(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) ) +#define BITS_CHK_CLASH_ADA2_TX_CHANNEL_SEL(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_CHK_CLASH_ADA2_RX_CHANNEL_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_CHK_CLASH_ADA1_TX_CHANNEL_SEL(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_CHK_CLASH_ADA1_RX_CHANNEL_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CLASH_STATUS2 */ +#define BITS_CHK_CLASH_APCDAC2_CHANNEL_SEL(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_CHK_CLASH_APCDAC1_CHANNEL_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CHK_CLASH_AFCDAC2_CHANNEL_SEL(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_CHK_CLASH_AFCDAC1_CHANNEL_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CLASH_STATUS3 */ +#define BITS_CHK_CLASH_RFSBI2_CHANNEL_SEL(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_CHK_CLASH_RFSBI1_CHANNEL_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CHK_CLASH_RFMIPI2_CHANNEL_SEL(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_CHK_CLASH_RFMIPI1_CHANNEL_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_EXTRA_CFG0 */ +#define BITS_APT_DCM2_EXTRA_CFG(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_APT_DCM2_ADI_EN ( BIT(23) ) +#define BITS_APT_DCM2_CHANNEL_SSET(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BIT_APT_DCM2_SST ( BIT(19) ) +#define BITS_APT_DCM2_CHANNEL_MASK(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)) ) +#define BITS_APT_DCM1_EXTRA_CFG(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_APT_DCM1_ADI_EN ( BIT(7) ) +#define BITS_APT_DCM1_CHANNEL_SSET(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_APT_DCM1_SST ( BIT(3) ) +#define BITS_APT_DCM1_CHANNEL_MASK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_EXTRA_CFG1 */ +#define BITS_MDAR_EXTRA_CFG1(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_MDAR_EXTRA_CFG1_2 ( BIT(12) ) +#define BIT_MDAR_EXTRA_CFG1_1 ( BIT(11) ) +#define BIT_MDAR_EXTRA_CFG1_0 ( BIT(10) ) +#define BITS_MDAR_BB_LDO_REFCTRL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_MDAR_BB_LDO_SLEEP_PD_EN ( BIT(6) ) +#define BIT_MDAR_BB_LDO_FORCE_ON ( BIT(5) ) +#define BIT_MDAR_BB_LDO_FORCE_PD ( BIT(4) ) +#define BIT_MDAR_BB_BG_SLEEP_PD_EN ( BIT(2) ) +#define BIT_MDAR_BB_BG_FORCE_ON ( BIT(1) ) +#define BIT_MDAR_BB_BG_FORCE_PD ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF0 */ +#define BITS_CHK_CLASH_RFCTRL15_CHX_SEL(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BIT_RFCTRL15_CHK_INTRP_EN ( BIT(16) ) +#define BIT_RFCTRL15_RTC_REFRESH ( BIT(12) ) +#define BIT_RFCTRL15_SNAP_REFRESH ( BIT(8) ) +#define BITS_RFCTRL15_SSET(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BITS_RFCTRL15_MASK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF1 */ +#define BITS_RFCTRL15_CH0_SNAP1_RTC_TIME(_X_) (_X_) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF2 */ +#define BITS_RFCTRL15_CH0_SNAP0_RTC_TIME(_X_) (_X_) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF3 */ +#define BITS_RFCTRL15_CH1_SNAP1_RTC_TIME(_X_) (_X_) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF4 */ +#define BITS_RFCTRL15_CH1_SNAP0_RTC_TIME(_X_) (_X_) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF5 */ +#define BITS_RFCTRL15_CH2_SNAP1_RTC_TIME(_X_) (_X_) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF6 */ +#define BITS_RFCTRL15_CH2_SNAP0_RTC_TIME(_X_) (_X_) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG4 */ +#define BITS_RFCTRL_CHANNEL_MASK3(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_RFCTRL_CHANNEL_MASK2(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BITS_RFCTRL_CHANNEL_MASK1(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RFCTRL_CHANNEL_MASK0(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_RFCTRL150_SST(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG5 */ +#define BITS_RFCTRL_CHANNEL_MASK13(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_RFCTRL_CHANNEL_MASK12(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BITS_RFCTRL_CHANNEL_MASK11(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RFCTRL_CHANNEL_MASK10(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_RFCTRL_CHANNEL_MASK9(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) ) +#define BITS_RFCTRL_CHANNEL_MASK8(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_RFCTRL_CHANNEL_MASK7(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_RFCTRL_CHANNEL_MASK6(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_RFCTRL_CHANNEL_MASK5(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_RFCTRL_CHANNEL_MASK4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG6 */ +#define BITS_RFCTRL_CHANNEL_SSET7(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_RFCTRL_CHANNEL_SSET6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BITS_RFCTRL_CHANNEL_SSET5(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RFCTRL_CHANNEL_SSET4(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_RFCTRL_CHANNEL_SSET3(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) ) +#define BITS_RFCTRL_CHANNEL_SSET2(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_RFCTRL_CHANNEL_SSET1(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_RFCTRL_CHANNEL_SSET0(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_RFCTRL_CHANNEL_MASK15(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_RFCTRL_CHANNEL_MASK14(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG7 */ +#define BITS_RFCTRL_CHANNEL_SSET15(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RFCTRL_CHANNEL_SSET14(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_RFCTRL_CHANNEL_SSET13(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) ) +#define BITS_RFCTRL_CHANNEL_SSET12(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_RFCTRL_CHANNEL_SSET11(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_RFCTRL_CHANNEL_SSET10(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_RFCTRL_CHANNEL_SSET9(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_RFCTRL_CHANNEL_SSET8(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG8 */ +#define BITS_RFCTRL_CHANNEL_MASK19(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_RFCTRL_CHANNEL_MASK18(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BITS_RFCTRL_CHANNEL_MASK17(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RFCTRL_CHANNEL_MASK16(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_RFCTRL3130_SST(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_RFCTRL2916_SST(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG9 */ +#define BITS_RFCTRL_CHANNEL_MASK29(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_RFCTRL_CHANNEL_MASK28(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BITS_RFCTRL_CHANNEL_MASK27(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RFCTRL_CHANNEL_MASK26(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_RFCTRL_CHANNEL_MASK25(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) ) +#define BITS_RFCTRL_CHANNEL_MASK24(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_RFCTRL_CHANNEL_MASK23(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_RFCTRL_CHANNEL_MASK22(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_RFCTRL_CHANNEL_MASK21(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_RFCTRL_CHANNEL_MASK20(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG10 */ +#define BITS_RFCTRL_CHANNEL_SSET23(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_RFCTRL_CHANNEL_SSET22(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BITS_RFCTRL_CHANNEL_SSET21(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RFCTRL_CHANNEL_SSET20(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_RFCTRL_CHANNEL_SSET19(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) ) +#define BITS_RFCTRL_CHANNEL_SSET18(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_RFCTRL_CHANNEL_SSET17(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_RFCTRL_CHANNEL_SSET16(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_RFCTRL_CHANNEL_MASK31(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_RFCTRL_CHANNEL_MASK30(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG11 */ +#define BITS_RFCTRL_CHANNEL_SSET31(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RFCTRL_CHANNEL_SSET30(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_RFCTRL_CHANNEL_SSET29(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) ) +#define BITS_RFCTRL_CHANNEL_SSET28(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_RFCTRL_CHANNEL_SSET27(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_RFCTRL_CHANNEL_SSET26(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_RFCTRL_CHANNEL_SSET25(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_RFCTRL_CHANNEL_SSET24(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG12 */ +#define BITS_RFCTRL_WTGCFGH(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_RFCTRL_WTGCFGL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG13 */ +#define BITS_RFCTRL_GGECFGH(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_RFCTRL_GGECFGL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG14 */ +#define BITS_MDAR_CFG14(_X_) (_X_) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG15 */ +#define BITS_MDAR_ANALOG_BB_RSV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG10 */ +#define BIT_ADC1_IMBP_CLK_SEL_5 ( BIT(21) ) +#define BIT_ADC1_IMBP_CLK_SEL_4 ( BIT(20) ) +#define BIT_ADC1_IMBP_CLK_SEL_3 ( BIT(19) ) +#define BIT_ADC1_IMBP_CLK_SEL_2 ( BIT(18) ) +#define BIT_ADC1_IMBP_CLK_SEL_1 ( BIT(17) ) +#define BIT_ADC1_IMBP_CLK_SEL_0 ( BIT(16) ) +#define BIT_DAC1_IMBP_BYPASS_5 ( BIT(13) ) +#define BIT_DAC1_IMBP_BYPASS_4 ( BIT(12) ) +#define BIT_DAC1_IMBP_BYPASS_3 ( BIT(11) ) +#define BIT_DAC1_IMBP_BYPASS_2 ( BIT(10) ) +#define BIT_DAC1_IMBP_BYPASS_1 ( BIT(9) ) +#define BIT_DAC1_IMBP_BYPASS_0 ( BIT(8) ) +#define BIT_ADC1_IMBP_BYPASS_5 ( BIT(5) ) +#define BIT_ADC1_IMBP_BYPASS_4 ( BIT(4) ) +#define BIT_ADC1_IMBP_BYPASS_3 ( BIT(3) ) +#define BIT_ADC1_IMBP_BYPASS_2 ( BIT(2) ) +#define BIT_ADC1_IMBP_BYPASS_1 ( BIT(1) ) +#define BIT_ADC1_IMBP_BYPASS_0 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG11 */ +#define BITS_ADC1_BAL_B(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_ADC1_BAL_A(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG12 */ +#define BITS_ADC1_BAL_D(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_ADC1_BAL_C(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG13 */ +#define BITS_DAC1_BAL_B(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_DAC1_BAL_A(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG14 */ +#define BITS_DAC1_BAL_D(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_DAC1_BAL_C(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG20 */ +#define BIT_ADC2_IMBP_CLK_SEL_5 ( BIT(21) ) +#define BIT_ADC2_IMBP_CLK_SEL_4 ( BIT(20) ) +#define BIT_ADC2_IMBP_CLK_SEL_3 ( BIT(19) ) +#define BIT_ADC2_IMBP_CLK_SEL_2 ( BIT(18) ) +#define BIT_ADC2_IMBP_CLK_SEL_1 ( BIT(17) ) +#define BIT_ADC2_IMBP_CLK_SEL_0 ( BIT(16) ) +#define BIT_DAC2_IMBP_BYPASS_5 ( BIT(13) ) +#define BIT_DAC2_IMBP_BYPASS_4 ( BIT(12) ) +#define BIT_DAC2_IMBP_BYPASS_3 ( BIT(11) ) +#define BIT_DAC2_IMBP_BYPASS_2 ( BIT(10) ) +#define BIT_DAC2_IMBP_BYPASS_1 ( BIT(9) ) +#define BIT_DAC2_IMBP_BYPASS_0 ( BIT(8) ) +#define BIT_ADC2_IMBP_BYPASS_5 ( BIT(5) ) +#define BIT_ADC2_IMBP_BYPASS_4 ( BIT(4) ) +#define BIT_ADC2_IMBP_BYPASS_3 ( BIT(3) ) +#define BIT_ADC2_IMBP_BYPASS_2 ( BIT(2) ) +#define BIT_ADC2_IMBP_BYPASS_1 ( BIT(1) ) +#define BIT_ADC2_IMBP_BYPASS_0 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG21 */ +#define BITS_ADC2_BAL_B(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_ADC2_BAL_A(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG22 */ +#define BITS_ADC2_BAL_D(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_ADC2_BAL_C(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG23 */ +#define BITS_DAC2_BAL_B(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_DAC2_BAL_A(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG24 */ +#define BITS_DAC2_BAL_D(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_DAC2_BAL_C(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG30 */ +#define BIT_ADC3_IMBP_CLK_SEL_5 ( BIT(21) ) +#define BIT_ADC3_IMBP_CLK_SEL_4 ( BIT(20) ) +#define BIT_ADC3_IMBP_CLK_SEL_3 ( BIT(19) ) +#define BIT_ADC3_IMBP_CLK_SEL_2 ( BIT(18) ) +#define BIT_ADC3_IMBP_CLK_SEL_1 ( BIT(17) ) +#define BIT_ADC3_IMBP_CLK_SEL_0 ( BIT(16) ) +#define BIT_DAC3_IMBP_BYPASS_5 ( BIT(13) ) +#define BIT_DAC3_IMBP_BYPASS_4 ( BIT(12) ) +#define BIT_DAC3_IMBP_BYPASS_3 ( BIT(11) ) +#define BIT_DAC3_IMBP_BYPASS_2 ( BIT(10) ) +#define BIT_DAC3_IMBP_BYPASS_1 ( BIT(9) ) +#define BIT_DAC3_IMBP_BYPASS_0 ( BIT(8) ) +#define BIT_ADC3_IMBP_BYPASS_5 ( BIT(5) ) +#define BIT_ADC3_IMBP_BYPASS_4 ( BIT(4) ) +#define BIT_ADC3_IMBP_BYPASS_3 ( BIT(3) ) +#define BIT_ADC3_IMBP_BYPASS_2 ( BIT(2) ) +#define BIT_ADC3_IMBP_BYPASS_1 ( BIT(1) ) +#define BIT_ADC3_IMBP_BYPASS_0 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG31 */ +#define BITS_ADC3_BAL_B(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_ADC3_BAL_A(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG32 */ +#define BITS_ADC3_BAL_D(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_ADC3_BAL_C(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG33 */ +#define BITS_DAC3_BAL_B(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_DAC3_BAL_A(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG34 */ +#define BITS_DAC3_BAL_D(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_DAC3_BAL_C(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +#endif diff --git a/include/soc/sprd/chip_x35l64/__regs_mm_ahb_rf.h b/include/soc/sprd/chip_x35l64/__regs_mm_ahb_rf.h new file mode 100755 index 00000000..af50d060 --- /dev/null +++ b/include/soc/sprd/chip_x35l64/__regs_mm_ahb_rf.h @@ -0,0 +1,102 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + + + +#ifndef __H_REGS_MM_AHB_RF_HEADFILE_H__ +#define __H_REGS_MM_AHB_RF_HEADFILE_H__ __FILE__ + +#define REGS_MM_AHB_RF + +/* registers definitions for MM_AHB_RF */ +#define REG_MM_AHB_AHB_EB SCI_ADDR(REGS_MM_AHB_BASE, 0x0000)/*AHB_EB*/ +#define REG_MM_AHB_AHB_RST SCI_ADDR(REGS_MM_AHB_BASE, 0x0004)/*AHB_RST*/ +#define REG_MM_AHB_GEN_CKG_CFG SCI_ADDR(REGS_MM_AHB_BASE, 0x0008)/*GEN_CKG_CFG*/ +#define REG_MM_AHB_MIPI_CSI2_CTRL SCI_ADDR(REGS_MM_AHB_BASE, 0x000C)/*MIPI_CSI2_CTRL*/ +#define REG_MM_AHB_MM_QOS_CFG SCI_ADDR(REGS_MM_AHB_BASE, 0x0010)/*MM_QOS_CFG*/ + +#define REG_MM_AHB_RF_AHB_EB REG_MM_AHB_AHB_EB +#define REG_MM_AHB_RF_AHB_RST REG_MM_AHB_AHB_RST +#define REG_MM_AHB_RF_GEN_CKG_CFG REG_MM_AHB_GEN_CKG_CFG +#define REG_MM_AHB_RF_MIPI_CSI2_CTRL REG_MM_AHB_MIPI_CSI2_CTRL +#define REG_MM_AHB_RF_MM_QOS_CFG REG_MM_AHB_MM_QOS_CFG + + + +/* bits definitions for register REG_MM_AHB_AHB_EB */ +#define BIT_MMU_EB ( BIT(7) ) +#define BIT_MM_AHB_CKG_EB ( BIT(6) ) +#define BIT_MM_CKG_EB BIT_MM_AHB_CKG_EB +#define BIT_JPG_EB ( BIT(5) ) +#define BIT_CSI_EB ( BIT(4) ) +#define BIT_VSP_EB ( BIT(3) ) +#define BIT_ISP_EB ( BIT(2) ) +#define BIT_CCIR_EB ( BIT(1) ) +#define BIT_DCAM_EB ( BIT(0) ) + +/* bits definitions for register REG_MM_AHB_AHB_RST */ +#define BIT_MMU_SOFT_RST ( BIT(14) ) +#define BIT_MM_AHB_CKG_SOFT_RST ( BIT(13) ) +#define BIT_MM_CKG_SOFT_RST BIT_MM_AHB_CKG_SOFT_RST +#define BIT_MM_MTX_SOFT_RST ( BIT(12) ) +#define BIT_OR1200_SOFT_RST ( BIT(11) ) +#define BIT_ROT_SOFT_RST ( BIT(10) ) +#define BIT_CAM2_SOFT_RST ( BIT(9) ) +#define BIT_CAM1_SOFT_RST ( BIT(8) ) +#define BIT_CAM0_SOFT_RST ( BIT(7) ) +#define BIT_JPG_SOFT_RST ( BIT(6) ) +#define BIT_CSI_SOFT_RST ( BIT(5) ) +#define BIT_VSP_SOFT_RST ( BIT(4) ) +#define BIT_ISP_CFG_SOFT_RST ( BIT(3) ) +#define BIT_ISP_LOG_SOFT_RST ( BIT(2) ) +#define BIT_CCIR_SOFT_RST ( BIT(1) ) +#define BIT_DCAM_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_MM_AHB_GEN_CKG_CFG */ +#define BIT_MM_MTX_AXI_CKG_EN ( BIT(8) ) +#define BIT_MM_AXI_CKG_EN ( BIT(7) ) +#define BIT_JPG_AXI_CKG_EN ( BIT(6) ) +#define BIT_VSP_AXI_CKG_EN ( BIT(5) ) +#define BIT_ISP_AXI_CKG_EN ( BIT(4) ) +#define BIT_DCAM_AXI_CKG_EN ( BIT(3) ) +#define BIT_SENSOR_CKG_EN ( BIT(2) ) +#define BIT_MIPI_CSI_CKG_EN ( BIT(1) ) +#define BIT_CPHY_CFG_CKG_EN ( BIT(0) ) + +/* bits definitions for register REG_MM_AHB_MIPI_CSI2_CTRL */ +#define BITS_MIPI_CPHY_SAMPLE_SEL(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)) ) +#define BIT_MIPI_CPHY_SYNC_MODE ( BIT(2) ) +#define BIT_MIPI_CPHY_TEST_CTL ( BIT(1) ) +#define BIT_MIPI_CPHY_SEL ( BIT(0) ) + +/* bits definitions for register REG_MM_AHB_MM_QOS_CFG */ +#define BITS_QOS_R_DCAM(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_QOS_W_DCAM(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_QOS_R_JPG(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_QOS_W_JPG(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_QOS_R_ISP(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_QOS_W_ISP(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_QOS_R_VSP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_QOS_W_VSP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +#endif diff --git a/include/soc/sprd/chip_x35l64/__regs_mm_clk.h b/include/soc/sprd/chip_x35l64/__regs_mm_clk.h new file mode 100644 index 00000000..4b73f5ef --- /dev/null +++ b/include/soc/sprd/chip_x35l64/__regs_mm_clk.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __REGS_MM_CLK_H__ +#define __REGS_MM_CLK_H__ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, include <mach/sci_glb_regs.h>" +#endif + +#define REGS_MM_CLK + +/* registers definitions for controller REGS_MM_CLK */ +#define REG_MM_CLK_MM_AHB_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0020) +#define REG_MM_CLK_SENSOR_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0024) +#define REG_MM_CLK_CCIR_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0028) +#define REG_MM_CLK_DCAM_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x002c) +#define REG_MM_CLK_VSP_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0030) +#define REG_MM_CLK_ISP_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0034) +#define REG_MM_CLK_JPG_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0038) +#define REG_MM_CLK_MIPI_CSI_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x003c) +#define REG_MM_CLK_CPHY_CFG_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0040) +#define REG_MM_CLK_ORP_TCK_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0044) + +/* vars definitions for controller REGS_MM_CLK */ + +#endif //__REGS_MM_CLK_H__ diff --git a/include/soc/sprd/chip_x35l64/__regs_pinmap.h b/include/soc/sprd/chip_x35l64/__regs_pinmap.h new file mode 100755 index 00000000..be98c3a0 --- /dev/null +++ b/include/soc/sprd/chip_x35l64/__regs_pinmap.h @@ -0,0 +1,283 @@ +#ifndef __ASM_ARM_ARCH_PINMAP_H +#error "Don't include this file directly, Pls include pinmap.h" +#endif + +#ifndef _REGS_PINMAP_H_ +#define _REGS_PINMAP_H_ + +#define CTL_PIN_BASE ( SPRD_PIN_BASE ) + +/* registers definitions for controller CTL_PIN */ +#define REG_PIN_CTRL0 ( 0x0000 ) +#define REG_PIN_CTRL1 ( 0x0004 ) +#define REG_PIN_CTRL2 ( 0x0008 ) +#define REG_PIN_CTRL3 ( 0x000c ) +#define REG_PIN_CTRL4 ( 0x0010 ) +#define REG_PIN_CTRL5 ( 0x0014 ) +#define REG_PIN_SIMCLK0 ( 0x0018 ) +#define REG_PIN_SIMDA0 ( 0x001c ) +#define REG_PIN_SIMRST0 ( 0x0020 ) +#define REG_PIN_SIMCLK1 ( 0x0024 ) +#define REG_PIN_SIMDA1 ( 0x0028 ) +#define REG_PIN_SIMRST1 ( 0x002c ) +#define REG_PIN_SD0_CLK ( 0x0030 ) +#define REG_PIN_SD0_CMD ( 0x0034 ) +#define REG_PIN_SD0_D0 ( 0x0038 ) +#define REG_PIN_SD0_D1 ( 0x003c ) +#define REG_PIN_SD0_D2 ( 0x0040 ) +#define REG_PIN_SD0_D3 ( 0x0044 ) +#define REG_PIN_ANA_INT ( 0x0048 ) +#define REG_PIN_EXT_RST_B ( 0x004c ) +#define REG_PIN_CLK_26M ( 0x0050 ) +#define REG_PIN_CHIP_SLEEP ( 0x0054 ) +#define REG_PIN_XTL_BUF_EN ( 0x0058 ) +#define REG_PIN_CLK_32K ( 0x005c ) +#define REG_PIN_AUD_SCLK ( 0x0060 ) +#define REG_PIN_AUD_ADD0 ( 0x0064 ) +#define REG_PIN_AUD_ADSYNC ( 0x0068 ) +#define REG_PIN_AUD_DAD1 ( 0x006c ) +#define REG_PIN_AUD_DAD0 ( 0x0070 ) +#define REG_PIN_AUD_DASYNC ( 0x0074 ) +#define REG_PIN_TD_TXPD ( 0x0078 ) +#define REG_PIN_TD_RXPD ( 0x007c ) +#define REG_PIN_GSM_TXPD ( 0x0080 ) +#define REG_PIN_GSM_RXPD ( 0x0084 ) +#define REG_PIN_TD_RX_CLK ( 0x0088 ) +#define REG_PIN_ADI_D ( 0x008c ) +#define REG_PIN_ADI_SYNC ( 0x0090 ) +#define REG_PIN_ADI_SCLK ( 0x0094 ) +#define REG_PIN_ANA_INT2 ( 0x0098 ) +#define REG_PIN_COM_TX_APCD ( 0x009c ) +#define REG_PIN_COM_TX_DQ1 ( 0x00a0 ) +#define REG_PIN_COM_TX_DQ0 ( 0x00a4 ) +#define REG_PIN_COM_TX_DI1 ( 0x00a8 ) +#define REG_PIN_COM_TX_DI0 ( 0x00ac ) +#define REG_PIN_COM_TX_SYNC ( 0x00b0 ) +#define REG_PIN_COM_TX_SCLK ( 0x00b4 ) +#define REG_PIN_COM_RX_DQ1 ( 0x00b8 ) +#define REG_PIN_COM_RX_DQ0 ( 0x00bc ) +#define REG_PIN_COM_RX_DI1 ( 0x00c0 ) +#define REG_PIN_COM_RX_DI0 ( 0x00c4 ) +#define REG_PIN_COM_RX_SYNC ( 0x00c8 ) +#define REG_PIN_COM_RX_SCLK ( 0x00cc ) +#define REG_PIN_CCIRCK ( 0x00d0 ) +#define REG_PIN_CCIRMCLK ( 0x00d4 ) +#define REG_PIN_CCIRHS ( 0x00d8 ) +#define REG_PIN_CCIRVS ( 0x00dc ) +#define REG_PIN_CCIRD0 ( 0x00e0 ) +#define REG_PIN_CCIRD1 ( 0x00e4 ) +#define REG_PIN_CCIRD2 ( 0x00e8 ) +#define REG_PIN_CCIRD3 ( 0x00ec ) +#define REG_PIN_CCIRD4 ( 0x00f0 ) +#define REG_PIN_CCIRD5 ( 0x00f4 ) +#define REG_PIN_CCIRD6 ( 0x00f8 ) +#define REG_PIN_CCIRD7 ( 0x00fc ) +#define REG_PIN_CCIRD8 ( 0x0100 ) +#define REG_PIN_CCIRD9 ( 0x0104 ) +#define REG_PIN_CCIRRST ( 0x0108 ) +#define REG_PIN_CCIRPD1 ( 0x010c ) +#define REG_PIN_CCIRPD0 ( 0x0110 ) +#define REG_PIN_SCL1 ( 0x0114 ) +#define REG_PIN_SDA1 ( 0x0118 ) +#define REG_PIN_KEYOUT0 ( 0x011c ) +#define REG_PIN_KEYOUT1 ( 0x0120 ) +#define REG_PIN_KEYOUT2 ( 0x0124 ) +#define REG_PIN_KEYOUT3 ( 0x0128 ) +#define REG_PIN_KEYOUT4 ( 0x012c ) +#define REG_PIN_KEYOUT5 ( 0x0130 ) +#define REG_PIN_GPIO135 ( 0x0134 ) +#define REG_PIN_GPIO136 ( 0x0138 ) +#define REG_PIN_GPIO137 ( 0x013c ) +#define REG_PIN_GPIO138 ( 0x0140 ) +#define REG_PIN_GPIO139 ( 0x0144 ) +#define REG_PIN_GPIO140 ( 0x0148 ) +#define REG_PIN_KEYOUT6 ( 0x014c ) +#define REG_PIN_KEYOUT7 ( 0x0150 ) +#define REG_PIN_KEYIN0 ( 0x0154 ) +#define REG_PIN_KEYIN1 ( 0x0158 ) +#define REG_PIN_KEYIN2 ( 0x015c ) +#define REG_PIN_KEYIN3 ( 0x0160 ) +#define REG_PIN_KEYIN4 ( 0x0164 ) +#define REG_PIN_KEYIN5 ( 0x0168 ) +#define REG_PIN_KEYIN6 ( 0x016c ) +#define REG_PIN_KEYIN7 ( 0x0170 ) +#define REG_PIN_NFWPN ( 0x0174 ) +#define REG_PIN_NFRB ( 0x0178 ) +#define REG_PIN_NFCLE ( 0x017c ) +#define REG_PIN_NFALE ( 0x0180 ) +#define REG_PIN_NFCEN ( 0x0184 ) +#define REG_PIN_NFREN ( 0x0188 ) +#define REG_PIN_NFWEN ( 0x018c ) +#define REG_PIN_NFD0 ( 0x0190 ) +#define REG_PIN_NFD1 ( 0x0194 ) +#define REG_PIN_NFD2 ( 0x0198 ) +#define REG_PIN_NFD3 ( 0x019c ) +#define REG_PIN_NFD4 ( 0x01a0 ) +#define REG_PIN_NFD5 ( 0x01a4 ) +#define REG_PIN_NFD6 ( 0x01a8 ) +#define REG_PIN_NFD7 ( 0x01ac ) +#define REG_PIN_NFD8 ( 0x01b0 ) +#define REG_PIN_NFD9 ( 0x01b4 ) +#define REG_PIN_NFD10 ( 0x01b8 ) +#define REG_PIN_NFD11 ( 0x01bc ) +#define REG_PIN_NFD12 ( 0x01c0 ) +#define REG_PIN_NFD13 ( 0x01c4 ) +#define REG_PIN_NFD14 ( 0x01c8 ) +#define REG_PIN_NFD15 ( 0x01cc ) +#define REG_PIN_SD3_CLK ( 0x01d0 ) +#define REG_PIN_SD3_CMD ( 0x01d4 ) +#define REG_PIN_SD3_D0 ( 0x01d8 ) +#define REG_PIN_SD3_D1 ( 0x01dc ) +#define REG_PIN_SD3_D2 ( 0x01e0 ) +#define REG_PIN_SD3_D3 ( 0x01e4 ) +#define REG_PIN_SD3_D4 ( 0x01e8 ) +#define REG_PIN_SD3_D5 ( 0x01ec ) +#define REG_PIN_SD3_D6 ( 0x01f0 ) +#define REG_PIN_SD3_D7 ( 0x01f4 ) +#define REG_PIN_EMMC_RST ( 0x01f8 ) +#define REG_PIN_SD1_CLK ( 0x01fc ) +#define REG_PIN_SD1_CMD ( 0x0200 ) +#define REG_PIN_SD1_D0 ( 0x0204 ) +#define REG_PIN_SD1_D1 ( 0x0208 ) +#define REG_PIN_SD1_D2 ( 0x020c ) +#define REG_PIN_SD1_D3 ( 0x0210 ) +#define REG_PIN_LCD_CSN1 ( 0x0214 ) +#define REG_PIN_LCD_RSTN ( 0x0218 ) +#define REG_PIN_LCD_CD ( 0x021c ) +#define REG_PIN_LCD_D0 ( 0x0220 ) +#define REG_PIN_LCD_D1 ( 0x0224 ) +#define REG_PIN_LCD_D2 ( 0x0228 ) +#define REG_PIN_LCD_D3 ( 0x022c ) +#define REG_PIN_LCD_D4 ( 0x0230 ) +#define REG_PIN_LCD_D5 ( 0x0234 ) +#define REG_PIN_LCD_D6 ( 0x0238 ) +#define REG_PIN_LCD_D7 ( 0x023c ) +#define REG_PIN_LCD_D8 ( 0x0240 ) +#define REG_PIN_LCD_WRN ( 0x0244 ) +#define REG_PIN_LCD_RDN ( 0x0248 ) +#define REG_PIN_LCD_CSN0 ( 0x024c ) +#define REG_PIN_LCD_D9 ( 0x0250 ) +#define REG_PIN_LCD_D10 ( 0x0254 ) +#define REG_PIN_LCD_D11 ( 0x0258 ) +#define REG_PIN_LCD_D12 ( 0x025c ) +#define REG_PIN_LCD_D13 ( 0x0260 ) +#define REG_PIN_LCD_D14 ( 0x0264 ) +#define REG_PIN_LCD_D15 ( 0x0268 ) +#define REG_PIN_LCD_D16 ( 0x026c ) +#define REG_PIN_LCD_D17 ( 0x0270 ) +#define REG_PIN_LCD_D18 ( 0x0274 ) +#define REG_PIN_LCD_D19 ( 0x0278 ) +#define REG_PIN_LCD_D20 ( 0x027c ) +#define REG_PIN_LCD_D21 ( 0x0280 ) +#define REG_PIN_LCD_D22 ( 0x0284 ) +#define REG_PIN_LCD_D23 ( 0x0288 ) +#define REG_PIN_LCD_FMARK ( 0x028c ) +#define REG_PIN_SPI2_CSN ( 0x0290 ) +#define REG_PIN_SPI2_DO ( 0x0294 ) +#define REG_PIN_SPI2_DI ( 0x0298 ) +#define REG_PIN_SPI2_CLK ( 0x029c ) +#define REG_PIN_SCL0 ( 0x02a0 ) +#define REG_PIN_SDA0 ( 0x02a4 ) +#define REG_PIN_SCL2 ( 0x02a8 ) +#define REG_PIN_SDA2 ( 0x02ac ) +#define REG_PIN_SCL3 ( 0x02b0 ) +#define REG_PIN_SDA3 ( 0x02b4 ) +#define REG_PIN_CLK_AUX0 ( 0x02b8 ) +#define REG_PIN_IIS0DI ( 0x02bc ) +#define REG_PIN_IIS0DO ( 0x02c0 ) +#define REG_PIN_IIS0CLK ( 0x02c4 ) +#define REG_PIN_IIS0LRCK ( 0x02c8 ) +#define REG_PIN_IIS0MCK ( 0x02cc ) +#define REG_PIN_SPI0_CSN ( 0x02d0 ) +#define REG_PIN_SPI0_DO ( 0x02d4 ) +#define REG_PIN_SPI0_DI ( 0x02d8 ) +#define REG_PIN_SPI0_CLK ( 0x02dc ) +#define REG_PIN_GPIO141 ( 0x02e0 ) +#define REG_PIN_GPIO142 ( 0x02e4 ) +#define REG_PIN_MTDO ( 0x02e8 ) + +#define REG_PIN_MTDI ( 0x02ec ) +#define REG_PIN_MTCK ( 0x02f0 ) +#define REG_PIN_MTMS ( 0x02f4 ) +#define REG_PIN_MTRST_N ( 0x02f8 ) +#define REG_PIN_TRACECLK ( 0x02fc ) +#define REG_PIN_TRACECTRL ( 0x0300 ) +#define REG_PIN_TRACEDAT0 ( 0x0304 ) +#define REG_PIN_TRACEDAT1 ( 0x0308 ) +#define REG_PIN_TRACEDAT2 ( 0x030c ) +#define REG_PIN_TRACEDAT3 ( 0x0310 ) +#define REG_PIN_TRACEDAT4 ( 0x0314 ) +#define REG_PIN_TRACEDAT5 ( 0x0318 ) +#define REG_PIN_TRACEDAT6 ( 0x031c ) +#define REG_PIN_TRACEDAT7 ( 0x0320 ) +#define REG_PIN_U0TXD ( 0x0324 ) +#define REG_PIN_U0RXD ( 0x0328 ) +#define REG_PIN_U0CTS ( 0x032c ) +#define REG_PIN_U0RTS ( 0x0330 ) +#define REG_PIN_U1TXD ( 0x0334 ) +#define REG_PIN_U1RXD ( 0x0338 ) +#define REG_PIN_U2TXD ( 0x033c ) +#define REG_PIN_U2RXD ( 0x0340 ) +#define REG_PIN_U2CTS ( 0x0344 ) +#define REG_PIN_U2RTS ( 0x0348 ) +#define REG_PIN_U3TXD ( 0x034c ) +#define REG_PIN_U3RXD ( 0x0350 ) +#define REG_PIN_U3CTS ( 0x0354 ) +#define REG_PIN_U3RTS ( 0x0358 ) +#define REG_PIN_CLK_REQ1 ( 0x035c ) +#define REG_PIN_CLK_REQ2 ( 0x0360 ) +#define REG_PIN_RFSDA0 ( 0x0364 ) +#define REG_PIN_RFSCK0 ( 0x0368 ) +#define REG_PIN_RFSEN0 ( 0x036c ) +#define REG_PIN_RFCTL0 ( 0x0370 ) +#define REG_PIN_RFCTL1 ( 0x0374 ) +#define REG_PIN_RFCTL2 ( 0x0378 ) +#define REG_PIN_RFCTL3 ( 0x037c ) + +#define REG_PIN_RFCTL4 ( 0x0380 ) +#define REG_PIN_RFCTL5 ( 0x0384 ) +#define REG_PIN_RFCTL6 ( 0x0388 ) +#define REG_PIN_RFCTL7 ( 0x038c ) +#define REG_PIN_RFCTL8 ( 0x0390 ) +#define REG_PIN_RFCTL9 ( 0x0394 ) +#define REG_PIN_RFCTL10 ( 0x0398 ) +#define REG_PIN_RFCTL11 ( 0x039c ) +#define REG_PIN_RFCTL12 ( 0x03a0 ) +#define REG_PIN_RFCTL13 ( 0x03a4 ) +#define REG_PIN_RFCTL14 ( 0x03a8 ) +#define REG_PIN_RFCTL15 ( 0x03ac ) +#define REG_PIN_XTL_EN ( 0x03b0 ) +#define REG_PIN_PTEST ( 0x03b4 ) +#define REG_PIN_GPIO143 ( 0x03b8 ) +#define REG_PIN_GPIO144 ( 0x03bc ) + + +/* bits definitions for register REG_PIN_XXX */ +#define BITS_PIN_DS(_x_) ( (_x_) << 19 & (BIT(19)|BIT(20)) ) +#define BITS_PIN_DS_3(_x_) ( (_x_) << 19 & (BIT(19)|BIT(20)|BIT(21)) ) +#define BITS_PIN_DS_4(_x_) ( (_x_) << 19 & (BIT(19)|BIT(20)|BIT(21)|BIT(22)) ) +#define BIT_PIN_SLP_AP ( BIT(13) ) +#define BIT_PIN_WPU ( BIT(7) ) +#define BIT_PIN_WPD ( BIT(6) ) +#define BITS_PIN_AF(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BIT_PIN_SLP_WPU ( BIT(3) ) +#define BIT_PIN_SLP_WPD ( BIT(2) ) +#define BIT_PIN_SLP_IE ( BIT(1) ) +#define BIT_PIN_SLP_OE ( BIT(0) ) + +/* vars definitions for controller CTL_PIN */ +#define BIT_PIN_NUL ( 0 ) +#define BIT_PIN_SLP_NUL ( 0 ) +#define BIT_PIN_SLP_Z ( 0 ) + + + + + + + + + + + +#endif diff --git a/include/soc/sprd/chip_x35l64/__regs_pmu_apb_rf.h b/include/soc/sprd/chip_x35l64/__regs_pmu_apb_rf.h new file mode 100755 index 00000000..3dfcd989 --- /dev/null +++ b/include/soc/sprd/chip_x35l64/__regs_pmu_apb_rf.h @@ -0,0 +1,1236 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + + + +#ifndef __H_REGS_PMU_APB_RF_HEADFILE_H__ +#define __H_REGS_PMU_APB_RF_HEADFILE_H__ __FILE__ + +#define REGS_PMU_APB_RF + +/* registers definitions for PMU_APB_RF */ +#define REG_PMU_APB_PD_APCPU_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0000)/*PD_APCPU_TOP_CFG*/ +#define REG_PMU_APB_PD_APCPU_C0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0004)/*PD_APCPU_C0_CFG*/ +#define REG_PMU_APB_PD_APCPU_C1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0008)/*PD_APCPU_C1_CFG*/ +#define REG_PMU_APB_PD_APCPU_C2_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x000C)/*PD_APCPU_C2_CFG*/ +#define REG_PMU_APB_PD_APCPU_C3_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0010)/*PD_APCPU_C3_CFG*/ +#define REG_PMU_APB_PD_CA7_TOP_CFG REG_PMU_APB_PD_APCPU_TOP_CFG +#define REG_PMU_APB_PD_CA7_C0_CFG REG_PMU_APB_PD_APCPU_C0_CFG +#define REG_PMU_APB_PD_CA7_C1_CFG REG_PMU_APB_PD_APCPU_C1_CFG +#define REG_PMU_APB_PD_CA7_C2_CFG REG_PMU_APB_PD_APCPU_C2_CFG +#define REG_PMU_APB_PD_CA7_C3_CFG REG_PMU_APB_PD_APCPU_C3_CFG +#define REG_PMU_APB_PD_AP_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0018) +#define REG_PMU_APB_PD_MM_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x001C) +#define REG_PMU_APB_PD_GPU_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0020) +#define REG_PMU_APB_PD_CP0_ARM9_0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0024) +#define REG_PMU_APB_PD_CP0_ARM9_1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0028) +#define REG_PMU_APB_PD_CP0_HU3GE_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x002C) +#define REG_PMU_APB_PD_CP0_GSM_0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0030) +#define REG_PMU_APB_PD_CP0_GSM_1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0034) +#define REG_PMU_APB_PD_CP0_TD_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0038) +#define REG_PMU_APB_PD_CP0_CEVA_0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x003C) +#define REG_PMU_APB_PD_CP0_CEVA_1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0040) +#define REG_PMU_APB_PD_CP0_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0044) +#define REG_PMU_APB_PD_CP1_CA5_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0048) +#define REG_PMU_APB_PD_CP1_LTE_P1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x004C) +#define REG_PMU_APB_PD_CP1_LTE_P2_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0050) +#define REG_PMU_APB_PD_CP1_CEVA_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0054) +#define REG_PMU_APB_PD_CP1_COMWRAP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0058) +#define REG_PMU_APB_PD_PUB_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x005C) +#define REG_PMU_APB_AP_WAKEUP_POR_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0060) +#define REG_PMU_APB_XTL_WAIT_CNT SCI_ADDR(REGS_PMU_APB_BASE, 0x0070) +#define REG_PMU_APB_XTLBUF_WAIT_CNT SCI_ADDR(REGS_PMU_APB_BASE, 0x0074) +#define REG_PMU_APB_PLL_WAIT_CNT1 SCI_ADDR(REGS_PMU_APB_BASE, 0x0078) +#define REG_PMU_APB_PLL_WAIT_CNT2 SCI_ADDR(REGS_PMU_APB_BASE, 0x007C) +#define REG_PMU_APB_XTL0_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0080) +#define REG_PMU_APB_XTL1_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0084) +#define REG_PMU_APB_XTLBUF0_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x008C) +#define REG_PMU_APB_XTLBUF1_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0090) +#define REG_PMU_APB_MPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0094) +#define REG_PMU_APB_DPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0098) +#define REG_PMU_APB_LTEPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x009C) +#define REG_PMU_APB_TWPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00A0) +#define REG_PMU_APB_LVDSDIS_PLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00A4) +#define REG_PMU_APB_CP_SOFT_RST SCI_ADDR(REGS_PMU_APB_BASE, 0x00B0) +#define REG_PMU_APB_CP_SLP_STATUS_DBG0 SCI_ADDR(REGS_PMU_APB_BASE, 0x00B4) +#define REG_PMU_APB_PWR_STATUS0_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00BC) +#define REG_PMU_APB_PWR_STATUS1_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00C0) +#define REG_PMU_APB_PWR_STATUS2_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00C4) +#define REG_PMU_APB_SLEEP_CTRL SCI_ADDR(REGS_PMU_APB_BASE, 0x00CC) +#define REG_PMU_APB_DDR_SLEEP_CTRL SCI_ADDR(REGS_PMU_APB_BASE, 0x00D0) +#define REG_PMU_APB_SLEEP_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x00D4) +#define REG_PMU_APB_APCPU_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00E4)/*APCPU_TOP_CFG*/ +#define REG_PMU_APB_APCPU_C0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00E8)/*APCPU_C0_CFG*/ +#define REG_PMU_APB_APCPU_C1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00EC)/*APCPU_C1_CFG*/ +#define REG_PMU_APB_APCPU_C2_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00F0)/*APCPU_C2_CFG*/ +#define REG_PMU_APB_APCPU_C3_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00F4)/*APCPU_C3_CFG*/ +#define REG_PMU_APB_CA7_TOP_CFG REG_PMU_APB_APCPU_TOP_CFG +#define REG_PMU_APB_CA7_C0_CFG REG_PMU_APB_APCPU_C0_CFG +#define REG_PMU_APB_CA7_C1_CFG REG_PMU_APB_APCPU_C1_CFG +#define REG_PMU_APB_CA7_C2_CFG REG_PMU_APB_APCPU_C2_CFG +#define REG_PMU_APB_CA7_C3_CFG REG_PMU_APB_APCPU_C3_CFG +#define REG_PMU_APB_DDR_CHN_SLEEP_CTRL0 SCI_ADDR(REGS_PMU_APB_BASE, 0x00F8) +#define REG_PMU_APB_DDR_CHN_SLEEP_CTRL1 SCI_ADDR(REGS_PMU_APB_BASE, 0x00FC) +#define REG_PMU_APB_DDR_OP_MODE_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x012C) +#define REG_PMU_APB_DDR_PHY_RET_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0130) +#define REG_PMU_APB_26M_SEL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0134)/*26M_SEL_CFG*/ +#define REG_PMU_APB_R26M_SEL_CFG REG_PMU_APB_26M_SEL_CFG +#define REG_PMU_APB_BISR_DONE_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x0138) +#define REG_PMU_APB_BISR_BUSY_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x013C) +#define REG_PMU_APB_BISR_BYP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0140) +#define REG_PMU_APB_BISR_EN_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0144) +#define REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG0 SCI_ADDR(REGS_PMU_APB_BASE, 0x0148) +#define REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG1 SCI_ADDR(REGS_PMU_APB_BASE, 0x014C) +#define REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG2 SCI_ADDR(REGS_PMU_APB_BASE, 0x0150) +#define REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG3 SCI_ADDR(REGS_PMU_APB_BASE, 0x0154) +#define REG_PMU_APB_CGM_FORCE_EN_CFG0 SCI_ADDR(REGS_PMU_APB_BASE, 0x0158) +#define REG_PMU_APB_CGM_FORCE_EN_CFG1 SCI_ADDR(REGS_PMU_APB_BASE, 0x015C) +#define REG_PMU_APB_CGM_FORCE_EN_CFG2 SCI_ADDR(REGS_PMU_APB_BASE, 0x0160) +#define REG_PMU_APB_CGM_FORCE_EN_CFG3 SCI_ADDR(REGS_PMU_APB_BASE, 0x0164) +#define REG_PMU_APB_SLEEP_XTLON_CTRL SCI_ADDR(REGS_PMU_APB_BASE, 0x0168) +#define REG_PMU_APB_MEM_SLP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x016C) +#define REG_PMU_APB_MEM_SD_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0170) +#define REG_PMU_APB_APCPU_CORE_PU_LOCK SCI_ADDR(REGS_PMU_APB_BASE, 0x0174)/*APCPU_CORE_PU_LOCK*/ +#define REG_PMU_APB_CA7_CORE_PU_LOCK REG_PMU_APB_APCPU_CORE_PU_LOCK +#define REG_PMU_APB_ARM7_HOLD_CGM_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0178) +#define REG_PMU_APB_PWR_CNT_WAIT_CFG0 SCI_ADDR(REGS_PMU_APB_BASE, 0x017C) +#define REG_PMU_APB_PWR_CNT_WAIT_CFG1 SCI_ADDR(REGS_PMU_APB_BASE, 0x0180) +#define REG_PMU_APB_RC0_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0184) +#define REG_PMU_APB_RC1_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0188) +#define REG_PMU_APB_RC_CNT_WAIT_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x018C) +#define REG_PMU_APB_MEM_AUTO_SLP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0190) +#define REG_PMU_APB_MEM_AUTO_SD_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0194) +#define REG_PMU_APB_CP0_PD_SHUTDOWN_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0198) +#define REG_PMU_APB_CP1_PD_SHUTDOWN_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x019C) +#define REG_PMU_APB_WAKEUP_LOCK_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x01A0) +#define REG_PMU_APB_PD_APCPU_C0_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3000)/*PD_APCPU_C0_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_APCPU_C1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3004)/*PD_APCPU_C1_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_APCPU_C2_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3008)/*PD_APCPU_C2_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_APCPU_C3_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x300C)/*PD_APCPU_C3_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_APCPU_TOP_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3010)/*PD_APCPU_TOP_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CA7_C0_SHUTDOWN_MARK_STATUS REG_PMU_APB_PD_APCPU_C0_SHUTDOWN_MARK_STATUS +#define REG_PMU_APB_PD_CA7_C1_SHUTDOWN_MARK_STATUS REG_PMU_APB_PD_APCPU_C1_SHUTDOWN_MARK_STATUS +#define REG_PMU_APB_PD_CA7_C2_SHUTDOWN_MARK_STATUS REG_PMU_APB_PD_APCPU_C2_SHUTDOWN_MARK_STATUS +#define REG_PMU_APB_PD_CA7_C3_SHUTDOWN_MARK_STATUS REG_PMU_APB_PD_APCPU_C3_SHUTDOWN_MARK_STATUS +#define REG_PMU_APB_PD_CA7_TOP_SHUTDOWN_MARK_STATUS REG_PMU_APB_PD_APCPU_TOP_SHUTDOWN_MARK_STATUS +#define REG_PMU_APB_PD_AP_SYS_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3014) +#define REG_PMU_APB_PD_GPU_TOP_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3018) +#define REG_PMU_APB_PD_MM_TOP_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x301C) +#define REG_PMU_APB_PD_CP0_ARM9_0_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3020) +#define REG_PMU_APB_PD_CP0_ARM9_1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3024) +#define REG_PMU_APB_PD_CP0_CEVA_0_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3028) +#define REG_PMU_APB_PD_CP0_CEVA_1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x302C) +#define REG_PMU_APB_PD_CP0_GSM_0_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3030) +#define REG_PMU_APB_PD_CP0_GSM_1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3034) +#define REG_PMU_APB_PD_CP0_TD_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3038) +#define REG_PMU_APB_PD_CP0_HU3GE_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x303C) +#define REG_PMU_APB_PD_CP1_CA5_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3040) +#define REG_PMU_APB_PD_CP1_CEVA_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3044) +#define REG_PMU_APB_PD_CP1_LTE_P1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3048) +#define REG_PMU_APB_PD_CP1_LTE_P2_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x304C) +#define REG_PMU_APB_PD_CP1_COMWRAP_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3050) +#define REG_PMU_APB_PD_PUB_SYS_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3054) + + + +/* bits definitions for register REG_PMU_APB_PD_APCPU_TOP_CFG */ +#define BIT_PD_APCPU_TOP_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_PD_APCPU_TOP_STOP_EN ( BIT(27) ) +#define BIT_PD_APCPU_TOP_PWR_INT_EN ( BIT(26) ) +#define BIT_PD_APCPU_TOP_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_APCPU_TOP_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_APCPU_TOP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_APCPU_TOP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_APCPU_TOP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_PD_CA7_TOP_DBG_SHUTDOWN_EN BIT_PD_APCPU_TOP_DBG_SHUTDOWN_EN +#define BIT_PD_CA7_TOP_STOP_EN BIT_PD_APCPU_TOP_STOP_EN +#define BIT_PD_CA7_TOP_PWR_INT_EN BIT_PD_APCPU_TOP_PWR_INT_EN +#define BIT_PD_CA7_TOP_FORCE_SHUTDOWN BIT_PD_APCPU_TOP_FORCE_SHUTDOWN +#define BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN BIT_PD_APCPU_TOP_AUTO_SHUTDOWN_EN +#define BITS_PD_CA7_TOP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA7_TOP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_APCPU_C0_CFG */ +#define BIT_PD_APCPU_C0_WFI_SHUTDOWN_EN ( BIT(29) ) +#define BIT_PD_APCPU_C0_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_PD_APCPU_C0_PWR_RST_CFG ( BIT(26) ) +#define BIT_PD_APCPU_C0_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_APCPU_C0_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_APCPU_C0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_APCPU_C0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_APCPU_C0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_PD_CA7_C0_WFI_SHUTDOWN_EN BIT_PD_APCPU_C0_WFI_SHUTDOWN_EN +#define BIT_PD_CA7_C0_DBG_SHUTDOWN_EN BIT_PD_APCPU_C0_DBG_SHUTDOWN_EN +#define BIT_PD_CA7_C0_PWR_RST_CFG BIT_PD_APCPU_C0_PWR_RST_CFG +#define BIT_PD_CA7_C0_FORCE_SHUTDOWN BIT_PD_APCPU_C0_FORCE_SHUTDOWN +#define BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN BIT_PD_APCPU_C0_AUTO_SHUTDOWN_EN +#define BITS_PD_CA7_C0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA7_C0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_APCPU_C1_CFG */ +#define BIT_PD_APCPU_C1_WFI_SHUTDOWN_EN ( BIT(29) ) +#define BIT_PD_APCPU_C1_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_PD_APCPU_C1_PWR_RST_CFG ( BIT(26) ) +#define BIT_PD_APCPU_C1_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_APCPU_C1_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_APCPU_C1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_APCPU_C1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_APCPU_C1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_PD_CA7_C1_WFI_SHUTDOWN_EN BIT_PD_APCPU_C1_WFI_SHUTDOWN_EN +#define BIT_PD_CA7_C1_DBG_SHUTDOWN_EN BIT_PD_APCPU_C1_DBG_SHUTDOWN_EN +#define BIT_PD_CA7_C1_PWR_RST_CFG BIT_PD_APCPU_C1_PWR_RST_CFG +#define BIT_PD_CA7_C1_FORCE_SHUTDOWN BIT_PD_APCPU_C1_FORCE_SHUTDOWN +#define BIT_PD_CA7_C1_AUTO_SHUTDOWN_EN BIT_PD_APCPU_C1_AUTO_SHUTDOWN_EN +#define BITS_PD_CA7_C1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA7_C1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_APCPU_C2_CFG */ +#define BIT_PD_APCPU_C2_WFI_SHUTDOWN_EN ( BIT(29) ) +#define BIT_PD_APCPU_C2_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_PD_APCPU_C2_PWR_RST_CFG ( BIT(26) ) +#define BIT_PD_APCPU_C2_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_APCPU_C2_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_APCPU_C2_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_APCPU_C2_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_APCPU_C2_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_PD_CA7_C2_WFI_SHUTDOWN_EN BIT_PD_APCPU_C2_WFI_SHUTDOWN_EN +#define BIT_PD_CA7_C2_DBG_SHUTDOWN_EN BIT_PD_APCPU_C2_DBG_SHUTDOWN_EN +#define BIT_PD_CA7_C2_PWR_RST_CFG BIT_PD_APCPU_C2_PWR_RST_CFG +#define BIT_PD_CA7_C2_FORCE_SHUTDOWN BIT_PD_APCPU_C2_FORCE_SHUTDOWN +#define BIT_PD_CA7_C2_AUTO_SHUTDOWN_EN BIT_PD_APCPU_C2_AUTO_SHUTDOWN_EN +#define BITS_PD_CA7_C2_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA7_C2_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_APCPU_C3_CFG */ +#define BIT_PD_APCPU_C3_WFI_SHUTDOWN_EN ( BIT(29) ) +#define BIT_PD_APCPU_C3_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_PD_APCPU_C3_PWR_RST_CFG ( BIT(26) ) +#define BIT_PD_APCPU_C3_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_APCPU_C3_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_APCPU_C3_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_APCPU_C3_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_APCPU_C3_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_PD_CA7_C3_WFI_SHUTDOWN_EN BIT_PD_APCPU_C3_WFI_SHUTDOWN_EN +#define BIT_PD_CA7_C3_DBG_SHUTDOWN_EN BIT_PD_APCPU_C3_DBG_SHUTDOWN_EN +#define BIT_PD_CA7_C3_PWR_RST_CFG BIT_PD_APCPU_C3_PWR_RST_CFG +#define BIT_PD_CA7_C3_FORCE_SHUTDOWN BIT_PD_APCPU_C3_FORCE_SHUTDOWN +#define BIT_PD_CA7_C3_AUTO_SHUTDOWN_EN BIT_PD_APCPU_C3_AUTO_SHUTDOWN_EN +#define BITS_PD_CA7_C3_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA7_C3_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_AP_SYS_CFG */ +#define BIT_PD_AP_SYS_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_AP_SYS_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_AP_SYS_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_MM_TOP_CFG */ +#define BIT_PD_MM_TOP_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_MM_TOP_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_MM_TOP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_MM_TOP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_GPU_TOP_CFG */ +#define BIT_PD_GPU_TOP_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_GPU_TOP_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_GPU_TOP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_GPU_TOP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_0_CFG */ +#define BIT_PD_CP0_ARM9_0_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_ARM9_0_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_ARM9_0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_ARM9_0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_ARM9_0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_1_CFG */ +#define BIT_PD_CP0_ARM9_1_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_ARM9_1_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_ARM9_1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_ARM9_1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_ARM9_1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_HU3GE_CFG */ +#define BIT_PD_CP0_HU3GE_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_HU3GE_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_HU3GE_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_HU3GE_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_HU3GE_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_GSM_0_CFG */ +#define BIT_PD_CP0_GSM_0_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_GSM_0_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_GSM_0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_GSM_0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_GSM_0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_GSM_1_CFG */ +#define BIT_PD_CP0_GSM_1_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_GSM_1_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_GSM_1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_GSM_1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_GSM_1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_TD_CFG */ +#define BIT_PD_CP0_TD_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_TD_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_TD_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_TD_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_TD_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_CEVA_0_CFG */ +#define BIT_PD_CP0_CEVA_0_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_CEVA_0_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_CEVA_0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_CEVA_0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_CEVA_0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_CEVA_1_CFG */ +#define BIT_PD_CP0_CEVA_1_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_CEVA_1_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_CEVA_1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_CEVA_1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_CEVA_1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_SYS_CFG */ + +/* bits definitions for register REG_PMU_APB_PD_CP1_CA5_CFG */ +#define BIT_PD_CP1_CA5_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP1_CA5_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP1_CA5_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_CA5_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_CA5_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_LTE_P1_CFG */ +#define BIT_PD_CP1_LTE_P1_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP1_LTE_P1_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP1_LTE_P1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_LTE_P1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_LTE_P1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_LTE_P2_CFG */ +#define BIT_PD_CP1_LTE_P2_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP1_LTE_P2_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP1_LTE_P2_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_LTE_P2_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_LTE_P2_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_CEVA_CFG */ +#define BIT_PD_CP1_CEVA_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP1_CEVA_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP1_CEVA_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_CEVA_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_CEVA_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_COMWRAP_CFG */ +#define BIT_PD_CP1_COMWRAP_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP1_COMWRAP_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP1_COMWRAP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_COMWRAP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_COMWRAP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_PUB_SYS_CFG */ +#define BIT_PD_PUB_SYS_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_PUB_SYS_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_PUB_SYS_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_AP_WAKEUP_POR_CFG */ +#define BIT_AP_WAKEUP_POR_N ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_XTL_WAIT_CNT */ +#define BITS_XTL1_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_XTL0_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_XTLBUF_WAIT_CNT */ +#define BITS_XTLBUF1_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_XTLBUF0_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PLL_WAIT_CNT1 */ +#define BITS_LTEPLL_WAIT_CNT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_TWPLL_WAIT_CNT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DPLL_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_MPLL_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PLL_WAIT_CNT2 */ +#define BITS_LVDSDIS_PLL_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_XTL0_REL_CFG */ +#define BIT_XTL0_ARM7_SEL ( BIT(5) ) +#define BIT_XTL0_VCP1_SEL ( BIT(4) ) +#define BIT_XTL0_VCP0_SEL ( BIT(3) ) +#define BIT_XTL0_CP1_SEL ( BIT(2) ) +#define BIT_XTL0_CP0_SEL ( BIT(1) ) +#define BIT_XTL0_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_XTL1_REL_CFG */ +#define BIT_XTL1_ARM7_SEL ( BIT(5) ) +#define BIT_XTL1_VCP1_SEL ( BIT(4) ) +#define BIT_XTL1_VCP0_SEL ( BIT(3) ) +#define BIT_XTL1_CP1_SEL ( BIT(2) ) +#define BIT_XTL1_CP0_SEL ( BIT(1) ) +#define BIT_XTL1_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_XTLBUF0_REL_CFG */ +#define BIT_XTLBUF0_ARM7_SEL ( BIT(5) ) +#define BIT_XTLBUF0_VCP1_SEL ( BIT(4) ) +#define BIT_XTLBUF0_VCP0_SEL ( BIT(3) ) +#define BIT_XTLBUF0_CP1_SEL ( BIT(2) ) +#define BIT_XTLBUF0_CP0_SEL ( BIT(1) ) +#define BIT_XTLBUF0_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_XTLBUF1_REL_CFG */ +#define BIT_XTLBUF1_ARM7_SEL ( BIT(5) ) +#define BIT_XTLBUF1_VCP1_SEL ( BIT(4) ) +#define BIT_XTLBUF1_VCP0_SEL ( BIT(3) ) +#define BIT_XTLBUF1_CP1_SEL ( BIT(2) ) +#define BIT_XTLBUF1_CP0_SEL ( BIT(1) ) +#define BIT_XTLBUF1_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_MPLL_REL_CFG */ +#define BIT_MPLL_REF_SEL ( BIT(8) ) +#define BIT_MPLL_ARM7_SEL ( BIT(5) ) +#define BIT_MPLL_VCP1_SEL ( BIT(4) ) +#define BIT_MPLL_VCP0_SEL ( BIT(3) ) +#define BIT_MPLL_CP1_SEL ( BIT(2) ) +#define BIT_MPLL_CP0_SEL ( BIT(1) ) +#define BIT_MPLL_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_DPLL_REL_CFG */ +#define BIT_DPLL_REF_SEL ( BIT(8) ) +#define BIT_DPLL_ARM7_SEL ( BIT(5) ) +#define BIT_DPLL_VCP1_SEL ( BIT(4) ) +#define BIT_DPLL_VCP0_SEL ( BIT(3) ) +#define BIT_DPLL_CP1_SEL ( BIT(2) ) +#define BIT_DPLL_CP0_SEL ( BIT(1) ) +#define BIT_DPLL_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_LTEPLL_REL_CFG */ +#define BIT_LTEPLL_REF_SEL ( BIT(8) ) +#define BIT_LTEPLL_ARM7_SEL ( BIT(5) ) +#define BIT_LTEPLL_VCP1_SEL ( BIT(4) ) +#define BIT_LTEPLL_VCP0_SEL ( BIT(3) ) +#define BIT_LTEPLL_CP1_SEL ( BIT(2) ) +#define BIT_LTEPLL_CP0_SEL ( BIT(1) ) +#define BIT_LTEPLL_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_TWPLL_REL_CFG */ +#define BIT_TWPLL_REF_SEL ( BIT(8) ) +#define BIT_TWPLL_ARM7_SEL ( BIT(5) ) +#define BIT_TWPLL_VCP1_SEL ( BIT(4) ) +#define BIT_TWPLL_VCP0_SEL ( BIT(3) ) +#define BIT_TWPLL_CP1_SEL ( BIT(2) ) +#define BIT_TWPLL_CP0_SEL ( BIT(1) ) +#define BIT_TWPLL_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_LVDSDIS_PLL_REL_CFG */ +#define BIT_LVDSDIS_PLL_REF_SEL ( BIT(8) ) +#define BIT_LVDSDIS_PLL_ARM7_SEL ( BIT(5) ) +#define BIT_LVDSDIS_PLL_VCP1_SEL ( BIT(4) ) +#define BIT_LVDSDIS_PLL_VCP0_SEL ( BIT(3) ) +#define BIT_LVDSDIS_PLL_CP1_SEL ( BIT(2) ) +#define BIT_LVDSDIS_PLL_CP0_SEL ( BIT(1) ) +#define BIT_LVDSDIS_PLL_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CP_SOFT_RST */ +#define BIT_ARM7_SOFT_RST ( BIT(8) ) +#define BIT_PUB_SOFT_RST ( BIT(6) ) +#define BIT_AP_SOFT_RST ( BIT(5) ) +#define BIT_PMU_APB_GPU_SOFT_RST ( BIT(4) ) +#define BIT_MM_SOFT_RST ( BIT(3) ) +#define BIT_CP1_SOFT_RST ( BIT(1) ) +#define BIT_CP0_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CP_SLP_STATUS_DBG0 */ +#define BITS_CP1_DEEP_SLP_DBG(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_CP0_DEEP_SLP_DBG(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_PMU_APB_PWR_STATUS0_DBG */ +#define BITS_PD_MM_TOP_STATE(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_PD_GPU_TOP_STATE(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_PD_AP_SYS_STATE(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_APCPU_C3_STATE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_PD_APCPU_C2_STATE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_APCPU_C1_STATE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_PD_APCPU_C0_STATE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_PD_APCPU_TOP_STATE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) +#define BITS_PD_CA7_C3_STATE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_PD_CA7_C2_STATE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA7_C1_STATE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_PD_CA7_C0_STATE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_PD_CA7_TOP_STATE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + + +/* bits definitions for register REG_PMU_APB_PWR_STATUS1_DBG */ +#define BITS_PD_CP0_CEVA_1_STATE(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_PD_CP0_CEVA_0_STATE(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_PD_CP0_GSM_0_STATE(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_GSM_1_STATE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_PD_CP0_HU3GE_STATE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_ARM9_1_STATE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_PD_CP0_ARM9_0_STATE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_PD_CP0_TD_STATE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PWR_STATUS2_DBG */ +#define BITS_PD_PUB_SYS_STATE(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_PD_CP1_COMWRAP_STATE(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_LTE_P2_STATE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_PD_CP1_LTE_P1_STATE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_CEVA_STATE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_PD_CP1_CA5_STATE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_SLEEP_CTRL */ +#define BIT_VCP1_FORCE_LIGHT_SLEEP ( BIT(28) ) +#define BIT_VCP0_FORCE_LIGHT_SLEEP ( BIT(27) ) +#define BIT_CP1_FORCE_LIGHT_SLEEP ( BIT(26) ) +#define BIT_CP0_FORCE_LIGHT_SLEEP ( BIT(25) ) +#define BIT_AP_FORCE_LIGHT_SLEEP ( BIT(24) ) +#define BIT_ARM7_FORCE_DEEP_SLEEP ( BIT(21) ) +#define BIT_VCP1_FORCE_DEEP_SLEEP ( BIT(20) ) +#define BIT_VCP0_FORCE_DEEP_SLEEP ( BIT(19) ) +#define BIT_CP1_FORCE_DEEP_SLEEP ( BIT(18) ) +#define BIT_CP0_FORCE_DEEP_SLEEP ( BIT(17) ) +#define BIT_AP_FORCE_DEEP_SLEEP ( BIT(16) ) +#define BIT_VCP1_LIGHT_SLEEP ( BIT(12) ) +#define BIT_VCP0_LIGHT_SLEEP ( BIT(11) ) +#define BIT_CP1_LIGHT_SLEEP ( BIT(10) ) +#define BIT_CP0_LIGHT_SLEEP ( BIT(9) ) +#define BIT_AP_LIGHT_SLEEP ( BIT(8) ) +#define BIT_VCP1_DEEP_SLEEP ( BIT(4) ) +#define BIT_VCP0_DEEP_SLEEP ( BIT(3) ) +#define BIT_CP1_DEEP_SLEEP ( BIT(2) ) +#define BIT_CP0_DEEP_SLEEP ( BIT(1) ) +#define BIT_AP_DEEP_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_DDR_SLEEP_CTRL */ +#define BIT_BUSY_TRANSFER_HWDATA_SEL ( BIT(16) ) +#define BIT_DDR_PUBL_APB_SOFT_RST ( BIT(12) ) +#define BIT_DDR_UMCTL_APB_SOFT_RST ( BIT(11) ) +#define BIT_DDR_PUBL_SOFT_RST ( BIT(10) ) +#define BIT_DDR_PHY_SOFT_RST ( BIT(8) ) +#define BIT_DDR_PHY_AUTO_GATE_EN ( BIT(6) ) +#define BIT_DDR_PUBL_AUTO_GATE_EN ( BIT(5) ) +#define BIT_DDR_UMCTL_AUTO_GATE_EN ( BIT(4) ) +#define BIT_DDR_PHY_EB ( BIT(2) ) +#define BIT_DDR_UMCTL_EB ( BIT(1) ) +#define BIT_DDR_PUBL_EB ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_SLEEP_STATUS */ +#define BITS_ARM7_SLP_STATUS(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_VCP1_SLP_STATUS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_VCP0_SLP_STATUS(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_CP1_SLP_STATUS(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CP0_SLP_STATUS(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_AP_SLP_STATUS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_CA7_TOP_CFG */ +#define BIT_APCPU_L2RSTDISABLE ( BIT(0) ) +#define BIT_CA7_L2RSTDISABLE BIT_APCPU_L2RSTDISABLE + +/* bits definitions for register REG_PMU_APB_APCPU_C0_CFG */ +#define BIT_APCPU_VINITHI_C0 ( BIT(0) ) +#define BIT_CA7_VINITHI_C0 BIT_APCPU_VINITHI_C0 + + +/* bits definitions for register REG_PMU_APB_APCPU_C1_CFG */ +#define BIT_APCPU_VINITHI_C1 ( BIT(0) ) +#define BIT_CA7_VINITHI_C1 BIT_APCPU_VINITHI_C1 + +/* bits definitions for register REG_PMU_APB_APCPU_C2_CFG */ +#define BIT_APCPU_VINITHI_C2 ( BIT(0) ) +#define BIT_CA7_VINITHI_C2 BIT_APCPU_VINITHI_C2 + +/* bits definitions for register REG_PMU_APB_APCPU_C3_CFG */ +#define BIT_APCPU_VINITHI_C3 ( BIT(0) ) +#define BIT_CA7_VINITHI_C3 BIT_APCPU_VINITHI_C3 + +/* bits definitions for register REG_PMU_APB_DDR_CHN_SLEEP_CTRL0 */ +#define BIT_DDR_CTRL_AXI_LP_EN ( BIT(31) ) +#define BIT_DDR_CTRL_CGM_SEL ( BIT(30) ) +#define BIT_DDR_CHN9_AXI_LP_EN ( BIT(25) ) +#define BIT_DDR_CHN8_AXI_LP_EN ( BIT(24) ) +#define BIT_DDR_CHN7_AXI_LP_EN ( BIT(23) ) +#define BIT_DDR_CHN6_AXI_LP_EN ( BIT(22) ) +#define BIT_DDR_CHN5_AXI_LP_EN ( BIT(21) ) +#define BIT_DDR_CHN4_AXI_LP_EN ( BIT(20) ) +#define BIT_DDR_CHN3_AXI_LP_EN ( BIT(19) ) +#define BIT_DDR_CHN2_AXI_LP_EN ( BIT(18) ) +#define BIT_DDR_CHN1_AXI_LP_EN ( BIT(17) ) +#define BIT_DDR_CHN0_AXI_LP_EN ( BIT(16) ) +#define BIT_DDR_CHN9_CGM_SEL ( BIT(9) ) +#define BIT_DDR_CHN8_CGM_SEL ( BIT(8) ) +#define BIT_DDR_CHN7_CGM_SEL ( BIT(7) ) +#define BIT_DDR_CHN6_CGM_SEL ( BIT(6) ) +#define BIT_DDR_CHN5_CGM_SEL ( BIT(5) ) +#define BIT_DDR_CHN4_CGM_SEL ( BIT(4) ) +#define BIT_DDR_CHN3_CGM_SEL ( BIT(3) ) +#define BIT_DDR_CHN2_CGM_SEL ( BIT(2) ) +#define BIT_DDR_CHN1_CGM_SEL ( BIT(1) ) +#define BIT_DDR_CHN0_CGM_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_DDR_CHN_SLEEP_CTRL1 */ +#define BIT_DDR_CHN9_AXI_STOP_SEL ( BIT(9) ) +#define BIT_DDR_CHN8_AXI_STOP_SEL ( BIT(8) ) +#define BIT_DDR_CHN7_AXI_STOP_SEL ( BIT(7) ) +#define BIT_DDR_CHN6_AXI_STOP_SEL ( BIT(6) ) +#define BIT_DDR_CHN5_AXI_STOP_SEL ( BIT(5) ) +#define BIT_DDR_CHN4_AXI_STOP_SEL ( BIT(4) ) +#define BIT_DDR_CHN3_AXI_STOP_SEL ( BIT(3) ) +#define BIT_DDR_CHN2_AXI_STOP_SEL ( BIT(2) ) +#define BIT_DDR_CHN1_AXI_STOP_SEL ( BIT(1) ) +#define BIT_DDR_CHN0_AXI_STOP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_DDR_OP_MODE_CFG */ +#define BIT_DDR_OPERATE_MODE_BUSY ( BIT(28) ) +#define BIT_DDR_PUBL_RET_EN ( BIT(27) ) +#define BIT_DDR_PHY_ISO_RST_EN ( BIT(26) ) +#define BIT_DDR_UMCTL_RET_EN ( BIT(25) ) +#define BIT_DDR_PHY_AUTO_RET_EN ( BIT(24) ) +#define BITS_DDR_OPERATE_MODE_CNT_LMT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DDR_OPERATE_MODE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_DDR_OPERATE_MODE_IDLE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_PMU_APB_DDR_PHY_RET_CFG */ +#define BIT_DDR_UMCTL_SOFT_RST ( BIT(16) ) +#define BIT_DDR_PHY_RET_EN ( BIT(0) ) +#define BIT_DDR_PHY_CKE_RET_EN BIT_DDR_PHY_RET_EN + +/* bits definitions for register REG_PMU_APB_26M_SEL_CFG */ +#define BIT_AON_RC_4M_SEL ( BIT(8) ) +#define BIT_GGE_26M_SEL ( BIT(6) ) +#define BIT_PUB_26M_SEL ( BIT(5) ) +#define BIT_AON_26M_SEL ( BIT(4) ) +#define BIT_CP1_26M_SEL ( BIT(2) ) +#define BIT_CP0_26M_SEL ( BIT(1) ) +#define BIT_AP_26M_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_BISR_DONE_STATUS */ +#define BIT_PD_CP1_COMWRAP_BISR_DONE ( BIT(21) ) +#define BIT_PD_CP1_LTE_P2_BISR_DONE ( BIT(20) ) +#define BIT_PD_CP1_LTE_P1_BISR_DONE ( BIT(19) ) +#define BIT_PD_CP1_CEVA_BISR_DONE ( BIT(18) ) +#define BIT_PD_CP1_CA5_BISR_DONE ( BIT(17) ) +#define BIT_PD_CP0_HU3GE_BISR_DONE ( BIT(15) ) +#define BIT_PD_CP0_TD_BISR_DONE ( BIT(14) ) +#define BIT_PD_CP0_GSM_1_BISR_DONE ( BIT(13) ) +#define BIT_PD_CP0_GSM_0_BISR_DONE ( BIT(12) ) +#define BIT_PD_CP0_CEVA_1_BISR_DONE ( BIT(11) ) +#define BIT_PD_CP0_CEVA_0_BISR_DONE ( BIT(10) ) +#define BIT_PD_CP0_ARM9_1_BISR_DONE ( BIT(9) ) +#define BIT_PD_CP0_ARM9_0_BISR_DONE ( BIT(8) ) +#define BIT_PD_MM_TOP_BISR_DONE ( BIT(7) ) +#define BIT_PD_GPU_TOP_BISR_DONE ( BIT(6) ) +#define BIT_PD_AP_SYS_BISR_DONE ( BIT(5) ) +#define BIT_PD_APCPU_TOP_BISR_DONE ( BIT(4) ) +#define BIT_PD_APCPU_C3_BISR_DONE ( BIT(3) ) +#define BIT_PD_APCPU_C2_BISR_DONE ( BIT(2) ) +#define BIT_PD_APCPU_C1_BISR_DONE ( BIT(1) ) +#define BIT_PD_APCPU_C0_BISR_DONE ( BIT(0) ) +#define BIT_PD_CA7_TOP_BISR_DONE BIT_PD_APCPU_TOP_BISR_DONE +#define BIT_PD_CA7_C3_BISR_DONE BIT_PD_APCPU_C3_BISR_DONE +#define BIT_PD_CA7_C2_BISR_DONE BIT_PD_APCPU_C2_BISR_DONE +#define BIT_PD_CA7_C1_BISR_DONE BIT_PD_APCPU_C1_BISR_DONE +#define BIT_PD_CA7_C0_BISR_DONE BIT_PD_APCPU_C0_BISR_DONE + +/* bits definitions for register REG_PMU_APB_BISR_BUSY_STATUS */ +#define BIT_PD_CP1_COMWRAP_BISR_BUSY ( BIT(21) ) +#define BIT_PD_CP1_LTE_P2_BISR_BUSY ( BIT(20) ) +#define BIT_PD_CP1_LTE_P1_BISR_BUSY ( BIT(19) ) +#define BIT_PD_CP1_CEVA_BISR_BUSY ( BIT(18) ) +#define BIT_PD_CP1_CA5_BISR_BUSY ( BIT(17) ) +#define BIT_PD_CP0_HU3GE_BISR_BUSY ( BIT(15) ) +#define BIT_PD_CP0_TD_BISR_BUSY ( BIT(14) ) +#define BIT_PD_CP0_GSM_1_BISR_BUSY ( BIT(13) ) +#define BIT_PD_CP0_GSM_0_BISR_BUSY ( BIT(12) ) +#define BIT_PD_CP0_CEVA_1_BISR_BUSY ( BIT(11) ) +#define BIT_PD_CP0_CEVA_0_BISR_BUSY ( BIT(10) ) +#define BIT_PD_CP0_ARM9_1_BISR_BUSY ( BIT(9) ) +#define BIT_PD_CP0_ARM9_0_BISR_BUSY ( BIT(8) ) +#define BIT_PD_MM_TOP_BISR_BUSY ( BIT(7) ) +#define BIT_PD_GPU_TOP_BISR_BUSY ( BIT(6) ) +#define BIT_PD_AP_SYS_BISR_BUSY ( BIT(5) ) +#define BIT_PD_APCPU_TOP_BISR_BUSY ( BIT(4) ) +#define BIT_PD_APCPU_C3_BISR_BUSY ( BIT(3) ) +#define BIT_PD_APCPU_C2_BISR_BUSY ( BIT(2) ) +#define BIT_PD_APCPU_C1_BISR_BUSY ( BIT(1) ) +#define BIT_PD_APCPU_C0_BISR_BUSY ( BIT(0) ) +#define BIT_PD_CA7_TOP_BISR_BUSY BIT_PD_APCPU_TOP_BISR_BUSY +#define BIT_PD_CA7_C3_BISR_BUSY BIT_PD_APCPU_C3_BISR_BUSY +#define BIT_PD_CA7_C2_BISR_BUSY BIT_PD_APCPU_C2_BISR_BUSY +#define BIT_PD_CA7_C1_BISR_BUSY BIT_PD_APCPU_C1_BISR_BUSY +#define BIT_PD_CA7_C0_BISR_BUSY BIT_PD_APCPU_C0_BISR_BUSY + +/* bits definitions for register REG_PMU_APB_BISR_BYP_CFG */ +#define BIT_PD_CP1_COMWRAP_BISR_FORCE_BYP ( BIT(21) ) +#define BIT_PD_CP1_LTE_P2_BISR_FORCE_BYP ( BIT(20) ) +#define BIT_PD_CP1_LTE_P1_BISR_FORCE_BYP ( BIT(19) ) +#define BIT_PD_CP1_CEVA_BISR_FORCE_BYP ( BIT(18) ) +#define BIT_PD_CP1_CA5_BISR_FORCE_BYP ( BIT(17) ) +#define BIT_PD_CP0_HU3GE_BISR_FORCE_BYP ( BIT(15) ) +#define BIT_PD_CP0_TD_BISR_FORCE_BYP ( BIT(14) ) +#define BIT_PD_CP0_GSM_1_BISR_FORCE_BYP ( BIT(13) ) +#define BIT_PD_CP0_GSM_0_BISR_FORCE_BYP ( BIT(12) ) +#define BIT_PD_CP0_CEVA_1_BISR_FORCE_BYP ( BIT(11) ) +#define BIT_PD_CP0_CEVA_0_BISR_FORCE_BYP ( BIT(10) ) +#define BIT_PD_CP0_ARM9_1_BISR_FORCE_BYP ( BIT(9) ) +#define BIT_PD_CP0_ARM9_0_BISR_FORCE_BYP ( BIT(8) ) +#define BIT_PD_MM_TOP_BISR_FORCE_BYP ( BIT(7) ) +#define BIT_PD_GPU_TOP_BISR_FORCE_BYP ( BIT(6) ) +#define BIT_PD_AP_SYS_BISR_FORCE_BYP ( BIT(5) ) +#define BIT_PD_APCPU_TOP_BISR_FORCE_BYP ( BIT(4) ) +#define BIT_PD_APCPU_C3_BISR_FORCE_BYP ( BIT(3) ) +#define BIT_PD_APCPU_C2_BISR_FORCE_BYP ( BIT(2) ) +#define BIT_PD_APCPU_C1_BISR_FORCE_BYP ( BIT(1) ) +#define BIT_PD_APCPU_C0_BISR_FORCE_BYP ( BIT(0) ) +#define BIT_PD_CA7_TOP_BISR_FORCE_BYP BIT_PD_APCPU_TOP_BISR_FORCE_BYP +#define BIT_PD_CA7_C3_BISR_FORCE_BYP BIT_PD_APCPU_C3_BISR_FORCE_BYP +#define BIT_PD_CA7_C2_BISR_FORCE_BYP BIT_PD_APCPU_C2_BISR_FORCE_BYP +#define BIT_PD_CA7_C1_BISR_FORCE_BYP BIT_PD_APCPU_C1_BISR_FORCE_BYP +#define BIT_PD_CA7_C0_BISR_FORCE_BYP BIT_PD_APCPU_C0_BISR_FORCE_BYP + +/* bits definitions for register REG_PMU_APB_BISR_EN_CFG */ +#define BIT_PD_CP1_COMWRAP_BISR_FORCE_EN ( BIT(21) ) +#define BIT_PD_CP1_LTE_P2_BISR_FORCE_EN ( BIT(20) ) +#define BIT_PD_CP1_LTE_P1_BISR_FORCE_EN ( BIT(19) ) +#define BIT_PD_CP1_CEVA_BISR_FORCE_EN ( BIT(18) ) +#define BIT_PD_CP1_CA5_BISR_FORCE_EN ( BIT(17) ) +#define BIT_PD_CP0_HU3GE_BISR_FORCE_EN ( BIT(15) ) +#define BIT_PD_CP0_TD_BISR_FORCE_EN ( BIT(14) ) +#define BIT_PD_CP0_GSM_1_BISR_FORCE_EN ( BIT(13) ) +#define BIT_PD_CP0_GSM_0_BISR_FORCE_EN ( BIT(12) ) +#define BIT_PD_CP0_CEVA_1_BISR_FORCE_EN ( BIT(11) ) +#define BIT_PD_CP0_CEVA_0_BISR_FORCE_EN ( BIT(10) ) +#define BIT_PD_CP0_ARM9_1_BISR_FORCE_EN ( BIT(9) ) +#define BIT_PD_CP0_ARM9_0_BISR_FORCE_EN ( BIT(8) ) +#define BIT_PD_MM_TOP_BISR_FORCE_EN ( BIT(7) ) +#define BIT_PD_GPU_TOP_BISR_FORCE_EN ( BIT(6) ) +#define BIT_PD_AP_SYS_BISR_FORCE_EN ( BIT(5) ) +#define BIT_PD_APCPU_TOP_BISR_FORCE_EN ( BIT(4) ) +#define BIT_PD_APCPU_C3_BISR_FORCE_EN ( BIT(3) ) +#define BIT_PD_APCPU_C2_BISR_FORCE_EN ( BIT(2) ) +#define BIT_PD_APCPU_C1_BISR_FORCE_EN ( BIT(1) ) +#define BIT_PD_APCPU_C0_BISR_FORCE_EN ( BIT(0) ) +#define BIT_PD_CA7_TOP_BISR_FORCE_EN BIT_PD_APCPU_TOP_BISR_FORCE_EN +#define BIT_PD_CA7_C3_BISR_FORCE_EN BIT_PD_APCPU_C3_BISR_FORCE_EN +#define BIT_PD_CA7_C2_BISR_FORCE_EN BIT_PD_APCPU_C2_BISR_FORCE_EN +#define BIT_PD_CA7_C1_BISR_FORCE_EN BIT_PD_APCPU_C1_BISR_FORCE_EN +#define BIT_PD_CA7_C0_BISR_FORCE_EN BIT_PD_APCPU_C0_BISR_FORCE_EN + +/* bits definitions for register REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG0 */ +#define BITS_CGM_AUTO_GATE_SEL_CFG0(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG1 */ + +#define BIT_CGM_TWPLL_128M_MM_AUTO_GATE_SEL_CFG1 (BIT(31)) +#define BIT_CGM_TWPLL_153M6_MM_AUTO_GATE_SEL (BIT(30)) +#define BIT_CGM_TWPLL_192M_MM_AUTO_GATE_SEL ( BIT(29) ) +#define BIT_CGM_TWPLL_256M_MM_AUTO_GATE_SEL ( BIT(28) ) +#define BIT_CGM_TWPLL_307M2_MM_AUTO_GATE_SEL ( BIT(27) ) +#define BIT_CGM_26M_MM_AUTO_GATE_SEL ( BIT(26) ) +#define BIT_CGM_TWPLL_12M_AP_AUTO_GATE_SEL ( BIT(25) ) +#define BIT_CGM_TWPLL_24M_AP_AUTO_GATE_SEL ( BIT(24) ) +#define BIT_CGM_TWPLL_48M_AP_AUTO_GATE_SEL ( BIT(23) ) +#define BIT_CGM_TWPLL_51M2_AP_AUTO_GATE_SEL ( BIT(22) ) +#define BIT_CGM_TWPLL_64M_AP_AUTO_GATE_SEL ( BIT(21) ) +#define BIT_CGM_TWPLL_76M8_AP_AUTO_GATE_SEL ( BIT(20) ) +#define BIT_CGM_TWPLL_96M_AP_AUTO_GATE_SEL ( BIT(19) ) +#define BIT_CGM_TWPLL_128M_AP_AUTO_GATE_SEL ( BIT(18) ) +#define BIT_CGM_TWPLL_153M6_AP_AUTO_GATE_SEL ( BIT(17) ) +#define BIT_CGM_TWPLL_192M_AP_AUTO_GATE_SEL ( BIT(16) ) +#define BIT_CGM_TWPLL_256M_AP_AUTO_GATE_SEL ( BIT(15) ) +#define BIT_CGM_TWPLL_307M2_AP_AUTO_GATE_SEL ( BIT(14) ) +#define BIT_CGM_TWPLL_384M_AP_AUTO_GATE_SEL ( BIT(13) ) +#define BIT_CGM_TWPLL_512M_AP_AUTO_GATE_SEL ( BIT(12) ) +#define BIT_CGM_TWPLL_768M_AP_AUTO_GATE_SEL ( BIT(11) ) +#define BIT_CGM_LTEPLL_AP_AUTO_GATE_SEL ( BIT(10) ) +#define BIT_CGM_TWPLL_AP_AUTO_GATE_SEL ( BIT(9) ) +#define BIT_CGM_DPLL_AP_AUTO_GATE_SEL ( BIT(8) ) +#define BIT_CGM_MPLL_AP_AUTO_GATE_SEL ( BIT(7) ) +#define BIT_CGM_26M_AP_AUTO_GATE_SEL ( BIT(6) ) +#define BIT_RC1_2M_AUTO_GATE_SEL ( BIT(5) ) +#define BIT_RC0_2M_AUTO_GATE_SEL ( BIT(4) ) +#define BIT_AON_1M_AUTO_GATE_SEL ( BIT(3) ) +#define BIT_AON_2M_AUTO_GATE_SEL ( BIT(2) ) +#define BIT_AON_13M_AUTO_GATE_SEL ( BIT(1) ) +#define BIT_LTEPLL_DIV_30M72_AUTO_GATE_SEL ( BIT(0) ) +#define BITS_CGM_AUTO_GATE_SEL_CFG1(_X_) (_X_) +/* bits definitions for register REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG2 */ +#define BIT_CGM_LTEPLL_245M76_CP1_AUTO_GATE_SEL ( BIT(31) ) +#define BIT_CGM_LTEPLL_307M2_CP1_AUTO_GATE_SEL ( BIT(30) ) +#define BIT_CGM_LTEPLL_614M4_CP1_AUTO_GATE_SEL ( BIT(29) ) +#define BIT_CGM_26M_CP1_AUTO_GATE_SEL ( BIT(28) ) +#define BIT_CGM_TWPLL_5M12_CP0_AUTO_GATE_SEL ( BIT(27) ) +#define BIT_CGM_TWPLL_10M24_CP0_AUTO_GATE_SEL ( BIT(26) ) +#define BIT_CGM_TWPLL_51M2_CP0_AUTO_GATE_SEL ( BIT(25) ) +#define BIT_CGM_TWPLL_76M8_CP0_AUTO_GATE_SEL ( BIT(24) ) +#define BIT_CGM_TWPLL_153M6_CP0_AUTO_GATE_SEL ( BIT(23) ) +#define BIT_CGM_TWPLL_48M_CP0_AUTO_GATE_SEL ( BIT(22) ) +#define BIT_CGM_TWPLL_96M_CP0_AUTO_GATE_SEL ( BIT(21) ) +#define BIT_CGM_TWPLL_192M_CP0_AUTO_GATE_SEL ( BIT(20) ) +#define BIT_CGM_TWPLL_64M_CP0_AUTO_GATE_SEL ( BIT(19) ) +#define BIT_CGM_TWPLL_102M4_CP0_AUTO_GATE_SEL ( BIT(18) ) +#define BIT_CGM_TWPLL_128M_CP0_AUTO_GATE_SEL ( BIT(17) ) +#define BIT_CGM_TWPLL_256M_CP0_AUTO_GATE_SEL ( BIT(16) ) +#define BIT_CGM_TWPLL_219M_CP0_AUTO_GATE_SEL ( BIT(15) ) +#define BIT_CGM_TWPLL_219M4_CP0_AUTO_GATE_SEL ( BIT(14) ) +#define BIT_CGM_TWPLL_307M2_CP0_AUTO_GATE_SEL ( BIT(13) ) +#define BIT_CGM_TWPLL_512M_CP0_AUTO_GATE_SEL ( BIT(12) ) +#define BIT_CGM_26M_CP0_AUTO_GATE_SEL ( BIT(11) ) +#define BIT_CGM_TWPLL_153M6_GPU_AUTO_GATE_SEL ( BIT(10) ) +#define BIT_CGM_TWPLL_192M_GPU_AUTO_GATE_SEL ( BIT(9) ) +#define BIT_CGM_TWPLL_256M_GPU_AUTO_GATE_SEL ( BIT(8) ) +#define BIT_CGM_TWPLL_307M2_GPU_AUTO_GATE_SEL ( BIT(7) ) +#define BIT_CGM_TWPLL_384M_GPU_AUTO_GATE_SEL ( BIT(6) ) +#define BIT_CGM_TWPLL_512M_GPU_AUTO_GATE_SEL ( BIT(5) ) +#define BIT_CGM_TWPLL_24M_MM_AUTO_GATE_SEL ( BIT(4) ) +#define BIT_CGM_TWPLL_48M_MM_AUTO_GATE_SEL ( BIT(3) ) +#define BIT_CGM_TWPLL_64M_MM_AUTO_GATE_SEL ( BIT(2) ) +#define BIT_CGM_TWPLL_76M8_MM_AUTO_GATE_SEL ( BIT(1) ) +#define BIT_CGM_TWPLL_96M_MM_AUTO_GATE_SEL ( BIT(0) ) +#define BITS_CGM_AUTO_GATE_SEL_CFG2(_X_) (_X_) +/* bits definitions for register REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG3 */ +#define BIT_CA5_TOP_AUTO_GATE_SEL ( BIT(19) ) +#define BIT_CA7_TOP_AUTO_GATE_SEL ( BIT(18) ) +#define BIT_CGM_TWPLL_48M_CP1_AUTO_GATE_SEL ( BIT(17) ) +#define BIT_CGM_TWPLL_51M2_CP1_AUTO_GATE_SEL ( BIT(16) ) +#define BIT_CGM_TWPLL_64M_CP1_AUTO_GATE_SEL ( BIT(15) ) +#define BIT_CGM_TWPLL_76M8_CP1_AUTO_GATE_SEL ( BIT(14) ) +#define BIT_CGM_TWPLL_96M_CP1_AUTO_GATE_SEL ( BIT(13) ) +#define BIT_CGM_TWPLL_128M_CP1_AUTO_GATE_SEL ( BIT(12) ) +#define BIT_CGM_TWPLL_153M6_CP1_AUTO_GATE_SEL ( BIT(11) ) +#define BIT_CGM_TWPLL_192M_CP1_AUTO_GATE_SEL ( BIT(10) ) +#define BIT_CGM_TWPLL_256M_CP1_AUTO_GATE_SEL ( BIT(9) ) +#define BIT_CGM_TWPLL_512M_CP1_AUTO_GATE_SEL ( BIT(8) ) +#define BIT_CGM_TWPLL_768M_CP1_AUTO_GATE_SEL ( BIT(7) ) +#define BIT_CGM_LTEPLL_30M72_CP1_AUTO_GATE_SEL ( BIT(6) ) +#define BIT_CGM_LTEPLL_61M44_CP1_AUTO_GATE_SEL ( BIT(5) ) +#define BIT_CGM_LTEPLL_68M26_CP1_AUTO_GATE_SEL ( BIT(4) ) +#define BIT_CGM_LTEPLL_102M4_CP1_AUTO_GATE_SEL ( BIT(3) ) +#define BIT_CGM_LTEPLL_122M88_CP1_AUTO_GATE_SEL ( BIT(2) ) +#define BIT_CGM_LTEPLL_153M6_CP1_AUTO_GATE_SEL ( BIT(1) ) +#define BIT_CGM_LTEPLL_204M8_CP1_AUTO_GATE_SEL ( BIT(0) ) +#define BITS_CGM_AUTO_GATE_SEL_CFG3(_X_) (_X_) +/* bits definitions for register REG_PMU_APB_CGM_FORCE_EN_CFG0 */ +#define BIT_CGM_TWPLL_512M_GPU_FORCE_EN ( BIT(31) ) +#define BIT_CGM_TWPLL_24M_MM_FORCE_EN ( BIT(30) ) +#define BIT_CGM_TWPLL_48M_MM_FORCE_EN ( BIT(29) ) +#define BIT_CGM_TWPLL_64M_MM_FORCE_EN ( BIT(28) ) +#define BIT_CGM_TWPLL_76M8_MM_FORCE_EN ( BIT(27) ) +#define BIT_CGM_TWPLL_96M_MM_FORCE_EN ( BIT(26) ) +#define BIT_CGM_TWPLL_128M_MM_FORCE_EN_CFG1 ( BIT(25) ) +#define BIT_CGM_TWPLL_153M6_MM_FORCE_EN ( BIT(24) ) +#define BIT_CGM_TWPLL_192M_MM_FORCE_EN ( BIT(23) ) +#define BIT_CGM_TWPLL_256M_MM_FORCE_EN ( BIT(22) ) +#define BIT_CGM_TWPLL_307M2_MM_FORCE_EN ( BIT(21) ) +#define BIT_CGM_26M_MM_FORCE_EN ( BIT(20) ) +#define BIT_CGM_TWPLL_12M_AP_FORCE_EN ( BIT(19) ) +#define BIT_CGM_TWPLL_24M_AP_FORCE_EN ( BIT(18) ) +#define BIT_CGM_TWPLL_48M_AP_FORCE_EN ( BIT(17) ) +#define BIT_CGM_TWPLL_51M2_AP_FORCE_EN ( BIT(16) ) +#define BIT_CGM_TWPLL_64M_AP_FORCE_EN ( BIT(15) ) +#define BIT_CGM_TWPLL_76M8_AP_FORCE_EN ( BIT(14) ) +#define BIT_CGM_TWPLL_96M_AP_FORCE_EN ( BIT(13) ) +#define BIT_CGM_TWPLL_128M_AP_FORCE_EN ( BIT(12) ) +#define BIT_CGM_TWPLL_153M6_AP_FORCE_EN ( BIT(11) ) +#define BIT_CGM_TWPLL_192M_AP_FORCE_EN ( BIT(10) ) +#define BIT_CGM_TWPLL_256M_AP_FORCE_EN ( BIT(9) ) +#define BIT_CGM_TWPLL_307M2_AP_FORCE_EN ( BIT(8) ) +#define BIT_CGM_TWPLL_384M_AP_FORCE_EN ( BIT(7) ) +#define BIT_CGM_TWPLL_512M_AP_FORCE_EN ( BIT(6) ) +#define BIT_CGM_TWPLL_768M_AP_FORCE_EN ( BIT(5) ) +#define BIT_CGM_LTEPLL_AP_FORCE_EN ( BIT(4) ) +#define BIT_CGM_TWPLL_AP_FORCE_EN ( BIT(3) ) +#define BIT_CGM_DPLL_AP_FORCE_EN ( BIT(2) ) +#define BIT_CGM_MPLL_AP_FORCE_EN ( BIT(1) ) +#define BIT_CGM_26M_AP_FORCE_EN ( BIT(0) ) +#define BITS_CGM_FORCE_EN_CFG0(_X_) (_X_) +/* bits definitions for register REG_PMU_APB_CGM_FORCE_EN_CFG1 */ +#define BIT_CGM_LTEPLL_61M44_CP1_FORCE_EN ( BIT(31) ) +#define BIT_CGM_LTEPLL_68M26_CP1_FORCE_EN ( BIT(30) ) +#define BIT_CGM_LTEPLL_102M4_CP1_FORCE_EN ( BIT(29) ) +#define BIT_CGM_LTEPLL_122M88_CP1_FORCE_EN ( BIT(28) ) +#define BIT_CGM_LTEPLL_153M6_CP1_FORCE_EN ( BIT(27) ) +#define BIT_CGM_LTEPLL_204M8_CP1_FORCE_EN ( BIT(26) ) +#define BIT_CGM_LTEPLL_245M76_CP1_FORCE_EN ( BIT(25) ) +#define BIT_CGM_LTEPLL_307M2_CP1_FORCE_EN ( BIT(24) ) +#define BIT_CGM_LTEPLL_614M4_CP1_FORCE_EN ( BIT(23) ) +#define BIT_CGM_26M_CP1_FORCE_EN ( BIT(22) ) +#define BIT_CGM_TWPLL_5M12_CP0_FORCE_EN ( BIT(21) ) +#define BIT_CGM_TWPLL_10M24_CP0_FORCE_EN ( BIT(20) ) +#define BIT_CGM_TWPLL_51M2_CP0_FORCE_EN ( BIT(19) ) +#define BIT_CGM_TWPLL_76M8_CP0_FORCE_EN ( BIT(18) ) +#define BIT_CGM_TWPLL_153M6_CP0_FORCE_EN ( BIT(17) ) +#define BIT_CGM_TWPLL_48M_CP0_FORCE_EN ( BIT(16) ) +#define BIT_CGM_TWPLL_96M_CP0_FORCE_EN ( BIT(15) ) +#define BIT_CGM_TWPLL_192M_CP0_FORCE_EN ( BIT(14) ) +#define BIT_CGM_TWPLL_64M_CP0_FORCE_EN ( BIT(13) ) +#define BIT_CGM_TWPLL_102M4_CP0_FORCE_EN ( BIT(12) ) +#define BIT_CGM_TWPLL_128M_CP0_FORCE_EN ( BIT(11) ) +#define BIT_CGM_TWPLL_256M_CP0_FORCE_EN ( BIT(10) ) +#define BIT_CGM_TWPLL_219M_CP0_FORCE_EN ( BIT(9) ) +#define BIT_CGM_TWPLL_219M4_CP0_FORCE_EN ( BIT(8) ) +#define BIT_CGM_TWPLL_307M2_CP0_FORCE_EN ( BIT(7) ) +#define BIT_CGM_TWPLL_512M_CP0_FORCE_EN ( BIT(6) ) +#define BIT_CGM_26M_CP0_FORCE_EN ( BIT(5) ) +#define BIT_CGM_TWPLL_153M6_GPU_FORCE_EN ( BIT(4) ) +#define BIT_CGM_TWPLL_192M_GPU_FORCE_EN ( BIT(3) ) +#define BIT_CGM_TWPLL_256M_GPU_FORCE_EN ( BIT(2) ) +#define BIT_CGM_TWPLL_307M2_GPU_FORCE_EN ( BIT(1) ) +#define BIT_CGM_TWPLL_384M_GPU_FORCE_EN ( BIT(0) ) +#define BITS_CGM_FORCE_EN_CFG1(_X_) (_X_) +/* bits definitions for register REG_PMU_APB_CGM_FORCE_EN_CFG2 */ +#define BIT_TWPLL_DIV_38M4_FORCE_EN ( BIT(31) ) +#define BIT_TWPLL_DIV_76M8_FORCE_EN ( BIT(30) ) +#define BIT_TWPLL_DIV_51M2_FORCE_EN ( BIT(29) ) +#define BIT_TWPLL_DIV_153M6_FORCE_EN ( BIT(28) ) +#define BIT_TWPLL_DIV_64M_FORCE_EN ( BIT(27) ) +#define BIT_TWPLL_DIV_128M_FORCE_EN ( BIT(26) ) +#define BIT_TWPLL_DIV_256M_FORCE_EN ( BIT(25) ) +#define BIT_TWPLL_DIV_12M_FORCE_EN ( BIT(24) ) +#define BIT_TWPLL_DIV_24M_FORCE_EN ( BIT(23) ) +#define BIT_TWPLL_DIV_48M_FORCE_EN ( BIT(22) ) +#define BIT_TWPLL_DIV_96M_FORCE_EN ( BIT(21) ) +#define BIT_TWPLL_DIV_102M4_FORCE_EN ( BIT(20) ) +#define BIT_TWPLL_DIV_192M_FORCE_EN ( BIT(19) ) +#define BIT_TWPLL_DIV_219M4_FORCE_EN ( BIT(18) ) +#define BIT_TWPLL_DIV_307M2_FORCE_EN ( BIT(17) ) +#define BIT_TWPLL_DIV_384M_FORCE_EN ( BIT(16) ) +#define BIT_TWPLL_DIV_512M_FORCE_EN ( BIT(15) ) +#define BIT_TWPLL_DIV_768M_FORCE_EN ( BIT(14) ) +#define BIT_DPLL_DIV_33M_FORCE_EN ( BIT(13) ) +#define BIT_MPLL_DIV_50M_FORCE_EN ( BIT(12) ) +#define BIT_CGM_TWPLL_48M_CP1_FORCE_EN ( BIT(11) ) +#define BIT_CGM_TWPLL_51M2_CP1_FORCE_EN ( BIT(10) ) +#define BIT_CGM_TWPLL_64M_CP1_FORCE_EN ( BIT(9) ) +#define BIT_CGM_TWPLL_76M8_CP1_FORCE_EN ( BIT(8) ) +#define BIT_CGM_TWPLL_96M_CP1_FORCE_EN ( BIT(7) ) +#define BIT_CGM_TWPLL_128M_CP1_FORCE_EN ( BIT(6) ) +#define BIT_CGM_TWPLL_153M6_CP1_FORCE_EN ( BIT(5) ) +#define BIT_CGM_TWPLL_192M_CP1_FORCE_EN ( BIT(4) ) +#define BIT_CGM_TWPLL_256M_CP1_FORCE_EN ( BIT(3) ) +#define BIT_CGM_TWPLL_512M_CP1_FORCE_EN ( BIT(2) ) +#define BIT_CGM_TWPLL_768M_CP1_FORCE_EN ( BIT(1) ) +#define BIT_CGM_LTEPLL_30M72_CP1_FORCE_EN ( BIT(0) ) +#define BITS_CGM_FORCE_EN_CFG2(_X_) (_X_) +/* bits definitions for register REG_PMU_APB_CGM_FORCE_EN_CFG3 */ +#define BIT_RC1_2M_FORCE_EN ( BIT(17) ) +#define BIT_RC0_2M_FORCE_EN ( BIT(16) ) +#define BIT_AON_1M_FORCE_EN ( BIT(15) ) +#define BIT_AON_2M_FORCE_EN ( BIT(14) ) +#define BIT_AON_13M_FORCE_EN ( BIT(13) ) +#define BIT_LTEPLL_DIV_30M72_FORCE_EN ( BIT(12) ) +#define BIT_LTEPLL_DIV_61M44_FORCE_EN ( BIT(11) ) +#define BIT_LTEPLL_DIV_122M88_FORCE_EN ( BIT(10) ) +#define BIT_LTEPLL_DIV_245M76_FORCE_EN ( BIT(9) ) +#define BIT_LTEPLL_DIV_68M26_FORCE_EN ( BIT(8) ) +#define BIT_LTEPLL_DIV_102M4_FORCE_EN ( BIT(7) ) +#define BIT_LTEPLL_DIV_204M8_FORCE_EN ( BIT(6) ) +#define BIT_LTEPLL_DIV_409M6_FORCE_EN ( BIT(5) ) +#define BIT_LTEPLL_DIV_153M6_FORCE_EN ( BIT(4) ) +#define BIT_LTEPLL_DIV_307M2_FORCE_EN ( BIT(3) ) +#define BIT_LTEPLL_DIV_614M4_FORCE_EN ( BIT(2) ) +#define BIT_TWPLL_DIV_5M12_FORCE_EN ( BIT(1) ) +#define BIT_TWPLL_DIV_10M24_FORCE_EN ( BIT(0) ) +#define BITS_CGM_FORCE_EN_CFG3(_X_) (_X_) +/* bits definitions for register REG_PMU_APB_SLEEP_XTLON_CTRL */ +#define BIT_ARM7_SLEEP_XTL_ON ( BIT(5) ) +#define BIT_VCP1_SLEEP_XTL_ON ( BIT(4) ) +#define BIT_VCP0_SLEEP_XTL_ON ( BIT(3) ) +#define BIT_CP1_SLEEP_XTL_ON ( BIT(2) ) +#define BIT_CP0_SLEEP_XTL_ON ( BIT(1) ) +#define BIT_AP_SLEEP_XTL_ON ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_MEM_SLP_CFG */ +#define BIT_ARM7_MEM_SLP_UART ( BIT(28) ) +#define BIT_ARM7_MEM_SLP_IMC ( BIT(27) ) +#define BIT_AON_MEM_SLP_IMC ( BIT(26) ) +#define BIT_AON_MEM_SLP_DMA ( BIT(25) ) +#define BIT_AON_MEM_SLP_VBC ( BIT(24) ) +#define BIT_AON_MEM_SLP_AUD ( BIT(23) ) +#define BIT_AON_MEM_SLP_FM ( BIT(22) ) +#define BIT_CP0_GGE_DSP_MEM_SLP_RFT ( BIT(21) ) +#define BIT_CP0_GGE_DSP_MEM_SLP_DMA ( BIT(20) ) +#define BIT_CP0_GGE_DSP_MEM_SLP_SHM ( BIT(19) ) +#define BIT_CP0_GGE_DSP_MEM_SLP_STC ( BIT(18) ) +#define BIT_CP0_W_MEM_SLP_UART1 ( BIT(17) ) +#define BIT_CP0_W_MEM_SLP_UART0 ( BIT(16) ) +#define BIT_CP0_W_MEM_SLP_IRAM ( BIT(15) ) +#define BIT_CP0_W_MEM_SLP_PERIF ( BIT(14) ) +#define BIT_CP0_DSP_MEM_SLP_DMA ( BIT(13) ) +#define BIT_CP0_DSP_MEM_SLP_SHM ( BIT(12) ) +#define BIT_CP0_DSP_MEM_SLP_RFT ( BIT(11) ) +#define BIT_CP0_DSP_MEM_SLP_STC ( BIT(10) ) +#define BIT_CP0_ARM_MEM_SLP_IIS3 ( BIT(9) ) +#define BIT_CP0_ARM_MEM_SLP_IIS2 ( BIT(8) ) +#define BIT_CP0_ARM_MEM_SLP_IIS1 ( BIT(7) ) +#define BIT_CP0_ARM_MEM_SLP_IIS0 ( BIT(6) ) +#define BIT_CP0_ARM_MEM_SLP_UART2 ( BIT(5) ) +#define BIT_CP0_ARM_MEM_SLP_UART1 ( BIT(4) ) +#define BIT_CP0_ARM_MEM_SLP_UART0 ( BIT(3) ) +#define BIT_CP0_ARM_MEM_SLP_EPT ( BIT(2) ) +#define BIT_CP0_ARM_MEM_SLP_LZMA ( BIT(1) ) +#define BIT_CP0_ARM_MEM_SLP_DMA ( BIT(0) ) +#define BITS_MEM_SLP_CFG(_X_) (_X_) +/* bits definitions for register REG_PMU_APB_MEM_SD_CFG */ +#define BIT_ARM7_MEM_SD_UART ( BIT(28) ) +#define BIT_ARM7_MEM_SD_IMC ( BIT(27) ) +#define BIT_AON_MEM_SD_IMC ( BIT(26) ) +#define BIT_AON_MEM_SD_DMA ( BIT(25) ) +#define BIT_AON_MEM_SD_VBC ( BIT(24) ) +#define BIT_AON_MEM_SD_AUD ( BIT(23) ) +#define BIT_AON_MEM_SD_FM ( BIT(22) ) +#define BIT_CP0_GGE_DSP_MEM_SD_RFT ( BIT(21) ) +#define BIT_CP0_GGE_DSP_MEM_SD_DMA ( BIT(20) ) +#define BIT_CP0_GGE_DSP_MEM_SD_SHM ( BIT(19) ) +#define BIT_CP0_GGE_DSP_MEM_SD_STC ( BIT(18) ) +#define BIT_CP0_W_MEM_SD_UART1 ( BIT(17) ) +#define BIT_CP0_W_MEM_SD_UART0 ( BIT(16) ) +#define BIT_CP0_W_MEM_SD_IRAM ( BIT(15) ) +#define BIT_CP0_W_MEM_SD_PERIF ( BIT(14) ) +#define BIT_CP0_DSP_MEM_SD_DMA ( BIT(13) ) +#define BIT_CP0_DSP_MEM_SD_SHM ( BIT(12) ) +#define BIT_CP0_DSP_MEM_SD_RFT ( BIT(11) ) +#define BIT_CP0_DSP_MEM_SD_STC ( BIT(10) ) +#define BIT_CP0_ARM_MEM_SD_IIS3 ( BIT(9) ) +#define BIT_CP0_ARM_MEM_SD_IIS2 ( BIT(8) ) +#define BIT_CP0_ARM_MEM_SD_IIS1 ( BIT(7) ) +#define BIT_CP0_ARM_MEM_SD_IIS0 ( BIT(6) ) +#define BIT_CP0_ARM_MEM_SD_UART2 ( BIT(5) ) +#define BIT_CP0_ARM_MEM_SD_UART1 ( BIT(4) ) +#define BIT_CP0_ARM_MEM_SD_UART0 ( BIT(3) ) +#define BIT_CP0_ARM_MEM_SD_EPT ( BIT(2) ) +#define BIT_CP0_ARM_MEM_SD_LZMA ( BIT(1) ) +#define BIT_CP0_ARM_MEM_SD_DMA ( BIT(0) ) +#define BITS_MEM_SD_CFG(_X_) (_X_) +/* bits definitions for register REG_PMU_APB_APCPU_CORE_PU_LOCK */ +#define BIT_APCPU_C3_GIC_WAKEUP_EN ( BIT(11) ) +#define BIT_APCPU_C2_GIC_WAKEUP_EN ( BIT(10) ) +#define BIT_APCPU_C1_GIC_WAKEUP_EN ( BIT(9) ) +#define BIT_APCPU_C0_GIC_WAKEUP_EN ( BIT(8) ) +#define BIT_PMU_APB_APCPU_C3_PU_LOCK ( BIT(3) ) +#define BIT_PMU_APB_APCPU_C2_PU_LOCK ( BIT(2) ) +#define BIT_PMU_APB_APCPU_C1_PU_LOCK ( BIT(1) ) +#define BIT_PMU_APB_APCPU_C0_PU_LOCK ( BIT(0) ) +/* bits definitions for register REG_PMU_APB_CA7_CORE_PU_LOCK */ +#define BIT_CA7_C3_GIC_WAKEUP_EN BIT_APCPU_C3_GIC_WAKEUP_EN +#define BIT_CA7_C2_GIC_WAKEUP_EN BIT_APCPU_C2_GIC_WAKEUP_EN +#define BIT_CA7_C1_GIC_WAKEUP_EN BIT_APCPU_C1_GIC_WAKEUP_EN +#define BIT_CA7_C0_GIC_WAKEUP_EN BIT_APCPU_C0_GIC_WAKEUP_EN +#define BIT_PMU_APB_CA7_C3_PU_LOCK BIT_PMU_APB_APCPU_C3_PU_LOCK +#define BIT_PMU_APB_CA7_C2_PU_LOCK BIT_PMU_APB_APCPU_C2_PU_LOCK +#define BIT_PMU_APB_CA7_C1_PU_LOCK BIT_PMU_APB_APCPU_C1_PU_LOCK +#define BIT_PMU_APB_CA7_C0_PU_LOCK BIT_PMU_APB_APCPU_C0_PU_LOCK +/* bits definitions for register REG_PMU_APB_ARM7_HOLD_CGM_EN */ +#define BIT_PD_CP1_CEVA_CGM_HOLD_EN ( BIT(10) ) +#define BIT_PD_CP1_CA5_CGM_HOLD_EN ( BIT(9) ) +#define BIT_PD_CP0_CEVA_1_CGM_HOLD_EN ( BIT(8) ) +#define BIT_PD_CP0_CEVA_0_CGM_HOLD_EN ( BIT(7) ) +#define BIT_PD_CP0_ARM9_1_CGM_HOLD_EN ( BIT(6) ) +#define BIT_PD_CP0_ARM9_0_CGM_HOLD_EN ( BIT(5) ) +#define BIT_PD_APCPU_TOP_CMG_HOLD_EN ( BIT(4) ) +#define BIT_PD_APCPU_C3_CMG_HOLD_EN ( BIT(3) ) +#define BIT_PD_APCPU_C2_CMG_HOLD_EN ( BIT(2) ) +#define BIT_PD_APCPU_C1_CMG_HOLD_EN ( BIT(1) ) +#define BIT_PD_APCPU_C0_CMG_HOLD_EN ( BIT(0) ) +#define BIT_PD_CA7_TOP_CMG_HOLD_EN BIT_PD_APCPU_TOP_CMG_HOLD_EN +#define BIT_PD_CA7_C3_CMG_HOLD_EN BIT_PD_APCPU_C3_CMG_HOLD_EN +#define BIT_PD_CA7_C2_CMG_HOLD_EN BIT_PD_APCPU_C2_CMG_HOLD_EN +#define BIT_PD_CA7_C1_CMG_HOLD_EN BIT_PD_APCPU_C1_CMG_HOLD_EN +#define BIT_PD_CA7_C0_CMG_HOLD_EN BIT_PD_APCPU_C0_CMG_HOLD_EN + +/* bits definitions for register REG_PMU_APB_PWR_CNT_WAIT_CFG0 */ +#define BITS_VCP0_PWR_WAIT_CNT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_CP1_PWR_WAIT_CNT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_CP0_PWR_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_AP_PWR_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PWR_CNT_WAIT_CFG1 */ +#define BITS_ARM7_PWR_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_VCP1_PWR_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_RC0_REL_CFG */ +#define BIT_RC0_ARM7_SEL ( BIT(5) ) +#define BIT_RC0_VCP1_SEL ( BIT(4) ) +#define BIT_RC0_VCP0_SEL ( BIT(3) ) +#define BIT_RC0_CP1_SEL ( BIT(2) ) +#define BIT_RC0_CP0_SEL ( BIT(1) ) +#define BIT_RC0_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_RC1_REL_CFG */ +#define BIT_RC1_ARM7_SEL ( BIT(5) ) +#define BIT_RC1_VCP1_SEL ( BIT(4) ) +#define BIT_RC1_VCP0_SEL ( BIT(3) ) +#define BIT_RC1_CP1_SEL ( BIT(2) ) +#define BIT_RC1_CP0_SEL ( BIT(1) ) +#define BIT_RC1_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_RC_CNT_WAIT_CFG */ +#define BITS_RC1_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_RC0_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_MEM_AUTO_SLP_CFG */ +#define BITS_MEM_AUTO_SLP_EN(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_MEM_AUTO_SD_CFG */ +#define BITS_MEM_AUTO_SD_EN(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CP0_PD_SHUTDOWN_CFG */ +#define BIT_PD_CP0_HU3GE_VCP1_SEL ( BIT(20) ) +#define BIT_PD_CP0_TD_VCP1_SEL ( BIT(19) ) +#define BIT_PD_CP0_GSM_0_VCP1_SEL ( BIT(18) ) +#define BIT_PD_CP0_CEVA_0_VCP1_SEL ( BIT(17) ) +#define BIT_PD_CP0_ARM9_1_VCP1_SEL ( BIT(16) ) +#define BIT_PD_CP0_ARM9_0_VCP0_SEL ( BIT(8) ) +#define BIT_PD_CP0_HU3GE_CP0_SEL ( BIT(5) ) +#define BIT_PD_CP0_TD_CP0_SEL ( BIT(4) ) +#define BIT_PD_CP0_GSM_0_CP0_SEL ( BIT(3) ) +#define BIT_PD_CP0_CEVA_0_CP0_SEL ( BIT(2) ) +#define BIT_PD_CP0_ARM9_1_CP0_SEL ( BIT(1) ) +#define BIT_PD_CP0_ARM9_0_CP0_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CP1_PD_SHUTDOWN_CFG */ +#define BIT_PD_CP1_COMWRAP_VCP1_SEL ( BIT(20) ) +#define BIT_PD_CP1_CEVA_VCP1_SEL ( BIT(19) ) +#define BIT_PD_CP1_LTE_P2_VCP1_SEL ( BIT(18) ) +#define BIT_PD_CP1_LTE_P1_VCP1_SEL ( BIT(17) ) +#define BIT_PD_CP1_CA5_VCP1_SEL ( BIT(16) ) +#define BIT_PD_CP1_COMWRAP_CP1_SEL ( BIT(4) ) +#define BIT_PD_CP1_CEVA_CP1_SEL ( BIT(3) ) +#define BIT_PD_CP1_LTE_P2_CP1_SEL ( BIT(2) ) +#define BIT_PD_CP1_LTE_P1_CP1_SEL ( BIT(1) ) +#define BIT_PD_CP1_CA5_CP1_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_WAKEUP_LOCK_EN */ +#define BIT_VCP1_SYS_WAKEUP_LOCK_EN ( BIT(26) ) +#define BIT_VCP0_SYS_WAKEUP_LOCK_EN ( BIT(25) ) +#define BIT_CP1_SYS_WAKEUP_LOCK_EN ( BIT(24) ) +#define BIT_CP0_SYS_WAKEUP_LOCK_EN ( BIT(23) ) +#define BIT_AP_SYS_WAKEUP_LOCK_EN ( BIT(22) ) +#define BIT_PD_PUB_SYS_WAKEUP_LOCK_EN ( BIT(21) ) +#define BIT_PD_CP1_COMWRAP_WAKEUP_LOCK_EN ( BIT(20) ) +#define BIT_PD_CP1_CEVA_WAKEUP_LOCK_EN ( BIT(19) ) +#define BIT_PD_CP1_LTE_P2_WAKEUP_LOCK_EN ( BIT(18) ) +#define BIT_PD_CP1_LTE_P1_WAKEUP_LOCK_EN ( BIT(17) ) +#define BIT_PD_CP1_CA5_WAKEUP_LOCK_EN ( BIT(16) ) +#define BIT_PD_CP0_CEVA_1_WAKEUP_LOCK_EN ( BIT(15) ) +#define BIT_PD_CP0_CEVA_0_WAKEUP_LOCK_EN ( BIT(14) ) +#define BIT_PD_CP0_TD_WAKEUP_LOCK_EN ( BIT(13) ) +#define BIT_PD_CP0_GSM_1_WAKEUP_LOCK_EN ( BIT(12) ) +#define BIT_PD_CP0_GSM_0_WAKEUP_LOCK_EN ( BIT(11) ) +#define BIT_PD_CP0_HU3GE_WAKEUP_LOCK_EN ( BIT(10) ) +#define BIT_PD_CP0_ARM9_1_WAKEUP_LOCK_EN ( BIT(9) ) +#define BIT_PD_CP0_ARM9_0_WAKEUP_LOCK_EN ( BIT(8) ) +#define BIT_PD_MM_TOP_WAKEUP_LOCK_EN ( BIT(7) ) +#define BIT_PD_GPU_TOP_WAKEUP_LOCK_EN ( BIT(6) ) +#define BIT_PD_AP_SYS_WAKEUP_LOCK_EN ( BIT(5) ) +#define BIT_PD_APCPU_TOP_WAKEUP_LOCK_EN ( BIT(4) ) +#define BIT_PD_APCPU_C3_WAKEUP_LOCK_EN ( BIT(3) ) +#define BIT_PD_APCPU_C2_WAKEUP_LOCK_EN ( BIT(2) ) +#define BIT_PD_APCPU_C1_WAKEUP_LOCK_EN ( BIT(1) ) +#define BIT_PD_APCPU_C0_WAKEUP_LOCK_EN ( BIT(0) ) +#define BIT_PD_CA7_TOP_WAKEUP_LOCK_EN BIT_PD_APCPU_TOP_WAKEUP_LOCK_EN +#define BIT_PD_CA7_C3_WAKEUP_LOCK_EN BIT_PD_APCPU_C3_WAKEUP_LOCK_EN +#define BIT_PD_CA7_C2_WAKEUP_LOCK_EN BIT_PD_APCPU_C2_WAKEUP_LOCK_EN +#define BIT_PD_CA7_C1_WAKEUP_LOCK_EN BIT_PD_APCPU_C1_WAKEUP_LOCK_EN +#define BIT_PD_CA7_C0_WAKEUP_LOCK_EN BIT_PD_APCPU_C0_WAKEUP_LOCK_EN + +/* bits definitions for register REG_PMU_APB_PD_APCPU_C0_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_APCPU_C0_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) +#define BITS_PD_CA7_C0_SHUTDOWN_MARK(_X_) BITS_PD_APCPU_C0_SHUTDOWN_MARK(_X_) + +/* bits definitions for register REG_PMU_APB_PD_APCPU_C1_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_APCPU_C1_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) +#define BITS_PD_CA7_C1_SHUTDOWN_MARK(_X_) BITS_PD_APCPU_C1_SHUTDOWN_MARK(_X_) + +/* bits definitions for register REG_PMU_APB_PD_APCPU_C2_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_APCPU_C2_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) +#define BITS_PD_CA7_C2_SHUTDOWN_MARK(_X_) BITS_PD_APCPU_C2_SHUTDOWN_MARK(_X_) + +/* bits definitions for register REG_PMU_APB_PD_APCPU_C3_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_APCPU_C3_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) +#define BITS_PD_CA7_C3_SHUTDOWN_MARK(_X_) BITS_PD_APCPU_C3_SHUTDOWN_MARK(_X_) + +/* bits definitions for register REG_PMU_APB_PD_APCPU_TOP_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_APCPU_TOP_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) +#define BITS_PD_CA7_TOP_SHUTDOWN_MARK(_X_) BITS_PD_APCPU_TOP_SHUTDOWN_MARK(_X_) +/* bits definitions for register REG_PMU_APB_PD_AP_SYS_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_AP_SYS_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_GPU_TOP_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_GPU_TOP_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_MM_TOP_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_MM_TOP_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_0_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_ARM9_0_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_1_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_ARM9_1_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_CEVA_0_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_CEVA_0_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_CEVA_1_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_CEVA_1_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_GSM_0_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_GSM_0_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_GSM_1_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_GSM_1_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_TD_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_TD_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_HU3GE_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_HU3GE_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_CA5_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP1_CA5_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_CEVA_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP1_CEVA_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_LTE_P1_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP1_LTE_P1_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_LTE_P2_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP1_LTE_P2_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_COMWRAP_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP1_COMWRAP_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_PUB_SYS_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_PUB_SYS_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +#endif diff --git a/include/soc/sprd/chip_x35l64/__regs_pub_apb.h b/include/soc/sprd/chip_x35l64/__regs_pub_apb.h new file mode 100644 index 00000000..3f0109f2 --- /dev/null +++ b/include/soc/sprd/chip_x35l64/__regs_pub_apb.h @@ -0,0 +1,477 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_PUB_APB_HEADFILE_H__ +#define __H_REGS_PUB_APB_HEADFILE_H__ __FILE__ + +#define REGS_PUB_APB + +/* registers definitions for PUB_APB */ +#define REG_PUB_APB_BUSMON_CNT_START SCI_ADDR(REGS_PUB_APB_BASE, 0x0000) +#define REG_PUB_APB_BUSMON_CFG SCI_ADDR(REGS_PUB_APB_BASE, 0x0004) +#define REG_PUB_APB_DDR_EB SCI_ADDR(REGS_PUB_APB_BASE, 0x0008) +#define REG_PUB_APB_DDR_SOFT_RST SCI_ADDR(REGS_PUB_APB_BASE, 0x000C) +#define REG_PUB_APB_DDR_QOS_CFG1 SCI_ADDR(REGS_PUB_APB_BASE, 0x0010) +#define REG_PUB_APB_DDR_QOS_CFG2 SCI_ADDR(REGS_PUB_APB_BASE, 0x0014) +#define REG_PUB_APB_DDR_QOS_CFG3 SCI_ADDR(REGS_PUB_APB_BASE, 0x0018) +#define REG_PUB_APB_DDR_MRR_STATUS SCI_ADDR(REGS_PUB_APB_BASE, 0x001C) +#define REG_PUB_APB_DDR_ID2QOS_SEL SCI_ADDR(REGS_PUB_APB_BASE, 0x003C) +#define REG_PUB_APB_DDR_ID2QOS_RCFG0 SCI_ADDR(REGS_PUB_APB_BASE, 0x0040) +#define REG_PUB_APB_DDR_ID2QOS_RCFG1 SCI_ADDR(REGS_PUB_APB_BASE, 0x0044) +#define REG_PUB_APB_DDR_ID2QOS_RCFG2 SCI_ADDR(REGS_PUB_APB_BASE, 0x0048) +#define REG_PUB_APB_DDR_ID2QOS_RCFG3 SCI_ADDR(REGS_PUB_APB_BASE, 0x004c) +#define REG_PUB_APB_DDR_ID2QOS_RCFG4 SCI_ADDR(REGS_PUB_APB_BASE, 0x0050) +#define REG_PUB_APB_DDR_ID2QOS_RCFG5 SCI_ADDR(REGS_PUB_APB_BASE, 0x0054) +#define REG_PUB_APB_DDR_ID2QOS_RCFG6 SCI_ADDR(REGS_PUB_APB_BASE, 0x0058) +#define REG_PUB_APB_DDR_ID2QOS_RCFG7 SCI_ADDR(REGS_PUB_APB_BASE, 0x005c) +#define REG_PUB_APB_DDR_ID2QOS_RCFG8 SCI_ADDR(REGS_PUB_APB_BASE, 0x0060) +#define REG_PUB_APB_DDR_ID2QOS_RCFG9 SCI_ADDR(REGS_PUB_APB_BASE, 0x0064) +#define REG_PUB_APB_DDR_ID2QOS_WCFG0 SCI_ADDR(REGS_PUB_APB_BASE, 0x0080) +#define REG_PUB_APB_DDR_ID2QOS_WCFG1 SCI_ADDR(REGS_PUB_APB_BASE, 0x0084) +#define REG_PUB_APB_DDR_ID2QOS_WCFG2 SCI_ADDR(REGS_PUB_APB_BASE, 0x0088) +#define REG_PUB_APB_DDR_ID2QOS_WCFG3 SCI_ADDR(REGS_PUB_APB_BASE, 0x008c) +#define REG_PUB_APB_DDR_ID2QOS_WCFG4 SCI_ADDR(REGS_PUB_APB_BASE, 0x0090) +#define REG_PUB_APB_DDR_ID2QOS_WCFG5 SCI_ADDR(REGS_PUB_APB_BASE, 0x0094) +#define REG_PUB_APB_DDR_ID2QOS_WCFG6 SCI_ADDR(REGS_PUB_APB_BASE, 0x0098) +#define REG_PUB_APB_DDR_ID2QOS_WCFG7 SCI_ADDR(REGS_PUB_APB_BASE, 0x009c) +#define REG_PUB_APB_DDR_ID2QOS_WCFG8 SCI_ADDR(REGS_PUB_APB_BASE, 0x00a0) +#define REG_PUB_APB_DDR_ID2QOS_WCFG9 SCI_ADDR(REGS_PUB_APB_BASE, 0x00a4) +#define REG_PUB_APB_DFI_TIMEOUT_CFG SCI_ADDR(REGS_PUB_APB_BASE, 0x0100) +#define REG_PUB_APB_DFI_TIMEOUT_STATUS SCI_ADDR(REGS_PUB_APB_BASE, 0x0104) +#define REG_PUB_APB_DFI_TIMEOUT_EN_CNT SCI_ADDR(REGS_PUB_APB_BASE, 0x0108) +#define REG_PUB_APB_DFI_TIMEOUT_VALID_CNT SCI_ADDR(REGS_PUB_APB_BASE, 0x010c) +#define REG_PUB_APB_DMC_PORT_REMAP_EN SCI_ADDR(REGS_PUB_APB_BASE, 0x3000) +#define REG_PUB_APB_DMC_PORTS_MPU_EN SCI_ADDR(REGS_PUB_APB_BASE, 0x3004) +#define REG_PUB_APB_DMC_PORT0_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3008) +#define REG_PUB_APB_DMC_PORT1_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x300C) +#define REG_PUB_APB_DMC_PORT2_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3010) +#define REG_PUB_APB_DMC_PORT3_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3014) +#define REG_PUB_APB_DMC_PORT4_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3018) +#define REG_PUB_APB_DMC_PORT5_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x301C) +#define REG_PUB_APB_DMC_PORT6_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3020) +#define REG_PUB_APB_DMC_PORT7_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3024) +#define REG_PUB_APB_DMC_PORT8_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3028) +#define REG_PUB_APB_DMC_PORT9_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x302C) +#define REG_PUB_APB_DMC_PORT0_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3030) +#define REG_PUB_APB_DMC_PORT1_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3034) +#define REG_PUB_APB_DMC_PORT2_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3038) +#define REG_PUB_APB_DMC_PORT3_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x303C) +#define REG_PUB_APB_DMC_PORT4_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3040) +#define REG_PUB_APB_DMC_PORT5_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3044) +#define REG_PUB_APB_DMC_PORT6_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3048) +#define REG_PUB_APB_DMC_PORT7_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3050) +#define REG_PUB_APB_DMC_PORT8_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3054) +#define REG_PUB_APB_DMC_PORT9_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3058) +#define REG_PUB_APB_DMC_PORT0_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x305C) +#define REG_PUB_APB_DMC_PORT1_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3060) +#define REG_PUB_APB_DMC_PORT2_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3064) +#define REG_PUB_APB_DMC_PORT3_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3068) +#define REG_PUB_APB_DMC_PORT4_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x306C) +#define REG_PUB_APB_DMC_PORT5_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3070) +#define REG_PUB_APB_DMC_PORT6_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3074) +#define REG_PUB_APB_DMC_PORT7_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3078) +#define REG_PUB_APB_DMC_PORT8_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x307C) +#define REG_PUB_APB_DMC_PORT9_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3080) + + + +/* bits definitions for register REG_PUB_APB_BUSMON_CNT_START */ +#define BIT_PUB_BUSMON_CNT_START ( BIT(0) ) + +/* bits definitions for register REG_PUB_APB_BUSMON_CFG */ +#define BIT_PUB_BUSMON9_EB ( BIT(25) ) +#define BIT_PUB_BUSMON8_EB ( BIT(24) ) +#define BIT_PUB_BUSMON7_EB ( BIT(23) ) +#define BIT_PUB_BUSMON6_EB ( BIT(22) ) +#define BIT_PUB_BUSMON5_EB ( BIT(21) ) +#define BIT_PUB_BUSMON4_EB ( BIT(20) ) +#define BIT_PUB_BUSMON3_EB ( BIT(19) ) +#define BIT_PUB_BUSMON2_EB ( BIT(18) ) +#define BIT_PUB_BUSMON1_EB ( BIT(17) ) +#define BIT_PUB_BUSMON0_EB ( BIT(16) ) +#define BIT_PUB_BUSMON9_SOFT_RST ( BIT(9) ) +#define BIT_PUB_BUSMON8_SOFT_RST ( BIT(8) ) +#define BIT_PUB_BUSMON7_SOFT_RST ( BIT(7) ) +#define BIT_PUB_BUSMON6_SOFT_RST ( BIT(6) ) +#define BIT_PUB_BUSMON5_SOFT_RST ( BIT(5) ) +#define BIT_PUB_BUSMON4_SOFT_RST ( BIT(4) ) +#define BIT_PUB_BUSMON3_SOFT_RST ( BIT(3) ) +#define BIT_PUB_BUSMON2_SOFT_RST ( BIT(2) ) +#define BIT_PUB_BUSMON1_SOFT_RST ( BIT(1) ) +#define BIT_PUB_BUSMON0_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_PUB_APB_DDR_EB */ + +/* bits definitions for register REG_PUB_APB_DDR_SOFT_RST */ + +/* bits definitions for register REG_PUB_APB_DDR_QOS_CFG1 */ +#define BITS_DMC_ARQOS_3(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_3(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_2(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_2(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_1(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_0(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_QOS_CFG2 */ +#define BITS_DMC_ARQOS_7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_7(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_6(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_6(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_5(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_5(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_4(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_QOS_CFG3 */ +#define BITS_DMC_ARQOS_9(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_9(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_8(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_8(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_MRR_STATUS */ +#define BIT_DDRC_CO_RD_MRR_DATA_VALID ( BIT(8) ) +#define BITS_DDRC_CO_RD_MRR_DATA(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_SEL */ +#define BITS_DMC_ID_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DMC_QOS_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG0 */ +#define BITS_DMC_ARQOS_0_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_0_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_0_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_0_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_0_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_0_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_0_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_0_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG1 */ +#define BITS_DMC_ARQOS_1_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_1_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_1_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_1_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_1_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_1_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_1_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_1_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG2 */ +#define BITS_DMC_ARQOS_2_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_2_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_2_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_2_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_2_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_2_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_2_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_2_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG3 */ +#define BITS_DMC_ARQOS_3_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_3_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_3_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_3_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_3_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_3_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_3_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_3_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG4 */ +#define BITS_DMC_ARQOS_4_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_4_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_4_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_4_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_4_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_4_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_4_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_4_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG5 */ +#define BITS_DMC_ARQOS_5_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_5_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_5_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_5_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_5_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_5_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_5_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_5_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG6 */ +#define BITS_DMC_ARQOS_6_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_6_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_6_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_6_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_6_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_6_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_6_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_6_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG7 */ +#define BITS_DMC_ARQOS_7_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_7_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_7_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_7_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_7_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_7_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_7_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_7_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG8 */ +#define BITS_DMC_ARQOS_8_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_8_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_8_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_8_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_8_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_8_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_8_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_8_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG9 */ +#define BITS_DMC_ARQOS_9_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_9_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_9_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_9_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_9_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_9_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_9_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_9_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG0 */ +#define BITS_DMC_AWQOS_0_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_0_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_0_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_0_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_0_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_0_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_0_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_0_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG1 */ +#define BITS_DMC_AWQOS_1_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_1_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_1_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_1_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_1_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_1_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_1_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_1_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG2 */ +#define BITS_DMC_AWQOS_2_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_2_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_2_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_2_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_2_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_2_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_2_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_2_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG3 */ +#define BITS_DMC_AWQOS_3_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_3_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_3_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_3_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_3_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_3_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_3_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_3_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG4 */ +#define BITS_DMC_AWQOS_4_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_4_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_4_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_4_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_4_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_4_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_4_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_4_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG5 */ +#define BITS_DMC_AWQOS_5_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_5_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_5_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_5_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_5_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_5_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_5_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_5_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG6 */ +#define BITS_DMC_AWQOS_6_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_6_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_6_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_6_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_6_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_6_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_6_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_6_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG7 */ +#define BITS_DMC_AWQOS_7_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_7_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_7_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_7_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_7_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_7_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_7_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_7_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG8 */ +#define BITS_DMC_AWQOS_8_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_8_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_8_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_8_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_8_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_8_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_8_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_8_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG9 */ +#define BITS_DMC_AWQOS_9_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_9_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_9_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_9_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_9_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_9_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_9_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_9_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DFI_TIMEOUT_CFG */ +#define BITS_DFI_TIMEOUT_THRESHOLD(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DFI_TIMEOUT_CLR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DFI_TIMEOUT_EN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DFI_TIMEOUT_STATUS */ +#define BITS_DFI_TIMEOUT_STATUS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PUB_APB_DFI_TIMEOUT_EN_CNT */ +#define BITS_DFI_TIMEOUT_EN3_CNT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DFI_TIMEOUT_EN2_CNT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DFI_TIMEOUT_EN1_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DFI_TIMEOUT_EN0_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PUB_APB_DFI_TIMEOUT_VALID_CNT */ +#define BITS_DFI_TIMEOUT_VALID3_CNT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DFI_TIMEOUT_VALID2_CNT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DFI_TIMEOUT_VALID1_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DFI_TIMEOUT_VALID0_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PUB_APB_DMC_PORT_REMAP_EN */ +#define BITS_DMC_PORTS_REMAP_EN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_PUB_APB_DMC_PORTS_MPU_EN */ +#define BITS_DMC_PORTS_MPU_EN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_PUB_APB_DMC_PORT0_ADDR_REMAP */ +#define BITS_DMC_PORT0_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT1_ADDR_REMAP */ +#define BITS_DMC_PORT1_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT2_ADDR_REMAP */ +#define BITS_DMC_PORT2_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT3_ADDR_REMAP */ +#define BITS_DMC_PORT3_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT4_ADDR_REMAP */ +#define BITS_DMC_PORT4_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT5_ADDR_REMAP */ +#define BITS_DMC_PORT5_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT6_ADDR_REMAP */ +#define BITS_DMC_PORT6_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT7_ADDR_REMAP */ +#define BITS_DMC_PORT7_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT8_ADDR_REMAP */ +#define BITS_DMC_PORT8_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT9_ADDR_REMAP */ +#define BITS_DMC_PORT9_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT0_MPU_RANGE */ +#define BITS_DMC_PORT0_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT1_MPU_RANGE */ +#define BITS_DMC_PORT1_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT2_MPU_RANGE */ +#define BITS_DMC_PORT2_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT3_MPU_RANGE */ +#define BITS_DMC_PORT3_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT4_MPU_RANGE */ +#define BITS_DMC_PORT4_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT5_MPU_RANGE */ +#define BITS_DMC_PORT5_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT6_MPU_RANGE */ +#define BITS_DMC_PORT6_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT7_MPU_RANGE */ +#define BITS_DMC_PORT7_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT8_MPU_RANGE */ +#define BITS_DMC_PORT8_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT9_MPU_RANGE */ +#define BITS_DMC_PORT9_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT0_DUMP_ADDR */ +#define BITS_DMC_PORT0_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT1_DUMP_ADDR */ +#define BITS_DMC_PORT1_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT2_DUMP_ADDR */ +#define BITS_DMC_PORT2_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT3_DUMP_ADDR */ +#define BITS_DMC_PORT3_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT4_DUMP_ADDR */ +#define BITS_DMC_PORT4_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT5_DUMP_ADDR */ +#define BITS_DMC_PORT5_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT6_DUMP_ADDR */ +#define BITS_DMC_PORT6_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT7_DUMP_ADDR */ +#define BITS_DMC_PORT7_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT8_DUMP_ADDR */ +#define BITS_DMC_PORT8_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_PUB_APB_DMC_PORT9_DUMP_ADDR */ +#define BITS_DMC_PORT9_DUMP_ADDR(_X_) (_X_) + +#endif diff --git a/include/soc/sprd/chip_x35l64/__regs_wcdma_ahb_rf.h b/include/soc/sprd/chip_x35l64/__regs_wcdma_ahb_rf.h new file mode 100644 index 00000000..32d5cbb9 --- /dev/null +++ b/include/soc/sprd/chip_x35l64/__regs_wcdma_ahb_rf.h @@ -0,0 +1,123 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_WCDMA_AHB_RF_HEADFILE_H__ +#define __H_REGS_WCDMA_AHB_RF_HEADFILE_H__ __FILE__ + +#define REGS_WCDMA_AHB_RF + +/* registers definitions for WCDMA_AHB_RF */ +#define REG_WCDMA_AHB_RF_AHB_EB0 SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0000) +#define REG_WCDMA_AHB_RF_AHB_RST0 SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0004) +#define REG_WCDMA_AHB_RF_ARCH_EB_REG SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0018) +#define REG_WCDMA_AHB_RF_AHB_REMAP SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x001C) +#define REG_WCDMA_AHB_RF_AHB_MISC_CTL SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0020) +#define REG_WCDMA_AHB_RF_AHB_MTX_PRI_SEL0 SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0024) +#define REG_WCDMA_AHB_RF_AHB_MTX_PRI_SEL1 SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0028) +#define REG_WCDMA_AHB_RF_AHB1_PAUSE SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x002C) +#define REG_WCDMA_AHB_RF_AHB_SLP_CTL SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0034) +#define REG_WCDMA_AHB_RF_AHB2_SLP_STS SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0038) +#define REG_WCDMA_AHB_RF_MCU_CLK_CTL SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x003C) +#define REG_WCDMA_AHB_RF_CHIP_ID SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x01FC) + + + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB_EB0 */ +#define BITS_WCDMA_EN(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BIT_BUSMON0_EN ( BIT(1) ) +#define BIT_SPINLOCK_EN ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB_RST0 */ +#define BIT_WCDMA_SOFT_RST ( BIT(3) ) +#define BIT_BUSMON0_SOFT_RST ( BIT(1) ) +#define BIT_SPINLOCK_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_ARCH_EB_REG */ +#define BIT_AHB_ARCH_EB ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB_REMAP */ +#define BIT_ARM_JTAG_EN_ARM1 ( BIT(1) ) +#define BIT_REMAP ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB_MISC_CTL */ +#define BIT_FORCE_WSYS_ACC_STOP ( BIT(3) ) +#define BIT_W_DMA_LSLP_EN ( BIT(2) ) +#define BIT_BUSMON0_SEL ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB_MTX_PRI_SEL0 */ +#define BITS_ARMMTX_M3TOS0_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ARMMTX_M3TOS0_ADJ_EN ( BIT(27) ) +#define BIT_ARMMTX_M3TOS0_RND_EN ( BIT(26) ) +#define BITS_ARMMTX_M3TOS0_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_ARMMTX_M2TOS0_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M2TOS0_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M2TOS0_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M2TOS0_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M1TOS0_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M1TOS0_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M1TOS0_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M1TOS0_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M0TOS0_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M0TOS0_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M0TOS0_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M0TOS0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB_MTX_PRI_SEL1 */ +#define BITS_ARMMTX_M6TOS0_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M6TOS0_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M6TOS0_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M6TOS0_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M5TOS0_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M5TOS0_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M5TOS0_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M5TOS0_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M4TOS0_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M4TOS0_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M4TOS0_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M4TOS0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB1_PAUSE */ +#define BIT_APB1_SLEEP ( BIT(3) ) +#define BIT_MCU1_DEEP_SLEEP_EN ( BIT(2) ) +#define BIT_MCU1_SYS_SLEEP_EN ( BIT(1) ) +#define BIT_MCU1_CORE_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB_SLP_CTL */ +#define BIT_MCUMTX_AUTO_GATE_EN ( BIT(4) ) +#define BIT_MCU_AUTO_GATE_EN ( BIT(3) ) +#define BIT_AHB_AUTO_GATE_EN ( BIT(2) ) +#define BIT_ARM1_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB2_SLP_STS */ +#define BIT_APB1_PERI_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_MCU_CLK_CTL */ +#define BITS_CLK_AHB_DIV(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_CLK_MCU_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_APB_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CLK_MCU_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_CHIP_ID */ +#define BITS_CHIP_ID(_X_) (_X_) + +#endif diff --git a/include/soc/sprd/chip_x35l64/__regs_wcdma_apb_rf.h b/include/soc/sprd/chip_x35l64/__regs_wcdma_apb_rf.h new file mode 100644 index 00000000..a5a57b74 --- /dev/null +++ b/include/soc/sprd/chip_x35l64/__regs_wcdma_apb_rf.h @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_WCDMA_APB_RF_HEADFILE_H__ +#define __H_REGS_WCDMA_APB_RF_HEADFILE_H__ __FILE__ + +#define REGS_WCDMA_APB_RF + +/* registers definitions for WCDMA_APB_RF */ +#define REG_WCDMA_APB_RF_APB_EB SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0000) +#define REG_WCDMA_APB_RF_APB_RST SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0004) +#define REG_WCDMA_APB_RF_APB_SLEEP_ST SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0008) +#define REG_WCDMA_APB_RF_APB_MCU_RST SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0018) +#define REG_WCDMA_APB_RF_APB_CLK_SEL0 SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x001C) +#define REG_WCDMA_APB_RF_APB_CLK_DIV0 SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0020) +#define REG_WCDMA_APB_RF_APB_ARCH_EB SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0024) +#define REG_WCDMA_APB_RF_APB_SLP_CTL SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0028) + + + +/* bits definitions for register REG_WCDMA_APB_RF_APB_EB */ +#define BIT_TMR_RTC_EB ( BIT(6) ) +#define BIT_TMR_EB ( BIT(5) ) +#define BIT_SYSTMR_RTC_EB ( BIT(4) ) +#define BIT_SYSTMR_EB ( BIT(3) ) +#define BIT_UART0_EB ( BIT(2) ) +#define BIT_WDG_RTC_EB ( BIT(1) ) +#define BIT_WDG_EB ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_APB_RF_APB_RST */ +#define BIT_TMR_SOFT_RST ( BIT(3) ) +#define BIT_SYSTMR_SOFT_RST ( BIT(2) ) +#define BIT_UART0_SOFT_RST ( BIT(1) ) +#define BIT_WDG_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_APB_RF_APB_SLEEP_ST */ +#define BIT_CHIP_SLEEP_REC_CLR ( BIT(1) ) +#define BIT_CHIP_SLEEP_REC ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_APB_RF_APB_MCU_RST */ +#define BIT_MCU_SOFT_RST_SET ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_APB_RF_APB_CLK_SEL0 */ +#define BITS_CLK_UART0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_WCDMA_APB_RF_APB_CLK_DIV0 */ +#define BITS_CLK_UART0_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_WCDMA_APB_RF_APB_ARCH_EB */ +#define BIT_RTC_ARCH_EB ( BIT(1) ) +#define BIT_APB_ARCH_EB ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_APB_RF_APB_SLP_CTL */ +#define BIT_APB_PERI_FRC_ON ( BIT(1) ) +#define BIT_APB_PERI_FRC_SLP ( BIT(0) ) + +#endif diff --git a/include/soc/sprd/chip_x35l64/__sc2723_regulator_map.h b/include/soc/sprd/chip_x35l64/__sc2723_regulator_map.h new file mode 100644 index 00000000..7879ec63 --- /dev/null +++ b/include/soc/sprd/chip_x35l64/__sc2723_regulator_map.h @@ -0,0 +1,128 @@ +/* + * Copyright (C) 2013 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +/* + * Regulator (0)Name, Regulator (1)Type, Power Off (2)Ctrl and (3)Bit, PWR_SEL (4) and (5) Bit, + * Voltage Trimming (6)Ctrl and (7)Bits, Calibration (8)Ctrl and (9)Bits, + * Voltage (10)Default, Voltage (11)Ctrl and (12)Bits, Voltage Select (13)Count and Voltage (14)List[ ... ...] + */ + + SCI_REGU_REG(vddcore, 0x12, ANA_REG_GLB_LDO_DCDC_PD, BIT(9), ANA_REG_GLB_PWR_SEL, BIT(0), + ANA_REG_GLB_DCDC_CORE_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_DCDC_CTRL15, BIT(14)|BIT(16)|BIT(18)|BIT(19), + 900, ANA_REG_GLB_DCDC_CORE_ADI, BIT(5)|BIT(6)|BIT(7), 8, 1100, 700, 800, 900, 1000, 650, 1200, 1300); + + SCI_REGU_REG(vddarm, 0x12, ANA_REG_GLB_LDO_DCDC_PD, BIT(10), ANA_REG_GLB_PWR_SEL, BIT(2), + ANA_REG_GLB_DCDC_ARM_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_DCDC_CTRL15, BIT(13)|BIT(16)|BIT(18)|BIT(19), + 900, ANA_REG_GLB_DCDC_ARM_ADI, BIT(5)|BIT(6)|BIT(7), 8, 1100, 700, 800, 900, 1000, 650, 1200, 1300); + + SCI_REGU_REG(vddmem, 0x12, ANA_REG_GLB_LDO_DCDC_PD, BIT(11), ANA_REG_GLB_PWR_SEL, BIT(3), + ANA_REG_GLB_DCDC_MEM_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_DCDC_CTRL15, BIT(13)|BIT(14)|BIT(16)|BIT(18)|BIT(19), + 1200, 0, 0, 2, 600, 3125); + + SCI_REGU_REG(vddgen, 0x12, ANA_REG_GLB_LDO_DCDC_PD, BIT(12), ANA_REG_GLB_PWR_SEL, BIT(4), + ANA_REG_GLB_DCDC_GEN_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_DCDC_CTRL15, BIT(15)|BIT(16)|BIT(18)|BIT(19), + 2400, 0, 0, 2, 600, 3125); + + SCI_REGU_REG(vddrf, 0x12, ANA_REG_GLB_LDO_DCDC_PD, BIT(13), ANA_REG_GLB_PWR_SEL, BIT(5), + ANA_REG_GLB_DCDC_RF_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_DCDC_CTRL15, BIT(13)|BIT(15)|BIT(16)|BIT(18)|BIT(19), + 1500, 0, 0, 2, 600, 3125); + + SCI_REGU_REG(vddcon, 0x2, ANA_REG_GLB_LDO_PD_CTRL, BIT(13), 0, 0, + ANA_REG_GLB_DCDC_CON_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_DCDC_CTRL15, BIT(14)|BIT(15)|BIT(16)|BIT(18)|BIT(19), + 1600, 0, 0, 2, 600, 3125); + + SCI_REGU_REG(vddwpa, 0x2, ANA_REG_GLB_LDO_PD_CTRL, BIT(14), 0, 0, + ANA_REG_GLB_DCDC_WPA_ADI, BIT(0)|BIT(1)|BIT(2), ANA_REG_GLB_DCDC_CTRL15, BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(18)|BIT(19), + 0, 0, 0, 0); + + SCI_REGU_REG(vddrf0, 0x10, ANA_REG_GLB_LDO_DCDC_PD, BIT(8), ANA_REG_GLB_PWR_SEL, BIT(11), + ANA_REG_GLB_LDO_V_CTRL0, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), ANA_REG_GLB_LDO_V_CTRL11, BIT(2)|BIT(16)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1150, 6250); + + SCI_REGU_REG(vddemmccore, 0x10, ANA_REG_GLB_LDO_DCDC_PD, BIT(7), ANA_REG_GLB_PWR_SEL, BIT(7), + ANA_REG_GLB_LDO_V_CTRL7, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), ANA_REG_GLB_LDO_V_CTRL11, BIT(5)|BIT(6)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 3000, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddgen1, 0x10, ANA_REG_GLB_LDO_DCDC_PD, BIT(6), ANA_REG_GLB_PWR_SEL, BIT(12), + ANA_REG_GLB_LDO_V_CTRL3, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_V_CTRL11, BIT(0)|BIT(2)|BIT(16)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1150, 6250); + + SCI_REGU_REG(vddgen0, 0x10, ANA_REG_GLB_LDO_DCDC_PD, BIT(4), ANA_REG_GLB_PWR_SEL, BIT(13), + ANA_REG_GLB_LDO_V_CTRL2, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6), ANA_REG_GLB_LDO_V_CTRL11, BIT(1)|BIT(2)|BIT(16)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1150, 6250); + + SCI_REGU_REG(vdddcxo, 0x10, ANA_REG_GLB_LDO_DCDC_PD, BIT(5), ANA_REG_GLB_PWR_SEL, BIT(8), + ANA_REG_GLB_LDO_V_CTRL8, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), ANA_REG_GLB_LDO_V_CTRL11, BIT(7)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vdd25, 0x10, ANA_REG_GLB_LDO_DCDC_PD, BIT(3), ANA_REG_GLB_PWR_SEL, BIT(6), + ANA_REG_GLB_LDO_V_CTRL10, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_LDO_V_CTRL11, BIT(8)|BIT(17)|BIT(18)|BIT(20), + 2800, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vdd28, 0x10, ANA_REG_GLB_LDO_DCDC_PD, BIT(2), ANA_REG_GLB_PWR_SEL, BIT(9), + ANA_REG_GLB_LDO_V_CTRL3, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_LDO_V_CTRL11, BIT(6)|BIT(7)|BIT(10)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 2800, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vdd18, 0x10, ANA_REG_GLB_LDO_DCDC_PD, BIT(1), ANA_REG_GLB_PWR_SEL, BIT(10), + ANA_REG_GLB_LDO_V_CTRL9, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_V_CTRL11, BIT(0)|BIT(16)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1150, 6250); + + SCI_REGU_REG(vddwifipa, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(11), 0, 0, + ANA_REG_GLB_LDO_V_CTRL0, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_LDO_V_CTRL11, BIT(5)|BIT(10)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 3300, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddsdcore, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(10), 0, 0, + ANA_REG_GLB_LDO_V_CTRL6, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), ANA_REG_GLB_LDO_V_CTRL11, BIT(5)|BIT(7)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 3000, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddsdio, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(0), 0, 0, + ANA_REG_GLB_LDO_V_CTRL4, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_LDO_V_CTRL11, BIT(3)|BIT(16)|BIT(18)|BIT(19)|BIT(20), + 3000, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddsim0, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(1), 0, 0, + ANA_REG_GLB_LDO_V_CTRL4, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), ANA_REG_GLB_LDO_V_CTRL11, BIT(8)|BIT(10)|BIT(17)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddsim1, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(2), 0, 0, + ANA_REG_GLB_LDO_V_CTRL5, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_LDO_V_CTRL11, BIT(10)|BIT(17)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddsim2, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(3), 0, 0, + ANA_REG_GLB_LDO_V_CTRL5, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), ANA_REG_GLB_LDO_V_CTRL11, BIT(8)|BIT(9)|BIT(17)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddcama, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(4), 0, 0, + ANA_REG_GLB_LDO_V_CTRL6, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_LDO_V_CTRL11, BIT(9)|BIT(17)|BIT(18)|BIT(20), + 2800, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddcamd, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(5), 0, 0, + ANA_REG_GLB_LDO_V_CTRL1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6), ANA_REG_GLB_LDO_V_CTRL11, BIT(1)|BIT(16)|BIT(18)|BIT(20), + 1500, 0, 0, 2, 1150, 6250); + + SCI_REGU_REG(vddcamio, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(6), 0, 0, + ANA_REG_GLB_LDO_V_CTRL1, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_V_CTRL11, BIT(0)|BIT(1)|BIT(16)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1150, 6250); + + SCI_REGU_REG(vddcammot, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(7), 0, 0, + ANA_REG_GLB_LDO_V_CTRL7, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_LDO_V_CTRL11, BIT(6)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 2800, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddusb, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(8), 0, 0, + ANA_REG_GLB_LDO_V_CTRL9, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_LDO_V_CTRL11, BIT(4)|BIT(16)|BIT(18)|BIT(19)|BIT(20), + 3300, 0, 0, 2, 1200, 10000); + diff --git a/include/soc/sprd/chip_x35l64/__scx35l_clock_tree.h b/include/soc/sprd/chip_x35l64/__scx35l_clock_tree.h new file mode 100644 index 00000000..992ad053 --- /dev/null +++ b/include/soc/sprd/chip_x35l64/__scx35l_clock_tree.h @@ -0,0 +1,557 @@ +/* + * Copyright (C) 2013 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#define REG_0X20E0(_o_) SCI_ADDR(SPRD_AHB_BASE, (_o_)) +#define REG_0X2150(_o_) SCI_ADDR(SPRD_APBCKG_BASE, (_o_)) +#define REG_0X402E(_o_) SCI_ADDR(SPRD_AONAPB_BASE, (_o_)) +#define REG_0X402D(_o_) SCI_ADDR(SPRD_AONCKG_BASE, (_o_)) +#define REG_0X6010(_o_) SCI_ADDR(SPRD_GPUAPB_BASE, (_o_)) +#define REG_0X60D0(_o_) SCI_ADDR(SPRD_MMAHB_BASE, (_o_)) +#define REG_0X60E0(_o_) SCI_ADDR(SPRD_MMCKG_BASE, (_o_)) +#define REG_0X7130(_o_) SCI_ADDR(SPRD_APBREG_BASE, (_o_)) + +#define REG_0X402E0044 REG_0X402E(0x0044) +#define REG_0X402E004C REG_0X402E(0x004C) +#define REG_0X402E005C REG_0X402E(0x005C) +#define REG_0X402E0054 REG_0X402E(0x0054) +#define REG_0X402E0064 REG_0X402E(0x0064) +#define REG_0X20E00038 REG_0X20E0(0x0038) +#define REG_0X20E00054 REG_0X20E0(0x0054) +#define REG_0X402D0020 REG_0X402D(0x0020) +#define REG_0X402D002C REG_0X402D(0x002C) +#define REG_0X402D0030 REG_0X402D(0x0030) +#define REG_0X402E0000 REG_0X402E(0x0000) +#define REG_0X402D0034 REG_0X402D(0x0034) +#define REG_0X402E0004 REG_0X402E(0x0004) +#define REG_0X402D0038 REG_0X402D(0x0038) +#define REG_0X402D003C REG_0X402D(0x003C) +#define REG_0X402D0040 REG_0X402D(0x0040) +#define REG_0X402D0044 REG_0X402D(0x0044) +#define REG_0X402D0048 REG_0X402D(0x0048) +#define REG_0X402D004C REG_0X402D(0x004C) +#define REG_0X402D0050 REG_0X402D(0x0050) +#define REG_0X402D0054 REG_0X402D(0x0054) +#define REG_0X402D0058 REG_0X402D(0x0058) +#define REG_0X402D0068 REG_0X402D(0x0068) +#define REG_0X402D006C REG_0X402D(0x006C) +#define REG_0X402D0070 REG_0X402D(0x0070) +#define REG_0X402D0074 REG_0X402D(0x0074) +#define REG_0X402D0078 REG_0X402D(0x0078) +#define REG_0X402D007C REG_0X402D(0x007C) +#define REG_0X402D0080 REG_0X402D(0x0080) +#define REG_0X402D0090 REG_0X402D(0x0090) +#define REG_0X402D0098 REG_0X402D(0x0098) +#define REG_0X402D00C8 REG_0X402D(0x00C8) +#define REG_0X402D00CC REG_0X402D(0x00CC) +#define REG_0X402D00D0 REG_0X402D(0x00D0) +#define REG_0X21500020 REG_0X2150(0x0020) +#define REG_0X21500024 REG_0X2150(0x0024) +#define REG_0X20E00000 REG_0X20E0(0x0000) +#define REG_0X21500028 REG_0X2150(0x0028) +#define REG_0X2150002C REG_0X2150(0x002C) +#define REG_0X21500030 REG_0X2150(0x0030) +#define REG_0X21500034 REG_0X2150(0x0034) +#define REG_0X21500054 REG_0X2150(0x0054) +#define REG_0X21500058 REG_0X2150(0x0058) +#define REG_0X2150005C REG_0X2150(0x005C) +#define REG_0X21500060 REG_0X2150(0x0060) +#define REG_0X21500068 REG_0X2150(0x0068) +#define REG_0X21500070 REG_0X2150(0x0070) +#define REG_0X21500074 REG_0X2150(0x0074) +#define REG_0X2150007C REG_0X2150(0x007C) +#define REG_0X71300000 REG_0X7130(0x0000) +#define REG_0X21500084 REG_0X2150(0x0084) +#define REG_0X21500088 REG_0X2150(0x0088) +#define REG_0X2150008C REG_0X2150(0x008C) +#define REG_0X21500090 REG_0X2150(0x0090) +#define REG_0X21500094 REG_0X2150(0x0094) +#define REG_0X21500098 REG_0X2150(0x0098) +#define REG_0X2150009C REG_0X2150(0x009C) +#define REG_0X215000A0 REG_0X2150(0x00A0) +#define REG_0X215000A4 REG_0X2150(0x00A4) +#define REG_0X215000A8 REG_0X2150(0x00A8) +#define REG_0X215000AC REG_0X2150(0x00AC) +#define REG_0X215000B0 REG_0X2150(0x00B0) +#define REG_0X215000B4 REG_0X2150(0x00B4) +#define REG_0X215000B8 REG_0X2150(0x00B8) +#define REG_0X215000BC REG_0X2150(0x00BC) +#define REG_0X215000C0 REG_0X2150(0x00C0) +#define REG_0X215000C4 REG_0X2150(0x00C4) +#define REG_0X215000C8 REG_0X2150(0x00C8) +#define REG_0X215000CC REG_0X2150(0x00CC) +#define REG_0X60100020 REG_0X6010(0x0020) +#define REG_0X60E00020 REG_0X60E0(0x0020) +#define REG_0X60D00008 REG_0X60D0(0x0008) +#define REG_0X60D00000 REG_0X60D0(0x0000) +#define REG_0X60E00038 REG_0X60E0(0x0038) +#define REG_0X60E00030 REG_0X60E0(0x0030) +#define REG_0X60E00034 REG_0X60E0(0x0034) +#define REG_0X60E00028 REG_0X60E0(0x0028) +#define REG_0X60E00024 REG_0X60E0(0x0024) +#define REG_0X60E0002C REG_0X60E0(0x002C) + +/* + * Clock (0)Name, Clock (1)fixed rate, Clock Enable (2)Ctrl and (3)Bit, + * Clock Divisor (4)Ctrl and (5)Bit, Clock Parent (6)Ctrl and (7)Bit, + * and Parent Select (15)Count and (16)Lists[ ... ...] + */ + +SCI_CLK_ADD(ext_26m, 26000000, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(ext_32k, 32768, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(ext_26m_rf1, 26000000, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(ext_1m, 1000000, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(ext_2m, 2000000, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(ext_4m, 4000000, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_pad, 64000000, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_mpll, 0, 0, 0, + REG_0X402E0044, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, 0); + +SCI_CLK_ADD(clk_dpll, 0, 0, 0, + REG_0X402E004C, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, 0); + +SCI_CLK_ADD(clk_ltepll, 0, 0, 0, + REG_0X402E005C, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, 0); + +SCI_CLK_ADD(clk_twpll, 0, 0, 0, + REG_0X402E0054, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, 0); + +SCI_CLK_ADD(clk_lvdspll, 0, 0, 0, + REG_0X402E0064, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, 0); + +SCI_CLK_ADD(clk_768m, 0, 0, 0, + 2, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_512m, 0, 0, 0, + 3, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_384m, 0, 0, 0, + 4, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_312m, 0, 0, 0, + 5, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_307m2, 0, 0, 0, + 5, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_256m, 0, 0, 0, + 6, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_192m, 0, 0, 0, + 8, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_153m6, 0, 0, 0, + 10, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_128m, 0, 0, 0, + 12, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_96m, 0, 0, 0, + 16, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_76m8, 0, 0, 0, + 20, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_64m, 0, 0, 0, + 24, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_51m2, 0, 0, 0, + 30, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_48m, 0, 0, 0, + 32, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_38m4, 0, 0, 0, + 40, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_24m, 0, 0, 0, + 64, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_12m, 0, 0, 0, + 128, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_42m_d, 0, 0, 0, + 32, 0, 0, 0, + 1, &clk_dpll); + +SCI_CLK_ADD(clk_56m_m, 0, 0, 0, + 32, 0, 0, 0, + 1, &clk_mpll); + +SCI_CLK_ADD(clk_38m4_lte, 0, 0, 0, + 32, 0, 0, 0, + 1, &clk_ltepll); + +SCI_CLK_ADD(clk_44m_lvds, 0, 0, 0, + 32, 0, 0, 0, + 1, &clk_lvdspll); + +SCI_CLK_ADD(clk_614m4, 0, 0, 0, + 2, 0, 0, 0, + 1, &clk_ltepll); + +SCI_CLK_ADD(clk_mcu, 0, 0, 0, + REG_0X20E00038, BIT(4)|BIT(5)|BIT(6), REG_0X20E00054, BIT(0)|BIT(1)|BIT(2), + 7, &ext_26m, &clk_512m, &clk_768m, &clk_dpll, &clk_ltepll, &clk_twpll, &clk_mpll); + +SCI_CLK_ADD(clk_ca7_core, 0, 0, 0, + 0, 0, 0, 0, + 1, &clk_mcu); + +SCI_CLK_ADD(clk_ca7_axi, 0, 0, 0, + REG_0X20E00038, BIT(8)|BIT(9)|BIT(10), 0, 0, + 1, &clk_mcu); + +SCI_CLK_ADD(clk_ca7_dbg, 0, 0, 0, + REG_0X20E00038, BIT(16)|BIT(17)|BIT(18), 0, 0, + 1, &clk_mcu); + +SCI_CLK_ADD(clk_emc_4x, 0, 0, 0, + REG_0X402D0020, BIT(8)|BIT(9), REG_0X402D0020, BIT(0)|BIT(1)|BIT(2), + 8, &ext_26m, &clk_192m, &clk_307m2, &clk_384m, &clk_512m, &clk_614m4, &clk_768m, &clk_dpll); + +SCI_CLK_ADD(clk_pub_ahb, 0, 0, 0, + REG_0X402D002C, BIT(8)|BIT(9), REG_0X402D002C, BIT(0)|BIT(1), + 4, &ext_26m, &ext_4m, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_aon_apb, 0, 0, 0, + REG_0X402D0030, BIT(8)|BIT(9), REG_0X402D0030, BIT(0)|BIT(1), + 4, &ext_4m, &ext_26m, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_adi, 0, REG_0X402E0000, BIT(16), + 0, 0, REG_0X402D0034, BIT(0)|BIT(1), + 4, &ext_26m, &ext_4m, &clk_38m4, &clk_51m2); + +SCI_CLK_ADD(clk_aux0, 0, REG_0X402E0004, BIT(2), + 0, 0, REG_0X402D0038, BIT(0)|BIT(1)|BIT(2), + 7, &ext_32k, &ext_26m, &ext_26m_rf1, &ext_4m, &clk_42m_d, &clk_48m, &clk_56m_m); + +SCI_CLK_ADD(clk_aux1, 0, REG_0X402E0004, BIT(3), + 0, 0, REG_0X402D003C, BIT(0)|BIT(1)|BIT(2)|BIT(3), + 9, &ext_32k, &ext_26m, &ext_26m_rf1, &ext_4m, &clk_42m_d, &clk_48m, &clk_56m_m, &clk_38m4_lte, &clk_44m_lvds); + +SCI_CLK_ADD(clk_aux2, 0, REG_0X402E0004, BIT(4), + 0, 0, REG_0X402D0040, BIT(0)|BIT(1)|BIT(2)|BIT(3), + 9, &ext_32k, &ext_26m, &ext_26m_rf1, &ext_4m, &clk_42m_d, &clk_48m, &clk_56m_m, &clk_38m4_lte, &clk_44m_lvds); + +SCI_CLK_ADD(clk_probe, 0, REG_0X402E0004, BIT(5), + 0, 0, REG_0X402D0044, BIT(0)|BIT(1)|BIT(2)|BIT(3), + 9, &ext_32k, &ext_26m, &ext_26m_rf1, &ext_4m, &clk_42m_d, &clk_48m, &clk_56m_m, &clk_38m4_lte, &clk_44m_lvds); + +SCI_CLK_ADD(clk_pwm0, 0, REG_0X402E0000, BIT(4), + 0, 0, REG_0X402D0048, BIT(0)|BIT(1), + 4, &ext_32k, &ext_26m, &ext_26m_rf1, &clk_48m); + +SCI_CLK_ADD(clk_pwm1, 0, REG_0X402E0000, BIT(5), + 0, 0, REG_0X402D004C, BIT(0)|BIT(1), + 4, &ext_32k, &ext_26m, &ext_26m_rf1, &clk_48m); + +SCI_CLK_ADD(clk_pwm2, 0, REG_0X402E0000, BIT(6), + 0, 0, REG_0X402D0050, BIT(0)|BIT(1), + 4, &ext_32k, &ext_26m, &ext_26m_rf1, &clk_48m); + +SCI_CLK_ADD(clk_pwm3, 0, REG_0X402E0000, BIT(7), + 0, 0, REG_0X402D0054, BIT(0)|BIT(1), + 4, &ext_32k, &ext_26m, &ext_26m_rf1, &clk_48m); + +SCI_CLK_ADD(clk_efuse, 0, REG_0X402E0000, BIT(13), + 0, 0, REG_0X402D0058, BIT(0), + 1, &ext_26m); + +SCI_CLK_ADD(clk_thm, 0, REG_0X402E0004, BIT(1), + 0, 0, REG_0X402D0068, BIT(0), + 2, &ext_32k, &ext_1m); + +SCI_CLK_ADD(clk_mspi, 0, REG_0X402E0000, BIT(23), + 0, 0, REG_0X402D006C, BIT(0), + 4, &ext_26m, &clk_51m2, &clk_76m8, &clk_96m); + +SCI_CLK_ADD(clk_i2c, 0, REG_0X402E0000, BIT(31), + 0, 0, REG_0X402D0070, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_avs, 0, REG_0X402E0004, BIT(6), + 0, 0, REG_0X402D0074, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_aud, 0, REG_0X402E0000, BIT(18), + 0, 0, REG_0X402D0078, BIT(0), + 1, &ext_26m); + +SCI_CLK_ADD(clk_audif, 0, REG_0X402E0000, BIT(17), + 0, 0, REG_0X402D007C, BIT(0)|BIT(1), + 3, &ext_26m, &clk_38m4, &clk_51m2); + +SCI_CLK_ADD(clk_vbc, 0, REG_0X402E0000, BIT(19), + 0, 0, REG_0X402D0080, BIT(0), + 1, &ext_26m); + +SCI_CLK_ADD(clk_ca7_dap, 0, REG_0X402E0000, BIT(30), + 0, 0, REG_0X402D0090, BIT(0)|BIT(1), + 4, &ext_26m, &clk_76m8, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_ca7_ts, 0, REG_0X402E0000, BIT(28), + 0, 0, REG_0X402D0098, BIT(0)|BIT(1), + 4, &ext_32k, &ext_26m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_djtag_tck, 0, 0, 0, + 0, 0, REG_0X402D00C8, BIT(0), + 3, &ext_26m, &ext_4m, &clk_pad); + +SCI_CLK_ADD(clk_arm7_ahb, 0, 0, 0, + REG_0X402D00CC, BIT(8)|BIT(9), REG_0X402D00CC, BIT(0)|BIT(1), + 4, &ext_4m, &ext_26m, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_ca5_ts, 0, REG_0X402E0004, BIT(26), + 0, 0, REG_0X402D00D0, BIT(0)|BIT(1), + 4, &ext_32k, &ext_26m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_disp_emc, 0, REG_0X402E0004, BIT(11), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_gsp_emc, 0, REG_0X402E0004, BIT(13), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_ap_ahb, 0, 0, 0, + 0, 0, REG_0X21500020, BIT(0)|BIT(1), + 4, &ext_26m, &clk_76m8, &clk_128m, &clk_192m); + +SCI_CLK_ADD(clk_ap_apb, 0, 0, 0, + 0, 0, REG_0X21500024, BIT(0)|BIT(1), + 4, &ext_26m, &clk_64m, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_gsp, 0, REG_0X20E00000, BIT(3), + 0, 0, REG_0X21500028, BIT(0)|BIT(1), + 4, &clk_96m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_dispc0, 0, REG_0X20E00000, BIT(1), + REG_0X2150002C, BIT(8)|BIT(9)|BIT(10), REG_0X2150002C, BIT(0)|BIT(1), + 4, &clk_153m6, &clk_192m, &clk_256m, &clk_307m2); + +SCI_CLK_ADD(clk_dispc0_dbi, 0, 0, 0, + REG_0X21500030, BIT(8)|BIT(9)|BIT(10), REG_0X21500030, BIT(0)|BIT(1), + 4, &clk_128m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_dispc0_dpi, 0, 0, 0, + REG_0X21500034, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), REG_0X21500034, BIT(0)|BIT(1), + 5, &clk_128m, &clk_153m6, &clk_192m, &clk_384m, &clk_pad); + +SCI_CLK_ADD(clk_nandc_2x, 0, REG_0X20E00000, BIT(18), + 0, 0, REG_0X21500054, BIT(0)|BIT(1), + 4, &clk_192m, &clk_256m, &clk_307m2, &clk_384m); + +SCI_CLK_ADD(clk_nandc_ecc, 0, REG_0X20E00000, BIT(19), + 0, 0, REG_0X21500058, BIT(0), + 2, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_sdio0, 0, REG_0X20E00000, BIT(8), + REG_0X2150005C, BIT(8)|BIT(9)|BIT(10), REG_0X2150005C, BIT(0)|BIT(1), + 4, &ext_26m, &clk_256m, &clk_307m2, &clk_384m); + +SCI_CLK_ADD(clk_sdio1, 0, REG_0X20E00000, BIT(9), + 0, 0, REG_0X21500060, BIT(0)|BIT(1), + 4, &clk_48m, &clk_76m8, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_sdio2, 0, REG_0X20E00000, BIT(10), + 0, 0, REG_0X21500068, BIT(0)|BIT(1), + 4, &clk_48m, &clk_76m8, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_emmc, 0, REG_0X20E00000, BIT(11), + 0, 0, REG_0X21500070, BIT(0)|BIT(1), + 4, &ext_26m, &clk_256m, &clk_307m2, &clk_384m); + +SCI_CLK_ADD(clk_otg_ref, 0, REG_0X20E00000, BIT(4), + 0, 0, REG_0X21500074, BIT(0), + 2, &clk_12m, &clk_24m); + +SCI_CLK_ADD(clk_hsic_ref, 0, REG_0X20E00000, BIT(2), + 0, 0, REG_0X2150007C, BIT(0), + 2, &clk_12m, &clk_24m); + +SCI_CLK_ADD(clk_uart0, 0, REG_0X71300000, BIT(13), + REG_0X21500084, BIT(8)|BIT(9)|BIT(10), REG_0X21500084, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart1, 0, REG_0X71300000, BIT(14), + REG_0X21500088, BIT(8)|BIT(9)|BIT(10), REG_0X21500088, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart2, 0, REG_0X71300000, BIT(15), + REG_0X2150008C, BIT(8)|BIT(9)|BIT(10), REG_0X2150008C, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart3, 0, REG_0X71300000, BIT(16), + REG_0X21500090, BIT(8)|BIT(9)|BIT(10), REG_0X21500090, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart4, 0, REG_0X71300000, BIT(17), + REG_0X21500094, BIT(8)|BIT(9)|BIT(10), REG_0X21500094, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_i2c0, 0, REG_0X71300000, BIT(8), + REG_0X21500098, BIT(8)|BIT(9)|BIT(10), REG_0X21500098, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_i2c1, 0, REG_0X71300000, BIT(9), + REG_0X2150009C, BIT(8)|BIT(9)|BIT(10), REG_0X2150009C, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_i2c2, 0, REG_0X71300000, BIT(10), + REG_0X215000A0, BIT(8)|BIT(9)|BIT(10), REG_0X215000A0, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_i2c3, 0, REG_0X71300000, BIT(11), + REG_0X215000A4, BIT(8)|BIT(9)|BIT(10), REG_0X215000A4, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_i2c4, 0, REG_0X71300000, BIT(12), + REG_0X215000A8, BIT(8)|BIT(9)|BIT(10), REG_0X215000A8, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_spi0, 0, REG_0X71300000, BIT(5), + REG_0X215000AC, BIT(8)|BIT(9)|BIT(10), REG_0X215000AC, BIT(0)|BIT(1), + 5, &ext_26m, &clk_96m, &clk_153m6, &clk_192m, &clk_pad); + +SCI_CLK_ADD(clk_spi1, 0, REG_0X71300000, BIT(6), + REG_0X215000B0, BIT(8)|BIT(9)|BIT(10), REG_0X215000B0, BIT(0)|BIT(1), + 5, &ext_26m, &clk_96m, &clk_153m6, &clk_192m, &clk_pad); + +SCI_CLK_ADD(clk_spi2, 0, REG_0X71300000, BIT(7), + REG_0X215000B4, BIT(8)|BIT(9)|BIT(10), REG_0X215000B4, BIT(0)|BIT(1), + 5, &ext_26m, &clk_96m, &clk_153m6, &clk_192m, &clk_pad); + +SCI_CLK_ADD(clk_iis0, 0, REG_0X71300000, BIT(1), + REG_0X215000B8, BIT(8)|BIT(9)|BIT(10), REG_0X215000B8, BIT(0)|BIT(1), + 4, &ext_26m, &clk_128m, &clk_153m6, &clk_pad); + +SCI_CLK_ADD(clk_iis1, 0, REG_0X71300000, BIT(2), + REG_0X215000BC, BIT(8)|BIT(9)|BIT(10), REG_0X215000BC, BIT(0)|BIT(1), + 4, &ext_26m, &clk_128m, &clk_153m6, &clk_pad); + +SCI_CLK_ADD(clk_iis2, 0, REG_0X71300000, BIT(3), + REG_0X215000C0, BIT(8)|BIT(9)|BIT(10), REG_0X215000C0, BIT(0)|BIT(1), + 4, &ext_26m, &clk_128m, &clk_153m6, &clk_pad); + +SCI_CLK_ADD(clk_iis3, 0, REG_0X71300000, BIT(4), + REG_0X215000C4, BIT(8)|BIT(9)|BIT(10), REG_0X215000C4, BIT(0)|BIT(1), + 4, &ext_26m, &clk_128m, &clk_153m6, &clk_pad); + +SCI_CLK_ADD(clk_zipenc, 0, REG_0X20E00000, BIT(20), + 0, 0, REG_0X215000C8, BIT(0)|BIT(1), + 4, &clk_96m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_zipdec, 0, REG_0X20E00000, BIT(21), + 0, 0, REG_0X215000CC, BIT(0)|BIT(1), + 4, &clk_96m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_gpu_i, 0, REG_0X402E0000, BIT(27), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_gpu, 0, REG_0X402E0000, BIT(27), + REG_0X60100020, BIT(8)|BIT(9), REG_0X60100020, BIT(0)|BIT(1)|BIT(2), + 6, &clk_153m6, &clk_192m, &clk_256m, &clk_307m2, &clk_384m, &clk_512m); + +SCI_CLK_ADD(clk_mm_i, 0, REG_0X402E0000, BIT(25), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_mm_ahb, 0, 0, 0, + 0, 0, REG_0X60E00020, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_mm_axi, 0, REG_0X60D00008, BIT(7), + 0, 0, 0, 0, + 1, &clk_mm_i); + +SCI_CLK_ADD(clk_mm_mtx_axi, 0, REG_0X60D00008, BIT(8), + 0, 0, 0, 0, + 1, &clk_mm_axi); + +SCI_CLK_ADD(clk_mmu, 0, REG_0X60D00000, BIT(7), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_mm_ckg, 0, REG_0X60D00000, BIT(6), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_jpg, 0, REG_0X60D00008, BIT(6), + 0, 0, REG_0X60E00038, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_256m, &clk_312m); + +SCI_CLK_ADD(clk_csi, 0, REG_0X60D00008, BIT(1), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_dcam_mipi, 0, REG_0X60D00008, BIT(0), + 0, 0, 0, 0, + 1, &clk_csi); + +SCI_CLK_ADD(clk_vsp, 0, REG_0X60D00008, BIT(5), + 0, 0, REG_0X60E00030, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_256m, &clk_312m); + +SCI_CLK_ADD(clk_isp, 0, REG_0X60D00008, BIT(4), + 0, 0, REG_0X60E00034, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_256m, &clk_312m); + +SCI_CLK_ADD(clk_ccir, 0, REG_0X60D00000, BIT(1), + 0, 0, REG_0X60E00028, BIT(16), + 2, &clk_24m, &clk_pad); + +SCI_CLK_ADD(clk_sensor, 0, REG_0X60D00008, BIT(2), + REG_0X60E00024, BIT(8)|BIT(9)|BIT(10), REG_0X60E00024, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_76m8, &clk_96m); + +SCI_CLK_ADD(clk_dcam, 0, REG_0X60D00008, BIT(3), + 0, 0, REG_0X60E0002C, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_256m, &clk_312m); + diff --git a/include/soc/sprd/chip_x35lt8/__clock_tree.h b/include/soc/sprd/chip_x35lt8/__clock_tree.h new file mode 100644 index 00000000..3c53b809 --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__clock_tree.h @@ -0,0 +1,514 @@ +/* + * Copyright (C) 2013 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +/* + * Clock (0)Name, Clock (1)fixed rate, Clock Enable (2)Ctrl and (3)Bit, + * Clock Divisor (4)Ctrl and (5)Bit, Clock Parent (6)Ctrl and (7)Bit, + * and Parent Select (15)Count and (16)Lists[ ... ...] + */ +SCI_CLK_ADD(ext_26m, 26000000, 0, 0, + 0, 0, 0, 0, 0); + +#if 0 +SCI_CLK_ADD(ext_32k, 32768, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_mpll, 0, REG_PMU_APB_CGM_AP_EN, BIT(6), + REG_AON_APB_MPLL_CFG, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_dpll, 0, REG_PMU_APB_CGM_AP_EN, BIT(1), + REG_AON_APB_DPLL_CFG, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_td_sel_i, 0, REG_PMU_APB_TDPLL_REL_CFG, BIT(0), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_w_sel_i, 0, REG_PMU_APB_WPLL_REL_CFG, BIT(0), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_c_sel_i, 0, REG_PMU_APB_CPLL_REL_CFG, BIT(0), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_wifi_sel_i, 0, REG_PMU_APB_WIFIPLL1_REL_CFG, BIT(0), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_tdpll, 768000000, REG_PMU_APB_CGM_AP_EN, BIT(3), + 0, 0, 0, 0, + 1, &clk_td_sel_i); + +SCI_CLK_ADD(clk_wpll, 921600000, REG_PMU_APB_CGM_AP_EN, BIT(5), + 0, 0, 0, 0, + 1, &clk_w_sel_i); + +SCI_CLK_ADD(clk_cpll, 624000000, REG_PMU_APB_CGM_AP_EN, BIT(2), + 0, 0, 0, 0, + 1, &clk_c_sel_i); + +SCI_CLK_ADD(clk_wifipll, 880000000, REG_PMU_APB_CGM_AP_EN, BIT(4), + 0, 0, 0, 0, + 1, &clk_wifi_sel_i); + +SCI_CLK_ADD(clk_300m, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(0), + 3, 0, 0, 0, + 1, &clk_mpll); + +SCI_CLK_ADD(clk_37m5, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(1), + 24, 0, 0, 0, + 1, &clk_mpll); + +SCI_CLK_ADD(clk_66m_d, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(2), + 8, 0, 0, 0, + 1, &clk_dpll); + +SCI_CLK_ADD(clk_51m2_w, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(23), + 18, 0, 0, 0, + 1, &clk_wpll); + +SCI_CLK_ADD(clk_40m_wf1, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(27), + 22, 0, 0, 0, + 1, &clk_wifipll); + +SCI_CLK_ADD(clk_312m, 0, REG_PMU_APB_CGM_AP_EN, BIT(7), + 2, 0, 0, 0, + 1, &clk_cpll); + +SCI_CLK_ADD(clk_208m, 0, REG_PMU_APB_CGM_AP_EN, BIT(20), + 3, 0, 0, 0, + 1, &clk_cpll); + +SCI_CLK_ADD(clk_104m, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(18), + 6, 0, 0, 0, + 1, &clk_cpll); + +SCI_CLK_ADD(clk_52m, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(19), + 12, 0, 0, 0, + 1, &clk_cpll); + +SCI_CLK_ADD(clk_384m, 0, REG_PMU_APB_CGM_AP_EN, BIT(8), + 2, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_256m, 0, REG_PMU_APB_CGM_AP_EN, BIT(9), + 3, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_192m, 0, REG_PMU_APB_CGM_AP_EN, BIT(10), + 4, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_153m6, 0, REG_PMU_APB_CGM_AP_EN, BIT(11), + 5, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_128m, 0, REG_PMU_APB_CGM_AP_EN, BIT(12), + 6, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_96m, 0, REG_PMU_APB_CGM_AP_EN, BIT(13), + 8, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_76m8, 0, REG_PMU_APB_CGM_AP_EN, BIT(14), + 10, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_64m, 0, REG_PMU_APB_CGM_AP_EN, BIT(15), + 12, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_51m2, 0, REG_PMU_APB_CGM_AP_EN, BIT(16), + 15, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_48m, 0, REG_PMU_APB_CGM_AP_EN, BIT(17), + 16, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_38m4, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(15), + 20, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_24m, 0, REG_PMU_APB_CGM_AP_EN, BIT(18), + 32, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_12m, 0, REG_PMU_APB_CGM_AP_EN, BIT(19), + 64, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_mcu, 0, 0, 0, + REG_AP_AHB_CA7_CKG_CFG, BIT(4)|BIT(5)|BIT(6), REG_AP_AHB_CA7_CKG_CFG, BIT(0)|BIT(1)|BIT(2), + 7, &ext_26m, &clk_dpll, &clk_cpll, &clk_tdpll, &clk_wifipll, &clk_wpll, &clk_mpll); + +SCI_CLK_ADD(clk_ca7_core, 0, 0, 0, + 0, 0, 0, 0, + 1, &clk_mcu); + +SCI_CLK_ADD(clk_ca7_axi, 0, 0, 0, + REG_AP_AHB_CA7_CKG_CFG, BIT(8)|BIT(9)|BIT(10), 0, 0, + 1, &clk_mcu); + +SCI_CLK_ADD(clk_ca7_dbg, 0, REG_AP_AHB_MISC_CKG_EN, BIT(8), + REG_AP_AHB_CA7_CKG_CFG, BIT(16)|BIT(17)|BIT(18), 0, 0, + 1, &clk_mcu); + +SCI_CLK_ADD(clk_ap_ahb, 0, 0, 0, + 0, 0, REG_AP_CLK_AP_AHB_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_76m8, &clk_128m, &clk_192m); + +SCI_CLK_ADD(clk_ap_apb, 0, 0, 0, + 0, 0, REG_AP_CLK_AP_APB_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_64m, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_pub_ahb, 0, 0, 0, + 0, 0, REG_AON_CLK_PUB_AHB_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_emc, 0, 0, 0, + REG_AON_CLK_EMC_CFG, BIT(8)|BIT(9), REG_AON_CLK_EMC_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_256m, &clk_384m, &clk_dpll); + +SCI_CLK_ADD(clk_aon_apb, 0, 0, 0, + REG_AON_CLK_AON_APB_CFG, BIT(8)|BIT(9), REG_AON_CLK_AON_APB_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_76m8, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_zip_emc, 0, REG_AON_APB_APB_EB1, BIT(12), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_disp_emc, 0, REG_AON_APB_APB_EB1, BIT(11), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_gsp, 0, REG_AP_AHB_AHB_EB, BIT(3), + 0, 0, REG_AP_CLK_GSP_CFG, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_96m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_disc0, 0, REG_AP_AHB_AHB_EB, BIT(1), + REG_AP_CLK_DISPC0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_DISPC0_CFG, BIT(0), + 2, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_disc0_dbi, 0, REG_AP_AHB_AHB_EB, BIT(1), + REG_AP_CLK_DISPC0_DBI_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_DISPC0_DBI_CFG, BIT(0)|BIT(1), + 4, &clk_128m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_disc0_dpi, 0, REG_AP_AHB_AHB_EB, BIT(1), + REG_AP_CLK_DISPC0_DPI_CFG, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), REG_AP_CLK_DISPC0_DPI_CFG, BIT(0)|BIT(1), + 4, &clk_128m, &clk_153m6, &clk_192m, &clk_384m); + +SCI_CLK_ADD(clk_disc1, 0, REG_AP_AHB_AHB_EB, BIT(2), + REG_AP_CLK_DISPC1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_DISPC1_CFG, BIT(0), + 2, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_disc1_dbi, 0, REG_AP_AHB_AHB_EB, BIT(2), + REG_AP_CLK_DISPC1_DBI_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_DISPC1_DBI_CFG, BIT(0)|BIT(1), + 4, &clk_128m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_disc1_dpi, 0, REG_AP_AHB_AHB_EB, BIT(2), + REG_AP_CLK_DISPC1_DPI_CFG, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), REG_AP_CLK_DISPC1_DPI_CFG, BIT(0)|BIT(1), + 4, &clk_128m, &clk_153m6, &clk_192m, &clk_384m); + +SCI_CLK_ADD(clk_zipdec_emc, 0, REG_AP_AHB_AHB_EB, BIT(21), + 0, 0, REG_AP_CLK_ZIPENC_CFG, BIT(0)|BIT(1), + 4, &clk_96m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_zipenc_emc, 0, REG_AP_AHB_AHB_EB, BIT(20), + 0, 0, REG_AP_CLK_ZIPENC_CFG, BIT(0)|BIT(1), + 4, &clk_96m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_nandc_ecc, 0, REG_AP_AHB_AHB_EB, BIT(19), + 0, 0, REG_AP_CLK_NANDC_ECC_CFG, BIT(0), + 2, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_nfc, 0, REG_AP_AHB_AHB_EB, BIT(6), + REG_AP_CLK_NFC_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_NFC_CFG, BIT(0)|BIT(1), + 3, &clk_64m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_sdio0, 0, REG_AP_AHB_AHB_EB, BIT(8), + REG_AP_CLK_SDIO0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_SDIO0_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_256m, &clk_312m, &clk_384m); + +SCI_CLK_ADD(clk_sdio1, 0, REG_AP_AHB_AHB_EB, BIT(9), + 0, 0, REG_AP_CLK_SDIO1_CFG, BIT(0)|BIT(1), + 4, &clk_48m, &clk_76m8, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_sdio2, 0, REG_AP_AHB_AHB_EB, BIT(10), + 0, 0, REG_AP_CLK_SDIO2_CFG, BIT(0)|BIT(1), + 4, &clk_48m, &clk_76m8, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_emmc, 0, REG_AP_AHB_AHB_EB, BIT(11), + 0, 0, REG_AP_CLK_EMMC_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_256m, &clk_312m, &clk_384m); + +SCI_CLK_ADD(clk_gps_tcxo, 64000000, REG_AP_CLK_GPS_TCXO_CFG, BIT(16), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_gps, 0, REG_AP_AHB_AHB_EB, BIT(12), + 0, 0, REG_AP_CLK_GPS_CFG, BIT(0), + 2, &clk_64m, &clk_76m8); + +SCI_CLK_ADD(clk_usb_ref, 0, REG_AP_AHB_AHB_EB, BIT(4), + 0, 0, REG_AP_CLK_USB_REF_CFG, BIT(0), + 2, &clk_12m, &clk_24m); + +SCI_CLK_ADD(clk_uart0, 0, REG_AP_APB_APB_EB, BIT(13), + REG_AP_CLK_UART0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_UART0_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart1, 0, REG_AP_APB_APB_EB, BIT(14), + REG_AP_CLK_UART1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_UART1_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart2, 0, REG_AP_APB_APB_EB, BIT(15), + REG_AP_CLK_UART2_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_UART2_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart3, 0, REG_AP_APB_APB_EB, BIT(16), + REG_AP_CLK_UART3_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_UART3_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_i2c0, 0, REG_AP_APB_APB_EB, BIT(8), + REG_AP_CLK_I2C0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_I2C0_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_i2c1, 0, REG_AP_APB_APB_EB, BIT(9), + REG_AP_CLK_I2C1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_I2C1_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_i2c2, 0, REG_AP_APB_APB_EB, BIT(10), + REG_AP_CLK_I2C2_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_I2C2_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_i2c3, 0, REG_AP_APB_APB_EB, BIT(11), + REG_AP_CLK_I2C3_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_I2C3_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_spi0, 0, REG_AP_APB_APB_EB, BIT(5), + REG_AP_CLK_SPI0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_SPI0_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_spi1, 0, REG_AP_APB_APB_EB, BIT(6), + REG_AP_CLK_SPI1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_SPI1_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_spi2, 0, REG_AP_APB_APB_EB, BIT(7), + REG_AP_CLK_SPI2_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_SPI2_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_iis0, 0, REG_AP_APB_APB_EB, BIT(1), + REG_AP_CLK_IIS0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_IIS0_CFG, BIT(0)|BIT(1), + 3, &ext_26m, &clk_76m8, &clk_128m); + +SCI_CLK_ADD(clk_iis1, 0, REG_AP_APB_APB_EB, BIT(2), + REG_AP_CLK_IIS1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_IIS1_CFG, BIT(0)|BIT(1), + 3, &ext_26m, &clk_76m8, &clk_128m); + +SCI_CLK_ADD(clk_gpu_top_i, 0, REG_PMU_APB_PD_GPU_TOP_CFG+1, BIT(25), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_gpu_i, 0, REG_AON_APB_APB_EB0, BIT(27), + 0, 0, 0, 0, + 1, &clk_gpu_top_i); + +SCI_CLK_ADD(clk_gpu, 0, &clk_gpu_i, 0, + REG_GPU_APB_APB_CLK_CTRL, BIT(2)|BIT(3), REG_GPU_APB_APB_CLK_CTRL, BIT(0)|BIT(1), + 4, &clk_208m, &clk_256m, &clk_300m, &clk_312m); + +SCI_CLK_ADD(clk_mm_top_i, 0, REG_PMU_APB_PD_MM_TOP_CFG+1, BIT(25), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_mm_i, 0, REG_AON_APB_APB_EB0, BIT(25), + 0, 0, 0, 0, + 1, &clk_mm_top_i); + +SCI_CLK_ADD(clk_mm_ahb, 0, 0, 0, + 0, 0, REG_MM_CLK_MM_AHB_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_mm_mtx_axi, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(8), + 0, 0, 0, 0, + 1, &clk_mm_i); + +SCI_CLK_ADD(clk_mm_axi, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(7), + 0, 0, 0, 0, + 1, &clk_mm_mtx_axi); + +SCI_CLK_ADD(clk_mmu, 0, REG_MM_AHB_AHB_EB, BIT(7), + 0, 0, 0, 0, + 1, &clk_mm_ahb); +SCI_CLK_ADD(clk_mm_ckg_i, 0, REG_MM_AHB_AHB_EB, BIT(6), + 0, 0, 0, 0, + 1, &clk_mm_i); + +SCI_CLK_ADD(clk_jpg_i, 0, REG_MM_AHB_AHB_EB, BIT(5), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_jpg_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(6), + 0, 0, 0, 0, + 1, &clk_jpg_i); + +SCI_CLK_ADD(clk_jpg, 0, &clk_jpg_ckg_i, 0, + 0, 0, REG_MM_CLK_JPG_CFG, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_vsp_i, 0, REG_MM_AHB_AHB_EB, BIT(3), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_vsp_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(5), + 0, 0, 0, 0, + 1, &clk_vsp_i); + +SCI_CLK_ADD(clk_vsp, 0, &clk_vsp_ckg_i, 0, + 0, 0, REG_MM_CLK_VSP_CFG, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_sensor_i, 0, REG_MM_AHB_AHB_EB, BIT(1), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_sensor_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(2), + 0, 0, 0, 0, + 1, &clk_sensor_i); + +SCI_CLK_ADD(clk_sensor, 0, &clk_sensor_ckg_i, 0, + REG_MM_CLK_SENSOR_CFG, BIT(8)|BIT(9)|BIT(10), REG_MM_CLK_SENSOR_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_76m8, &clk_96m); + +SCI_CLK_ADD(clk_ccir_in, 64000000, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_ccir_i, 0, REG_MM_AHB_AHB_EB, BIT(1), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_ccir, 0, &clk_ccir_i, 0, + 0, 0, REG_MM_CLK_CCIR_CFG, BIT(16), + 2, &clk_24m, &clk_ccir_in); + +SCI_CLK_ADD(clk_dcam_i, 0, REG_MM_AHB_AHB_EB, BIT(0), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_dcam_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(3), + 0, 0, 0, 0, + 1, &clk_dcam_i); + +SCI_CLK_ADD(clk_dcam, 0, &clk_dcam_ckg_i, 0, + 0, 0, REG_MM_CLK_DCAM_CFG, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_csi_i, 0, REG_MM_AHB_AHB_EB, BIT(4), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_csi_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(1), + 0, 0, 0, 0, + 1, &clk_csi_i); + +SCI_CLK_ADD(clk_cphy_cfg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(0), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_dcam_mipi, 0, &clk_cphy_cfg_i, 0, + 0, 0, 0, 0, + 1, &clk_csi_ckg_i); + +SCI_CLK_ADD(clk_aud, 0, REG_AON_APB_APB_EB0, BIT(18), + 0, 0, 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_audif, 0, REG_AON_APB_APB_EB0, BIT(17), + 0, 0, REG_AON_CLK_AUDIF_CFG, BIT(0)|BIT(1), + 3, &ext_26m, &clk_38m4, &clk_51m2); + +SCI_CLK_ADD(clk_vbc, 0, REG_AON_APB_APB_EB0, BIT(19), + 0, 0, 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_fm_in, 64000000, REG_AON_CLK_FM_CFG, BIT(16), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_fm, 0, REG_AON_APB_APB_EB0, BIT(1), + 0, 0, 0, 0, + 1, &clk_fm_in); + +SCI_CLK_ADD(clk_adi, 0, REG_AON_APB_APB_EB0, BIT(16), + 0, 0, REG_AON_CLK_ADI_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_38m4, &clk_51m2, &clk_64m); + +SCI_CLK_ADD(clk_aux0, 0, REG_AON_APB_APB_EB1, BIT(2), + REG_AON_APB_AON_CGM_CFG, BIT(16)|BIT(17)|BIT(18)|BIT(19), REG_AON_APB_AON_CGM_CFG, BIT(0)|BIT(1)|BIT(2)|BIT(3), + 9, &ext_32k, &ext_26m, &ext_26m, &clk_48m, &clk_52m, &clk_51m2_w, &clk_37m5, &clk_40m_wf1, &clk_66m_d); + +SCI_CLK_ADD(clk_aux1, 0, REG_AON_APB_APB_EB1, BIT(3), + REG_AON_APB_AON_CGM_CFG, BIT(20)|BIT(21)|BIT(22)|BIT(23), REG_AON_APB_AON_CGM_CFG, BIT(4)|BIT(5)|BIT(6)|BIT(7), + 9, &ext_32k, &ext_26m, &ext_26m, &clk_48m, &clk_52m, &clk_51m2_w, &clk_37m5, &clk_40m_wf1, &clk_66m_d); + +SCI_CLK_ADD(clk_aux2, 0, REG_AON_APB_APB_EB1, BIT(4), + REG_AON_APB_AON_CGM_CFG, BIT(24)|BIT(25)|BIT(26)|BIT(27), REG_AON_APB_AON_CGM_CFG, BIT(8)|BIT(9)|BIT(10)|BIT(11), + 9, &ext_32k, &ext_26m, &ext_26m, &clk_48m, &clk_52m, &clk_51m2_w, &clk_37m5, &clk_40m_wf1, &clk_66m_d); + +SCI_CLK_ADD(clk_pwm0, 0, REG_AON_APB_APB_EB0, BIT(4), + 0, 0, REG_AON_CLK_PWM0_CFG, BIT(0), + 2, &ext_32k, &ext_26m); + +SCI_CLK_ADD(clk_pwm1, 0, REG_AON_APB_APB_EB0, BIT(5), + 0, 0, REG_AON_CLK_PWM1_CFG, BIT(0), + 2, &ext_32k, &ext_26m); + +SCI_CLK_ADD(clk_pwm2, 0, REG_AON_APB_APB_EB0, BIT(6), + 0, 0, REG_AON_CLK_PWM2_CFG, BIT(0), + 2, &ext_32k, &ext_26m); + +SCI_CLK_ADD(clk_pwm3, 0, REG_AON_APB_APB_EB0, BIT(7), + 0, 0, REG_AON_CLK_PWM3_CFG, BIT(0), + 2, &ext_32k, &ext_26m); + +SCI_CLK_ADD(clk_efuse, 0, REG_AON_APB_APB_EB0, BIT(13), + 0, 0, 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_ca7_dap, 0, REG_AON_APB_APB_EB0, BIT(30), + 0, 0, REG_AON_CLK_CA7_DAP_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_76m8, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_ca7_ts, 0, REG_AON_APB_APB_EB0, BIT(28), + 0, 0, REG_AON_CLK_CA7_TS_CFG, BIT(0)|BIT(1), + 4, &ext_32k, &ext_26m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_mspi, 0, REG_AON_APB_APB_EB0, BIT(23), + 0, 0, REG_AON_CLK_MSPI_CFG, BIT(0)|BIT(1), + 3, &clk_52m, &clk_76m8, &clk_96m); + +SCI_CLK_ADD(clk_i2c, 0, REG_AON_APB_APB_EB0, BIT(31), + 0, 0, REG_AON_CLK_I2C_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_avs0, 0, REG_AON_APB_APB_EB0, BIT(6), + 0, 0, REG_AON_CLK_AVS0_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_avs1, 0, REG_AON_APB_APB_EB0, BIT(7), + 0, 0, REG_AON_CLK_AVS1_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_ada_apb_rf.h b/include/soc/sprd/chip_x35lt8/__regs_ada_apb_rf.h new file mode 100644 index 00000000..57cf1dae --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_ada_apb_rf.h @@ -0,0 +1,179 @@ +/* the head file modifier: g 2015-03-19 15:44:42*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_ADA_APB_RF_HEADFILE_H__ +#define __H_REGS_ADA_APB_RF_HEADFILE_H__ __FILE__ + +#define REGS_ADA_APB_RF + +/* registers definitions for ADA_APB_RF */ +#define REG_ADA_APB_RF_APB_DAC_CTR0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0000)/*DAC control0*/ +#define REG_ADA_APB_RF_APB_DAC_CTR1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0004)/*DAC control1*/ +#define REG_ADA_APB_RF_APB_DAC_CTR2 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0008)/*DAC control2*/ +#define REG_ADA_APB_RF_APB_DAC_CTR3 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x000C)/*DAC control3*/ +#define REG_ADA_APB_RF_APB_DAC_CTR4 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0010)/*DAC control4*/ +#define REG_ADA_APB_RF_APB_DAC_STS0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0014)/*DAC status0*/ +#define REG_ADA_APB_RF_APB_DAC_STS1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0018)/*DAC status1*/ +#define REG_ADA_APB_RF_APB_ADC0_CTR0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x001C)/*ADC 0 control0*/ +#define REG_ADA_APB_RF_APB_ADC0_CTR1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0020)/*ADC 0 control1*/ +#define REG_ADA_APB_RF_APB_ADC0_CTR2 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0024)/*ADC 0 control2 for mode 0*/ +#define REG_ADA_APB_RF_APB_ADC0_CTR3 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0028)/*ADC 0 control3 for mode 1*/ +#define REG_ADA_APB_RF_APB_CAL_CTR0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0030)/*Calibration Control 0*/ +#define REG_ADA_APB_RF_APB_CAL_CTR1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0034)/*Calibration Control 1*/ +#define REG_ADA_APB_RF_APB_CAL_CTR3 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x003C)/*Calibration Control 3*/ +#define REG_ADA_APB_RF_APB_CAL_STS0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0044)/*Calibration Status 0*/ +#define REG_ADA_APB_RF_APB_CAL_STS1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0048)/*Calibration Status 1*/ +#define REG_ADA_APB_RF_APB_ADA_CTRL0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0054)/*ADA control 0*/ +#define REG_ADA_APB_RF_APB_ADA_CTRL1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0058)/*ADA control 1*/ +#define REG_ADA_APB_RF_APB_RX_GSM_DFT SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x005C)/*GSM RX default*/ +#define REG_ADA_APB_RF_APB_RX_3G_DFT SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0060)/*3G RX default*/ + + + +/* bits definitions for register REG_ADA_APB_RF_APB_DAC_CTR0 */ +#define BITS_DAC_PCTRL_1(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BIT_DAC_OUT_SEL_1 ( BIT(17) ) +#define BIT_DAC_CLK_SEL_1 ( BIT(16) ) +#define BITS_DAC_PCTRL_0(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_DAC_OUT_SEL_0 ( BIT(1) ) +#define BIT_DAC_CLK_SEL_0 ( BIT(0) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_DAC_CTR1 */ +#define BITS_DAC_WD_OVR(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DAC_WADDR_OVR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DAC_WLE_OVR ( BIT(2) ) +#define BIT_DAC_W_OVR_I_QN ( BIT(1) ) +#define BIT_DAC_W_OVR_EN ( BIT(0) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_DAC_CTR2 */ +#define BITS_DAC_RSV(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BIT_DAC_IQ_OUT_MSB_INV ( BIT(21) ) +#define BIT_DAC_IQ_IN_MSB_INV ( BIT(20) ) +#define BIT_DAC_OVR_EN_CAL ( BIT(19) ) +#define BIT_DAC_EN_OOSCAL ( BIT(18) ) +#define BIT_DAC_IQ_SWAP ( BIT(17) ) +#define BIT_DAC_CAL_START ( BIT(16) ) +#define BITS_DAC_OFFSETI(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DAC_OFFSETQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_DAC_CTR3 */ +#define BITS_DAC_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_DAC_CTR4 */ +#define BITS_DAC_I_CAL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC_Q_CAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_DAC_STS0 */ +#define BITS_DAC_WTI(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DAC_WTQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_DAC_STS1 */ +#define BITS_DAC_DA_STATE(_X_) ( (_X_) << 17 & (BIT(17)|BIT(18)) ) +#define BIT_DAC_DONE ( BIT(16) ) +#define BITS_DAC_WQ_OVR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_ADC0_CTR0 */ +#define BITS_ADC0_CALRDOUT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BIT_ADC0_CAL_SOFT_RST ( BIT(10) ) +#define BIT_ADC0_CALRD ( BIT(9) ) +#define BIT_ADC0_CALEN ( BIT(8) ) +#define BITS_ADC0_CALADDR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_ADC0_CTR1 */ +#define BITS_ADC0_DLL_OUT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_ADC0_DLLOOF(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)) ) +#define BIT_ADC0_IQ_SWAP ( BIT(14) ) +#define BITS_ADC0_DLLIN(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_ADC0_IQ_OUT_MSB_INV ( BIT(7) ) +#define BIT_ADC0_IQ_IN_MSB_INV ( BIT(6) ) +#define BIT_ADC0_DLL_SOFT_RST ( BIT(4) ) +#define BIT_ADC0_DLLWR ( BIT(3) ) +#define BIT_ADC0_DLLRD ( BIT(2) ) +#define BIT_ADC0_DLLEN ( BIT(1) ) +#define BIT_ADC0_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_ADC0_CTR2 */ +#define BITS_ADC0_RSV_0(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ADC0_DIG_CLK_SEL_0 ( BIT(11) ) +#define BIT_ADC0_VCM_SEL_0 ( BIT(10) ) +#define BITS_ADC0_DELAY_CAP_0(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ADC0_BIT_SEL_0(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_ADC0_VREF_SEL_0(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_ADC0_VREF_BOOST_0(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_ADC0_QUANT_BOOST_0(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_ADC0_CTR3 */ +#define BITS_ADC0_RSV_1(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ADC0_DIG_CLK_SEL_1 ( BIT(11) ) +#define BIT_ADC0_VCM_SEL_1 ( BIT(10) ) +#define BITS_ADC0_DELAY_CAP_1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ADC0_BIT_SEL_1(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_ADC0_VREF_SEL_1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_ADC0_VREF_BOOST_1(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_ADC0_QUANT_BOOST_1(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_CAL_CTR0 */ +#define BIT_LDO_EN_AUTO_EN ( BIT(27) ) +#define BIT_LDO_EN_FRC ( BIT(26) ) +#define BIT_BG_EN_AUTO_EN ( BIT(25) ) +#define BIT_BG_EN_FRC ( BIT(24) ) +#define BITS_ADC_CLK_CAL_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_ADA_CAL_WAIT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_CLK_ADA_CAL_EN ( BIT(6) ) +#define BIT_DAC_PD_CAL ( BIT(5) ) +#define BIT_ADC0_EN_CAL ( BIT(3) ) +#define BIT_ADC0_CAL ( BIT(1) ) +#define BIT_ADA_MODE_SEL ( BIT(0) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_CAL_CTR1 */ +#define BITS_ADC0_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) ) +#define BITS_ADC0_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_CAL_CTR3 */ +#define BIT_ADA0_CAL_START ( BIT(0) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_CAL_STS0 */ +#define BIT_ADA0_CAL_DONE ( BIT(31) ) +#define BITS_ADC0_I_CAL_RESULT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_CAL_STS1 */ +#define BITS_ADC0_Q_CAL_RESULT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_ADA_CTRL0 */ +#define BITS_ADA_AUTO_CTRL(_X_) (_X_) + +/* bits definitions for register REG_ADA_APB_RF_APB_ADA_CTRL1 */ +#define BITS_ADA_FRC_CTRL(_X_) (_X_) + +/* bits definitions for register REG_ADA_APB_RF_APB_RX_GSM_DFT */ +#define BITS_RX_GSM_DFT_Q(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) ) +#define BITS_RX_GSM_DFT_I(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_RX_3G_DFT */ +#define BITS_RX_3G_DFT_Q(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) ) +#define BITS_RX_3G_DFT_I(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_ana_glb.h b/include/soc/sprd/chip_x35lt8/__regs_ana_glb.h new file mode 100644 index 00000000..97d72f38 --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_ana_glb.h @@ -0,0 +1,836 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __ANA_REGS_GLB_H__ +#define __ANA_REGS_GLB_H__ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, include <mach/sci_glb_regs.h>" +#endif + +#define ANA_REGS_GLB + +/* registers definitions for controller ANA_REGS_GLB */ +#define ANA_REG_GLB_ARM_MODULE_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0000) +#define ANA_REG_GLB_ARM_CLK_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0004) +#define ANA_REG_GLB_RTC_CLK_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0008) +#define ANA_REG_GLB_ARM_RST SCI_ADDR(ANA_REGS_GLB_BASE, 0x000C) +#define ANA_REG_GLB_LDO_DCDC_PD_RTCSET SCI_ADDR(ANA_REGS_GLB_BASE, 0x0010) +#define ANA_REG_GLB_LDO_DCDC_PD_RTCCLR SCI_ADDR(ANA_REGS_GLB_BASE, 0x0014) +#define ANA_REG_GLB_RTC_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0018) +#define ANA_REG_GLB_LDO_PD_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x001C) +#define ANA_REG_GLB_LDO_V_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0020) +#define ANA_REG_GLB_LDO_V_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0024) +#define ANA_REG_GLB_LDO_V_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0028) +#define ANA_REG_GLB_LDO_CAL_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x002C) +#define ANA_REG_GLB_LDO_CAL_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0030) +#define ANA_REG_GLB_LDO_CAL_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0034) +#define ANA_REG_GLB_LDO_CAL_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0038) +#define ANA_REG_GLB_LDO_CAL_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x003C) +#define ANA_REG_GLB_LDO_CAL_CTRL5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0040) +#define ANA_REG_GLB_LDO_CAL_CTRL6 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0044) +#define ANA_REG_GLB_AUXAD_CTL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0048) +#define ANA_REG_GLB_DCDC_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x004C) +#define ANA_REG_GLB_DCDC_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0050) +#define ANA_REG_GLB_DCDC_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0054) +#define ANA_REG_GLB_DCDC_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0058) +#define ANA_REG_GLB_DCDC_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x005C) +#define ANA_REG_GLB_DCDC_CTRL5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0060) +#define ANA_REG_GLB_DCDC_CTRL6 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0064) +#define ANA_REG_GLB_DDR2_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0068) +#define ANA_REG_GLB_SLP_WAIT_DCDCARM SCI_ADDR(ANA_REGS_GLB_BASE, 0x006C) +#define ANA_REG_GLB_LDO1828_XTL_CTL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0070) +#define ANA_REG_GLB_LDO_SLP_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0074) +#define ANA_REG_GLB_LDO_SLP_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0078) +#define ANA_REG_GLB_LDO_SLP_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x007C) +#define ANA_REG_GLB_LDO_SLP_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0080) +#define ANA_REG_GLB_AUD_SLP_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0084) +#define ANA_REG_GLB_DCDC_SLP_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0088) +#define ANA_REG_GLB_XTL_WAIT_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x008C) +#define ANA_REG_GLB_FLASH_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0090) +#define ANA_REG_GLB_WHTLED_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0094) +#define ANA_REG_GLB_WHTLED_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0098) +#define ANA_REG_GLB_WHTLED_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x009C) +#define ANA_REG_GLB_ANA_DRV_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A0) +#define ANA_REG_GLB_VIBR_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A4) +#define ANA_REG_GLB_VIBR_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A8) +#define ANA_REG_GLB_VIBR_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00AC) +#define ANA_REG_GLB_VIBR_WR_PROT_VALUE SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B0) +#define ANA_REG_GLB_AUDIO_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B4) +#define ANA_REG_GLB_CHGR_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B8) +#define ANA_REG_GLB_CHGR_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00BC) +#define ANA_REG_GLB_CHGR_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C0) +#define ANA_REG_GLB_CHGR_STATUS SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C4) +#define ANA_REG_GLB_ANA_MIXED_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C8) +#define ANA_REG_GLB_PWR_XTL_EN0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00CC) +#define ANA_REG_GLB_PWR_XTL_EN1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D0) +#define ANA_REG_GLB_PWR_XTL_EN2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D4) +#define ANA_REG_GLB_PWR_XTL_EN3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D8) +#define ANA_REG_GLB_PWR_XTL_EN4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00DC) +#define ANA_REG_GLB_PWR_XTL_EN5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E0) +#define ANA_REG_GLB_ANA_STATUS SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E4) +#define ANA_REG_GLB_POR_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E8) +#define ANA_REG_GLB_WDG_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x00EC) +#define ANA_REG_GLB_POR_PIN_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F0) +#define ANA_REG_GLB_POR_SRC_FLAG SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F4) +#define ANA_REG_GLB_POR_7S_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F8) +#define ANA_REG_GLB_INT_DEBUG SCI_ADDR(ANA_REGS_GLB_BASE, 0x00FC) +#define ANA_REG_GLB_GPI_DEBUG SCI_ADDR(ANA_REGS_GLB_BASE, 0x0100) +#define ANA_REG_GLB_HWRST_RTC SCI_ADDR(ANA_REGS_GLB_BASE, 0x0104) +#define ANA_REG_GLB_CHIP_ID_LOW SCI_ADDR(ANA_REGS_GLB_BASE, 0x0108) +#define ANA_REG_GLB_CHIP_ID_HIGH SCI_ADDR(ANA_REGS_GLB_BASE, 0x010C) +#define ANA_REG_GLB_ARM_MF_REG SCI_ADDR(ANA_REGS_GLB_BASE, 0x0110) +#define ANA_REG_GLB_AFUSE_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0114) +#define ANA_REG_GLB_AFUSE_OUT0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0118) +#define ANA_REG_GLB_AFUSE_OUT1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x011C) +#define ANA_REG_GLB_AFUSE_OUT2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0120) +#define ANA_REG_GLB_AFUSE_OUT3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0124) +#define ANA_REG_GLB_ARCH_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0128) +#define ANA_REG_GLB_MCU_WR_PROT_VALUE SCI_ADDR(ANA_REGS_GLB_BASE, 0x012C) +#define ANA_REG_GLB_MP_MISC_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0148) +#define ANA_REG_GLB_DCDC_CORE_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0160) +#define ANA_REG_GLB_DCDC_ARM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0164) +#define ANA_REG_GLB_DCDC_MEM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0168) +#define ANA_REG_GLB_DCDC_GEN_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x016C) +#define ANA_REG_GLB_DCDC_WRF_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0170) +#define ANA_REG_GLB_DCDC_WPA_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0174) +#define ANA_REG_GLB_DCDC_WPA_DCM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x017C) +#define ANA_REG_GLB_LDO_CAL_SEL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0044) + +/* bits definitions for register ANA_REG_GLB_ARM_MODULE_EN */ +#define BIT_ANA_THM_EN ( BIT(12) ) +#define BIT_ANA_BLTC_EN ( BIT(10) ) +#define BIT_ANA_PINREG_EN ( BIT(9) ) +#define BIT_ANA_FGU_EN ( BIT(8) ) +#define BIT_ANA_GPIO_EN ( BIT(7) ) +#define BIT_ANA_ADC_EN ( BIT(6) ) +#define BIT_ANA_HDT_EN ( BIT(5) ) +#define BIT_ANA_AUD_EN ( BIT(4) ) +#define BIT_ANA_EIC_EN ( BIT(3) ) +#define BIT_ANA_WDG_EN ( BIT(2) ) +#define BIT_ANA_RTC_EN ( BIT(1) ) + +/* bits definitions for register ANA_REG_GLB_ARM_CLK_EN */ +#define BIT_CLK_AUXAD_EN ( BIT(9) ) +#define BIT_CLK_AUXADC_EN ( BIT(8) ) +#define BIT_CLK_AUD_HID_EN ( BIT(5) ) +#define BIT_CLK_AUD_HBD_EN ( BIT(4) ) +#define BIT_CLK_AUD_LOOP_EN ( BIT(3) ) +#define BIT_CLK_AUD_6P5M_EN ( BIT(2) ) +#define BIT_CLK_AUDIF_EN ( BIT(1) ) + +/* bits definitions for register ANA_REG_GLB_RTC_CLK_EN */ +#define BIT_RTC_FLASH_EN ( BIT(13) ) +#define BIT_RTC_THMA_AUTO_EN ( BIT(12) ) +#define BIT_RTC_THMA_EN ( BIT(11) ) +#define BIT_RTC_THM_EN ( BIT(10) ) +#define BIT_RTC_BLTC_EN ( BIT(8) ) +#define BIT_RTC_FGU_EN ( BIT(7) ) +#define BIT_RTC_FGUA_EN ( BIT(6) ) +#define BIT_RTC_VIBR_EN ( BIT(5) ) +#define BIT_RTC_AUD_EN ( BIT(4) ) +#define BIT_RTC_EIC_EN ( BIT(3) ) +#define BIT_RTC_WDG_EN ( BIT(2) ) +#define BIT_RTC_RTC_EN ( BIT(1) ) +#define BIT_RTC_ARCH_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_ARM_RST */ +#define BIT_ANA_THMA_SOFT_RST ( BIT(14) ) +#define BIT_ANA_THM_SOFT_RST ( BIT(13) ) +#define BIT_ANA_AUD_32K_SOFT_RST ( BIT(12) ) +#define BIT_ANA_AUDTX_SOFT_RST ( BIT(11) ) +#define BIT_ANA_AUDRX_SOFT_RST ( BIT(10) ) +#define BIT_ANA_AUD_SOFT_RST ( BIT(9) ) +#define BIT_ANA_AUD_HDT_SOFT_RST ( BIT(8) ) +#define BIT_ANA_GPIO_SOFT_RST ( BIT(7) ) +#define BIT_ANA_ADC_SOFT_RST ( BIT(6) ) +#define BIT_ANA_PWM0_SOFT_RST ( BIT(5) ) +#define BIT_ANA_FGU_SOFT_RST ( BIT(4) ) +#define BIT_ANA_EIC_SOFT_RST ( BIT(3) ) +#define BIT_ANA_WDG_SOFT_RST ( BIT(2) ) +#define BIT_ANA_RTC_SOFT_RST ( BIT(1) ) +#define BIT_ANA_BLTC_SOFT_RST ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_DCDC_PD_RTCSET */ +#define BIT_DCDC_OTP_PD_RTCSET ( BIT(14) ) +#define BIT_DCDC_WRF_PD_RTCSET ( BIT(13) ) +#define BIT_DCDC_GEN_PD_RTCSET ( BIT(12) ) +#define BIT_DCDC_MEM_PD_RTCSET ( BIT(11) ) +#define BIT_DCDC_ARM_PD_RTCSET ( BIT(10) ) +#define BIT_DCDC_CORE_PD_RTCSET ( BIT(9) ) +#define BIT_LDO_EMMCCORE_PD_RTCSET ( BIT(8) ) +#define BIT_LDO_EMMCIO_PD_RTCSET ( BIT(7) ) +#define BIT_LDO_RF2_PD_RTCSET ( BIT(6) ) +#define BIT_LDO_RF1_PD_RTCSET ( BIT(5) ) +#define BIT_LDO_RF0_PD_RTCSET ( BIT(4) ) +#define BIT_LDO_VDD25_PD_RTCSET ( BIT(3) ) +#define BIT_LDO_VDD28_PD_RTCSET ( BIT(2) ) +#define BIT_LDO_VDD18_PD_RTCSET ( BIT(1) ) +#define BIT_BG_PD_RTCSET ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_DCDC_PD_RTCCLR */ +#define BIT_DCDC_OTP_PD_RTCCLR ( BIT(14) ) +#define BIT_DCDC_WRF_PD_RTCCLR ( BIT(13) ) +#define BIT_DCDC_GEN_PD_RTCCLR ( BIT(12) ) +#define BIT_DCDC_MEM_PD_RTCCLR ( BIT(11) ) +#define BIT_DCDC_ARM_PD_RTCCLR ( BIT(10) ) +#define BIT_DCDC_CORE_PD_RTCCLR ( BIT(9) ) +#define BIT_LDO_EMMCCORE_PD_RTCCLR ( BIT(8) ) +#define BIT_LDO_EMMCIO_PD_RTCCLR ( BIT(7) ) +#define BIT_LDO_RF2_PD_RTCCLR ( BIT(6) ) +#define BIT_LDO_RF1_PD_RTCCLR ( BIT(5) ) +#define BIT_LDO_RF0_PD_RTCCLR ( BIT(4) ) +#define BIT_LDO_VDD25_PD_RTCCLR ( BIT(3) ) +#define BIT_LDO_VDD28_PD_RTCCLR ( BIT(2) ) +#define BIT_LDO_VDD18_PD_RTCCLR ( BIT(1) ) +#define BIT_BG_PD_RTCCLR ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_RTC_CTRL */ +#define BITS_XOSC32K_CTL_STS(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BIT_XOSC32K_CTL_B3_RTCCLR ( BIT(7) ) +#define BIT_XOSC32K_CTL_B2_RTCCLR ( BIT(6) ) +#define BIT_XOSC32K_CTL_B1_RTCCLR ( BIT(5) ) +#define BIT_XOSC32K_CTL_B0_RTCCLR ( BIT(4) ) +#define BIT_XOSC32K_CTL_B3_RTCSET ( BIT(3) ) +#define BIT_XOSC32K_CTL_B2_RTCSET ( BIT(2) ) +#define BIT_XOSC32K_CTL_B1_RTCSET ( BIT(1) ) +#define BIT_XOSC32K_CTL_B0_RTCSET ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_PD_CTRL */ +#define BIT_LDO_LPREF_PD_SW ( BIT(12) ) +#define BIT_DCDC_WPA_PD ( BIT(11) ) +#define BIT_LDO_CLSG_PD ( BIT(10) ) +#define BIT_LDO_USB_PD ( BIT(9) ) +#define BIT_LDO_CAMMOT_PD ( BIT(8) ) +#define BIT_LDO_CAMIO_PD ( BIT(7) ) +#define BIT_LDO_CAMD_PD ( BIT(6) ) +#define BIT_LDO_CAMA_PD ( BIT(5) ) +#define BIT_LDO_SIM2_PD ( BIT(4) ) +#define BIT_LDO_SIM1_PD ( BIT(3) ) +#define BIT_LDO_SIM0_PD ( BIT(2) ) +#define BIT_LDO_SD_PD ( BIT(1) ) +#define BIT_LDO_AVDD18_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL0 */ +#define BITS_LDO_EMMCCORE_V(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_LDO_EMMCIO_V(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_LDO_RF2_V(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_LDO_RF1_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_LDO_RF0_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_LDO_VDD25_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_LDO_VDD28_V(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_LDO_VDD18_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL1 */ +#define BITS_LDO_SIM2_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_LDO_SIM1_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_LDO_SIM0_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_LDO_SD_V(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_LDO_AVDD18_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL2 */ +#define BITS_VBATBK_RES(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_VBATBK_V(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_LDO_CLSG_V(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_LDO_USB_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_LDO_CAMMOT_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_LDO_CAMIO_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_LDO_CAMD_V(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_LDO_CAMA_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL0 */ +#define BITS_LDO_VDD25_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_VDD28_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_VDD18_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL1 */ +#define BITS_LDO_RF2_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_RF1_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_RF0_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL2 */ +#define BITS_LDO_USB_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_EMMCCORE_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_EMMCIO_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL3 */ +#define BITS_LDO_SD_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_AVDD18_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL4 */ +#define BITS_LDO_CAMA_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_SIM2_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_SIM_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL5 */ +#define BITS_LDO_CAMMOT_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_CAMIO_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_CAMD_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL6 */ +#define BITS_LDOA_CAL_SEL(_x_) ( (_x_) << 11 & (BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_LDOD_CAL_SEL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_LDODCDC_CAL_SEL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_LDO_CLSG_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_AUXAD_CTL */ +#define BIT_AUXAD_CURRENTSEN_EN ( BIT(6) ) +#define BIT_AUXAD_CURRENTSEL ( BIT(5) ) +#define BITS_AUXAD_CURRENT_IBS(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL0 */ +#define BIT_DCDC_CORE_LP_EN ( BIT(15) ) +#define BIT_DCDC_CORE_CL_CTRL ( BIT(14) ) +#define BITS_DCDC_CORE_PDRSLOW(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_DCDC_CORE_PFM ( BIT(9) ) +#define BIT_DCDC_CORE_DCM ( BIT(8) ) +#define BIT_DCDC_ARM_LP_EN ( BIT(7) ) +#define BIT_DCDC_ARM_CL_CTRL ( BIT(6) ) +#define BITS_DCDC_ARM_PDRSLOW(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) +#define BIT_DCDC_ARM_PFM ( BIT(1) ) +#define BIT_DCDC_ARM_DCM ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL1 */ +#define BIT_DCDC_MEM_LP_EN ( BIT(15) ) +#define BIT_DCDC_MEM_CL_CTRL ( BIT(14) ) +#define BITS_DCDC_MEM_PDRSLOW(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_DCDC_MEM_PFM ( BIT(9) ) +#define BIT_DCDC_MEM_DCM ( BIT(8) ) +#define BIT_DCDC_GEN_LP_EN ( BIT(7) ) +#define BIT_DCDC_GEN_CL_CTRL ( BIT(6) ) +#define BITS_DCDC_GEN_PDRSLOW(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) +#define BIT_DCDC_GEN_PFM ( BIT(1) ) +#define BIT_DCDC_GEN_DCM ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL2 */ +#define BIT_DCDC_BG_LP_EN ( BIT(15) ) +#define BIT_DCDC_OTP_CHIP_PD_FLAG_CLR ( BIT(14) ) +#define BIT_DCDC_OTP_CHIP_PD_FLAG ( BIT(13) ) +#define BIT_DCDC_OTP_AUTO_PD_EN ( BIT(12) ) +#define BIT_DCDC_OTP_VBEOP ( BIT(11) ) +#define BITS_DCDC_OTP_S(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BIT_DCDC_WRF_LP_EN ( BIT(7) ) +#define BIT_DCDC_WRF_CL_CTRL ( BIT(6) ) +#define BITS_DCDC_WRF_PDRSLOW(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) +#define BIT_DCDC_WRF_PFM ( BIT(1) ) +#define BIT_DCDC_WRF_DCM ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL3 */ +#define BIT_DCDC_WPA_LP_EN ( BIT(8) ) +#define BIT_DCDC_WPA_CL_CTRL ( BIT(7) ) +#define BIT_DCDC_WPA_ZXOP ( BIT(6) ) +#define BITS_DCDC_WPA_PDRSLOW(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) +#define BIT_DCDC_WPA_PFM ( BIT(1) ) +#define BIT_DCDC_WPA_APTEN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL4 */ +#define BIT_DCDC_CORE_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_CORE_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_CORE_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_CORE_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_ARM_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_ARM_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_ARM_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_ARM_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL5 */ +#define BIT_DCDC_MEM_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_MEM_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_MEM_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_MEM_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_GEN_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_GEN_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_GEN_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_GEN_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL6 */ +#define BIT_DCDC_WPA_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_WPA_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_WPA_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_WPA_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_WRF_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_WRF_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_WRF_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_WRF_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DDR2_CTRL */ +#define BIT_DDR2_BUF_PD_HW ( BIT(9) ) +#define BITS_DDR2_BUF_S_DS(_x_) ( (_x_) << 7 & (BIT(7)|BIT(8)) ) +#define BITS_DDR2_BUF_CHNS_DS(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)) ) +#define BIT_DDR2_BUF_PD ( BIT(4) ) +#define BITS_DDR2_BUF_S(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DDR2_BUF_CHNS(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_SLP_WAIT_DCDCARM */ +#define BITS_SLP_IN_WAIT_DCDCARM(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_SLP_OUT_WAIT_DCDCARM(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO1828_XTL_CTL */ +#define BIT_LDO_VDD18_EXT_XTL2_EN ( BIT(11) ) +#define BIT_LDO_VDD18_EXT_XTL1_EN ( BIT(10) ) +#define BIT_LDO_VDD18_EXT_XTL0_EN ( BIT(9) ) +#define BIT_LDO_VDD18_XTL2_EN ( BIT(8) ) +#define BIT_LDO_VDD18_XTL1_EN ( BIT(7) ) +#define BIT_LDO_VDD18_XTL0_EN ( BIT(6) ) +#define BIT_LDO_VDD28_EXT_XTL2_EN ( BIT(5) ) +#define BIT_LDO_VDD28_EXT_XTL1_EN ( BIT(4) ) +#define BIT_LDO_VDD28_EXT_XTL0_EN ( BIT(3) ) +#define BIT_LDO_VDD28_XTL2_EN ( BIT(2) ) +#define BIT_LDO_VDD28_XTL1_EN ( BIT(1) ) +#define BIT_LDO_VDD28_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SLP_CTRL0 */ +#define BIT_SLP_IO_EN ( BIT(15) ) +#define BIT_SLP_DCDC_OTP_PD_EN ( BIT(13) ) +#define BIT_SLP_DCDCGEN_PD_EN ( BIT(12) ) +#define BIT_SLP_DCDCWPA_PD_EN ( BIT(11) ) +#define BIT_SLP_DCDCWRF_PD_EN ( BIT(10) ) +#define BIT_SLP_DCDCARM_PD_EN ( BIT(9) ) +#define BIT_SLP_LDOEMMCCORE_PD_EN ( BIT(7) ) +#define BIT_SLP_LDOEMMCIO_PD_EN ( BIT(6) ) +#define BIT_SLP_LDORF2_PD_EN ( BIT(5) ) +#define BIT_SLP_LDORF1_PD_EN ( BIT(4) ) +#define BIT_SLP_LDORF0_PD_EN ( BIT(3) ) +#define BIT_SLP_LDOVDD25_PD_EN ( BIT(2) ) +#define BIT_SLP_LDOVDD28_PD_EN ( BIT(1) ) +#define BIT_SLP_LDOVDD18_PD_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SLP_CTRL1 */ +#define BIT_SLP_LDO_PD_EN ( BIT(12) ) +#define BIT_SLP_LDOLPREF_PD_EN ( BIT(11) ) +#define BIT_SLP_LDOCLSG_PD_EN ( BIT(10) ) +#define BIT_SLP_LDOUSB_PD_EN ( BIT(9) ) +#define BIT_SLP_LDOCAMMOT_PD_EN ( BIT(8) ) +#define BIT_SLP_LDOCAMIO_PD_EN ( BIT(7) ) +#define BIT_SLP_LDOCAMD_PD_EN ( BIT(6) ) +#define BIT_SLP_LDOCAMA_PD_EN ( BIT(5) ) +#define BIT_SLP_LDOSIM2_PD_EN ( BIT(4) ) +#define BIT_SLP_LDOSIM1_PD_EN ( BIT(3) ) +#define BIT_SLP_LDOSIM0_PD_EN ( BIT(2) ) +#define BIT_SLP_LDOSD_PD_EN ( BIT(1) ) +#define BIT_SLP_LDOAVDD18_PD_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SLP_CTRL2 */ +#define BIT_SLP_DCDC_BG_LP_EN ( BIT(15) ) +#define BIT_SLP_DCDCCORE_LP_EN ( BIT(11) ) +#define BIT_SLP_DCDCMEM_LP_EN ( BIT(10) ) +#define BIT_SLP_DCDCARM_LP_EN ( BIT(9) ) +#define BIT_SLP_DCDCGEN_LP_EN ( BIT(8) ) +#define BIT_SLP_DCDCWPA_LP_EN ( BIT(6) ) +#define BIT_SLP_DCDCWRF_LP_EN ( BIT(5) ) +#define BIT_SLP_LDOEMMCCORE_LP_EN ( BIT(4) ) +#define BIT_SLP_LDOEMMCIO_LP_EN ( BIT(3) ) +#define BIT_SLP_LDORF2_LP_EN ( BIT(2) ) +#define BIT_SLP_LDORF1_LP_EN ( BIT(1) ) +#define BIT_SLP_LDORF0_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SLP_CTRL3 */ +#define BIT_SLP_BG_LP_EN ( BIT(15) ) +#define BIT_SLP_LDOVDD25_LP_EN ( BIT(13) ) +#define BIT_SLP_LDOVDD28_LP_EN ( BIT(12) ) +#define BIT_SLP_LDOVDD18_LP_EN ( BIT(11) ) +#define BIT_SLP_LDOCLSG_LP_EN ( BIT(10) ) +#define BIT_SLP_LDOUSB_LP_EN ( BIT(9) ) +#define BIT_SLP_LDOCAMMOT_LP_EN ( BIT(8) ) +#define BIT_SLP_LDOCAMIO_LP_EN ( BIT(7) ) +#define BIT_SLP_LDOCAMD_LP_EN ( BIT(6) ) +#define BIT_SLP_LDOCAMA_LP_EN ( BIT(5) ) +#define BIT_SLP_LDOSIM2_LP_EN ( BIT(4) ) +#define BIT_SLP_LDOSIM1_LP_EN ( BIT(3) ) +#define BIT_SLP_LDOSIM0_LP_EN ( BIT(2) ) +#define BIT_SLP_LDOSD_LP_EN ( BIT(1) ) +#define BIT_SLP_LDOAVDD18_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_AUD_SLP_CTRL4 */ +#define BIT_SLP_AUD_PA_SW_PD_EN ( BIT(15) ) +#define BIT_SLP_AUD_PA_LDO_PD_EN ( BIT(14) ) +#define BIT_SLP_AUD_PA_PD_EN ( BIT(13) ) +#define BIT_SLP_AUD_OVP_PD_PD_EN ( BIT(9) ) +#define BIT_SLP_AUD_OVP_LDO_PD_EN ( BIT(8) ) +#define BIT_SLP_AUD_VB_PD_EN ( BIT(7) ) +#define BIT_SLP_AUD_VBO_PD_EN ( BIT(6) ) +#define BIT_SLP_AUD_HEADMICBIAS_PD_EN ( BIT(5) ) +#define BIT_SLP_AUD_MICBIAS_HV_PD_EN ( BIT(2) ) +#define BIT_SLP_AUD_HEADMIC_PD_EN ( BIT(1) ) +#define BIT_SLP_AUD_PMUR1_PD_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL */ +#define BITS_SLP_DCDCCORE_VOL_DROP_CNT(_x_)( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DCDC_CORE_CTL_DS(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register ANA_REG_GLB_XTL_WAIT_CTRL */ +#define BIT_SLP_XTLBUF_PD_EN ( BIT(9) ) +#define BIT_XTL_EN ( BIT(8) ) +#define BITS_XTL_WAIT(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_FLASH_CTRL */ +#define BIT_FLASH_PON ( BIT(15) ) +#define BIT_FLASH_V_HW_EN ( BIT(6) ) +#define BITS_FLASH_V_HW_STEP(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_FLASH_V_SW(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register ANA_REG_GLB_WHTLED_CTRL0 */ +#define BIT_WHTLED_PD_STS ( BIT(15) ) +#define BITS_WHTLED_DC(_x_) ( (_x_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BIT_WHTLED_BOOST_EN ( BIT(8) ) +#define BIT_WHTLED_SERIES_EN ( BIT(7) ) +#define BITS_WHTLED_V(_x_) ( (_x_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_WHTLED_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_WHTLED_CTRL1 */ +#define BIT_LCM_CABC_PWM_SEL ( BIT(15) ) +#define BIT_RTC_PWM0_EN ( BIT(14) ) +#define BIT_PWM0_EN ( BIT(13) ) +#define BITS_WHTLED_ISET(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_WHTLED_FRE_AD(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)) ) +#define BITS_WHTLED_CLMIT_OP(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_WHTLED_CTRL2 */ +#define BIT_WHTLED_DIMMING_SEL ( BIT(15) ) +#define BIT_WHTLED_PD_SEL ( BIT(14) ) +#define BIT_WHTLED_DIS_OVST ( BIT(13) ) +#define BIT_WHTLED_DIM_SEL ( BIT(12) ) +#define BIT_WHTLED_DE_BIAS ( BIT(11) ) +#define BIT_WHTLED_BUFF_SHT ( BIT(10) ) +#define BITS_WHTLED_STB_OP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_WHTLED_CAP_OPTION ( BIT(7) ) +#define BIT_WHTLED_OVP_DIS ( BIT(6) ) +#define BITS_WHTLED_REF_DC(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register ANA_REG_GLB_ANA_DRV_CTRL */ +#define BIT_SLP_RGB_PD_EN ( BIT(14) ) +#define BIT_RGB_PD_HW_EN ( BIT(13) ) +#define BITS_RGB_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BITS_KPLED_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_RGB_PD_SW ( BIT(2) ) +#define BIT_KPLED_PD ( BIT(1) ) +#define BIT_KPLED_PD_STS ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_VIBR_CTRL0 */ +#define BITS_VIBR_STABLE_V_HW(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_VIBR_INIT_V_HW(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_VIBR_V_SW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_VIBR_PON ( BIT(2) ) +#define BIT_VIBR_SW_EN ( BIT(1) ) + +/* bits definitions for register ANA_REG_GLB_VIBR_CTRL1 */ +#define BITS_VIBR_V_CONVERT_CNT_HW(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_VIBR_CTRL2 */ +#define BIT_VIBR_PWR_ON_STS ( BIT(15) ) +#define BIT_VIBR_HW_FLOW_ERR1 ( BIT(14) ) +#define BIT_VIBR_HW_FLOW_ERR1_CLR ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_VIBR_WR_PROT_VALUE */ +#define BIT_VIBR_WR_PROT ( BIT(15) ) +#define BITS_VIBR_WR_PROT_VALUE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_AUDIO_CTRL */ +#define BIT_AUD_SLP_APP_RST_EN ( BIT(10) ) +#define BITS_CLK_AUD_HBD_DIV(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BIT_CLK_AUD_LOOP_INV_EN ( BIT(4) ) +#define BIT_CLK_AUDIF_TX_INV_EN ( BIT(3) ) +#define BIT_CLK_AUDIF_RX_INV_EN ( BIT(2) ) +#define BIT_CLK_AUD_6P5M_TX_INV_EN ( BIT(1) ) +#define BIT_CLK_AUD_6P5M_RX_INV_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL0 */ +#define BIT_CHGR_PD_STS ( BIT(15) ) +#define BITS_CHGR_CV_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CHGR_END_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CHG_PUMP_V(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BIT_CHGR_PD_RTCCLR ( BIT(1) ) +#define BIT_CHGR_PD_RTCSET ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL1 */ +#define BIT_DP_DM_SW_EN ( BIT(15) ) +#define BITS_CHGR_CC_I(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_VBAT_OVP_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_VCHG_OVP_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL2 */ +#define BITS_CHG_PUMP_CAL(_x_) ( (_x_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_CHG_PUMP_PD ( BIT(8) ) +#define BIT_CHGR_CC_EN ( BIT(1) ) +#define BIT_RECHG ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_STATUS */ +#define BIT_CHG_DET_DONE ( BIT(11) ) +#define BIT_DP_LOW ( BIT(10) ) +#define BIT_DCP_DET ( BIT(9) ) +#define BIT_CHG_DET ( BIT(8) ) +#define BIT_SDP_INT ( BIT(7) ) +#define BIT_DCP_INT ( BIT(6) ) +#define BIT_CDP_INT ( BIT(5) ) +#define BIT_CHGR_CV_STATUS ( BIT(4) ) +#define BIT_CHGR_ON ( BIT(3) ) +#define BIT_CHGR_INT ( BIT(2) ) +#define BIT_VBAT_OVI ( BIT(1) ) +#define BIT_VCHG_OVI ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_ANA_MIXED_CTRL */ +#define BIT_PTEST_PD_RTCSET ( BIT(15) ) +#define BIT_THM_CHIP_PD_FLAG ( BIT(8) ) +#define BIT_THM_CHIP_PD_FLAG_CLR ( BIT(7) ) +#define BITS_THM_CAL_SEL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)) ) +#define BIT_THM_AUTO_PD_EN ( BIT(4) ) +#define BIT_BG_LP_EN ( BIT(3) ) +#define BITS_UVHO_T(_x_) ( (_x_) << 1 & (BIT(1)|BIT(2)) ) +#define BIT_UVHO_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN0 */ +#define BIT_LDO_XTL_EN ( BIT(15) ) +#define BIT_LDO_RF1_EXT_XTL2_EN ( BIT(11) ) +#define BIT_LDO_RF1_EXT_XTL1_EN ( BIT(10) ) +#define BIT_LDO_RF1_EXT_XTL0_EN ( BIT(9) ) +#define BIT_LDO_RF1_XTL2_EN ( BIT(8) ) +#define BIT_LDO_RF1_XTL1_EN ( BIT(7) ) +#define BIT_LDO_RF1_XTL0_EN ( BIT(6) ) +#define BIT_LDO_RF0_EXT_XTL2_EN ( BIT(5) ) +#define BIT_LDO_RF0_EXT_XTL1_EN ( BIT(4) ) +#define BIT_LDO_RF0_EXT_XTL0_EN ( BIT(3) ) +#define BIT_LDO_RF0_XTL2_EN ( BIT(2) ) +#define BIT_LDO_RF0_XTL1_EN ( BIT(1) ) +#define BIT_LDO_RF0_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN1 */ +#define BIT_LDO_VDD25_EXT_XTL2_EN ( BIT(11) ) +#define BIT_LDO_VDD25_EXT_XTL1_EN ( BIT(10) ) +#define BIT_LDO_VDD25_EXT_XTL0_EN ( BIT(9) ) +#define BIT_LDO_VDD25_XTL2_EN ( BIT(8) ) +#define BIT_LDO_VDD25_XTL1_EN ( BIT(7) ) +#define BIT_LDO_VDD25_XTL0_EN ( BIT(6) ) +#define BIT_LDO_RF2_EXT_XTL2_EN ( BIT(5) ) +#define BIT_LDO_RF2_EXT_XTL1_EN ( BIT(4) ) +#define BIT_LDO_RF2_EXT_XTL0_EN ( BIT(3) ) +#define BIT_LDO_RF2_XTL2_EN ( BIT(2) ) +#define BIT_LDO_RF2_XTL1_EN ( BIT(1) ) +#define BIT_LDO_RF2_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN2 */ +#define BIT_LDO_AVDD18_EXT_XTL2_EN ( BIT(11) ) +#define BIT_LDO_AVDD18_EXT_XTL1_EN ( BIT(10) ) +#define BIT_LDO_AVDD18_EXT_XTL0_EN ( BIT(9) ) +#define BIT_LDO_AVDD18_XTL2_EN ( BIT(8) ) +#define BIT_LDO_AVDD18_XTL1_EN ( BIT(7) ) +#define BIT_LDO_AVDD18_XTL0_EN ( BIT(6) ) +#define BIT_LDO_SIM2_EXT_XTL2_EN ( BIT(5) ) +#define BIT_LDO_SIM2_EXT_XTL1_EN ( BIT(4) ) +#define BIT_LDO_SIM2_EXT_XTL0_EN ( BIT(3) ) +#define BIT_LDO_SIM2_XTL2_EN ( BIT(2) ) +#define BIT_LDO_SIM2_XTL1_EN ( BIT(1) ) +#define BIT_LDO_SIM2_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN3 */ +#define BIT_DCDC_BG_EXT_XTL2_EN ( BIT(11) ) +#define BIT_DCDC_BG_EXT_XTL1_EN ( BIT(10) ) +#define BIT_DCDC_BG_EXT_XTL0_EN ( BIT(9) ) +#define BIT_DCDC_BG_XTL2_EN ( BIT(8) ) +#define BIT_DCDC_BG_XTL1_EN ( BIT(7) ) +#define BIT_DCDC_BG_XTL0_EN ( BIT(6) ) +#define BIT_BG_EXT_XTL2_EN ( BIT(5) ) +#define BIT_BG_EXT_XTL1_EN ( BIT(4) ) +#define BIT_BG_EXT_XTL0_EN ( BIT(3) ) +#define BIT_BG_XTL2_EN ( BIT(2) ) +#define BIT_BG_XTL1_EN ( BIT(1) ) +#define BIT_BG_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN4 */ +#define BIT_DCDC_WRF_XTL2_EN ( BIT(14) ) +#define BIT_DCDC_WRF_XTL1_EN ( BIT(13) ) +#define BIT_DCDC_WRF_XTL0_EN ( BIT(12) ) +#define BIT_DCDC_WPA_XTL2_EN ( BIT(11) ) +#define BIT_DCDC_WPA_XTL1_EN ( BIT(10) ) +#define BIT_DCDC_WPA_XTL0_EN ( BIT(9) ) +#define BIT_DCDC_MEM_XTL2_EN ( BIT(8) ) +#define BIT_DCDC_MEM_XTL1_EN ( BIT(7) ) +#define BIT_DCDC_MEM_XTL0_EN ( BIT(6) ) +#define BIT_DCDC_GEN_XTL2_EN ( BIT(5) ) +#define BIT_DCDC_GEN_XTL1_EN ( BIT(4) ) +#define BIT_DCDC_GEN_XTL0_EN ( BIT(3) ) +#define BIT_DCDC_CORE_XTL2_EN ( BIT(2) ) +#define BIT_DCDC_CORE_XTL1_EN ( BIT(1) ) +#define BIT_DCDC_CORE_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN5 */ +#define BIT_DCDC_WRF_EXT_XTL2_EN ( BIT(14) ) +#define BIT_DCDC_WRF_EXT_XTL1_EN ( BIT(13) ) +#define BIT_DCDC_WRF_EXT_XTL0_EN ( BIT(12) ) +#define BIT_DCDC_WPA_EXT_XTL2_EN ( BIT(11) ) +#define BIT_DCDC_WPA_EXT_XTL1_EN ( BIT(10) ) +#define BIT_DCDC_WPA_EXT_XTL0_EN ( BIT(9) ) +#define BIT_DCDC_MEM_EXT_XTL2_EN ( BIT(8) ) +#define BIT_DCDC_MEM_EXT_XTL1_EN ( BIT(7) ) +#define BIT_DCDC_MEM_EXT_XTL0_EN ( BIT(6) ) +#define BIT_DCDC_GEN_EXT_XTL2_EN ( BIT(5) ) +#define BIT_DCDC_GEN_EXT_XTL1_EN ( BIT(4) ) +#define BIT_DCDC_GEN_EXT_XTL0_EN ( BIT(3) ) +#define BIT_DCDC_CORE_EXT_XTL2_EN ( BIT(2) ) +#define BIT_DCDC_CORE_EXT_XTL1_EN ( BIT(1) ) +#define BIT_DCDC_CORE_EXT_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_ANA_STATUS */ +#define BIT_BONDOPT5 ( BIT(5) ) +#define BIT_BONDOPT4 ( BIT(4) ) +#define BIT_BONDOPT3 ( BIT(3) ) +#define BIT_BONDOPT2 ( BIT(2) ) +#define BIT_BONDOPT1 ( BIT(1) ) +#define BIT_BONDOPT0 ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_POR_RST_MONITOR */ +#define BITS_POR_RST_MONITOR(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_WDG_RST_MONITOR */ +#define BITS_WDG_RST_MONITOR(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_POR_PIN_RST_MONITOR */ +#define BITS_POR_PIN_RST_MONITOR(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_POR_SRC_FLAG */ +#define BIT_POR_SW_FORCE_ON ( BIT(15) ) +#define BITS_POR_SRC_FLAG(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_POR_7S_CTRL */ +#define BIT_PBINT_7S_FLAG_CLR ( BIT(15) ) +#define BIT_EXT_RSTN_FLAG_CLR ( BIT(14) ) +#define BIT_CHGR_INT_FLAG_CLR ( BIT(13) ) +#define BIT_PBINT2_FLAG_CLR ( BIT(12) ) +#define BIT_PBINT_FLAG_CLR ( BIT(11) ) +#define BIT_PBINT_7S_RST_SWMODE_RTCSTS ( BIT(10) ) +#define BIT_PBINT_7S_RST_SWMODE_RTCCLR ( BIT(9) ) +#define BIT_PBINT_7S_RST_SWMODE_RTCSET ( BIT(8) ) +#define BITS_PBINT_7S_RST_THRESHOLD(_x_)( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_PBINT_7S_RST_DISABLE ( BIT(3) ) +#define BIT_PBINT_7S_RST_MODE_RTCSTS ( BIT(2) ) +#define BIT_PBINT_7S_RST_MODE_RTCCLR ( BIT(1) ) +#define BIT_PBINT_7S_RST_MODE_RTCSET ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_INT_DEBUG */ +#define BIT_OTP_INT_DEB ( BIT(10) ) +#define BIT_THM_INT_DEB ( BIT(9) ) +#define BIT_AUD_PROT_INT_DEB ( BIT(8) ) +#define BIT_AUD_HEADBTN_INT_DEB ( BIT(7) ) +#define BIT_EIC_INT_DEB ( BIT(6) ) +#define BIT_FGU_INT_DEB ( BIT(5) ) +#define BIT_WDG_INT_DEB ( BIT(4) ) +#define BIT_RTC_INT_DEB ( BIT(3) ) +#define BIT_GPIO_INT_DEB ( BIT(2) ) +#define BIT_ADC_INT_DEB ( BIT(1) ) +#define BIT_INT_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_GPI_DEBUG */ +#define BIT_HEAD_INSERT2_DEB ( BIT(9) ) +#define BIT_HEAD_INSERT_DEB ( BIT(8) ) +#define BIT_HEAD_BUTTON_DEB ( BIT(7) ) +#define BIT_PBINT2_DEB ( BIT(6) ) +#define BIT_PBINT_DEB ( BIT(5) ) +#define BIT_VCHG_OVI_DEB ( BIT(4) ) +#define BIT_VBAT_OVI_DEB ( BIT(3) ) +#define BIT_CHGR_INT_DEB ( BIT(2) ) +#define BIT_GPI_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_HWRST_RTC */ +#define BITS_HWRST_RTC_REG_STS(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_HWRST_RTC_REG_SET(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_CHIP_ID_LOW */ +#define BITS_CHIP_ID_LOW(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_CHIP_ID_HIGH */ +#define BITS_CHIP_ID_HIGH(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_ARM_MF_REG */ +#define BITS_ARM_MF_REG(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_AFUSE_CTRL */ +#define BIT_AFUSE_READ_REQ ( BIT(7) ) +#define BITS_AFUSE_READ_DLY(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) + +/* bits definitions for register ANA_REG_GLB_AFUSE_OUT0 */ +#define BITS_AFUSE_OUT0(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_AFUSE_OUT1 */ +#define BITS_AFUSE_OUT1(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_AFUSE_OUT2 */ +#define BITS_AFUSE_OUT2(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_AFUSE_OUT3 */ +#define BITS_AFUSE_OUT3(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_ARCH_EN */ +#define BIT_ARCH_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_MCU_WR_PROT_VALUE */ +#define BIT_MCU_WR_PROT ( BIT(15) ) +#define BITS_MCU_WR_PROT_VALUE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CORE_ADI */ +#define BITS_DCDC_CORE_CTL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DCDC_CORE_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_ARM_ADI */ +#define BITS_DCDC_ARM_CTL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DCDC_ARM_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_MEM_ADI */ +#define BIT_DCDC_MEM_CTL_ADI ( BIT(5) ) +#define BITS_DCDC_MEM_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_GEN_ADI */ +#define BITS_DCDC_GEN_CTL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DCDC_GEN_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_WRF_ADI */ +#define BITS_DCDC_WRF_CTL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)) ) +#define BITS_DCDC_WRF_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_WPA_ADI */ +#define BITS_DCDC_WPA_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_WPA_DCM_ADI */ +#define BIT_DCDC_WPA_DCM_ADI ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_SEL */ +#define BIT_LDO_CAMIO_CAL_EN ( BIT(5) ) +#define BIT_LDO_CLSG_CAL_EN ( BIT(6) ) +#define BITS_LDO_CAMD_CAL_EN(_x_) ( (_x_) & (BIT(5)|BIT(6)) ) +#define BIT_LDO_EMMCIO_CAL_EN ( BIT(7) ) +#define BITS_LDO_AVDD18_CAL_EN(_x_) ( (_x_) & (BIT(5)|BIT(7)) ) +#define BITS_LDO_VDD18_CAL_EN(_x_) ( (_x_) & (BIT(6)|BIT(7)) ) +#define BIT_LDO_SIM0_CAL_EN ( BIT(9) ) +#define BIT_LDO_SIM1_CAL_EN ( BIT(9) ) +#define BITS_LDO_SIM2_CAL_EN(_x_) ( (_x_) & (BIT(8)|BIT(9)) ) +#define BIT_LDO_EMMCCORE_CAL_EN ( BIT(10) ) +#define BITS_LDO_VDD28_CAL_EN(_x_) ( (_x_) & (BIT(8)|BIT(10)) ) +#define BITS_LDO_VDD25_CAL_EN(_x_) ( (_x_) & (BIT(9)|BIT(10)) ) +#define BITS_LDO_USB_CAL_EN(_x_) ( (_x_) & (BIT(8)|BIT(9)|BIT(10)) ) +#define BIT_LDO_SD_CAL_EN ( BIT(11) ) +#define BIT_LDO_CAMA_CAL_EN ( BIT(12) ) +#define BITS_LDO_RF2_CAL_EN(_x_) ( (_x_) & (BIT(11)|BIT(12)) ) +#define BIT_LDO_RF1_CAL_EN ( BIT(13) ) +#define BITS_LDO_RF0_CAL_EN(_x_) ( (_x_) & (BIT(11)|BIT(13)) ) +#define BITS_LDO_CAMMOT_CAL_EN(_x_) ( (_x_) & (BIT(12)|BIT(13)) ) +#define BITS_LDO_CAL_SEL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +#define SHFT_LDO_CAL_SEL ( 5 ) +#define MASK_LDO_CAL_SEL ( BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13) ) + +/* vars definitions for controller ANA_REGS_GLB */ + +#endif //__ANA_REGS_GLB_H__ diff --git a/include/soc/sprd/chip_x35lt8/__regs_ana_sc2723_glb.h b/include/soc/sprd/chip_x35lt8/__regs_ana_sc2723_glb.h new file mode 100755 index 00000000..fe9cd745 --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_ana_sc2723_glb.h @@ -0,0 +1,952 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __ANA_REGS_GLB_H__ +#define __ANA_REGS_GLB_H__ + +#define ANA_REGS_GLB + +/* registers definitions for controller ANA_REGS_GLB */ +#define ANA_REG_GLB_ARM_MODULE_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0000) +#define ANA_REG_GLB_ARM_CLK_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0004) +#define ANA_REG_GLB_RTC_CLK_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0008) +#define ANA_REG_GLB_ARM_RST SCI_ADDR(ANA_REGS_GLB_BASE, 0x000C) +#define ANA_REG_GLB_LDO_DCDC_PD SCI_ADDR(ANA_REGS_GLB_BASE, 0x0010) +#define ANA_REG_GLB_LDO_PD_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0014) +#define ANA_REG_GLB_LDO_V_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0018) +#define ANA_REG_GLB_LDO_V_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x001C) +#define ANA_REG_GLB_LDO_V_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0020) +#define ANA_REG_GLB_LDO_V_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0024) +#define ANA_REG_GLB_LDO_V_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0028) +#define ANA_REG_GLB_LDO_V_CTRL5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x002C) +#define ANA_REG_GLB_LDO_V_CTRL6 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0030) +#define ANA_REG_GLB_LDO_V_CTRL7 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0034) +#define ANA_REG_GLB_LDO_V_CTRL8 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0038) +#define ANA_REG_GLB_LDO_V_CTRL9 SCI_ADDR(ANA_REGS_GLB_BASE, 0x003C) +#define ANA_REG_GLB_LDO_V_CTRL10 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0040) +#define ANA_REG_GLB_LDO_V_CTRL11 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0044) +#define ANA_REG_GLB_LDO_LP_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0048) +#define ANA_REG_GLB_DCDC_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x004C) +#define ANA_REG_GLB_DCDC_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0050) +#define ANA_REG_GLB_DCDC_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0054) +#define ANA_REG_GLB_DCDC_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0058) +#define ANA_REG_GLB_DCDC_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x005C) +#define ANA_REG_GLB_DCDC_CTRL5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0060) +#define ANA_REG_GLB_DCDC_CTRL6 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0064) +#define ANA_REG_GLB_DCDC_CTRL7 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0068) +#define ANA_REG_GLB_DCDC_CTRL8 SCI_ADDR(ANA_REGS_GLB_BASE, 0x006C) +#define ANA_REG_GLB_DCDC_CTRL9 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0070) +#define ANA_REG_GLB_DCDC_CTRL10 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0074) +#define ANA_REG_GLB_DCDC_CTRL11 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0078) +#define ANA_REG_GLB_DCDC_CTRL12 SCI_ADDR(ANA_REGS_GLB_BASE, 0x007C) +#define ANA_REG_GLB_DCDC_CTRL13 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0080) +#define ANA_REG_GLB_DCDC_CTRL14 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0084) +#define ANA_REG_GLB_DCDC_CTRL15 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0088) +#define ANA_REG_GLB_SLP_WAIT_DCDCARM SCI_ADDR(ANA_REGS_GLB_BASE, 0x008C) +#define ANA_REG_GLB_PWR_SLP_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0090) +#define ANA_REG_GLB_PWR_SLP_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0094) +#define ANA_REG_GLB_PWR_SLP_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0098) +#define ANA_REG_GLB_PWR_SLP_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x009C) +#define ANA_REG_GLB_PWR_SLP_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A0) +#define ANA_REG_GLB_AUD_SLP_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A4) +#define ANA_REG_GLB_DCDC_SLP_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A8) +#define ANA_REG_GLB_DCDC_SLP_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00AC) +#define ANA_REG_GLB_DCDC_SLP_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B0) +#define ANA_REG_GLB_DCDC_SLP_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B4) +#define ANA_REG_GLB_DCDC_SLP_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B8) +#define ANA_REG_GLB_DCDC_SLP_CTRL5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00BC) +#define ANA_REG_GLB_PWR_SEL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C0) +#define ANA_REG_GLB_PWR_XTL_EN0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C4) +#define ANA_REG_GLB_PWR_XTL_EN1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C8) +#define ANA_REG_GLB_PWR_XTL_EN2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00CC) +#define ANA_REG_GLB_PWR_XTL_EN3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D0) +#define ANA_REG_GLB_32KLESS_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D4) +#define ANA_REG_GLB_32KLESS_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D8) +#define ANA_REG_GLB_32KLESS_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00DC) +#define ANA_REG_GLB_32KLESS_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E0) +#define ANA_REG_GLB_AUXAD_CTL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E4) +#define ANA_REG_GLB_XTL_WAIT_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E8) +#define ANA_REG_GLB_RGB_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00EC) +#define ANA_REG_GLB_WHTLED_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F0) +#define ANA_REG_GLB_WHTLED_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0094) +#define ANA_REG_GLB_WHTLED_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0098) +#define ANA_REG_GLB_KPLED_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F4) +#define ANA_REG_GLB_VIBR_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F8) +#define ANA_REG_GLB_AUDIO_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00FC) +#define ANA_REG_GLB_AUDIO_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0100) +#define ANA_REG_GLB_CHGR_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0104) +#define ANA_REG_GLB_CHGR_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0108) +#define ANA_REG_GLB_CHGR_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x010C) +#define ANA_REG_GLB_CHGR_DET_FGU_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0110) +#define ANA_REG_GLB_CHGR_STATUS SCI_ADDR(ANA_REGS_GLB_BASE, 0x0114) +#define ANA_REG_GLB_MIXED_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0118) +#define ANA_REG_GLB_MIXED_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x011C) +#define ANA_REG_GLB_SWRST_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0120) +#define ANA_REG_GLB_POR_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x0124) +#define ANA_REG_GLB_WDG_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x0128) +#define ANA_REG_GLB_POR_PIN_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x012C) +#define ANA_REG_GLB_POR_SRC_FLAG SCI_ADDR(ANA_REGS_GLB_BASE, 0x0130) +#define ANA_REG_GLB_POR_7S_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0134) +#define ANA_REG_GLB_HWRST_RTC SCI_ADDR(ANA_REGS_GLB_BASE, 0x0138) +#define ANA_REG_GLB_CHIP_ID_LOW SCI_ADDR(ANA_REGS_GLB_BASE, 0x013C) +#define ANA_REG_GLB_CHIP_ID_HIGH SCI_ADDR(ANA_REGS_GLB_BASE, 0x0140) +#define ANA_REG_GLB_ARM_MF_REG SCI_ADDR(ANA_REGS_GLB_BASE, 0x0144) +#define ANA_REG_GLB_ARCH_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0148) +#define ANA_REG_GLB_MCU_WR_PROT_VALUE SCI_ADDR(ANA_REGS_GLB_BASE, 0x014C) +#define ANA_REG_GLB_PWR_WR_PROT_VALUE SCI_ADDR(ANA_REGS_GLB_BASE, 0x0150) +#define ANA_REG_GLB_SMPL_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0154) +#define ANA_REG_GLB_SMPL_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0158) +#define ANA_REG_GLB_RTC_RST0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x015C) +#define ANA_REG_GLB_RTC_RST1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0160) +#define ANA_REG_GLB_RTC_RST2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0164) +#define ANA_REG_GLB_LDO_SHPT_PD1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0188) +#define ANA_REG_GLB_LDO_SHPT_PD2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x018C) +#define ANA_REG_GLB_BATDET_CUR_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0190) +#define ANA_REG_GLB_RTC_CLK_STOP SCI_ADDR(ANA_REGS_GLB_BASE, 0x0194) +#define ANA_REG_GLB_VBAT_DROP_CNT SCI_ADDR(ANA_REGS_GLB_BASE, 0x0198) +#define ANA_REG_GLB_DCDC_DISCHRG SCI_ADDR(ANA_REGS_GLB_BASE, 0x019C) +#define ANA_REG_GLB_DCDC_CORE_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0200) +#define ANA_REG_GLB_DCDC_ARM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0204) +#define ANA_REG_GLB_DCDC_MEM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0208) +#define ANA_REG_GLB_DCDC_GEN_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x020C) +#define ANA_REG_GLB_DCDC_WPA_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0210) +#define ANA_REG_GLB_DCDC_WPA_DCM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0214) +#define ANA_REG_GLB_DCDC_CON_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0218) +#define ANA_REG_GLB_DCDC_RF_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x021C) + +/* bits definitions for register ANA_REG_GLB_ARM_MODULE_EN */ +#define BIT_ANA_IMPD_ADC_EN ( BIT(12) ) +#define BIT_ANA_THM_EN ( BIT(11) ) +#define BIT_ANA_BLTC_EN ( BIT(10) ) +#define BIT_ANA_PINREG_EN ( BIT(9) ) +#define BIT_ANA_FGU_EN ( BIT(8) ) +#define BIT_ANA_EFS_EN ( BIT(7) ) +#define BIT_ANA_ADC_EN ( BIT(6) ) +#define BIT_ANA_HDT_EN ( BIT(5) ) +#define BIT_ANA_AUD_EN ( BIT(4) ) +#define BIT_ANA_EIC_EN ( BIT(3) ) +#define BIT_ANA_WDG_EN ( BIT(2) ) +#define BIT_ANA_RTC_EN ( BIT(1) ) +#define BIT_ANA_CAL_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_ARM_CLK_EN */ +#define BIT_CLK_IMPD_ADC_EN ( BIT(10) ) +#define BIT_CLK_AUXAD_EN ( BIT(9) ) +#define BIT_CLK_AUXADC_EN ( BIT(8) ) +#define BITS_CLK_CAL_SRC_SEL(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BIT_CLK_CAL_EN ( BIT(5) ) +#define BIT_CLK_AUD_HID_EN ( BIT(4) ) +#define BIT_CLK_AUD_HBD_EN ( BIT(3) ) +#define BIT_CLK_AUD_LOOP_EN ( BIT(2) ) +#define BIT_CLK_AUD_6P5M_EN ( BIT(1) ) +#define BIT_CLK_AUDIF_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_RTC_CLK_EN */ +#define BIT_RTC_EFS_EN ( BIT(12) ) +#define BIT_RTC_THMA_AUTO_EN ( BIT(11) ) +#define BIT_RTC_THMA_EN ( BIT(10) ) +#define BIT_RTC_THM_EN ( BIT(9) ) +#define BIT_RTC_BLTC_EN ( BIT(8) ) +#define BIT_RTC_FGU_EN ( BIT(7) ) +#define BIT_RTC_FGUA_EN ( BIT(6) ) +#define BIT_RTC_VIBR_EN ( BIT(5) ) +#define BIT_RTC_AUD_EN ( BIT(4) ) +#define BIT_RTC_EIC_EN ( BIT(3) ) +#define BIT_RTC_WDG_EN ( BIT(2) ) +#define BIT_RTC_RTC_EN ( BIT(1) ) +#define BIT_RTC_ARCH_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_ARM_RST */ +#define BIT_ANA_THMA_SOFT_RST ( BIT(15) ) +#define BIT_ANA_THM_SOFT_RST ( BIT(14) ) +#define BIT_ANA_BLTC_SOFT_RST ( BIT(13) ) +#define BIT_ANA_AUD_32K_SOFT_RST ( BIT(12) ) +#define BIT_ANA_AUDTX_SOFT_RST ( BIT(11) ) +#define BIT_ANA_AUDRX_SOFT_RST ( BIT(10) ) +#define BIT_ANA_AUD_SOFT_RST ( BIT(9) ) +#define BIT_ANA_AUD_HDT_SOFT_RST ( BIT(8) ) +#define BIT_ANA_EFS_SOFT_RST ( BIT(7) ) +#define BIT_ANA_ADC_SOFT_RST ( BIT(6) ) +#define BIT_ANA_PWM0_SOFT_RST ( BIT(5) ) +#define BIT_ANA_FGU_SOFT_RST ( BIT(4) ) +#define BIT_ANA_EIC_SOFT_RST ( BIT(3) ) +#define BIT_ANA_WDG_SOFT_RST ( BIT(2) ) +#define BIT_ANA_RTC_SOFT_RST ( BIT(1) ) +#define BIT_ANA_CAL_SOFT_RST ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_DCDC_PD */ +#define BIT_LDO_EMM_PD ( BIT(15) ) +#define BIT_DCDC_TOPCLK6M_PD ( BIT(14) ) +#define BIT_DCDC_RF_PD ( BIT(13) ) +#define BIT_DCDC_GEN_PD ( BIT(12) ) +#define BIT_DCDC_MEM_PD ( BIT(11) ) +#define BIT_DCDC_ARM_PD ( BIT(10) ) +#define BIT_DCDC_CORE_PD ( BIT(9) ) +#define BIT_LDO_RF0_PD ( BIT(8) ) +#define BIT_LDO_EMMCCORE_PD ( BIT(7) ) +#define BIT_LDO_GEN1_PD ( BIT(6) ) +#define BIT_LDO_DCXO_PD ( BIT(5) ) +#define BIT_LDO_GEN0_PD ( BIT(4) ) +#define BIT_LDO_VDD25_PD ( BIT(3) ) +#define BIT_LDO_VDD28_PD ( BIT(2) ) +#define BIT_LDO_VDD18_PD ( BIT(1) ) +#define BIT_BG_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_PD_CTRL */ +#define BIT_LDO_LPREF_PD_SW ( BIT(15) ) +#define BIT_DCDC_WPA_PD ( BIT(14) ) +#define BIT_DCDC_CON_PD ( BIT(13) ) +#define BIT_LDO_WIFIPA_PD ( BIT(11) ) +#define BIT_LDO_SDCORE_PD ( BIT(10) ) +#define BIT_LDO_USB_PD ( BIT(8) ) +#define BIT_LDO_CAMMOT_PD ( BIT(7) ) +#define BIT_LDO_CAMIO_PD ( BIT(6) ) +#define BIT_LDO_CAMD_PD ( BIT(5) ) +#define BIT_LDO_CAMA_PD ( BIT(4) ) +#define BIT_LDO_SIM2_PD ( BIT(3) ) +#define BIT_LDO_SIM1_PD ( BIT(2) ) +#define BIT_LDO_SIM0_PD ( BIT(1) ) +#define BIT_LDO_SDIO_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL0 */ +#define BITS_LDO_RF0_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_WIFIPA_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL1 */ +#define BITS_LDO_CAMIO_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_CAMD_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL2 */ +#define BITS_LDO_GEN0_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL3 */ +#define BITS_LDO_GEN1_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_VDD28_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL4 */ +#define BITS_LDO_SIM0_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_SDIO_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL5 */ +#define BITS_LDO_SIM2_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_SIM1_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL6 */ +#define BITS_LDO_SDCORE_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_CAMA_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL7 */ +#define BITS_LDO_EMMCCORE_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_CAMMOT_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL8 */ +#define BITS_LDO_DCXO_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_DCXO_LP_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL9 */ +#define BITS_LDO_VDD18_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_USB_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL10 */ +#define BITS_LDO_VDD25_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL11 */ +#define BITS_VBATBK_V(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_LDOB_CAL_SEL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_LDOA_CAL_SEL (_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_LDOD_CAL_SEL(_x_) ( (_x_) << 3 & (BIT(3)|BIT(4)) ) +#define BITS_LDODCDC_CAL_SEL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_LP_CTRL */ +#define BITS_LDOB_LP_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDOA_LP_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDODCDC_LP_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL0 */ +#define BITS_DCDC_CORE_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_CORE_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_CORE_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_CORE_QKRSPS ( BIT(3) ) +#define BIT_DCDC_CORE_PFM ( BIT(2) ) +#define BIT_DCDC_CORE_DCM ( BIT(1) ) +#define BIT_DCDC_CORE_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL1 */ +#define BITS_DCDC_MEM_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_MEM_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_MEM_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_MEM_QKRSPS ( BIT(3) ) +#define BIT_DCDC_MEM_PFM ( BIT(2) ) +#define BIT_DCDC_MEM_DCM ( BIT(1) ) +#define BIT_DCDC_MEM_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL2 */ +#define BITS_DCDC_GEN_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_GEN_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_GEN_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_GEN_QKRSPS ( BIT(3) ) +#define BIT_DCDC_GEN_PFM ( BIT(2) ) +#define BIT_DCDC_GEN_DCM ( BIT(1) ) +#define BIT_DCDC_GEN_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL3 */ +#define BITS_DCDC_ARM_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_ARM_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_ARM_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_ARM_QKRSPS ( BIT(3) ) +#define BIT_DCDC_ARM_PFM ( BIT(2) ) +#define BIT_DCDC_ARM_DCM ( BIT(1) ) +#define BIT_DCDC_ARM_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL4 */ +#define BITS_DCDC_WPA_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_WPA_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_WPA_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_WPA_QKRSPS ( BIT(3) ) +#define BIT_DCDC_WPA_PFM ( BIT(2) ) +#define BIT_DCDC_WPA_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL5 */ +#define BITS_DCDC_RF_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_RF_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_RF_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_RF_QKRSPS ( BIT(3) ) +#define BIT_DCDC_RF_PFM ( BIT(2) ) +#define BIT_DCDC_RF_DCM ( BIT(1) ) +#define BIT_DCDC_RF_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL6 */ +#define BITS_DCDC_CON_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_CON_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_CON_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_CON_QKRSPS ( BIT(3) ) +#define BIT_DCDC_CON_PFM ( BIT(2) ) +#define BIT_DCDC_CON_DCM ( BIT(1) ) +#define BIT_DCDC_CON_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL7 */ +#define BITS_DCDC_MEM_CF(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_DCDC_MEM_PFMAD(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_DCDC_MEM_CL_CTRL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_DCDC_CORE_DUALSEL ( BIT(7) ) +#define BIT_DCDC_CORE_MERGEEN ( BIT(6) ) +#define BITS_DCDC_CORE_CF(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_DCDC_CORE_PFMAD(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DCDC_CORE_CL_CTRL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL8 */ +#define BIT_DCDC_ARM_DUALSEL ( BIT(15) ) +#define BIT_DCDC_ARM_MERGEEN ( BIT(14) ) +#define BITS_DCDC_ARM_CF(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_DCDC_ARM_PFMAD(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_DCDC_ARM_CL_CTRL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_DCDC_GEN_CF(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_DCDC_GEN_PFMAD(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DCDC_GEN_CL_CTRL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL9 */ +#define BIT_DCDC_CON_MERGEEN ( BIT(14) ) +#define BITS_DCDC_CON_CF(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_DCDC_CON_PFMAD(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_DCDC_CON_CL_CTRL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_DCDC_RF_MERGEEN ( BIT(6) ) +#define BITS_DCDC_RF_CF(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_DCDC_RF_PFMAD(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DCDC_RF_CL_CTRL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL10 */ +#define BIT_DCDC_WPA_BPOUT_SOFTW ( BIT(15) ) +#define BITS_DCDC_WPA_VBAT_DIV(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BIT_DCDC_WPA_BPEN ( BIT(11) ) +#define BIT_DCDC_WPA_BPMODE ( BIT(10) ) +#define BIT_DCDC_WPA_DEGEN ( BIT(9) ) +#define BIT_DCDC_WPA_APTEN ( BIT(8) ) +#define BITS_DCDC_WPA_DEBC_SEL(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_DCDC_WPA_CF(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_DCDC_WPA_PFMAD(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DCDC_WPA_CL_CTRL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL11 */ +#define BIT_DCDC_3MCLKCAL_EN ( BIT(13) ) +#define BIT_DCDC_2MCLKCAL_EN ( BIT(12) ) +#define BITS_DCDC_6MFRECAL_SW(_x_) ( (_x_) << 7 & (BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DCDC_4MFRECAL_SW(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_DCDC_CLK_SP_SEL ( BIT(1) ) +#define BIT_DCDC_CLK_SP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL12 */ +#define BIT_DCDC_CORE_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_CORE_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_CORE_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_CORE_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_ARM_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_ARM_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_ARM_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_ARM_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL13 */ +#define BIT_DCDC_MEM_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_MEM_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_MEM_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_MEM_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_GEN_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_GEN_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_GEN_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_GEN_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL14 */ +#define BIT_DCDC_WPA_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_WPA_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_WPA_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_WPA_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_RF_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_RF_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_RF_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_RF_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL15 */ +#define BITS_DCDC_CAL_SEL(_x_) ( (_x_) << 13 & (BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_DCDC_CON_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_CON_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_CON_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_CON_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_SLP_WAIT_DCDCARM */ +#define BITS_SLP_IN_WAIT_DCDCARM(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_SLP_OUT_WAIT_DCDCARM(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL0 */ +#define BIT_SLP_IO_EN ( BIT(15) ) +#define BIT_SLP_DCDCRF_PD_EN ( BIT(13) ) +#define BIT_SLP_DCDCCON_PD_EN ( BIT(12) ) +#define BIT_SLP_DCDCGEN_PD_EN ( BIT(11) ) +#define BIT_SLP_DCDCWPA_PD_EN ( BIT(10) ) +#define BIT_SLP_DCDCARM_PD_EN ( BIT(9) ) +#define BIT_SLP_LDOVDD25_PD_EN ( BIT(8) ) +#define BIT_SLP_LDORF0_PD_EN ( BIT(7) ) +#define BIT_SLP_LDOEMMCCORE_PD_EN ( BIT(6) ) +#define BIT_SLP_LDOGEN0_PD_EN ( BIT(5) ) +#define BIT_SLP_LDODCXO_PD_EN ( BIT(4) ) +#define BIT_SLP_LDOGEN1_PD_EN ( BIT(3) ) +#define BIT_SLP_LDOWIFIPA_PD_EN ( BIT(2) ) +#define BIT_SLP_LDOVDD28_PD_EN ( BIT(1) ) +#define BIT_SLP_LDOVDD18_PD_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL1 */ +#define BIT_SLP_LDO_PD_EN ( BIT(15) ) +#define BIT_SLP_LDOLPREF_PD_EN ( BIT(14) ) +#define BIT_SLP_LDOSDCORE_PD_EN ( BIT(9) ) +#define BIT_SLP_LDOUSB_PD_EN ( BIT(8) ) +#define BIT_SLP_LDOCAMMOT_PD_EN ( BIT(7) ) +#define BIT_SLP_LDOCAMIO_PD_EN ( BIT(6) ) +#define BIT_SLP_LDOCAMD_PD_EN ( BIT(5) ) +#define BIT_SLP_LDOCAMA_PD_EN ( BIT(4) ) +#define BIT_SLP_LDOSIM2_PD_EN ( BIT(3) ) +#define BIT_SLP_LDOSIM1_PD_EN ( BIT(2) ) +#define BIT_SLP_LDOSIM0_PD_EN ( BIT(1) ) +#define BIT_SLP_LDOSDIO_PD_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL2 */ +#define BIT_SLP_DCDCRF_LP_EN ( BIT(14) ) +#define BIT_SLP_DCDCCON_LP_EN ( BIT(13) ) +#define BIT_SLP_DCDCCORE_LP_EN ( BIT(12) ) +#define BIT_SLP_DCDCMEM_LP_EN ( BIT(11) ) +#define BIT_SLP_DCDCARM_LP_EN ( BIT(10) ) +#define BIT_SLP_DCDCGEN_LP_EN ( BIT(9) ) +#define BIT_SLP_DCDCWPA_LP_EN ( BIT(8) ) +#define BIT_SLP_LDORF0_LP_EN ( BIT(7) ) +#define BIT_SLP_LDOEMMCCORE_LP_EN ( BIT(6) ) +#define BIT_SLP_LDOGEN0_LP_EN ( BIT(5) ) +#define BIT_SLP_LDODCXO_LP_EN ( BIT(4) ) +#define BIT_SLP_LDOGEN1_LP_EN ( BIT(3) ) +#define BIT_SLP_LDOWIFIPA_LP_EN ( BIT(2) ) +#define BIT_SLP_LDOVDD28_LP_EN ( BIT(1) ) +#define BIT_SLP_LDOVDD18_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL3 */ +#define BIT_SLP_BG_LP_EN ( BIT(15) ) +#define BIT_LDOVDD25_LP_EN_SW ( BIT(14) ) +#define BIT_LDOSDCORE_LP_EN_SW ( BIT(13) ) +#define BIT_LDOUSB_LP_EN_SW ( BIT(12) ) +#define BIT_SLP_LDOVDD25_LP_EN ( BIT(10) ) +#define BIT_SLP_LDOSDCORE_LP_EN ( BIT(9) ) +#define BIT_SLP_LDOUSB_LP_EN ( BIT(8) ) +#define BIT_SLP_LDOCAMMOT_LP_EN ( BIT(7) ) +#define BIT_SLP_LDOCAMIO_LP_EN ( BIT(6) ) +#define BIT_SLP_LDOCAMD_LP_EN ( BIT(5) ) +#define BIT_SLP_LDOCAMA_LP_EN ( BIT(4) ) +#define BIT_SLP_LDOSIM2_LP_EN ( BIT(3) ) +#define BIT_SLP_LDOSIM1_LP_EN ( BIT(2) ) +#define BIT_SLP_LDOSIM0_LP_EN ( BIT(1) ) +#define BIT_SLP_LDOSDIO_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL4 */ +#define BIT_LDOCAMIO_LP_EN_SW ( BIT(15) ) +#define BIT_LDOCAMMOT_LP_EN_SW ( BIT(14) ) +#define BIT_LDOCAMD_LP_EN_SW ( BIT(13) ) +#define BIT_LDOCAMA_LP_EN_SW ( BIT(12) ) +#define BIT_LDOSIM2_LP_EN_SW ( BIT(11) ) +#define BIT_LDOSIM1_LP_EN_SW ( BIT(10) ) +#define BIT_LDOSIM0_LP_EN_SW ( BIT(9) ) +#define BIT_LDOSDIO_LP_EN_SW ( BIT(8) ) +#define BIT_LDORF0_LP_EN_SW ( BIT(7) ) +#define BIT_LDOEMMCCORE_LP_EN_SW ( BIT(6) ) +#define BIT_LDOGEN0_LP_EN_SW ( BIT(5) ) +#define BIT_LDODCXO_LP_EN_SW ( BIT(4) ) +#define BIT_LDOGEN1_LP_EN_SW ( BIT(3) ) +#define BIT_LDOWIFIPA_LP_EN_SW ( BIT(2) ) +#define BIT_LDOVDD28_LP_EN_SW ( BIT(1) ) +#define BIT_LDOVDD18_LP_EN_SW ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_AUD_SLP_CTRL */ +#define BIT_SLP_AUD_PMUR1_PD_EN ( BIT(14) ) +#define BIT_SLP_AUD_PA_SW_PD_EN ( BIT(13) ) +#define BIT_SLP_AUD_PA_LDO_PD_EN ( BIT(12) ) +#define BIT_SLP_AUD_PA_PD_EN ( BIT(11) ) +#define BIT_SLP_AUD_OVP_PD_PD_EN ( BIT(10) ) +#define BIT_SLP_AUD_OVP_LDO_PD_EN ( BIT(9) ) +#define BIT_SLP_AUD_LDOCG_PD_PD_EN ( BIT(8) ) +#define BIT_SLP_AUD_VB_PD_EN ( BIT(7) ) +#define BIT_SLP_AUD_VBO_PD_EN ( BIT(6) ) +#define BIT_SLP_AUD_HEADMICBIAS_PD_EN ( BIT(5) ) +#define BIT_SLP_AUD_HEADMIC_SLEEP_PD_EN ( BIT(4) ) +#define BIT_SLP_AUD_PLGPD_PD_EN ( BIT(3) ) +#define BIT_SLP_AUD_VB_NLEAK_PD ( BIT(2) ) +#define BITS_SLP_AUD_PMUR0_PD_EN(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL0 */ +#define BITS_SLP_DCDCCORE_VOL_DROP_CNT(_x_)( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_PWR_OFF_SEQ_EN ( BIT(2) ) +#define BIT_DCDC_CORE_SLP_OUT_STEP_EN ( BIT(1) ) +#define BIT_DCDC_CORE_SLP_IN_STEP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL1 */ +#define BITS_DCDC_CORE_CAL_DS_SW(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CTRL_DS_SW(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL2 */ +#define BITS_DCDC_CORE_CTRL_SLP_STEP3(_x_)( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_DCDC_CORE_CTRL_SLP_STEP2(_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CTRL_SLP_STEP1(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL3 */ +#define BITS_DCDC_CORE_CTRL_SLP_STEP5(_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CTRL_SLP_STEP4(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL4 */ +#define BITS_DCDC_CORE_CAL_SLP_STEP3(_x_)( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_DCDC_CORE_CAL_SLP_STEP2(_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CAL_SLP_STEP1(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL5 */ +#define BITS_DCDC_CORE_CAL_SLP_STEP5(_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CAL_SLP_STEP4(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SEL */ +#define BIT_LDO_GEN0_SW_SEL ( BIT(13) ) +#define BIT_LDO_GEN1_SW_SEL ( BIT(12) ) +#define BIT_LDO_RF0_SW_SEL ( BIT(11) ) +#define BIT_LDO_VDD18_SW_SEL ( BIT(10) ) +#define BIT_LDO_VDD28_SW_SEL ( BIT(9) ) +#define BIT_LDO_DCXO_SW_SEL ( BIT(8) ) +#define BIT_LDO_EMMCCORE_SW_SEL ( BIT(7) ) +#define BIT_LDO_VDD25_SW_SEL ( BIT(6) ) +#define BIT_DCDC_RF_SW_SEL ( BIT(5) ) +#define BIT_DCDC_GEN_SW_SEL ( BIT(4) ) +#define BIT_DCDC_MEM_SW_SEL ( BIT(3) ) +#define BIT_DCDC_ARM_SW_SEL ( BIT(2) ) +#define BIT_DCDC_CORE_SLP_SW_SEL ( BIT(1) ) +#define BIT_DCDC_CORE_NOR_SW_SEL ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN0 */ +#define BIT_LDO_XTL_EN ( BIT(15) ) +#define BIT_LDO_GEN0_EXT_XTL0_EN ( BIT(14) ) +#define BIT_LDO_GEN0_XTL1_EN ( BIT(13) ) +#define BIT_LDO_GEN0_XTL0_EN ( BIT(12) ) +#define BIT_LDO_GEN1_EXT_XTL0_EN ( BIT(11) ) +#define BIT_LDO_GEN1_XTL1_EN ( BIT(10) ) +#define BIT_LDO_GEN1_XTL0_EN ( BIT(9) ) +#define BIT_LDO_DCXO_EXT_XTL0_EN ( BIT(8) ) +#define BIT_LDO_DCXO_XTL1_EN ( BIT(7) ) +#define BIT_LDO_DCXO_XTL0_EN ( BIT(6) ) +#define BIT_LDO_VDD18_EXT_XTL0_EN ( BIT(5) ) +#define BIT_LDO_VDD18_XTL1_EN ( BIT(4) ) +#define BIT_LDO_VDD18_XTL0_EN ( BIT(3) ) +#define BIT_LDO_VDD28_EXT_XTL0_EN ( BIT(2) ) +#define BIT_LDO_VDD28_XTL1_EN ( BIT(1) ) +#define BIT_LDO_VDD28_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN1 */ +#define BIT_LDO_RF0_EXT_XTL0_EN ( BIT(14) ) +#define BIT_LDO_RF0_XTL1_EN ( BIT(13) ) +#define BIT_LDO_RF0_XTL0_EN ( BIT(12) ) +#define BIT_LDO_WIFIPA_EXT_XTL0_EN ( BIT(11) ) +#define BIT_LDO_WIFIPA_XTL1_EN ( BIT(10) ) +#define BIT_LDO_WIFIPA_XTL0_EN ( BIT(9) ) +#define BIT_LDO_SIM2_EXT_XTL0_EN ( BIT(8) ) +#define BIT_LDO_SIM2_XTL1_EN ( BIT(7) ) +#define BIT_LDO_SIM2_XTL0_EN ( BIT(6) ) +#define BIT_LDO_SIM1_EXT_XTL0_EN ( BIT(5) ) +#define BIT_LDO_SIM1_XTL1_EN ( BIT(4) ) +#define BIT_LDO_SIM1_XTL0_EN ( BIT(3) ) +#define BIT_LDO_SIM0_EXT_XTL0_EN ( BIT(2) ) +#define BIT_LDO_SIM0_XTL1_EN ( BIT(1) ) +#define BIT_LDO_SIM0_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN2 */ +#define BIT_LDO_VDD25_EXT_XTL0_EN ( BIT(11) ) +#define BIT_LDO_VDD25_XTL1_EN ( BIT(10) ) +#define BIT_LDO_VDD25_XTL0_EN ( BIT(9) ) +#define BIT_DCDC_RF_EXT_XTL0_EN ( BIT(8) ) +#define BIT_DCDC_RF_XTL1_EN ( BIT(7) ) +#define BIT_DCDC_RF_XTL0_EN ( BIT(6) ) +#define BIT_XO_EXT_XTL0_EN ( BIT(5) ) +#define BIT_XO_XTL1_EN ( BIT(4) ) +#define BIT_XO_XTL0_EN ( BIT(3) ) +#define BIT_BG_EXT_XTL0_EN ( BIT(2) ) +#define BIT_BG_XTL1_EN ( BIT(1) ) +#define BIT_BG_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN3 */ +#define BIT_DCDC_CON_EXT_XTL0_EN ( BIT(14) ) +#define BIT_DCDC_CON_XTL1_EN ( BIT(13) ) +#define BIT_DCDC_CON_XTL0_EN ( BIT(12) ) +#define BIT_DCDC_WPA_EXT_XTL0_EN ( BIT(11) ) +#define BIT_DCDC_WPA_XTL1_EN ( BIT(10) ) +#define BIT_DCDC_WPA_XTL0_EN ( BIT(9) ) +#define BIT_DCDC_MEM_EXT_XTL0_EN ( BIT(8) ) +#define BIT_DCDC_MEM_XTL1_EN ( BIT(7) ) +#define BIT_DCDC_MEM_XTL0_EN ( BIT(6) ) +#define BIT_DCDC_GEN_EXT_XTL0_EN ( BIT(5) ) +#define BIT_DCDC_GEN_XTL1_EN ( BIT(4) ) +#define BIT_DCDC_GEN_XTL0_EN ( BIT(3) ) +#define BIT_DCDC_CORE_EXT_XTL0_EN ( BIT(2) ) +#define BIT_DCDC_CORE_XTL1_EN ( BIT(1) ) +#define BIT_DCDC_CORE_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_32KLESS_CTRL0 */ +#define BIT_RC_MODE_WR_ACK_FLAG ( BIT(14) ) +#define BIT_XO_LOW_CUR_FLAG ( BIT(13) ) +#define BIT_XO_LOW_CUR_FRC_RTCSET ( BIT(12) ) +#define BIT_XO_LOW_CUR_FRC_RTCCLR ( BIT(11) ) +#define BIT_RC_MODE_WR_ACK_FLAG_CLR ( BIT(10) ) +#define BIT_XO_LOW_CUR_FLAG_CLR ( BIT(9) ) +#define BIT_XO_LOW_CUR_CNT_CLR ( BIT(8) ) +#define BIT_LDO_DCXO_LP_PD_RTCSET ( BIT(7) ) +#define BIT_LDO_DCXO_LP_PD_RTCCLR ( BIT(6) ) +#define BIT_SLP_XO_LOW_CUR_EN ( BIT(5) ) +#define BIT_XO_LOW_CUR_EN ( BIT(3) ) +#define BIT_EXT_32K_PD ( BIT(2) ) +#define BIT_RC_32K_SEL ( BIT(1) ) +#define BIT_RC_32K_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_32KLESS_CTRL1 */ +#define BITS_RC_MODE(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_32KLESS_CTRL2 */ +#define BITS_XO_LOW_CUR_CNT_LOW(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_32KLESS_CTRL3 */ +#define BITS_XO_LOW_CUR_CNT_HIGH(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_AUXAD_CTL */ +#define BIT_AUXAD_CURRENTSEN_EN ( BIT(6) ) +#define BIT_AUXAD_CURRENTSEL ( BIT(5) ) +#define BITS_AUXAD_CURRENT_IBS(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_XTL_WAIT_CTRL */ +#define BIT_SLP_XTLBUF_PD_EN ( BIT(9) ) +#define BIT_XTL_EN ( BIT(8) ) +#define BITS_XTL_WAIT(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_RGB_CTRL */ +#define BIT_RTC_PWM0_EN ( BIT(15) ) +#define BIT_PWM0_EN ( BIT(14) ) +#define BIT_IB_REX_EN ( BIT(12) ) +#define BIT_IB_TRIM_EM_SEL ( BIT(11) ) +#define BITS_RGB_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) ) +#define BIT_SLP_RGB_PD_EN ( BIT(2) ) +#define BIT_RGB_PD_HW_EN ( BIT(1) ) +#define BIT_RGB_PD_SW ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_WHTLED_CTRL */ +#define BITS_IB_TRIM(_x_) ( (_x_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_WHTLED_SERIES_EN ( BIT(8) ) +#define BIT_WHTLED_PD_SEL ( BIT(7) ) +#define BIT_WHTLED_BOOST_EN ( BIT(8) ) +#define BITS_WHTLED_V(_x_) ( (_x_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_WHTLED_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_KPLED_CTRL */ +#define BITS_KPLED_V(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_KPLED_PD ( BIT(11) ) +#define BIT_KPLED_PULLDOWN_EN ( BIT(10) ) +#define BIT_SLP_LDOKPLED_PD_EN ( BIT(9) ) +#define BIT_LDO_KPLED_PD ( BIT(8) ) +#define BITS_LDO_KPLED_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_VIBR_CTRL0 */ +#define BITS_CUR_DRV_CAL_SEL(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BIT_VIBR_PULLDOWN_EN ( BIT(11) ) +#define BIT_VIBR_PULLUP_EN ( BIT(10) ) +#define BIT_SLP_LDOVIBR_PD_EN ( BIT(9) ) +#define BIT_LDO_VIBR_PD ( BIT(8) ) +#define BITS_LDO_VIBR_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_AUDIO_CTRL0 */ +#define BIT_AUD_SLP_APP_RST_EN ( BIT(15) ) +#define BITS_CLK_AUD_HBD_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_CLK_AUD_LOOP_INV_EN ( BIT(4) ) +#define BIT_CLK_AUDIF_TX_INV_EN ( BIT(3) ) +#define BIT_CLK_AUDIF_RX_INV_EN ( BIT(2) ) +#define BIT_CLK_AUD_6P5M_TX_INV_EN ( BIT(1) ) +#define BIT_CLK_AUD_6P5M_RX_INV_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_AUDIO_CTRL1 */ +#define BIT_IMPD_ADC_SOFT_RST ( BIT(7) ) +#define BIT_HEAD_INSERT_EIC_EN ( BIT(6) ) +#define BIT_AUDIO_CHP_CLK_DIV_EN ( BIT(5) ) +#define BITS_AUDIO_CHP_CLK_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL0 */ +#define BIT_CHGLDO_DIS ( BIT(15) ) +#define BITS_CHGR_CV_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CHGR_END_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BIT_CHGR_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL1 */ +#define BITS_CHGR_CC_I(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_VBAT_OVP_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_VCHG_OVP_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL2 */ +#define BIT_CHGR_INT_EN ( BIT(15) ) +#define BIT_CHGR_DRV ( BIT(7) ) +#define BIT_CHGR_OSC ( BIT(6) ) +#define BITS_CHGR_DPM(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CHGR_ITERM(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BIT_CHGR_CC_EN ( BIT(1) ) +#define BIT_RECHG ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_DET_FGU_CTRL */ +#define BIT_FGUA_SOFT_RST ( BIT(13) ) +#define BIT_LDO_FGU_PD ( BIT(12) ) +#define BIT_SD_CHOP_CAP_EN ( BIT(8) ) +#define BITS_SD_CLK_P(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BIT_SD_DCOFFSET_EN ( BIT(5) ) +#define BIT_SD_CHOP_EN ( BIT(4) ) +#define BIT_DP_DM_AUX_EN ( BIT(1) ) +#define BIT_DP_DM_SW_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_STATUS */ +#define BIT_CHG_DET_DONE ( BIT(11) ) +#define BIT_DP_LOW ( BIT(10) ) +#define BIT_DCP_DET ( BIT(9) ) +#define BIT_CHG_DET ( BIT(8) ) +#define BIT_SDP_INT ( BIT(7) ) +#define BIT_DCP_INT ( BIT(6) ) +#define BIT_CDP_INT ( BIT(5) ) +#define BIT_CHGR_CV_STATUS ( BIT(4) ) +#define BIT_CHGR_ON ( BIT(3) ) +#define BIT_CHGR_INT ( BIT(2) ) +#define BIT_VBAT_OVI ( BIT(1) ) +#define BIT_VCHG_OVI ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_MIXED_CTRL0 */ +#define BIT_PTEST_PD_RTCSET ( BIT(15) ) +#define BIT_DCDC_V_CTRL_MODE ( BIT(14) ) +#define BIT_LDO_RAMP_EN ( BIT(13) ) +#define BIT_BG_LP_EN ( BIT(12) ) +#define BITS_VBAT_CRASH_V(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BIT_OVLO_EN ( BIT(9) ) +#define BITS_OVLO_CAL(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_OVLO_V(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_OVLO_T(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_MIXED_CTRL1 */ +#define BITS_XOSC32K_CTL(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_BATON_T(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BIT_BATDET_LDO_SEL ( BIT(9) ) +#define BIT_THM_CHIP_PD_FLAG ( BIT(8) ) +#define BIT_THM_CHIP_PD_FLAG_CLR ( BIT(7) ) +#define BITS_THM_CAL_SEL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)) ) +#define BIT_THM_AUTO_PD_EN ( BIT(4) ) +#define BIT_ALL_GPI_DEB ( BIT(3) ) +#define BIT_GPI_DEBUG_EN ( BIT(2) ) +#define BIT_ALL_INT_DEB ( BIT(1) ) +#define BIT_INT_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_SWRST_CTRL */ +#define BIT_POR_RTC_PD ( BIT(15) ) +#define BITS_POR_RTC_I(_x_) ( (_x_) << 13 & (BIT(13)|BIT(14)) ) +#define BIT_SW_RST_GEN1_PD_EN ( BIT(12) ) +#define BIT_SW_RST_GEN0_PD_EN ( BIT(11) ) +#define BIT_EXT_RSTN_PD_EN ( BIT(10) ) +#define BIT_PB_7S_RST_PD_EN ( BIT(9) ) +#define BIT_SW_RST_EMMCCORE_PD_EN ( BIT(8) ) +#define BIT_KEY2_7S_RST_EN ( BIT(7) ) +#define BIT_WDG_RST_PD_EN ( BIT(6) ) +#define BITS_SW_RST_PD_THRESHOLD(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register ANA_REG_GLB_POR_RST_MONITOR */ +#define BITS_POR_RST_MONITOR(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_WDG_RST_MONITOR */ +#define BITS_WDG_RST_MONITOR(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_POR_PIN_RST_MONITOR */ +#define BITS_POR_PIN_RST_MONITOR(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_POR_SRC_FLAG */ +#define BIT_POR_SW_FORCE_ON ( BIT(15) ) +#define BITS_POR_SRC_FLAG(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_POR_7S_CTRL */ +#define BIT_PBINT_7S_FLAG_CLR ( BIT(15) ) +#define BIT_EXT_RSTN_FLAG_CLR ( BIT(14) ) +#define BIT_CHGR_INT_FLAG_CLR ( BIT(13) ) +#define BIT_PBINT2_FLAG_CLR ( BIT(12) ) +#define BIT_PBINT_FLAG_CLR ( BIT(11) ) +#define BIT_PBINT_7S_RST_SWMODE ( BIT(8) ) +#define BITS_PBINT_7S_RST_THRESHOLD(_x_)( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_PBINT_7S_AUTO_ON_EN ( BIT(2) ) +#define BIT_PBINT_7S_RST_DISABLE ( BIT(1) ) +#define BIT_PBINT_7S_RST_MODE ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_HWRST_RTC */ +#define BITS_HWRST_RTC_REG_STS(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_HWRST_RTC_REG_SET(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_CHIP_ID_LOW */ +#define BITS_CHIP_ID_LOW(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_CHIP_ID_HIGH */ +#define BITS_CHIP_ID_HIGH(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_ARM_MF_REG */ +#define BITS_ARM_MF_REG(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_ARCH_EN */ +#define BIT_ARCH_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_MCU_WR_PROT_VALUE */ +#define BIT_MCU_WR_PROT ( BIT(15) ) +#define BITS_MCU_WR_PROT_VALUE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_PWR_WR_PROT_VALUE */ +#define BIT_PWR_WR_PROT ( BIT(15) ) +#define BITS_PWR_WR_PROT_VALUE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_SMPL_CTRL0 */ +#define BITS_SMPL_MODE(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_SMPL_CTRL1 */ +#define BIT_SMPL_PWR_ON_FLAG ( BIT(15) ) +#define BIT_SMPL_MODE_WR_ACK_FLAG ( BIT(14) ) +#define BIT_SMPL_PWR_ON_FLAG_CLR ( BIT(13) ) +#define BIT_SMPL_MODE_WR_ACK_FLAG_CLR ( BIT(12) ) +#define BIT_SMPL_PWR_ON_SET ( BIT(11) ) +#define BIT_SMPL_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_RTC_RST0 */ +#define BITS_RTC_CLK_FLAG_SET(_x_) ( (_x_) << 15 & (BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_RTC_RST1 */ +#define BITS_RTC_CLK_FLAG_CLR(_x_) ( (_x_) << 15 & (BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_RTC_RST2 */ +#define BITS_RTC_CLK_FLAG_RTC(_x_) ( (_x_) << 15 & (BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SHPT_PD1 */ +#define BIT_LDO_USB_SHPT_PD ( BIT(12) ) +#define BIT_LDO_DCXO_SHPT_PD ( BIT(11) ) +#define BIT_LDO_WIFIPA_SHPT_PD ( BIT(10) ) +#define BIT_LDO_VDD25_SHPT_PD ( BIT(9) ) +#define BIT_LDO_VDD28_SHPT_PD ( BIT(8) ) +#define BIT_LDO_SDIO_SHPT_PD ( BIT(7) ) +#define BIT_LDO_SDCORE_SHPT_PD ( BIT(6) ) +#define BIT_LDO_EMMCCORE_SHPT_PD ( BIT(5) ) +#define BIT_LDO_SIM2_SHPT_PD ( BIT(4) ) +#define BIT_LDO_SIM1_SHPT_PD ( BIT(3) ) +#define BIT_LDO_SIM0_SHPT_PD ( BIT(2) ) +#define BIT_LDO_CAMMOT_SHPT_PD ( BIT(1) ) +#define BIT_LDO_CAMA_SHPT_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SHPT_PD2 */ +#define BIT_LDO_RF0_SHPT_PD ( BIT(7) ) +#define BIT_LDO_GEN1_SHPT_PD ( BIT(6) ) +#define BIT_LDO_GEN0_SHPT_PD ( BIT(5) ) +#define BIT_LDO_CAMD_SHPT_PD ( BIT(4) ) +#define BIT_LDO_VDD18_SHPT_PD ( BIT(3) ) +#define BIT_LDO_CAMIO_SHPT_PD ( BIT(2) ) +#define BIT_LDO_KPLED_SHPT_PD ( BIT(1) ) +#define BIT_LDO_VIBR_SHPT_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_BATDET_CUR_CTRL */ +#define BIT_BATDET_CUR_EN ( BIT(4) ) +#define BITS_BATDET_CUR_I(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register ANA_REG_GLB_RTC_CLK_STOP */ +#define BIT_RTC_CLK_STOP_FLAG ( BIT(7) ) +#define BITS_RTC_CLK_STOP_THRESHOLD(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) + +/* bits definitions for register ANA_REG_GLB_VBAT_DROP_CNT */ +#define BITS_VBAT_DROP_CNT(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_DISCHRG */ +#define BITS_DCDC_ARM_DISCHRG(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_DCDC_CORE_DISCHRG(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_DCDC_MEM_DISCHRG(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_DCDC_GEN_DISCHRG(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_DCDC_RF_DISCHRG(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_DCDC_CON_DISCHRG(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DCDC_WPA_DISCHRG(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CORE_ADI */ +#define BITS_DCDC_CORE_CTL_SW_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CAL_SW_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_ARM_ADI */ +#define BITS_DCDC_ARM_CTL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_ARM_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_MEM_ADI */ +#define BITS_DCDC_MEM_CTRL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_MEM_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_GEN_ADI */ +#define BITS_DCDC_GEN_CTRL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_GEN_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_WPA_ADI */ +#define BITS_DCDC_WPA_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_WPA_DCM_ADI */ +#define BIT_DCDC_WPA_DCM_ADI ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CON_ADI */ +#define BITS_DCDC_CON_CTRL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CON_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_RF_ADI */ +#define BITS_DCDC_RF_CTRL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_RF_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* vars definitions for controller ANA_REGS_GLB */ + +#endif /* __ANA_REGS_GLB_H__ */ diff --git a/include/soc/sprd/chip_x35lt8/__regs_aon_apb_rf.h b/include/soc/sprd/chip_x35lt8/__regs_aon_apb_rf.h new file mode 100644 index 00000000..43bb0138 --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_aon_apb_rf.h @@ -0,0 +1,886 @@ +/* the head file modifier: g 2015-03-19 15:30:08*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_AON_APB_RF_HEADFILE_H__ +#define __H_REGS_AON_APB_RF_HEADFILE_H__ __FILE__ + +#define REGS_AON_APB_RF + +/* registers definitions for AON_APB_RF */ +#define REG_AON_APB_APB_EB0 SCI_ADDR(REGS_AON_APB_BASE, 0x0000)/*AHB_EB0*/ +#define REG_AON_APB_APB_EB1 SCI_ADDR(REGS_AON_APB_BASE, 0x0004)/*AHB_EB1*/ +#define REG_AON_APB_APB_RST0 SCI_ADDR(REGS_AON_APB_BASE, 0x0008)/*AHB_RST0*/ +#define REG_AON_APB_APB_RST1 SCI_ADDR(REGS_AON_APB_BASE, 0x000C)/*AHB_RST1*/ +#define REG_AON_APB_APB_RTC_EB SCI_ADDR(REGS_AON_APB_BASE, 0x0010)/*APB_RTC_EB*/ +#define REG_AON_APB_REC_26MHZ_BUF_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0014)/*REC_26MHZ_BUF_CFG*/ +#define REG_AON_APB_SINDRV_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0018)/*SINDRV_CTRL*/ +#define REG_AON_APB_ADA_SEL_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x001C)/*ADA_SEL_CTRL*/ +#define REG_AON_APB_VBC_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0020)/*VBC_CTRL*/ +#define REG_AON_APB_PWR_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0024)/*PWR_CTRL*/ +#define REG_AON_APB_TS_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0028)/*TS_CFG*/ +#define REG_AON_APB_BOOT_MODE SCI_ADDR(REGS_AON_APB_BASE, 0x002C)/*BOOT_MODE*/ +#define REG_AON_APB_BB_BG_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0030)/*BB_BG_CTRL*/ +#define REG_AON_APB_CP_ARM_JTAG_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0034)/*CP_ARM_JTAG_CTRL*/ +#define REG_AON_APB_PLL_SOFT_CNT_DONE SCI_ADDR(REGS_AON_APB_BASE, 0x0038)/*PLL_SOFT_CNT_DONE*/ +#define REG_AON_APB_DCXO_LC_REG0 SCI_ADDR(REGS_AON_APB_BASE, 0x003C)/*DCXO_LC_REG0*/ +#define REG_AON_APB_DCXO_LC_REG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0040)/*DCXO_LC_REG1*/ +#define REG_AON_APB_MPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0044)/*MPLL_CFG1*/ +#define REG_AON_APB_MPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0048)/*MPLL_CFG2*/ +#define REG_AON_APB_DPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x004C)/*DPLL_CFG1*/ +#define REG_AON_APB_DPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0050)/*DPLL_CFG2*/ +#define REG_AON_APB_TWPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0054)/*TWPLL_CFG1*/ +#define REG_AON_APB_TWPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0058)/*TWPLL_CFG2*/ +#define REG_AON_APB_LTEPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x005C)/*LTEPLL_CFG1*/ +#define REG_AON_APB_LTEPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0060)/*LTEPLL_CFG2*/ +#define REG_AON_APB_LVDSDISPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0064)/*LVDSDISPLL_CFG1*/ +#define REG_AON_APB_LVDSDISPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0068)/*LVDSDISPLL_CFG2*/ +#define REG_AON_APB_AON_REG_PROT SCI_ADDR(REGS_AON_APB_BASE, 0x006C)/*AON_REG_PROT*/ +#define REG_AON_APB_LDSP_BOOT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x0070)/*LDSP_BOOT_EN*/ +#define REG_AON_APB_LDSP_BOOT_VEC SCI_ADDR(REGS_AON_APB_BASE, 0x0074)/*LDSP_BOOT_VEC*/ +#define REG_AON_APB_LDSP_RST SCI_ADDR(REGS_AON_APB_BASE, 0x0078)/*LDSP_RST*/ +#define REG_AON_APB_LDSP_MTX_CTRL1 SCI_ADDR(REGS_AON_APB_BASE, 0x007C)/*LDSP_MTX_CT1RL1*/ +#define REG_AON_APB_LDSP_MTX_CTRL2 SCI_ADDR(REGS_AON_APB_BASE, 0x0080)/*LDSP_MTX_CTRL2*/ +#define REG_AON_APB_LDSP_MTX_CTRL3 SCI_ADDR(REGS_AON_APB_BASE, 0x0084)/*LDSP_MTX_CTRL3*/ +#define REG_AON_APB_AON_CGM_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0088)/*AON_CGM_CFG*/ +#define REG_AON_APB_LACC_MTX_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x008C)/*LACC_MTX_CTRL*/ +#define REG_AON_APB_CORTEX_MTX_CTRL1 SCI_ADDR(REGS_AON_APB_BASE, 0x0090)/*CORTEX_MTX_CTRL1*/ +#define REG_AON_APB_CORTEX_MTX_CTRL2 SCI_ADDR(REGS_AON_APB_BASE, 0x0094)/*CORTEX_MTX_CTRL2*/ +#define REG_AON_APB_CORTEX_MTX_CTRL3 SCI_ADDR(REGS_AON_APB_BASE, 0x0098)/*CORTEX_MTX_CTRL3*/ +#define REG_AON_APB_CA5_TCLK_DLY_LEN SCI_ADDR(REGS_AON_APB_BASE, 0x009C)/*CA5_TCLK_DLY_LEN*/ +#define REG_AON_APB_PLD_ID_0 SCI_ADDR(REGS_AON_APB_BASE, 0x00E0)/*PLD_ID_0*/ +#define REG_AON_APB_PLD_ID_1 SCI_ADDR(REGS_AON_APB_BASE, 0x00E4)/*PLD_ID_1*/ +#define REG_AON_APB_PROJ_ID_0 SCI_ADDR(REGS_AON_APB_BASE, 0x00E8)/*PROJ_ID_0*/ +#define REG_AON_APB_PROJ_ID_1 SCI_ADDR(REGS_AON_APB_BASE, 0x00EC)/*PROJ_ID_1*/ +#define REG_AON_APB_DERIVED_ID SCI_ADDR(REGS_AON_APB_BASE, 0x00F4)/*DERIVED_ID*/ +#define REG_AON_APB_MANU_ID SCI_ADDR(REGS_AON_APB_BASE, 0x00F8)/*MANU_ID*/ +#define REG_AON_APB_IMP_ID SCI_ADDR(REGS_AON_APB_BASE, 0x00FC)/*IMP_ID*/ +#define REG_AON_APB_CCIR_RCVR_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0100)/*CCIR_RCVR_CFG*/ +#define REG_AON_APB_PLL_BG_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0108)/*PLL_BG_CFG*/ +#define REG_AON_APB_LVDSDIS_SEL SCI_ADDR(REGS_AON_APB_BASE, 0x010C)/*LVDSDIS_SEL*/ +#define REG_AON_APB_DJTAG_MUX_SEL SCI_ADDR(REGS_AON_APB_BASE, 0x0110)/*DJTAG_MUX_SEL*/ +#define REG_AON_APB_ARM7_SYS_SOFT_RST SCI_ADDR(REGS_AON_APB_BASE, 0x0114)/*ARM7_SYS_SOFT_RST*/ +#define REG_AON_APB_CP1_CP0_ADDR_MSB SCI_ADDR(REGS_AON_APB_BASE, 0x0118)/*CP1_CP0_ADDR_MSB*/ +#define REG_AON_APB_AON_DMA_INT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x011C)/*AON_DMA_INT_EN*/ +#define REG_AON_APB_EMC_AUTO_GATE_EN SCI_ADDR(REGS_AON_APB_BASE, 0x0120)/*EMC_AUTO_GATE_EN*/ +#define REG_AON_APB_ARM7_CFG_BUS SCI_ADDR(REGS_AON_APB_BASE, 0x0124)/*ARM7_CFG_BUS*/ +#define REG_AON_APB_RTC4M_0_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0128)/*RTC4M_0_CFG*/ +#define REG_AON_APB_RTC4M_1_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x012C)/*RTC4M_1_CFG*/ +#define REG_AON_APB_APB_RST2 SCI_ADDR(REGS_AON_APB_BASE, 0x0130)/*AHB_RST2*/ +#define REG_AON_APB_OSC_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0134)/*CA53_OSC_CTRL*/ +#define REG_AON_APB_OSC_OBS SCI_ADDR(REGS_AON_APB_BASE, 0x0138)/*CA53_OSC_OBS*/ +#define REG_AON_APB_AP_SDISABLE SCI_ADDR(REGS_AON_APB_BASE, 0x013C)/*APCPU_SDISABLE*/ +#define REG_AON_APB_MPLL0_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0140)/*MPLL0_CFG1*/ +#define REG_AON_APB_MPLL0_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0144)/*MPLL0_CFG2*/ +#define REG_AON_APB_GPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0148)/*GPLL_CFG1*/ +#define REG_AON_APB_GPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x014C)/*GPLL_CFG2*/ +#define REG_AON_APB_UPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0150)/*UPLL_CFG1*/ +#define REG_AON_APB_UPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0154)/*UPLL_CFG2*/ +#define REG_AON_APB_APCPU_CCI_CKG_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0158)/*APCPU_CCI_CKG_CFG*/ +#define REG_AON_APB_AP_MODULE_FOLLOW_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x15C)/*AP_MODULE_FOLLOW_CTRL*/ +#define REG_AON_APB_AVS_SOFT_RST SCI_ADDR(REGS_AON_APB_BASE, 0x0160)/*AVS_SOFT_RST*/ +#define REG_AON_APB_AP_IRAM_REMAP SCI_ADDR(REGS_AON_APB_BASE, 0x0164)/*AP_IRAM_REMAP*/ +#define REG_AON_APB_APCPU_BIG_SOFT_RST SCI_ADDR(REGS_AON_APB_BASE, 0x0168)/*APCPU_BIG_SOFT_RST*/ +#define REG_AON_APB_APCPU_LIT_SOFT_RST SCI_ADDR(REGS_AON_APB_BASE, 0x016c)/*APCPU_LIT_SOFT_RST*/ +#define REG_AON_APB_APCPU_TOP_SOFT_RST SCI_ADDR(REGS_AON_APB_BASE, 0x0170)/*APCPU_TOP_SOFT_RST*/ +#define REG_AON_APB_CA5_BIG_THM_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x01A0)/*CA5_BIG_THM_CTRL*/ +#define REG_AON_APB_CA5_LIT_THM_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x01A4)/*CA5_LIT_THM_CTRL*/ +#define REG_AON_APB_A53_BIGCORE_VDROP SNSR_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x01A8)/*A53_BIGCORE_VDROP SNSR_CTRL*/ +#define REG_AON_APB_A53_LITCORE_VDROP SNSR_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x01AC)/*A53_LITCORE_VDROP SNSR_CTRL*/ +#define REG_AON_APB_A53_AUTO_REG_SAVE_CRTL SCI_ADDR(REGS_AON_APB_BASE, 0x01B0)/*A53_AUTO_REG_SAVE_CRTL*/ +#define REG_AON_APB_CSSYS_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x01B4)/*CSSYS_CFG*/ +#define REG_AON_APB_REDUN_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x01B8)/*REDUN_CFG*/ +#define REG_AON_APB_AP_WPROT_EN1 SCI_ADDR(REGS_AON_APB_BASE, 0x3004)/*AP_WPROT_EN1*/ +#define REG_AON_APB_CP0_WPROT_EN1 SCI_ADDR(REGS_AON_APB_BASE, 0x3008)/*CP0_WPROT_EN1*/ +#define REG_AON_APB_CP1_WPROT_EN1 SCI_ADDR(REGS_AON_APB_BASE, 0x300C)/*CP1_WPROT_EN1*/ +#define REG_AON_APB_IO_DLY_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x3014)/*IO_DLY_CTRL*/ +#define REG_AON_APB_AP_WPROT_EN0 SCI_ADDR(REGS_AON_APB_BASE, 0x3018)/*AP_WPROT_EN0*/ +#define REG_AON_APB_CP0_WPROT_EN0 SCI_ADDR(REGS_AON_APB_BASE, 0x3020)/*CP0_WPROT_EN0*/ +#define REG_AON_APB_CP1_WPROT_EN0 SCI_ADDR(REGS_AON_APB_BASE, 0x3024)/*CP1_WPROT_EN0*/ +#define REG_AON_APB_PMU_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x302C)/*PMU_RST_MONITOR*/ +#define REG_AON_APB_THM_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3030)/*THM_RST_MONITOR*/ +#define REG_AON_APB_AP_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3034)/*AP_RST_MONITOR*/ +#define REG_AON_APB_APCPU_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3038)/*APCPU_RST_MONITOR*/ +#define REG_AON_APB_BOND_OPT0 SCI_ADDR(REGS_AON_APB_BASE, 0x303C)/*BOND_OPT0*/ +#define REG_AON_APB_BOND_OPT1 SCI_ADDR(REGS_AON_APB_BASE, 0x3040)/*BOND_OPT1*/ +#define REG_AON_APB_RES_REG0 SCI_ADDR(REGS_AON_APB_BASE, 0x3044)/*RES_REG0*/ +#define REG_AON_APB_RES_REG1 SCI_ADDR(REGS_AON_APB_BASE, 0x3048)/*RES_REG1*/ +#define REG_AON_APB_AON_QOS_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x304C)/*AON_QOS_CFG*/ +#define REG_AON_APB_BB_LDO_CAL_START SCI_ADDR(REGS_AON_APB_BASE, 0x3050)/*BB_LDO_CAL_START*/ +#define REG_AON_APB_AON_MTX_PROT_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3058)/*AON_MTX_PROT_CFG*/ +#define REG_AON_APB_LVDS_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3060)/*LVDS_CFG*/ +#define REG_AON_APB_PLL_LOCK_OUT_SEL SCI_ADDR(REGS_AON_APB_BASE, 0x3064)/*PLL_LOCK_OUT_SEL*/ +#define REG_AON_APB_RTC4M_RC_VAL SCI_ADDR(REGS_AON_APB_BASE, 0x3068)/*RTC4M_RC_VAL*/ +#define REG_AON_APB_PROT_BUS_SECURE_EN SCI_ADDR(REGS_AON_APB_BASE, 0x3080)/*PROT_BUS_SECURE_EN*/ +#define REG_AON_APB_PROT_ARM7_SPACE_EN SCI_ADDR(REGS_AON_APB_BASE, 0x3084)/*PROT_ARM7_SPACE_EN*/ +#define REG_AON_APB_AON_APB_RSV SCI_ADDR(REGS_AON_APB_BASE, 0x30F0)/*AON_APB_RSV*/ + + + +/* bits definitions for register REG_AON_APB_APB_EB0 */ +#define BIT_I2C_EB ( BIT(31) ) +#define BIT_APCPU_DAP_EB ( BIT(30) ) +#define BIT_APCPU_TS1_EB ( BIT(29) ) +#define BIT_APCPU_TS0_EB ( BIT(28) ) +#define BIT_CA7_DAP_EB BIT_APCPU_DAP_EB +#define BIT_CA7_TS1_EB BIT_APCPU_TS1_EB +#define BIT_CA7_TS0_EB BIT_APCPU_TS0_EB +#define BIT_GPU_EB ( BIT(27) ) +#define BIT_CKG_EB ( BIT(26) ) +#define BIT_AON_CKG_EB BIT_CKG_EB +#define BIT_MM_EB ( BIT(25) ) +#define BIT_AP_WDG_EB ( BIT(24) ) +#define BIT_MSPI_EB ( BIT(23) ) +#define BIT_SPLK_EB ( BIT(22) ) +#define BIT_IPI_EB ( BIT(21) ) +#define BIT_PIN_EB ( BIT(20) ) +#define BIT_VBC_EB ( BIT(19) ) +#define BIT_AUD_EB ( BIT(18) ) +#define BIT_AUDIF_EB ( BIT(17) ) +#define BIT_ADI_EB ( BIT(16) ) +#define BIT_INTC_EB ( BIT(15) ) +#define BIT_EIC_EB ( BIT(14) ) +#define BIT_EFUSE_EB ( BIT(13) ) +#define BIT_AP_TMR0_EB ( BIT(12) ) +#define BIT_AON_TMR_EB ( BIT(11) ) +#define BIT_AP_SYST_EB ( BIT(10) ) +#define BIT_AON_SYST_EB ( BIT(9) ) +#define BIT_KPD_EB ( BIT(8) ) +#define BIT_PWM3_EB ( BIT(7) ) +#define BIT_PWM2_EB ( BIT(6) ) +#define BIT_PWM1_EB ( BIT(5) ) +#define BIT_PWM0_EB ( BIT(4) ) +#define BIT_GPIO_EB ( BIT(3) ) +#define BIT_AON_GPIO_EB ( BIT_GPIO_EB ) +#define BIT_TPC_EB ( BIT(2) ) +#define BIT_FM_EB ( BIT(1) ) +#define BIT_ADC_EB ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_APB_EB1 */ +#define BIT_CODEC_EB ( BIT(31) ) +#define BIT_CSSYS_EB ( BIT(30) ) +#define BIT_CA53_LIT_AVS_EB ( BIT(29) ) +#define BIT_CA53_BIG_AVS_EB ( BIT(28) ) +#define BIT_ORP_JTAG_EB ( BIT(27) ) +#define BIT_CA5_TS0_EB ( BIT(26) ) +#define BIT_DEF_EB ( BIT(25) ) +#define BIT_LVDS_PLL_DIV_EN ( BIT(24) ) +#define BIT_ARM7_JTAG_EB ( BIT(23) ) +#define BIT_AON_DMA_EB ( BIT(22) ) +#define BIT_MBOX_EB ( BIT(21) ) +#define BIT_DJTAG_EB ( BIT(20) ) +#define BIT_RTC4M1_CAL_EB ( BIT(19) ) +#define BIT_RTC4M0_CAL_EB ( BIT(18) ) +#define BIT_MDAR_EB ( BIT(17) ) +#define BIT_LVDS_TCXO_EB ( BIT(16) ) +#define BIT_LVDS_TRX_EB ( BIT(15) ) +#define BIT_CA5_DAP_EB ( BIT(14) ) +#define BIT_GSP_EMC_EB ( BIT(13) ) +#define BIT_ZIP_EMC_EB ( BIT(12) ) +#define BIT_DISP_EMC_EB ( BIT(11) ) +#define BIT_AP_TMR2_EB ( BIT(10) ) +#define BIT_AP_TMR1_EB ( BIT(9) ) +#define BIT_APCPU_WDG_EB ( BIT(8) ) +#define BIT_CCI_EB ( BIT(7) ) +#define BIT_CA7_WDG_EB BIT_APCPU_WDG_EB +#define BIT_AVS_EB ( BIT(6) ) +#define BIT_PROBE_EB ( BIT(5) ) +#define BIT_AUX2_EB ( BIT(4) ) +#define BIT_AUX1_EB ( BIT(3) ) +#define BIT_AUX0_EB ( BIT(2) ) +#define BIT_THM_EB ( BIT(1) ) +#define BIT_PMU_EB ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_APB_RST0 */ +#define BIT_CA5_TS0_SOFT_RST ( BIT(31) ) +#define BIT_I2C_SOFT_RST ( BIT(30) ) +#define BIT_APCPU_TS1_SOFT_RST ( BIT(29) ) +#define BIT_APCPU_TS0_SOFT_RST ( BIT(28) ) +#define BIT_CA7_TS1_SOFT_RST BIT_APCPU_TS1_SOFT_RST +#define BIT_CA7_TS0_SOFT_RST BIT_APCPU_TS0_SOFT_RST +#define BIT_DAP_MTX_SOFT_RST ( BIT(27) ) +#define BIT_MSPI1_SOFT_RST ( BIT(26) ) +#define BIT_MSPI0_SOFT_RST ( BIT(25) ) +#define BIT_SPLK_SOFT_RST ( BIT(24) ) +#define BIT_IPI_SOFT_RST ( BIT(23) ) +#define BIT_CKG_SOFT_RST ( BIT(22) ) +#define BIT_AON_CKG_SOFT_RST BIT_CKG_SOFT_RST +#define BIT_PIN_SOFT_RST ( BIT(21) ) +#define BIT_VBC_SOFT_RST ( BIT(20) ) +#define BIT_AUD_SOFT_RST ( BIT(19) ) +#define BIT_AUDIF_SOFT_RST ( BIT(18) ) +#define BIT_ADI_SOFT_RST ( BIT(17) ) +#define BIT_INTC_SOFT_RST ( BIT(16) ) +#define BIT_EIC_SOFT_RST ( BIT(15) ) +#define BIT_EFUSE_SOFT_RST ( BIT(14) ) +#define BIT_AP_WDG_SOFT_RST ( BIT(13) ) +#define BIT_AP_TMR0_SOFT_RST ( BIT(12) ) +#define BIT_AON_TMR_SOFT_RST ( BIT(11) ) +#define BIT_AP_SYST_SOFT_RST ( BIT(10) ) +#define BIT_AON_SYST_SOFT_RST ( BIT(9) ) +#define BIT_KPD_SOFT_RST ( BIT(8) ) +#define BIT_PWM3_SOFT_RST ( BIT(7) ) +#define BIT_PWM2_SOFT_RST ( BIT(6) ) +#define BIT_PWM1_SOFT_RST ( BIT(5) ) +#define BIT_PWM0_SOFT_RST ( BIT(4) ) +#define BIT_GPIO_SOFT_RST ( BIT(3) ) +#define BIT_TPC_SOFT_RST ( BIT(2) ) +#define BIT_FM_SOFT_RST ( BIT(1) ) +#define BIT_ADC_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_APB_RST1 */ +#define BIT_RTC4M_ANA_SOFT_RST ( BIT(31) ) +#define BIT_DEF_SLV_INT_SOFT_CLR ( BIT(30) ) +#define BIT_DEF_SOFT_RST ( BIT(29) ) +#define BIT_ADC3_SOFT_RST ( BIT(28) ) +#define BIT_ADC2_SOFT_RST ( BIT(27) ) +#define BIT_ADC1_SOFT_RST ( BIT(26) ) +#define BIT_MBOX_SOFT_RST ( BIT(25) ) +#define BIT_RTC4M1_CAL_SOFT_RST ( BIT(23) ) +#define BIT_RTC4M0_CAL_SOFT_RST ( BIT(22) ) +#define BIT_LDSP_SYS_SOFT_RST ( BIT(21) ) +#define BIT_LCP_SYS_SOFT_RST ( BIT(20) ) +#define BIT_DAC3_SOFT_RST ( BIT(19) ) +#define BIT_DAC2_SOFT_RST ( BIT(18) ) +#define BIT_DAC1_SOFT_RST ( BIT(17) ) +#define BIT_ADC3_CAL_SOFT_RST ( BIT(16) ) +#define BIT_ADC2_CAL_SOFT_RST ( BIT(15) ) +#define BIT_ADC1_CAL_SOFT_RST ( BIT(14) ) +#define BIT_MDAR_SOFT_RST ( BIT(13) ) +#define BIT_LVDSDIS_SOFT_RST ( BIT(12) ) +#define BIT_BB_CAL_SOFT_RST ( BIT(11) ) +#define BIT_DCXO_LC_SOFT_RST ( BIT(10) ) +#define BIT_AP_TMR2_SOFT_RST ( BIT(9) ) +#define BIT_AP_TMR1_SOFT_RST ( BIT(8) ) +#define BIT_APCPU_WDG_SOFT_RST ( BIT(7) ) +#define BIT_CA7_WDG_SOFT_RST BIT_APCPU_WDG_SOFT_RST +#define BIT_AON_DMA_SOFT_RST ( BIT(6) ) +#define BIT_AVS_SOFT_RST ( BIT(5) ) +#define BIT_DMC_PHY_SOFT_RST ( BIT(4) ) +#define BIT_GPU_THMA_SOFT_RST ( BIT(3) ) +#define BIT_ARM_THMA_SOFT_RST ( BIT(2) ) +#define BIT_THM_SOFT_RST ( BIT(1) ) +#define BIT_PMU_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_APB_RTC_EB */ +#define BIT_CA53_BIG_THMA_RTC_EB ( BIT(20) ) +#define BIT_CP0_LTE_EB ( BIT(19) ) +#define BIT_BB_CAL_RTC_EB ( BIT(18) ) +#define BIT_DCXO_LC_RTC_EB ( BIT(17) ) +#define BIT_AP_TMR2_RTC_EB ( BIT(16) ) +#define BIT_AP_TMR1_RTC_EB ( BIT(15) ) +#define BIT_GPU_THMA_RTC_AUTO_EN ( BIT(14) ) +#define BIT_ARM_THMA_RTC_AUTO_EN ( BIT(13) ) +#define BIT_GPU_THMA_RTC_EB ( BIT(12) ) +#define BIT_CA53_LIT_THMA_RTC_EB ( BIT(11) ) +#define BIT_THM_RTC_EB ( BIT(10) ) +#define BIT_APCPU_WDG_RTC_EB ( BIT(9) ) +#define BIT_CA7_WDG_RTC_EB BIT_APCPU_WDG_RTC_EB +#define BIT_AP_WDG_RTC_EB ( BIT(8) ) +#define BIT_EIC_RTCDV5_EB ( BIT(7) ) +#define BIT_EIC_RTC_EB ( BIT(6) ) +#define BIT_AP_TMR0_RTC_EB ( BIT(5) ) +#define BIT_AON_TMR_RTC_EB ( BIT(4) ) +#define BIT_AP_SYST_RTC_EB ( BIT(3) ) +#define BIT_AON_SYST_RTC_EB ( BIT(2) ) +#define BIT_KPD_RTC_EB ( BIT(1) ) +#define BIT_ARCH_RTC_EB ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_REC_26MHZ_BUF_CFG */ +#define BITS_PLL_PROBE_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_REC_26MHZ_1_CUR_SEL ( BIT(4) ) +#define BIT_REC_26MHZ_0_CUR_SEL ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_SINDRV_CTRL */ +#define BITS_SINDRV_LVL(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)) ) +#define BIT_SINDRV_CLIP_MODE ( BIT(2) ) +#define BIT_SINDRV_ENA_SQUARE ( BIT(1) ) +#define BIT_SINDRV_ENA ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_ADA_SEL_CTRL */ +#define BIT_TW_MODE_SEL ( BIT(3) ) +#define BIT_WGADC_DIV_EN ( BIT(2) ) +#define BIT_AFCDAC_SYS_SEL ( BIT(1) ) +#define BIT_APCDAC_SYS_SEL ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_VBC_CTRL */ +#define BIT_AUDIF_CKG_AUTO_EN ( BIT(20) ) +#define BITS_AUD_INT_SYS_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_VBC_AFIFO_INT_SYS_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_VBC_AD23_INT_SYS_SEL(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_VBC_AD01_INT_SYS_SEL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_VBC_DA01_INT_SYS_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_VBC_AD23_DMA_SYS_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_VBC_AD01_DMA_SYS_SEL(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_VBC_DA01_DMA_SYS_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BIT_VBC_INT_CP0_ARM_SEL ( BIT(3) ) +#define BIT_VBC_INT_CP1_ARM_SEL ( BIT(2) ) +#define BIT_VBC_DMA_CP0_ARM_SEL ( BIT(1) ) +#define BIT_VBC_DMA_CP1_ARM_SEL ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_PWR_CTRL */ +#define BIT_HSIC_PLL_EN ( BIT(19) ) +#define BIT_HSIC_PHY_PD ( BIT(18) ) +#define BIT_HSIC_PS_PD_S ( BIT(17) ) +#define BIT_HSIC_PS_PD_L ( BIT(16) ) +#define BIT_MIPI_DSI_PS_PD_S ( BIT(15) ) +#define BIT_MIPI_DSI_PS_PD_L ( BIT(14) ) +#define BIT_MIPI_CSI_4LANE_PS_PD_S ( BIT(13) ) +#define BIT_MIPI_CSI_4LANE_PS_PD_L ( BIT(12) ) +#define BIT_MIPI_CSI_2LANE_PS_PD_S ( BIT(11) ) +#define BIT_MIPI_CSI_2LANE_PS_PD_L ( BIT(10) ) +#define BIT_APCPU_TS1_STOP ( BIT(9) ) +#define BIT_APCPU_TS0_STOP ( BIT(8) ) +#define BIT_CA7_TS1_STOP BIT_APCPU_TS1_STOP +#define BIT_CA7_TS0_STOP BIT_APCPU_TS0_STOP +#define BIT_EFUSE_BIST_PWR_ON ( BIT(3) ) +#define BIT_FORCE_DSI_PHY_SHUTDOWNZ ( BIT(2) ) +#define BIT_FORCE_CSI_PHY_SHUTDOWNZ ( BIT(1) ) +#define BIT_USB_PHY_PD ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_TS_CFG */ +#define BIT_CSYSACK_TS_LP_2 ( BIT(13) ) +#define BIT_CSYSREQ_TS_LP_2 ( BIT(12) ) +#define BIT_CSYSACK_TS_LP_1 ( BIT(11) ) +#define BIT_CSYSREQ_TS_LP_1 ( BIT(10) ) +#define BIT_CSYSACK_TS_LP_0 ( BIT(9) ) +#define BIT_CSYSREQ_TS_LP_0 ( BIT(8) ) +#define BIT_EVENTACK_RESTARTREQ_TS01 ( BIT(4) ) +#define BIT_EVENT_RESTARTREQ_TS01 ( BIT(1) ) +#define BIT_EVENT_HALTREQ_TS01 ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_BOOT_MODE */ +#define BIT_ARM_JTAG_EN ( BIT(13) ) +#define BIT_WPLL_OVR_FREQ_SEL ( BIT(12) ) +#define BIT_PTEST_FUNC_ATSPEED_SEL ( BIT(8) ) +#define BIT_PTEST_FUNC_MODE ( BIT(7) ) +#define BIT_USB_DLOAD_EN ( BIT(4) ) +#define BIT_ARM_BOOT_MD3 ( BIT(3) ) +#define BIT_ARM_BOOT_MD2 ( BIT(2) ) +#define BIT_ARM_BOOT_MD1 ( BIT(1) ) +#define BIT_ARM_BOOT_MD0 ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_BB_BG_CTRL */ +#define BIT_BB_CON_BG ( BIT(22) ) +#define BITS_BB_BG_RSV(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)) ) +#define BITS_BB_LDO_V(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BIT_BB_BG_RBIAS_EN ( BIT(15) ) +#define BIT_BB_BG_IEXT_IB_EN ( BIT(14) ) +#define BITS_BB_LDO_REFCTRL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) ) +#define BIT_BB_LDO_AUTO_PD_EN ( BIT(11) ) +#define BIT_BB_LDO_SLP_PD_EN ( BIT(10) ) +#define BIT_BB_LDO_FORCE_ON ( BIT(9) ) +#define BIT_BB_LDO_FORCE_PD ( BIT(8) ) +#define BIT_BB_BG_AUTO_PD_EN ( BIT(3) ) +#define BIT_BB_BG_SLP_PD_EN ( BIT(2) ) +#define BIT_BB_BG_FORCE_ON ( BIT(1) ) +#define BIT_BB_BG_FORCE_PD ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_CP_ARM_JTAG_CTRL */ +#define BIT_AON_ETM_PIN_SEL ( BIT(3) ) +#define BITS_CP_ARM_JTAG_PIN_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AON_APB_PLL_SOFT_CNT_DONE */ +#define BIT_RC1_SOFT_CNT_DONE ( BIT(13) ) +#define BIT_RC0_SOFT_CNT_DONE ( BIT(12) ) +#define BIT_XTLBUF1_SOFT_CNT_DONE ( BIT(9) ) +#define BIT_XTLBUF0_SOFT_CNT_DONE ( BIT(8) ) +#define BIT_GPLL_SOFT_CNT_DONE ( BIT(6) ) +#define BIT_MPLL_SOFT_CNT_DONE ( BIT(5) ) +#define BIT_LVDSPLL_SOFT_CNT_DONE ( BIT(4) ) +#define BIT_LPLL_SOFT_CNT_DONE ( BIT(3) ) +#define BIT_TWPLL_SOFT_CNT_DONE ( BIT(2) ) +#define BIT_DPLL_SOFT_CNT_DONE ( BIT(1) ) +#define BIT_MPLL0_SOFT_CNT_DONE ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_DCXO_LC_REG0 */ +#define BIT_DCXO_LC_FLAG ( BIT(8) ) +#define BIT_DCXO_LC_FLAG_CLR ( BIT(1) ) +#define BIT_DCXO_LC_CNT_CLR ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_DCXO_LC_REG1 */ +#define BITS_DCXO_LC_CNT(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_MPLL_CFG1 */ +#define BITS_MPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)) ) +#define BIT_MPLL_LOCK_DONE ( BIT(27) ) +#define BIT_MPLL_DIV_S ( BIT(26) ) +#define BIT_MPLL_MOD_EN ( BIT(25) ) +#define BIT_MPLL_SDM_EN ( BIT(24) ) +#define BITS_MPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_MPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_MPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_MPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AON_APB_MPLL_CFG2 */ +#define BITS_MPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_MPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_AON_APB_DPLL_CFG1 */ +#define BITS_DPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)) ) +#define BIT_DPLL_LOCK_DONE ( BIT(27) ) +#define BIT_DPLL_DIV_S ( BIT(26) ) +#define BIT_DPLL_MOD_EN ( BIT(25) ) +#define BIT_DPLL_SDM_EN ( BIT(24) ) +#define BITS_DPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_DPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_DPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_DPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AON_APB_DPLL_CFG2 */ +#define BITS_DPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_DPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_AON_APB_TWPLL_CFG1 */ +#define BITS_TWPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)) ) +#define BIT_TWPLL_LOCK_DONE ( BIT(27) ) +#define BIT_TWPLL_DIV_S ( BIT(26) ) +#define BIT_TWPLL_MOD_EN ( BIT(25) ) +#define BIT_TWPLL_SDM_EN ( BIT(24) ) +#define BITS_TWPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_TWPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_TWPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_TWPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AON_APB_TWPLL_CFG2 */ +#define BITS_TWPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_TWPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_AON_APB_LTEPLL_CFG1 */ +#define BITS_LTEPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)) ) +#define BIT_LTEPLL_LOCK_DONE ( BIT(27) ) +#define BIT_LTEPLL_DIV_S ( BIT(26) ) +#define BIT_LTEPLL_MOD_EN ( BIT(25) ) +#define BIT_LTEPLL_SDM_EN ( BIT(24) ) +#define BITS_LTEPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_LTEPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_LTEPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_LTEPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AON_APB_LTEPLL_CFG2 */ +#define BITS_LTEPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_LTEPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_AON_APB_LVDSDISPLL_CFG1 */ +#define BITS_LVDSDISPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_LVDSDISPLL_LOCK_DONE ( BIT(27) ) +#define BIT_LVDSDISPLL_DIV_S ( BIT(26) ) +#define BIT_LVDSDISPLL_MOD_EN ( BIT(25) ) +#define BIT_LVDSDISPLL_SDM_EN ( BIT(24) ) +#define BITS_LVDSDISPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_LVDSDISPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_LVDSDISPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_LVDSDISPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AON_APB_LVDSDISPLL_CFG2 */ +#define BITS_LVDSDISPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_LVDSDISPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_AON_APB_AON_REG_PROT */ +#define BIT_LDSP_CTRL_PROT ( BIT(31) ) +#define BITS_REG_PROT_VAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AON_APB_LDSP_BOOT_EN */ +#define BIT_FRC_CLK_LDSP_EN ( BIT(1) ) +#define BIT_LDSP_BOOT_EN ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_LDSP_BOOT_VEC */ +#define BITS_LDSP_BOOT_VECTOR(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_LDSP_RST */ +#define BIT_LDSP_SYS_SRST ( BIT(1) ) +#define BIT_LDSP_CORE_SRST_N ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_LDSP_MTX_CTRL1 */ +#define BITS_LDSP_MTX_CTRL1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_LDSP_MTX_CTRL2 */ +#define BITS_LDSP_MTX_CTRL2(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_LDSP_MTX_CTRL3 */ +#define BITS_LDSP_MTX_CTRL3(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_AON_CGM_CFG */ +#define BITS_PROBE_CKG_DIV(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_AUX2_CKG_DIV(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_AUX1_CKG_DIV(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_AUX0_CKG_DIV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_PROBE_CKG_SEL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_AUX2_CKG_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_AUX1_CKG_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_AUX0_CKG_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_LACC_MTX_CTRL */ +#define BITS_LACC_MTX_CTRL(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CORTEX_MTX_CTRL1 */ +#define BITS_CORTEX_MTX_CTRL1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CORTEX_MTX_CTRL2 */ +#define BITS_CORTEX_MTX_CTRL2(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CORTEX_MTX_CTRL3 */ +#define BITS_CORTEX_MTX_CTRL3(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AON_APB_CA5_TCLK_DLY_LEN */ +#define BITS_CA5_TCLK_DLY_LEN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AON_APB_PLD_ID_0 */ +#define BITS_PLD_ID_0(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_PLD_ID_1 */ +#define BITS_PLD_ID_1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_PROJ_ID_0 */ +#define BITS_PROJ_ID_0(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_PROJ_ID_1 */ +#define BITS_PROJ_ID_1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_DERIVED_ID */ +#define BITS_DERIVED_ID(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_MF_ID(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_AON_APB_MANU_ID */ +#define BITS_PROCESS_ID(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_FOUNDRY_ID(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_AON_APB_IMP_ID */ +#define BITS_MEM_CMP(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_STD_CELL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_AON_APB_CCIR_RCVR_CFG */ +#define BITS_ANALOG_PLL_RSV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_ANALOG_TESTMUX(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_CCIR_SE ( BIT(1) ) +#define BIT_CCIR_IE ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_PLL_BG_CFG */ +#define BITS_PLL_BG_RSV(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BIT_PLL_BG_RBIAS_EN ( BIT(3) ) +#define BIT_PLL_BG_PD ( BIT(2) ) +#define BIT_PLL_BG_IEXT_IBEN ( BIT(1) ) +#define BIT_PLL_CON_BG ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_LVDSDIS_SEL */ +#define BITS_LVDSDIS_LOG_SEL(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)) ) +#define BIT_LVDSDIS_DBG_SEL ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_DJTAG_MUX_SEL */ +#define BIT_DJTAG_CODEC_SEL ( BIT(7) ) +#define BIT_DJTAG_AON_SEL ( BIT(6) ) +#define BIT_DJTAG_PUB_SEL ( BIT(5) ) +#define BIT_DJTAG_CP1_SEL ( BIT(4) ) +#define BIT_DJTAG_CP0_SEL ( BIT(3) ) +#define BIT_DJTAG_GPU_SEL ( BIT(2) ) +#define BIT_DJTAG_MM_SEL ( BIT(1) ) +#define BIT_DJTAG_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_ARM7_SYS_SOFT_RST */ +#define BIT_ARM7_SYS_SOFT_RST ( BIT(4) ) +#define BIT_ARM7_CORE_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_CP1_CP0_ADDR_MSB */ +#define BITS_CP1_CP0_ADDR_MSB(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_AON_DMA_INT_EN */ +#define BIT_AON_DMA_INT_ARM7_EN ( BIT(6) ) +#define BIT_AON_DMA_INT_CP1_DSP_EN ( BIT(5) ) +#define BIT_AON_DMA_INT_CP1_CA5_EN ( BIT(4) ) +#define BIT_AON_DMA_INT_CP0_DSP_1_EN ( BIT(3) ) +#define BIT_AON_DMA_INT_CP0_DSP_0_EN ( BIT(2) ) +#define BIT_AON_DMA_INT_CP0_ARM9_0_EN ( BIT(1) ) +#define BIT_AON_DMA_INT_AP_EN ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_EMC_AUTO_GATE_EN */ +#define BIT_CP1_PUB_AUTO_GATE_EN ( BIT(19) ) +#define BIT_CP0_PUB_AUTO_GATE_EN ( BIT(18) ) +#define BIT_AP_PUB_AUTO_GATE_EN ( BIT(17) ) +#define BIT_AON_APB_PUB_AUTO_GATE_EN ( BIT(16) ) +#define BIT_CP1_EMC_AUTO_GATE_EN ( BIT(3) ) +#define BIT_CP0_EMC_AUTO_GATE_EN ( BIT(2) ) +#define BIT_AON_AP_EMC_AUTO_GATE_EN ( BIT(1) ) +#define BIT_AON_APCPU_EMC_AUTO_GATE_EN ( BIT(0) ) +#define BIT_AON_CA7_EMC_AUTO_GATE_EN ( BIT_AON_APCPU_EMC_AUTO_GATE_EN ) + +/* bits definitions for register REG_AON_APB_ARM7_CFG_BUS */ +#define BIT_ARM7_CFG_BUS_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_RTC4M_0_CFG */ +#define BITS_RTC4M0_RSV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RTC4M0_I_C(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BIT_RTC4M0_CAL_DONE ( BIT(6) ) +#define BIT_RTC4M0_CAL_START ( BIT(5) ) +#define BIT_RTC4M0_CHOP_EN ( BIT(4) ) +#define BIT_RTC4M0_FORCE_EN ( BIT(1) ) +#define BIT_RTC4M0_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_RTC4M_1_CFG */ +#define BITS_RTC4M1_RSV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RTC4M1_I_C(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BIT_RTC4M1_CAL_DONE ( BIT(6) ) +#define BIT_RTC4M1_CAL_START ( BIT(5) ) +#define BIT_RTC4M1_CHOP_EN ( BIT(4) ) +#define BIT_RTC4M1_FORCE_EN ( BIT(1) ) +#define BIT_RTC4M1_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_APB_RST2 */ +#define BIT_CODEC_DJTAG_SOFT_RST ( BIT(7) ) +#define BIT_AON_DJTAG_SOFT_RST ( BIT(6) ) +#define BIT_PUB_DJTAG_SOFT_RST ( BIT(5) ) +#define BIT_GPU_DJTAG_SOFT_RST ( BIT(4) ) +#define BIT_MM_DJTAG_SOFT_RST ( BIT(3) ) +#define BIT_CP1_DJTAG_SOFT_RST ( BIT(2) ) +#define BIT_CP0_DJTAG_SOFT_RST ( BIT(1) ) +#define BIT_AP_DJTAG_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_OSC_CTRL */ +#define BITS_OSC_CTRL_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BIT_OSC_CTRL_EN ( BIT(15) ) +#define BIT_OSC_CTRL_START ( BIT(14) ) +#define BIT_OSC_CTRL_RSTN ( BIT(13) ) +#define BITS_OSC_CTRL_CLK_NUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) + +/* bits definitions for register REG_AON_APB_OSC_OBS */ +#define BIT_OSC_OBS_OVERFLOW ( BIT(15) ) +#define BITS_OSC_OBS_SPEED_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register REG_AON_APB_APCPU_SDISABLE */ +#define BITS_APCPU_BIG_CP15SDISABLE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BIT_APCPU_CFGSDISABLE ( BIT(4) ) +#define BITS_APCPU_LIT_CP15SDISABLE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_MPLL0_CFG1 */ +#define BITS_MPLL0_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)) ) +#define BIT_MPLL0_LOCK_DONE ( BIT(27) ) +#define BIT_MPLL0_DIV_S ( BIT(26) ) +#define BIT_MPLL0_MOD_EN ( BIT(25) ) +#define BIT_MPLL0_SDM_EN ( BIT(24) ) +#define BITS_MPLL0_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_MPLL0_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_MPLL0_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_MPLL0_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AON_APB_MPLL0_CFG2 */ +#define BITS_MPLL0_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_MPLL0_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_AON_APB_GPLL_CFG1 */ +#define BITS_GPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)) ) +#define BIT_GPLL_LOCK_DONE ( BIT(27) ) +#define BIT_GPLL_DIV_S ( BIT(26) ) +#define BIT_GPLL_MOD_EN ( BIT(25) ) +#define BIT_GPLL_SDM_EN ( BIT(24) ) +#define BITS_GPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_GPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_GPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_GPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AON_APB_GPLL_CFG2 */ +#define BITS_GPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_GPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_AON_APB_UPLL_CFG1 */ +#define BITS_UPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)) ) +#define BIT_UPLL_LOCK_DONE ( BIT(27) ) +#define BIT_UPLL_DIV_S ( BIT(26) ) +#define BIT_UPLL_MOD_EN ( BIT(25) ) +#define BIT_UPLL_SDM_EN ( BIT(24) ) +#define BITS_UPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_UPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_UPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_UPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AON_APB_UPLL_CFG2 */ +#define BITS_UPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_UPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_AON_APB_APCPU_CCI_CKG_CFG */ +#define BIT_APCPU_CCI_CKG_EN ( BIT(1) ) +#define BIT_APCPU_CCI_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_AP_MODULE_FOLLOW_CTRL */ +#define BIT_AP_GPU_CLK_FOLLOW_AP ( BIT(2) ) +#define BIT_AP_MM_CODEC_CLK_FOLLOW_AP ( BIT(1) ) +#define BIT_AP_MM_CLK_FOLLOW_AP ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_AVS_SOFT_RST */ +#define BIT_CA53_LIT_AVS_SOFT_RST ( BIT(2) ) +#define BIT_CA53_BIG_AVS_SOFT_RST ( BIT(1) ) +#define BIT_GPU_AVS_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_AP_IRAM_REMAP */ +#define BIT_AP_IRAM_REMAP ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_APCPU_BIG_SOFT_RST */ +#define BIT_APCPU_BIG_DBG_SOFT_RST ( BIT(9) ) +#define BIT_APCPU_BIG_L2_SOFT_RST ( BIT(8) ) +#define BITS_APCPU_BIG_ATB_SOFT_RST(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_APCPU_BIG_CORE_SOFT_RST(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_APCPU_LIT_SOFT_RST */ +#define BIT_APCPU_LIT_DBG_SOFT_RST ( BIT(9) ) +#define BIT_APCPU_LIT_L2_SOFT_RST ( BIT(8) ) +#define BITS_APCPU_LIT_ATB_SOFT_RST(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_APCPU_LIT_CORE_SOFT_RST(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_APCPU_TOP_SOFT_RST */ +#define BIT_APCPU_MTX_SOFT_RST ( BIT(2) ) +#define BIT_APCPU_EMC_SOFT_RST ( BIT(1) ) +#define BIT_APCPU_DAP_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_CA5_BIG_THM_CTRL */ +#define BITS_CA53_BIG_THM_CALI_RSVD(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_AON_APB_CA5_LIT_THM_CTRL */ +#define BITS_CA53_LIT_THM_CALI_RSVD(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_AON_APB_A53_BIGCORE_VDROP SNSR_CTRL */ +#define BITS_CA53_BIG_VDROP1_RESERVED_CTRL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_CA53_BIG_VDROP1_CTRL(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)) ) +#define BITS_CA53_BIG_VDROP1_CURRENT_CTRL(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)) ) +#define BIT_CA53_BIG_VDROP1_OUT ( BIT(17) ) +#define BIT_CA53_BIG_VDROP1_EN ( BIT(16) ) +#define BITS_CA53_BIG_VDROP0_RESERVED_CTRL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CA53_BIG_VDROP0_CTRL(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_CA53_BIG_VDROP0_CURRENT_CTRL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BIT_CA53_BIG_VDROP0_OUT ( BIT(1) ) +#define BIT_CA53_BIG_VDROP0_EN ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_A53_LITCORE_VDROP SNSR_CTRL */ +#define BITS_CA53_LIT_VDROP1_RESERVED_CTRL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_CA53_LIT_VDROP1_CTRL(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)) ) +#define BITS_CA53_LIT_VDROP1_CURRENT_CTRL(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)) ) +#define BIT_CA53_LIT_VDROP1_OUT ( BIT(17) ) +#define BIT_CA53_LIT_VDROP1_EN ( BIT(16) ) +#define BITS_CA53_LIT_VDROP0_RESERVED_CTRL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CA53_LIT_VDROP0_CTRL(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_CA53_LIT_VDROP0_CURRENT_CTRL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BIT_CA53_LIT_VDROP0_OUT ( BIT(1) ) +#define BIT_CA53_LIT_VDROP0_EN ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_A53_AUTO_REG_SAVE_CRTL */ +#define BIT_APCPU_AUTO_REG_SAVE_TRIG_SEL ( BIT(1) ) +#define BIT_AUTO_REG_SAVE_EN ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_CSSYS_CFG */ +#define BIT_CSSYS_TPIU_TPCTL ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_REDUN_CFG */ +#define BIT_REDUN_CFG_3 ( BIT(3) ) +#define BIT_REDUN_CFG_2 ( BIT(2) ) +#define BIT_REDUN_CFG_1 ( BIT(1) ) +#define BIT_REDUN_CFG_0 ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_AP_WPROT_EN1 */ +#define BITS_AP_AWADDR_WPROT_EN1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CP0_WPROT_EN1 */ +#define BITS_CP0_AWADDR_WPROT_EN1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CP1_WPROT_EN1 */ +#define BITS_CP1_AWADDR_WPROT_EN1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_IO_DLY_CTRL */ +#define BITS_CLK_CCIR_DLY_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CLK_CP1DSP_DLY_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_CLK_CP0DSP_DLY_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_AP_WPROT_EN0 */ +#define BITS_AP_AWADDR_WPROT_EN0(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CP0_WPROT_EN0 */ +#define BITS_CP0_AWADDR_WPROT_EN0(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CP1_WPROT_EN0 */ +#define BITS_CP1_AWADDR_WPROT_EN0(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_PMU_RST_MONITOR */ +#define BITS_PMU_RST_MONITOR(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_THM_RST_MONITOR */ +#define BITS_THM_RST_MONITOR(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_AP_RST_MONITOR */ +#define BITS_AP_RST_MONITOR(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_APCPU_RST_MONITOR */ +#define BITS_APCPU_RST_MONITOR(_X_) (_X_) +#define BITS_CA7_RST_MONITOR(_X_) BITS_APCPU_RST_MONITOR + +/* bits definitions for register REG_AON_APB_BOND_OPT0 */ +#define BITS_BOND_OPTION0(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_BOND_OPT1 */ +#define BITS_BOND_OPTION1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_RES_REG0 */ +#define BITS_RES_REG0(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_RES_REG1 */ +#define BITS_RES_REG1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_AON_QOS_CFG */ +#define BITS_QOS_R_GPU(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_QOS_W_GPU(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_QOS_R_GSP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_QOS_W_GSP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_BB_LDO_CAL_START */ +#define BIT_BB_LDO_CAL_START ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_AON_MTX_PROT_CFG */ +#define BITS_AON_HPROT_DMAW(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_AON_HPROT_DMAR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_LVDS_CFG */ +#define BITS_LVDSDIS_TXCLKDATA(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_LVDSDIS_TXCOM(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_LVDSDIS_TXSLEW(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_LVDSDIS_TXSW(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_LVDSDIS_TXRERSER(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_LVDSDIS_PRE_EMP(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)) ) +#define BIT_LVDSDIS_TXPD ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_PLL_LOCK_OUT_SEL */ +#define BIT_SLEEP_PLLLOCK_SEL ( BIT(7) ) +#define BITS_PLL_LOCK_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BITS_SLEEP_DBG_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_RTC4M_RC_VAL */ +#define BIT_RTC4M1_RC_SEL ( BIT(31) ) +#define BITS_RTC4M1_RC_VAL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) ) +#define BIT_RTC4M0_RC_SEL ( BIT(15) ) +#define BITS_RTC4M0_RC_VAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) ) + +/* bits definitions for register REG_AON_APB_PROT_BUS_SECURE_EN */ +#define BIT_BUS_SECURE_EN ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_PROT_ARM7_SPACE_EN */ +#define BIT_ARM7_SPACE_EN ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_AON_APB_RSV */ +#define BITS_AON_APB_RSV(_X_) (_X_) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_aon_clk.h b/include/soc/sprd/chip_x35lt8/__regs_aon_clk.h new file mode 100644 index 00000000..04713eb0 --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_aon_clk.h @@ -0,0 +1,156 @@ +/* the head file modifier: g 2015-03-19 17:10:17*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_AON_CLK_CORE_HEADFILE_H__ +#define __H_REGS_AON_CLK_CORE_HEADFILE_H__ __FILE__ + +#define REGS_AON_CLK_CORE + +/* registers definitions for AON_CLK_CORE */ +#define REG_AON_CLK_CORE_clk_pub_ahb_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x20)/*clk_pub_ahb_cfg*/ +#define REG_AON_CLK_CORE_clk_aon_apb_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x24)/*clk_aon_apb_cfg*/ +#define REG_AON_CLK_CORE_clk_adi_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x28)/*clk_adi_cfg*/ +#define REG_AON_CLK_CORE_clk_pwm0_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x2c)/*clk_pwm0_cfg*/ +#define REG_AON_CLK_CORE_clk_pwm1_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x30)/*clk_pwm1_cfg*/ +#define REG_AON_CLK_CORE_clk_pwm2_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x34)/*clk_pwm2_cfg*/ +#define REG_AON_CLK_CORE_clk_pwm3_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x38)/*clk_pwm3_cfg*/ +#define REG_AON_CLK_CORE_clk_arm7_uart_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x3c)/*clk_arm7_uart_cfg*/ +#define REG_AON_CLK_CORE_clk_thm_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x40)/*clk_thm_cfg*/ +#define REG_AON_CLK_CORE_clk_mspi_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x44)/*clk_mspi_cfg*/ +#define REG_AON_CLK_CORE_clk_i2c_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x48)/*clk_i2c_cfg*/ +#define REG_AON_CLK_CORE_clk_gpu_avs_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x4c)/*clk_gpu_avs_cfg*/ +#define REG_AON_CLK_CORE_clk_audif_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x50)/*clk_audif_cfg*/ +#define REG_AON_CLK_CORE_clk_apcpu_dap_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x54)/*clk_apcpu_dap_cfg*/ +#define REG_AON_CLK_CORE_clk_emc_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x58)/*clk_emc_cfg*/ +#define REG_AON_CLK_CORE_clk_apcpu_ts_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x5c)/*clk_apcpu_ts_cfg*/ +#define REG_AON_CLK_CORE_clk_djtag_tck_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x60)/*clk_djtag_tck_cfg*/ +#define REG_AON_CLK_CORE_clk_arm7_ahb_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x64)/*clk_arm7_ahb_cfg*/ +#define REG_AON_CLK_CORE_clk_ca5_ts_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x68)/*clk_ca5_ts_cfg*/ +#define REG_AON_CLK_CORE_clk_ca53_big_avs_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x6c)/*clk_ca53_big_avs_cfg*/ +#define REG_AON_CLK_CORE_clk_ca53_lit_avs_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x70)/*clk_ca53_lit_avs_cfg*/ +#define REG_AON_CLK_CORE_clk_cci_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x74)/*clk_cci_cfg*/ +#define REG_AON_CLK_CORE_clk_cssys_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x78)/*clk_cssys_cfg*/ +/* registers definitions for controller REGS_AON_CLK */ +#define REG_AON_CLK_PUB_AHB_CFG REG_AON_CLK_CORE_clk_pub_ahb_cfg +#define REG_AON_CLK_AON_APB_CFG REG_AON_CLK_CORE_clk_aon_apb_cfg +#define REG_AON_CLK_ADI_CFG REG_AON_CLK_CORE_clk_adi_cfg +#define REG_AON_CLK_PWM0_CFG REG_AON_CLK_CORE_clk_pwm0_cfg +#define REG_AON_CLK_PWM1_CFG REG_AON_CLK_CORE_clk_pwm1_cfg +#define REG_AON_CLK_PWM2_CFG REG_AON_CLK_CORE_clk_pwm2_cfg +#define REG_AON_CLK_PWM3_CFG REG_AON_CLK_CORE_clk_pwm3_cfg +#define REG_AON_CLK_ARM7_UART_CFG REG_AON_CLK_CORE_clk_arm7_uart_cfg +#define REG_AON_CLK_THM_CFG REG_AON_CLK_CORE_clk_thm_cfg +#define REG_AON_CLK_MSPI_CFG REG_AON_CLK_CORE_clk_mspi_cfg +#define REG_AON_CLK_I2C_CFG REG_AON_CLK_CORE_clk_i2c_cfg +#define REG_AON_CLK_AVS_CFG REG_AON_CLK_CORE_clk_avs_cfg +#define REG_AON_CLK_AUDIF_CFG REG_AON_CLK_CORE_clk_audif_cfg +#define REG_AON_CLK_CA7_DAP_CFG REG_AON_CLK_CORE_clk_apcpu_dap_cfg +#define REG_AON_CLK_EMC_CFG REG_AON_CLK_CORE_clk_emc_cfg +#define REG_AON_CLK_CA7_TS_CFG REG_AON_CLK_CORE_clk_apcpu_ts_cfg +#define REG_AON_CLK_DJTAG_CLK_CFG REG_AON_CLK_CORE_clk_djtag_tck_cfg +#define REG_AON_CLK_ARM7_AHB_CFG REG_AON_CLK_CORE_clk_arm7_ahb_cfg +#define REG_AON_CLK_CA5_TS_CFG REG_AON_CLK_CORE_clk_ca5_ts_cfg +/* vars definitions for controller REGS_AON_CLK */ +#define PUB_AHB_CLK_SEL_SHIFT (0x0) +#define PUB_AHB_CLK_SEL_MASK (0x3 << PUB_AHB_CLK_SEL_SHIFT) + + +/* bits definitions for register REG_AON_CLK_CORE_clk_pub_ahb_cfg */ +#define BITS_CLK_PUB_AHB_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_CLK_PUB_AHB_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_aon_apb_cfg */ +#define BITS_CLK_AON_APB_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_CLK_AON_APB_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_adi_cfg */ +#define BITS_CLK_ADI_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_pwm0_cfg */ +#define BITS_CLK_PWM0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_pwm1_cfg */ +#define BITS_CLK_PWM1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_pwm2_cfg */ +#define BITS_CLK_PWM2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_pwm3_cfg */ +#define BITS_CLK_PWM3_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_arm7_uart_cfg */ +#define BITS_CLK_ARM7_UART_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_thm_cfg */ +#define BIT_CLK_THM_SEL ( BIT(0) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_mspi_cfg */ +#define BITS_CLK_MSPI_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_i2c_cfg */ +#define BITS_CLK_I2C_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_gpu_avs_cfg */ +#define BITS_CLK_GPU_AVS_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_audif_cfg */ +#define BITS_CLK_AUDIF_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_apcpu_dap_cfg */ +#define BITS_CLK_APCPU_DAP_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_emc_cfg */ +#define BITS_CLK_EMC_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_CLK_EMC_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_apcpu_ts_cfg */ +#define BITS_CLK_APCPU_TS_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_djtag_tck_cfg */ +#define BIT_CLK_DJTAG_TCK_PAD_SEL ( BIT(16) ) +#define BIT_CLK_DJTAG_TCK_SEL ( BIT(0) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_arm7_ahb_cfg */ +#define BITS_CLK_ARM7_AHB_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_CLK_ARM7_AHB_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_ca5_ts_cfg */ +#define BITS_CLK_CA5_TS_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_ca53_big_avs_cfg */ +#define BITS_CLK_CA53_BIG_AVS_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_ca53_lit_avs_cfg */ +#define BITS_CLK_CA53_LIT_AVS_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_cci_cfg */ +#define BITS_CLK_CCI_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_CLK_CCI_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_cssys_cfg */ +#define BITS_CLK_CSSYS_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_CLK_CSSYS_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_ap_ahb_rf.h b/include/soc/sprd/chip_x35lt8/__regs_ap_ahb_rf.h new file mode 100644 index 00000000..3ce3ad16 --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_ap_ahb_rf.h @@ -0,0 +1,552 @@ +/* the head file modifier: g 2015-03-19 15:39:58*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_AP_AHB_RF_HEADFILE_H__ +#define __H_REGS_AP_AHB_RF_HEADFILE_H__ __FILE__ + +#define REGS_AP_AHB_RF + +/* registers definitions for AP_AHB_RF */ +#define REG_AP_AHB_AHB_EB SCI_ADDR(REGS_AP_AHB_BASE, 0x0000)/*AHB_EB*/ +#define REG_AP_AHB_AHB_RST SCI_ADDR(REGS_AP_AHB_BASE, 0x0004)/*AHB_RST*/ +#define REG_AP_AHB_APCPU_RST_SET SCI_ADDR(REGS_AP_AHB_BASE, 0x0008)/*APCPU_RST_SET*/ +#define REG_AP_AHB_CA7_RST_SET REG_AP_AHB_APCPU_RST_SET +#define REG_AP_AHB_AP_SYS_FORCE_SLEEP_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x000C)/*AP_SYS_FORCE_SLEEP_CFG*/ +#define REG_AP_AHB_AP_SYS_AUTO_SLEEP_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x0010)/*AP_SYS_AUTO_SLEEP_CFG*/ +#define REG_AP_AHB_HOLDING_PEN SCI_ADDR(REGS_AP_AHB_BASE, 0x0014)/*HOLDING_PEN*/ +#define REG_AP_AHB_JMP_ADDR_APCPU_C0 SCI_ADDR(REGS_AP_AHB_BASE, 0x0018)/*JMP_ADDR_APCPU_C0*/ +#define REG_AP_AHB_JMP_ADDR_APCPU_C1 SCI_ADDR(REGS_AP_AHB_BASE, 0x001C)/*JMP_ADDR_APCPU_C1*/ +#define REG_AP_AHB_JMP_ADDR_APCPU_C2 SCI_ADDR(REGS_AP_AHB_BASE, 0x0020)/*JMP_ADDR_APCPU_C2*/ +#define REG_AP_AHB_JMP_ADDR_APCPU_C3 SCI_ADDR(REGS_AP_AHB_BASE, 0x0024)/*JMP_ADDR_APCPU_C3*/ +#define REG_AP_AHB_APCPU_C0_PU_LOCK SCI_ADDR(REGS_AP_AHB_BASE, 0x0028)/*APCPU_C0_PU_LOCK*/ +#define REG_AP_AHB_APCPU_C1_PU_LOCK SCI_ADDR(REGS_AP_AHB_BASE, 0x002C)/*APCPU_C1_PU_LOCK*/ +#define REG_AP_AHB_APCPU_C2_PU_LOCK SCI_ADDR(REGS_AP_AHB_BASE, 0x0030)/*APCPU_C2_PU_LOCK*/ +#define REG_AP_AHB_APCPU_C3_PU_LOCK SCI_ADDR(REGS_AP_AHB_BASE, 0x0034)/*APCPU_C3_PU_LOCK*/ +#define REG_AP_AHB_APCPU_CKG_DIV_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x0038)/*APCPU_CKG_DIV_CFG*/ +#define REG_AP_AHB_JMP_ADDR_CA7_C0 REG_AP_AHB_JMP_ADDR_APCPU_C0 +#define REG_AP_AHB_JMP_ADDR_CA7_C1 REG_AP_AHB_JMP_ADDR_APCPU_C1 +#define REG_AP_AHB_JMP_ADDR_CA7_C2 REG_AP_AHB_JMP_ADDR_APCPU_C2 +#define REG_AP_AHB_JMP_ADDR_CA7_C3 REG_AP_AHB_JMP_ADDR_APCPU_C3 +#define REG_AP_AHB_CA7_C0_PU_LOCK REG_AP_AHB_APCPU_C0_PU_LOCK +#define REG_AP_AHB_CA7_C1_PU_LOCK REG_AP_AHB_APCPU_C1_PU_LOCK +#define REG_AP_AHB_CA7_C2_PU_LOCK REG_AP_AHB_APCPU_C2_PU_LOCK +#define REG_AP_AHB_CA7_C3_PU_LOCK REG_AP_AHB_APCPU_C3_PU_LOCK +#define REG_AP_AHB_CA7_CKG_DIV_CFG REG_AP_AHB_APCPU_CKG_DIV_CFG +#define REG_AP_AHB_MCU_PAUSE SCI_ADDR(REGS_AP_AHB_BASE, 0x003C)/*MCU_PAUSE*/ +#define REG_AP_AHB_MISC_CKG_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x0040)/*MISC_CKG_EN*/ +#define REG_AP_AHB_APCPU_C0_AUTO_FORCE_SHUTDOWN_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x0044)/*APCPU_C0_AUTO_FORCE_SHUTDOWN_EN*/ +#define REG_AP_AHB_APCPU_C1_AUTO_FORCE_SHUTDOWN_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x0048)/*APCPU_C1_AUTO_FORCE_SHUTDOWN_EN*/ +#define REG_AP_AHB_APCPU_C2_AUTO_FORCE_SHUTDOWN_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x004C)/*APCPU_C2_AUTO_FORCE_SHUTDOWN_EN*/ +#define REG_AP_AHB_APCPU_C3_AUTO_FORCE_SHUTDOWN_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x0050)/*APCPU_C3_AUTO_FORCE_SHUTDOWN_EN*/ +#define REG_AP_AHB_APCPU_CKG_SEL_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x0054)/*APCPU_CKG_SEL_CFG*/ +#define REG_AP_AHB_APCPU_AUTO_GATE_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x0058)/*APCPU_AUTO_GATE_EN*/ +#define REG_AP_AHB_CA7_C0_AUTO_FORCE_SHUTDOWN_EN REG_AP_AHB_APCPU_C0_AUTO_FORCE_SHUTDOWN_EN +#define REG_AP_AHB_CA7_C1_AUTO_FORCE_SHUTDOWN_EN REG_AP_AHB_APCPU_C1_AUTO_FORCE_SHUTDOWN_EN +#define REG_AP_AHB_CA7_C2_AUTO_FORCE_SHUTDOWN_EN REG_AP_AHB_APCPU_C2_AUTO_FORCE_SHUTDOWN_EN +#define REG_AP_AHB_CA7_C3_AUTO_FORCE_SHUTDOWN_EN REG_AP_AHB_APCPU_C3_AUTO_FORCE_SHUTDOWN_EN +#define REG_AP_AHB_CA7_CKG_SEL_CFG REG_AP_AHB_APCPU_CKG_SEL_CFG +#define REG_AP_AHB_APCPU_GIC_CKG_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x005c)/*APCPU_GIC_CKG_CFG*/ +#define REG_AP_AHB_APCPU_GIC_CLK_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x0060)/*APCPU_GIC_CLK_CFG*/ +#define REG_AP_AHB_APCPU_LIT_CKG_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x0064)/*APCPU_LIT_CKG_EN*/ +#define REG_AP_AHB_APCPU_BIG_CKG_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x0068)/*APCPU_LIT_CKG_EN*/ +#define REG_AP_AHB_APCPU_LIT_L2FLUSH SCI_ADDR(REGS_AP_AHB_BASE, 0x006C)/*APCPU_LIT_L2FLUSH*/ +#define REG_AP_AHB_APCPU_BIG_L2FLUSH SCI_ADDR(REGS_AP_AHB_BASE, 0x0070)/*APCPU_BIG_L2FLUSH*/ +#define REG_AP_AHB_APCPU_CCI_BASE_H25 SCI_ADDR(REGS_AP_AHB_BASE, 0x0074)/*APCPU_CCI_BASE_H25*/ +#define REG_AP_AHB_APCPU_CCI_CTRL SCI_ADDR(REGS_AP_AHB_BASE, 0x0078)/*APCPU_CCI_CTRL*/ +#define REG_AP_AHB_MISC_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x3000)/*MISC_CFG*/ +#define REG_AP_AHB_AP_MAIN_MTX_HPROT_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x3004)/*AP_MAIN_MTX_HPROT_CFG*/ +#define REG_AP_AHB_APCPU_STANDBY_STATUS SCI_ADDR(REGS_AP_AHB_BASE, 0x3008)/*APCPU_STANDBY_STATUS*/ +#define REG_AP_AHB_CA7_STANDBY_STATUS REG_AP_AHB_APCPU_STANDBY_STATUS +#define REG_AP_AHB_NANC_CLK_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x300C)/*NANDC_CLK_CFG*/ +#define REG_AP_AHB_LVDS_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x3010)/*LVDS_CFG*/ +#define REG_AP_AHB_LVDS_PLL_CFG0 SCI_ADDR(REGS_AP_AHB_BASE, 0x3014)/*LVDS_PLL_CFG0*/ +#define REG_AP_AHB_LVDS_PLL_CFG1 SCI_ADDR(REGS_AP_AHB_BASE, 0x3018)/*LVDS_PLL_CFG1*/ +#define REG_AP_AHB_AP_QOS_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x301C)/*AP_QOS_CFG*/ +#define REG_AP_AHB_OTG_PHY_TUNE SCI_ADDR(REGS_AP_AHB_BASE, 0x3020)/*USB_PHY_TUNE*/ +#define REG_AP_AHB_OTG_PHY_TEST SCI_ADDR(REGS_AP_AHB_BASE, 0x3024)/*MISC_CKG_EN*/ +#define REG_AP_AHB_OTG_PHY_CTRL SCI_ADDR(REGS_AP_AHB_BASE, 0x3028)/*USB_PHY_CTRL*/ +#define REG_AP_AHB_HSIC_PHY_TUNE SCI_ADDR(REGS_AP_AHB_BASE, 0x302C)/*USB_PHY_TUNE*/ +#define REG_AP_AHB_HSIC_PHY_TEST SCI_ADDR(REGS_AP_AHB_BASE, 0x3030)/*MISC_CKG_EN*/ +#define REG_AP_AHB_HSIC_PHY_CTRL SCI_ADDR(REGS_AP_AHB_BASE, 0x3034)/*USB_PHY_CTRL*/ +#define REG_AP_AHB_ZIP_MTX_QOS_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x3038)/*ZIP_MTX_QOS_CFG*/ +#define REG_AP_AHB_APCPU_QCHN_CTL_BIG SCI_ADDR(REGS_AP_AHB_BASE, 0x303C)/*APCPU_QCHN_CTL_BIG*/ +#define REG_AP_AHB_APCPU_QCHN_STA_BIG SCI_ADDR(REGS_AP_AHB_BASE, 0x3040)/*APCPU_QCHN_STA_BIG*/ +#define REG_AP_AHB_APCPU_QCHN_CTL_LIT SCI_ADDR(REGS_AP_AHB_BASE, 0x3044)/*APCPU_QCHN_CTL_LIT*/ +#define REG_AP_AHB_APCPU_QCHN_STA_LIT SCI_ADDR(REGS_AP_AHB_BASE, 0x3048)/*APCPU_QCHN_STA_LIT*/ +#define REG_AP_AHB_GSP_SEL SCI_ADDR(REGS_AP_AHB_BASE, 0x304c)/*GSP_SEL*/ +#define REG_AP_AHB_RES_REG SCI_ADDR(REGS_AP_AHB_BASE, 0x30F0)/*RES_REG*/ +#define REG_AP_AHB_CHIP_ID SCI_ADDR(REGS_AP_AHB_BASE, 0x30FC)/*CHIP_ID*/ + + + +/* bits definitions for register REG_AP_AHB_AHB_EB */ +#define BIT_ZIPMTX_EB ( BIT(23) ) +#define BIT_LVDS_EB ( BIT(22) ) +#define BIT_ZIPDEC_EB ( BIT(21) ) +#define BIT_ZIPENC_EB ( BIT(20) ) +#define BIT_NANDC_ECC_EB ( BIT(19) ) +#define BIT_NANDC_2X_EB ( BIT(18) ) +#define BIT_NANDC_EB ( BIT(17) ) +#define BIT_BUSMON2_EB ( BIT(16) ) +#define BIT_BUSMON1_EB ( BIT(15) ) +#define BIT_BUSMON0_EB ( BIT(14) ) +#define BIT_SPINLOCK_EB ( BIT(13) ) +#define BIT_EMMC_EB ( BIT(11) ) +#define BIT_SDIO2_EB ( BIT(10) ) +#define BIT_SDIO1_EB ( BIT(9) ) +#define BIT_SDIO0_EB ( BIT(8) ) +#define BIT_DRM_EB ( BIT(7) ) +#define BIT_NFC_EB ( BIT(6) ) +#define BIT_DMA_EB ( BIT(5) ) +#define BIT_OTG_EB ( BIT(4) ) +#define BIT_USB_EB (BIT_OTG_EB) +#define BIT_GSP_EB ( BIT(3) ) +#define BIT_HSIC_EB ( BIT(2) ) +#define BIT_DISPC_EB ( BIT(1) ) +#define BIT_DISPC0_EB (BIT_DISPC_EB) +#define BIT_DSI_EB ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_AHB_RST */ +#define BIT_HSIC_PHY_SOFT_RST ( BIT(30) ) +#define BIT_HSIC_UTMI_SOFT_RST ( BIT(29) ) +#define BIT_HSIC_SOFT_RST ( BIT(28) ) +#define BIT_LVDS_SOFT_RST ( BIT(25) ) +#define BIT_ZIP_MTX_SOFT_RST ( BIT(24) ) +#define BIT_ZIPDEC_SOFT_RST ( BIT(23) ) +#define BIT_ZIPENC_SOFT_RST ( BIT(22) ) +#define BIT_CCI_SOFT_RST ( BIT(21) ) +#define BIT_NANDC_SOFT_RST ( BIT(20) ) +#define BIT_BUSMON2_SOFT_RST ( BIT(19) ) +#define BIT_BUSMON1_SOFT_RST ( BIT(18) ) +#define BIT_BUSMON0_SOFT_RST ( BIT(17) ) +#define BIT_SPINLOCK_SOFT_RST ( BIT(16) ) +#define BIT_EMMC_SOFT_RST ( BIT(14) ) +#define BIT_SDIO2_SOFT_RST ( BIT(13) ) +#define BIT_SDIO1_SOFT_RST ( BIT(12) ) +#define BIT_SDIO0_SOFT_RST ( BIT(11) ) +#define BIT_DRM_SOFT_RST ( BIT(10) ) +#define BIT_NFC_SOFT_RST ( BIT(9) ) +#define BIT_DMA_SOFT_RST ( BIT(8) ) +#define BIT_CSSYS_SOFT_RST ( BIT(7) ) +#define BIT_OTG_PHY_SOFT_RST ( BIT(6) ) +#define BIT_OTG_UTMI_SOFT_RST ( BIT(5) ) +#define BIT_OTG_SOFT_RST ( BIT(4) ) +#define BIT_GSP_SOFT_RST ( BIT(3) ) +#define BIT_DISP_MTX_SOFT_RST ( BIT(2) ) +#define BIT_DISPC_SOFT_RST ( BIT(1) ) +#define BIT_DSI_SOFT_RST ( BIT(0) ) +#define BIT_DISPC0_SOFT_RST (BIT_DISPC_SOFT_RST) + +/* bits definitions for register REG_AP_AHB_APCPU_RST_SET */ +#define BIT_AP_QCHN_BIG_SOFT_RST ( BIT(17) ) +#define BIT_AP_QCHN_LIT_SOFT_RST ( BIT(16) ) +#define BIT_APCPU_GIC_SOFT_RST ( BIT(15) ) +#define BIT_APCPU_CS_DBG_SOFT_RST ( BIT(14) ) +#define BIT_APCPU_SOCDBG_SOFT_RST ( BIT(12) ) +#define BITS_APCPU_ETM_SOFT_RST(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_APCPU_DBG_SOFT_RST(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_APCPU_CORE_SOFT_RST(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) +#define BIT_CA7_CS_DBG_SOFT_RST BIT_APCPU_CS_DBG_SOFT_RST +#define BIT_CA7_SOCDBG_SOFT_RST BIT_APCPU_SOCDBG_SOFT_RST +#define BITS_CA7_ETM_SOFT_RST(_x_) BITS_APCPU_ETM_SOFT_RST(_x_) +#define BITS_CA7_DBG_SOFT_RST(_x_) BITS_APCPU_DBG_SOFT_RST(_x_) +#define BITS_CA7_CORE_SOFT_RST(_x_) BITS_APCPU_CORE_SOFT_RST(_x_) + +/* bits definitions for register REG_AP_AHB_AP_SYS_FORCE_SLEEP_CFG */ +#define BIT_APCPU_C3_AUTO_SLP_EN ( BIT(15) ) +#define BIT_APCPU_C2_AUTO_SLP_EN ( BIT(14) ) +#define BIT_APCPU_C1_AUTO_SLP_EN ( BIT(13) ) +#define BIT_APCPU_C0_AUTO_SLP_EN ( BIT(12) ) +#define BIT_APCPU_C3_WFI_SHUTDOWN_EN ( BIT(11) ) +#define BIT_APCPU_C2_WFI_SHUTDOWN_EN ( BIT(10) ) +#define BIT_APCPU_C1_WFI_SHUTDOWN_EN ( BIT(9) ) +#define BIT_APCPU_C0_WFI_SHUTDOWN_EN ( BIT(8) ) +#define BIT_MCU_APCPU_C3_SLEEP ( BIT(7) ) +#define BIT_MCU_APCPU_C2_SLEEP ( BIT(6) ) +#define BIT_MCU_APCPU_C1_SLEEP ( BIT(5) ) +#define BIT_MCU_APCPU_C0_SLEEP ( BIT(4) ) +#define BIT_CA7_C3_AUTO_SLP_EN BIT_APCPU_C3_AUTO_SLP_EN +#define BIT_CA7_C2_AUTO_SLP_EN BIT_APCPU_C2_AUTO_SLP_EN +#define BIT_CA7_C1_AUTO_SLP_EN BIT_APCPU_C1_AUTO_SLP_EN +#define BIT_CA7_C0_AUTO_SLP_EN BIT_APCPU_C0_AUTO_SLP_EN +#define BIT_CA7_C3_WFI_SHUTDOWN_EN BIT_APCPU_C3_WFI_SHUTDOWN_EN +#define BIT_CA7_C2_WFI_SHUTDOWN_EN BIT_APCPU_C2_WFI_SHUTDOWN_EN +#define BIT_CA7_C1_WFI_SHUTDOWN_EN BIT_APCPU_C1_WFI_SHUTDOWN_EN +#define BIT_CA7_C0_WFI_SHUTDOWN_EN BIT_APCPU_C0_WFI_SHUTDOWN_EN +#define BIT_MCU_CA7_C3_SLEEP BIT_MCU_APCPU_C3_SLEEP +#define BIT_MCU_CA7_C2_SLEEP BIT_MCU_APCPU_C2_SLEEP +#define BIT_MCU_CA7_C1_SLEEP BIT_MCU_APCPU_C1_SLEEP +#define BIT_MCU_CA7_C0_SLEEP BIT_MCU_APCPU_C0_SLEEP +#define BIT_CA53_C3_AUTO_SLP_EN BIT_APCPU_C3_AUTO_SLP_EN +#define BIT_CA53_C2_AUTO_SLP_EN BIT_APCPU_C2_AUTO_SLP_EN +#define BIT_CA53_C1_AUTO_SLP_EN BIT_APCPU_C1_AUTO_SLP_EN +#define BIT_CA53_C0_AUTO_SLP_EN BIT_APCPU_C0_AUTO_SLP_EN +#define BIT_CA53_C3_WFI_SHUTDOWN_EN BIT_APCPU_C3_WFI_SHUTDOWN_EN +#define BIT_CA53_C2_WFI_SHUTDOWN_EN BIT_APCPU_C2_WFI_SHUTDOWN_EN +#define BIT_CA53_C1_WFI_SHUTDOWN_EN BIT_APCPU_C1_WFI_SHUTDOWN_EN +#define BIT_CA53_C0_WFI_SHUTDOWN_EN BIT_APCPU_C0_WFI_SHUTDOWN_EN +#define BIT_MCU_CA53_C3_SLEEP BIT_MCU_APCPU_C3_SLEEP +#define BIT_MCU_CA53_C2_SLEEP BIT_MCU_APCPU_C2_SLEEP +#define BIT_MCU_CA53_C1_SLEEP BIT_MCU_APCPU_C1_SLEEP +#define BIT_MCU_CA53_C0_SLEEP BIT_MCU_APCPU_C0_SLEEP +#define BIT_AP_PERI_FORCE_ON ( BIT(2) ) +#define BIT_AP_PERI_FORCE_SLP ( BIT(1) ) +#define BIT_AP_APB_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_AP_SYS_AUTO_SLEEP_CFG */ +#define BIT_GSP_CKG_FORCE_EN ( BIT(9) ) +#define BIT_GSP_AUTO_GATE_EN ( BIT(8) ) +#define BIT_APCPU_TRACE_FORCE_SLEEP ( BIT(7) ) +#define BIT_APCPU_TRACE_AUTO_GATE_EN ( BIT(6) ) +#define BIT_AP_AHB_AUTO_GATE_EN ( BIT(5) ) +#define BIT_AP_EMC_AUTO_GATE_EN ( BIT(4) ) +#define BIT_APCPU_EMC_AUTO_GATE_EN ( BIT(3) ) +#define BIT_APCPU_DBG_FORCE_SLEEP ( BIT(2) ) +#define BIT_APCPU_DBG_AUTO_GATE_EN ( BIT(1) ) +#define BIT_APCPU_CORE_AUTO_GATE_EN ( BIT(0) ) +#define BIT_CA7_EMC_AUTO_GATE_EN BIT_APCPU_EMC_AUTO_GATE_EN +#define BIT_CA7_DBG_FORCE_SLEEP BIT_APCPU_DBG_FORCE_SLEEP +#define BIT_CA7_DBG_AUTO_GATE_EN BIT_APCPU_DBG_AUTO_GATE_EN +#define BIT_CA7_CORE_AUTO_GATE_EN BIT_APCPU_CORE_AUTO_GATE_EN +#define BIT_CA53_EMC_AUTO_GATE_EN BIT_APCPU_EMC_AUTO_GATE_EN +#define BIT_CA53_DBG_FORCE_SLEEP BIT_APCPU_DBG_FORCE_SLEEP +#define BIT_CA53_DBG_AUTO_GATE_EN BIT_APCPU_DBG_AUTO_GATE_EN +#define BIT_CA53_CORE_AUTO_GATE_EN BIT_APCPU_CORE_AUTO_GATE_EN + +/* bits definitions for register REG_AP_AHB_HOLDING_PEN */ +#define BITS_HOLDING_PEN(_x_) ( (_x_) << 0 ) + +/* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C0 */ +#define BITS_JMP_ADDR_APCPU_C0(_x_) (_x_) +#define BITS_JMP_ADDR_CA7_C0(_x_) BITS_JMP_ADDR_APCPU_C0 + +/* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C1 */ +#define BITS_JMP_ADDR_APCPU_C1(_x_) (_x_) +#define BITS_JMP_ADDR_CA7_C1(_x_) BITS_JMP_ADDR_APCPU_C1(_x_) + +/* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C2 */ +#define BITS_JMP_ADDR_APCPU_C2(_x_) (_x_) +#define BITS_JMP_ADDR_CA7_C2(_x_) BITS_JMP_ADDR_APCPU_C2(_x_) + +/* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C3 */ +#define BITS_JMP_ADDR_APCPU_C3(_x_) (_x_) +#define BITS_JMP_ADDR_CA7_C3(_x_) BITS_JMP_ADDR_APCPU_C3(_x_) + +/* bits definitions for register REG_AP_AHB_CA7_C0_PU_LOCK */ +#define BIT_APCPU_C0_PU_LOCK ( BIT(0) ) +#define BIT_CA7_C0_PU_LOCK BIT_APCPU_C0_PU_LOCK +#define BIT_CA53_C0_PU_LOCK BIT_APCPU_C0_PU_LOCK + +/* bits definitions for register REG_AP_AHB_CA7_C1_PU_LOCK */ +#define BIT_APCPU_C1_PU_LOCK ( BIT(0) ) +#define BIT_CA7_C1_PU_LOCK BIT_APCPU_C1_PU_LOCK +#define BIT_CA53_C1_PU_LOCK BIT_APCPU_C1_PU_LOCK + +/* bits definitions for register REG_AP_AHB_CA7_C2_PU_LOCK */ +#define BIT_APCPU_C2_PU_LOCK ( BIT(0) ) +#define BIT_CA7_C2_PU_LOCK BIT_APCPU_C2_PU_LOCK +#define BIT_CA53_C2_PU_LOCK BIT_APCPU_C2_PU_LOCK + +/* bits definitions for register REG_AP_AHB_CA7_C3_PU_LOCK */ +#define BIT_APCPU_C3_PU_LOCK ( BIT(0) ) +#define BIT_CA7_C3_PU_LOCK BIT_APCPU_C3_PU_LOCK +#define BIT_CA53_C3_PU_LOCK BIT_APCPU_C3_PU_LOCK + +/* bits definitions for register REG_AP_AHB_APCPU_CKG_DIV_CFG */ +#define BITS_APCPU_LIT_ATB_CKG_DIV(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_APCPU_BIG_ATB_CKG_DIV(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_APCPU_LIT_DBG_CKG_DIV(_X_) ( (_X_) << 17 & (BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_APCPU_BIG_DBG_CKG_DIV(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)|BIT(16)) ) +#define BITS_APCPU_LIT_ACE_CKG_DIV(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_APCPU_BIG_ACE_CKG_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_APCPU_LIT_MCU_CKG_DIV(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BITS_APCPU_BIG_MCU_CKG_DIV(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AP_AHB_MCU_PAUSE */ +#define BIT_DMA_ACT_LIGHT_EN ( BIT(5) ) +#define BIT_MCU_SLEEP_FOLLOW_APCPU_EN ( BIT(4) ) +#define BIT_MCU_SLEEP_FOLLOW_CA7_EN BIT_MCU_SLEEP_FOLLOW_APCPU_EN +#define BIT_MCU_SLEEP_FOLLOW_CA53_EN BIT_MCU_SLEEP_FOLLOW_APCPU_EN +#define BIT_MCU_LIGHT_SLEEP_EN ( BIT(3) ) +#define BIT_MCU_DEEP_SLEEP_EN ( BIT(2) ) +#define BIT_MCU_SYS_SLEEP_EN ( BIT(1) ) +#define BIT_MCU_CORE_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_MISC_CKG_EN */ +#define BIT_ASHB_APCPU_DBG_VLD ( BIT(9) ) +#define BIT_ASHB_APCPU_DBG_EN ( BIT(8) ) +#define BIT_ASHB_CA7_DBG_VLD BIT_ASHB_APCPU_DBG_VLD +#define BIT_ASHB_CA7_DBG_EN BIT_ASHB_APCPU_DBG_EN +#define BIT_ASHB_CA53_DBG_VLD BIT_ASHB_APCPU_DBG_VLD +#define BIT_ASHB_CA53_DBG_EN BIT_ASHB_APCPU_DBG_EN +#define BIT_DISP_TMC_CKG_EN ( BIT(4) ) +#define BIT_DPHY_REF_CKG_EN ( BIT(1) ) +#define BIT_DPHY_CFG_CKG_EN ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_CA7_C0_AUTO_FORCE_SHUTDOWN_EN */ +#define BIT_APCPU_C0_AUTO_FORCE_SHUTDOWN_EN ( BIT(0) ) +#define BIT_CA7_C0_AUTO_FORCE_SHUTDOWN_EN BIT_APCPU_C0_AUTO_FORCE_SHUTDOWN_EN +#define BIT_CA53_C0_AUTO_FORCE_SHUTDOWN_EN BIT_APCPU_C0_AUTO_FORCE_SHUTDOWN_EN + +/* bits definitions for register REG_AP_AHB_CA7_C1_AUTO_FORCE_SHUTDOWN_EN */ +#define BIT_APCPU_C1_AUTO_FORCE_SHUTDOWN_EN ( BIT(0) ) +#define BIT_CA7_C1_AUTO_FORCE_SHUTDOWN_EN BIT_APCPU_C1_AUTO_FORCE_SHUTDOWN_EN +#define BIT_CA53_C1_AUTO_FORCE_SHUTDOWN_EN BIT_APCPU_C1_AUTO_FORCE_SHUTDOWN_EN + +/* bits definitions for register REG_AP_AHB_CA7_C2_AUTO_FORCE_SHUTDOWN_EN */ +#define BIT_APCPU_C2_AUTO_FORCE_SHUTDOWN_EN ( BIT(0) ) +#define BIT_CA7_C2_AUTO_FORCE_SHUTDOWN_EN BIT_APCPU_C2_AUTO_FORCE_SHUTDOWN_EN +#define BIT_CA53_C2_AUTO_FORCE_SHUTDOWN_EN BIT_APCPU_C2_AUTO_FORCE_SHUTDOWN_EN + +/* bits definitions for register REG_AP_AHB_CA7_C3_AUTO_FORCE_SHUTDOWN_EN */ +#define BIT_APCPU_C3_AUTO_FORCE_SHUTDOWN_EN ( BIT(0) ) +#define BIT_CA7_C3_AUTO_FORCE_SHUTDOWN_EN BIT_APCPU_C3_AUTO_FORCE_SHUTDOWN_EN +#define BIT_CA53_C3_AUTO_FORCE_SHUTDOWN_EN BIT_APCPU_C3_AUTO_FORCE_SHUTDOWN_EN + +/* bits definitions for register REG_AP_AHB_APCPU_CKG_SEL_CFG */ +#define BITS_APCPU_LIT_MCU_CKG_SEL(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_APCPU_BIG_MCU_CKG_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AP_AHB_APCPU_AUTO_GATE_EN */ +#define BIT_APCPU_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_APCPU_GIC_CKG_CFG */ +#define BIT_APCPU_GIC_CKG_EN ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_APCPU_GIC_CLK_CFG */ +#define BITS_APCPU_GIC_CLK_DIV(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_APCPU_GIC_CLK_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_AHB_APCPU_LIT_CKG_EN */ +#define BIT_APCPU_LIT_ATB_EN ( BIT(2) ) +#define BIT_APCPU_LIT_DBG_EN ( BIT(1) ) +#define BIT_APCPU_LIT_CORE_EN ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_APCPU_BIG_CKG_EN */ +#define BIT_APCPU_BIG_ATB_EN ( BIT(2) ) +#define BIT_APCPU_BIG_DBG_EN ( BIT(1) ) +#define BIT_APCPU_BIG_CORE_EN ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_APCPU_LIT_L2FLUSH */ +#define BIT_APCPU_LIT_L2FLUSHDONE ( BIT(1) ) +#define BIT_APCPU_LIT_L2FLUSHREQ ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_APCPU_BIG_L2FLUSH */ +#define BIT_APCPU_BIG_L2FLUSHDONE ( BIT(1) ) +#define BIT_APCPU_BIG_L2FLUSHREQ ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_APCPU_CCI_BASE_H25 */ +#define BITS_APCPU_CCI_BASE_H25(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) ) + +/* bits definitions for register REG_AP_AHB_APCPU_CCI_CTRL */ +#define BITS_APCPU_CCI_ARQOS_LIT(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_APCPU_CCI_AWQOS_LIT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_APCPU_CCI_ARQOS_BIG(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_APCPU_CCI_AWQOS_BIG(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_APCPU_CCI_BUFOVRD(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_APCPU_CCI_QOSOVRD(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register REG_AP_AHB_MISC_CFG */ +#define BIT_APCPU_DAP_SNOOP_DISABLE ( BIT(25) ) +#define BIT_APCPU_BIG_INT_DISABLE ( BIT(24) ) +#define BIT_APCPU_IRAM_REMAP ( BIT(23) ) +#define BIT_APCPU_L2RAM_LIGHT_SLEEP_EN ( BIT(22) ) +#define BIT_APCPU_AUTO_REG_SAVE_TRIG_SEL ( BIT(21) ) +#define BIT_APCPU_AUTO_REG_SAVE_EN ( BIT(20) ) +#define BITS_EMMC_SLOT_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_SDIO0_SLOT_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_BUSMON2_CHN_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_BUSMON1_CHN_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_BUSMON0_CHN_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_SDIO2_SLOT_SEL(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_SDIO1_SLOT_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_AHB_AP_MAIN_MTX_HPROT_CFG */ +#define BITS_HPROT_NFC(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_HPROT_EMMC(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_HPROT_SDIO2(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_HPROT_SDIO1(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_HPROT_SDIO0(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_HPROT_DMAW(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_HPROT_DMAR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AP_AHB_APCPU_STANDBY_STATUS */ +#define BIT_STANDBYWFIL2_BIG ( BIT(24) ) +#define BITS_STANDBYWFE_BIG(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_STANDBYWFI_BIG(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BIT_STANDBYWFIL2_LIT ( BIT(8) ) +#define BITS_STANDBYWFE_LIT(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_STANDBYWFI_LIT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AP_AHB_NANC_CLK_CFG */ +#define BITS_CLK_NANDC2X_DIV(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_CLK_NANDC2X_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_AHB_LVDS_CFG */ +#define BITS_LVDS_TXCLKDATA(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_LVDS_TXCOM(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_LVDS_TXSLEW(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_LVDS_TXSW(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_LVDS_TXRERSER(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_LVDS_PRE_EMP(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)) ) +#define BIT_LVDS_TXPD ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_LVDS_PLL_CFG0 */ +#define BIT_LVDS_PLL_LOCK_DET ( BIT(31) ) +#define BITS_LVDS_PLL_REFIN(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_LVDS_PLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BIT_LVDS_PLL_DIV_S ( BIT(18) ) +#define BITS_LVDS_PLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_LVDS_PLLN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AP_AHB_LVDS_PLL_CFG1 */ +#define BITS_LVDS_PLL_KINT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_LVDS_PLL_RSV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_LVDS_PLL_MOD_EN ( BIT(7) ) +#define BIT_LVDS_PLL_SDM_EN ( BIT(6) ) +#define BITS_LVDS_PLL_NINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_AP_AHB_AP_QOS_CFG */ +#define BITS_QOS_R_TMC(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_QOS_W_TMC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_QOS_R_DISPC(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_QOS_W_DISPC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AP_AHB_OTG_PHY_TUNE */ +#define BIT_OTG_TXPREEMPPULSETUNE ( BIT(20) ) +#define BITS_OTG_TXRESTUNE(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_OTG_TXHSXVTUNE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_OTG_TXVREFTUNE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_OTG_TXPREEMPAMPTUNE(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_OTG_TXRISETUNE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_OTG_TXFSLSTUNE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_OTG_SQRXTUNE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AP_AHB_OTG_PHY_TEST */ +#define BIT_OTG_ATERESET ( BIT(31) ) +#define BIT_OTG_VBUS_VALID_EXT_SEL ( BIT(26) ) +#define BIT_OTG_VBUS_VALID_EXT ( BIT(25) ) +#define BIT_OTG_OTGDISABLE ( BIT(24) ) +#define BIT_OTG_TESTBURNIN ( BIT(21) ) +#define BIT_OTG_LOOPBACKENB ( BIT(20) ) +#define BITS_OTG_TESTDATAOUT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_OTG_VATESTENB(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) ) +#define BIT_OTG_TESTCLK ( BIT(13) ) +#define BIT_OTG_TESTDATAOUTSEL ( BIT(12) ) +#define BITS_OTG_TESTADDR(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_OTG_TESTDATAIN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_AP_AHB_OTG_PHY_CTRL */ +#define BITS_OTG_SS_SCALEDOWNMODE(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BIT_OTG_TXBITSTUFFENH ( BIT(23) ) +#define BIT_OTG_TXBITSTUFFEN ( BIT(22) ) +#define BIT_OTG_DMPULLDOWN ( BIT(21) ) +#define BIT_OTG_DPPULLDOWN ( BIT(20) ) +#define BIT_OTG_DMPULLUP ( BIT(9) ) +#define BIT_OTG_COMMONONN ( BIT(8) ) +#define BITS_OTG_REFCLKSEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_OTG_FSEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AP_AHB_HSIC_PHY_TUNE */ +#define BITS_HSIC_REFCLK_DIV(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) ) +#define BIT_HSIC_TXPREEMPPULSETUNE ( BIT(20) ) +#define BITS_HSIC_TXRESTUNE(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_HSIC_TXHSXVTUNE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_HSIC_TXVREFTUNE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_HSIC_TXPREEMPAMPTUNE(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_HSIC_TXRISETUNE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_HSIC_TXFSLSTUNE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_HSIC_SQRXTUNE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AP_AHB_HSIC_PHY_TEST */ +#define BIT_HSIC_ATERESET ( BIT(31) ) +#define BIT_HSIC_VBUS_VALID_EXT_SEL ( BIT(26) ) +#define BIT_HSIC_VBUS_VALID_EXT ( BIT(25) ) +#define BIT_HSIC_OTGDISABLE ( BIT(24) ) +#define BIT_HSIC_TESTBURNIN ( BIT(21) ) +#define BIT_HSIC_LOOPBACKENB ( BIT(20) ) +#define BITS_HSIC_TESTDATAOUT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_HSIC_VATESTENB(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) ) +#define BIT_HSIC_TESTCLK ( BIT(13) ) +#define BIT_HSIC_TESTDATAOUTSEL ( BIT(12) ) +#define BITS_HSIC_TESTADDR(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_HSIC_TESTDATAIN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_AP_AHB_HSIC_PHY_CTRL */ +#define BITS_HSIC_SS_SCALEDOWNMODE(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BIT_HSIC_TXBITSTUFFENH ( BIT(23) ) +#define BIT_HSIC_TXBITSTUFFEN ( BIT(22) ) +#define BIT_HSIC_DMPULLDOWN ( BIT(21) ) +#define BIT_HSIC_DPPULLDOWN ( BIT(20) ) +#define BIT_HSIC_IF_MODE ( BIT(16) ) +#define BIT_IF_SELECT_HSIC ( BIT(13) ) +#define BIT_HSIC_DBNCE_FLTR_BYPASS ( BIT(12) ) +#define BIT_HSIC_DMPULLUP ( BIT(9) ) +#define BIT_HSIC_COMMONONN ( BIT(8) ) +#define BITS_HSIC_REFCLKSEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_HSIC_FSEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AP_AHB_ZIP_MTX_QOS_CFG */ +#define BITS_ZIPMTX_S0_ARQOS(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_ZIPMTX_S0_AWQOS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_ZIPDEC_ARQOS(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_ZIPDEC_AWQOS(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_ZIPENC_ARQOS(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_ZIPENC_AWQOS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AP_AHB_APCPU_QCHN_CTL_BIG */ +#define BITS_APCPU_Q_NEG_THD_BIG(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_APCPU_Q_WAIT_GAP_BIG(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_APCPU_Q_PGEN_DUR_BIG(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_APCPU_Q_WAIT_REQ_BIG(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_APCPU_Q_RETN_BYP_BIG ( BIT(2) ) +#define BIT_APCPU_Q_RETN_SEL_BIG ( BIT(1) ) +#define BIT_APCPU_Q_LP_EN_BIG ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_APCPU_QCHN_STA_BIG */ +#define BITS_APCPU_Q_STATUS_BIG(_X_) (_X_) + +/* bits definitions for register REG_AP_AHB_APCPU_QCHN_CTL_LIT */ +#define BITS_APCPU_Q_NEG_THD_LIT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_APCPU_Q_WAIT_GAP_LIT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_APCPU_Q_PGEN_DUR_LIT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_APCPU_Q_WAIT_REQ_LIT(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_APCPU_Q_RETN_BYP_LIT ( BIT(2) ) +#define BIT_APCPU_Q_RETN_SEL_LIT ( BIT(1) ) +#define BIT_APCPU_Q_LP_EN_LIT ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_APCPU_QCHN_STA_LIT */ +#define BITS_APCPU_Q_STATUS_LIT(_X_) (_X_) + +/* bits definitions for register REG_AP_AHB_GSP_SEL */ +#define BIT_GSP_VER_SEL ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_RES_REG */ +#define BITS_RES_REG(_X_) (_X_) + +/* bits definitions for register REG_AP_AHB_CHIP_ID */ +#define BITS_CHIP_ID(_X_) (_X_) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_ap_apb.h b/include/soc/sprd/chip_x35lt8/__regs_ap_apb.h new file mode 100644 index 00000000..facd6da4 --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_ap_apb.h @@ -0,0 +1,94 @@ +/* the head file modifier: g 2015-03-19 15:40:29*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_AP_APB_HEADFILE_H__ +#define __H_REGS_AP_APB_HEADFILE_H__ __FILE__ + +#define REGS_AP_APB + +/* registers definitions for AP_APB */ +#define REG_AP_APB_APB_EB SCI_ADDR(REGS_AP_APB_BASE, 0x0000)/*AHB_EB*/ +#define REG_AP_APB_APB_RST SCI_ADDR(REGS_AP_APB_BASE, 0x0004)/*AHB_RST*/ +#define REG_AP_APB_APB_MISC_CTRL SCI_ADDR(REGS_AP_APB_BASE, 0x0008)/*APB_MISC_CTRL*/ + + + +/* bits definitions for register REG_AP_APB_APB_EB */ +#define BIT_INTC3_EB ( BIT(22) ) +#define BIT_INTC2_EB ( BIT(21) ) +#define BIT_INTC1_EB ( BIT(20) ) +#define BIT_INTC0_EB ( BIT(19) ) +#define BIT_CKG_EB ( BIT(18) ) +#define BIT_AP_CKG_EB ( BIT_CKG_EB ) +#define BIT_UART4_EB ( BIT(17) ) +#define BIT_UART3_EB ( BIT(16) ) +#define BIT_UART2_EB ( BIT(15) ) +#define BIT_UART1_EB ( BIT(14) ) +#define BIT_UART0_EB ( BIT(13) ) +#define BIT_I2C4_EB ( BIT(12) ) +#define BIT_I2C3_EB ( BIT(11) ) +#define BIT_I2C2_EB ( BIT(10) ) +#define BIT_I2C1_EB ( BIT(9) ) +#define BIT_I2C0_EB ( BIT(8) ) +#define BIT_SPI2_EB ( BIT(7) ) +#define BIT_SPI1_EB ( BIT(6) ) +#define BIT_SPI0_EB ( BIT(5) ) +#define BIT_IIS3_EB ( BIT(4) ) +#define BIT_IIS2_EB ( BIT(3) ) +#define BIT_IIS1_EB ( BIT(2) ) +#define BIT_IIS0_EB ( BIT(1) ) +#define BIT_SIM0_EB ( BIT(0) ) + +/* bits definitions for register REG_AP_APB_APB_RST */ +#define BIT_INTC3_SOFT_RST ( BIT(22) ) +#define BIT_INTC2_SOFT_RST ( BIT(21) ) +#define BIT_INTC1_SOFT_RST ( BIT(20) ) +#define BIT_INTC0_SOFT_RST ( BIT(19) ) +#define BIT_CKG_SOFT_RST ( BIT(18) ) +#define BIT_AP_CKG_SOFT_RST BIT_CKG_SOFT_RST +#define BIT_UART4_SOFT_RST ( BIT(17) ) +#define BIT_UART3_SOFT_RST ( BIT(16) ) +#define BIT_UART2_SOFT_RST ( BIT(15) ) +#define BIT_UART1_SOFT_RST ( BIT(14) ) +#define BIT_UART0_SOFT_RST ( BIT(13) ) +#define BIT_I2C4_SOFT_RST ( BIT(12) ) +#define BIT_I2C3_SOFT_RST ( BIT(11) ) +#define BIT_I2C2_SOFT_RST ( BIT(10) ) +#define BIT_I2C1_SOFT_RST ( BIT(9) ) +#define BIT_I2C0_SOFT_RST ( BIT(8) ) +#define BIT_SPI2_SOFT_RST ( BIT(7) ) +#define BIT_SPI1_SOFT_RST ( BIT(6) ) +#define BIT_SPI0_SOFT_RST ( BIT(5) ) +#define BIT_IIS3_SOFT_RST ( BIT(4) ) +#define BIT_IIS2_SOFT_RST ( BIT(3) ) +#define BIT_IIS1_SOFT_RST ( BIT(2) ) +#define BIT_IIS0_SOFT_RST ( BIT(1) ) +#define BIT_SIM0_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_AP_APB_APB_MISC_CTRL */ +#define BIT_SIM_CLK_POLARITY ( BIT(1) ) +#define BIT_FMARK_POLARITY_INV ( BIT(0) ) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_ap_clk.h b/include/soc/sprd/chip_x35lt8/__regs_ap_clk.h new file mode 100644 index 00000000..f7d1073b --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_ap_clk.h @@ -0,0 +1,227 @@ +/* the head file modifier: g 2015-03-19 15:40:59*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_AP_CLK_CORE_HEADFILE_H__ +#define __H_REGS_AP_CLK_CORE_HEADFILE_H__ __FILE__ + +#define REGS_AP_CLK_CORE + +/* registers definitions for AP_CLK_CORE */ +#define REG_AP_CLK_CORE_clk_ap_ahb_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x20)/*clk_ap_ahb_cfg*/ +#define REG_AP_CLK_CORE_clk_ap_apb_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x24)/*clk_ap_apb_cfg*/ +#define REG_AP_CLK_CORE_clk_gsp0_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x28)/*clk_gsp_cfg*/ +#define REG_AP_CLK_CORE_clk_dispc0_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x2c)/*clk_dispc0_cfg*/ +#define REG_AP_CLK_CORE_clk_dispc0_dbi_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x30)/*clk_dispc0_dbi_cfg*/ +#define REG_AP_CLK_CORE_clk_dispc0_dpi_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x34)/*clk_dispc0_dpi_cfg*/ +#define REG_AP_CLK_CORE_clk_nandc_ecc_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x38)/*clk_nandc_ecc_cfg*/ +#define REG_AP_CLK_CORE_clk_sdio0_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x3c)/*clk_sdio0_cfg*/ +#define REG_AP_CLK_CORE_clk_sdio1_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x40)/*clk_sdio1_cfg*/ +#define REG_AP_CLK_CORE_clk_sdio2_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x44)/*clk_sdio2_cfg*/ +#define REG_AP_CLK_CORE_clk_emmc_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x48)/*clk_emmc_cfg*/ +#define REG_AP_CLK_CORE_clk_otg_ref_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x4c)/*clk_otg_ref_cfg*/ +#define REG_AP_CLK_CORE_clk_hsic_ref_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x50)/*clk_hsic_ref_cfg*/ +#define REG_AP_CLK_CORE_clk_uart0_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x54)/*clk_uart0_cfg*/ +#define REG_AP_CLK_CORE_clk_uart1_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x58)/*clk_uart1_cfg*/ +#define REG_AP_CLK_CORE_clk_uart2_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x5c)/*clk_uart2_cfg*/ +#define REG_AP_CLK_CORE_clk_uart3_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x60)/*clk_uart3_cfg*/ +#define REG_AP_CLK_CORE_clk_uart4_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x64)/*clk_uart4_cfg*/ +#define REG_AP_CLK_CORE_clk_i2c0_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x68)/*clk_i2c0_cfg*/ +#define REG_AP_CLK_CORE_clk_i2c1_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x6c)/*clk_i2c1_cfg*/ +#define REG_AP_CLK_CORE_clk_i2c2_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x70)/*clk_i2c2_cfg*/ +#define REG_AP_CLK_CORE_clk_i2c3_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x74)/*clk_i2c3_cfg*/ +#define REG_AP_CLK_CORE_clk_i2c4_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x78)/*clk_i2c4_cfg*/ +#define REG_AP_CLK_CORE_clk_spi0_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x7c)/*clk_spi0_cfg*/ +#define REG_AP_CLK_CORE_clk_spi1_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x80)/*clk_spi1_cfg*/ +#define REG_AP_CLK_CORE_clk_spi2_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x84)/*clk_spi2_cfg*/ +#define REG_AP_CLK_CORE_clk_iis0_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x88)/*clk_iis0_cfg*/ +#define REG_AP_CLK_CORE_clk_iis1_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x8c)/*clk_iis1_cfg*/ +#define REG_AP_CLK_CORE_clk_iis2_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x90)/*clk_iis2_cfg*/ +#define REG_AP_CLK_CORE_clk_iis3_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x94)/*clk_iis3_cfg*/ +#define REG_AP_CLK_CORE_clk_zipenc_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x98)/*clk_zipenc_cfg*/ +#define REG_AP_CLK_CORE_clk_zipdec_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x9c)/*clk_zipdec_cfg*/ +#define REG_AP_CLK_CORE_clk_gsp1_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0xa0)/*clk_gsp1_cfg*/ +#define REG_AP_CLK_AP_AHB_CFG REG_AP_CLK_CORE_clk_ap_ahb_cfg +#define REG_AP_CLK_AP_APB_CFG REG_AP_CLK_CORE_clk_ap_apb_cfg +#define REG_AP_CLK_GSP_CFG REG_AP_CLK_CORE_clk_gsp0_cfg +#define REG_AP_CLK_DISPC0_CFG REG_AP_CLK_CORE_clk_dispc0_cfg +#define REG_AP_CLK_DISPC0_DBI_CFG REG_AP_CLK_CORE_clk_dispc0_dbi_cfg +#define REG_AP_CLK_DISPC0_DPI_CFG REG_AP_CLK_CORE_clk_dispc0_dpi_cfg +#define REG_AP_CLK_NANDC_ECC_CFG REG_AP_CLK_CORE_clk_nandc_ecc_cfg +#define REG_AP_CLK_SDIO0_CFG REG_AP_CLK_CORE_clk_sdio0_cfg +#define REG_AP_CLK_SDIO1_CFG REG_AP_CLK_CORE_clk_sdio1_cfg +#define REG_AP_CLK_SDIO2_CFG REG_AP_CLK_CORE_clk_sdio2_cfg +#define REG_AP_CLK_EMMC_CFG REG_AP_CLK_CORE_clk_emmc_cfg +#define REG_AP_CLK_OTG_REF_CFG REG_AP_CLK_CORE_clk_otg_ref_cfg +#define REG_AP_CLK_HSIC_REF_CFG REG_AP_CLK_CORE_clk_hsic_ref_cfg +#define REG_AP_CLK_UART0_CFG REG_AP_CLK_CORE_clk_uart0_cfg +#define REG_AP_CLK_UART1_CFG REG_AP_CLK_CORE_clk_uart1_cfg +#define REG_AP_CLK_UART2_CFG REG_AP_CLK_CORE_clk_uart2_cfg +#define REG_AP_CLK_UART3_CFG REG_AP_CLK_CORE_clk_uart3_cfg +#define REG_AP_CLK_UART4_CFG REG_AP_CLK_CORE_clk_uart4_cfg +#define REG_AP_CLK_I2C0_CFG REG_AP_CLK_CORE_clk_i2c0_cfg +#define REG_AP_CLK_I2C1_CFG REG_AP_CLK_CORE_clk_i2c1_cfg +#define REG_AP_CLK_I2C2_CFG REG_AP_CLK_CORE_clk_i2c2_cfg +#define REG_AP_CLK_I2C3_CFG REG_AP_CLK_CORE_clk_i2c3_cfg +#define REG_AP_CLK_I2C4_CFG REG_AP_CLK_CORE_clk_i2c4_cfg +#define REG_AP_CLK_SPI0_CFG REG_AP_CLK_CORE_clk_spi0_cfg +#define REG_AP_CLK_SPI1_CFG REG_AP_CLK_CORE_clk_spi1_cfg +#define REG_AP_CLK_SPI2_CFG REG_AP_CLK_CORE_clk_spi2_cfg +#define REG_AP_CLK_IIS0_CFG REG_AP_CLK_CORE_clk_iis0_cfg +#define REG_AP_CLK_IIS1_CFG REG_AP_CLK_CORE_clk_iis1_cfg +#define REG_AP_CLK_IIS2_CFG REG_AP_CLK_CORE_clk_iis2_cfg +#define REG_AP_CLK_IIS3_CFG REG_AP_CLK_CORE_clk_iis3_cfg +#define REG_AP_CLK_ZIPENC_CFG REG_AP_CLK_CORE_clk_zipenc_cfg +#define REG_AP_CLK_ZIPDEC_CFG REG_AP_CLK_CORE_clk_zipdec_cfg + + +/* bits definitions for register REG_AP_CLK_CORE_clk_ap_ahb_cfg */ +#define BITS_CLK_AP_AHB_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_ap_apb_cfg */ +#define BITS_CLK_AP_APB_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_gsp0_cfg */ +#define BITS_CLK_GSP0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_dispc0_cfg */ +#define BITS_CLK_DISPC0_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_DISPC0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_dispc0_dbi_cfg */ +#define BITS_CLK_DISPC0_DBI_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_DISPC0_DBI_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_dispc0_dpi_cfg */ +#define BIT_CLK_DISPC0_DPI_PAD_SEL ( BIT(16) ) +#define BITS_CLK_DISPC0_DPI_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_CLK_DISPC0_DPI_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_nandc_ecc_cfg */ +#define BIT_CLK_NANDC_ECC_SEL ( BIT(0) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_sdio0_cfg */ +#define BITS_CLK_SDIO0_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_SDIO0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_sdio1_cfg */ +#define BITS_CLK_SDIO1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_sdio2_cfg */ +#define BITS_CLK_SDIO2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_emmc_cfg */ +#define BITS_CLK_EMMC_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_otg_ref_cfg */ +#define BIT_CLK_OTG_REF_SEL ( BIT(0) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_hsic_ref_cfg */ +#define BIT_CLK_HSIC_REF_SEL ( BIT(0) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_uart0_cfg */ +#define BITS_CLK_UART0_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_UART0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_uart1_cfg */ +#define BITS_CLK_UART1_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_UART1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_uart2_cfg */ +#define BITS_CLK_UART2_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_UART2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_uart3_cfg */ +#define BITS_CLK_UART3_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_UART3_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_uart4_cfg */ +#define BITS_CLK_UART4_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_UART4_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_i2c0_cfg */ +#define BITS_CLK_I2C0_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_I2C0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_i2c1_cfg */ +#define BITS_CLK_I2C1_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_I2C1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_i2c2_cfg */ +#define BITS_CLK_I2C2_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_I2C2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_i2c3_cfg */ +#define BITS_CLK_I2C3_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_I2C3_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_i2c4_cfg */ +#define BITS_CLK_I2C4_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_I2C4_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_spi0_cfg */ +#define BIT_CLK_SPI0_PAD_SEL ( BIT(16) ) +#define BITS_CLK_SPI0_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_SPI0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_spi1_cfg */ +#define BIT_CLK_SPI1_PAD_SEL ( BIT(16) ) +#define BITS_CLK_SPI1_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_SPI1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_spi2_cfg */ +#define BIT_CLK_SPI2_PAD_SEL ( BIT(16) ) +#define BITS_CLK_SPI2_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_SPI2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_iis0_cfg */ +#define BIT_CLK_IIS0_PAD_SEL ( BIT(16) ) +#define BITS_CLK_IIS0_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_IIS0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_iis1_cfg */ +#define BIT_CLK_IIS1_PAD_SEL ( BIT(16) ) +#define BITS_CLK_IIS1_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_IIS1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_iis2_cfg */ +#define BIT_CLK_IIS2_PAD_SEL ( BIT(16) ) +#define BITS_CLK_IIS2_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_IIS2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_iis3_cfg */ +#define BIT_CLK_IIS3_PAD_SEL ( BIT(16) ) +#define BITS_CLK_IIS3_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_IIS3_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_zipenc_cfg */ +#define BITS_CLK_ZIPENC_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_zipdec_cfg */ +#define BITS_CLK_ZIPDEC_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_gsp1_cfg */ +#define BITS_CLK_GSP1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_arm7_ahb_rf.h b/include/soc/sprd/chip_x35lt8/__regs_arm7_ahb_rf.h new file mode 100644 index 00000000..5a0eb47e --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_arm7_ahb_rf.h @@ -0,0 +1,161 @@ +/* the head file modifier: g 2015-03-19 15:41:25*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_ARM7_AHB_RF_HEADFILE_H__ +#define __H_REGS_ARM7_AHB_RF_HEADFILE_H__ __FILE__ + +#define REGS_ARM7_AHB_RF + +/* registers definitions for ARM7_AHB_RF */ +#define REG_ARM7_AHB_RF_ARM7_EB SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0000)/*ARM7_EB*/ +#define REG_ARM7_AHB_RF_ARM7_SOFT_RST SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0004)/*ARM7_SOFT_RST*/ +#define REG_ARM7_AHB_RF_AHB_PAUSE SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0008)/*AHB_PAUSE*/ +#define REG_ARM7_AHB_RF_ARM7_SLP_CTL SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x000C)/*ARM7_SLP_CTL*/ +#define REG_ARM7_AHB_RF_CLK_EMC4X_CFG SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0010)/*CLK_EMC4X_CFG*/ +#define REG_ARM7_AHB_RF_APCPU_LIT_RVBADDR0 SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0020)/*APCPU_LIT_RVBADDR0*/ +#define REG_ARM7_AHB_RF_APCPU_LIT_RVBADDR1 SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0024)/*APCPU_LIT_RVBADDR1*/ +#define REG_ARM7_AHB_RF_APCPU_LIT_RVBADDR2 SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0028)/*APCPU_LIT_RVBADDR2*/ +#define REG_ARM7_AHB_RF_APCPU_LIT_RVBADDR3 SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x002C)/*APCPU_LIT_RVBADDR3*/ +#define REG_ARM7_AHB_RF_APCPU_LIT_PROT_CTL SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0030)/*APCPU_LIT_PROT_CTL*/ +#define REG_ARM7_AHB_RF_APCPU_LIT_COMM_CTL SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0034)/*APCPU_LIT_COMM_CTL*/ +#define REG_ARM7_AHB_RF_ARM7_RES_REG SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0044)/*ARM7_RES_REG*/ +#define REG_ARM7_AHB_RF_APCPU_BIG_RVBADDR0 SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0050)/*APCPU_BIG_RVBADDR0*/ +#define REG_ARM7_AHB_RF_APCPU_BIG_RVBADDR1 SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0054)/*APCPU_BIG_RVBADDR1*/ +#define REG_ARM7_AHB_RF_APCPU_BIG_RVBADDR2 SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0058)/*APCPU_BIG_RVBADDR2*/ +#define REG_ARM7_AHB_RF_APCPU_BIG_RVBADDR3 SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x005C)/*APCPU_BIG_RVBADDR3*/ +#define REG_ARM7_AHB_RF_APCPU_BIG_PROT_CTL SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0060)/*APCPU_BIG_PROT_CTL*/ +#define REG_ARM7_AHB_RF_APCPU_BIG_COMM_CTL SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0064)/*APCPU_BIG_COMM_CTL*/ +#define REG_ARM7_AHB_RF_CSSYS_PROT_CTL SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0070)/*CSSYS_PROT_CTL*/ +#define REG_ARM7_AHB_RF_CCI_PROT_CTL SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0074)/*CCI_PROT_CTL*/ + + + +/* bits definitions for register REG_ARM7_AHB_RF_ARM7_EB */ +#define BIT_ARM7_GPIO_EB ( BIT(10) ) +#define BIT_ARM7_UART_EB ( BIT(9) ) +#define BIT_ARM7_TMR_EB ( BIT(8) ) +#define BIT_ARM7_SYST_EB ( BIT(7) ) +#define BIT_ARM7_WDG_EB ( BIT(6) ) +#define BIT_ARM7_EIC_EB ( BIT(5) ) +#define BIT_ARM7_INTC_EB ( BIT(4) ) +#define BIT_ARM7_EFUSE_EB ( BIT(3) ) +#define BIT_ARM7_IMC_EB ( BIT(2) ) +#define BIT_ARM7_TIC_EB ( BIT(1) ) +#define BIT_ARM7_DMA_EB ( BIT(0) ) + +/* bits definitions for register REG_ARM7_AHB_RF_ARM7_SOFT_RST */ +#define BIT_ARM7_GPIO_SOFT_RST ( BIT(10) ) +#define BIT_ARM7_UART_SOFT_RST ( BIT(9) ) +#define BIT_ARM7_TMR_SOFT_RST ( BIT(8) ) +#define BIT_ARM7_SYST_SOFT_RST ( BIT(7) ) +#define BIT_ARM7_WDG_SOFT_RST ( BIT(6) ) +#define BIT_ARM7_EIC_SOFT_RST ( BIT(5) ) +#define BIT_ARM7_INTC_SOFT_RST ( BIT(4) ) +#define BIT_ARM7_EFUSE_SOFT_RST ( BIT(3) ) +#define BIT_ARM7_IMC_SOFT_RST ( BIT(2) ) +#define BIT_ARM7_TIC_SOFT_RST ( BIT(1) ) +#define BIT_ARM7_ARCH_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_ARM7_AHB_RF_AHB_PAUSE */ +#define BIT_ARM7_DEEP_SLEEP_EN ( BIT(2) ) +#define BIT_ARM7_SYS_SLEEP_EN ( BIT(1) ) +#define BIT_ARM7_CORE_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_ARM7_AHB_RF_ARM7_SLP_CTL */ +#define BIT_ARM7_SYS_AUTO_GATE_EN ( BIT(2) ) +#define BIT_ARM7_AHB_AUTO_GATE_EN ( BIT(1) ) +#define BIT_ARM7_CORE_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_ARM7_AHB_RF_CLK_EMC4X_CFG */ +#define BITS_CLK_EMC4X_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_EMC4X_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_ARM7_AHB_RF_APCPU_LIT_RVBADDR0 */ +#define BITS_APCPU_LIT_RVBADDR0(_X_) (_X_) + +/* bits definitions for register REG_ARM7_AHB_RF_APCPU_LIT_RVBADDR1 */ +#define BITS_APCPU_LIT_RVBADDR1(_X_) (_X_) + +/* bits definitions for register REG_ARM7_AHB_RF_APCPU_LIT_RVBADDR2 */ +#define BITS_APCPU_LIT_RVBADDR2(_X_) (_X_) + +/* bits definitions for register REG_ARM7_AHB_RF_APCPU_LIT_RVBADDR3 */ +#define BITS_APCPU_LIT_RVBADDR3(_X_) (_X_) + +/* bits definitions for register REG_ARM7_AHB_RF_APCPU_LIT_PROT_CTL */ +#define BITS_APCPU_LIT_SPNIDEN(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_APCPU_LIT_SPIDEN(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_APCPU_LIT_NIDEN(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_APCPU_LIT_DBGEN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_ARM7_AHB_RF_APCPU_LIT_COMM_CTL */ +#define BIT_APCPU_LIT_DBGL1RSTDISABLE ( BIT(17) ) +#define BIT_APCPU_LIT_L2RSTDISABLE ( BIT(16) ) +#define BITS_APCPU_LIT_CFGTE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_APCPU_LIT_AA64NAA32(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_ARM7_AHB_RF_ARM7_RES_REG */ +#define BITS_ARM7_RES_REG_H(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ARM7_RES_REG_L(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) + +/* bits definitions for register REG_ARM7_AHB_RF_APCPU_BIG_RVBADDR0 */ +#define BITS_APCPU_BIG_RVBADDR0(_X_) (_X_) + +/* bits definitions for register REG_ARM7_AHB_RF_APCPU_BIG_RVBADDR1 */ +#define BITS_APCPU_BIG_RVBADDR1(_X_) (_X_) + +/* bits definitions for register REG_ARM7_AHB_RF_APCPU_BIG_RVBADDR2 */ +#define BITS_APCPU_BIG_RVBADDR2(_X_) (_X_) + +/* bits definitions for register REG_ARM7_AHB_RF_APCPU_BIG_RVBADDR3 */ +#define BITS_APCPU_BIG_RVBADDR3(_X_) (_X_) + +/* bits definitions for register REG_ARM7_AHB_RF_APCPU_BIG_PROT_CTL */ +#define BITS_APCPU_BIG_SPNIDEN(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_APCPU_BIG_SPIDEN(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_APCPU_BIG_NIDEN(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_APCPU_BIG_DBGEN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_ARM7_AHB_RF_APCPU_BIG_COMM_CTL */ +#define BIT_APCPU_BIG_DBGL1RSTDISABLE ( BIT(17) ) +#define BIT_APCPU_BIG_L2RSTDISABLE ( BIT(16) ) +#define BITS_APCPU_BIG_CFGTE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_APCPU_BIG_AA64NAA32(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_ARM7_AHB_RF_CSSYS_PROT_CTL */ +#define BIT_CSSYS_DAP_SPIDEN ( BIT(10) ) +#define BIT_CSSYS_DAP_DBGEN ( BIT(8) ) +#define BIT_CSSYS_DAP_DEVICEEN ( BIT(7) ) +#define BIT_CSSYS_STM_NSGUAREN ( BIT(5) ) +#define BIT_CSSYS_SPNIDEN ( BIT(3) ) +#define BIT_CSSYS_SPIDEN ( BIT(2) ) +#define BIT_CSSYS_NIDEN ( BIT(1) ) +#define BIT_CSSYS_DBGEN ( BIT(0) ) + +/* bits definitions for register REG_ARM7_AHB_RF_CCI_PROT_CTL */ +#define BIT_CCI_SPNIDEN ( BIT(3) ) +#define BIT_CCI_NIDEN ( BIT(1) ) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_avs_apb_rf.h b/include/soc/sprd/chip_x35lt8/__regs_avs_apb_rf.h new file mode 100644 index 00000000..e47f8055 --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_avs_apb_rf.h @@ -0,0 +1,104 @@ +/* the head file modifier: g 2015-03-19 15:41:46*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_AVS_APB_RF_HEADFILE_H__ +#define __H_REGS_AVS_APB_RF_HEADFILE_H__ __FILE__ + +#define REGS_AVS_APB_RF + +/* registers definitions for AVS_APB_RF */ +#define REG_AVS_APB_RF_AVS_TUNE_LMT_CFG SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0000)/*AVS_TUNE_LMT_CFG*/ +#define REG_AVS_APB_RF_AVS_TUNE_STATUS SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0004)/*AVS_TUNE_STATUS*/ +#define REG_AVS_APB_RF_AVS_CFG SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0008)/*AVS_CFG*/ +#define REG_AVS_APB_RF_AVS_TUNE_STEP_CFG SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x000C)/*AVS_TUNE_STEP_CFG*/ +#define REG_AVS_APB_RF_AVS_WAIT_CFG SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0010)/*AVS_WAIT_CFG*/ +#define REG_AVS_APB_RF_AVS_INT_CFG SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0014)/*AVS_INT_CFG*/ +#define REG_AVS_APB_RF_AVS_START_SINGLE_ACT SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0018)/*AVS_START_SINGLE_ACT*/ +#define REG_AVS_APB_RF_AVS_START_REPEAT_ACT SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x001C)/*AVS_START_REPEAT_ACT*/ +#define REG_AVS_APB_RF_AVS_HPM_EN SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0020)/*AVS_HPM_EN*/ +#define REG_AVS_APB_RF_AVS_HPM_RPT_ANLS SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0024)/*AVS_HPM_RPT_ANLS*/ +#define REG_AVS_APB_RF_AVS_HPM_RPT_VLD_STATUS_0 SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0028)/*AVS_HPM_RPT_VLD_STATUS_0*/ +#define REG_AVS_APB_RF_AVS_HPM_RPT_VLD_STATUS_1 SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x002C)/*AVS_HPM_RPT_VLD_STATUS_1*/ +#define REG_AVS_APB_RF_AVS_FSM_STS SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0030)/*AVS_FSM_STS*/ +#define REG_AVS_APB_RF_FSM_STS REG_AVS_APB_RF_AVS_FSM_STS + + +/* bits definitions for register REG_AVS_APB_RF_AVS_TUNE_LMT_CFG */ +#define BITS_VOLT_TUNE_VAL_MAX(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_VOLT_TUNE_VAL_MIN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_TUNE_STATUS */ +#define BITS_VOLT_TUNE_VAL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_VOLT_OBS_VAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_CFG */ +#define BIT_HPM1_RPT_CHKSUM_ERR_EN ( BIT(17) ) +#define BIT_HPM0_RPT_CHKSUM_ERR_EN ( BIT(16) ) +#define BIT_PAUSE_OCCUR_ERR_EN ( BIT(8) ) +#define BIT_VOLT_TUNE_FORBID_EN ( BIT(4) ) +#define BIT_VOLT_OBS_FORBID_EN ( BIT(0) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_TUNE_STEP_CFG */ +#define BITS_VOLT_TUNE_DOWN_STEP(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) ) +#define BITS_VOLT_TUNE_UP_STEP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_WAIT_CFG */ +#define BITS_RND_INTVAL_WAIT_NUM(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_VOLT_STB_WAIT_NUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_INT_CFG */ +#define BIT_AVS_TUNE_DONE_INT_MASK_STATUS ( BIT(13) ) +#define BIT_AVS_TUNE_ERR_INT_MASK_STATUS ( BIT(12) ) +#define BIT_AVS_TUNE_DONE_INT_RAW_STATUS ( BIT(9) ) +#define BIT_AVS_TUNE_ERR_INT_RAW_STATUS ( BIT(8) ) +#define BIT_AVS_TUNE_DONE_INT_CLR ( BIT(5) ) +#define BIT_AVS_TUNE_ERR_INT_CLR ( BIT(4) ) +#define BIT_AVS_TUNE_DONE_INT_EN ( BIT(1) ) +#define BIT_AVS_TUNE_ERR_INT_EN ( BIT(0) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_START_SINGLE_ACT */ +#define BIT_AVS_START_SINGLE_ACT ( BIT(0) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_START_REPEAT_ACT */ +#define BIT_AVS_START_REPEAT_ACT ( BIT(0) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_HPM_EN */ +#define BIT_HPM1_EN ( BIT(1) ) +#define BIT_HPM0_EN ( BIT(0) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_HPM_RPT_ANLS */ +#define BITS_HPM_RPT_TUNE_DWN_MARK(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_HPM_RPT_TUNE_UP_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_HPM_RPT_VLD_STATUS_0 */ +#define BITS_HPM1_RPT_VLD(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_HPM0_RPT_VLD(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_HPM_RPT_VLD_STATUS_1 */ + +/* bits definitions for register REG_AVS_APB_RF_AVS_FSM_STS */ +#define BITS_AVS_FSM_STS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_codec_ahb.h b/include/soc/sprd/chip_x35lt8/__regs_codec_ahb.h new file mode 100644 index 00000000..28c975ee --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_codec_ahb.h @@ -0,0 +1,58 @@ +/* the head file modifier: g 2015-03-19 15:44:20*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_CODEC_AHB_HEADFILE_H__ +#define __H_REGS_CODEC_AHB_HEADFILE_H__ __FILE__ + +#define REGS_CODEC_AHB + +/* registers definitions for CODEC_AHB */ +#define REG_CODEC_AHB_AHB_RST SCI_ADDR(REGS_CODEC_AHB_BASE, 0x0000)/*AHB_RST*/ +#define REG_CODEC_AHB_CKG_ENABLE SCI_ADDR(REGS_CODEC_AHB_BASE, 0x0004)/*CKG_ENABLE*/ +#define REG_CODEC_AHB_CLOCK_SEL SCI_ADDR(REGS_CODEC_AHB_BASE, 0x0008)/*CLOCK_SEL*/ +#define REG_CODEC_AHB_CODA7_STAT SCI_ADDR(REGS_CODEC_AHB_BASE, 0x000C)/*CODA7_STAT*/ + + + +/* bits definitions for register REG_CODEC_AHB_RF_AHB_RST */ +#define BIT_CODA7_APB_SOFT_RST ( BIT(2) ) +#define BIT_CODA7_CC_SOFT_RST ( BIT(1) ) +#define BIT_CODA7_AXI_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_CODEC_AHB_RF_CKG_ENABLE */ +#define BIT_CODA7_CKG_EN ( BIT(4) ) +#define BIT_CODA7_CC_CKG_EN ( BIT(1) ) +#define BIT_CODA7_AXI_CKG_EN ( BIT(0) ) + +/* bits definitions for register REG_CODEC_AHB_RF_CLOCK_SEL */ +#define BITS_CLK_CODA7_AXI_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_CLK_CODA7_CC_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CLK_CODA7_APB_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CODEC_AHB_RF_CODA7_STAT */ +#define BIT_CODA7_RUN ( BIT(1) ) +#define BIT_CODA7_IDLE ( BIT(0) ) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_cortex_ahb_rf.h b/include/soc/sprd/chip_x35lt8/__regs_cortex_ahb_rf.h new file mode 100644 index 00000000..f36694d6 --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_cortex_ahb_rf.h @@ -0,0 +1,205 @@ +/* the head file modifier: g 2015-03-19 15:42:42*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_CORTEX_AHB_RF_HEADFILE_H__ +#define __H_REGS_CORTEX_AHB_RF_HEADFILE_H__ __FILE__ + +#define REGS_CORTEX_AHB_RF + +/* registers definitions for CORTEX_AHB_RF */ +#define REG_CORTEX_AHB_RF_CLK_CORTEX_AXI_CTRL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0000)/*CLK_CORTEX_AXI_CTRL*/ +#define REG_CORTEX_AHB_RF_CLK_CORTEX_AHB_CTRL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0004)/*CLK_CORTEX_AHB_CTRL*/ +#define REG_CORTEX_AHB_RF_CLK_CORTEX_APB_CTRL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0008)/*CLK_CORTEX_APB_CTRL*/ +#define REG_CORTEX_AHB_RF_CLK_SEC0_CTRL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x000C)/*CLK_SEC0_CTRL*/ +#define REG_CORTEX_AHB_RF_CLK_SEC1_CTRL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0010)/*CLK_SEC1_CTRL*/ +#define REG_CORTEX_AHB_RF_CA5_CFG SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0030)/*CA5_CFG*/ +#define REG_CORTEX_AHB_RF_AHB_CTRL0 SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0034)/*AHB_CTRL0*/ +#define REG_CORTEX_AHB_RF_AHB_CTRL2 SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x003C)/*AHB_CTRL2*/ +#define REG_CORTEX_AHB_RF_AHB_RST0_STS SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0060)/*AHB_RST0_STS*/ +#define REG_CORTEX_AHB_RF_CA5_RST_SET SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0064)/*CA5_RST_SET*/ +#define REG_CORTEX_AHB_RF_ARCH_EB SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0068)/*ARCH_EB*/ +#define REG_CORTEX_AHB_RF_PTEST_FUNC SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x006C)/*REMAP*/ +#define REG_CORTEX_AHB_RF_AHB_MISC_CTL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0070)/*AHB_MISC_CTL*/ +#define REG_CORTEX_AHB_RF_CA5_CTRL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0074)/*CA5_CTRL*/ +#define REG_CORTEX_AHB_RF_AUTO_GATE_CTRL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0078)/*AUTO_GATE_CTRL*/ +#define REG_CORTEX_AHB_RF_AHB_PAUSE SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0080)/*AHB_PAUSE*/ +#define REG_CORTEX_AHB_RF_AHB_SLP_CTL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0084)/*AHB_SLP_CTL*/ +#define REG_CORTEX_AHB_RF_AHB_SLP_STS SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0088)/*AHB_SLP_STS*/ +#define REG_CORTEX_AHB_RF_MCU_CLK_CTL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x008C)/*MCU_CLK_CTL*/ +#define REG_CORTEX_AHB_RF_RES_REG0 SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x00F4)/*RES_REG0*/ +#define REG_CORTEX_AHB_RF_CHIP_ID SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0200)/*CHIP_ID*/ + + + +/* bits definitions for register REG_CORTEX_AHB_RF_CLK_CORTEX_AXI_CTRL */ +#define BITS_CLK_CORTEX_AXI_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_CLK_CORTEX_AHB_CTRL */ +#define BITS_CLK_CORTEX_AHB_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_CLK_CORTEX_APB_CTRL */ +#define BITS_CLK_CORTEX_APB_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_CLK_SEC0_CTRL */ +#define BITS_CLK_SEC0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_CLK_SEC1_CTRL */ +#define BITS_CLK_SEC1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_CA5_CFG */ +#define BITS_CA5_DBG_DIV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_CA5_AXI_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CA5_MCU_DIV(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BITS_CA5_MCU_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_AHB_CTRL0 */ +#define BITS_TFT_MST_HPROT(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_PPP1_MST_HPROT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_PPP0_MST_HPROT(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_TFT_EB ( BIT(18) ) +#define BIT_PPP1_EB ( BIT(17) ) +#define BIT_PPP0_EB ( BIT(16) ) +#define BITS_SEC1_MST_HPROT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_SEC0_MST_HPROT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BIT_SEC1_EB ( BIT(5) ) +#define BIT_SEC1_CKG_EN ( BIT(4) ) +#define BIT_SEC0_EB ( BIT(3) ) +#define BIT_SEC0_CKG_EN ( BIT(2) ) +#define BIT_DMA_EB ( BIT(1) ) +#define BIT_DMA_CKG_EN ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_AHB_CTRL2 */ +#define BITS_BUSMON1_CHN_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_AXIBUSMON_CHN_SEL(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_BUSMON0_CHN_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BIT_BUSMON1_EB ( BIT(3) ) +#define BIT_SPINLOCK_EB ( BIT(2) ) +#define BIT_AXIBUSMON_EB ( BIT(1) ) +#define BIT_BUSMON0_EB ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_AHB_RST0_STS */ +#define BIT_TFT_SOFT_RST ( BIT(11) ) +#define BIT_PPP1_SOFT_RST ( BIT(10) ) +#define BIT_PPP0_SOFT_RST ( BIT(9) ) +#define BIT_SEC1_CMD_PARSER_RST ( BIT(8) ) +#define BIT_SEC0_CMD_PARSER_RST ( BIT(7) ) +#define BIT_SPINLOCK_SOFT_RST ( BIT(6) ) +#define BIT_SEC1_SOFT_RST ( BIT(5) ) +#define BIT_SEC0_SOFT_RST ( BIT(4) ) +#define BIT_BUSMON1_SOFT_RST ( BIT(3) ) +#define BIT_AXIBUSMON_SOFT_RST ( BIT(2) ) +#define BIT_BUSMON0_SOFT_RST ( BIT(1) ) +#define BIT_DMA_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_CA5_RST_SET */ +#define BIT_CA5_MTX_SOFT_RST ( BIT(3) ) +#define BIT_CA5_L2_SOFT_RST ( BIT(2) ) +#define BIT_CA5_DBG_SOFT_RST ( BIT(1) ) +#define BIT_CA5_CORE_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_ARCH_EB */ +#define BIT_AHB_ARCH_EB ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_PTEST_FUNC */ +#define BIT_PTEST_FUNC_ATSPEED_SEL ( BIT(2) ) +#define BIT_PTEST_FUNC_MODE ( BIT(1) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_AHB_MISC_CTL */ +#define BITS_DMA_W_PROT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMA_R_PROT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BIT_LCP2PUB_ACCESS_EN ( BIT(4) ) +#define BITS_MCU_SHM_CTRL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_CA5_CTRL */ +#define BIT_CA5_WDRESET_EN ( BIT(18) ) +#define BIT_CA5_TS_EN ( BIT(17) ) +#define BIT_CA5_CFGSDISABLE ( BIT(13) ) +#define BITS_CA5_CLK_AXI_DIV(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)) ) +#define BIT_CA5_CLK_DBG_EN_SEL ( BIT(10) ) +#define BIT_CA5_CLK_DBG_EN ( BIT(9) ) +#define BIT_CA5_DBGEN ( BIT(8) ) +#define BIT_CA5_NIDEN ( BIT(7) ) +#define BIT_CA5_SPIDEN ( BIT(6) ) +#define BIT_CA5_SPNIDEN ( BIT(5) ) +#define BIT_CA5_CP15DISABLE ( BIT(4) ) +#define BIT_CA5_TEINIT ( BIT(3) ) +#define BIT_CA5_L1RSTDISABLE ( BIT(2) ) +#define BIT_CA5_L2CFGEND ( BIT(1) ) +#define BIT_CA5_L2SPNIDEN ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_AUTO_GATE_CTRL */ +#define BIT_CORTEX_AHB_AUTO_GATE_EN ( BIT(5) ) +#define BIT_CA5_DBG_FORCE_SLEEP ( BIT(4) ) +#define BIT_CA5_DBG_AUTO_GATE_EN ( BIT(3) ) +#define BIT_CA5_CORE_AUTO_GATE_EN ( BIT(2) ) +#define BIT_LCPX_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_AHB_PAUSE */ +#define BIT_EMC_LIGHT_SLEEP_EN ( BIT(25) ) +#define BIT_EMC_DEEP_SLEEP_EN ( BIT(24) ) +#define BIT_APB_SLEEP_EN ( BIT(18) ) +#define BIT_APB_PERI_FRC_SLP ( BIT(17) ) +#define BIT_APB_PERI_FRC_ON ( BIT(16) ) +#define BIT_MCU_FORCE_DEEP_SLEEP ( BIT(15) ) +#define BIT_DMA_LSLP_EN ( BIT(4) ) +#define BIT_MCU_LIGHT_SLEEP_EN ( BIT(3) ) +#define BIT_MCU_DEEP_SLEEP_EN ( BIT(2) ) +#define BIT_MCU_SYS_SLEEP_EN ( BIT(1) ) +#define BIT_MCU_CORE_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_AHB_SLP_CTL */ +#define BIT_ARM_DAHB_SLEEP_EN ( BIT(4) ) +#define BIT_MCUMTX_AUTO_GATE_EN ( BIT(3) ) +#define BIT_MCU_AUTO_GATE_EN ( BIT(2) ) +#define BIT_AHB_AUTO_GATE_EN ( BIT(1) ) +#define BIT_ARM_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_AHB_SLP_STS */ +#define BIT_CHIP_SLP_ARM_CLR ( BIT(5) ) +#define BIT_CHIP_SLEEP_REC_ARM ( BIT(4) ) +#define BIT_APB_PERI_SLEEP ( BIT(3) ) +#define BIT_DMA_BUSY ( BIT(1) ) +#define BIT_EMC_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_MCU_CLK_CTL */ +#define BIT_CLK_LCP2LDSP_BRG_EN ( BIT(24) ) +#define BIT_CLK_LCP2PUB_BRG_EN ( BIT(23) ) +#define BIT_CLK_LCP2CP0_BRG_EN ( BIT(22) ) +#define BIT_CLK_CP_DBG_SEL ( BIT(21) ) +#define BIT_CLK_MCU_DBG_SEL ( BIT(20) ) +#define BITS_CLK_COM_DBG_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_CLK_SYS_DBG_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_CLK_AHB_DIV(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_CLK_MCU_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_APB_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CLK_MCU_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_RES_REG0 */ +#define BITS_RES_REG0(_X_) (_X_) + +/* bits definitions for register REG_CORTEX_AHB_RF_CHIP_ID */ +#define BITS_CHIP_ID(_X_) (_X_) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_cortex_glb.h b/include/soc/sprd/chip_x35lt8/__regs_cortex_glb.h new file mode 100644 index 00000000..b452c971 --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_cortex_glb.h @@ -0,0 +1,155 @@ +/* the head file modifier: g 2015-03-19 15:43:07*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_CORTEX_GLB_HEADFILE_H__ +#define __H_REGS_CORTEX_GLB_HEADFILE_H__ __FILE__ + +#define REGS_CORTEX_GLB + +/* registers definitions for CORTEX_GLB */ +#define REG_CORTEX_GLB_APB_EB0_STS SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0008)/*APB_EB0_STS*/ +#define REG_CORTEX_GLB_APB_RST0_STS SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0014)/*APB_RST0_STS*/ +#define REG_CORTEX_GLB_APB_MCU_RST SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0018)/*APB_MCU_RST*/ +#define REG_CORTEX_GLB_APB_CLK_SEL0 SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x001C)/*APB_CLK_SEL0*/ +#define REG_CORTEX_GLB_APB_CLK_SEL1 SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0020)/*APB_CLK_SEL1*/ +#define REG_CORTEX_GLB_APB_ARCH_EB SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0024)/*APB_ARCH_EB*/ +#define REG_CORTEX_GLB_APB_MISC_CTL0 SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0028)/*APB_MISC_CTL0*/ +#define REG_CORTEX_GLB_APB_MISC_CTL1 SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x002C)/*APB_MISC_CTL1*/ +#define REG_CORTEX_GLB_APB_CLK_SEL2 SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0030)/*APB_CLK_SEL2*/ +#define REG_CORTEX_GLB_APB_BUS_CTL0 SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0058)/*APB_BUS_CTL0*/ +#define REG_CORTEX_GLB_APB_DSP_INT_CLR SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0074)/*APB_DSP_INT_CLR*/ +#define REG_CORTEX_GLB_APB_MISC_INT_STS SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0078)/*APB_MISC_INT_STS*/ +#define REG_CORTEX_GLB_APB_HWRST SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0080)/*APB_HWRST*/ +#define REG_CORTEX_GLB_APB_ARM_BOOT_ADDR SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0084)/*APB_ARM_BOOT_ADDR*/ + + + +/* bits definitions for register REG_CORTEX_GLB_APB_EB0_STS */ +#define BIT_EIC_RTC_EB ( BIT(19) ) +#define BIT_EIC_EB ( BIT(18) ) +#define BIT_RFFE_EB ( BIT(17) ) +#define BIT_EPT_EB ( BIT(16) ) +#define BIT_GPIO_EB ( BIT(15) ) +#define BIT_TMR_RTC_EB ( BIT(14) ) +#define BIT_TMR_EB ( BIT(13) ) +#define BIT_SYSTMR_RTC_EB ( BIT(12) ) +#define BIT_SYSTMR_EB ( BIT(11) ) +#define BIT_IIS3_EB ( BIT(10) ) +#define BIT_IIS2_EB ( BIT(9) ) +#define BIT_IIS1_EB ( BIT(8) ) +#define BIT_IIS0_EB ( BIT(7) ) +#define BIT_SIM2_EB ( BIT(6) ) +#define BIT_SIM1_EB ( BIT(5) ) +#define BIT_SIM0_EB ( BIT(4) ) +#define BIT_UART1_EB ( BIT(3) ) +#define BIT_UART0_EB ( BIT(2) ) +#define BIT_WDG_RTC_EB ( BIT(1) ) +#define BIT_WDG_EB ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_RST0_STS */ +#define BIT_EIC_SOFT_RST ( BIT(16) ) +#define BIT_RFFE_SOFT_RST ( BIT(15) ) +#define BIT_MCU_DSP_RST ( BIT(14) ) +#define BIT_EPT_SOFT_RST ( BIT(13) ) +#define BIT_GPIO_SOFT_RST ( BIT(12) ) +#define BIT_TMR_SOFT_RST ( BIT(11) ) +#define BIT_SYSTMR_SOFT_RST ( BIT(10) ) +#define BIT_IIS3_SOFT_RST ( BIT(9) ) +#define BIT_IIS2_SOFT_RST ( BIT(8) ) +#define BIT_IIS1_SOFT_RST ( BIT(7) ) +#define BIT_IIS0_SOFT_RST ( BIT(6) ) +#define BIT_SIM2_SOFT_RST ( BIT(5) ) +#define BIT_SIM1_SOFT_RST ( BIT(4) ) +#define BIT_SIM0_SOFT_RST ( BIT(3) ) +#define BIT_UART1_SOFT_RST ( BIT(2) ) +#define BIT_UART0_SOFT_RST ( BIT(1) ) +#define BIT_WDG_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_MCU_RST */ +#define BIT_MCU_SOFT_RST_SET ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_CLK_SEL0 */ +#define BITS_CLK_UART1_DIV(_X_) ( (_X_) << 7 & (BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_CLK_UART1_SEL(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)) ) +#define BITS_CLK_UART0_DIV(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)) ) +#define BITS_CLK_UART0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_CLK_SEL1 */ +#define BIT_CLK_IIS1_PAD_SEL ( BIT(24) ) +#define BITS_CLK_IIS1_DIV(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_CLK_IIS1_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BIT_CLK_IIS0_PAD_SEL ( BIT(8) ) +#define BITS_CLK_IIS0_DIV(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_CLK_IIS0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_ARCH_EB */ +#define BIT_RTC_ARCH_EB ( BIT(1) ) +#define BIT_APB_ARCH_EB ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_MISC_CTL0 */ +#define BIT_ALL_CLK_EN ( BIT(28) ) +#define BIT_DMA_LSLP_EN ( BIT(27) ) +#define BIT_WAKEUP_XTL_EN_3G ( BIT(26) ) +#define BIT_WAKEUP_XTL_EN_2G ( BIT(25) ) +#define BIT_ARM_JTAG_EN ( BIT(24) ) +#define BITS_ARM_FRC_STOP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_MISC_CTL1 */ +#define BITS_BUFON_CTRL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_SIM2_CLK_POLARITY ( BIT(3) ) +#define BIT_SIM1_CLK_POLARITY ( BIT(2) ) +#define BIT_SIM0_CLK_POLARITY ( BIT(1) ) +#define BIT_ROM_CLK_EN ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_CLK_SEL2 */ +#define BIT_CLK_IIS3_PAD_SEL ( BIT(24) ) +#define BITS_CLK_IIS3_DIV(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_CLK_IIS3_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BIT_CLK_IIS2_PAD_SEL ( BIT(8) ) +#define BITS_CLK_IIS2_DIV(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_CLK_IIS2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_BUS_CTL0 */ +#define BIT_IIS3_CTRL_SEL ( BIT(7) ) +#define BIT_IIS2_CTRL_SEL ( BIT(6) ) +#define BIT_RFFE_CTRL_SEL ( BIT(5) ) +#define BIT_IIS1_CTRL_SEL ( BIT(3) ) +#define BIT_IIS0_CTRL_SEL ( BIT(2) ) +#define BIT_UART0_CTRL_SEL ( BIT(1) ) +#define BIT_UART1_CTRL_SEL ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_DSP_INT_CLR */ +#define BIT_RFT_INT_CLR ( BIT(2) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_MISC_INT_STS */ +#define BIT_RFT_INT ( BIT(2) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_HWRST */ +#define BITS_HWRST_REG(_X_) (_X_) + +/* bits definitions for register REG_CORTEX_GLB_APB_ARM_BOOT_ADDR */ +#define BITS_ARMBOOT_ADDR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_cp_ahb_rf.h b/include/soc/sprd/chip_x35lt8/__regs_cp_ahb_rf.h new file mode 100644 index 00000000..a3a6275d --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_cp_ahb_rf.h @@ -0,0 +1,299 @@ +/* the head file modifier: g 2015-03-19 17:10:49*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_CP_AHB_RF_HEADFILE_H__ +#define __H_REGS_CP_AHB_RF_HEADFILE_H__ __FILE__ + +#define REGS_CP_AHB_RF + +/* registers definitions for CP_AHB_RF */ +#define REG_CP_AHB_RF_AHB_EB0_STS SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0008)/*AHB_EB0_STS*/ +#define REG_CP_AHB_RF_AHB_RST0_STS SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0014)/*AHB_RST0_STS*/ +#define REG_CP_AHB_RF_ARCH_EB SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0018)/*ARCH_EB*/ +#define REG_CP_AHB_RF_AHB_REMAP SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x001C)/*AHB_REMAP*/ +#define REG_CP_AHB_RF_AHB_MISC_CTL SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0020)/*AHB_MISC_CTL*/ +#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL0 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0024)/*AHB_MTX_PRI_SEL0*/ +#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL1 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0028)/*AHB_MTX_PRI_SEL1*/ +#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL2 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x002C)/*AHB_MTX_PRI_SEL2*/ +#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL3 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0030)/*AHB_MTX_PRI_SEL3*/ +#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL4 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0034)/*AHB_MTX_PRI_SEL4*/ +#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL5 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0038)/*AHB_MTX_PRI_SEL5*/ +#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL6 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x003C)/*AHB_MTX_PRI_SEL6*/ +#define REG_CP_AHB_RF_AHB_PAUSE SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0040)/*AHB_PAUSE*/ +#define REG_CP_AHB_RF_AHB_SLP_CTL SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0044)/*AHB_SLP_CTL*/ +#define REG_CP_AHB_RF_AHB_SLP_STS SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0048)/*AHB_SLP_STS*/ +#define REG_CP_AHB_RF_MCU_CLK_CTL SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x004C)/*MCU_CLK_CTL*/ +#define REG_CP_AHB_RF_DSP_CTL SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0050)/*DSP_CTL*/ +#define REG_CP_AHB_RF_DSP_BOOT_VECTOR SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0054)/*DSP_BOOT_VECTOR*/ +#define REG_CP_AHB_RF_DSP_RST SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0058)/*DSP_RST*/ +#define REG_CP_AHB_RF_DSP_JTAG_CTL SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x005C)/*DSP_JTAG_CTL*/ +#define REG_CP_AHB_RF_MCU_C2C_SEMA SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0060)/*MCU_C2C_SEMA*/ +#define REG_CP_AHB_RF_GGE_DSP_BOOT_VECTOR SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0064)/*GGE_DSP_BOOT_VECTOR*/ +#define REG_CP_AHB_RF_CHIP_ID SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x01FC)/*CHIP_ID*/ + + + +/* bits definitions for register REG_CP_AHB_RF_AHB_EB0_STS */ +#define BIT_LZMA_EN ( BIT(11) ) +#define BIT_WCDMA_EN5 ( BIT(9) ) +#define BIT_WCDMA_EN4 ( BIT(8) ) +#define BIT_WCDMA_EN3 ( BIT(7) ) +#define BIT_WCDMA_EN2 ( BIT(6) ) +#define BIT_WCDMA_EN1 ( BIT(5) ) +#define BIT_WCDMA_EN0 ( BIT(4) ) +#define BIT_BUSMON2_EN ( BIT(3) ) +#define BIT_BUSMON1_EN ( BIT(2) ) +#define BIT_BUSMON0_EN ( BIT(1) ) +#define BIT_DMA_EN ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_RST0_STS */ +#define BIT_LZMA_SOFT_RST ( BIT(8) ) +#define BIT_WSYS_SOFT_RST ( BIT(6) ) +#define BIT_ARM1_SOFT_RST ( BIT(4) ) +#define BIT_BUSMON2_SOFT_RST ( BIT(3) ) +#define BIT_BUSMON1_SOFT_RST ( BIT(2) ) +#define BIT_BUSMON0_SOFT_RST ( BIT(1) ) +#define BIT_DMA_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_ARCH_EB */ +#define BIT_AHB_ARCH_EB ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_REMAP */ +#define BIT_PTEST_FUNC_ATSPEED_SEL ( BIT(2) ) +#define BIT_PTEST_FUNC_MODE ( BIT(1) ) +#define BIT_REMAP ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_MISC_CTL */ +#define BITS_MCU_GGE_SHM_CTRL(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)) ) +#define BITS_LZMA_M_PROT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMA_W_PROT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMA_R_PROT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_MCU_SHM_CTRL(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BIT_RF_SWT_AUTO_EN ( BIT(1) ) +#define BIT_WCDMA_ASHB_EN ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL0 */ +#define BITS_ARMMTX_M3TOS0_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ARMMTX_M3TOS0_ADJ_EN ( BIT(27) ) +#define BIT_ARMMTX_M3TOS0_RND_EN ( BIT(26) ) +#define BITS_ARMMTX_M3TOS0_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_ARMMTX_M2TOS0_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M2TOS0_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M2TOS0_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M2TOS0_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M1TOS0_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M1TOS0_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M1TOS0_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M1TOS0_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M0TOS0_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M0TOS0_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M0TOS0_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M0TOS0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL1 */ +#define BITS_ARMMTX_M3TOS1_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ARMMTX_M3TOS1_ADJ_EN ( BIT(27) ) +#define BIT_ARMMTX_M3TOS1_RND_EN ( BIT(26) ) +#define BITS_ARMMTX_M3TOS1_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_ARMMTX_M2TOS1_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M2TOS1_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M2TOS1_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M2TOS1_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M1TOS1_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M1TOS1_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M1TOS1_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M1TOS1_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M0TOS1_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M0TOS1_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M0TOS1_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M0TOS1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL2 */ +#define BITS_ARMMTX_M1TOS2_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ARMMTX_M1TOS2_ADJ_EN ( BIT(27) ) +#define BIT_ARMMTX_M1TOS2_RND_EN ( BIT(26) ) +#define BITS_ARMMTX_M1TOS2_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_ARMMTX_M0TOS2_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M0TOS2_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M0TOS2_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M0TOS2_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M5TOS1_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M5TOS1_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M5TOS1_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M5TOS1_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M4TOS1_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M4TOS1_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M4TOS1_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M4TOS1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL3 */ +#define BITS_ARMMTX_M5TOS2_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ARMMTX_M5TOS2_ADJ_EN ( BIT(27) ) +#define BIT_ARMMTX_M5TOS2_RND_EN ( BIT(26) ) +#define BITS_ARMMTX_M5TOS2_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_ARMMTX_M5TOS4_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M5TOS4_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M5TOS4_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M5TOS4_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M3TOS2_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M3TOS2_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M3TOS2_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M3TOS2_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M2TOS2_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M2TOS2_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M2TOS2_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M2TOS2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL4 */ +#define BITS_ARMMTX_M4TOS3_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M4TOS3_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M4TOS3_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M4TOS3_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M1TOS3_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M1TOS3_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M1TOS3_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M1TOS3_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M0TOS3_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M0TOS3_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M0TOS3_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M0TOS3_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL5 */ +#define BITS_ARMMTX_M4TOS0_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ARMMTX_M4TOS0_ADJ_EN ( BIT(27) ) +#define BIT_ARMMTX_M4TOS0_RND_EN ( BIT(26) ) +#define BITS_ARMMTX_M4TOS0_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_ARMMTX_M4TOS4_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M4TOS4_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M4TOS4_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M4TOS4_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M1TOS4_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M1TOS4_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M1TOS4_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M1TOS4_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M0TOS4_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M0TOS4_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M0TOS4_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M0TOS4_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL6 */ +#define BITS_ARMMTX_M3TOS5_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ARMMTX_M3TOS5_ADJ_EN ( BIT(27) ) +#define BIT_ARMMTX_M3TOS5_RND_EN ( BIT(26) ) +#define BITS_ARMMTX_M3TOS5_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_ARMMTX_M2TOS5_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M2TOS5_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M2TOS5_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M2TOS5_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M1TOS5_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M1TOS5_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M1TOS5_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M1TOS5_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M0TOS5_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M0TOS5_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M0TOS5_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M0TOS5_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_PAUSE */ +#define BIT_MCU_GGE_DEEP_SLEEP_EN ( BIT(5) ) +#define BIT_MCU_LIGHT_SLEEP_EN ( BIT(4) ) +#define BIT_APB_SLEEP ( BIT(3) ) +#define BIT_MCU_DEEP_SLEEP_EN ( BIT(2) ) +#define BIT_MCU_SYS_SLEEP_EN ( BIT(1) ) +#define BIT_MCU_CORE_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_SLP_CTL */ +#define BIT_AHB_VCP1_DEEP_SLEEP_EN ( BIT(6) ) +#define BIT_GGE_ARM_DAHB_SLEEP_EN ( BIT(5) ) +#define BIT_ARM_DAHB_SLEEP_EN ( BIT(4) ) +#define BIT_MCUMTX_AUTO_GATE_EN ( BIT(3) ) +#define BIT_MCU_AUTO_GATE_EN ( BIT(2) ) +#define BIT_AHB_AUTO_GATE_EN ( BIT(1) ) +#define BIT_ARM_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_SLP_STS */ +#define BIT_GGE_DSP_MAHB_SLEEP_EN ( BIT(4) ) +#define BIT_APB_PERI_SLEEP ( BIT(3) ) +#define BIT_DSP_MAHB_SLEEP_EN ( BIT(2) ) +#define BIT_DMA_BUSY ( BIT(1) ) +#define BIT_EMC_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_MCU_CLK_CTL */ +#define BIT_CLK_CP_DBG_GGE_SEL ( BIT(28) ) +#define BIT_CLK_GGE_DBG_SEL ( BIT(27) ) +#define BITS_CLK_COM_GGE_DBG_SEL(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BIT_CLK_SYS_GGE_DBG_SEL ( BIT(24) ) +#define BITS_CLK_LZMA_SEL(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)) ) +#define BIT_CLK_CP_DBG_SEL ( BIT(21) ) +#define BIT_CLK_MCU_DBG_SEL ( BIT(20) ) +#define BITS_CLK_COM_DBG_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_CLK_SYS_DBG_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_CLK_AHB_DIV(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_CLK_MCU_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_APB_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CLK_MCU_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_CP_AHB_RF_DSP_CTL */ +#define BIT_GGE_ASHB_ARMTODSP_EN ( BIT(5) ) +#define BIT_GGE_FRC_CLK_DSP_EN ( BIT(4) ) +#define BIT_GGE_DSP_BOOT_EN ( BIT(3) ) +#define BIT_ASHB_ARMTODSP_EN ( BIT(2) ) +#define BIT_FRC_CLK_DSP_EN ( BIT(1) ) +#define BIT_DSP_BOOT_EN ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_DSP_BOOT_VECTOR */ +#define BITS_DSP_BOOT_VECTOR(_X_) (_X_) + +/* bits definitions for register REG_CP_AHB_RF_DSP_RST */ +#define BIT_GGE_DSP_SYS_SRST ( BIT(3) ) +#define BIT_GGE_DSP_CORE_SRST_N ( BIT(2) ) +#define BIT_DSP_SYS_SRST ( BIT(1) ) +#define BIT_DSP_CORE_SRST_N ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_DSP_JTAG_CTL */ +#define BIT_GGE_CEVA_SW_JTAG_ENA ( BIT(24) ) +#define BIT_GGE_STDO ( BIT(20) ) +#define BIT_GGE_STCK ( BIT(19) ) +#define BIT_GGE_STMS ( BIT(18) ) +#define BIT_GGE_STDI ( BIT(17) ) +#define BIT_GGE_STRTCK ( BIT(16) ) +#define BIT_CEVA_SW_JTAG_ENA ( BIT(8) ) +#define BIT_STDO ( BIT(4) ) +#define BIT_STCK ( BIT(3) ) +#define BIT_STMS ( BIT(2) ) +#define BIT_STDI ( BIT(1) ) +#define BIT_STRTCK ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_MCU_C2C_SEMA */ +#define BITS_GGE_MCU_C2C_SEMA(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_MCU_C2C_SEMA(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_CP_AHB_RF_GGE_DSP_BOOT_VECTOR */ +#define BITS_GGE_DSP_BOOT_VECTOR(_X_) (_X_) + +/* bits definitions for register REG_CP_AHB_RF_CHIP_ID */ +#define BITS_CHIP_ID(_X_) (_X_) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_cp_apb_rf.h b/include/soc/sprd/chip_x35lt8/__regs_cp_apb_rf.h new file mode 100644 index 00000000..dc847447 --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_cp_apb_rf.h @@ -0,0 +1,247 @@ +/* the head file modifier: g 2015-03-19 15:46:02*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_CP_APB_RF_HEADFILE_H__ +#define __H_REGS_CP_APB_RF_HEADFILE_H__ __FILE__ + +#define REGS_CP_APB_RF + +/* registers definitions for CP_APB_RF */ +#define REG_CP_APB_RF_APB_EB0_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0008)/*APB_EB0_STS*/ +#define REG_CP_APB_RF_APB_RST0_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0014)/*APB_RST0_STS*/ +#define REG_CP_APB_RF_APB_MCU_RST SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0018)/*APB_MCU_RST*/ +#define REG_CP_APB_RF_APB_CLK_SEL0 SCI_ADDR(REGS_CP_APB_RF_BASE, 0x001C)/*APB_CLK_SEL0*/ +#define REG_CP_APB_RF_APB_CLK_DIV0 SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0020)/*APB_CLK_DIV0*/ +#define REG_CP_APB_RF_APB_ARCH_EB SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0024)/*APB_ARCH_EB*/ +#define REG_CP_APB_RF_APB_MISC_CTL0 SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0028)/*APB_MISC_CTL0*/ +#define REG_CP_APB_RF_APB_MISC_CTL1 SCI_ADDR(REGS_CP_APB_RF_BASE, 0x002C)/*APB_MISC_CTL1*/ +#define REG_CP_APB_RF_APB_PIN_SEL SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0040)/*APB_PIN_SEL*/ +#define REG_CP_APB_RF_APB_SLP_CTL SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0044)/*APB_SLP_CTL*/ +#define REG_CP_APB_RF_APB_WSYS_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0048)/*APB_WSYS_STS*/ +#define REG_CP_APB_RF_APB_SLP_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0050)/*APB_SLP_STS*/ +#define REG_CP_APB_RF_APB_ROM_PD_CTL SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0054)/*APB_ROM_PD_CTL*/ +#define REG_CP_APB_RF_APB_BUS_CTL0 SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0058)/*APB_BUS_CTL0*/ +#define REG_CP_APB_RF_APB_DSP_INT_CLR SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0074)/*APB_DSP_INT_CLR*/ +#define REG_CP_APB_RF_APB_MISC_INT_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0078)/*APB_MISC_INT_STS*/ +#define REG_CP_APB_RF_APB_HWRST SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0080)/*APB_HWRST*/ +#define REG_CP_APB_RF_APB_ARM_BOOT_ADDR SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0084)/*APB_ARM_BOOT_ADDR*/ +#define REG_CP_APB_RF_APB_GGE_SLP_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0088)/*APB_GGE_SLP_STS*/ + + + +/* bits definitions for register REG_CP_APB_RF_APB_EB0_STS */ +#define BIT_UART2_EB ( BIT(20) ) +#define BIT_EIC_RTC_EB ( BIT(19) ) +#define BIT_EIC_EB ( BIT(18) ) +#define BIT_RFFE_EB ( BIT(17) ) +#define BIT_EPT_EB ( BIT(16) ) +#define BIT_GPIO_EB ( BIT(15) ) +#define BIT_TMR_RTC_EB ( BIT(14) ) +#define BIT_TMR_EB ( BIT(13) ) +#define BIT_SYSTMR_RTC_EB ( BIT(12) ) +#define BIT_SYSTMR_EB ( BIT(11) ) +#define BIT_IIS3_EB ( BIT(10) ) +#define BIT_IIS2_EB ( BIT(9) ) +#define BIT_IIS1_EB ( BIT(8) ) +#define BIT_IIS0_EB ( BIT(7) ) +#define BIT_SIM2_EB ( BIT(6) ) +#define BIT_SIM1_EB ( BIT(5) ) +#define BIT_SIM0_EB ( BIT(4) ) +#define BIT_UART1_EB ( BIT(3) ) +#define BIT_UART0_EB ( BIT(2) ) +#define BIT_WDG_RTC_EB ( BIT(1) ) +#define BIT_WDG_EB ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_RST0_STS */ +#define BIT_UART2_SOFT_RST ( BIT(20) ) +#define BIT_GGE_MCU_DSP_RST ( BIT(19) ) +#define BIT_EIC_SOFT_RST ( BIT(16) ) +#define BIT_RFFE_SOFT_RST ( BIT(15) ) +#define BIT_MCU_DSP_RST ( BIT(14) ) +#define BIT_EPT_SOFT_RST ( BIT(13) ) +#define BIT_GPIO_SOFT_RST ( BIT(12) ) +#define BIT_TMR_SOFT_RST ( BIT(11) ) +#define BIT_SYSTMR_SOFT_RST ( BIT(10) ) +#define BIT_IIS3_SOFT_RST ( BIT(9) ) +#define BIT_IIS2_SOFT_RST ( BIT(8) ) +#define BIT_IIS1_SOFT_RST ( BIT(7) ) +#define BIT_IIS0_SOFT_RST ( BIT(6) ) +#define BIT_SIM2_SOFT_RST ( BIT(5) ) +#define BIT_SIM1_SOFT_RST ( BIT(4) ) +#define BIT_SIM0_SOFT_RST ( BIT(3) ) +#define BIT_UART1_SOFT_RST ( BIT(2) ) +#define BIT_UART0_SOFT_RST ( BIT(1) ) +#define BIT_WDG_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_MCU_RST */ +#define BIT_MCU_SOFT_RST_SET ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_CLK_SEL0 */ +#define BIT_CLK_IIS3_PAD_SEL ( BIT(19) ) +#define BIT_CLK_IIS2_PAD_SEL ( BIT(18) ) +#define BIT_CLK_IIS1_PAD_SEL ( BIT(17) ) +#define BIT_CLK_IIS0_PAD_SEL ( BIT(16) ) +#define BITS_CLK_UART2_SEL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_CLK_IIS3_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_CLK_IIS2_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_CLK_IIS1_SEL(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_CLK_IIS0_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CLK_UART1_SEL(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_CLK_UART0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CP_APB_RF_APB_CLK_DIV0 */ +#define BITS_CLK_IIS2_DIV(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_CLK_IIS1_DIV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)) ) +#define BITS_CLK_IIS0_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_CLK_UART1_DIV(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BITS_CLK_UART0_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_CP_APB_RF_APB_ARCH_EB */ +#define BITS_CLK_UART2_DIV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)) ) +#define BITS_CLK_IIS3_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_RTC_ARCH_EB ( BIT(1) ) +#define BIT_APB_ARCH_EB ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_MISC_CTL0 */ +#define BIT_GGE_ALL_CLK_EN ( BIT(29) ) +#define BIT_ALL_CLK_EN ( BIT(28) ) +#define BIT_DMA_LSLP_EN ( BIT(27) ) +#define BIT_WAKEUP_XTL_EN_3G_W ( BIT(26) ) +#define BIT_WAKEUP_XTL_EN_2G ( BIT(25) ) +#define BIT_ARM_JTAG_EN ( BIT(24) ) +#define BIT_WAKEUP_XTL_EN_3G_TD ( BIT(23) ) +#define BIT_GGE_WAKEUP_XTL_EN_2G ( BIT(22) ) +#define BITS_ARM_FRC_STOP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) ) + +/* bits definitions for register REG_CP_APB_RF_APB_MISC_CTL1 */ +#define BITS_BUFON_CTRL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_SIM2_CLK_POLARITY ( BIT(3) ) +#define BIT_SIM1_CLK_POLARITY ( BIT(2) ) +#define BIT_SIM0_CLK_POLARITY ( BIT(1) ) +#define BIT_ROM_CLK_EN ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_PIN_SEL */ +#define BIT_DJTAG_PIN_IN_SEL ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_SLP_CTL */ +#define BITS_GGE_DEEP_SLP_DBG(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_APB_PERI_FRC_ON ( BIT(20) ) +#define BIT_APB_PERI_FRC_SLP ( BIT(16) ) +#define BIT_MCU_XTLEN_AUTOPD_EN ( BIT(12) ) +#define BIT_MCU_FORCE_GGE_LIGHT_SLEEP ( BIT(9) ) +#define BIT_MCU_FORCE_LIGHT_SLEEP ( BIT(8) ) +#define BIT_CHIP_SLP_ARM_CLR ( BIT(4) ) +#define BIT_MCU_FORCE_GGE_DEEP_SLEEP ( BIT(3) ) +#define BIT_MCU_FORCE_WSYS_LT_STOP ( BIT(2) ) +#define BIT_MCU_FORCE_WSYS_STOP ( BIT(1) ) +#define BIT_MCU_FORCE_DEEP_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_WSYS_STS */ +#define BITS_DEEP_SLP_DBG(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_WSYS_STATUS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_CP_APB_RF_APB_SLP_STS */ +#define BIT_DSP_MAHB_SLEEP_EN ( BIT(28) ) +#define BIT_MCU_PERI_STOP ( BIT(27) ) +#define BIT_DSP_PERI_STOP ( BIT(26) ) +#define BIT_ECC_CKG_EN ( BIT(25) ) +#define BIT_QBC_CKG_EN ( BIT(24) ) +#define BIT_DSP_TWPLL_EN ( BIT(21) ) +#define BIT_STC_TMR_AUTOPD_XTL_EN ( BIT(20) ) +#define BIT_RFT_TMR_AUTOPD_XTL_EN ( BIT(19) ) +#define BIT_STC_TMR_AUTOPD_RF_EN ( BIT(18) ) +#define BIT_RFT_TMR_AUTOPD_RF_EN ( BIT(17) ) +#define BIT_CHIP_SLEEP_REC_ARM ( BIT(16) ) +#define BIT_DSP_CORE_STOP ( BIT(15) ) +#define BIT_DSP_MTX_STOP ( BIT(14) ) +#define BIT_DSP_AHB_STOP ( BIT(13) ) +#define BIT_DSP_SYS_STOP ( BIT(12) ) +#define BIT_DSP_DEEP_STOP ( BIT(11) ) +#define BIT_ASHB_DSPTOARM_EN ( BIT(10) ) +#define BIT_ASHB_ARMTODSP_VALID ( BIT(9) ) +#define BIT_EMC_STOP_CH3 ( BIT(8) ) +#define BIT_EMC_STOP_CH4 ( BIT(7) ) +#define BIT_EMC_STOP_CH5 ( BIT(6) ) +#define BIT_FRC_WAKE_EN ( BIT(5) ) +#define BIT_TMR_WAKE_AFC ( BIT(4) ) +#define BIT_SCH_SLEEP ( BIT(3) ) +#define BIT_DSP_STOP ( BIT(2) ) +#define BIT_MCU_STOP ( BIT(1) ) +#define BIT_EMC_STOP ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_ROM_PD_CTL */ +#define BIT_GGE_ROM_FORCE_ON ( BIT(1) ) +#define BIT_ROM_FORCE_ON ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_BUS_CTL0 */ +#define BIT_IIS3_DSP_CTRL_SEL ( BIT(11) ) +#define BIT_IIS2_DSP_CTRL_SEL ( BIT(10) ) +#define BIT_IIS1_DSP_CTRL_SEL ( BIT(9) ) +#define BIT_IIS0_DSP_CTRL_SEL ( BIT(8) ) +#define BIT_UART2_CTRL_SEL ( BIT(7) ) +#define BIT_RFFE_CTRL_SEL ( BIT(5) ) +#define BIT_IIS3_CTRL_SEL ( BIT(4) ) +#define BIT_IIS2_CTRL_SEL ( BIT(3) ) +#define BIT_IIS1_CTRL_SEL ( BIT(2) ) +#define BIT_IIS0_CTRL_SEL ( BIT(1) ) +#define BIT_UART1_CTRL_SEL ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_DSP_INT_CLR */ +#define BIT_RFT_INT_CLR ( BIT(2) ) + +/* bits definitions for register REG_CP_APB_RF_APB_MISC_INT_STS */ +#define BIT_RFT_INT ( BIT(2) ) + +/* bits definitions for register REG_CP_APB_RF_APB_HWRST */ +#define BITS_HWRST_REG(_X_) (_X_) + +/* bits definitions for register REG_CP_APB_RF_APB_ARM_BOOT_ADDR */ +#define BITS_ARMBOOT_ADDR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_CP_APB_RF_APB_GGE_SLP_STS */ +#define BIT_GGE_DSP_MAHB_SLEEP_EN ( BIT(21) ) +#define BIT_GGE_DSP_PERI_STOP ( BIT(20) ) +#define BIT_GGE_QBC_CKG_EN ( BIT(19) ) +#define BIT_GGE_DSP_TWPLL_EN ( BIT(18) ) +#define BIT_GGE_STC_TMR_AUTOPD_XTL_EN ( BIT(17) ) +#define BIT_GGE_STC_TMR_AUTOPD_RF_EN ( BIT(16) ) +#define BIT_GGE_DSP_CORE_STOP ( BIT(15) ) +#define BIT_GGE_DSP_MTX_STOP ( BIT(14) ) +#define BIT_GGE_DSP_AHB_STOP ( BIT(13) ) +#define BIT_GGE_DSP_SYS_STOP ( BIT(12) ) +#define BIT_GGE_DSP_DEEP_STOP ( BIT(11) ) +#define BIT_GGE_ASHB_DSPTOARM_EN ( BIT(10) ) +#define BIT_GGE_ASHB_ARMTODSP_VALID ( BIT(9) ) +#define BIT_GGE_EMC_STOP_CH3 ( BIT(8) ) +#define BIT_GGE_EMC_STOP_CH4 ( BIT(7) ) +#define BIT_GGE_EMC_STOP_CH5 ( BIT(6) ) +#define BIT_GGE_FRC_WAKE_EN ( BIT(5) ) +#define BIT_GGE_TMR_WAKE_AFC ( BIT(4) ) +#define BIT_GGE_SCH_SLEEP ( BIT(3) ) +#define BIT_GGE_DSP_STOP ( BIT(2) ) +#define BIT_GGE_MCU_STOP ( BIT(1) ) +#define BIT_GGE_EMC_STOP ( BIT(0) ) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_djtag_apb_rf.h b/include/soc/sprd/chip_x35lt8/__regs_djtag_apb_rf.h new file mode 100644 index 00000000..862a626f --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_djtag_apb_rf.h @@ -0,0 +1,63 @@ +/* the head file modifier: g 2015-03-19 15:38:39*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_DJTAG_APB_RF_HEADFILE_H__ +#define __H_REGS_DJTAG_APB_RF_HEADFILE_H__ __FILE__ + +#define REGS_DJTAG_APB_RF + +/* registers definitions for DJTAG_APB_RF */ +#define REG_DJTAG_APB_RF_DJTAG_IR_LEN_CFG SCI_ADDR(REGS_DJTAG_APB_RF_BASE, 0x0000)/*DJTAG_IR_LEN_CFG*/ +#define REG_DJTAG_APB_RF_DJTAG_DR_LEN_CFG SCI_ADDR(REGS_DJTAG_APB_RF_BASE, 0x0004)/*DJTAG_DR_LEN_CFG*/ +#define REG_DJTAG_APB_RF_DJTAG_IR_CFG SCI_ADDR(REGS_DJTAG_APB_RF_BASE, 0x0008)/*DJTAG_IR_CFG*/ +#define REG_DJTAG_APB_RF_DJTAG_DR_CFG SCI_ADDR(REGS_DJTAG_APB_RF_BASE, 0x000C)/*DJTAG_DR_CFG*/ +#define REG_DJTAG_APB_RF_DR_PAUSE_RECOV_CFG SCI_ADDR(REGS_DJTAG_APB_RF_BASE, 0x0010)/*DR_PAUSE_RECOV_CFG*/ +#define REG_DJTAG_APB_RF_DJTAG_RND_EN_CFG SCI_ADDR(REGS_DJTAG_APB_RF_BASE, 0x0014)/*DJTAG_RND_EN_CFG*/ +#define REG_DJTAG_APB_RF_DJTAG_UPD_DR_CFG SCI_ADDR(REGS_DJTAG_APB_RF_BASE, 0x0018)/*DJTAG_UPD_DR_CFG*/ + + + +/* bits definitions for register REG_DJTAG_APB_RF_DJTAG_IR_LEN_CFG */ +#define BITS_IR_LEN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_DJTAG_APB_RF_DJTAG_DR_LEN_CFG */ +#define BITS_DR_LEN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_DJTAG_APB_RF_DJTAG_IR_CFG */ +#define BITS_DJTAG_IR(_X_) (_X_) + +/* bits definitions for register REG_DJTAG_APB_RF_DJTAG_DR_CFG */ +#define BITS_DJTAG_DR(_X_) (_X_) + +/* bits definitions for register REG_DJTAG_APB_RF_DR_PAUSE_RECOV_CFG */ +#define BIT_DR_PAUSE_RECOV ( BIT(0) ) + +/* bits definitions for register REG_DJTAG_APB_RF_DJTAG_RND_EN_CFG */ +#define BIT_DJTAG_RND_EN ( BIT(0) ) + +/* bits definitions for register REG_DJTAG_APB_RF_DJTAG_UPD_DR_CFG */ +#define BITS_DJTAG_UPD_DR(_X_) (_X_) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_gpu_apb_rf.h b/include/soc/sprd/chip_x35lt8/__regs_gpu_apb_rf.h new file mode 100644 index 00000000..5454b47a --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_gpu_apb_rf.h @@ -0,0 +1,48 @@ +/* the head file modifier: g 2015-03-19 15:47:17*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_GPU_APB_RF_HEADFILE_H__ +#define __H_REGS_GPU_APB_RF_HEADFILE_H__ __FILE__ + +#define REGS_GPU_APB_RF + +/* registers definitions for GPU_APB_RF */ +#define REG_GPU_APB_APB_RST SCI_ADDR(REGS_GPU_APB_BASE, 0x0000)/*APB_RST*/ +#define REG_GPU_APB_APB_CLK_CTRL SCI_ADDR(REGS_GPU_APB_BASE, 0x0004)/*APB_CLK_CTRL*/ +#define REG_GPU_APB_APB_BARRIER_CTRL SCI_ADDR(REGS_GPU_APB_BASE, 0x0008)/*APB_BARRIER_CTRL*/ + + + +/* bits definitions for register REG_GPU_APB_APB_RST */ +#define BIT_GPU_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_GPU_APB_APB_CLK_CTRL */ +#define BITS_CLK_GPU_DIV(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CLK_GPU_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_GPU_APB_APB_BARRIER_CTRL */ +#define BIT_GPU_BARRIER_DISABLE_EN ( BIT(0) ) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_lte_cevax_pmu.h b/include/soc/sprd/chip_x35lt8/__regs_lte_cevax_pmu.h new file mode 100644 index 00000000..4996d47e --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_lte_cevax_pmu.h @@ -0,0 +1,371 @@ +/* the head file modifier: g 2015-03-19 15:47:41*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_LTE_CEVAX_PMU_HEADFILE_H__ +#define __H_REGS_LTE_CEVAX_PMU_HEADFILE_H__ __FILE__ + +#define REGS_LTE_CEVAX_PMU + +/* registers definitions for LTE_CEVAX_PMU */ +#define REG_LTE_CEVAX_PMU_PLL_CFG0 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0000)/*PLL Config 0*/ +#define REG_LTE_CEVAX_PMU_PLL_CFG1 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0004)/*PLL Config 1*/ +#define REG_LTE_CEVAX_PMU_CXCLK_DIV SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0008)/*CX Clock Division*/ +#define REG_LTE_CEVAX_PMU_XHCLK_DIV SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x000C)/*XH Clock Division*/ +#define REG_LTE_CEVAX_PMU_XPCLK_DIV SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0010)/*XP Clock Division*/ +#define REG_LTE_CEVAX_PMU_CXPMOD SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0014)/*CX Power Mode*/ +#define REG_LTE_CEVAX_PMU_XHPMOD SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0018)/*XH Power Mode*/ +#define REG_LTE_CEVAX_PMU_XAPBMOD SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x001C)/*XP Power Mode*/ +#define REG_LTE_CEVAX_PMU_VERSION_CR SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0020)/*Version information*/ +#define REG_LTE_CEVAX_PMU_SLEEP_STATUS SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0024)/*Sleep Status*/ +#define REG_LTE_CEVAX_PMU_POW_CTL0 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0028)/*Power Control0*/ +#define REG_LTE_CEVAX_PMU_POW_CTL1 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x002C)/*Power Control1*/ +#define REG_LTE_CEVAX_PMU_POW_CTL2 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0030)/*Power Control2*/ +#define REG_LTE_CEVAX_PMU_ACCCLK_EN0 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0034)/*Accelerator Clock Enable0*/ +#define REG_LTE_CEVAX_PMU_ACCCLK_EN1 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0038)/*Accelerator Clock Enable1*/ +#define REG_LTE_CEVAX_PMU_ACCCLK_EN2 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x003C)/*Accelerator Clock Enable2*/ +#define REG_LTE_CEVAX_PMU_SOFT_RST0 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0040)/*SOFT_RST0*/ +#define REG_LTE_CEVAX_PMU_SOFT_RST1 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0044)/*SOFT_RST1*/ +#define REG_LTE_CEVAX_PMU_DSP_CKG_SEL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0048)/*DSP_CKG_SEL*/ +#define REG_LTE_CEVAX_PMU_CLK_DLCH_SEL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0050)/*CLK_DLCH_SEL*/ +#define REG_LTE_CEVAX_PMU_CLK_ULCH_SEL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0054)/*CLK_ULCH_SEL*/ +#define REG_LTE_CEVAX_PMU_CLK_RATEM_SEL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0058)/*CLK_RATEM_SEL*/ +#define REG_LTE_CEVAX_PMU_CLK_LTE_SPI_DIV_SEL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x005C)/*clk_lte_spi_div and clk_lte_spi_sel*/ +#define REG_LTE_CEVAX_PMU_CX_CKG_DIV SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0078)/*CX_CKG_DIV*/ +#define REG_LTE_CEVAX_PMU_XH_CKG_DIV SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x007C)/*XH_CKG_DIV*/ +#define REG_LTE_CEVAX_PMU_XP_CKG_DIV SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0080)/*XP_CKG_DIV*/ +#define REG_LTE_CEVAX_PMU_LTE_PMU_CKG_EN SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0084)/*CKG_EN*/ +#define REG_LTE_CEVAX_PMU_LTE_PMU_CLK_EN SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0088)/*LTE_PMU_CLK_EN*/ +#define REG_LTE_CEVAX_PMU_APB_CLK_SEL0 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x008C)/*APB_CLK_SEL0*/ +#define REG_LTE_CEVAX_PMU_APB_CLK_SEL1 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0090)/*APB_CLK_SEL1*/ +#define REG_LTE_CEVAX_PMU_CLK_CXTMR0_SEL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0094)/*CLK_CXTMR0_SEL*/ +#define REG_LTE_CEVAX_PMU_CLK_CXTMR1_SEL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0098)/*CLK_CXTMR1_SEL*/ +#define REG_LTE_CEVAX_PMU_CLK_CXTMR2_SEL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x009C)/*CLK_CXTMR2_SEL*/ +#define REG_LTE_CEVAX_PMU_APB_CLK_SEL2 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x00A0)/*APB_CLK_SEL2*/ +#define REG_LTE_CEVAX_PMU_MEM_LP_CTRL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0xA4)/*MEM_LP_CTRL*/ +#define REG_LTE_CEVAX_PMU_AXI_MON_CTRL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0xA8)/*AXI_MON_CTRL*/ +#define REG_LTE_CEVAX_PMU_RES_REG0 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0140)/*RES_REG0*/ +#define REG_LTE_CEVAX_PMU_RES_REG1 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0144)/*RES_REG1*/ +#define REG_LTE_CEVAX_PMU_RES_REG2 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0148)/*RES_REG2*/ + + + +/* bits definitions for register REG_LTE_CEVAX_PMU_PLL_CFG0 */ +#define BITS_PLL_CFG0_R(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_IIS3_EB ( BIT(10) ) +#define BIT_IIS2_EB ( BIT(9) ) +#define BIT_DSP_DLCH_EN ( BIT(8) ) +#define BIT_DSP_ULCH_EN ( BIT(7) ) +#define BIT_DLCH_AUTO_EN ( BIT(6) ) +#define BIT_ULCH_AUTO_EN ( BIT(5) ) +#define BIT_IIS1_EB ( BIT(4) ) +#define BIT_IIS0_EB ( BIT(3) ) +#define BIT_UART1_EB ( BIT(2) ) +#define BIT_UART0_EB ( BIT(1) ) +#define BIT_RFFE_EB ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_PLL_CFG1 */ +#define BIT_CHIP_SLP_REC_DSP ( BIT(16) ) +#define BIT_LTE_POW_OFF ( BIT(10) ) +#define BIT_LTE_POW_READY ( BIT(9) ) +#define BITS_LTE_POW_WAIT(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) ) +#define BIT_CHIP_SLP_DSP_CLR ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CXCLK_DIV */ +#define BITS_CXREG_AUTO_OFF(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_XHCLK_DIV */ +#define BIT_BUSMON2_CHN_SEL ( BIT(25) ) +#define BIT_BUSMON1_CHN_SEL ( BIT(24) ) +#define BIT_BUSMON0_CHN_SEL ( BIT(23) ) +#define BITS_DSP_SHM_CTRL(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BIT_DSPAPB_DES_AUTO_EN ( BIT(20) ) +#define BIT_DSPAHB_DES_AUTO_EN ( BIT(19) ) +#define BITS_LBUSMON2_CHN_SEL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_LBUSMON1_CHN_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_LBUSMON0_CHN_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_DSPAPB_DIV_DES(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DSPAHB_DIV_DES(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)) ) +#define BITS_CX_DSPPLL_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_XPCLK_DIV */ +#define BIT_PMU_DMA_FRC_EB ( BIT(24) ) +#define BIT_ZBUS_32ACCESS ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CXPMOD */ +#define BIT_MCU_FORCE_DEEP_SLEEP ( BIT(31) ) +#define BIT_LDSP_DEEP_SLP_CTRL ( BIT(30) ) +#define BIT_EMC_LIGHT_SLEEP_EN_M6 ( BIT(29) ) +#define BIT_EMC_DEEP_SLEEP_EN_M6 ( BIT(28) ) +#define BIT_EMC_LIGHT_SLEEP_EN_M7 ( BIT(27) ) +#define BIT_EMC_DEEP_SLEEP_EN_M7 ( BIT(26) ) +#define BIT_EMC_LIGHT_SLEEP_EN_M8 ( BIT(25) ) +#define BIT_EMC_DEEP_SLEEP_EN_M8 ( BIT(24) ) +#define BIT_LDSP2PUB_ACCESS_EN ( BIT(8) ) +#define BIT_LDSP_WAKEUP_XTL_EN ( BIT(7) ) +#define BIT_DMA_LSLP_EN ( BIT(4) ) +#define BIT_DSP_LIGHT_SLEEP_EN ( BIT(3) ) +#define BIT_DSP_DEEP_SLEEP_EN ( BIT(2) ) +#define BIT_DSP_SYS_SLEEP_EN ( BIT(1) ) +#define BIT_DSP_CORE_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_XHPMOD */ +#define BIT_BUSMON2_EB ( BIT(31) ) +#define BIT_BUSMON1_EB ( BIT(30) ) +#define BIT_BUSMON0_EB ( BIT(29) ) +#define BIT_LACCX_AUTO_GATE_EN ( BIT(14) ) +#define BIT_LDSPX_AUTO_GATE_EN ( BIT(13) ) +#define BIT_CXDMA_CLK_AUTO_EN ( BIT(12) ) +#define BIT_CXAPB_AUTO_GATE_EN ( BIT(11) ) +#define BIT_CXAHB_AUTO_GATE_EN ( BIT(10) ) +#define BIT_CXDSP_AUTO_GATE_EN ( BIT(9) ) +#define BIT_CXCORE_AUTO_GATE_EN ( BIT(8) ) +#define BIT_CXMTX_AUTO_GATE_EN ( BIT(7) ) +#define BIT_DSP_MAHB_SLEEP_EN ( BIT(6) ) +#define BIT_ACCZ_ARCH_EB ( BIT(5) ) +#define BIT_CXBUS_ARCH_EB ( BIT(4) ) +#define BIT_LTEPROC_ARCH_EB ( BIT(3) ) +#define BIT_PMU_DLCH_SLEEP_R ( BIT(1) ) +#define BIT_PMU_ULCH_SLEEP_R ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_XAPBMOD */ +#define BITS_HPROTDMAW(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_HPROTDMAR(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_PMU_XPSLEEP_P_R(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_VERSION_CR */ +#define BITS_VERSION_CR(_X_) (_X_) + +/* bits definitions for register REG_LTE_CEVAX_PMU_SLEEP_STATUS */ +#define BITS_PMU_SLEEP_STATUS(_X_) (_X_) + +/* bits definitions for register REG_LTE_CEVAX_PMU_POW_CTL0 */ +#define BITS_LTE_ISO_ON_NUM(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LTE_ISO_OFF_NUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_POW_CTL1 */ +#define BIT_CLK_PWR_LTE_SEL ( BIT(10) ) +#define BIT_LTE_SLP_POWOFF_AUTO_EN ( BIT(9) ) +#define BIT_LTE_POW_FORCE_PD ( BIT(8) ) +#define BITS_DSP_MEM_PD_REG(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_POW_CTL2 */ +#define BITS_DSP_MEM_PD_EN(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)) ) +#define BITS_PD_LTE_STATUS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_ACCCLK_EN0 */ +#define BIT_FFT_OFFLN_HCLKEN ( BIT(30) ) +#define BIT_FFT_OFFLN_CLKEN ( BIT(29) ) +#define BIT_FFT_ONLN_HCLKEN ( BIT(28) ) +#define BIT_FFT_ONLN_CLKEN ( BIT(27) ) +#define BIT_LTE_DRM_CLKEN ( BIT(24) ) +#define BIT_MIMO_HCLKEN ( BIT(23) ) +#define BIT_MIMO_CLKEN ( BIT(22) ) +#define BIT_PBCH_ACLKEN ( BIT(21) ) +#define BIT_PBCH_HCLKEN ( BIT(20) ) +#define BIT_PBCH_CLKEN ( BIT(19) ) +#define BIT_PCFICH_PHICH_HCLKEN ( BIT(18) ) +#define BIT_PCFICH_PHICH_CLKEN ( BIT(17) ) +#define BIT_PDCCH_ACLKEN ( BIT(16) ) +#define BIT_PDCCH_HCLKEN ( BIT(15) ) +#define BIT_PDCCH_CLKEN ( BIT(14) ) +#define BIT_PDSCH_TB_CTL_HCLKEN ( BIT(13) ) +#define BIT_PDSCH_TB_CTL_CLKEN ( BIT(12) ) +#define BIT_RXDFE_HCLKEN ( BIT(11) ) +#define BIT_SYNC_ACLKEN ( BIT(10) ) +#define BIT_SYNC_HCLKEN ( BIT(9) ) +#define BIT_SYNC_CLKEN ( BIT(8) ) +#define BIT_TBUF_ACLKEN ( BIT(7) ) +#define BIT_TBUF_HCLKEN ( BIT(6) ) +#define BIT_TBUF_CLKEN ( BIT(5) ) +#define BIT_VTB_CLKEN ( BIT(4) ) +#define BIT_LTE_PROC_HCLKEN ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_ACCCLK_EN1 */ +#define BIT_LBUSMON2_EB ( BIT(28) ) +#define BIT_LBUSMON1_EB ( BIT(27) ) +#define BIT_LBUSMON0_EB ( BIT(26) ) +#define BIT_HSDL_CLKEN ( BIT(25) ) +#define BIT_ULMAC_HCLKEN ( BIT(24) ) +#define BIT_TBE_HCLKEN ( BIT(23) ) +#define BIT_TBE_CLKEN ( BIT(22) ) +#define BIT_RM_HCLKEN ( BIT(21) ) +#define BIT_RM_CLKEN ( BIT(20) ) +#define BIT_PCM_HCLKEN ( BIT(19) ) +#define BIT_PCM_CLKEN ( BIT(18) ) +#define BIT_UCM_HCLKEN ( BIT(17) ) +#define BIT_UCM_CLKEN ( BIT(16) ) +#define BIT_CHE_ACLKEN ( BIT(15) ) +#define BIT_CHE_HCLKEN ( BIT(14) ) +#define BIT_CHE_SYS_CLKEN ( BIT(13) ) +#define BIT_CHEPP_ACLKEN ( BIT(12) ) +#define BIT_CHEPP_HCLKEN ( BIT(11) ) +#define BIT_CHEPP_SYS_CLKEN ( BIT(10) ) +#define BIT_DBUF_ACLKEN ( BIT(9) ) +#define BIT_DBUF_HCLKEN ( BIT(8) ) +#define BIT_DBUF_CLKEN ( BIT(7) ) +#define BIT_DFE_CLKEN ( BIT(6) ) +#define BIT_FBUF_ACLKEN ( BIT(5) ) +#define BIT_FBUF_HCLKEN ( BIT(4) ) +#define BIT_FBUF_CLKEN ( BIT(3) ) +#define BIT_FEC_ACLKEN ( BIT(2) ) +#define BIT_FEC_HCLKEN ( BIT(1) ) +#define BIT_FEC_CLKEN ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_ACCCLK_EN2 */ + +/* bits definitions for register REG_LTE_CEVAX_PMU_SOFT_RST0 */ +#define BITS_SOFT_RST_R(_X_) (_X_) + +/* bits definitions for register REG_LTE_CEVAX_PMU_SOFT_RST1 */ +#define BIT_LTE_PROC_SOFT_RST_RFT ( BIT(31) ) +#define BIT_HSDL_SOFT_RST ( BIT(30) ) +#define BIT_RFSPI_SOFT_RST ( BIT(29) ) +#define BIT_LTE_PROC_SOFT_RST ( BIT(28) ) +#define BIT_ULMAC_SOFT_RST ( BIT(27) ) +#define BIT_PCM_SOFT_RST ( BIT(26) ) +#define BIT_UCM_SOFT_RST ( BIT(25) ) +#define BIT_TBE_SOFT_RST ( BIT(24) ) +#define BIT_RM_SOFT_RST ( BIT(23) ) +#define BIT_RFT_SOFT_RST ( BIT(22) ) +#define BIT_DFE_SOFT_RST ( BIT(21) ) +#define BIT_MIMO_SOFT_RST ( BIT(20) ) +#define BIT_ON_LINE_FFT_SOFT_RST ( BIT(19) ) +#define BIT_OFF_LINE_FFT_SOFT_RST ( BIT(18) ) +#define BIT_PCFICH_SOFT_RST ( BIT(17) ) +#define BIT_PDSCH_SOFT_RST ( BIT(16) ) +#define BIT_DRM_SOFT_RST ( BIT(15) ) +#define BIT_VTB_SOFT_RST ( BIT(14) ) +#define BIT_FEC_SOFT_RST ( BIT(13) ) +#define BIT_CHE_SOFT_RST ( BIT(12) ) +#define BIT_CHEPP_SOFT_RST ( BIT(11) ) +#define BIT_SYNC_SOFT_RST ( BIT(10) ) +#define BIT_TBUF_SOFT_RST ( BIT(9) ) +#define BIT_DBUF_SOFT_RST ( BIT(8) ) +#define BIT_FBUF_SOFT_RST ( BIT(7) ) +#define BIT_PDCCH_SOFT_RST ( BIT(6) ) +#define BIT_PBCH_SOFT_RST ( BIT(5) ) +#define BIT_RXADC_SOFT_RST ( BIT(4) ) +#define BIT_TXDAC_SOFT_RST ( BIT(3) ) +#define BIT_CAL_SOFT_RST ( BIT(2) ) +#define BIT_RTC_SOFT_RST ( BIT(1) ) +#define BIT_LTE_SPI_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_DSP_CKG_SEL */ +#define BITS_DSP_CKG_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CLK_DLCH_SEL */ +#define BITS_CLK_DLCH_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CLK_ULCH_SEL */ +#define BITS_CLK_ULCH_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CLK_RATEM_SEL */ +#define BITS_CLK_RATEM_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CLK_LTE_SPI_DIV_SEL */ +#define BITS_CLK_LTE_SPI_DIV(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)) ) +#define BITS_CLK_LTE_SPI_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CX_CKG_DIV */ +#define BITS_CX_CKG_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_XH_CKG_DIV */ +#define BITS_XH_CKG_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_XP_CKG_DIV */ +#define BITS_XP_CKG_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_LTE_PMU_CKG_EN */ +#define BIT_DSP_CKG_EN ( BIT(8) ) +#define BIT_CX_CKG_EN ( BIT(6) ) +#define BIT_XH_CKG_EN ( BIT(5) ) +#define BIT_XP_CKG_EN ( BIT(4) ) +#define BIT_DMA_CKG_EN ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_LTE_PMU_CLK_EN */ +#define BIT_CLK_LTE_SA_EN ( BIT(17) ) +#define BIT_CLK_CXTMR2_EN ( BIT(16) ) +#define BIT_CLK_CXTMR1_EN ( BIT(15) ) +#define BIT_CLK_CXTMR0_EN ( BIT(14) ) +#define BIT_CLK_AXI_EN ( BIT(13) ) +#define BIT_CLK_AHB_EN ( BIT(12) ) +#define BIT_CLK_DFE_EN ( BIT(11) ) +#define BIT_CLK_RFT_EN ( BIT(10) ) +#define BIT_CLK_DLCH_EN ( BIT(9) ) +#define BIT_CLK_ULCH_EN ( BIT(8) ) +#define BIT_CLK_RATEM_EN ( BIT(7) ) +#define BIT_CLK_RXADC_EN ( BIT(6) ) +#define BIT_CLK_TXDAC_EN ( BIT(5) ) +#define BIT_CLK_LTE_ANA_2X_EN ( BIT(4) ) +#define BIT_CLK_LTE_ANA_1X_EN ( BIT(3) ) +#define BIT_CLK_CAL_EN ( BIT(2) ) +#define BIT_CLK_RTC_EN ( BIT(1) ) +#define BIT_CLK_LTE_SPI_EN ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_APB_CLK_SEL0 */ +#define BITS_CLK_UART1_DIV(_X_) ( (_X_) << 7 & (BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_CLK_UART1_SEL(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)) ) +#define BITS_CLK_UART0_DIV(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)) ) +#define BITS_CLK_UART0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_APB_CLK_SEL1 */ +#define BITS_CLK_IIS1_DIV(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_CLK_IIS1_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_CLK_IIS0_DIV(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_CLK_IIS0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CLK_CXTMR0_SEL */ +#define BITS_CLK_CXTMR0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CLK_CXTMR1_SEL */ +#define BITS_CLK_CXTMR1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CLK_CXTMR2_SEL */ +#define BITS_CLK_CXTMR2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_APB_CLK_SEL2 */ +#define BITS_CLK_IIS3_DIV(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_CLK_IIS3_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_CLK_IIS2_DIV(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_CLK_IIS2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_MEM_LP_CTRL */ +#define BITS_MEM_LP_CTRL(_X_) (_X_) + +/* bits definitions for register REG_LTE_CEVAX_PMU_AXI_MON_CTRL */ +#define BIT_AXI_MON_WAIT_EB ( BIT(21) ) +#define BIT_AXI_MON_CLKEN_EB ( BIT(20) ) +#define BITS_AXI_MONITOR_STATUS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_RES_REG0 */ +#define BITS_RES_REG0(_X_) (_X_) + +/* bits definitions for register REG_LTE_CEVAX_PMU_RES_REG1 */ +#define BITS_RES_REG1(_X_) (_X_) + +/* bits definitions for register REG_LTE_CEVAX_PMU_RES_REG2 */ +#define BITS_RES_REG2(_X_) (_X_) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_mdar_apb_rf.h b/include/soc/sprd/chip_x35lt8/__regs_mdar_apb_rf.h new file mode 100644 index 00000000..2828f484 --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_mdar_apb_rf.h @@ -0,0 +1,1183 @@ +/* the head file modifier: g 2015-03-19 17:11:33*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_MDAR_APB_RF_HEADFILE_H__ +#define __H_REGS_MDAR_APB_RF_HEADFILE_H__ __FILE__ + +#define REGS_MDAR_APB_RF + +/* registers definitions for MDAR_APB_RF */ +#define REG_MDAR_APB_RF_MDAR_CFG0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0000)/*MDAR configuration set 0*/ +#define REG_MDAR_APB_RF_MDAR_CFG1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0004)/*MDAR configuration set 1*/ +#define REG_MDAR_APB_RF_MDAR_CFG3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x000C)/*MDAR configuration set 3*/ +#define REG_MDAR_APB_RF_MDAR_DAC1_CTR1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0010)/*DAC1 control1*/ +#define REG_MDAR_APB_RF_MDAR_DAC1_CTR2 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0014)/*DAC1 control2*/ +#define REG_MDAR_APB_RF_MDAR_DAC1_CTR3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0018)/*DAC1control3*/ +#define REG_MDAR_APB_RF_MDAR_DAC1_CTR4 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x001C)/*DAC1 control4*/ +#define REG_MDAR_APB_RF_MDAR_DAC1_STS0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0020)/*DAC1 status0*/ +#define REG_MDAR_APB_RF_MDAR_DAC1_STS1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0024)/*DAC1 status1*/ +#define REG_MDAR_APB_RF_MDAR_CAL1_CTR0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0028)/*Calibration1 Control 0*/ +#define REG_MDAR_APB_RF_MDAR_CAL1_CTR1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x002C)/*Calibration1 Control 1*/ +#define REG_MDAR_APB_RF_MDAR_CAL1_CTR3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0030)/*Calibration1 Control 3*/ +#define REG_MDAR_APB_RF_MDAR_CAL1_STS0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0034)/*Calibration1 Status 0*/ +#define REG_MDAR_APB_RF_MDAR_CAL1_STS1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0038)/*Calibration1 Status 1*/ +#define REG_MDAR_APB_RF_MDAR_DAC1_CTR00 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x003C)/*DAC1 control00*/ +#define REG_MDAR_APB_RF_MDAR_DAC1_CTR10 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0040)/*DAC1 control10*/ +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0044)/*ADC1 control0*/ +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR00 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0048)/*ADC1 control00*/ +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR01 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x004C)/*ADC1 control01*/ +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR02 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0050)/*ADC1 control02*/ +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR10 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0054)/*ADC1 control10*/ +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR11 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0058)/*ADC1 control11*/ +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR12 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x005C)/*ADC1 control12*/ +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR20 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0060)/*ADC1 control20*/ +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR21 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0064)/*ADC1 control21*/ +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR22 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0068)/*ADC1 control22*/ +#define REG_MDAR_APB_RF_MDAR_DAC2_CTR1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0070)/*DAC2 control1*/ +#define REG_MDAR_APB_RF_MDAR_DAC2_CTR2 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0074)/*DAC2 control2*/ +#define REG_MDAR_APB_RF_MDAR_DAC2_CTR3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0078)/*DAC2control3*/ +#define REG_MDAR_APB_RF_MDAR_DAC2_CTR4 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x007C)/*DAC2 control4*/ +#define REG_MDAR_APB_RF_MDAR_DAC2_STS0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0080)/*DAC2 status0*/ +#define REG_MDAR_APB_RF_MDAR_DAC2_STS1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0084)/*DAC2 status1*/ +#define REG_MDAR_APB_RF_MDAR_CAL2_CTR0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0088)/*Calibration2 Control 0*/ +#define REG_MDAR_APB_RF_MDAR_CAL2_CTR1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x008C)/*Calibration2 Control 1*/ +#define REG_MDAR_APB_RF_MDAR_CAL2_CTR3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0090)/*Calibration2 Control 3*/ +#define REG_MDAR_APB_RF_MDAR_CAL2_STS0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0094)/*Calibration2 Status 0*/ +#define REG_MDAR_APB_RF_MDAR_CAL2_STS1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0098)/*Calibration2 Status 1*/ +#define REG_MDAR_APB_RF_MDAR_DAC2_CTR00 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x009C)/*DAC2 control00*/ +#define REG_MDAR_APB_RF_MDAR_DAC2_CTR10 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00A0)/*DAC2 control10*/ +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00A4)/*ADC2 control0*/ +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR00 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00A8)/*ADC2 control00*/ +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR01 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00AC)/*ADC2 control01*/ +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR02 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00B0)/*ADC2 control02*/ +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR10 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00B4)/*ADC2 control10*/ +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR11 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00B8)/*ADC2 control11*/ +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR12 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00BC)/*ADC2 control12*/ +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR20 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00C0)/*ADC2 control20*/ +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR21 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00C4)/*ADC2 control21*/ +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR22 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00C8)/*ADC2 control22*/ +#define REG_MDAR_APB_RF_MDAR_DAC3_CTR1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00D0)/*DAC3 control1*/ +#define REG_MDAR_APB_RF_MDAR_DAC3_CTR2 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00D4)/*DAC3 control2*/ +#define REG_MDAR_APB_RF_MDAR_DAC3_CTR3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00D8)/*DAC3control3*/ +#define REG_MDAR_APB_RF_MDAR_DAC3_CTR4 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00DC)/*DAC3 control4*/ +#define REG_MDAR_APB_RF_MDAR_DAC3_STS0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00E0)/*DAC3 status0*/ +#define REG_MDAR_APB_RF_MDAR_DAC3_STS1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00E4)/*DAC3 status1*/ +#define REG_MDAR_APB_RF_MDAR_CAL3_CTR0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00E8)/*Calibration3 Control 0*/ +#define REG_MDAR_APB_RF_MDAR_CAL3_CTR1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00EC)/*Calibration3 Control 1*/ +#define REG_MDAR_APB_RF_MDAR_CAL3_CTR3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00F0)/*Calibration3 Control 3*/ +#define REG_MDAR_APB_RF_MDAR_CAL3_STS0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00F4)/*Calibration3 Status 0*/ +#define REG_MDAR_APB_RF_MDAR_CAL3_STS1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00F8)/*Calibration3 Status 1*/ +#define REG_MDAR_APB_RF_MDAR_DAC3_CTR00 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00FC)/*DAC3 control00*/ +#define REG_MDAR_APB_RF_MDAR_DAC3_CTR10 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0100)/*DAC3 control10*/ +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0104)/*ADC3 control0*/ +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR00 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0108)/*ADC3 control00*/ +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR01 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x010C)/*ADC3 control01*/ +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR02 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0110)/*ADC3 control02*/ +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR10 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0114)/*ADC3 control10*/ +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR11 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0118)/*ADC3 control11*/ +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR12 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x011C)/*ADC3 control12*/ +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR20 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0120)/*ADC3 control20*/ +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR21 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0124)/*ADC3 control21*/ +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR22 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0128)/*ADC3 control22*/ +#define REG_MDAR_APB_RF_MDAR_AFCDAC1_CFG SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x012C)/*AFCDAC1 configuration register*/ +#define REG_MDAR_APB_RF_MDAR_AFCDAC2_CFG SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0130)/*AFCDAC2 configuration register*/ +#define REG_MDAR_APB_RF_MDAR_APCDAC1_CFG SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0134)/*APCDAC1 configuration register*/ +#define REG_MDAR_APB_RF_MDAR_APCDAC2_CFG SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0138)/*APCDAC2 configuration register*/ +#define REG_MDAR_APB_RF_MDAR_RFSPI_CFG SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x13C)/*RFSPI configuration register*/ +#define REG_MDAR_APB_RF_MDAR_RFMIPI_CFG SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x140)/*RFMIPI configuration register*/ +#define REG_MDAR_APB_RF_MDAR_APCDAC_OUTSEL SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x144)/*Multi-mode APC_OUT_SEL configuration register*/ +#define REG_MDAR_APB_RF_MDAR_CLASH_CHK SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x148)/*Multi-mode clash operation set register*/ +#define REG_MDAR_APB_RF_MDAR_CLASH_SNAP SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x14C)/*Multi-mode clash operation snap timer*/ +#define REG_MDAR_APB_RF_MDAR_CLASH_STATUS1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x150)/*Multi-mode clash detail information rgister1*/ +#define REG_MDAR_APB_RF_MDAR_CLASH_STATUS2 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x154)/*Multi-mode clash detail information rgister2*/ +#define REG_MDAR_APB_RF_MDAR_CLASH_STATUS3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x158)/*Multi-mode clash detail information rgister3*/ +#define REG_MDAR_APB_RF_MDAR_EXTRA_CFG0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x160)/*mdar extra cfg0*/ +#define REG_MDAR_APB_RF_MDAR_EXTRA_CFG1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x164)/*mdar extra cfg1*/ +#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x168)/*mdar_rfctrl15_inf0*/ +#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x16C)/*mdar_rfctrl15_inf*/ +#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF2 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x170)/*mdar_rfctrl15_inf*/ +#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x174)/*mdar_rfctrl15_inf*/ +#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF4 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x178)/*mdar_rfctrl15_inf*/ +#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF5 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x17C)/*mdar_rfctrl15_inf*/ +#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF6 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x180)/*mdar_rfctrl15_inf*/ +#define REG_MDAR_APB_RF_MDAR_CFG4 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0184)/*MDAR configuration set 4*/ +#define REG_MDAR_APB_RF_MDAR_CFG5 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0188)/*MDAR configuration set 5*/ +#define REG_MDAR_APB_RF_MDAR_CFG6 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x018C)/*MDAR configuration set 6*/ +#define REG_MDAR_APB_RF_MDAR_CFG7 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0190)/*MDAR configuration set 7*/ +#define REG_MDAR_APB_RF_MDAR_CFG8 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0194)/*MDAR configuration set 8*/ +#define REG_MDAR_APB_RF_MDAR_CFG9 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0198)/*MDAR configuration set 9*/ +#define REG_MDAR_APB_RF_MDAR_CFG10 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x019C)/*MDAR configuration set 10*/ +#define REG_MDAR_APB_RF_MDAR_CFG11 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x01B0)/*MDAR configuration set 11*/ +#define REG_MDAR_APB_RF_MDAR_CFG12 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x01B4)/*MDAR configuration set 12*/ +#define REG_MDAR_APB_RF_MDAR_CFG13 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x01B8)/*MDAR configuration set 13*/ +#define REG_MDAR_APB_RF_MDAR_CFG14 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x01BC)/*MDAR configuration set 14*/ +#define REG_MDAR_APB_RF_MDAR_CFG15 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1C0)/*MDAR configuration set15*/ +#define REG_MDAR_APB_RF_MDAR_IMB_CFG10 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1C4)/*MDAR IQ Imblace process set10*/ +#define REG_MDAR_APB_RF_MDAR_IMB_CFG11 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1C8)/*MDAR IQ Imblace process set11*/ +#define REG_MDAR_APB_RF_MDAR_IMB_CFG12 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1CC)/*MDAR IQ Imblace process set12*/ +#define REG_MDAR_APB_RF_MDAR_IMB_CFG13 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1D0)/*MDAR IQ Imblace process set13*/ +#define REG_MDAR_APB_RF_MDAR_IMB_CFG14 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1D4)/*MDAR IQ Imblace process set14*/ +#define REG_MDAR_APB_RF_MDAR_IMB_CFG20 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1D8)/*MDAR IQ Imblace process set20*/ +#define REG_MDAR_APB_RF_MDAR_IMB_CFG21 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1DC)/*MDAR IQ Imblace process set21*/ +#define REG_MDAR_APB_RF_MDAR_IMB_CFG22 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1E0)/*MDAR IQ Imblace process set22*/ +#define REG_MDAR_APB_RF_MDAR_IMB_CFG23 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1E4)/*MDAR IQ Imblace process set23*/ +#define REG_MDAR_APB_RF_MDAR_IMB_CFG24 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1E8)/*MDAR IQ Imblace process set24*/ +#define REG_MDAR_APB_RF_MDAR_IMB_CFG30 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1EC)/*MDAR IQ Imblace process set30*/ +#define REG_MDAR_APB_RF_MDAR_IMB_CFG31 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1F0)/*MDAR IQ Imblace process set31*/ +#define REG_MDAR_APB_RF_MDAR_IMB_CFG32 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1F4)/*MDAR IQ Imblace process set32*/ +#define REG_MDAR_APB_RF_MDAR_IMB_CFG33 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1F8)/*MDAR IQ Imblace process set33*/ +#define REG_MDAR_APB_RF_MDAR_IMB_CFG34 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1FC)/*MDAR IQ Imblace process set34*/ + + + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG0 */ +#define BIT_MDAR_ADA_MODE ( BIT(31) ) +#define BITS_ADC3_CHANNEL_SSET(_X_) ( (_X_) << 26 & (BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_ADC2_CHANNEL_SSET(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_ADC1_CHANNEL_SSET(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)) ) +#define BIT_MDAR_WTG_MODE ( BIT(15) ) +#define BITS_ADC3_CHANNEL_MASK(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_ADC2_CHANNEL_MASK(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_ADC1_CHANNEL_MASK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG1 */ +#define BITS_DAC3_CHANNEL_SSET(_X_) ( (_X_) << 26 & (BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_DAC2_CHANNEL_SSET(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC1_CHANNEL_SSET(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_DAC3_CHANNEL_MASK(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_DAC2_CHANNEL_MASK(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DAC1_CHANNEL_MASK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG3 */ +#define BITS_DACX_SBC_SET(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_ADCX_SBC_SET(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_CTR1 */ +#define BITS_DAC1_WD_OVR(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DAC1_WADDR_OVR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DAC1_WLE_OVR ( BIT(2) ) +#define BIT_DAC1_W_OVR_I_QN ( BIT(1) ) +#define BIT_DAC1_W_OVR_EN ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_CTR2 */ +#define BIT_DAC1_AUTO_RST ( BIT(23) ) +#define BIT_DAC1_SOFT_RST ( BIT(22) ) +#define BIT_DAC1_OSBC ( BIT(21) ) +#define BIT_DAC1_ISBC ( BIT(20) ) +#define BIT_DAC1_OVR_EN_CAL ( BIT(19) ) +#define BIT_DAC1_EN_OOSCAL ( BIT(18) ) +#define BIT_DAC1_IQSWAP ( BIT(17) ) +#define BIT_DAC1_CAL_START ( BIT(16) ) +#define BITS_DAC1_OFFSETI(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DAC1_OFFSETQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_CTR3 */ +#define BITS_DAC1_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DAC1_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_CTR4 */ +#define BITS_DAC1_I_CAL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DAC1_Q_CAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_STS0 */ +#define BITS_DAC1_WTI(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DAC1_WTQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_STS1 */ +#define BITS_DAC1_DA_STATE(_X_) ( (_X_) << 17 & (BIT(17)|BIT(18)) ) +#define BIT_DAC1_DONE ( BIT(16) ) +#define BITS_DAC1_WQ_OVR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL1_CTR0 */ +#define BITS_ADC1_CLK_CAL_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_ADA1_CAL_WAIT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_CLK_ADA1_CAL_EN ( BIT(6) ) +#define BIT_DAC1_PD_CAL ( BIT(5) ) +#define BIT_ADC1_EN_CAL ( BIT(3) ) +#define BIT_ADC1_CAL ( BIT(1) ) +#define BIT_ADA1_MODE_SEL ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL1_CTR1 */ +#define BITS_ADC1_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) ) +#define BITS_ADC1_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL1_CTR3 */ +#define BIT_ADA1_CAL_START ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL1_STS0 */ +#define BIT_ADA1_CAL_DONE ( BIT(31) ) +#define BITS_ADC1_CAL_I_SUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL1_STS1 */ +#define BITS_ADC1_CAL_Q_SUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_CTR00 */ +#define BIT_DAC1_OUT_SEL_2 ( BIT(26) ) +#define BITS_DAC1_RSV_2(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC1_PCTRL_2(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)) ) +#define BIT_DAC1_CLK_SEL_2 ( BIT(18) ) +#define BIT_DAC1_OUT_SEL_1 ( BIT(17) ) +#define BITS_DAC1_RSV_1(_X_) ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)) ) +#define BITS_DAC1_PCTRL_1(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DAC1_CLK_SEL_1 ( BIT(9) ) +#define BIT_DAC1_OUT_SEL_0 ( BIT(8) ) +#define BITS_DAC1_RSV_0(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DAC1_PCTRL_0(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)) ) +#define BIT_DAC1_CLK_SEL_0 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_CTR10 */ +#define BIT_DAC1_OUT_SEL_5 ( BIT(26) ) +#define BITS_DAC1_RSV_5(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC1_PCTRL_5(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)) ) +#define BIT_DAC1_CLK_SEL_5 ( BIT(18) ) +#define BIT_DAC1_OUT_SEL_4 ( BIT(17) ) +#define BITS_DAC1_RSV_4(_X_) ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)) ) +#define BITS_DAC1_PCTRL_4(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DAC1_CLK_SEL_4 ( BIT(9) ) +#define BIT_DAC1_OUT_SEL_3 ( BIT(8) ) +#define BITS_DAC1_RSV_3(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DAC1_PCTRL_3(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)) ) +#define BIT_DAC1_CLK_SEL_3 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR0 */ +#define BIT_ADC1_SOFT_RST ( BIT(31) ) +#define BITS_ADC1_DLL_OUT(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_ADC1_CALRDOUT(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) ) +#define BIT_ADC1_DLL_SOFT_RST ( BIT(10) ) +#define BIT_ADC1_CAL_SOFT_RST ( BIT(9) ) +#define BIT_ADC1_CALRD ( BIT(8) ) +#define BIT_ADC1_CALEN ( BIT(7) ) +#define BITS_ADC1_CALADDR(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_ADC1_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR00 */ +#define BITS_ADC1_RSV_1(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC1_RSV_0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR01 */ +#define BIT_ADC1_DIG_CLK_SEL_0 ( BIT(30) ) +#define BIT_ADC1_VCM_SEL_0 ( BIT(29) ) +#define BITS_ADC1_DELAY_CAP_0(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC1_BIT_SEL_0(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC1_VREF_SEL_0(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC1_VREF_BOOST_0(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC1_QUANT_BOOST_0(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC1_DLLRD_0 ( BIT(18) ) +#define BIT_ADC1_DLLWR_0 ( BIT(17) ) +#define BIT_ADC1_DLLEN_0 ( BIT(16) ) +#define BIT_ADC1_CSBC ( BIT(15) ) +#define BIT_ADC1_IQSWAP ( BIT(14) ) +#define BITS_ADC1_DLLOOF_0(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_ADC1_OSBC ( BIT(7) ) +#define BIT_ADC1_ISBC ( BIT(6) ) +#define BITS_ADC1_DLLIN_0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR02 */ +#define BIT_ADC1_DIG_CLK_SEL_1 ( BIT(30) ) +#define BIT_ADC1_VCM_SEL_1 ( BIT(29) ) +#define BITS_ADC1_DELAY_CAP_1(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC1_BIT_SEL_1(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC1_VREF_SEL_1(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC1_VREF_BOOST_1(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC1_QUANT_BOOST_1(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC1_DLLRD_1 ( BIT(18) ) +#define BIT_ADC1_DLLWR_1 ( BIT(17) ) +#define BIT_ADC1_DLLEN_1 ( BIT(16) ) +#define BITS_ADC1_DLLOOF_1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC1_DLLIN_1(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR10 */ +#define BITS_ADC1_RSV_3(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC1_RSV_2(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR11 */ +#define BIT_ADC1_DIG_CLK_SEL_2 ( BIT(30) ) +#define BIT_ADC1_VCM_SEL_2 ( BIT(29) ) +#define BITS_ADC1_DELAY_CAP_2(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC1_BIT_SEL_2(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC1_VREF_SEL_2(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC1_VREF_BOOST_2(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC1_QUANT_BOOST_2(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC1_DLLRD_2 ( BIT(18) ) +#define BIT_ADC1_DLLWR_2 ( BIT(17) ) +#define BIT_ADC1_DLLEN_2 ( BIT(16) ) +#define BITS_ADC1_DLLOOF_2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC1_DLLIN_2(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR12 */ +#define BIT_ADC1_DIG_CLK_SEL_3 ( BIT(30) ) +#define BIT_ADC1_VCM_SEL_3 ( BIT(29) ) +#define BITS_ADC1_DELAY_CAP_3(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC1_BIT_SEL_3(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC1_VREF_SEL_3(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC1_VREF_BOOST_3(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC1_QUANT_BOOST_3(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC1_DLLRD_3 ( BIT(18) ) +#define BIT_ADC1_DLLWR_3 ( BIT(17) ) +#define BIT_ADC1_DLLEN_3 ( BIT(16) ) +#define BITS_ADC1_DLLOOF_3(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC1_DLLIN_3(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR20 */ +#define BITS_ADC1_RSV_5(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC1_RSV_4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR21 */ +#define BIT_ADC1_DIG_CLK_SEL_4 ( BIT(30) ) +#define BIT_ADC1_VCM_SEL_4 ( BIT(29) ) +#define BITS_ADC1_DELAY_CAP_4(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC1_BIT_SEL_4(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC1_VREF_SEL_4(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC1_VREF_BOOST_4(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC1_QUANT_BOOST_4(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC1_DLLRD_4 ( BIT(18) ) +#define BIT_ADC1_DLLWR_4 ( BIT(17) ) +#define BIT_ADC1_DLLEN_4 ( BIT(16) ) +#define BITS_ADC1_DLLOOF_4(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC1_DLLIN_4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR22 */ +#define BIT_ADC1_DIG_CLK_SEL_5 ( BIT(30) ) +#define BIT_ADC1_VCM_SEL_5 ( BIT(29) ) +#define BITS_ADC1_DELAY_CAP_5(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC1_BIT_SEL_5(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC1_VREF_SEL_5(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC1_VREF_BOOST_5(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC1_QUANT_BOOST_5(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC1_DLLRD_5 ( BIT(18) ) +#define BIT_ADC1_DLLWR_5 ( BIT(17) ) +#define BIT_ADC1_DLLEN_5 ( BIT(16) ) +#define BITS_ADC1_DLLOOF_5(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC1_DLLIN_5(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_CTR1 */ +#define BITS_DAC2_WD_OVR(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DAC2_WADDR_OVR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DAC2_WLE_OVR ( BIT(2) ) +#define BIT_DAC2_W_OVR_I_QN ( BIT(1) ) +#define BIT_DAC2_W_OVR_EN ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_CTR2 */ +#define BIT_DAC2_AUTO_RST ( BIT(23) ) +#define BIT_DAC2_SOFT_RST ( BIT(22) ) +#define BIT_DAC2_OSBC ( BIT(21) ) +#define BIT_DAC2_ISBC ( BIT(20) ) +#define BIT_DAC2_OVR_EN_CAL ( BIT(19) ) +#define BIT_DAC2_EN_OOSCAL ( BIT(18) ) +#define BIT_DAC2_IQSWAP ( BIT(17) ) +#define BIT_DAC2_CAL_START ( BIT(16) ) +#define BITS_DAC2_OFFSETI(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DAC2_OFFSETQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_CTR3 */ +#define BITS_DAC2_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DAC2_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_CTR4 */ +#define BITS_DAC2_I_CAL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DAC2_Q_CAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_STS0 */ +#define BITS_DAC2_WTI(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DAC2_WTQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_STS1 */ +#define BITS_DAC2_DA_STATE(_X_) ( (_X_) << 17 & (BIT(17)|BIT(18)) ) +#define BIT_DAC2_DONE ( BIT(16) ) +#define BITS_DAC2_WQ_OVR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL2_CTR0 */ +#define BITS_ADC2_CLK_CAL_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_ADA2_CAL_WAIT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_CLK_ADA2_CAL_EN ( BIT(6) ) +#define BIT_DAC2_PD_CAL ( BIT(5) ) +#define BIT_ADC2_EN_CAL ( BIT(3) ) +#define BIT_ADC2_CAL ( BIT(1) ) +#define BIT_ADA2_MODE_SEL ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL2_CTR1 */ +#define BITS_ADC2_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) ) +#define BITS_ADC2_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL2_CTR3 */ +#define BIT_ADA2_CAL_START ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL2_STS0 */ +#define BIT_ADA2_CAL_DONE ( BIT(31) ) +#define BITS_ADC2_CAL_I_SUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL2_STS1 */ +#define BITS_ADC2_CAL_Q_SUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_CTR00 */ +#define BIT_DAC2_OUT_SEL_2 ( BIT(26) ) +#define BITS_DAC2_RSV_2(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC2_PCTRL_2(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)) ) +#define BIT_DAC2_CLK_SEL_2 ( BIT(18) ) +#define BIT_DAC2_OUT_SEL_1 ( BIT(17) ) +#define BITS_DAC2_RSV_1(_X_) ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)) ) +#define BITS_DAC2_PCTRL_1(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DAC2_CLK_SEL_1 ( BIT(9) ) +#define BIT_DAC2_OUT_SEL_0 ( BIT(8) ) +#define BITS_DAC2_RSV_0(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DAC2_PCTRL_0(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)) ) +#define BIT_DAC2_CLK_SEL_0 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_CTR10 */ +#define BIT_DAC2_OUT_SEL_5 ( BIT(26) ) +#define BITS_DAC2_RSV_5(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC2_PCTRL_5(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)) ) +#define BIT_DAC2_CLK_SEL_5 ( BIT(18) ) +#define BIT_DAC2_OUT_SEL_4 ( BIT(17) ) +#define BITS_DAC2_RSV_4(_X_) ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)) ) +#define BITS_DAC2_PCTRL_4(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DAC2_CLK_SEL_4 ( BIT(9) ) +#define BIT_DAC2_OUT_SEL_3 ( BIT(8) ) +#define BITS_DAC2_RSV_3(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DAC2_PCTRL_3(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)) ) +#define BIT_DAC2_CLK_SEL_3 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR0 */ +#define BIT_ADC2_SOFT_RST ( BIT(31) ) +#define BITS_ADC2_DLL_OUT(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_ADC2_CALRDOUT(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) ) +#define BIT_ADC2_DLL_SOFT_RST ( BIT(10) ) +#define BIT_ADC2_CAL_SOFT_RST ( BIT(9) ) +#define BIT_ADC2_CALRD ( BIT(8) ) +#define BIT_ADC2_CALEN ( BIT(7) ) +#define BITS_ADC2_CALADDR(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_ADC2_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR00 */ +#define BITS_ADC2_RSV_1(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC2_RSV_0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR01 */ +#define BIT_ADC2_DIG_CLK_SEL_0 ( BIT(30) ) +#define BIT_ADC2_VCM_SEL_0 ( BIT(29) ) +#define BITS_ADC2_DELAY_CAP_0(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC2_BIT_SEL_0(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC2_VREF_SEL_0(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC2_VREF_BOOST_0(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC2_QUANT_BOOST_0(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC2_DLLRD_0 ( BIT(18) ) +#define BIT_ADC2_DLLWR_0 ( BIT(17) ) +#define BIT_ADC2_DLLEN_0 ( BIT(16) ) +#define BIT_ADC2_CSBC ( BIT(15) ) +#define BIT_ADC2_IQSWAP ( BIT(14) ) +#define BITS_ADC2_DLLOOF_0(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_ADC2_OSBC ( BIT(7) ) +#define BIT_ADC2_ISBC ( BIT(6) ) +#define BITS_ADC2_DLLIN_0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR02 */ +#define BIT_ADC2_DIG_CLK_SEL_1 ( BIT(30) ) +#define BIT_ADC2_VCM_SEL_1 ( BIT(29) ) +#define BITS_ADC2_DELAY_CAP_1(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC2_BIT_SEL_1(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC2_VREF_SEL_1(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC2_VREF_BOOST_1(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC2_QUANT_BOOST_1(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC2_DLLRD_1 ( BIT(18) ) +#define BIT_ADC2_DLLWR_1 ( BIT(17) ) +#define BIT_ADC2_DLLEN_1 ( BIT(16) ) +#define BITS_ADC2_DLLOOF_1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC2_DLLIN_1(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR10 */ +#define BITS_ADC2_RSV_3(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC2_RSV_2(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR11 */ +#define BIT_ADC2_DIG_CLK_SEL_2 ( BIT(30) ) +#define BIT_ADC2_VCM_SEL_2 ( BIT(29) ) +#define BITS_ADC2_DELAY_CAP_2(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC2_BIT_SEL_2(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC2_VREF_SEL_2(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC2_VREF_BOOST_2(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC2_QUANT_BOOST_2(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC2_DLLRD_2 ( BIT(18) ) +#define BIT_ADC2_DLLWR_2 ( BIT(17) ) +#define BIT_ADC2_DLLEN_2 ( BIT(16) ) +#define BITS_ADC2_DLLOOF_2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC2_DLLIN_2(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR12 */ +#define BIT_ADC2_DIG_CLK_SEL_3 ( BIT(30) ) +#define BIT_ADC2_VCM_SEL_3 ( BIT(29) ) +#define BITS_ADC2_DELAY_CAP_3(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC2_BIT_SEL_3(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC2_VREF_SEL_3(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC2_VREF_BOOST_3(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC2_QUANT_BOOST_3(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC2_DLLRD_3 ( BIT(18) ) +#define BIT_ADC2_DLLWR_3 ( BIT(17) ) +#define BIT_ADC2_DLLEN_3 ( BIT(16) ) +#define BITS_ADC2_DLLOOF_3(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC2_DLLIN_3(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR20 */ +#define BITS_ADC2_RSV_5(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC2_RSV_4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR21 */ +#define BIT_ADC2_DIG_CLK_SEL_4 ( BIT(30) ) +#define BIT_ADC2_VCM_SEL_4 ( BIT(29) ) +#define BITS_ADC2_DELAY_CAP_4(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC2_BIT_SEL_4(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC2_VREF_SEL_4(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC2_VREF_BOOST_4(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC2_QUANT_BOOST_4(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC2_DLLRD_4 ( BIT(18) ) +#define BIT_ADC2_DLLWR_4 ( BIT(17) ) +#define BIT_ADC2_DLLEN_4 ( BIT(16) ) +#define BITS_ADC2_DLLOOF_4(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC2_DLLIN_4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR22 */ +#define BIT_ADC2_DIG_CLK_SEL_5 ( BIT(30) ) +#define BIT_ADC2_VCM_SEL_5 ( BIT(29) ) +#define BITS_ADC2_DELAY_CAP_5(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC2_BIT_SEL_5(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC2_VREF_SEL_5(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC2_VREF_BOOST_5(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC2_QUANT_BOOST_5(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC2_DLLRD_5 ( BIT(18) ) +#define BIT_ADC2_DLLWR_5 ( BIT(17) ) +#define BIT_ADC2_DLLEN_5 ( BIT(16) ) +#define BITS_ADC2_DLLOOF_5(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC2_DLLIN_5(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_CTR1 */ +#define BITS_DAC3_WD_OVR(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DAC3_WADDR_OVR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DAC3_WLE_OVR ( BIT(2) ) +#define BIT_DAC3_W_OVR_I_QN ( BIT(1) ) +#define BIT_DAC3_W_OVR_EN ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_CTR2 */ +#define BIT_DAC3_AUTO_RST ( BIT(23) ) +#define BIT_DAC3_SOFT_RST ( BIT(22) ) +#define BIT_DAC3_OSBC ( BIT(21) ) +#define BIT_DAC3_ISBC ( BIT(20) ) +#define BIT_DAC3_OVR_EN_CAL ( BIT(19) ) +#define BIT_DAC3_EN_OOSCAL ( BIT(18) ) +#define BIT_DAC3_IQSWAP ( BIT(17) ) +#define BIT_DAC3_CAL_START ( BIT(16) ) +#define BITS_DAC3_OFFSETI(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DAC3_OFFSETQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_CTR3 */ +#define BITS_DAC3_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DAC3_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_CTR4 */ +#define BITS_DAC3_I_CAL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DAC3_Q_CAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_STS0 */ +#define BITS_DAC3_WTI(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DAC3_WTQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_STS1 */ +#define BITS_DAC3_DA_STATE(_X_) ( (_X_) << 17 & (BIT(17)|BIT(18)) ) +#define BIT_DAC3_DONE ( BIT(16) ) +#define BITS_DAC3_WQ_OVR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL3_CTR0 */ +#define BITS_ADC3_CLK_CAL_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_ADA3_CAL_WAIT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_CLK_ADA3_CAL_EN ( BIT(6) ) +#define BIT_DAC3_PD_CAL ( BIT(5) ) +#define BIT_ADC3_EN_CAL ( BIT(3) ) +#define BIT_ADC3_CAL ( BIT(1) ) +#define BIT_ADA3_MODE_SEL ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL3_CTR1 */ +#define BITS_ADC3_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) ) +#define BITS_ADC3_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL3_CTR3 */ +#define BIT_ADA3_CAL_START ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL3_STS0 */ +#define BIT_ADA3_CAL_DONE ( BIT(31) ) +#define BITS_ADC3_CAL_I_SUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL3_STS1 */ +#define BITS_ADC3_CAL_Q_SUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_CTR00 */ +#define BIT_DAC3_OUT_SEL_2 ( BIT(26) ) +#define BITS_DAC3_RSV_2(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC3_PCTRL_2(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)) ) +#define BIT_DAC3_CLK_SEL_2 ( BIT(18) ) +#define BIT_DAC3_OUT_SEL_1 ( BIT(17) ) +#define BITS_DAC3_RSV_1(_X_) ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)) ) +#define BITS_DAC3_PCTRL_1(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DAC3_CLK_SEL_1 ( BIT(9) ) +#define BIT_DAC3_OUT_SEL_0 ( BIT(8) ) +#define BITS_DAC3_RSV_0(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DAC3_PCTRL_0(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)) ) +#define BIT_DAC3_CLK_SEL_0 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_CTR10 */ +#define BIT_DAC3_OUT_SEL_5 ( BIT(26) ) +#define BITS_DAC3_RSV_5(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC3_PCTRL_5(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)) ) +#define BIT_DAC3_CLK_SEL_5 ( BIT(18) ) +#define BIT_DAC3_OUT_SEL_4 ( BIT(17) ) +#define BITS_DAC3_RSV_4(_X_) ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)) ) +#define BITS_DAC3_PCTRL_4(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DAC3_CLK_SEL_4 ( BIT(9) ) +#define BIT_DAC3_OUT_SEL_3 ( BIT(8) ) +#define BITS_DAC3_RSV_3(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DAC3_PCTRL_3(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)) ) +#define BIT_DAC3_CLK_SEL_3 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR0 */ +#define BIT_ADC3_SOFT_RST ( BIT(31) ) +#define BITS_ADC3_DLL_OUT(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_ADC3_CALRDOUT(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) ) +#define BIT_ADC3_DLL_SOFT_RST ( BIT(10) ) +#define BIT_ADC3_CAL_SOFT_RST ( BIT(9) ) +#define BIT_ADC3_CALRD ( BIT(8) ) +#define BIT_ADC3_CALEN ( BIT(7) ) +#define BITS_ADC3_CALADDR(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_ADC3_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR00 */ +#define BITS_ADC3_RSV_1(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC3_RSV_0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR01 */ +#define BIT_ADC3_DIG_CLK_SEL_0 ( BIT(30) ) +#define BIT_ADC3_VCM_SEL_0 ( BIT(29) ) +#define BITS_ADC3_DELAY_CAP_0(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC3_BIT_SEL_0(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC3_VREF_SEL_0(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC3_VREF_BOOST_0(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC3_QUANT_BOOST_0(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC3_DLLRD_0 ( BIT(18) ) +#define BIT_ADC3_DLLWR_0 ( BIT(17) ) +#define BIT_ADC3_DLLEN_0 ( BIT(16) ) +#define BIT_ADC3_CSBC ( BIT(15) ) +#define BIT_ADC3_IQSWAP ( BIT(14) ) +#define BITS_ADC3_DLLOOF_0(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_ADC3_OSBC ( BIT(7) ) +#define BIT_ADC3_ISBC ( BIT(6) ) +#define BITS_ADC3_DLLIN_0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR02 */ +#define BIT_ADC3_DIG_CLK_SEL_1 ( BIT(30) ) +#define BIT_ADC3_VCM_SEL_1 ( BIT(29) ) +#define BITS_ADC3_DELAY_CAP_1(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC3_BIT_SEL_1(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC3_VREF_SEL_1(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC3_VREF_BOOST_1(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC3_QUANT_BOOST_1(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC3_DLLRD_1 ( BIT(18) ) +#define BIT_ADC3_DLLWR_1 ( BIT(17) ) +#define BIT_ADC3_DLLEN_1 ( BIT(16) ) +#define BITS_ADC3_DLLOOF_1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC3_DLLIN_1(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR10 */ +#define BITS_ADC3_RSV_3(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC3_RSV_2(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR11 */ +#define BIT_ADC3_DIG_CLK_SEL_2 ( BIT(30) ) +#define BIT_ADC3_VCM_SEL_2 ( BIT(29) ) +#define BITS_ADC3_DELAY_CAP_2(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC3_BIT_SEL_2(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC3_VREF_SEL_2(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC3_VREF_BOOST_2(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC3_QUANT_BOOST_2(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC3_DLLRD_2 ( BIT(18) ) +#define BIT_ADC3_DLLWR_2 ( BIT(17) ) +#define BIT_ADC3_DLLEN_2 ( BIT(16) ) +#define BITS_ADC3_DLLOOF_2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC3_DLLIN_2(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR12 */ +#define BIT_ADC3_DIG_CLK_SEL_3 ( BIT(30) ) +#define BIT_ADC3_VCM_SEL_3 ( BIT(29) ) +#define BITS_ADC3_DELAY_CAP_3(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC3_BIT_SEL_3(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC3_VREF_SEL_3(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC3_VREF_BOOST_3(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC3_QUANT_BOOST_3(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC3_DLLRD_3 ( BIT(18) ) +#define BIT_ADC3_DLLWR_3 ( BIT(17) ) +#define BIT_ADC3_DLLEN_3 ( BIT(16) ) +#define BITS_ADC3_DLLOOF_3(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC3_DLLIN_3(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR20 */ +#define BITS_ADC3_RSV_5(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC3_RSV_4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR21 */ +#define BIT_ADC3_DIG_CLK_SEL_4 ( BIT(30) ) +#define BIT_ADC3_VCM_SEL_4 ( BIT(29) ) +#define BITS_ADC3_DELAY_CAP_4(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC3_BIT_SEL_4(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC3_VREF_SEL_4(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC3_VREF_BOOST_4(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC3_QUANT_BOOST_4(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC3_DLLRD_4 ( BIT(18) ) +#define BIT_ADC3_DLLWR_4 ( BIT(17) ) +#define BIT_ADC3_DLLEN_4 ( BIT(16) ) +#define BITS_ADC3_DLLOOF_4(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC3_DLLIN_4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR22 */ +#define BIT_ADC3_DIG_CLK_SEL_5 ( BIT(30) ) +#define BIT_ADC3_VCM_SEL_5 ( BIT(29) ) +#define BITS_ADC3_DELAY_CAP_5(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC3_BIT_SEL_5(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC3_VREF_SEL_5(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC3_VREF_BOOST_5(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC3_QUANT_BOOST_5(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC3_DLLRD_5 ( BIT(18) ) +#define BIT_ADC3_DLLWR_5 ( BIT(17) ) +#define BIT_ADC3_DLLEN_5 ( BIT(16) ) +#define BITS_ADC3_DLLOOF_5(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC3_DLLIN_5(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_AFCDAC1_CFG */ +#define BITS_AFCDAC1_CHANNEL_MASK(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_AFCDAC1_CHANNEL_SSET(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BIT_AFCDAC1_LOW_V_CON_SST ( BIT(23) ) +#define BIT_AFCDAC1_BP_RES_SST ( BIT(20) ) +#define BITS_AFCDAC1_G_SST(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_AFCDAC1_CTL_SST(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BIT_AFCDAC1_PD_SST ( BIT(15) ) +#define BITS_AFCDAC1_D_SST(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_AFCDAC2_CFG */ +#define BITS_AFCDAC2_CHANNEL_MASK(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_AFCDAC2_CHANNEL_SSET(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BIT_AFCDAC2_LOW_V_CON_SST ( BIT(23) ) +#define BIT_AFCDAC2_BP_RES_SST ( BIT(20) ) +#define BITS_AFCDAC2_G_SST(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_AFCDAC2_CTL_SST(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BIT_AFCDAC2_PD_SST ( BIT(15) ) +#define BITS_AFCDAC2_D_SST(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_APCDAC1_CFG */ +#define BITS_APCDAC1_CHANNEL_MASK(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_APCDAC1_CHANNEL_SSET(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BIT_APCDAC1_LOW_V_CON_SST ( BIT(23) ) +#define BITS_APCDAC1_OUTSEL_SST(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BIT_APCDAC1_BP_RES_SST ( BIT(20) ) +#define BITS_APCDAC1_G_SST(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_APCDAC1_CTL_SST(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BIT_APCDAC1_PD_SST ( BIT(15) ) +#define BIT_APCDAC1_SEL_SST ( BIT(14) ) +#define BITS_APCDAC1_D_SST(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_APCDAC2_CFG */ +#define BITS_APCDAC2_CHANNEL_MASK(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_APCDAC2_CHANNEL_SSET(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BIT_APCDAC2_LOW_V_CON_SST ( BIT(23) ) +#define BITS_APCDAC2_OUTSEL_SST(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BIT_APCDAC2_BP_RES_SST ( BIT(20) ) +#define BITS_APCDAC2_G_SST(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_APCDAC2_CTL_SST(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BIT_APCDAC2_PD_SST ( BIT(15) ) +#define BIT_APCDAC2_SEL_SST ( BIT(14) ) +#define BITS_APCDAC2_D_SST(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFSPI_CFG */ +#define BITS_RFSBI2_CHANNEL_MASK(_X_) ( (_X_) << 29 & (BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_RFSBI2_CHANNEL_SSET(_X_) ( (_X_) << 26 & (BIT(26)|BIT(27)|BIT(28)) ) +#define BIT_RFSBI2_IDATA_SST ( BIT(25) ) +#define BIT_RFSBI2_ODATA_SST ( BIT(24) ) +#define BIT_RFSBI2_DATA_OE_SST ( BIT(23) ) +#define BIT_RFSBI2_DATA_IE_SST ( BIT(22) ) +#define BIT_RFSBI2_CLK_SST ( BIT(21) ) +#define BIT_RFSBI2_CLK_OE_SST ( BIT(20) ) +#define BIT_RFSBI2_EN0_SST ( BIT(19) ) +#define BIT_RFSBI2_EN0_OE_SST ( BIT(18) ) +#define BIT_RFSBI2_EN1_SST ( BIT(17) ) +#define BIT_RFSBI2_EN1_OE_SST ( BIT(16) ) +#define BITS_RFSBI1_CHANNEL_MASK(_X_) ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_RFSBI1_CHANNEL_SSET(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_RFSBI1_IDATA_SST ( BIT(9) ) +#define BIT_RFSBI1_ODATA_SST ( BIT(8) ) +#define BIT_RFSBI1_DATA_OE_SST ( BIT(7) ) +#define BIT_RFSBI1_DATA_IE_SST ( BIT(6) ) +#define BIT_RFSBI1_CLK_SST ( BIT(5) ) +#define BIT_RFSBI1_CLK_OE_SST ( BIT(4) ) +#define BIT_RFSBI1_EN0_SST ( BIT(3) ) +#define BIT_RFSBI1_EN0_OE_SST ( BIT(2) ) +#define BIT_RFSBI1_EN1_SST ( BIT(1) ) +#define BIT_RFSBI1_EN1_OE_SST ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFMIPI_CFG */ +#define BITS_RFMIPI2_CHANNEL_MASK(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_RFMIPI2_CHANNEL_SSET(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BIT_PAD_OUT_RFFE2_CLK_SST ( BIT(20) ) +#define BIT_PAD_OUT_RFFE2_DATA_SST ( BIT(19) ) +#define BIT_PAD_IN_RFFE2_DATA_SST ( BIT(18) ) +#define BIT_PAD_OE_RFFE2_DATA_SST ( BIT(17) ) +#define BIT_PAD_IE_RFFE2_DATA_SST ( BIT(16) ) +#define BITS_RFMIPI1_CHANNEL_MASK(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_RFMIPI1_CHANNEL_SSET(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BIT_PAD_OUT_RFFE1_CLK_SST ( BIT(4) ) +#define BIT_PAD_OUT_RFFE1_DATA_SST ( BIT(3) ) +#define BIT_PAD_IN_RFFE1_DATA_SST ( BIT(2) ) +#define BIT_PAD_OE_RFFE1_DATA_SST ( BIT(1) ) +#define BIT_PAD_IE_RFFE1_DATA_SST ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_APCDAC_OUTSEL */ +#define BIT_AFCDAC_LOW_V_CON_GGE ( BIT(31) ) +#define BIT_AFCDAC_LOW_V_CON_WG ( BIT(30) ) +#define BIT_AFCDAC_LOW_V_CON_WD ( BIT(29) ) +#define BIT_AFCDAC_LOW_V_CON_TG ( BIT(28) ) +#define BIT_AFCDAC_LOW_V_CON_TD ( BIT(27) ) +#define BIT_AFCDAC_LOW_V_CON_LTE ( BIT(26) ) +#define BITS_APCDACX_G3_SST(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_APCDACX_G2_SST(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)) ) +#define BITS_APCDACX_G1_SST(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)) ) +#define BITS_APCDACX_G0_SST(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BIT_APCDAC_LOW_V_CON_GGE ( BIT(17) ) +#define BIT_APCDAC_LOW_V_CON_WG ( BIT(16) ) +#define BIT_APCDAC_LOW_V_CON_WD ( BIT(15) ) +#define BIT_APCDAC_LOW_V_CON_TG ( BIT(14) ) +#define BIT_APCDAC_LOW_V_CON_TD ( BIT(13) ) +#define BIT_APCDAC_LOW_V_CON_LTE ( BIT(12) ) +#define BITS_APCDAC_OUTSEL_GGE(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_APCDAC_OUTSEL_WG(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_APCDAC_OUTSEL_WD(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_APCDAC_OUTSEL_TG(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_APCDAC_OUTSEL_TD(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_APCDAC_OUTSEL_LTE(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CLASH_CHK */ +#define BIT_RFSBI2_CLASH_CHK_INTRP_EN ( BIT(29) ) +#define BIT_RFSBI1_CLASH_CHK_INTRP_EN ( BIT(28) ) +#define BIT_RFMIPI2_CLASH_CHK_INTRP_EN ( BIT(27) ) +#define BIT_RFMIPI1_CLASH_CHK_INTRP_EN ( BIT(26) ) +#define BIT_APCDAC2_CLASH_CHK_INTRP_EN ( BIT(25) ) +#define BIT_APCDAC1_CLASH_CHK_INTRP_EN ( BIT(24) ) +#define BIT_AFCDAC2_CLASH_CHK_INTRP_EN ( BIT(23) ) +#define BIT_AFCDAC1_CLASH_CHK_INTRP_EN ( BIT(22) ) +#define BIT_ADA3_TX_CLASH_CHK_INTRP_EN ( BIT(21) ) +#define BIT_ADA3_RX_CLASH_CHK_INTRP_EN ( BIT(20) ) +#define BIT_ADA2_TX_CLASH_CHK_INTRP_EN ( BIT(19) ) +#define BIT_ADA2_RX_CLASH_CHK_INTRP_EN ( BIT(18) ) +#define BIT_ADA1_TX_CLASH_CHK_INTRP_EN ( BIT(17) ) +#define BIT_ADA1_RX_CLASH_CHK_INTRP_EN ( BIT(16) ) +#define BIT_CHK_CLASH_STFREE ( BIT(8) ) +#define BIT_CHK_CLASH_CLR ( BIT(7) ) +#define BIT_CHK_CLASH_RTC_SNAP_MODE ( BIT(4) ) +#define BIT_CHK_CLASH_RTC_SNAP_EDGE ( BIT(3) ) +#define BIT_CHK_CLASH_RTC_SNAP_INTRP_TYPE ( BIT(2) ) +#define BIT_CHK_CLASH_RTC_SNAP_INTRP_CLR ( BIT(1) ) +#define BIT_CHK_CLASH_RTC_SNAP_INTRP ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CLASH_SNAP */ +#define BITS_CHK_CLASH_RTC_SNAP_TIME(_X_) (_X_) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CLASH_STATUS1 */ +#define BITS_CHK_CLASH_ADA3_TX_CHANNEL_SEL(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_CHK_CLASH_ADA3_RX_CHANNEL_SEL(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) ) +#define BITS_CHK_CLASH_ADA2_TX_CHANNEL_SEL(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_CHK_CLASH_ADA2_RX_CHANNEL_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_CHK_CLASH_ADA1_TX_CHANNEL_SEL(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_CHK_CLASH_ADA1_RX_CHANNEL_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CLASH_STATUS2 */ +#define BITS_CHK_CLASH_APCDAC2_CHANNEL_SEL(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_CHK_CLASH_APCDAC1_CHANNEL_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CHK_CLASH_AFCDAC2_CHANNEL_SEL(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_CHK_CLASH_AFCDAC1_CHANNEL_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CLASH_STATUS3 */ +#define BITS_CHK_CLASH_RFSBI2_CHANNEL_SEL(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_CHK_CLASH_RFSBI1_CHANNEL_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CHK_CLASH_RFMIPI2_CHANNEL_SEL(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_CHK_CLASH_RFMIPI1_CHANNEL_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_EXTRA_CFG0 */ +#define BITS_APT_DCM2_EXTRA_CFG(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_APT_DCM2_ADI_EN ( BIT(23) ) +#define BITS_APT_DCM2_CHANNEL_SSET(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BIT_APT_DCM2_SST ( BIT(19) ) +#define BITS_APT_DCM2_CHANNEL_MASK(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)) ) +#define BITS_APT_DCM1_EXTRA_CFG(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_APT_DCM1_ADI_EN ( BIT(7) ) +#define BITS_APT_DCM1_CHANNEL_SSET(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_APT_DCM1_SST ( BIT(3) ) +#define BITS_APT_DCM1_CHANNEL_MASK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_EXTRA_CFG1 */ +#define BITS_MDAR_EXTRA_CFG1(_X_) ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_MDAR_EXTRA_CFG1_2 ( BIT(12) ) +#define BIT_MDAR_EXTRA_CFG1_1 ( BIT(11) ) +#define BIT_MDAR_EXTRA_CFG1_0 ( BIT(10) ) +#define BITS_MDAR_BB_LDO_REFCTRL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_MDAR_BB_LDO_SLEEP_PD_EN ( BIT(6) ) +#define BIT_MDAR_BB_LDO_FORCE_ON ( BIT(5) ) +#define BIT_MDAR_BB_LDO_FORCE_PD ( BIT(4) ) +#define BIT_MDAR_BB_BG_SLEEP_PD_EN ( BIT(2) ) +#define BIT_MDAR_BB_BG_FORCE_ON ( BIT(1) ) +#define BIT_MDAR_BB_BG_FORCE_PD ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF0 */ +#define BITS_CHK_CLASH_RFCTRL15_CHX_SEL(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BIT_RFCTRL15_CHK_INTRP_EN ( BIT(16) ) +#define BIT_RFCTRL15_RTC_REFRESH ( BIT(12) ) +#define BIT_RFCTRL15_SNAP_REFRESH ( BIT(8) ) +#define BITS_RFCTRL15_SSET(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BITS_RFCTRL15_MASK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF1 */ +#define BITS_RFCTRL15_CH0_SNAP1_RTC_TIME(_X_) (_X_) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF2 */ +#define BITS_RFCTRL15_CH0_SNAP0_RTC_TIME(_X_) (_X_) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF3 */ +#define BITS_RFCTRL15_CH1_SNAP1_RTC_TIME(_X_) (_X_) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF4 */ +#define BITS_RFCTRL15_CH1_SNAP0_RTC_TIME(_X_) (_X_) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF5 */ +#define BITS_RFCTRL15_CH2_SNAP1_RTC_TIME(_X_) (_X_) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF6 */ +#define BITS_RFCTRL15_CH2_SNAP0_RTC_TIME(_X_) (_X_) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG4 */ +#define BITS_RFCTRL_CHANNEL_MASK3(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_RFCTRL_CHANNEL_MASK2(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BITS_RFCTRL_CHANNEL_MASK1(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RFCTRL_CHANNEL_MASK0(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_RFCTRL150_SST(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG5 */ +#define BITS_RFCTRL_CHANNEL_MASK13(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_RFCTRL_CHANNEL_MASK12(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BITS_RFCTRL_CHANNEL_MASK11(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RFCTRL_CHANNEL_MASK10(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_RFCTRL_CHANNEL_MASK9(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) ) +#define BITS_RFCTRL_CHANNEL_MASK8(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_RFCTRL_CHANNEL_MASK7(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_RFCTRL_CHANNEL_MASK6(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_RFCTRL_CHANNEL_MASK5(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_RFCTRL_CHANNEL_MASK4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG6 */ +#define BITS_RFCTRL_CHANNEL_SSET7(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_RFCTRL_CHANNEL_SSET6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BITS_RFCTRL_CHANNEL_SSET5(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RFCTRL_CHANNEL_SSET4(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_RFCTRL_CHANNEL_SSET3(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) ) +#define BITS_RFCTRL_CHANNEL_SSET2(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_RFCTRL_CHANNEL_SSET1(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_RFCTRL_CHANNEL_SSET0(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_RFCTRL_CHANNEL_MASK15(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_RFCTRL_CHANNEL_MASK14(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG7 */ +#define BITS_RFCTRL_CHANNEL_SSET15(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RFCTRL_CHANNEL_SSET14(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_RFCTRL_CHANNEL_SSET13(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) ) +#define BITS_RFCTRL_CHANNEL_SSET12(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_RFCTRL_CHANNEL_SSET11(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_RFCTRL_CHANNEL_SSET10(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_RFCTRL_CHANNEL_SSET9(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_RFCTRL_CHANNEL_SSET8(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG8 */ +#define BITS_RFCTRL_CHANNEL_MASK19(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_RFCTRL_CHANNEL_MASK18(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BITS_RFCTRL_CHANNEL_MASK17(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RFCTRL_CHANNEL_MASK16(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_RFCTRL3130_SST(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_RFCTRL2916_SST(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG9 */ +#define BITS_RFCTRL_CHANNEL_MASK29(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_RFCTRL_CHANNEL_MASK28(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BITS_RFCTRL_CHANNEL_MASK27(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RFCTRL_CHANNEL_MASK26(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_RFCTRL_CHANNEL_MASK25(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) ) +#define BITS_RFCTRL_CHANNEL_MASK24(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_RFCTRL_CHANNEL_MASK23(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_RFCTRL_CHANNEL_MASK22(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_RFCTRL_CHANNEL_MASK21(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_RFCTRL_CHANNEL_MASK20(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG10 */ +#define BITS_RFCTRL_CHANNEL_SSET23(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_RFCTRL_CHANNEL_SSET22(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BITS_RFCTRL_CHANNEL_SSET21(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RFCTRL_CHANNEL_SSET20(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_RFCTRL_CHANNEL_SSET19(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) ) +#define BITS_RFCTRL_CHANNEL_SSET18(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_RFCTRL_CHANNEL_SSET17(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_RFCTRL_CHANNEL_SSET16(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_RFCTRL_CHANNEL_MASK31(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_RFCTRL_CHANNEL_MASK30(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG11 */ +#define BITS_RFCTRL_CHANNEL_SSET31(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RFCTRL_CHANNEL_SSET30(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_RFCTRL_CHANNEL_SSET29(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) ) +#define BITS_RFCTRL_CHANNEL_SSET28(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_RFCTRL_CHANNEL_SSET27(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_RFCTRL_CHANNEL_SSET26(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_RFCTRL_CHANNEL_SSET25(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_RFCTRL_CHANNEL_SSET24(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG12 */ +#define BITS_RFCTRL_WTGCFGH(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_RFCTRL_WTGCFGL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG13 */ +#define BITS_RFCTRL_GGECFGH(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_RFCTRL_GGECFGL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG14 */ +#define BITS_MDAR_CFG14(_X_) (_X_) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG15 */ +#define BITS_MDAR_ANALOG_BB_RSV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG10 */ +#define BIT_ADC1_IMBP_CLK_SEL_5 ( BIT(21) ) +#define BIT_ADC1_IMBP_CLK_SEL_4 ( BIT(20) ) +#define BIT_ADC1_IMBP_CLK_SEL_3 ( BIT(19) ) +#define BIT_ADC1_IMBP_CLK_SEL_2 ( BIT(18) ) +#define BIT_ADC1_IMBP_CLK_SEL_1 ( BIT(17) ) +#define BIT_ADC1_IMBP_CLK_SEL_0 ( BIT(16) ) +#define BIT_DAC1_IMBP_BYPASS_5 ( BIT(13) ) +#define BIT_DAC1_IMBP_BYPASS_4 ( BIT(12) ) +#define BIT_DAC1_IMBP_BYPASS_3 ( BIT(11) ) +#define BIT_DAC1_IMBP_BYPASS_2 ( BIT(10) ) +#define BIT_DAC1_IMBP_BYPASS_1 ( BIT(9) ) +#define BIT_DAC1_IMBP_BYPASS_0 ( BIT(8) ) +#define BIT_ADC1_IMBP_BYPASS_5 ( BIT(5) ) +#define BIT_ADC1_IMBP_BYPASS_4 ( BIT(4) ) +#define BIT_ADC1_IMBP_BYPASS_3 ( BIT(3) ) +#define BIT_ADC1_IMBP_BYPASS_2 ( BIT(2) ) +#define BIT_ADC1_IMBP_BYPASS_1 ( BIT(1) ) +#define BIT_ADC1_IMBP_BYPASS_0 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG11 */ +#define BITS_ADC1_BAL_B(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_ADC1_BAL_A(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG12 */ +#define BITS_ADC1_BAL_D(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_ADC1_BAL_C(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG13 */ +#define BITS_DAC1_BAL_B(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_DAC1_BAL_A(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG14 */ +#define BITS_DAC1_BAL_D(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_DAC1_BAL_C(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG20 */ +#define BIT_ADC2_IMBP_CLK_SEL_5 ( BIT(21) ) +#define BIT_ADC2_IMBP_CLK_SEL_4 ( BIT(20) ) +#define BIT_ADC2_IMBP_CLK_SEL_3 ( BIT(19) ) +#define BIT_ADC2_IMBP_CLK_SEL_2 ( BIT(18) ) +#define BIT_ADC2_IMBP_CLK_SEL_1 ( BIT(17) ) +#define BIT_ADC2_IMBP_CLK_SEL_0 ( BIT(16) ) +#define BIT_DAC2_IMBP_BYPASS_5 ( BIT(13) ) +#define BIT_DAC2_IMBP_BYPASS_4 ( BIT(12) ) +#define BIT_DAC2_IMBP_BYPASS_3 ( BIT(11) ) +#define BIT_DAC2_IMBP_BYPASS_2 ( BIT(10) ) +#define BIT_DAC2_IMBP_BYPASS_1 ( BIT(9) ) +#define BIT_DAC2_IMBP_BYPASS_0 ( BIT(8) ) +#define BIT_ADC2_IMBP_BYPASS_5 ( BIT(5) ) +#define BIT_ADC2_IMBP_BYPASS_4 ( BIT(4) ) +#define BIT_ADC2_IMBP_BYPASS_3 ( BIT(3) ) +#define BIT_ADC2_IMBP_BYPASS_2 ( BIT(2) ) +#define BIT_ADC2_IMBP_BYPASS_1 ( BIT(1) ) +#define BIT_ADC2_IMBP_BYPASS_0 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG21 */ +#define BITS_ADC2_BAL_B(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_ADC2_BAL_A(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG22 */ +#define BITS_ADC2_BAL_D(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_ADC2_BAL_C(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG23 */ +#define BITS_DAC2_BAL_B(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_DAC2_BAL_A(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG24 */ +#define BITS_DAC2_BAL_D(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_DAC2_BAL_C(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG30 */ +#define BIT_ADC3_IMBP_CLK_SEL_5 ( BIT(21) ) +#define BIT_ADC3_IMBP_CLK_SEL_4 ( BIT(20) ) +#define BIT_ADC3_IMBP_CLK_SEL_3 ( BIT(19) ) +#define BIT_ADC3_IMBP_CLK_SEL_2 ( BIT(18) ) +#define BIT_ADC3_IMBP_CLK_SEL_1 ( BIT(17) ) +#define BIT_ADC3_IMBP_CLK_SEL_0 ( BIT(16) ) +#define BIT_DAC3_IMBP_BYPASS_5 ( BIT(13) ) +#define BIT_DAC3_IMBP_BYPASS_4 ( BIT(12) ) +#define BIT_DAC3_IMBP_BYPASS_3 ( BIT(11) ) +#define BIT_DAC3_IMBP_BYPASS_2 ( BIT(10) ) +#define BIT_DAC3_IMBP_BYPASS_1 ( BIT(9) ) +#define BIT_DAC3_IMBP_BYPASS_0 ( BIT(8) ) +#define BIT_ADC3_IMBP_BYPASS_5 ( BIT(5) ) +#define BIT_ADC3_IMBP_BYPASS_4 ( BIT(4) ) +#define BIT_ADC3_IMBP_BYPASS_3 ( BIT(3) ) +#define BIT_ADC3_IMBP_BYPASS_2 ( BIT(2) ) +#define BIT_ADC3_IMBP_BYPASS_1 ( BIT(1) ) +#define BIT_ADC3_IMBP_BYPASS_0 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG31 */ +#define BITS_ADC3_BAL_B(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_ADC3_BAL_A(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG32 */ +#define BITS_ADC3_BAL_D(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_ADC3_BAL_C(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG33 */ +#define BITS_DAC3_BAL_B(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_DAC3_BAL_A(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG34 */ +#define BITS_DAC3_BAL_D(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_DAC3_BAL_C(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_mm_ahb_rf.h b/include/soc/sprd/chip_x35lt8/__regs_mm_ahb_rf.h new file mode 100644 index 00000000..a4d01e30 --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_mm_ahb_rf.h @@ -0,0 +1,111 @@ +/* the head file modifier: g 2015-03-19 17:13:17*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_MM_AHB_RF_HEADFILE_H__ +#define __H_REGS_MM_AHB_RF_HEADFILE_H__ __FILE__ + +#define REGS_MM_AHB_RF + +/* registers definitions for MM_AHB_RF */ +#define REG_MM_AHB_AHB_EB SCI_ADDR(REGS_MM_AHB_BASE, 0x0000)/*AHB_EB*/ +#define REG_MM_AHB_AHB_RST SCI_ADDR(REGS_MM_AHB_BASE, 0x0004)/*AHB_RST*/ +#define REG_MM_AHB_GEN_CKG_CFG SCI_ADDR(REGS_MM_AHB_BASE, 0x0008)/*GEN_CKG_CFG*/ +#define REG_MM_AHB_MIPI_CSI2_CTRL SCI_ADDR(REGS_MM_AHB_BASE, 0x000C)/*MIPI_CSI2_CTRL*/ +#define REG_MM_AHB_MM_QOS_CFG0 SCI_ADDR(REGS_MM_AHB_BASE, 0x0010)/*MM_QOS_CFG0*/ +#define REG_MM_AHB_MM_QOS_CFG1 SCI_ADDR(REGS_MM_AHB_BASE, 0x0014)/*MM_QOS_CFG1*/ +#define REG_MM_AHB_RF_AHB_EB REG_MM_AHB_AHB_EB +#define REG_MM_AHB_RF_AHB_RST REG_MM_AHB_AHB_RST +#define REG_MM_AHB_RF_GEN_CKG_CFG REG_MM_AHB_GEN_CKG_CFG +#define REG_MM_AHB_RF_MIPI_CSI2_CTRL REG_MM_AHB_MIPI_CSI2_CTRL +#define REG_MM_AHB_RF_MM_QOS_CFG REG_MM_AHB_MM_QOS_CFG0 + + + +/* bits definitions for register REG_MM_AHB_AHB_EB */ +#define BIT_VPP_EB ( BIT(8) ) +#define BIT_MMU_EB ( BIT(7) ) +#define BIT_CKG_EB ( BIT(6) ) +#define BIT_MM_CKG_EB BIT_CKG_EB +#define BIT_JPG_EB ( BIT(5) ) +#define BIT_CSI_EB ( BIT(4) ) +#define BIT_VSP_EB ( BIT(3) ) +#define BIT_ISP_EB ( BIT(2) ) +#define BIT_CCIR_EB ( BIT(1) ) +#define BIT_DCAM_EB ( BIT(0) ) + +/* bits definitions for register REG_MM_AHB_AHB_RST */ +#define BIT_VPP_SOFT_RST ( BIT(15) ) +#define BIT_MMU_SOFT_RST ( BIT(14) ) +#define BIT_CKG_SOFT_RST ( BIT(13) ) +#define BIT_MM_CKG_SOFT_RST BIT_CKG_SOFT_RST +#define BIT_MM_MTX_SOFT_RST ( BIT(12) ) +#define BIT_OR1200_SOFT_RST ( BIT(11) ) +#define BIT_ROT_SOFT_RST ( BIT(10) ) +#define BIT_CAM2_SOFT_RST ( BIT(9) ) +#define BIT_CAM1_SOFT_RST ( BIT(8) ) +#define BIT_CAM0_SOFT_RST ( BIT(7) ) +#define BIT_JPG_SOFT_RST ( BIT(6) ) +#define BIT_CSI_SOFT_RST ( BIT(5) ) +#define BIT_VSP_SOFT_RST ( BIT(4) ) +#define BIT_ISP_CFG_SOFT_RST ( BIT(3) ) +#define BIT_ISP_LOG_SOFT_RST ( BIT(2) ) +#define BIT_CCIR_SOFT_RST ( BIT(1) ) +#define BIT_DCAM_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_MM_AHB_GEN_CKG_CFG */ +#define BIT_VPP_AXI_CKG_EN ( BIT(9) ) +#define BIT_MM_MTX_AXI_CKG_EN ( BIT(8) ) +#define BIT_MM_AXI_CKG_EN ( BIT(7) ) +#define BIT_JPG_AXI_CKG_EN ( BIT(6) ) +#define BIT_VSP_AXI_CKG_EN ( BIT(5) ) +#define BIT_ISP_AXI_CKG_EN ( BIT(4) ) +#define BIT_DCAM_AXI_CKG_EN ( BIT(3) ) +#define BIT_SENSOR_CKG_EN ( BIT(2) ) +#define BIT_MIPI_CSI_CKG_EN ( BIT(1) ) +#define BIT_CPHY_CFG_CKG_EN ( BIT(0) ) + +/* bits definitions for register REG_MM_AHB_MIPI_CSI2_CTRL */ +#define BITS_MIPI_CPHY_SAMPLE_SEL(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)) ) +#define BIT_MIPI_CPHY_SYNC_MODE ( BIT(2) ) +#define BIT_MIPI_CPHY_TEST_CTL ( BIT(1) ) +#define BIT_MIPI_CPHY_SEL ( BIT(0) ) + +/* bits definitions for register REG_MM_AHB_MM_QOS_CFG0 */ +#define BITS_QOS_R_DCAM(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_QOS_W_DCAM(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_QOS_R_JPG(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_QOS_W_JPG(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_QOS_R_ISP(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_QOS_W_ISP(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_QOS_R_VSP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_QOS_W_VSP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_MM_QOS_CFG1 */ +#define BITS_QOS_R_VPP(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_QOS_W_VPP(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_QOS_R_CODEC(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_QOS_W_CODEC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_mm_clk.h b/include/soc/sprd/chip_x35lt8/__regs_mm_clk.h new file mode 100644 index 00000000..3e6f4e45 --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_mm_clk.h @@ -0,0 +1,69 @@ +/* the head file modifier: g 2015-03-19 15:48:44*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_MM_CLK_RF_HEADFILE_H__ +#define __H_REGS_MM_CLK_RF_HEADFILE_H__ + +#define REGS_MM_CLK + +/* registers definitions for controller REGS_MM_CLK */ +#define REG_MM_CLK_MM_AHB_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0020) +#define REG_MM_CLK_SENSOR_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0024) +#define REG_MM_CLK_CCIR_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0028) +#define REG_MM_CLK_DCAM_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x002c) +#define REG_MM_CLK_VSP_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0030) +#define REG_MM_CLK_ISP_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0034) +#define REG_MM_CLK_JPG_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0038) +#define REG_MM_CLK_MIPI_CSI_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x003c) + + + +/* bits definitions for register REG_MM_AHB_RF_clk_mm_ahb_cfg */ +#define BITS_CLK_MM_AHB_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_MM_AHB_RF_clk_sensor_cfg */ +#define BITS_CLK_SENSOR_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_SENSOR_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_MM_AHB_RF_clk_ccir_cfg */ +#define BIT_CLK_CCIR_PAD_SEL ( BIT(16) ) +#define BIT_CLK_CCIR_SEL ( BIT(0) ) + +/* bits definitions for register REG_MM_AHB_RF_clk_dcam_cfg */ +#define BITS_CLK_DCAM_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_MM_AHB_RF_clk_vsp_cfg */ +#define BITS_CLK_VSP_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_MM_AHB_RF_clk_isp_cfg */ +#define BITS_CLK_ISP_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_MM_AHB_RF_clk_jpg_cfg */ +#define BITS_CLK_JPG_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_MM_AHB_RF_clk_vpp_cfg */ +#define BITS_CLK_VPP_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_pinmap.h b/include/soc/sprd/chip_x35lt8/__regs_pinmap.h new file mode 100755 index 00000000..be98c3a0 --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_pinmap.h @@ -0,0 +1,283 @@ +#ifndef __ASM_ARM_ARCH_PINMAP_H +#error "Don't include this file directly, Pls include pinmap.h" +#endif + +#ifndef _REGS_PINMAP_H_ +#define _REGS_PINMAP_H_ + +#define CTL_PIN_BASE ( SPRD_PIN_BASE ) + +/* registers definitions for controller CTL_PIN */ +#define REG_PIN_CTRL0 ( 0x0000 ) +#define REG_PIN_CTRL1 ( 0x0004 ) +#define REG_PIN_CTRL2 ( 0x0008 ) +#define REG_PIN_CTRL3 ( 0x000c ) +#define REG_PIN_CTRL4 ( 0x0010 ) +#define REG_PIN_CTRL5 ( 0x0014 ) +#define REG_PIN_SIMCLK0 ( 0x0018 ) +#define REG_PIN_SIMDA0 ( 0x001c ) +#define REG_PIN_SIMRST0 ( 0x0020 ) +#define REG_PIN_SIMCLK1 ( 0x0024 ) +#define REG_PIN_SIMDA1 ( 0x0028 ) +#define REG_PIN_SIMRST1 ( 0x002c ) +#define REG_PIN_SD0_CLK ( 0x0030 ) +#define REG_PIN_SD0_CMD ( 0x0034 ) +#define REG_PIN_SD0_D0 ( 0x0038 ) +#define REG_PIN_SD0_D1 ( 0x003c ) +#define REG_PIN_SD0_D2 ( 0x0040 ) +#define REG_PIN_SD0_D3 ( 0x0044 ) +#define REG_PIN_ANA_INT ( 0x0048 ) +#define REG_PIN_EXT_RST_B ( 0x004c ) +#define REG_PIN_CLK_26M ( 0x0050 ) +#define REG_PIN_CHIP_SLEEP ( 0x0054 ) +#define REG_PIN_XTL_BUF_EN ( 0x0058 ) +#define REG_PIN_CLK_32K ( 0x005c ) +#define REG_PIN_AUD_SCLK ( 0x0060 ) +#define REG_PIN_AUD_ADD0 ( 0x0064 ) +#define REG_PIN_AUD_ADSYNC ( 0x0068 ) +#define REG_PIN_AUD_DAD1 ( 0x006c ) +#define REG_PIN_AUD_DAD0 ( 0x0070 ) +#define REG_PIN_AUD_DASYNC ( 0x0074 ) +#define REG_PIN_TD_TXPD ( 0x0078 ) +#define REG_PIN_TD_RXPD ( 0x007c ) +#define REG_PIN_GSM_TXPD ( 0x0080 ) +#define REG_PIN_GSM_RXPD ( 0x0084 ) +#define REG_PIN_TD_RX_CLK ( 0x0088 ) +#define REG_PIN_ADI_D ( 0x008c ) +#define REG_PIN_ADI_SYNC ( 0x0090 ) +#define REG_PIN_ADI_SCLK ( 0x0094 ) +#define REG_PIN_ANA_INT2 ( 0x0098 ) +#define REG_PIN_COM_TX_APCD ( 0x009c ) +#define REG_PIN_COM_TX_DQ1 ( 0x00a0 ) +#define REG_PIN_COM_TX_DQ0 ( 0x00a4 ) +#define REG_PIN_COM_TX_DI1 ( 0x00a8 ) +#define REG_PIN_COM_TX_DI0 ( 0x00ac ) +#define REG_PIN_COM_TX_SYNC ( 0x00b0 ) +#define REG_PIN_COM_TX_SCLK ( 0x00b4 ) +#define REG_PIN_COM_RX_DQ1 ( 0x00b8 ) +#define REG_PIN_COM_RX_DQ0 ( 0x00bc ) +#define REG_PIN_COM_RX_DI1 ( 0x00c0 ) +#define REG_PIN_COM_RX_DI0 ( 0x00c4 ) +#define REG_PIN_COM_RX_SYNC ( 0x00c8 ) +#define REG_PIN_COM_RX_SCLK ( 0x00cc ) +#define REG_PIN_CCIRCK ( 0x00d0 ) +#define REG_PIN_CCIRMCLK ( 0x00d4 ) +#define REG_PIN_CCIRHS ( 0x00d8 ) +#define REG_PIN_CCIRVS ( 0x00dc ) +#define REG_PIN_CCIRD0 ( 0x00e0 ) +#define REG_PIN_CCIRD1 ( 0x00e4 ) +#define REG_PIN_CCIRD2 ( 0x00e8 ) +#define REG_PIN_CCIRD3 ( 0x00ec ) +#define REG_PIN_CCIRD4 ( 0x00f0 ) +#define REG_PIN_CCIRD5 ( 0x00f4 ) +#define REG_PIN_CCIRD6 ( 0x00f8 ) +#define REG_PIN_CCIRD7 ( 0x00fc ) +#define REG_PIN_CCIRD8 ( 0x0100 ) +#define REG_PIN_CCIRD9 ( 0x0104 ) +#define REG_PIN_CCIRRST ( 0x0108 ) +#define REG_PIN_CCIRPD1 ( 0x010c ) +#define REG_PIN_CCIRPD0 ( 0x0110 ) +#define REG_PIN_SCL1 ( 0x0114 ) +#define REG_PIN_SDA1 ( 0x0118 ) +#define REG_PIN_KEYOUT0 ( 0x011c ) +#define REG_PIN_KEYOUT1 ( 0x0120 ) +#define REG_PIN_KEYOUT2 ( 0x0124 ) +#define REG_PIN_KEYOUT3 ( 0x0128 ) +#define REG_PIN_KEYOUT4 ( 0x012c ) +#define REG_PIN_KEYOUT5 ( 0x0130 ) +#define REG_PIN_GPIO135 ( 0x0134 ) +#define REG_PIN_GPIO136 ( 0x0138 ) +#define REG_PIN_GPIO137 ( 0x013c ) +#define REG_PIN_GPIO138 ( 0x0140 ) +#define REG_PIN_GPIO139 ( 0x0144 ) +#define REG_PIN_GPIO140 ( 0x0148 ) +#define REG_PIN_KEYOUT6 ( 0x014c ) +#define REG_PIN_KEYOUT7 ( 0x0150 ) +#define REG_PIN_KEYIN0 ( 0x0154 ) +#define REG_PIN_KEYIN1 ( 0x0158 ) +#define REG_PIN_KEYIN2 ( 0x015c ) +#define REG_PIN_KEYIN3 ( 0x0160 ) +#define REG_PIN_KEYIN4 ( 0x0164 ) +#define REG_PIN_KEYIN5 ( 0x0168 ) +#define REG_PIN_KEYIN6 ( 0x016c ) +#define REG_PIN_KEYIN7 ( 0x0170 ) +#define REG_PIN_NFWPN ( 0x0174 ) +#define REG_PIN_NFRB ( 0x0178 ) +#define REG_PIN_NFCLE ( 0x017c ) +#define REG_PIN_NFALE ( 0x0180 ) +#define REG_PIN_NFCEN ( 0x0184 ) +#define REG_PIN_NFREN ( 0x0188 ) +#define REG_PIN_NFWEN ( 0x018c ) +#define REG_PIN_NFD0 ( 0x0190 ) +#define REG_PIN_NFD1 ( 0x0194 ) +#define REG_PIN_NFD2 ( 0x0198 ) +#define REG_PIN_NFD3 ( 0x019c ) +#define REG_PIN_NFD4 ( 0x01a0 ) +#define REG_PIN_NFD5 ( 0x01a4 ) +#define REG_PIN_NFD6 ( 0x01a8 ) +#define REG_PIN_NFD7 ( 0x01ac ) +#define REG_PIN_NFD8 ( 0x01b0 ) +#define REG_PIN_NFD9 ( 0x01b4 ) +#define REG_PIN_NFD10 ( 0x01b8 ) +#define REG_PIN_NFD11 ( 0x01bc ) +#define REG_PIN_NFD12 ( 0x01c0 ) +#define REG_PIN_NFD13 ( 0x01c4 ) +#define REG_PIN_NFD14 ( 0x01c8 ) +#define REG_PIN_NFD15 ( 0x01cc ) +#define REG_PIN_SD3_CLK ( 0x01d0 ) +#define REG_PIN_SD3_CMD ( 0x01d4 ) +#define REG_PIN_SD3_D0 ( 0x01d8 ) +#define REG_PIN_SD3_D1 ( 0x01dc ) +#define REG_PIN_SD3_D2 ( 0x01e0 ) +#define REG_PIN_SD3_D3 ( 0x01e4 ) +#define REG_PIN_SD3_D4 ( 0x01e8 ) +#define REG_PIN_SD3_D5 ( 0x01ec ) +#define REG_PIN_SD3_D6 ( 0x01f0 ) +#define REG_PIN_SD3_D7 ( 0x01f4 ) +#define REG_PIN_EMMC_RST ( 0x01f8 ) +#define REG_PIN_SD1_CLK ( 0x01fc ) +#define REG_PIN_SD1_CMD ( 0x0200 ) +#define REG_PIN_SD1_D0 ( 0x0204 ) +#define REG_PIN_SD1_D1 ( 0x0208 ) +#define REG_PIN_SD1_D2 ( 0x020c ) +#define REG_PIN_SD1_D3 ( 0x0210 ) +#define REG_PIN_LCD_CSN1 ( 0x0214 ) +#define REG_PIN_LCD_RSTN ( 0x0218 ) +#define REG_PIN_LCD_CD ( 0x021c ) +#define REG_PIN_LCD_D0 ( 0x0220 ) +#define REG_PIN_LCD_D1 ( 0x0224 ) +#define REG_PIN_LCD_D2 ( 0x0228 ) +#define REG_PIN_LCD_D3 ( 0x022c ) +#define REG_PIN_LCD_D4 ( 0x0230 ) +#define REG_PIN_LCD_D5 ( 0x0234 ) +#define REG_PIN_LCD_D6 ( 0x0238 ) +#define REG_PIN_LCD_D7 ( 0x023c ) +#define REG_PIN_LCD_D8 ( 0x0240 ) +#define REG_PIN_LCD_WRN ( 0x0244 ) +#define REG_PIN_LCD_RDN ( 0x0248 ) +#define REG_PIN_LCD_CSN0 ( 0x024c ) +#define REG_PIN_LCD_D9 ( 0x0250 ) +#define REG_PIN_LCD_D10 ( 0x0254 ) +#define REG_PIN_LCD_D11 ( 0x0258 ) +#define REG_PIN_LCD_D12 ( 0x025c ) +#define REG_PIN_LCD_D13 ( 0x0260 ) +#define REG_PIN_LCD_D14 ( 0x0264 ) +#define REG_PIN_LCD_D15 ( 0x0268 ) +#define REG_PIN_LCD_D16 ( 0x026c ) +#define REG_PIN_LCD_D17 ( 0x0270 ) +#define REG_PIN_LCD_D18 ( 0x0274 ) +#define REG_PIN_LCD_D19 ( 0x0278 ) +#define REG_PIN_LCD_D20 ( 0x027c ) +#define REG_PIN_LCD_D21 ( 0x0280 ) +#define REG_PIN_LCD_D22 ( 0x0284 ) +#define REG_PIN_LCD_D23 ( 0x0288 ) +#define REG_PIN_LCD_FMARK ( 0x028c ) +#define REG_PIN_SPI2_CSN ( 0x0290 ) +#define REG_PIN_SPI2_DO ( 0x0294 ) +#define REG_PIN_SPI2_DI ( 0x0298 ) +#define REG_PIN_SPI2_CLK ( 0x029c ) +#define REG_PIN_SCL0 ( 0x02a0 ) +#define REG_PIN_SDA0 ( 0x02a4 ) +#define REG_PIN_SCL2 ( 0x02a8 ) +#define REG_PIN_SDA2 ( 0x02ac ) +#define REG_PIN_SCL3 ( 0x02b0 ) +#define REG_PIN_SDA3 ( 0x02b4 ) +#define REG_PIN_CLK_AUX0 ( 0x02b8 ) +#define REG_PIN_IIS0DI ( 0x02bc ) +#define REG_PIN_IIS0DO ( 0x02c0 ) +#define REG_PIN_IIS0CLK ( 0x02c4 ) +#define REG_PIN_IIS0LRCK ( 0x02c8 ) +#define REG_PIN_IIS0MCK ( 0x02cc ) +#define REG_PIN_SPI0_CSN ( 0x02d0 ) +#define REG_PIN_SPI0_DO ( 0x02d4 ) +#define REG_PIN_SPI0_DI ( 0x02d8 ) +#define REG_PIN_SPI0_CLK ( 0x02dc ) +#define REG_PIN_GPIO141 ( 0x02e0 ) +#define REG_PIN_GPIO142 ( 0x02e4 ) +#define REG_PIN_MTDO ( 0x02e8 ) + +#define REG_PIN_MTDI ( 0x02ec ) +#define REG_PIN_MTCK ( 0x02f0 ) +#define REG_PIN_MTMS ( 0x02f4 ) +#define REG_PIN_MTRST_N ( 0x02f8 ) +#define REG_PIN_TRACECLK ( 0x02fc ) +#define REG_PIN_TRACECTRL ( 0x0300 ) +#define REG_PIN_TRACEDAT0 ( 0x0304 ) +#define REG_PIN_TRACEDAT1 ( 0x0308 ) +#define REG_PIN_TRACEDAT2 ( 0x030c ) +#define REG_PIN_TRACEDAT3 ( 0x0310 ) +#define REG_PIN_TRACEDAT4 ( 0x0314 ) +#define REG_PIN_TRACEDAT5 ( 0x0318 ) +#define REG_PIN_TRACEDAT6 ( 0x031c ) +#define REG_PIN_TRACEDAT7 ( 0x0320 ) +#define REG_PIN_U0TXD ( 0x0324 ) +#define REG_PIN_U0RXD ( 0x0328 ) +#define REG_PIN_U0CTS ( 0x032c ) +#define REG_PIN_U0RTS ( 0x0330 ) +#define REG_PIN_U1TXD ( 0x0334 ) +#define REG_PIN_U1RXD ( 0x0338 ) +#define REG_PIN_U2TXD ( 0x033c ) +#define REG_PIN_U2RXD ( 0x0340 ) +#define REG_PIN_U2CTS ( 0x0344 ) +#define REG_PIN_U2RTS ( 0x0348 ) +#define REG_PIN_U3TXD ( 0x034c ) +#define REG_PIN_U3RXD ( 0x0350 ) +#define REG_PIN_U3CTS ( 0x0354 ) +#define REG_PIN_U3RTS ( 0x0358 ) +#define REG_PIN_CLK_REQ1 ( 0x035c ) +#define REG_PIN_CLK_REQ2 ( 0x0360 ) +#define REG_PIN_RFSDA0 ( 0x0364 ) +#define REG_PIN_RFSCK0 ( 0x0368 ) +#define REG_PIN_RFSEN0 ( 0x036c ) +#define REG_PIN_RFCTL0 ( 0x0370 ) +#define REG_PIN_RFCTL1 ( 0x0374 ) +#define REG_PIN_RFCTL2 ( 0x0378 ) +#define REG_PIN_RFCTL3 ( 0x037c ) + +#define REG_PIN_RFCTL4 ( 0x0380 ) +#define REG_PIN_RFCTL5 ( 0x0384 ) +#define REG_PIN_RFCTL6 ( 0x0388 ) +#define REG_PIN_RFCTL7 ( 0x038c ) +#define REG_PIN_RFCTL8 ( 0x0390 ) +#define REG_PIN_RFCTL9 ( 0x0394 ) +#define REG_PIN_RFCTL10 ( 0x0398 ) +#define REG_PIN_RFCTL11 ( 0x039c ) +#define REG_PIN_RFCTL12 ( 0x03a0 ) +#define REG_PIN_RFCTL13 ( 0x03a4 ) +#define REG_PIN_RFCTL14 ( 0x03a8 ) +#define REG_PIN_RFCTL15 ( 0x03ac ) +#define REG_PIN_XTL_EN ( 0x03b0 ) +#define REG_PIN_PTEST ( 0x03b4 ) +#define REG_PIN_GPIO143 ( 0x03b8 ) +#define REG_PIN_GPIO144 ( 0x03bc ) + + +/* bits definitions for register REG_PIN_XXX */ +#define BITS_PIN_DS(_x_) ( (_x_) << 19 & (BIT(19)|BIT(20)) ) +#define BITS_PIN_DS_3(_x_) ( (_x_) << 19 & (BIT(19)|BIT(20)|BIT(21)) ) +#define BITS_PIN_DS_4(_x_) ( (_x_) << 19 & (BIT(19)|BIT(20)|BIT(21)|BIT(22)) ) +#define BIT_PIN_SLP_AP ( BIT(13) ) +#define BIT_PIN_WPU ( BIT(7) ) +#define BIT_PIN_WPD ( BIT(6) ) +#define BITS_PIN_AF(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BIT_PIN_SLP_WPU ( BIT(3) ) +#define BIT_PIN_SLP_WPD ( BIT(2) ) +#define BIT_PIN_SLP_IE ( BIT(1) ) +#define BIT_PIN_SLP_OE ( BIT(0) ) + +/* vars definitions for controller CTL_PIN */ +#define BIT_PIN_NUL ( 0 ) +#define BIT_PIN_SLP_NUL ( 0 ) +#define BIT_PIN_SLP_Z ( 0 ) + + + + + + + + + + + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_pmu_apb_rf.h b/include/soc/sprd/chip_x35lt8/__regs_pmu_apb_rf.h new file mode 100755 index 00000000..02a30989 --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_pmu_apb_rf.h @@ -0,0 +1,1176 @@ +/* the head file modifier: g 2015-03-19 15:49:17*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +//#ifndef __SCI_GLB_REGS_H__ +//#error "Don't include this file directly, Pls include sci_glb_regs.h" +//#endif + + + + +#ifndef __H_REGS_PMU_APB_RF_HEADFILE_H__ +#define __H_REGS_PMU_APB_RF_HEADFILE_H__ __FILE__ + +#define REGS_PMU_APB_RF + +/* registers definitions for MM_AHB_RF */ +#define REG_PMU_APB_PD_CA53_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0000)/*PD_CA53_TOP_CFG*/ +#define REG_PMU_APB_PD_CA53_LIT_C0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0004)/*PD_CA53_LIT_C0_CFG*/ +#define REG_PMU_APB_PD_CA53_LIT_C1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0008)/*PD_CA53_LIT_C1_CFG*/ +#define REG_PMU_APB_PD_CA53_LIT_C2_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x000C)/*PD_CA53_LIT_C2_CFG*/ +#define REG_PMU_APB_PD_CA53_LIT_C3_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0010)/*PD_CA53_LIT_C3_CFG*/ +#define REG_PMU_APB_PD_CA53_LIT_MP4_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0014)/*PD_CA53_LIT_MP4_CFG*/ +#define REG_PMU_APB_PD_APCPU_TOP_CFG REG_PMU_APB_PD_CA53_TOP_CFG +#define REG_PMU_APB_PD_APCPU_LIT_C0_CFG REG_PMU_APB_PD_CA53_LIT_C0_CFG +#define REG_PMU_APB_PD_APCPU_LIT_C1_CFG REG_PMU_APB_PD_CA53_LIT_C1_CFG +#define REG_PMU_APB_PD_APCPU_LIT_C2_CFG REG_PMU_APB_PD_CA53_LIT_C2_CFG +#define REG_PMU_APB_PD_APCPU_LIT_C3_CFG REG_PMU_APB_PD_CA53_LIT_C3_CFG +#define REG_PMU_APB_PD_APCPU_LIT_MP4_CFG REG_PMU_APB_PD_CA53_LIT_MP4_CFG +#define REG_PMU_APB_PD_AP_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0018)/*PD_AP_SYS_CFG*/ +#define REG_PMU_APB_PD_MM_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x001C)/*PD_MM_TOP_CFG*/ +#define REG_PMU_APB_PD_GPU_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0020)/*PD_GPU_TOP_CFG*/ +#define REG_PMU_APB_PD_CP0_ARM9_0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0024)/*PD_CP0_ARM9_0_CFG*/ +#define REG_PMU_APB_PD_CP0_ARM9_1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0028)/*PD_CP0_ARM9_1_CFG*/ +#define REG_PMU_APB_PD_CP0_HU3GE_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x002C)/*PD_CP0_HU3GE_CFG*/ +#define REG_PMU_APB_PD_CP0_GSM_0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0030)/*PD_CP0_GSM_0_CFG*/ +#define REG_PMU_APB_PD_CP0_GSM_1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0034)/*PD_CP0_GSM_1_CFG*/ +#define REG_PMU_APB_PD_CP0_TD_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0038)/*PD_CP0_TD_CFG*/ +#define REG_PMU_APB_PD_CP0_CEVA_0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x003C)/*PD_CP0_CEVA_0_CFG*/ +#define REG_PMU_APB_PD_CP0_CEVA_1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0040)/*PD_CP0_CEVA_1_CFG*/ +#define REG_PMU_APB_PD_MM_CODEC_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0044)/*PD_MM_CODEC_CFG*/ +#define REG_PMU_APB_PD_CP1_CA5_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0048)/*PD_CP1_CA5_CFG*/ +#define REG_PMU_APB_PD_CP1_LTE_P1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x004C)/*PD_CP1_LTE_P1_CFG*/ +#define REG_PMU_APB_PD_CP1_LTE_P2_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0050)/*PD_CP1_LTE_P2_CFG*/ +#define REG_PMU_APB_PD_CP1_CEVA_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0054)/*PD_CP1_CEVA_CFG*/ +#define REG_PMU_APB_PD_CP1_COMWRAP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0058)/*PD_CP1_COMWRAP_CFG*/ +#define REG_PMU_APB_PD_PUB_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x005C)/*PD_PUB_SYS_CFG*/ +#define REG_PMU_APB_AP_WAKEUP_POR_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0060)/*AP_WAKEUP_POR_CFG*/ +#define REG_PMU_APB_PD_GPU_C0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0064)/*PD_GPU_C0_CFG*/ +#define REG_PMU_APB_PD_GPU_C1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0068)/*PD_GPU_C1_CFG*/ +#define REG_PMU_APB_XTL_WAIT_CNT SCI_ADDR(REGS_PMU_APB_BASE, 0x0070)/*XTL_WAIT_CNT*/ +#define REG_PMU_APB_XTLBUF_WAIT_CNT SCI_ADDR(REGS_PMU_APB_BASE, 0x0074)/*XTLBUF_WAIT_CNT*/ +#define REG_PMU_APB_PLL_WAIT_CNT1 SCI_ADDR(REGS_PMU_APB_BASE, 0x0078)/*PLL_WAIT_CNT1*/ +#define REG_PMU_APB_PLL_WAIT_CNT2 SCI_ADDR(REGS_PMU_APB_BASE, 0x007C)/*PLL_WAIT_CNT2*/ +#define REG_PMU_APB_XTL0_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0080)/*XTL0_REL_CFG*/ +#define REG_PMU_APB_XTL1_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0084)/*XTL1_REL_CFG*/ +#define REG_PMU_APB_PLL_PD_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0088)/*PLL_PD_CFG*/ +#define REG_PMU_APB_XTLBUF0_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x008C)/*XTLBUF0_REL_CFG*/ +#define REG_PMU_APB_XTLBUF1_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0090)/*XTLBUF1_REL_CFG*/ +#define REG_PMU_APB_MPLL0_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0094)/*MPLL0_REL_CFG*/ +#define REG_PMU_APB_DPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0098)/*DPLL_REL_CFG*/ +#define REG_PMU_APB_LTEPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x009C)/*LTEPLL_REL_CFG*/ +#define REG_PMU_APB_TWPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00A0)/*TWPLL_REL_CFG*/ +#define REG_PMU_APB_LVDSDIS_PLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00A4)/*LVDSDIS_PLL_REL_CFG*/ +#define REG_PMU_APB_MPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00A8)/*MPLL_REL_CFG*/ +#define REG_PMU_APB_GPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00AC)/*GPLL_REL_CFG*/ +#define REG_PMU_APB_CP_SOFT_RST SCI_ADDR(REGS_PMU_APB_BASE, 0x00B0)/*CP_SOFT_RST*/ +#define REG_PMU_APB_CP_SLP_STATUS_DBG0 SCI_ADDR(REGS_PMU_APB_BASE, 0x00B4)/*CP_SLP_STATUS_DBG0*/ +#define REG_PMU_APB_PWR_STATUS0_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00BC)/*PWR_STATUS0_DBG*/ +#define REG_PMU_APB_PWR_STATUS1_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00C0)/*PWR_STATUS1_DBG*/ +#define REG_PMU_APB_PWR_STATUS2_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00C4)/*PWR_STATUS2_DBG*/ +#define REG_PMU_APB_PWR_STATUS3_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00C8)/*PWR_STATUS3_DBG*/ +#define REG_PMU_APB_SLEEP_CTRL SCI_ADDR(REGS_PMU_APB_BASE, 0x00CC)/*SLEEP_CTRL*/ +#define REG_PMU_APB_DDR_SLEEP_CTRL SCI_ADDR(REGS_PMU_APB_BASE, 0x00D0)/*DDR_SLEEP_CTRL*/ +#define REG_PMU_APB_SLEEP_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x00D4)/*SLEEP_STATUS*/ +#define REG_PMU_APB_DDR_CHN_SLEEP_CTRL0 SCI_ADDR(REGS_PMU_APB_BASE, 0x00F8)/*DDR_CHN_SLEEP_CTRL0*/ +#define REG_PMU_APB_DDR_CHN_SLEEP_CTRL1 SCI_ADDR(REGS_PMU_APB_BASE, 0x00FC)/*DDR_CHN_SLEEP_CTRL1*/ +#define REG_PMU_APB_PD_CA53_BIG_C0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0100)/*PD_CA53_BIG_C0_CFG*/ +#define REG_PMU_APB_PD_CA53_BIG_C1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0104)/*PD_CA53_BIG_C1_CFG*/ +#define REG_PMU_APB_PD_CA53_BIG_C2_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0108)/*PD_CA53_BIG_C2_CFG*/ +#define REG_PMU_APB_PD_CA53_BIG_C3_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x010C)/*PD_CA53_BIG_C3_CFG*/ +#define REG_PMU_APB_PD_CA53_BIG_MP4_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0110)/*PD_CA53_BIG_MP4_CFG*/ +#define REG_PMU_APB_PD_APCPU_BIG_C0_CFG REG_PMU_APB_PD_CA53_BIG_C0_CFG +#define REG_PMU_APB_PD_APCPU_BIG_C1_CFG REG_PMU_APB_PD_CA53_BIG_C1_CFG +#define REG_PMU_APB_PD_APCPU_BIG_C2_CFG REG_PMU_APB_PD_CA53_BIG_C2_CFG +#define REG_PMU_APB_PD_APCPU_BIG_C3_CFG REG_PMU_APB_PD_CA53_BIG_C3_CFG +#define REG_PMU_APB_PD_APCPU_BIG_MP4_CFG REG_PMU_APB_PD_CA53_BIG_MP4_CFG +#define REG_PMU_APB_DDR_OP_MODE_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x012C)/*DDR_OP_MODE_CFG*/ +#define REG_PMU_APB_DDR_PHY_RET_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0130)/*DDR_PHY_RET_CFG*/ +#define REG_PMU_APB_26M_SEL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0134)/*26M_SEL_CFG*/ +#define REG_PMU_APB_R26M_SEL_CFG REG_PMU_APB_26M_SEL_CFG +#define REG_PMU_APB_BISR_DONE_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x0138)/*BISR_DONE_STATUS*/ +#define REG_PMU_APB_BISR_BUSY_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x013C)/*BISR_BUSY_STATUS*/ +#define REG_PMU_APB_BISR_BYP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0140)/*BISR_BYP_CFG*/ +#define REG_PMU_APB_BISR_EN_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0144)/*BISR_EN_CFG*/ +#define REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG0 SCI_ADDR(REGS_PMU_APB_BASE, 0x0148)/*CGM_AUTO_GATE_SEL_CFG0*/ +#define REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG1 SCI_ADDR(REGS_PMU_APB_BASE, 0x014C)/*CGM_AUTO_GATE_SEL_CFG1*/ +#define REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG2 SCI_ADDR(REGS_PMU_APB_BASE, 0x0150)/*CGM_AUTO_GATE_SEL_CFG2*/ +#define REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG3 SCI_ADDR(REGS_PMU_APB_BASE, 0x0154)/*CGM_AUTO_GATE_SEL_CFG3*/ +#define REG_PMU_APB_CGM_FORCE_EN_CFG0 SCI_ADDR(REGS_PMU_APB_BASE, 0x0158)/*CGM_FORCE_EN_CFG0*/ +#define REG_PMU_APB_CGM_FORCE_EN_CFG1 SCI_ADDR(REGS_PMU_APB_BASE, 0x015C)/*CGM_FORCE_EN_CFG1*/ +#define REG_PMU_APB_CGM_FORCE_EN_CFG2 SCI_ADDR(REGS_PMU_APB_BASE, 0x0160)/*CGM_FORCE_EN_CFG2*/ +#define REG_PMU_APB_CGM_FORCE_EN_CFG3 SCI_ADDR(REGS_PMU_APB_BASE, 0x0164)/*CGM_FORCE_EN_CFG3*/ +#define REG_PMU_APB_SLEEP_XTLON_CTRL SCI_ADDR(REGS_PMU_APB_BASE, 0x0168)/*SLEEP_XTLON_CTRL*/ +#define REG_PMU_APB_MEM_SLP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x016C)/*MEM_SLP_CFG*/ +#define REG_PMU_APB_MEM_SD_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0170)/*MEM_SD_CFG*/ +#define REG_PMU_APB_APCPU_CORE_PU_LOCK SCI_ADDR(REGS_PMU_APB_BASE, 0x0174)/*APCPU_CORE_PU_LOCK*/ +#define REG_PMU_APB_CA7_CORE_PU_LOCK REG_PMU_APB_APCPU_CORE_PU_LOCK +#define REG_PMU_APB_ARM7_HOLD_CGM_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0178)/*ARM7_HOLD_CGM_EN*/ +#define REG_PMU_APB_PWR_CNT_WAIT_CFG0 SCI_ADDR(REGS_PMU_APB_BASE, 0x017C)/*PWR_CNT_WAIT_CFG0*/ +#define REG_PMU_APB_PWR_CNT_WAIT_CFG1 SCI_ADDR(REGS_PMU_APB_BASE, 0x0180)/*PWR_CNT_WAIT_CFG1*/ +#define REG_PMU_APB_RC0_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0184)/*RC0_REL_CFG*/ +#define REG_PMU_APB_RC1_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0188)/*RC1_REL_CFG*/ +#define REG_PMU_APB_RC_CNT_WAIT_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x018C)/*RC_CNT_WAIT_CFG*/ +#define REG_PMU_APB_MEM_AUTO_SLP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0190)/*MEM_AUTO_SLP_CFG*/ +#define REG_PMU_APB_MEM_AUTO_SD_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0194)/*MEM_AUTO_SD_CFG*/ +#define REG_PMU_APB_CP0_PD_SHUTDOWN_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0198)/*CP0_PD_SHUTDOWN_CFG*/ +#define REG_PMU_APB_CP1_PD_SHUTDOWN_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x019C)/*CP1_PD_SHUTDOWN_CFG*/ +#define REG_PMU_APB_WAKEUP_LOCK_EN0 SCI_ADDR(REGS_PMU_APB_BASE, 0x01A0)/*WAKEUP_LOCK_EN0*/ +#define REG_PMU_APB_WAKEUP_LOCK_EN1 SCI_ADDR(REGS_PMU_APB_BASE, 0x01A4)/*WAKEUP_LOCK_EN1*/ +#define REG_PMU_APB_LP_AUTO_CTRL SCI_ADDR(REGS_PMU_APB_BASE, 0x01A8)/*LP_AUTO_CTRL*/ +#define REG_PMU_APB_CA53_LIT_C0_INT_DISABLE SCI_ADDR(REGS_PMU_APB_BASE, 0x01AC)/*CA53_LIT_C0_INT_DISABLE*/ +#define REG_PMU_APB_CA53_LIT_C1_INT_DISABLE SCI_ADDR(REGS_PMU_APB_BASE, 0x01B0)/*CA53_LIT_C1_INT_DISABLE*/ +#define REG_PMU_APB_CA53_LIT_C2_INT_DISABLE SCI_ADDR(REGS_PMU_APB_BASE, 0x01B4)/*CA53_LIT_C2_INT_DISABLE*/ +#define REG_PMU_APB_CA53_LIT_C3_INT_DISABLE SCI_ADDR(REGS_PMU_APB_BASE, 0x01B8)/*CA53_LIT_C3_INT_DISABLE*/ +#define REG_PMU_APB_CA53_BIG_C0_INT_DISABLE SCI_ADDR(REGS_PMU_APB_BASE, 0x01BC)/*CA53_BIG_C0_INT_DISABLE*/ +#define REG_PMU_APB_CA53_BIG_C1_INT_DISABLE SCI_ADDR(REGS_PMU_APB_BASE, 0x01C0)/*CA53_BIG_C1_INT_DISABLE*/ +#define REG_PMU_APB_CA53_BIG_C2_INT_DISABLE SCI_ADDR(REGS_PMU_APB_BASE, 0x01C4)/*CA53_BIG_C2_INT_DISABLE*/ +#define REG_PMU_APB_CA53_BIG_C3_INT_DISABLE SCI_ADDR(REGS_PMU_APB_BASE, 0x01C8)/*CA53_BIG_C3_INT_DISABLE*/ +#define REG_PMU_APB_APCPU_LIT_C0_INT_DISABLE REG_PMU_APB_CA53_LIT_C0_INT_DISABLE +#define REG_PMU_APB_APCPU_LIT_C1_INT_DISABLE REG_PMU_APB_CA53_LIT_C1_INT_DISABLE +#define REG_PMU_APB_APCPU_LIT_C2_INT_DISABLE REG_PMU_APB_CA53_LIT_C2_INT_DISABLE +#define REG_PMU_APB_APCPU_LIT_C3_INT_DISABLE REG_PMU_APB_CA53_LIT_C3_INT_DISABLE +#define REG_PMU_APB_APCPU_BIG_C0_INT_DISABLE REG_PMU_APB_CA53_BIG_C0_INT_DISABLE +#define REG_PMU_APB_APCPU_BIG_C1_INT_DISABLE REG_PMU_APB_CA53_BIG_C1_INT_DISABLE +#define REG_PMU_APB_APCPU_BIG_C2_INT_DISABLE REG_PMU_APB_CA53_BIG_C2_INT_DISABLE +#define REG_PMU_APB_APCPU_BIG_C3_INT_DISABLE REG_PMU_APB_CA53_BIG_C3_INT_DISABLE +#define REG_PMU_APB_PUB_ACC_RDY SCI_ADDR(REGS_PMU_APB_BASE, 0x01CC)/*PUB_ACC_RDY*/ +#define REG_PMU_APB_PUB_CLK_RDY SCI_ADDR(REGS_PMU_APB_BASE, 0x01D0)/*PUB_CLK_RDY*/ +#define REG_PMU_APB_PD_CA53_LIT_C0_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3000)/*PD_CA53_LITC0_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CA53_LIT_C1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3004)/*PD_CA53_LIT_C1_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CA53_LIT_C2_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3008)/*PD_CA53_LIT_C2_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CA53_LIT_C3_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x300C)/*PD_CA53_LIT_C3_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CA53_TOP_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3010)/*PD_CA53_TOP_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_AP_SYS_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3014)/*PD_AP_SYS_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_GPU_TOP_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3018)/*PD_GPU_TOP_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_MM_TOP_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x301C)/*PD_MM_TOP_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CP0_ARM9_0_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3020)/*PD_CP0_ARM9_0_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CP0_ARM9_1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3024)/*PD_CP0_ARM9_1_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CP0_CEVA_0_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3028)/*PD_CP0_CEVA_0_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CP0_CEVA_1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x302C)/*PD_CP0_CEVA_1_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CP0_GSM_0_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3030)/*PD_CP0_GSM_0_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CP0_GSM_1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3034)/*PD_CP0_GSM_1_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CP0_TD_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3038)/*PD_CP0_TD_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CP0_HU3GE_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x303C)/*PD_CP0_HU3GE_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CP1_CA5_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3040)/*PD_CP1_CA5_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CP1_CEVA_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3044)/*PD_CP1_CEVA_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CP1_LTE_P1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3048)/*PD_CP1_LTE_P1_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CP1_LTE_P2_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x304C)/*PD_CP1_LTE_P2_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CP1_COMWRAP_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3050)/*PD_CP1_COMWRAP_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_PUB_SYS_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3054)/*PD_PUB_SYS_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_GPU_C0_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3058)/*PD_GPU_C0_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_GPU_C1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x305C)/*PD_GPU_C1_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CA53_LIT_MP4_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3060)/*PD_CA53_LIT_MP4_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CA53_BIG_C0_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3064)/*PD_CA53_BIG_C0_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CA53_BIG_C1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3068)/*PD_CA53_BIG_C1_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CA53_BIG_C2_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x306C)/*PD_CA53_BIG_C2_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CA53_BIG_C3_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3070)/*PD_CA53_BIG_C3_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CA53_BIG_MP4_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3074)/*PD_CA53_BIG_MP4_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_APCPU_LIT_MP4_SHUTDOWN_MARK_STATUS REG_PMU_APB_PD_CA53_LIT_MP4_SHUTDOWN_MARK_STATUS +#define REG_PMU_APB_PD_APCPU_BIG_C0_SHUTDOWN_MARK_STATUS REG_PMU_APB_PD_CA53_BIG_C0_SHUTDOWN_MARK_STATUS +#define REG_PMU_APB_PD_APCPU_BIG_C1_SHUTDOWN_MARK_STATUS REG_PMU_APB_PD_CA53_BIG_C1_SHUTDOWN_MARK_STATUS +#define REG_PMU_APB_PD_APCPU_BIG_C2_SHUTDOWN_MARK_STATUS REG_PMU_APB_PD_CA53_BIG_C2_SHUTDOWN_MARK_STATUS +#define REG_PMU_APB_PD_APCPU_BIG_C3_SHUTDOWN_MARK_STATUS REG_PMU_APB_PD_CA53_BIG_C3_SHUTDOWN_MARK_STATUS +#define REG_PMU_APB_PD_APCPU_BIG_MP4_SHUTDOWN_MARK_STATUS REG_PMU_APB_PD_CA53_BIG_MP4_SHUTDOWN_MARK_STATUS +#define REG_PMU_APB_PD_MM_CODEC_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3078)/*PD_MM_CODEC_SHUTDOWN_MARK_STATUS*/ + + + +/* bits definitions for register REG_PMU_APB_PD_CA53_TOP_CFG */ +#define BIT_PD_CA53_TOP_PD_SEL ( BIT(29) ) +#define BIT_PD_CA53_TOP_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_PD_CA53_TOP_STOP_EN ( BIT(27) ) +#define BIT_PD_CA53_TOP_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA53_TOP_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BIT_PD_CA7_TOP_DBG_SHUTDOWN_EN BIT_PD_CA53_TOP_DBG_SHUTDOWN_EN +#define BIT_PD_CA7_TOP_STOP_EN BIT_PD_CA53_TOP_STOP_EN +#define BIT_PD_CA7_TOP_FORCE_SHUTDOWN BIT_PD_CA53_TOP_FORCE_SHUTDOWN +#define BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN BIT_PD_CA53_TOP_AUTO_SHUTDOWN_EN +#define BITS_PD_CA53_TOP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA53_TOP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA53_TOP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_LIT_C0_CFG */ +#define BIT_CA53_LIT_C0_WAKEUP_EN ( BIT(30) ) +#define BIT_PD_CA53_LIT_C0_PD_SEL ( BIT(29) ) +#define BIT_PD_CA53_LIT_C0_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_CA53_LIT_C0_DSLP_ENA ( BIT(27) ) +#define BIT_PD_CA53_LIT_C0_PWR_RST_CFG ( BIT(26) ) +#define BIT_PD_CA53_LIT_C0_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA53_LIT_C0_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CA53_LIT_C0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA53_LIT_C0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA53_LIT_C0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_LIT_C1_CFG */ +#define BIT_CA53_LIT_C1_WAKEUP_EN ( BIT(30) ) +#define BIT_PD_CA53_LIT_C1_PD_SEL ( BIT(29) ) +#define BIT_PD_CA53_LIT_C1_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_CA53_LIT_C1_DSLP_ENA ( BIT(27) ) +#define BIT_PD_CA53_LIT_C1_PWR_RST_CFG ( BIT(26) ) +#define BIT_PD_CA53_LIT_C1_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA53_LIT_C1_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CA53_LIT_C1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA53_LIT_C1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA53_LIT_C1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_LIT_C2_CFG */ +#define BIT_CA53_LIT_C2_WAKEUP_EN ( BIT(30) ) +#define BIT_PD_CA53_LIT_C2_PD_SEL ( BIT(29) ) +#define BIT_PD_CA53_LIT_C2_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_CA53_LIT_C2_DSLP_ENA ( BIT(27) ) +#define BIT_PD_CA53_LIT_C2_PWR_RST_CFG ( BIT(26) ) +#define BIT_PD_CA53_LIT_C2_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA53_LIT_C2_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CA53_LIT_C2_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA53_LIT_C2_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA53_LIT_C2_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_LIT_C3_CFG */ +#define BIT_CA53_LIT_C3_WAKEUP_EN ( BIT(30) ) +#define BIT_PD_CA53_LIT_C3_PD_SEL ( BIT(29) ) +#define BIT_PD_CA53_LIT_C3_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_CA53_LIT_C3_DSLP_ENA ( BIT(27) ) +#define BIT_PD_CA53_LIT_C3_PWR_RST_CFG ( BIT(26) ) +#define BIT_PD_CA53_LIT_C3_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA53_LIT_C3_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CA53_LIT_C3_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA53_LIT_C3_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA53_LIT_C3_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_LIT_MP4_CFG */ +#define BIT_CA53_LIT_MP4_WAKEUP_EN ( BIT(30) ) +#define BIT_PD_CA53_LIT_MP4_PD_SEL ( BIT(29) ) +#define BIT_PD_CA53_LIT_MP4_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_CA53_LIT_MP4_DSLP_ENA ( BIT(27) ) +#define BIT_PD_CA53_LIT_MP4_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA53_LIT_MP4_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CA53_LIT_MP4_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA53_LIT_MP4_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA53_LIT_MP4_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_AP_SYS_CFG */ +#define BIT_PD_AP_SYS_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_AP_SYS_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_AP_SYS_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_MM_TOP_CFG */ +#define BIT_PD_MM_TOP_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_MM_TOP_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_MM_TOP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_MM_TOP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_GPU_TOP_CFG */ +#define BIT_PD_GPU_TOP_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_GPU_TOP_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_GPU_TOP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_GPU_TOP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_0_CFG */ +#define BIT_PD_CP0_ARM9_0_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_ARM9_0_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_ARM9_0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_ARM9_0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_ARM9_0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_1_CFG */ +#define BIT_PD_CP0_ARM9_1_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_ARM9_1_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_ARM9_1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_ARM9_1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_ARM9_1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_HU3GE_CFG */ +#define BIT_PD_CP0_HU3GE_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_HU3GE_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_HU3GE_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_HU3GE_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_HU3GE_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_GSM_0_CFG */ +#define BIT_PD_CP0_GSM_0_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_GSM_0_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_GSM_0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_GSM_0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_GSM_0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_GSM_1_CFG */ +#define BIT_PD_CP0_GSM_1_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_GSM_1_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_GSM_1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_GSM_1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_GSM_1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_TD_CFG */ +#define BIT_PD_CP0_TD_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_TD_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_TD_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_TD_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_TD_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_CEVA_0_CFG */ +#define BIT_PD_CP0_CEVA_0_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_CEVA_0_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_CEVA_0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_CEVA_0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_CEVA_0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_CEVA_1_CFG */ +#define BIT_PD_CP0_CEVA_1_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_CEVA_1_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_CEVA_1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_CEVA_1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_CEVA_1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_MM_CODEC_CFG */ +#define BIT_PD_MM_CODEC_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_MM_CODEC_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_MM_CODEC_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_MM_CODEC_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_MM_CODEC_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_CA5_CFG */ +#define BIT_PD_CP1_CA5_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP1_CA5_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP1_CA5_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_CA5_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_CA5_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_LTE_P1_CFG */ +#define BIT_PD_CP1_LTE_P1_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP1_LTE_P1_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP1_LTE_P1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_LTE_P1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_LTE_P1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_LTE_P2_CFG */ +#define BIT_PD_CP1_LTE_P2_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP1_LTE_P2_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP1_LTE_P2_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_LTE_P2_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_LTE_P2_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_CEVA_CFG */ +#define BIT_PD_CP1_CEVA_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP1_CEVA_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP1_CEVA_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_CEVA_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_CEVA_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_COMWRAP_CFG */ +#define BIT_PD_CP1_COMWRAP_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP1_COMWRAP_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP1_COMWRAP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_COMWRAP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_COMWRAP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_PUB_SYS_CFG */ +#define BIT_PD_PUB_SYS_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_PUB_SYS_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_PUB_SYS_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_AP_WAKEUP_POR_CFG */ +#define BIT_AP_WAKEUP_POR_N ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_PD_GPU_C0_CFG */ +#define BIT_PD_GPU_C0_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_GPU_C0_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_GPU_C0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_GPU_C0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_GPU_C0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_GPU_C1_CFG */ +#define BIT_PD_GPU_C1_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_GPU_C1_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_GPU_C1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_GPU_C1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_GPU_C1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_XTL_WAIT_CNT */ +#define BITS_XTL1_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_XTL0_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_XTLBUF_WAIT_CNT */ +#define BITS_XTLBUF1_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_XTLBUF0_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PLL_WAIT_CNT1 */ +#define BITS_LTEPLL_WAIT_CNT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_TWPLL_WAIT_CNT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DPLL_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_MPLL0_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PLL_WAIT_CNT2 */ +#define BITS_GPLL_WAIT_CNT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_MPLL_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LVDSDIS_PLL_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_XTL0_REL_CFG */ +#define BIT_XTL0_ARM7_SEL ( BIT(5) ) +#define BIT_XTL0_VCP1_SEL ( BIT(4) ) +#define BIT_XTL0_VCP0_SEL ( BIT(3) ) +#define BIT_XTL0_CP1_SEL ( BIT(2) ) +#define BIT_XTL0_CP0_SEL ( BIT(1) ) +#define BIT_XTL0_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_XTL1_REL_CFG */ +#define BIT_XTL1_ARM7_SEL ( BIT(5) ) +#define BIT_XTL1_VCP1_SEL ( BIT(4) ) +#define BIT_XTL1_VCP0_SEL ( BIT(3) ) +#define BIT_XTL1_CP1_SEL ( BIT(2) ) +#define BIT_XTL1_CP0_SEL ( BIT(1) ) +#define BIT_XTL1_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_PLL_PD_CFG */ +#define BIT_MPLL_FORCE_PD ( BIT(2) ) +#define BIT_USBPLL_PD ( BIT(1) ) +#define BIT_GPLL_PD ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_XTLBUF0_REL_CFG */ +#define BIT_XTLBUF0_ARM7_SEL ( BIT(5) ) +#define BIT_XTLBUF0_VCP1_SEL ( BIT(4) ) +#define BIT_XTLBUF0_VCP0_SEL ( BIT(3) ) +#define BIT_XTLBUF0_CP1_SEL ( BIT(2) ) +#define BIT_XTLBUF0_CP0_SEL ( BIT(1) ) +#define BIT_XTLBUF0_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_XTLBUF1_REL_CFG */ +#define BIT_XTLBUF1_ARM7_SEL ( BIT(5) ) +#define BIT_XTLBUF1_VCP1_SEL ( BIT(4) ) +#define BIT_XTLBUF1_VCP0_SEL ( BIT(3) ) +#define BIT_XTLBUF1_CP1_SEL ( BIT(2) ) +#define BIT_XTLBUF1_CP0_SEL ( BIT(1) ) +#define BIT_XTLBUF1_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_MPLL0_REL_CFG */ +#define BIT_MPLL0_REF_SEL ( BIT(8) ) +#define BIT_MPLL0_ARM7_SEL ( BIT(5) ) +#define BIT_MPLL0_VCP1_SEL ( BIT(4) ) +#define BIT_MPLL0_VCP0_SEL ( BIT(3) ) +#define BIT_MPLL0_CP1_SEL ( BIT(2) ) +#define BIT_MPLL0_CP0_SEL ( BIT(1) ) +#define BIT_MPLL0_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_DPLL_REL_CFG */ +#define BIT_DPLL_REF_SEL ( BIT(8) ) +#define BIT_DPLL_ARM7_SEL ( BIT(5) ) +#define BIT_DPLL_VCP1_SEL ( BIT(4) ) +#define BIT_DPLL_VCP0_SEL ( BIT(3) ) +#define BIT_DPLL_CP1_SEL ( BIT(2) ) +#define BIT_DPLL_CP0_SEL ( BIT(1) ) +#define BIT_DPLL_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_LTEPLL_REL_CFG */ +#define BIT_LTEPLL_REF_SEL ( BIT(8) ) +#define BIT_LTEPLL_ARM7_SEL ( BIT(5) ) +#define BIT_LTEPLL_VCP1_SEL ( BIT(4) ) +#define BIT_LTEPLL_VCP0_SEL ( BIT(3) ) +#define BIT_LTEPLL_CP1_SEL ( BIT(2) ) +#define BIT_LTEPLL_CP0_SEL ( BIT(1) ) +#define BIT_LTEPLL_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_TWPLL_REL_CFG */ +#define BIT_TWPLL_REF_SEL ( BIT(8) ) +#define BIT_TWPLL_ARM7_SEL ( BIT(5) ) +#define BIT_TWPLL_VCP1_SEL ( BIT(4) ) +#define BIT_TWPLL_VCP0_SEL ( BIT(3) ) +#define BIT_TWPLL_CP1_SEL ( BIT(2) ) +#define BIT_TWPLL_CP0_SEL ( BIT(1) ) +#define BIT_TWPLL_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_LVDSDIS_PLL_REL_CFG */ +#define BIT_LVDSDIS_PLL_REF_SEL ( BIT(8) ) +#define BIT_LVDSDIS_PLL_ARM7_SEL ( BIT(5) ) +#define BIT_LVDSDIS_PLL_VCP1_SEL ( BIT(4) ) +#define BIT_LVDSDIS_PLL_VCP0_SEL ( BIT(3) ) +#define BIT_LVDSDIS_PLL_CP1_SEL ( BIT(2) ) +#define BIT_LVDSDIS_PLL_CP0_SEL ( BIT(1) ) +#define BIT_LVDSDIS_PLL_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_MPLL_REL_CFG */ +#define BIT_MPLL_REF_SEL ( BIT(8) ) +#define BIT_MPLL_ARM7_SEL ( BIT(5) ) +#define BIT_MPLL_VCP1_SEL ( BIT(4) ) +#define BIT_MPLL_VCP0_SEL ( BIT(3) ) +#define BIT_MPLL_CP1_SEL ( BIT(2) ) +#define BIT_MPLL_CP0_SEL ( BIT(1) ) +#define BIT_MPLL_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_GPLL_REL_CFG */ +#define BIT_GPLL_REF_SEL ( BIT(8) ) + +/* bits definitions for register REG_PMU_APB_CP_SOFT_RST */ +#define BIT_ARM7_SOFT_RST ( BIT(8) ) +#define BIT_PUB_SOFT_RST ( BIT(6) ) +#define BIT_AP_SOFT_RST ( BIT(5) ) +#define BIT_GPU_SOFT_RST ( BIT(4) ) +#define BIT_MM_SOFT_RST ( BIT(3) ) +#define BIT_CP1_SOFT_RST ( BIT(1) ) +#define BIT_CP0_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CP_SLP_STATUS_DBG0 */ +#define BITS_CP1_DEEP_SLP_DBG(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_CP0_DEEP_SLP_DBG(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_PMU_APB_PWR_STATUS0_DBG */ +#define BITS_PD_MM_TOP_STATE(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_PD_GPU_TOP_STATE(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_PD_AP_SYS_STATE(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA53_LIT_C3_STATE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_PD_CA53_LIT_C2_STATE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA53_LIT_C1_STATE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_PD_CA53_LIT_C0_STATE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_PD_CA53_TOP_STATE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PWR_STATUS1_DBG */ +#define BITS_PD_CP0_CEVA_1_STATE(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_PD_CP0_CEVA_0_STATE(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_PD_CP0_GSM_0_STATE(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_GSM_1_STATE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_PD_CP0_HU3GE_STATE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_ARM9_1_STATE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_PD_CP0_ARM9_0_STATE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_PD_CP0_TD_STATE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PWR_STATUS2_DBG */ +#define BITS_PD_PUB_SYS_STATE(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_PD_CP1_COMWRAP_STATE(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_LTE_P2_STATE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_PD_CP1_LTE_P1_STATE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_CEVA_STATE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_PD_CP1_CA5_STATE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_PD_CA53_LIT_MP4_STATE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PWR_STATUS3_DBG */ +#define BITS_PD_MM_CODEC_STATE(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_PD_CA53_BIG_C3_STATE(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_PD_CA53_BIG_C2_STATE(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA53_BIG_C1_STATE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_PD_CA53_BIG_C0_STATE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA53_BIG_MP4_STATE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_PD_GPU_C1_STATE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_PD_GPU_C0_STATE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_SLEEP_CTRL */ +#define BIT_VCP1_FORCE_LIGHT_SLEEP ( BIT(28) ) +#define BIT_VCP0_FORCE_LIGHT_SLEEP ( BIT(27) ) +#define BIT_CP1_FORCE_LIGHT_SLEEP ( BIT(26) ) +#define BIT_CP0_FORCE_LIGHT_SLEEP ( BIT(25) ) +#define BIT_AP_FORCE_LIGHT_SLEEP ( BIT(24) ) +#define BIT_ARM7_FORCE_DEEP_SLEEP ( BIT(21) ) +#define BIT_VCP1_FORCE_DEEP_SLEEP ( BIT(20) ) +#define BIT_VCP0_FORCE_DEEP_SLEEP ( BIT(19) ) +#define BIT_CP1_FORCE_DEEP_SLEEP ( BIT(18) ) +#define BIT_CP0_FORCE_DEEP_SLEEP ( BIT(17) ) +#define BIT_AP_FORCE_DEEP_SLEEP ( BIT(16) ) +#define BIT_VCP1_LIGHT_SLEEP ( BIT(12) ) +#define BIT_VCP0_LIGHT_SLEEP ( BIT(11) ) +#define BIT_CP1_LIGHT_SLEEP ( BIT(10) ) +#define BIT_CP0_LIGHT_SLEEP ( BIT(9) ) +#define BIT_AP_LIGHT_SLEEP ( BIT(8) ) +#define BIT_VCP1_DEEP_SLEEP ( BIT(4) ) +#define BIT_VCP0_DEEP_SLEEP ( BIT(3) ) +#define BIT_CP1_DEEP_SLEEP ( BIT(2) ) +#define BIT_CP0_DEEP_SLEEP ( BIT(1) ) +#define BIT_AP_DEEP_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_DDR_SLEEP_CTRL */ +#define BIT_BUSY_TRANSFER_HWDATA_SEL ( BIT(16) ) +#define BIT_DDR_PUBL_APB_SOFT_RST ( BIT(12) ) +#define BIT_DDR_UMCTL_APB_SOFT_RST ( BIT(11) ) +#define BIT_DDR_PUBL_SOFT_RST ( BIT(10) ) +#define BIT_DDR_PHY_SOFT_RST ( BIT(8) ) +#define BIT_DDR_PHY_AUTO_GATE_EN ( BIT(6) ) +#define BIT_DDR_PUBL_AUTO_GATE_EN ( BIT(5) ) +#define BIT_DDR_UMCTL_AUTO_GATE_EN ( BIT(4) ) +#define BIT_DDR_PHY_EB ( BIT(2) ) +#define BIT_DDR_UMCTL_EB ( BIT(1) ) +#define BIT_DDR_PUBL_EB ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_SLEEP_STATUS */ +#define BITS_ARM7_SLP_STATUS(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_VCP1_SLP_STATUS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_VCP0_SLP_STATUS(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_CP1_SLP_STATUS(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CP0_SLP_STATUS(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_AP_SLP_STATUS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_DDR_CHN_SLEEP_CTRL0 */ +#define BIT_DDR_CTRL_AXI_LP_EN ( BIT(31) ) +#define BIT_DDR_CTRL_CGM_SEL ( BIT(30) ) +#define BIT_DDR_CHN9_AXI_LP_EN ( BIT(25) ) +#define BIT_DDR_CHN8_AXI_LP_EN ( BIT(24) ) +#define BIT_DDR_CHN7_AXI_LP_EN ( BIT(23) ) +#define BIT_DDR_CHN6_AXI_LP_EN ( BIT(22) ) +#define BIT_DDR_CHN5_AXI_LP_EN ( BIT(21) ) +#define BIT_DDR_CHN4_AXI_LP_EN ( BIT(20) ) +#define BIT_DDR_CHN3_AXI_LP_EN ( BIT(19) ) +#define BIT_DDR_CHN2_AXI_LP_EN ( BIT(18) ) +#define BIT_DDR_CHN1_AXI_LP_EN ( BIT(17) ) +#define BIT_DDR_CHN0_AXI_LP_EN ( BIT(16) ) +#define BIT_DDR_CHN9_CGM_SEL ( BIT(9) ) +#define BIT_DDR_CHN8_CGM_SEL ( BIT(8) ) +#define BIT_DDR_CHN7_CGM_SEL ( BIT(7) ) +#define BIT_DDR_CHN6_CGM_SEL ( BIT(6) ) +#define BIT_DDR_CHN5_CGM_SEL ( BIT(5) ) +#define BIT_DDR_CHN4_CGM_SEL ( BIT(4) ) +#define BIT_DDR_CHN3_CGM_SEL ( BIT(3) ) +#define BIT_DDR_CHN2_CGM_SEL ( BIT(2) ) +#define BIT_DDR_CHN1_CGM_SEL ( BIT(1) ) +#define BIT_DDR_CHN0_CGM_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_DDR_CHN_SLEEP_CTRL1 */ +#define BIT_DDR_CHN9_AXI_STOP_SEL ( BIT(9) ) +#define BIT_DDR_CHN8_AXI_STOP_SEL ( BIT(8) ) +#define BIT_DDR_CHN7_AXI_STOP_SEL ( BIT(7) ) +#define BIT_DDR_CHN6_AXI_STOP_SEL ( BIT(6) ) +#define BIT_DDR_CHN5_AXI_STOP_SEL ( BIT(5) ) +#define BIT_DDR_CHN4_AXI_STOP_SEL ( BIT(4) ) +#define BIT_DDR_CHN3_AXI_STOP_SEL ( BIT(3) ) +#define BIT_DDR_CHN2_AXI_STOP_SEL ( BIT(2) ) +#define BIT_DDR_CHN1_AXI_STOP_SEL ( BIT(1) ) +#define BIT_DDR_CHN0_AXI_STOP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_BIG_C0_CFG */ +#define BIT_CA53_BIG_C0_WAKEUP_EN ( BIT(30) ) +#define BIT_PD_CA53_BIG_C0_PD_SEL ( BIT(29) ) +#define BIT_PD_CA53_BIG_C0_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_CA53_BIG_C0_DSLP_ENA ( BIT(27) ) +#define BIT_PD_CA53_BIG_C0_PWR_RST_CFG ( BIT(26) ) +#define BIT_PD_CA53_BIG_C0_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA53_BIG_C0_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CA53_BIG_C0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA53_BIG_C0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA53_BIG_C0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_BIG_C1_CFG */ +#define BIT_CA53_BIG_C1_WAKEUP_EN ( BIT(30) ) +#define BIT_PD_CA53_BIG_C1_PD_SEL ( BIT(29) ) +#define BIT_PD_CA53_BIG_C1_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_CA53_BIG_C1_DSLP_ENA ( BIT(27) ) +#define BIT_PD_CA53_BIG_C1_PWR_RST_CFG ( BIT(26) ) +#define BIT_PD_CA53_BIG_C1_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA53_BIG_C1_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CA53_BIG_C1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA53_BIG_C1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA53_BIG_C1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_BIG_C2_CFG */ +#define BIT_CA53_BIG_C2_WAKEUP_EN ( BIT(30) ) +#define BIT_PD_CA53_BIG_C2_PD_SEL ( BIT(29) ) +#define BIT_PD_CA53_BIG_C2_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_CA53_BIG_C2_DSLP_ENA ( BIT(27) ) +#define BIT_PD_CA53_BIG_C2_PWR_RST_CFG ( BIT(26) ) +#define BIT_PD_CA53_BIG_C2_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA53_BIG_C2_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CA53_BIG_C2_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA53_BIG_C2_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA53_BIG_C2_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_BIG_C3_CFG */ +#define BIT_CA53_BIG_C3_WAKEUP_EN ( BIT(30) ) +#define BIT_PD_CA53_BIG_C3_PD_SEL ( BIT(29) ) +#define BIT_PD_CA53_BIG_C3_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_CA53_BIG_C3_DSLP_ENA ( BIT(27) ) +#define BIT_PD_CA53_BIG_C3_PWR_RST_CFG ( BIT(26) ) +#define BIT_PD_CA53_BIG_C3_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA53_BIG_C3_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CA53_BIG_C3_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA53_BIG_C3_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA53_BIG_C3_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_BIG_MP4_CFG */ +#define BIT_CA53_BIG_MP4_WAKEUP_EN ( BIT(30) ) +#define BIT_PD_CA53_BIG_MP4_PD_SEL ( BIT(29) ) +#define BIT_PD_CA53_BIG_MP4_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_CA53_BIG_MP4_DSLP_ENA ( BIT(27) ) +#define BIT_PD_CA53_BIG_MP4_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA53_BIG_MP4_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CA53_BIG_MP4_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA53_BIG_MP4_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA53_BIG_MP4_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_DDR_OP_MODE_CFG */ +#define BIT_DDR_OPERATE_MODE_BUSY ( BIT(28) ) +#define BIT_DDR_PUBL_RET_EN ( BIT(27) ) +#define BIT_DDR_PHY_ISO_RST_EN ( BIT(26) ) +#define BIT_DDR_UMCTL_RET_EN ( BIT(25) ) +#define BIT_DDR_PHY_AUTO_RET_EN ( BIT(24) ) +#define BITS_DDR_OPERATE_MODE_CNT_LMT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DDR_OPERATE_MODE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_DDR_OPERATE_MODE_IDLE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_PMU_APB_DDR_PHY_RET_CFG */ +#define BIT_DDR_UMCTL_SOFT_RST ( BIT(16) ) +#define BIT_DDR_PHY_CKE_RET_EN ( BIT(0) ) +#define BIT_DDR_PHY_CKE_RET_EN BIT_DDR_PHY_CKE_RET_EN + +/* bits definitions for register REG_PMU_APB_26M_SEL_CFG */ +#define BIT_AON_RC_4M_SEL ( BIT(8) ) +#define BIT_GGE_26M_SEL ( BIT(6) ) +#define BIT_PUB_26M_SEL ( BIT(5) ) +#define BIT_AON_26M_SEL ( BIT(4) ) +#define BIT_CP1_26M_SEL ( BIT(2) ) +#define BIT_CP0_26M_SEL ( BIT(1) ) +#define BIT_AP_26M_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_BISR_DONE_STATUS */ +#define BIT_PD_MM_CODEC_BISR_DONE ( BIT(29) ) +#define BIT_PD_CA53_BIG_MP4_BISR_DONE ( BIT(28) ) +#define BIT_PD_CA53_BIG_C3_BISR_DONE ( BIT(27) ) +#define BIT_PD_CA53_BIG_C2_BISR_DONE ( BIT(26) ) +#define BIT_PD_CA53_BIG_C1_BISR_DONE ( BIT(25) ) +#define BIT_PD_CA53_BIG_C0_BISR_DONE ( BIT(24) ) +#define BIT_PD_GPU_C1_BISR_DONE ( BIT(23) ) +#define BIT_PD_GPU_C0_BISR_DONE ( BIT(22) ) +#define BIT_PD_CP1_COMWRAP_BISR_DONE ( BIT(21) ) +#define BIT_PD_CP1_LTE_P2_BISR_DONE ( BIT(20) ) +#define BIT_PD_CP1_LTE_P1_BISR_DONE ( BIT(19) ) +#define BIT_PD_CP1_CEVA_BISR_DONE ( BIT(18) ) +#define BIT_PD_CP1_CA5_BISR_DONE ( BIT(17) ) +#define BIT_PD_CA53_LIT_MP4_BISR_DONE ( BIT(16) ) +#define BIT_PD_CP0_HU3GE_BISR_DONE ( BIT(15) ) +#define BIT_PD_CP0_TD_BISR_DONE ( BIT(14) ) +#define BIT_PD_CP0_GSM_1_BISR_DONE ( BIT(13) ) +#define BIT_PD_CP0_GSM_0_BISR_DONE ( BIT(12) ) +#define BIT_PD_CP0_CEVA_1_BISR_DONE ( BIT(11) ) +#define BIT_PD_CP0_CEVA_0_BISR_DONE ( BIT(10) ) +#define BIT_PD_CP0_ARM9_1_BISR_DONE ( BIT(9) ) +#define BIT_PD_CP0_ARM9_0_BISR_DONE ( BIT(8) ) +#define BIT_PD_MM_TOP_BISR_DONE ( BIT(7) ) +#define BIT_PD_GPU_TOP_BISR_DONE ( BIT(6) ) +#define BIT_PD_AP_SYS_BISR_DONE ( BIT(5) ) +#define BIT_PD_CA53_TOP_BISR_DONE ( BIT(4) ) +#define BIT_PD_CA53_LIT_C3_BISR_DONE ( BIT(3) ) +#define BIT_PD_CA53_LIT_C2_BISR_DONE ( BIT(2) ) +#define BIT_PD_CA53_LIT_C1_BISR_DONE ( BIT(1) ) +#define BIT_PD_CA53_LIT_C0_BISR_DONE ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_BISR_BUSY_STATUS */ +#define BIT_PD_MM_CODEC_BISR_BUSY ( BIT(29) ) +#define BIT_PD_CA53_BIG_MP4_BISR_BUSY ( BIT(28) ) +#define BIT_PD_CA53_BIG_C3_BISR_BUSY ( BIT(27) ) +#define BIT_PD_CA53_BIG_C2_BISR_BUSY ( BIT(26) ) +#define BIT_PD_CA53_BIG_C1_BISR_BUSY ( BIT(25) ) +#define BIT_PD_CA53_BIG_C0_BISR_BUSY ( BIT(24) ) +#define BIT_PD_GPU_C1_BISR_BUSY ( BIT(23) ) +#define BIT_PD_GPU_C0_BISR_BUSY ( BIT(22) ) +#define BIT_PD_CP1_COMWRAP_BISR_BUSY ( BIT(21) ) +#define BIT_PD_CP1_LTE_P2_BISR_BUSY ( BIT(20) ) +#define BIT_PD_CP1_LTE_P1_BISR_BUSY ( BIT(19) ) +#define BIT_PD_CP1_CEVA_BISR_BUSY ( BIT(18) ) +#define BIT_PD_CP1_CA5_BISR_BUSY ( BIT(17) ) +#define BIT_PD_CA53_LIT_MP4_BISR_BUSY ( BIT(16) ) +#define BIT_PD_CP0_HU3GE_BISR_BUSY ( BIT(15) ) +#define BIT_PD_CP0_TD_BISR_BUSY ( BIT(14) ) +#define BIT_PD_CP0_GSM_1_BISR_BUSY ( BIT(13) ) +#define BIT_PD_CP0_GSM_0_BISR_BUSY ( BIT(12) ) +#define BIT_PD_CP0_CEVA_1_BISR_BUSY ( BIT(11) ) +#define BIT_PD_CP0_CEVA_0_BISR_BUSY ( BIT(10) ) +#define BIT_PD_CP0_ARM9_1_BISR_BUSY ( BIT(9) ) +#define BIT_PD_CP0_ARM9_0_BISR_BUSY ( BIT(8) ) +#define BIT_PD_MM_TOP_BISR_BUSY ( BIT(7) ) +#define BIT_PD_GPU_TOP_BISR_BUSY ( BIT(6) ) +#define BIT_PD_AP_SYS_BISR_BUSY ( BIT(5) ) +#define BIT_PD_CA53_TOP_BISR_BUSY ( BIT(4) ) +#define BIT_PD_CA53_LIT_C3_BISR_BUSY ( BIT(3) ) +#define BIT_PD_CA53_LIT_C2_BISR_BUSY ( BIT(2) ) +#define BIT_PD_CA53_LIT_C1_BISR_BUSY ( BIT(1) ) +#define BIT_PD_CA53_LIT_C0_BISR_BUSY ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_BISR_BYP_CFG */ +#define BIT_PD_MM_CODEC_BISR_FORCE_BYP ( BIT(29) ) +#define BIT_PD_CA53_BIG_MP4_BISR_FORCE_BYP ( BIT(28) ) +#define BIT_PD_CA53_BIG_C3_BISR_FORCE_BYP ( BIT(27) ) +#define BIT_PD_CA53_BIG_C2_BISR_FORCE_BYP ( BIT(26) ) +#define BIT_PD_CA53_BIG_C1_BISR_FORCE_BYP ( BIT(25) ) +#define BIT_PD_CA53_BIG_C0_BISR_FORCE_BYP ( BIT(24) ) +#define BIT_PD_GPU_C1_BISR_FORCE_BYP ( BIT(23) ) +#define BIT_PD_GPU_C0_BISR_FORCE_BYP ( BIT(22) ) +#define BIT_PD_CP1_COMWRAP_BISR_FORCE_BYP ( BIT(21) ) +#define BIT_PD_CP1_LTE_P2_BISR_FORCE_BYP ( BIT(20) ) +#define BIT_PD_CP1_LTE_P1_BISR_FORCE_BYP ( BIT(19) ) +#define BIT_PD_CP1_CEVA_BISR_FORCE_BYP ( BIT(18) ) +#define BIT_PD_CP1_CA5_BISR_FORCE_BYP ( BIT(17) ) +#define BIT_PD_CA53_LIT_MP4_BISR_FORCE_BYP ( BIT(16) ) +#define BIT_PD_CP0_HU3GE_BISR_FORCE_BYP ( BIT(15) ) +#define BIT_PD_CP0_TD_BISR_FORCE_BYP ( BIT(14) ) +#define BIT_PD_CP0_GSM_1_BISR_FORCE_BYP ( BIT(13) ) +#define BIT_PD_CP0_GSM_0_BISR_FORCE_BYP ( BIT(12) ) +#define BIT_PD_CP0_CEVA_1_BISR_FORCE_BYP ( BIT(11) ) +#define BIT_PD_CP0_CEVA_0_BISR_FORCE_BYP ( BIT(10) ) +#define BIT_PD_CP0_ARM9_1_BISR_FORCE_BYP ( BIT(9) ) +#define BIT_PD_CP0_ARM9_0_BISR_FORCE_BYP ( BIT(8) ) +#define BIT_PD_MM_TOP_BISR_FORCE_BYP ( BIT(7) ) +#define BIT_PD_GPU_TOP_BISR_FORCE_BYP ( BIT(6) ) +#define BIT_PD_AP_SYS_BISR_FORCE_BYP ( BIT(5) ) +#define BIT_PD_CA53_TOP_BISR_FORCE_BYP ( BIT(4) ) +#define BIT_PD_CA53_LIT_C3_BISR_FORCE_BYP ( BIT(3) ) +#define BIT_PD_CA53_LIT_C2_BISR_FORCE_BYP ( BIT(2) ) +#define BIT_PD_CA53_LIT_C1_BISR_FORCE_BYP ( BIT(1) ) +#define BIT_PD_CA53_LIT_C0_BISR_FORCE_BYP ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_BISR_EN_CFG */ +#define BIT_PD_MM_CODEC_BISR_FORCE_EN ( BIT(29) ) +#define BIT_PD_CA53_BIG_MP4_BISR_FORCE_EN ( BIT(28) ) +#define BIT_PD_CA53_BIG_C3_BISR_FORCE_EN ( BIT(27) ) +#define BIT_PD_CA53_BIG_C2_BISR_FORCE_EN ( BIT(26) ) +#define BIT_PD_CA53_BIG_C1_BISR_FORCE_EN ( BIT(25) ) +#define BIT_PD_CA53_BIG_C0_BISR_FORCE_EN ( BIT(24) ) +#define BIT_PD_GPU_C1_BISR_FORCE_EN ( BIT(23) ) +#define BIT_PD_GPU_C0_BISR_FORCE_EN ( BIT(22) ) +#define BIT_PD_CP1_COMWRAP_BISR_FORCE_EN ( BIT(21) ) +#define BIT_PD_CP1_LTE_P2_BISR_FORCE_EN ( BIT(20) ) +#define BIT_PD_CP1_LTE_P1_BISR_FORCE_EN ( BIT(19) ) +#define BIT_PD_CP1_CEVA_BISR_FORCE_EN ( BIT(18) ) +#define BIT_PD_CP1_CA5_BISR_FORCE_EN ( BIT(17) ) +#define BIT_PD_CA53_LIT_MP4_BISR_FORCE_EN ( BIT(16) ) +#define BIT_PD_CP0_HU3GE_BISR_FORCE_EN ( BIT(15) ) +#define BIT_PD_CP0_TD_BISR_FORCE_EN ( BIT(14) ) +#define BIT_PD_CP0_GSM_1_BISR_FORCE_EN ( BIT(13) ) +#define BIT_PD_CP0_GSM_0_BISR_FORCE_EN ( BIT(12) ) +#define BIT_PD_CP0_CEVA_1_BISR_FORCE_EN ( BIT(11) ) +#define BIT_PD_CP0_CEVA_0_BISR_FORCE_EN ( BIT(10) ) +#define BIT_PD_CP0_ARM9_1_BISR_FORCE_EN ( BIT(9) ) +#define BIT_PD_CP0_ARM9_0_BISR_FORCE_EN ( BIT(8) ) +#define BIT_PD_MM_TOP_BISR_FORCE_EN ( BIT(7) ) +#define BIT_PD_GPU_TOP_BISR_FORCE_EN ( BIT(6) ) +#define BIT_PD_AP_SYS_BISR_FORCE_EN ( BIT(5) ) +#define BIT_PD_CA53_TOP_BISR_FORCE_EN ( BIT(4) ) +#define BIT_PD_CA53_LIT_C3_BISR_FORCE_EN ( BIT(3) ) +#define BIT_PD_CA53_LIT_C2_BISR_FORCE_EN ( BIT(2) ) +#define BIT_PD_CA53_LIT_C1_BISR_FORCE_EN ( BIT(1) ) +#define BIT_PD_CA53_LIT_C0_BISR_FORCE_EN ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG0 */ +#define BITS_CGM_AUTO_GATE_SEL_CFG0(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG1 */ +#define BITS_CGM_AUTO_GATE_SEL_CFG1(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG2 */ +#define BITS_CGM_AUTO_GATE_SEL_CFG2(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG3 */ +#define BITS_CGM_AUTO_GATE_SEL_CFG3(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CGM_FORCE_EN_CFG0 */ +#define BITS_CGM_FORCE_EN_CFG0(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CGM_FORCE_EN_CFG1 */ +#define BITS_CGM_FORCE_EN_CFG1(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CGM_FORCE_EN_CFG2 */ +#define BITS_CGM_FORCE_EN_CFG2(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CGM_FORCE_EN_CFG3 */ +#define BITS_CGM_FORCE_EN_CFG3(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_SLEEP_XTLON_CTRL */ +#define BIT_ARM7_SLEEP_XTL_ON ( BIT(5) ) +#define BIT_VCP1_SLEEP_XTL_ON ( BIT(4) ) +#define BIT_VCP0_SLEEP_XTL_ON ( BIT(3) ) +#define BIT_CP1_SLEEP_XTL_ON ( BIT(2) ) +#define BIT_CP0_SLEEP_XTL_ON ( BIT(1) ) +#define BIT_AP_SLEEP_XTL_ON ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_MEM_SLP_CFG */ +#define BITS_MEM_SLP_CFG(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_MEM_SD_CFG */ +#define BITS_MEM_SD_CFG(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_APCPU_CORE_PU_LOCK */ +#define BIT_PMU_APB_APCPU_C3_PU_LOCK ( BIT(3) ) +#define BIT_PMU_APB_APCPU_C2_PU_LOCK ( BIT(2) ) +#define BIT_PMU_APB_APCPU_C1_PU_LOCK ( BIT(1) ) +#define BIT_PMU_APB_APCPU_C0_PU_LOCK ( BIT(0) ) +#define BIT_PMU_APB_CA7_C3_PU_LOCK BIT_PMU_APB_APCPU_C3_PU_LOCK +#define BIT_PMU_APB_CA7_C2_PU_LOCK BIT_PMU_APB_APCPU_C2_PU_LOCK +#define BIT_PMU_APB_CA7_C1_PU_LOCK BIT_PMU_APB_APCPU_C1_PU_LOCK +#define BIT_PMU_APB_CA7_C0_PU_LOCK BIT_PMU_APB_APCPU_C0_PU_LOCK +/* bits definitions for register REG_PMU_APB_ARM7_HOLD_CGM_EN */ +#define BIT_PD_CP1_CEVA_CGM_HOLD_EN ( BIT(10) ) +#define BIT_PD_CP1_CA5_CGM_HOLD_EN ( BIT(9) ) +#define BIT_PD_CP0_CEVA_1_CGM_HOLD_EN ( BIT(8) ) +#define BIT_PD_CP0_CEVA_0_CGM_HOLD_EN ( BIT(7) ) +#define BIT_PD_CP0_ARM9_1_CGM_HOLD_EN ( BIT(6) ) +#define BIT_PD_CP0_ARM9_0_CGM_HOLD_EN ( BIT(5) ) +#define BIT_PD_CA53_TOP_CMG_HOLD_EN ( BIT(4) ) +#define BIT_PD_CA53_C3_CMG_HOLD_EN ( BIT(3) ) +#define BIT_PD_CA53_C2_CMG_HOLD_EN ( BIT(2) ) +#define BIT_PD_CA53_C1_CMG_HOLD_EN ( BIT(1) ) +#define BIT_PD_CA53_C0_CMG_HOLD_EN ( BIT(0) ) +#define BIT_PD_CA7_TOP_CMG_HOLD_EN BIT_PD_CA53_TOP_CMG_HOLD_EN +#define BIT_PD_CA7_C3_CMG_HOLD_EN BIT_PD_CA53_C3_CMG_HOLD_EN +#define BIT_PD_CA7_C2_CMG_HOLD_EN BIT_PD_CA53_C2_CMG_HOLD_EN +#define BIT_PD_CA7_C1_CMG_HOLD_EN BIT_PD_CA53_C1_CMG_HOLD_EN +#define BIT_PD_CA7_C0_CMG_HOLD_EN BIT_PD_CA53_C0_CMG_HOLD_EN + +/* bits definitions for register REG_PMU_APB_PWR_CNT_WAIT_CFG0 */ +#define BITS_VCP0_PWR_WAIT_CNT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_CP1_PWR_WAIT_CNT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_CP0_PWR_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_AP_PWR_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PWR_CNT_WAIT_CFG1 */ +#define BITS_ARM7_PWR_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_VCP1_PWR_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_RC0_REL_CFG */ +#define BIT_RC0_ARM7_SEL ( BIT(5) ) +#define BIT_RC0_VCP1_SEL ( BIT(4) ) +#define BIT_RC0_VCP0_SEL ( BIT(3) ) +#define BIT_RC0_CP1_SEL ( BIT(2) ) +#define BIT_RC0_CP0_SEL ( BIT(1) ) +#define BIT_RC0_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_RC1_REL_CFG */ +#define BIT_RC1_ARM7_SEL ( BIT(5) ) +#define BIT_RC1_VCP1_SEL ( BIT(4) ) +#define BIT_RC1_VCP0_SEL ( BIT(3) ) +#define BIT_RC1_CP1_SEL ( BIT(2) ) +#define BIT_RC1_CP0_SEL ( BIT(1) ) +#define BIT_RC1_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_RC_CNT_WAIT_CFG */ +#define BITS_RC1_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_RC0_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_MEM_AUTO_SLP_CFG */ +#define BITS_MEM_AUTO_SLP_EN(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_MEM_AUTO_SD_CFG */ +#define BITS_MEM_AUTO_SD_EN(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CP0_PD_SHUTDOWN_CFG */ +#define BIT_PD_CP0_HU3GE_VCP1_SEL ( BIT(20) ) +#define BIT_PD_CP0_TD_VCP1_SEL ( BIT(19) ) +#define BIT_PD_CP0_GSM_0_VCP1_SEL ( BIT(18) ) +#define BIT_PD_CP0_CEVA_0_VCP1_SEL ( BIT(17) ) +#define BIT_PD_CP0_ARM9_1_VCP1_SEL ( BIT(16) ) +#define BIT_PD_CP0_ARM9_0_VCP0_SEL ( BIT(8) ) +#define BIT_PD_CP0_HU3GE_CP0_SEL ( BIT(5) ) +#define BIT_PD_CP0_TD_CP0_SEL ( BIT(4) ) +#define BIT_PD_CP0_GSM_0_CP0_SEL ( BIT(3) ) +#define BIT_PD_CP0_CEVA_0_CP0_SEL ( BIT(2) ) +#define BIT_PD_CP0_ARM9_1_CP0_SEL ( BIT(1) ) +#define BIT_PD_CP0_ARM9_0_CP0_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CP1_PD_SHUTDOWN_CFG */ +#define BIT_PD_CP1_COMWRAP_VCP1_SEL ( BIT(20) ) +#define BIT_PD_CP1_CEVA_VCP1_SEL ( BIT(19) ) +#define BIT_PD_CP1_LTE_P2_VCP1_SEL ( BIT(18) ) +#define BIT_PD_CP1_LTE_P1_VCP1_SEL ( BIT(17) ) +#define BIT_PD_CP1_CA5_VCP1_SEL ( BIT(16) ) +#define BIT_PD_CP1_COMWRAP_CP1_SEL ( BIT(4) ) +#define BIT_PD_CP1_CEVA_CP1_SEL ( BIT(3) ) +#define BIT_PD_CP1_LTE_P2_CP1_SEL ( BIT(2) ) +#define BIT_PD_CP1_LTE_P1_CP1_SEL ( BIT(1) ) +#define BIT_PD_CP1_CA5_CP1_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_WAKEUP_LOCK_EN0 */ +#define BIT_PD_MM_CODEC_WAKEUP_LOCK_EN ( BIT(30) ) +#define BIT_PD_GPU_C1_WAKEUP_LOCK_EN ( BIT(29) ) +#define BIT_PD_GPU_C0_WAKEUP_LOCK_EN ( BIT(28) ) +#define BIT_PD_CA53_LIT_MP4_WAKEUP_LOCK_EN ( BIT(27) ) +#define BIT_VCP1_SYS_WAKEUP_LOCK_EN ( BIT(26) ) +#define BIT_VCP0_SYS_WAKEUP_LOCK_EN ( BIT(25) ) +#define BIT_CP1_SYS_WAKEUP_LOCK_EN ( BIT(24) ) +#define BIT_CP0_SYS_WAKEUP_LOCK_EN ( BIT(23) ) +#define BIT_AP_SYS_WAKEUP_LOCK_EN ( BIT(22) ) +#define BIT_PD_PUB_SYS_WAKEUP_LOCK_EN ( BIT(21) ) +#define BIT_PD_CP1_COMWRAP_WAKEUP_LOCK_EN ( BIT(20) ) +#define BIT_PD_CP1_CEVA_WAKEUP_LOCK_EN ( BIT(19) ) +#define BIT_PD_CP1_LTE_P2_WAKEUP_LOCK_EN ( BIT(18) ) +#define BIT_PD_CP1_LTE_P1_WAKEUP_LOCK_EN ( BIT(17) ) +#define BIT_PD_CP1_CA5_WAKEUP_LOCK_EN ( BIT(16) ) +#define BIT_PD_CP0_CEVA_1_WAKEUP_LOCK_EN ( BIT(15) ) +#define BIT_PD_CP0_CEVA_0_WAKEUP_LOCK_EN ( BIT(14) ) +#define BIT_PD_CP0_TD_WAKEUP_LOCK_EN ( BIT(13) ) +#define BIT_PD_CP0_GSM_1_WAKEUP_LOCK_EN ( BIT(12) ) +#define BIT_PD_CP0_GSM_0_WAKEUP_LOCK_EN ( BIT(11) ) +#define BIT_PD_CP0_HU3GE_WAKEUP_LOCK_EN ( BIT(10) ) +#define BIT_PD_CP0_ARM9_1_WAKEUP_LOCK_EN ( BIT(9) ) +#define BIT_PD_CP0_ARM9_0_WAKEUP_LOCK_EN ( BIT(8) ) +#define BIT_PD_MM_TOP_WAKEUP_LOCK_EN ( BIT(7) ) +#define BIT_PD_GPU_TOP_WAKEUP_LOCK_EN ( BIT(6) ) +#define BIT_PD_AP_SYS_WAKEUP_LOCK_EN ( BIT(5) ) +#define BIT_PD_CA53_TOP_WAKEUP_LOCK_EN ( BIT(4) ) +#define BIT_PD_CA53_LIT_C3_WAKEUP_LOCK_EN ( BIT(3) ) +#define BIT_PD_CA53_LIT_C2_WAKEUP_LOCK_EN ( BIT(2) ) +#define BIT_PD_CA53_LIT_C1_WAKEUP_LOCK_EN ( BIT(1) ) +#define BIT_PD_CA53_LIT_C0_WAKEUP_LOCK_EN ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_WAKEUP_LOCK_EN1 */ +#define BIT_PD_CA53_BIG_MP4_WAKEUP_LOCK_EN ( BIT(4) ) +#define BIT_PD_CA53_BIG_C3_WAKEUP_LOCK_EN ( BIT(3) ) +#define BIT_PD_CA53_BIG_C2_WAKEUP_LOCK_EN ( BIT(2) ) +#define BIT_PD_CA53_BIG_C1_WAKEUP_LOCK_EN ( BIT(1) ) +#define BIT_PD_CA53_BIG_C0_WAKEUP_LOCK_EN ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_LP_AUTO_CTRL */ +#define BIT_RST_DLY_CFG ( BIT(31) ) +#define BIT_EIC_DEEP_SLEEP_SEL ( BIT(30) ) +#define BIT_EIC_LIGHT_SLEEP_SEL ( BIT(29) ) +#define BIT_REDUN_CFG_3 ( BIT(28) ) +#define BIT_REDUN_CFG_2 ( BIT(27) ) +#define BIT_REDUN_CFG_1 ( BIT(26) ) +#define BIT_REDUN_CFG_0 ( BIT(25) ) +#define BIT_ADB_CTRL_EN_BIG ( BIT(8) ) +#define BIT_ADB_CTRL_EN_LIT ( BIT(7) ) +#define BIT_ACINACTM_CTRL ( BIT(6) ) +#define BIT_ACINACTM_BIG ( BIT(5) ) +#define BIT_ACINACTM_LIT ( BIT(4) ) +#define BIT_NIC_LP_CTRL_DISABLE ( BIT(3) ) +#define BIT_CA53_BIG_AUTO_CLK_CTRL_DISABLE ( BIT(2) ) +#define BIT_CA53_LIT_AUTO_CLK_CTRL_DISABLE ( BIT(1) ) +#define BIT_DAP_CA53_CCI_EN ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CA53_LIT_C0_INT_DISABLE */ +#define BIT_CA53_LIT_C0_INT_DISABLE ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CA53_LIT_C1_INT_DISABLE */ +#define BIT_CA53_LIT_C1_INT_DISABLE ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CA53_LIT_C2_INT_DISABLE */ +#define BIT_CA53_LIT_C2_INT_DISABLE ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CA53_LIT_C3_INT_DISABLE */ +#define BIT_CA53_LIT_C3_INT_DISABLE ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CA53_BIG_C0_INT_DISABLE */ +#define BIT_CA53_BIG_C0_INT_DISABLE ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CA53_BIG_C1_INT_DISABLE */ +#define BIT_CA53_BIG_C1_INT_DISABLE ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CA53_BIG_C2_INT_DISABLE */ +#define BIT_CA53_BIG_C2_INT_DISABLE ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CA53_BIG_C3_INT_DISABLE */ +#define BIT_CA53_BIG_C3_INT_DISABLE ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_PUB_ACC_RDY */ +#define BIT_PUB_ACC_RDY ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_PUB_CLK_RDY */ +#define BIT_PUB_CLK_RDY ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_LIT_C0_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CA53_LIT_C0_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_LIT_C1_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CA53_LIT_C1_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_LIT_C2_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CA53_LIT_C2_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_LIT_C3_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CA53_LIT_C3_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_TOP_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CA53_TOP_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_AP_SYS_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_AP_SYS_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_GPU_TOP_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_GPU_TOP_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_MM_TOP_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_MM_TOP_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_0_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_ARM9_0_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_1_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_ARM9_1_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_CEVA_0_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_CEVA_0_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_CEVA_1_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_CEVA_1_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_GSM_0_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_GSM_0_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_GSM_1_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_GSM_1_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_TD_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_TD_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_HU3GE_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_HU3GE_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_CA5_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP1_CA5_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_CEVA_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP1_CEVA_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_LTE_P1_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP1_LTE_P1_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_LTE_P2_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP1_LTE_P2_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_COMWRAP_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP1_COMWRAP_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_PUB_SYS_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_PUB_SYS_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_GPU_C0_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_GPU_C0_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_GPU_C1_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_GPU_C1_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_LIT_MP4_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CA53_LIT_MP4_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_BIG_C0_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CA53_BIG_C0_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_BIG_C1_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CA53_BIG_C1_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_BIG_C2_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CA53_BIG_C2_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_BIG_C3_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CA53_BIG_C3_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_BIG_MP4_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CA53_BIG_MP4_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_MM_CODEC_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_MM_CODEC_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_pub_apb.h b/include/soc/sprd/chip_x35lt8/__regs_pub_apb.h new file mode 100644 index 00000000..f018b7dd --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_pub_apb.h @@ -0,0 +1,479 @@ +/* the head file modifier: g 2015-03-19 15:50:04*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_PUB_APB_HEADFILE_H__ +#define __H_REGS_PUB_APB_HEADFILE_H__ __FILE__ + +#define REGS_PUB_APB + +/* registers definitions for PUB_APB */ +#define REG_PUB_APB_BUSMON_CNT_START SCI_ADDR(REGS_PUB_APB_BASE, 0x0000) +#define REG_PUB_APB_BUSMON_CFG SCI_ADDR(REGS_PUB_APB_BASE, 0x0004) +#define REG_PUB_APB_DDR_EB SCI_ADDR(REGS_PUB_APB_BASE, 0x0008) +#define REG_PUB_APB_DDR_SOFT_RST SCI_ADDR(REGS_PUB_APB_BASE, 0x000C) +#define REG_PUB_APB_DDR_QOS_CFG1 SCI_ADDR(REGS_PUB_APB_BASE, 0x0010) +#define REG_PUB_APB_DDR_QOS_CFG2 SCI_ADDR(REGS_PUB_APB_BASE, 0x0014) +#define REG_PUB_APB_DDR_QOS_CFG3 SCI_ADDR(REGS_PUB_APB_BASE, 0x0018) +#define REG_PUB_APB_DDR_MRR_STATUS SCI_ADDR(REGS_PUB_APB_BASE, 0x001C) +#define REG_PUB_APB_DDR_ID2QOS_SEL SCI_ADDR(REGS_PUB_APB_BASE, 0x003C) +#define REG_PUB_APB_DDR_ID2QOS_RCFG0 SCI_ADDR(REGS_PUB_APB_BASE, 0x0040) +#define REG_PUB_APB_DDR_ID2QOS_RCFG1 SCI_ADDR(REGS_PUB_APB_BASE, 0x0044) +#define REG_PUB_APB_DDR_ID2QOS_RCFG2 SCI_ADDR(REGS_PUB_APB_BASE, 0x0048) +#define REG_PUB_APB_DDR_ID2QOS_RCFG3 SCI_ADDR(REGS_PUB_APB_BASE, 0x004c) +#define REG_PUB_APB_DDR_ID2QOS_RCFG4 SCI_ADDR(REGS_PUB_APB_BASE, 0x0050) +#define REG_PUB_APB_DDR_ID2QOS_RCFG5 SCI_ADDR(REGS_PUB_APB_BASE, 0x0054) +#define REG_PUB_APB_DDR_ID2QOS_RCFG6 SCI_ADDR(REGS_PUB_APB_BASE, 0x0058) +#define REG_PUB_APB_DDR_ID2QOS_RCFG7 SCI_ADDR(REGS_PUB_APB_BASE, 0x005c) +#define REG_PUB_APB_DDR_ID2QOS_RCFG8 SCI_ADDR(REGS_PUB_APB_BASE, 0x0060) +#define REG_PUB_APB_DDR_ID2QOS_RCFG9 SCI_ADDR(REGS_PUB_APB_BASE, 0x0064) +#define REG_PUB_APB_DDR_ID2QOS_WCFG0 SCI_ADDR(REGS_PUB_APB_BASE, 0x0080) +#define REG_PUB_APB_DDR_ID2QOS_WCFG1 SCI_ADDR(REGS_PUB_APB_BASE, 0x0084) +#define REG_PUB_APB_DDR_ID2QOS_WCFG2 SCI_ADDR(REGS_PUB_APB_BASE, 0x0088) +#define REG_PUB_APB_DDR_ID2QOS_WCFG3 SCI_ADDR(REGS_PUB_APB_BASE, 0x008c) +#define REG_PUB_APB_DDR_ID2QOS_WCFG4 SCI_ADDR(REGS_PUB_APB_BASE, 0x0090) +#define REG_PUB_APB_DDR_ID2QOS_WCFG5 SCI_ADDR(REGS_PUB_APB_BASE, 0x0094) +#define REG_PUB_APB_DDR_ID2QOS_WCFG6 SCI_ADDR(REGS_PUB_APB_BASE, 0x0098) +#define REG_PUB_APB_DDR_ID2QOS_WCFG7 SCI_ADDR(REGS_PUB_APB_BASE, 0x009c) +#define REG_PUB_APB_DDR_ID2QOS_WCFG8 SCI_ADDR(REGS_PUB_APB_BASE, 0x00a0) +#define REG_PUB_APB_DDR_ID2QOS_WCFG9 SCI_ADDR(REGS_PUB_APB_BASE, 0x00a4) +#define REG_PUB_APB_DFI_TIMEOUT_CFG SCI_ADDR(REGS_PUB_APB_BASE, 0x0100) +#define REG_PUB_APB_DFI_TIMEOUT_STATUS SCI_ADDR(REGS_PUB_APB_BASE, 0x0104) +#define REG_PUB_APB_DFI_TIMEOUT_EN_CNT SCI_ADDR(REGS_PUB_APB_BASE, 0x0108) +#define REG_PUB_APB_DFI_TIMEOUT_VALID_CNT SCI_ADDR(REGS_PUB_APB_BASE, 0x010c) +#define REG_PUB_APB_DMC_PORT_REMAP_EN SCI_ADDR(REGS_PUB_APB_BASE, 0x3000) +#define REG_PUB_APB_DMC_PORTS_MPU_EN SCI_ADDR(REGS_PUB_APB_BASE, 0x3004) +#define REG_PUB_APB_DMC_PORT0_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3008) +#define REG_PUB_APB_DMC_PORT1_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x300C) +#define REG_PUB_APB_DMC_PORT2_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3010) +#define REG_PUB_APB_DMC_PORT3_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3014) +#define REG_PUB_APB_DMC_PORT4_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3018) +#define REG_PUB_APB_DMC_PORT5_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x301C) +#define REG_PUB_APB_DMC_PORT6_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3020) +#define REG_PUB_APB_DMC_PORT7_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3024) +#define REG_PUB_APB_DMC_PORT8_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3028) +#define REG_PUB_APB_DMC_PORT9_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x302C) +#define REG_PUB_APB_DMC_PORT0_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3030) +#define REG_PUB_APB_DMC_PORT1_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3034) +#define REG_PUB_APB_DMC_PORT2_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3038) +#define REG_PUB_APB_DMC_PORT3_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x303C) +#define REG_PUB_APB_DMC_PORT4_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3040) +#define REG_PUB_APB_DMC_PORT5_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3044) +#define REG_PUB_APB_DMC_PORT6_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3048) +#define REG_PUB_APB_DMC_PORT7_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3050) +#define REG_PUB_APB_DMC_PORT8_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3054) +#define REG_PUB_APB_DMC_PORT9_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3058) +#define REG_PUB_APB_DMC_PORT0_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x305C) +#define REG_PUB_APB_DMC_PORT1_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3060) +#define REG_PUB_APB_DMC_PORT2_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3064) +#define REG_PUB_APB_DMC_PORT3_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3068) +#define REG_PUB_APB_DMC_PORT4_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x306C) +#define REG_PUB_APB_DMC_PORT5_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3070) +#define REG_PUB_APB_DMC_PORT6_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3074) +#define REG_PUB_APB_DMC_PORT7_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3078) +#define REG_PUB_APB_DMC_PORT8_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x307C) +#define REG_PUB_APB_DMC_PORT9_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3080) + + + +/* bits definitions for register REG_MM_AHB_RF_BUSMON_CNT_START */ +#define BIT_PUB_BUSMON_CNT_START ( BIT(0) ) + +/* bits definitions for register REG_MM_AHB_RF_BUSMON_CFG */ +#define BIT_PUB_BUSMON9_EB ( BIT(25) ) +#define BIT_PUB_BUSMON8_EB ( BIT(24) ) +#define BIT_PUB_BUSMON7_EB ( BIT(23) ) +#define BIT_PUB_BUSMON6_EB ( BIT(22) ) +#define BIT_PUB_BUSMON5_EB ( BIT(21) ) +#define BIT_PUB_BUSMON4_EB ( BIT(20) ) +#define BIT_PUB_BUSMON3_EB ( BIT(19) ) +#define BIT_PUB_BUSMON2_EB ( BIT(18) ) +#define BIT_PUB_BUSMON1_EB ( BIT(17) ) +#define BIT_PUB_BUSMON0_EB ( BIT(16) ) +#define BIT_PUB_BUSMON9_SOFT_RST ( BIT(9) ) +#define BIT_PUB_BUSMON8_SOFT_RST ( BIT(8) ) +#define BIT_PUB_BUSMON7_SOFT_RST ( BIT(7) ) +#define BIT_PUB_BUSMON6_SOFT_RST ( BIT(6) ) +#define BIT_PUB_BUSMON5_SOFT_RST ( BIT(5) ) +#define BIT_PUB_BUSMON4_SOFT_RST ( BIT(4) ) +#define BIT_PUB_BUSMON3_SOFT_RST ( BIT(3) ) +#define BIT_PUB_BUSMON2_SOFT_RST ( BIT(2) ) +#define BIT_PUB_BUSMON1_SOFT_RST ( BIT(1) ) +#define BIT_PUB_BUSMON0_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_EB */ + +/* bits definitions for register REG_MM_AHB_RF_DDR_SOFT_RST */ + +/* bits definitions for register REG_MM_AHB_RF_DDR_QOS_CFG1 */ +#define BITS_DMC_ARQOS_3(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_3(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_2(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_2(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_1(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_0(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_QOS_CFG2 */ +#define BITS_DMC_ARQOS_7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_7(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_6(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_6(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_5(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_5(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_4(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_QOS_CFG3 */ +#define BITS_DMC_ARQOS_9(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_9(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_8(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_8(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_MRR_STATUS */ +#define BIT_DDRC_CO_RD_MRR_DATA_VALID ( BIT(8) ) +#define BITS_DDRC_CO_RD_MRR_DATA(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_SEL */ +#define BITS_DMC_ID_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DMC_QOS_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_RCFG0 */ +#define BITS_DMC_ARQOS_0_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_0_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_0_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_0_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_0_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_0_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_0_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_0_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_RCFG1 */ +#define BITS_DMC_ARQOS_1_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_1_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_1_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_1_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_1_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_1_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_1_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_1_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_RCFG2 */ +#define BITS_DMC_ARQOS_2_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_2_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_2_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_2_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_2_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_2_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_2_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_2_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_RCFG3 */ +#define BITS_DMC_ARQOS_3_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_3_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_3_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_3_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_3_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_3_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_3_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_3_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_RCFG4 */ +#define BITS_DMC_ARQOS_4_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_4_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_4_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_4_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_4_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_4_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_4_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_4_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_RCFG5 */ +#define BITS_DMC_ARQOS_5_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_5_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_5_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_5_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_5_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_5_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_5_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_5_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_RCFG6 */ +#define BITS_DMC_ARQOS_6_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_6_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_6_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_6_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_6_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_6_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_6_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_6_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_RCFG7 */ +#define BITS_DMC_ARQOS_7_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_7_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_7_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_7_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_7_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_7_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_7_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_7_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_RCFG8 */ +#define BITS_DMC_ARQOS_8_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_8_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_8_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_8_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_8_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_8_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_8_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_8_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_RCFG9 */ +#define BITS_DMC_ARQOS_9_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_9_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_9_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_9_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_9_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_9_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_9_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_9_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_WCFG0 */ +#define BITS_DMC_AWQOS_0_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_0_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_0_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_0_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_0_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_0_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_0_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_0_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_WCFG1 */ +#define BITS_DMC_AWQOS_1_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_1_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_1_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_1_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_1_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_1_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_1_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_1_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_WCFG2 */ +#define BITS_DMC_AWQOS_2_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_2_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_2_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_2_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_2_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_2_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_2_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_2_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_WCFG3 */ +#define BITS_DMC_AWQOS_3_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_3_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_3_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_3_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_3_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_3_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_3_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_3_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_WCFG4 */ +#define BITS_DMC_AWQOS_4_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_4_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_4_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_4_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_4_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_4_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_4_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_4_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_WCFG5 */ +#define BITS_DMC_AWQOS_5_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_5_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_5_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_5_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_5_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_5_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_5_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_5_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_WCFG6 */ +#define BITS_DMC_AWQOS_6_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_6_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_6_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_6_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_6_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_6_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_6_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_6_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_WCFG7 */ +#define BITS_DMC_AWQOS_7_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_7_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_7_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_7_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_7_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_7_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_7_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_7_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_WCFG8 */ +#define BITS_DMC_AWQOS_8_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_8_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_8_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_8_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_8_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_8_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_8_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_8_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_WCFG9 */ +#define BITS_DMC_AWQOS_9_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_9_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_9_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_9_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_9_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_9_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_9_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_9_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DFI_TIMEOUT_CFG */ +#define BITS_DFI_TIMEOUT_THRESHOLD(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DFI_TIMEOUT_CLR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DFI_TIMEOUT_EN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DFI_TIMEOUT_STATUS */ +#define BITS_DFI_TIMEOUT_STATUS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DFI_TIMEOUT_EN_CNT */ +#define BITS_DFI_TIMEOUT_EN3_CNT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DFI_TIMEOUT_EN2_CNT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DFI_TIMEOUT_EN1_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DFI_TIMEOUT_EN0_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_MM_AHB_RF_DFI_TIMEOUT_VALID_CNT */ +#define BITS_DFI_TIMEOUT_VALID3_CNT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DFI_TIMEOUT_VALID2_CNT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DFI_TIMEOUT_VALID1_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DFI_TIMEOUT_VALID0_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT_REMAP_EN */ +#define BITS_DMC_PORTS_REMAP_EN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORTS_MPU_EN */ +#define BITS_DMC_PORTS_MPU_EN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT0_ADDR_REMAP */ +#define BITS_DMC_PORT0_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT1_ADDR_REMAP */ +#define BITS_DMC_PORT1_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT2_ADDR_REMAP */ +#define BITS_DMC_PORT2_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT3_ADDR_REMAP */ +#define BITS_DMC_PORT3_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT4_ADDR_REMAP */ +#define BITS_DMC_PORT4_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT5_ADDR_REMAP */ +#define BITS_DMC_PORT5_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT6_ADDR_REMAP */ +#define BITS_DMC_PORT6_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT7_ADDR_REMAP */ +#define BITS_DMC_PORT7_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT8_ADDR_REMAP */ +#define BITS_DMC_PORT8_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT9_ADDR_REMAP */ +#define BITS_DMC_PORT9_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT0_MPU_RANGE */ +#define BITS_DMC_PORT0_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT1_MPU_RANGE */ +#define BITS_DMC_PORT1_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT2_MPU_RANGE */ +#define BITS_DMC_PORT2_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT3_MPU_RANGE */ +#define BITS_DMC_PORT3_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT4_MPU_RANGE */ +#define BITS_DMC_PORT4_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT5_MPU_RANGE */ +#define BITS_DMC_PORT5_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT6_MPU_RANGE */ +#define BITS_DMC_PORT6_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT7_MPU_RANGE */ +#define BITS_DMC_PORT7_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT8_MPU_RANGE */ +#define BITS_DMC_PORT8_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT9_MPU_RANGE */ +#define BITS_DMC_PORT9_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT0_DUMP_ADDR */ +#define BITS_DMC_PORT0_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT1_DUMP_ADDR */ +#define BITS_DMC_PORT1_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT2_DUMP_ADDR */ +#define BITS_DMC_PORT2_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT3_DUMP_ADDR */ +#define BITS_DMC_PORT3_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT4_DUMP_ADDR */ +#define BITS_DMC_PORT4_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT5_DUMP_ADDR */ +#define BITS_DMC_PORT5_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT6_DUMP_ADDR */ +#define BITS_DMC_PORT6_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT7_DUMP_ADDR */ +#define BITS_DMC_PORT7_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT8_DUMP_ADDR */ +#define BITS_DMC_PORT8_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT9_DUMP_ADDR */ +#define BITS_DMC_PORT9_DUMP_ADDR(_X_) (_X_) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_wcdma_ahb_rf.h b/include/soc/sprd/chip_x35lt8/__regs_wcdma_ahb_rf.h new file mode 100644 index 00000000..84cfa532 --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_wcdma_ahb_rf.h @@ -0,0 +1,125 @@ +/* the head file modifier: g 2015-03-19 17:11:11*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_WCDMA_AHB_RF_HEADFILE_H__ +#define __H_REGS_WCDMA_AHB_RF_HEADFILE_H__ __FILE__ + +#define REGS_WCDMA_AHB_RF + +/* registers definitions for WCDMA_AHB_RF */ +#define REG_WCDMA_AHB_RF_AHB_EB0 SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0000)/*AHB_EB0*/ +#define REG_WCDMA_AHB_RF_AHB_RST0 SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0004)/*AHB_RST0*/ +#define REG_WCDMA_AHB_RF_ARCH_EB_REG SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0018)/*ARCH_EB_REG*/ +#define REG_WCDMA_AHB_RF_AHB_REMAP SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x001C)/*AHB_REMAP*/ +#define REG_WCDMA_AHB_RF_AHB_MISC_CTL SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0020)/*AHB_MISC_CTL*/ +#define REG_WCDMA_AHB_RF_AHB_MTX_PRI_SEL0 SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0024)/*AHB_MTX_PRI_SEL0*/ +#define REG_WCDMA_AHB_RF_AHB_MTX_PRI_SEL1 SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0028)/*AHB_MTX_PRI_SEL1*/ +#define REG_WCDMA_AHB_RF_AHB1_PAUSE SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x002C)/*AHB1_PAUSE*/ +#define REG_WCDMA_AHB_RF_AHB_SLP_CTL SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0034)/*AHB_SLP_CTL*/ +#define REG_WCDMA_AHB_RF_AHB2_SLP_STS SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0038)/*AHB2_SLP_STS*/ +#define REG_WCDMA_AHB_RF_MCU_CLK_CTL SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x003C)/*MCU_CLK_CTL*/ +#define REG_WCDMA_AHB_RF_CHIP_ID SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x01FC)/*CHIP_ID*/ + + + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB_EB0 */ +#define BITS_WCDMA_EN(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BIT_BUSMON0_EN ( BIT(1) ) +#define BIT_SPINLOCK_EN ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB_RST0 */ +#define BIT_WCDMA_SOFT_RST ( BIT(3) ) +#define BIT_BUSMON0_SOFT_RST ( BIT(1) ) +#define BIT_SPINLOCK_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_ARCH_EB_REG */ +#define BIT_AHB_ARCH_EB ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB_REMAP */ +#define BIT_ARM_JTAG_EN_ARM1 ( BIT(1) ) +#define BIT_REMAP ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB_MISC_CTL */ +#define BIT_FORCE_WSYS_ACC_STOP ( BIT(3) ) +#define BIT_W_DMA_LSLP_EN ( BIT(2) ) +#define BIT_BUSMON0_SEL ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB_MTX_PRI_SEL0 */ +#define BITS_ARMMTX_M3TOS0_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ARMMTX_M3TOS0_ADJ_EN ( BIT(27) ) +#define BIT_ARMMTX_M3TOS0_RND_EN ( BIT(26) ) +#define BITS_ARMMTX_M3TOS0_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_ARMMTX_M2TOS0_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M2TOS0_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M2TOS0_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M2TOS0_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M1TOS0_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M1TOS0_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M1TOS0_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M1TOS0_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M0TOS0_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M0TOS0_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M0TOS0_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M0TOS0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB_MTX_PRI_SEL1 */ +#define BITS_ARMMTX_M6TOS0_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M6TOS0_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M6TOS0_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M6TOS0_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M5TOS0_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M5TOS0_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M5TOS0_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M5TOS0_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M4TOS0_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M4TOS0_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M4TOS0_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M4TOS0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB1_PAUSE */ +#define BIT_APB1_SLEEP ( BIT(3) ) +#define BIT_MCU1_DEEP_SLEEP_EN ( BIT(2) ) +#define BIT_MCU1_SYS_SLEEP_EN ( BIT(1) ) +#define BIT_MCU1_CORE_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB_SLP_CTL */ +#define BIT_MCUMTX_AUTO_GATE_EN ( BIT(4) ) +#define BIT_MCU_AUTO_GATE_EN ( BIT(3) ) +#define BIT_AHB_AUTO_GATE_EN ( BIT(2) ) +#define BIT_ARM1_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB2_SLP_STS */ +#define BIT_APB1_PERI_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_MCU_CLK_CTL */ +#define BITS_CLK_AHB_DIV(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_CLK_MCU_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_APB_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CLK_MCU_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_CHIP_ID */ +#define BITS_CHIP_ID(_X_) (_X_) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_wcdma_apb_rf.h b/include/soc/sprd/chip_x35lt8/__regs_wcdma_apb_rf.h new file mode 100644 index 00000000..ae6e1ba6 --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_wcdma_apb_rf.h @@ -0,0 +1,79 @@ +/* the head file modifier: g 2015-03-19 15:46:40*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_WCDMA_APB_RF_HEADFILE_H__ +#define __H_REGS_WCDMA_APB_RF_HEADFILE_H__ __FILE__ + +#define REGS_WCDMA_APB_RF + +/* registers definitions for WCDMA_APB_RF */ +#define REG_WCDMA_APB_RF_APB_EB SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0000)/*APB_EB*/ +#define REG_WCDMA_APB_RF_APB_RST SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0004)/*APB_RST*/ +#define REG_WCDMA_APB_RF_APB_SLEEP_ST SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0008)/*APB_SLEEP_ST*/ +#define REG_WCDMA_APB_RF_APB_MCU_RST SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0018)/*APB_MCU_RST*/ +#define REG_WCDMA_APB_RF_APB_CLK_SEL0 SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x001C)/*APB_CLK_SEL0*/ +#define REG_WCDMA_APB_RF_APB_CLK_DIV0 SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0020)/*APB_CLK_DIV0*/ +#define REG_WCDMA_APB_RF_APB_ARCH_EB SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0024)/*APB_ARCH_EB*/ +#define REG_WCDMA_APB_RF_APB_SLP_CTL SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0028)/*APB_SLP_CTL*/ + + + +/* bits definitions for register REG_WCDMA_APB_RF_APB_EB */ +#define BIT_TMR_RTC_EB ( BIT(6) ) +#define BIT_TMR_EB ( BIT(5) ) +#define BIT_SYSTMR_RTC_EB ( BIT(4) ) +#define BIT_SYSTMR_EB ( BIT(3) ) +#define BIT_UART0_EB ( BIT(2) ) +#define BIT_WDG_RTC_EB ( BIT(1) ) +#define BIT_WDG_EB ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_APB_RF_APB_RST */ +#define BIT_TMR_SOFT_RST ( BIT(3) ) +#define BIT_SYSTMR_SOFT_RST ( BIT(2) ) +#define BIT_UART0_SOFT_RST ( BIT(1) ) +#define BIT_WDG_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_APB_RF_APB_SLEEP_ST */ +#define BIT_CHIP_SLEEP_REC_CLR ( BIT(1) ) +#define BIT_CHIP_SLEEP_REC ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_APB_RF_APB_MCU_RST */ +#define BIT_MCU_SOFT_RST_SET ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_APB_RF_APB_CLK_SEL0 */ +#define BITS_CLK_UART0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_WCDMA_APB_RF_APB_CLK_DIV0 */ +#define BITS_CLK_UART0_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_WCDMA_APB_RF_APB_ARCH_EB */ +#define BIT_RTC_ARCH_EB ( BIT(1) ) +#define BIT_APB_ARCH_EB ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_APB_RF_APB_SLP_CTL */ +#define BIT_APB_PERI_FRC_ON ( BIT(1) ) +#define BIT_APB_PERI_FRC_SLP ( BIT(0) ) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__sc2723_regulator_map.h b/include/soc/sprd/chip_x35lt8/__sc2723_regulator_map.h new file mode 100644 index 00000000..7879ec63 --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__sc2723_regulator_map.h @@ -0,0 +1,128 @@ +/* + * Copyright (C) 2013 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +/* + * Regulator (0)Name, Regulator (1)Type, Power Off (2)Ctrl and (3)Bit, PWR_SEL (4) and (5) Bit, + * Voltage Trimming (6)Ctrl and (7)Bits, Calibration (8)Ctrl and (9)Bits, + * Voltage (10)Default, Voltage (11)Ctrl and (12)Bits, Voltage Select (13)Count and Voltage (14)List[ ... ...] + */ + + SCI_REGU_REG(vddcore, 0x12, ANA_REG_GLB_LDO_DCDC_PD, BIT(9), ANA_REG_GLB_PWR_SEL, BIT(0), + ANA_REG_GLB_DCDC_CORE_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_DCDC_CTRL15, BIT(14)|BIT(16)|BIT(18)|BIT(19), + 900, ANA_REG_GLB_DCDC_CORE_ADI, BIT(5)|BIT(6)|BIT(7), 8, 1100, 700, 800, 900, 1000, 650, 1200, 1300); + + SCI_REGU_REG(vddarm, 0x12, ANA_REG_GLB_LDO_DCDC_PD, BIT(10), ANA_REG_GLB_PWR_SEL, BIT(2), + ANA_REG_GLB_DCDC_ARM_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_DCDC_CTRL15, BIT(13)|BIT(16)|BIT(18)|BIT(19), + 900, ANA_REG_GLB_DCDC_ARM_ADI, BIT(5)|BIT(6)|BIT(7), 8, 1100, 700, 800, 900, 1000, 650, 1200, 1300); + + SCI_REGU_REG(vddmem, 0x12, ANA_REG_GLB_LDO_DCDC_PD, BIT(11), ANA_REG_GLB_PWR_SEL, BIT(3), + ANA_REG_GLB_DCDC_MEM_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_DCDC_CTRL15, BIT(13)|BIT(14)|BIT(16)|BIT(18)|BIT(19), + 1200, 0, 0, 2, 600, 3125); + + SCI_REGU_REG(vddgen, 0x12, ANA_REG_GLB_LDO_DCDC_PD, BIT(12), ANA_REG_GLB_PWR_SEL, BIT(4), + ANA_REG_GLB_DCDC_GEN_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_DCDC_CTRL15, BIT(15)|BIT(16)|BIT(18)|BIT(19), + 2400, 0, 0, 2, 600, 3125); + + SCI_REGU_REG(vddrf, 0x12, ANA_REG_GLB_LDO_DCDC_PD, BIT(13), ANA_REG_GLB_PWR_SEL, BIT(5), + ANA_REG_GLB_DCDC_RF_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_DCDC_CTRL15, BIT(13)|BIT(15)|BIT(16)|BIT(18)|BIT(19), + 1500, 0, 0, 2, 600, 3125); + + SCI_REGU_REG(vddcon, 0x2, ANA_REG_GLB_LDO_PD_CTRL, BIT(13), 0, 0, + ANA_REG_GLB_DCDC_CON_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_DCDC_CTRL15, BIT(14)|BIT(15)|BIT(16)|BIT(18)|BIT(19), + 1600, 0, 0, 2, 600, 3125); + + SCI_REGU_REG(vddwpa, 0x2, ANA_REG_GLB_LDO_PD_CTRL, BIT(14), 0, 0, + ANA_REG_GLB_DCDC_WPA_ADI, BIT(0)|BIT(1)|BIT(2), ANA_REG_GLB_DCDC_CTRL15, BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(18)|BIT(19), + 0, 0, 0, 0); + + SCI_REGU_REG(vddrf0, 0x10, ANA_REG_GLB_LDO_DCDC_PD, BIT(8), ANA_REG_GLB_PWR_SEL, BIT(11), + ANA_REG_GLB_LDO_V_CTRL0, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), ANA_REG_GLB_LDO_V_CTRL11, BIT(2)|BIT(16)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1150, 6250); + + SCI_REGU_REG(vddemmccore, 0x10, ANA_REG_GLB_LDO_DCDC_PD, BIT(7), ANA_REG_GLB_PWR_SEL, BIT(7), + ANA_REG_GLB_LDO_V_CTRL7, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), ANA_REG_GLB_LDO_V_CTRL11, BIT(5)|BIT(6)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 3000, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddgen1, 0x10, ANA_REG_GLB_LDO_DCDC_PD, BIT(6), ANA_REG_GLB_PWR_SEL, BIT(12), + ANA_REG_GLB_LDO_V_CTRL3, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_V_CTRL11, BIT(0)|BIT(2)|BIT(16)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1150, 6250); + + SCI_REGU_REG(vddgen0, 0x10, ANA_REG_GLB_LDO_DCDC_PD, BIT(4), ANA_REG_GLB_PWR_SEL, BIT(13), + ANA_REG_GLB_LDO_V_CTRL2, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6), ANA_REG_GLB_LDO_V_CTRL11, BIT(1)|BIT(2)|BIT(16)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1150, 6250); + + SCI_REGU_REG(vdddcxo, 0x10, ANA_REG_GLB_LDO_DCDC_PD, BIT(5), ANA_REG_GLB_PWR_SEL, BIT(8), + ANA_REG_GLB_LDO_V_CTRL8, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), ANA_REG_GLB_LDO_V_CTRL11, BIT(7)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vdd25, 0x10, ANA_REG_GLB_LDO_DCDC_PD, BIT(3), ANA_REG_GLB_PWR_SEL, BIT(6), + ANA_REG_GLB_LDO_V_CTRL10, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_LDO_V_CTRL11, BIT(8)|BIT(17)|BIT(18)|BIT(20), + 2800, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vdd28, 0x10, ANA_REG_GLB_LDO_DCDC_PD, BIT(2), ANA_REG_GLB_PWR_SEL, BIT(9), + ANA_REG_GLB_LDO_V_CTRL3, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_LDO_V_CTRL11, BIT(6)|BIT(7)|BIT(10)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 2800, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vdd18, 0x10, ANA_REG_GLB_LDO_DCDC_PD, BIT(1), ANA_REG_GLB_PWR_SEL, BIT(10), + ANA_REG_GLB_LDO_V_CTRL9, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_V_CTRL11, BIT(0)|BIT(16)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1150, 6250); + + SCI_REGU_REG(vddwifipa, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(11), 0, 0, + ANA_REG_GLB_LDO_V_CTRL0, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_LDO_V_CTRL11, BIT(5)|BIT(10)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 3300, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddsdcore, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(10), 0, 0, + ANA_REG_GLB_LDO_V_CTRL6, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), ANA_REG_GLB_LDO_V_CTRL11, BIT(5)|BIT(7)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 3000, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddsdio, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(0), 0, 0, + ANA_REG_GLB_LDO_V_CTRL4, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_LDO_V_CTRL11, BIT(3)|BIT(16)|BIT(18)|BIT(19)|BIT(20), + 3000, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddsim0, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(1), 0, 0, + ANA_REG_GLB_LDO_V_CTRL4, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), ANA_REG_GLB_LDO_V_CTRL11, BIT(8)|BIT(10)|BIT(17)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddsim1, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(2), 0, 0, + ANA_REG_GLB_LDO_V_CTRL5, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_LDO_V_CTRL11, BIT(10)|BIT(17)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddsim2, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(3), 0, 0, + ANA_REG_GLB_LDO_V_CTRL5, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), ANA_REG_GLB_LDO_V_CTRL11, BIT(8)|BIT(9)|BIT(17)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddcama, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(4), 0, 0, + ANA_REG_GLB_LDO_V_CTRL6, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_LDO_V_CTRL11, BIT(9)|BIT(17)|BIT(18)|BIT(20), + 2800, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddcamd, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(5), 0, 0, + ANA_REG_GLB_LDO_V_CTRL1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6), ANA_REG_GLB_LDO_V_CTRL11, BIT(1)|BIT(16)|BIT(18)|BIT(20), + 1500, 0, 0, 2, 1150, 6250); + + SCI_REGU_REG(vddcamio, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(6), 0, 0, + ANA_REG_GLB_LDO_V_CTRL1, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_V_CTRL11, BIT(0)|BIT(1)|BIT(16)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1150, 6250); + + SCI_REGU_REG(vddcammot, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(7), 0, 0, + ANA_REG_GLB_LDO_V_CTRL7, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_LDO_V_CTRL11, BIT(6)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 2800, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddusb, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(8), 0, 0, + ANA_REG_GLB_LDO_V_CTRL9, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_LDO_V_CTRL11, BIT(4)|BIT(16)|BIT(18)|BIT(19)|BIT(20), + 3300, 0, 0, 2, 1200, 10000); + diff --git a/include/soc/sprd/chip_x35lt8/__scx35l_clock_tree.h b/include/soc/sprd/chip_x35lt8/__scx35l_clock_tree.h new file mode 100644 index 00000000..992ad053 --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__scx35l_clock_tree.h @@ -0,0 +1,557 @@ +/* + * Copyright (C) 2013 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#define REG_0X20E0(_o_) SCI_ADDR(SPRD_AHB_BASE, (_o_)) +#define REG_0X2150(_o_) SCI_ADDR(SPRD_APBCKG_BASE, (_o_)) +#define REG_0X402E(_o_) SCI_ADDR(SPRD_AONAPB_BASE, (_o_)) +#define REG_0X402D(_o_) SCI_ADDR(SPRD_AONCKG_BASE, (_o_)) +#define REG_0X6010(_o_) SCI_ADDR(SPRD_GPUAPB_BASE, (_o_)) +#define REG_0X60D0(_o_) SCI_ADDR(SPRD_MMAHB_BASE, (_o_)) +#define REG_0X60E0(_o_) SCI_ADDR(SPRD_MMCKG_BASE, (_o_)) +#define REG_0X7130(_o_) SCI_ADDR(SPRD_APBREG_BASE, (_o_)) + +#define REG_0X402E0044 REG_0X402E(0x0044) +#define REG_0X402E004C REG_0X402E(0x004C) +#define REG_0X402E005C REG_0X402E(0x005C) +#define REG_0X402E0054 REG_0X402E(0x0054) +#define REG_0X402E0064 REG_0X402E(0x0064) +#define REG_0X20E00038 REG_0X20E0(0x0038) +#define REG_0X20E00054 REG_0X20E0(0x0054) +#define REG_0X402D0020 REG_0X402D(0x0020) +#define REG_0X402D002C REG_0X402D(0x002C) +#define REG_0X402D0030 REG_0X402D(0x0030) +#define REG_0X402E0000 REG_0X402E(0x0000) +#define REG_0X402D0034 REG_0X402D(0x0034) +#define REG_0X402E0004 REG_0X402E(0x0004) +#define REG_0X402D0038 REG_0X402D(0x0038) +#define REG_0X402D003C REG_0X402D(0x003C) +#define REG_0X402D0040 REG_0X402D(0x0040) +#define REG_0X402D0044 REG_0X402D(0x0044) +#define REG_0X402D0048 REG_0X402D(0x0048) +#define REG_0X402D004C REG_0X402D(0x004C) +#define REG_0X402D0050 REG_0X402D(0x0050) +#define REG_0X402D0054 REG_0X402D(0x0054) +#define REG_0X402D0058 REG_0X402D(0x0058) +#define REG_0X402D0068 REG_0X402D(0x0068) +#define REG_0X402D006C REG_0X402D(0x006C) +#define REG_0X402D0070 REG_0X402D(0x0070) +#define REG_0X402D0074 REG_0X402D(0x0074) +#define REG_0X402D0078 REG_0X402D(0x0078) +#define REG_0X402D007C REG_0X402D(0x007C) +#define REG_0X402D0080 REG_0X402D(0x0080) +#define REG_0X402D0090 REG_0X402D(0x0090) +#define REG_0X402D0098 REG_0X402D(0x0098) +#define REG_0X402D00C8 REG_0X402D(0x00C8) +#define REG_0X402D00CC REG_0X402D(0x00CC) +#define REG_0X402D00D0 REG_0X402D(0x00D0) +#define REG_0X21500020 REG_0X2150(0x0020) +#define REG_0X21500024 REG_0X2150(0x0024) +#define REG_0X20E00000 REG_0X20E0(0x0000) +#define REG_0X21500028 REG_0X2150(0x0028) +#define REG_0X2150002C REG_0X2150(0x002C) +#define REG_0X21500030 REG_0X2150(0x0030) +#define REG_0X21500034 REG_0X2150(0x0034) +#define REG_0X21500054 REG_0X2150(0x0054) +#define REG_0X21500058 REG_0X2150(0x0058) +#define REG_0X2150005C REG_0X2150(0x005C) +#define REG_0X21500060 REG_0X2150(0x0060) +#define REG_0X21500068 REG_0X2150(0x0068) +#define REG_0X21500070 REG_0X2150(0x0070) +#define REG_0X21500074 REG_0X2150(0x0074) +#define REG_0X2150007C REG_0X2150(0x007C) +#define REG_0X71300000 REG_0X7130(0x0000) +#define REG_0X21500084 REG_0X2150(0x0084) +#define REG_0X21500088 REG_0X2150(0x0088) +#define REG_0X2150008C REG_0X2150(0x008C) +#define REG_0X21500090 REG_0X2150(0x0090) +#define REG_0X21500094 REG_0X2150(0x0094) +#define REG_0X21500098 REG_0X2150(0x0098) +#define REG_0X2150009C REG_0X2150(0x009C) +#define REG_0X215000A0 REG_0X2150(0x00A0) +#define REG_0X215000A4 REG_0X2150(0x00A4) +#define REG_0X215000A8 REG_0X2150(0x00A8) +#define REG_0X215000AC REG_0X2150(0x00AC) +#define REG_0X215000B0 REG_0X2150(0x00B0) +#define REG_0X215000B4 REG_0X2150(0x00B4) +#define REG_0X215000B8 REG_0X2150(0x00B8) +#define REG_0X215000BC REG_0X2150(0x00BC) +#define REG_0X215000C0 REG_0X2150(0x00C0) +#define REG_0X215000C4 REG_0X2150(0x00C4) +#define REG_0X215000C8 REG_0X2150(0x00C8) +#define REG_0X215000CC REG_0X2150(0x00CC) +#define REG_0X60100020 REG_0X6010(0x0020) +#define REG_0X60E00020 REG_0X60E0(0x0020) +#define REG_0X60D00008 REG_0X60D0(0x0008) +#define REG_0X60D00000 REG_0X60D0(0x0000) +#define REG_0X60E00038 REG_0X60E0(0x0038) +#define REG_0X60E00030 REG_0X60E0(0x0030) +#define REG_0X60E00034 REG_0X60E0(0x0034) +#define REG_0X60E00028 REG_0X60E0(0x0028) +#define REG_0X60E00024 REG_0X60E0(0x0024) +#define REG_0X60E0002C REG_0X60E0(0x002C) + +/* + * Clock (0)Name, Clock (1)fixed rate, Clock Enable (2)Ctrl and (3)Bit, + * Clock Divisor (4)Ctrl and (5)Bit, Clock Parent (6)Ctrl and (7)Bit, + * and Parent Select (15)Count and (16)Lists[ ... ...] + */ + +SCI_CLK_ADD(ext_26m, 26000000, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(ext_32k, 32768, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(ext_26m_rf1, 26000000, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(ext_1m, 1000000, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(ext_2m, 2000000, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(ext_4m, 4000000, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_pad, 64000000, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_mpll, 0, 0, 0, + REG_0X402E0044, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, 0); + +SCI_CLK_ADD(clk_dpll, 0, 0, 0, + REG_0X402E004C, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, 0); + +SCI_CLK_ADD(clk_ltepll, 0, 0, 0, + REG_0X402E005C, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, 0); + +SCI_CLK_ADD(clk_twpll, 0, 0, 0, + REG_0X402E0054, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, 0); + +SCI_CLK_ADD(clk_lvdspll, 0, 0, 0, + REG_0X402E0064, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, 0); + +SCI_CLK_ADD(clk_768m, 0, 0, 0, + 2, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_512m, 0, 0, 0, + 3, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_384m, 0, 0, 0, + 4, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_312m, 0, 0, 0, + 5, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_307m2, 0, 0, 0, + 5, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_256m, 0, 0, 0, + 6, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_192m, 0, 0, 0, + 8, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_153m6, 0, 0, 0, + 10, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_128m, 0, 0, 0, + 12, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_96m, 0, 0, 0, + 16, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_76m8, 0, 0, 0, + 20, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_64m, 0, 0, 0, + 24, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_51m2, 0, 0, 0, + 30, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_48m, 0, 0, 0, + 32, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_38m4, 0, 0, 0, + 40, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_24m, 0, 0, 0, + 64, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_12m, 0, 0, 0, + 128, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_42m_d, 0, 0, 0, + 32, 0, 0, 0, + 1, &clk_dpll); + +SCI_CLK_ADD(clk_56m_m, 0, 0, 0, + 32, 0, 0, 0, + 1, &clk_mpll); + +SCI_CLK_ADD(clk_38m4_lte, 0, 0, 0, + 32, 0, 0, 0, + 1, &clk_ltepll); + +SCI_CLK_ADD(clk_44m_lvds, 0, 0, 0, + 32, 0, 0, 0, + 1, &clk_lvdspll); + +SCI_CLK_ADD(clk_614m4, 0, 0, 0, + 2, 0, 0, 0, + 1, &clk_ltepll); + +SCI_CLK_ADD(clk_mcu, 0, 0, 0, + REG_0X20E00038, BIT(4)|BIT(5)|BIT(6), REG_0X20E00054, BIT(0)|BIT(1)|BIT(2), + 7, &ext_26m, &clk_512m, &clk_768m, &clk_dpll, &clk_ltepll, &clk_twpll, &clk_mpll); + +SCI_CLK_ADD(clk_ca7_core, 0, 0, 0, + 0, 0, 0, 0, + 1, &clk_mcu); + +SCI_CLK_ADD(clk_ca7_axi, 0, 0, 0, + REG_0X20E00038, BIT(8)|BIT(9)|BIT(10), 0, 0, + 1, &clk_mcu); + +SCI_CLK_ADD(clk_ca7_dbg, 0, 0, 0, + REG_0X20E00038, BIT(16)|BIT(17)|BIT(18), 0, 0, + 1, &clk_mcu); + +SCI_CLK_ADD(clk_emc_4x, 0, 0, 0, + REG_0X402D0020, BIT(8)|BIT(9), REG_0X402D0020, BIT(0)|BIT(1)|BIT(2), + 8, &ext_26m, &clk_192m, &clk_307m2, &clk_384m, &clk_512m, &clk_614m4, &clk_768m, &clk_dpll); + +SCI_CLK_ADD(clk_pub_ahb, 0, 0, 0, + REG_0X402D002C, BIT(8)|BIT(9), REG_0X402D002C, BIT(0)|BIT(1), + 4, &ext_26m, &ext_4m, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_aon_apb, 0, 0, 0, + REG_0X402D0030, BIT(8)|BIT(9), REG_0X402D0030, BIT(0)|BIT(1), + 4, &ext_4m, &ext_26m, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_adi, 0, REG_0X402E0000, BIT(16), + 0, 0, REG_0X402D0034, BIT(0)|BIT(1), + 4, &ext_26m, &ext_4m, &clk_38m4, &clk_51m2); + +SCI_CLK_ADD(clk_aux0, 0, REG_0X402E0004, BIT(2), + 0, 0, REG_0X402D0038, BIT(0)|BIT(1)|BIT(2), + 7, &ext_32k, &ext_26m, &ext_26m_rf1, &ext_4m, &clk_42m_d, &clk_48m, &clk_56m_m); + +SCI_CLK_ADD(clk_aux1, 0, REG_0X402E0004, BIT(3), + 0, 0, REG_0X402D003C, BIT(0)|BIT(1)|BIT(2)|BIT(3), + 9, &ext_32k, &ext_26m, &ext_26m_rf1, &ext_4m, &clk_42m_d, &clk_48m, &clk_56m_m, &clk_38m4_lte, &clk_44m_lvds); + +SCI_CLK_ADD(clk_aux2, 0, REG_0X402E0004, BIT(4), + 0, 0, REG_0X402D0040, BIT(0)|BIT(1)|BIT(2)|BIT(3), + 9, &ext_32k, &ext_26m, &ext_26m_rf1, &ext_4m, &clk_42m_d, &clk_48m, &clk_56m_m, &clk_38m4_lte, &clk_44m_lvds); + +SCI_CLK_ADD(clk_probe, 0, REG_0X402E0004, BIT(5), + 0, 0, REG_0X402D0044, BIT(0)|BIT(1)|BIT(2)|BIT(3), + 9, &ext_32k, &ext_26m, &ext_26m_rf1, &ext_4m, &clk_42m_d, &clk_48m, &clk_56m_m, &clk_38m4_lte, &clk_44m_lvds); + +SCI_CLK_ADD(clk_pwm0, 0, REG_0X402E0000, BIT(4), + 0, 0, REG_0X402D0048, BIT(0)|BIT(1), + 4, &ext_32k, &ext_26m, &ext_26m_rf1, &clk_48m); + +SCI_CLK_ADD(clk_pwm1, 0, REG_0X402E0000, BIT(5), + 0, 0, REG_0X402D004C, BIT(0)|BIT(1), + 4, &ext_32k, &ext_26m, &ext_26m_rf1, &clk_48m); + +SCI_CLK_ADD(clk_pwm2, 0, REG_0X402E0000, BIT(6), + 0, 0, REG_0X402D0050, BIT(0)|BIT(1), + 4, &ext_32k, &ext_26m, &ext_26m_rf1, &clk_48m); + +SCI_CLK_ADD(clk_pwm3, 0, REG_0X402E0000, BIT(7), + 0, 0, REG_0X402D0054, BIT(0)|BIT(1), + 4, &ext_32k, &ext_26m, &ext_26m_rf1, &clk_48m); + +SCI_CLK_ADD(clk_efuse, 0, REG_0X402E0000, BIT(13), + 0, 0, REG_0X402D0058, BIT(0), + 1, &ext_26m); + +SCI_CLK_ADD(clk_thm, 0, REG_0X402E0004, BIT(1), + 0, 0, REG_0X402D0068, BIT(0), + 2, &ext_32k, &ext_1m); + +SCI_CLK_ADD(clk_mspi, 0, REG_0X402E0000, BIT(23), + 0, 0, REG_0X402D006C, BIT(0), + 4, &ext_26m, &clk_51m2, &clk_76m8, &clk_96m); + +SCI_CLK_ADD(clk_i2c, 0, REG_0X402E0000, BIT(31), + 0, 0, REG_0X402D0070, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_avs, 0, REG_0X402E0004, BIT(6), + 0, 0, REG_0X402D0074, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_aud, 0, REG_0X402E0000, BIT(18), + 0, 0, REG_0X402D0078, BIT(0), + 1, &ext_26m); + +SCI_CLK_ADD(clk_audif, 0, REG_0X402E0000, BIT(17), + 0, 0, REG_0X402D007C, BIT(0)|BIT(1), + 3, &ext_26m, &clk_38m4, &clk_51m2); + +SCI_CLK_ADD(clk_vbc, 0, REG_0X402E0000, BIT(19), + 0, 0, REG_0X402D0080, BIT(0), + 1, &ext_26m); + +SCI_CLK_ADD(clk_ca7_dap, 0, REG_0X402E0000, BIT(30), + 0, 0, REG_0X402D0090, BIT(0)|BIT(1), + 4, &ext_26m, &clk_76m8, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_ca7_ts, 0, REG_0X402E0000, BIT(28), + 0, 0, REG_0X402D0098, BIT(0)|BIT(1), + 4, &ext_32k, &ext_26m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_djtag_tck, 0, 0, 0, + 0, 0, REG_0X402D00C8, BIT(0), + 3, &ext_26m, &ext_4m, &clk_pad); + +SCI_CLK_ADD(clk_arm7_ahb, 0, 0, 0, + REG_0X402D00CC, BIT(8)|BIT(9), REG_0X402D00CC, BIT(0)|BIT(1), + 4, &ext_4m, &ext_26m, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_ca5_ts, 0, REG_0X402E0004, BIT(26), + 0, 0, REG_0X402D00D0, BIT(0)|BIT(1), + 4, &ext_32k, &ext_26m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_disp_emc, 0, REG_0X402E0004, BIT(11), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_gsp_emc, 0, REG_0X402E0004, BIT(13), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_ap_ahb, 0, 0, 0, + 0, 0, REG_0X21500020, BIT(0)|BIT(1), + 4, &ext_26m, &clk_76m8, &clk_128m, &clk_192m); + +SCI_CLK_ADD(clk_ap_apb, 0, 0, 0, + 0, 0, REG_0X21500024, BIT(0)|BIT(1), + 4, &ext_26m, &clk_64m, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_gsp, 0, REG_0X20E00000, BIT(3), + 0, 0, REG_0X21500028, BIT(0)|BIT(1), + 4, &clk_96m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_dispc0, 0, REG_0X20E00000, BIT(1), + REG_0X2150002C, BIT(8)|BIT(9)|BIT(10), REG_0X2150002C, BIT(0)|BIT(1), + 4, &clk_153m6, &clk_192m, &clk_256m, &clk_307m2); + +SCI_CLK_ADD(clk_dispc0_dbi, 0, 0, 0, + REG_0X21500030, BIT(8)|BIT(9)|BIT(10), REG_0X21500030, BIT(0)|BIT(1), + 4, &clk_128m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_dispc0_dpi, 0, 0, 0, + REG_0X21500034, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), REG_0X21500034, BIT(0)|BIT(1), + 5, &clk_128m, &clk_153m6, &clk_192m, &clk_384m, &clk_pad); + +SCI_CLK_ADD(clk_nandc_2x, 0, REG_0X20E00000, BIT(18), + 0, 0, REG_0X21500054, BIT(0)|BIT(1), + 4, &clk_192m, &clk_256m, &clk_307m2, &clk_384m); + +SCI_CLK_ADD(clk_nandc_ecc, 0, REG_0X20E00000, BIT(19), + 0, 0, REG_0X21500058, BIT(0), + 2, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_sdio0, 0, REG_0X20E00000, BIT(8), + REG_0X2150005C, BIT(8)|BIT(9)|BIT(10), REG_0X2150005C, BIT(0)|BIT(1), + 4, &ext_26m, &clk_256m, &clk_307m2, &clk_384m); + +SCI_CLK_ADD(clk_sdio1, 0, REG_0X20E00000, BIT(9), + 0, 0, REG_0X21500060, BIT(0)|BIT(1), + 4, &clk_48m, &clk_76m8, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_sdio2, 0, REG_0X20E00000, BIT(10), + 0, 0, REG_0X21500068, BIT(0)|BIT(1), + 4, &clk_48m, &clk_76m8, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_emmc, 0, REG_0X20E00000, BIT(11), + 0, 0, REG_0X21500070, BIT(0)|BIT(1), + 4, &ext_26m, &clk_256m, &clk_307m2, &clk_384m); + +SCI_CLK_ADD(clk_otg_ref, 0, REG_0X20E00000, BIT(4), + 0, 0, REG_0X21500074, BIT(0), + 2, &clk_12m, &clk_24m); + +SCI_CLK_ADD(clk_hsic_ref, 0, REG_0X20E00000, BIT(2), + 0, 0, REG_0X2150007C, BIT(0), + 2, &clk_12m, &clk_24m); + +SCI_CLK_ADD(clk_uart0, 0, REG_0X71300000, BIT(13), + REG_0X21500084, BIT(8)|BIT(9)|BIT(10), REG_0X21500084, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart1, 0, REG_0X71300000, BIT(14), + REG_0X21500088, BIT(8)|BIT(9)|BIT(10), REG_0X21500088, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart2, 0, REG_0X71300000, BIT(15), + REG_0X2150008C, BIT(8)|BIT(9)|BIT(10), REG_0X2150008C, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart3, 0, REG_0X71300000, BIT(16), + REG_0X21500090, BIT(8)|BIT(9)|BIT(10), REG_0X21500090, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart4, 0, REG_0X71300000, BIT(17), + REG_0X21500094, BIT(8)|BIT(9)|BIT(10), REG_0X21500094, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_i2c0, 0, REG_0X71300000, BIT(8), + REG_0X21500098, BIT(8)|BIT(9)|BIT(10), REG_0X21500098, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_i2c1, 0, REG_0X71300000, BIT(9), + REG_0X2150009C, BIT(8)|BIT(9)|BIT(10), REG_0X2150009C, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_i2c2, 0, REG_0X71300000, BIT(10), + REG_0X215000A0, BIT(8)|BIT(9)|BIT(10), REG_0X215000A0, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_i2c3, 0, REG_0X71300000, BIT(11), + REG_0X215000A4, BIT(8)|BIT(9)|BIT(10), REG_0X215000A4, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_i2c4, 0, REG_0X71300000, BIT(12), + REG_0X215000A8, BIT(8)|BIT(9)|BIT(10), REG_0X215000A8, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_spi0, 0, REG_0X71300000, BIT(5), + REG_0X215000AC, BIT(8)|BIT(9)|BIT(10), REG_0X215000AC, BIT(0)|BIT(1), + 5, &ext_26m, &clk_96m, &clk_153m6, &clk_192m, &clk_pad); + +SCI_CLK_ADD(clk_spi1, 0, REG_0X71300000, BIT(6), + REG_0X215000B0, BIT(8)|BIT(9)|BIT(10), REG_0X215000B0, BIT(0)|BIT(1), + 5, &ext_26m, &clk_96m, &clk_153m6, &clk_192m, &clk_pad); + +SCI_CLK_ADD(clk_spi2, 0, REG_0X71300000, BIT(7), + REG_0X215000B4, BIT(8)|BIT(9)|BIT(10), REG_0X215000B4, BIT(0)|BIT(1), + 5, &ext_26m, &clk_96m, &clk_153m6, &clk_192m, &clk_pad); + +SCI_CLK_ADD(clk_iis0, 0, REG_0X71300000, BIT(1), + REG_0X215000B8, BIT(8)|BIT(9)|BIT(10), REG_0X215000B8, BIT(0)|BIT(1), + 4, &ext_26m, &clk_128m, &clk_153m6, &clk_pad); + +SCI_CLK_ADD(clk_iis1, 0, REG_0X71300000, BIT(2), + REG_0X215000BC, BIT(8)|BIT(9)|BIT(10), REG_0X215000BC, BIT(0)|BIT(1), + 4, &ext_26m, &clk_128m, &clk_153m6, &clk_pad); + +SCI_CLK_ADD(clk_iis2, 0, REG_0X71300000, BIT(3), + REG_0X215000C0, BIT(8)|BIT(9)|BIT(10), REG_0X215000C0, BIT(0)|BIT(1), + 4, &ext_26m, &clk_128m, &clk_153m6, &clk_pad); + +SCI_CLK_ADD(clk_iis3, 0, REG_0X71300000, BIT(4), + REG_0X215000C4, BIT(8)|BIT(9)|BIT(10), REG_0X215000C4, BIT(0)|BIT(1), + 4, &ext_26m, &clk_128m, &clk_153m6, &clk_pad); + +SCI_CLK_ADD(clk_zipenc, 0, REG_0X20E00000, BIT(20), + 0, 0, REG_0X215000C8, BIT(0)|BIT(1), + 4, &clk_96m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_zipdec, 0, REG_0X20E00000, BIT(21), + 0, 0, REG_0X215000CC, BIT(0)|BIT(1), + 4, &clk_96m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_gpu_i, 0, REG_0X402E0000, BIT(27), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_gpu, 0, REG_0X402E0000, BIT(27), + REG_0X60100020, BIT(8)|BIT(9), REG_0X60100020, BIT(0)|BIT(1)|BIT(2), + 6, &clk_153m6, &clk_192m, &clk_256m, &clk_307m2, &clk_384m, &clk_512m); + +SCI_CLK_ADD(clk_mm_i, 0, REG_0X402E0000, BIT(25), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_mm_ahb, 0, 0, 0, + 0, 0, REG_0X60E00020, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_mm_axi, 0, REG_0X60D00008, BIT(7), + 0, 0, 0, 0, + 1, &clk_mm_i); + +SCI_CLK_ADD(clk_mm_mtx_axi, 0, REG_0X60D00008, BIT(8), + 0, 0, 0, 0, + 1, &clk_mm_axi); + +SCI_CLK_ADD(clk_mmu, 0, REG_0X60D00000, BIT(7), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_mm_ckg, 0, REG_0X60D00000, BIT(6), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_jpg, 0, REG_0X60D00008, BIT(6), + 0, 0, REG_0X60E00038, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_256m, &clk_312m); + +SCI_CLK_ADD(clk_csi, 0, REG_0X60D00008, BIT(1), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_dcam_mipi, 0, REG_0X60D00008, BIT(0), + 0, 0, 0, 0, + 1, &clk_csi); + +SCI_CLK_ADD(clk_vsp, 0, REG_0X60D00008, BIT(5), + 0, 0, REG_0X60E00030, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_256m, &clk_312m); + +SCI_CLK_ADD(clk_isp, 0, REG_0X60D00008, BIT(4), + 0, 0, REG_0X60E00034, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_256m, &clk_312m); + +SCI_CLK_ADD(clk_ccir, 0, REG_0X60D00000, BIT(1), + 0, 0, REG_0X60E00028, BIT(16), + 2, &clk_24m, &clk_pad); + +SCI_CLK_ADD(clk_sensor, 0, REG_0X60D00008, BIT(2), + REG_0X60E00024, BIT(8)|BIT(9)|BIT(10), REG_0X60E00024, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_76m8, &clk_96m); + +SCI_CLK_ADD(clk_dcam, 0, REG_0X60D00008, BIT(3), + 0, 0, REG_0X60E0002C, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_256m, &clk_312m); + diff --git a/include/soc/sprd/clkdev.h b/include/soc/sprd/clkdev.h new file mode 100644 index 00000000..730c49d1 --- /dev/null +++ b/include/soc/sprd/clkdev.h @@ -0,0 +1,13 @@ +#ifndef __MACH_CLKDEV_H +#define __MACH_CLKDEV_H + +static inline int __clk_get(struct clk *clk) +{ + return 1; +} + +static inline void __clk_put(struct clk *clk) +{ +} + +#endif diff --git a/include/soc/sprd/common.h b/include/soc/sprd/common.h new file mode 100644 index 00000000..e10c6c65 --- /dev/null +++ b/include/soc/sprd/common.h @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARCH_SPRD_COMMON_H +#define __ASM_ARCH_SPRD_COMMON_H + +#define INTC_DYNAMIC_CLK_GATE_EN (1<<6) +#define SCU_DYNAMIC_CLK_GATE_EN (1<<5) + +extern void __iomem *sprd_get_gic_dist_base(void); +extern void __iomem *sprd_get_gic_cpu_base(void); + + +extern void gic_cpu_enable(unsigned int cpu); +extern void gic_cpu_disable(unsigned int cpu); +extern void gic_dist_enable(void); +extern void gic_dist_disable(void); + + +extern void sprd_pm_cpu_enter_lowpower(unsigned int cpu); +extern void __iomem *sprd_get_scu_base(void); +#endif diff --git a/include/soc/sprd/cpuidle.h b/include/soc/sprd/cpuidle.h new file mode 100755 index 00000000..609d4128 --- /dev/null +++ b/include/soc/sprd/cpuidle.h @@ -0,0 +1,10 @@ +#ifndef _MACH_SC_CPUIDLE_H +#define _MACH_SC_CPUIDLE_H + +/* cpuidle events */ +#define SC_CPUIDLE_PREPARE 0x01 /* Going to light sleep status */ + +extern int register_sc_cpuidle_notifier(struct notifier_block *nb); +extern int unregister_sc_cpuidle_notifier(struct notifier_block *nb); + +#endif diff --git a/include/soc/sprd/debug-macro.S b/include/soc/sprd/debug-macro.S new file mode 100644 index 00000000..d7394ea9 --- /dev/null +++ b/include/soc/sprd/debug-macro.S @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "hardware.h" + + .macro addruart,rp, rv, tmp + ldr \rp, =LL_DEBUG_UART_PHYS + ldr \rv, =LL_DEBUG_UART_BASE + .endm + + .macro senduart,rd,rx + and \rd,\rd,#0xFF + str \rd, [\rx, #0x00] + .endm + + .macro waituart,rd,rx + @ wait for TX_READY +1: ldr \rd, [\rx, #0x0C] + mov \rd,\rd,lsr #8 + and \rd,\rd,#0xFF + teq \rd, #0x00 + bne 1b + .endm + + .macro busyuart,rd,rx + @ wait for TX_READY +2: ldr \rd, [\rx, #0x0C] + mov \rd,\rd,lsr #8 + and \rd,\rd,#0xFF + teq \rd, #0x00 + bne 2b + .endm diff --git a/include/soc/sprd/dma.h b/include/soc/sprd/dma.h new file mode 100644 index 00000000..b165d19f --- /dev/null +++ b/include/soc/sprd/dma.h @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_DMA_H +#define __MACH_DMA_H + + +#if defined(CONFIG_ARCH_SC8825) || defined(CONFIG_ARCH_SC7710) +#define DMA_VER_R1P0 +#include <soc/sprd/dma_r1p0.h> + +#define DMA_UID_SOFTWARE 0 +#define DMA_UART0_TX 1 +#define DMA_UART0_RX 2 +#define DMA_UART1_TX 3 +#define DMA_UART1_RX 4 +#define DMA_UART2_TX 5 +#define DMA_UART2_RX 6 +#define DMA_IIS_TX 7 +#define DMA_IIS_RX 8 +#define DMA_EPT_RX 9 +#define DMA_EPT_TX 10 +#define DMA_VB_DA0 11 +#define DMA_VB_DA1 12 +#define DMA_VB_AD0 13 +#define DMA_VB_AD1 14 +#define DMA_SIM0_TX 15 +#define DMA_SIM0_RX 16 +#define DMA_SIM1_TX 17 +#define DMA_SIM1_RX 18 +#define DMA_SPI0_TX 19 +#define DMA_SPI0_RX 20 +#define DMA_ROT 21 +#define DMA_SPI1_TX 22 +#define DMA_SPI1_RX 23 +#define DMA_IIS1_TX 24 +#define DMA_IIS1_RX 25 +#define DMA_NFC_TX 26 +#define DMA_NFC_RX 27 +#define DMA_DRM_RAW 29 +#define DMA_DRM_CPT 30 + +#define DMA_UID_MIN 0 +#define DMA_UID_MAX 32 + +#endif + + +#ifdef CONFIG_ARCH_SCX35 +#define DMA_VER_R4P0 +#include <soc/sprd/dma_r4p0.h> +/*DMA Request ID def*/ +#define DMA_SIM_RX 1 +#define DMA_SIM_TX 2 +#define DMA_IIS0_RX 3 +#define DMA_IIS0_TX 4 +#define DMA_IIS1_RX 5 +#define DMA_IIS1_TX 6 +#define DMA_IIS2_RX 7 +#define DMA_IIS2_TX 8 +#define DMA_IIS3_RX 9 +#define DMA_IIS3_TX 10 +#define DMA_SPI0_RX 11 +#define DMA_SPI0_TX 12 +#define DMA_SPI1_RX 13 +#define DMA_SPI1_TX 14 +#define DMA_SPI2_RX 15 +#define DMA_SPI2_TX 16 +#define DMA_UART0_RX 17 +#define DMA_UART0_TX 18 +#define DMA_UART1_RX 19 +#define DMA_UART1_TX 20 +#define DMA_UART2_RX 21 +#define DMA_UART2_TX 22 +#define DMA_UART3_RX 23 +#define DMA_UART3_TX 24 +#define DMA_UART4_RX 25 +#define DMA_UART4_TX 26 +#define DMA_DRM_CPT 27 +#define DMA_DRM_RAW 28 +#define DMA_VB_DA0 29 +#define DMA_VB_DA1 30 +#define DMA_VB_AD0 31 +#define DMA_VB_AD1 32 +#define DMA_VB_AD2 33 +#define DMA_VB_AD3 34 +#define DMA_GPS 35 + +#define DMA_IIS_RX DMA_IIS0_RX +#define DMA_IIS_TX DMA_IIS0_TX + +#endif + +#endif diff --git a/include/soc/sprd/dma_r4p0.h b/include/soc/sprd/dma_r4p0.h new file mode 100644 index 00000000..b8ef71e2 --- /dev/null +++ b/include/soc/sprd/dma_r4p0.h @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARCH_SPRD_DMA_H +#define __ASM_ARCH_SPRD_DMA_H + +#define IRQ_DMA_INT 82 + +#ifdef CONFIG_ARCH_SCX35 +/*logic dma chn = phy dma chn + 1*/ +#define LOGIC_PHY_DMA_CHN_OFFSET 1 +#define AP_DMA_CHN_START LOGIC_PHY_DMA_CHN_OFFSET +#define DMA_CHN_MIN LOGIC_PHY_DMA_CHN_OFFSET + +#ifdef AON_DMA_SUPPORT +/*AP 32 DMA chns + AON 32 DMA chns*/ +#define DMA_CHN_MAX 64 +#else +#define DMA_CHN_MAX 32 +#endif + +#define STD_CHN_START 0 +#define STD_CHN_END 23 +#define FULL_CHN_START 24 +#define FULL_CHN_END 31 + +#ifdef AON_DMA_SUPPORT +#define AON_DMA_CHN_START (FULL_CHN_END + LOGIC_PHY_DMA_CHN_OFFSET + 1) +#endif + +#define DMA_UID_SOFTWARE 0 +#define DMA_LINKLIST_CFG_NODE_SIZE 64 + +#endif + + +typedef enum { + NO_INT = 0x00, + FRAG_DONE, + BLK_DONE, + LIST_DONE, + TRANS_DONE, + CONFIG_ERR, +} dma_int_type; + +typedef enum { + BYTE_WIDTH = 0X01, + SHORT_WIDTH, + WORD_WIDTH, +} dma_datawidth; + +typedef enum { + DMA_PRI_0 = 0, + DMA_PRI_1, + DMA_PRI_2, + DMA_PRI_3, +} dma_pri_level; + +typedef enum { + STD_DMA_CHN, + FULL_DMA_CHN, +#ifdef AON_DMA_SUPPORT + AON_STD_DMA_CHN, + AON_FULL_DMA_CHN, +#endif +} dma_chn_type; + +struct reg_cfg_addr { + unsigned long virt_addr; + u32 phys_addr; +}; + +typedef enum { + FRAG_REQ_MODE = 0x0, + BLOCK_REQ_MODE, + TRANS_REQ_MODE, + LIST_REQ_MODE, +} dma_request_mode; + +struct sci_dma_cfg { + dma_datawidth datawidth; + u32 src_addr; + u32 des_addr; + u32 fragmens_len; + u32 block_len; + u32 src_step; + u32 des_step; + dma_request_mode req_mode; + /*only full chn need following config*/ + u32 transcation_len; + u32 src_frag_step; + u32 dst_frag_step; + u32 wrap_ptr; + u32 wrap_to; + u32 src_blk_step; + u32 dst_blk_step; + u32 linklist_ptr; + u32 is_end; +}; + +typedef enum { + SET_IRQ_TYPE = 0x0, + SET_WRAP_MODE, + SET_REQ_MODE, + SET_CHN_PRIO, + SET_INT_TYPE, +} dma_cmd; + + +int sci_dma_request(const char *dev_name, dma_chn_type chn_type); +int sci_dma_free(u32 dma_chn); +int sci_dma_config(u32 dma_chn, struct sci_dma_cfg *cfg_list, + u32 node_size, struct reg_cfg_addr *cfg_addr); + +int sci_dma_register_irqhandle(u32 dma_chn, dma_int_type int_type, + void (*irq_handle) (int, void *), void *data); +int sci_dma_start(u32 dma_chn, u32 dev_id); +int sci_dma_stop(u32 dma_chn, u32 dev_id); +u32 sci_dma_get_src_addr(u32 dma_chn); +u32 sci_dma_get_dst_addr(u32 dma_chn); +int sci_dma_dump_reg(u32 dma_chn, u32 *reg_base); +int sci_dma_memcpy(u32 dest, u32 src, size_t size); +#endif diff --git a/include/soc/sprd/dma_reg.h b/include/soc/sprd/dma_reg.h new file mode 100644 index 00000000..05c034c7 --- /dev/null +++ b/include/soc/sprd/dma_reg.h @@ -0,0 +1,211 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARCH_SPRD_DMA_REG_H +#define __ASM_ARCH_SPRD_DMA_REG_H + +#include <linux/interrupt.h> +#include <asm/io.h> +#include <soc/sprd/dma.h> + +/**----------------------------------------------------------------------------* +** Micro Define ** +**----------------------------------------------------------------------------*/ + +/*dma r1p0 register offset define start*/ +#ifdef DMA_VER_R1P0 +#define DMA_REG_BASE SPRD_DMA0_BASE + +/* 0X00 */ +#define DMA_BLK_WAIT (DMA_REG_BASE + 0x0000) +#define DMA_CHN_EN_STATUS (DMA_REG_BASE + 0x0004) +#define DMA_LINKLIST_EN (DMA_REG_BASE + 0x0008) +#define DMA_SOFTLINK_EN (DMA_REG_BASE + 0x000C) + +/* 0X10 */ +#define DMA_SOFTLIST_SIZE (DMA_REG_BASE + 0x0010) +#define DMA_SOFTLIST_CMD (DMA_REG_BASE + 0x0014) +#define DMA_SOFTLIST_STS (DMA_REG_BASE + 0x0018) +#define DMA_SOFTLIST_BASEADDR (DMA_REG_BASE + 0x001C) + +/* 0X20 */ +#define DMA_PRI_REG0 (DMA_REG_BASE + 0x0020) +#define DMA_PRI_REG1 (DMA_REG_BASE + 0x0024) + +/* 0X30 */ +#define DMA_INT_STS (DMA_REG_BASE + 0x0030) +#define DMA_INT_RAW (DMA_REG_BASE + 0x0034) + +/* 0X40 */ +#define DMA_LISTDONE_INT_EN (DMA_REG_BASE + 0x0040) +#define DMA_BLOCK_INT_EN (DMA_REG_BASE + 0x0044) +#define DMA_TRANSF_INT_EN (DMA_REG_BASE + 0x0048) + +/* 0X50 */ +#define DMA_LISTDONE_INT_STS (DMA_REG_BASE + 0x0050) +#define DMA_BURST_INT_STS (DMA_REG_BASE + 0x0054) +#define DMA_TRANSF_INT_STS (DMA_REG_BASE + 0x0058) + +/* 0X60 */ +#define DMA_LISTDONE_INT_RAW (DMA_REG_BASE + 0x0060) +#define DMA_BURST_INT_RAW (DMA_REG_BASE + 0x0064) +#define DMA_TRANSF_INT_RAW (DMA_REG_BASE + 0x0068) + +/* 0X70 */ +#define DMA_LISTDONE_INT_CLR (DMA_REG_BASE + 0x0070) +#define DMA_BURST_INT_CLR (DMA_REG_BASE + 0x0074) +#define DMA_TRANSF_INT_CLR (DMA_REG_BASE + 0x0078) + +/* 0X80 */ +#define DMA_SOFT_REQ (DMA_REG_BASE + 0x0080) +#define DMA_TRANS_STS (DMA_REG_BASE + 0x0084) +#define DMA_REQ_PEND (DMA_REG_BASE + 0x0088) + +/* 0X90 */ +#define DMA_WRAP_START (DMA_REG_BASE + 0x0090) +#define DMA_WRAP_END (DMA_REG_BASE + 0x0094) + +#define DMA_CHN_UID_BASE (DMA_REG_BASE + 0x0098) +#define DMA_CHN_UID0 (DMA_REG_BASE + 0x0098) +#define DMA_CHN_UID1 (DMA_REG_BASE + 0x009C) +#define DMA_CHN_UID2 (DMA_REG_BASE + 0x00A0) +#define DMA_CHN_UID3 (DMA_REG_BASE + 0x00A4) +#define DMA_CHN_UID4 (DMA_REG_BASE + 0x00A8) +#define DMA_CHN_UID5 (DMA_REG_BASE + 0x00AC) +#define DMA_CHN_UID6 (DMA_REG_BASE + 0x00B0) +#define DMA_CHN_UID7 (DMA_REG_BASE + 0x00B4) + +#define DMA_CHx_EN (DMA_REG_BASE + 0x00C0) +#define DMA_CHx_DIS (DMA_REG_BASE + 0x00C4) + +/* Chanel x dma contral regisers address offset*/ +#define DMA_CH_CFG (0x0000) +#define DMA_CH_TOTAL_LEN (0x0004) +#define DMA_CH_SRC_ADDR (0x0008) +#define DMA_CH_DEST_ADDR (0x000c) +#define DMA_CH_LLPTR (0x0010) +#define DMA_CH_SDEP (0x0014) +#define DMA_CH_SBP (0x0018) +#define DMA_CH_DBP (0x001c) + +/* Channel x dma contral regisers address */ +#define DMA_CHx_CTL_BASE (DMA_REG_BASE + 0x0400) +#define DMA_CHx_OFFSET (0x20) +#define DMA_CHx_BASE(x) (DMA_CHx_CTL_BASE + DMA_CHx_OFFSET * x ) +#define DMA_CHx_CFG(x) (DMA_CHx_BASE(x) + DMA_CH_CFG) +#define DMA_CHx_TOTAL_LEN(x) (DMA_CHx_BASE(x) + DMA_CH_TOTAL_LEN) +#define DMA_CHx_SRC_ADDR(x) (DMA_CHx_BASE(x) + DMA_CH_SRC_ADDR) +#define DMA_CHx_DEST_ADDR(x) (DMA_CHx_BASE(x) + DMA_CH_DEST_ADDR) +#define DMA_CHx_LLPTR(x) (DMA_CHx_BASE(x) + DMA_CH_LLPTR) +#define DMA_CHx_SDEP(x) (DMA_CHx_BASE(x) + DMA_CH_SDEP) +#define DMA_CHx_SBP(x) (DMA_CHx_BASE(x) + DMA_CH_SBP) +#define DMA_CHx_DBP(x) (DMA_CHx_BASE(x) + DMA_CH_DBP) + +/*there is no different between full and std chn is DMA r1p0*/ +struct sci_dma_reg { + u32 cfg; + u32 total_len; + u32 src_addr; + u32 des_addr; + u32 llist_ptr; + u32 elem_postm; + u32 src_blk_postm; + u32 des_blk_postm; +}; + +#endif +/*dma r1p0 register offset define end*/ + +/*dma r3p0 and r4p0 register offset define start*/ +#ifdef DMA_VER_R4P0 + +#define DMA_CHx_OFFSET (0x40) +#define DMA_CHx_BASE(reg_base, chn) \ + (reg_base + 0x1000 + DMA_CHx_OFFSET * (chn)) + +#define DMA_REQ_CID(reg_base, uid) (reg_base + 0x2000 + 0x4 * ((uid) -1)) + + +/*FRAG_LEN*/ +#define CHN_PRIORITY_OFFSET 12 +#define CHN_PRIORITY_MASK 0x3 +#define LLIST_EN_OFFSET 4; + +#define SRC_DATAWIDTH_OFFSET 30 +#define DES_DATAWIDTH_OFFSET 28 +#define SWT_MODE_OFFSET 26 +#define REQ_MODE_OFFSET 24 +#define ADDR_WRAP_SEL_OFFSET 23 +#define ADDR_WRAP_EN_OFFSET 22 +#define ADDR_FIX_SEL_OFFSET 21 +#define ADDR_FIX_SEL_EN 20 +#define LLIST_END_OFFSET 19 +#define BLK_LEN_REC_H_OFFSET 17 +#define FRG_LEN_OFFSET 0 + +#define DEST_TRSF_STEP_OFFSET 16 +#define SRC_TRSF_STEP_OFFSET 0 +#define DEST_FRAG_STEP_OFFSET 16 +#define SRC_FRAG_STEP_OFFSET 0 + +#define TRSF_STEP_MASK 0xffff +#define FRAG_STEP_MASK 0xffff + +#define DATAWIDTH_MASK 0x3 +#define SWT_MODE_MASK 0x3 +#define REQ_MODE_MASK 0x3 +#define ADDR_WRAP_SEL_MASK 0x1 +#define ADDR_WRAP_EN_MASK 0x1 +#define ADDR_FIX_SEL_MASK 0x1 +#define ADDR_FIX_SEL_MASK 0x1 +#define LLIST_END_MASK 0x1 +#define BLK_LEN_REC_H_MASKT 0x3 +#define FRG_LEN_MASK 0x1ffff + +#define BLK_LEN_MASK 0x1ffff +#define TRSC_LEN_MASK 0xfffffff + +struct sci_dma_glb_reg { + u32 pause; + u32 frag_wait; + u32 pend0_en; + u32 pend1_en; + u32 int_raw_sts; + u32 int_msk_sts; + u32 req_sts; + u32 en_sts; + u32 debug_sts; + u32 arb_sel_sts; +}; + +struct sci_dma_chn_reg { + u32 pause; + u32 req; + u32 cfg; + u32 intc; + u32 src_addr; + u32 des_addr; + u32 frg_len; + u32 blk_len; + /* only full chn have following regs */ + u32 trsc_len; + u32 trsf_step; + u32 wrap_ptr; + u32 wrap_to; + u32 llist_ptr; + u32 frg_step; + u32 src_blk_step; + u32 des_blk_step; +}; +#endif +#endif diff --git a/include/soc/sprd/efuse.h b/include/soc/sprd/efuse.h new file mode 100644 index 00000000..3a32e8f9 --- /dev/null +++ b/include/soc/sprd/efuse.h @@ -0,0 +1,43 @@ +/* * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __EFUSE_H__ +#define __EFUSE_H__ + +//interface params.definition, pls don't modify it +#define __EFUSE_DDIE(_X_) ((_X_) | 0x0) +#define ADIE_EFUSE_MSK (0x1 << 16) +#define __EFUSE_ADIE(_X_) ((_X_) | ADIE_EFUSE_MSK) + +//blk id define +#define EFUSE_DDIE_BLK_0 __EFUSE_DDIE(0) +#define EFUSE_DDIE_BLK_1 __EFUSE_DDIE(1) +#define EFUSE_DDIE_BLK_2 __EFUSE_DDIE(2) +#define EFUSE_DDIE_BLK_3 __EFUSE_DDIE(3) +#define EFUSE_DDIE_BLK_4 __EFUSE_DDIE(4) +#define EFUSE_DDIE_BLK_5 __EFUSE_DDIE(5) +#define EFUSE_DDIE_BLK_6 __EFUSE_DDIE(6) +#define EFUSE_DDIE_BLK_7 __EFUSE_DDIE(7) + +#define EFUSE_ADIE_BLK_0 __EFUSE_ADIE(0) + +/** + * sci_efuse_get(u32 blk) - read data from the specified adie/deie efuse block; + * @blk: blk is the number that indicate block type(Adie/Ddie) and index number. + * This function will read data from the block, + * pls use the blk id MACRO to indicate blk. + */ +int sci_efuse_get(u32 blk); + + +#endif diff --git a/include/soc/sprd/entry-macro.S b/include/soc/sprd/entry-macro.S new file mode 100644 index 00000000..1312f11b --- /dev/null +++ b/include/soc/sprd/entry-macro.S @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef CONFIG_ARM_GIC +#include <mach/hardware.h> + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + @ enable imprecise aborts + @cpsie a + ldr \base, =SPRD_INTC0_BASE + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + @ldr \irqstat, [\base, #0x0004] + ldr \irqstat, [\base] + cmp \irqstat, #0 + clzne \irqnr, \irqstat + rsbne \irqnr, \irqnr, #31 + .endm + +#endif diff --git a/include/soc/sprd/globalregs.h b/include/soc/sprd/globalregs.h new file mode 100644 index 00000000..da709fe5 --- /dev/null +++ b/include/soc/sprd/globalregs.h @@ -0,0 +1,345 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARM_ARCH_GLOBALREGS_H +#define __ASM_ARM_ARCH_GLOBALREGS_H + +#if defined (CONFIG_ARCH_SC8825) + +#include <mach/hardware.h> + +/* general global register offset */ +#define GR_GEN0 0x0008 +#define GR_PCTL 0x000C +#define GR_IRQ 0x0010 +#define GR_ICLR 0x0014 +#define GR_GEN1 0x0018 +#define GR_GEN3 0x001C +#define GR_BOOT_FLAG 0x0020 /* GR_HWRST */ +#define GR_MPLL_MN 0x0024 +#define GR_PIN_CTL 0x0028 +#define GR_GEN2 0x002C +#define GR_ARM_BOOT_ADDR 0x0030 +#define GR_STC_STATE 0x0034 +#define GR_DPLL_CTRL 0x0040 +#define GR_BUSCLK 0x0044 /* GR_BUSCLK_ALM */ +#define GR_ARCH_CTL 0x0048 +#define GR_SOFT_RST 0x004C /* GR_SOFT_RST */ +#define GR_NFC_MEM_DLY 0x0058 +#define GR_CLK_DLY 0x005C +#define GR_GEN4 0x0060 +#define GR_POWCTL0 0x0068 +#define GR_POWCTL1 0x006C +#define GR_PLL_SCR 0x0070 +#define GR_CLK_EN 0x0074 +#define GR_CLK_GEN5 0x007C +#define GR_GPU_PWR_CTRL 0x0080 +#define GR_MM_PWR_CTRL 0x0084 +#define GR_CEVA_RAM_TH_PWR_CTRL 0x0088 +#define GR_GSM_PWR_CTRL 0x008C +#define GR_TD_PWR_CTRL 0x0090 +#define GR_PERI_PWR_CTRL 0x0094 +#define GR_CEVA_RAM_BH_PWR_CTRL 0x0098 +#define GR_ARM_SYS_PWR_CTRL 0x009C +#define GR_G3D_PWR_CTRL 0x00A0 + +#define GR_SWRST GR_SOFT_RST +#define GR_BUSCLK_ALM GR_BUSCLK + +/* the GEN0 register bit */ +#define GEN0_UART3_EN BIT(0) +#define GEN0_SPI2_EN BIT(1) +#define GEN0_TIMER_EN BIT(2) +#define GEN0_SIM0_EN BIT(3) +#define GEN0_I2C_EN BIT(4) +#define GEN0_I2C0_EN GEN0_I2C_EN +#define GEN0_GPIO_EN BIT(5) +#define GEN0_ADI_EN BIT(6) +#define GEN0_EFUSE_EN BIT(7) +#define GEN0_KPD_EN BIT(8) +#define GEN0_EIC_EN BIT(9) +#define GEN0_MCU_DSP_RST BIT(10) +#define GEN0_MCU_SOFT_RST BIT(11) +#define GEN0_I2S_EN BIT(12) +#define GEN0_I2S0_EN GEN0_I2S_EN +#define GEN0_PIN_EN BIT(13) +#define GEN0_CCIR_MCLK_EN BIT(14) +#define GEN0_EPT_EN BIT(15) +#define GEN0_SIM1_EN BIT(16) +#define GEN0_SPI_EN BIT(17) +#define GEN0_SPI0_EN GEN0_SPI_EN +#define GEN0_SPI1_EN BIT(18) +#define GEN0_SYST_EN BIT(19) +#define GEN0_UART0_EN BIT(20) +#define GEN0_UART1_EN BIT(21) +#define GEN0_UART2_EN BIT(22) +#define GEN0_VB_EN BIT(23) +#define GEN0_GPIO_RTC_EN BIT(24) +#define GEN0_EIC_RTC_EN GEN0_GPIO_RTC_EN +#define GEN0_I2S1_EN BIT(25) +#define GEN0_KPD_RTC_EN BIT(26) +#define GEN0_SYST_RTC_EN BIT(27) +#define GEN0_TMR_RTC_EN BIT(28) +#define GEN0_I2C1_EN BIT(29) +#define GEN0_I2C2_EN BIT(30) +#define GEN0_I2C3_EN BIT(31) + +/* GR_PCTL */ +#define MCU_MPLL_EN BIT(1) + +/* GR_GEN1 */ +#define GEN1_MPLL_MN_EN BIT(9) +#define GEN1_CLK_AUX0_EN BIT(10) +#define GEN1_CLK_AUX1_EN BIT(11) +#define GEN1_RTC_ARCH_EN BIT(18) +#define GEN1_VBC_EN BIT(14) +#define GEN1_AUX0_EN BIT(11) +#define GEN1_AUX1_EN BIT(10) + +/* the APB Soft Reset register bit */ +#define SWRST_I2C_RST BIT(0) +#define SWRST_KPD_RST BIT(1) +#define SWRST_SIM0_RST BIT(5) +#define SWRST_SIM1_RST BIT(6) +#define SWRST_TIMER_RST BIT(8) +#define SWRST_EPT_RST BIT(10) +#define SWRST_UART0_RST BIT(11) +#define SWRST_UART1_RST BIT(12) +#define SWRST_UART2_RST BIT(13) +#define SWRST_SPI0_RST BIT(14) +#define SWRST_SPI1_RST BIT(15) +#define SWRST_IIS_RST BIT(16) +#define SWRST_SYST_RST BIT(19) +#define SWRST_PINREG_RST BIT(20) +#define SWRST_GPIO_RST BIT(21) +#define SWRST_ADI_RST BIT(22) +#define SWRST_VBC_RST BIT(23) +#define SWRST_PWM0_RST BIT(24) +#define SWRST_PWM1_RST BIT(25) +#define SWRST_PWM2_RST BIT(26) +#define SWRST_PWM3_RST BIT(27) +#define SWRST_EFUSE_RST BIT(28) +#define SWRST_SPI2_RST BIT(31) + +/* the ARM VB CTRL register bit */ +#define ARM_VB_IIS_SEL BIT(0) +#define ARM_VB_MCLKON BIT(1) +#define ARM_VB_DA0ON BIT(2) +#define ARM_VB_DA1ON BIT(3) +#define ARM_VB_AD0ON BIT(4) +#define ARM_VB_AD1ON BIT(5) +#define ARM_VB_ANAON BIT(6) +#define ARM_VB_ACC BIT(27) +#define ARM_VB_SEL BIT(28) +#define ARM_VB_ADCON ARM_VB_AD0ON + +/* the Interrupt control register bit */ +#define IRQ_MCU_IRQ0 BIT(0) +#define IRQ_MCU_FRQ0 BIT(1) +#define IRQ_MCU_IRQ1 BIT(2) +#define IRQ_MCU_FRQ1 BIT(3) +#define IRQ_VBCAD_IRQ BIT(5) +#define IRQ_VBCDA_IRQ BIT(6) +#define IRQ_RFT_INT BIT(12) + +/* the Interrupt clear register bit */ +#define ICLR_DSP_IRQ0_CLR BIT(0) +#define ICLR_DSP_FRQ0_CLR BIT(1) +#define ICLR_DSP_IRQ1_CLR BIT(2) +#define ICLR_DSP_FIQ1_CLR BIT(3) +#define ICLR_VBCAD_IRQ_CLR BIT(5) +#define ICLR_VBCDA_IRQ_CLR BIT(6) +#define ICLR_RFT_INT_CLR BIT(12) + +#define CP2AP_IRQ0_CLR BIT(0) +#define CP2AP_FRQ0_CLR BIT(1) +#define CP2AP_IRQ1_CLR BIT(2) +#define CP2AP_FRQ1_CLR BIT(3) + +/* the Clock enable register bit */ +#define CLK_PWM0_EN BIT(21) +#define CLK_PWM1_EN BIT(22) +#define CLK_PWM2_EN BIT(23) +#define CLK_PWM3_EN BIT(24) +#define CLK_PWM0_SEL BIT(25) +#define CLK_PWM1_SEL BIT(26) +#define CLK_PWM2_SEL BIT(27) +#define CLK_PWM3_SEL BIT(28) + +/* POWER CTL1 */ +#define POWCTL1_CONFIG 0x0423F91E /* isolation number 1ms:30cycles */ +#define DSP_ROM_SLP_PD_EN BIT(2) +#define MCU_ROM_SLP_PD_EN BIT(0) + +/* bits definition for CLK_EN. */ +#define BUFON_CTRL_LOW BIT(16) +#define BUFON_CTRL_HI BIT(17) +#define MCU_XTLEN_AUTOPD_EN BIT(18) +#define APB_PERI_FRC_CLP BIT(19) + +/* bits definition for GR_STC_STATE. */ + +#define GR_EMC_STOP BIT(0) +#define GR_MCU_STOP BIT(1) +#define GR_DSP_STOP BIT(2) + +/* bits definition for GR_CLK_DLY. */ +#define GR_EMC_STOP_CH5 BIT(4) +#define GR_EMC_STOP_CH4 BIT(5) +#define GR_EMC_STOP_CH3 BIT(6) +#define DSP_DEEP_STOP BIT(9) +#define DSP_SYS_STOP BIT(10) +#define DSP_AHB_STOP BIT(11) +#define DSP_MTX_STOP BIT(12) +#define DSP_CORE_STOP BIT(13) + +/* PIN_CTRL */ +#define PINCTRL_I2C2_SEL BIT(8) + +/* ****************************************************************** */ + +/* AHB register offset */ +#define AHB_CTL0 0x00 +#define AHB_CTL1 0x04 +#define AHB_CTL2 0x08 +#define AHB_CTL3 0x0C +#define AHB_SOFT_RST 0x10 +#define AHB_PAUSE 0x14 +#define AHB_REMAP 0x18 +#define AHB_ARM_CLK 0x24 +#define AHB_SDIO_CTL 0x28 +#define AHB_CTL4 0x2C +#define AHB_ENDIAN_SEL 0x30 +#define AHB_STS 0x34 +#define AHB_CA5_CFG 0x38 +#define AHB_HOLDING_PEN 0x40 +#define AHB_JUMP_ADDR_CPU0 0x44 +#define AHB_JUMP_ADDR_CPU1 0x48 +#define AHB_DSP_BOOT_EN 0x84 +#define AHB_DSP_BOOT_VECTOR 0x88 +#define AHB_DSP_RESET 0x8C +#define AHB_ENDIAN_EN 0x90 +#define USB_PHY_CTRL 0xA0 +#define USB_SPR_REG 0xC0 +#define CHIP_ID 0x1FC + +/* AHB_CTL0 bits */ +#define AHB_CTL0_DCAM_EN BIT(1) +#define AHB_CTL0_CCIR_IN_EN BIT(2) +#define AHB_CTL0_LCDC_EN BIT(3) +#define AHB_CTL0_SDIO_EN BIT(4) +#define AHB_CTL0_SDIO0_EN AHB_CTL0_SDIO_EN +#define AHB_CTL0_USBD_EN BIT(5) +#define AHB_CTL0_DMA_EN BIT(6) +#define AHB_CTL0_BM0_EN BIT(7) +#define AHB_CTL0_NFC_EN BIT(8) +#define AHB_CTL0_CCIR_EN BIT(9) +#define AHB_CTL0_DCAM_MIPI_EN BIT(10) +#define AHB_CTL0_BM1_EN BIT(11) +#define AHB_CTL0_ISP_EN BIT(12) +#define AHB_CTL0_VSP_EN BIT(13) +#define AHB_CTL0_ROT_EN BIT(14) +#define AHB_CTL0_BM2_EN BIT(15) +#define AHB_CTL0_BM3_EN BIT(16) +#define AHB_CTL0_BM4_EN BIT(17) +#define AHB_CTL0_DRM_EN BIT(18) +#define AHB_CTL0_SDIO1_EN BIT(19) +#define AHB_CTL0_G2D_EN BIT(20) +#define AHB_CTL0_G3D_EN BIT(21) +#define AHB_CTL0_DISPC_EN BIT(22) +#define AHB_CTL0_EMMC_EN BIT(23) +#define AHB_CTL0_SDIO2_EN BIT(24) +#define AHB_CTL0_SPINLOCK_EN BIT(25) +#define AHB_CTL0_AHB_ARCH_EB BIT(27) +#define AHB_CTL0_EMC_EN BIT(28) +#define AHB_CTL0_AXIBUSMON0_EN BIT(29) +#define AHB_CTL0_AXIBUSMON1_EN BIT(30) +#define AHB_CTL0_AXIBUSMON2_EN BIT(31) + +/* AHB_CTRL1 bits */ +#define AHB_CTRL1_EMC_AUTO_GATE_EN BIT(8) +#define AHB_CTRL1_EMC_CH_AUTO_GATE_EN BIT(9) +#define AHB_CTRL1_ARM_AUTO_GATE_EN BIT(11) +#define AHB_CTRL1_AHB_AUTO_GATE_EN BIT(12) +#define AHB_CTRL1_MCU_AUTO_GATE_EN BIT(13) +#define AHB_CTRL1_MSTMTX_AUTO_GATE_EN BIT(14) +#define AHB_CTRL1_ARMMTX_AUTO_GATE_EN BIT(15) +#define AHB_CTRL1_ARM_DAHB_SLEEP_EN BIT(16) +#define AHB_CTRL1_DCAM_BUF_SW BIT(0) +#define AHB_SOFT_RST_CCIR_SOFT_RST BIT(2) +#define AHB_SOFT_RST_DCAM_SOFT_RST BIT(1) + +#define AHB_CTL2_DISPMTX_CLK_EN BIT(11) +#define AHB_CTL2_MMMTX_CLK_EN BIT(10) +#define AHB_CTL2_DISPC_CORE_CLK_EN BIT(9) +#define AHB_CTL2_LCDC_CORE_CLK_EN BIT(8) +#define AHB_CTL2_ISP_CORE_CLK_EN BIT(7) +#define AHB_CTL2_VSP_CORE_CLK_EN BIT(6) +#define AHB_CTL2_DCAM_CORE_CLK_EN BIT(5) +/* USB_PHY_CTRL bits */ +#define USB_DM_PULLUP_BIT BIT(19) +#define USB_DP_PULLDOWN_BIT BIT(20) +#define USB_DM_PULLDOWN_BIT BIT(21) + +/* bit definitions for register DSP_BOOT_EN */ +#define DSP_BOOT_ENABLE BIT(0) + +/* bit definitions for register DSP_RST */ +#define DSP_RESET BIT(0) + +/* bit definitions for register AHB_PAUSE */ +#define MCU_CORE_SLEEP BIT(0) +#define MCU_SYS_SLEEP_EN BIT(1) +#define MCU_DEEP_SLEEP_EN BIT(2) +#define APB_SLEEP BIT(3) + + +/* bit definitions for register AHB_STS */ +#define EMC_STOP_CH0 BIT(0) +#define EMC_STOP_CH1 BIT(1) +#define EMC_STOP_CH2 BIT(2) +#define EMC_STOP_CH3 BIT(3) +#define EMC_STOP_CH4 BIT(4) +#define EMC_STOP_CH5 BIT(5) +#define EMC_STOP_CH6 BIT(6) +#define EMC_STOP_CH7 BIT(7) +#define EMC_STOP_CH8 BIT(8) +#define ARMMTX_STOP_CH0 BIT(12) +#define ARMMTX_STOP_CH1 BIT(13) +#define ARMMTX_STOP_CH2 BIT(14) +#define AHB_STS_EMC_STOP BIT(16) +#define AHB_STS_EMC_SLEEP BIT(17) +#define DMA_BUSY BIT(18) +#define DSP_MAHB_SLEEP_EN BIT(19) +#define APB_PRI_EN BIT(20) + +/*********************************************************************/ +#define CHIP_ID_8810S (0x88100001UL) //Smic +/*********************************************************************/ +/* ****************************************************************** */ + +/* global register types */ +enum { + REG_TYPE_GLOBAL = 0, + REG_TYPE_AHB_GLOBAL, + REG_TYPE_MAX +}; + +int32_t sprd_greg_read(uint32_t type, uint32_t reg_offset) __deprecated; +void sprd_greg_write(uint32_t type, uint32_t value, uint32_t reg_offset) __deprecated; +void sprd_greg_set_bits(uint32_t type, uint32_t bits, uint32_t reg_offset) __deprecated; +void sprd_greg_clear_bits(uint32_t type, uint32_t bits, uint32_t reg_offset) __deprecated; + +#endif +#endif + diff --git a/include/soc/sprd/gpio.h b/include/soc/sprd/gpio.h new file mode 100755 index 00000000..6a85491c --- /dev/null +++ b/include/soc/sprd/gpio.h @@ -0,0 +1,109 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARM_ARCH_GPIO_H +#define __ASM_ARM_ARCH_GPIO_H + +/* + * SC8825 GPIO&EIC bank and number summary: + * + * Bank From To NR Type + * 1 0 ~ 15 16 EIC + * 2 16 ~ 271 256 GPIO + * 3 272 ~ 287 16 ANA EIC + * 4 288 ~ 319 32 ANA GPIO + */ + +#ifdef CONFIG_ARCH_SCX35 +#define D_GPIO_START 0 +#define D_GPIO_NR 256 + +#define A_GPIO_START ( D_GPIO_START + D_GPIO_NR ) +#if defined(CONFIG_ARCH_SCX15) +#define A_GPIO_NR 0 +#else +#define A_GPIO_NR 32 +#endif + +#define D_EIC_START ( A_GPIO_START + A_GPIO_NR) +#define D_EIC_NR 16 + +#define A_EIC_START ( D_EIC_START + D_EIC_NR ) +#define A_EIC_NR 16 +#else +#define D_EIC_START 0 +#define D_EIC_NR 16 + +#define D_GPIO_START ( D_EIC_START + D_EIC_NR ) +#define D_GPIO_NR 256 + +#define A_EIC_START ( D_GPIO_START + D_GPIO_NR ) +#define A_EIC_NR 16 + +#define A_GPIO_START ( A_EIC_START + A_EIC_NR ) +#define A_GPIO_NR 32 +#endif + +#define ARCH_NR_GPIOS ( D_EIC_NR + D_GPIO_NR + A_EIC_NR + A_GPIO_NR ) + +#ifdef CONFIG_64BIT +#include <asm-generic/gpio.h> +#include <soc/sprd/irqs.h> +#else +#include <asm-generic/gpio.h> +#include <mach/irqs.h> +#endif + +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value +#define gpio_cansleep __gpio_cansleep +#define gpio_to_irq __gpio_to_irq + + +/* Digital GPIO/EIC base address */ +#define CTL_GPIO_BASE (SPRD_GPIO_BASE) +#define CTL_EIC_BASE (SPRD_EIC_BASE) + +/* Analog GPIO/EIC base address */ + +#if defined(CONFIG_ARCH_SCX35) +#define ANA_CTL_EIC_BASE (ANA_EIC_BASE) +#define ANA_CTL_GPIO_BASE (ANA_GPIO_INT_BASE) +#else +#define ANA_CTL_EIC_BASE (SPRD_MISC_BASE + 0x0100) +#define ANA_CTL_GPIO_BASE (SPRD_MISC_BASE + 0x0480) +#endif + + +enum { + ENUM_ID_D_GPIO = 0, + ENUM_ID_D_EIC, + ENUM_ID_A_GPIO, + ENUM_ID_A_EIC, + + ENUM_ID_END_NR, +}; + +struct eic_gpio_resource { + int irq; + int base_addr; + int chip_base; + int chip_ngpio; +}; + +static inline int irq_to_gpio(int irq) +{ + return irq - GPIO_IRQ_START; +} + +#endif diff --git a/include/soc/sprd/hardware.h b/include/soc/sprd/hardware.h new file mode 100755 index 00000000..d1883262 --- /dev/null +++ b/include/soc/sprd/hardware.h @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARCH_SCI_HARDWARE_H +#define __ASM_ARCH_SCI_HARDWARE_H +/* +#define SCI_IOMAP(x) (SCI_IOMAP_BASE + (x)) + +#ifndef SCI_ADDR +#define SCI_ADDR(_b_, _o_) ( (u32)(_b_) + (_o_) ) +#endif +*/ +#include <asm/sizes.h> + +#if defined(CONFIG_64BIT) +#define SPRD_IRAM2_PHYS 0x50002000 +#define SPRD_IRAM2_SIZE (SZ_16K + SZ_4K + SZ_2K + SZ_1K) +#endif + +#if !defined(CONFIG_64BIT) +#if defined(CONFIG_ARCH_SCX35L) +#include "__hardware-sc9630.h" +#elif defined(CONFIG_ARCH_SCX30G) +#include "__hardware-sc7731.h" +#elif defined(CONFIG_ARCH_SCX35) +#include "__hardware-sc8830.h" +#elif defined(CONFIG_ARCH_SC8825) +#include "__hardware-sc8825.h" +#else +#error "Unknown architecture specification" +#endif +#endif + +#endif diff --git a/include/soc/sprd/i2c-sprd.h b/include/soc/sprd/i2c-sprd.h new file mode 100644 index 00000000..867bc2f0 --- /dev/null +++ b/include/soc/sprd/i2c-sprd.h @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __I2C_SPRD_H +#define __I2C_SPRD_H + +void sprd_i2c_ctl_chg_clk (unsigned int id_nr, unsigned int freq); + + +#endif diff --git a/include/soc/sprd/i2s.h b/include/soc/sprd/i2s.h new file mode 100644 index 00000000..9af57f81 --- /dev/null +++ b/include/soc/sprd/i2s.h @@ -0,0 +1,135 @@ +/* + * sound/soc/sprd/dai/i2s/i2s.h + * + * SPRD SoC CPU-DAI -- SpreadTrum SOC DAI i2s. + * + * Copyright (C) 2012 SpreadTrum Ltd. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __I2S_H +#define __I2S_H + +#include <soc/sprd/sprd-audio.h> +#include <linux/string.h> +#include <linux/io.h> +#include <sound/info.h> +#include <sound/core.h> +#include <sound/soc.h> + + +#define I2S_VERSION "i2s.r0p0" + +#define I2S_MAGIC_ID (0x124) + +/* bus_type */ +#define I2S_BUS 0 +#define PCM_BUS 1 + +/* byte_per_chan */ +#define I2S_BPCH_8 0 +#define I2S_BPCH_16 1 +#define I2S_BPCH_32 2 + +/* mode */ +#define I2S_MASTER 0 +#define I2S_SLAVE 1 + +/* lsb */ +#define I2S_MSB 0 +#define I2S_LSB 1 + +/* rtx_mode */ +#define I2S_RTX_DIS 0 +#define I2S_RX_MODE 1 +#define I2S_TX_MODE 2 +#define I2S_RTX_MODE 3 + +/* sync_mode */ +#define I2S_LRCK 0 +#define I2S_SYNC 1 + +/* lrck_inv */ +#define I2S_L_LEFT 0 +#define I2S_L_RIGTH 1 + +/* clk_inv */ +#define I2S_CLK_N 0 +#define I2S_CLK_R 1 + +/* i2s_bus_mode */ +#define I2S_MSBJUSTFIED 0 +#define I2S_COMPATIBLE 1 + +/* pcm_bus_mode */ +#define I2S_LONG_FRAME 0 +#define I2S_SHORT_FRAME 1 + +struct i2s_config { + u32 hw_port; + u32 fs; + u32 slave_timeout; + u32 bus_type:1; + u32 byte_per_chan:2; + u32 mode:1; + u32 lsb:1; + u32 rtx_mode:2; + u32 sync_mode:1; + u32 lrck_inv:1; + u32 clk_inv:2; + u32 i2s_bus_mode:1; + u32 pcm_bus_mode:1; + u32 pcm_slot:3; + u16 pcm_cycle; + u16 tx_watermark; + u16 rx_watermark; +}; + +/* -------------------------- */ +#define I2S_FIFO_DEPTH 32 + +/**********i2s-debug*********/ +#define SAMPLATE_MIN 8000 +#define SAMPLATE_MAX 96000 + + +#define FUN_REG(f) ((unsigned short)(-((f) + 1))) +enum { + FS = 0, + HW_PROT, + SLAVE_TIMEOUT, + BUS_TYPE, + BYTE_PER_CHAN, + MODE, + LSB, + TRX_MODE, + LRCK_INV, + SYNC_MODE, + CLK_INV, + I2S_BUS_MODE, + PCM_BUS_MODE, + PCM_SLOT, + PCM_CYCLE, + TX_WATERMARK, + RX_WATERMARK, + I2S_CONFIG_MAX +}; +void i2s_debug_write(struct snd_info_entry *entry, + struct snd_info_buffer *buffer); +void i2s_debug_read(struct snd_info_entry *entry, + struct snd_info_buffer *buffer); +void i2s_register_proc_read(struct snd_info_entry *entry, + struct snd_info_buffer *buffer); +int i2s_config_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int i2s_config_set(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); + +#endif /* __I2S_H */ diff --git a/include/soc/sprd/iomap.h b/include/soc/sprd/iomap.h new file mode 100644 index 00000000..7b72a871 --- /dev/null +++ b/include/soc/sprd/iomap.h @@ -0,0 +1,342 @@ +#ifndef __SCI_IOMAP_H__ +#define __SCI_IOMAP_H__ + +#ifndef __ASSEMBLER__ + +struct iomap_sprd { + unsigned long vaddr; + unsigned long paddr; + unsigned long length; +}; + +extern struct iotable_sprd io_addr_sprd; +struct iotable_sprd { + struct iomap_sprd AHB; +#define SPRD_AHB_PHYS io_addr_sprd.AHB.paddr +#define SPRD_AHB_BASE io_addr_sprd.AHB.vaddr +#define SPRD_AHB_SIZE io_addr_sprd.AHB.length + +/* struct iomap_sprd HWLOCK0; +#define SPRD_HWLOCK0_PHYS io_addr_sprd.HWLOCK0.paddr +#define SPRD_HWLOCK0_BASE io_addr_sprd.HWLOCK0.vaddr +#define SPRD_HWLOCK0_SIZE io_addr_sprd.HWLOCK0.length +*/ + struct iomap_sprd PUB; +#define SPRD_PUB_PHYS io_addr_sprd.PUB.paddr +#define SPRD_PUB_BASE io_addr_sprd.PUB.vaddr +#define SPRD_PUB_SIZE io_addr_sprd.PUB.length + + struct iomap_sprd AONAPB; +#define SPRD_AONAPB_PHYS io_addr_sprd.AONAPB.paddr +#define SPRD_AONAPB_BASE io_addr_sprd.AONAPB.vaddr +#define SPRD_AONAPB_SIZE io_addr_sprd.AONAPB.length + + struct iomap_sprd PMU; +#define SPRD_PMU_PHYS io_addr_sprd.PMU.paddr +#define SPRD_PMU_BASE io_addr_sprd.PMU.vaddr +#define SPRD_PMU_SIZE io_addr_sprd.PMU.length + + struct iomap_sprd MMAHB; +#define SPRD_MMAHB_PHYS io_addr_sprd.MMAHB.paddr +#define SPRD_MMAHB_BASE io_addr_sprd.MMAHB.vaddr +#define SPRD_MMAHB_SIZE io_addr_sprd.MMAHB.length + + struct iomap_sprd MMCKG; +#define SPRD_MMCKG_PHYS io_addr_sprd.MMCKG.paddr +#define SPRD_MMCKG_BASE io_addr_sprd.MMCKG.vaddr +#define SPRD_MMCKG_SIZE io_addr_sprd.MMCKG.length + +#if defined(CONFIG_MACH_SP9830I) || defined(CONFIG_ARCH_SCX30G2) || defined(CONFIG_ARCH_SCX35LT8) + struct iomap_sprd CODECAHB; +#define SPRD_CODECAHB_PHYS io_addr_sprd.CODECAHB.paddr +#define SPRD_CODECAHB_BASE io_addr_sprd.CODECAHB.vaddr +#define SPRD_CODECAHB_SIZE io_addr_sprd.CODECAHB.length +#endif + + struct iomap_sprd APBREG; +#define SPRD_APBREG_PHYS io_addr_sprd.APBREG.paddr +#define SPRD_APBREG_BASE io_addr_sprd.APBREG.vaddr +#define SPRD_APBREG_SIZE io_addr_sprd.APBREG.length + + struct iomap_sprd GPUAPB; +#define SPRD_GPUAPB_PHYS io_addr_sprd.GPUAPB.paddr +#define SPRD_GPUAPB_BASE io_addr_sprd.GPUAPB.vaddr +#define SPRD_GPUAPB_SIZE io_addr_sprd.GPUAPB.length + + struct iomap_sprd APBCKG; +#define SPRD_APBCKG_PHYS io_addr_sprd.APBCKG.paddr +#define SPRD_APBCKG_BASE io_addr_sprd.APBCKG.vaddr +#define SPRD_APBCKG_SIZE io_addr_sprd.APBCKG.length + +/* seems not good to keep */ + struct iomap_sprd DMA0; +#define SPRD_DMA0_PHYS io_addr_sprd.DMA0.paddr +#define SPRD_DMA0_BASE io_addr_sprd.DMA0.vaddr +#define SPRD_DMA0_SIZE io_addr_sprd.DMA0.length + + struct iomap_sprd WDG; +#define SPRD_WDG_PHYS (io_addr_sprd.WDG.paddr) +#define SPRD_WDG_BASE (io_addr_sprd.WDG.vaddr) +#define SPRD_WDG_SIZE (io_addr_sprd.WDG.length) + + struct iomap_sprd HWSPINLOCK0; +#define SPRD_HWSPINLOCK0_PHYS io_addr_sprd.HWSPINLOCK0.paddr +#define SPRD_HWSPINLOCK0_BASE io_addr_sprd.HWSPINLOCK0.vaddr +#define SPRD_HWSPINLOCK0_SIZE io_addr_sprd.HWSPINLOCK0.length + + struct iomap_sprd HWSPINLOCK1; +#define SPRD_HWSPINLOCK1_PHYS io_addr_sprd.HWSPINLOCK1.paddr +#define SPRD_HWSPINLOCK1_BASE io_addr_sprd.HWSPINLOCK1.vaddr +#define SPRD_HWSPINLOCK1_SIZE io_addr_sprd.HWSPINLOCK1.length + +/************** 64BIT private map **************/ +#ifdef CONFIG_64BIT + struct iomap_sprd APCKG; +#define SPRD_APCKG_PHYS io_addr_sprd.APCKG.paddr +#define SPRD_APCKG_BASE io_addr_sprd.APCKG.vaddr +#define SPRD_APCKG_SIZE io_addr_sprd.APCKG.length + + struct iomap_sprd AONDMA; +#define SPRD_AONDMA_PHYS io_addr_sprd.AONDMA.paddr +#define SPRD_AONDMA_BASE io_addr_sprd.AONDMA.vaddr +#define SPRD_AONDMA_SIZE io_addr_sprd.AONDMA.length + + struct iomap_sprd PWM; +#define SPRD_PWM_PHYS io_addr_sprd.PWM.paddr +#define SPRD_PWM_BASE io_addr_sprd.PWM.vaddr +#define SPRD_PWM_SIZE io_addr_sprd.PWM.length + + struct iomap_sprd ISP; +#define SPRD_ISP_PHYS io_addr_sprd.ISP.paddr +#define SPRD_ISP_BASE io_addr_sprd.ISP.vaddr +#define SPRD_ISP_SIZE io_addr_sprd.ISP.length + + struct iomap_sprd CSI2; +#define SPRD_CSI2_PHYS io_addr_sprd.CSI2.paddr +#define SPRD_CSI2_BASE io_addr_sprd.CSI2.vaddr +#define SPRD_CSI2_SIZE io_addr_sprd.CSI2.length + + struct iomap_sprd DCAM; +#define SPRD_DCAM_PHYS io_addr_sprd.DCAM.paddr +#define SPRD_DCAM_BASE io_addr_sprd.DCAM.vaddr +#define SPRD_DCAM_SIZE io_addr_sprd.DCAM.length + + struct iomap_sprd PIN; +#define SPRD_PIN_PHYS io_addr_sprd.PIN.paddr +#define SPRD_PIN_BASE io_addr_sprd.PIN.vaddr +#define SPRD_PIN_SIZE io_addr_sprd.PIN.length + + struct iomap_sprd GPIO; +#define SPRD_GPIO_PHYS io_addr_sprd.GPIO.paddr +#define SPRD_GPIO_BASE io_addr_sprd.GPIO.vaddr +#define SPRD_GPIO_SIZE io_addr_sprd.GPIO.length + + struct iomap_sprd INTC2; +#define SPRD_INTC2_PHYS io_addr_sprd.INTC2.paddr +#define SPRD_INTC2_BASE io_addr_sprd.INTC2.vaddr +#define SPRD_INTC2_SIZE io_addr_sprd.INTC2.length + + struct iomap_sprd SYSCNT; +#define SPRD_SYSCNT_PHYS io_addr_sprd.SYSCNT.paddr +#define SPRD_SYSCNT_BASE io_addr_sprd.SYSCNT.vaddr +#define SPRD_SYSCNT_SIZE io_addr_sprd.SYSCNT.length + + struct iomap_sprd AONCKG; +#define SPRD_AONCKG_PHYS io_addr_sprd.AONCKG.paddr +#define SPRD_AONCKG_BASE io_addr_sprd.AONCKG.vaddr +#define SPRD_AONCKG_SIZE io_addr_sprd.AONCKG.length + + struct iomap_sprd CORE; +#define SPRD_CORE_PHYS io_addr_sprd.CORE.paddr +#define SPRD_CORE_BASE io_addr_sprd.CORE.vaddr +#define SPRD_CORE_SIZE io_addr_sprd.CORE.length + + struct iomap_sprd GPUCKG; +#define SPRD_GPUCKG_PHYS io_addr_sprd.GPUCKG.paddr +#define SPRD_GPUCKG_BASE io_addr_sprd.GPUCKG.vaddr +#define SPRD_GPUCKG_SIZE io_addr_sprd.GPUCKG.length + + struct iomap_sprd INT; +#define SPRD_INT_PHYS io_addr_sprd.INT.paddr +#define SPRD_INT_BASE io_addr_sprd.INT.vaddr +#define SPRD_INT_SIZE io_addr_sprd.INT.length + + struct iomap_sprd INTC0; +#define SPRD_INTC0_PHYS io_addr_sprd.INTC0.paddr +#define SPRD_INTC0_BASE io_addr_sprd.INTC0.vaddr +#define SPRD_INTC0_SIZE io_addr_sprd.INTC0.length + + struct iomap_sprd INTC1; +#define SPRD_INTC1_PHYS io_addr_sprd.INTC1.paddr +#define SPRD_INTC1_BASE io_addr_sprd.INTC1.vaddr +#define SPRD_INTC1_SIZE io_addr_sprd.INTC1.length + + struct iomap_sprd INTC3; +#define SPRD_INTC3_PHYS io_addr_sprd.INTC3.paddr +#define SPRD_INTC3_BASE io_addr_sprd.INTC3.vaddr +#define SPRD_INTC3_SIZE io_addr_sprd.INTC3.length + + struct iomap_sprd UIDEFUSE; +#define SPRD_UIDEFUSE_PHYS io_addr_sprd.UIDEFUSE.paddr +#define SPRD_UIDEFUSE_BASE io_addr_sprd.UIDEFUSE.vaddr +#define SPRD_UIDEFUSE_SIZE io_addr_sprd.UIDEFUSE.length + + struct iomap_sprd CA7WDG; +#define SPRD_CA7WDG_PHYS io_addr_sprd.CA7WDG.paddr +#define SPRD_CA7WDG_BASE io_addr_sprd.CA7WDG.vaddr +#define SPRD_CA7WDG_SIZE io_addr_sprd.CA7WDG.length + + struct iomap_sprd EIC; +#define SPRD_EIC_PHYS io_addr_sprd.EIC.paddr +#define SPRD_EIC_BASE io_addr_sprd.EIC.vaddr +#define SPRD_EIC_SIZE io_addr_sprd.EIC.length + + struct iomap_sprd IPI; +#define SPRD_IPI_PHYS io_addr_sprd.IPI.paddr +#define SPRD_IPI_BASE io_addr_sprd.IPI.vaddr +#define SPRD_IPI_SIZE io_addr_sprd.IPI.length + + struct iomap_sprd LPDDR2; +#define SPRD_LPDDR2_PHYS io_addr_sprd.LPDDR2.paddr +#define SPRD_LPDDR2_BASE io_addr_sprd.LPDDR2.vaddr +#define SPRD_LPDDR2_SIZE io_addr_sprd.LPDDR2.length + + struct iomap_sprd UART0; +#define SPRD_UART0_PHYS io_addr_sprd.UART0.paddr +#define SPRD_UART0_BASE io_addr_sprd.UART0.vaddr +#define SPRD_UART0_SIZE io_addr_sprd.UART0.length + + struct iomap_sprd UART1; +#define SPRD_UART1_PHYS io_addr_sprd.UART1.paddr +#define SPRD_UART1_BASE io_addr_sprd.UART1.vaddr +#define SPRD_UART1_SIZE io_addr_sprd.UART1.length + + struct iomap_sprd UART2; +#define SPRD_UART2_PHYS io_addr_sprd.UART2.paddr +#define SPRD_UART2_BASE io_addr_sprd.UART2.vaddr +#define SPRD_UART2_SIZE io_addr_sprd.UART2.length + + struct iomap_sprd UART3; +#define SPRD_UART3_PHYS io_addr_sprd.UART3.paddr +#define SPRD_UART3_BASE io_addr_sprd.UART3.vaddr +#define SPRD_UART3_SIZE io_addr_sprd.UART3.length + + struct iomap_sprd UART4; +#define SPRD_UART4_PHYS io_addr_sprd.UART4.paddr +#define SPRD_UART4_BASE io_addr_sprd.UART4.vaddr +#define SPRD_UART4_SIZE io_addr_sprd.UART4.length + + /* indicate base address of maps */ + unsigned long base; + +/************** 32BIT private map **************/ +#else /* 32BIT */ + struct iomap_sprd AONCKG; +#define SPRD_AONCKG_PHYS io_addr_sprd.AONCKG.paddr +#define SPRD_AONCKG_BASE io_addr_sprd.AONCKG.vaddr +#define SPRD_AONCKG_SIZE io_addr_sprd.AONCKG.length + + struct iomap_sprd CORE; +#define SPRD_CORE_PHYS io_addr_sprd.CORE.paddr +#define SPRD_CORE_BASE io_addr_sprd.CORE.vaddr +#define SPRD_CORE_SIZE io_addr_sprd.CORE.length + + struct iomap_sprd GPUCKG; +#define SPRD_GPUCKG_PHYS io_addr_sprd.GPUCKG.paddr +#define SPRD_GPUCKG_BASE io_addr_sprd.GPUCKG.vaddr +#define SPRD_GPUCKG_SIZE io_addr_sprd.GPUCKG.length + + struct iomap_sprd INT; +#define SPRD_INT_PHYS io_addr_sprd.INT.paddr +#define SPRD_INT_BASE io_addr_sprd.INT.vaddr +#define SPRD_INT_SIZE io_addr_sprd.INT.length + + struct iomap_sprd INTC0; +#define SPRD_INTC0_PHYS io_addr_sprd.INTC0.paddr +#define SPRD_INTC0_BASE io_addr_sprd.INTC0.vaddr +#define SPRD_INTC0_SIZE io_addr_sprd.INTC0.length + + struct iomap_sprd INTC1; +#define SPRD_INTC1_PHYS io_addr_sprd.INTC1.paddr +#define SPRD_INTC1_BASE io_addr_sprd.INTC1.vaddr +#define SPRD_INTC1_SIZE io_addr_sprd.INTC1.length + + struct iomap_sprd INTC2; +#define SPRD_INTC2_PHYS io_addr_sprd.INTC2.paddr +#define SPRD_INTC2_BASE io_addr_sprd.INTC2.vaddr +#define SPRD_INTC2_SIZE io_addr_sprd.INTC2.length + + struct iomap_sprd INTC3; +#define SPRD_INTC3_PHYS io_addr_sprd.INTC3.paddr +#define SPRD_INTC3_BASE io_addr_sprd.INTC3.vaddr +#define SPRD_INTC3_SIZE io_addr_sprd.INTC3.length + + struct iomap_sprd UIDEFUSE; +#define SPRD_UIDEFUSE_PHYS io_addr_sprd.UIDEFUSE.paddr +#define SPRD_UIDEFUSE_BASE io_addr_sprd.UIDEFUSE.vaddr +#define SPRD_UIDEFUSE_SIZE io_addr_sprd.UIDEFUSE.length + + struct iomap_sprd ISP; +#define SPRD_ISP_PHYS io_addr_sprd.ISP.paddr +#define SPRD_ISP_BASE io_addr_sprd.ISP.vaddr +#define SPRD_ISP_SIZE io_addr_sprd.ISP.length + + struct iomap_sprd CA7WDG; +#define SPRD_CA7WDG_PHYS (io_addr_sprd.CA7WDG.paddr) +#define SPRD_CA7WDG_BASE (io_addr_sprd.CA7WDG.vaddr) +#define SPRD_CA7WDG_SIZE (io_addr_sprd.CA7WDG.length) + + struct iomap_sprd CSI2; +#define SPRD_CSI2_PHYS io_addr_sprd.CSI2.paddr +#define SPRD_CSI2_BASE io_addr_sprd.CSI2.vaddr +#define SPRD_CSI2_SIZE io_addr_sprd.CSI2.length + + struct iomap_sprd EIC; +#define SPRD_EIC_PHYS io_addr_sprd.EIC.paddr +#define SPRD_EIC_BASE io_addr_sprd.EIC.vaddr +#define SPRD_EIC_SIZE io_addr_sprd.EIC.length + + struct iomap_sprd IPI; +#define SPRD_IPI_PHYS io_addr_sprd.IPI.paddr +#define SPRD_IPI_BASE io_addr_sprd.IPI.vaddr +#define SPRD_IPI_SIZE io_addr_sprd.IPI.length + + struct iomap_sprd DCAM; +#define SPRD_DCAM_PHYS io_addr_sprd.DCAM.paddr +#define SPRD_DCAM_BASE io_addr_sprd.DCAM.vaddr +#define SPRD_DCAM_SIZE io_addr_sprd.DCAM.length + +/* struct iomap_sprd VSP; +#define SPRD_VSP_PHYS io_addr_sprd.VSP.paddr +#define SPRD_VSP_BASE io_addr_sprd.VSP.vaddr +#define SPRD_VSP_SIZE io_addr_sprd.VSP.length +*/ + struct iomap_sprd SYSCNT; +#define SPRD_SYSCNT_PHYS io_addr_sprd.SYSCNT.paddr +#define SPRD_SYSCNT_BASE io_addr_sprd.SYSCNT.vaddr +#define SPRD_SYSCNT_SIZE io_addr_sprd.SYSCNT.length + + struct iomap_sprd PIN; +#define SPRD_PIN_PHYS io_addr_sprd.PIN.paddr +#define SPRD_PIN_BASE io_addr_sprd.PIN.vaddr +#define SPRD_PIN_SIZE io_addr_sprd.PIN.length + + struct iomap_sprd GPIO; +#define SPRD_GPIO_PHYS io_addr_sprd.GPIO.paddr +#define SPRD_GPIO_BASE io_addr_sprd.GPIO.vaddr +#define SPRD_GPIO_SIZE io_addr_sprd.GPIO.length + +#endif +}; + +#else /* __ASSEMBLER__ */ + +#if !defined(CONFIG_64BIT) +#define SPRD_UART1_PHYS 0x70100000 +#endif + +#endif /* __ASSEMBLER__ */ +#if defined(CONFIG_ARCH_SCX30G2) || defined(CONFIG_MACH_SP9830I) || defined(CONFIG_ARCH_SCX35LT8) +#define REGS_CODEC_AHB_BASE SPRD_CODECAHB_BASE +#endif +#endif /* __SCI_IOMAP_H__ */ diff --git a/include/soc/sprd/irqs.h b/include/soc/sprd/irqs.h new file mode 100755 index 00000000..54ce8732 --- /dev/null +++ b/include/soc/sprd/irqs.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARCH_SCI_IRQS_H +#define __ASM_ARCH_SCI_IRQS_H + +#if defined(CONFIG_ARCH_SCX35) +#include "__irqs-sc8830.h" +#elif defined(CONFIG_ARCH_SC8825) +#include "__irqs-sc8825.h" +#else +#error "Unknown architecture specification" +#endif + +#ifndef __ASSEMBLY__ + +// /*raw interrupt intc interrupt enable */ +// void sci_intc_unmask(u32 irq); +// /*raw interrupt intc interrupt disable */ +// void sci_intc_mask(u32 irq); + +#endif + +#endif diff --git a/include/soc/sprd/kpd.h b/include/soc/sprd/kpd.h new file mode 100644 index 00000000..3ebe4940 --- /dev/null +++ b/include/soc/sprd/kpd.h @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * contact <steve.zhan@spreadtrum.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ARCH_KPD_H +#define __ARCH_KPD_H + +/** + For example, if you using chip row0 and (col0,col1) to define some keys + pls set : + rows_choose_hw = row0 + cols_choose_hw = col0 | col1 +*/ +struct sci_keypad_platform_data { + int rows_choose_hw; /* choose chip keypad controler rows */ + int cols_choose_hw; /* choose chip keypad controler cols */ + int rows_number; /*How many rows are there in board. */ + int cols_number; /*How many cols are there in board. */ + const struct matrix_keymap_data *keymap_data; + int support_long_key; + unsigned short repeat; + unsigned int debounce_time; /* in ns */ + int wakeup; +}; + +/* chip define begin */ +#define SCI_COL7 (0x01 << 15) +#define SCI_COL6 (0x01 << 14) +#define SCI_COL5 (0x01 << 13) +#define SCI_COL4 (0x01 << 12) +#define SCI_COL3 (0x01 << 11) +#define SCI_COL2 (0x01 << 10) +#define SCI_COL1 (0x01 << 9) +#define SCI_COL0 (0x01 << 8) + +#define SCI_ROW7 (0x01 << 23) +#define SCI_ROW6 (0x01 << 22) +#define SCI_ROW5 (0x01 << 21) +#define SCI_ROW4 (0x01 << 20) +#define SCI_ROW3 (0x01 << 19) +#define SCI_ROW2 (0x01 << 18) +#define SCI_ROW1 (0x01 << 17) +#define SCI_ROW0 (0x01 << 16) + +/*using example */ +/* +#define CUSTOM_KEYPAD_ROWS (SCI_ROW0 | SCI_ROW1) +#define CUSTOM_KEYPAD_COLS (SCI_COL0 | SCI_COL1) +#define ROWS (2) +#define COLS (2) + +static const unsigned int board_keymap[] = { + KEY(0, 0, KEY_VOLUMEDOWN), + KEY(1, 0, KEY_VOLUMEUP), + KEY(0, 1, KEY_HOME), +}; + +static const struct matrix_keymap_data customize_keymap = { + .keymap = board_keymap, + .keymap_size = ARRAY_SIZE(board_keymap), +}; + +static struct sci_keypad_platform_data sci_keypad_data = { + .rows_choose_hw = CUSTOM_KEYPAD_ROWS, + .cols_choose_hw = CUSTOM_KEYPAD_COLS, + .rows_number = ROWS, + .cols_number = COLS, + .keymap_data = &customize_keymap, + .support_long_key = 1, + .repeat = 0, + .debounce_time = 5000, +}; +platform_device_add_data(&sprd_keypad_device,(const void*)&sci_keypad_data,sizeof(sci_keypad_data)); +platform_add_devices(sprd_keypad_device, sizeof(sprd_keypad_device)); +*/ + + +#endif diff --git a/include/soc/sprd/mailbox.h b/include/soc/sprd/mailbox.h new file mode 100644 index 00000000..075449c1 --- /dev/null +++ b/include/soc/sprd/mailbox.h @@ -0,0 +1,30 @@ +/* mailbox.h */ + +#ifndef MAILBOX_H +#define MAILBOX_H + +#include <linux/spinlock.h> +#include <linux/workqueue.h> +#include <linux/interrupt.h> +#include <linux/device.h> +#include <linux/kfifo.h> +enum { + AP_CA7 = 0x0, + ARM7, + CP0_DSP0, + CP0_DSP1, + CP0_ARM0, + CP0_ARM1, + CP1_DSP, + CP1_CA5, + MBOX_NR, +}; + +#define MBOX_CORE_GGE CP0_ARM0 +#define MBOX_CORE_LTE CP1_CA5 + +int mbox_register_irq_handle(u8 target_id, irq_handler_t irq_handler, void *priv_data); +int mbox_unregister_irq_handle(u8 target_id); +int mbox_raw_sent(u8 target_id, u64 msg); + +#endif /* MAILBOX_H */ diff --git a/include/soc/sprd/memory.h b/include/soc/sprd/memory.h new file mode 100644 index 00000000..794a7efd --- /dev/null +++ b/include/soc/sprd/memory.h @@ -0,0 +1,27 @@ +/* arch/arm/mach-sc8810/include/mach/io.h + * + * Copyright (C) 2012 Spreadtrum + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H __FILE__ + +#define __pfn_to_bus(x) __pfn_to_phys(x) +#define __bus_to_pfn(x) __phys_to_pfn(x) + +/* Maximum of 256MiB in one bank */ +#define MAX_PHYSMEM_BITS 32 +#define SECTION_SIZE_BITS 28 + +#endif + diff --git a/include/soc/sprd/modem_interface.h b/include/soc/sprd/modem_interface.h new file mode 100644 index 00000000..26876fd5 --- /dev/null +++ b/include/soc/sprd/modem_interface.h @@ -0,0 +1,74 @@ +/* + * linux/arch/arm/mach-sprd/modem_interface.h + * + * Generic modem interface structure defination. + * + * Author: Jiayong.Yang(Jiayong.Yang@spreadtrum.com) + * Created: Jul 27, 2012 + * Copyright: Spreadtrum Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef _MODEM_INTF_H +#define _MODEM_INTF_H + +enum MODEM_Mode_type { + MODEM_MODE_SHUTDOWN, + MODEM_MODE_BOOT, + MODEM_MODE_BOOTCOMP, + MODEM_MODE_NORMAL, + MODEM_MODE_DUMP, + MODEM_MODE_RESET, + MODEM_MODE_UNKNOWN +}; + +enum MODEM_device_type { + MODEM_DEV_UART, + MODEM_DEV_SPI, + MODEM_DEV_SDIO, + MODEM_DEV_VPIP +}; + +enum { + MODEM_STATUS_REBOOT, + MODEM_STATUS_ALVIE, + MODEM_STATUS_ASSERT, + MODEM_STATUS_POWERON +}; + +enum { + MODEMSTS_LEVEL_MUX = 50, + MODEMSTS_LEVEL_SDIO = 100, + MODEMSTS_LEVEL_SPI = 150, +}; + +struct modemsts_chg { + struct list_head link; + int level; + void *data; + void (*modemsts_notifier)(struct modemsts_chg *h, unsigned int state); +}; + +struct modem_intf_platform_data{ + enum MODEM_device_type dev_type; + void *modem_dev_parameter; + int modem_power_gpio; + int modem_boot_gpio; + int modem_watchdog_gpio; + int modem_alive_gpio; + int modem_crash_gpio; + int modem_reset_gpio; +}; +extern int modem_intf_open(enum MODEM_Mode_type mode,int index); +extern int modem_intf_read(char *buffer, int size,int index); +extern int modem_intf_write(char *buffer, int size,int index); +extern void modem_intf_set_mode(enum MODEM_Mode_type mode,int index); + +extern int modemsts_notifier_register(struct modemsts_chg *handler); + +extern int modemsts_notifier_unregister(struct modemsts_chg *handler); + +extern void modemsts_change_notification(unsigned int state); +#endif diff --git a/include/soc/sprd/pin_switch.h b/include/soc/sprd/pin_switch.h new file mode 100755 index 00000000..06394612 --- /dev/null +++ b/include/soc/sprd/pin_switch.h @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARM_ARCH_PIN_SWITCH_H +#define __ASM_ARM_ARCH_PIN_SWITCH_H + +struct sprd_pin_switch_platform_data { + const char * power_domain; + u32 reg; + u32 bit_offset; + u32 bit_width; +}; + +enum power_domain_id { + VDD28, + VDD28_1, + VDDSIM0, + VDDSIM1, + VDDSIM2, + VDDSD, + VDD18, + //PD_CNT, +}; + +#ifdef CONFIG_ARCH_SCX20 +#define PD_CNT 5 +#else +#define PD_CNT 7 +#endif + +#define VOL_THRESHOLD 1800000 + +#endif + diff --git a/include/soc/sprd/pinmap.h b/include/soc/sprd/pinmap.h new file mode 100755 index 00000000..6e6dddb8 --- /dev/null +++ b/include/soc/sprd/pinmap.h @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARM_ARCH_PINMAP_H +#define __ASM_ARM_ARCH_PINMAP_H + +#include "hardware.h" + +#define BIT_NONE 0x00 +#define BIT_0 0x01 +#define BIT_1 0x02 +#define BIT_2 0x04 +#define BIT_3 0x08 +#define BIT_4 0x10 +#define BIT_5 0x20 +#define BIT_6 0x40 +#define BIT_7 0x80 +#define BIT_8 0x0100 +#define BIT_9 0x0200 +#define BIT_10 0x0400 +#define BIT_11 0x0800 +#define BIT_12 0x1000 +#define BIT_13 0x2000 +#define BIT_14 0x4000 +#define BIT_15 0x8000 +#define BIT_16 0x010000 +#define BIT_17 0x020000 +#define BIT_18 0x040000 +#define BIT_19 0x080000 +#define BIT_20 0x100000 +#define BIT_21 0x200000 +#define BIT_22 0x400000 +#define BIT_23 0x800000 +#define BIT_24 0x01000000 +#define BIT_25 0x02000000 +#define BIT_26 0x04000000 +#define BIT_27 0x08000000 +#define BIT_28 0x10000000 +#define BIT_29 0x20000000 +#define BIT_30 0x40000000 +#define BIT_31 0x80000000 + +#if defined(CONFIG_ARCH_SCX15) +#include "chip_x15/__regs_pinmap.h" +#elif defined(CONFIG_ARCH_SCX30G) +#include "chip_x30g/__regs_pinmap.h" +#elif defined(CONFIG_ARCH_SCX35L) +#include "chip_x35l/__regs_pinmap.h" +#elif defined(CONFIG_ARCH_SCX35) +#include "chip_x35/__regs_pinmap.h" +#else +#error "Unknown architecture specification" +#endif /* end of CONFIG_ARCH_SCX15 */ + +u32 pinmap_get(u32 offset); +int pinmap_set(u32 offset, u32 value); + +#endif /* end of __ASM_ARM_ARCH_PINMAP_H */ diff --git a/include/soc/sprd/pm_debug.h b/include/soc/sprd/pm_debug.h new file mode 100644 index 00000000..c91bb335 --- /dev/null +++ b/include/soc/sprd/pm_debug.h @@ -0,0 +1,59 @@ +#ifndef _MACH_PM_DEBUG_H +#define _MACH_PM_DEBUG_H + +#include<soc/sprd/hardware.h> +#include<linux/io.h> + +/*print message every 30 second*/ +#define PM_PRINT_ENABLE + +/* use this method we can get time everytime */ +#if !(defined(CONFIG_ARCH_SCX35L64)||defined(CONFIG_ARCH_SCX35LT8)) +#define TIMER_REG(off) (SPRD_TIMER_BASE + (off)) +#define SYSCNT_REG(off) (SPRD_SYSCNT_BASE + (off)) +#define SYSCNT_COUNT SYSCNT_REG(0x0004) +static u32 inline get_sys_cnt(void) +{ + u32 val1, val2; + val1 = __raw_readl(SYSCNT_COUNT); + val2 = __raw_readl(SYSCNT_COUNT); + while(val2 != val1) { + val1 = val2; + val2 = __raw_readl(SYSCNT_COUNT); + } + return val2; +} +#endif + +/*just for pm_sc8810.c & pm_vlx.c*/ + +/*sleep mode info*/ +#define SLP_MODE_ARM 0 +#define SLP_MODE_MCU 1 +#define SLP_MODE_DEP 2 +#define SLP_MODE_LIT 3 +#define SLP_MODE_NON 4 + +extern void pm_debug_init(void); +extern void print_statisic(void); +extern void wakeup_irq_set(void); +extern void print_irq_loop(void); +extern void hard_irq_set(void); +extern void print_int_status(void); +extern void clr_sleep_mode(void); +extern void set_sleep_mode(int sm); +extern void time_statisic_begin(void); +extern void time_statisic_end(void); +extern void print_time(void); +extern void irq_wakeup_set(void); +extern void time_add(unsigned int time, int ret); +extern void print_hard_irq_inloop(int ret); +extern void pm_debug_save_ahb_glb_regs(void); +extern void pm_debug_set_wakeup_timer(void); +extern int is_print_linux_clock; +extern int is_print_modem_clock; + +/* *just for ddi.c */ +extern void inc_irq(int irq); + +#endif diff --git a/include/soc/sprd/regulator.h b/include/soc/sprd/regulator.h new file mode 100644 index 00000000..e69de29b --- /dev/null +++ b/include/soc/sprd/regulator.h diff --git a/include/soc/sprd/sc8830_emc_freq_data.h b/include/soc/sprd/sc8830_emc_freq_data.h new file mode 100644 index 00000000..382064c2 --- /dev/null +++ b/include/soc/sprd/sc8830_emc_freq_data.h @@ -0,0 +1,1119 @@ +#ifndef __EMC_CHANGE_FREQ_DADTA_H +#define __EMC_CHANGE_FREQ_DADTA_H +u32 cp0_dfs_code_data[] = +{ +0xE59FF048, +0xE3A0F004, +0xE3A0F008, +0xE3A0F00C, +0xE3A0F010, +0xE3A0F014, +0xE3A0F018, +0xE3A0F01C, +0xE321F093, +0xE3A03EF0, +0xE1A0D003, +0xEA000118, +0xE3A00000, +0xEE070F90, +0xE1A00000, +0xE1A00000, +0xE1A00000, +0xE1A00000, +0xE1A00000, +0xE12FFF1E, +0x00000020, +0x68104AE2, +0x04492101, +0x60104308, +0x4ADF4770, +0x21016810, +0x43880449, +0x47706010, +0xB53048DC, +0x4ADC6800, +0x62516841, +0x33204BDA, +0x22026819, +0x60194051, +0x6A0249D7, +0x600A31C0, +0x604A6A42, +0x608A6A82, +0x610A6B02, +0x618A6B82, +0x31801C01, +0x4AD1680B, +0x4BD06153, +0x3340684C, +0x4CCE615C, +0x3480688D, +0x68CD6165, +0x31C049CB, +0x6F05614D, +0x6F426015, +0x6F82601A, +0x6FC06022, +0xBD306008, +0x1C14B5F8, +0x20084684, +0x05451C19, +0x68686328, +0x0F400740, +0xD1FA2801, +0x4AC148C0, +0x4BC16190, +0x2001681A, +0x601A4302, +0x33304BBD, +0x4382681A, +0x2600601A, +0x1C324BBB, +0xE0033B04, +0x2F01685F, +0x3201D100, +0xD3F92A05, +0x33204BB2, +0x2001681A, +0x60184310, +0x30011C30, +0xD3FC2802, +0xF0004660, +0x1C30F934, +0x28023001, +0x49AFD3FC, +0x27406808, +0x600843B8, +0x30011C30, +0xD3FC2802, +0xD1212C00, +0xFF7EF7FF, +0x680849A8, +0x60084338, +0x2E023601, +0x4A9ED3FC, +0x21116810, +0x60104308, +0x68C81F11, +0xD5FC07C0, +0x07C068C8, +0x489ED5FC, +0x680138A0, +0x04090C09, +0x489B6001, +0x68013898, +0x04090C09, +0xE0586001, +0xD0012C01, +0xD1542C02, +0x32104A8F, +0x07116810, +0x60104388, +0x320C4A8F, +0x43886810, +0x4A8D6010, +0x6810324C, +0x60104388, +0x328C4A8A, +0x43886810, +0x4A886010, +0x681032CC, +0x60104388, +0x30011C30, +0xD3FC2802, +0xFF41F7FF, +0x68084986, +0x60084338, +0x30011C30, +0xD3FC2802, +0x3010487B, +0x07006801, +0x43014A79, +0x60113210, +0x310C497A, +0x4A796809, +0x320C4301, +0x4A776011, +0x6811324C, +0x60114301, +0x328C4A74, +0x43016811, +0x4A726011, +0x681132CC, +0x60104308, +0x2E0A3601, +0x4A71D3FC, +0x68103AA0, +0x43080C11, +0x4A6E6010, +0x68103A98, +0x43082120, +0x48676010, +0x68013020, +0x00490849, +0xF7FF6001, +0x4B66FF0B, +0x68183330, +0x43082101, +0x48646018, +0x08496801, +0x60010049, +0xD1042C00, +0x4A5F4862, +0x20096190, +0x200AE000, +0xBDF86328, +0x4A5FE726, +0x210D6810, +0x60104308, +0x38A4485A, +0x21016800, +0x43080609, +0x39A44957, +0x1D0A6008, +0x20016811, +0x43010640, +0x32046011, +0x43086811, +0x47706010, +0x4A52B5F8, +0x68103208, +0x01492181, +0x60104308, +0x1C202400, +0x28143001, +0x484CD3FC, +0x68003008, +0x494A2501, +0x31084328, +0x02A86008, +0x60880501, +0x213F4847, +0x63880189, +0xFFC9F7FF, +0xF894F000, +0x68004844, +0x43082106, +0x60084942, +0x3824483F, +0x43296801, +0x4B406001, +0x210F681A, +0x601A430A, +0x681A3304, +0x60194311, +0x68193304, +0x4311221F, +0x68016019, +0x600143A9, +0x68084934, +0x43282510, +0x48346008, +0x38442400, +0x49306084, +0x39442000, +0x492E6088, +0x39042016, +0xF7FF6008, +0x482CEE6E, +0x3001243F, +0x63A001A4, +0x2101482C, +0x6BE36041, +0x0F010518, +0x079A0218, +0x4F1B071B, +0x0F920F9B, +0x37280D00, +0x43AE683E, +0x260F603E, +0x02364F17, +0xF7FF603E, +0x4922FEA3, +0x43286808, +0x481C6008, +0x63A03024, +0xB530E7CD, +0x22021C04, +0x2CC001D0, +0xD0074D1C, +0x338123FF, +0xD10A429C, +0x43C06A69, +0xE0014008, +0x43086A69, +0x08806268, +0x43100080, +0x6A6AE007, +0x401043C0, +0x43080209, +0x21036268, +0x62684308, +0x0000BD30, +0x01010004, +0x000004A0, +0x01000040, +0x010101C0, +0x0700F000, +0x01000180, +0x01000304, +0x022B00C8, +0x0700F100, +0x20100044, +0x11223344, +0x40010044, +0x1010002C, +0x4000F000, +0x00000FFC, +0x022D0000, +0xB5104819, +0x22106801, +0x60014391, +0x310C4916, +0x2304680A, +0x600A431A, +0x68224C14, +0x021B2307, +0x6022431A, +0x341C4C11, +0x23016822, +0x431A035B, +0x4C0F6022, +0x22018823, +0x431303D2, +0x3C028023, +0x431A8823, +0x4C0A8022, +0x88223494, +0x031B2301, +0x8022431A, +0x23106802, +0x6002431A, +0x22046808, +0x60084390, +0x0000BD10, +0x20100044, +0x50130014, +0x50640256, +0xE59FC000, +0xE12FFF1C, +0x000002B9, + +}; +u32 cp1_dfs_code_data[] = +{ +#ifdef CONFIG_SCX35_DMC_FREQ_DDR3 +0xE59FF048, +0xE3A0F004, +0xE3A0F008, +0xE3A0F00C, +0xE3A0F010, +0xE3A0F014, +0xE3A0F018, +0xE3A0F01C, +0xE321F093, +0xE3A03EF0, +0xE1A0D003, +0xEA000108, +0xE3A00000, +0xEE070F90, +0xE1A00000, +0xE1A00000, +0xE1A00000, +0xE1A00000, +0xE1A00000, +0xE12FFF1E, +0x00000020, +0x68104AE8, +0x04492101, +0x60104308, +0x4AE54770, +0x21016810, +0x43880449, +0x47706010, +0xB53048E2, +0x4AE26800, +0x62516841, +0x33204BE0, +0x22026819, +0x60194051, +0x6A0249DD, +0x600A31C0, +0x604A6A42, +0x608A6A82, +0x610A6B02, +0x618A6B82, +0x31801C01, +0x4AD7680B, +0x4BD66153, +0x3340684C, +0x4CD4615C, +0x3480688D, +0x68CD6165, +0x31C049D1, +0x6F05614D, +0x6F426015, +0x6F82601A, +0x6FC06022, +0xBD306008, +0x1C14B5F8, +0x25011C19, +0x062D2600, +0x4684632E, +0x07406868, +0x28010F40, +0x48C6D1FA, +0x61904AC6, +0x681A4BC6, +0x43022001, +0x4BC3601A, +0x681A3330, +0x601A4382, +0x1C324BC1, +0xE0033B04, +0x2F01685F, +0x3201D100, +0xD3F92A05, +0x33204BB8, +0x2001681A, +0x60184310, +0x30011C30, +0xD3FC2802, +0xF0004660, +0x1C30F94A, +0x28023001, +0x49B5D3FC, +0x27406808, +0x600843B8, +0x30011C30, +0xD3FC2802, +0xD1212C00, +0xFF7EF7FF, +0x680849AE, +0x60084338, +0x2E023601, +0x4AA4D3FC, +0x21116810, +0x60104308, +0x68C81F11, +0xD5FC07C0, +0x07C068C8, +0x48A4D5FC, +0x680138A0, +0x04090C09, +0x48A16001, +0x68013898, +0x04090C09, +0xE0586001, +0xD0012C01, +0xD1542C02, +0x32104A95, +0x07116810, +0x60104388, +0x320C4A95, +0x43886810, +0x4A936010, +0x6810324C, +0x60104388, +0x328C4A90, +0x43886810, +0x4A8E6010, +0x681032CC, +0x60104388, +0x30011C30, +0xD3FC2802, +0xFF41F7FF, +0x6808498C, +0x60084338, +0x30011C30, +0xD3FC2802, +0x30104881, +0x07006801, +0x43014A7F, +0x60113210, +0x310C4980, +0x4A7F6809, +0x320C4301, +0x4A7D6011, +0x6811324C, +0x60114301, +0x328C4A7A, +0x43016811, +0x4A786011, +0x681132CC, +0x60104308, +0x2E0A3601, +0x4A77D3FC, +0x68103AA0, +0x43080C11, +0x4A746010, +0x68103A98, +0x43082120, +0x486D6010, +0x68013020, +0x00490849, +0xF7FF6001, +0x4B6CFF0B, +0x68183330, +0x43082101, +0x486A6018, +0x438A6802, +0x2C006002, +0x4869D104, +0x61904A65, +0xBDF86329, +0x63282002, +0xE727E7FB, +0x68014865, +0x03122201, +0x60014311, +0x221D6801, +0x60014311, +0xB5F04770, +0x6808495F, +0x43902210, +0x4A5D6008, +0x6810320C, +0x43182304, +0x485B6010, +0x24076803, +0x43230224, +0x4D586003, +0x682B351C, +0x03642405, +0x602B4323, +0x25016803, +0x432B06ED, +0x4C536003, +0x09AE6823, +0x60234333, +0x883C4F51, +0x431C0B2B, +0x4F4E803C, +0x683C3F04, +0x603C4334, +0x3E024E4C, +0x431C8834, +0x4E498034, +0x68343E74, +0x60334323, +0x36944E47, +0x0BEC8833, +0x80334323, +0x43AB6803, +0x68086003, +0x43182310, +0x68106008, +0x43882104, +0xBDF06010, +0x4A3BB5F8, +0x68103208, +0x01492181, +0x60104308, +0x1C202400, +0x28143001, +0x6810D3FC, +0x43082103, +0x20016010, +0x05010280, +0x48356088, +0x01AD253F, +0xF7FF63A8, +0xF7FFFF91, +0x4832FF9A, +0x60842400, +0x2000492B, +0x60883944, +0x20164929, +0x60083904, +0xEE58F7FF, +0x243F482A, +0x01A43001, +0x492A63A0, +0x60482001, +0x05186BE3, +0x02180F01, +0x071B079A, +0x0F9B4F16, +0x0D000F92, +0x683E3728, +0x43AE2510, +0x260F603E, +0x02364F12, +0xF7FF603E, +0x491FFE8D, +0x43286808, +0x481A6008, +0x63A03024, +0xB530E7CD, +0x22021C04, +0x2CC001D0, +0xD0074D19, +0x338123FF, +0xD12F429C, +0x43C06A69, +0xE0014008, +0x43086A69, +0x08806268, +0x43100080, +0x0000E02C, +0x01010004, +0x00000460, +0x01000040, +0x010101C0, +0x0700F000, +0x01000180, +0x01000304, +0x022B00C8, +0x0700F100, +0x20100044, +0x50130014, +0x50750108, +0x50640256, +0x11223344, +0x40010000, +0x4000F000, +0x00000FFC, +0x022D0000, +0x43C06A6A, +0x02094010, +0x62684308, +0x43082103, +0xBD306268, +0xE59FC000, +0xE12FFF1C, +0x0000032D +#else +0xE59FF048, +0xE3A0F004, +0xE3A0F008, +0xE3A0F00C, +0xE3A0F010, +0xE3A0F014, +0xE3A0F018, +0xE3A0F01C, +0xE321F093, +0xE3A03EF0, +0xE1A0D003, +0xEA000108, +0xE3A00000, +0xEE070F90, +0xE1A00000, +0xE1A00000, +0xE1A00000, +0xE1A00000, +0xE1A00000, +0xE12FFF1E, +0x00000020, +0x68104AE8, +0x04492101, +0x60104308, +0x4AE54770, +0x21016810, +0x43880449, +0x47706010, +0xB53048E2, +0x4AE26800, +0x62516841, +0x33204BE0, +0x22026819, +0x60194051, +0x6A0249DD, +0x600A31C0, +0x604A6A42, +0x608A6A82, +0x610A6B02, +0x618A6B82, +0x31801C01, +0x4AD7680B, +0x4BD66153, +0x3340684C, +0x4CD4615C, +0x3480688D, +0x68CD6165, +0x31C049D1, +0x6F05614D, +0x6F426015, +0x6F82601A, +0x6FC06022, +0xBD306008, +0x1C14B5F8, +0x20084684, +0x05451C19, +0x68686328, +0x0F400740, +0xD1FA2801, +0x4AC748C6, +0x4BC76190, +0x2001681A, +0x601A4302, +0x33304BC3, +0x4382681A, +0x2600601A, +0x1C324BC1, +0xE0033B04, +0x2F01685F, +0x3201D100, +0xD3F92A05, +0x33204BB8, +0x2001681A, +0x60184310, +0x30011C30, +0xD3FC2802, +0xF0004660, +0x1C30F94B, +0x28023001, +0x49B5D3FC, +0x27406808, +0x600843B8, +0x30011C30, +0xD3FC2802, +0xD1212C00, +0xFF7EF7FF, +0x680849AE, +0x60084338, +0x2E023601, +0x4AA4D3FC, +0x21116810, +0x60104308, +0x68C81F11, +0xD5FC07C0, +0x07C068C8, +0x48A4D5FC, +0x680138A0, +0x04090C09, +0x48A16001, +0x68013898, +0x04090C09, +0xE0586001, +0xD0012C01, +0xD1542C02, +0x32104A95, +0x07116810, +0x60104388, +0x320C4A95, +0x43886810, +0x4A936010, +0x6810324C, +0x60104388, +0x328C4A90, +0x43886810, +0x4A8E6010, +0x681032CC, +0x60104388, +0x30011C30, +0xD3FC2802, +0xFF41F7FF, +0x6808498C, +0x60084338, +0x30011C30, +0xD3FC2802, +0x30104881, +0x07006801, +0x43014A7F, +0x60113210, +0x310C4980, +0x4A7F6809, +0x320C4301, +0x4A7D6011, +0x6811324C, +0x60114301, +0x328C4A7A, +0x43016811, +0x4A786011, +0x681132CC, +0x60104308, +0x2E0A3601, +0x4A77D3FC, +0x68103AA0, +0x43080C11, +0x4A746010, +0x68103A98, +0x43082120, +0x486D6010, +0x68013020, +0x00490849, +0xF7FF6001, +0x4B6CFF0B, +0x68183330, +0x43082101, +0x486A6018, +0x08496801, +0x60010049, +0xD1042C00, +0x4A654868, +0x20096190, +0x200AE000, +0xBDF86328, +0x4865E726, +0x22016801, +0x43110312, +0x68016001, +0x4311221D, +0x47706001, +0x495FB5F0, +0x22106808, +0x60084390, +0x320C4A5C, +0x23046810, +0x60104318, +0x6803485A, +0x02242407, +0x60034323, +0x351C4D57, +0x2405682B, +0x43230364, +0x6803602B, +0x06ED2501, +0x6003432B, +0x68234C52, +0x433309AE, +0x4F516023, +0x0B2B883C, +0x803C431C, +0x3F044F4D, +0x4334683C, +0x4E4C603C, +0x88343E02, +0x8034431C, +0x3E744E48, +0x43236834, +0x4E476033, +0x88333694, +0x43230BEC, +0x68038033, +0x600343AB, +0x23106808, +0x60084318, +0x21046810, +0x60104388, +0xB5F8BDF0, +0x32084A3A, +0x21816810, +0x43080149, +0x24006010, +0x30011C20, +0xD3FC2814, +0x21036810, +0x60104308, +0x02802001, +0x60880501, +0x253F4834, +0x63A801AD, +0xFF91F7FF, +0xFF9AF7FF, +0x24004831, +0x492B6084, +0x39442000, +0x49296088, +0x39042016, +0xF7FF6008, +0x482AEE58, +0x3001243F, +0x63A001A4, +0x20014929, +0x6BE36048, +0x0F010518, +0x079A0218, +0x4F16071B, +0x0F920F9B, +0x37280D00, +0x2510683E, +0x603E43AE, +0x4F12260F, +0x603E0236, +0xFE8CF7FF, +0x6808491E, +0x60084328, +0x30244819, +0xE7CD63A0, +0x1C04B530, +0x01D02202, +0x4D192CC0, +0x23FFD007, +0x429C3381, +0x6A69D12E, +0x400843C0, +0x6A69E001, +0x62684308, +0x00800880, +0xE02B4310, +0x01010004, +0x00000460, +0x01000040, +0x010101C0, +0x0700F000, +0x01000180, +0x01000304, +0x022B00C8, +0x0700F100, +0x20100044, +0x50130014, +0x50750108, +0x50640256, +0x11223344, +0x40010000, +0x4000F000, +0x00000FFC, +0x022D0000, +0x43C06A6A, +0x02094010, +0x62684308, +0x43082103, +0xBD306268, +0xE59FC000, +0xE12FFF1C, +0x0000032F, +#endif +}; + + +u32 cp2_dfs_code_data[] = +{ +0xE59FF048, +0xE3A0F004, +0xE3A0F008, +0xE3A0F00C, +0xE3A0F010, +0xE3A0F014, +0xE3A0F018, +0xE3A0F01C, +0xE321F093, +0xE3A03EF0, +0xE1A0D003, +0xEA0000E5, +0xE3A00000, +0xEE070F90, +0xE1A00000, +0xE1A00000, +0xE1A00000, +0xE1A00000, +0xE1A00000, +0xE12FFF1E, +0x00000020, +0x68104ACC, +0x04492101, +0x60104308, +0x4AC94770, +0x21016810, +0x43880449, +0x47706010, +0xB53048C6, +0x4AC66800, +0x62516841, +0x33204BC4, +0x22026819, +0x60194051, +0x6A0249C1, +0x600A31C0, +0x604A6A42, +0x608A6A82, +0x610A6B02, +0x618A6B82, +0x31801C01, +0x4ABB680B, +0x4BBA6153, +0x3340684C, +0x4CB8615C, +0x3480688D, +0x68CD6165, +0x31C049B5, +0x6F05614D, +0x6F426015, +0x6F82601A, +0x6FC06022, +0xBD306008, +0x1C14B5F8, +0x20084684, +0x05451C19, +0x68686328, +0x0F400740, +0xD1FA2801, +0x4AAB48AA, +0x4BAB6190, +0x2001681A, +0x601A4302, +0x33304BA7, +0x4382681A, +0x2600601A, +0x1C324BA5, +0xE0033B04, +0x2F01685F, +0x3201D100, +0xD3F92A05, +0x33204B9C, +0x2001681A, +0x60184310, +0x30011C30, +0xD3FC2802, +0xF0004660, +0x1C30F909, +0x28023001, +0x4999D3FC, +0x27406808, +0x600843B8, +0x30011C30, +0xD3FC2802, +0xD1212C00, +0xFF7EF7FF, +0x68084992, +0x60084338, +0x2E023601, +0x4A88D3FC, +0x21116810, +0x60104308, +0x68C81F11, +0xD5FC07C0, +0x07C068C8, +0x4888D5FC, +0x680138A0, +0x04090C09, +0x48856001, +0x68013898, +0x04090C09, +0xE0586001, +0xD0012C01, +0xD1542C02, +0x32104A79, +0x07116810, +0x60104388, +0x320C4A79, +0x43886810, +0x4A776010, +0x6810324C, +0x60104388, +0x328C4A74, +0x43886810, +0x4A726010, +0x681032CC, +0x60104388, +0x30011C30, +0xD3FC2802, +0xFF41F7FF, +0x68084970, +0x60084338, +0x30011C30, +0xD3FC2802, +0x30104865, +0x07006801, +0x43014A63, +0x60113210, +0x310C4964, +0x4A636809, +0x320C4301, +0x4A616011, +0x6811324C, +0x60114301, +0x328C4A5E, +0x43016811, +0x4A5C6011, +0x681132CC, +0x60104308, +0x2E0A3601, +0x4A5BD3FC, +0x68103AA0, +0x43080C11, +0x4A586010, +0x68103A98, +0x43082120, +0x48516010, +0x68013020, +0x00490849, +0xF7FF6001, +0x4B50FF0B, +0x68183330, +0x43082101, +0x484E6018, +0x08496801, +0x60010049, +0xD1042C00, +0x4A49484C, +0x20096190, +0x200AE000, +0xBDF86328, +0x4A47E726, +0x68103A74, +0x06092101, +0x60104308, +0x68103204, +0x60104308, +0x68104A43, +0x40084943, +0x48436010, +0x09096801, +0x60010109, +0xB5F84770, +0x02802001, +0x60880501, +0x312C493B, +0x25016808, +0x60084328, +0x30012000, +0xD3FC2814, +0x32284A36, +0x21606810, +0x60104308, +0x243F4836, +0x63A001A4, +0xFFCFF7FF, +0x32CC4A32, +0x21FF6810, +0x43083119, +0xF7FF6010, +0x482FEE9C, +0x3001243F, +0x63A001A4, +0x6045482D, +0x6BC31C20, +0x0F010518, +0x079A0218, +0x4F1C071B, +0x0F920F9B, +0x37280D00, +0x2410683E, +0x603E43A6, +0x4F18260F, +0x603E0236, +0xFED0F7FF, +0x68084922, +0x60084320, +0x213F481E, +0x01893024, +0xE7CF6388, +0x1C04B530, +0x01D02202, +0x4D1C2CC0, +0x23FFD007, +0x429C3381, +0x6A69D10A, +0x400843C0, +0x6A69E001, +0x62684308, +0x00800880, +0xE0074310, +0x43C06A6A, +0x02094010, +0x62684308, +0x43082103, +0xBD306268, +0x01010004, +0x000003D4, +0x01000040, +0x010101C0, +0x0700F000, +0x01000180, +0x01000304, +0x022B00C8, +0x0700F100, +0x40060018, +0xFE040003, +0x60400008, +0x11223344, +0x400E0000, +0x00000FFC, +0x022D0000, +0xE59FC000, +0xE12FFF1C, +0x000002B3, +}; +#endif diff --git a/include/soc/sprd/sci.h b/include/soc/sprd/sci.h new file mode 100644 index 00000000..7e3dbe46 --- /dev/null +++ b/include/soc/sprd/sci.h @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#ifndef __SPRD_SCI_H__ +#define __SPRD_SCI_H__ + +/** + * sci_glb_read - read value from d-die global register + * @reg: global register address + * @msk: + * + * If read all bits, set msk = -1 + * + * Return read value and mask. + */ +u32 sci_glb_read(unsigned long reg, u32 msk); + +/** + * sci_glb_write - safely write value to d-die global register + * @reg: global register address + * @val: + * @msk: + * + * If write all bits, set msk = -1 + * + * Returns success (0) or negative errno. + */ +int sci_glb_write(unsigned long reg, u32 val, u32 msk); + +/** + * sci_glb_set - force set bit to d-die global register + * @reg: global register address + * @bit: commonly, only set one bit + * + * + * tiger use stand-alone xxx_set/xxx_clr address for all global register + * + * Returns success (0) or negative errno. + */ +int sci_glb_set(unsigned long reg, u32 bit); + +/** + * sci_glb_clr - force clr bit to d-die gglobal register + * @reg: global register address + * @bit: commonly, only clear one bit + * + * + * tiger use stand-alone xxx_set/xxx_clr address for all d-die global register + * + * Returns success (0) or negative errno. + */ +int sci_glb_clr(unsigned long reg, u32 bit); + +#define sci_glb_raw_read(reg) sci_glb_read(reg, -1UL) +#define sci_glb_raw_write(reg, val) sci_glb_write(reg, val, -1UL) + +#define sci_assert(condition) do { WARN_ON(!(condition)); }while(0) + +#endif diff --git a/include/soc/sprd/sci_glb_regs.h b/include/soc/sprd/sci_glb_regs.h new file mode 100644 index 00000000..01b996d7 --- /dev/null +++ b/include/soc/sprd/sci_glb_regs.h @@ -0,0 +1,290 @@ +/* + * Copyright (C) 2013 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SCI_GLB_REGS_H__ +#define __SCI_GLB_REGS_H__ + +#ifndef REG_GLB_CLR +#define REG_GLB_CLR(A) ( A + 0x2000 ) +#endif +#ifndef REG_GLB_SET +#define REG_GLB_SET(A) ( A + 0x1000 ) +#endif + +#ifndef __ASSEMBLER__ + +extern unsigned long sprd_adi_base; +extern unsigned long sprd_adi_phys; +#define SPRD_ADI_BASE sprd_adi_base +#define SPRD_ADI_PHYS sprd_adi_phys + +#include "iomap.h" + +#define REGS_AP_AHB_BASE SPRD_AHB_BASE +#define REGS_AP_APB_BASE SPRD_APBREG_BASE +#define REGS_AON_APB_BASE SPRD_AONAPB_BASE +#define REGS_GPU_APB_BASE SPRD_GPUAPB_BASE +#define REGS_MM_AHB_BASE SPRD_MMAHB_BASE +#define REGS_PMU_APB_BASE SPRD_PMU_BASE +#define REGS_AON_CLK_BASE SPRD_AONCKG_BASE +#define REGS_AON_CLK_CORE_BASE SPRD_AONCKG_BASE +//#define REGS_AON_CLK_BASE SPRD_AON_CLK_CORE_BASE +#define REGS_AP_CLK_BASE SPRD_APBCKG_BASE +#define REGS_AP_CLK_CORE_BASE SPRD_APBCKG_BASE +#define REGS_GPU_CLK_BASE SPRD_GPUCKG_BASE +#define REGS_MM_CLK_BASE SPRD_MMCKG_BASE +#define REGS_PUB_APB_BASE SPRD_PUB_BASE +#define REGS_GLB_BASE SPRD_AONAPB_BASE +/* XXX: please check it! */ +#define REGS_AHB_BASE (SPRD_AHB_BASE + 0x200) +#define SPRD_MISC_BASE SPRD_ADI_BASE + +#define ANA_PWM_BASE (SPRD_ADISLAVE_BASE + 0x20 ) +#define ANA_WDG_BASE (SPRD_ADISLAVE_BASE + 0x40 ) +#define ANA_RTC_BASE (SPRD_ADISLAVE_BASE + 0x80 ) +#define ANA_EIC_BASE (SPRD_ADISLAVE_BASE + 0x100 ) +#define ANA_PIN_BASE (SPRD_ADISLAVE_BASE + 0x180 ) +#define ANA_THM_BASE (SPRD_ADISLAVE_BASE + 0x280 ) +#define ADC_BASE (SPRD_ADISLAVE_BASE + 0x300 ) +#define ANA_CTL_INT_BASE (SPRD_ADISLAVE_BASE + 0x380 ) +#define ANA_BTLC_INT_BASE (SPRD_ADISLAVE_BASE + 0x3c0 ) +#define ANA_AUDIFA_INT_BASE (SPRD_ADISLAVE_BASE + 0x400 ) +#define ANA_GPIO_INT_BASE (SPRD_ADISLAVE_BASE + 0x480 ) +#define ANA_FPU_INT_BASE (SPRD_ADISLAVE_BASE + 0x500 ) +#define ANA_AUDCFGA_INT_BASE (SPRD_ADISLAVE_BASE + 0x600 ) +#define ANA_HDT_INT_BASE (SPRD_ADISLAVE_BASE + 0x700 ) +#define ANA_CTL_GLB_BASE (SPRD_ADISLAVE_BASE + 0x800 ) +#define REGS_ADC_BASE (REGS_ADISLAVE_BASE + 0x300) +#define ANA_REGS_GLB_BASE (REGS_ADISLAVE_BASE + 0x800) + +#ifdef CONFIG_64BIT +#define SPRD_DEV_P2V(paddr) (paddr + io_addr_sprd.base) +#define SPRD_DEV_V2P(vaddr) (vaddr - io_addr_sprd.base) +#else +#define in_range(b, first, len) \ + ((b) >= (first) && (b) <= (first) + (len) - 1) +#define to_range(b, first, base) \ + ( (b) - (first) + (base) ) +static inline unsigned long SPRD_DEV_P2V(paddr) +{ + struct iomap_sprd *mapp; + int length = sizeof(struct iotable_sprd)/sizeof(struct iomap_sprd); + for (mapp = (struct iomap_sprd*) &io_addr_sprd; + length--; mapp++) { + if (in_range(paddr, mapp->paddr, mapp->length) + && mapp->paddr && mapp->length) + return to_range(paddr, mapp->paddr, mapp->vaddr); + } + return ~0; +} + +static inline unsigned long SPRD_DEV_V2P(vaddr) +{ + struct iomap_sprd *mapp; + int length = sizeof(struct iotable_sprd)/sizeof(struct iomap_sprd); + for (mapp = (struct iomap_sprd*) &io_addr_sprd; + length--; mapp++) { + if (in_range(vaddr, mapp->vaddr, mapp->length) + && mapp->vaddr && mapp->length) + return to_range(vaddr, mapp->vaddr, mapp->paddr); + } + return ~0; +} + +#endif + +#define SCI_ADDR(x, y) \ + (phys_addr_t)((phys_addr_t)(x) + (phys_addr_t)(y)) + +#endif + +#if defined(CONFIG_ARCH_SC8825) + +#include "__regs_ahb.h" +#include "__regs_ana_glb2.h" +#include "__regs_ana_glb.h" +#include "__regs_emc.h" +#include "__regs_glb.h" + +#elif defined(CONFIG_ARCH_SCX20) + +#include "./chip_x20/__regs_ada_apb_rf.h" +//#include "./chip_x20/__regs_ana_apb_if.h" +#if defined(CONFIG_ADIE_SC2723S) || defined(CONFIG_ADIE_SC2723) +#include "./chip_x20/__regs_ana_sc2723_glb.h" +#else +#include "./chip_x20/__regs_ana_sc2713s_glb.h" +#endif +#include "./chip_x20/__regs_aon_apb.h" +#include "./chip_x20/__regs_ap_ahb.h" +#include "./chip_x20/__regs_ap_apb.h" +#include "./chip_x20/__regs_avs_apb.h" +#include "./chip_x20/__regs_gpu_apb_rf.h" +#include "./chip_x20/__regs_mm_ahb_rf.h" +#include "./chip_x20/__regs_pmu_apb.h" +#include "./chip_x20/__regs_pub_apb.h" +#include "./chip_x20/__regs_mm_clk.h" +#include "./chip_x20/__regs_aon_clk.h" +#include "./chip_x20/__regs_ap_clk.h" +#define REG_AON_APB_CHIP_ID REG_AON_APB_AON_CHIP_ID + +#elif defined(CONFIG_ARCH_SCX30G) + +#include "./chip_x30g/__regs_ada_apb_rf.h" + +#if defined(CONFIG_ADIE_SC2723S) || defined(CONFIG_ADIE_SC2723) +#include "./chip_x30g/__regs_ana_sc2723_glb.h" +#else +#include "./chip_x30g/__regs_ana_sc2713s_glb.h" +#endif +#if defined(CONFIG_ARCH_SCX30G2) +#include "./chip_x30g/__regs_aon_apb_tshark2.h" +#include "./chip_x30g/__regs_mm_ahb_rf_tshark2.h" +#include "./chip_x30g/__regs_pmu_apb_tshark2.h" +#include "./chip_x30g/__regs_codec_ahb.h" +#else +#include "./chip_x30g/__regs_aon_apb.h" +#include "./chip_x30g/__regs_mm_ahb_rf.h" +#include "./chip_x30g/__regs_pmu_apb.h" +#endif +#include "./chip_x30g/__regs_ap_ahb.h" +#include "./chip_x30g/__regs_ap_apb.h" +#include "./chip_x30g/__regs_avs_apb.h" +#include "./chip_x30g/__regs_gpu_apb_rf.h" +#include "./chip_x30g/__regs_pub_apb.h" +#include "./chip_x30g/__regs_mm_clk.h" +#include "./chip_x30g/__regs_aon_clk.h" +#include "./chip_x30g/__regs_ap_clk.h" +#define REG_AON_APB_CHIP_ID REG_AON_APB_AON_CHIP_ID + + +#elif defined(CONFIG_ARCH_SCX15) +#define REGS_ANA_APB_IF_BASE ANA_REGS_GLB_BASE +#include "./chip_x15/__regs_ana_apb_if.h" +#include "./chip_x15/__regs_aon_apb.h" +#include "./chip_x15/__regs_ap_ahb.h" +#include "./chip_x15/__regs_ap_apb.h" +#include "./chip_x15/__regs_cp_apb_rf.h" +#include "./chip_x15/__regs_wcdma_ahb_rf.h" +#include "./chip_x15/__regs_mm_ahb_rf.h" +#include "./chip_x15/__regs_pmu_apb.h" +#include "./chip_x15/__regs_pub_apb.h" +#include "./chip_x15/__regs_avs_apb.h" +#include "./chip_x15/__regs_aon_clk.h" +#include "./chip_x15/__regs_ap_clk.h" +#include "./chip_x15/__regs_mm_clk.h" +#include "./chip_x15/__regs_gpu_apb.h" +#include "./chip_x15/__regs_gpu_clk.h" +#ifndef BIT_GPIO_EB +#define BIT_GPIO_EB BIT_AON_GPIO_EB +#endif +#define ANA_REG_GLB_LDO_SLP_CTRL0 ANA_REG_GLB_PWR_SLP_CTRL0 +#define ANA_REG_GLB_LDO_SLP_CTRL1 ANA_REG_GLB_PWR_SLP_CTRL1 +#define ANA_REG_GLB_LDO_SLP_CTRL2 ANA_REG_GLB_PWR_SLP_CTRL2 +#define ANA_REG_GLB_LDO_SLP_CTRL3 ANA_REG_GLB_PWR_SLP_CTRL3 +#define REG_AON_APB_CHIP_ID REG_AON_APB_AON_CHIP_ID + +#elif defined(CONFIG_ARCH_SCX35L) + #if defined (CONFIG_ARCH_SCX35L64) + #include "./chip_x35l64/__regs_ana_sc2723_glb.h" + #include "./chip_x35l64/__regs_ada_apb_rf.h" + #include "./chip_x35l64/__regs_aon_apb_rf.h" + #include "./chip_x35l64/__regs_aon_clk.h" + #include "./chip_x35l64/__regs_ap_ahb_rf.h" + #include "./chip_x35l64/__regs_ap_clk.h" + #include "./chip_x35l64/__regs_ap_apb.h" + #include "./chip_x35l64/__regs_gpu_apb_rf.h" + #include "./chip_x35l64/__regs_mm_ahb_rf.h" + #include "./chip_x35l64/__regs_mm_clk.h" + #include "./chip_x35l64/__regs_pmu_apb_rf.h" + #include "./chip_x35l64/__regs_pub_apb.h" + #elif defined (CONFIG_ARCH_SCX35LT8) + #include "./chip_x35lt8/__regs_ana_sc2723_glb.h" + #include "./chip_x35lt8/__regs_ada_apb_rf.h" + #include "./chip_x35lt8/__regs_aon_apb_rf.h" + #include "./chip_x35lt8/__regs_aon_clk.h" + #include "./chip_x35lt8/__regs_ap_ahb_rf.h" + #include "./chip_x35lt8/__regs_ap_clk.h" + #include "./chip_x35lt8/__regs_ap_apb.h" + #include "./chip_x35lt8/__regs_codec_ahb.h" + #include "./chip_x35lt8/__regs_gpu_apb_rf.h" + #include "./chip_x35lt8/__regs_mm_ahb_rf.h" + #include "./chip_x35lt8/__regs_mm_clk.h" + #include "./chip_x35lt8/__regs_pmu_apb_rf.h" + #include "./chip_x35lt8/__regs_pub_apb.h" + +#define REG_AON_APB_CHIP_ID0 REG_AON_APB_PROJ_ID_0 +#define REG_AON_APB_CHIP_ID1 REG_AON_APB_PROJ_ID_1 + + #elif defined(CONFIG_ARCH_SCX20L) + #include "./chip_x20l/__regs_ana_sc2723_glb.h" + #include "./chip_x20l/__regs_ada_apb_rf.h" + #include "./chip_x20l/__regs_aon_apb_rf.h" + #include "./chip_x20l/__regs_aon_clk.h" + #include "./chip_x20l/__regs_ap_ahb_rf.h" + #include "./chip_x20l/__regs_ap_clk.h" + #include "./chip_x20l/__regs_ap_apb.h" + #include "./chip_x20l/__regs_gpu_apb_rf.h" + #include "./chip_x20l/__regs_mm_ahb_rf.h" + #include "./chip_x20l/__regs_mm_clk.h" + #include "./chip_x20l/__regs_pmu_apb_rf.h" + #include "./chip_x20l/__regs_pub_apb.h" + #include "./chip_x20l/__regs_arm7_ahb_rf.h" + #else + #include "./chip_x35l/__regs_ana_sc2723_glb.h" + #include "./chip_x35l/__regs_ada_apb_rf.h" + #include "./chip_x35l/__regs_aon_apb_rf.h" + #include "./chip_x35l/__regs_aon_clk.h" + #include "./chip_x35l/__regs_ap_ahb_rf.h" + #include "./chip_x35l/__regs_ap_clk.h" + #include "./chip_x35l/__regs_ap_apb.h" + #include "./chip_x35l/__regs_gpu_apb_rf.h" + #include "./chip_x35l/__regs_mm_ahb_rf.h" + #include "./chip_x35l/__regs_mm_clk.h" + #include "./chip_x35l/__regs_pmu_apb_rf.h" + #include "./chip_x35l/__regs_pub_apb.h" + #if defined(CONFIG_MACH_SP9830I) + #include "./chip_x35l/__regs_codec_ahb.h" + #endif + #endif +#define REG_AON_APB_CHIP_ID REG_AON_APB_AON_CHIP_ID + +#elif defined(CONFIG_ARCH_SCX35) + +#if defined(CONFIG_ADIE_SC2713S) +#include "./chip_x35/__regs_ana_sc2713s_glb.h" +#else +#include "./chip_x35/__regs_ana_glb.h" +#endif +#include "./chip_x35/__regs_aon_apb.h" +#include "./chip_x35/__regs_aon_clk.h" +#include "./chip_x35/__regs_ap_ahb.h" +#include "./chip_x35/__regs_ap_apb.h" +#include "./chip_x35/__regs_ap_clk.h" +#include "./chip_x35/__regs_gpu_apb.h" +#include "./chip_x35/__regs_gpu_clk.h" +#include "./chip_x35/__regs_mm_ahb.h" +#include "./chip_x35/__regs_mm_clk.h" +#include "./chip_x35/__regs_pmu_apb.h" +#include "./chip_x35/__regs_pub_apb.h" + + +#else + +#error "Unknown architecture specification" + +#endif + +#endif + diff --git a/include/soc/sprd/serial_sprd.h b/include/soc/sprd/serial_sprd.h new file mode 100644 index 00000000..1bf11250 --- /dev/null +++ b/include/soc/sprd/serial_sprd.h @@ -0,0 +1,21 @@ +#ifndef __SERIAL_SPRD_H__ +#define __SERIAL_SPRD_H__ + +/* + * Spreadtrum Bluetooth host wake up type + */ +typedef enum bt_host_wakeup_type{ + BT_NO_WAKE_UP, + BT_RX_WAKE_UP, + BT_RTS_HIGH_WHEN_SLEEP, +}BT_HOST_WAKEUP_TYPE; + +/* + * Spreadtrum platform_data for serial + */ +struct serial_data{ + BT_HOST_WAKEUP_TYPE wakeup_type; + int clk; +}; + +#endif diff --git a/include/soc/sprd/sprd-audio.h b/include/soc/sprd/sprd-audio.h new file mode 100644 index 00000000..3989db1d --- /dev/null +++ b/include/soc/sprd/sprd-audio.h @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARCH_AUDIO_GLB_H +#define __ASM_ARCH_AUDIO_GLB_H + +#if defined(CONFIG_ARCH_SCX35L) +#include "__sprd_audio_sc8835l.h" +#elif defined(CONFIG_ARCH_SCX35) +#include "__sprd_audio_sc8830.h" +#elif defined(CONFIG_ARCH_SC8825) +#include "__sprd_audio_sc8825.h" +#else +#error "Unknown architecture specification" +#endif + +#include "__sprd_audio_power.h" + +typedef struct glb_reg_dump { + char *reg_name; + unsigned long reg; + int count; + int (*func)(void *); +} glb_reg_dump_t; + +#define REG_PAIR(t, r, c, f) {t->reg_name = #r; t->reg = r; t->count = c; t->func = f; t++; } + +#ifndef AUDIO_VBC_REG_DUMP_LIST +#define AUDIO_VBC_REG_DUMP_LIST(t) +#endif +#ifndef AUDIO_CODEC_REG_DUMP_LIST +#define AUDIO_CODEC_REG_DUMP_LIST(t) +#endif +#ifndef AUDIO_IIS_REG_DUMP_LIST +#define AUDIO_IIS_REG_DUMP_LIST(t) +#endif + +#define AUDIO_GLB_REG_DUMP_LIST(t) { \ + AUDIO_VBC_REG_DUMP_LIST(t) \ + AUDIO_CODEC_REG_DUMP_LIST(t) \ + AUDIO_IIS_REG_DUMP_LIST(t) \ +} + +#endif diff --git a/include/soc/sprd/sprd_debug.h b/include/soc/sprd/sprd_debug.h new file mode 100644 index 00000000..d612f299 --- /dev/null +++ b/include/soc/sprd/sprd_debug.h @@ -0,0 +1,172 @@ +#ifndef SPRD_DEBUG_H +#define SPRD_DEBUG_H + +#include <linux/sched.h> +#include <linux/semaphore.h> + + + +#if defined(CONFIG_SPRD_DEBUG) + +#define MAGIC_ADDR (SPRD_IRAM_BASE + 0x00003f64) +#define SPRD_INFORM0 (MAGIC_ADDR + 0x00000004) +#define SPRD_INFORM1 (SPRD_INFORM0 + 0x00000004) +#define SPRD_INFORM2 (SPRD_INFORM1 + 0x00000004) +#define SPRD_INFORM3 (SPRD_INFORM2 + 0x00000004) +#define SPRD_INFORM4 (SPRD_INFORM3 + 0x00000004) +#define SPRD_INFORM5 (SPRD_INFORM4 + 0x00000004) +#define SPRD_INFORM6 (SPRD_INFORM5 + 0x00000004) + +union sprd_debug_level_t { + struct { + u16 kernel_fault; + u16 user_fault; + } en; + u32 uint_val; +}; + +extern union sprd_debug_level_t sprd_debug_level; + +extern int sprd_debug_init(void); + +extern void sprd_debug_check_crash_key(unsigned int code, int value); + +extern void sprd_debug_save_pte(void *pte, int task_addr); + +#else +static inline int sprd_debug_init(void) +{ + return 0; +} + +static inline void sprd_debug_check_crash_key(unsigned int code, int value) +{ +} + +void sprd_debug_save_pte(void *pte, unsigned int faulttype ) +{ +} + +#endif + +struct worker; +struct work_struct; + +#ifdef CONFIG_SPRD_DEBUG_SCHED_LOG +extern void __sprd_debug_task_log(int cpu, struct task_struct *task); +extern void __sprd_debug_irq_log(unsigned int irq, void *fn, int en); +extern void __sprd_debug_work_log(struct worker *worker, + struct work_struct *work, work_func_t f); +extern void __sprd_debug_hrtimer_log(struct hrtimer *timer, + enum hrtimer_restart (*fn) (struct hrtimer *), int en); + +static inline void sprd_debug_task_log(int cpu, struct task_struct *task) +{ + if (unlikely(sprd_debug_level.en.kernel_fault)) + __sprd_debug_task_log(cpu, task); +} + +static inline void sprd_debug_irq_log(unsigned int irq, void *fn, int en) +{ + if (unlikely(sprd_debug_level.en.kernel_fault)) + __sprd_debug_irq_log(irq, fn, en); +} + +static inline void sprd_debug_work_log(struct worker *worker, + struct work_struct *work, work_func_t f) +{ + if (unlikely(sprd_debug_level.en.kernel_fault)) + __sprd_debug_work_log(worker, work, f); +} + +static inline void sprd_debug_hrtimer_log(struct hrtimer *timer, + enum hrtimer_restart (*fn) (struct hrtimer *), int en) +{ +#ifdef CONFIG_SPRD_DEBUG_HRTIMER_LOG + if (unlikely(sprd_debug_level.en.kernel_fault)) + __sprd_debug_hrtimer_log(timer, fn, en); +#endif +} + +static inline void sprd_debug_softirq_log(unsigned int irq, void *fn, int en) +{ +#ifdef CONFIG_SPRD_DEBUG_SOFTIRQ_LOG + if (unlikely(sprd_debug_level.en.kernel_fault)) + __sprd_debug_irq_log(irq, fn, en); +#endif +} + +#else + +static inline void sprd_debug_task_log(int cpu, struct task_struct *task) +{ +} + +static inline void sprd_debug_irq_log(unsigned int irq, void *fn, int en) +{ +} + +static inline void sprd_debug_work_log(struct worker *worker, + struct work_struct *work, work_func_t f) +{ +} + +static inline void sprd_debug_hrtimer_log(struct hrtimer *timer, + enum hrtimer_restart (*fn) (struct hrtimer *), int en) +{ +} + +static inline void sprd_debug_softirq_log(unsigned int irq, void *fn, int en) +{ +} +#endif + + + +/* klaatu - schedule log */ +#ifdef CONFIG_SPRD_DEBUG_SCHED_LOG +#define SCHED_LOG_MAX 1024 +//#define CP_DEBUG + +struct sched_log { + struct task_log { + unsigned long long time; +#ifdef CP_DEBUG + unsigned long sys_cnt; +#endif + char comm[TASK_COMM_LEN]; + pid_t pid; + } task[NR_CPUS][SCHED_LOG_MAX]; + struct irq_log { + unsigned long long time; +#ifdef CP_DEBUG + unsigned long sys_cnt; +#endif + int irq; + void *fn; + int en; + } irq[NR_CPUS][SCHED_LOG_MAX]; + struct work_log { + unsigned long long time; +#ifdef CP_DEBUG + unsigned long sys_cnt; +#endif + struct worker *worker; + struct work_struct *work; + work_func_t f; + } work[NR_CPUS][SCHED_LOG_MAX]; + struct hrtimer_log { + unsigned long long time; +#ifdef CP_DEBUG + unsigned long sys_cnt; +#endif + struct hrtimer *timer; + enum hrtimer_restart (*fn)(struct hrtimer *); + int en; + } hrtimers[NR_CPUS][8]; +}; +#endif /* CONFIG_SPRD_DEBUG_SCHED_LOG */ + + + +#endif /* SPRD_DEBUG_H */ diff --git a/include/soc/sprd/sprd_mem_pool.h b/include/soc/sprd/sprd_mem_pool.h new file mode 100644 index 00000000..27125c4f --- /dev/null +++ b/include/soc/sprd/sprd_mem_pool.h @@ -0,0 +1,6 @@ +#ifndef __SPRD_MEM_POOL_H +#define __SPRD_MEM_POOL_H + +extern struct page *sprd_page_alloc(gfp_t gfp_mask, unsigned int order, unsigned long zoneidx); +extern int sprd_page_mask_check(int pid); +#endif diff --git a/include/soc/sprd/sprd_persistent_clock.h b/include/soc/sprd/sprd_persistent_clock.h new file mode 100644 index 00000000..86909a9e --- /dev/null +++ b/include/soc/sprd/sprd_persistent_clock.h @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __PERSISTENT_CLOCK_SPRD_H +#define __PERSISTENT_CLOCK_SPRD_H + +struct sprd_ap_system_timer { + void __iomem *base; + int irqnr; +}; + +u32 get_sys_cnt(void); +void set_ap_system_timer_expires(u32 expires_ms); +#endif diff --git a/include/soc/sprd/sys_reset.h b/include/soc/sprd/sys_reset.h new file mode 100644 index 00000000..eb84c87c --- /dev/null +++ b/include/soc/sprd/sys_reset.h @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MACH_WATCHDOG_H_ +#define _MACH_WATCHDOG_H_ +#include <linux/spinlock.h> +#include <linux/bitops.h> +#include <soc/sprd/adi.h> +#include <soc/sprd/sci_glb_regs.h> +#include <soc/sprd/sci.h> +#include <soc/sprd/hardware.h> +#define WDG_BASE (ANA_WDG_BASE) +#define SPRD_ANA_BASE (ANA_CTL_GLB_BASE) + +#define WDG_LOAD_LOW (WDG_BASE + 0x00) +#define WDG_LOAD_HIGH (WDG_BASE + 0x04) +#define WDG_CTRL (WDG_BASE + 0x08) +#define WDG_INT_CLR (WDG_BASE + 0x0C) +#define WDG_INT_RAW (WDG_BASE + 0x10) +#define WDG_INT_MSK (WDG_BASE + 0x14) +#define WDG_CNT_LOW (WDG_BASE + 0x18) +#define WDG_CNT_HIGH (WDG_BASE + 0x1C) +#define WDG_LOCK (WDG_BASE + 0x20) + +#define WDG_INT_EN_BIT BIT(0) +#define WDG_CNT_EN_BIT BIT(1) +#define WDG_NEW_VER_EN BIT(2) +#define WDG_INT_CLEAR_BIT BIT(0) +#define WDG_RST_CLEAR_BIT BIT(3) +#define WDG_LD_BUSY_BIT BIT(4) +#define WDG_RST_EN_BIT BIT(3) + +#define WDG_NEW_VERSION +#define ANA_RST_STATUS ANA_REG_GLB_POR_RST_MONITOR +#define ANA_AGEN ANA_REG_GLB_ARM_MODULE_EN +#define ANA_RTC_CLK_EN ANA_REG_GLB_RTC_CLK_EN +#define AGEN_WDG_EN BIT_ANA_WDG_EN +#define AGEN_RTC_WDG_EN BIT_RTC_WDG_EN + +#define WDG_CLK 32768 +#define WDG_UNLOCK_KEY 0xE551 + +#define ANA_WDG_LOAD_TIMEOUT_NUM (10000) + +#ifdef WDG_NEW_VERSION +#define WDG_LOAD_TIMER_VALUE(value) \ + do{\ + sci_adi_raw_write( WDG_LOAD_HIGH, (uint16_t)(((value) >> 16 ) & 0xffff));\ + sci_adi_raw_write( WDG_LOAD_LOW , (uint16_t)((value) & 0xffff) );\ + }while(0) +#else +#define WDG_LOAD_TIMER_VALUE(value) \ + do{\ + uint32_t cnt = 0;\ + sci_adi_raw_write( WDG_LOAD_HIGH, (uint16_t)(((value) >> 16 ) & 0xffff));\ + sci_adi_raw_write( WDG_LOAD_LOW , (uint16_t)((value) & 0xffff) );\ + while((sci_adi_read(WDG_INT_RAW) & WDG_LD_BUSY_BIT) && ( cnt < ANA_WDG_LOAD_TIMEOUT_NUM )) cnt++;\ + }while(0) +#endif + +#define HWRST_STATUS_RECOVERY (0x20) +#define HWRST_STATUS_NORMAL (0X40) +#define HWRST_STATUS_ALARM (0X50) +#define HWRST_STATUS_SLEEP (0X60) +#define HWRST_STATUS_FASTBOOT (0X30) +#define HWRST_STATUS_SPECIAL (0x70) +#define HWRST_STATUS_PANIC (0X80) +#define HWRST_STATUS_CFTREBOOT (0x90) +#define HWRST_STATUS_AUTODLOADER (0xa0) +#define HWRST_STATUS_IQMODE (0xb0) + +void sprd_set_reboot_mode(const char *cmd); +void sprd_turnon_watchdog(unsigned int ms); +void sprd_turnoff_watchdog(void); + +#endif diff --git a/include/soc/sprd/system.h b/include/soc/sprd/system.h new file mode 100644 index 00000000..4aa2ea34 --- /dev/null +++ b/include/soc/sprd/system.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H __FILE__ + +#include <soc/sprd/hardware.h> +#include <soc/sprd/sys_reset.h> + +static inline void arch_idle(void) +{ +} + +static inline void arch_reset(char mode, const char *cmd) +{ + sprd_set_reboot_mode(cmd); + sprd_turnon_watchdog(50); +} + +#endif diff --git a/include/soc/sprd/usb.h b/include/soc/sprd/usb.h new file mode 100644 index 00000000..3d759781 --- /dev/null +++ b/include/soc/sprd/usb.h @@ -0,0 +1,17 @@ +#ifndef _MACH_USB_H +#define _MACH_USB_H + +extern void udc_enable(void); +extern void udc_disable(void); +extern void udc_phy_down(void); +extern void udc_phy_up(void); + +struct usb_hotplug_callback { + int (*plugin)(int usb_cable, void *data); + int (*plugout)(int usb_cable, void *data); + void *data; +}; + +extern int usb_register_hotplug_callback(struct usb_hotplug_callback *cb); + +#endif |