diff options
Diffstat (limited to 'include/soc/sprd/chip_x20l/__regs_pmu_apb_rf.h')
| -rwxr-xr-x | include/soc/sprd/chip_x20l/__regs_pmu_apb_rf.h | 868 |
1 files changed, 868 insertions, 0 deletions
diff --git a/include/soc/sprd/chip_x20l/__regs_pmu_apb_rf.h b/include/soc/sprd/chip_x20l/__regs_pmu_apb_rf.h new file mode 100755 index 00000000..25fd9ced --- /dev/null +++ b/include/soc/sprd/chip_x20l/__regs_pmu_apb_rf.h @@ -0,0 +1,868 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_PMU_APB_HEADFILE_H__ +#define __H_REGS_PMU_APB_HEADFILE_H__ __FILE__ + +#define REGS_PMU_APB_RF + +/* registers definitions for PMU_APB_RF */ +#define REG_PMU_APB_PD_CA7_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0000) +#define REG_PMU_APB_PD_CA7_C0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0004) +#define REG_PMU_APB_PD_CA7_C1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0008) +#define REG_PMU_APB_PD_CA7_C2_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x000C) +#define REG_PMU_APB_PD_CA7_C3_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0010) +#define REG_PMU_APB_PD_AP_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0018) +#define REG_PMU_APB_PD_MM_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x001C) +#define REG_PMU_APB_PD_GPU_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0020) +#define REG_PMU_APB_PD_CP0_ARM9_0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0024) +#define REG_PMU_APB_PD_CP0_ARM9_1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0028) +#define REG_PMU_APB_PD_CP0_HU3GE_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x002C) +#define REG_PMU_APB_PD_CP0_GSM_0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0030) +#define REG_PMU_APB_PD_CP0_GSM_1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0034) +#define REG_PMU_APB_PD_CP0_TD_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0038) +#define REG_PMU_APB_PD_CP0_CEVA_0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x003C) +#define REG_PMU_APB_PD_CP0_CEVA_1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0040) +#define REG_PMU_APB_PD_CP0_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0044) +#define REG_PMU_APB_PD_CP1_CA5_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0048) +#define REG_PMU_APB_PD_CP1_LTE_P1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x004C) +#define REG_PMU_APB_PD_CP1_LTE_P2_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0050) +#define REG_PMU_APB_PD_CP1_CEVA_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0054) +#define REG_PMU_APB_PD_CP1_COMWRAP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0058) +#define REG_PMU_APB_PD_PUB_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x005C) +#define REG_PMU_APB_AP_WAKEUP_POR_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0060) +#define REG_PMU_APB_XTL_WAIT_CNT SCI_ADDR(REGS_PMU_APB_BASE, 0x0070) +#define REG_PMU_APB_XTLBUF_WAIT_CNT SCI_ADDR(REGS_PMU_APB_BASE, 0x0074) +#define REG_PMU_APB_PLL_WAIT_CNT1 SCI_ADDR(REGS_PMU_APB_BASE, 0x0078) +#define REG_PMU_APB_PLL_WAIT_CNT2 SCI_ADDR(REGS_PMU_APB_BASE, 0x007C) +#define REG_PMU_APB_XTL0_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0080) +#define REG_PMU_APB_XTL1_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0084) +#define REG_PMU_APB_XTLBUF0_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x008C) +#define REG_PMU_APB_XTLBUF1_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0090) +#define REG_PMU_APB_MPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0094) +#define REG_PMU_APB_DPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0098) +#define REG_PMU_APB_LTEPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x009C) +#define REG_PMU_APB_TWPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00A0) +#define REG_PMU_APB_LVDSDIS_PLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00A4) +#define REG_PMU_APB_CP_SOFT_RST SCI_ADDR(REGS_PMU_APB_BASE, 0x00B0) +#define REG_PMU_APB_CP_SLP_STATUS_DBG0 SCI_ADDR(REGS_PMU_APB_BASE, 0x00B4) +#define REG_PMU_APB_PWR_STATUS0_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00BC) +#define REG_PMU_APB_PWR_STATUS1_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00C0) +#define REG_PMU_APB_PWR_STATUS2_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00C4) +#define REG_PMU_APB_SLEEP_CTRL SCI_ADDR(REGS_PMU_APB_BASE, 0x00CC) +#define REG_PMU_APB_DDR_SLEEP_CTRL SCI_ADDR(REGS_PMU_APB_BASE, 0x00D0) +#define REG_PMU_APB_SLEEP_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x00D4) +#define REG_PMU_APB_CA7_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00E4) +#define REG_PMU_APB_CA7_C0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00E8) +#define REG_PMU_APB_CA7_C1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00EC) +#define REG_PMU_APB_CA7_C2_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00F0) +#define REG_PMU_APB_CA7_C3_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00F4) +#define REG_PMU_APB_DDR_CHN_SLEEP_CTRL0 SCI_ADDR(REGS_PMU_APB_BASE, 0x00F8) +#define REG_PMU_APB_DDR_CHN_SLEEP_CTRL1 SCI_ADDR(REGS_PMU_APB_BASE, 0x00FC) +#define REG_PMU_APB_DDR_OP_MODE_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x012C) +#define REG_PMU_APB_DDR_PHY_RET_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0130) +#define REG_PMU_APB_26M_SEL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0134) +#define REG_PMU_APB_BISR_DONE_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x0138) +#define REG_PMU_APB_BISR_BUSY_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x013C) +#define REG_PMU_APB_BISR_BYP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0140) +#define REG_PMU_APB_BISR_EN_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0144) +#define REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG0 SCI_ADDR(REGS_PMU_APB_BASE, 0x0148) +#define REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG1 SCI_ADDR(REGS_PMU_APB_BASE, 0x014C) +#define REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG2 SCI_ADDR(REGS_PMU_APB_BASE, 0x0150) +#define REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG3 SCI_ADDR(REGS_PMU_APB_BASE, 0x0154) +#define REG_PMU_APB_CGM_FORCE_EN_CFG0 SCI_ADDR(REGS_PMU_APB_BASE, 0x0158) +#define REG_PMU_APB_CGM_FORCE_EN_CFG1 SCI_ADDR(REGS_PMU_APB_BASE, 0x015C) +#define REG_PMU_APB_CGM_FORCE_EN_CFG2 SCI_ADDR(REGS_PMU_APB_BASE, 0x0160) +#define REG_PMU_APB_CGM_FORCE_EN_CFG3 SCI_ADDR(REGS_PMU_APB_BASE, 0x0164) +#define REG_PMU_APB_SLEEP_XTLON_CTRL SCI_ADDR(REGS_PMU_APB_BASE, 0x0168) +#define REG_PMU_APB_MEM_SLP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x016C) +#define REG_PMU_APB_MEM_SD_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0170) +#define REG_PMU_APB_CA7_CORE_PU_LOCK SCI_ADDR(REGS_PMU_APB_BASE, 0x0174) +#define REG_PMU_APB_ARM7_HOLD_CGM_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0178) +#define REG_PMU_APB_PWR_CNT_WAIT_CFG0 SCI_ADDR(REGS_PMU_APB_BASE, 0x017C) +#define REG_PMU_APB_PWR_CNT_WAIT_CFG1 SCI_ADDR(REGS_PMU_APB_BASE, 0x0180) +#define REG_PMU_APB_RC0_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0184) +#define REG_PMU_APB_RC1_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0188) +#define REG_PMU_APB_RC_CNT_WAIT_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x018C) +#define REG_PMU_APB_MEM_AUTO_SLP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0190) +#define REG_PMU_APB_MEM_AUTO_SD_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0194) +#define REG_PMU_APB_CP0_PD_SHUTDOWN_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0198) +#define REG_PMU_APB_CP1_PD_SHUTDOWN_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x019C) +#define REG_PMU_APB_WAKEUP_LOCK_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x01A0) +#define REG_PMU_APB_PD_CA7_C0_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3000) +#define REG_PMU_APB_PD_CA7_C1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3004) +#define REG_PMU_APB_PD_CA7_C2_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3008) +#define REG_PMU_APB_PD_CA7_C3_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x300C) +#define REG_PMU_APB_PD_CA7_TOP_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3010) +#define REG_PMU_APB_PD_AP_SYS_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3014) +#define REG_PMU_APB_PD_GPU_TOP_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3018) +#define REG_PMU_APB_PD_MM_TOP_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x301C) +#define REG_PMU_APB_PD_CP0_ARM9_0_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3020) +#define REG_PMU_APB_PD_CP0_ARM9_1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3024) +#define REG_PMU_APB_PD_CP0_CEVA_0_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3028) +#define REG_PMU_APB_PD_CP0_CEVA_1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x302C) +#define REG_PMU_APB_PD_CP0_GSM_0_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3030) +#define REG_PMU_APB_PD_CP0_GSM_1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3034) +#define REG_PMU_APB_PD_CP0_TD_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3038) +#define REG_PMU_APB_PD_CP0_HU3GE_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x303C) +#define REG_PMU_APB_PD_CP1_CA5_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3040) +#define REG_PMU_APB_PD_CP1_CEVA_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3044) +#define REG_PMU_APB_PD_CP1_LTE_P1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3048) +#define REG_PMU_APB_PD_CP1_LTE_P2_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x304C) +#define REG_PMU_APB_PD_CP1_COMWRAP_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3050) +#define REG_PMU_APB_PD_PUB_SYS_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3054) + + + +/* bits definitions for register REG_PMU_APB_PD_CA7_TOP_CFG */ +#define BIT_PD_CA7_TOP_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_PD_CA7_TOP_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CA7_TOP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA7_TOP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA7_C0_CFG */ +#define BIT_PD_CA7_C0_WFI_SHUTDOWN_EN ( BIT(29) ) +#define BIT_PD_CA7_C0_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_PD_CA7_C0_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CA7_C0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA7_C0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA7_C1_CFG */ +#define BIT_PD_CA7_C1_WFI_SHUTDOWN_EN ( BIT(29) ) +#define BIT_PD_CA7_C1_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_PD_CA7_C1_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA7_C1_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CA7_C1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA7_C1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA7_C2_CFG */ +#define BIT_PD_CA7_C2_WFI_SHUTDOWN_EN ( BIT(29) ) +#define BIT_PD_CA7_C2_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_PD_CA7_C2_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA7_C2_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CA7_C2_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA7_C2_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA7_C3_CFG */ +#define BIT_PD_CA7_C3_WFI_SHUTDOWN_EN ( BIT(29) ) +#define BIT_PD_CA7_C3_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_PD_CA7_C3_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA7_C3_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CA7_C3_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA7_C3_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_AP_SYS_CFG */ +#define BIT_PD_AP_SYS_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_AP_SYS_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_AP_SYS_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_MM_TOP_CFG */ +#define BIT_PD_MM_TOP_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_MM_TOP_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_MM_TOP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_MM_TOP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_GPU_TOP_CFG */ +#define BIT_PD_GPU_TOP_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_GPU_TOP_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_GPU_TOP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_GPU_TOP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_0_CFG */ +#define BIT_PD_CP0_ARM9_0_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_ARM9_0_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_ARM9_0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_ARM9_0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_ARM9_0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_1_CFG */ +#define BIT_PD_CP0_ARM9_1_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_ARM9_1_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_ARM9_1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_ARM9_1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_ARM9_1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_HU3GE_CFG */ +#define BIT_PD_CP0_HU3GE_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_HU3GE_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_HU3GE_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_HU3GE_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_HU3GE_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_GSM_0_CFG */ +#define BIT_PD_CP0_GSM_0_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_GSM_0_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_GSM_0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_GSM_0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_GSM_0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_GSM_1_CFG */ +#define BIT_PD_CP0_GSM_1_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_GSM_1_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_GSM_1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_GSM_1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_GSM_1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_TD_CFG */ +#define BIT_PD_CP0_TD_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_TD_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_TD_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_TD_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_TD_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_CEVA_0_CFG */ +#define BIT_PD_CP0_CEVA_0_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_CEVA_0_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_CEVA_0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_CEVA_0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_CEVA_0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_CEVA_1_CFG */ +#define BIT_PD_CP0_CEVA_1_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_CEVA_1_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_CEVA_1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_CEVA_1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_CEVA_1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_SYS_CFG */ + +/* bits definitions for register REG_PMU_APB_PD_CP1_CA5_CFG */ +#define BIT_PD_CP1_CA5_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP1_CA5_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP1_CA5_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_CA5_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_CA5_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_LTE_P1_CFG */ +#define BIT_PD_CP1_LTE_P1_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP1_LTE_P1_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP1_LTE_P1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_LTE_P1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_LTE_P1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_LTE_P2_CFG */ +#define BIT_PD_CP1_LTE_P2_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP1_LTE_P2_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP1_LTE_P2_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_LTE_P2_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_LTE_P2_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_CEVA_CFG */ +#define BIT_PD_CP1_CEVA_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP1_CEVA_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP1_CEVA_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_CEVA_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_CEVA_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_COMWRAP_CFG */ +#define BIT_PD_CP1_COMWRAP_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP1_COMWRAP_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP1_COMWRAP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_COMWRAP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_COMWRAP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_PUB_SYS_CFG */ +#define BIT_PD_PUB_SYS_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_PUB_SYS_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_PUB_SYS_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_AP_WAKEUP_POR_CFG */ +#define BIT_AP_WAKEUP_POR_N ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_XTL_WAIT_CNT */ +#define BITS_XTL1_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_XTL0_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_XTLBUF_WAIT_CNT */ +#define BITS_XTLBUF1_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_XTLBUF0_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PLL_WAIT_CNT1 */ +#define BITS_LTEPLL_WAIT_CNT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_TWPLL_WAIT_CNT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DPLL_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_MPLL_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PLL_WAIT_CNT2 */ +#define BITS_LVDSDIS_PLL_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_XTL0_REL_CFG */ +#define BIT_XTL0_ARM7_SEL ( BIT(5) ) +#define BIT_XTL0_VCP1_SEL ( BIT(4) ) +#define BIT_XTL0_VCP0_SEL ( BIT(3) ) +#define BIT_XTL0_CP1_SEL ( BIT(2) ) +#define BIT_XTL0_CP0_SEL ( BIT(1) ) +#define BIT_XTL0_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_XTL1_REL_CFG */ +#define BIT_XTL1_ARM7_SEL ( BIT(5) ) +#define BIT_XTL1_VCP1_SEL ( BIT(4) ) +#define BIT_XTL1_VCP0_SEL ( BIT(3) ) +#define BIT_XTL1_CP1_SEL ( BIT(2) ) +#define BIT_XTL1_CP0_SEL ( BIT(1) ) +#define BIT_XTL1_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_XTLBUF0_REL_CFG */ +#define BIT_XTLBUF0_ARM7_SEL ( BIT(5) ) +#define BIT_XTLBUF0_VCP1_SEL ( BIT(4) ) +#define BIT_XTLBUF0_VCP0_SEL ( BIT(3) ) +#define BIT_XTLBUF0_CP1_SEL ( BIT(2) ) +#define BIT_XTLBUF0_CP0_SEL ( BIT(1) ) +#define BIT_XTLBUF0_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_XTLBUF1_REL_CFG */ +#define BIT_XTLBUF1_ARM7_SEL ( BIT(5) ) +#define BIT_XTLBUF1_VCP1_SEL ( BIT(4) ) +#define BIT_XTLBUF1_VCP0_SEL ( BIT(3) ) +#define BIT_XTLBUF1_CP1_SEL ( BIT(2) ) +#define BIT_XTLBUF1_CP0_SEL ( BIT(1) ) +#define BIT_XTLBUF1_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_MPLL_REL_CFG */ +#define BIT_MPLL_REF_SEL ( BIT(8) ) +#define BIT_MPLL_ARM7_SEL ( BIT(5) ) +#define BIT_MPLL_VCP1_SEL ( BIT(4) ) +#define BIT_MPLL_VCP0_SEL ( BIT(3) ) +#define BIT_MPLL_CP1_SEL ( BIT(2) ) +#define BIT_MPLL_CP0_SEL ( BIT(1) ) +#define BIT_MPLL_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_DPLL_REL_CFG */ +#define BIT_DPLL_REF_SEL ( BIT(8) ) +#define BIT_DPLL_ARM7_SEL ( BIT(5) ) +#define BIT_DPLL_VCP1_SEL ( BIT(4) ) +#define BIT_DPLL_VCP0_SEL ( BIT(3) ) +#define BIT_DPLL_CP1_SEL ( BIT(2) ) +#define BIT_DPLL_CP0_SEL ( BIT(1) ) +#define BIT_DPLL_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_LTEPLL_REL_CFG */ +#define BIT_LTEPLL_REF_SEL ( BIT(8) ) +#define BIT_LTEPLL_ARM7_SEL ( BIT(5) ) +#define BIT_LTEPLL_VCP1_SEL ( BIT(4) ) +#define BIT_LTEPLL_VCP0_SEL ( BIT(3) ) +#define BIT_LTEPLL_CP1_SEL ( BIT(2) ) +#define BIT_LTEPLL_CP0_SEL ( BIT(1) ) +#define BIT_LTEPLL_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_TWPLL_REL_CFG */ +#define BIT_TWPLL_REF_SEL ( BIT(8) ) +#define BIT_TWPLL_ARM7_SEL ( BIT(5) ) +#define BIT_TWPLL_VCP1_SEL ( BIT(4) ) +#define BIT_TWPLL_VCP0_SEL ( BIT(3) ) +#define BIT_TWPLL_CP1_SEL ( BIT(2) ) +#define BIT_TWPLL_CP0_SEL ( BIT(1) ) +#define BIT_TWPLL_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_LVDSDIS_PLL_REL_CFG */ +#define BIT_LVDSDIS_PLL_REF_SEL ( BIT(8) ) +#define BIT_LVDSDIS_PLL_ARM7_SEL ( BIT(5) ) +#define BIT_LVDSDIS_PLL_VCP1_SEL ( BIT(4) ) +#define BIT_LVDSDIS_PLL_VCP0_SEL ( BIT(3) ) +#define BIT_LVDSDIS_PLL_CP1_SEL ( BIT(2) ) +#define BIT_LVDSDIS_PLL_CP0_SEL ( BIT(1) ) +#define BIT_LVDSDIS_PLL_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CP_SOFT_RST */ +#define BIT_ARM7_SOFT_RST ( BIT(8) ) +#define BIT_PUB_SOFT_RST ( BIT(6) ) +#define BIT_AP_SOFT_RST ( BIT(5) ) +#define BIT_GPU_SOFT_RST ( BIT(4) ) +#define BIT_MM_SOFT_RST ( BIT(3) ) +#define BIT_CP1_SOFT_RST ( BIT(1) ) +#define BIT_CP0_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CP_SLP_STATUS_DBG0 */ +#define BITS_CP1_DEEP_SLP_DBG(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_CP0_DEEP_SLP_DBG(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_PMU_APB_PWR_STATUS0_DBG */ +#define BITS_PD_MM_TOP_STATE(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_PD_GPU_TOP_STATE(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_PD_AP_SYS_STATE(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA7_C3_STATE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_PD_CA7_C2_STATE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA7_C1_STATE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_PD_CA7_C0_STATE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_PD_CA7_TOP_STATE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PWR_STATUS1_DBG */ +#define BITS_PD_CP0_CEVA_1_STATE(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_PD_CP0_CEVA_0_STATE(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_PD_CP0_GSM_0_STATE(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_GSM_1_STATE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_PD_CP0_HU3GE_STATE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_ARM9_1_STATE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_PD_CP0_ARM9_0_STATE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_PD_CP0_TD_STATE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PWR_STATUS2_DBG */ +#define BITS_PD_PUB_SYS_STATE(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_PD_CP1_COMWRAP_STATE(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_LTE_P2_STATE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_PD_CP1_LTE_P1_STATE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_CEVA_STATE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_PD_CP1_CA5_STATE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_SLEEP_CTRL */ +#define BIT_VCP1_FORCE_LIGHT_SLEEP ( BIT(28) ) +#define BIT_VCP0_FORCE_LIGHT_SLEEP ( BIT(27) ) +#define BIT_CP1_FORCE_LIGHT_SLEEP ( BIT(26) ) +#define BIT_CP0_FORCE_LIGHT_SLEEP ( BIT(25) ) +#define BIT_AP_FORCE_LIGHT_SLEEP ( BIT(24) ) +#define BIT_ARM7_FORCE_DEEP_SLEEP ( BIT(21) ) +#define BIT_VCP1_FORCE_DEEP_SLEEP ( BIT(20) ) +#define BIT_VCP0_FORCE_DEEP_SLEEP ( BIT(19) ) +#define BIT_CP1_FORCE_DEEP_SLEEP ( BIT(18) ) +#define BIT_CP0_FORCE_DEEP_SLEEP ( BIT(17) ) +#define BIT_AP_FORCE_DEEP_SLEEP ( BIT(16) ) +#define BIT_VCP1_LIGHT_SLEEP ( BIT(12) ) +#define BIT_VCP0_LIGHT_SLEEP ( BIT(11) ) +#define BIT_CP1_LIGHT_SLEEP ( BIT(10) ) +#define BIT_CP0_LIGHT_SLEEP ( BIT(9) ) +#define BIT_AP_LIGHT_SLEEP ( BIT(8) ) +#define BIT_VCP1_DEEP_SLEEP ( BIT(4) ) +#define BIT_VCP0_DEEP_SLEEP ( BIT(3) ) +#define BIT_CP1_DEEP_SLEEP ( BIT(2) ) +#define BIT_CP0_DEEP_SLEEP ( BIT(1) ) +#define BIT_AP_DEEP_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_DDR_SLEEP_CTRL */ +#define BIT_BUSY_TRANSFER_HWDATA_SEL ( BIT(16) ) +#define BIT_DDR_PUBL_APB_SOFT_RST ( BIT(12) ) +#define BIT_DDR_UMCTL_APB_SOFT_RST ( BIT(11) ) +#define BIT_DDR_PUBL_SOFT_RST ( BIT(10) ) +#define BIT_DDR_PHY_SOFT_RST ( BIT(8) ) +#define BIT_DDR_PHY_AUTO_GATE_EN ( BIT(6) ) +#define BIT_DDR_PUBL_AUTO_GATE_EN ( BIT(5) ) +#define BIT_DDR_UMCTL_AUTO_GATE_EN ( BIT(4) ) +#define BIT_DDR_PHY_EB ( BIT(2) ) +#define BIT_DDR_UMCTL_EB ( BIT(1) ) +#define BIT_DDR_PUBL_EB ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_SLEEP_STATUS */ +#define BITS_ARM7_SLP_STATUS(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_VCP1_SLP_STATUS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_VCP0_SLP_STATUS(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_CP1_SLP_STATUS(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CP0_SLP_STATUS(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_AP_SLP_STATUS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_CA7_TOP_CFG */ +#define BIT_CA7_L2RSTDISABLE ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CA7_C0_CFG */ +#define BIT_CA7_VINITHI_C0 ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CA7_C1_CFG */ +#define BIT_CA7_VINITHI_C1 ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CA7_C2_CFG */ +#define BIT_CA7_VINITHI_C2 ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CA7_C3_CFG */ +#define BIT_CA7_VINITHI_C3 ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_DDR_CHN_SLEEP_CTRL0 */ +#define BIT_DDR_CTRL_AXI_LP_EN ( BIT(31) ) +#define BIT_DDR_CTRL_CGM_SEL ( BIT(30) ) +#define BIT_DDR_CHN9_AXI_LP_EN ( BIT(25) ) +#define BIT_DDR_CHN8_AXI_LP_EN ( BIT(24) ) +#define BIT_DDR_CHN7_AXI_LP_EN ( BIT(23) ) +#define BIT_DDR_CHN6_AXI_LP_EN ( BIT(22) ) +#define BIT_DDR_CHN5_AXI_LP_EN ( BIT(21) ) +#define BIT_DDR_CHN4_AXI_LP_EN ( BIT(20) ) +#define BIT_DDR_CHN3_AXI_LP_EN ( BIT(19) ) +#define BIT_DDR_CHN2_AXI_LP_EN ( BIT(18) ) +#define BIT_DDR_CHN1_AXI_LP_EN ( BIT(17) ) +#define BIT_DDR_CHN0_AXI_LP_EN ( BIT(16) ) +#define BIT_DDR_CHN9_CGM_SEL ( BIT(9) ) +#define BIT_DDR_CHN8_CGM_SEL ( BIT(8) ) +#define BIT_DDR_CHN7_CGM_SEL ( BIT(7) ) +#define BIT_DDR_CHN6_CGM_SEL ( BIT(6) ) +#define BIT_DDR_CHN5_CGM_SEL ( BIT(5) ) +#define BIT_DDR_CHN4_CGM_SEL ( BIT(4) ) +#define BIT_DDR_CHN3_CGM_SEL ( BIT(3) ) +#define BIT_DDR_CHN2_CGM_SEL ( BIT(2) ) +#define BIT_DDR_CHN1_CGM_SEL ( BIT(1) ) +#define BIT_DDR_CHN0_CGM_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_DDR_CHN_SLEEP_CTRL1 */ +#define BIT_DDR_CHN9_AXI_STOP_SEL ( BIT(9) ) +#define BIT_DDR_CHN8_AXI_STOP_SEL ( BIT(8) ) +#define BIT_DDR_CHN7_AXI_STOP_SEL ( BIT(7) ) +#define BIT_DDR_CHN6_AXI_STOP_SEL ( BIT(6) ) +#define BIT_DDR_CHN5_AXI_STOP_SEL ( BIT(5) ) +#define BIT_DDR_CHN4_AXI_STOP_SEL ( BIT(4) ) +#define BIT_DDR_CHN3_AXI_STOP_SEL ( BIT(3) ) +#define BIT_DDR_CHN2_AXI_STOP_SEL ( BIT(2) ) +#define BIT_DDR_CHN1_AXI_STOP_SEL ( BIT(1) ) +#define BIT_DDR_CHN0_AXI_STOP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_DDR_OP_MODE_CFG */ +#define BIT_DDR_OPERATE_MODE_BUSY ( BIT(28) ) +#define BIT_DDR_PUBL_RET_EN ( BIT(27) ) +#define BIT_DDR_PHY_ISO_RST_EN ( BIT(26) ) +#define BIT_DDR_UMCTL_RET_EN ( BIT(25) ) +#define BIT_DDR_PHY_AUTO_RET_EN ( BIT(24) ) +#define BITS_DDR_OPERATE_MODE_CNT_LMT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DDR_OPERATE_MODE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_DDR_OPERATE_MODE_IDLE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_PMU_APB_DDR_PHY_RET_CFG */ +#define BIT_DDR_UMCTL_SOFT_RST ( BIT(16) ) +#define BIT_DDR_PHY_CKE_RET_EN ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_26M_SEL_CFG */ +#define BIT_AON_RC_4M_SEL ( BIT(8) ) +#define BIT_GGE_26M_SEL ( BIT(6) ) +#define BIT_PUB_26M_SEL ( BIT(5) ) +#define BIT_AON_26M_SEL ( BIT(4) ) +#define BIT_CP1_26M_SEL ( BIT(2) ) +#define BIT_CP0_26M_SEL ( BIT(1) ) +#define BIT_AP_26M_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_BISR_DONE_STATUS */ +#define BIT_PD_CP1_COMWRAP_BISR_DONE ( BIT(21) ) +#define BIT_PD_CP1_LTE_P2_BISR_DONE ( BIT(20) ) +#define BIT_PD_CP1_LTE_P1_BISR_DONE ( BIT(19) ) +#define BIT_PD_CP1_CEVA_BISR_DONE ( BIT(18) ) +#define BIT_PD_CP1_CA5_BISR_DONE ( BIT(17) ) +#define BIT_PD_CP0_HU3GE_BISR_DONE ( BIT(15) ) +#define BIT_PD_CP0_TD_BISR_DONE ( BIT(14) ) +#define BIT_PD_CP0_GSM_1_BISR_DONE ( BIT(13) ) +#define BIT_PD_CP0_GSM_0_BISR_DONE ( BIT(12) ) +#define BIT_PD_CP0_CEVA_1_BISR_DONE ( BIT(11) ) +#define BIT_PD_CP0_CEVA_0_BISR_DONE ( BIT(10) ) +#define BIT_PD_CP0_ARM9_1_BISR_DONE ( BIT(9) ) +#define BIT_PD_CP0_ARM9_0_BISR_DONE ( BIT(8) ) +#define BIT_PD_MM_TOP_BISR_DONE ( BIT(7) ) +#define BIT_PD_GPU_TOP_BISR_DONE ( BIT(6) ) +#define BIT_PD_AP_SYS_BISR_DONE ( BIT(5) ) +#define BIT_PD_CA7_TOP_BISR_DONE ( BIT(4) ) +#define BIT_PD_CA7_C3_BISR_DONE ( BIT(3) ) +#define BIT_PD_CA7_C2_BISR_DONE ( BIT(2) ) +#define BIT_PD_CA7_C1_BISR_DONE ( BIT(1) ) +#define BIT_PD_CA7_C0_BISR_DONE ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_BISR_BUSY_STATUS */ +#define BIT_PD_CP1_COMWRAP_BISR_BUSY ( BIT(21) ) +#define BIT_PD_CP1_LTE_P2_BISR_BUSY ( BIT(20) ) +#define BIT_PD_CP1_LTE_P1_BISR_BUSY ( BIT(19) ) +#define BIT_PD_CP1_CEVA_BISR_BUSY ( BIT(18) ) +#define BIT_PD_CP1_CA5_BISR_BUSY ( BIT(17) ) +#define BIT_PD_CP0_HU3GE_BISR_BUSY ( BIT(15) ) +#define BIT_PD_CP0_TD_BISR_BUSY ( BIT(14) ) +#define BIT_PD_CP0_GSM_1_BISR_BUSY ( BIT(13) ) +#define BIT_PD_CP0_GSM_0_BISR_BUSY ( BIT(12) ) +#define BIT_PD_CP0_CEVA_1_BISR_BUSY ( BIT(11) ) +#define BIT_PD_CP0_CEVA_0_BISR_BUSY ( BIT(10) ) +#define BIT_PD_CP0_ARM9_1_BISR_BUSY ( BIT(9) ) +#define BIT_PD_CP0_ARM9_0_BISR_BUSY ( BIT(8) ) +#define BIT_PD_MM_TOP_BISR_BUSY ( BIT(7) ) +#define BIT_PD_GPU_TOP_BISR_BUSY ( BIT(6) ) +#define BIT_PD_AP_SYS_BISR_BUSY ( BIT(5) ) +#define BIT_PD_CA7_TOP_BISR_BUSY ( BIT(4) ) +#define BIT_PD_CA7_C3_BISR_BUSY ( BIT(3) ) +#define BIT_PD_CA7_C2_BISR_BUSY ( BIT(2) ) +#define BIT_PD_CA7_C1_BISR_BUSY ( BIT(1) ) +#define BIT_PD_CA7_C0_BISR_BUSY ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_BISR_BYP_CFG */ +#define BIT_PD_CP1_COMWRAP_BISR_FORCE_BYP ( BIT(21) ) +#define BIT_PD_CP1_LTE_P2_BISR_FORCE_BYP ( BIT(20) ) +#define BIT_PD_CP1_LTE_P1_BISR_FORCE_BYP ( BIT(19) ) +#define BIT_PD_CP1_CEVA_BISR_FORCE_BYP ( BIT(18) ) +#define BIT_PD_CP1_CA5_BISR_FORCE_BYP ( BIT(17) ) +#define BIT_PD_CP0_HU3GE_BISR_FORCE_BYP ( BIT(15) ) +#define BIT_PD_CP0_TD_BISR_FORCE_BYP ( BIT(14) ) +#define BIT_PD_CP0_GSM_1_BISR_FORCE_BYP ( BIT(13) ) +#define BIT_PD_CP0_GSM_0_BISR_FORCE_BYP ( BIT(12) ) +#define BIT_PD_CP0_CEVA_1_BISR_FORCE_BYP ( BIT(11) ) +#define BIT_PD_CP0_CEVA_0_BISR_FORCE_BYP ( BIT(10) ) +#define BIT_PD_CP0_ARM9_1_BISR_FORCE_BYP ( BIT(9) ) +#define BIT_PD_CP0_ARM9_0_BISR_FORCE_BYP ( BIT(8) ) +#define BIT_PD_MM_TOP_BISR_FORCE_BYP ( BIT(7) ) +#define BIT_PD_GPU_TOP_BISR_FORCE_BYP ( BIT(6) ) +#define BIT_PD_AP_SYS_BISR_FORCE_BYP ( BIT(5) ) +#define BIT_PD_CA7_TOP_BISR_FORCE_BYP ( BIT(4) ) +#define BIT_PD_CA7_C3_BISR_FORCE_BYP ( BIT(3) ) +#define BIT_PD_CA7_C2_BISR_FORCE_BYP ( BIT(2) ) +#define BIT_PD_CA7_C1_BISR_FORCE_BYP ( BIT(1) ) +#define BIT_PD_CA7_C0_BISR_FORCE_BYP ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_BISR_EN_CFG */ +#define BIT_PD_CP1_COMWRAP_BISR_FORCE_EN ( BIT(21) ) +#define BIT_PD_CP1_LTE_P2_BISR_FORCE_EN ( BIT(20) ) +#define BIT_PD_CP1_LTE_P1_BISR_FORCE_EN ( BIT(19) ) +#define BIT_PD_CP1_CEVA_BISR_FORCE_EN ( BIT(18) ) +#define BIT_PD_CP1_CA5_BISR_FORCE_EN ( BIT(17) ) +#define BIT_PD_CP0_HU3GE_BISR_FORCE_EN ( BIT(15) ) +#define BIT_PD_CP0_TD_BISR_FORCE_EN ( BIT(14) ) +#define BIT_PD_CP0_GSM_1_BISR_FORCE_EN ( BIT(13) ) +#define BIT_PD_CP0_GSM_0_BISR_FORCE_EN ( BIT(12) ) +#define BIT_PD_CP0_CEVA_1_BISR_FORCE_EN ( BIT(11) ) +#define BIT_PD_CP0_CEVA_0_BISR_FORCE_EN ( BIT(10) ) +#define BIT_PD_CP0_ARM9_1_BISR_FORCE_EN ( BIT(9) ) +#define BIT_PD_CP0_ARM9_0_BISR_FORCE_EN ( BIT(8) ) +#define BIT_PD_MM_TOP_BISR_FORCE_EN ( BIT(7) ) +#define BIT_PD_GPU_TOP_BISR_FORCE_EN ( BIT(6) ) +#define BIT_PD_AP_SYS_BISR_FORCE_EN ( BIT(5) ) +#define BIT_PD_CA7_TOP_BISR_FORCE_EN ( BIT(4) ) +#define BIT_PD_CA7_C3_BISR_FORCE_EN ( BIT(3) ) +#define BIT_PD_CA7_C2_BISR_FORCE_EN ( BIT(2) ) +#define BIT_PD_CA7_C1_BISR_FORCE_EN ( BIT(1) ) +#define BIT_PD_CA7_C0_BISR_FORCE_EN ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG0 */ +#define BITS_CGM_AUTO_GATE_SEL_CFG0(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG1 */ +#define BITS_CGM_AUTO_GATE_SEL_CFG1(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG2 */ +#define BITS_CGM_AUTO_GATE_SEL_CFG2(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG3 */ +#define BITS_CGM_AUTO_GATE_SEL_CFG3(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CGM_FORCE_EN_CFG0 */ +#define BITS_CGM_FORCE_EN_CFG0(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CGM_FORCE_EN_CFG1 */ +#define BITS_CGM_FORCE_EN_CFG1(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CGM_FORCE_EN_CFG2 */ +#define BITS_CGM_FORCE_EN_CFG2(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CGM_FORCE_EN_CFG3 */ +#define BITS_CGM_FORCE_EN_CFG3(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_SLEEP_XTLON_CTRL */ +#define BIT_ARM7_SLEEP_XTL_ON ( BIT(5) ) +#define BIT_VCP1_SLEEP_XTL_ON ( BIT(4) ) +#define BIT_VCP0_SLEEP_XTL_ON ( BIT(3) ) +#define BIT_CP1_SLEEP_XTL_ON ( BIT(2) ) +#define BIT_CP0_SLEEP_XTL_ON ( BIT(1) ) +#define BIT_AP_SLEEP_XTL_ON ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_MEM_SLP_CFG */ +#define BITS_MEM_SLP_CFG(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_MEM_SD_CFG */ +#define BITS_MEM_SD_CFG(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CA7_CORE_PU_LOCK */ +#define BIT_CA7_C3_GIC_WAKEUP_EN ( BIT(11) ) +#define BIT_CA7_C2_GIC_WAKEUP_EN ( BIT(10) ) +#define BIT_CA7_C1_GIC_WAKEUP_EN ( BIT(9) ) +#define BIT_CA7_C0_GIC_WAKEUP_EN ( BIT(8) ) +#define BIT_CA7_C3_PU_LOCK ( BIT(3) ) +#define BIT_CA7_C2_PU_LOCK ( BIT(2) ) +#define BIT_CA7_C1_PU_LOCK ( BIT(1) ) +#define BIT_CA7_C0_PU_LOCK ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_ARM7_HOLD_CGM_EN */ +#define BIT_PD_CP1_CEVA_CGM_HOLD_EN ( BIT(10) ) +#define BIT_PD_CP1_CA5_CGM_HOLD_EN ( BIT(9) ) +#define BIT_PD_CP0_CEVA_1_CGM_HOLD_EN ( BIT(8) ) +#define BIT_PD_CP0_CEVA_0_CGM_HOLD_EN ( BIT(7) ) +#define BIT_PD_CP0_ARM9_1_CGM_HOLD_EN ( BIT(6) ) +#define BIT_PD_CP0_ARM9_0_CGM_HOLD_EN ( BIT(5) ) +#define BIT_PD_CA7_TOP_CMG_HOLD_EN ( BIT(4) ) +#define BIT_PD_CA7_C3_CMG_HOLD_EN ( BIT(3) ) +#define BIT_PD_CA7_C2_CMG_HOLD_EN ( BIT(2) ) +#define BIT_PD_CA7_C1_CMG_HOLD_EN ( BIT(1) ) +#define BIT_PD_CA7_C0_CMG_HOLD_EN ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_PWR_CNT_WAIT_CFG0 */ +#define BITS_VCP0_PWR_WAIT_CNT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_CP1_PWR_WAIT_CNT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_CP0_PWR_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_AP_PWR_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PWR_CNT_WAIT_CFG1 */ +#define BITS_ARM7_PWR_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_VCP1_PWR_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_RC0_REL_CFG */ +#define BIT_RC0_ARM7_SEL ( BIT(5) ) +#define BIT_RC0_VCP1_SEL ( BIT(4) ) +#define BIT_RC0_VCP0_SEL ( BIT(3) ) +#define BIT_RC0_CP1_SEL ( BIT(2) ) +#define BIT_RC0_CP0_SEL ( BIT(1) ) +#define BIT_RC0_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_RC1_REL_CFG */ +#define BIT_RC1_ARM7_SEL ( BIT(5) ) +#define BIT_RC1_VCP1_SEL ( BIT(4) ) +#define BIT_RC1_VCP0_SEL ( BIT(3) ) +#define BIT_RC1_CP1_SEL ( BIT(2) ) +#define BIT_RC1_CP0_SEL ( BIT(1) ) +#define BIT_RC1_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_RC_CNT_WAIT_CFG */ +#define BITS_RC1_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_RC0_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_MEM_AUTO_SLP_CFG */ +#define BITS_MEM_AUTO_SLP_EN(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_MEM_AUTO_SD_CFG */ +#define BITS_MEM_AUTO_SD_EN(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CP0_PD_SHUTDOWN_CFG */ +#define BIT_PD_CP0_HU3GE_VCP1_SEL ( BIT(20) ) +#define BIT_PD_CP0_TD_VCP1_SEL ( BIT(19) ) +#define BIT_PD_CP0_GSM_0_VCP1_SEL ( BIT(18) ) +#define BIT_PD_CP0_CEVA_0_VCP1_SEL ( BIT(17) ) +#define BIT_PD_CP0_ARM9_1_VCP1_SEL ( BIT(16) ) +#define BIT_PD_CP0_ARM9_0_VCP0_SEL ( BIT(8) ) +#define BIT_PD_CP0_HU3GE_CP0_SEL ( BIT(5) ) +#define BIT_PD_CP0_TD_CP0_SEL ( BIT(4) ) +#define BIT_PD_CP0_GSM_0_CP0_SEL ( BIT(3) ) +#define BIT_PD_CP0_CEVA_0_CP0_SEL ( BIT(2) ) +#define BIT_PD_CP0_ARM9_1_CP0_SEL ( BIT(1) ) +#define BIT_PD_CP0_ARM9_0_CP0_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CP1_PD_SHUTDOWN_CFG */ +#define BIT_PD_CP1_COMWRAP_VCP1_SEL ( BIT(20) ) +#define BIT_PD_CP1_CEVA_VCP1_SEL ( BIT(19) ) +#define BIT_PD_CP1_LTE_P2_VCP1_SEL ( BIT(18) ) +#define BIT_PD_CP1_LTE_P1_VCP1_SEL ( BIT(17) ) +#define BIT_PD_CP1_CA5_VCP1_SEL ( BIT(16) ) +#define BIT_PD_CP1_COMWRAP_CP1_SEL ( BIT(4) ) +#define BIT_PD_CP1_CEVA_CP1_SEL ( BIT(3) ) +#define BIT_PD_CP1_LTE_P2_CP1_SEL ( BIT(2) ) +#define BIT_PD_CP1_LTE_P1_CP1_SEL ( BIT(1) ) +#define BIT_PD_CP1_CA5_CP1_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_WAKEUP_LOCK_EN */ +#define BIT_VCP1_SYS_WAKEUP_LOCK_EN ( BIT(26) ) +#define BIT_VCP0_SYS_WAKEUP_LOCK_EN ( BIT(25) ) +#define BIT_CP1_SYS_WAKEUP_LOCK_EN ( BIT(24) ) +#define BIT_CP0_SYS_WAKEUP_LOCK_EN ( BIT(23) ) +#define BIT_AP_SYS_WAKEUP_LOCK_EN ( BIT(22) ) +#define BIT_PD_PUB_SYS_WAKEUP_LOCK_EN ( BIT(21) ) +#define BIT_PD_CP1_COMWRAP_WAKEUP_LOCK_EN ( BIT(20) ) +#define BIT_PD_CP1_CEVA_WAKEUP_LOCK_EN ( BIT(19) ) +#define BIT_PD_CP1_LTE_P2_WAKEUP_LOCK_EN ( BIT(18) ) +#define BIT_PD_CP1_LTE_P1_WAKEUP_LOCK_EN ( BIT(17) ) +#define BIT_PD_CP1_CA5_WAKEUP_LOCK_EN ( BIT(16) ) +#define BIT_PD_CP0_CEVA_1_WAKEUP_LOCK_EN ( BIT(15) ) +#define BIT_PD_CP0_CEVA_0_WAKEUP_LOCK_EN ( BIT(14) ) +#define BIT_PD_CP0_TD_WAKEUP_LOCK_EN ( BIT(13) ) +#define BIT_PD_CP0_GSM_1_WAKEUP_LOCK_EN ( BIT(12) ) +#define BIT_PD_CP0_GSM_0_WAKEUP_LOCK_EN ( BIT(11) ) +#define BIT_PD_CP0_HU3GE_WAKEUP_LOCK_EN ( BIT(10) ) +#define BIT_PD_CP0_ARM9_1_WAKEUP_LOCK_EN ( BIT(9) ) +#define BIT_PD_CP0_ARM9_0_WAKEUP_LOCK_EN ( BIT(8) ) +#define BIT_PD_MM_TOP_WAKEUP_LOCK_EN ( BIT(7) ) +#define BIT_PD_GPU_TOP_WAKEUP_LOCK_EN ( BIT(6) ) +#define BIT_PD_AP_SYS_WAKEUP_LOCK_EN ( BIT(5) ) +#define BIT_PD_CA7_TOP_WAKEUP_LOCK_EN ( BIT(4) ) +#define BIT_PD_CA7_C3_WAKEUP_LOCK_EN ( BIT(3) ) +#define BIT_PD_CA7_C2_WAKEUP_LOCK_EN ( BIT(2) ) +#define BIT_PD_CA7_C1_WAKEUP_LOCK_EN ( BIT(1) ) +#define BIT_PD_CA7_C0_WAKEUP_LOCK_EN ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_PD_CA7_C0_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CA7_C0_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA7_C1_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CA7_C1_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA7_C2_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CA7_C2_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA7_C3_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CA7_C3_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA7_TOP_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CA7_TOP_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_AP_SYS_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_AP_SYS_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_GPU_TOP_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_GPU_TOP_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_MM_TOP_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_MM_TOP_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_0_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_ARM9_0_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_1_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_ARM9_1_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_CEVA_0_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_CEVA_0_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_CEVA_1_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_CEVA_1_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_GSM_0_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_GSM_0_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_GSM_1_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_GSM_1_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_TD_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_TD_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_HU3GE_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_HU3GE_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_CA5_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP1_CA5_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_CEVA_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP1_CEVA_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_LTE_P1_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP1_LTE_P1_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_LTE_P2_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP1_LTE_P2_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_COMWRAP_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP1_COMWRAP_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_PUB_SYS_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_PUB_SYS_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +#endif |