diff options
Diffstat (limited to 'include/soc/sprd/chip_x35lt8/__regs_ap_clk.h')
| -rw-r--r-- | include/soc/sprd/chip_x35lt8/__regs_ap_clk.h | 227 |
1 files changed, 227 insertions, 0 deletions
diff --git a/include/soc/sprd/chip_x35lt8/__regs_ap_clk.h b/include/soc/sprd/chip_x35lt8/__regs_ap_clk.h new file mode 100644 index 00000000..f7d1073b --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_ap_clk.h @@ -0,0 +1,227 @@ +/* the head file modifier: g 2015-03-19 15:40:59*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_AP_CLK_CORE_HEADFILE_H__ +#define __H_REGS_AP_CLK_CORE_HEADFILE_H__ __FILE__ + +#define REGS_AP_CLK_CORE + +/* registers definitions for AP_CLK_CORE */ +#define REG_AP_CLK_CORE_clk_ap_ahb_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x20)/*clk_ap_ahb_cfg*/ +#define REG_AP_CLK_CORE_clk_ap_apb_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x24)/*clk_ap_apb_cfg*/ +#define REG_AP_CLK_CORE_clk_gsp0_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x28)/*clk_gsp_cfg*/ +#define REG_AP_CLK_CORE_clk_dispc0_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x2c)/*clk_dispc0_cfg*/ +#define REG_AP_CLK_CORE_clk_dispc0_dbi_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x30)/*clk_dispc0_dbi_cfg*/ +#define REG_AP_CLK_CORE_clk_dispc0_dpi_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x34)/*clk_dispc0_dpi_cfg*/ +#define REG_AP_CLK_CORE_clk_nandc_ecc_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x38)/*clk_nandc_ecc_cfg*/ +#define REG_AP_CLK_CORE_clk_sdio0_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x3c)/*clk_sdio0_cfg*/ +#define REG_AP_CLK_CORE_clk_sdio1_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x40)/*clk_sdio1_cfg*/ +#define REG_AP_CLK_CORE_clk_sdio2_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x44)/*clk_sdio2_cfg*/ +#define REG_AP_CLK_CORE_clk_emmc_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x48)/*clk_emmc_cfg*/ +#define REG_AP_CLK_CORE_clk_otg_ref_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x4c)/*clk_otg_ref_cfg*/ +#define REG_AP_CLK_CORE_clk_hsic_ref_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x50)/*clk_hsic_ref_cfg*/ +#define REG_AP_CLK_CORE_clk_uart0_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x54)/*clk_uart0_cfg*/ +#define REG_AP_CLK_CORE_clk_uart1_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x58)/*clk_uart1_cfg*/ +#define REG_AP_CLK_CORE_clk_uart2_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x5c)/*clk_uart2_cfg*/ +#define REG_AP_CLK_CORE_clk_uart3_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x60)/*clk_uart3_cfg*/ +#define REG_AP_CLK_CORE_clk_uart4_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x64)/*clk_uart4_cfg*/ +#define REG_AP_CLK_CORE_clk_i2c0_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x68)/*clk_i2c0_cfg*/ +#define REG_AP_CLK_CORE_clk_i2c1_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x6c)/*clk_i2c1_cfg*/ +#define REG_AP_CLK_CORE_clk_i2c2_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x70)/*clk_i2c2_cfg*/ +#define REG_AP_CLK_CORE_clk_i2c3_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x74)/*clk_i2c3_cfg*/ +#define REG_AP_CLK_CORE_clk_i2c4_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x78)/*clk_i2c4_cfg*/ +#define REG_AP_CLK_CORE_clk_spi0_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x7c)/*clk_spi0_cfg*/ +#define REG_AP_CLK_CORE_clk_spi1_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x80)/*clk_spi1_cfg*/ +#define REG_AP_CLK_CORE_clk_spi2_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x84)/*clk_spi2_cfg*/ +#define REG_AP_CLK_CORE_clk_iis0_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x88)/*clk_iis0_cfg*/ +#define REG_AP_CLK_CORE_clk_iis1_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x8c)/*clk_iis1_cfg*/ +#define REG_AP_CLK_CORE_clk_iis2_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x90)/*clk_iis2_cfg*/ +#define REG_AP_CLK_CORE_clk_iis3_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x94)/*clk_iis3_cfg*/ +#define REG_AP_CLK_CORE_clk_zipenc_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x98)/*clk_zipenc_cfg*/ +#define REG_AP_CLK_CORE_clk_zipdec_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x9c)/*clk_zipdec_cfg*/ +#define REG_AP_CLK_CORE_clk_gsp1_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0xa0)/*clk_gsp1_cfg*/ +#define REG_AP_CLK_AP_AHB_CFG REG_AP_CLK_CORE_clk_ap_ahb_cfg +#define REG_AP_CLK_AP_APB_CFG REG_AP_CLK_CORE_clk_ap_apb_cfg +#define REG_AP_CLK_GSP_CFG REG_AP_CLK_CORE_clk_gsp0_cfg +#define REG_AP_CLK_DISPC0_CFG REG_AP_CLK_CORE_clk_dispc0_cfg +#define REG_AP_CLK_DISPC0_DBI_CFG REG_AP_CLK_CORE_clk_dispc0_dbi_cfg +#define REG_AP_CLK_DISPC0_DPI_CFG REG_AP_CLK_CORE_clk_dispc0_dpi_cfg +#define REG_AP_CLK_NANDC_ECC_CFG REG_AP_CLK_CORE_clk_nandc_ecc_cfg +#define REG_AP_CLK_SDIO0_CFG REG_AP_CLK_CORE_clk_sdio0_cfg +#define REG_AP_CLK_SDIO1_CFG REG_AP_CLK_CORE_clk_sdio1_cfg +#define REG_AP_CLK_SDIO2_CFG REG_AP_CLK_CORE_clk_sdio2_cfg +#define REG_AP_CLK_EMMC_CFG REG_AP_CLK_CORE_clk_emmc_cfg +#define REG_AP_CLK_OTG_REF_CFG REG_AP_CLK_CORE_clk_otg_ref_cfg +#define REG_AP_CLK_HSIC_REF_CFG REG_AP_CLK_CORE_clk_hsic_ref_cfg +#define REG_AP_CLK_UART0_CFG REG_AP_CLK_CORE_clk_uart0_cfg +#define REG_AP_CLK_UART1_CFG REG_AP_CLK_CORE_clk_uart1_cfg +#define REG_AP_CLK_UART2_CFG REG_AP_CLK_CORE_clk_uart2_cfg +#define REG_AP_CLK_UART3_CFG REG_AP_CLK_CORE_clk_uart3_cfg +#define REG_AP_CLK_UART4_CFG REG_AP_CLK_CORE_clk_uart4_cfg +#define REG_AP_CLK_I2C0_CFG REG_AP_CLK_CORE_clk_i2c0_cfg +#define REG_AP_CLK_I2C1_CFG REG_AP_CLK_CORE_clk_i2c1_cfg +#define REG_AP_CLK_I2C2_CFG REG_AP_CLK_CORE_clk_i2c2_cfg +#define REG_AP_CLK_I2C3_CFG REG_AP_CLK_CORE_clk_i2c3_cfg +#define REG_AP_CLK_I2C4_CFG REG_AP_CLK_CORE_clk_i2c4_cfg +#define REG_AP_CLK_SPI0_CFG REG_AP_CLK_CORE_clk_spi0_cfg +#define REG_AP_CLK_SPI1_CFG REG_AP_CLK_CORE_clk_spi1_cfg +#define REG_AP_CLK_SPI2_CFG REG_AP_CLK_CORE_clk_spi2_cfg +#define REG_AP_CLK_IIS0_CFG REG_AP_CLK_CORE_clk_iis0_cfg +#define REG_AP_CLK_IIS1_CFG REG_AP_CLK_CORE_clk_iis1_cfg +#define REG_AP_CLK_IIS2_CFG REG_AP_CLK_CORE_clk_iis2_cfg +#define REG_AP_CLK_IIS3_CFG REG_AP_CLK_CORE_clk_iis3_cfg +#define REG_AP_CLK_ZIPENC_CFG REG_AP_CLK_CORE_clk_zipenc_cfg +#define REG_AP_CLK_ZIPDEC_CFG REG_AP_CLK_CORE_clk_zipdec_cfg + + +/* bits definitions for register REG_AP_CLK_CORE_clk_ap_ahb_cfg */ +#define BITS_CLK_AP_AHB_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_ap_apb_cfg */ +#define BITS_CLK_AP_APB_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_gsp0_cfg */ +#define BITS_CLK_GSP0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_dispc0_cfg */ +#define BITS_CLK_DISPC0_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_DISPC0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_dispc0_dbi_cfg */ +#define BITS_CLK_DISPC0_DBI_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_DISPC0_DBI_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_dispc0_dpi_cfg */ +#define BIT_CLK_DISPC0_DPI_PAD_SEL ( BIT(16) ) +#define BITS_CLK_DISPC0_DPI_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_CLK_DISPC0_DPI_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_nandc_ecc_cfg */ +#define BIT_CLK_NANDC_ECC_SEL ( BIT(0) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_sdio0_cfg */ +#define BITS_CLK_SDIO0_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_SDIO0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_sdio1_cfg */ +#define BITS_CLK_SDIO1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_sdio2_cfg */ +#define BITS_CLK_SDIO2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_emmc_cfg */ +#define BITS_CLK_EMMC_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_otg_ref_cfg */ +#define BIT_CLK_OTG_REF_SEL ( BIT(0) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_hsic_ref_cfg */ +#define BIT_CLK_HSIC_REF_SEL ( BIT(0) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_uart0_cfg */ +#define BITS_CLK_UART0_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_UART0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_uart1_cfg */ +#define BITS_CLK_UART1_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_UART1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_uart2_cfg */ +#define BITS_CLK_UART2_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_UART2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_uart3_cfg */ +#define BITS_CLK_UART3_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_UART3_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_uart4_cfg */ +#define BITS_CLK_UART4_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_UART4_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_i2c0_cfg */ +#define BITS_CLK_I2C0_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_I2C0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_i2c1_cfg */ +#define BITS_CLK_I2C1_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_I2C1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_i2c2_cfg */ +#define BITS_CLK_I2C2_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_I2C2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_i2c3_cfg */ +#define BITS_CLK_I2C3_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_I2C3_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_i2c4_cfg */ +#define BITS_CLK_I2C4_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_I2C4_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_spi0_cfg */ +#define BIT_CLK_SPI0_PAD_SEL ( BIT(16) ) +#define BITS_CLK_SPI0_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_SPI0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_spi1_cfg */ +#define BIT_CLK_SPI1_PAD_SEL ( BIT(16) ) +#define BITS_CLK_SPI1_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_SPI1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_spi2_cfg */ +#define BIT_CLK_SPI2_PAD_SEL ( BIT(16) ) +#define BITS_CLK_SPI2_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_SPI2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_iis0_cfg */ +#define BIT_CLK_IIS0_PAD_SEL ( BIT(16) ) +#define BITS_CLK_IIS0_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_IIS0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_iis1_cfg */ +#define BIT_CLK_IIS1_PAD_SEL ( BIT(16) ) +#define BITS_CLK_IIS1_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_IIS1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_iis2_cfg */ +#define BIT_CLK_IIS2_PAD_SEL ( BIT(16) ) +#define BITS_CLK_IIS2_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_IIS2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_iis3_cfg */ +#define BIT_CLK_IIS3_PAD_SEL ( BIT(16) ) +#define BITS_CLK_IIS3_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_IIS3_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_zipenc_cfg */ +#define BITS_CLK_ZIPENC_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_zipdec_cfg */ +#define BITS_CLK_ZIPDEC_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_gsp1_cfg */ +#define BITS_CLK_GSP1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +#endif |