diff options
| author | Yuval Adam <_@yuv.al> | 2017-08-30 08:25:59 +0000 |
|---|---|---|
| committer | Yuval Adam <_@yuv.al> | 2017-08-30 08:25:59 +0000 |
| commit | 8e4bff4cab0ddac6060645b0715210484d02ff40 (patch) | |
| tree | 3a5c3024371a04692a3a6d9974d001cdff8ebf84 /include/soc/sprd/chip_x35lt8 | |
Diffstat (limited to 'include/soc/sprd/chip_x35lt8')
29 files changed, 10297 insertions, 0 deletions
diff --git a/include/soc/sprd/chip_x35lt8/__clock_tree.h b/include/soc/sprd/chip_x35lt8/__clock_tree.h new file mode 100644 index 00000000..3c53b809 --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__clock_tree.h @@ -0,0 +1,514 @@ +/* + * Copyright (C) 2013 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +/* + * Clock (0)Name, Clock (1)fixed rate, Clock Enable (2)Ctrl and (3)Bit, + * Clock Divisor (4)Ctrl and (5)Bit, Clock Parent (6)Ctrl and (7)Bit, + * and Parent Select (15)Count and (16)Lists[ ... ...] + */ +SCI_CLK_ADD(ext_26m, 26000000, 0, 0, + 0, 0, 0, 0, 0); + +#if 0 +SCI_CLK_ADD(ext_32k, 32768, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_mpll, 0, REG_PMU_APB_CGM_AP_EN, BIT(6), + REG_AON_APB_MPLL_CFG, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_dpll, 0, REG_PMU_APB_CGM_AP_EN, BIT(1), + REG_AON_APB_DPLL_CFG, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_td_sel_i, 0, REG_PMU_APB_TDPLL_REL_CFG, BIT(0), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_w_sel_i, 0, REG_PMU_APB_WPLL_REL_CFG, BIT(0), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_c_sel_i, 0, REG_PMU_APB_CPLL_REL_CFG, BIT(0), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_wifi_sel_i, 0, REG_PMU_APB_WIFIPLL1_REL_CFG, BIT(0), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_tdpll, 768000000, REG_PMU_APB_CGM_AP_EN, BIT(3), + 0, 0, 0, 0, + 1, &clk_td_sel_i); + +SCI_CLK_ADD(clk_wpll, 921600000, REG_PMU_APB_CGM_AP_EN, BIT(5), + 0, 0, 0, 0, + 1, &clk_w_sel_i); + +SCI_CLK_ADD(clk_cpll, 624000000, REG_PMU_APB_CGM_AP_EN, BIT(2), + 0, 0, 0, 0, + 1, &clk_c_sel_i); + +SCI_CLK_ADD(clk_wifipll, 880000000, REG_PMU_APB_CGM_AP_EN, BIT(4), + 0, 0, 0, 0, + 1, &clk_wifi_sel_i); + +SCI_CLK_ADD(clk_300m, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(0), + 3, 0, 0, 0, + 1, &clk_mpll); + +SCI_CLK_ADD(clk_37m5, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(1), + 24, 0, 0, 0, + 1, &clk_mpll); + +SCI_CLK_ADD(clk_66m_d, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(2), + 8, 0, 0, 0, + 1, &clk_dpll); + +SCI_CLK_ADD(clk_51m2_w, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(23), + 18, 0, 0, 0, + 1, &clk_wpll); + +SCI_CLK_ADD(clk_40m_wf1, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(27), + 22, 0, 0, 0, + 1, &clk_wifipll); + +SCI_CLK_ADD(clk_312m, 0, REG_PMU_APB_CGM_AP_EN, BIT(7), + 2, 0, 0, 0, + 1, &clk_cpll); + +SCI_CLK_ADD(clk_208m, 0, REG_PMU_APB_CGM_AP_EN, BIT(20), + 3, 0, 0, 0, + 1, &clk_cpll); + +SCI_CLK_ADD(clk_104m, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(18), + 6, 0, 0, 0, + 1, &clk_cpll); + +SCI_CLK_ADD(clk_52m, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(19), + 12, 0, 0, 0, + 1, &clk_cpll); + +SCI_CLK_ADD(clk_384m, 0, REG_PMU_APB_CGM_AP_EN, BIT(8), + 2, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_256m, 0, REG_PMU_APB_CGM_AP_EN, BIT(9), + 3, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_192m, 0, REG_PMU_APB_CGM_AP_EN, BIT(10), + 4, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_153m6, 0, REG_PMU_APB_CGM_AP_EN, BIT(11), + 5, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_128m, 0, REG_PMU_APB_CGM_AP_EN, BIT(12), + 6, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_96m, 0, REG_PMU_APB_CGM_AP_EN, BIT(13), + 8, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_76m8, 0, REG_PMU_APB_CGM_AP_EN, BIT(14), + 10, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_64m, 0, REG_PMU_APB_CGM_AP_EN, BIT(15), + 12, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_51m2, 0, REG_PMU_APB_CGM_AP_EN, BIT(16), + 15, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_48m, 0, REG_PMU_APB_CGM_AP_EN, BIT(17), + 16, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_38m4, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(15), + 20, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_24m, 0, REG_PMU_APB_CGM_AP_EN, BIT(18), + 32, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_12m, 0, REG_PMU_APB_CGM_AP_EN, BIT(19), + 64, 0, 0, 0, + 1, &clk_tdpll); + +SCI_CLK_ADD(clk_mcu, 0, 0, 0, + REG_AP_AHB_CA7_CKG_CFG, BIT(4)|BIT(5)|BIT(6), REG_AP_AHB_CA7_CKG_CFG, BIT(0)|BIT(1)|BIT(2), + 7, &ext_26m, &clk_dpll, &clk_cpll, &clk_tdpll, &clk_wifipll, &clk_wpll, &clk_mpll); + +SCI_CLK_ADD(clk_ca7_core, 0, 0, 0, + 0, 0, 0, 0, + 1, &clk_mcu); + +SCI_CLK_ADD(clk_ca7_axi, 0, 0, 0, + REG_AP_AHB_CA7_CKG_CFG, BIT(8)|BIT(9)|BIT(10), 0, 0, + 1, &clk_mcu); + +SCI_CLK_ADD(clk_ca7_dbg, 0, REG_AP_AHB_MISC_CKG_EN, BIT(8), + REG_AP_AHB_CA7_CKG_CFG, BIT(16)|BIT(17)|BIT(18), 0, 0, + 1, &clk_mcu); + +SCI_CLK_ADD(clk_ap_ahb, 0, 0, 0, + 0, 0, REG_AP_CLK_AP_AHB_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_76m8, &clk_128m, &clk_192m); + +SCI_CLK_ADD(clk_ap_apb, 0, 0, 0, + 0, 0, REG_AP_CLK_AP_APB_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_64m, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_pub_ahb, 0, 0, 0, + 0, 0, REG_AON_CLK_PUB_AHB_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_emc, 0, 0, 0, + REG_AON_CLK_EMC_CFG, BIT(8)|BIT(9), REG_AON_CLK_EMC_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_256m, &clk_384m, &clk_dpll); + +SCI_CLK_ADD(clk_aon_apb, 0, 0, 0, + REG_AON_CLK_AON_APB_CFG, BIT(8)|BIT(9), REG_AON_CLK_AON_APB_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_76m8, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_zip_emc, 0, REG_AON_APB_APB_EB1, BIT(12), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_disp_emc, 0, REG_AON_APB_APB_EB1, BIT(11), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_gsp, 0, REG_AP_AHB_AHB_EB, BIT(3), + 0, 0, REG_AP_CLK_GSP_CFG, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_96m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_disc0, 0, REG_AP_AHB_AHB_EB, BIT(1), + REG_AP_CLK_DISPC0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_DISPC0_CFG, BIT(0), + 2, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_disc0_dbi, 0, REG_AP_AHB_AHB_EB, BIT(1), + REG_AP_CLK_DISPC0_DBI_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_DISPC0_DBI_CFG, BIT(0)|BIT(1), + 4, &clk_128m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_disc0_dpi, 0, REG_AP_AHB_AHB_EB, BIT(1), + REG_AP_CLK_DISPC0_DPI_CFG, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), REG_AP_CLK_DISPC0_DPI_CFG, BIT(0)|BIT(1), + 4, &clk_128m, &clk_153m6, &clk_192m, &clk_384m); + +SCI_CLK_ADD(clk_disc1, 0, REG_AP_AHB_AHB_EB, BIT(2), + REG_AP_CLK_DISPC1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_DISPC1_CFG, BIT(0), + 2, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_disc1_dbi, 0, REG_AP_AHB_AHB_EB, BIT(2), + REG_AP_CLK_DISPC1_DBI_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_DISPC1_DBI_CFG, BIT(0)|BIT(1), + 4, &clk_128m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_disc1_dpi, 0, REG_AP_AHB_AHB_EB, BIT(2), + REG_AP_CLK_DISPC1_DPI_CFG, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), REG_AP_CLK_DISPC1_DPI_CFG, BIT(0)|BIT(1), + 4, &clk_128m, &clk_153m6, &clk_192m, &clk_384m); + +SCI_CLK_ADD(clk_zipdec_emc, 0, REG_AP_AHB_AHB_EB, BIT(21), + 0, 0, REG_AP_CLK_ZIPENC_CFG, BIT(0)|BIT(1), + 4, &clk_96m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_zipenc_emc, 0, REG_AP_AHB_AHB_EB, BIT(20), + 0, 0, REG_AP_CLK_ZIPENC_CFG, BIT(0)|BIT(1), + 4, &clk_96m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_nandc_ecc, 0, REG_AP_AHB_AHB_EB, BIT(19), + 0, 0, REG_AP_CLK_NANDC_ECC_CFG, BIT(0), + 2, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_nfc, 0, REG_AP_AHB_AHB_EB, BIT(6), + REG_AP_CLK_NFC_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_NFC_CFG, BIT(0)|BIT(1), + 3, &clk_64m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_sdio0, 0, REG_AP_AHB_AHB_EB, BIT(8), + REG_AP_CLK_SDIO0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_SDIO0_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_256m, &clk_312m, &clk_384m); + +SCI_CLK_ADD(clk_sdio1, 0, REG_AP_AHB_AHB_EB, BIT(9), + 0, 0, REG_AP_CLK_SDIO1_CFG, BIT(0)|BIT(1), + 4, &clk_48m, &clk_76m8, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_sdio2, 0, REG_AP_AHB_AHB_EB, BIT(10), + 0, 0, REG_AP_CLK_SDIO2_CFG, BIT(0)|BIT(1), + 4, &clk_48m, &clk_76m8, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_emmc, 0, REG_AP_AHB_AHB_EB, BIT(11), + 0, 0, REG_AP_CLK_EMMC_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_256m, &clk_312m, &clk_384m); + +SCI_CLK_ADD(clk_gps_tcxo, 64000000, REG_AP_CLK_GPS_TCXO_CFG, BIT(16), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_gps, 0, REG_AP_AHB_AHB_EB, BIT(12), + 0, 0, REG_AP_CLK_GPS_CFG, BIT(0), + 2, &clk_64m, &clk_76m8); + +SCI_CLK_ADD(clk_usb_ref, 0, REG_AP_AHB_AHB_EB, BIT(4), + 0, 0, REG_AP_CLK_USB_REF_CFG, BIT(0), + 2, &clk_12m, &clk_24m); + +SCI_CLK_ADD(clk_uart0, 0, REG_AP_APB_APB_EB, BIT(13), + REG_AP_CLK_UART0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_UART0_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart1, 0, REG_AP_APB_APB_EB, BIT(14), + REG_AP_CLK_UART1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_UART1_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart2, 0, REG_AP_APB_APB_EB, BIT(15), + REG_AP_CLK_UART2_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_UART2_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart3, 0, REG_AP_APB_APB_EB, BIT(16), + REG_AP_CLK_UART3_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_UART3_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_i2c0, 0, REG_AP_APB_APB_EB, BIT(8), + REG_AP_CLK_I2C0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_I2C0_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_i2c1, 0, REG_AP_APB_APB_EB, BIT(9), + REG_AP_CLK_I2C1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_I2C1_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_i2c2, 0, REG_AP_APB_APB_EB, BIT(10), + REG_AP_CLK_I2C2_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_I2C2_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_i2c3, 0, REG_AP_APB_APB_EB, BIT(11), + REG_AP_CLK_I2C3_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_I2C3_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_spi0, 0, REG_AP_APB_APB_EB, BIT(5), + REG_AP_CLK_SPI0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_SPI0_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_spi1, 0, REG_AP_APB_APB_EB, BIT(6), + REG_AP_CLK_SPI1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_SPI1_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_spi2, 0, REG_AP_APB_APB_EB, BIT(7), + REG_AP_CLK_SPI2_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_SPI2_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_iis0, 0, REG_AP_APB_APB_EB, BIT(1), + REG_AP_CLK_IIS0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_IIS0_CFG, BIT(0)|BIT(1), + 3, &ext_26m, &clk_76m8, &clk_128m); + +SCI_CLK_ADD(clk_iis1, 0, REG_AP_APB_APB_EB, BIT(2), + REG_AP_CLK_IIS1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_IIS1_CFG, BIT(0)|BIT(1), + 3, &ext_26m, &clk_76m8, &clk_128m); + +SCI_CLK_ADD(clk_gpu_top_i, 0, REG_PMU_APB_PD_GPU_TOP_CFG+1, BIT(25), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_gpu_i, 0, REG_AON_APB_APB_EB0, BIT(27), + 0, 0, 0, 0, + 1, &clk_gpu_top_i); + +SCI_CLK_ADD(clk_gpu, 0, &clk_gpu_i, 0, + REG_GPU_APB_APB_CLK_CTRL, BIT(2)|BIT(3), REG_GPU_APB_APB_CLK_CTRL, BIT(0)|BIT(1), + 4, &clk_208m, &clk_256m, &clk_300m, &clk_312m); + +SCI_CLK_ADD(clk_mm_top_i, 0, REG_PMU_APB_PD_MM_TOP_CFG+1, BIT(25), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_mm_i, 0, REG_AON_APB_APB_EB0, BIT(25), + 0, 0, 0, 0, + 1, &clk_mm_top_i); + +SCI_CLK_ADD(clk_mm_ahb, 0, 0, 0, + 0, 0, REG_MM_CLK_MM_AHB_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_mm_mtx_axi, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(8), + 0, 0, 0, 0, + 1, &clk_mm_i); + +SCI_CLK_ADD(clk_mm_axi, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(7), + 0, 0, 0, 0, + 1, &clk_mm_mtx_axi); + +SCI_CLK_ADD(clk_mmu, 0, REG_MM_AHB_AHB_EB, BIT(7), + 0, 0, 0, 0, + 1, &clk_mm_ahb); +SCI_CLK_ADD(clk_mm_ckg_i, 0, REG_MM_AHB_AHB_EB, BIT(6), + 0, 0, 0, 0, + 1, &clk_mm_i); + +SCI_CLK_ADD(clk_jpg_i, 0, REG_MM_AHB_AHB_EB, BIT(5), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_jpg_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(6), + 0, 0, 0, 0, + 1, &clk_jpg_i); + +SCI_CLK_ADD(clk_jpg, 0, &clk_jpg_ckg_i, 0, + 0, 0, REG_MM_CLK_JPG_CFG, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_vsp_i, 0, REG_MM_AHB_AHB_EB, BIT(3), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_vsp_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(5), + 0, 0, 0, 0, + 1, &clk_vsp_i); + +SCI_CLK_ADD(clk_vsp, 0, &clk_vsp_ckg_i, 0, + 0, 0, REG_MM_CLK_VSP_CFG, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_sensor_i, 0, REG_MM_AHB_AHB_EB, BIT(1), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_sensor_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(2), + 0, 0, 0, 0, + 1, &clk_sensor_i); + +SCI_CLK_ADD(clk_sensor, 0, &clk_sensor_ckg_i, 0, + REG_MM_CLK_SENSOR_CFG, BIT(8)|BIT(9)|BIT(10), REG_MM_CLK_SENSOR_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_76m8, &clk_96m); + +SCI_CLK_ADD(clk_ccir_in, 64000000, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_ccir_i, 0, REG_MM_AHB_AHB_EB, BIT(1), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_ccir, 0, &clk_ccir_i, 0, + 0, 0, REG_MM_CLK_CCIR_CFG, BIT(16), + 2, &clk_24m, &clk_ccir_in); + +SCI_CLK_ADD(clk_dcam_i, 0, REG_MM_AHB_AHB_EB, BIT(0), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_dcam_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(3), + 0, 0, 0, 0, + 1, &clk_dcam_i); + +SCI_CLK_ADD(clk_dcam, 0, &clk_dcam_ckg_i, 0, + 0, 0, REG_MM_CLK_DCAM_CFG, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_csi_i, 0, REG_MM_AHB_AHB_EB, BIT(4), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_csi_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(1), + 0, 0, 0, 0, + 1, &clk_csi_i); + +SCI_CLK_ADD(clk_cphy_cfg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(0), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_dcam_mipi, 0, &clk_cphy_cfg_i, 0, + 0, 0, 0, 0, + 1, &clk_csi_ckg_i); + +SCI_CLK_ADD(clk_aud, 0, REG_AON_APB_APB_EB0, BIT(18), + 0, 0, 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_audif, 0, REG_AON_APB_APB_EB0, BIT(17), + 0, 0, REG_AON_CLK_AUDIF_CFG, BIT(0)|BIT(1), + 3, &ext_26m, &clk_38m4, &clk_51m2); + +SCI_CLK_ADD(clk_vbc, 0, REG_AON_APB_APB_EB0, BIT(19), + 0, 0, 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_fm_in, 64000000, REG_AON_CLK_FM_CFG, BIT(16), + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_fm, 0, REG_AON_APB_APB_EB0, BIT(1), + 0, 0, 0, 0, + 1, &clk_fm_in); + +SCI_CLK_ADD(clk_adi, 0, REG_AON_APB_APB_EB0, BIT(16), + 0, 0, REG_AON_CLK_ADI_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_38m4, &clk_51m2, &clk_64m); + +SCI_CLK_ADD(clk_aux0, 0, REG_AON_APB_APB_EB1, BIT(2), + REG_AON_APB_AON_CGM_CFG, BIT(16)|BIT(17)|BIT(18)|BIT(19), REG_AON_APB_AON_CGM_CFG, BIT(0)|BIT(1)|BIT(2)|BIT(3), + 9, &ext_32k, &ext_26m, &ext_26m, &clk_48m, &clk_52m, &clk_51m2_w, &clk_37m5, &clk_40m_wf1, &clk_66m_d); + +SCI_CLK_ADD(clk_aux1, 0, REG_AON_APB_APB_EB1, BIT(3), + REG_AON_APB_AON_CGM_CFG, BIT(20)|BIT(21)|BIT(22)|BIT(23), REG_AON_APB_AON_CGM_CFG, BIT(4)|BIT(5)|BIT(6)|BIT(7), + 9, &ext_32k, &ext_26m, &ext_26m, &clk_48m, &clk_52m, &clk_51m2_w, &clk_37m5, &clk_40m_wf1, &clk_66m_d); + +SCI_CLK_ADD(clk_aux2, 0, REG_AON_APB_APB_EB1, BIT(4), + REG_AON_APB_AON_CGM_CFG, BIT(24)|BIT(25)|BIT(26)|BIT(27), REG_AON_APB_AON_CGM_CFG, BIT(8)|BIT(9)|BIT(10)|BIT(11), + 9, &ext_32k, &ext_26m, &ext_26m, &clk_48m, &clk_52m, &clk_51m2_w, &clk_37m5, &clk_40m_wf1, &clk_66m_d); + +SCI_CLK_ADD(clk_pwm0, 0, REG_AON_APB_APB_EB0, BIT(4), + 0, 0, REG_AON_CLK_PWM0_CFG, BIT(0), + 2, &ext_32k, &ext_26m); + +SCI_CLK_ADD(clk_pwm1, 0, REG_AON_APB_APB_EB0, BIT(5), + 0, 0, REG_AON_CLK_PWM1_CFG, BIT(0), + 2, &ext_32k, &ext_26m); + +SCI_CLK_ADD(clk_pwm2, 0, REG_AON_APB_APB_EB0, BIT(6), + 0, 0, REG_AON_CLK_PWM2_CFG, BIT(0), + 2, &ext_32k, &ext_26m); + +SCI_CLK_ADD(clk_pwm3, 0, REG_AON_APB_APB_EB0, BIT(7), + 0, 0, REG_AON_CLK_PWM3_CFG, BIT(0), + 2, &ext_32k, &ext_26m); + +SCI_CLK_ADD(clk_efuse, 0, REG_AON_APB_APB_EB0, BIT(13), + 0, 0, 0, 0, + 1, &ext_26m); + +SCI_CLK_ADD(clk_ca7_dap, 0, REG_AON_APB_APB_EB0, BIT(30), + 0, 0, REG_AON_CLK_CA7_DAP_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_76m8, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_ca7_ts, 0, REG_AON_APB_APB_EB0, BIT(28), + 0, 0, REG_AON_CLK_CA7_TS_CFG, BIT(0)|BIT(1), + 4, &ext_32k, &ext_26m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_mspi, 0, REG_AON_APB_APB_EB0, BIT(23), + 0, 0, REG_AON_CLK_MSPI_CFG, BIT(0)|BIT(1), + 3, &clk_52m, &clk_76m8, &clk_96m); + +SCI_CLK_ADD(clk_i2c, 0, REG_AON_APB_APB_EB0, BIT(31), + 0, 0, REG_AON_CLK_I2C_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_avs0, 0, REG_AON_APB_APB_EB0, BIT(6), + 0, 0, REG_AON_CLK_AVS0_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_avs1, 0, REG_AON_APB_APB_EB0, BIT(7), + 0, 0, REG_AON_CLK_AVS1_CFG, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_ada_apb_rf.h b/include/soc/sprd/chip_x35lt8/__regs_ada_apb_rf.h new file mode 100644 index 00000000..57cf1dae --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_ada_apb_rf.h @@ -0,0 +1,179 @@ +/* the head file modifier: g 2015-03-19 15:44:42*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_ADA_APB_RF_HEADFILE_H__ +#define __H_REGS_ADA_APB_RF_HEADFILE_H__ __FILE__ + +#define REGS_ADA_APB_RF + +/* registers definitions for ADA_APB_RF */ +#define REG_ADA_APB_RF_APB_DAC_CTR0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0000)/*DAC control0*/ +#define REG_ADA_APB_RF_APB_DAC_CTR1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0004)/*DAC control1*/ +#define REG_ADA_APB_RF_APB_DAC_CTR2 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0008)/*DAC control2*/ +#define REG_ADA_APB_RF_APB_DAC_CTR3 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x000C)/*DAC control3*/ +#define REG_ADA_APB_RF_APB_DAC_CTR4 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0010)/*DAC control4*/ +#define REG_ADA_APB_RF_APB_DAC_STS0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0014)/*DAC status0*/ +#define REG_ADA_APB_RF_APB_DAC_STS1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0018)/*DAC status1*/ +#define REG_ADA_APB_RF_APB_ADC0_CTR0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x001C)/*ADC 0 control0*/ +#define REG_ADA_APB_RF_APB_ADC0_CTR1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0020)/*ADC 0 control1*/ +#define REG_ADA_APB_RF_APB_ADC0_CTR2 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0024)/*ADC 0 control2 for mode 0*/ +#define REG_ADA_APB_RF_APB_ADC0_CTR3 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0028)/*ADC 0 control3 for mode 1*/ +#define REG_ADA_APB_RF_APB_CAL_CTR0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0030)/*Calibration Control 0*/ +#define REG_ADA_APB_RF_APB_CAL_CTR1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0034)/*Calibration Control 1*/ +#define REG_ADA_APB_RF_APB_CAL_CTR3 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x003C)/*Calibration Control 3*/ +#define REG_ADA_APB_RF_APB_CAL_STS0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0044)/*Calibration Status 0*/ +#define REG_ADA_APB_RF_APB_CAL_STS1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0048)/*Calibration Status 1*/ +#define REG_ADA_APB_RF_APB_ADA_CTRL0 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0054)/*ADA control 0*/ +#define REG_ADA_APB_RF_APB_ADA_CTRL1 SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0058)/*ADA control 1*/ +#define REG_ADA_APB_RF_APB_RX_GSM_DFT SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x005C)/*GSM RX default*/ +#define REG_ADA_APB_RF_APB_RX_3G_DFT SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0060)/*3G RX default*/ + + + +/* bits definitions for register REG_ADA_APB_RF_APB_DAC_CTR0 */ +#define BITS_DAC_PCTRL_1(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BIT_DAC_OUT_SEL_1 ( BIT(17) ) +#define BIT_DAC_CLK_SEL_1 ( BIT(16) ) +#define BITS_DAC_PCTRL_0(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_DAC_OUT_SEL_0 ( BIT(1) ) +#define BIT_DAC_CLK_SEL_0 ( BIT(0) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_DAC_CTR1 */ +#define BITS_DAC_WD_OVR(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DAC_WADDR_OVR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DAC_WLE_OVR ( BIT(2) ) +#define BIT_DAC_W_OVR_I_QN ( BIT(1) ) +#define BIT_DAC_W_OVR_EN ( BIT(0) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_DAC_CTR2 */ +#define BITS_DAC_RSV(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BIT_DAC_IQ_OUT_MSB_INV ( BIT(21) ) +#define BIT_DAC_IQ_IN_MSB_INV ( BIT(20) ) +#define BIT_DAC_OVR_EN_CAL ( BIT(19) ) +#define BIT_DAC_EN_OOSCAL ( BIT(18) ) +#define BIT_DAC_IQ_SWAP ( BIT(17) ) +#define BIT_DAC_CAL_START ( BIT(16) ) +#define BITS_DAC_OFFSETI(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DAC_OFFSETQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_DAC_CTR3 */ +#define BITS_DAC_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_DAC_CTR4 */ +#define BITS_DAC_I_CAL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC_Q_CAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_DAC_STS0 */ +#define BITS_DAC_WTI(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DAC_WTQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_DAC_STS1 */ +#define BITS_DAC_DA_STATE(_X_) ( (_X_) << 17 & (BIT(17)|BIT(18)) ) +#define BIT_DAC_DONE ( BIT(16) ) +#define BITS_DAC_WQ_OVR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_ADC0_CTR0 */ +#define BITS_ADC0_CALRDOUT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BIT_ADC0_CAL_SOFT_RST ( BIT(10) ) +#define BIT_ADC0_CALRD ( BIT(9) ) +#define BIT_ADC0_CALEN ( BIT(8) ) +#define BITS_ADC0_CALADDR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_ADC0_CTR1 */ +#define BITS_ADC0_DLL_OUT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_ADC0_DLLOOF(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)) ) +#define BIT_ADC0_IQ_SWAP ( BIT(14) ) +#define BITS_ADC0_DLLIN(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_ADC0_IQ_OUT_MSB_INV ( BIT(7) ) +#define BIT_ADC0_IQ_IN_MSB_INV ( BIT(6) ) +#define BIT_ADC0_DLL_SOFT_RST ( BIT(4) ) +#define BIT_ADC0_DLLWR ( BIT(3) ) +#define BIT_ADC0_DLLRD ( BIT(2) ) +#define BIT_ADC0_DLLEN ( BIT(1) ) +#define BIT_ADC0_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_ADC0_CTR2 */ +#define BITS_ADC0_RSV_0(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ADC0_DIG_CLK_SEL_0 ( BIT(11) ) +#define BIT_ADC0_VCM_SEL_0 ( BIT(10) ) +#define BITS_ADC0_DELAY_CAP_0(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ADC0_BIT_SEL_0(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_ADC0_VREF_SEL_0(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_ADC0_VREF_BOOST_0(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_ADC0_QUANT_BOOST_0(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_ADC0_CTR3 */ +#define BITS_ADC0_RSV_1(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ADC0_DIG_CLK_SEL_1 ( BIT(11) ) +#define BIT_ADC0_VCM_SEL_1 ( BIT(10) ) +#define BITS_ADC0_DELAY_CAP_1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ADC0_BIT_SEL_1(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_ADC0_VREF_SEL_1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_ADC0_VREF_BOOST_1(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_ADC0_QUANT_BOOST_1(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_CAL_CTR0 */ +#define BIT_LDO_EN_AUTO_EN ( BIT(27) ) +#define BIT_LDO_EN_FRC ( BIT(26) ) +#define BIT_BG_EN_AUTO_EN ( BIT(25) ) +#define BIT_BG_EN_FRC ( BIT(24) ) +#define BITS_ADC_CLK_CAL_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_ADA_CAL_WAIT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_CLK_ADA_CAL_EN ( BIT(6) ) +#define BIT_DAC_PD_CAL ( BIT(5) ) +#define BIT_ADC0_EN_CAL ( BIT(3) ) +#define BIT_ADC0_CAL ( BIT(1) ) +#define BIT_ADA_MODE_SEL ( BIT(0) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_CAL_CTR1 */ +#define BITS_ADC0_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) ) +#define BITS_ADC0_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_CAL_CTR3 */ +#define BIT_ADA0_CAL_START ( BIT(0) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_CAL_STS0 */ +#define BIT_ADA0_CAL_DONE ( BIT(31) ) +#define BITS_ADC0_I_CAL_RESULT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_CAL_STS1 */ +#define BITS_ADC0_Q_CAL_RESULT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_ADA_CTRL0 */ +#define BITS_ADA_AUTO_CTRL(_X_) (_X_) + +/* bits definitions for register REG_ADA_APB_RF_APB_ADA_CTRL1 */ +#define BITS_ADA_FRC_CTRL(_X_) (_X_) + +/* bits definitions for register REG_ADA_APB_RF_APB_RX_GSM_DFT */ +#define BITS_RX_GSM_DFT_Q(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) ) +#define BITS_RX_GSM_DFT_I(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) + +/* bits definitions for register REG_ADA_APB_RF_APB_RX_3G_DFT */ +#define BITS_RX_3G_DFT_Q(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) ) +#define BITS_RX_3G_DFT_I(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_ana_glb.h b/include/soc/sprd/chip_x35lt8/__regs_ana_glb.h new file mode 100644 index 00000000..97d72f38 --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_ana_glb.h @@ -0,0 +1,836 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __ANA_REGS_GLB_H__ +#define __ANA_REGS_GLB_H__ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, include <mach/sci_glb_regs.h>" +#endif + +#define ANA_REGS_GLB + +/* registers definitions for controller ANA_REGS_GLB */ +#define ANA_REG_GLB_ARM_MODULE_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0000) +#define ANA_REG_GLB_ARM_CLK_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0004) +#define ANA_REG_GLB_RTC_CLK_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0008) +#define ANA_REG_GLB_ARM_RST SCI_ADDR(ANA_REGS_GLB_BASE, 0x000C) +#define ANA_REG_GLB_LDO_DCDC_PD_RTCSET SCI_ADDR(ANA_REGS_GLB_BASE, 0x0010) +#define ANA_REG_GLB_LDO_DCDC_PD_RTCCLR SCI_ADDR(ANA_REGS_GLB_BASE, 0x0014) +#define ANA_REG_GLB_RTC_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0018) +#define ANA_REG_GLB_LDO_PD_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x001C) +#define ANA_REG_GLB_LDO_V_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0020) +#define ANA_REG_GLB_LDO_V_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0024) +#define ANA_REG_GLB_LDO_V_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0028) +#define ANA_REG_GLB_LDO_CAL_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x002C) +#define ANA_REG_GLB_LDO_CAL_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0030) +#define ANA_REG_GLB_LDO_CAL_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0034) +#define ANA_REG_GLB_LDO_CAL_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0038) +#define ANA_REG_GLB_LDO_CAL_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x003C) +#define ANA_REG_GLB_LDO_CAL_CTRL5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0040) +#define ANA_REG_GLB_LDO_CAL_CTRL6 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0044) +#define ANA_REG_GLB_AUXAD_CTL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0048) +#define ANA_REG_GLB_DCDC_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x004C) +#define ANA_REG_GLB_DCDC_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0050) +#define ANA_REG_GLB_DCDC_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0054) +#define ANA_REG_GLB_DCDC_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0058) +#define ANA_REG_GLB_DCDC_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x005C) +#define ANA_REG_GLB_DCDC_CTRL5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0060) +#define ANA_REG_GLB_DCDC_CTRL6 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0064) +#define ANA_REG_GLB_DDR2_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0068) +#define ANA_REG_GLB_SLP_WAIT_DCDCARM SCI_ADDR(ANA_REGS_GLB_BASE, 0x006C) +#define ANA_REG_GLB_LDO1828_XTL_CTL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0070) +#define ANA_REG_GLB_LDO_SLP_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0074) +#define ANA_REG_GLB_LDO_SLP_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0078) +#define ANA_REG_GLB_LDO_SLP_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x007C) +#define ANA_REG_GLB_LDO_SLP_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0080) +#define ANA_REG_GLB_AUD_SLP_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0084) +#define ANA_REG_GLB_DCDC_SLP_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0088) +#define ANA_REG_GLB_XTL_WAIT_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x008C) +#define ANA_REG_GLB_FLASH_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0090) +#define ANA_REG_GLB_WHTLED_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0094) +#define ANA_REG_GLB_WHTLED_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0098) +#define ANA_REG_GLB_WHTLED_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x009C) +#define ANA_REG_GLB_ANA_DRV_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A0) +#define ANA_REG_GLB_VIBR_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A4) +#define ANA_REG_GLB_VIBR_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A8) +#define ANA_REG_GLB_VIBR_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00AC) +#define ANA_REG_GLB_VIBR_WR_PROT_VALUE SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B0) +#define ANA_REG_GLB_AUDIO_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B4) +#define ANA_REG_GLB_CHGR_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B8) +#define ANA_REG_GLB_CHGR_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00BC) +#define ANA_REG_GLB_CHGR_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C0) +#define ANA_REG_GLB_CHGR_STATUS SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C4) +#define ANA_REG_GLB_ANA_MIXED_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C8) +#define ANA_REG_GLB_PWR_XTL_EN0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00CC) +#define ANA_REG_GLB_PWR_XTL_EN1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D0) +#define ANA_REG_GLB_PWR_XTL_EN2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D4) +#define ANA_REG_GLB_PWR_XTL_EN3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D8) +#define ANA_REG_GLB_PWR_XTL_EN4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00DC) +#define ANA_REG_GLB_PWR_XTL_EN5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E0) +#define ANA_REG_GLB_ANA_STATUS SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E4) +#define ANA_REG_GLB_POR_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E8) +#define ANA_REG_GLB_WDG_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x00EC) +#define ANA_REG_GLB_POR_PIN_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F0) +#define ANA_REG_GLB_POR_SRC_FLAG SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F4) +#define ANA_REG_GLB_POR_7S_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F8) +#define ANA_REG_GLB_INT_DEBUG SCI_ADDR(ANA_REGS_GLB_BASE, 0x00FC) +#define ANA_REG_GLB_GPI_DEBUG SCI_ADDR(ANA_REGS_GLB_BASE, 0x0100) +#define ANA_REG_GLB_HWRST_RTC SCI_ADDR(ANA_REGS_GLB_BASE, 0x0104) +#define ANA_REG_GLB_CHIP_ID_LOW SCI_ADDR(ANA_REGS_GLB_BASE, 0x0108) +#define ANA_REG_GLB_CHIP_ID_HIGH SCI_ADDR(ANA_REGS_GLB_BASE, 0x010C) +#define ANA_REG_GLB_ARM_MF_REG SCI_ADDR(ANA_REGS_GLB_BASE, 0x0110) +#define ANA_REG_GLB_AFUSE_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0114) +#define ANA_REG_GLB_AFUSE_OUT0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0118) +#define ANA_REG_GLB_AFUSE_OUT1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x011C) +#define ANA_REG_GLB_AFUSE_OUT2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0120) +#define ANA_REG_GLB_AFUSE_OUT3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0124) +#define ANA_REG_GLB_ARCH_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0128) +#define ANA_REG_GLB_MCU_WR_PROT_VALUE SCI_ADDR(ANA_REGS_GLB_BASE, 0x012C) +#define ANA_REG_GLB_MP_MISC_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0148) +#define ANA_REG_GLB_DCDC_CORE_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0160) +#define ANA_REG_GLB_DCDC_ARM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0164) +#define ANA_REG_GLB_DCDC_MEM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0168) +#define ANA_REG_GLB_DCDC_GEN_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x016C) +#define ANA_REG_GLB_DCDC_WRF_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0170) +#define ANA_REG_GLB_DCDC_WPA_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0174) +#define ANA_REG_GLB_DCDC_WPA_DCM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x017C) +#define ANA_REG_GLB_LDO_CAL_SEL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0044) + +/* bits definitions for register ANA_REG_GLB_ARM_MODULE_EN */ +#define BIT_ANA_THM_EN ( BIT(12) ) +#define BIT_ANA_BLTC_EN ( BIT(10) ) +#define BIT_ANA_PINREG_EN ( BIT(9) ) +#define BIT_ANA_FGU_EN ( BIT(8) ) +#define BIT_ANA_GPIO_EN ( BIT(7) ) +#define BIT_ANA_ADC_EN ( BIT(6) ) +#define BIT_ANA_HDT_EN ( BIT(5) ) +#define BIT_ANA_AUD_EN ( BIT(4) ) +#define BIT_ANA_EIC_EN ( BIT(3) ) +#define BIT_ANA_WDG_EN ( BIT(2) ) +#define BIT_ANA_RTC_EN ( BIT(1) ) + +/* bits definitions for register ANA_REG_GLB_ARM_CLK_EN */ +#define BIT_CLK_AUXAD_EN ( BIT(9) ) +#define BIT_CLK_AUXADC_EN ( BIT(8) ) +#define BIT_CLK_AUD_HID_EN ( BIT(5) ) +#define BIT_CLK_AUD_HBD_EN ( BIT(4) ) +#define BIT_CLK_AUD_LOOP_EN ( BIT(3) ) +#define BIT_CLK_AUD_6P5M_EN ( BIT(2) ) +#define BIT_CLK_AUDIF_EN ( BIT(1) ) + +/* bits definitions for register ANA_REG_GLB_RTC_CLK_EN */ +#define BIT_RTC_FLASH_EN ( BIT(13) ) +#define BIT_RTC_THMA_AUTO_EN ( BIT(12) ) +#define BIT_RTC_THMA_EN ( BIT(11) ) +#define BIT_RTC_THM_EN ( BIT(10) ) +#define BIT_RTC_BLTC_EN ( BIT(8) ) +#define BIT_RTC_FGU_EN ( BIT(7) ) +#define BIT_RTC_FGUA_EN ( BIT(6) ) +#define BIT_RTC_VIBR_EN ( BIT(5) ) +#define BIT_RTC_AUD_EN ( BIT(4) ) +#define BIT_RTC_EIC_EN ( BIT(3) ) +#define BIT_RTC_WDG_EN ( BIT(2) ) +#define BIT_RTC_RTC_EN ( BIT(1) ) +#define BIT_RTC_ARCH_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_ARM_RST */ +#define BIT_ANA_THMA_SOFT_RST ( BIT(14) ) +#define BIT_ANA_THM_SOFT_RST ( BIT(13) ) +#define BIT_ANA_AUD_32K_SOFT_RST ( BIT(12) ) +#define BIT_ANA_AUDTX_SOFT_RST ( BIT(11) ) +#define BIT_ANA_AUDRX_SOFT_RST ( BIT(10) ) +#define BIT_ANA_AUD_SOFT_RST ( BIT(9) ) +#define BIT_ANA_AUD_HDT_SOFT_RST ( BIT(8) ) +#define BIT_ANA_GPIO_SOFT_RST ( BIT(7) ) +#define BIT_ANA_ADC_SOFT_RST ( BIT(6) ) +#define BIT_ANA_PWM0_SOFT_RST ( BIT(5) ) +#define BIT_ANA_FGU_SOFT_RST ( BIT(4) ) +#define BIT_ANA_EIC_SOFT_RST ( BIT(3) ) +#define BIT_ANA_WDG_SOFT_RST ( BIT(2) ) +#define BIT_ANA_RTC_SOFT_RST ( BIT(1) ) +#define BIT_ANA_BLTC_SOFT_RST ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_DCDC_PD_RTCSET */ +#define BIT_DCDC_OTP_PD_RTCSET ( BIT(14) ) +#define BIT_DCDC_WRF_PD_RTCSET ( BIT(13) ) +#define BIT_DCDC_GEN_PD_RTCSET ( BIT(12) ) +#define BIT_DCDC_MEM_PD_RTCSET ( BIT(11) ) +#define BIT_DCDC_ARM_PD_RTCSET ( BIT(10) ) +#define BIT_DCDC_CORE_PD_RTCSET ( BIT(9) ) +#define BIT_LDO_EMMCCORE_PD_RTCSET ( BIT(8) ) +#define BIT_LDO_EMMCIO_PD_RTCSET ( BIT(7) ) +#define BIT_LDO_RF2_PD_RTCSET ( BIT(6) ) +#define BIT_LDO_RF1_PD_RTCSET ( BIT(5) ) +#define BIT_LDO_RF0_PD_RTCSET ( BIT(4) ) +#define BIT_LDO_VDD25_PD_RTCSET ( BIT(3) ) +#define BIT_LDO_VDD28_PD_RTCSET ( BIT(2) ) +#define BIT_LDO_VDD18_PD_RTCSET ( BIT(1) ) +#define BIT_BG_PD_RTCSET ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_DCDC_PD_RTCCLR */ +#define BIT_DCDC_OTP_PD_RTCCLR ( BIT(14) ) +#define BIT_DCDC_WRF_PD_RTCCLR ( BIT(13) ) +#define BIT_DCDC_GEN_PD_RTCCLR ( BIT(12) ) +#define BIT_DCDC_MEM_PD_RTCCLR ( BIT(11) ) +#define BIT_DCDC_ARM_PD_RTCCLR ( BIT(10) ) +#define BIT_DCDC_CORE_PD_RTCCLR ( BIT(9) ) +#define BIT_LDO_EMMCCORE_PD_RTCCLR ( BIT(8) ) +#define BIT_LDO_EMMCIO_PD_RTCCLR ( BIT(7) ) +#define BIT_LDO_RF2_PD_RTCCLR ( BIT(6) ) +#define BIT_LDO_RF1_PD_RTCCLR ( BIT(5) ) +#define BIT_LDO_RF0_PD_RTCCLR ( BIT(4) ) +#define BIT_LDO_VDD25_PD_RTCCLR ( BIT(3) ) +#define BIT_LDO_VDD28_PD_RTCCLR ( BIT(2) ) +#define BIT_LDO_VDD18_PD_RTCCLR ( BIT(1) ) +#define BIT_BG_PD_RTCCLR ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_RTC_CTRL */ +#define BITS_XOSC32K_CTL_STS(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BIT_XOSC32K_CTL_B3_RTCCLR ( BIT(7) ) +#define BIT_XOSC32K_CTL_B2_RTCCLR ( BIT(6) ) +#define BIT_XOSC32K_CTL_B1_RTCCLR ( BIT(5) ) +#define BIT_XOSC32K_CTL_B0_RTCCLR ( BIT(4) ) +#define BIT_XOSC32K_CTL_B3_RTCSET ( BIT(3) ) +#define BIT_XOSC32K_CTL_B2_RTCSET ( BIT(2) ) +#define BIT_XOSC32K_CTL_B1_RTCSET ( BIT(1) ) +#define BIT_XOSC32K_CTL_B0_RTCSET ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_PD_CTRL */ +#define BIT_LDO_LPREF_PD_SW ( BIT(12) ) +#define BIT_DCDC_WPA_PD ( BIT(11) ) +#define BIT_LDO_CLSG_PD ( BIT(10) ) +#define BIT_LDO_USB_PD ( BIT(9) ) +#define BIT_LDO_CAMMOT_PD ( BIT(8) ) +#define BIT_LDO_CAMIO_PD ( BIT(7) ) +#define BIT_LDO_CAMD_PD ( BIT(6) ) +#define BIT_LDO_CAMA_PD ( BIT(5) ) +#define BIT_LDO_SIM2_PD ( BIT(4) ) +#define BIT_LDO_SIM1_PD ( BIT(3) ) +#define BIT_LDO_SIM0_PD ( BIT(2) ) +#define BIT_LDO_SD_PD ( BIT(1) ) +#define BIT_LDO_AVDD18_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL0 */ +#define BITS_LDO_EMMCCORE_V(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_LDO_EMMCIO_V(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_LDO_RF2_V(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_LDO_RF1_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_LDO_RF0_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_LDO_VDD25_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_LDO_VDD28_V(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_LDO_VDD18_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL1 */ +#define BITS_LDO_SIM2_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_LDO_SIM1_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_LDO_SIM0_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_LDO_SD_V(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_LDO_AVDD18_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL2 */ +#define BITS_VBATBK_RES(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_VBATBK_V(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_LDO_CLSG_V(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_LDO_USB_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_LDO_CAMMOT_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_LDO_CAMIO_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_LDO_CAMD_V(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_LDO_CAMA_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL0 */ +#define BITS_LDO_VDD25_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_VDD28_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_VDD18_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL1 */ +#define BITS_LDO_RF2_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_RF1_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_RF0_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL2 */ +#define BITS_LDO_USB_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_EMMCCORE_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_EMMCIO_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL3 */ +#define BITS_LDO_SD_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_AVDD18_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL4 */ +#define BITS_LDO_CAMA_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_SIM2_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_SIM_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL5 */ +#define BITS_LDO_CAMMOT_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_CAMIO_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDO_CAMD_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL6 */ +#define BITS_LDOA_CAL_SEL(_x_) ( (_x_) << 11 & (BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_LDOD_CAL_SEL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_LDODCDC_CAL_SEL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_LDO_CLSG_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_AUXAD_CTL */ +#define BIT_AUXAD_CURRENTSEN_EN ( BIT(6) ) +#define BIT_AUXAD_CURRENTSEL ( BIT(5) ) +#define BITS_AUXAD_CURRENT_IBS(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL0 */ +#define BIT_DCDC_CORE_LP_EN ( BIT(15) ) +#define BIT_DCDC_CORE_CL_CTRL ( BIT(14) ) +#define BITS_DCDC_CORE_PDRSLOW(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_DCDC_CORE_PFM ( BIT(9) ) +#define BIT_DCDC_CORE_DCM ( BIT(8) ) +#define BIT_DCDC_ARM_LP_EN ( BIT(7) ) +#define BIT_DCDC_ARM_CL_CTRL ( BIT(6) ) +#define BITS_DCDC_ARM_PDRSLOW(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) +#define BIT_DCDC_ARM_PFM ( BIT(1) ) +#define BIT_DCDC_ARM_DCM ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL1 */ +#define BIT_DCDC_MEM_LP_EN ( BIT(15) ) +#define BIT_DCDC_MEM_CL_CTRL ( BIT(14) ) +#define BITS_DCDC_MEM_PDRSLOW(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_DCDC_MEM_PFM ( BIT(9) ) +#define BIT_DCDC_MEM_DCM ( BIT(8) ) +#define BIT_DCDC_GEN_LP_EN ( BIT(7) ) +#define BIT_DCDC_GEN_CL_CTRL ( BIT(6) ) +#define BITS_DCDC_GEN_PDRSLOW(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) +#define BIT_DCDC_GEN_PFM ( BIT(1) ) +#define BIT_DCDC_GEN_DCM ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL2 */ +#define BIT_DCDC_BG_LP_EN ( BIT(15) ) +#define BIT_DCDC_OTP_CHIP_PD_FLAG_CLR ( BIT(14) ) +#define BIT_DCDC_OTP_CHIP_PD_FLAG ( BIT(13) ) +#define BIT_DCDC_OTP_AUTO_PD_EN ( BIT(12) ) +#define BIT_DCDC_OTP_VBEOP ( BIT(11) ) +#define BITS_DCDC_OTP_S(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BIT_DCDC_WRF_LP_EN ( BIT(7) ) +#define BIT_DCDC_WRF_CL_CTRL ( BIT(6) ) +#define BITS_DCDC_WRF_PDRSLOW(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) +#define BIT_DCDC_WRF_PFM ( BIT(1) ) +#define BIT_DCDC_WRF_DCM ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL3 */ +#define BIT_DCDC_WPA_LP_EN ( BIT(8) ) +#define BIT_DCDC_WPA_CL_CTRL ( BIT(7) ) +#define BIT_DCDC_WPA_ZXOP ( BIT(6) ) +#define BITS_DCDC_WPA_PDRSLOW(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) +#define BIT_DCDC_WPA_PFM ( BIT(1) ) +#define BIT_DCDC_WPA_APTEN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL4 */ +#define BIT_DCDC_CORE_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_CORE_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_CORE_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_CORE_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_ARM_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_ARM_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_ARM_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_ARM_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL5 */ +#define BIT_DCDC_MEM_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_MEM_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_MEM_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_MEM_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_GEN_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_GEN_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_GEN_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_GEN_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL6 */ +#define BIT_DCDC_WPA_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_WPA_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_WPA_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_WPA_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_WRF_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_WRF_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_WRF_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_WRF_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DDR2_CTRL */ +#define BIT_DDR2_BUF_PD_HW ( BIT(9) ) +#define BITS_DDR2_BUF_S_DS(_x_) ( (_x_) << 7 & (BIT(7)|BIT(8)) ) +#define BITS_DDR2_BUF_CHNS_DS(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)) ) +#define BIT_DDR2_BUF_PD ( BIT(4) ) +#define BITS_DDR2_BUF_S(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DDR2_BUF_CHNS(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_SLP_WAIT_DCDCARM */ +#define BITS_SLP_IN_WAIT_DCDCARM(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_SLP_OUT_WAIT_DCDCARM(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO1828_XTL_CTL */ +#define BIT_LDO_VDD18_EXT_XTL2_EN ( BIT(11) ) +#define BIT_LDO_VDD18_EXT_XTL1_EN ( BIT(10) ) +#define BIT_LDO_VDD18_EXT_XTL0_EN ( BIT(9) ) +#define BIT_LDO_VDD18_XTL2_EN ( BIT(8) ) +#define BIT_LDO_VDD18_XTL1_EN ( BIT(7) ) +#define BIT_LDO_VDD18_XTL0_EN ( BIT(6) ) +#define BIT_LDO_VDD28_EXT_XTL2_EN ( BIT(5) ) +#define BIT_LDO_VDD28_EXT_XTL1_EN ( BIT(4) ) +#define BIT_LDO_VDD28_EXT_XTL0_EN ( BIT(3) ) +#define BIT_LDO_VDD28_XTL2_EN ( BIT(2) ) +#define BIT_LDO_VDD28_XTL1_EN ( BIT(1) ) +#define BIT_LDO_VDD28_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SLP_CTRL0 */ +#define BIT_SLP_IO_EN ( BIT(15) ) +#define BIT_SLP_DCDC_OTP_PD_EN ( BIT(13) ) +#define BIT_SLP_DCDCGEN_PD_EN ( BIT(12) ) +#define BIT_SLP_DCDCWPA_PD_EN ( BIT(11) ) +#define BIT_SLP_DCDCWRF_PD_EN ( BIT(10) ) +#define BIT_SLP_DCDCARM_PD_EN ( BIT(9) ) +#define BIT_SLP_LDOEMMCCORE_PD_EN ( BIT(7) ) +#define BIT_SLP_LDOEMMCIO_PD_EN ( BIT(6) ) +#define BIT_SLP_LDORF2_PD_EN ( BIT(5) ) +#define BIT_SLP_LDORF1_PD_EN ( BIT(4) ) +#define BIT_SLP_LDORF0_PD_EN ( BIT(3) ) +#define BIT_SLP_LDOVDD25_PD_EN ( BIT(2) ) +#define BIT_SLP_LDOVDD28_PD_EN ( BIT(1) ) +#define BIT_SLP_LDOVDD18_PD_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SLP_CTRL1 */ +#define BIT_SLP_LDO_PD_EN ( BIT(12) ) +#define BIT_SLP_LDOLPREF_PD_EN ( BIT(11) ) +#define BIT_SLP_LDOCLSG_PD_EN ( BIT(10) ) +#define BIT_SLP_LDOUSB_PD_EN ( BIT(9) ) +#define BIT_SLP_LDOCAMMOT_PD_EN ( BIT(8) ) +#define BIT_SLP_LDOCAMIO_PD_EN ( BIT(7) ) +#define BIT_SLP_LDOCAMD_PD_EN ( BIT(6) ) +#define BIT_SLP_LDOCAMA_PD_EN ( BIT(5) ) +#define BIT_SLP_LDOSIM2_PD_EN ( BIT(4) ) +#define BIT_SLP_LDOSIM1_PD_EN ( BIT(3) ) +#define BIT_SLP_LDOSIM0_PD_EN ( BIT(2) ) +#define BIT_SLP_LDOSD_PD_EN ( BIT(1) ) +#define BIT_SLP_LDOAVDD18_PD_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SLP_CTRL2 */ +#define BIT_SLP_DCDC_BG_LP_EN ( BIT(15) ) +#define BIT_SLP_DCDCCORE_LP_EN ( BIT(11) ) +#define BIT_SLP_DCDCMEM_LP_EN ( BIT(10) ) +#define BIT_SLP_DCDCARM_LP_EN ( BIT(9) ) +#define BIT_SLP_DCDCGEN_LP_EN ( BIT(8) ) +#define BIT_SLP_DCDCWPA_LP_EN ( BIT(6) ) +#define BIT_SLP_DCDCWRF_LP_EN ( BIT(5) ) +#define BIT_SLP_LDOEMMCCORE_LP_EN ( BIT(4) ) +#define BIT_SLP_LDOEMMCIO_LP_EN ( BIT(3) ) +#define BIT_SLP_LDORF2_LP_EN ( BIT(2) ) +#define BIT_SLP_LDORF1_LP_EN ( BIT(1) ) +#define BIT_SLP_LDORF0_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SLP_CTRL3 */ +#define BIT_SLP_BG_LP_EN ( BIT(15) ) +#define BIT_SLP_LDOVDD25_LP_EN ( BIT(13) ) +#define BIT_SLP_LDOVDD28_LP_EN ( BIT(12) ) +#define BIT_SLP_LDOVDD18_LP_EN ( BIT(11) ) +#define BIT_SLP_LDOCLSG_LP_EN ( BIT(10) ) +#define BIT_SLP_LDOUSB_LP_EN ( BIT(9) ) +#define BIT_SLP_LDOCAMMOT_LP_EN ( BIT(8) ) +#define BIT_SLP_LDOCAMIO_LP_EN ( BIT(7) ) +#define BIT_SLP_LDOCAMD_LP_EN ( BIT(6) ) +#define BIT_SLP_LDOCAMA_LP_EN ( BIT(5) ) +#define BIT_SLP_LDOSIM2_LP_EN ( BIT(4) ) +#define BIT_SLP_LDOSIM1_LP_EN ( BIT(3) ) +#define BIT_SLP_LDOSIM0_LP_EN ( BIT(2) ) +#define BIT_SLP_LDOSD_LP_EN ( BIT(1) ) +#define BIT_SLP_LDOAVDD18_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_AUD_SLP_CTRL4 */ +#define BIT_SLP_AUD_PA_SW_PD_EN ( BIT(15) ) +#define BIT_SLP_AUD_PA_LDO_PD_EN ( BIT(14) ) +#define BIT_SLP_AUD_PA_PD_EN ( BIT(13) ) +#define BIT_SLP_AUD_OVP_PD_PD_EN ( BIT(9) ) +#define BIT_SLP_AUD_OVP_LDO_PD_EN ( BIT(8) ) +#define BIT_SLP_AUD_VB_PD_EN ( BIT(7) ) +#define BIT_SLP_AUD_VBO_PD_EN ( BIT(6) ) +#define BIT_SLP_AUD_HEADMICBIAS_PD_EN ( BIT(5) ) +#define BIT_SLP_AUD_MICBIAS_HV_PD_EN ( BIT(2) ) +#define BIT_SLP_AUD_HEADMIC_PD_EN ( BIT(1) ) +#define BIT_SLP_AUD_PMUR1_PD_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL */ +#define BITS_SLP_DCDCCORE_VOL_DROP_CNT(_x_)( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DCDC_CORE_CTL_DS(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register ANA_REG_GLB_XTL_WAIT_CTRL */ +#define BIT_SLP_XTLBUF_PD_EN ( BIT(9) ) +#define BIT_XTL_EN ( BIT(8) ) +#define BITS_XTL_WAIT(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_FLASH_CTRL */ +#define BIT_FLASH_PON ( BIT(15) ) +#define BIT_FLASH_V_HW_EN ( BIT(6) ) +#define BITS_FLASH_V_HW_STEP(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_FLASH_V_SW(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register ANA_REG_GLB_WHTLED_CTRL0 */ +#define BIT_WHTLED_PD_STS ( BIT(15) ) +#define BITS_WHTLED_DC(_x_) ( (_x_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BIT_WHTLED_BOOST_EN ( BIT(8) ) +#define BIT_WHTLED_SERIES_EN ( BIT(7) ) +#define BITS_WHTLED_V(_x_) ( (_x_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_WHTLED_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_WHTLED_CTRL1 */ +#define BIT_LCM_CABC_PWM_SEL ( BIT(15) ) +#define BIT_RTC_PWM0_EN ( BIT(14) ) +#define BIT_PWM0_EN ( BIT(13) ) +#define BITS_WHTLED_ISET(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_WHTLED_FRE_AD(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)) ) +#define BITS_WHTLED_CLMIT_OP(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_WHTLED_CTRL2 */ +#define BIT_WHTLED_DIMMING_SEL ( BIT(15) ) +#define BIT_WHTLED_PD_SEL ( BIT(14) ) +#define BIT_WHTLED_DIS_OVST ( BIT(13) ) +#define BIT_WHTLED_DIM_SEL ( BIT(12) ) +#define BIT_WHTLED_DE_BIAS ( BIT(11) ) +#define BIT_WHTLED_BUFF_SHT ( BIT(10) ) +#define BITS_WHTLED_STB_OP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_WHTLED_CAP_OPTION ( BIT(7) ) +#define BIT_WHTLED_OVP_DIS ( BIT(6) ) +#define BITS_WHTLED_REF_DC(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register ANA_REG_GLB_ANA_DRV_CTRL */ +#define BIT_SLP_RGB_PD_EN ( BIT(14) ) +#define BIT_RGB_PD_HW_EN ( BIT(13) ) +#define BITS_RGB_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BITS_KPLED_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_RGB_PD_SW ( BIT(2) ) +#define BIT_KPLED_PD ( BIT(1) ) +#define BIT_KPLED_PD_STS ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_VIBR_CTRL0 */ +#define BITS_VIBR_STABLE_V_HW(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_VIBR_INIT_V_HW(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_VIBR_V_SW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_VIBR_PON ( BIT(2) ) +#define BIT_VIBR_SW_EN ( BIT(1) ) + +/* bits definitions for register ANA_REG_GLB_VIBR_CTRL1 */ +#define BITS_VIBR_V_CONVERT_CNT_HW(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_VIBR_CTRL2 */ +#define BIT_VIBR_PWR_ON_STS ( BIT(15) ) +#define BIT_VIBR_HW_FLOW_ERR1 ( BIT(14) ) +#define BIT_VIBR_HW_FLOW_ERR1_CLR ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_VIBR_WR_PROT_VALUE */ +#define BIT_VIBR_WR_PROT ( BIT(15) ) +#define BITS_VIBR_WR_PROT_VALUE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_AUDIO_CTRL */ +#define BIT_AUD_SLP_APP_RST_EN ( BIT(10) ) +#define BITS_CLK_AUD_HBD_DIV(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BIT_CLK_AUD_LOOP_INV_EN ( BIT(4) ) +#define BIT_CLK_AUDIF_TX_INV_EN ( BIT(3) ) +#define BIT_CLK_AUDIF_RX_INV_EN ( BIT(2) ) +#define BIT_CLK_AUD_6P5M_TX_INV_EN ( BIT(1) ) +#define BIT_CLK_AUD_6P5M_RX_INV_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL0 */ +#define BIT_CHGR_PD_STS ( BIT(15) ) +#define BITS_CHGR_CV_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CHGR_END_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CHG_PUMP_V(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BIT_CHGR_PD_RTCCLR ( BIT(1) ) +#define BIT_CHGR_PD_RTCSET ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL1 */ +#define BIT_DP_DM_SW_EN ( BIT(15) ) +#define BITS_CHGR_CC_I(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_VBAT_OVP_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_VCHG_OVP_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL2 */ +#define BITS_CHG_PUMP_CAL(_x_) ( (_x_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_CHG_PUMP_PD ( BIT(8) ) +#define BIT_CHGR_CC_EN ( BIT(1) ) +#define BIT_RECHG ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_STATUS */ +#define BIT_CHG_DET_DONE ( BIT(11) ) +#define BIT_DP_LOW ( BIT(10) ) +#define BIT_DCP_DET ( BIT(9) ) +#define BIT_CHG_DET ( BIT(8) ) +#define BIT_SDP_INT ( BIT(7) ) +#define BIT_DCP_INT ( BIT(6) ) +#define BIT_CDP_INT ( BIT(5) ) +#define BIT_CHGR_CV_STATUS ( BIT(4) ) +#define BIT_CHGR_ON ( BIT(3) ) +#define BIT_CHGR_INT ( BIT(2) ) +#define BIT_VBAT_OVI ( BIT(1) ) +#define BIT_VCHG_OVI ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_ANA_MIXED_CTRL */ +#define BIT_PTEST_PD_RTCSET ( BIT(15) ) +#define BIT_THM_CHIP_PD_FLAG ( BIT(8) ) +#define BIT_THM_CHIP_PD_FLAG_CLR ( BIT(7) ) +#define BITS_THM_CAL_SEL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)) ) +#define BIT_THM_AUTO_PD_EN ( BIT(4) ) +#define BIT_BG_LP_EN ( BIT(3) ) +#define BITS_UVHO_T(_x_) ( (_x_) << 1 & (BIT(1)|BIT(2)) ) +#define BIT_UVHO_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN0 */ +#define BIT_LDO_XTL_EN ( BIT(15) ) +#define BIT_LDO_RF1_EXT_XTL2_EN ( BIT(11) ) +#define BIT_LDO_RF1_EXT_XTL1_EN ( BIT(10) ) +#define BIT_LDO_RF1_EXT_XTL0_EN ( BIT(9) ) +#define BIT_LDO_RF1_XTL2_EN ( BIT(8) ) +#define BIT_LDO_RF1_XTL1_EN ( BIT(7) ) +#define BIT_LDO_RF1_XTL0_EN ( BIT(6) ) +#define BIT_LDO_RF0_EXT_XTL2_EN ( BIT(5) ) +#define BIT_LDO_RF0_EXT_XTL1_EN ( BIT(4) ) +#define BIT_LDO_RF0_EXT_XTL0_EN ( BIT(3) ) +#define BIT_LDO_RF0_XTL2_EN ( BIT(2) ) +#define BIT_LDO_RF0_XTL1_EN ( BIT(1) ) +#define BIT_LDO_RF0_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN1 */ +#define BIT_LDO_VDD25_EXT_XTL2_EN ( BIT(11) ) +#define BIT_LDO_VDD25_EXT_XTL1_EN ( BIT(10) ) +#define BIT_LDO_VDD25_EXT_XTL0_EN ( BIT(9) ) +#define BIT_LDO_VDD25_XTL2_EN ( BIT(8) ) +#define BIT_LDO_VDD25_XTL1_EN ( BIT(7) ) +#define BIT_LDO_VDD25_XTL0_EN ( BIT(6) ) +#define BIT_LDO_RF2_EXT_XTL2_EN ( BIT(5) ) +#define BIT_LDO_RF2_EXT_XTL1_EN ( BIT(4) ) +#define BIT_LDO_RF2_EXT_XTL0_EN ( BIT(3) ) +#define BIT_LDO_RF2_XTL2_EN ( BIT(2) ) +#define BIT_LDO_RF2_XTL1_EN ( BIT(1) ) +#define BIT_LDO_RF2_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN2 */ +#define BIT_LDO_AVDD18_EXT_XTL2_EN ( BIT(11) ) +#define BIT_LDO_AVDD18_EXT_XTL1_EN ( BIT(10) ) +#define BIT_LDO_AVDD18_EXT_XTL0_EN ( BIT(9) ) +#define BIT_LDO_AVDD18_XTL2_EN ( BIT(8) ) +#define BIT_LDO_AVDD18_XTL1_EN ( BIT(7) ) +#define BIT_LDO_AVDD18_XTL0_EN ( BIT(6) ) +#define BIT_LDO_SIM2_EXT_XTL2_EN ( BIT(5) ) +#define BIT_LDO_SIM2_EXT_XTL1_EN ( BIT(4) ) +#define BIT_LDO_SIM2_EXT_XTL0_EN ( BIT(3) ) +#define BIT_LDO_SIM2_XTL2_EN ( BIT(2) ) +#define BIT_LDO_SIM2_XTL1_EN ( BIT(1) ) +#define BIT_LDO_SIM2_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN3 */ +#define BIT_DCDC_BG_EXT_XTL2_EN ( BIT(11) ) +#define BIT_DCDC_BG_EXT_XTL1_EN ( BIT(10) ) +#define BIT_DCDC_BG_EXT_XTL0_EN ( BIT(9) ) +#define BIT_DCDC_BG_XTL2_EN ( BIT(8) ) +#define BIT_DCDC_BG_XTL1_EN ( BIT(7) ) +#define BIT_DCDC_BG_XTL0_EN ( BIT(6) ) +#define BIT_BG_EXT_XTL2_EN ( BIT(5) ) +#define BIT_BG_EXT_XTL1_EN ( BIT(4) ) +#define BIT_BG_EXT_XTL0_EN ( BIT(3) ) +#define BIT_BG_XTL2_EN ( BIT(2) ) +#define BIT_BG_XTL1_EN ( BIT(1) ) +#define BIT_BG_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN4 */ +#define BIT_DCDC_WRF_XTL2_EN ( BIT(14) ) +#define BIT_DCDC_WRF_XTL1_EN ( BIT(13) ) +#define BIT_DCDC_WRF_XTL0_EN ( BIT(12) ) +#define BIT_DCDC_WPA_XTL2_EN ( BIT(11) ) +#define BIT_DCDC_WPA_XTL1_EN ( BIT(10) ) +#define BIT_DCDC_WPA_XTL0_EN ( BIT(9) ) +#define BIT_DCDC_MEM_XTL2_EN ( BIT(8) ) +#define BIT_DCDC_MEM_XTL1_EN ( BIT(7) ) +#define BIT_DCDC_MEM_XTL0_EN ( BIT(6) ) +#define BIT_DCDC_GEN_XTL2_EN ( BIT(5) ) +#define BIT_DCDC_GEN_XTL1_EN ( BIT(4) ) +#define BIT_DCDC_GEN_XTL0_EN ( BIT(3) ) +#define BIT_DCDC_CORE_XTL2_EN ( BIT(2) ) +#define BIT_DCDC_CORE_XTL1_EN ( BIT(1) ) +#define BIT_DCDC_CORE_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN5 */ +#define BIT_DCDC_WRF_EXT_XTL2_EN ( BIT(14) ) +#define BIT_DCDC_WRF_EXT_XTL1_EN ( BIT(13) ) +#define BIT_DCDC_WRF_EXT_XTL0_EN ( BIT(12) ) +#define BIT_DCDC_WPA_EXT_XTL2_EN ( BIT(11) ) +#define BIT_DCDC_WPA_EXT_XTL1_EN ( BIT(10) ) +#define BIT_DCDC_WPA_EXT_XTL0_EN ( BIT(9) ) +#define BIT_DCDC_MEM_EXT_XTL2_EN ( BIT(8) ) +#define BIT_DCDC_MEM_EXT_XTL1_EN ( BIT(7) ) +#define BIT_DCDC_MEM_EXT_XTL0_EN ( BIT(6) ) +#define BIT_DCDC_GEN_EXT_XTL2_EN ( BIT(5) ) +#define BIT_DCDC_GEN_EXT_XTL1_EN ( BIT(4) ) +#define BIT_DCDC_GEN_EXT_XTL0_EN ( BIT(3) ) +#define BIT_DCDC_CORE_EXT_XTL2_EN ( BIT(2) ) +#define BIT_DCDC_CORE_EXT_XTL1_EN ( BIT(1) ) +#define BIT_DCDC_CORE_EXT_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_ANA_STATUS */ +#define BIT_BONDOPT5 ( BIT(5) ) +#define BIT_BONDOPT4 ( BIT(4) ) +#define BIT_BONDOPT3 ( BIT(3) ) +#define BIT_BONDOPT2 ( BIT(2) ) +#define BIT_BONDOPT1 ( BIT(1) ) +#define BIT_BONDOPT0 ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_POR_RST_MONITOR */ +#define BITS_POR_RST_MONITOR(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_WDG_RST_MONITOR */ +#define BITS_WDG_RST_MONITOR(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_POR_PIN_RST_MONITOR */ +#define BITS_POR_PIN_RST_MONITOR(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_POR_SRC_FLAG */ +#define BIT_POR_SW_FORCE_ON ( BIT(15) ) +#define BITS_POR_SRC_FLAG(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_POR_7S_CTRL */ +#define BIT_PBINT_7S_FLAG_CLR ( BIT(15) ) +#define BIT_EXT_RSTN_FLAG_CLR ( BIT(14) ) +#define BIT_CHGR_INT_FLAG_CLR ( BIT(13) ) +#define BIT_PBINT2_FLAG_CLR ( BIT(12) ) +#define BIT_PBINT_FLAG_CLR ( BIT(11) ) +#define BIT_PBINT_7S_RST_SWMODE_RTCSTS ( BIT(10) ) +#define BIT_PBINT_7S_RST_SWMODE_RTCCLR ( BIT(9) ) +#define BIT_PBINT_7S_RST_SWMODE_RTCSET ( BIT(8) ) +#define BITS_PBINT_7S_RST_THRESHOLD(_x_)( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_PBINT_7S_RST_DISABLE ( BIT(3) ) +#define BIT_PBINT_7S_RST_MODE_RTCSTS ( BIT(2) ) +#define BIT_PBINT_7S_RST_MODE_RTCCLR ( BIT(1) ) +#define BIT_PBINT_7S_RST_MODE_RTCSET ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_INT_DEBUG */ +#define BIT_OTP_INT_DEB ( BIT(10) ) +#define BIT_THM_INT_DEB ( BIT(9) ) +#define BIT_AUD_PROT_INT_DEB ( BIT(8) ) +#define BIT_AUD_HEADBTN_INT_DEB ( BIT(7) ) +#define BIT_EIC_INT_DEB ( BIT(6) ) +#define BIT_FGU_INT_DEB ( BIT(5) ) +#define BIT_WDG_INT_DEB ( BIT(4) ) +#define BIT_RTC_INT_DEB ( BIT(3) ) +#define BIT_GPIO_INT_DEB ( BIT(2) ) +#define BIT_ADC_INT_DEB ( BIT(1) ) +#define BIT_INT_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_GPI_DEBUG */ +#define BIT_HEAD_INSERT2_DEB ( BIT(9) ) +#define BIT_HEAD_INSERT_DEB ( BIT(8) ) +#define BIT_HEAD_BUTTON_DEB ( BIT(7) ) +#define BIT_PBINT2_DEB ( BIT(6) ) +#define BIT_PBINT_DEB ( BIT(5) ) +#define BIT_VCHG_OVI_DEB ( BIT(4) ) +#define BIT_VBAT_OVI_DEB ( BIT(3) ) +#define BIT_CHGR_INT_DEB ( BIT(2) ) +#define BIT_GPI_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_HWRST_RTC */ +#define BITS_HWRST_RTC_REG_STS(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_HWRST_RTC_REG_SET(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_CHIP_ID_LOW */ +#define BITS_CHIP_ID_LOW(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_CHIP_ID_HIGH */ +#define BITS_CHIP_ID_HIGH(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_ARM_MF_REG */ +#define BITS_ARM_MF_REG(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_AFUSE_CTRL */ +#define BIT_AFUSE_READ_REQ ( BIT(7) ) +#define BITS_AFUSE_READ_DLY(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) + +/* bits definitions for register ANA_REG_GLB_AFUSE_OUT0 */ +#define BITS_AFUSE_OUT0(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_AFUSE_OUT1 */ +#define BITS_AFUSE_OUT1(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_AFUSE_OUT2 */ +#define BITS_AFUSE_OUT2(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_AFUSE_OUT3 */ +#define BITS_AFUSE_OUT3(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_ARCH_EN */ +#define BIT_ARCH_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_MCU_WR_PROT_VALUE */ +#define BIT_MCU_WR_PROT ( BIT(15) ) +#define BITS_MCU_WR_PROT_VALUE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CORE_ADI */ +#define BITS_DCDC_CORE_CTL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DCDC_CORE_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_ARM_ADI */ +#define BITS_DCDC_ARM_CTL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DCDC_ARM_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_MEM_ADI */ +#define BIT_DCDC_MEM_CTL_ADI ( BIT(5) ) +#define BITS_DCDC_MEM_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_GEN_ADI */ +#define BITS_DCDC_GEN_CTL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DCDC_GEN_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_WRF_ADI */ +#define BITS_DCDC_WRF_CTL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)) ) +#define BITS_DCDC_WRF_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_WPA_ADI */ +#define BITS_DCDC_WPA_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_WPA_DCM_ADI */ +#define BIT_DCDC_WPA_DCM_ADI ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_CAL_SEL */ +#define BIT_LDO_CAMIO_CAL_EN ( BIT(5) ) +#define BIT_LDO_CLSG_CAL_EN ( BIT(6) ) +#define BITS_LDO_CAMD_CAL_EN(_x_) ( (_x_) & (BIT(5)|BIT(6)) ) +#define BIT_LDO_EMMCIO_CAL_EN ( BIT(7) ) +#define BITS_LDO_AVDD18_CAL_EN(_x_) ( (_x_) & (BIT(5)|BIT(7)) ) +#define BITS_LDO_VDD18_CAL_EN(_x_) ( (_x_) & (BIT(6)|BIT(7)) ) +#define BIT_LDO_SIM0_CAL_EN ( BIT(9) ) +#define BIT_LDO_SIM1_CAL_EN ( BIT(9) ) +#define BITS_LDO_SIM2_CAL_EN(_x_) ( (_x_) & (BIT(8)|BIT(9)) ) +#define BIT_LDO_EMMCCORE_CAL_EN ( BIT(10) ) +#define BITS_LDO_VDD28_CAL_EN(_x_) ( (_x_) & (BIT(8)|BIT(10)) ) +#define BITS_LDO_VDD25_CAL_EN(_x_) ( (_x_) & (BIT(9)|BIT(10)) ) +#define BITS_LDO_USB_CAL_EN(_x_) ( (_x_) & (BIT(8)|BIT(9)|BIT(10)) ) +#define BIT_LDO_SD_CAL_EN ( BIT(11) ) +#define BIT_LDO_CAMA_CAL_EN ( BIT(12) ) +#define BITS_LDO_RF2_CAL_EN(_x_) ( (_x_) & (BIT(11)|BIT(12)) ) +#define BIT_LDO_RF1_CAL_EN ( BIT(13) ) +#define BITS_LDO_RF0_CAL_EN(_x_) ( (_x_) & (BIT(11)|BIT(13)) ) +#define BITS_LDO_CAMMOT_CAL_EN(_x_) ( (_x_) & (BIT(12)|BIT(13)) ) +#define BITS_LDO_CAL_SEL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +#define SHFT_LDO_CAL_SEL ( 5 ) +#define MASK_LDO_CAL_SEL ( BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13) ) + +/* vars definitions for controller ANA_REGS_GLB */ + +#endif //__ANA_REGS_GLB_H__ diff --git a/include/soc/sprd/chip_x35lt8/__regs_ana_sc2723_glb.h b/include/soc/sprd/chip_x35lt8/__regs_ana_sc2723_glb.h new file mode 100755 index 00000000..fe9cd745 --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_ana_sc2723_glb.h @@ -0,0 +1,952 @@ +/* + * Copyright (C) 2014 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __ANA_REGS_GLB_H__ +#define __ANA_REGS_GLB_H__ + +#define ANA_REGS_GLB + +/* registers definitions for controller ANA_REGS_GLB */ +#define ANA_REG_GLB_ARM_MODULE_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0000) +#define ANA_REG_GLB_ARM_CLK_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0004) +#define ANA_REG_GLB_RTC_CLK_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0008) +#define ANA_REG_GLB_ARM_RST SCI_ADDR(ANA_REGS_GLB_BASE, 0x000C) +#define ANA_REG_GLB_LDO_DCDC_PD SCI_ADDR(ANA_REGS_GLB_BASE, 0x0010) +#define ANA_REG_GLB_LDO_PD_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0014) +#define ANA_REG_GLB_LDO_V_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0018) +#define ANA_REG_GLB_LDO_V_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x001C) +#define ANA_REG_GLB_LDO_V_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0020) +#define ANA_REG_GLB_LDO_V_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0024) +#define ANA_REG_GLB_LDO_V_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0028) +#define ANA_REG_GLB_LDO_V_CTRL5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x002C) +#define ANA_REG_GLB_LDO_V_CTRL6 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0030) +#define ANA_REG_GLB_LDO_V_CTRL7 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0034) +#define ANA_REG_GLB_LDO_V_CTRL8 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0038) +#define ANA_REG_GLB_LDO_V_CTRL9 SCI_ADDR(ANA_REGS_GLB_BASE, 0x003C) +#define ANA_REG_GLB_LDO_V_CTRL10 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0040) +#define ANA_REG_GLB_LDO_V_CTRL11 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0044) +#define ANA_REG_GLB_LDO_LP_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0048) +#define ANA_REG_GLB_DCDC_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x004C) +#define ANA_REG_GLB_DCDC_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0050) +#define ANA_REG_GLB_DCDC_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0054) +#define ANA_REG_GLB_DCDC_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0058) +#define ANA_REG_GLB_DCDC_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x005C) +#define ANA_REG_GLB_DCDC_CTRL5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0060) +#define ANA_REG_GLB_DCDC_CTRL6 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0064) +#define ANA_REG_GLB_DCDC_CTRL7 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0068) +#define ANA_REG_GLB_DCDC_CTRL8 SCI_ADDR(ANA_REGS_GLB_BASE, 0x006C) +#define ANA_REG_GLB_DCDC_CTRL9 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0070) +#define ANA_REG_GLB_DCDC_CTRL10 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0074) +#define ANA_REG_GLB_DCDC_CTRL11 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0078) +#define ANA_REG_GLB_DCDC_CTRL12 SCI_ADDR(ANA_REGS_GLB_BASE, 0x007C) +#define ANA_REG_GLB_DCDC_CTRL13 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0080) +#define ANA_REG_GLB_DCDC_CTRL14 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0084) +#define ANA_REG_GLB_DCDC_CTRL15 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0088) +#define ANA_REG_GLB_SLP_WAIT_DCDCARM SCI_ADDR(ANA_REGS_GLB_BASE, 0x008C) +#define ANA_REG_GLB_PWR_SLP_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0090) +#define ANA_REG_GLB_PWR_SLP_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0094) +#define ANA_REG_GLB_PWR_SLP_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0098) +#define ANA_REG_GLB_PWR_SLP_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x009C) +#define ANA_REG_GLB_PWR_SLP_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A0) +#define ANA_REG_GLB_AUD_SLP_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A4) +#define ANA_REG_GLB_DCDC_SLP_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A8) +#define ANA_REG_GLB_DCDC_SLP_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00AC) +#define ANA_REG_GLB_DCDC_SLP_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B0) +#define ANA_REG_GLB_DCDC_SLP_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B4) +#define ANA_REG_GLB_DCDC_SLP_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B8) +#define ANA_REG_GLB_DCDC_SLP_CTRL5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00BC) +#define ANA_REG_GLB_PWR_SEL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C0) +#define ANA_REG_GLB_PWR_XTL_EN0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C4) +#define ANA_REG_GLB_PWR_XTL_EN1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C8) +#define ANA_REG_GLB_PWR_XTL_EN2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00CC) +#define ANA_REG_GLB_PWR_XTL_EN3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D0) +#define ANA_REG_GLB_32KLESS_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D4) +#define ANA_REG_GLB_32KLESS_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D8) +#define ANA_REG_GLB_32KLESS_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00DC) +#define ANA_REG_GLB_32KLESS_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E0) +#define ANA_REG_GLB_AUXAD_CTL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E4) +#define ANA_REG_GLB_XTL_WAIT_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E8) +#define ANA_REG_GLB_RGB_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00EC) +#define ANA_REG_GLB_WHTLED_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F0) +#define ANA_REG_GLB_WHTLED_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0094) +#define ANA_REG_GLB_WHTLED_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0098) +#define ANA_REG_GLB_KPLED_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F4) +#define ANA_REG_GLB_VIBR_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F8) +#define ANA_REG_GLB_AUDIO_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00FC) +#define ANA_REG_GLB_AUDIO_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0100) +#define ANA_REG_GLB_CHGR_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0104) +#define ANA_REG_GLB_CHGR_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0108) +#define ANA_REG_GLB_CHGR_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x010C) +#define ANA_REG_GLB_CHGR_DET_FGU_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0110) +#define ANA_REG_GLB_CHGR_STATUS SCI_ADDR(ANA_REGS_GLB_BASE, 0x0114) +#define ANA_REG_GLB_MIXED_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0118) +#define ANA_REG_GLB_MIXED_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x011C) +#define ANA_REG_GLB_SWRST_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0120) +#define ANA_REG_GLB_POR_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x0124) +#define ANA_REG_GLB_WDG_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x0128) +#define ANA_REG_GLB_POR_PIN_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x012C) +#define ANA_REG_GLB_POR_SRC_FLAG SCI_ADDR(ANA_REGS_GLB_BASE, 0x0130) +#define ANA_REG_GLB_POR_7S_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0134) +#define ANA_REG_GLB_HWRST_RTC SCI_ADDR(ANA_REGS_GLB_BASE, 0x0138) +#define ANA_REG_GLB_CHIP_ID_LOW SCI_ADDR(ANA_REGS_GLB_BASE, 0x013C) +#define ANA_REG_GLB_CHIP_ID_HIGH SCI_ADDR(ANA_REGS_GLB_BASE, 0x0140) +#define ANA_REG_GLB_ARM_MF_REG SCI_ADDR(ANA_REGS_GLB_BASE, 0x0144) +#define ANA_REG_GLB_ARCH_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0148) +#define ANA_REG_GLB_MCU_WR_PROT_VALUE SCI_ADDR(ANA_REGS_GLB_BASE, 0x014C) +#define ANA_REG_GLB_PWR_WR_PROT_VALUE SCI_ADDR(ANA_REGS_GLB_BASE, 0x0150) +#define ANA_REG_GLB_SMPL_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0154) +#define ANA_REG_GLB_SMPL_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0158) +#define ANA_REG_GLB_RTC_RST0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x015C) +#define ANA_REG_GLB_RTC_RST1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0160) +#define ANA_REG_GLB_RTC_RST2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0164) +#define ANA_REG_GLB_LDO_SHPT_PD1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0188) +#define ANA_REG_GLB_LDO_SHPT_PD2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x018C) +#define ANA_REG_GLB_BATDET_CUR_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0190) +#define ANA_REG_GLB_RTC_CLK_STOP SCI_ADDR(ANA_REGS_GLB_BASE, 0x0194) +#define ANA_REG_GLB_VBAT_DROP_CNT SCI_ADDR(ANA_REGS_GLB_BASE, 0x0198) +#define ANA_REG_GLB_DCDC_DISCHRG SCI_ADDR(ANA_REGS_GLB_BASE, 0x019C) +#define ANA_REG_GLB_DCDC_CORE_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0200) +#define ANA_REG_GLB_DCDC_ARM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0204) +#define ANA_REG_GLB_DCDC_MEM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0208) +#define ANA_REG_GLB_DCDC_GEN_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x020C) +#define ANA_REG_GLB_DCDC_WPA_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0210) +#define ANA_REG_GLB_DCDC_WPA_DCM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0214) +#define ANA_REG_GLB_DCDC_CON_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0218) +#define ANA_REG_GLB_DCDC_RF_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x021C) + +/* bits definitions for register ANA_REG_GLB_ARM_MODULE_EN */ +#define BIT_ANA_IMPD_ADC_EN ( BIT(12) ) +#define BIT_ANA_THM_EN ( BIT(11) ) +#define BIT_ANA_BLTC_EN ( BIT(10) ) +#define BIT_ANA_PINREG_EN ( BIT(9) ) +#define BIT_ANA_FGU_EN ( BIT(8) ) +#define BIT_ANA_EFS_EN ( BIT(7) ) +#define BIT_ANA_ADC_EN ( BIT(6) ) +#define BIT_ANA_HDT_EN ( BIT(5) ) +#define BIT_ANA_AUD_EN ( BIT(4) ) +#define BIT_ANA_EIC_EN ( BIT(3) ) +#define BIT_ANA_WDG_EN ( BIT(2) ) +#define BIT_ANA_RTC_EN ( BIT(1) ) +#define BIT_ANA_CAL_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_ARM_CLK_EN */ +#define BIT_CLK_IMPD_ADC_EN ( BIT(10) ) +#define BIT_CLK_AUXAD_EN ( BIT(9) ) +#define BIT_CLK_AUXADC_EN ( BIT(8) ) +#define BITS_CLK_CAL_SRC_SEL(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BIT_CLK_CAL_EN ( BIT(5) ) +#define BIT_CLK_AUD_HID_EN ( BIT(4) ) +#define BIT_CLK_AUD_HBD_EN ( BIT(3) ) +#define BIT_CLK_AUD_LOOP_EN ( BIT(2) ) +#define BIT_CLK_AUD_6P5M_EN ( BIT(1) ) +#define BIT_CLK_AUDIF_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_RTC_CLK_EN */ +#define BIT_RTC_EFS_EN ( BIT(12) ) +#define BIT_RTC_THMA_AUTO_EN ( BIT(11) ) +#define BIT_RTC_THMA_EN ( BIT(10) ) +#define BIT_RTC_THM_EN ( BIT(9) ) +#define BIT_RTC_BLTC_EN ( BIT(8) ) +#define BIT_RTC_FGU_EN ( BIT(7) ) +#define BIT_RTC_FGUA_EN ( BIT(6) ) +#define BIT_RTC_VIBR_EN ( BIT(5) ) +#define BIT_RTC_AUD_EN ( BIT(4) ) +#define BIT_RTC_EIC_EN ( BIT(3) ) +#define BIT_RTC_WDG_EN ( BIT(2) ) +#define BIT_RTC_RTC_EN ( BIT(1) ) +#define BIT_RTC_ARCH_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_ARM_RST */ +#define BIT_ANA_THMA_SOFT_RST ( BIT(15) ) +#define BIT_ANA_THM_SOFT_RST ( BIT(14) ) +#define BIT_ANA_BLTC_SOFT_RST ( BIT(13) ) +#define BIT_ANA_AUD_32K_SOFT_RST ( BIT(12) ) +#define BIT_ANA_AUDTX_SOFT_RST ( BIT(11) ) +#define BIT_ANA_AUDRX_SOFT_RST ( BIT(10) ) +#define BIT_ANA_AUD_SOFT_RST ( BIT(9) ) +#define BIT_ANA_AUD_HDT_SOFT_RST ( BIT(8) ) +#define BIT_ANA_EFS_SOFT_RST ( BIT(7) ) +#define BIT_ANA_ADC_SOFT_RST ( BIT(6) ) +#define BIT_ANA_PWM0_SOFT_RST ( BIT(5) ) +#define BIT_ANA_FGU_SOFT_RST ( BIT(4) ) +#define BIT_ANA_EIC_SOFT_RST ( BIT(3) ) +#define BIT_ANA_WDG_SOFT_RST ( BIT(2) ) +#define BIT_ANA_RTC_SOFT_RST ( BIT(1) ) +#define BIT_ANA_CAL_SOFT_RST ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_DCDC_PD */ +#define BIT_LDO_EMM_PD ( BIT(15) ) +#define BIT_DCDC_TOPCLK6M_PD ( BIT(14) ) +#define BIT_DCDC_RF_PD ( BIT(13) ) +#define BIT_DCDC_GEN_PD ( BIT(12) ) +#define BIT_DCDC_MEM_PD ( BIT(11) ) +#define BIT_DCDC_ARM_PD ( BIT(10) ) +#define BIT_DCDC_CORE_PD ( BIT(9) ) +#define BIT_LDO_RF0_PD ( BIT(8) ) +#define BIT_LDO_EMMCCORE_PD ( BIT(7) ) +#define BIT_LDO_GEN1_PD ( BIT(6) ) +#define BIT_LDO_DCXO_PD ( BIT(5) ) +#define BIT_LDO_GEN0_PD ( BIT(4) ) +#define BIT_LDO_VDD25_PD ( BIT(3) ) +#define BIT_LDO_VDD28_PD ( BIT(2) ) +#define BIT_LDO_VDD18_PD ( BIT(1) ) +#define BIT_BG_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_PD_CTRL */ +#define BIT_LDO_LPREF_PD_SW ( BIT(15) ) +#define BIT_DCDC_WPA_PD ( BIT(14) ) +#define BIT_DCDC_CON_PD ( BIT(13) ) +#define BIT_LDO_WIFIPA_PD ( BIT(11) ) +#define BIT_LDO_SDCORE_PD ( BIT(10) ) +#define BIT_LDO_USB_PD ( BIT(8) ) +#define BIT_LDO_CAMMOT_PD ( BIT(7) ) +#define BIT_LDO_CAMIO_PD ( BIT(6) ) +#define BIT_LDO_CAMD_PD ( BIT(5) ) +#define BIT_LDO_CAMA_PD ( BIT(4) ) +#define BIT_LDO_SIM2_PD ( BIT(3) ) +#define BIT_LDO_SIM1_PD ( BIT(2) ) +#define BIT_LDO_SIM0_PD ( BIT(1) ) +#define BIT_LDO_SDIO_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL0 */ +#define BITS_LDO_RF0_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_WIFIPA_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL1 */ +#define BITS_LDO_CAMIO_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_CAMD_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL2 */ +#define BITS_LDO_GEN0_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL3 */ +#define BITS_LDO_GEN1_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_VDD28_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL4 */ +#define BITS_LDO_SIM0_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_SDIO_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL5 */ +#define BITS_LDO_SIM2_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_SIM1_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL6 */ +#define BITS_LDO_SDCORE_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_CAMA_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL7 */ +#define BITS_LDO_EMMCCORE_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_CAMMOT_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL8 */ +#define BITS_LDO_DCXO_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LDO_DCXO_LP_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL9 */ +#define BITS_LDO_VDD18_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDO_USB_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL10 */ +#define BITS_LDO_VDD25_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL11 */ +#define BITS_VBATBK_V(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_LDOB_CAL_SEL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_LDOA_CAL_SEL (_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_LDOD_CAL_SEL(_x_) ( (_x_) << 3 & (BIT(3)|BIT(4)) ) +#define BITS_LDODCDC_CAL_SEL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_LP_CTRL */ +#define BITS_LDOB_LP_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_LDOA_LP_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_LDODCDC_LP_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL0 */ +#define BITS_DCDC_CORE_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_CORE_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_CORE_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_CORE_QKRSPS ( BIT(3) ) +#define BIT_DCDC_CORE_PFM ( BIT(2) ) +#define BIT_DCDC_CORE_DCM ( BIT(1) ) +#define BIT_DCDC_CORE_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL1 */ +#define BITS_DCDC_MEM_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_MEM_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_MEM_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_MEM_QKRSPS ( BIT(3) ) +#define BIT_DCDC_MEM_PFM ( BIT(2) ) +#define BIT_DCDC_MEM_DCM ( BIT(1) ) +#define BIT_DCDC_MEM_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL2 */ +#define BITS_DCDC_GEN_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_GEN_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_GEN_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_GEN_QKRSPS ( BIT(3) ) +#define BIT_DCDC_GEN_PFM ( BIT(2) ) +#define BIT_DCDC_GEN_DCM ( BIT(1) ) +#define BIT_DCDC_GEN_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL3 */ +#define BITS_DCDC_ARM_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_ARM_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_ARM_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_ARM_QKRSPS ( BIT(3) ) +#define BIT_DCDC_ARM_PFM ( BIT(2) ) +#define BIT_DCDC_ARM_DCM ( BIT(1) ) +#define BIT_DCDC_ARM_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL4 */ +#define BITS_DCDC_WPA_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_WPA_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_WPA_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_WPA_QKRSPS ( BIT(3) ) +#define BIT_DCDC_WPA_PFM ( BIT(2) ) +#define BIT_DCDC_WPA_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL5 */ +#define BITS_DCDC_RF_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_RF_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_RF_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_RF_QKRSPS ( BIT(3) ) +#define BIT_DCDC_RF_PFM ( BIT(2) ) +#define BIT_DCDC_RF_DCM ( BIT(1) ) +#define BIT_DCDC_RF_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL6 */ +#define BITS_DCDC_CON_DEADTIME(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_DCDC_CON_STBOP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_DCDC_CON_PDRSLOW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DCDC_CON_QKRSPS ( BIT(3) ) +#define BIT_DCDC_CON_PFM ( BIT(2) ) +#define BIT_DCDC_CON_DCM ( BIT(1) ) +#define BIT_DCDC_CON_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL7 */ +#define BITS_DCDC_MEM_CF(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_DCDC_MEM_PFMAD(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_DCDC_MEM_CL_CTRL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_DCDC_CORE_DUALSEL ( BIT(7) ) +#define BIT_DCDC_CORE_MERGEEN ( BIT(6) ) +#define BITS_DCDC_CORE_CF(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_DCDC_CORE_PFMAD(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DCDC_CORE_CL_CTRL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL8 */ +#define BIT_DCDC_ARM_DUALSEL ( BIT(15) ) +#define BIT_DCDC_ARM_MERGEEN ( BIT(14) ) +#define BITS_DCDC_ARM_CF(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_DCDC_ARM_PFMAD(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_DCDC_ARM_CL_CTRL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_DCDC_GEN_CF(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_DCDC_GEN_PFMAD(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DCDC_GEN_CL_CTRL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL9 */ +#define BIT_DCDC_CON_MERGEEN ( BIT(14) ) +#define BITS_DCDC_CON_CF(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_DCDC_CON_PFMAD(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_DCDC_CON_CL_CTRL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_DCDC_RF_MERGEEN ( BIT(6) ) +#define BITS_DCDC_RF_CF(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_DCDC_RF_PFMAD(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DCDC_RF_CL_CTRL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL10 */ +#define BIT_DCDC_WPA_BPOUT_SOFTW ( BIT(15) ) +#define BITS_DCDC_WPA_VBAT_DIV(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BIT_DCDC_WPA_BPEN ( BIT(11) ) +#define BIT_DCDC_WPA_BPMODE ( BIT(10) ) +#define BIT_DCDC_WPA_DEGEN ( BIT(9) ) +#define BIT_DCDC_WPA_APTEN ( BIT(8) ) +#define BITS_DCDC_WPA_DEBC_SEL(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_DCDC_WPA_CF(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_DCDC_WPA_PFMAD(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DCDC_WPA_CL_CTRL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL11 */ +#define BIT_DCDC_3MCLKCAL_EN ( BIT(13) ) +#define BIT_DCDC_2MCLKCAL_EN ( BIT(12) ) +#define BITS_DCDC_6MFRECAL_SW(_x_) ( (_x_) << 7 & (BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DCDC_4MFRECAL_SW(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_DCDC_CLK_SP_SEL ( BIT(1) ) +#define BIT_DCDC_CLK_SP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL12 */ +#define BIT_DCDC_CORE_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_CORE_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_CORE_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_CORE_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_ARM_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_ARM_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_ARM_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_ARM_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL13 */ +#define BIT_DCDC_MEM_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_MEM_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_MEM_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_MEM_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_GEN_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_GEN_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_GEN_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_GEN_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL14 */ +#define BIT_DCDC_WPA_OSCSYCEN_SW ( BIT(15) ) +#define BIT_DCDC_WPA_OSCSYCEN_HW_EN ( BIT(14) ) +#define BIT_DCDC_WPA_OSCSYC_DIV_EN ( BIT(13) ) +#define BITS_DCDC_WPA_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DCDC_RF_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_RF_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_RF_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_RF_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CTRL15 */ +#define BITS_DCDC_CAL_SEL(_x_) ( (_x_) << 13 & (BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_DCDC_CON_OSCSYCEN_SW ( BIT(7) ) +#define BIT_DCDC_CON_OSCSYCEN_HW_EN ( BIT(6) ) +#define BIT_DCDC_CON_OSCSYC_DIV_EN ( BIT(5) ) +#define BITS_DCDC_CON_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_SLP_WAIT_DCDCARM */ +#define BITS_SLP_IN_WAIT_DCDCARM(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_SLP_OUT_WAIT_DCDCARM(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL0 */ +#define BIT_SLP_IO_EN ( BIT(15) ) +#define BIT_SLP_DCDCRF_PD_EN ( BIT(13) ) +#define BIT_SLP_DCDCCON_PD_EN ( BIT(12) ) +#define BIT_SLP_DCDCGEN_PD_EN ( BIT(11) ) +#define BIT_SLP_DCDCWPA_PD_EN ( BIT(10) ) +#define BIT_SLP_DCDCARM_PD_EN ( BIT(9) ) +#define BIT_SLP_LDOVDD25_PD_EN ( BIT(8) ) +#define BIT_SLP_LDORF0_PD_EN ( BIT(7) ) +#define BIT_SLP_LDOEMMCCORE_PD_EN ( BIT(6) ) +#define BIT_SLP_LDOGEN0_PD_EN ( BIT(5) ) +#define BIT_SLP_LDODCXO_PD_EN ( BIT(4) ) +#define BIT_SLP_LDOGEN1_PD_EN ( BIT(3) ) +#define BIT_SLP_LDOWIFIPA_PD_EN ( BIT(2) ) +#define BIT_SLP_LDOVDD28_PD_EN ( BIT(1) ) +#define BIT_SLP_LDOVDD18_PD_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL1 */ +#define BIT_SLP_LDO_PD_EN ( BIT(15) ) +#define BIT_SLP_LDOLPREF_PD_EN ( BIT(14) ) +#define BIT_SLP_LDOSDCORE_PD_EN ( BIT(9) ) +#define BIT_SLP_LDOUSB_PD_EN ( BIT(8) ) +#define BIT_SLP_LDOCAMMOT_PD_EN ( BIT(7) ) +#define BIT_SLP_LDOCAMIO_PD_EN ( BIT(6) ) +#define BIT_SLP_LDOCAMD_PD_EN ( BIT(5) ) +#define BIT_SLP_LDOCAMA_PD_EN ( BIT(4) ) +#define BIT_SLP_LDOSIM2_PD_EN ( BIT(3) ) +#define BIT_SLP_LDOSIM1_PD_EN ( BIT(2) ) +#define BIT_SLP_LDOSIM0_PD_EN ( BIT(1) ) +#define BIT_SLP_LDOSDIO_PD_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL2 */ +#define BIT_SLP_DCDCRF_LP_EN ( BIT(14) ) +#define BIT_SLP_DCDCCON_LP_EN ( BIT(13) ) +#define BIT_SLP_DCDCCORE_LP_EN ( BIT(12) ) +#define BIT_SLP_DCDCMEM_LP_EN ( BIT(11) ) +#define BIT_SLP_DCDCARM_LP_EN ( BIT(10) ) +#define BIT_SLP_DCDCGEN_LP_EN ( BIT(9) ) +#define BIT_SLP_DCDCWPA_LP_EN ( BIT(8) ) +#define BIT_SLP_LDORF0_LP_EN ( BIT(7) ) +#define BIT_SLP_LDOEMMCCORE_LP_EN ( BIT(6) ) +#define BIT_SLP_LDOGEN0_LP_EN ( BIT(5) ) +#define BIT_SLP_LDODCXO_LP_EN ( BIT(4) ) +#define BIT_SLP_LDOGEN1_LP_EN ( BIT(3) ) +#define BIT_SLP_LDOWIFIPA_LP_EN ( BIT(2) ) +#define BIT_SLP_LDOVDD28_LP_EN ( BIT(1) ) +#define BIT_SLP_LDOVDD18_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL3 */ +#define BIT_SLP_BG_LP_EN ( BIT(15) ) +#define BIT_LDOVDD25_LP_EN_SW ( BIT(14) ) +#define BIT_LDOSDCORE_LP_EN_SW ( BIT(13) ) +#define BIT_LDOUSB_LP_EN_SW ( BIT(12) ) +#define BIT_SLP_LDOVDD25_LP_EN ( BIT(10) ) +#define BIT_SLP_LDOSDCORE_LP_EN ( BIT(9) ) +#define BIT_SLP_LDOUSB_LP_EN ( BIT(8) ) +#define BIT_SLP_LDOCAMMOT_LP_EN ( BIT(7) ) +#define BIT_SLP_LDOCAMIO_LP_EN ( BIT(6) ) +#define BIT_SLP_LDOCAMD_LP_EN ( BIT(5) ) +#define BIT_SLP_LDOCAMA_LP_EN ( BIT(4) ) +#define BIT_SLP_LDOSIM2_LP_EN ( BIT(3) ) +#define BIT_SLP_LDOSIM1_LP_EN ( BIT(2) ) +#define BIT_SLP_LDOSIM0_LP_EN ( BIT(1) ) +#define BIT_SLP_LDOSDIO_LP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL4 */ +#define BIT_LDOCAMIO_LP_EN_SW ( BIT(15) ) +#define BIT_LDOCAMMOT_LP_EN_SW ( BIT(14) ) +#define BIT_LDOCAMD_LP_EN_SW ( BIT(13) ) +#define BIT_LDOCAMA_LP_EN_SW ( BIT(12) ) +#define BIT_LDOSIM2_LP_EN_SW ( BIT(11) ) +#define BIT_LDOSIM1_LP_EN_SW ( BIT(10) ) +#define BIT_LDOSIM0_LP_EN_SW ( BIT(9) ) +#define BIT_LDOSDIO_LP_EN_SW ( BIT(8) ) +#define BIT_LDORF0_LP_EN_SW ( BIT(7) ) +#define BIT_LDOEMMCCORE_LP_EN_SW ( BIT(6) ) +#define BIT_LDOGEN0_LP_EN_SW ( BIT(5) ) +#define BIT_LDODCXO_LP_EN_SW ( BIT(4) ) +#define BIT_LDOGEN1_LP_EN_SW ( BIT(3) ) +#define BIT_LDOWIFIPA_LP_EN_SW ( BIT(2) ) +#define BIT_LDOVDD28_LP_EN_SW ( BIT(1) ) +#define BIT_LDOVDD18_LP_EN_SW ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_AUD_SLP_CTRL */ +#define BIT_SLP_AUD_PMUR1_PD_EN ( BIT(14) ) +#define BIT_SLP_AUD_PA_SW_PD_EN ( BIT(13) ) +#define BIT_SLP_AUD_PA_LDO_PD_EN ( BIT(12) ) +#define BIT_SLP_AUD_PA_PD_EN ( BIT(11) ) +#define BIT_SLP_AUD_OVP_PD_PD_EN ( BIT(10) ) +#define BIT_SLP_AUD_OVP_LDO_PD_EN ( BIT(9) ) +#define BIT_SLP_AUD_LDOCG_PD_PD_EN ( BIT(8) ) +#define BIT_SLP_AUD_VB_PD_EN ( BIT(7) ) +#define BIT_SLP_AUD_VBO_PD_EN ( BIT(6) ) +#define BIT_SLP_AUD_HEADMICBIAS_PD_EN ( BIT(5) ) +#define BIT_SLP_AUD_HEADMIC_SLEEP_PD_EN ( BIT(4) ) +#define BIT_SLP_AUD_PLGPD_PD_EN ( BIT(3) ) +#define BIT_SLP_AUD_VB_NLEAK_PD ( BIT(2) ) +#define BITS_SLP_AUD_PMUR0_PD_EN(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL0 */ +#define BITS_SLP_DCDCCORE_VOL_DROP_CNT(_x_)( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_PWR_OFF_SEQ_EN ( BIT(2) ) +#define BIT_DCDC_CORE_SLP_OUT_STEP_EN ( BIT(1) ) +#define BIT_DCDC_CORE_SLP_IN_STEP_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL1 */ +#define BITS_DCDC_CORE_CAL_DS_SW(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CTRL_DS_SW(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL2 */ +#define BITS_DCDC_CORE_CTRL_SLP_STEP3(_x_)( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_DCDC_CORE_CTRL_SLP_STEP2(_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CTRL_SLP_STEP1(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL3 */ +#define BITS_DCDC_CORE_CTRL_SLP_STEP5(_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CTRL_SLP_STEP4(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL4 */ +#define BITS_DCDC_CORE_CAL_SLP_STEP3(_x_)( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_DCDC_CORE_CAL_SLP_STEP2(_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CAL_SLP_STEP1(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL5 */ +#define BITS_DCDC_CORE_CAL_SLP_STEP5(_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CAL_SLP_STEP4(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_PWR_SEL */ +#define BIT_LDO_GEN0_SW_SEL ( BIT(13) ) +#define BIT_LDO_GEN1_SW_SEL ( BIT(12) ) +#define BIT_LDO_RF0_SW_SEL ( BIT(11) ) +#define BIT_LDO_VDD18_SW_SEL ( BIT(10) ) +#define BIT_LDO_VDD28_SW_SEL ( BIT(9) ) +#define BIT_LDO_DCXO_SW_SEL ( BIT(8) ) +#define BIT_LDO_EMMCCORE_SW_SEL ( BIT(7) ) +#define BIT_LDO_VDD25_SW_SEL ( BIT(6) ) +#define BIT_DCDC_RF_SW_SEL ( BIT(5) ) +#define BIT_DCDC_GEN_SW_SEL ( BIT(4) ) +#define BIT_DCDC_MEM_SW_SEL ( BIT(3) ) +#define BIT_DCDC_ARM_SW_SEL ( BIT(2) ) +#define BIT_DCDC_CORE_SLP_SW_SEL ( BIT(1) ) +#define BIT_DCDC_CORE_NOR_SW_SEL ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN0 */ +#define BIT_LDO_XTL_EN ( BIT(15) ) +#define BIT_LDO_GEN0_EXT_XTL0_EN ( BIT(14) ) +#define BIT_LDO_GEN0_XTL1_EN ( BIT(13) ) +#define BIT_LDO_GEN0_XTL0_EN ( BIT(12) ) +#define BIT_LDO_GEN1_EXT_XTL0_EN ( BIT(11) ) +#define BIT_LDO_GEN1_XTL1_EN ( BIT(10) ) +#define BIT_LDO_GEN1_XTL0_EN ( BIT(9) ) +#define BIT_LDO_DCXO_EXT_XTL0_EN ( BIT(8) ) +#define BIT_LDO_DCXO_XTL1_EN ( BIT(7) ) +#define BIT_LDO_DCXO_XTL0_EN ( BIT(6) ) +#define BIT_LDO_VDD18_EXT_XTL0_EN ( BIT(5) ) +#define BIT_LDO_VDD18_XTL1_EN ( BIT(4) ) +#define BIT_LDO_VDD18_XTL0_EN ( BIT(3) ) +#define BIT_LDO_VDD28_EXT_XTL0_EN ( BIT(2) ) +#define BIT_LDO_VDD28_XTL1_EN ( BIT(1) ) +#define BIT_LDO_VDD28_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN1 */ +#define BIT_LDO_RF0_EXT_XTL0_EN ( BIT(14) ) +#define BIT_LDO_RF0_XTL1_EN ( BIT(13) ) +#define BIT_LDO_RF0_XTL0_EN ( BIT(12) ) +#define BIT_LDO_WIFIPA_EXT_XTL0_EN ( BIT(11) ) +#define BIT_LDO_WIFIPA_XTL1_EN ( BIT(10) ) +#define BIT_LDO_WIFIPA_XTL0_EN ( BIT(9) ) +#define BIT_LDO_SIM2_EXT_XTL0_EN ( BIT(8) ) +#define BIT_LDO_SIM2_XTL1_EN ( BIT(7) ) +#define BIT_LDO_SIM2_XTL0_EN ( BIT(6) ) +#define BIT_LDO_SIM1_EXT_XTL0_EN ( BIT(5) ) +#define BIT_LDO_SIM1_XTL1_EN ( BIT(4) ) +#define BIT_LDO_SIM1_XTL0_EN ( BIT(3) ) +#define BIT_LDO_SIM0_EXT_XTL0_EN ( BIT(2) ) +#define BIT_LDO_SIM0_XTL1_EN ( BIT(1) ) +#define BIT_LDO_SIM0_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN2 */ +#define BIT_LDO_VDD25_EXT_XTL0_EN ( BIT(11) ) +#define BIT_LDO_VDD25_XTL1_EN ( BIT(10) ) +#define BIT_LDO_VDD25_XTL0_EN ( BIT(9) ) +#define BIT_DCDC_RF_EXT_XTL0_EN ( BIT(8) ) +#define BIT_DCDC_RF_XTL1_EN ( BIT(7) ) +#define BIT_DCDC_RF_XTL0_EN ( BIT(6) ) +#define BIT_XO_EXT_XTL0_EN ( BIT(5) ) +#define BIT_XO_XTL1_EN ( BIT(4) ) +#define BIT_XO_XTL0_EN ( BIT(3) ) +#define BIT_BG_EXT_XTL0_EN ( BIT(2) ) +#define BIT_BG_XTL1_EN ( BIT(1) ) +#define BIT_BG_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN3 */ +#define BIT_DCDC_CON_EXT_XTL0_EN ( BIT(14) ) +#define BIT_DCDC_CON_XTL1_EN ( BIT(13) ) +#define BIT_DCDC_CON_XTL0_EN ( BIT(12) ) +#define BIT_DCDC_WPA_EXT_XTL0_EN ( BIT(11) ) +#define BIT_DCDC_WPA_XTL1_EN ( BIT(10) ) +#define BIT_DCDC_WPA_XTL0_EN ( BIT(9) ) +#define BIT_DCDC_MEM_EXT_XTL0_EN ( BIT(8) ) +#define BIT_DCDC_MEM_XTL1_EN ( BIT(7) ) +#define BIT_DCDC_MEM_XTL0_EN ( BIT(6) ) +#define BIT_DCDC_GEN_EXT_XTL0_EN ( BIT(5) ) +#define BIT_DCDC_GEN_XTL1_EN ( BIT(4) ) +#define BIT_DCDC_GEN_XTL0_EN ( BIT(3) ) +#define BIT_DCDC_CORE_EXT_XTL0_EN ( BIT(2) ) +#define BIT_DCDC_CORE_XTL1_EN ( BIT(1) ) +#define BIT_DCDC_CORE_XTL0_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_32KLESS_CTRL0 */ +#define BIT_RC_MODE_WR_ACK_FLAG ( BIT(14) ) +#define BIT_XO_LOW_CUR_FLAG ( BIT(13) ) +#define BIT_XO_LOW_CUR_FRC_RTCSET ( BIT(12) ) +#define BIT_XO_LOW_CUR_FRC_RTCCLR ( BIT(11) ) +#define BIT_RC_MODE_WR_ACK_FLAG_CLR ( BIT(10) ) +#define BIT_XO_LOW_CUR_FLAG_CLR ( BIT(9) ) +#define BIT_XO_LOW_CUR_CNT_CLR ( BIT(8) ) +#define BIT_LDO_DCXO_LP_PD_RTCSET ( BIT(7) ) +#define BIT_LDO_DCXO_LP_PD_RTCCLR ( BIT(6) ) +#define BIT_SLP_XO_LOW_CUR_EN ( BIT(5) ) +#define BIT_XO_LOW_CUR_EN ( BIT(3) ) +#define BIT_EXT_32K_PD ( BIT(2) ) +#define BIT_RC_32K_SEL ( BIT(1) ) +#define BIT_RC_32K_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_32KLESS_CTRL1 */ +#define BITS_RC_MODE(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_32KLESS_CTRL2 */ +#define BITS_XO_LOW_CUR_CNT_LOW(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_32KLESS_CTRL3 */ +#define BITS_XO_LOW_CUR_CNT_HIGH(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_AUXAD_CTL */ +#define BIT_AUXAD_CURRENTSEN_EN ( BIT(6) ) +#define BIT_AUXAD_CURRENTSEL ( BIT(5) ) +#define BITS_AUXAD_CURRENT_IBS(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_XTL_WAIT_CTRL */ +#define BIT_SLP_XTLBUF_PD_EN ( BIT(9) ) +#define BIT_XTL_EN ( BIT(8) ) +#define BITS_XTL_WAIT(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_RGB_CTRL */ +#define BIT_RTC_PWM0_EN ( BIT(15) ) +#define BIT_PWM0_EN ( BIT(14) ) +#define BIT_IB_REX_EN ( BIT(12) ) +#define BIT_IB_TRIM_EM_SEL ( BIT(11) ) +#define BITS_RGB_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) ) +#define BIT_SLP_RGB_PD_EN ( BIT(2) ) +#define BIT_RGB_PD_HW_EN ( BIT(1) ) +#define BIT_RGB_PD_SW ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_WHTLED_CTRL */ +#define BITS_IB_TRIM(_x_) ( (_x_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_WHTLED_SERIES_EN ( BIT(8) ) +#define BIT_WHTLED_PD_SEL ( BIT(7) ) +#define BIT_WHTLED_BOOST_EN ( BIT(8) ) +#define BITS_WHTLED_V(_x_) ( (_x_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_WHTLED_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_KPLED_CTRL */ +#define BITS_KPLED_V(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_KPLED_PD ( BIT(11) ) +#define BIT_KPLED_PULLDOWN_EN ( BIT(10) ) +#define BIT_SLP_LDOKPLED_PD_EN ( BIT(9) ) +#define BIT_LDO_KPLED_PD ( BIT(8) ) +#define BITS_LDO_KPLED_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_VIBR_CTRL0 */ +#define BITS_CUR_DRV_CAL_SEL(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BIT_VIBR_PULLDOWN_EN ( BIT(11) ) +#define BIT_VIBR_PULLUP_EN ( BIT(10) ) +#define BIT_SLP_LDOVIBR_PD_EN ( BIT(9) ) +#define BIT_LDO_VIBR_PD ( BIT(8) ) +#define BITS_LDO_VIBR_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_AUDIO_CTRL0 */ +#define BIT_AUD_SLP_APP_RST_EN ( BIT(15) ) +#define BITS_CLK_AUD_HBD_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_CLK_AUD_LOOP_INV_EN ( BIT(4) ) +#define BIT_CLK_AUDIF_TX_INV_EN ( BIT(3) ) +#define BIT_CLK_AUDIF_RX_INV_EN ( BIT(2) ) +#define BIT_CLK_AUD_6P5M_TX_INV_EN ( BIT(1) ) +#define BIT_CLK_AUD_6P5M_RX_INV_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_AUDIO_CTRL1 */ +#define BIT_IMPD_ADC_SOFT_RST ( BIT(7) ) +#define BIT_HEAD_INSERT_EIC_EN ( BIT(6) ) +#define BIT_AUDIO_CHP_CLK_DIV_EN ( BIT(5) ) +#define BITS_AUDIO_CHP_CLK_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL0 */ +#define BIT_CHGLDO_DIS ( BIT(15) ) +#define BITS_CHGR_CV_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CHGR_END_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BIT_CHGR_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL1 */ +#define BITS_CHGR_CC_I(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_VBAT_OVP_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_VCHG_OVP_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_CTRL2 */ +#define BIT_CHGR_INT_EN ( BIT(15) ) +#define BIT_CHGR_DRV ( BIT(7) ) +#define BIT_CHGR_OSC ( BIT(6) ) +#define BITS_CHGR_DPM(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CHGR_ITERM(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BIT_CHGR_CC_EN ( BIT(1) ) +#define BIT_RECHG ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_DET_FGU_CTRL */ +#define BIT_FGUA_SOFT_RST ( BIT(13) ) +#define BIT_LDO_FGU_PD ( BIT(12) ) +#define BIT_SD_CHOP_CAP_EN ( BIT(8) ) +#define BITS_SD_CLK_P(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BIT_SD_DCOFFSET_EN ( BIT(5) ) +#define BIT_SD_CHOP_EN ( BIT(4) ) +#define BIT_DP_DM_AUX_EN ( BIT(1) ) +#define BIT_DP_DM_SW_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_CHGR_STATUS */ +#define BIT_CHG_DET_DONE ( BIT(11) ) +#define BIT_DP_LOW ( BIT(10) ) +#define BIT_DCP_DET ( BIT(9) ) +#define BIT_CHG_DET ( BIT(8) ) +#define BIT_SDP_INT ( BIT(7) ) +#define BIT_DCP_INT ( BIT(6) ) +#define BIT_CDP_INT ( BIT(5) ) +#define BIT_CHGR_CV_STATUS ( BIT(4) ) +#define BIT_CHGR_ON ( BIT(3) ) +#define BIT_CHGR_INT ( BIT(2) ) +#define BIT_VBAT_OVI ( BIT(1) ) +#define BIT_VCHG_OVI ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_MIXED_CTRL0 */ +#define BIT_PTEST_PD_RTCSET ( BIT(15) ) +#define BIT_DCDC_V_CTRL_MODE ( BIT(14) ) +#define BIT_LDO_RAMP_EN ( BIT(13) ) +#define BIT_BG_LP_EN ( BIT(12) ) +#define BITS_VBAT_CRASH_V(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BIT_OVLO_EN ( BIT(9) ) +#define BITS_OVLO_CAL(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_OVLO_V(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_OVLO_T(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_MIXED_CTRL1 */ +#define BITS_XOSC32K_CTL(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_BATON_T(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BIT_BATDET_LDO_SEL ( BIT(9) ) +#define BIT_THM_CHIP_PD_FLAG ( BIT(8) ) +#define BIT_THM_CHIP_PD_FLAG_CLR ( BIT(7) ) +#define BITS_THM_CAL_SEL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)) ) +#define BIT_THM_AUTO_PD_EN ( BIT(4) ) +#define BIT_ALL_GPI_DEB ( BIT(3) ) +#define BIT_GPI_DEBUG_EN ( BIT(2) ) +#define BIT_ALL_INT_DEB ( BIT(1) ) +#define BIT_INT_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_SWRST_CTRL */ +#define BIT_POR_RTC_PD ( BIT(15) ) +#define BITS_POR_RTC_I(_x_) ( (_x_) << 13 & (BIT(13)|BIT(14)) ) +#define BIT_SW_RST_GEN1_PD_EN ( BIT(12) ) +#define BIT_SW_RST_GEN0_PD_EN ( BIT(11) ) +#define BIT_EXT_RSTN_PD_EN ( BIT(10) ) +#define BIT_PB_7S_RST_PD_EN ( BIT(9) ) +#define BIT_SW_RST_EMMCCORE_PD_EN ( BIT(8) ) +#define BIT_KEY2_7S_RST_EN ( BIT(7) ) +#define BIT_WDG_RST_PD_EN ( BIT(6) ) +#define BITS_SW_RST_PD_THRESHOLD(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register ANA_REG_GLB_POR_RST_MONITOR */ +#define BITS_POR_RST_MONITOR(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_WDG_RST_MONITOR */ +#define BITS_WDG_RST_MONITOR(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_POR_PIN_RST_MONITOR */ +#define BITS_POR_PIN_RST_MONITOR(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_POR_SRC_FLAG */ +#define BIT_POR_SW_FORCE_ON ( BIT(15) ) +#define BITS_POR_SRC_FLAG(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_POR_7S_CTRL */ +#define BIT_PBINT_7S_FLAG_CLR ( BIT(15) ) +#define BIT_EXT_RSTN_FLAG_CLR ( BIT(14) ) +#define BIT_CHGR_INT_FLAG_CLR ( BIT(13) ) +#define BIT_PBINT2_FLAG_CLR ( BIT(12) ) +#define BIT_PBINT_FLAG_CLR ( BIT(11) ) +#define BIT_PBINT_7S_RST_SWMODE ( BIT(8) ) +#define BITS_PBINT_7S_RST_THRESHOLD(_x_)( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_PBINT_7S_AUTO_ON_EN ( BIT(2) ) +#define BIT_PBINT_7S_RST_DISABLE ( BIT(1) ) +#define BIT_PBINT_7S_RST_MODE ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_HWRST_RTC */ +#define BITS_HWRST_RTC_REG_STS(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_HWRST_RTC_REG_SET(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register ANA_REG_GLB_CHIP_ID_LOW */ +#define BITS_CHIP_ID_LOW(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_CHIP_ID_HIGH */ +#define BITS_CHIP_ID_HIGH(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_ARM_MF_REG */ +#define BITS_ARM_MF_REG(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_ARCH_EN */ +#define BIT_ARCH_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_MCU_WR_PROT_VALUE */ +#define BIT_MCU_WR_PROT ( BIT(15) ) +#define BITS_MCU_WR_PROT_VALUE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_PWR_WR_PROT_VALUE */ +#define BIT_PWR_WR_PROT ( BIT(15) ) +#define BITS_PWR_WR_PROT_VALUE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register ANA_REG_GLB_SMPL_CTRL0 */ +#define BITS_SMPL_MODE(_x_) ( (_x_) << 0 ) + +/* bits definitions for register ANA_REG_GLB_SMPL_CTRL1 */ +#define BIT_SMPL_PWR_ON_FLAG ( BIT(15) ) +#define BIT_SMPL_MODE_WR_ACK_FLAG ( BIT(14) ) +#define BIT_SMPL_PWR_ON_FLAG_CLR ( BIT(13) ) +#define BIT_SMPL_MODE_WR_ACK_FLAG_CLR ( BIT(12) ) +#define BIT_SMPL_PWR_ON_SET ( BIT(11) ) +#define BIT_SMPL_EN ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_RTC_RST0 */ +#define BITS_RTC_CLK_FLAG_SET(_x_) ( (_x_) << 15 & (BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_RTC_RST1 */ +#define BITS_RTC_CLK_FLAG_CLR(_x_) ( (_x_) << 15 & (BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_RTC_RST2 */ +#define BITS_RTC_CLK_FLAG_RTC(_x_) ( (_x_) << 15 & (BIT(15)) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SHPT_PD1 */ +#define BIT_LDO_USB_SHPT_PD ( BIT(12) ) +#define BIT_LDO_DCXO_SHPT_PD ( BIT(11) ) +#define BIT_LDO_WIFIPA_SHPT_PD ( BIT(10) ) +#define BIT_LDO_VDD25_SHPT_PD ( BIT(9) ) +#define BIT_LDO_VDD28_SHPT_PD ( BIT(8) ) +#define BIT_LDO_SDIO_SHPT_PD ( BIT(7) ) +#define BIT_LDO_SDCORE_SHPT_PD ( BIT(6) ) +#define BIT_LDO_EMMCCORE_SHPT_PD ( BIT(5) ) +#define BIT_LDO_SIM2_SHPT_PD ( BIT(4) ) +#define BIT_LDO_SIM1_SHPT_PD ( BIT(3) ) +#define BIT_LDO_SIM0_SHPT_PD ( BIT(2) ) +#define BIT_LDO_CAMMOT_SHPT_PD ( BIT(1) ) +#define BIT_LDO_CAMA_SHPT_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_LDO_SHPT_PD2 */ +#define BIT_LDO_RF0_SHPT_PD ( BIT(7) ) +#define BIT_LDO_GEN1_SHPT_PD ( BIT(6) ) +#define BIT_LDO_GEN0_SHPT_PD ( BIT(5) ) +#define BIT_LDO_CAMD_SHPT_PD ( BIT(4) ) +#define BIT_LDO_VDD18_SHPT_PD ( BIT(3) ) +#define BIT_LDO_CAMIO_SHPT_PD ( BIT(2) ) +#define BIT_LDO_KPLED_SHPT_PD ( BIT(1) ) +#define BIT_LDO_VIBR_SHPT_PD ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_BATDET_CUR_CTRL */ +#define BIT_BATDET_CUR_EN ( BIT(4) ) +#define BITS_BATDET_CUR_I(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register ANA_REG_GLB_RTC_CLK_STOP */ +#define BIT_RTC_CLK_STOP_FLAG ( BIT(7) ) +#define BITS_RTC_CLK_STOP_THRESHOLD(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) + +/* bits definitions for register ANA_REG_GLB_VBAT_DROP_CNT */ +#define BITS_VBAT_DROP_CNT(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_DISCHRG */ +#define BITS_DCDC_ARM_DISCHRG(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_DCDC_CORE_DISCHRG(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_DCDC_MEM_DISCHRG(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_DCDC_GEN_DISCHRG(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_DCDC_RF_DISCHRG(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_DCDC_CON_DISCHRG(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_DCDC_WPA_DISCHRG(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CORE_ADI */ +#define BITS_DCDC_CORE_CTL_SW_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CORE_CAL_SW_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_ARM_ADI */ +#define BITS_DCDC_ARM_CTL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_ARM_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_MEM_ADI */ +#define BITS_DCDC_MEM_CTRL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_MEM_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_GEN_ADI */ +#define BITS_DCDC_GEN_CTRL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_GEN_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_WPA_ADI */ +#define BITS_DCDC_WPA_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_WPA_DCM_ADI */ +#define BIT_DCDC_WPA_DCM_ADI ( BIT(0) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_CON_ADI */ +#define BITS_DCDC_CON_CTRL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_CON_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register ANA_REG_GLB_DCDC_RF_ADI */ +#define BITS_DCDC_RF_CTRL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DCDC_RF_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* vars definitions for controller ANA_REGS_GLB */ + +#endif /* __ANA_REGS_GLB_H__ */ diff --git a/include/soc/sprd/chip_x35lt8/__regs_aon_apb_rf.h b/include/soc/sprd/chip_x35lt8/__regs_aon_apb_rf.h new file mode 100644 index 00000000..43bb0138 --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_aon_apb_rf.h @@ -0,0 +1,886 @@ +/* the head file modifier: g 2015-03-19 15:30:08*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_AON_APB_RF_HEADFILE_H__ +#define __H_REGS_AON_APB_RF_HEADFILE_H__ __FILE__ + +#define REGS_AON_APB_RF + +/* registers definitions for AON_APB_RF */ +#define REG_AON_APB_APB_EB0 SCI_ADDR(REGS_AON_APB_BASE, 0x0000)/*AHB_EB0*/ +#define REG_AON_APB_APB_EB1 SCI_ADDR(REGS_AON_APB_BASE, 0x0004)/*AHB_EB1*/ +#define REG_AON_APB_APB_RST0 SCI_ADDR(REGS_AON_APB_BASE, 0x0008)/*AHB_RST0*/ +#define REG_AON_APB_APB_RST1 SCI_ADDR(REGS_AON_APB_BASE, 0x000C)/*AHB_RST1*/ +#define REG_AON_APB_APB_RTC_EB SCI_ADDR(REGS_AON_APB_BASE, 0x0010)/*APB_RTC_EB*/ +#define REG_AON_APB_REC_26MHZ_BUF_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0014)/*REC_26MHZ_BUF_CFG*/ +#define REG_AON_APB_SINDRV_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0018)/*SINDRV_CTRL*/ +#define REG_AON_APB_ADA_SEL_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x001C)/*ADA_SEL_CTRL*/ +#define REG_AON_APB_VBC_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0020)/*VBC_CTRL*/ +#define REG_AON_APB_PWR_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0024)/*PWR_CTRL*/ +#define REG_AON_APB_TS_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0028)/*TS_CFG*/ +#define REG_AON_APB_BOOT_MODE SCI_ADDR(REGS_AON_APB_BASE, 0x002C)/*BOOT_MODE*/ +#define REG_AON_APB_BB_BG_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0030)/*BB_BG_CTRL*/ +#define REG_AON_APB_CP_ARM_JTAG_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0034)/*CP_ARM_JTAG_CTRL*/ +#define REG_AON_APB_PLL_SOFT_CNT_DONE SCI_ADDR(REGS_AON_APB_BASE, 0x0038)/*PLL_SOFT_CNT_DONE*/ +#define REG_AON_APB_DCXO_LC_REG0 SCI_ADDR(REGS_AON_APB_BASE, 0x003C)/*DCXO_LC_REG0*/ +#define REG_AON_APB_DCXO_LC_REG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0040)/*DCXO_LC_REG1*/ +#define REG_AON_APB_MPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0044)/*MPLL_CFG1*/ +#define REG_AON_APB_MPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0048)/*MPLL_CFG2*/ +#define REG_AON_APB_DPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x004C)/*DPLL_CFG1*/ +#define REG_AON_APB_DPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0050)/*DPLL_CFG2*/ +#define REG_AON_APB_TWPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0054)/*TWPLL_CFG1*/ +#define REG_AON_APB_TWPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0058)/*TWPLL_CFG2*/ +#define REG_AON_APB_LTEPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x005C)/*LTEPLL_CFG1*/ +#define REG_AON_APB_LTEPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0060)/*LTEPLL_CFG2*/ +#define REG_AON_APB_LVDSDISPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0064)/*LVDSDISPLL_CFG1*/ +#define REG_AON_APB_LVDSDISPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0068)/*LVDSDISPLL_CFG2*/ +#define REG_AON_APB_AON_REG_PROT SCI_ADDR(REGS_AON_APB_BASE, 0x006C)/*AON_REG_PROT*/ +#define REG_AON_APB_LDSP_BOOT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x0070)/*LDSP_BOOT_EN*/ +#define REG_AON_APB_LDSP_BOOT_VEC SCI_ADDR(REGS_AON_APB_BASE, 0x0074)/*LDSP_BOOT_VEC*/ +#define REG_AON_APB_LDSP_RST SCI_ADDR(REGS_AON_APB_BASE, 0x0078)/*LDSP_RST*/ +#define REG_AON_APB_LDSP_MTX_CTRL1 SCI_ADDR(REGS_AON_APB_BASE, 0x007C)/*LDSP_MTX_CT1RL1*/ +#define REG_AON_APB_LDSP_MTX_CTRL2 SCI_ADDR(REGS_AON_APB_BASE, 0x0080)/*LDSP_MTX_CTRL2*/ +#define REG_AON_APB_LDSP_MTX_CTRL3 SCI_ADDR(REGS_AON_APB_BASE, 0x0084)/*LDSP_MTX_CTRL3*/ +#define REG_AON_APB_AON_CGM_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0088)/*AON_CGM_CFG*/ +#define REG_AON_APB_LACC_MTX_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x008C)/*LACC_MTX_CTRL*/ +#define REG_AON_APB_CORTEX_MTX_CTRL1 SCI_ADDR(REGS_AON_APB_BASE, 0x0090)/*CORTEX_MTX_CTRL1*/ +#define REG_AON_APB_CORTEX_MTX_CTRL2 SCI_ADDR(REGS_AON_APB_BASE, 0x0094)/*CORTEX_MTX_CTRL2*/ +#define REG_AON_APB_CORTEX_MTX_CTRL3 SCI_ADDR(REGS_AON_APB_BASE, 0x0098)/*CORTEX_MTX_CTRL3*/ +#define REG_AON_APB_CA5_TCLK_DLY_LEN SCI_ADDR(REGS_AON_APB_BASE, 0x009C)/*CA5_TCLK_DLY_LEN*/ +#define REG_AON_APB_PLD_ID_0 SCI_ADDR(REGS_AON_APB_BASE, 0x00E0)/*PLD_ID_0*/ +#define REG_AON_APB_PLD_ID_1 SCI_ADDR(REGS_AON_APB_BASE, 0x00E4)/*PLD_ID_1*/ +#define REG_AON_APB_PROJ_ID_0 SCI_ADDR(REGS_AON_APB_BASE, 0x00E8)/*PROJ_ID_0*/ +#define REG_AON_APB_PROJ_ID_1 SCI_ADDR(REGS_AON_APB_BASE, 0x00EC)/*PROJ_ID_1*/ +#define REG_AON_APB_DERIVED_ID SCI_ADDR(REGS_AON_APB_BASE, 0x00F4)/*DERIVED_ID*/ +#define REG_AON_APB_MANU_ID SCI_ADDR(REGS_AON_APB_BASE, 0x00F8)/*MANU_ID*/ +#define REG_AON_APB_IMP_ID SCI_ADDR(REGS_AON_APB_BASE, 0x00FC)/*IMP_ID*/ +#define REG_AON_APB_CCIR_RCVR_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0100)/*CCIR_RCVR_CFG*/ +#define REG_AON_APB_PLL_BG_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0108)/*PLL_BG_CFG*/ +#define REG_AON_APB_LVDSDIS_SEL SCI_ADDR(REGS_AON_APB_BASE, 0x010C)/*LVDSDIS_SEL*/ +#define REG_AON_APB_DJTAG_MUX_SEL SCI_ADDR(REGS_AON_APB_BASE, 0x0110)/*DJTAG_MUX_SEL*/ +#define REG_AON_APB_ARM7_SYS_SOFT_RST SCI_ADDR(REGS_AON_APB_BASE, 0x0114)/*ARM7_SYS_SOFT_RST*/ +#define REG_AON_APB_CP1_CP0_ADDR_MSB SCI_ADDR(REGS_AON_APB_BASE, 0x0118)/*CP1_CP0_ADDR_MSB*/ +#define REG_AON_APB_AON_DMA_INT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x011C)/*AON_DMA_INT_EN*/ +#define REG_AON_APB_EMC_AUTO_GATE_EN SCI_ADDR(REGS_AON_APB_BASE, 0x0120)/*EMC_AUTO_GATE_EN*/ +#define REG_AON_APB_ARM7_CFG_BUS SCI_ADDR(REGS_AON_APB_BASE, 0x0124)/*ARM7_CFG_BUS*/ +#define REG_AON_APB_RTC4M_0_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0128)/*RTC4M_0_CFG*/ +#define REG_AON_APB_RTC4M_1_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x012C)/*RTC4M_1_CFG*/ +#define REG_AON_APB_APB_RST2 SCI_ADDR(REGS_AON_APB_BASE, 0x0130)/*AHB_RST2*/ +#define REG_AON_APB_OSC_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0134)/*CA53_OSC_CTRL*/ +#define REG_AON_APB_OSC_OBS SCI_ADDR(REGS_AON_APB_BASE, 0x0138)/*CA53_OSC_OBS*/ +#define REG_AON_APB_AP_SDISABLE SCI_ADDR(REGS_AON_APB_BASE, 0x013C)/*APCPU_SDISABLE*/ +#define REG_AON_APB_MPLL0_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0140)/*MPLL0_CFG1*/ +#define REG_AON_APB_MPLL0_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0144)/*MPLL0_CFG2*/ +#define REG_AON_APB_GPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0148)/*GPLL_CFG1*/ +#define REG_AON_APB_GPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x014C)/*GPLL_CFG2*/ +#define REG_AON_APB_UPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0150)/*UPLL_CFG1*/ +#define REG_AON_APB_UPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0154)/*UPLL_CFG2*/ +#define REG_AON_APB_APCPU_CCI_CKG_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0158)/*APCPU_CCI_CKG_CFG*/ +#define REG_AON_APB_AP_MODULE_FOLLOW_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x15C)/*AP_MODULE_FOLLOW_CTRL*/ +#define REG_AON_APB_AVS_SOFT_RST SCI_ADDR(REGS_AON_APB_BASE, 0x0160)/*AVS_SOFT_RST*/ +#define REG_AON_APB_AP_IRAM_REMAP SCI_ADDR(REGS_AON_APB_BASE, 0x0164)/*AP_IRAM_REMAP*/ +#define REG_AON_APB_APCPU_BIG_SOFT_RST SCI_ADDR(REGS_AON_APB_BASE, 0x0168)/*APCPU_BIG_SOFT_RST*/ +#define REG_AON_APB_APCPU_LIT_SOFT_RST SCI_ADDR(REGS_AON_APB_BASE, 0x016c)/*APCPU_LIT_SOFT_RST*/ +#define REG_AON_APB_APCPU_TOP_SOFT_RST SCI_ADDR(REGS_AON_APB_BASE, 0x0170)/*APCPU_TOP_SOFT_RST*/ +#define REG_AON_APB_CA5_BIG_THM_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x01A0)/*CA5_BIG_THM_CTRL*/ +#define REG_AON_APB_CA5_LIT_THM_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x01A4)/*CA5_LIT_THM_CTRL*/ +#define REG_AON_APB_A53_BIGCORE_VDROP SNSR_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x01A8)/*A53_BIGCORE_VDROP SNSR_CTRL*/ +#define REG_AON_APB_A53_LITCORE_VDROP SNSR_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x01AC)/*A53_LITCORE_VDROP SNSR_CTRL*/ +#define REG_AON_APB_A53_AUTO_REG_SAVE_CRTL SCI_ADDR(REGS_AON_APB_BASE, 0x01B0)/*A53_AUTO_REG_SAVE_CRTL*/ +#define REG_AON_APB_CSSYS_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x01B4)/*CSSYS_CFG*/ +#define REG_AON_APB_REDUN_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x01B8)/*REDUN_CFG*/ +#define REG_AON_APB_AP_WPROT_EN1 SCI_ADDR(REGS_AON_APB_BASE, 0x3004)/*AP_WPROT_EN1*/ +#define REG_AON_APB_CP0_WPROT_EN1 SCI_ADDR(REGS_AON_APB_BASE, 0x3008)/*CP0_WPROT_EN1*/ +#define REG_AON_APB_CP1_WPROT_EN1 SCI_ADDR(REGS_AON_APB_BASE, 0x300C)/*CP1_WPROT_EN1*/ +#define REG_AON_APB_IO_DLY_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x3014)/*IO_DLY_CTRL*/ +#define REG_AON_APB_AP_WPROT_EN0 SCI_ADDR(REGS_AON_APB_BASE, 0x3018)/*AP_WPROT_EN0*/ +#define REG_AON_APB_CP0_WPROT_EN0 SCI_ADDR(REGS_AON_APB_BASE, 0x3020)/*CP0_WPROT_EN0*/ +#define REG_AON_APB_CP1_WPROT_EN0 SCI_ADDR(REGS_AON_APB_BASE, 0x3024)/*CP1_WPROT_EN0*/ +#define REG_AON_APB_PMU_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x302C)/*PMU_RST_MONITOR*/ +#define REG_AON_APB_THM_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3030)/*THM_RST_MONITOR*/ +#define REG_AON_APB_AP_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3034)/*AP_RST_MONITOR*/ +#define REG_AON_APB_APCPU_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3038)/*APCPU_RST_MONITOR*/ +#define REG_AON_APB_BOND_OPT0 SCI_ADDR(REGS_AON_APB_BASE, 0x303C)/*BOND_OPT0*/ +#define REG_AON_APB_BOND_OPT1 SCI_ADDR(REGS_AON_APB_BASE, 0x3040)/*BOND_OPT1*/ +#define REG_AON_APB_RES_REG0 SCI_ADDR(REGS_AON_APB_BASE, 0x3044)/*RES_REG0*/ +#define REG_AON_APB_RES_REG1 SCI_ADDR(REGS_AON_APB_BASE, 0x3048)/*RES_REG1*/ +#define REG_AON_APB_AON_QOS_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x304C)/*AON_QOS_CFG*/ +#define REG_AON_APB_BB_LDO_CAL_START SCI_ADDR(REGS_AON_APB_BASE, 0x3050)/*BB_LDO_CAL_START*/ +#define REG_AON_APB_AON_MTX_PROT_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3058)/*AON_MTX_PROT_CFG*/ +#define REG_AON_APB_LVDS_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3060)/*LVDS_CFG*/ +#define REG_AON_APB_PLL_LOCK_OUT_SEL SCI_ADDR(REGS_AON_APB_BASE, 0x3064)/*PLL_LOCK_OUT_SEL*/ +#define REG_AON_APB_RTC4M_RC_VAL SCI_ADDR(REGS_AON_APB_BASE, 0x3068)/*RTC4M_RC_VAL*/ +#define REG_AON_APB_PROT_BUS_SECURE_EN SCI_ADDR(REGS_AON_APB_BASE, 0x3080)/*PROT_BUS_SECURE_EN*/ +#define REG_AON_APB_PROT_ARM7_SPACE_EN SCI_ADDR(REGS_AON_APB_BASE, 0x3084)/*PROT_ARM7_SPACE_EN*/ +#define REG_AON_APB_AON_APB_RSV SCI_ADDR(REGS_AON_APB_BASE, 0x30F0)/*AON_APB_RSV*/ + + + +/* bits definitions for register REG_AON_APB_APB_EB0 */ +#define BIT_I2C_EB ( BIT(31) ) +#define BIT_APCPU_DAP_EB ( BIT(30) ) +#define BIT_APCPU_TS1_EB ( BIT(29) ) +#define BIT_APCPU_TS0_EB ( BIT(28) ) +#define BIT_CA7_DAP_EB BIT_APCPU_DAP_EB +#define BIT_CA7_TS1_EB BIT_APCPU_TS1_EB +#define BIT_CA7_TS0_EB BIT_APCPU_TS0_EB +#define BIT_GPU_EB ( BIT(27) ) +#define BIT_CKG_EB ( BIT(26) ) +#define BIT_AON_CKG_EB BIT_CKG_EB +#define BIT_MM_EB ( BIT(25) ) +#define BIT_AP_WDG_EB ( BIT(24) ) +#define BIT_MSPI_EB ( BIT(23) ) +#define BIT_SPLK_EB ( BIT(22) ) +#define BIT_IPI_EB ( BIT(21) ) +#define BIT_PIN_EB ( BIT(20) ) +#define BIT_VBC_EB ( BIT(19) ) +#define BIT_AUD_EB ( BIT(18) ) +#define BIT_AUDIF_EB ( BIT(17) ) +#define BIT_ADI_EB ( BIT(16) ) +#define BIT_INTC_EB ( BIT(15) ) +#define BIT_EIC_EB ( BIT(14) ) +#define BIT_EFUSE_EB ( BIT(13) ) +#define BIT_AP_TMR0_EB ( BIT(12) ) +#define BIT_AON_TMR_EB ( BIT(11) ) +#define BIT_AP_SYST_EB ( BIT(10) ) +#define BIT_AON_SYST_EB ( BIT(9) ) +#define BIT_KPD_EB ( BIT(8) ) +#define BIT_PWM3_EB ( BIT(7) ) +#define BIT_PWM2_EB ( BIT(6) ) +#define BIT_PWM1_EB ( BIT(5) ) +#define BIT_PWM0_EB ( BIT(4) ) +#define BIT_GPIO_EB ( BIT(3) ) +#define BIT_AON_GPIO_EB ( BIT_GPIO_EB ) +#define BIT_TPC_EB ( BIT(2) ) +#define BIT_FM_EB ( BIT(1) ) +#define BIT_ADC_EB ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_APB_EB1 */ +#define BIT_CODEC_EB ( BIT(31) ) +#define BIT_CSSYS_EB ( BIT(30) ) +#define BIT_CA53_LIT_AVS_EB ( BIT(29) ) +#define BIT_CA53_BIG_AVS_EB ( BIT(28) ) +#define BIT_ORP_JTAG_EB ( BIT(27) ) +#define BIT_CA5_TS0_EB ( BIT(26) ) +#define BIT_DEF_EB ( BIT(25) ) +#define BIT_LVDS_PLL_DIV_EN ( BIT(24) ) +#define BIT_ARM7_JTAG_EB ( BIT(23) ) +#define BIT_AON_DMA_EB ( BIT(22) ) +#define BIT_MBOX_EB ( BIT(21) ) +#define BIT_DJTAG_EB ( BIT(20) ) +#define BIT_RTC4M1_CAL_EB ( BIT(19) ) +#define BIT_RTC4M0_CAL_EB ( BIT(18) ) +#define BIT_MDAR_EB ( BIT(17) ) +#define BIT_LVDS_TCXO_EB ( BIT(16) ) +#define BIT_LVDS_TRX_EB ( BIT(15) ) +#define BIT_CA5_DAP_EB ( BIT(14) ) +#define BIT_GSP_EMC_EB ( BIT(13) ) +#define BIT_ZIP_EMC_EB ( BIT(12) ) +#define BIT_DISP_EMC_EB ( BIT(11) ) +#define BIT_AP_TMR2_EB ( BIT(10) ) +#define BIT_AP_TMR1_EB ( BIT(9) ) +#define BIT_APCPU_WDG_EB ( BIT(8) ) +#define BIT_CCI_EB ( BIT(7) ) +#define BIT_CA7_WDG_EB BIT_APCPU_WDG_EB +#define BIT_AVS_EB ( BIT(6) ) +#define BIT_PROBE_EB ( BIT(5) ) +#define BIT_AUX2_EB ( BIT(4) ) +#define BIT_AUX1_EB ( BIT(3) ) +#define BIT_AUX0_EB ( BIT(2) ) +#define BIT_THM_EB ( BIT(1) ) +#define BIT_PMU_EB ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_APB_RST0 */ +#define BIT_CA5_TS0_SOFT_RST ( BIT(31) ) +#define BIT_I2C_SOFT_RST ( BIT(30) ) +#define BIT_APCPU_TS1_SOFT_RST ( BIT(29) ) +#define BIT_APCPU_TS0_SOFT_RST ( BIT(28) ) +#define BIT_CA7_TS1_SOFT_RST BIT_APCPU_TS1_SOFT_RST +#define BIT_CA7_TS0_SOFT_RST BIT_APCPU_TS0_SOFT_RST +#define BIT_DAP_MTX_SOFT_RST ( BIT(27) ) +#define BIT_MSPI1_SOFT_RST ( BIT(26) ) +#define BIT_MSPI0_SOFT_RST ( BIT(25) ) +#define BIT_SPLK_SOFT_RST ( BIT(24) ) +#define BIT_IPI_SOFT_RST ( BIT(23) ) +#define BIT_CKG_SOFT_RST ( BIT(22) ) +#define BIT_AON_CKG_SOFT_RST BIT_CKG_SOFT_RST +#define BIT_PIN_SOFT_RST ( BIT(21) ) +#define BIT_VBC_SOFT_RST ( BIT(20) ) +#define BIT_AUD_SOFT_RST ( BIT(19) ) +#define BIT_AUDIF_SOFT_RST ( BIT(18) ) +#define BIT_ADI_SOFT_RST ( BIT(17) ) +#define BIT_INTC_SOFT_RST ( BIT(16) ) +#define BIT_EIC_SOFT_RST ( BIT(15) ) +#define BIT_EFUSE_SOFT_RST ( BIT(14) ) +#define BIT_AP_WDG_SOFT_RST ( BIT(13) ) +#define BIT_AP_TMR0_SOFT_RST ( BIT(12) ) +#define BIT_AON_TMR_SOFT_RST ( BIT(11) ) +#define BIT_AP_SYST_SOFT_RST ( BIT(10) ) +#define BIT_AON_SYST_SOFT_RST ( BIT(9) ) +#define BIT_KPD_SOFT_RST ( BIT(8) ) +#define BIT_PWM3_SOFT_RST ( BIT(7) ) +#define BIT_PWM2_SOFT_RST ( BIT(6) ) +#define BIT_PWM1_SOFT_RST ( BIT(5) ) +#define BIT_PWM0_SOFT_RST ( BIT(4) ) +#define BIT_GPIO_SOFT_RST ( BIT(3) ) +#define BIT_TPC_SOFT_RST ( BIT(2) ) +#define BIT_FM_SOFT_RST ( BIT(1) ) +#define BIT_ADC_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_APB_RST1 */ +#define BIT_RTC4M_ANA_SOFT_RST ( BIT(31) ) +#define BIT_DEF_SLV_INT_SOFT_CLR ( BIT(30) ) +#define BIT_DEF_SOFT_RST ( BIT(29) ) +#define BIT_ADC3_SOFT_RST ( BIT(28) ) +#define BIT_ADC2_SOFT_RST ( BIT(27) ) +#define BIT_ADC1_SOFT_RST ( BIT(26) ) +#define BIT_MBOX_SOFT_RST ( BIT(25) ) +#define BIT_RTC4M1_CAL_SOFT_RST ( BIT(23) ) +#define BIT_RTC4M0_CAL_SOFT_RST ( BIT(22) ) +#define BIT_LDSP_SYS_SOFT_RST ( BIT(21) ) +#define BIT_LCP_SYS_SOFT_RST ( BIT(20) ) +#define BIT_DAC3_SOFT_RST ( BIT(19) ) +#define BIT_DAC2_SOFT_RST ( BIT(18) ) +#define BIT_DAC1_SOFT_RST ( BIT(17) ) +#define BIT_ADC3_CAL_SOFT_RST ( BIT(16) ) +#define BIT_ADC2_CAL_SOFT_RST ( BIT(15) ) +#define BIT_ADC1_CAL_SOFT_RST ( BIT(14) ) +#define BIT_MDAR_SOFT_RST ( BIT(13) ) +#define BIT_LVDSDIS_SOFT_RST ( BIT(12) ) +#define BIT_BB_CAL_SOFT_RST ( BIT(11) ) +#define BIT_DCXO_LC_SOFT_RST ( BIT(10) ) +#define BIT_AP_TMR2_SOFT_RST ( BIT(9) ) +#define BIT_AP_TMR1_SOFT_RST ( BIT(8) ) +#define BIT_APCPU_WDG_SOFT_RST ( BIT(7) ) +#define BIT_CA7_WDG_SOFT_RST BIT_APCPU_WDG_SOFT_RST +#define BIT_AON_DMA_SOFT_RST ( BIT(6) ) +#define BIT_AVS_SOFT_RST ( BIT(5) ) +#define BIT_DMC_PHY_SOFT_RST ( BIT(4) ) +#define BIT_GPU_THMA_SOFT_RST ( BIT(3) ) +#define BIT_ARM_THMA_SOFT_RST ( BIT(2) ) +#define BIT_THM_SOFT_RST ( BIT(1) ) +#define BIT_PMU_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_APB_RTC_EB */ +#define BIT_CA53_BIG_THMA_RTC_EB ( BIT(20) ) +#define BIT_CP0_LTE_EB ( BIT(19) ) +#define BIT_BB_CAL_RTC_EB ( BIT(18) ) +#define BIT_DCXO_LC_RTC_EB ( BIT(17) ) +#define BIT_AP_TMR2_RTC_EB ( BIT(16) ) +#define BIT_AP_TMR1_RTC_EB ( BIT(15) ) +#define BIT_GPU_THMA_RTC_AUTO_EN ( BIT(14) ) +#define BIT_ARM_THMA_RTC_AUTO_EN ( BIT(13) ) +#define BIT_GPU_THMA_RTC_EB ( BIT(12) ) +#define BIT_CA53_LIT_THMA_RTC_EB ( BIT(11) ) +#define BIT_THM_RTC_EB ( BIT(10) ) +#define BIT_APCPU_WDG_RTC_EB ( BIT(9) ) +#define BIT_CA7_WDG_RTC_EB BIT_APCPU_WDG_RTC_EB +#define BIT_AP_WDG_RTC_EB ( BIT(8) ) +#define BIT_EIC_RTCDV5_EB ( BIT(7) ) +#define BIT_EIC_RTC_EB ( BIT(6) ) +#define BIT_AP_TMR0_RTC_EB ( BIT(5) ) +#define BIT_AON_TMR_RTC_EB ( BIT(4) ) +#define BIT_AP_SYST_RTC_EB ( BIT(3) ) +#define BIT_AON_SYST_RTC_EB ( BIT(2) ) +#define BIT_KPD_RTC_EB ( BIT(1) ) +#define BIT_ARCH_RTC_EB ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_REC_26MHZ_BUF_CFG */ +#define BITS_PLL_PROBE_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_REC_26MHZ_1_CUR_SEL ( BIT(4) ) +#define BIT_REC_26MHZ_0_CUR_SEL ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_SINDRV_CTRL */ +#define BITS_SINDRV_LVL(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)) ) +#define BIT_SINDRV_CLIP_MODE ( BIT(2) ) +#define BIT_SINDRV_ENA_SQUARE ( BIT(1) ) +#define BIT_SINDRV_ENA ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_ADA_SEL_CTRL */ +#define BIT_TW_MODE_SEL ( BIT(3) ) +#define BIT_WGADC_DIV_EN ( BIT(2) ) +#define BIT_AFCDAC_SYS_SEL ( BIT(1) ) +#define BIT_APCDAC_SYS_SEL ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_VBC_CTRL */ +#define BIT_AUDIF_CKG_AUTO_EN ( BIT(20) ) +#define BITS_AUD_INT_SYS_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_VBC_AFIFO_INT_SYS_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_VBC_AD23_INT_SYS_SEL(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_VBC_AD01_INT_SYS_SEL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_VBC_DA01_INT_SYS_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_VBC_AD23_DMA_SYS_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_VBC_AD01_DMA_SYS_SEL(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_VBC_DA01_DMA_SYS_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BIT_VBC_INT_CP0_ARM_SEL ( BIT(3) ) +#define BIT_VBC_INT_CP1_ARM_SEL ( BIT(2) ) +#define BIT_VBC_DMA_CP0_ARM_SEL ( BIT(1) ) +#define BIT_VBC_DMA_CP1_ARM_SEL ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_PWR_CTRL */ +#define BIT_HSIC_PLL_EN ( BIT(19) ) +#define BIT_HSIC_PHY_PD ( BIT(18) ) +#define BIT_HSIC_PS_PD_S ( BIT(17) ) +#define BIT_HSIC_PS_PD_L ( BIT(16) ) +#define BIT_MIPI_DSI_PS_PD_S ( BIT(15) ) +#define BIT_MIPI_DSI_PS_PD_L ( BIT(14) ) +#define BIT_MIPI_CSI_4LANE_PS_PD_S ( BIT(13) ) +#define BIT_MIPI_CSI_4LANE_PS_PD_L ( BIT(12) ) +#define BIT_MIPI_CSI_2LANE_PS_PD_S ( BIT(11) ) +#define BIT_MIPI_CSI_2LANE_PS_PD_L ( BIT(10) ) +#define BIT_APCPU_TS1_STOP ( BIT(9) ) +#define BIT_APCPU_TS0_STOP ( BIT(8) ) +#define BIT_CA7_TS1_STOP BIT_APCPU_TS1_STOP +#define BIT_CA7_TS0_STOP BIT_APCPU_TS0_STOP +#define BIT_EFUSE_BIST_PWR_ON ( BIT(3) ) +#define BIT_FORCE_DSI_PHY_SHUTDOWNZ ( BIT(2) ) +#define BIT_FORCE_CSI_PHY_SHUTDOWNZ ( BIT(1) ) +#define BIT_USB_PHY_PD ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_TS_CFG */ +#define BIT_CSYSACK_TS_LP_2 ( BIT(13) ) +#define BIT_CSYSREQ_TS_LP_2 ( BIT(12) ) +#define BIT_CSYSACK_TS_LP_1 ( BIT(11) ) +#define BIT_CSYSREQ_TS_LP_1 ( BIT(10) ) +#define BIT_CSYSACK_TS_LP_0 ( BIT(9) ) +#define BIT_CSYSREQ_TS_LP_0 ( BIT(8) ) +#define BIT_EVENTACK_RESTARTREQ_TS01 ( BIT(4) ) +#define BIT_EVENT_RESTARTREQ_TS01 ( BIT(1) ) +#define BIT_EVENT_HALTREQ_TS01 ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_BOOT_MODE */ +#define BIT_ARM_JTAG_EN ( BIT(13) ) +#define BIT_WPLL_OVR_FREQ_SEL ( BIT(12) ) +#define BIT_PTEST_FUNC_ATSPEED_SEL ( BIT(8) ) +#define BIT_PTEST_FUNC_MODE ( BIT(7) ) +#define BIT_USB_DLOAD_EN ( BIT(4) ) +#define BIT_ARM_BOOT_MD3 ( BIT(3) ) +#define BIT_ARM_BOOT_MD2 ( BIT(2) ) +#define BIT_ARM_BOOT_MD1 ( BIT(1) ) +#define BIT_ARM_BOOT_MD0 ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_BB_BG_CTRL */ +#define BIT_BB_CON_BG ( BIT(22) ) +#define BITS_BB_BG_RSV(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)) ) +#define BITS_BB_LDO_V(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BIT_BB_BG_RBIAS_EN ( BIT(15) ) +#define BIT_BB_BG_IEXT_IB_EN ( BIT(14) ) +#define BITS_BB_LDO_REFCTRL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) ) +#define BIT_BB_LDO_AUTO_PD_EN ( BIT(11) ) +#define BIT_BB_LDO_SLP_PD_EN ( BIT(10) ) +#define BIT_BB_LDO_FORCE_ON ( BIT(9) ) +#define BIT_BB_LDO_FORCE_PD ( BIT(8) ) +#define BIT_BB_BG_AUTO_PD_EN ( BIT(3) ) +#define BIT_BB_BG_SLP_PD_EN ( BIT(2) ) +#define BIT_BB_BG_FORCE_ON ( BIT(1) ) +#define BIT_BB_BG_FORCE_PD ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_CP_ARM_JTAG_CTRL */ +#define BIT_AON_ETM_PIN_SEL ( BIT(3) ) +#define BITS_CP_ARM_JTAG_PIN_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AON_APB_PLL_SOFT_CNT_DONE */ +#define BIT_RC1_SOFT_CNT_DONE ( BIT(13) ) +#define BIT_RC0_SOFT_CNT_DONE ( BIT(12) ) +#define BIT_XTLBUF1_SOFT_CNT_DONE ( BIT(9) ) +#define BIT_XTLBUF0_SOFT_CNT_DONE ( BIT(8) ) +#define BIT_GPLL_SOFT_CNT_DONE ( BIT(6) ) +#define BIT_MPLL_SOFT_CNT_DONE ( BIT(5) ) +#define BIT_LVDSPLL_SOFT_CNT_DONE ( BIT(4) ) +#define BIT_LPLL_SOFT_CNT_DONE ( BIT(3) ) +#define BIT_TWPLL_SOFT_CNT_DONE ( BIT(2) ) +#define BIT_DPLL_SOFT_CNT_DONE ( BIT(1) ) +#define BIT_MPLL0_SOFT_CNT_DONE ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_DCXO_LC_REG0 */ +#define BIT_DCXO_LC_FLAG ( BIT(8) ) +#define BIT_DCXO_LC_FLAG_CLR ( BIT(1) ) +#define BIT_DCXO_LC_CNT_CLR ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_DCXO_LC_REG1 */ +#define BITS_DCXO_LC_CNT(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_MPLL_CFG1 */ +#define BITS_MPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)) ) +#define BIT_MPLL_LOCK_DONE ( BIT(27) ) +#define BIT_MPLL_DIV_S ( BIT(26) ) +#define BIT_MPLL_MOD_EN ( BIT(25) ) +#define BIT_MPLL_SDM_EN ( BIT(24) ) +#define BITS_MPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_MPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_MPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_MPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AON_APB_MPLL_CFG2 */ +#define BITS_MPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_MPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_AON_APB_DPLL_CFG1 */ +#define BITS_DPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)) ) +#define BIT_DPLL_LOCK_DONE ( BIT(27) ) +#define BIT_DPLL_DIV_S ( BIT(26) ) +#define BIT_DPLL_MOD_EN ( BIT(25) ) +#define BIT_DPLL_SDM_EN ( BIT(24) ) +#define BITS_DPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_DPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_DPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_DPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AON_APB_DPLL_CFG2 */ +#define BITS_DPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_DPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_AON_APB_TWPLL_CFG1 */ +#define BITS_TWPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)) ) +#define BIT_TWPLL_LOCK_DONE ( BIT(27) ) +#define BIT_TWPLL_DIV_S ( BIT(26) ) +#define BIT_TWPLL_MOD_EN ( BIT(25) ) +#define BIT_TWPLL_SDM_EN ( BIT(24) ) +#define BITS_TWPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_TWPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_TWPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_TWPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AON_APB_TWPLL_CFG2 */ +#define BITS_TWPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_TWPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_AON_APB_LTEPLL_CFG1 */ +#define BITS_LTEPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)) ) +#define BIT_LTEPLL_LOCK_DONE ( BIT(27) ) +#define BIT_LTEPLL_DIV_S ( BIT(26) ) +#define BIT_LTEPLL_MOD_EN ( BIT(25) ) +#define BIT_LTEPLL_SDM_EN ( BIT(24) ) +#define BITS_LTEPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_LTEPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_LTEPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_LTEPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AON_APB_LTEPLL_CFG2 */ +#define BITS_LTEPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_LTEPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_AON_APB_LVDSDISPLL_CFG1 */ +#define BITS_LVDSDISPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_LVDSDISPLL_LOCK_DONE ( BIT(27) ) +#define BIT_LVDSDISPLL_DIV_S ( BIT(26) ) +#define BIT_LVDSDISPLL_MOD_EN ( BIT(25) ) +#define BIT_LVDSDISPLL_SDM_EN ( BIT(24) ) +#define BITS_LVDSDISPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_LVDSDISPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_LVDSDISPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_LVDSDISPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AON_APB_LVDSDISPLL_CFG2 */ +#define BITS_LVDSDISPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_LVDSDISPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_AON_APB_AON_REG_PROT */ +#define BIT_LDSP_CTRL_PROT ( BIT(31) ) +#define BITS_REG_PROT_VAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AON_APB_LDSP_BOOT_EN */ +#define BIT_FRC_CLK_LDSP_EN ( BIT(1) ) +#define BIT_LDSP_BOOT_EN ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_LDSP_BOOT_VEC */ +#define BITS_LDSP_BOOT_VECTOR(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_LDSP_RST */ +#define BIT_LDSP_SYS_SRST ( BIT(1) ) +#define BIT_LDSP_CORE_SRST_N ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_LDSP_MTX_CTRL1 */ +#define BITS_LDSP_MTX_CTRL1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_LDSP_MTX_CTRL2 */ +#define BITS_LDSP_MTX_CTRL2(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_LDSP_MTX_CTRL3 */ +#define BITS_LDSP_MTX_CTRL3(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_AON_CGM_CFG */ +#define BITS_PROBE_CKG_DIV(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_AUX2_CKG_DIV(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_AUX1_CKG_DIV(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_AUX0_CKG_DIV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_PROBE_CKG_SEL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_AUX2_CKG_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_AUX1_CKG_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_AUX0_CKG_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_LACC_MTX_CTRL */ +#define BITS_LACC_MTX_CTRL(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CORTEX_MTX_CTRL1 */ +#define BITS_CORTEX_MTX_CTRL1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CORTEX_MTX_CTRL2 */ +#define BITS_CORTEX_MTX_CTRL2(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CORTEX_MTX_CTRL3 */ +#define BITS_CORTEX_MTX_CTRL3(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AON_APB_CA5_TCLK_DLY_LEN */ +#define BITS_CA5_TCLK_DLY_LEN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AON_APB_PLD_ID_0 */ +#define BITS_PLD_ID_0(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_PLD_ID_1 */ +#define BITS_PLD_ID_1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_PROJ_ID_0 */ +#define BITS_PROJ_ID_0(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_PROJ_ID_1 */ +#define BITS_PROJ_ID_1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_DERIVED_ID */ +#define BITS_DERIVED_ID(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_MF_ID(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_AON_APB_MANU_ID */ +#define BITS_PROCESS_ID(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_FOUNDRY_ID(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_AON_APB_IMP_ID */ +#define BITS_MEM_CMP(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_STD_CELL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_AON_APB_CCIR_RCVR_CFG */ +#define BITS_ANALOG_PLL_RSV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_ANALOG_TESTMUX(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_CCIR_SE ( BIT(1) ) +#define BIT_CCIR_IE ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_PLL_BG_CFG */ +#define BITS_PLL_BG_RSV(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BIT_PLL_BG_RBIAS_EN ( BIT(3) ) +#define BIT_PLL_BG_PD ( BIT(2) ) +#define BIT_PLL_BG_IEXT_IBEN ( BIT(1) ) +#define BIT_PLL_CON_BG ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_LVDSDIS_SEL */ +#define BITS_LVDSDIS_LOG_SEL(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)) ) +#define BIT_LVDSDIS_DBG_SEL ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_DJTAG_MUX_SEL */ +#define BIT_DJTAG_CODEC_SEL ( BIT(7) ) +#define BIT_DJTAG_AON_SEL ( BIT(6) ) +#define BIT_DJTAG_PUB_SEL ( BIT(5) ) +#define BIT_DJTAG_CP1_SEL ( BIT(4) ) +#define BIT_DJTAG_CP0_SEL ( BIT(3) ) +#define BIT_DJTAG_GPU_SEL ( BIT(2) ) +#define BIT_DJTAG_MM_SEL ( BIT(1) ) +#define BIT_DJTAG_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_ARM7_SYS_SOFT_RST */ +#define BIT_ARM7_SYS_SOFT_RST ( BIT(4) ) +#define BIT_ARM7_CORE_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_CP1_CP0_ADDR_MSB */ +#define BITS_CP1_CP0_ADDR_MSB(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_AON_DMA_INT_EN */ +#define BIT_AON_DMA_INT_ARM7_EN ( BIT(6) ) +#define BIT_AON_DMA_INT_CP1_DSP_EN ( BIT(5) ) +#define BIT_AON_DMA_INT_CP1_CA5_EN ( BIT(4) ) +#define BIT_AON_DMA_INT_CP0_DSP_1_EN ( BIT(3) ) +#define BIT_AON_DMA_INT_CP0_DSP_0_EN ( BIT(2) ) +#define BIT_AON_DMA_INT_CP0_ARM9_0_EN ( BIT(1) ) +#define BIT_AON_DMA_INT_AP_EN ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_EMC_AUTO_GATE_EN */ +#define BIT_CP1_PUB_AUTO_GATE_EN ( BIT(19) ) +#define BIT_CP0_PUB_AUTO_GATE_EN ( BIT(18) ) +#define BIT_AP_PUB_AUTO_GATE_EN ( BIT(17) ) +#define BIT_AON_APB_PUB_AUTO_GATE_EN ( BIT(16) ) +#define BIT_CP1_EMC_AUTO_GATE_EN ( BIT(3) ) +#define BIT_CP0_EMC_AUTO_GATE_EN ( BIT(2) ) +#define BIT_AON_AP_EMC_AUTO_GATE_EN ( BIT(1) ) +#define BIT_AON_APCPU_EMC_AUTO_GATE_EN ( BIT(0) ) +#define BIT_AON_CA7_EMC_AUTO_GATE_EN ( BIT_AON_APCPU_EMC_AUTO_GATE_EN ) + +/* bits definitions for register REG_AON_APB_ARM7_CFG_BUS */ +#define BIT_ARM7_CFG_BUS_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_RTC4M_0_CFG */ +#define BITS_RTC4M0_RSV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RTC4M0_I_C(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BIT_RTC4M0_CAL_DONE ( BIT(6) ) +#define BIT_RTC4M0_CAL_START ( BIT(5) ) +#define BIT_RTC4M0_CHOP_EN ( BIT(4) ) +#define BIT_RTC4M0_FORCE_EN ( BIT(1) ) +#define BIT_RTC4M0_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_RTC4M_1_CFG */ +#define BITS_RTC4M1_RSV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RTC4M1_I_C(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BIT_RTC4M1_CAL_DONE ( BIT(6) ) +#define BIT_RTC4M1_CAL_START ( BIT(5) ) +#define BIT_RTC4M1_CHOP_EN ( BIT(4) ) +#define BIT_RTC4M1_FORCE_EN ( BIT(1) ) +#define BIT_RTC4M1_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_APB_RST2 */ +#define BIT_CODEC_DJTAG_SOFT_RST ( BIT(7) ) +#define BIT_AON_DJTAG_SOFT_RST ( BIT(6) ) +#define BIT_PUB_DJTAG_SOFT_RST ( BIT(5) ) +#define BIT_GPU_DJTAG_SOFT_RST ( BIT(4) ) +#define BIT_MM_DJTAG_SOFT_RST ( BIT(3) ) +#define BIT_CP1_DJTAG_SOFT_RST ( BIT(2) ) +#define BIT_CP0_DJTAG_SOFT_RST ( BIT(1) ) +#define BIT_AP_DJTAG_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_OSC_CTRL */ +#define BITS_OSC_CTRL_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BIT_OSC_CTRL_EN ( BIT(15) ) +#define BIT_OSC_CTRL_START ( BIT(14) ) +#define BIT_OSC_CTRL_RSTN ( BIT(13) ) +#define BITS_OSC_CTRL_CLK_NUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) + +/* bits definitions for register REG_AON_APB_OSC_OBS */ +#define BIT_OSC_OBS_OVERFLOW ( BIT(15) ) +#define BITS_OSC_OBS_SPEED_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register REG_AON_APB_APCPU_SDISABLE */ +#define BITS_APCPU_BIG_CP15SDISABLE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BIT_APCPU_CFGSDISABLE ( BIT(4) ) +#define BITS_APCPU_LIT_CP15SDISABLE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_MPLL0_CFG1 */ +#define BITS_MPLL0_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)) ) +#define BIT_MPLL0_LOCK_DONE ( BIT(27) ) +#define BIT_MPLL0_DIV_S ( BIT(26) ) +#define BIT_MPLL0_MOD_EN ( BIT(25) ) +#define BIT_MPLL0_SDM_EN ( BIT(24) ) +#define BITS_MPLL0_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_MPLL0_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_MPLL0_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_MPLL0_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AON_APB_MPLL0_CFG2 */ +#define BITS_MPLL0_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_MPLL0_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_AON_APB_GPLL_CFG1 */ +#define BITS_GPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)) ) +#define BIT_GPLL_LOCK_DONE ( BIT(27) ) +#define BIT_GPLL_DIV_S ( BIT(26) ) +#define BIT_GPLL_MOD_EN ( BIT(25) ) +#define BIT_GPLL_SDM_EN ( BIT(24) ) +#define BITS_GPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_GPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_GPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_GPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AON_APB_GPLL_CFG2 */ +#define BITS_GPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_GPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_AON_APB_UPLL_CFG1 */ +#define BITS_UPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)) ) +#define BIT_UPLL_LOCK_DONE ( BIT(27) ) +#define BIT_UPLL_DIV_S ( BIT(26) ) +#define BIT_UPLL_MOD_EN ( BIT(25) ) +#define BIT_UPLL_SDM_EN ( BIT(24) ) +#define BITS_UPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_UPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_UPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_UPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AON_APB_UPLL_CFG2 */ +#define BITS_UPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_UPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_AON_APB_APCPU_CCI_CKG_CFG */ +#define BIT_APCPU_CCI_CKG_EN ( BIT(1) ) +#define BIT_APCPU_CCI_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_AP_MODULE_FOLLOW_CTRL */ +#define BIT_AP_GPU_CLK_FOLLOW_AP ( BIT(2) ) +#define BIT_AP_MM_CODEC_CLK_FOLLOW_AP ( BIT(1) ) +#define BIT_AP_MM_CLK_FOLLOW_AP ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_AVS_SOFT_RST */ +#define BIT_CA53_LIT_AVS_SOFT_RST ( BIT(2) ) +#define BIT_CA53_BIG_AVS_SOFT_RST ( BIT(1) ) +#define BIT_GPU_AVS_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_AP_IRAM_REMAP */ +#define BIT_AP_IRAM_REMAP ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_APCPU_BIG_SOFT_RST */ +#define BIT_APCPU_BIG_DBG_SOFT_RST ( BIT(9) ) +#define BIT_APCPU_BIG_L2_SOFT_RST ( BIT(8) ) +#define BITS_APCPU_BIG_ATB_SOFT_RST(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_APCPU_BIG_CORE_SOFT_RST(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_APCPU_LIT_SOFT_RST */ +#define BIT_APCPU_LIT_DBG_SOFT_RST ( BIT(9) ) +#define BIT_APCPU_LIT_L2_SOFT_RST ( BIT(8) ) +#define BITS_APCPU_LIT_ATB_SOFT_RST(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_APCPU_LIT_CORE_SOFT_RST(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_APCPU_TOP_SOFT_RST */ +#define BIT_APCPU_MTX_SOFT_RST ( BIT(2) ) +#define BIT_APCPU_EMC_SOFT_RST ( BIT(1) ) +#define BIT_APCPU_DAP_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_CA5_BIG_THM_CTRL */ +#define BITS_CA53_BIG_THM_CALI_RSVD(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_AON_APB_CA5_LIT_THM_CTRL */ +#define BITS_CA53_LIT_THM_CALI_RSVD(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_AON_APB_A53_BIGCORE_VDROP SNSR_CTRL */ +#define BITS_CA53_BIG_VDROP1_RESERVED_CTRL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_CA53_BIG_VDROP1_CTRL(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)) ) +#define BITS_CA53_BIG_VDROP1_CURRENT_CTRL(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)) ) +#define BIT_CA53_BIG_VDROP1_OUT ( BIT(17) ) +#define BIT_CA53_BIG_VDROP1_EN ( BIT(16) ) +#define BITS_CA53_BIG_VDROP0_RESERVED_CTRL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CA53_BIG_VDROP0_CTRL(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_CA53_BIG_VDROP0_CURRENT_CTRL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BIT_CA53_BIG_VDROP0_OUT ( BIT(1) ) +#define BIT_CA53_BIG_VDROP0_EN ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_A53_LITCORE_VDROP SNSR_CTRL */ +#define BITS_CA53_LIT_VDROP1_RESERVED_CTRL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_CA53_LIT_VDROP1_CTRL(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)) ) +#define BITS_CA53_LIT_VDROP1_CURRENT_CTRL(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)) ) +#define BIT_CA53_LIT_VDROP1_OUT ( BIT(17) ) +#define BIT_CA53_LIT_VDROP1_EN ( BIT(16) ) +#define BITS_CA53_LIT_VDROP0_RESERVED_CTRL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CA53_LIT_VDROP0_CTRL(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_CA53_LIT_VDROP0_CURRENT_CTRL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BIT_CA53_LIT_VDROP0_OUT ( BIT(1) ) +#define BIT_CA53_LIT_VDROP0_EN ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_A53_AUTO_REG_SAVE_CRTL */ +#define BIT_APCPU_AUTO_REG_SAVE_TRIG_SEL ( BIT(1) ) +#define BIT_AUTO_REG_SAVE_EN ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_CSSYS_CFG */ +#define BIT_CSSYS_TPIU_TPCTL ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_REDUN_CFG */ +#define BIT_REDUN_CFG_3 ( BIT(3) ) +#define BIT_REDUN_CFG_2 ( BIT(2) ) +#define BIT_REDUN_CFG_1 ( BIT(1) ) +#define BIT_REDUN_CFG_0 ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_AP_WPROT_EN1 */ +#define BITS_AP_AWADDR_WPROT_EN1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CP0_WPROT_EN1 */ +#define BITS_CP0_AWADDR_WPROT_EN1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CP1_WPROT_EN1 */ +#define BITS_CP1_AWADDR_WPROT_EN1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_IO_DLY_CTRL */ +#define BITS_CLK_CCIR_DLY_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CLK_CP1DSP_DLY_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_CLK_CP0DSP_DLY_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_AP_WPROT_EN0 */ +#define BITS_AP_AWADDR_WPROT_EN0(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CP0_WPROT_EN0 */ +#define BITS_CP0_AWADDR_WPROT_EN0(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_CP1_WPROT_EN0 */ +#define BITS_CP1_AWADDR_WPROT_EN0(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_PMU_RST_MONITOR */ +#define BITS_PMU_RST_MONITOR(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_THM_RST_MONITOR */ +#define BITS_THM_RST_MONITOR(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_AP_RST_MONITOR */ +#define BITS_AP_RST_MONITOR(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_APCPU_RST_MONITOR */ +#define BITS_APCPU_RST_MONITOR(_X_) (_X_) +#define BITS_CA7_RST_MONITOR(_X_) BITS_APCPU_RST_MONITOR + +/* bits definitions for register REG_AON_APB_BOND_OPT0 */ +#define BITS_BOND_OPTION0(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_BOND_OPT1 */ +#define BITS_BOND_OPTION1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_RES_REG0 */ +#define BITS_RES_REG0(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_RES_REG1 */ +#define BITS_RES_REG1(_X_) (_X_) + +/* bits definitions for register REG_AON_APB_AON_QOS_CFG */ +#define BITS_QOS_R_GPU(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_QOS_W_GPU(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_QOS_R_GSP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_QOS_W_GSP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_BB_LDO_CAL_START */ +#define BIT_BB_LDO_CAL_START ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_AON_MTX_PROT_CFG */ +#define BITS_AON_HPROT_DMAW(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_AON_HPROT_DMAR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_LVDS_CFG */ +#define BITS_LVDSDIS_TXCLKDATA(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_LVDSDIS_TXCOM(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_LVDSDIS_TXSLEW(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_LVDSDIS_TXSW(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_LVDSDIS_TXRERSER(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_LVDSDIS_PRE_EMP(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)) ) +#define BIT_LVDSDIS_TXPD ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_PLL_LOCK_OUT_SEL */ +#define BIT_SLEEP_PLLLOCK_SEL ( BIT(7) ) +#define BITS_PLL_LOCK_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BITS_SLEEP_DBG_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AON_APB_RTC4M_RC_VAL */ +#define BIT_RTC4M1_RC_SEL ( BIT(31) ) +#define BITS_RTC4M1_RC_VAL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) ) +#define BIT_RTC4M0_RC_SEL ( BIT(15) ) +#define BITS_RTC4M0_RC_VAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) ) + +/* bits definitions for register REG_AON_APB_PROT_BUS_SECURE_EN */ +#define BIT_BUS_SECURE_EN ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_PROT_ARM7_SPACE_EN */ +#define BIT_ARM7_SPACE_EN ( BIT(0) ) + +/* bits definitions for register REG_AON_APB_AON_APB_RSV */ +#define BITS_AON_APB_RSV(_X_) (_X_) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_aon_clk.h b/include/soc/sprd/chip_x35lt8/__regs_aon_clk.h new file mode 100644 index 00000000..04713eb0 --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_aon_clk.h @@ -0,0 +1,156 @@ +/* the head file modifier: g 2015-03-19 17:10:17*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_AON_CLK_CORE_HEADFILE_H__ +#define __H_REGS_AON_CLK_CORE_HEADFILE_H__ __FILE__ + +#define REGS_AON_CLK_CORE + +/* registers definitions for AON_CLK_CORE */ +#define REG_AON_CLK_CORE_clk_pub_ahb_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x20)/*clk_pub_ahb_cfg*/ +#define REG_AON_CLK_CORE_clk_aon_apb_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x24)/*clk_aon_apb_cfg*/ +#define REG_AON_CLK_CORE_clk_adi_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x28)/*clk_adi_cfg*/ +#define REG_AON_CLK_CORE_clk_pwm0_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x2c)/*clk_pwm0_cfg*/ +#define REG_AON_CLK_CORE_clk_pwm1_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x30)/*clk_pwm1_cfg*/ +#define REG_AON_CLK_CORE_clk_pwm2_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x34)/*clk_pwm2_cfg*/ +#define REG_AON_CLK_CORE_clk_pwm3_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x38)/*clk_pwm3_cfg*/ +#define REG_AON_CLK_CORE_clk_arm7_uart_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x3c)/*clk_arm7_uart_cfg*/ +#define REG_AON_CLK_CORE_clk_thm_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x40)/*clk_thm_cfg*/ +#define REG_AON_CLK_CORE_clk_mspi_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x44)/*clk_mspi_cfg*/ +#define REG_AON_CLK_CORE_clk_i2c_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x48)/*clk_i2c_cfg*/ +#define REG_AON_CLK_CORE_clk_gpu_avs_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x4c)/*clk_gpu_avs_cfg*/ +#define REG_AON_CLK_CORE_clk_audif_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x50)/*clk_audif_cfg*/ +#define REG_AON_CLK_CORE_clk_apcpu_dap_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x54)/*clk_apcpu_dap_cfg*/ +#define REG_AON_CLK_CORE_clk_emc_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x58)/*clk_emc_cfg*/ +#define REG_AON_CLK_CORE_clk_apcpu_ts_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x5c)/*clk_apcpu_ts_cfg*/ +#define REG_AON_CLK_CORE_clk_djtag_tck_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x60)/*clk_djtag_tck_cfg*/ +#define REG_AON_CLK_CORE_clk_arm7_ahb_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x64)/*clk_arm7_ahb_cfg*/ +#define REG_AON_CLK_CORE_clk_ca5_ts_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x68)/*clk_ca5_ts_cfg*/ +#define REG_AON_CLK_CORE_clk_ca53_big_avs_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x6c)/*clk_ca53_big_avs_cfg*/ +#define REG_AON_CLK_CORE_clk_ca53_lit_avs_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x70)/*clk_ca53_lit_avs_cfg*/ +#define REG_AON_CLK_CORE_clk_cci_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x74)/*clk_cci_cfg*/ +#define REG_AON_CLK_CORE_clk_cssys_cfg SCI_ADDR(REGS_AON_CLK_CORE_BASE, 0x78)/*clk_cssys_cfg*/ +/* registers definitions for controller REGS_AON_CLK */ +#define REG_AON_CLK_PUB_AHB_CFG REG_AON_CLK_CORE_clk_pub_ahb_cfg +#define REG_AON_CLK_AON_APB_CFG REG_AON_CLK_CORE_clk_aon_apb_cfg +#define REG_AON_CLK_ADI_CFG REG_AON_CLK_CORE_clk_adi_cfg +#define REG_AON_CLK_PWM0_CFG REG_AON_CLK_CORE_clk_pwm0_cfg +#define REG_AON_CLK_PWM1_CFG REG_AON_CLK_CORE_clk_pwm1_cfg +#define REG_AON_CLK_PWM2_CFG REG_AON_CLK_CORE_clk_pwm2_cfg +#define REG_AON_CLK_PWM3_CFG REG_AON_CLK_CORE_clk_pwm3_cfg +#define REG_AON_CLK_ARM7_UART_CFG REG_AON_CLK_CORE_clk_arm7_uart_cfg +#define REG_AON_CLK_THM_CFG REG_AON_CLK_CORE_clk_thm_cfg +#define REG_AON_CLK_MSPI_CFG REG_AON_CLK_CORE_clk_mspi_cfg +#define REG_AON_CLK_I2C_CFG REG_AON_CLK_CORE_clk_i2c_cfg +#define REG_AON_CLK_AVS_CFG REG_AON_CLK_CORE_clk_avs_cfg +#define REG_AON_CLK_AUDIF_CFG REG_AON_CLK_CORE_clk_audif_cfg +#define REG_AON_CLK_CA7_DAP_CFG REG_AON_CLK_CORE_clk_apcpu_dap_cfg +#define REG_AON_CLK_EMC_CFG REG_AON_CLK_CORE_clk_emc_cfg +#define REG_AON_CLK_CA7_TS_CFG REG_AON_CLK_CORE_clk_apcpu_ts_cfg +#define REG_AON_CLK_DJTAG_CLK_CFG REG_AON_CLK_CORE_clk_djtag_tck_cfg +#define REG_AON_CLK_ARM7_AHB_CFG REG_AON_CLK_CORE_clk_arm7_ahb_cfg +#define REG_AON_CLK_CA5_TS_CFG REG_AON_CLK_CORE_clk_ca5_ts_cfg +/* vars definitions for controller REGS_AON_CLK */ +#define PUB_AHB_CLK_SEL_SHIFT (0x0) +#define PUB_AHB_CLK_SEL_MASK (0x3 << PUB_AHB_CLK_SEL_SHIFT) + + +/* bits definitions for register REG_AON_CLK_CORE_clk_pub_ahb_cfg */ +#define BITS_CLK_PUB_AHB_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_CLK_PUB_AHB_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_aon_apb_cfg */ +#define BITS_CLK_AON_APB_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_CLK_AON_APB_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_adi_cfg */ +#define BITS_CLK_ADI_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_pwm0_cfg */ +#define BITS_CLK_PWM0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_pwm1_cfg */ +#define BITS_CLK_PWM1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_pwm2_cfg */ +#define BITS_CLK_PWM2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_pwm3_cfg */ +#define BITS_CLK_PWM3_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_arm7_uart_cfg */ +#define BITS_CLK_ARM7_UART_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_thm_cfg */ +#define BIT_CLK_THM_SEL ( BIT(0) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_mspi_cfg */ +#define BITS_CLK_MSPI_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_i2c_cfg */ +#define BITS_CLK_I2C_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_gpu_avs_cfg */ +#define BITS_CLK_GPU_AVS_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_audif_cfg */ +#define BITS_CLK_AUDIF_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_apcpu_dap_cfg */ +#define BITS_CLK_APCPU_DAP_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_emc_cfg */ +#define BITS_CLK_EMC_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_CLK_EMC_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_apcpu_ts_cfg */ +#define BITS_CLK_APCPU_TS_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_djtag_tck_cfg */ +#define BIT_CLK_DJTAG_TCK_PAD_SEL ( BIT(16) ) +#define BIT_CLK_DJTAG_TCK_SEL ( BIT(0) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_arm7_ahb_cfg */ +#define BITS_CLK_ARM7_AHB_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_CLK_ARM7_AHB_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_ca5_ts_cfg */ +#define BITS_CLK_CA5_TS_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_ca53_big_avs_cfg */ +#define BITS_CLK_CA53_BIG_AVS_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_ca53_lit_avs_cfg */ +#define BITS_CLK_CA53_LIT_AVS_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_cci_cfg */ +#define BITS_CLK_CCI_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_CLK_CCI_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AON_CLK_CORE_clk_cssys_cfg */ +#define BITS_CLK_CSSYS_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_CLK_CSSYS_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_ap_ahb_rf.h b/include/soc/sprd/chip_x35lt8/__regs_ap_ahb_rf.h new file mode 100644 index 00000000..3ce3ad16 --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_ap_ahb_rf.h @@ -0,0 +1,552 @@ +/* the head file modifier: g 2015-03-19 15:39:58*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_AP_AHB_RF_HEADFILE_H__ +#define __H_REGS_AP_AHB_RF_HEADFILE_H__ __FILE__ + +#define REGS_AP_AHB_RF + +/* registers definitions for AP_AHB_RF */ +#define REG_AP_AHB_AHB_EB SCI_ADDR(REGS_AP_AHB_BASE, 0x0000)/*AHB_EB*/ +#define REG_AP_AHB_AHB_RST SCI_ADDR(REGS_AP_AHB_BASE, 0x0004)/*AHB_RST*/ +#define REG_AP_AHB_APCPU_RST_SET SCI_ADDR(REGS_AP_AHB_BASE, 0x0008)/*APCPU_RST_SET*/ +#define REG_AP_AHB_CA7_RST_SET REG_AP_AHB_APCPU_RST_SET +#define REG_AP_AHB_AP_SYS_FORCE_SLEEP_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x000C)/*AP_SYS_FORCE_SLEEP_CFG*/ +#define REG_AP_AHB_AP_SYS_AUTO_SLEEP_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x0010)/*AP_SYS_AUTO_SLEEP_CFG*/ +#define REG_AP_AHB_HOLDING_PEN SCI_ADDR(REGS_AP_AHB_BASE, 0x0014)/*HOLDING_PEN*/ +#define REG_AP_AHB_JMP_ADDR_APCPU_C0 SCI_ADDR(REGS_AP_AHB_BASE, 0x0018)/*JMP_ADDR_APCPU_C0*/ +#define REG_AP_AHB_JMP_ADDR_APCPU_C1 SCI_ADDR(REGS_AP_AHB_BASE, 0x001C)/*JMP_ADDR_APCPU_C1*/ +#define REG_AP_AHB_JMP_ADDR_APCPU_C2 SCI_ADDR(REGS_AP_AHB_BASE, 0x0020)/*JMP_ADDR_APCPU_C2*/ +#define REG_AP_AHB_JMP_ADDR_APCPU_C3 SCI_ADDR(REGS_AP_AHB_BASE, 0x0024)/*JMP_ADDR_APCPU_C3*/ +#define REG_AP_AHB_APCPU_C0_PU_LOCK SCI_ADDR(REGS_AP_AHB_BASE, 0x0028)/*APCPU_C0_PU_LOCK*/ +#define REG_AP_AHB_APCPU_C1_PU_LOCK SCI_ADDR(REGS_AP_AHB_BASE, 0x002C)/*APCPU_C1_PU_LOCK*/ +#define REG_AP_AHB_APCPU_C2_PU_LOCK SCI_ADDR(REGS_AP_AHB_BASE, 0x0030)/*APCPU_C2_PU_LOCK*/ +#define REG_AP_AHB_APCPU_C3_PU_LOCK SCI_ADDR(REGS_AP_AHB_BASE, 0x0034)/*APCPU_C3_PU_LOCK*/ +#define REG_AP_AHB_APCPU_CKG_DIV_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x0038)/*APCPU_CKG_DIV_CFG*/ +#define REG_AP_AHB_JMP_ADDR_CA7_C0 REG_AP_AHB_JMP_ADDR_APCPU_C0 +#define REG_AP_AHB_JMP_ADDR_CA7_C1 REG_AP_AHB_JMP_ADDR_APCPU_C1 +#define REG_AP_AHB_JMP_ADDR_CA7_C2 REG_AP_AHB_JMP_ADDR_APCPU_C2 +#define REG_AP_AHB_JMP_ADDR_CA7_C3 REG_AP_AHB_JMP_ADDR_APCPU_C3 +#define REG_AP_AHB_CA7_C0_PU_LOCK REG_AP_AHB_APCPU_C0_PU_LOCK +#define REG_AP_AHB_CA7_C1_PU_LOCK REG_AP_AHB_APCPU_C1_PU_LOCK +#define REG_AP_AHB_CA7_C2_PU_LOCK REG_AP_AHB_APCPU_C2_PU_LOCK +#define REG_AP_AHB_CA7_C3_PU_LOCK REG_AP_AHB_APCPU_C3_PU_LOCK +#define REG_AP_AHB_CA7_CKG_DIV_CFG REG_AP_AHB_APCPU_CKG_DIV_CFG +#define REG_AP_AHB_MCU_PAUSE SCI_ADDR(REGS_AP_AHB_BASE, 0x003C)/*MCU_PAUSE*/ +#define REG_AP_AHB_MISC_CKG_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x0040)/*MISC_CKG_EN*/ +#define REG_AP_AHB_APCPU_C0_AUTO_FORCE_SHUTDOWN_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x0044)/*APCPU_C0_AUTO_FORCE_SHUTDOWN_EN*/ +#define REG_AP_AHB_APCPU_C1_AUTO_FORCE_SHUTDOWN_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x0048)/*APCPU_C1_AUTO_FORCE_SHUTDOWN_EN*/ +#define REG_AP_AHB_APCPU_C2_AUTO_FORCE_SHUTDOWN_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x004C)/*APCPU_C2_AUTO_FORCE_SHUTDOWN_EN*/ +#define REG_AP_AHB_APCPU_C3_AUTO_FORCE_SHUTDOWN_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x0050)/*APCPU_C3_AUTO_FORCE_SHUTDOWN_EN*/ +#define REG_AP_AHB_APCPU_CKG_SEL_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x0054)/*APCPU_CKG_SEL_CFG*/ +#define REG_AP_AHB_APCPU_AUTO_GATE_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x0058)/*APCPU_AUTO_GATE_EN*/ +#define REG_AP_AHB_CA7_C0_AUTO_FORCE_SHUTDOWN_EN REG_AP_AHB_APCPU_C0_AUTO_FORCE_SHUTDOWN_EN +#define REG_AP_AHB_CA7_C1_AUTO_FORCE_SHUTDOWN_EN REG_AP_AHB_APCPU_C1_AUTO_FORCE_SHUTDOWN_EN +#define REG_AP_AHB_CA7_C2_AUTO_FORCE_SHUTDOWN_EN REG_AP_AHB_APCPU_C2_AUTO_FORCE_SHUTDOWN_EN +#define REG_AP_AHB_CA7_C3_AUTO_FORCE_SHUTDOWN_EN REG_AP_AHB_APCPU_C3_AUTO_FORCE_SHUTDOWN_EN +#define REG_AP_AHB_CA7_CKG_SEL_CFG REG_AP_AHB_APCPU_CKG_SEL_CFG +#define REG_AP_AHB_APCPU_GIC_CKG_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x005c)/*APCPU_GIC_CKG_CFG*/ +#define REG_AP_AHB_APCPU_GIC_CLK_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x0060)/*APCPU_GIC_CLK_CFG*/ +#define REG_AP_AHB_APCPU_LIT_CKG_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x0064)/*APCPU_LIT_CKG_EN*/ +#define REG_AP_AHB_APCPU_BIG_CKG_EN SCI_ADDR(REGS_AP_AHB_BASE, 0x0068)/*APCPU_LIT_CKG_EN*/ +#define REG_AP_AHB_APCPU_LIT_L2FLUSH SCI_ADDR(REGS_AP_AHB_BASE, 0x006C)/*APCPU_LIT_L2FLUSH*/ +#define REG_AP_AHB_APCPU_BIG_L2FLUSH SCI_ADDR(REGS_AP_AHB_BASE, 0x0070)/*APCPU_BIG_L2FLUSH*/ +#define REG_AP_AHB_APCPU_CCI_BASE_H25 SCI_ADDR(REGS_AP_AHB_BASE, 0x0074)/*APCPU_CCI_BASE_H25*/ +#define REG_AP_AHB_APCPU_CCI_CTRL SCI_ADDR(REGS_AP_AHB_BASE, 0x0078)/*APCPU_CCI_CTRL*/ +#define REG_AP_AHB_MISC_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x3000)/*MISC_CFG*/ +#define REG_AP_AHB_AP_MAIN_MTX_HPROT_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x3004)/*AP_MAIN_MTX_HPROT_CFG*/ +#define REG_AP_AHB_APCPU_STANDBY_STATUS SCI_ADDR(REGS_AP_AHB_BASE, 0x3008)/*APCPU_STANDBY_STATUS*/ +#define REG_AP_AHB_CA7_STANDBY_STATUS REG_AP_AHB_APCPU_STANDBY_STATUS +#define REG_AP_AHB_NANC_CLK_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x300C)/*NANDC_CLK_CFG*/ +#define REG_AP_AHB_LVDS_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x3010)/*LVDS_CFG*/ +#define REG_AP_AHB_LVDS_PLL_CFG0 SCI_ADDR(REGS_AP_AHB_BASE, 0x3014)/*LVDS_PLL_CFG0*/ +#define REG_AP_AHB_LVDS_PLL_CFG1 SCI_ADDR(REGS_AP_AHB_BASE, 0x3018)/*LVDS_PLL_CFG1*/ +#define REG_AP_AHB_AP_QOS_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x301C)/*AP_QOS_CFG*/ +#define REG_AP_AHB_OTG_PHY_TUNE SCI_ADDR(REGS_AP_AHB_BASE, 0x3020)/*USB_PHY_TUNE*/ +#define REG_AP_AHB_OTG_PHY_TEST SCI_ADDR(REGS_AP_AHB_BASE, 0x3024)/*MISC_CKG_EN*/ +#define REG_AP_AHB_OTG_PHY_CTRL SCI_ADDR(REGS_AP_AHB_BASE, 0x3028)/*USB_PHY_CTRL*/ +#define REG_AP_AHB_HSIC_PHY_TUNE SCI_ADDR(REGS_AP_AHB_BASE, 0x302C)/*USB_PHY_TUNE*/ +#define REG_AP_AHB_HSIC_PHY_TEST SCI_ADDR(REGS_AP_AHB_BASE, 0x3030)/*MISC_CKG_EN*/ +#define REG_AP_AHB_HSIC_PHY_CTRL SCI_ADDR(REGS_AP_AHB_BASE, 0x3034)/*USB_PHY_CTRL*/ +#define REG_AP_AHB_ZIP_MTX_QOS_CFG SCI_ADDR(REGS_AP_AHB_BASE, 0x3038)/*ZIP_MTX_QOS_CFG*/ +#define REG_AP_AHB_APCPU_QCHN_CTL_BIG SCI_ADDR(REGS_AP_AHB_BASE, 0x303C)/*APCPU_QCHN_CTL_BIG*/ +#define REG_AP_AHB_APCPU_QCHN_STA_BIG SCI_ADDR(REGS_AP_AHB_BASE, 0x3040)/*APCPU_QCHN_STA_BIG*/ +#define REG_AP_AHB_APCPU_QCHN_CTL_LIT SCI_ADDR(REGS_AP_AHB_BASE, 0x3044)/*APCPU_QCHN_CTL_LIT*/ +#define REG_AP_AHB_APCPU_QCHN_STA_LIT SCI_ADDR(REGS_AP_AHB_BASE, 0x3048)/*APCPU_QCHN_STA_LIT*/ +#define REG_AP_AHB_GSP_SEL SCI_ADDR(REGS_AP_AHB_BASE, 0x304c)/*GSP_SEL*/ +#define REG_AP_AHB_RES_REG SCI_ADDR(REGS_AP_AHB_BASE, 0x30F0)/*RES_REG*/ +#define REG_AP_AHB_CHIP_ID SCI_ADDR(REGS_AP_AHB_BASE, 0x30FC)/*CHIP_ID*/ + + + +/* bits definitions for register REG_AP_AHB_AHB_EB */ +#define BIT_ZIPMTX_EB ( BIT(23) ) +#define BIT_LVDS_EB ( BIT(22) ) +#define BIT_ZIPDEC_EB ( BIT(21) ) +#define BIT_ZIPENC_EB ( BIT(20) ) +#define BIT_NANDC_ECC_EB ( BIT(19) ) +#define BIT_NANDC_2X_EB ( BIT(18) ) +#define BIT_NANDC_EB ( BIT(17) ) +#define BIT_BUSMON2_EB ( BIT(16) ) +#define BIT_BUSMON1_EB ( BIT(15) ) +#define BIT_BUSMON0_EB ( BIT(14) ) +#define BIT_SPINLOCK_EB ( BIT(13) ) +#define BIT_EMMC_EB ( BIT(11) ) +#define BIT_SDIO2_EB ( BIT(10) ) +#define BIT_SDIO1_EB ( BIT(9) ) +#define BIT_SDIO0_EB ( BIT(8) ) +#define BIT_DRM_EB ( BIT(7) ) +#define BIT_NFC_EB ( BIT(6) ) +#define BIT_DMA_EB ( BIT(5) ) +#define BIT_OTG_EB ( BIT(4) ) +#define BIT_USB_EB (BIT_OTG_EB) +#define BIT_GSP_EB ( BIT(3) ) +#define BIT_HSIC_EB ( BIT(2) ) +#define BIT_DISPC_EB ( BIT(1) ) +#define BIT_DISPC0_EB (BIT_DISPC_EB) +#define BIT_DSI_EB ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_AHB_RST */ +#define BIT_HSIC_PHY_SOFT_RST ( BIT(30) ) +#define BIT_HSIC_UTMI_SOFT_RST ( BIT(29) ) +#define BIT_HSIC_SOFT_RST ( BIT(28) ) +#define BIT_LVDS_SOFT_RST ( BIT(25) ) +#define BIT_ZIP_MTX_SOFT_RST ( BIT(24) ) +#define BIT_ZIPDEC_SOFT_RST ( BIT(23) ) +#define BIT_ZIPENC_SOFT_RST ( BIT(22) ) +#define BIT_CCI_SOFT_RST ( BIT(21) ) +#define BIT_NANDC_SOFT_RST ( BIT(20) ) +#define BIT_BUSMON2_SOFT_RST ( BIT(19) ) +#define BIT_BUSMON1_SOFT_RST ( BIT(18) ) +#define BIT_BUSMON0_SOFT_RST ( BIT(17) ) +#define BIT_SPINLOCK_SOFT_RST ( BIT(16) ) +#define BIT_EMMC_SOFT_RST ( BIT(14) ) +#define BIT_SDIO2_SOFT_RST ( BIT(13) ) +#define BIT_SDIO1_SOFT_RST ( BIT(12) ) +#define BIT_SDIO0_SOFT_RST ( BIT(11) ) +#define BIT_DRM_SOFT_RST ( BIT(10) ) +#define BIT_NFC_SOFT_RST ( BIT(9) ) +#define BIT_DMA_SOFT_RST ( BIT(8) ) +#define BIT_CSSYS_SOFT_RST ( BIT(7) ) +#define BIT_OTG_PHY_SOFT_RST ( BIT(6) ) +#define BIT_OTG_UTMI_SOFT_RST ( BIT(5) ) +#define BIT_OTG_SOFT_RST ( BIT(4) ) +#define BIT_GSP_SOFT_RST ( BIT(3) ) +#define BIT_DISP_MTX_SOFT_RST ( BIT(2) ) +#define BIT_DISPC_SOFT_RST ( BIT(1) ) +#define BIT_DSI_SOFT_RST ( BIT(0) ) +#define BIT_DISPC0_SOFT_RST (BIT_DISPC_SOFT_RST) + +/* bits definitions for register REG_AP_AHB_APCPU_RST_SET */ +#define BIT_AP_QCHN_BIG_SOFT_RST ( BIT(17) ) +#define BIT_AP_QCHN_LIT_SOFT_RST ( BIT(16) ) +#define BIT_APCPU_GIC_SOFT_RST ( BIT(15) ) +#define BIT_APCPU_CS_DBG_SOFT_RST ( BIT(14) ) +#define BIT_APCPU_SOCDBG_SOFT_RST ( BIT(12) ) +#define BITS_APCPU_ETM_SOFT_RST(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_APCPU_DBG_SOFT_RST(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_APCPU_CORE_SOFT_RST(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) +#define BIT_CA7_CS_DBG_SOFT_RST BIT_APCPU_CS_DBG_SOFT_RST +#define BIT_CA7_SOCDBG_SOFT_RST BIT_APCPU_SOCDBG_SOFT_RST +#define BITS_CA7_ETM_SOFT_RST(_x_) BITS_APCPU_ETM_SOFT_RST(_x_) +#define BITS_CA7_DBG_SOFT_RST(_x_) BITS_APCPU_DBG_SOFT_RST(_x_) +#define BITS_CA7_CORE_SOFT_RST(_x_) BITS_APCPU_CORE_SOFT_RST(_x_) + +/* bits definitions for register REG_AP_AHB_AP_SYS_FORCE_SLEEP_CFG */ +#define BIT_APCPU_C3_AUTO_SLP_EN ( BIT(15) ) +#define BIT_APCPU_C2_AUTO_SLP_EN ( BIT(14) ) +#define BIT_APCPU_C1_AUTO_SLP_EN ( BIT(13) ) +#define BIT_APCPU_C0_AUTO_SLP_EN ( BIT(12) ) +#define BIT_APCPU_C3_WFI_SHUTDOWN_EN ( BIT(11) ) +#define BIT_APCPU_C2_WFI_SHUTDOWN_EN ( BIT(10) ) +#define BIT_APCPU_C1_WFI_SHUTDOWN_EN ( BIT(9) ) +#define BIT_APCPU_C0_WFI_SHUTDOWN_EN ( BIT(8) ) +#define BIT_MCU_APCPU_C3_SLEEP ( BIT(7) ) +#define BIT_MCU_APCPU_C2_SLEEP ( BIT(6) ) +#define BIT_MCU_APCPU_C1_SLEEP ( BIT(5) ) +#define BIT_MCU_APCPU_C0_SLEEP ( BIT(4) ) +#define BIT_CA7_C3_AUTO_SLP_EN BIT_APCPU_C3_AUTO_SLP_EN +#define BIT_CA7_C2_AUTO_SLP_EN BIT_APCPU_C2_AUTO_SLP_EN +#define BIT_CA7_C1_AUTO_SLP_EN BIT_APCPU_C1_AUTO_SLP_EN +#define BIT_CA7_C0_AUTO_SLP_EN BIT_APCPU_C0_AUTO_SLP_EN +#define BIT_CA7_C3_WFI_SHUTDOWN_EN BIT_APCPU_C3_WFI_SHUTDOWN_EN +#define BIT_CA7_C2_WFI_SHUTDOWN_EN BIT_APCPU_C2_WFI_SHUTDOWN_EN +#define BIT_CA7_C1_WFI_SHUTDOWN_EN BIT_APCPU_C1_WFI_SHUTDOWN_EN +#define BIT_CA7_C0_WFI_SHUTDOWN_EN BIT_APCPU_C0_WFI_SHUTDOWN_EN +#define BIT_MCU_CA7_C3_SLEEP BIT_MCU_APCPU_C3_SLEEP +#define BIT_MCU_CA7_C2_SLEEP BIT_MCU_APCPU_C2_SLEEP +#define BIT_MCU_CA7_C1_SLEEP BIT_MCU_APCPU_C1_SLEEP +#define BIT_MCU_CA7_C0_SLEEP BIT_MCU_APCPU_C0_SLEEP +#define BIT_CA53_C3_AUTO_SLP_EN BIT_APCPU_C3_AUTO_SLP_EN +#define BIT_CA53_C2_AUTO_SLP_EN BIT_APCPU_C2_AUTO_SLP_EN +#define BIT_CA53_C1_AUTO_SLP_EN BIT_APCPU_C1_AUTO_SLP_EN +#define BIT_CA53_C0_AUTO_SLP_EN BIT_APCPU_C0_AUTO_SLP_EN +#define BIT_CA53_C3_WFI_SHUTDOWN_EN BIT_APCPU_C3_WFI_SHUTDOWN_EN +#define BIT_CA53_C2_WFI_SHUTDOWN_EN BIT_APCPU_C2_WFI_SHUTDOWN_EN +#define BIT_CA53_C1_WFI_SHUTDOWN_EN BIT_APCPU_C1_WFI_SHUTDOWN_EN +#define BIT_CA53_C0_WFI_SHUTDOWN_EN BIT_APCPU_C0_WFI_SHUTDOWN_EN +#define BIT_MCU_CA53_C3_SLEEP BIT_MCU_APCPU_C3_SLEEP +#define BIT_MCU_CA53_C2_SLEEP BIT_MCU_APCPU_C2_SLEEP +#define BIT_MCU_CA53_C1_SLEEP BIT_MCU_APCPU_C1_SLEEP +#define BIT_MCU_CA53_C0_SLEEP BIT_MCU_APCPU_C0_SLEEP +#define BIT_AP_PERI_FORCE_ON ( BIT(2) ) +#define BIT_AP_PERI_FORCE_SLP ( BIT(1) ) +#define BIT_AP_APB_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_AP_SYS_AUTO_SLEEP_CFG */ +#define BIT_GSP_CKG_FORCE_EN ( BIT(9) ) +#define BIT_GSP_AUTO_GATE_EN ( BIT(8) ) +#define BIT_APCPU_TRACE_FORCE_SLEEP ( BIT(7) ) +#define BIT_APCPU_TRACE_AUTO_GATE_EN ( BIT(6) ) +#define BIT_AP_AHB_AUTO_GATE_EN ( BIT(5) ) +#define BIT_AP_EMC_AUTO_GATE_EN ( BIT(4) ) +#define BIT_APCPU_EMC_AUTO_GATE_EN ( BIT(3) ) +#define BIT_APCPU_DBG_FORCE_SLEEP ( BIT(2) ) +#define BIT_APCPU_DBG_AUTO_GATE_EN ( BIT(1) ) +#define BIT_APCPU_CORE_AUTO_GATE_EN ( BIT(0) ) +#define BIT_CA7_EMC_AUTO_GATE_EN BIT_APCPU_EMC_AUTO_GATE_EN +#define BIT_CA7_DBG_FORCE_SLEEP BIT_APCPU_DBG_FORCE_SLEEP +#define BIT_CA7_DBG_AUTO_GATE_EN BIT_APCPU_DBG_AUTO_GATE_EN +#define BIT_CA7_CORE_AUTO_GATE_EN BIT_APCPU_CORE_AUTO_GATE_EN +#define BIT_CA53_EMC_AUTO_GATE_EN BIT_APCPU_EMC_AUTO_GATE_EN +#define BIT_CA53_DBG_FORCE_SLEEP BIT_APCPU_DBG_FORCE_SLEEP +#define BIT_CA53_DBG_AUTO_GATE_EN BIT_APCPU_DBG_AUTO_GATE_EN +#define BIT_CA53_CORE_AUTO_GATE_EN BIT_APCPU_CORE_AUTO_GATE_EN + +/* bits definitions for register REG_AP_AHB_HOLDING_PEN */ +#define BITS_HOLDING_PEN(_x_) ( (_x_) << 0 ) + +/* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C0 */ +#define BITS_JMP_ADDR_APCPU_C0(_x_) (_x_) +#define BITS_JMP_ADDR_CA7_C0(_x_) BITS_JMP_ADDR_APCPU_C0 + +/* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C1 */ +#define BITS_JMP_ADDR_APCPU_C1(_x_) (_x_) +#define BITS_JMP_ADDR_CA7_C1(_x_) BITS_JMP_ADDR_APCPU_C1(_x_) + +/* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C2 */ +#define BITS_JMP_ADDR_APCPU_C2(_x_) (_x_) +#define BITS_JMP_ADDR_CA7_C2(_x_) BITS_JMP_ADDR_APCPU_C2(_x_) + +/* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C3 */ +#define BITS_JMP_ADDR_APCPU_C3(_x_) (_x_) +#define BITS_JMP_ADDR_CA7_C3(_x_) BITS_JMP_ADDR_APCPU_C3(_x_) + +/* bits definitions for register REG_AP_AHB_CA7_C0_PU_LOCK */ +#define BIT_APCPU_C0_PU_LOCK ( BIT(0) ) +#define BIT_CA7_C0_PU_LOCK BIT_APCPU_C0_PU_LOCK +#define BIT_CA53_C0_PU_LOCK BIT_APCPU_C0_PU_LOCK + +/* bits definitions for register REG_AP_AHB_CA7_C1_PU_LOCK */ +#define BIT_APCPU_C1_PU_LOCK ( BIT(0) ) +#define BIT_CA7_C1_PU_LOCK BIT_APCPU_C1_PU_LOCK +#define BIT_CA53_C1_PU_LOCK BIT_APCPU_C1_PU_LOCK + +/* bits definitions for register REG_AP_AHB_CA7_C2_PU_LOCK */ +#define BIT_APCPU_C2_PU_LOCK ( BIT(0) ) +#define BIT_CA7_C2_PU_LOCK BIT_APCPU_C2_PU_LOCK +#define BIT_CA53_C2_PU_LOCK BIT_APCPU_C2_PU_LOCK + +/* bits definitions for register REG_AP_AHB_CA7_C3_PU_LOCK */ +#define BIT_APCPU_C3_PU_LOCK ( BIT(0) ) +#define BIT_CA7_C3_PU_LOCK BIT_APCPU_C3_PU_LOCK +#define BIT_CA53_C3_PU_LOCK BIT_APCPU_C3_PU_LOCK + +/* bits definitions for register REG_AP_AHB_APCPU_CKG_DIV_CFG */ +#define BITS_APCPU_LIT_ATB_CKG_DIV(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_APCPU_BIG_ATB_CKG_DIV(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_APCPU_LIT_DBG_CKG_DIV(_X_) ( (_X_) << 17 & (BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_APCPU_BIG_DBG_CKG_DIV(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)|BIT(16)) ) +#define BITS_APCPU_LIT_ACE_CKG_DIV(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_APCPU_BIG_ACE_CKG_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_APCPU_LIT_MCU_CKG_DIV(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BITS_APCPU_BIG_MCU_CKG_DIV(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AP_AHB_MCU_PAUSE */ +#define BIT_DMA_ACT_LIGHT_EN ( BIT(5) ) +#define BIT_MCU_SLEEP_FOLLOW_APCPU_EN ( BIT(4) ) +#define BIT_MCU_SLEEP_FOLLOW_CA7_EN BIT_MCU_SLEEP_FOLLOW_APCPU_EN +#define BIT_MCU_SLEEP_FOLLOW_CA53_EN BIT_MCU_SLEEP_FOLLOW_APCPU_EN +#define BIT_MCU_LIGHT_SLEEP_EN ( BIT(3) ) +#define BIT_MCU_DEEP_SLEEP_EN ( BIT(2) ) +#define BIT_MCU_SYS_SLEEP_EN ( BIT(1) ) +#define BIT_MCU_CORE_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_MISC_CKG_EN */ +#define BIT_ASHB_APCPU_DBG_VLD ( BIT(9) ) +#define BIT_ASHB_APCPU_DBG_EN ( BIT(8) ) +#define BIT_ASHB_CA7_DBG_VLD BIT_ASHB_APCPU_DBG_VLD +#define BIT_ASHB_CA7_DBG_EN BIT_ASHB_APCPU_DBG_EN +#define BIT_ASHB_CA53_DBG_VLD BIT_ASHB_APCPU_DBG_VLD +#define BIT_ASHB_CA53_DBG_EN BIT_ASHB_APCPU_DBG_EN +#define BIT_DISP_TMC_CKG_EN ( BIT(4) ) +#define BIT_DPHY_REF_CKG_EN ( BIT(1) ) +#define BIT_DPHY_CFG_CKG_EN ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_CA7_C0_AUTO_FORCE_SHUTDOWN_EN */ +#define BIT_APCPU_C0_AUTO_FORCE_SHUTDOWN_EN ( BIT(0) ) +#define BIT_CA7_C0_AUTO_FORCE_SHUTDOWN_EN BIT_APCPU_C0_AUTO_FORCE_SHUTDOWN_EN +#define BIT_CA53_C0_AUTO_FORCE_SHUTDOWN_EN BIT_APCPU_C0_AUTO_FORCE_SHUTDOWN_EN + +/* bits definitions for register REG_AP_AHB_CA7_C1_AUTO_FORCE_SHUTDOWN_EN */ +#define BIT_APCPU_C1_AUTO_FORCE_SHUTDOWN_EN ( BIT(0) ) +#define BIT_CA7_C1_AUTO_FORCE_SHUTDOWN_EN BIT_APCPU_C1_AUTO_FORCE_SHUTDOWN_EN +#define BIT_CA53_C1_AUTO_FORCE_SHUTDOWN_EN BIT_APCPU_C1_AUTO_FORCE_SHUTDOWN_EN + +/* bits definitions for register REG_AP_AHB_CA7_C2_AUTO_FORCE_SHUTDOWN_EN */ +#define BIT_APCPU_C2_AUTO_FORCE_SHUTDOWN_EN ( BIT(0) ) +#define BIT_CA7_C2_AUTO_FORCE_SHUTDOWN_EN BIT_APCPU_C2_AUTO_FORCE_SHUTDOWN_EN +#define BIT_CA53_C2_AUTO_FORCE_SHUTDOWN_EN BIT_APCPU_C2_AUTO_FORCE_SHUTDOWN_EN + +/* bits definitions for register REG_AP_AHB_CA7_C3_AUTO_FORCE_SHUTDOWN_EN */ +#define BIT_APCPU_C3_AUTO_FORCE_SHUTDOWN_EN ( BIT(0) ) +#define BIT_CA7_C3_AUTO_FORCE_SHUTDOWN_EN BIT_APCPU_C3_AUTO_FORCE_SHUTDOWN_EN +#define BIT_CA53_C3_AUTO_FORCE_SHUTDOWN_EN BIT_APCPU_C3_AUTO_FORCE_SHUTDOWN_EN + +/* bits definitions for register REG_AP_AHB_APCPU_CKG_SEL_CFG */ +#define BITS_APCPU_LIT_MCU_CKG_SEL(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_APCPU_BIG_MCU_CKG_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AP_AHB_APCPU_AUTO_GATE_EN */ +#define BIT_APCPU_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_APCPU_GIC_CKG_CFG */ +#define BIT_APCPU_GIC_CKG_EN ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_APCPU_GIC_CLK_CFG */ +#define BITS_APCPU_GIC_CLK_DIV(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_APCPU_GIC_CLK_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_AHB_APCPU_LIT_CKG_EN */ +#define BIT_APCPU_LIT_ATB_EN ( BIT(2) ) +#define BIT_APCPU_LIT_DBG_EN ( BIT(1) ) +#define BIT_APCPU_LIT_CORE_EN ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_APCPU_BIG_CKG_EN */ +#define BIT_APCPU_BIG_ATB_EN ( BIT(2) ) +#define BIT_APCPU_BIG_DBG_EN ( BIT(1) ) +#define BIT_APCPU_BIG_CORE_EN ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_APCPU_LIT_L2FLUSH */ +#define BIT_APCPU_LIT_L2FLUSHDONE ( BIT(1) ) +#define BIT_APCPU_LIT_L2FLUSHREQ ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_APCPU_BIG_L2FLUSH */ +#define BIT_APCPU_BIG_L2FLUSHDONE ( BIT(1) ) +#define BIT_APCPU_BIG_L2FLUSHREQ ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_APCPU_CCI_BASE_H25 */ +#define BITS_APCPU_CCI_BASE_H25(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) ) + +/* bits definitions for register REG_AP_AHB_APCPU_CCI_CTRL */ +#define BITS_APCPU_CCI_ARQOS_LIT(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_APCPU_CCI_AWQOS_LIT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_APCPU_CCI_ARQOS_BIG(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_APCPU_CCI_AWQOS_BIG(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_APCPU_CCI_BUFOVRD(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_APCPU_CCI_QOSOVRD(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register REG_AP_AHB_MISC_CFG */ +#define BIT_APCPU_DAP_SNOOP_DISABLE ( BIT(25) ) +#define BIT_APCPU_BIG_INT_DISABLE ( BIT(24) ) +#define BIT_APCPU_IRAM_REMAP ( BIT(23) ) +#define BIT_APCPU_L2RAM_LIGHT_SLEEP_EN ( BIT(22) ) +#define BIT_APCPU_AUTO_REG_SAVE_TRIG_SEL ( BIT(21) ) +#define BIT_APCPU_AUTO_REG_SAVE_EN ( BIT(20) ) +#define BITS_EMMC_SLOT_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_SDIO0_SLOT_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_BUSMON2_CHN_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_BUSMON1_CHN_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_BUSMON0_CHN_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_SDIO2_SLOT_SEL(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_SDIO1_SLOT_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_AHB_AP_MAIN_MTX_HPROT_CFG */ +#define BITS_HPROT_NFC(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_HPROT_EMMC(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_HPROT_SDIO2(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_HPROT_SDIO1(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_HPROT_SDIO0(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_HPROT_DMAW(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_HPROT_DMAR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AP_AHB_APCPU_STANDBY_STATUS */ +#define BIT_STANDBYWFIL2_BIG ( BIT(24) ) +#define BITS_STANDBYWFE_BIG(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_STANDBYWFI_BIG(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BIT_STANDBYWFIL2_LIT ( BIT(8) ) +#define BITS_STANDBYWFE_LIT(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_STANDBYWFI_LIT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AP_AHB_NANC_CLK_CFG */ +#define BITS_CLK_NANDC2X_DIV(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_CLK_NANDC2X_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_AHB_LVDS_CFG */ +#define BITS_LVDS_TXCLKDATA(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)) ) +#define BITS_LVDS_TXCOM(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_LVDS_TXSLEW(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_LVDS_TXSW(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_LVDS_TXRERSER(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_LVDS_PRE_EMP(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)) ) +#define BIT_LVDS_TXPD ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_LVDS_PLL_CFG0 */ +#define BIT_LVDS_PLL_LOCK_DET ( BIT(31) ) +#define BITS_LVDS_PLL_REFIN(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_LVDS_PLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BIT_LVDS_PLL_DIV_S ( BIT(18) ) +#define BITS_LVDS_PLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_LVDS_PLLN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) ) + +/* bits definitions for register REG_AP_AHB_LVDS_PLL_CFG1 */ +#define BITS_LVDS_PLL_KINT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_LVDS_PLL_RSV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_LVDS_PLL_MOD_EN ( BIT(7) ) +#define BIT_LVDS_PLL_SDM_EN ( BIT(6) ) +#define BITS_LVDS_PLL_NINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_AP_AHB_AP_QOS_CFG */ +#define BITS_QOS_R_TMC(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_QOS_W_TMC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_QOS_R_DISPC(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_QOS_W_DISPC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AP_AHB_OTG_PHY_TUNE */ +#define BIT_OTG_TXPREEMPPULSETUNE ( BIT(20) ) +#define BITS_OTG_TXRESTUNE(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_OTG_TXHSXVTUNE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_OTG_TXVREFTUNE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_OTG_TXPREEMPAMPTUNE(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_OTG_TXRISETUNE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_OTG_TXFSLSTUNE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_OTG_SQRXTUNE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AP_AHB_OTG_PHY_TEST */ +#define BIT_OTG_ATERESET ( BIT(31) ) +#define BIT_OTG_VBUS_VALID_EXT_SEL ( BIT(26) ) +#define BIT_OTG_VBUS_VALID_EXT ( BIT(25) ) +#define BIT_OTG_OTGDISABLE ( BIT(24) ) +#define BIT_OTG_TESTBURNIN ( BIT(21) ) +#define BIT_OTG_LOOPBACKENB ( BIT(20) ) +#define BITS_OTG_TESTDATAOUT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_OTG_VATESTENB(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) ) +#define BIT_OTG_TESTCLK ( BIT(13) ) +#define BIT_OTG_TESTDATAOUTSEL ( BIT(12) ) +#define BITS_OTG_TESTADDR(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_OTG_TESTDATAIN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_AP_AHB_OTG_PHY_CTRL */ +#define BITS_OTG_SS_SCALEDOWNMODE(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BIT_OTG_TXBITSTUFFENH ( BIT(23) ) +#define BIT_OTG_TXBITSTUFFEN ( BIT(22) ) +#define BIT_OTG_DMPULLDOWN ( BIT(21) ) +#define BIT_OTG_DPPULLDOWN ( BIT(20) ) +#define BIT_OTG_DMPULLUP ( BIT(9) ) +#define BIT_OTG_COMMONONN ( BIT(8) ) +#define BITS_OTG_REFCLKSEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_OTG_FSEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AP_AHB_HSIC_PHY_TUNE */ +#define BITS_HSIC_REFCLK_DIV(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) ) +#define BIT_HSIC_TXPREEMPPULSETUNE ( BIT(20) ) +#define BITS_HSIC_TXRESTUNE(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_HSIC_TXHSXVTUNE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_HSIC_TXVREFTUNE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_HSIC_TXPREEMPAMPTUNE(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_HSIC_TXRISETUNE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_HSIC_TXFSLSTUNE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_HSIC_SQRXTUNE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AP_AHB_HSIC_PHY_TEST */ +#define BIT_HSIC_ATERESET ( BIT(31) ) +#define BIT_HSIC_VBUS_VALID_EXT_SEL ( BIT(26) ) +#define BIT_HSIC_VBUS_VALID_EXT ( BIT(25) ) +#define BIT_HSIC_OTGDISABLE ( BIT(24) ) +#define BIT_HSIC_TESTBURNIN ( BIT(21) ) +#define BIT_HSIC_LOOPBACKENB ( BIT(20) ) +#define BITS_HSIC_TESTDATAOUT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_HSIC_VATESTENB(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) ) +#define BIT_HSIC_TESTCLK ( BIT(13) ) +#define BIT_HSIC_TESTDATAOUTSEL ( BIT(12) ) +#define BITS_HSIC_TESTADDR(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_HSIC_TESTDATAIN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_AP_AHB_HSIC_PHY_CTRL */ +#define BITS_HSIC_SS_SCALEDOWNMODE(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BIT_HSIC_TXBITSTUFFENH ( BIT(23) ) +#define BIT_HSIC_TXBITSTUFFEN ( BIT(22) ) +#define BIT_HSIC_DMPULLDOWN ( BIT(21) ) +#define BIT_HSIC_DPPULLDOWN ( BIT(20) ) +#define BIT_HSIC_IF_MODE ( BIT(16) ) +#define BIT_IF_SELECT_HSIC ( BIT(13) ) +#define BIT_HSIC_DBNCE_FLTR_BYPASS ( BIT(12) ) +#define BIT_HSIC_DMPULLUP ( BIT(9) ) +#define BIT_HSIC_COMMONONN ( BIT(8) ) +#define BITS_HSIC_REFCLKSEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_HSIC_FSEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_AP_AHB_ZIP_MTX_QOS_CFG */ +#define BITS_ZIPMTX_S0_ARQOS(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_ZIPMTX_S0_AWQOS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_ZIPDEC_ARQOS(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_ZIPDEC_AWQOS(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_ZIPENC_ARQOS(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_ZIPENC_AWQOS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_AP_AHB_APCPU_QCHN_CTL_BIG */ +#define BITS_APCPU_Q_NEG_THD_BIG(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_APCPU_Q_WAIT_GAP_BIG(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_APCPU_Q_PGEN_DUR_BIG(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_APCPU_Q_WAIT_REQ_BIG(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_APCPU_Q_RETN_BYP_BIG ( BIT(2) ) +#define BIT_APCPU_Q_RETN_SEL_BIG ( BIT(1) ) +#define BIT_APCPU_Q_LP_EN_BIG ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_APCPU_QCHN_STA_BIG */ +#define BITS_APCPU_Q_STATUS_BIG(_X_) (_X_) + +/* bits definitions for register REG_AP_AHB_APCPU_QCHN_CTL_LIT */ +#define BITS_APCPU_Q_NEG_THD_LIT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_APCPU_Q_WAIT_GAP_LIT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_APCPU_Q_PGEN_DUR_LIT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_APCPU_Q_WAIT_REQ_LIT(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_APCPU_Q_RETN_BYP_LIT ( BIT(2) ) +#define BIT_APCPU_Q_RETN_SEL_LIT ( BIT(1) ) +#define BIT_APCPU_Q_LP_EN_LIT ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_APCPU_QCHN_STA_LIT */ +#define BITS_APCPU_Q_STATUS_LIT(_X_) (_X_) + +/* bits definitions for register REG_AP_AHB_GSP_SEL */ +#define BIT_GSP_VER_SEL ( BIT(0) ) + +/* bits definitions for register REG_AP_AHB_RES_REG */ +#define BITS_RES_REG(_X_) (_X_) + +/* bits definitions for register REG_AP_AHB_CHIP_ID */ +#define BITS_CHIP_ID(_X_) (_X_) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_ap_apb.h b/include/soc/sprd/chip_x35lt8/__regs_ap_apb.h new file mode 100644 index 00000000..facd6da4 --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_ap_apb.h @@ -0,0 +1,94 @@ +/* the head file modifier: g 2015-03-19 15:40:29*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_AP_APB_HEADFILE_H__ +#define __H_REGS_AP_APB_HEADFILE_H__ __FILE__ + +#define REGS_AP_APB + +/* registers definitions for AP_APB */ +#define REG_AP_APB_APB_EB SCI_ADDR(REGS_AP_APB_BASE, 0x0000)/*AHB_EB*/ +#define REG_AP_APB_APB_RST SCI_ADDR(REGS_AP_APB_BASE, 0x0004)/*AHB_RST*/ +#define REG_AP_APB_APB_MISC_CTRL SCI_ADDR(REGS_AP_APB_BASE, 0x0008)/*APB_MISC_CTRL*/ + + + +/* bits definitions for register REG_AP_APB_APB_EB */ +#define BIT_INTC3_EB ( BIT(22) ) +#define BIT_INTC2_EB ( BIT(21) ) +#define BIT_INTC1_EB ( BIT(20) ) +#define BIT_INTC0_EB ( BIT(19) ) +#define BIT_CKG_EB ( BIT(18) ) +#define BIT_AP_CKG_EB ( BIT_CKG_EB ) +#define BIT_UART4_EB ( BIT(17) ) +#define BIT_UART3_EB ( BIT(16) ) +#define BIT_UART2_EB ( BIT(15) ) +#define BIT_UART1_EB ( BIT(14) ) +#define BIT_UART0_EB ( BIT(13) ) +#define BIT_I2C4_EB ( BIT(12) ) +#define BIT_I2C3_EB ( BIT(11) ) +#define BIT_I2C2_EB ( BIT(10) ) +#define BIT_I2C1_EB ( BIT(9) ) +#define BIT_I2C0_EB ( BIT(8) ) +#define BIT_SPI2_EB ( BIT(7) ) +#define BIT_SPI1_EB ( BIT(6) ) +#define BIT_SPI0_EB ( BIT(5) ) +#define BIT_IIS3_EB ( BIT(4) ) +#define BIT_IIS2_EB ( BIT(3) ) +#define BIT_IIS1_EB ( BIT(2) ) +#define BIT_IIS0_EB ( BIT(1) ) +#define BIT_SIM0_EB ( BIT(0) ) + +/* bits definitions for register REG_AP_APB_APB_RST */ +#define BIT_INTC3_SOFT_RST ( BIT(22) ) +#define BIT_INTC2_SOFT_RST ( BIT(21) ) +#define BIT_INTC1_SOFT_RST ( BIT(20) ) +#define BIT_INTC0_SOFT_RST ( BIT(19) ) +#define BIT_CKG_SOFT_RST ( BIT(18) ) +#define BIT_AP_CKG_SOFT_RST BIT_CKG_SOFT_RST +#define BIT_UART4_SOFT_RST ( BIT(17) ) +#define BIT_UART3_SOFT_RST ( BIT(16) ) +#define BIT_UART2_SOFT_RST ( BIT(15) ) +#define BIT_UART1_SOFT_RST ( BIT(14) ) +#define BIT_UART0_SOFT_RST ( BIT(13) ) +#define BIT_I2C4_SOFT_RST ( BIT(12) ) +#define BIT_I2C3_SOFT_RST ( BIT(11) ) +#define BIT_I2C2_SOFT_RST ( BIT(10) ) +#define BIT_I2C1_SOFT_RST ( BIT(9) ) +#define BIT_I2C0_SOFT_RST ( BIT(8) ) +#define BIT_SPI2_SOFT_RST ( BIT(7) ) +#define BIT_SPI1_SOFT_RST ( BIT(6) ) +#define BIT_SPI0_SOFT_RST ( BIT(5) ) +#define BIT_IIS3_SOFT_RST ( BIT(4) ) +#define BIT_IIS2_SOFT_RST ( BIT(3) ) +#define BIT_IIS1_SOFT_RST ( BIT(2) ) +#define BIT_IIS0_SOFT_RST ( BIT(1) ) +#define BIT_SIM0_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_AP_APB_APB_MISC_CTRL */ +#define BIT_SIM_CLK_POLARITY ( BIT(1) ) +#define BIT_FMARK_POLARITY_INV ( BIT(0) ) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_ap_clk.h b/include/soc/sprd/chip_x35lt8/__regs_ap_clk.h new file mode 100644 index 00000000..f7d1073b --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_ap_clk.h @@ -0,0 +1,227 @@ +/* the head file modifier: g 2015-03-19 15:40:59*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_AP_CLK_CORE_HEADFILE_H__ +#define __H_REGS_AP_CLK_CORE_HEADFILE_H__ __FILE__ + +#define REGS_AP_CLK_CORE + +/* registers definitions for AP_CLK_CORE */ +#define REG_AP_CLK_CORE_clk_ap_ahb_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x20)/*clk_ap_ahb_cfg*/ +#define REG_AP_CLK_CORE_clk_ap_apb_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x24)/*clk_ap_apb_cfg*/ +#define REG_AP_CLK_CORE_clk_gsp0_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x28)/*clk_gsp_cfg*/ +#define REG_AP_CLK_CORE_clk_dispc0_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x2c)/*clk_dispc0_cfg*/ +#define REG_AP_CLK_CORE_clk_dispc0_dbi_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x30)/*clk_dispc0_dbi_cfg*/ +#define REG_AP_CLK_CORE_clk_dispc0_dpi_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x34)/*clk_dispc0_dpi_cfg*/ +#define REG_AP_CLK_CORE_clk_nandc_ecc_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x38)/*clk_nandc_ecc_cfg*/ +#define REG_AP_CLK_CORE_clk_sdio0_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x3c)/*clk_sdio0_cfg*/ +#define REG_AP_CLK_CORE_clk_sdio1_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x40)/*clk_sdio1_cfg*/ +#define REG_AP_CLK_CORE_clk_sdio2_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x44)/*clk_sdio2_cfg*/ +#define REG_AP_CLK_CORE_clk_emmc_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x48)/*clk_emmc_cfg*/ +#define REG_AP_CLK_CORE_clk_otg_ref_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x4c)/*clk_otg_ref_cfg*/ +#define REG_AP_CLK_CORE_clk_hsic_ref_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x50)/*clk_hsic_ref_cfg*/ +#define REG_AP_CLK_CORE_clk_uart0_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x54)/*clk_uart0_cfg*/ +#define REG_AP_CLK_CORE_clk_uart1_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x58)/*clk_uart1_cfg*/ +#define REG_AP_CLK_CORE_clk_uart2_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x5c)/*clk_uart2_cfg*/ +#define REG_AP_CLK_CORE_clk_uart3_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x60)/*clk_uart3_cfg*/ +#define REG_AP_CLK_CORE_clk_uart4_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x64)/*clk_uart4_cfg*/ +#define REG_AP_CLK_CORE_clk_i2c0_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x68)/*clk_i2c0_cfg*/ +#define REG_AP_CLK_CORE_clk_i2c1_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x6c)/*clk_i2c1_cfg*/ +#define REG_AP_CLK_CORE_clk_i2c2_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x70)/*clk_i2c2_cfg*/ +#define REG_AP_CLK_CORE_clk_i2c3_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x74)/*clk_i2c3_cfg*/ +#define REG_AP_CLK_CORE_clk_i2c4_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x78)/*clk_i2c4_cfg*/ +#define REG_AP_CLK_CORE_clk_spi0_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x7c)/*clk_spi0_cfg*/ +#define REG_AP_CLK_CORE_clk_spi1_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x80)/*clk_spi1_cfg*/ +#define REG_AP_CLK_CORE_clk_spi2_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x84)/*clk_spi2_cfg*/ +#define REG_AP_CLK_CORE_clk_iis0_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x88)/*clk_iis0_cfg*/ +#define REG_AP_CLK_CORE_clk_iis1_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x8c)/*clk_iis1_cfg*/ +#define REG_AP_CLK_CORE_clk_iis2_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x90)/*clk_iis2_cfg*/ +#define REG_AP_CLK_CORE_clk_iis3_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x94)/*clk_iis3_cfg*/ +#define REG_AP_CLK_CORE_clk_zipenc_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x98)/*clk_zipenc_cfg*/ +#define REG_AP_CLK_CORE_clk_zipdec_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0x9c)/*clk_zipdec_cfg*/ +#define REG_AP_CLK_CORE_clk_gsp1_cfg SCI_ADDR(REGS_AP_CLK_CORE_BASE, 0xa0)/*clk_gsp1_cfg*/ +#define REG_AP_CLK_AP_AHB_CFG REG_AP_CLK_CORE_clk_ap_ahb_cfg +#define REG_AP_CLK_AP_APB_CFG REG_AP_CLK_CORE_clk_ap_apb_cfg +#define REG_AP_CLK_GSP_CFG REG_AP_CLK_CORE_clk_gsp0_cfg +#define REG_AP_CLK_DISPC0_CFG REG_AP_CLK_CORE_clk_dispc0_cfg +#define REG_AP_CLK_DISPC0_DBI_CFG REG_AP_CLK_CORE_clk_dispc0_dbi_cfg +#define REG_AP_CLK_DISPC0_DPI_CFG REG_AP_CLK_CORE_clk_dispc0_dpi_cfg +#define REG_AP_CLK_NANDC_ECC_CFG REG_AP_CLK_CORE_clk_nandc_ecc_cfg +#define REG_AP_CLK_SDIO0_CFG REG_AP_CLK_CORE_clk_sdio0_cfg +#define REG_AP_CLK_SDIO1_CFG REG_AP_CLK_CORE_clk_sdio1_cfg +#define REG_AP_CLK_SDIO2_CFG REG_AP_CLK_CORE_clk_sdio2_cfg +#define REG_AP_CLK_EMMC_CFG REG_AP_CLK_CORE_clk_emmc_cfg +#define REG_AP_CLK_OTG_REF_CFG REG_AP_CLK_CORE_clk_otg_ref_cfg +#define REG_AP_CLK_HSIC_REF_CFG REG_AP_CLK_CORE_clk_hsic_ref_cfg +#define REG_AP_CLK_UART0_CFG REG_AP_CLK_CORE_clk_uart0_cfg +#define REG_AP_CLK_UART1_CFG REG_AP_CLK_CORE_clk_uart1_cfg +#define REG_AP_CLK_UART2_CFG REG_AP_CLK_CORE_clk_uart2_cfg +#define REG_AP_CLK_UART3_CFG REG_AP_CLK_CORE_clk_uart3_cfg +#define REG_AP_CLK_UART4_CFG REG_AP_CLK_CORE_clk_uart4_cfg +#define REG_AP_CLK_I2C0_CFG REG_AP_CLK_CORE_clk_i2c0_cfg +#define REG_AP_CLK_I2C1_CFG REG_AP_CLK_CORE_clk_i2c1_cfg +#define REG_AP_CLK_I2C2_CFG REG_AP_CLK_CORE_clk_i2c2_cfg +#define REG_AP_CLK_I2C3_CFG REG_AP_CLK_CORE_clk_i2c3_cfg +#define REG_AP_CLK_I2C4_CFG REG_AP_CLK_CORE_clk_i2c4_cfg +#define REG_AP_CLK_SPI0_CFG REG_AP_CLK_CORE_clk_spi0_cfg +#define REG_AP_CLK_SPI1_CFG REG_AP_CLK_CORE_clk_spi1_cfg +#define REG_AP_CLK_SPI2_CFG REG_AP_CLK_CORE_clk_spi2_cfg +#define REG_AP_CLK_IIS0_CFG REG_AP_CLK_CORE_clk_iis0_cfg +#define REG_AP_CLK_IIS1_CFG REG_AP_CLK_CORE_clk_iis1_cfg +#define REG_AP_CLK_IIS2_CFG REG_AP_CLK_CORE_clk_iis2_cfg +#define REG_AP_CLK_IIS3_CFG REG_AP_CLK_CORE_clk_iis3_cfg +#define REG_AP_CLK_ZIPENC_CFG REG_AP_CLK_CORE_clk_zipenc_cfg +#define REG_AP_CLK_ZIPDEC_CFG REG_AP_CLK_CORE_clk_zipdec_cfg + + +/* bits definitions for register REG_AP_CLK_CORE_clk_ap_ahb_cfg */ +#define BITS_CLK_AP_AHB_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_ap_apb_cfg */ +#define BITS_CLK_AP_APB_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_gsp0_cfg */ +#define BITS_CLK_GSP0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_dispc0_cfg */ +#define BITS_CLK_DISPC0_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_DISPC0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_dispc0_dbi_cfg */ +#define BITS_CLK_DISPC0_DBI_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_DISPC0_DBI_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_dispc0_dpi_cfg */ +#define BIT_CLK_DISPC0_DPI_PAD_SEL ( BIT(16) ) +#define BITS_CLK_DISPC0_DPI_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_CLK_DISPC0_DPI_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_nandc_ecc_cfg */ +#define BIT_CLK_NANDC_ECC_SEL ( BIT(0) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_sdio0_cfg */ +#define BITS_CLK_SDIO0_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_SDIO0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_sdio1_cfg */ +#define BITS_CLK_SDIO1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_sdio2_cfg */ +#define BITS_CLK_SDIO2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_emmc_cfg */ +#define BITS_CLK_EMMC_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_otg_ref_cfg */ +#define BIT_CLK_OTG_REF_SEL ( BIT(0) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_hsic_ref_cfg */ +#define BIT_CLK_HSIC_REF_SEL ( BIT(0) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_uart0_cfg */ +#define BITS_CLK_UART0_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_UART0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_uart1_cfg */ +#define BITS_CLK_UART1_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_UART1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_uart2_cfg */ +#define BITS_CLK_UART2_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_UART2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_uart3_cfg */ +#define BITS_CLK_UART3_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_UART3_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_uart4_cfg */ +#define BITS_CLK_UART4_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_UART4_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_i2c0_cfg */ +#define BITS_CLK_I2C0_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_I2C0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_i2c1_cfg */ +#define BITS_CLK_I2C1_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_I2C1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_i2c2_cfg */ +#define BITS_CLK_I2C2_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_I2C2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_i2c3_cfg */ +#define BITS_CLK_I2C3_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_I2C3_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_i2c4_cfg */ +#define BITS_CLK_I2C4_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_I2C4_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_spi0_cfg */ +#define BIT_CLK_SPI0_PAD_SEL ( BIT(16) ) +#define BITS_CLK_SPI0_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_SPI0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_spi1_cfg */ +#define BIT_CLK_SPI1_PAD_SEL ( BIT(16) ) +#define BITS_CLK_SPI1_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_SPI1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_spi2_cfg */ +#define BIT_CLK_SPI2_PAD_SEL ( BIT(16) ) +#define BITS_CLK_SPI2_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_SPI2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_iis0_cfg */ +#define BIT_CLK_IIS0_PAD_SEL ( BIT(16) ) +#define BITS_CLK_IIS0_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_IIS0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_iis1_cfg */ +#define BIT_CLK_IIS1_PAD_SEL ( BIT(16) ) +#define BITS_CLK_IIS1_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_IIS1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_iis2_cfg */ +#define BIT_CLK_IIS2_PAD_SEL ( BIT(16) ) +#define BITS_CLK_IIS2_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_IIS2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_iis3_cfg */ +#define BIT_CLK_IIS3_PAD_SEL ( BIT(16) ) +#define BITS_CLK_IIS3_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_IIS3_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_zipenc_cfg */ +#define BITS_CLK_ZIPENC_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_zipdec_cfg */ +#define BITS_CLK_ZIPDEC_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_AP_CLK_CORE_clk_gsp1_cfg */ +#define BITS_CLK_GSP1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_arm7_ahb_rf.h b/include/soc/sprd/chip_x35lt8/__regs_arm7_ahb_rf.h new file mode 100644 index 00000000..5a0eb47e --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_arm7_ahb_rf.h @@ -0,0 +1,161 @@ +/* the head file modifier: g 2015-03-19 15:41:25*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_ARM7_AHB_RF_HEADFILE_H__ +#define __H_REGS_ARM7_AHB_RF_HEADFILE_H__ __FILE__ + +#define REGS_ARM7_AHB_RF + +/* registers definitions for ARM7_AHB_RF */ +#define REG_ARM7_AHB_RF_ARM7_EB SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0000)/*ARM7_EB*/ +#define REG_ARM7_AHB_RF_ARM7_SOFT_RST SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0004)/*ARM7_SOFT_RST*/ +#define REG_ARM7_AHB_RF_AHB_PAUSE SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0008)/*AHB_PAUSE*/ +#define REG_ARM7_AHB_RF_ARM7_SLP_CTL SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x000C)/*ARM7_SLP_CTL*/ +#define REG_ARM7_AHB_RF_CLK_EMC4X_CFG SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0010)/*CLK_EMC4X_CFG*/ +#define REG_ARM7_AHB_RF_APCPU_LIT_RVBADDR0 SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0020)/*APCPU_LIT_RVBADDR0*/ +#define REG_ARM7_AHB_RF_APCPU_LIT_RVBADDR1 SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0024)/*APCPU_LIT_RVBADDR1*/ +#define REG_ARM7_AHB_RF_APCPU_LIT_RVBADDR2 SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0028)/*APCPU_LIT_RVBADDR2*/ +#define REG_ARM7_AHB_RF_APCPU_LIT_RVBADDR3 SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x002C)/*APCPU_LIT_RVBADDR3*/ +#define REG_ARM7_AHB_RF_APCPU_LIT_PROT_CTL SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0030)/*APCPU_LIT_PROT_CTL*/ +#define REG_ARM7_AHB_RF_APCPU_LIT_COMM_CTL SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0034)/*APCPU_LIT_COMM_CTL*/ +#define REG_ARM7_AHB_RF_ARM7_RES_REG SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0044)/*ARM7_RES_REG*/ +#define REG_ARM7_AHB_RF_APCPU_BIG_RVBADDR0 SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0050)/*APCPU_BIG_RVBADDR0*/ +#define REG_ARM7_AHB_RF_APCPU_BIG_RVBADDR1 SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0054)/*APCPU_BIG_RVBADDR1*/ +#define REG_ARM7_AHB_RF_APCPU_BIG_RVBADDR2 SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0058)/*APCPU_BIG_RVBADDR2*/ +#define REG_ARM7_AHB_RF_APCPU_BIG_RVBADDR3 SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x005C)/*APCPU_BIG_RVBADDR3*/ +#define REG_ARM7_AHB_RF_APCPU_BIG_PROT_CTL SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0060)/*APCPU_BIG_PROT_CTL*/ +#define REG_ARM7_AHB_RF_APCPU_BIG_COMM_CTL SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0064)/*APCPU_BIG_COMM_CTL*/ +#define REG_ARM7_AHB_RF_CSSYS_PROT_CTL SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0070)/*CSSYS_PROT_CTL*/ +#define REG_ARM7_AHB_RF_CCI_PROT_CTL SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0074)/*CCI_PROT_CTL*/ + + + +/* bits definitions for register REG_ARM7_AHB_RF_ARM7_EB */ +#define BIT_ARM7_GPIO_EB ( BIT(10) ) +#define BIT_ARM7_UART_EB ( BIT(9) ) +#define BIT_ARM7_TMR_EB ( BIT(8) ) +#define BIT_ARM7_SYST_EB ( BIT(7) ) +#define BIT_ARM7_WDG_EB ( BIT(6) ) +#define BIT_ARM7_EIC_EB ( BIT(5) ) +#define BIT_ARM7_INTC_EB ( BIT(4) ) +#define BIT_ARM7_EFUSE_EB ( BIT(3) ) +#define BIT_ARM7_IMC_EB ( BIT(2) ) +#define BIT_ARM7_TIC_EB ( BIT(1) ) +#define BIT_ARM7_DMA_EB ( BIT(0) ) + +/* bits definitions for register REG_ARM7_AHB_RF_ARM7_SOFT_RST */ +#define BIT_ARM7_GPIO_SOFT_RST ( BIT(10) ) +#define BIT_ARM7_UART_SOFT_RST ( BIT(9) ) +#define BIT_ARM7_TMR_SOFT_RST ( BIT(8) ) +#define BIT_ARM7_SYST_SOFT_RST ( BIT(7) ) +#define BIT_ARM7_WDG_SOFT_RST ( BIT(6) ) +#define BIT_ARM7_EIC_SOFT_RST ( BIT(5) ) +#define BIT_ARM7_INTC_SOFT_RST ( BIT(4) ) +#define BIT_ARM7_EFUSE_SOFT_RST ( BIT(3) ) +#define BIT_ARM7_IMC_SOFT_RST ( BIT(2) ) +#define BIT_ARM7_TIC_SOFT_RST ( BIT(1) ) +#define BIT_ARM7_ARCH_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_ARM7_AHB_RF_AHB_PAUSE */ +#define BIT_ARM7_DEEP_SLEEP_EN ( BIT(2) ) +#define BIT_ARM7_SYS_SLEEP_EN ( BIT(1) ) +#define BIT_ARM7_CORE_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_ARM7_AHB_RF_ARM7_SLP_CTL */ +#define BIT_ARM7_SYS_AUTO_GATE_EN ( BIT(2) ) +#define BIT_ARM7_AHB_AUTO_GATE_EN ( BIT(1) ) +#define BIT_ARM7_CORE_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_ARM7_AHB_RF_CLK_EMC4X_CFG */ +#define BITS_CLK_EMC4X_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_EMC4X_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_ARM7_AHB_RF_APCPU_LIT_RVBADDR0 */ +#define BITS_APCPU_LIT_RVBADDR0(_X_) (_X_) + +/* bits definitions for register REG_ARM7_AHB_RF_APCPU_LIT_RVBADDR1 */ +#define BITS_APCPU_LIT_RVBADDR1(_X_) (_X_) + +/* bits definitions for register REG_ARM7_AHB_RF_APCPU_LIT_RVBADDR2 */ +#define BITS_APCPU_LIT_RVBADDR2(_X_) (_X_) + +/* bits definitions for register REG_ARM7_AHB_RF_APCPU_LIT_RVBADDR3 */ +#define BITS_APCPU_LIT_RVBADDR3(_X_) (_X_) + +/* bits definitions for register REG_ARM7_AHB_RF_APCPU_LIT_PROT_CTL */ +#define BITS_APCPU_LIT_SPNIDEN(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_APCPU_LIT_SPIDEN(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_APCPU_LIT_NIDEN(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_APCPU_LIT_DBGEN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_ARM7_AHB_RF_APCPU_LIT_COMM_CTL */ +#define BIT_APCPU_LIT_DBGL1RSTDISABLE ( BIT(17) ) +#define BIT_APCPU_LIT_L2RSTDISABLE ( BIT(16) ) +#define BITS_APCPU_LIT_CFGTE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_APCPU_LIT_AA64NAA32(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_ARM7_AHB_RF_ARM7_RES_REG */ +#define BITS_ARM7_RES_REG_H(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ARM7_RES_REG_L(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) + +/* bits definitions for register REG_ARM7_AHB_RF_APCPU_BIG_RVBADDR0 */ +#define BITS_APCPU_BIG_RVBADDR0(_X_) (_X_) + +/* bits definitions for register REG_ARM7_AHB_RF_APCPU_BIG_RVBADDR1 */ +#define BITS_APCPU_BIG_RVBADDR1(_X_) (_X_) + +/* bits definitions for register REG_ARM7_AHB_RF_APCPU_BIG_RVBADDR2 */ +#define BITS_APCPU_BIG_RVBADDR2(_X_) (_X_) + +/* bits definitions for register REG_ARM7_AHB_RF_APCPU_BIG_RVBADDR3 */ +#define BITS_APCPU_BIG_RVBADDR3(_X_) (_X_) + +/* bits definitions for register REG_ARM7_AHB_RF_APCPU_BIG_PROT_CTL */ +#define BITS_APCPU_BIG_SPNIDEN(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_APCPU_BIG_SPIDEN(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_APCPU_BIG_NIDEN(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_APCPU_BIG_DBGEN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_ARM7_AHB_RF_APCPU_BIG_COMM_CTL */ +#define BIT_APCPU_BIG_DBGL1RSTDISABLE ( BIT(17) ) +#define BIT_APCPU_BIG_L2RSTDISABLE ( BIT(16) ) +#define BITS_APCPU_BIG_CFGTE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_APCPU_BIG_AA64NAA32(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_ARM7_AHB_RF_CSSYS_PROT_CTL */ +#define BIT_CSSYS_DAP_SPIDEN ( BIT(10) ) +#define BIT_CSSYS_DAP_DBGEN ( BIT(8) ) +#define BIT_CSSYS_DAP_DEVICEEN ( BIT(7) ) +#define BIT_CSSYS_STM_NSGUAREN ( BIT(5) ) +#define BIT_CSSYS_SPNIDEN ( BIT(3) ) +#define BIT_CSSYS_SPIDEN ( BIT(2) ) +#define BIT_CSSYS_NIDEN ( BIT(1) ) +#define BIT_CSSYS_DBGEN ( BIT(0) ) + +/* bits definitions for register REG_ARM7_AHB_RF_CCI_PROT_CTL */ +#define BIT_CCI_SPNIDEN ( BIT(3) ) +#define BIT_CCI_NIDEN ( BIT(1) ) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_avs_apb_rf.h b/include/soc/sprd/chip_x35lt8/__regs_avs_apb_rf.h new file mode 100644 index 00000000..e47f8055 --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_avs_apb_rf.h @@ -0,0 +1,104 @@ +/* the head file modifier: g 2015-03-19 15:41:46*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_AVS_APB_RF_HEADFILE_H__ +#define __H_REGS_AVS_APB_RF_HEADFILE_H__ __FILE__ + +#define REGS_AVS_APB_RF + +/* registers definitions for AVS_APB_RF */ +#define REG_AVS_APB_RF_AVS_TUNE_LMT_CFG SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0000)/*AVS_TUNE_LMT_CFG*/ +#define REG_AVS_APB_RF_AVS_TUNE_STATUS SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0004)/*AVS_TUNE_STATUS*/ +#define REG_AVS_APB_RF_AVS_CFG SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0008)/*AVS_CFG*/ +#define REG_AVS_APB_RF_AVS_TUNE_STEP_CFG SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x000C)/*AVS_TUNE_STEP_CFG*/ +#define REG_AVS_APB_RF_AVS_WAIT_CFG SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0010)/*AVS_WAIT_CFG*/ +#define REG_AVS_APB_RF_AVS_INT_CFG SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0014)/*AVS_INT_CFG*/ +#define REG_AVS_APB_RF_AVS_START_SINGLE_ACT SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0018)/*AVS_START_SINGLE_ACT*/ +#define REG_AVS_APB_RF_AVS_START_REPEAT_ACT SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x001C)/*AVS_START_REPEAT_ACT*/ +#define REG_AVS_APB_RF_AVS_HPM_EN SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0020)/*AVS_HPM_EN*/ +#define REG_AVS_APB_RF_AVS_HPM_RPT_ANLS SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0024)/*AVS_HPM_RPT_ANLS*/ +#define REG_AVS_APB_RF_AVS_HPM_RPT_VLD_STATUS_0 SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0028)/*AVS_HPM_RPT_VLD_STATUS_0*/ +#define REG_AVS_APB_RF_AVS_HPM_RPT_VLD_STATUS_1 SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x002C)/*AVS_HPM_RPT_VLD_STATUS_1*/ +#define REG_AVS_APB_RF_AVS_FSM_STS SCI_ADDR(REGS_AVS_APB_RF_BASE, 0x0030)/*AVS_FSM_STS*/ +#define REG_AVS_APB_RF_FSM_STS REG_AVS_APB_RF_AVS_FSM_STS + + +/* bits definitions for register REG_AVS_APB_RF_AVS_TUNE_LMT_CFG */ +#define BITS_VOLT_TUNE_VAL_MAX(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_VOLT_TUNE_VAL_MIN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_TUNE_STATUS */ +#define BITS_VOLT_TUNE_VAL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_VOLT_OBS_VAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_CFG */ +#define BIT_HPM1_RPT_CHKSUM_ERR_EN ( BIT(17) ) +#define BIT_HPM0_RPT_CHKSUM_ERR_EN ( BIT(16) ) +#define BIT_PAUSE_OCCUR_ERR_EN ( BIT(8) ) +#define BIT_VOLT_TUNE_FORBID_EN ( BIT(4) ) +#define BIT_VOLT_OBS_FORBID_EN ( BIT(0) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_TUNE_STEP_CFG */ +#define BITS_VOLT_TUNE_DOWN_STEP(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) ) +#define BITS_VOLT_TUNE_UP_STEP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_WAIT_CFG */ +#define BITS_RND_INTVAL_WAIT_NUM(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_VOLT_STB_WAIT_NUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_INT_CFG */ +#define BIT_AVS_TUNE_DONE_INT_MASK_STATUS ( BIT(13) ) +#define BIT_AVS_TUNE_ERR_INT_MASK_STATUS ( BIT(12) ) +#define BIT_AVS_TUNE_DONE_INT_RAW_STATUS ( BIT(9) ) +#define BIT_AVS_TUNE_ERR_INT_RAW_STATUS ( BIT(8) ) +#define BIT_AVS_TUNE_DONE_INT_CLR ( BIT(5) ) +#define BIT_AVS_TUNE_ERR_INT_CLR ( BIT(4) ) +#define BIT_AVS_TUNE_DONE_INT_EN ( BIT(1) ) +#define BIT_AVS_TUNE_ERR_INT_EN ( BIT(0) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_START_SINGLE_ACT */ +#define BIT_AVS_START_SINGLE_ACT ( BIT(0) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_START_REPEAT_ACT */ +#define BIT_AVS_START_REPEAT_ACT ( BIT(0) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_HPM_EN */ +#define BIT_HPM1_EN ( BIT(1) ) +#define BIT_HPM0_EN ( BIT(0) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_HPM_RPT_ANLS */ +#define BITS_HPM_RPT_TUNE_DWN_MARK(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_HPM_RPT_TUNE_UP_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_HPM_RPT_VLD_STATUS_0 */ +#define BITS_HPM1_RPT_VLD(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_HPM0_RPT_VLD(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_AVS_APB_RF_AVS_HPM_RPT_VLD_STATUS_1 */ + +/* bits definitions for register REG_AVS_APB_RF_AVS_FSM_STS */ +#define BITS_AVS_FSM_STS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_codec_ahb.h b/include/soc/sprd/chip_x35lt8/__regs_codec_ahb.h new file mode 100644 index 00000000..28c975ee --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_codec_ahb.h @@ -0,0 +1,58 @@ +/* the head file modifier: g 2015-03-19 15:44:20*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_CODEC_AHB_HEADFILE_H__ +#define __H_REGS_CODEC_AHB_HEADFILE_H__ __FILE__ + +#define REGS_CODEC_AHB + +/* registers definitions for CODEC_AHB */ +#define REG_CODEC_AHB_AHB_RST SCI_ADDR(REGS_CODEC_AHB_BASE, 0x0000)/*AHB_RST*/ +#define REG_CODEC_AHB_CKG_ENABLE SCI_ADDR(REGS_CODEC_AHB_BASE, 0x0004)/*CKG_ENABLE*/ +#define REG_CODEC_AHB_CLOCK_SEL SCI_ADDR(REGS_CODEC_AHB_BASE, 0x0008)/*CLOCK_SEL*/ +#define REG_CODEC_AHB_CODA7_STAT SCI_ADDR(REGS_CODEC_AHB_BASE, 0x000C)/*CODA7_STAT*/ + + + +/* bits definitions for register REG_CODEC_AHB_RF_AHB_RST */ +#define BIT_CODA7_APB_SOFT_RST ( BIT(2) ) +#define BIT_CODA7_CC_SOFT_RST ( BIT(1) ) +#define BIT_CODA7_AXI_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_CODEC_AHB_RF_CKG_ENABLE */ +#define BIT_CODA7_CKG_EN ( BIT(4) ) +#define BIT_CODA7_CC_CKG_EN ( BIT(1) ) +#define BIT_CODA7_AXI_CKG_EN ( BIT(0) ) + +/* bits definitions for register REG_CODEC_AHB_RF_CLOCK_SEL */ +#define BITS_CLK_CODA7_AXI_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_CLK_CODA7_CC_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CLK_CODA7_APB_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CODEC_AHB_RF_CODA7_STAT */ +#define BIT_CODA7_RUN ( BIT(1) ) +#define BIT_CODA7_IDLE ( BIT(0) ) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_cortex_ahb_rf.h b/include/soc/sprd/chip_x35lt8/__regs_cortex_ahb_rf.h new file mode 100644 index 00000000..f36694d6 --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_cortex_ahb_rf.h @@ -0,0 +1,205 @@ +/* the head file modifier: g 2015-03-19 15:42:42*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_CORTEX_AHB_RF_HEADFILE_H__ +#define __H_REGS_CORTEX_AHB_RF_HEADFILE_H__ __FILE__ + +#define REGS_CORTEX_AHB_RF + +/* registers definitions for CORTEX_AHB_RF */ +#define REG_CORTEX_AHB_RF_CLK_CORTEX_AXI_CTRL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0000)/*CLK_CORTEX_AXI_CTRL*/ +#define REG_CORTEX_AHB_RF_CLK_CORTEX_AHB_CTRL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0004)/*CLK_CORTEX_AHB_CTRL*/ +#define REG_CORTEX_AHB_RF_CLK_CORTEX_APB_CTRL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0008)/*CLK_CORTEX_APB_CTRL*/ +#define REG_CORTEX_AHB_RF_CLK_SEC0_CTRL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x000C)/*CLK_SEC0_CTRL*/ +#define REG_CORTEX_AHB_RF_CLK_SEC1_CTRL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0010)/*CLK_SEC1_CTRL*/ +#define REG_CORTEX_AHB_RF_CA5_CFG SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0030)/*CA5_CFG*/ +#define REG_CORTEX_AHB_RF_AHB_CTRL0 SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0034)/*AHB_CTRL0*/ +#define REG_CORTEX_AHB_RF_AHB_CTRL2 SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x003C)/*AHB_CTRL2*/ +#define REG_CORTEX_AHB_RF_AHB_RST0_STS SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0060)/*AHB_RST0_STS*/ +#define REG_CORTEX_AHB_RF_CA5_RST_SET SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0064)/*CA5_RST_SET*/ +#define REG_CORTEX_AHB_RF_ARCH_EB SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0068)/*ARCH_EB*/ +#define REG_CORTEX_AHB_RF_PTEST_FUNC SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x006C)/*REMAP*/ +#define REG_CORTEX_AHB_RF_AHB_MISC_CTL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0070)/*AHB_MISC_CTL*/ +#define REG_CORTEX_AHB_RF_CA5_CTRL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0074)/*CA5_CTRL*/ +#define REG_CORTEX_AHB_RF_AUTO_GATE_CTRL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0078)/*AUTO_GATE_CTRL*/ +#define REG_CORTEX_AHB_RF_AHB_PAUSE SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0080)/*AHB_PAUSE*/ +#define REG_CORTEX_AHB_RF_AHB_SLP_CTL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0084)/*AHB_SLP_CTL*/ +#define REG_CORTEX_AHB_RF_AHB_SLP_STS SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0088)/*AHB_SLP_STS*/ +#define REG_CORTEX_AHB_RF_MCU_CLK_CTL SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x008C)/*MCU_CLK_CTL*/ +#define REG_CORTEX_AHB_RF_RES_REG0 SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x00F4)/*RES_REG0*/ +#define REG_CORTEX_AHB_RF_CHIP_ID SCI_ADDR(REGS_CORTEX_AHB_RF_BASE, 0x0200)/*CHIP_ID*/ + + + +/* bits definitions for register REG_CORTEX_AHB_RF_CLK_CORTEX_AXI_CTRL */ +#define BITS_CLK_CORTEX_AXI_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_CLK_CORTEX_AHB_CTRL */ +#define BITS_CLK_CORTEX_AHB_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_CLK_CORTEX_APB_CTRL */ +#define BITS_CLK_CORTEX_APB_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_CLK_SEC0_CTRL */ +#define BITS_CLK_SEC0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_CLK_SEC1_CTRL */ +#define BITS_CLK_SEC1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_CA5_CFG */ +#define BITS_CA5_DBG_DIV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_CA5_AXI_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CA5_MCU_DIV(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BITS_CA5_MCU_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_AHB_CTRL0 */ +#define BITS_TFT_MST_HPROT(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_PPP1_MST_HPROT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_PPP0_MST_HPROT(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_TFT_EB ( BIT(18) ) +#define BIT_PPP1_EB ( BIT(17) ) +#define BIT_PPP0_EB ( BIT(16) ) +#define BITS_SEC1_MST_HPROT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_SEC0_MST_HPROT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BIT_SEC1_EB ( BIT(5) ) +#define BIT_SEC1_CKG_EN ( BIT(4) ) +#define BIT_SEC0_EB ( BIT(3) ) +#define BIT_SEC0_CKG_EN ( BIT(2) ) +#define BIT_DMA_EB ( BIT(1) ) +#define BIT_DMA_CKG_EN ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_AHB_CTRL2 */ +#define BITS_BUSMON1_CHN_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_AXIBUSMON_CHN_SEL(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_BUSMON0_CHN_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BIT_BUSMON1_EB ( BIT(3) ) +#define BIT_SPINLOCK_EB ( BIT(2) ) +#define BIT_AXIBUSMON_EB ( BIT(1) ) +#define BIT_BUSMON0_EB ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_AHB_RST0_STS */ +#define BIT_TFT_SOFT_RST ( BIT(11) ) +#define BIT_PPP1_SOFT_RST ( BIT(10) ) +#define BIT_PPP0_SOFT_RST ( BIT(9) ) +#define BIT_SEC1_CMD_PARSER_RST ( BIT(8) ) +#define BIT_SEC0_CMD_PARSER_RST ( BIT(7) ) +#define BIT_SPINLOCK_SOFT_RST ( BIT(6) ) +#define BIT_SEC1_SOFT_RST ( BIT(5) ) +#define BIT_SEC0_SOFT_RST ( BIT(4) ) +#define BIT_BUSMON1_SOFT_RST ( BIT(3) ) +#define BIT_AXIBUSMON_SOFT_RST ( BIT(2) ) +#define BIT_BUSMON0_SOFT_RST ( BIT(1) ) +#define BIT_DMA_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_CA5_RST_SET */ +#define BIT_CA5_MTX_SOFT_RST ( BIT(3) ) +#define BIT_CA5_L2_SOFT_RST ( BIT(2) ) +#define BIT_CA5_DBG_SOFT_RST ( BIT(1) ) +#define BIT_CA5_CORE_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_ARCH_EB */ +#define BIT_AHB_ARCH_EB ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_PTEST_FUNC */ +#define BIT_PTEST_FUNC_ATSPEED_SEL ( BIT(2) ) +#define BIT_PTEST_FUNC_MODE ( BIT(1) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_AHB_MISC_CTL */ +#define BITS_DMA_W_PROT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMA_R_PROT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BIT_LCP2PUB_ACCESS_EN ( BIT(4) ) +#define BITS_MCU_SHM_CTRL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_CA5_CTRL */ +#define BIT_CA5_WDRESET_EN ( BIT(18) ) +#define BIT_CA5_TS_EN ( BIT(17) ) +#define BIT_CA5_CFGSDISABLE ( BIT(13) ) +#define BITS_CA5_CLK_AXI_DIV(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)) ) +#define BIT_CA5_CLK_DBG_EN_SEL ( BIT(10) ) +#define BIT_CA5_CLK_DBG_EN ( BIT(9) ) +#define BIT_CA5_DBGEN ( BIT(8) ) +#define BIT_CA5_NIDEN ( BIT(7) ) +#define BIT_CA5_SPIDEN ( BIT(6) ) +#define BIT_CA5_SPNIDEN ( BIT(5) ) +#define BIT_CA5_CP15DISABLE ( BIT(4) ) +#define BIT_CA5_TEINIT ( BIT(3) ) +#define BIT_CA5_L1RSTDISABLE ( BIT(2) ) +#define BIT_CA5_L2CFGEND ( BIT(1) ) +#define BIT_CA5_L2SPNIDEN ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_AUTO_GATE_CTRL */ +#define BIT_CORTEX_AHB_AUTO_GATE_EN ( BIT(5) ) +#define BIT_CA5_DBG_FORCE_SLEEP ( BIT(4) ) +#define BIT_CA5_DBG_AUTO_GATE_EN ( BIT(3) ) +#define BIT_CA5_CORE_AUTO_GATE_EN ( BIT(2) ) +#define BIT_LCPX_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_AHB_PAUSE */ +#define BIT_EMC_LIGHT_SLEEP_EN ( BIT(25) ) +#define BIT_EMC_DEEP_SLEEP_EN ( BIT(24) ) +#define BIT_APB_SLEEP_EN ( BIT(18) ) +#define BIT_APB_PERI_FRC_SLP ( BIT(17) ) +#define BIT_APB_PERI_FRC_ON ( BIT(16) ) +#define BIT_MCU_FORCE_DEEP_SLEEP ( BIT(15) ) +#define BIT_DMA_LSLP_EN ( BIT(4) ) +#define BIT_MCU_LIGHT_SLEEP_EN ( BIT(3) ) +#define BIT_MCU_DEEP_SLEEP_EN ( BIT(2) ) +#define BIT_MCU_SYS_SLEEP_EN ( BIT(1) ) +#define BIT_MCU_CORE_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_AHB_SLP_CTL */ +#define BIT_ARM_DAHB_SLEEP_EN ( BIT(4) ) +#define BIT_MCUMTX_AUTO_GATE_EN ( BIT(3) ) +#define BIT_MCU_AUTO_GATE_EN ( BIT(2) ) +#define BIT_AHB_AUTO_GATE_EN ( BIT(1) ) +#define BIT_ARM_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_AHB_SLP_STS */ +#define BIT_CHIP_SLP_ARM_CLR ( BIT(5) ) +#define BIT_CHIP_SLEEP_REC_ARM ( BIT(4) ) +#define BIT_APB_PERI_SLEEP ( BIT(3) ) +#define BIT_DMA_BUSY ( BIT(1) ) +#define BIT_EMC_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_MCU_CLK_CTL */ +#define BIT_CLK_LCP2LDSP_BRG_EN ( BIT(24) ) +#define BIT_CLK_LCP2PUB_BRG_EN ( BIT(23) ) +#define BIT_CLK_LCP2CP0_BRG_EN ( BIT(22) ) +#define BIT_CLK_CP_DBG_SEL ( BIT(21) ) +#define BIT_CLK_MCU_DBG_SEL ( BIT(20) ) +#define BITS_CLK_COM_DBG_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_CLK_SYS_DBG_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_CLK_AHB_DIV(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_CLK_MCU_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_APB_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CLK_MCU_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_AHB_RF_RES_REG0 */ +#define BITS_RES_REG0(_X_) (_X_) + +/* bits definitions for register REG_CORTEX_AHB_RF_CHIP_ID */ +#define BITS_CHIP_ID(_X_) (_X_) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_cortex_glb.h b/include/soc/sprd/chip_x35lt8/__regs_cortex_glb.h new file mode 100644 index 00000000..b452c971 --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_cortex_glb.h @@ -0,0 +1,155 @@ +/* the head file modifier: g 2015-03-19 15:43:07*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_CORTEX_GLB_HEADFILE_H__ +#define __H_REGS_CORTEX_GLB_HEADFILE_H__ __FILE__ + +#define REGS_CORTEX_GLB + +/* registers definitions for CORTEX_GLB */ +#define REG_CORTEX_GLB_APB_EB0_STS SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0008)/*APB_EB0_STS*/ +#define REG_CORTEX_GLB_APB_RST0_STS SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0014)/*APB_RST0_STS*/ +#define REG_CORTEX_GLB_APB_MCU_RST SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0018)/*APB_MCU_RST*/ +#define REG_CORTEX_GLB_APB_CLK_SEL0 SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x001C)/*APB_CLK_SEL0*/ +#define REG_CORTEX_GLB_APB_CLK_SEL1 SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0020)/*APB_CLK_SEL1*/ +#define REG_CORTEX_GLB_APB_ARCH_EB SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0024)/*APB_ARCH_EB*/ +#define REG_CORTEX_GLB_APB_MISC_CTL0 SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0028)/*APB_MISC_CTL0*/ +#define REG_CORTEX_GLB_APB_MISC_CTL1 SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x002C)/*APB_MISC_CTL1*/ +#define REG_CORTEX_GLB_APB_CLK_SEL2 SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0030)/*APB_CLK_SEL2*/ +#define REG_CORTEX_GLB_APB_BUS_CTL0 SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0058)/*APB_BUS_CTL0*/ +#define REG_CORTEX_GLB_APB_DSP_INT_CLR SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0074)/*APB_DSP_INT_CLR*/ +#define REG_CORTEX_GLB_APB_MISC_INT_STS SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0078)/*APB_MISC_INT_STS*/ +#define REG_CORTEX_GLB_APB_HWRST SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0080)/*APB_HWRST*/ +#define REG_CORTEX_GLB_APB_ARM_BOOT_ADDR SCI_ADDR(REGS_CORTEX_GLB_BASE, 0x0084)/*APB_ARM_BOOT_ADDR*/ + + + +/* bits definitions for register REG_CORTEX_GLB_APB_EB0_STS */ +#define BIT_EIC_RTC_EB ( BIT(19) ) +#define BIT_EIC_EB ( BIT(18) ) +#define BIT_RFFE_EB ( BIT(17) ) +#define BIT_EPT_EB ( BIT(16) ) +#define BIT_GPIO_EB ( BIT(15) ) +#define BIT_TMR_RTC_EB ( BIT(14) ) +#define BIT_TMR_EB ( BIT(13) ) +#define BIT_SYSTMR_RTC_EB ( BIT(12) ) +#define BIT_SYSTMR_EB ( BIT(11) ) +#define BIT_IIS3_EB ( BIT(10) ) +#define BIT_IIS2_EB ( BIT(9) ) +#define BIT_IIS1_EB ( BIT(8) ) +#define BIT_IIS0_EB ( BIT(7) ) +#define BIT_SIM2_EB ( BIT(6) ) +#define BIT_SIM1_EB ( BIT(5) ) +#define BIT_SIM0_EB ( BIT(4) ) +#define BIT_UART1_EB ( BIT(3) ) +#define BIT_UART0_EB ( BIT(2) ) +#define BIT_WDG_RTC_EB ( BIT(1) ) +#define BIT_WDG_EB ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_RST0_STS */ +#define BIT_EIC_SOFT_RST ( BIT(16) ) +#define BIT_RFFE_SOFT_RST ( BIT(15) ) +#define BIT_MCU_DSP_RST ( BIT(14) ) +#define BIT_EPT_SOFT_RST ( BIT(13) ) +#define BIT_GPIO_SOFT_RST ( BIT(12) ) +#define BIT_TMR_SOFT_RST ( BIT(11) ) +#define BIT_SYSTMR_SOFT_RST ( BIT(10) ) +#define BIT_IIS3_SOFT_RST ( BIT(9) ) +#define BIT_IIS2_SOFT_RST ( BIT(8) ) +#define BIT_IIS1_SOFT_RST ( BIT(7) ) +#define BIT_IIS0_SOFT_RST ( BIT(6) ) +#define BIT_SIM2_SOFT_RST ( BIT(5) ) +#define BIT_SIM1_SOFT_RST ( BIT(4) ) +#define BIT_SIM0_SOFT_RST ( BIT(3) ) +#define BIT_UART1_SOFT_RST ( BIT(2) ) +#define BIT_UART0_SOFT_RST ( BIT(1) ) +#define BIT_WDG_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_MCU_RST */ +#define BIT_MCU_SOFT_RST_SET ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_CLK_SEL0 */ +#define BITS_CLK_UART1_DIV(_X_) ( (_X_) << 7 & (BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_CLK_UART1_SEL(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)) ) +#define BITS_CLK_UART0_DIV(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)) ) +#define BITS_CLK_UART0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_CLK_SEL1 */ +#define BIT_CLK_IIS1_PAD_SEL ( BIT(24) ) +#define BITS_CLK_IIS1_DIV(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_CLK_IIS1_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BIT_CLK_IIS0_PAD_SEL ( BIT(8) ) +#define BITS_CLK_IIS0_DIV(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_CLK_IIS0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_ARCH_EB */ +#define BIT_RTC_ARCH_EB ( BIT(1) ) +#define BIT_APB_ARCH_EB ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_MISC_CTL0 */ +#define BIT_ALL_CLK_EN ( BIT(28) ) +#define BIT_DMA_LSLP_EN ( BIT(27) ) +#define BIT_WAKEUP_XTL_EN_3G ( BIT(26) ) +#define BIT_WAKEUP_XTL_EN_2G ( BIT(25) ) +#define BIT_ARM_JTAG_EN ( BIT(24) ) +#define BITS_ARM_FRC_STOP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_MISC_CTL1 */ +#define BITS_BUFON_CTRL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_SIM2_CLK_POLARITY ( BIT(3) ) +#define BIT_SIM1_CLK_POLARITY ( BIT(2) ) +#define BIT_SIM0_CLK_POLARITY ( BIT(1) ) +#define BIT_ROM_CLK_EN ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_CLK_SEL2 */ +#define BIT_CLK_IIS3_PAD_SEL ( BIT(24) ) +#define BITS_CLK_IIS3_DIV(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_CLK_IIS3_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BIT_CLK_IIS2_PAD_SEL ( BIT(8) ) +#define BITS_CLK_IIS2_DIV(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_CLK_IIS2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_BUS_CTL0 */ +#define BIT_IIS3_CTRL_SEL ( BIT(7) ) +#define BIT_IIS2_CTRL_SEL ( BIT(6) ) +#define BIT_RFFE_CTRL_SEL ( BIT(5) ) +#define BIT_IIS1_CTRL_SEL ( BIT(3) ) +#define BIT_IIS0_CTRL_SEL ( BIT(2) ) +#define BIT_UART0_CTRL_SEL ( BIT(1) ) +#define BIT_UART1_CTRL_SEL ( BIT(0) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_DSP_INT_CLR */ +#define BIT_RFT_INT_CLR ( BIT(2) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_MISC_INT_STS */ +#define BIT_RFT_INT ( BIT(2) ) + +/* bits definitions for register REG_CORTEX_GLB_APB_HWRST */ +#define BITS_HWRST_REG(_X_) (_X_) + +/* bits definitions for register REG_CORTEX_GLB_APB_ARM_BOOT_ADDR */ +#define BITS_ARMBOOT_ADDR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_cp_ahb_rf.h b/include/soc/sprd/chip_x35lt8/__regs_cp_ahb_rf.h new file mode 100644 index 00000000..a3a6275d --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_cp_ahb_rf.h @@ -0,0 +1,299 @@ +/* the head file modifier: g 2015-03-19 17:10:49*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_CP_AHB_RF_HEADFILE_H__ +#define __H_REGS_CP_AHB_RF_HEADFILE_H__ __FILE__ + +#define REGS_CP_AHB_RF + +/* registers definitions for CP_AHB_RF */ +#define REG_CP_AHB_RF_AHB_EB0_STS SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0008)/*AHB_EB0_STS*/ +#define REG_CP_AHB_RF_AHB_RST0_STS SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0014)/*AHB_RST0_STS*/ +#define REG_CP_AHB_RF_ARCH_EB SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0018)/*ARCH_EB*/ +#define REG_CP_AHB_RF_AHB_REMAP SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x001C)/*AHB_REMAP*/ +#define REG_CP_AHB_RF_AHB_MISC_CTL SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0020)/*AHB_MISC_CTL*/ +#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL0 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0024)/*AHB_MTX_PRI_SEL0*/ +#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL1 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0028)/*AHB_MTX_PRI_SEL1*/ +#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL2 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x002C)/*AHB_MTX_PRI_SEL2*/ +#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL3 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0030)/*AHB_MTX_PRI_SEL3*/ +#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL4 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0034)/*AHB_MTX_PRI_SEL4*/ +#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL5 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0038)/*AHB_MTX_PRI_SEL5*/ +#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL6 SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x003C)/*AHB_MTX_PRI_SEL6*/ +#define REG_CP_AHB_RF_AHB_PAUSE SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0040)/*AHB_PAUSE*/ +#define REG_CP_AHB_RF_AHB_SLP_CTL SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0044)/*AHB_SLP_CTL*/ +#define REG_CP_AHB_RF_AHB_SLP_STS SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0048)/*AHB_SLP_STS*/ +#define REG_CP_AHB_RF_MCU_CLK_CTL SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x004C)/*MCU_CLK_CTL*/ +#define REG_CP_AHB_RF_DSP_CTL SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0050)/*DSP_CTL*/ +#define REG_CP_AHB_RF_DSP_BOOT_VECTOR SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0054)/*DSP_BOOT_VECTOR*/ +#define REG_CP_AHB_RF_DSP_RST SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0058)/*DSP_RST*/ +#define REG_CP_AHB_RF_DSP_JTAG_CTL SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x005C)/*DSP_JTAG_CTL*/ +#define REG_CP_AHB_RF_MCU_C2C_SEMA SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0060)/*MCU_C2C_SEMA*/ +#define REG_CP_AHB_RF_GGE_DSP_BOOT_VECTOR SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0064)/*GGE_DSP_BOOT_VECTOR*/ +#define REG_CP_AHB_RF_CHIP_ID SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x01FC)/*CHIP_ID*/ + + + +/* bits definitions for register REG_CP_AHB_RF_AHB_EB0_STS */ +#define BIT_LZMA_EN ( BIT(11) ) +#define BIT_WCDMA_EN5 ( BIT(9) ) +#define BIT_WCDMA_EN4 ( BIT(8) ) +#define BIT_WCDMA_EN3 ( BIT(7) ) +#define BIT_WCDMA_EN2 ( BIT(6) ) +#define BIT_WCDMA_EN1 ( BIT(5) ) +#define BIT_WCDMA_EN0 ( BIT(4) ) +#define BIT_BUSMON2_EN ( BIT(3) ) +#define BIT_BUSMON1_EN ( BIT(2) ) +#define BIT_BUSMON0_EN ( BIT(1) ) +#define BIT_DMA_EN ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_RST0_STS */ +#define BIT_LZMA_SOFT_RST ( BIT(8) ) +#define BIT_WSYS_SOFT_RST ( BIT(6) ) +#define BIT_ARM1_SOFT_RST ( BIT(4) ) +#define BIT_BUSMON2_SOFT_RST ( BIT(3) ) +#define BIT_BUSMON1_SOFT_RST ( BIT(2) ) +#define BIT_BUSMON0_SOFT_RST ( BIT(1) ) +#define BIT_DMA_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_ARCH_EB */ +#define BIT_AHB_ARCH_EB ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_REMAP */ +#define BIT_PTEST_FUNC_ATSPEED_SEL ( BIT(2) ) +#define BIT_PTEST_FUNC_MODE ( BIT(1) ) +#define BIT_REMAP ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_MISC_CTL */ +#define BITS_MCU_GGE_SHM_CTRL(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)) ) +#define BITS_LZMA_M_PROT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMA_W_PROT(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMA_R_PROT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_MCU_SHM_CTRL(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BIT_RF_SWT_AUTO_EN ( BIT(1) ) +#define BIT_WCDMA_ASHB_EN ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL0 */ +#define BITS_ARMMTX_M3TOS0_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ARMMTX_M3TOS0_ADJ_EN ( BIT(27) ) +#define BIT_ARMMTX_M3TOS0_RND_EN ( BIT(26) ) +#define BITS_ARMMTX_M3TOS0_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_ARMMTX_M2TOS0_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M2TOS0_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M2TOS0_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M2TOS0_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M1TOS0_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M1TOS0_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M1TOS0_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M1TOS0_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M0TOS0_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M0TOS0_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M0TOS0_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M0TOS0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL1 */ +#define BITS_ARMMTX_M3TOS1_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ARMMTX_M3TOS1_ADJ_EN ( BIT(27) ) +#define BIT_ARMMTX_M3TOS1_RND_EN ( BIT(26) ) +#define BITS_ARMMTX_M3TOS1_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_ARMMTX_M2TOS1_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M2TOS1_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M2TOS1_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M2TOS1_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M1TOS1_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M1TOS1_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M1TOS1_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M1TOS1_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M0TOS1_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M0TOS1_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M0TOS1_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M0TOS1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL2 */ +#define BITS_ARMMTX_M1TOS2_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ARMMTX_M1TOS2_ADJ_EN ( BIT(27) ) +#define BIT_ARMMTX_M1TOS2_RND_EN ( BIT(26) ) +#define BITS_ARMMTX_M1TOS2_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_ARMMTX_M0TOS2_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M0TOS2_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M0TOS2_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M0TOS2_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M5TOS1_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M5TOS1_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M5TOS1_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M5TOS1_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M4TOS1_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M4TOS1_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M4TOS1_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M4TOS1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL3 */ +#define BITS_ARMMTX_M5TOS2_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ARMMTX_M5TOS2_ADJ_EN ( BIT(27) ) +#define BIT_ARMMTX_M5TOS2_RND_EN ( BIT(26) ) +#define BITS_ARMMTX_M5TOS2_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_ARMMTX_M5TOS4_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M5TOS4_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M5TOS4_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M5TOS4_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M3TOS2_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M3TOS2_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M3TOS2_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M3TOS2_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M2TOS2_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M2TOS2_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M2TOS2_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M2TOS2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL4 */ +#define BITS_ARMMTX_M4TOS3_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M4TOS3_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M4TOS3_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M4TOS3_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M1TOS3_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M1TOS3_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M1TOS3_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M1TOS3_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M0TOS3_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M0TOS3_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M0TOS3_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M0TOS3_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL5 */ +#define BITS_ARMMTX_M4TOS0_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ARMMTX_M4TOS0_ADJ_EN ( BIT(27) ) +#define BIT_ARMMTX_M4TOS0_RND_EN ( BIT(26) ) +#define BITS_ARMMTX_M4TOS0_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_ARMMTX_M4TOS4_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M4TOS4_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M4TOS4_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M4TOS4_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M1TOS4_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M1TOS4_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M1TOS4_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M1TOS4_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M0TOS4_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M0TOS4_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M0TOS4_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M0TOS4_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL6 */ +#define BITS_ARMMTX_M3TOS5_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ARMMTX_M3TOS5_ADJ_EN ( BIT(27) ) +#define BIT_ARMMTX_M3TOS5_RND_EN ( BIT(26) ) +#define BITS_ARMMTX_M3TOS5_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_ARMMTX_M2TOS5_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M2TOS5_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M2TOS5_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M2TOS5_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M1TOS5_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M1TOS5_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M1TOS5_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M1TOS5_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M0TOS5_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M0TOS5_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M0TOS5_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M0TOS5_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_PAUSE */ +#define BIT_MCU_GGE_DEEP_SLEEP_EN ( BIT(5) ) +#define BIT_MCU_LIGHT_SLEEP_EN ( BIT(4) ) +#define BIT_APB_SLEEP ( BIT(3) ) +#define BIT_MCU_DEEP_SLEEP_EN ( BIT(2) ) +#define BIT_MCU_SYS_SLEEP_EN ( BIT(1) ) +#define BIT_MCU_CORE_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_SLP_CTL */ +#define BIT_AHB_VCP1_DEEP_SLEEP_EN ( BIT(6) ) +#define BIT_GGE_ARM_DAHB_SLEEP_EN ( BIT(5) ) +#define BIT_ARM_DAHB_SLEEP_EN ( BIT(4) ) +#define BIT_MCUMTX_AUTO_GATE_EN ( BIT(3) ) +#define BIT_MCU_AUTO_GATE_EN ( BIT(2) ) +#define BIT_AHB_AUTO_GATE_EN ( BIT(1) ) +#define BIT_ARM_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_AHB_SLP_STS */ +#define BIT_GGE_DSP_MAHB_SLEEP_EN ( BIT(4) ) +#define BIT_APB_PERI_SLEEP ( BIT(3) ) +#define BIT_DSP_MAHB_SLEEP_EN ( BIT(2) ) +#define BIT_DMA_BUSY ( BIT(1) ) +#define BIT_EMC_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_MCU_CLK_CTL */ +#define BIT_CLK_CP_DBG_GGE_SEL ( BIT(28) ) +#define BIT_CLK_GGE_DBG_SEL ( BIT(27) ) +#define BITS_CLK_COM_GGE_DBG_SEL(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BIT_CLK_SYS_GGE_DBG_SEL ( BIT(24) ) +#define BITS_CLK_LZMA_SEL(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)) ) +#define BIT_CLK_CP_DBG_SEL ( BIT(21) ) +#define BIT_CLK_MCU_DBG_SEL ( BIT(20) ) +#define BITS_CLK_COM_DBG_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_CLK_SYS_DBG_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_CLK_AHB_DIV(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_CLK_MCU_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_APB_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CLK_MCU_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_CP_AHB_RF_DSP_CTL */ +#define BIT_GGE_ASHB_ARMTODSP_EN ( BIT(5) ) +#define BIT_GGE_FRC_CLK_DSP_EN ( BIT(4) ) +#define BIT_GGE_DSP_BOOT_EN ( BIT(3) ) +#define BIT_ASHB_ARMTODSP_EN ( BIT(2) ) +#define BIT_FRC_CLK_DSP_EN ( BIT(1) ) +#define BIT_DSP_BOOT_EN ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_DSP_BOOT_VECTOR */ +#define BITS_DSP_BOOT_VECTOR(_X_) (_X_) + +/* bits definitions for register REG_CP_AHB_RF_DSP_RST */ +#define BIT_GGE_DSP_SYS_SRST ( BIT(3) ) +#define BIT_GGE_DSP_CORE_SRST_N ( BIT(2) ) +#define BIT_DSP_SYS_SRST ( BIT(1) ) +#define BIT_DSP_CORE_SRST_N ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_DSP_JTAG_CTL */ +#define BIT_GGE_CEVA_SW_JTAG_ENA ( BIT(24) ) +#define BIT_GGE_STDO ( BIT(20) ) +#define BIT_GGE_STCK ( BIT(19) ) +#define BIT_GGE_STMS ( BIT(18) ) +#define BIT_GGE_STDI ( BIT(17) ) +#define BIT_GGE_STRTCK ( BIT(16) ) +#define BIT_CEVA_SW_JTAG_ENA ( BIT(8) ) +#define BIT_STDO ( BIT(4) ) +#define BIT_STCK ( BIT(3) ) +#define BIT_STMS ( BIT(2) ) +#define BIT_STDI ( BIT(1) ) +#define BIT_STRTCK ( BIT(0) ) + +/* bits definitions for register REG_CP_AHB_RF_MCU_C2C_SEMA */ +#define BITS_GGE_MCU_C2C_SEMA(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_MCU_C2C_SEMA(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_CP_AHB_RF_GGE_DSP_BOOT_VECTOR */ +#define BITS_GGE_DSP_BOOT_VECTOR(_X_) (_X_) + +/* bits definitions for register REG_CP_AHB_RF_CHIP_ID */ +#define BITS_CHIP_ID(_X_) (_X_) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_cp_apb_rf.h b/include/soc/sprd/chip_x35lt8/__regs_cp_apb_rf.h new file mode 100644 index 00000000..dc847447 --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_cp_apb_rf.h @@ -0,0 +1,247 @@ +/* the head file modifier: g 2015-03-19 15:46:02*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_CP_APB_RF_HEADFILE_H__ +#define __H_REGS_CP_APB_RF_HEADFILE_H__ __FILE__ + +#define REGS_CP_APB_RF + +/* registers definitions for CP_APB_RF */ +#define REG_CP_APB_RF_APB_EB0_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0008)/*APB_EB0_STS*/ +#define REG_CP_APB_RF_APB_RST0_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0014)/*APB_RST0_STS*/ +#define REG_CP_APB_RF_APB_MCU_RST SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0018)/*APB_MCU_RST*/ +#define REG_CP_APB_RF_APB_CLK_SEL0 SCI_ADDR(REGS_CP_APB_RF_BASE, 0x001C)/*APB_CLK_SEL0*/ +#define REG_CP_APB_RF_APB_CLK_DIV0 SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0020)/*APB_CLK_DIV0*/ +#define REG_CP_APB_RF_APB_ARCH_EB SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0024)/*APB_ARCH_EB*/ +#define REG_CP_APB_RF_APB_MISC_CTL0 SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0028)/*APB_MISC_CTL0*/ +#define REG_CP_APB_RF_APB_MISC_CTL1 SCI_ADDR(REGS_CP_APB_RF_BASE, 0x002C)/*APB_MISC_CTL1*/ +#define REG_CP_APB_RF_APB_PIN_SEL SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0040)/*APB_PIN_SEL*/ +#define REG_CP_APB_RF_APB_SLP_CTL SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0044)/*APB_SLP_CTL*/ +#define REG_CP_APB_RF_APB_WSYS_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0048)/*APB_WSYS_STS*/ +#define REG_CP_APB_RF_APB_SLP_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0050)/*APB_SLP_STS*/ +#define REG_CP_APB_RF_APB_ROM_PD_CTL SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0054)/*APB_ROM_PD_CTL*/ +#define REG_CP_APB_RF_APB_BUS_CTL0 SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0058)/*APB_BUS_CTL0*/ +#define REG_CP_APB_RF_APB_DSP_INT_CLR SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0074)/*APB_DSP_INT_CLR*/ +#define REG_CP_APB_RF_APB_MISC_INT_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0078)/*APB_MISC_INT_STS*/ +#define REG_CP_APB_RF_APB_HWRST SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0080)/*APB_HWRST*/ +#define REG_CP_APB_RF_APB_ARM_BOOT_ADDR SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0084)/*APB_ARM_BOOT_ADDR*/ +#define REG_CP_APB_RF_APB_GGE_SLP_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0088)/*APB_GGE_SLP_STS*/ + + + +/* bits definitions for register REG_CP_APB_RF_APB_EB0_STS */ +#define BIT_UART2_EB ( BIT(20) ) +#define BIT_EIC_RTC_EB ( BIT(19) ) +#define BIT_EIC_EB ( BIT(18) ) +#define BIT_RFFE_EB ( BIT(17) ) +#define BIT_EPT_EB ( BIT(16) ) +#define BIT_GPIO_EB ( BIT(15) ) +#define BIT_TMR_RTC_EB ( BIT(14) ) +#define BIT_TMR_EB ( BIT(13) ) +#define BIT_SYSTMR_RTC_EB ( BIT(12) ) +#define BIT_SYSTMR_EB ( BIT(11) ) +#define BIT_IIS3_EB ( BIT(10) ) +#define BIT_IIS2_EB ( BIT(9) ) +#define BIT_IIS1_EB ( BIT(8) ) +#define BIT_IIS0_EB ( BIT(7) ) +#define BIT_SIM2_EB ( BIT(6) ) +#define BIT_SIM1_EB ( BIT(5) ) +#define BIT_SIM0_EB ( BIT(4) ) +#define BIT_UART1_EB ( BIT(3) ) +#define BIT_UART0_EB ( BIT(2) ) +#define BIT_WDG_RTC_EB ( BIT(1) ) +#define BIT_WDG_EB ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_RST0_STS */ +#define BIT_UART2_SOFT_RST ( BIT(20) ) +#define BIT_GGE_MCU_DSP_RST ( BIT(19) ) +#define BIT_EIC_SOFT_RST ( BIT(16) ) +#define BIT_RFFE_SOFT_RST ( BIT(15) ) +#define BIT_MCU_DSP_RST ( BIT(14) ) +#define BIT_EPT_SOFT_RST ( BIT(13) ) +#define BIT_GPIO_SOFT_RST ( BIT(12) ) +#define BIT_TMR_SOFT_RST ( BIT(11) ) +#define BIT_SYSTMR_SOFT_RST ( BIT(10) ) +#define BIT_IIS3_SOFT_RST ( BIT(9) ) +#define BIT_IIS2_SOFT_RST ( BIT(8) ) +#define BIT_IIS1_SOFT_RST ( BIT(7) ) +#define BIT_IIS0_SOFT_RST ( BIT(6) ) +#define BIT_SIM2_SOFT_RST ( BIT(5) ) +#define BIT_SIM1_SOFT_RST ( BIT(4) ) +#define BIT_SIM0_SOFT_RST ( BIT(3) ) +#define BIT_UART1_SOFT_RST ( BIT(2) ) +#define BIT_UART0_SOFT_RST ( BIT(1) ) +#define BIT_WDG_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_MCU_RST */ +#define BIT_MCU_SOFT_RST_SET ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_CLK_SEL0 */ +#define BIT_CLK_IIS3_PAD_SEL ( BIT(19) ) +#define BIT_CLK_IIS2_PAD_SEL ( BIT(18) ) +#define BIT_CLK_IIS1_PAD_SEL ( BIT(17) ) +#define BIT_CLK_IIS0_PAD_SEL ( BIT(16) ) +#define BITS_CLK_UART2_SEL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_CLK_IIS3_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_CLK_IIS2_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_CLK_IIS1_SEL(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_CLK_IIS0_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CLK_UART1_SEL(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_CLK_UART0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_CP_APB_RF_APB_CLK_DIV0 */ +#define BITS_CLK_IIS2_DIV(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_CLK_IIS1_DIV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)) ) +#define BITS_CLK_IIS0_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_CLK_UART1_DIV(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BITS_CLK_UART0_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_CP_APB_RF_APB_ARCH_EB */ +#define BITS_CLK_UART2_DIV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)) ) +#define BITS_CLK_IIS3_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_RTC_ARCH_EB ( BIT(1) ) +#define BIT_APB_ARCH_EB ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_MISC_CTL0 */ +#define BIT_GGE_ALL_CLK_EN ( BIT(29) ) +#define BIT_ALL_CLK_EN ( BIT(28) ) +#define BIT_DMA_LSLP_EN ( BIT(27) ) +#define BIT_WAKEUP_XTL_EN_3G_W ( BIT(26) ) +#define BIT_WAKEUP_XTL_EN_2G ( BIT(25) ) +#define BIT_ARM_JTAG_EN ( BIT(24) ) +#define BIT_WAKEUP_XTL_EN_3G_TD ( BIT(23) ) +#define BIT_GGE_WAKEUP_XTL_EN_2G ( BIT(22) ) +#define BITS_ARM_FRC_STOP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) ) + +/* bits definitions for register REG_CP_APB_RF_APB_MISC_CTL1 */ +#define BITS_BUFON_CTRL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_SIM2_CLK_POLARITY ( BIT(3) ) +#define BIT_SIM1_CLK_POLARITY ( BIT(2) ) +#define BIT_SIM0_CLK_POLARITY ( BIT(1) ) +#define BIT_ROM_CLK_EN ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_PIN_SEL */ +#define BIT_DJTAG_PIN_IN_SEL ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_SLP_CTL */ +#define BITS_GGE_DEEP_SLP_DBG(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_APB_PERI_FRC_ON ( BIT(20) ) +#define BIT_APB_PERI_FRC_SLP ( BIT(16) ) +#define BIT_MCU_XTLEN_AUTOPD_EN ( BIT(12) ) +#define BIT_MCU_FORCE_GGE_LIGHT_SLEEP ( BIT(9) ) +#define BIT_MCU_FORCE_LIGHT_SLEEP ( BIT(8) ) +#define BIT_CHIP_SLP_ARM_CLR ( BIT(4) ) +#define BIT_MCU_FORCE_GGE_DEEP_SLEEP ( BIT(3) ) +#define BIT_MCU_FORCE_WSYS_LT_STOP ( BIT(2) ) +#define BIT_MCU_FORCE_WSYS_STOP ( BIT(1) ) +#define BIT_MCU_FORCE_DEEP_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_WSYS_STS */ +#define BITS_DEEP_SLP_DBG(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_WSYS_STATUS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_CP_APB_RF_APB_SLP_STS */ +#define BIT_DSP_MAHB_SLEEP_EN ( BIT(28) ) +#define BIT_MCU_PERI_STOP ( BIT(27) ) +#define BIT_DSP_PERI_STOP ( BIT(26) ) +#define BIT_ECC_CKG_EN ( BIT(25) ) +#define BIT_QBC_CKG_EN ( BIT(24) ) +#define BIT_DSP_TWPLL_EN ( BIT(21) ) +#define BIT_STC_TMR_AUTOPD_XTL_EN ( BIT(20) ) +#define BIT_RFT_TMR_AUTOPD_XTL_EN ( BIT(19) ) +#define BIT_STC_TMR_AUTOPD_RF_EN ( BIT(18) ) +#define BIT_RFT_TMR_AUTOPD_RF_EN ( BIT(17) ) +#define BIT_CHIP_SLEEP_REC_ARM ( BIT(16) ) +#define BIT_DSP_CORE_STOP ( BIT(15) ) +#define BIT_DSP_MTX_STOP ( BIT(14) ) +#define BIT_DSP_AHB_STOP ( BIT(13) ) +#define BIT_DSP_SYS_STOP ( BIT(12) ) +#define BIT_DSP_DEEP_STOP ( BIT(11) ) +#define BIT_ASHB_DSPTOARM_EN ( BIT(10) ) +#define BIT_ASHB_ARMTODSP_VALID ( BIT(9) ) +#define BIT_EMC_STOP_CH3 ( BIT(8) ) +#define BIT_EMC_STOP_CH4 ( BIT(7) ) +#define BIT_EMC_STOP_CH5 ( BIT(6) ) +#define BIT_FRC_WAKE_EN ( BIT(5) ) +#define BIT_TMR_WAKE_AFC ( BIT(4) ) +#define BIT_SCH_SLEEP ( BIT(3) ) +#define BIT_DSP_STOP ( BIT(2) ) +#define BIT_MCU_STOP ( BIT(1) ) +#define BIT_EMC_STOP ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_ROM_PD_CTL */ +#define BIT_GGE_ROM_FORCE_ON ( BIT(1) ) +#define BIT_ROM_FORCE_ON ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_BUS_CTL0 */ +#define BIT_IIS3_DSP_CTRL_SEL ( BIT(11) ) +#define BIT_IIS2_DSP_CTRL_SEL ( BIT(10) ) +#define BIT_IIS1_DSP_CTRL_SEL ( BIT(9) ) +#define BIT_IIS0_DSP_CTRL_SEL ( BIT(8) ) +#define BIT_UART2_CTRL_SEL ( BIT(7) ) +#define BIT_RFFE_CTRL_SEL ( BIT(5) ) +#define BIT_IIS3_CTRL_SEL ( BIT(4) ) +#define BIT_IIS2_CTRL_SEL ( BIT(3) ) +#define BIT_IIS1_CTRL_SEL ( BIT(2) ) +#define BIT_IIS0_CTRL_SEL ( BIT(1) ) +#define BIT_UART1_CTRL_SEL ( BIT(0) ) + +/* bits definitions for register REG_CP_APB_RF_APB_DSP_INT_CLR */ +#define BIT_RFT_INT_CLR ( BIT(2) ) + +/* bits definitions for register REG_CP_APB_RF_APB_MISC_INT_STS */ +#define BIT_RFT_INT ( BIT(2) ) + +/* bits definitions for register REG_CP_APB_RF_APB_HWRST */ +#define BITS_HWRST_REG(_X_) (_X_) + +/* bits definitions for register REG_CP_APB_RF_APB_ARM_BOOT_ADDR */ +#define BITS_ARMBOOT_ADDR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_CP_APB_RF_APB_GGE_SLP_STS */ +#define BIT_GGE_DSP_MAHB_SLEEP_EN ( BIT(21) ) +#define BIT_GGE_DSP_PERI_STOP ( BIT(20) ) +#define BIT_GGE_QBC_CKG_EN ( BIT(19) ) +#define BIT_GGE_DSP_TWPLL_EN ( BIT(18) ) +#define BIT_GGE_STC_TMR_AUTOPD_XTL_EN ( BIT(17) ) +#define BIT_GGE_STC_TMR_AUTOPD_RF_EN ( BIT(16) ) +#define BIT_GGE_DSP_CORE_STOP ( BIT(15) ) +#define BIT_GGE_DSP_MTX_STOP ( BIT(14) ) +#define BIT_GGE_DSP_AHB_STOP ( BIT(13) ) +#define BIT_GGE_DSP_SYS_STOP ( BIT(12) ) +#define BIT_GGE_DSP_DEEP_STOP ( BIT(11) ) +#define BIT_GGE_ASHB_DSPTOARM_EN ( BIT(10) ) +#define BIT_GGE_ASHB_ARMTODSP_VALID ( BIT(9) ) +#define BIT_GGE_EMC_STOP_CH3 ( BIT(8) ) +#define BIT_GGE_EMC_STOP_CH4 ( BIT(7) ) +#define BIT_GGE_EMC_STOP_CH5 ( BIT(6) ) +#define BIT_GGE_FRC_WAKE_EN ( BIT(5) ) +#define BIT_GGE_TMR_WAKE_AFC ( BIT(4) ) +#define BIT_GGE_SCH_SLEEP ( BIT(3) ) +#define BIT_GGE_DSP_STOP ( BIT(2) ) +#define BIT_GGE_MCU_STOP ( BIT(1) ) +#define BIT_GGE_EMC_STOP ( BIT(0) ) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_djtag_apb_rf.h b/include/soc/sprd/chip_x35lt8/__regs_djtag_apb_rf.h new file mode 100644 index 00000000..862a626f --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_djtag_apb_rf.h @@ -0,0 +1,63 @@ +/* the head file modifier: g 2015-03-19 15:38:39*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_DJTAG_APB_RF_HEADFILE_H__ +#define __H_REGS_DJTAG_APB_RF_HEADFILE_H__ __FILE__ + +#define REGS_DJTAG_APB_RF + +/* registers definitions for DJTAG_APB_RF */ +#define REG_DJTAG_APB_RF_DJTAG_IR_LEN_CFG SCI_ADDR(REGS_DJTAG_APB_RF_BASE, 0x0000)/*DJTAG_IR_LEN_CFG*/ +#define REG_DJTAG_APB_RF_DJTAG_DR_LEN_CFG SCI_ADDR(REGS_DJTAG_APB_RF_BASE, 0x0004)/*DJTAG_DR_LEN_CFG*/ +#define REG_DJTAG_APB_RF_DJTAG_IR_CFG SCI_ADDR(REGS_DJTAG_APB_RF_BASE, 0x0008)/*DJTAG_IR_CFG*/ +#define REG_DJTAG_APB_RF_DJTAG_DR_CFG SCI_ADDR(REGS_DJTAG_APB_RF_BASE, 0x000C)/*DJTAG_DR_CFG*/ +#define REG_DJTAG_APB_RF_DR_PAUSE_RECOV_CFG SCI_ADDR(REGS_DJTAG_APB_RF_BASE, 0x0010)/*DR_PAUSE_RECOV_CFG*/ +#define REG_DJTAG_APB_RF_DJTAG_RND_EN_CFG SCI_ADDR(REGS_DJTAG_APB_RF_BASE, 0x0014)/*DJTAG_RND_EN_CFG*/ +#define REG_DJTAG_APB_RF_DJTAG_UPD_DR_CFG SCI_ADDR(REGS_DJTAG_APB_RF_BASE, 0x0018)/*DJTAG_UPD_DR_CFG*/ + + + +/* bits definitions for register REG_DJTAG_APB_RF_DJTAG_IR_LEN_CFG */ +#define BITS_IR_LEN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_DJTAG_APB_RF_DJTAG_DR_LEN_CFG */ +#define BITS_DR_LEN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_DJTAG_APB_RF_DJTAG_IR_CFG */ +#define BITS_DJTAG_IR(_X_) (_X_) + +/* bits definitions for register REG_DJTAG_APB_RF_DJTAG_DR_CFG */ +#define BITS_DJTAG_DR(_X_) (_X_) + +/* bits definitions for register REG_DJTAG_APB_RF_DR_PAUSE_RECOV_CFG */ +#define BIT_DR_PAUSE_RECOV ( BIT(0) ) + +/* bits definitions for register REG_DJTAG_APB_RF_DJTAG_RND_EN_CFG */ +#define BIT_DJTAG_RND_EN ( BIT(0) ) + +/* bits definitions for register REG_DJTAG_APB_RF_DJTAG_UPD_DR_CFG */ +#define BITS_DJTAG_UPD_DR(_X_) (_X_) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_gpu_apb_rf.h b/include/soc/sprd/chip_x35lt8/__regs_gpu_apb_rf.h new file mode 100644 index 00000000..5454b47a --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_gpu_apb_rf.h @@ -0,0 +1,48 @@ +/* the head file modifier: g 2015-03-19 15:47:17*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_GPU_APB_RF_HEADFILE_H__ +#define __H_REGS_GPU_APB_RF_HEADFILE_H__ __FILE__ + +#define REGS_GPU_APB_RF + +/* registers definitions for GPU_APB_RF */ +#define REG_GPU_APB_APB_RST SCI_ADDR(REGS_GPU_APB_BASE, 0x0000)/*APB_RST*/ +#define REG_GPU_APB_APB_CLK_CTRL SCI_ADDR(REGS_GPU_APB_BASE, 0x0004)/*APB_CLK_CTRL*/ +#define REG_GPU_APB_APB_BARRIER_CTRL SCI_ADDR(REGS_GPU_APB_BASE, 0x0008)/*APB_BARRIER_CTRL*/ + + + +/* bits definitions for register REG_GPU_APB_APB_RST */ +#define BIT_GPU_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_GPU_APB_APB_CLK_CTRL */ +#define BITS_CLK_GPU_DIV(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CLK_GPU_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_GPU_APB_APB_BARRIER_CTRL */ +#define BIT_GPU_BARRIER_DISABLE_EN ( BIT(0) ) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_lte_cevax_pmu.h b/include/soc/sprd/chip_x35lt8/__regs_lte_cevax_pmu.h new file mode 100644 index 00000000..4996d47e --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_lte_cevax_pmu.h @@ -0,0 +1,371 @@ +/* the head file modifier: g 2015-03-19 15:47:41*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_LTE_CEVAX_PMU_HEADFILE_H__ +#define __H_REGS_LTE_CEVAX_PMU_HEADFILE_H__ __FILE__ + +#define REGS_LTE_CEVAX_PMU + +/* registers definitions for LTE_CEVAX_PMU */ +#define REG_LTE_CEVAX_PMU_PLL_CFG0 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0000)/*PLL Config 0*/ +#define REG_LTE_CEVAX_PMU_PLL_CFG1 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0004)/*PLL Config 1*/ +#define REG_LTE_CEVAX_PMU_CXCLK_DIV SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0008)/*CX Clock Division*/ +#define REG_LTE_CEVAX_PMU_XHCLK_DIV SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x000C)/*XH Clock Division*/ +#define REG_LTE_CEVAX_PMU_XPCLK_DIV SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0010)/*XP Clock Division*/ +#define REG_LTE_CEVAX_PMU_CXPMOD SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0014)/*CX Power Mode*/ +#define REG_LTE_CEVAX_PMU_XHPMOD SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0018)/*XH Power Mode*/ +#define REG_LTE_CEVAX_PMU_XAPBMOD SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x001C)/*XP Power Mode*/ +#define REG_LTE_CEVAX_PMU_VERSION_CR SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0020)/*Version information*/ +#define REG_LTE_CEVAX_PMU_SLEEP_STATUS SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0024)/*Sleep Status*/ +#define REG_LTE_CEVAX_PMU_POW_CTL0 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0028)/*Power Control0*/ +#define REG_LTE_CEVAX_PMU_POW_CTL1 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x002C)/*Power Control1*/ +#define REG_LTE_CEVAX_PMU_POW_CTL2 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0030)/*Power Control2*/ +#define REG_LTE_CEVAX_PMU_ACCCLK_EN0 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0034)/*Accelerator Clock Enable0*/ +#define REG_LTE_CEVAX_PMU_ACCCLK_EN1 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0038)/*Accelerator Clock Enable1*/ +#define REG_LTE_CEVAX_PMU_ACCCLK_EN2 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x003C)/*Accelerator Clock Enable2*/ +#define REG_LTE_CEVAX_PMU_SOFT_RST0 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0040)/*SOFT_RST0*/ +#define REG_LTE_CEVAX_PMU_SOFT_RST1 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0044)/*SOFT_RST1*/ +#define REG_LTE_CEVAX_PMU_DSP_CKG_SEL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0048)/*DSP_CKG_SEL*/ +#define REG_LTE_CEVAX_PMU_CLK_DLCH_SEL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0050)/*CLK_DLCH_SEL*/ +#define REG_LTE_CEVAX_PMU_CLK_ULCH_SEL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0054)/*CLK_ULCH_SEL*/ +#define REG_LTE_CEVAX_PMU_CLK_RATEM_SEL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0058)/*CLK_RATEM_SEL*/ +#define REG_LTE_CEVAX_PMU_CLK_LTE_SPI_DIV_SEL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x005C)/*clk_lte_spi_div and clk_lte_spi_sel*/ +#define REG_LTE_CEVAX_PMU_CX_CKG_DIV SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0078)/*CX_CKG_DIV*/ +#define REG_LTE_CEVAX_PMU_XH_CKG_DIV SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x007C)/*XH_CKG_DIV*/ +#define REG_LTE_CEVAX_PMU_XP_CKG_DIV SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0080)/*XP_CKG_DIV*/ +#define REG_LTE_CEVAX_PMU_LTE_PMU_CKG_EN SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0084)/*CKG_EN*/ +#define REG_LTE_CEVAX_PMU_LTE_PMU_CLK_EN SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0088)/*LTE_PMU_CLK_EN*/ +#define REG_LTE_CEVAX_PMU_APB_CLK_SEL0 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x008C)/*APB_CLK_SEL0*/ +#define REG_LTE_CEVAX_PMU_APB_CLK_SEL1 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0090)/*APB_CLK_SEL1*/ +#define REG_LTE_CEVAX_PMU_CLK_CXTMR0_SEL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0094)/*CLK_CXTMR0_SEL*/ +#define REG_LTE_CEVAX_PMU_CLK_CXTMR1_SEL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0098)/*CLK_CXTMR1_SEL*/ +#define REG_LTE_CEVAX_PMU_CLK_CXTMR2_SEL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x009C)/*CLK_CXTMR2_SEL*/ +#define REG_LTE_CEVAX_PMU_APB_CLK_SEL2 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x00A0)/*APB_CLK_SEL2*/ +#define REG_LTE_CEVAX_PMU_MEM_LP_CTRL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0xA4)/*MEM_LP_CTRL*/ +#define REG_LTE_CEVAX_PMU_AXI_MON_CTRL SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0xA8)/*AXI_MON_CTRL*/ +#define REG_LTE_CEVAX_PMU_RES_REG0 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0140)/*RES_REG0*/ +#define REG_LTE_CEVAX_PMU_RES_REG1 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0144)/*RES_REG1*/ +#define REG_LTE_CEVAX_PMU_RES_REG2 SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0148)/*RES_REG2*/ + + + +/* bits definitions for register REG_LTE_CEVAX_PMU_PLL_CFG0 */ +#define BITS_PLL_CFG0_R(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_IIS3_EB ( BIT(10) ) +#define BIT_IIS2_EB ( BIT(9) ) +#define BIT_DSP_DLCH_EN ( BIT(8) ) +#define BIT_DSP_ULCH_EN ( BIT(7) ) +#define BIT_DLCH_AUTO_EN ( BIT(6) ) +#define BIT_ULCH_AUTO_EN ( BIT(5) ) +#define BIT_IIS1_EB ( BIT(4) ) +#define BIT_IIS0_EB ( BIT(3) ) +#define BIT_UART1_EB ( BIT(2) ) +#define BIT_UART0_EB ( BIT(1) ) +#define BIT_RFFE_EB ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_PLL_CFG1 */ +#define BIT_CHIP_SLP_REC_DSP ( BIT(16) ) +#define BIT_LTE_POW_OFF ( BIT(10) ) +#define BIT_LTE_POW_READY ( BIT(9) ) +#define BITS_LTE_POW_WAIT(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) ) +#define BIT_CHIP_SLP_DSP_CLR ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CXCLK_DIV */ +#define BITS_CXREG_AUTO_OFF(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_XHCLK_DIV */ +#define BIT_BUSMON2_CHN_SEL ( BIT(25) ) +#define BIT_BUSMON1_CHN_SEL ( BIT(24) ) +#define BIT_BUSMON0_CHN_SEL ( BIT(23) ) +#define BITS_DSP_SHM_CTRL(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BIT_DSPAPB_DES_AUTO_EN ( BIT(20) ) +#define BIT_DSPAHB_DES_AUTO_EN ( BIT(19) ) +#define BITS_LBUSMON2_CHN_SEL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) ) +#define BITS_LBUSMON1_CHN_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_LBUSMON0_CHN_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_DSPAPB_DIV_DES(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DSPAHB_DIV_DES(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)) ) +#define BITS_CX_DSPPLL_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_XPCLK_DIV */ +#define BIT_PMU_DMA_FRC_EB ( BIT(24) ) +#define BIT_ZBUS_32ACCESS ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CXPMOD */ +#define BIT_MCU_FORCE_DEEP_SLEEP ( BIT(31) ) +#define BIT_LDSP_DEEP_SLP_CTRL ( BIT(30) ) +#define BIT_EMC_LIGHT_SLEEP_EN_M6 ( BIT(29) ) +#define BIT_EMC_DEEP_SLEEP_EN_M6 ( BIT(28) ) +#define BIT_EMC_LIGHT_SLEEP_EN_M7 ( BIT(27) ) +#define BIT_EMC_DEEP_SLEEP_EN_M7 ( BIT(26) ) +#define BIT_EMC_LIGHT_SLEEP_EN_M8 ( BIT(25) ) +#define BIT_EMC_DEEP_SLEEP_EN_M8 ( BIT(24) ) +#define BIT_LDSP2PUB_ACCESS_EN ( BIT(8) ) +#define BIT_LDSP_WAKEUP_XTL_EN ( BIT(7) ) +#define BIT_DMA_LSLP_EN ( BIT(4) ) +#define BIT_DSP_LIGHT_SLEEP_EN ( BIT(3) ) +#define BIT_DSP_DEEP_SLEEP_EN ( BIT(2) ) +#define BIT_DSP_SYS_SLEEP_EN ( BIT(1) ) +#define BIT_DSP_CORE_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_XHPMOD */ +#define BIT_BUSMON2_EB ( BIT(31) ) +#define BIT_BUSMON1_EB ( BIT(30) ) +#define BIT_BUSMON0_EB ( BIT(29) ) +#define BIT_LACCX_AUTO_GATE_EN ( BIT(14) ) +#define BIT_LDSPX_AUTO_GATE_EN ( BIT(13) ) +#define BIT_CXDMA_CLK_AUTO_EN ( BIT(12) ) +#define BIT_CXAPB_AUTO_GATE_EN ( BIT(11) ) +#define BIT_CXAHB_AUTO_GATE_EN ( BIT(10) ) +#define BIT_CXDSP_AUTO_GATE_EN ( BIT(9) ) +#define BIT_CXCORE_AUTO_GATE_EN ( BIT(8) ) +#define BIT_CXMTX_AUTO_GATE_EN ( BIT(7) ) +#define BIT_DSP_MAHB_SLEEP_EN ( BIT(6) ) +#define BIT_ACCZ_ARCH_EB ( BIT(5) ) +#define BIT_CXBUS_ARCH_EB ( BIT(4) ) +#define BIT_LTEPROC_ARCH_EB ( BIT(3) ) +#define BIT_PMU_DLCH_SLEEP_R ( BIT(1) ) +#define BIT_PMU_ULCH_SLEEP_R ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_XAPBMOD */ +#define BITS_HPROTDMAW(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_HPROTDMAR(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_PMU_XPSLEEP_P_R(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_VERSION_CR */ +#define BITS_VERSION_CR(_X_) (_X_) + +/* bits definitions for register REG_LTE_CEVAX_PMU_SLEEP_STATUS */ +#define BITS_PMU_SLEEP_STATUS(_X_) (_X_) + +/* bits definitions for register REG_LTE_CEVAX_PMU_POW_CTL0 */ +#define BITS_LTE_ISO_ON_NUM(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LTE_ISO_OFF_NUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_POW_CTL1 */ +#define BIT_CLK_PWR_LTE_SEL ( BIT(10) ) +#define BIT_LTE_SLP_POWOFF_AUTO_EN ( BIT(9) ) +#define BIT_LTE_POW_FORCE_PD ( BIT(8) ) +#define BITS_DSP_MEM_PD_REG(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_POW_CTL2 */ +#define BITS_DSP_MEM_PD_EN(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)) ) +#define BITS_PD_LTE_STATUS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_ACCCLK_EN0 */ +#define BIT_FFT_OFFLN_HCLKEN ( BIT(30) ) +#define BIT_FFT_OFFLN_CLKEN ( BIT(29) ) +#define BIT_FFT_ONLN_HCLKEN ( BIT(28) ) +#define BIT_FFT_ONLN_CLKEN ( BIT(27) ) +#define BIT_LTE_DRM_CLKEN ( BIT(24) ) +#define BIT_MIMO_HCLKEN ( BIT(23) ) +#define BIT_MIMO_CLKEN ( BIT(22) ) +#define BIT_PBCH_ACLKEN ( BIT(21) ) +#define BIT_PBCH_HCLKEN ( BIT(20) ) +#define BIT_PBCH_CLKEN ( BIT(19) ) +#define BIT_PCFICH_PHICH_HCLKEN ( BIT(18) ) +#define BIT_PCFICH_PHICH_CLKEN ( BIT(17) ) +#define BIT_PDCCH_ACLKEN ( BIT(16) ) +#define BIT_PDCCH_HCLKEN ( BIT(15) ) +#define BIT_PDCCH_CLKEN ( BIT(14) ) +#define BIT_PDSCH_TB_CTL_HCLKEN ( BIT(13) ) +#define BIT_PDSCH_TB_CTL_CLKEN ( BIT(12) ) +#define BIT_RXDFE_HCLKEN ( BIT(11) ) +#define BIT_SYNC_ACLKEN ( BIT(10) ) +#define BIT_SYNC_HCLKEN ( BIT(9) ) +#define BIT_SYNC_CLKEN ( BIT(8) ) +#define BIT_TBUF_ACLKEN ( BIT(7) ) +#define BIT_TBUF_HCLKEN ( BIT(6) ) +#define BIT_TBUF_CLKEN ( BIT(5) ) +#define BIT_VTB_CLKEN ( BIT(4) ) +#define BIT_LTE_PROC_HCLKEN ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_ACCCLK_EN1 */ +#define BIT_LBUSMON2_EB ( BIT(28) ) +#define BIT_LBUSMON1_EB ( BIT(27) ) +#define BIT_LBUSMON0_EB ( BIT(26) ) +#define BIT_HSDL_CLKEN ( BIT(25) ) +#define BIT_ULMAC_HCLKEN ( BIT(24) ) +#define BIT_TBE_HCLKEN ( BIT(23) ) +#define BIT_TBE_CLKEN ( BIT(22) ) +#define BIT_RM_HCLKEN ( BIT(21) ) +#define BIT_RM_CLKEN ( BIT(20) ) +#define BIT_PCM_HCLKEN ( BIT(19) ) +#define BIT_PCM_CLKEN ( BIT(18) ) +#define BIT_UCM_HCLKEN ( BIT(17) ) +#define BIT_UCM_CLKEN ( BIT(16) ) +#define BIT_CHE_ACLKEN ( BIT(15) ) +#define BIT_CHE_HCLKEN ( BIT(14) ) +#define BIT_CHE_SYS_CLKEN ( BIT(13) ) +#define BIT_CHEPP_ACLKEN ( BIT(12) ) +#define BIT_CHEPP_HCLKEN ( BIT(11) ) +#define BIT_CHEPP_SYS_CLKEN ( BIT(10) ) +#define BIT_DBUF_ACLKEN ( BIT(9) ) +#define BIT_DBUF_HCLKEN ( BIT(8) ) +#define BIT_DBUF_CLKEN ( BIT(7) ) +#define BIT_DFE_CLKEN ( BIT(6) ) +#define BIT_FBUF_ACLKEN ( BIT(5) ) +#define BIT_FBUF_HCLKEN ( BIT(4) ) +#define BIT_FBUF_CLKEN ( BIT(3) ) +#define BIT_FEC_ACLKEN ( BIT(2) ) +#define BIT_FEC_HCLKEN ( BIT(1) ) +#define BIT_FEC_CLKEN ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_ACCCLK_EN2 */ + +/* bits definitions for register REG_LTE_CEVAX_PMU_SOFT_RST0 */ +#define BITS_SOFT_RST_R(_X_) (_X_) + +/* bits definitions for register REG_LTE_CEVAX_PMU_SOFT_RST1 */ +#define BIT_LTE_PROC_SOFT_RST_RFT ( BIT(31) ) +#define BIT_HSDL_SOFT_RST ( BIT(30) ) +#define BIT_RFSPI_SOFT_RST ( BIT(29) ) +#define BIT_LTE_PROC_SOFT_RST ( BIT(28) ) +#define BIT_ULMAC_SOFT_RST ( BIT(27) ) +#define BIT_PCM_SOFT_RST ( BIT(26) ) +#define BIT_UCM_SOFT_RST ( BIT(25) ) +#define BIT_TBE_SOFT_RST ( BIT(24) ) +#define BIT_RM_SOFT_RST ( BIT(23) ) +#define BIT_RFT_SOFT_RST ( BIT(22) ) +#define BIT_DFE_SOFT_RST ( BIT(21) ) +#define BIT_MIMO_SOFT_RST ( BIT(20) ) +#define BIT_ON_LINE_FFT_SOFT_RST ( BIT(19) ) +#define BIT_OFF_LINE_FFT_SOFT_RST ( BIT(18) ) +#define BIT_PCFICH_SOFT_RST ( BIT(17) ) +#define BIT_PDSCH_SOFT_RST ( BIT(16) ) +#define BIT_DRM_SOFT_RST ( BIT(15) ) +#define BIT_VTB_SOFT_RST ( BIT(14) ) +#define BIT_FEC_SOFT_RST ( BIT(13) ) +#define BIT_CHE_SOFT_RST ( BIT(12) ) +#define BIT_CHEPP_SOFT_RST ( BIT(11) ) +#define BIT_SYNC_SOFT_RST ( BIT(10) ) +#define BIT_TBUF_SOFT_RST ( BIT(9) ) +#define BIT_DBUF_SOFT_RST ( BIT(8) ) +#define BIT_FBUF_SOFT_RST ( BIT(7) ) +#define BIT_PDCCH_SOFT_RST ( BIT(6) ) +#define BIT_PBCH_SOFT_RST ( BIT(5) ) +#define BIT_RXADC_SOFT_RST ( BIT(4) ) +#define BIT_TXDAC_SOFT_RST ( BIT(3) ) +#define BIT_CAL_SOFT_RST ( BIT(2) ) +#define BIT_RTC_SOFT_RST ( BIT(1) ) +#define BIT_LTE_SPI_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_DSP_CKG_SEL */ +#define BITS_DSP_CKG_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CLK_DLCH_SEL */ +#define BITS_CLK_DLCH_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CLK_ULCH_SEL */ +#define BITS_CLK_ULCH_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CLK_RATEM_SEL */ +#define BITS_CLK_RATEM_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CLK_LTE_SPI_DIV_SEL */ +#define BITS_CLK_LTE_SPI_DIV(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)) ) +#define BITS_CLK_LTE_SPI_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CX_CKG_DIV */ +#define BITS_CX_CKG_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_XH_CKG_DIV */ +#define BITS_XH_CKG_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_XP_CKG_DIV */ +#define BITS_XP_CKG_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_LTE_PMU_CKG_EN */ +#define BIT_DSP_CKG_EN ( BIT(8) ) +#define BIT_CX_CKG_EN ( BIT(6) ) +#define BIT_XH_CKG_EN ( BIT(5) ) +#define BIT_XP_CKG_EN ( BIT(4) ) +#define BIT_DMA_CKG_EN ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_LTE_PMU_CLK_EN */ +#define BIT_CLK_LTE_SA_EN ( BIT(17) ) +#define BIT_CLK_CXTMR2_EN ( BIT(16) ) +#define BIT_CLK_CXTMR1_EN ( BIT(15) ) +#define BIT_CLK_CXTMR0_EN ( BIT(14) ) +#define BIT_CLK_AXI_EN ( BIT(13) ) +#define BIT_CLK_AHB_EN ( BIT(12) ) +#define BIT_CLK_DFE_EN ( BIT(11) ) +#define BIT_CLK_RFT_EN ( BIT(10) ) +#define BIT_CLK_DLCH_EN ( BIT(9) ) +#define BIT_CLK_ULCH_EN ( BIT(8) ) +#define BIT_CLK_RATEM_EN ( BIT(7) ) +#define BIT_CLK_RXADC_EN ( BIT(6) ) +#define BIT_CLK_TXDAC_EN ( BIT(5) ) +#define BIT_CLK_LTE_ANA_2X_EN ( BIT(4) ) +#define BIT_CLK_LTE_ANA_1X_EN ( BIT(3) ) +#define BIT_CLK_CAL_EN ( BIT(2) ) +#define BIT_CLK_RTC_EN ( BIT(1) ) +#define BIT_CLK_LTE_SPI_EN ( BIT(0) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_APB_CLK_SEL0 */ +#define BITS_CLK_UART1_DIV(_X_) ( (_X_) << 7 & (BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_CLK_UART1_SEL(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)) ) +#define BITS_CLK_UART0_DIV(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)) ) +#define BITS_CLK_UART0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_APB_CLK_SEL1 */ +#define BITS_CLK_IIS1_DIV(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_CLK_IIS1_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_CLK_IIS0_DIV(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_CLK_IIS0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CLK_CXTMR0_SEL */ +#define BITS_CLK_CXTMR0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CLK_CXTMR1_SEL */ +#define BITS_CLK_CXTMR1_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_CLK_CXTMR2_SEL */ +#define BITS_CLK_CXTMR2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_APB_CLK_SEL2 */ +#define BITS_CLK_IIS3_DIV(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_CLK_IIS3_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_CLK_IIS2_DIV(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_CLK_IIS2_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_MEM_LP_CTRL */ +#define BITS_MEM_LP_CTRL(_X_) (_X_) + +/* bits definitions for register REG_LTE_CEVAX_PMU_AXI_MON_CTRL */ +#define BIT_AXI_MON_WAIT_EB ( BIT(21) ) +#define BIT_AXI_MON_CLKEN_EB ( BIT(20) ) +#define BITS_AXI_MONITOR_STATUS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_LTE_CEVAX_PMU_RES_REG0 */ +#define BITS_RES_REG0(_X_) (_X_) + +/* bits definitions for register REG_LTE_CEVAX_PMU_RES_REG1 */ +#define BITS_RES_REG1(_X_) (_X_) + +/* bits definitions for register REG_LTE_CEVAX_PMU_RES_REG2 */ +#define BITS_RES_REG2(_X_) (_X_) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_mdar_apb_rf.h b/include/soc/sprd/chip_x35lt8/__regs_mdar_apb_rf.h new file mode 100644 index 00000000..2828f484 --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_mdar_apb_rf.h @@ -0,0 +1,1183 @@ +/* the head file modifier: g 2015-03-19 17:11:33*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_MDAR_APB_RF_HEADFILE_H__ +#define __H_REGS_MDAR_APB_RF_HEADFILE_H__ __FILE__ + +#define REGS_MDAR_APB_RF + +/* registers definitions for MDAR_APB_RF */ +#define REG_MDAR_APB_RF_MDAR_CFG0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0000)/*MDAR configuration set 0*/ +#define REG_MDAR_APB_RF_MDAR_CFG1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0004)/*MDAR configuration set 1*/ +#define REG_MDAR_APB_RF_MDAR_CFG3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x000C)/*MDAR configuration set 3*/ +#define REG_MDAR_APB_RF_MDAR_DAC1_CTR1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0010)/*DAC1 control1*/ +#define REG_MDAR_APB_RF_MDAR_DAC1_CTR2 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0014)/*DAC1 control2*/ +#define REG_MDAR_APB_RF_MDAR_DAC1_CTR3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0018)/*DAC1control3*/ +#define REG_MDAR_APB_RF_MDAR_DAC1_CTR4 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x001C)/*DAC1 control4*/ +#define REG_MDAR_APB_RF_MDAR_DAC1_STS0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0020)/*DAC1 status0*/ +#define REG_MDAR_APB_RF_MDAR_DAC1_STS1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0024)/*DAC1 status1*/ +#define REG_MDAR_APB_RF_MDAR_CAL1_CTR0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0028)/*Calibration1 Control 0*/ +#define REG_MDAR_APB_RF_MDAR_CAL1_CTR1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x002C)/*Calibration1 Control 1*/ +#define REG_MDAR_APB_RF_MDAR_CAL1_CTR3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0030)/*Calibration1 Control 3*/ +#define REG_MDAR_APB_RF_MDAR_CAL1_STS0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0034)/*Calibration1 Status 0*/ +#define REG_MDAR_APB_RF_MDAR_CAL1_STS1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0038)/*Calibration1 Status 1*/ +#define REG_MDAR_APB_RF_MDAR_DAC1_CTR00 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x003C)/*DAC1 control00*/ +#define REG_MDAR_APB_RF_MDAR_DAC1_CTR10 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0040)/*DAC1 control10*/ +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0044)/*ADC1 control0*/ +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR00 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0048)/*ADC1 control00*/ +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR01 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x004C)/*ADC1 control01*/ +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR02 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0050)/*ADC1 control02*/ +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR10 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0054)/*ADC1 control10*/ +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR11 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0058)/*ADC1 control11*/ +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR12 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x005C)/*ADC1 control12*/ +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR20 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0060)/*ADC1 control20*/ +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR21 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0064)/*ADC1 control21*/ +#define REG_MDAR_APB_RF_MDAR_ADC1_CTR22 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0068)/*ADC1 control22*/ +#define REG_MDAR_APB_RF_MDAR_DAC2_CTR1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0070)/*DAC2 control1*/ +#define REG_MDAR_APB_RF_MDAR_DAC2_CTR2 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0074)/*DAC2 control2*/ +#define REG_MDAR_APB_RF_MDAR_DAC2_CTR3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0078)/*DAC2control3*/ +#define REG_MDAR_APB_RF_MDAR_DAC2_CTR4 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x007C)/*DAC2 control4*/ +#define REG_MDAR_APB_RF_MDAR_DAC2_STS0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0080)/*DAC2 status0*/ +#define REG_MDAR_APB_RF_MDAR_DAC2_STS1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0084)/*DAC2 status1*/ +#define REG_MDAR_APB_RF_MDAR_CAL2_CTR0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0088)/*Calibration2 Control 0*/ +#define REG_MDAR_APB_RF_MDAR_CAL2_CTR1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x008C)/*Calibration2 Control 1*/ +#define REG_MDAR_APB_RF_MDAR_CAL2_CTR3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0090)/*Calibration2 Control 3*/ +#define REG_MDAR_APB_RF_MDAR_CAL2_STS0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0094)/*Calibration2 Status 0*/ +#define REG_MDAR_APB_RF_MDAR_CAL2_STS1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0098)/*Calibration2 Status 1*/ +#define REG_MDAR_APB_RF_MDAR_DAC2_CTR00 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x009C)/*DAC2 control00*/ +#define REG_MDAR_APB_RF_MDAR_DAC2_CTR10 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00A0)/*DAC2 control10*/ +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00A4)/*ADC2 control0*/ +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR00 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00A8)/*ADC2 control00*/ +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR01 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00AC)/*ADC2 control01*/ +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR02 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00B0)/*ADC2 control02*/ +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR10 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00B4)/*ADC2 control10*/ +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR11 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00B8)/*ADC2 control11*/ +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR12 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00BC)/*ADC2 control12*/ +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR20 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00C0)/*ADC2 control20*/ +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR21 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00C4)/*ADC2 control21*/ +#define REG_MDAR_APB_RF_MDAR_ADC2_CTR22 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00C8)/*ADC2 control22*/ +#define REG_MDAR_APB_RF_MDAR_DAC3_CTR1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00D0)/*DAC3 control1*/ +#define REG_MDAR_APB_RF_MDAR_DAC3_CTR2 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00D4)/*DAC3 control2*/ +#define REG_MDAR_APB_RF_MDAR_DAC3_CTR3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00D8)/*DAC3control3*/ +#define REG_MDAR_APB_RF_MDAR_DAC3_CTR4 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00DC)/*DAC3 control4*/ +#define REG_MDAR_APB_RF_MDAR_DAC3_STS0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00E0)/*DAC3 status0*/ +#define REG_MDAR_APB_RF_MDAR_DAC3_STS1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00E4)/*DAC3 status1*/ +#define REG_MDAR_APB_RF_MDAR_CAL3_CTR0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00E8)/*Calibration3 Control 0*/ +#define REG_MDAR_APB_RF_MDAR_CAL3_CTR1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00EC)/*Calibration3 Control 1*/ +#define REG_MDAR_APB_RF_MDAR_CAL3_CTR3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00F0)/*Calibration3 Control 3*/ +#define REG_MDAR_APB_RF_MDAR_CAL3_STS0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00F4)/*Calibration3 Status 0*/ +#define REG_MDAR_APB_RF_MDAR_CAL3_STS1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00F8)/*Calibration3 Status 1*/ +#define REG_MDAR_APB_RF_MDAR_DAC3_CTR00 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00FC)/*DAC3 control00*/ +#define REG_MDAR_APB_RF_MDAR_DAC3_CTR10 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0100)/*DAC3 control10*/ +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0104)/*ADC3 control0*/ +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR00 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0108)/*ADC3 control00*/ +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR01 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x010C)/*ADC3 control01*/ +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR02 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0110)/*ADC3 control02*/ +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR10 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0114)/*ADC3 control10*/ +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR11 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0118)/*ADC3 control11*/ +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR12 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x011C)/*ADC3 control12*/ +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR20 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0120)/*ADC3 control20*/ +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR21 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0124)/*ADC3 control21*/ +#define REG_MDAR_APB_RF_MDAR_ADC3_CTR22 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0128)/*ADC3 control22*/ +#define REG_MDAR_APB_RF_MDAR_AFCDAC1_CFG SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x012C)/*AFCDAC1 configuration register*/ +#define REG_MDAR_APB_RF_MDAR_AFCDAC2_CFG SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0130)/*AFCDAC2 configuration register*/ +#define REG_MDAR_APB_RF_MDAR_APCDAC1_CFG SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0134)/*APCDAC1 configuration register*/ +#define REG_MDAR_APB_RF_MDAR_APCDAC2_CFG SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0138)/*APCDAC2 configuration register*/ +#define REG_MDAR_APB_RF_MDAR_RFSPI_CFG SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x13C)/*RFSPI configuration register*/ +#define REG_MDAR_APB_RF_MDAR_RFMIPI_CFG SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x140)/*RFMIPI configuration register*/ +#define REG_MDAR_APB_RF_MDAR_APCDAC_OUTSEL SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x144)/*Multi-mode APC_OUT_SEL configuration register*/ +#define REG_MDAR_APB_RF_MDAR_CLASH_CHK SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x148)/*Multi-mode clash operation set register*/ +#define REG_MDAR_APB_RF_MDAR_CLASH_SNAP SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x14C)/*Multi-mode clash operation snap timer*/ +#define REG_MDAR_APB_RF_MDAR_CLASH_STATUS1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x150)/*Multi-mode clash detail information rgister1*/ +#define REG_MDAR_APB_RF_MDAR_CLASH_STATUS2 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x154)/*Multi-mode clash detail information rgister2*/ +#define REG_MDAR_APB_RF_MDAR_CLASH_STATUS3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x158)/*Multi-mode clash detail information rgister3*/ +#define REG_MDAR_APB_RF_MDAR_EXTRA_CFG0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x160)/*mdar extra cfg0*/ +#define REG_MDAR_APB_RF_MDAR_EXTRA_CFG1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x164)/*mdar extra cfg1*/ +#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF0 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x168)/*mdar_rfctrl15_inf0*/ +#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF1 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x16C)/*mdar_rfctrl15_inf*/ +#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF2 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x170)/*mdar_rfctrl15_inf*/ +#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF3 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x174)/*mdar_rfctrl15_inf*/ +#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF4 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x178)/*mdar_rfctrl15_inf*/ +#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF5 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x17C)/*mdar_rfctrl15_inf*/ +#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF6 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x180)/*mdar_rfctrl15_inf*/ +#define REG_MDAR_APB_RF_MDAR_CFG4 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0184)/*MDAR configuration set 4*/ +#define REG_MDAR_APB_RF_MDAR_CFG5 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0188)/*MDAR configuration set 5*/ +#define REG_MDAR_APB_RF_MDAR_CFG6 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x018C)/*MDAR configuration set 6*/ +#define REG_MDAR_APB_RF_MDAR_CFG7 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0190)/*MDAR configuration set 7*/ +#define REG_MDAR_APB_RF_MDAR_CFG8 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0194)/*MDAR configuration set 8*/ +#define REG_MDAR_APB_RF_MDAR_CFG9 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0198)/*MDAR configuration set 9*/ +#define REG_MDAR_APB_RF_MDAR_CFG10 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x019C)/*MDAR configuration set 10*/ +#define REG_MDAR_APB_RF_MDAR_CFG11 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x01B0)/*MDAR configuration set 11*/ +#define REG_MDAR_APB_RF_MDAR_CFG12 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x01B4)/*MDAR configuration set 12*/ +#define REG_MDAR_APB_RF_MDAR_CFG13 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x01B8)/*MDAR configuration set 13*/ +#define REG_MDAR_APB_RF_MDAR_CFG14 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x01BC)/*MDAR configuration set 14*/ +#define REG_MDAR_APB_RF_MDAR_CFG15 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1C0)/*MDAR configuration set15*/ +#define REG_MDAR_APB_RF_MDAR_IMB_CFG10 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1C4)/*MDAR IQ Imblace process set10*/ +#define REG_MDAR_APB_RF_MDAR_IMB_CFG11 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1C8)/*MDAR IQ Imblace process set11*/ +#define REG_MDAR_APB_RF_MDAR_IMB_CFG12 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1CC)/*MDAR IQ Imblace process set12*/ +#define REG_MDAR_APB_RF_MDAR_IMB_CFG13 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1D0)/*MDAR IQ Imblace process set13*/ +#define REG_MDAR_APB_RF_MDAR_IMB_CFG14 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1D4)/*MDAR IQ Imblace process set14*/ +#define REG_MDAR_APB_RF_MDAR_IMB_CFG20 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1D8)/*MDAR IQ Imblace process set20*/ +#define REG_MDAR_APB_RF_MDAR_IMB_CFG21 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1DC)/*MDAR IQ Imblace process set21*/ +#define REG_MDAR_APB_RF_MDAR_IMB_CFG22 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1E0)/*MDAR IQ Imblace process set22*/ +#define REG_MDAR_APB_RF_MDAR_IMB_CFG23 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1E4)/*MDAR IQ Imblace process set23*/ +#define REG_MDAR_APB_RF_MDAR_IMB_CFG24 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1E8)/*MDAR IQ Imblace process set24*/ +#define REG_MDAR_APB_RF_MDAR_IMB_CFG30 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1EC)/*MDAR IQ Imblace process set30*/ +#define REG_MDAR_APB_RF_MDAR_IMB_CFG31 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1F0)/*MDAR IQ Imblace process set31*/ +#define REG_MDAR_APB_RF_MDAR_IMB_CFG32 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1F4)/*MDAR IQ Imblace process set32*/ +#define REG_MDAR_APB_RF_MDAR_IMB_CFG33 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1F8)/*MDAR IQ Imblace process set33*/ +#define REG_MDAR_APB_RF_MDAR_IMB_CFG34 SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1FC)/*MDAR IQ Imblace process set34*/ + + + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG0 */ +#define BIT_MDAR_ADA_MODE ( BIT(31) ) +#define BITS_ADC3_CHANNEL_SSET(_X_) ( (_X_) << 26 & (BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_ADC2_CHANNEL_SSET(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_ADC1_CHANNEL_SSET(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)) ) +#define BIT_MDAR_WTG_MODE ( BIT(15) ) +#define BITS_ADC3_CHANNEL_MASK(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_ADC2_CHANNEL_MASK(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_ADC1_CHANNEL_MASK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG1 */ +#define BITS_DAC3_CHANNEL_SSET(_X_) ( (_X_) << 26 & (BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_DAC2_CHANNEL_SSET(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC1_CHANNEL_SSET(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_DAC3_CHANNEL_MASK(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_DAC2_CHANNEL_MASK(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_DAC1_CHANNEL_MASK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG3 */ +#define BITS_DACX_SBC_SET(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_ADCX_SBC_SET(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_CTR1 */ +#define BITS_DAC1_WD_OVR(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DAC1_WADDR_OVR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DAC1_WLE_OVR ( BIT(2) ) +#define BIT_DAC1_W_OVR_I_QN ( BIT(1) ) +#define BIT_DAC1_W_OVR_EN ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_CTR2 */ +#define BIT_DAC1_AUTO_RST ( BIT(23) ) +#define BIT_DAC1_SOFT_RST ( BIT(22) ) +#define BIT_DAC1_OSBC ( BIT(21) ) +#define BIT_DAC1_ISBC ( BIT(20) ) +#define BIT_DAC1_OVR_EN_CAL ( BIT(19) ) +#define BIT_DAC1_EN_OOSCAL ( BIT(18) ) +#define BIT_DAC1_IQSWAP ( BIT(17) ) +#define BIT_DAC1_CAL_START ( BIT(16) ) +#define BITS_DAC1_OFFSETI(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DAC1_OFFSETQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_CTR3 */ +#define BITS_DAC1_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DAC1_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_CTR4 */ +#define BITS_DAC1_I_CAL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DAC1_Q_CAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_STS0 */ +#define BITS_DAC1_WTI(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DAC1_WTQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_STS1 */ +#define BITS_DAC1_DA_STATE(_X_) ( (_X_) << 17 & (BIT(17)|BIT(18)) ) +#define BIT_DAC1_DONE ( BIT(16) ) +#define BITS_DAC1_WQ_OVR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL1_CTR0 */ +#define BITS_ADC1_CLK_CAL_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_ADA1_CAL_WAIT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_CLK_ADA1_CAL_EN ( BIT(6) ) +#define BIT_DAC1_PD_CAL ( BIT(5) ) +#define BIT_ADC1_EN_CAL ( BIT(3) ) +#define BIT_ADC1_CAL ( BIT(1) ) +#define BIT_ADA1_MODE_SEL ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL1_CTR1 */ +#define BITS_ADC1_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) ) +#define BITS_ADC1_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL1_CTR3 */ +#define BIT_ADA1_CAL_START ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL1_STS0 */ +#define BIT_ADA1_CAL_DONE ( BIT(31) ) +#define BITS_ADC1_CAL_I_SUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL1_STS1 */ +#define BITS_ADC1_CAL_Q_SUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_CTR00 */ +#define BIT_DAC1_OUT_SEL_2 ( BIT(26) ) +#define BITS_DAC1_RSV_2(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC1_PCTRL_2(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)) ) +#define BIT_DAC1_CLK_SEL_2 ( BIT(18) ) +#define BIT_DAC1_OUT_SEL_1 ( BIT(17) ) +#define BITS_DAC1_RSV_1(_X_) ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)) ) +#define BITS_DAC1_PCTRL_1(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DAC1_CLK_SEL_1 ( BIT(9) ) +#define BIT_DAC1_OUT_SEL_0 ( BIT(8) ) +#define BITS_DAC1_RSV_0(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DAC1_PCTRL_0(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)) ) +#define BIT_DAC1_CLK_SEL_0 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_CTR10 */ +#define BIT_DAC1_OUT_SEL_5 ( BIT(26) ) +#define BITS_DAC1_RSV_5(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC1_PCTRL_5(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)) ) +#define BIT_DAC1_CLK_SEL_5 ( BIT(18) ) +#define BIT_DAC1_OUT_SEL_4 ( BIT(17) ) +#define BITS_DAC1_RSV_4(_X_) ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)) ) +#define BITS_DAC1_PCTRL_4(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DAC1_CLK_SEL_4 ( BIT(9) ) +#define BIT_DAC1_OUT_SEL_3 ( BIT(8) ) +#define BITS_DAC1_RSV_3(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DAC1_PCTRL_3(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)) ) +#define BIT_DAC1_CLK_SEL_3 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR0 */ +#define BIT_ADC1_SOFT_RST ( BIT(31) ) +#define BITS_ADC1_DLL_OUT(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_ADC1_CALRDOUT(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) ) +#define BIT_ADC1_DLL_SOFT_RST ( BIT(10) ) +#define BIT_ADC1_CAL_SOFT_RST ( BIT(9) ) +#define BIT_ADC1_CALRD ( BIT(8) ) +#define BIT_ADC1_CALEN ( BIT(7) ) +#define BITS_ADC1_CALADDR(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_ADC1_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR00 */ +#define BITS_ADC1_RSV_1(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC1_RSV_0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR01 */ +#define BIT_ADC1_DIG_CLK_SEL_0 ( BIT(30) ) +#define BIT_ADC1_VCM_SEL_0 ( BIT(29) ) +#define BITS_ADC1_DELAY_CAP_0(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC1_BIT_SEL_0(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC1_VREF_SEL_0(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC1_VREF_BOOST_0(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC1_QUANT_BOOST_0(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC1_DLLRD_0 ( BIT(18) ) +#define BIT_ADC1_DLLWR_0 ( BIT(17) ) +#define BIT_ADC1_DLLEN_0 ( BIT(16) ) +#define BIT_ADC1_CSBC ( BIT(15) ) +#define BIT_ADC1_IQSWAP ( BIT(14) ) +#define BITS_ADC1_DLLOOF_0(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_ADC1_OSBC ( BIT(7) ) +#define BIT_ADC1_ISBC ( BIT(6) ) +#define BITS_ADC1_DLLIN_0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR02 */ +#define BIT_ADC1_DIG_CLK_SEL_1 ( BIT(30) ) +#define BIT_ADC1_VCM_SEL_1 ( BIT(29) ) +#define BITS_ADC1_DELAY_CAP_1(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC1_BIT_SEL_1(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC1_VREF_SEL_1(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC1_VREF_BOOST_1(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC1_QUANT_BOOST_1(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC1_DLLRD_1 ( BIT(18) ) +#define BIT_ADC1_DLLWR_1 ( BIT(17) ) +#define BIT_ADC1_DLLEN_1 ( BIT(16) ) +#define BITS_ADC1_DLLOOF_1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC1_DLLIN_1(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR10 */ +#define BITS_ADC1_RSV_3(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC1_RSV_2(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR11 */ +#define BIT_ADC1_DIG_CLK_SEL_2 ( BIT(30) ) +#define BIT_ADC1_VCM_SEL_2 ( BIT(29) ) +#define BITS_ADC1_DELAY_CAP_2(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC1_BIT_SEL_2(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC1_VREF_SEL_2(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC1_VREF_BOOST_2(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC1_QUANT_BOOST_2(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC1_DLLRD_2 ( BIT(18) ) +#define BIT_ADC1_DLLWR_2 ( BIT(17) ) +#define BIT_ADC1_DLLEN_2 ( BIT(16) ) +#define BITS_ADC1_DLLOOF_2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC1_DLLIN_2(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR12 */ +#define BIT_ADC1_DIG_CLK_SEL_3 ( BIT(30) ) +#define BIT_ADC1_VCM_SEL_3 ( BIT(29) ) +#define BITS_ADC1_DELAY_CAP_3(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC1_BIT_SEL_3(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC1_VREF_SEL_3(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC1_VREF_BOOST_3(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC1_QUANT_BOOST_3(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC1_DLLRD_3 ( BIT(18) ) +#define BIT_ADC1_DLLWR_3 ( BIT(17) ) +#define BIT_ADC1_DLLEN_3 ( BIT(16) ) +#define BITS_ADC1_DLLOOF_3(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC1_DLLIN_3(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR20 */ +#define BITS_ADC1_RSV_5(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC1_RSV_4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR21 */ +#define BIT_ADC1_DIG_CLK_SEL_4 ( BIT(30) ) +#define BIT_ADC1_VCM_SEL_4 ( BIT(29) ) +#define BITS_ADC1_DELAY_CAP_4(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC1_BIT_SEL_4(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC1_VREF_SEL_4(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC1_VREF_BOOST_4(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC1_QUANT_BOOST_4(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC1_DLLRD_4 ( BIT(18) ) +#define BIT_ADC1_DLLWR_4 ( BIT(17) ) +#define BIT_ADC1_DLLEN_4 ( BIT(16) ) +#define BITS_ADC1_DLLOOF_4(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC1_DLLIN_4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR22 */ +#define BIT_ADC1_DIG_CLK_SEL_5 ( BIT(30) ) +#define BIT_ADC1_VCM_SEL_5 ( BIT(29) ) +#define BITS_ADC1_DELAY_CAP_5(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC1_BIT_SEL_5(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC1_VREF_SEL_5(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC1_VREF_BOOST_5(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC1_QUANT_BOOST_5(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC1_DLLRD_5 ( BIT(18) ) +#define BIT_ADC1_DLLWR_5 ( BIT(17) ) +#define BIT_ADC1_DLLEN_5 ( BIT(16) ) +#define BITS_ADC1_DLLOOF_5(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC1_DLLIN_5(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_CTR1 */ +#define BITS_DAC2_WD_OVR(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DAC2_WADDR_OVR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DAC2_WLE_OVR ( BIT(2) ) +#define BIT_DAC2_W_OVR_I_QN ( BIT(1) ) +#define BIT_DAC2_W_OVR_EN ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_CTR2 */ +#define BIT_DAC2_AUTO_RST ( BIT(23) ) +#define BIT_DAC2_SOFT_RST ( BIT(22) ) +#define BIT_DAC2_OSBC ( BIT(21) ) +#define BIT_DAC2_ISBC ( BIT(20) ) +#define BIT_DAC2_OVR_EN_CAL ( BIT(19) ) +#define BIT_DAC2_EN_OOSCAL ( BIT(18) ) +#define BIT_DAC2_IQSWAP ( BIT(17) ) +#define BIT_DAC2_CAL_START ( BIT(16) ) +#define BITS_DAC2_OFFSETI(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DAC2_OFFSETQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_CTR3 */ +#define BITS_DAC2_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DAC2_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_CTR4 */ +#define BITS_DAC2_I_CAL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DAC2_Q_CAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_STS0 */ +#define BITS_DAC2_WTI(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DAC2_WTQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_STS1 */ +#define BITS_DAC2_DA_STATE(_X_) ( (_X_) << 17 & (BIT(17)|BIT(18)) ) +#define BIT_DAC2_DONE ( BIT(16) ) +#define BITS_DAC2_WQ_OVR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL2_CTR0 */ +#define BITS_ADC2_CLK_CAL_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_ADA2_CAL_WAIT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_CLK_ADA2_CAL_EN ( BIT(6) ) +#define BIT_DAC2_PD_CAL ( BIT(5) ) +#define BIT_ADC2_EN_CAL ( BIT(3) ) +#define BIT_ADC2_CAL ( BIT(1) ) +#define BIT_ADA2_MODE_SEL ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL2_CTR1 */ +#define BITS_ADC2_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) ) +#define BITS_ADC2_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL2_CTR3 */ +#define BIT_ADA2_CAL_START ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL2_STS0 */ +#define BIT_ADA2_CAL_DONE ( BIT(31) ) +#define BITS_ADC2_CAL_I_SUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL2_STS1 */ +#define BITS_ADC2_CAL_Q_SUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_CTR00 */ +#define BIT_DAC2_OUT_SEL_2 ( BIT(26) ) +#define BITS_DAC2_RSV_2(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC2_PCTRL_2(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)) ) +#define BIT_DAC2_CLK_SEL_2 ( BIT(18) ) +#define BIT_DAC2_OUT_SEL_1 ( BIT(17) ) +#define BITS_DAC2_RSV_1(_X_) ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)) ) +#define BITS_DAC2_PCTRL_1(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DAC2_CLK_SEL_1 ( BIT(9) ) +#define BIT_DAC2_OUT_SEL_0 ( BIT(8) ) +#define BITS_DAC2_RSV_0(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DAC2_PCTRL_0(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)) ) +#define BIT_DAC2_CLK_SEL_0 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_CTR10 */ +#define BIT_DAC2_OUT_SEL_5 ( BIT(26) ) +#define BITS_DAC2_RSV_5(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC2_PCTRL_5(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)) ) +#define BIT_DAC2_CLK_SEL_5 ( BIT(18) ) +#define BIT_DAC2_OUT_SEL_4 ( BIT(17) ) +#define BITS_DAC2_RSV_4(_X_) ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)) ) +#define BITS_DAC2_PCTRL_4(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DAC2_CLK_SEL_4 ( BIT(9) ) +#define BIT_DAC2_OUT_SEL_3 ( BIT(8) ) +#define BITS_DAC2_RSV_3(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DAC2_PCTRL_3(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)) ) +#define BIT_DAC2_CLK_SEL_3 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR0 */ +#define BIT_ADC2_SOFT_RST ( BIT(31) ) +#define BITS_ADC2_DLL_OUT(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_ADC2_CALRDOUT(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) ) +#define BIT_ADC2_DLL_SOFT_RST ( BIT(10) ) +#define BIT_ADC2_CAL_SOFT_RST ( BIT(9) ) +#define BIT_ADC2_CALRD ( BIT(8) ) +#define BIT_ADC2_CALEN ( BIT(7) ) +#define BITS_ADC2_CALADDR(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_ADC2_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR00 */ +#define BITS_ADC2_RSV_1(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC2_RSV_0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR01 */ +#define BIT_ADC2_DIG_CLK_SEL_0 ( BIT(30) ) +#define BIT_ADC2_VCM_SEL_0 ( BIT(29) ) +#define BITS_ADC2_DELAY_CAP_0(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC2_BIT_SEL_0(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC2_VREF_SEL_0(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC2_VREF_BOOST_0(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC2_QUANT_BOOST_0(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC2_DLLRD_0 ( BIT(18) ) +#define BIT_ADC2_DLLWR_0 ( BIT(17) ) +#define BIT_ADC2_DLLEN_0 ( BIT(16) ) +#define BIT_ADC2_CSBC ( BIT(15) ) +#define BIT_ADC2_IQSWAP ( BIT(14) ) +#define BITS_ADC2_DLLOOF_0(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_ADC2_OSBC ( BIT(7) ) +#define BIT_ADC2_ISBC ( BIT(6) ) +#define BITS_ADC2_DLLIN_0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR02 */ +#define BIT_ADC2_DIG_CLK_SEL_1 ( BIT(30) ) +#define BIT_ADC2_VCM_SEL_1 ( BIT(29) ) +#define BITS_ADC2_DELAY_CAP_1(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC2_BIT_SEL_1(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC2_VREF_SEL_1(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC2_VREF_BOOST_1(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC2_QUANT_BOOST_1(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC2_DLLRD_1 ( BIT(18) ) +#define BIT_ADC2_DLLWR_1 ( BIT(17) ) +#define BIT_ADC2_DLLEN_1 ( BIT(16) ) +#define BITS_ADC2_DLLOOF_1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC2_DLLIN_1(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR10 */ +#define BITS_ADC2_RSV_3(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC2_RSV_2(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR11 */ +#define BIT_ADC2_DIG_CLK_SEL_2 ( BIT(30) ) +#define BIT_ADC2_VCM_SEL_2 ( BIT(29) ) +#define BITS_ADC2_DELAY_CAP_2(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC2_BIT_SEL_2(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC2_VREF_SEL_2(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC2_VREF_BOOST_2(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC2_QUANT_BOOST_2(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC2_DLLRD_2 ( BIT(18) ) +#define BIT_ADC2_DLLWR_2 ( BIT(17) ) +#define BIT_ADC2_DLLEN_2 ( BIT(16) ) +#define BITS_ADC2_DLLOOF_2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC2_DLLIN_2(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR12 */ +#define BIT_ADC2_DIG_CLK_SEL_3 ( BIT(30) ) +#define BIT_ADC2_VCM_SEL_3 ( BIT(29) ) +#define BITS_ADC2_DELAY_CAP_3(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC2_BIT_SEL_3(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC2_VREF_SEL_3(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC2_VREF_BOOST_3(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC2_QUANT_BOOST_3(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC2_DLLRD_3 ( BIT(18) ) +#define BIT_ADC2_DLLWR_3 ( BIT(17) ) +#define BIT_ADC2_DLLEN_3 ( BIT(16) ) +#define BITS_ADC2_DLLOOF_3(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC2_DLLIN_3(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR20 */ +#define BITS_ADC2_RSV_5(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC2_RSV_4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR21 */ +#define BIT_ADC2_DIG_CLK_SEL_4 ( BIT(30) ) +#define BIT_ADC2_VCM_SEL_4 ( BIT(29) ) +#define BITS_ADC2_DELAY_CAP_4(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC2_BIT_SEL_4(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC2_VREF_SEL_4(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC2_VREF_BOOST_4(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC2_QUANT_BOOST_4(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC2_DLLRD_4 ( BIT(18) ) +#define BIT_ADC2_DLLWR_4 ( BIT(17) ) +#define BIT_ADC2_DLLEN_4 ( BIT(16) ) +#define BITS_ADC2_DLLOOF_4(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC2_DLLIN_4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR22 */ +#define BIT_ADC2_DIG_CLK_SEL_5 ( BIT(30) ) +#define BIT_ADC2_VCM_SEL_5 ( BIT(29) ) +#define BITS_ADC2_DELAY_CAP_5(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC2_BIT_SEL_5(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC2_VREF_SEL_5(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC2_VREF_BOOST_5(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC2_QUANT_BOOST_5(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC2_DLLRD_5 ( BIT(18) ) +#define BIT_ADC2_DLLWR_5 ( BIT(17) ) +#define BIT_ADC2_DLLEN_5 ( BIT(16) ) +#define BITS_ADC2_DLLOOF_5(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC2_DLLIN_5(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_CTR1 */ +#define BITS_DAC3_WD_OVR(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DAC3_WADDR_OVR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_DAC3_WLE_OVR ( BIT(2) ) +#define BIT_DAC3_W_OVR_I_QN ( BIT(1) ) +#define BIT_DAC3_W_OVR_EN ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_CTR2 */ +#define BIT_DAC3_AUTO_RST ( BIT(23) ) +#define BIT_DAC3_SOFT_RST ( BIT(22) ) +#define BIT_DAC3_OSBC ( BIT(21) ) +#define BIT_DAC3_ISBC ( BIT(20) ) +#define BIT_DAC3_OVR_EN_CAL ( BIT(19) ) +#define BIT_DAC3_EN_OOSCAL ( BIT(18) ) +#define BIT_DAC3_IQSWAP ( BIT(17) ) +#define BIT_DAC3_CAL_START ( BIT(16) ) +#define BITS_DAC3_OFFSETI(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DAC3_OFFSETQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_CTR3 */ +#define BITS_DAC3_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DAC3_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_CTR4 */ +#define BITS_DAC3_I_CAL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DAC3_Q_CAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_STS0 */ +#define BITS_DAC3_WTI(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DAC3_WTQ(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_STS1 */ +#define BITS_DAC3_DA_STATE(_X_) ( (_X_) << 17 & (BIT(17)|BIT(18)) ) +#define BIT_DAC3_DONE ( BIT(16) ) +#define BITS_DAC3_WQ_OVR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL3_CTR0 */ +#define BITS_ADC3_CLK_CAL_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_ADA3_CAL_WAIT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_CLK_ADA3_CAL_EN ( BIT(6) ) +#define BIT_DAC3_PD_CAL ( BIT(5) ) +#define BIT_ADC3_EN_CAL ( BIT(3) ) +#define BIT_ADC3_CAL ( BIT(1) ) +#define BIT_ADA3_MODE_SEL ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL3_CTR1 */ +#define BITS_ADC3_Q_DC(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) ) +#define BITS_ADC3_I_DC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL3_CTR3 */ +#define BIT_ADA3_CAL_START ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL3_STS0 */ +#define BIT_ADA3_CAL_DONE ( BIT(31) ) +#define BITS_ADC3_CAL_I_SUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL3_STS1 */ +#define BITS_ADC3_CAL_Q_SUM(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_CTR00 */ +#define BIT_DAC3_OUT_SEL_2 ( BIT(26) ) +#define BITS_DAC3_RSV_2(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC3_PCTRL_2(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)) ) +#define BIT_DAC3_CLK_SEL_2 ( BIT(18) ) +#define BIT_DAC3_OUT_SEL_1 ( BIT(17) ) +#define BITS_DAC3_RSV_1(_X_) ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)) ) +#define BITS_DAC3_PCTRL_1(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DAC3_CLK_SEL_1 ( BIT(9) ) +#define BIT_DAC3_OUT_SEL_0 ( BIT(8) ) +#define BITS_DAC3_RSV_0(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DAC3_PCTRL_0(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)) ) +#define BIT_DAC3_CLK_SEL_0 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_CTR10 */ +#define BIT_DAC3_OUT_SEL_5 ( BIT(26) ) +#define BITS_DAC3_RSV_5(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DAC3_PCTRL_5(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)) ) +#define BIT_DAC3_CLK_SEL_5 ( BIT(18) ) +#define BIT_DAC3_OUT_SEL_4 ( BIT(17) ) +#define BITS_DAC3_RSV_4(_X_) ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)) ) +#define BITS_DAC3_PCTRL_4(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_DAC3_CLK_SEL_4 ( BIT(9) ) +#define BIT_DAC3_OUT_SEL_3 ( BIT(8) ) +#define BITS_DAC3_RSV_3(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DAC3_PCTRL_3(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)) ) +#define BIT_DAC3_CLK_SEL_3 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR0 */ +#define BIT_ADC3_SOFT_RST ( BIT(31) ) +#define BITS_ADC3_DLL_OUT(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_ADC3_CALRDOUT(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) ) +#define BIT_ADC3_DLL_SOFT_RST ( BIT(10) ) +#define BIT_ADC3_CAL_SOFT_RST ( BIT(9) ) +#define BIT_ADC3_CALRD ( BIT(8) ) +#define BIT_ADC3_CALEN ( BIT(7) ) +#define BITS_ADC3_CALADDR(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_ADC3_DEBUG_EN ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR00 */ +#define BITS_ADC3_RSV_1(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC3_RSV_0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR01 */ +#define BIT_ADC3_DIG_CLK_SEL_0 ( BIT(30) ) +#define BIT_ADC3_VCM_SEL_0 ( BIT(29) ) +#define BITS_ADC3_DELAY_CAP_0(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC3_BIT_SEL_0(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC3_VREF_SEL_0(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC3_VREF_BOOST_0(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC3_QUANT_BOOST_0(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC3_DLLRD_0 ( BIT(18) ) +#define BIT_ADC3_DLLWR_0 ( BIT(17) ) +#define BIT_ADC3_DLLEN_0 ( BIT(16) ) +#define BIT_ADC3_CSBC ( BIT(15) ) +#define BIT_ADC3_IQSWAP ( BIT(14) ) +#define BITS_ADC3_DLLOOF_0(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BIT_ADC3_OSBC ( BIT(7) ) +#define BIT_ADC3_ISBC ( BIT(6) ) +#define BITS_ADC3_DLLIN_0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR02 */ +#define BIT_ADC3_DIG_CLK_SEL_1 ( BIT(30) ) +#define BIT_ADC3_VCM_SEL_1 ( BIT(29) ) +#define BITS_ADC3_DELAY_CAP_1(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC3_BIT_SEL_1(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC3_VREF_SEL_1(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC3_VREF_BOOST_1(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC3_QUANT_BOOST_1(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC3_DLLRD_1 ( BIT(18) ) +#define BIT_ADC3_DLLWR_1 ( BIT(17) ) +#define BIT_ADC3_DLLEN_1 ( BIT(16) ) +#define BITS_ADC3_DLLOOF_1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC3_DLLIN_1(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR10 */ +#define BITS_ADC3_RSV_3(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC3_RSV_2(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR11 */ +#define BIT_ADC3_DIG_CLK_SEL_2 ( BIT(30) ) +#define BIT_ADC3_VCM_SEL_2 ( BIT(29) ) +#define BITS_ADC3_DELAY_CAP_2(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC3_BIT_SEL_2(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC3_VREF_SEL_2(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC3_VREF_BOOST_2(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC3_QUANT_BOOST_2(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC3_DLLRD_2 ( BIT(18) ) +#define BIT_ADC3_DLLWR_2 ( BIT(17) ) +#define BIT_ADC3_DLLEN_2 ( BIT(16) ) +#define BITS_ADC3_DLLOOF_2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC3_DLLIN_2(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR12 */ +#define BIT_ADC3_DIG_CLK_SEL_3 ( BIT(30) ) +#define BIT_ADC3_VCM_SEL_3 ( BIT(29) ) +#define BITS_ADC3_DELAY_CAP_3(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC3_BIT_SEL_3(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC3_VREF_SEL_3(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC3_VREF_BOOST_3(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC3_QUANT_BOOST_3(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC3_DLLRD_3 ( BIT(18) ) +#define BIT_ADC3_DLLWR_3 ( BIT(17) ) +#define BIT_ADC3_DLLEN_3 ( BIT(16) ) +#define BITS_ADC3_DLLOOF_3(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC3_DLLIN_3(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR20 */ +#define BITS_ADC3_RSV_5(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_ADC3_RSV_4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR21 */ +#define BIT_ADC3_DIG_CLK_SEL_4 ( BIT(30) ) +#define BIT_ADC3_VCM_SEL_4 ( BIT(29) ) +#define BITS_ADC3_DELAY_CAP_4(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC3_BIT_SEL_4(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC3_VREF_SEL_4(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC3_VREF_BOOST_4(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC3_QUANT_BOOST_4(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC3_DLLRD_4 ( BIT(18) ) +#define BIT_ADC3_DLLWR_4 ( BIT(17) ) +#define BIT_ADC3_DLLEN_4 ( BIT(16) ) +#define BITS_ADC3_DLLOOF_4(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC3_DLLIN_4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR22 */ +#define BIT_ADC3_DIG_CLK_SEL_5 ( BIT(30) ) +#define BIT_ADC3_VCM_SEL_5 ( BIT(29) ) +#define BITS_ADC3_DELAY_CAP_5(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)) ) +#define BITS_ADC3_BIT_SEL_5(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)) ) +#define BITS_ADC3_VREF_SEL_5(_X_) ( (_X_) << 23 & (BIT(23)|BIT(24)) ) +#define BITS_ADC3_VREF_BOOST_5(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BITS_ADC3_QUANT_BOOST_5(_X_) ( (_X_) << 19 & (BIT(19)|BIT(20)) ) +#define BIT_ADC3_DLLRD_5 ( BIT(18) ) +#define BIT_ADC3_DLLWR_5 ( BIT(17) ) +#define BIT_ADC3_DLLEN_5 ( BIT(16) ) +#define BITS_ADC3_DLLOOF_5(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_ADC3_DLLIN_5(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_AFCDAC1_CFG */ +#define BITS_AFCDAC1_CHANNEL_MASK(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_AFCDAC1_CHANNEL_SSET(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BIT_AFCDAC1_LOW_V_CON_SST ( BIT(23) ) +#define BIT_AFCDAC1_BP_RES_SST ( BIT(20) ) +#define BITS_AFCDAC1_G_SST(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_AFCDAC1_CTL_SST(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BIT_AFCDAC1_PD_SST ( BIT(15) ) +#define BITS_AFCDAC1_D_SST(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_AFCDAC2_CFG */ +#define BITS_AFCDAC2_CHANNEL_MASK(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_AFCDAC2_CHANNEL_SSET(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BIT_AFCDAC2_LOW_V_CON_SST ( BIT(23) ) +#define BIT_AFCDAC2_BP_RES_SST ( BIT(20) ) +#define BITS_AFCDAC2_G_SST(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_AFCDAC2_CTL_SST(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BIT_AFCDAC2_PD_SST ( BIT(15) ) +#define BITS_AFCDAC2_D_SST(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_APCDAC1_CFG */ +#define BITS_APCDAC1_CHANNEL_MASK(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_APCDAC1_CHANNEL_SSET(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BIT_APCDAC1_LOW_V_CON_SST ( BIT(23) ) +#define BITS_APCDAC1_OUTSEL_SST(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BIT_APCDAC1_BP_RES_SST ( BIT(20) ) +#define BITS_APCDAC1_G_SST(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_APCDAC1_CTL_SST(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BIT_APCDAC1_PD_SST ( BIT(15) ) +#define BIT_APCDAC1_SEL_SST ( BIT(14) ) +#define BITS_APCDAC1_D_SST(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_APCDAC2_CFG */ +#define BITS_APCDAC2_CHANNEL_MASK(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_APCDAC2_CHANNEL_SSET(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BIT_APCDAC2_LOW_V_CON_SST ( BIT(23) ) +#define BITS_APCDAC2_OUTSEL_SST(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)) ) +#define BIT_APCDAC2_BP_RES_SST ( BIT(20) ) +#define BITS_APCDAC2_G_SST(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BITS_APCDAC2_CTL_SST(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BIT_APCDAC2_PD_SST ( BIT(15) ) +#define BIT_APCDAC2_SEL_SST ( BIT(14) ) +#define BITS_APCDAC2_D_SST(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFSPI_CFG */ +#define BITS_RFSBI2_CHANNEL_MASK(_X_) ( (_X_) << 29 & (BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_RFSBI2_CHANNEL_SSET(_X_) ( (_X_) << 26 & (BIT(26)|BIT(27)|BIT(28)) ) +#define BIT_RFSBI2_IDATA_SST ( BIT(25) ) +#define BIT_RFSBI2_ODATA_SST ( BIT(24) ) +#define BIT_RFSBI2_DATA_OE_SST ( BIT(23) ) +#define BIT_RFSBI2_DATA_IE_SST ( BIT(22) ) +#define BIT_RFSBI2_CLK_SST ( BIT(21) ) +#define BIT_RFSBI2_CLK_OE_SST ( BIT(20) ) +#define BIT_RFSBI2_EN0_SST ( BIT(19) ) +#define BIT_RFSBI2_EN0_OE_SST ( BIT(18) ) +#define BIT_RFSBI2_EN1_SST ( BIT(17) ) +#define BIT_RFSBI2_EN1_OE_SST ( BIT(16) ) +#define BITS_RFSBI1_CHANNEL_MASK(_X_) ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_RFSBI1_CHANNEL_SSET(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) ) +#define BIT_RFSBI1_IDATA_SST ( BIT(9) ) +#define BIT_RFSBI1_ODATA_SST ( BIT(8) ) +#define BIT_RFSBI1_DATA_OE_SST ( BIT(7) ) +#define BIT_RFSBI1_DATA_IE_SST ( BIT(6) ) +#define BIT_RFSBI1_CLK_SST ( BIT(5) ) +#define BIT_RFSBI1_CLK_OE_SST ( BIT(4) ) +#define BIT_RFSBI1_EN0_SST ( BIT(3) ) +#define BIT_RFSBI1_EN0_OE_SST ( BIT(2) ) +#define BIT_RFSBI1_EN1_SST ( BIT(1) ) +#define BIT_RFSBI1_EN1_OE_SST ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFMIPI_CFG */ +#define BITS_RFMIPI2_CHANNEL_MASK(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_RFMIPI2_CHANNEL_SSET(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BIT_PAD_OUT_RFFE2_CLK_SST ( BIT(20) ) +#define BIT_PAD_OUT_RFFE2_DATA_SST ( BIT(19) ) +#define BIT_PAD_IN_RFFE2_DATA_SST ( BIT(18) ) +#define BIT_PAD_OE_RFFE2_DATA_SST ( BIT(17) ) +#define BIT_PAD_IE_RFFE2_DATA_SST ( BIT(16) ) +#define BITS_RFMIPI1_CHANNEL_MASK(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_RFMIPI1_CHANNEL_SSET(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BIT_PAD_OUT_RFFE1_CLK_SST ( BIT(4) ) +#define BIT_PAD_OUT_RFFE1_DATA_SST ( BIT(3) ) +#define BIT_PAD_IN_RFFE1_DATA_SST ( BIT(2) ) +#define BIT_PAD_OE_RFFE1_DATA_SST ( BIT(1) ) +#define BIT_PAD_IE_RFFE1_DATA_SST ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_APCDAC_OUTSEL */ +#define BIT_AFCDAC_LOW_V_CON_GGE ( BIT(31) ) +#define BIT_AFCDAC_LOW_V_CON_WG ( BIT(30) ) +#define BIT_AFCDAC_LOW_V_CON_WD ( BIT(29) ) +#define BIT_AFCDAC_LOW_V_CON_TG ( BIT(28) ) +#define BIT_AFCDAC_LOW_V_CON_TD ( BIT(27) ) +#define BIT_AFCDAC_LOW_V_CON_LTE ( BIT(26) ) +#define BITS_APCDACX_G3_SST(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_APCDACX_G2_SST(_X_) ( (_X_) << 22 & (BIT(22)|BIT(23)) ) +#define BITS_APCDACX_G1_SST(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)) ) +#define BITS_APCDACX_G0_SST(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) ) +#define BIT_APCDAC_LOW_V_CON_GGE ( BIT(17) ) +#define BIT_APCDAC_LOW_V_CON_WG ( BIT(16) ) +#define BIT_APCDAC_LOW_V_CON_WD ( BIT(15) ) +#define BIT_APCDAC_LOW_V_CON_TG ( BIT(14) ) +#define BIT_APCDAC_LOW_V_CON_TD ( BIT(13) ) +#define BIT_APCDAC_LOW_V_CON_LTE ( BIT(12) ) +#define BITS_APCDAC_OUTSEL_GGE(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) ) +#define BITS_APCDAC_OUTSEL_WG(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_APCDAC_OUTSEL_WD(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) ) +#define BITS_APCDAC_OUTSEL_TG(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_APCDAC_OUTSEL_TD(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) ) +#define BITS_APCDAC_OUTSEL_LTE(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CLASH_CHK */ +#define BIT_RFSBI2_CLASH_CHK_INTRP_EN ( BIT(29) ) +#define BIT_RFSBI1_CLASH_CHK_INTRP_EN ( BIT(28) ) +#define BIT_RFMIPI2_CLASH_CHK_INTRP_EN ( BIT(27) ) +#define BIT_RFMIPI1_CLASH_CHK_INTRP_EN ( BIT(26) ) +#define BIT_APCDAC2_CLASH_CHK_INTRP_EN ( BIT(25) ) +#define BIT_APCDAC1_CLASH_CHK_INTRP_EN ( BIT(24) ) +#define BIT_AFCDAC2_CLASH_CHK_INTRP_EN ( BIT(23) ) +#define BIT_AFCDAC1_CLASH_CHK_INTRP_EN ( BIT(22) ) +#define BIT_ADA3_TX_CLASH_CHK_INTRP_EN ( BIT(21) ) +#define BIT_ADA3_RX_CLASH_CHK_INTRP_EN ( BIT(20) ) +#define BIT_ADA2_TX_CLASH_CHK_INTRP_EN ( BIT(19) ) +#define BIT_ADA2_RX_CLASH_CHK_INTRP_EN ( BIT(18) ) +#define BIT_ADA1_TX_CLASH_CHK_INTRP_EN ( BIT(17) ) +#define BIT_ADA1_RX_CLASH_CHK_INTRP_EN ( BIT(16) ) +#define BIT_CHK_CLASH_STFREE ( BIT(8) ) +#define BIT_CHK_CLASH_CLR ( BIT(7) ) +#define BIT_CHK_CLASH_RTC_SNAP_MODE ( BIT(4) ) +#define BIT_CHK_CLASH_RTC_SNAP_EDGE ( BIT(3) ) +#define BIT_CHK_CLASH_RTC_SNAP_INTRP_TYPE ( BIT(2) ) +#define BIT_CHK_CLASH_RTC_SNAP_INTRP_CLR ( BIT(1) ) +#define BIT_CHK_CLASH_RTC_SNAP_INTRP ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CLASH_SNAP */ +#define BITS_CHK_CLASH_RTC_SNAP_TIME(_X_) (_X_) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CLASH_STATUS1 */ +#define BITS_CHK_CLASH_ADA3_TX_CHANNEL_SEL(_X_) ( (_X_) << 25 & (BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_CHK_CLASH_ADA3_RX_CHANNEL_SEL(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) ) +#define BITS_CHK_CLASH_ADA2_TX_CHANNEL_SEL(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_CHK_CLASH_ADA2_RX_CHANNEL_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_CHK_CLASH_ADA1_TX_CHANNEL_SEL(_X_) ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BITS_CHK_CLASH_ADA1_RX_CHANNEL_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CLASH_STATUS2 */ +#define BITS_CHK_CLASH_APCDAC2_CHANNEL_SEL(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_CHK_CLASH_APCDAC1_CHANNEL_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CHK_CLASH_AFCDAC2_CHANNEL_SEL(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_CHK_CLASH_AFCDAC1_CHANNEL_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CLASH_STATUS3 */ +#define BITS_CHK_CLASH_RFSBI2_CHANNEL_SEL(_X_) ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)) ) +#define BITS_CHK_CLASH_RFSBI1_CHANNEL_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CHK_CLASH_RFMIPI2_CHANNEL_SEL(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_CHK_CLASH_RFMIPI1_CHANNEL_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_EXTRA_CFG0 */ +#define BITS_APT_DCM2_EXTRA_CFG(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_APT_DCM2_ADI_EN ( BIT(23) ) +#define BITS_APT_DCM2_CHANNEL_SSET(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BIT_APT_DCM2_SST ( BIT(19) ) +#define BITS_APT_DCM2_CHANNEL_MASK(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)) ) +#define BITS_APT_DCM1_EXTRA_CFG(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_APT_DCM1_ADI_EN ( BIT(7) ) +#define BITS_APT_DCM1_CHANNEL_SSET(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BIT_APT_DCM1_SST ( BIT(3) ) +#define BITS_APT_DCM1_CHANNEL_MASK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_EXTRA_CFG1 */ +#define BITS_MDAR_EXTRA_CFG1(_X_) ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_MDAR_EXTRA_CFG1_2 ( BIT(12) ) +#define BIT_MDAR_EXTRA_CFG1_1 ( BIT(11) ) +#define BIT_MDAR_EXTRA_CFG1_0 ( BIT(10) ) +#define BITS_MDAR_BB_LDO_REFCTRL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BIT_MDAR_BB_LDO_SLEEP_PD_EN ( BIT(6) ) +#define BIT_MDAR_BB_LDO_FORCE_ON ( BIT(5) ) +#define BIT_MDAR_BB_LDO_FORCE_PD ( BIT(4) ) +#define BIT_MDAR_BB_BG_SLEEP_PD_EN ( BIT(2) ) +#define BIT_MDAR_BB_BG_FORCE_ON ( BIT(1) ) +#define BIT_MDAR_BB_BG_FORCE_PD ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF0 */ +#define BITS_CHK_CLASH_RFCTRL15_CHX_SEL(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) ) +#define BIT_RFCTRL15_CHK_INTRP_EN ( BIT(16) ) +#define BIT_RFCTRL15_RTC_REFRESH ( BIT(12) ) +#define BIT_RFCTRL15_SNAP_REFRESH ( BIT(8) ) +#define BITS_RFCTRL15_SSET(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) ) +#define BITS_RFCTRL15_MASK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF1 */ +#define BITS_RFCTRL15_CH0_SNAP1_RTC_TIME(_X_) (_X_) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF2 */ +#define BITS_RFCTRL15_CH0_SNAP0_RTC_TIME(_X_) (_X_) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF3 */ +#define BITS_RFCTRL15_CH1_SNAP1_RTC_TIME(_X_) (_X_) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF4 */ +#define BITS_RFCTRL15_CH1_SNAP0_RTC_TIME(_X_) (_X_) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF5 */ +#define BITS_RFCTRL15_CH2_SNAP1_RTC_TIME(_X_) (_X_) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF6 */ +#define BITS_RFCTRL15_CH2_SNAP0_RTC_TIME(_X_) (_X_) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG4 */ +#define BITS_RFCTRL_CHANNEL_MASK3(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_RFCTRL_CHANNEL_MASK2(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BITS_RFCTRL_CHANNEL_MASK1(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RFCTRL_CHANNEL_MASK0(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_RFCTRL150_SST(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG5 */ +#define BITS_RFCTRL_CHANNEL_MASK13(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_RFCTRL_CHANNEL_MASK12(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BITS_RFCTRL_CHANNEL_MASK11(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RFCTRL_CHANNEL_MASK10(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_RFCTRL_CHANNEL_MASK9(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) ) +#define BITS_RFCTRL_CHANNEL_MASK8(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_RFCTRL_CHANNEL_MASK7(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_RFCTRL_CHANNEL_MASK6(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_RFCTRL_CHANNEL_MASK5(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_RFCTRL_CHANNEL_MASK4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG6 */ +#define BITS_RFCTRL_CHANNEL_SSET7(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_RFCTRL_CHANNEL_SSET6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BITS_RFCTRL_CHANNEL_SSET5(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RFCTRL_CHANNEL_SSET4(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_RFCTRL_CHANNEL_SSET3(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) ) +#define BITS_RFCTRL_CHANNEL_SSET2(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_RFCTRL_CHANNEL_SSET1(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_RFCTRL_CHANNEL_SSET0(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_RFCTRL_CHANNEL_MASK15(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_RFCTRL_CHANNEL_MASK14(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG7 */ +#define BITS_RFCTRL_CHANNEL_SSET15(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RFCTRL_CHANNEL_SSET14(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_RFCTRL_CHANNEL_SSET13(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) ) +#define BITS_RFCTRL_CHANNEL_SSET12(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_RFCTRL_CHANNEL_SSET11(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_RFCTRL_CHANNEL_SSET10(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_RFCTRL_CHANNEL_SSET9(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_RFCTRL_CHANNEL_SSET8(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG8 */ +#define BITS_RFCTRL_CHANNEL_MASK19(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_RFCTRL_CHANNEL_MASK18(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BITS_RFCTRL_CHANNEL_MASK17(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RFCTRL_CHANNEL_MASK16(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_RFCTRL3130_SST(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) ) +#define BITS_RFCTRL2916_SST(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG9 */ +#define BITS_RFCTRL_CHANNEL_MASK29(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_RFCTRL_CHANNEL_MASK28(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BITS_RFCTRL_CHANNEL_MASK27(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RFCTRL_CHANNEL_MASK26(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_RFCTRL_CHANNEL_MASK25(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) ) +#define BITS_RFCTRL_CHANNEL_MASK24(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_RFCTRL_CHANNEL_MASK23(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_RFCTRL_CHANNEL_MASK22(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_RFCTRL_CHANNEL_MASK21(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_RFCTRL_CHANNEL_MASK20(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG10 */ +#define BITS_RFCTRL_CHANNEL_SSET23(_X_) ( (_X_) << 27 & (BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_RFCTRL_CHANNEL_SSET22(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) ) +#define BITS_RFCTRL_CHANNEL_SSET21(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RFCTRL_CHANNEL_SSET20(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_RFCTRL_CHANNEL_SSET19(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) ) +#define BITS_RFCTRL_CHANNEL_SSET18(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_RFCTRL_CHANNEL_SSET17(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_RFCTRL_CHANNEL_SSET16(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_RFCTRL_CHANNEL_MASK31(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_RFCTRL_CHANNEL_MASK30(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG11 */ +#define BITS_RFCTRL_CHANNEL_SSET31(_X_) ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_RFCTRL_CHANNEL_SSET30(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) ) +#define BITS_RFCTRL_CHANNEL_SSET29(_X_) ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) ) +#define BITS_RFCTRL_CHANNEL_SSET28(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_RFCTRL_CHANNEL_SSET27(_X_) ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_RFCTRL_CHANNEL_SSET26(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) ) +#define BITS_RFCTRL_CHANNEL_SSET25(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) ) +#define BITS_RFCTRL_CHANNEL_SSET24(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG12 */ +#define BITS_RFCTRL_WTGCFGH(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_RFCTRL_WTGCFGL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG13 */ +#define BITS_RFCTRL_GGECFGH(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) ) +#define BITS_RFCTRL_GGECFGL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG14 */ +#define BITS_MDAR_CFG14(_X_) (_X_) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG15 */ +#define BITS_MDAR_ANALOG_BB_RSV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG10 */ +#define BIT_ADC1_IMBP_CLK_SEL_5 ( BIT(21) ) +#define BIT_ADC1_IMBP_CLK_SEL_4 ( BIT(20) ) +#define BIT_ADC1_IMBP_CLK_SEL_3 ( BIT(19) ) +#define BIT_ADC1_IMBP_CLK_SEL_2 ( BIT(18) ) +#define BIT_ADC1_IMBP_CLK_SEL_1 ( BIT(17) ) +#define BIT_ADC1_IMBP_CLK_SEL_0 ( BIT(16) ) +#define BIT_DAC1_IMBP_BYPASS_5 ( BIT(13) ) +#define BIT_DAC1_IMBP_BYPASS_4 ( BIT(12) ) +#define BIT_DAC1_IMBP_BYPASS_3 ( BIT(11) ) +#define BIT_DAC1_IMBP_BYPASS_2 ( BIT(10) ) +#define BIT_DAC1_IMBP_BYPASS_1 ( BIT(9) ) +#define BIT_DAC1_IMBP_BYPASS_0 ( BIT(8) ) +#define BIT_ADC1_IMBP_BYPASS_5 ( BIT(5) ) +#define BIT_ADC1_IMBP_BYPASS_4 ( BIT(4) ) +#define BIT_ADC1_IMBP_BYPASS_3 ( BIT(3) ) +#define BIT_ADC1_IMBP_BYPASS_2 ( BIT(2) ) +#define BIT_ADC1_IMBP_BYPASS_1 ( BIT(1) ) +#define BIT_ADC1_IMBP_BYPASS_0 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG11 */ +#define BITS_ADC1_BAL_B(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_ADC1_BAL_A(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG12 */ +#define BITS_ADC1_BAL_D(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_ADC1_BAL_C(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG13 */ +#define BITS_DAC1_BAL_B(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_DAC1_BAL_A(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG14 */ +#define BITS_DAC1_BAL_D(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_DAC1_BAL_C(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG20 */ +#define BIT_ADC2_IMBP_CLK_SEL_5 ( BIT(21) ) +#define BIT_ADC2_IMBP_CLK_SEL_4 ( BIT(20) ) +#define BIT_ADC2_IMBP_CLK_SEL_3 ( BIT(19) ) +#define BIT_ADC2_IMBP_CLK_SEL_2 ( BIT(18) ) +#define BIT_ADC2_IMBP_CLK_SEL_1 ( BIT(17) ) +#define BIT_ADC2_IMBP_CLK_SEL_0 ( BIT(16) ) +#define BIT_DAC2_IMBP_BYPASS_5 ( BIT(13) ) +#define BIT_DAC2_IMBP_BYPASS_4 ( BIT(12) ) +#define BIT_DAC2_IMBP_BYPASS_3 ( BIT(11) ) +#define BIT_DAC2_IMBP_BYPASS_2 ( BIT(10) ) +#define BIT_DAC2_IMBP_BYPASS_1 ( BIT(9) ) +#define BIT_DAC2_IMBP_BYPASS_0 ( BIT(8) ) +#define BIT_ADC2_IMBP_BYPASS_5 ( BIT(5) ) +#define BIT_ADC2_IMBP_BYPASS_4 ( BIT(4) ) +#define BIT_ADC2_IMBP_BYPASS_3 ( BIT(3) ) +#define BIT_ADC2_IMBP_BYPASS_2 ( BIT(2) ) +#define BIT_ADC2_IMBP_BYPASS_1 ( BIT(1) ) +#define BIT_ADC2_IMBP_BYPASS_0 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG21 */ +#define BITS_ADC2_BAL_B(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_ADC2_BAL_A(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG22 */ +#define BITS_ADC2_BAL_D(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_ADC2_BAL_C(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG23 */ +#define BITS_DAC2_BAL_B(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_DAC2_BAL_A(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG24 */ +#define BITS_DAC2_BAL_D(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_DAC2_BAL_C(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG30 */ +#define BIT_ADC3_IMBP_CLK_SEL_5 ( BIT(21) ) +#define BIT_ADC3_IMBP_CLK_SEL_4 ( BIT(20) ) +#define BIT_ADC3_IMBP_CLK_SEL_3 ( BIT(19) ) +#define BIT_ADC3_IMBP_CLK_SEL_2 ( BIT(18) ) +#define BIT_ADC3_IMBP_CLK_SEL_1 ( BIT(17) ) +#define BIT_ADC3_IMBP_CLK_SEL_0 ( BIT(16) ) +#define BIT_DAC3_IMBP_BYPASS_5 ( BIT(13) ) +#define BIT_DAC3_IMBP_BYPASS_4 ( BIT(12) ) +#define BIT_DAC3_IMBP_BYPASS_3 ( BIT(11) ) +#define BIT_DAC3_IMBP_BYPASS_2 ( BIT(10) ) +#define BIT_DAC3_IMBP_BYPASS_1 ( BIT(9) ) +#define BIT_DAC3_IMBP_BYPASS_0 ( BIT(8) ) +#define BIT_ADC3_IMBP_BYPASS_5 ( BIT(5) ) +#define BIT_ADC3_IMBP_BYPASS_4 ( BIT(4) ) +#define BIT_ADC3_IMBP_BYPASS_3 ( BIT(3) ) +#define BIT_ADC3_IMBP_BYPASS_2 ( BIT(2) ) +#define BIT_ADC3_IMBP_BYPASS_1 ( BIT(1) ) +#define BIT_ADC3_IMBP_BYPASS_0 ( BIT(0) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG31 */ +#define BITS_ADC3_BAL_B(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_ADC3_BAL_A(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG32 */ +#define BITS_ADC3_BAL_D(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_ADC3_BAL_C(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG33 */ +#define BITS_DAC3_BAL_B(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_DAC3_BAL_A(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG34 */ +#define BITS_DAC3_BAL_D(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) ) +#define BITS_DAC3_BAL_C(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) ) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_mm_ahb_rf.h b/include/soc/sprd/chip_x35lt8/__regs_mm_ahb_rf.h new file mode 100644 index 00000000..a4d01e30 --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_mm_ahb_rf.h @@ -0,0 +1,111 @@ +/* the head file modifier: g 2015-03-19 17:13:17*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_MM_AHB_RF_HEADFILE_H__ +#define __H_REGS_MM_AHB_RF_HEADFILE_H__ __FILE__ + +#define REGS_MM_AHB_RF + +/* registers definitions for MM_AHB_RF */ +#define REG_MM_AHB_AHB_EB SCI_ADDR(REGS_MM_AHB_BASE, 0x0000)/*AHB_EB*/ +#define REG_MM_AHB_AHB_RST SCI_ADDR(REGS_MM_AHB_BASE, 0x0004)/*AHB_RST*/ +#define REG_MM_AHB_GEN_CKG_CFG SCI_ADDR(REGS_MM_AHB_BASE, 0x0008)/*GEN_CKG_CFG*/ +#define REG_MM_AHB_MIPI_CSI2_CTRL SCI_ADDR(REGS_MM_AHB_BASE, 0x000C)/*MIPI_CSI2_CTRL*/ +#define REG_MM_AHB_MM_QOS_CFG0 SCI_ADDR(REGS_MM_AHB_BASE, 0x0010)/*MM_QOS_CFG0*/ +#define REG_MM_AHB_MM_QOS_CFG1 SCI_ADDR(REGS_MM_AHB_BASE, 0x0014)/*MM_QOS_CFG1*/ +#define REG_MM_AHB_RF_AHB_EB REG_MM_AHB_AHB_EB +#define REG_MM_AHB_RF_AHB_RST REG_MM_AHB_AHB_RST +#define REG_MM_AHB_RF_GEN_CKG_CFG REG_MM_AHB_GEN_CKG_CFG +#define REG_MM_AHB_RF_MIPI_CSI2_CTRL REG_MM_AHB_MIPI_CSI2_CTRL +#define REG_MM_AHB_RF_MM_QOS_CFG REG_MM_AHB_MM_QOS_CFG0 + + + +/* bits definitions for register REG_MM_AHB_AHB_EB */ +#define BIT_VPP_EB ( BIT(8) ) +#define BIT_MMU_EB ( BIT(7) ) +#define BIT_CKG_EB ( BIT(6) ) +#define BIT_MM_CKG_EB BIT_CKG_EB +#define BIT_JPG_EB ( BIT(5) ) +#define BIT_CSI_EB ( BIT(4) ) +#define BIT_VSP_EB ( BIT(3) ) +#define BIT_ISP_EB ( BIT(2) ) +#define BIT_CCIR_EB ( BIT(1) ) +#define BIT_DCAM_EB ( BIT(0) ) + +/* bits definitions for register REG_MM_AHB_AHB_RST */ +#define BIT_VPP_SOFT_RST ( BIT(15) ) +#define BIT_MMU_SOFT_RST ( BIT(14) ) +#define BIT_CKG_SOFT_RST ( BIT(13) ) +#define BIT_MM_CKG_SOFT_RST BIT_CKG_SOFT_RST +#define BIT_MM_MTX_SOFT_RST ( BIT(12) ) +#define BIT_OR1200_SOFT_RST ( BIT(11) ) +#define BIT_ROT_SOFT_RST ( BIT(10) ) +#define BIT_CAM2_SOFT_RST ( BIT(9) ) +#define BIT_CAM1_SOFT_RST ( BIT(8) ) +#define BIT_CAM0_SOFT_RST ( BIT(7) ) +#define BIT_JPG_SOFT_RST ( BIT(6) ) +#define BIT_CSI_SOFT_RST ( BIT(5) ) +#define BIT_VSP_SOFT_RST ( BIT(4) ) +#define BIT_ISP_CFG_SOFT_RST ( BIT(3) ) +#define BIT_ISP_LOG_SOFT_RST ( BIT(2) ) +#define BIT_CCIR_SOFT_RST ( BIT(1) ) +#define BIT_DCAM_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_MM_AHB_GEN_CKG_CFG */ +#define BIT_VPP_AXI_CKG_EN ( BIT(9) ) +#define BIT_MM_MTX_AXI_CKG_EN ( BIT(8) ) +#define BIT_MM_AXI_CKG_EN ( BIT(7) ) +#define BIT_JPG_AXI_CKG_EN ( BIT(6) ) +#define BIT_VSP_AXI_CKG_EN ( BIT(5) ) +#define BIT_ISP_AXI_CKG_EN ( BIT(4) ) +#define BIT_DCAM_AXI_CKG_EN ( BIT(3) ) +#define BIT_SENSOR_CKG_EN ( BIT(2) ) +#define BIT_MIPI_CSI_CKG_EN ( BIT(1) ) +#define BIT_CPHY_CFG_CKG_EN ( BIT(0) ) + +/* bits definitions for register REG_MM_AHB_MIPI_CSI2_CTRL */ +#define BITS_MIPI_CPHY_SAMPLE_SEL(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)) ) +#define BIT_MIPI_CPHY_SYNC_MODE ( BIT(2) ) +#define BIT_MIPI_CPHY_TEST_CTL ( BIT(1) ) +#define BIT_MIPI_CPHY_SEL ( BIT(0) ) + +/* bits definitions for register REG_MM_AHB_MM_QOS_CFG0 */ +#define BITS_QOS_R_DCAM(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_QOS_W_DCAM(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_QOS_R_JPG(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_QOS_W_JPG(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_QOS_R_ISP(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_QOS_W_ISP(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_QOS_R_VSP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_QOS_W_VSP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_MM_QOS_CFG1 */ +#define BITS_QOS_R_VPP(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_QOS_W_VPP(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_QOS_R_CODEC(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_QOS_W_CODEC(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_mm_clk.h b/include/soc/sprd/chip_x35lt8/__regs_mm_clk.h new file mode 100644 index 00000000..3e6f4e45 --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_mm_clk.h @@ -0,0 +1,69 @@ +/* the head file modifier: g 2015-03-19 15:48:44*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_MM_CLK_RF_HEADFILE_H__ +#define __H_REGS_MM_CLK_RF_HEADFILE_H__ + +#define REGS_MM_CLK + +/* registers definitions for controller REGS_MM_CLK */ +#define REG_MM_CLK_MM_AHB_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0020) +#define REG_MM_CLK_SENSOR_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0024) +#define REG_MM_CLK_CCIR_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0028) +#define REG_MM_CLK_DCAM_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x002c) +#define REG_MM_CLK_VSP_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0030) +#define REG_MM_CLK_ISP_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0034) +#define REG_MM_CLK_JPG_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0038) +#define REG_MM_CLK_MIPI_CSI_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x003c) + + + +/* bits definitions for register REG_MM_AHB_RF_clk_mm_ahb_cfg */ +#define BITS_CLK_MM_AHB_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_MM_AHB_RF_clk_sensor_cfg */ +#define BITS_CLK_SENSOR_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_SENSOR_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_MM_AHB_RF_clk_ccir_cfg */ +#define BIT_CLK_CCIR_PAD_SEL ( BIT(16) ) +#define BIT_CLK_CCIR_SEL ( BIT(0) ) + +/* bits definitions for register REG_MM_AHB_RF_clk_dcam_cfg */ +#define BITS_CLK_DCAM_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_MM_AHB_RF_clk_vsp_cfg */ +#define BITS_CLK_VSP_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_MM_AHB_RF_clk_isp_cfg */ +#define BITS_CLK_ISP_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_MM_AHB_RF_clk_jpg_cfg */ +#define BITS_CLK_JPG_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_MM_AHB_RF_clk_vpp_cfg */ +#define BITS_CLK_VPP_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_pinmap.h b/include/soc/sprd/chip_x35lt8/__regs_pinmap.h new file mode 100755 index 00000000..be98c3a0 --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_pinmap.h @@ -0,0 +1,283 @@ +#ifndef __ASM_ARM_ARCH_PINMAP_H +#error "Don't include this file directly, Pls include pinmap.h" +#endif + +#ifndef _REGS_PINMAP_H_ +#define _REGS_PINMAP_H_ + +#define CTL_PIN_BASE ( SPRD_PIN_BASE ) + +/* registers definitions for controller CTL_PIN */ +#define REG_PIN_CTRL0 ( 0x0000 ) +#define REG_PIN_CTRL1 ( 0x0004 ) +#define REG_PIN_CTRL2 ( 0x0008 ) +#define REG_PIN_CTRL3 ( 0x000c ) +#define REG_PIN_CTRL4 ( 0x0010 ) +#define REG_PIN_CTRL5 ( 0x0014 ) +#define REG_PIN_SIMCLK0 ( 0x0018 ) +#define REG_PIN_SIMDA0 ( 0x001c ) +#define REG_PIN_SIMRST0 ( 0x0020 ) +#define REG_PIN_SIMCLK1 ( 0x0024 ) +#define REG_PIN_SIMDA1 ( 0x0028 ) +#define REG_PIN_SIMRST1 ( 0x002c ) +#define REG_PIN_SD0_CLK ( 0x0030 ) +#define REG_PIN_SD0_CMD ( 0x0034 ) +#define REG_PIN_SD0_D0 ( 0x0038 ) +#define REG_PIN_SD0_D1 ( 0x003c ) +#define REG_PIN_SD0_D2 ( 0x0040 ) +#define REG_PIN_SD0_D3 ( 0x0044 ) +#define REG_PIN_ANA_INT ( 0x0048 ) +#define REG_PIN_EXT_RST_B ( 0x004c ) +#define REG_PIN_CLK_26M ( 0x0050 ) +#define REG_PIN_CHIP_SLEEP ( 0x0054 ) +#define REG_PIN_XTL_BUF_EN ( 0x0058 ) +#define REG_PIN_CLK_32K ( 0x005c ) +#define REG_PIN_AUD_SCLK ( 0x0060 ) +#define REG_PIN_AUD_ADD0 ( 0x0064 ) +#define REG_PIN_AUD_ADSYNC ( 0x0068 ) +#define REG_PIN_AUD_DAD1 ( 0x006c ) +#define REG_PIN_AUD_DAD0 ( 0x0070 ) +#define REG_PIN_AUD_DASYNC ( 0x0074 ) +#define REG_PIN_TD_TXPD ( 0x0078 ) +#define REG_PIN_TD_RXPD ( 0x007c ) +#define REG_PIN_GSM_TXPD ( 0x0080 ) +#define REG_PIN_GSM_RXPD ( 0x0084 ) +#define REG_PIN_TD_RX_CLK ( 0x0088 ) +#define REG_PIN_ADI_D ( 0x008c ) +#define REG_PIN_ADI_SYNC ( 0x0090 ) +#define REG_PIN_ADI_SCLK ( 0x0094 ) +#define REG_PIN_ANA_INT2 ( 0x0098 ) +#define REG_PIN_COM_TX_APCD ( 0x009c ) +#define REG_PIN_COM_TX_DQ1 ( 0x00a0 ) +#define REG_PIN_COM_TX_DQ0 ( 0x00a4 ) +#define REG_PIN_COM_TX_DI1 ( 0x00a8 ) +#define REG_PIN_COM_TX_DI0 ( 0x00ac ) +#define REG_PIN_COM_TX_SYNC ( 0x00b0 ) +#define REG_PIN_COM_TX_SCLK ( 0x00b4 ) +#define REG_PIN_COM_RX_DQ1 ( 0x00b8 ) +#define REG_PIN_COM_RX_DQ0 ( 0x00bc ) +#define REG_PIN_COM_RX_DI1 ( 0x00c0 ) +#define REG_PIN_COM_RX_DI0 ( 0x00c4 ) +#define REG_PIN_COM_RX_SYNC ( 0x00c8 ) +#define REG_PIN_COM_RX_SCLK ( 0x00cc ) +#define REG_PIN_CCIRCK ( 0x00d0 ) +#define REG_PIN_CCIRMCLK ( 0x00d4 ) +#define REG_PIN_CCIRHS ( 0x00d8 ) +#define REG_PIN_CCIRVS ( 0x00dc ) +#define REG_PIN_CCIRD0 ( 0x00e0 ) +#define REG_PIN_CCIRD1 ( 0x00e4 ) +#define REG_PIN_CCIRD2 ( 0x00e8 ) +#define REG_PIN_CCIRD3 ( 0x00ec ) +#define REG_PIN_CCIRD4 ( 0x00f0 ) +#define REG_PIN_CCIRD5 ( 0x00f4 ) +#define REG_PIN_CCIRD6 ( 0x00f8 ) +#define REG_PIN_CCIRD7 ( 0x00fc ) +#define REG_PIN_CCIRD8 ( 0x0100 ) +#define REG_PIN_CCIRD9 ( 0x0104 ) +#define REG_PIN_CCIRRST ( 0x0108 ) +#define REG_PIN_CCIRPD1 ( 0x010c ) +#define REG_PIN_CCIRPD0 ( 0x0110 ) +#define REG_PIN_SCL1 ( 0x0114 ) +#define REG_PIN_SDA1 ( 0x0118 ) +#define REG_PIN_KEYOUT0 ( 0x011c ) +#define REG_PIN_KEYOUT1 ( 0x0120 ) +#define REG_PIN_KEYOUT2 ( 0x0124 ) +#define REG_PIN_KEYOUT3 ( 0x0128 ) +#define REG_PIN_KEYOUT4 ( 0x012c ) +#define REG_PIN_KEYOUT5 ( 0x0130 ) +#define REG_PIN_GPIO135 ( 0x0134 ) +#define REG_PIN_GPIO136 ( 0x0138 ) +#define REG_PIN_GPIO137 ( 0x013c ) +#define REG_PIN_GPIO138 ( 0x0140 ) +#define REG_PIN_GPIO139 ( 0x0144 ) +#define REG_PIN_GPIO140 ( 0x0148 ) +#define REG_PIN_KEYOUT6 ( 0x014c ) +#define REG_PIN_KEYOUT7 ( 0x0150 ) +#define REG_PIN_KEYIN0 ( 0x0154 ) +#define REG_PIN_KEYIN1 ( 0x0158 ) +#define REG_PIN_KEYIN2 ( 0x015c ) +#define REG_PIN_KEYIN3 ( 0x0160 ) +#define REG_PIN_KEYIN4 ( 0x0164 ) +#define REG_PIN_KEYIN5 ( 0x0168 ) +#define REG_PIN_KEYIN6 ( 0x016c ) +#define REG_PIN_KEYIN7 ( 0x0170 ) +#define REG_PIN_NFWPN ( 0x0174 ) +#define REG_PIN_NFRB ( 0x0178 ) +#define REG_PIN_NFCLE ( 0x017c ) +#define REG_PIN_NFALE ( 0x0180 ) +#define REG_PIN_NFCEN ( 0x0184 ) +#define REG_PIN_NFREN ( 0x0188 ) +#define REG_PIN_NFWEN ( 0x018c ) +#define REG_PIN_NFD0 ( 0x0190 ) +#define REG_PIN_NFD1 ( 0x0194 ) +#define REG_PIN_NFD2 ( 0x0198 ) +#define REG_PIN_NFD3 ( 0x019c ) +#define REG_PIN_NFD4 ( 0x01a0 ) +#define REG_PIN_NFD5 ( 0x01a4 ) +#define REG_PIN_NFD6 ( 0x01a8 ) +#define REG_PIN_NFD7 ( 0x01ac ) +#define REG_PIN_NFD8 ( 0x01b0 ) +#define REG_PIN_NFD9 ( 0x01b4 ) +#define REG_PIN_NFD10 ( 0x01b8 ) +#define REG_PIN_NFD11 ( 0x01bc ) +#define REG_PIN_NFD12 ( 0x01c0 ) +#define REG_PIN_NFD13 ( 0x01c4 ) +#define REG_PIN_NFD14 ( 0x01c8 ) +#define REG_PIN_NFD15 ( 0x01cc ) +#define REG_PIN_SD3_CLK ( 0x01d0 ) +#define REG_PIN_SD3_CMD ( 0x01d4 ) +#define REG_PIN_SD3_D0 ( 0x01d8 ) +#define REG_PIN_SD3_D1 ( 0x01dc ) +#define REG_PIN_SD3_D2 ( 0x01e0 ) +#define REG_PIN_SD3_D3 ( 0x01e4 ) +#define REG_PIN_SD3_D4 ( 0x01e8 ) +#define REG_PIN_SD3_D5 ( 0x01ec ) +#define REG_PIN_SD3_D6 ( 0x01f0 ) +#define REG_PIN_SD3_D7 ( 0x01f4 ) +#define REG_PIN_EMMC_RST ( 0x01f8 ) +#define REG_PIN_SD1_CLK ( 0x01fc ) +#define REG_PIN_SD1_CMD ( 0x0200 ) +#define REG_PIN_SD1_D0 ( 0x0204 ) +#define REG_PIN_SD1_D1 ( 0x0208 ) +#define REG_PIN_SD1_D2 ( 0x020c ) +#define REG_PIN_SD1_D3 ( 0x0210 ) +#define REG_PIN_LCD_CSN1 ( 0x0214 ) +#define REG_PIN_LCD_RSTN ( 0x0218 ) +#define REG_PIN_LCD_CD ( 0x021c ) +#define REG_PIN_LCD_D0 ( 0x0220 ) +#define REG_PIN_LCD_D1 ( 0x0224 ) +#define REG_PIN_LCD_D2 ( 0x0228 ) +#define REG_PIN_LCD_D3 ( 0x022c ) +#define REG_PIN_LCD_D4 ( 0x0230 ) +#define REG_PIN_LCD_D5 ( 0x0234 ) +#define REG_PIN_LCD_D6 ( 0x0238 ) +#define REG_PIN_LCD_D7 ( 0x023c ) +#define REG_PIN_LCD_D8 ( 0x0240 ) +#define REG_PIN_LCD_WRN ( 0x0244 ) +#define REG_PIN_LCD_RDN ( 0x0248 ) +#define REG_PIN_LCD_CSN0 ( 0x024c ) +#define REG_PIN_LCD_D9 ( 0x0250 ) +#define REG_PIN_LCD_D10 ( 0x0254 ) +#define REG_PIN_LCD_D11 ( 0x0258 ) +#define REG_PIN_LCD_D12 ( 0x025c ) +#define REG_PIN_LCD_D13 ( 0x0260 ) +#define REG_PIN_LCD_D14 ( 0x0264 ) +#define REG_PIN_LCD_D15 ( 0x0268 ) +#define REG_PIN_LCD_D16 ( 0x026c ) +#define REG_PIN_LCD_D17 ( 0x0270 ) +#define REG_PIN_LCD_D18 ( 0x0274 ) +#define REG_PIN_LCD_D19 ( 0x0278 ) +#define REG_PIN_LCD_D20 ( 0x027c ) +#define REG_PIN_LCD_D21 ( 0x0280 ) +#define REG_PIN_LCD_D22 ( 0x0284 ) +#define REG_PIN_LCD_D23 ( 0x0288 ) +#define REG_PIN_LCD_FMARK ( 0x028c ) +#define REG_PIN_SPI2_CSN ( 0x0290 ) +#define REG_PIN_SPI2_DO ( 0x0294 ) +#define REG_PIN_SPI2_DI ( 0x0298 ) +#define REG_PIN_SPI2_CLK ( 0x029c ) +#define REG_PIN_SCL0 ( 0x02a0 ) +#define REG_PIN_SDA0 ( 0x02a4 ) +#define REG_PIN_SCL2 ( 0x02a8 ) +#define REG_PIN_SDA2 ( 0x02ac ) +#define REG_PIN_SCL3 ( 0x02b0 ) +#define REG_PIN_SDA3 ( 0x02b4 ) +#define REG_PIN_CLK_AUX0 ( 0x02b8 ) +#define REG_PIN_IIS0DI ( 0x02bc ) +#define REG_PIN_IIS0DO ( 0x02c0 ) +#define REG_PIN_IIS0CLK ( 0x02c4 ) +#define REG_PIN_IIS0LRCK ( 0x02c8 ) +#define REG_PIN_IIS0MCK ( 0x02cc ) +#define REG_PIN_SPI0_CSN ( 0x02d0 ) +#define REG_PIN_SPI0_DO ( 0x02d4 ) +#define REG_PIN_SPI0_DI ( 0x02d8 ) +#define REG_PIN_SPI0_CLK ( 0x02dc ) +#define REG_PIN_GPIO141 ( 0x02e0 ) +#define REG_PIN_GPIO142 ( 0x02e4 ) +#define REG_PIN_MTDO ( 0x02e8 ) + +#define REG_PIN_MTDI ( 0x02ec ) +#define REG_PIN_MTCK ( 0x02f0 ) +#define REG_PIN_MTMS ( 0x02f4 ) +#define REG_PIN_MTRST_N ( 0x02f8 ) +#define REG_PIN_TRACECLK ( 0x02fc ) +#define REG_PIN_TRACECTRL ( 0x0300 ) +#define REG_PIN_TRACEDAT0 ( 0x0304 ) +#define REG_PIN_TRACEDAT1 ( 0x0308 ) +#define REG_PIN_TRACEDAT2 ( 0x030c ) +#define REG_PIN_TRACEDAT3 ( 0x0310 ) +#define REG_PIN_TRACEDAT4 ( 0x0314 ) +#define REG_PIN_TRACEDAT5 ( 0x0318 ) +#define REG_PIN_TRACEDAT6 ( 0x031c ) +#define REG_PIN_TRACEDAT7 ( 0x0320 ) +#define REG_PIN_U0TXD ( 0x0324 ) +#define REG_PIN_U0RXD ( 0x0328 ) +#define REG_PIN_U0CTS ( 0x032c ) +#define REG_PIN_U0RTS ( 0x0330 ) +#define REG_PIN_U1TXD ( 0x0334 ) +#define REG_PIN_U1RXD ( 0x0338 ) +#define REG_PIN_U2TXD ( 0x033c ) +#define REG_PIN_U2RXD ( 0x0340 ) +#define REG_PIN_U2CTS ( 0x0344 ) +#define REG_PIN_U2RTS ( 0x0348 ) +#define REG_PIN_U3TXD ( 0x034c ) +#define REG_PIN_U3RXD ( 0x0350 ) +#define REG_PIN_U3CTS ( 0x0354 ) +#define REG_PIN_U3RTS ( 0x0358 ) +#define REG_PIN_CLK_REQ1 ( 0x035c ) +#define REG_PIN_CLK_REQ2 ( 0x0360 ) +#define REG_PIN_RFSDA0 ( 0x0364 ) +#define REG_PIN_RFSCK0 ( 0x0368 ) +#define REG_PIN_RFSEN0 ( 0x036c ) +#define REG_PIN_RFCTL0 ( 0x0370 ) +#define REG_PIN_RFCTL1 ( 0x0374 ) +#define REG_PIN_RFCTL2 ( 0x0378 ) +#define REG_PIN_RFCTL3 ( 0x037c ) + +#define REG_PIN_RFCTL4 ( 0x0380 ) +#define REG_PIN_RFCTL5 ( 0x0384 ) +#define REG_PIN_RFCTL6 ( 0x0388 ) +#define REG_PIN_RFCTL7 ( 0x038c ) +#define REG_PIN_RFCTL8 ( 0x0390 ) +#define REG_PIN_RFCTL9 ( 0x0394 ) +#define REG_PIN_RFCTL10 ( 0x0398 ) +#define REG_PIN_RFCTL11 ( 0x039c ) +#define REG_PIN_RFCTL12 ( 0x03a0 ) +#define REG_PIN_RFCTL13 ( 0x03a4 ) +#define REG_PIN_RFCTL14 ( 0x03a8 ) +#define REG_PIN_RFCTL15 ( 0x03ac ) +#define REG_PIN_XTL_EN ( 0x03b0 ) +#define REG_PIN_PTEST ( 0x03b4 ) +#define REG_PIN_GPIO143 ( 0x03b8 ) +#define REG_PIN_GPIO144 ( 0x03bc ) + + +/* bits definitions for register REG_PIN_XXX */ +#define BITS_PIN_DS(_x_) ( (_x_) << 19 & (BIT(19)|BIT(20)) ) +#define BITS_PIN_DS_3(_x_) ( (_x_) << 19 & (BIT(19)|BIT(20)|BIT(21)) ) +#define BITS_PIN_DS_4(_x_) ( (_x_) << 19 & (BIT(19)|BIT(20)|BIT(21)|BIT(22)) ) +#define BIT_PIN_SLP_AP ( BIT(13) ) +#define BIT_PIN_WPU ( BIT(7) ) +#define BIT_PIN_WPD ( BIT(6) ) +#define BITS_PIN_AF(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) ) +#define BIT_PIN_SLP_WPU ( BIT(3) ) +#define BIT_PIN_SLP_WPD ( BIT(2) ) +#define BIT_PIN_SLP_IE ( BIT(1) ) +#define BIT_PIN_SLP_OE ( BIT(0) ) + +/* vars definitions for controller CTL_PIN */ +#define BIT_PIN_NUL ( 0 ) +#define BIT_PIN_SLP_NUL ( 0 ) +#define BIT_PIN_SLP_Z ( 0 ) + + + + + + + + + + + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_pmu_apb_rf.h b/include/soc/sprd/chip_x35lt8/__regs_pmu_apb_rf.h new file mode 100755 index 00000000..02a30989 --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_pmu_apb_rf.h @@ -0,0 +1,1176 @@ +/* the head file modifier: g 2015-03-19 15:49:17*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +//#ifndef __SCI_GLB_REGS_H__ +//#error "Don't include this file directly, Pls include sci_glb_regs.h" +//#endif + + + + +#ifndef __H_REGS_PMU_APB_RF_HEADFILE_H__ +#define __H_REGS_PMU_APB_RF_HEADFILE_H__ __FILE__ + +#define REGS_PMU_APB_RF + +/* registers definitions for MM_AHB_RF */ +#define REG_PMU_APB_PD_CA53_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0000)/*PD_CA53_TOP_CFG*/ +#define REG_PMU_APB_PD_CA53_LIT_C0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0004)/*PD_CA53_LIT_C0_CFG*/ +#define REG_PMU_APB_PD_CA53_LIT_C1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0008)/*PD_CA53_LIT_C1_CFG*/ +#define REG_PMU_APB_PD_CA53_LIT_C2_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x000C)/*PD_CA53_LIT_C2_CFG*/ +#define REG_PMU_APB_PD_CA53_LIT_C3_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0010)/*PD_CA53_LIT_C3_CFG*/ +#define REG_PMU_APB_PD_CA53_LIT_MP4_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0014)/*PD_CA53_LIT_MP4_CFG*/ +#define REG_PMU_APB_PD_APCPU_TOP_CFG REG_PMU_APB_PD_CA53_TOP_CFG +#define REG_PMU_APB_PD_APCPU_LIT_C0_CFG REG_PMU_APB_PD_CA53_LIT_C0_CFG +#define REG_PMU_APB_PD_APCPU_LIT_C1_CFG REG_PMU_APB_PD_CA53_LIT_C1_CFG +#define REG_PMU_APB_PD_APCPU_LIT_C2_CFG REG_PMU_APB_PD_CA53_LIT_C2_CFG +#define REG_PMU_APB_PD_APCPU_LIT_C3_CFG REG_PMU_APB_PD_CA53_LIT_C3_CFG +#define REG_PMU_APB_PD_APCPU_LIT_MP4_CFG REG_PMU_APB_PD_CA53_LIT_MP4_CFG +#define REG_PMU_APB_PD_AP_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0018)/*PD_AP_SYS_CFG*/ +#define REG_PMU_APB_PD_MM_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x001C)/*PD_MM_TOP_CFG*/ +#define REG_PMU_APB_PD_GPU_TOP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0020)/*PD_GPU_TOP_CFG*/ +#define REG_PMU_APB_PD_CP0_ARM9_0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0024)/*PD_CP0_ARM9_0_CFG*/ +#define REG_PMU_APB_PD_CP0_ARM9_1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0028)/*PD_CP0_ARM9_1_CFG*/ +#define REG_PMU_APB_PD_CP0_HU3GE_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x002C)/*PD_CP0_HU3GE_CFG*/ +#define REG_PMU_APB_PD_CP0_GSM_0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0030)/*PD_CP0_GSM_0_CFG*/ +#define REG_PMU_APB_PD_CP0_GSM_1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0034)/*PD_CP0_GSM_1_CFG*/ +#define REG_PMU_APB_PD_CP0_TD_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0038)/*PD_CP0_TD_CFG*/ +#define REG_PMU_APB_PD_CP0_CEVA_0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x003C)/*PD_CP0_CEVA_0_CFG*/ +#define REG_PMU_APB_PD_CP0_CEVA_1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0040)/*PD_CP0_CEVA_1_CFG*/ +#define REG_PMU_APB_PD_MM_CODEC_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0044)/*PD_MM_CODEC_CFG*/ +#define REG_PMU_APB_PD_CP1_CA5_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0048)/*PD_CP1_CA5_CFG*/ +#define REG_PMU_APB_PD_CP1_LTE_P1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x004C)/*PD_CP1_LTE_P1_CFG*/ +#define REG_PMU_APB_PD_CP1_LTE_P2_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0050)/*PD_CP1_LTE_P2_CFG*/ +#define REG_PMU_APB_PD_CP1_CEVA_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0054)/*PD_CP1_CEVA_CFG*/ +#define REG_PMU_APB_PD_CP1_COMWRAP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0058)/*PD_CP1_COMWRAP_CFG*/ +#define REG_PMU_APB_PD_PUB_SYS_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x005C)/*PD_PUB_SYS_CFG*/ +#define REG_PMU_APB_AP_WAKEUP_POR_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0060)/*AP_WAKEUP_POR_CFG*/ +#define REG_PMU_APB_PD_GPU_C0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0064)/*PD_GPU_C0_CFG*/ +#define REG_PMU_APB_PD_GPU_C1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0068)/*PD_GPU_C1_CFG*/ +#define REG_PMU_APB_XTL_WAIT_CNT SCI_ADDR(REGS_PMU_APB_BASE, 0x0070)/*XTL_WAIT_CNT*/ +#define REG_PMU_APB_XTLBUF_WAIT_CNT SCI_ADDR(REGS_PMU_APB_BASE, 0x0074)/*XTLBUF_WAIT_CNT*/ +#define REG_PMU_APB_PLL_WAIT_CNT1 SCI_ADDR(REGS_PMU_APB_BASE, 0x0078)/*PLL_WAIT_CNT1*/ +#define REG_PMU_APB_PLL_WAIT_CNT2 SCI_ADDR(REGS_PMU_APB_BASE, 0x007C)/*PLL_WAIT_CNT2*/ +#define REG_PMU_APB_XTL0_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0080)/*XTL0_REL_CFG*/ +#define REG_PMU_APB_XTL1_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0084)/*XTL1_REL_CFG*/ +#define REG_PMU_APB_PLL_PD_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0088)/*PLL_PD_CFG*/ +#define REG_PMU_APB_XTLBUF0_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x008C)/*XTLBUF0_REL_CFG*/ +#define REG_PMU_APB_XTLBUF1_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0090)/*XTLBUF1_REL_CFG*/ +#define REG_PMU_APB_MPLL0_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0094)/*MPLL0_REL_CFG*/ +#define REG_PMU_APB_DPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0098)/*DPLL_REL_CFG*/ +#define REG_PMU_APB_LTEPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x009C)/*LTEPLL_REL_CFG*/ +#define REG_PMU_APB_TWPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00A0)/*TWPLL_REL_CFG*/ +#define REG_PMU_APB_LVDSDIS_PLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00A4)/*LVDSDIS_PLL_REL_CFG*/ +#define REG_PMU_APB_MPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00A8)/*MPLL_REL_CFG*/ +#define REG_PMU_APB_GPLL_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x00AC)/*GPLL_REL_CFG*/ +#define REG_PMU_APB_CP_SOFT_RST SCI_ADDR(REGS_PMU_APB_BASE, 0x00B0)/*CP_SOFT_RST*/ +#define REG_PMU_APB_CP_SLP_STATUS_DBG0 SCI_ADDR(REGS_PMU_APB_BASE, 0x00B4)/*CP_SLP_STATUS_DBG0*/ +#define REG_PMU_APB_PWR_STATUS0_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00BC)/*PWR_STATUS0_DBG*/ +#define REG_PMU_APB_PWR_STATUS1_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00C0)/*PWR_STATUS1_DBG*/ +#define REG_PMU_APB_PWR_STATUS2_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00C4)/*PWR_STATUS2_DBG*/ +#define REG_PMU_APB_PWR_STATUS3_DBG SCI_ADDR(REGS_PMU_APB_BASE, 0x00C8)/*PWR_STATUS3_DBG*/ +#define REG_PMU_APB_SLEEP_CTRL SCI_ADDR(REGS_PMU_APB_BASE, 0x00CC)/*SLEEP_CTRL*/ +#define REG_PMU_APB_DDR_SLEEP_CTRL SCI_ADDR(REGS_PMU_APB_BASE, 0x00D0)/*DDR_SLEEP_CTRL*/ +#define REG_PMU_APB_SLEEP_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x00D4)/*SLEEP_STATUS*/ +#define REG_PMU_APB_DDR_CHN_SLEEP_CTRL0 SCI_ADDR(REGS_PMU_APB_BASE, 0x00F8)/*DDR_CHN_SLEEP_CTRL0*/ +#define REG_PMU_APB_DDR_CHN_SLEEP_CTRL1 SCI_ADDR(REGS_PMU_APB_BASE, 0x00FC)/*DDR_CHN_SLEEP_CTRL1*/ +#define REG_PMU_APB_PD_CA53_BIG_C0_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0100)/*PD_CA53_BIG_C0_CFG*/ +#define REG_PMU_APB_PD_CA53_BIG_C1_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0104)/*PD_CA53_BIG_C1_CFG*/ +#define REG_PMU_APB_PD_CA53_BIG_C2_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0108)/*PD_CA53_BIG_C2_CFG*/ +#define REG_PMU_APB_PD_CA53_BIG_C3_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x010C)/*PD_CA53_BIG_C3_CFG*/ +#define REG_PMU_APB_PD_CA53_BIG_MP4_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0110)/*PD_CA53_BIG_MP4_CFG*/ +#define REG_PMU_APB_PD_APCPU_BIG_C0_CFG REG_PMU_APB_PD_CA53_BIG_C0_CFG +#define REG_PMU_APB_PD_APCPU_BIG_C1_CFG REG_PMU_APB_PD_CA53_BIG_C1_CFG +#define REG_PMU_APB_PD_APCPU_BIG_C2_CFG REG_PMU_APB_PD_CA53_BIG_C2_CFG +#define REG_PMU_APB_PD_APCPU_BIG_C3_CFG REG_PMU_APB_PD_CA53_BIG_C3_CFG +#define REG_PMU_APB_PD_APCPU_BIG_MP4_CFG REG_PMU_APB_PD_CA53_BIG_MP4_CFG +#define REG_PMU_APB_DDR_OP_MODE_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x012C)/*DDR_OP_MODE_CFG*/ +#define REG_PMU_APB_DDR_PHY_RET_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0130)/*DDR_PHY_RET_CFG*/ +#define REG_PMU_APB_26M_SEL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0134)/*26M_SEL_CFG*/ +#define REG_PMU_APB_R26M_SEL_CFG REG_PMU_APB_26M_SEL_CFG +#define REG_PMU_APB_BISR_DONE_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x0138)/*BISR_DONE_STATUS*/ +#define REG_PMU_APB_BISR_BUSY_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x013C)/*BISR_BUSY_STATUS*/ +#define REG_PMU_APB_BISR_BYP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0140)/*BISR_BYP_CFG*/ +#define REG_PMU_APB_BISR_EN_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0144)/*BISR_EN_CFG*/ +#define REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG0 SCI_ADDR(REGS_PMU_APB_BASE, 0x0148)/*CGM_AUTO_GATE_SEL_CFG0*/ +#define REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG1 SCI_ADDR(REGS_PMU_APB_BASE, 0x014C)/*CGM_AUTO_GATE_SEL_CFG1*/ +#define REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG2 SCI_ADDR(REGS_PMU_APB_BASE, 0x0150)/*CGM_AUTO_GATE_SEL_CFG2*/ +#define REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG3 SCI_ADDR(REGS_PMU_APB_BASE, 0x0154)/*CGM_AUTO_GATE_SEL_CFG3*/ +#define REG_PMU_APB_CGM_FORCE_EN_CFG0 SCI_ADDR(REGS_PMU_APB_BASE, 0x0158)/*CGM_FORCE_EN_CFG0*/ +#define REG_PMU_APB_CGM_FORCE_EN_CFG1 SCI_ADDR(REGS_PMU_APB_BASE, 0x015C)/*CGM_FORCE_EN_CFG1*/ +#define REG_PMU_APB_CGM_FORCE_EN_CFG2 SCI_ADDR(REGS_PMU_APB_BASE, 0x0160)/*CGM_FORCE_EN_CFG2*/ +#define REG_PMU_APB_CGM_FORCE_EN_CFG3 SCI_ADDR(REGS_PMU_APB_BASE, 0x0164)/*CGM_FORCE_EN_CFG3*/ +#define REG_PMU_APB_SLEEP_XTLON_CTRL SCI_ADDR(REGS_PMU_APB_BASE, 0x0168)/*SLEEP_XTLON_CTRL*/ +#define REG_PMU_APB_MEM_SLP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x016C)/*MEM_SLP_CFG*/ +#define REG_PMU_APB_MEM_SD_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0170)/*MEM_SD_CFG*/ +#define REG_PMU_APB_APCPU_CORE_PU_LOCK SCI_ADDR(REGS_PMU_APB_BASE, 0x0174)/*APCPU_CORE_PU_LOCK*/ +#define REG_PMU_APB_CA7_CORE_PU_LOCK REG_PMU_APB_APCPU_CORE_PU_LOCK +#define REG_PMU_APB_ARM7_HOLD_CGM_EN SCI_ADDR(REGS_PMU_APB_BASE, 0x0178)/*ARM7_HOLD_CGM_EN*/ +#define REG_PMU_APB_PWR_CNT_WAIT_CFG0 SCI_ADDR(REGS_PMU_APB_BASE, 0x017C)/*PWR_CNT_WAIT_CFG0*/ +#define REG_PMU_APB_PWR_CNT_WAIT_CFG1 SCI_ADDR(REGS_PMU_APB_BASE, 0x0180)/*PWR_CNT_WAIT_CFG1*/ +#define REG_PMU_APB_RC0_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0184)/*RC0_REL_CFG*/ +#define REG_PMU_APB_RC1_REL_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0188)/*RC1_REL_CFG*/ +#define REG_PMU_APB_RC_CNT_WAIT_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x018C)/*RC_CNT_WAIT_CFG*/ +#define REG_PMU_APB_MEM_AUTO_SLP_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0190)/*MEM_AUTO_SLP_CFG*/ +#define REG_PMU_APB_MEM_AUTO_SD_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0194)/*MEM_AUTO_SD_CFG*/ +#define REG_PMU_APB_CP0_PD_SHUTDOWN_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x0198)/*CP0_PD_SHUTDOWN_CFG*/ +#define REG_PMU_APB_CP1_PD_SHUTDOWN_CFG SCI_ADDR(REGS_PMU_APB_BASE, 0x019C)/*CP1_PD_SHUTDOWN_CFG*/ +#define REG_PMU_APB_WAKEUP_LOCK_EN0 SCI_ADDR(REGS_PMU_APB_BASE, 0x01A0)/*WAKEUP_LOCK_EN0*/ +#define REG_PMU_APB_WAKEUP_LOCK_EN1 SCI_ADDR(REGS_PMU_APB_BASE, 0x01A4)/*WAKEUP_LOCK_EN1*/ +#define REG_PMU_APB_LP_AUTO_CTRL SCI_ADDR(REGS_PMU_APB_BASE, 0x01A8)/*LP_AUTO_CTRL*/ +#define REG_PMU_APB_CA53_LIT_C0_INT_DISABLE SCI_ADDR(REGS_PMU_APB_BASE, 0x01AC)/*CA53_LIT_C0_INT_DISABLE*/ +#define REG_PMU_APB_CA53_LIT_C1_INT_DISABLE SCI_ADDR(REGS_PMU_APB_BASE, 0x01B0)/*CA53_LIT_C1_INT_DISABLE*/ +#define REG_PMU_APB_CA53_LIT_C2_INT_DISABLE SCI_ADDR(REGS_PMU_APB_BASE, 0x01B4)/*CA53_LIT_C2_INT_DISABLE*/ +#define REG_PMU_APB_CA53_LIT_C3_INT_DISABLE SCI_ADDR(REGS_PMU_APB_BASE, 0x01B8)/*CA53_LIT_C3_INT_DISABLE*/ +#define REG_PMU_APB_CA53_BIG_C0_INT_DISABLE SCI_ADDR(REGS_PMU_APB_BASE, 0x01BC)/*CA53_BIG_C0_INT_DISABLE*/ +#define REG_PMU_APB_CA53_BIG_C1_INT_DISABLE SCI_ADDR(REGS_PMU_APB_BASE, 0x01C0)/*CA53_BIG_C1_INT_DISABLE*/ +#define REG_PMU_APB_CA53_BIG_C2_INT_DISABLE SCI_ADDR(REGS_PMU_APB_BASE, 0x01C4)/*CA53_BIG_C2_INT_DISABLE*/ +#define REG_PMU_APB_CA53_BIG_C3_INT_DISABLE SCI_ADDR(REGS_PMU_APB_BASE, 0x01C8)/*CA53_BIG_C3_INT_DISABLE*/ +#define REG_PMU_APB_APCPU_LIT_C0_INT_DISABLE REG_PMU_APB_CA53_LIT_C0_INT_DISABLE +#define REG_PMU_APB_APCPU_LIT_C1_INT_DISABLE REG_PMU_APB_CA53_LIT_C1_INT_DISABLE +#define REG_PMU_APB_APCPU_LIT_C2_INT_DISABLE REG_PMU_APB_CA53_LIT_C2_INT_DISABLE +#define REG_PMU_APB_APCPU_LIT_C3_INT_DISABLE REG_PMU_APB_CA53_LIT_C3_INT_DISABLE +#define REG_PMU_APB_APCPU_BIG_C0_INT_DISABLE REG_PMU_APB_CA53_BIG_C0_INT_DISABLE +#define REG_PMU_APB_APCPU_BIG_C1_INT_DISABLE REG_PMU_APB_CA53_BIG_C1_INT_DISABLE +#define REG_PMU_APB_APCPU_BIG_C2_INT_DISABLE REG_PMU_APB_CA53_BIG_C2_INT_DISABLE +#define REG_PMU_APB_APCPU_BIG_C3_INT_DISABLE REG_PMU_APB_CA53_BIG_C3_INT_DISABLE +#define REG_PMU_APB_PUB_ACC_RDY SCI_ADDR(REGS_PMU_APB_BASE, 0x01CC)/*PUB_ACC_RDY*/ +#define REG_PMU_APB_PUB_CLK_RDY SCI_ADDR(REGS_PMU_APB_BASE, 0x01D0)/*PUB_CLK_RDY*/ +#define REG_PMU_APB_PD_CA53_LIT_C0_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3000)/*PD_CA53_LITC0_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CA53_LIT_C1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3004)/*PD_CA53_LIT_C1_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CA53_LIT_C2_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3008)/*PD_CA53_LIT_C2_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CA53_LIT_C3_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x300C)/*PD_CA53_LIT_C3_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CA53_TOP_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3010)/*PD_CA53_TOP_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_AP_SYS_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3014)/*PD_AP_SYS_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_GPU_TOP_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3018)/*PD_GPU_TOP_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_MM_TOP_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x301C)/*PD_MM_TOP_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CP0_ARM9_0_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3020)/*PD_CP0_ARM9_0_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CP0_ARM9_1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3024)/*PD_CP0_ARM9_1_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CP0_CEVA_0_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3028)/*PD_CP0_CEVA_0_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CP0_CEVA_1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x302C)/*PD_CP0_CEVA_1_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CP0_GSM_0_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3030)/*PD_CP0_GSM_0_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CP0_GSM_1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3034)/*PD_CP0_GSM_1_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CP0_TD_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3038)/*PD_CP0_TD_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CP0_HU3GE_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x303C)/*PD_CP0_HU3GE_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CP1_CA5_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3040)/*PD_CP1_CA5_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CP1_CEVA_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3044)/*PD_CP1_CEVA_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CP1_LTE_P1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3048)/*PD_CP1_LTE_P1_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CP1_LTE_P2_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x304C)/*PD_CP1_LTE_P2_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CP1_COMWRAP_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3050)/*PD_CP1_COMWRAP_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_PUB_SYS_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3054)/*PD_PUB_SYS_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_GPU_C0_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3058)/*PD_GPU_C0_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_GPU_C1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x305C)/*PD_GPU_C1_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CA53_LIT_MP4_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3060)/*PD_CA53_LIT_MP4_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CA53_BIG_C0_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3064)/*PD_CA53_BIG_C0_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CA53_BIG_C1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3068)/*PD_CA53_BIG_C1_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CA53_BIG_C2_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x306C)/*PD_CA53_BIG_C2_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CA53_BIG_C3_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3070)/*PD_CA53_BIG_C3_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_CA53_BIG_MP4_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3074)/*PD_CA53_BIG_MP4_SHUTDOWN_MARK_STATUS*/ +#define REG_PMU_APB_PD_APCPU_LIT_MP4_SHUTDOWN_MARK_STATUS REG_PMU_APB_PD_CA53_LIT_MP4_SHUTDOWN_MARK_STATUS +#define REG_PMU_APB_PD_APCPU_BIG_C0_SHUTDOWN_MARK_STATUS REG_PMU_APB_PD_CA53_BIG_C0_SHUTDOWN_MARK_STATUS +#define REG_PMU_APB_PD_APCPU_BIG_C1_SHUTDOWN_MARK_STATUS REG_PMU_APB_PD_CA53_BIG_C1_SHUTDOWN_MARK_STATUS +#define REG_PMU_APB_PD_APCPU_BIG_C2_SHUTDOWN_MARK_STATUS REG_PMU_APB_PD_CA53_BIG_C2_SHUTDOWN_MARK_STATUS +#define REG_PMU_APB_PD_APCPU_BIG_C3_SHUTDOWN_MARK_STATUS REG_PMU_APB_PD_CA53_BIG_C3_SHUTDOWN_MARK_STATUS +#define REG_PMU_APB_PD_APCPU_BIG_MP4_SHUTDOWN_MARK_STATUS REG_PMU_APB_PD_CA53_BIG_MP4_SHUTDOWN_MARK_STATUS +#define REG_PMU_APB_PD_MM_CODEC_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3078)/*PD_MM_CODEC_SHUTDOWN_MARK_STATUS*/ + + + +/* bits definitions for register REG_PMU_APB_PD_CA53_TOP_CFG */ +#define BIT_PD_CA53_TOP_PD_SEL ( BIT(29) ) +#define BIT_PD_CA53_TOP_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_PD_CA53_TOP_STOP_EN ( BIT(27) ) +#define BIT_PD_CA53_TOP_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA53_TOP_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BIT_PD_CA7_TOP_DBG_SHUTDOWN_EN BIT_PD_CA53_TOP_DBG_SHUTDOWN_EN +#define BIT_PD_CA7_TOP_STOP_EN BIT_PD_CA53_TOP_STOP_EN +#define BIT_PD_CA7_TOP_FORCE_SHUTDOWN BIT_PD_CA53_TOP_FORCE_SHUTDOWN +#define BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN BIT_PD_CA53_TOP_AUTO_SHUTDOWN_EN +#define BITS_PD_CA53_TOP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA53_TOP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA53_TOP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_LIT_C0_CFG */ +#define BIT_CA53_LIT_C0_WAKEUP_EN ( BIT(30) ) +#define BIT_PD_CA53_LIT_C0_PD_SEL ( BIT(29) ) +#define BIT_PD_CA53_LIT_C0_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_CA53_LIT_C0_DSLP_ENA ( BIT(27) ) +#define BIT_PD_CA53_LIT_C0_PWR_RST_CFG ( BIT(26) ) +#define BIT_PD_CA53_LIT_C0_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA53_LIT_C0_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CA53_LIT_C0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA53_LIT_C0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA53_LIT_C0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_LIT_C1_CFG */ +#define BIT_CA53_LIT_C1_WAKEUP_EN ( BIT(30) ) +#define BIT_PD_CA53_LIT_C1_PD_SEL ( BIT(29) ) +#define BIT_PD_CA53_LIT_C1_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_CA53_LIT_C1_DSLP_ENA ( BIT(27) ) +#define BIT_PD_CA53_LIT_C1_PWR_RST_CFG ( BIT(26) ) +#define BIT_PD_CA53_LIT_C1_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA53_LIT_C1_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CA53_LIT_C1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA53_LIT_C1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA53_LIT_C1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_LIT_C2_CFG */ +#define BIT_CA53_LIT_C2_WAKEUP_EN ( BIT(30) ) +#define BIT_PD_CA53_LIT_C2_PD_SEL ( BIT(29) ) +#define BIT_PD_CA53_LIT_C2_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_CA53_LIT_C2_DSLP_ENA ( BIT(27) ) +#define BIT_PD_CA53_LIT_C2_PWR_RST_CFG ( BIT(26) ) +#define BIT_PD_CA53_LIT_C2_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA53_LIT_C2_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CA53_LIT_C2_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA53_LIT_C2_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA53_LIT_C2_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_LIT_C3_CFG */ +#define BIT_CA53_LIT_C3_WAKEUP_EN ( BIT(30) ) +#define BIT_PD_CA53_LIT_C3_PD_SEL ( BIT(29) ) +#define BIT_PD_CA53_LIT_C3_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_CA53_LIT_C3_DSLP_ENA ( BIT(27) ) +#define BIT_PD_CA53_LIT_C3_PWR_RST_CFG ( BIT(26) ) +#define BIT_PD_CA53_LIT_C3_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA53_LIT_C3_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CA53_LIT_C3_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA53_LIT_C3_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA53_LIT_C3_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_LIT_MP4_CFG */ +#define BIT_CA53_LIT_MP4_WAKEUP_EN ( BIT(30) ) +#define BIT_PD_CA53_LIT_MP4_PD_SEL ( BIT(29) ) +#define BIT_PD_CA53_LIT_MP4_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_CA53_LIT_MP4_DSLP_ENA ( BIT(27) ) +#define BIT_PD_CA53_LIT_MP4_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA53_LIT_MP4_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CA53_LIT_MP4_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA53_LIT_MP4_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA53_LIT_MP4_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_AP_SYS_CFG */ +#define BIT_PD_AP_SYS_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_AP_SYS_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_AP_SYS_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_MM_TOP_CFG */ +#define BIT_PD_MM_TOP_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_MM_TOP_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_MM_TOP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_MM_TOP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_GPU_TOP_CFG */ +#define BIT_PD_GPU_TOP_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_GPU_TOP_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_GPU_TOP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_GPU_TOP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_0_CFG */ +#define BIT_PD_CP0_ARM9_0_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_ARM9_0_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_ARM9_0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_ARM9_0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_ARM9_0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_1_CFG */ +#define BIT_PD_CP0_ARM9_1_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_ARM9_1_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_ARM9_1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_ARM9_1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_ARM9_1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_HU3GE_CFG */ +#define BIT_PD_CP0_HU3GE_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_HU3GE_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_HU3GE_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_HU3GE_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_HU3GE_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_GSM_0_CFG */ +#define BIT_PD_CP0_GSM_0_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_GSM_0_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_GSM_0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_GSM_0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_GSM_0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_GSM_1_CFG */ +#define BIT_PD_CP0_GSM_1_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_GSM_1_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_GSM_1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_GSM_1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_GSM_1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_TD_CFG */ +#define BIT_PD_CP0_TD_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_TD_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_TD_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_TD_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_TD_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_CEVA_0_CFG */ +#define BIT_PD_CP0_CEVA_0_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_CEVA_0_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_CEVA_0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_CEVA_0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_CEVA_0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_CEVA_1_CFG */ +#define BIT_PD_CP0_CEVA_1_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP0_CEVA_1_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP0_CEVA_1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_CEVA_1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_CEVA_1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_MM_CODEC_CFG */ +#define BIT_PD_MM_CODEC_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_MM_CODEC_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_MM_CODEC_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_MM_CODEC_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_MM_CODEC_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_CA5_CFG */ +#define BIT_PD_CP1_CA5_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP1_CA5_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP1_CA5_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_CA5_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_CA5_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_LTE_P1_CFG */ +#define BIT_PD_CP1_LTE_P1_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP1_LTE_P1_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP1_LTE_P1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_LTE_P1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_LTE_P1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_LTE_P2_CFG */ +#define BIT_PD_CP1_LTE_P2_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP1_LTE_P2_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP1_LTE_P2_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_LTE_P2_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_LTE_P2_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_CEVA_CFG */ +#define BIT_PD_CP1_CEVA_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP1_CEVA_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP1_CEVA_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_CEVA_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_CEVA_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_COMWRAP_CFG */ +#define BIT_PD_CP1_COMWRAP_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CP1_COMWRAP_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CP1_COMWRAP_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_COMWRAP_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_COMWRAP_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_PUB_SYS_CFG */ +#define BIT_PD_PUB_SYS_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_PUB_SYS_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_PUB_SYS_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_AP_WAKEUP_POR_CFG */ +#define BIT_AP_WAKEUP_POR_N ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_PD_GPU_C0_CFG */ +#define BIT_PD_GPU_C0_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_GPU_C0_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_GPU_C0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_GPU_C0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_GPU_C0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_GPU_C1_CFG */ +#define BIT_PD_GPU_C1_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_GPU_C1_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_GPU_C1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_GPU_C1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_GPU_C1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_XTL_WAIT_CNT */ +#define BITS_XTL1_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_XTL0_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_XTLBUF_WAIT_CNT */ +#define BITS_XTLBUF1_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_XTLBUF0_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PLL_WAIT_CNT1 */ +#define BITS_LTEPLL_WAIT_CNT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_TWPLL_WAIT_CNT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DPLL_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_MPLL0_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PLL_WAIT_CNT2 */ +#define BITS_GPLL_WAIT_CNT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_MPLL_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_LVDSDIS_PLL_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_XTL0_REL_CFG */ +#define BIT_XTL0_ARM7_SEL ( BIT(5) ) +#define BIT_XTL0_VCP1_SEL ( BIT(4) ) +#define BIT_XTL0_VCP0_SEL ( BIT(3) ) +#define BIT_XTL0_CP1_SEL ( BIT(2) ) +#define BIT_XTL0_CP0_SEL ( BIT(1) ) +#define BIT_XTL0_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_XTL1_REL_CFG */ +#define BIT_XTL1_ARM7_SEL ( BIT(5) ) +#define BIT_XTL1_VCP1_SEL ( BIT(4) ) +#define BIT_XTL1_VCP0_SEL ( BIT(3) ) +#define BIT_XTL1_CP1_SEL ( BIT(2) ) +#define BIT_XTL1_CP0_SEL ( BIT(1) ) +#define BIT_XTL1_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_PLL_PD_CFG */ +#define BIT_MPLL_FORCE_PD ( BIT(2) ) +#define BIT_USBPLL_PD ( BIT(1) ) +#define BIT_GPLL_PD ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_XTLBUF0_REL_CFG */ +#define BIT_XTLBUF0_ARM7_SEL ( BIT(5) ) +#define BIT_XTLBUF0_VCP1_SEL ( BIT(4) ) +#define BIT_XTLBUF0_VCP0_SEL ( BIT(3) ) +#define BIT_XTLBUF0_CP1_SEL ( BIT(2) ) +#define BIT_XTLBUF0_CP0_SEL ( BIT(1) ) +#define BIT_XTLBUF0_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_XTLBUF1_REL_CFG */ +#define BIT_XTLBUF1_ARM7_SEL ( BIT(5) ) +#define BIT_XTLBUF1_VCP1_SEL ( BIT(4) ) +#define BIT_XTLBUF1_VCP0_SEL ( BIT(3) ) +#define BIT_XTLBUF1_CP1_SEL ( BIT(2) ) +#define BIT_XTLBUF1_CP0_SEL ( BIT(1) ) +#define BIT_XTLBUF1_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_MPLL0_REL_CFG */ +#define BIT_MPLL0_REF_SEL ( BIT(8) ) +#define BIT_MPLL0_ARM7_SEL ( BIT(5) ) +#define BIT_MPLL0_VCP1_SEL ( BIT(4) ) +#define BIT_MPLL0_VCP0_SEL ( BIT(3) ) +#define BIT_MPLL0_CP1_SEL ( BIT(2) ) +#define BIT_MPLL0_CP0_SEL ( BIT(1) ) +#define BIT_MPLL0_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_DPLL_REL_CFG */ +#define BIT_DPLL_REF_SEL ( BIT(8) ) +#define BIT_DPLL_ARM7_SEL ( BIT(5) ) +#define BIT_DPLL_VCP1_SEL ( BIT(4) ) +#define BIT_DPLL_VCP0_SEL ( BIT(3) ) +#define BIT_DPLL_CP1_SEL ( BIT(2) ) +#define BIT_DPLL_CP0_SEL ( BIT(1) ) +#define BIT_DPLL_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_LTEPLL_REL_CFG */ +#define BIT_LTEPLL_REF_SEL ( BIT(8) ) +#define BIT_LTEPLL_ARM7_SEL ( BIT(5) ) +#define BIT_LTEPLL_VCP1_SEL ( BIT(4) ) +#define BIT_LTEPLL_VCP0_SEL ( BIT(3) ) +#define BIT_LTEPLL_CP1_SEL ( BIT(2) ) +#define BIT_LTEPLL_CP0_SEL ( BIT(1) ) +#define BIT_LTEPLL_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_TWPLL_REL_CFG */ +#define BIT_TWPLL_REF_SEL ( BIT(8) ) +#define BIT_TWPLL_ARM7_SEL ( BIT(5) ) +#define BIT_TWPLL_VCP1_SEL ( BIT(4) ) +#define BIT_TWPLL_VCP0_SEL ( BIT(3) ) +#define BIT_TWPLL_CP1_SEL ( BIT(2) ) +#define BIT_TWPLL_CP0_SEL ( BIT(1) ) +#define BIT_TWPLL_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_LVDSDIS_PLL_REL_CFG */ +#define BIT_LVDSDIS_PLL_REF_SEL ( BIT(8) ) +#define BIT_LVDSDIS_PLL_ARM7_SEL ( BIT(5) ) +#define BIT_LVDSDIS_PLL_VCP1_SEL ( BIT(4) ) +#define BIT_LVDSDIS_PLL_VCP0_SEL ( BIT(3) ) +#define BIT_LVDSDIS_PLL_CP1_SEL ( BIT(2) ) +#define BIT_LVDSDIS_PLL_CP0_SEL ( BIT(1) ) +#define BIT_LVDSDIS_PLL_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_MPLL_REL_CFG */ +#define BIT_MPLL_REF_SEL ( BIT(8) ) +#define BIT_MPLL_ARM7_SEL ( BIT(5) ) +#define BIT_MPLL_VCP1_SEL ( BIT(4) ) +#define BIT_MPLL_VCP0_SEL ( BIT(3) ) +#define BIT_MPLL_CP1_SEL ( BIT(2) ) +#define BIT_MPLL_CP0_SEL ( BIT(1) ) +#define BIT_MPLL_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_GPLL_REL_CFG */ +#define BIT_GPLL_REF_SEL ( BIT(8) ) + +/* bits definitions for register REG_PMU_APB_CP_SOFT_RST */ +#define BIT_ARM7_SOFT_RST ( BIT(8) ) +#define BIT_PUB_SOFT_RST ( BIT(6) ) +#define BIT_AP_SOFT_RST ( BIT(5) ) +#define BIT_GPU_SOFT_RST ( BIT(4) ) +#define BIT_MM_SOFT_RST ( BIT(3) ) +#define BIT_CP1_SOFT_RST ( BIT(1) ) +#define BIT_CP0_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CP_SLP_STATUS_DBG0 */ +#define BITS_CP1_DEEP_SLP_DBG(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_CP0_DEEP_SLP_DBG(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) + +/* bits definitions for register REG_PMU_APB_PWR_STATUS0_DBG */ +#define BITS_PD_MM_TOP_STATE(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_PD_GPU_TOP_STATE(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_PD_AP_SYS_STATE(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA53_LIT_C3_STATE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_PD_CA53_LIT_C2_STATE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA53_LIT_C1_STATE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_PD_CA53_LIT_C0_STATE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_PD_CA53_TOP_STATE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PWR_STATUS1_DBG */ +#define BITS_PD_CP0_CEVA_1_STATE(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_PD_CP0_CEVA_0_STATE(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_PD_CP0_GSM_0_STATE(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP0_GSM_1_STATE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_PD_CP0_HU3GE_STATE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP0_ARM9_1_STATE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_PD_CP0_ARM9_0_STATE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_PD_CP0_TD_STATE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PWR_STATUS2_DBG */ +#define BITS_PD_PUB_SYS_STATE(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_PD_CP1_COMWRAP_STATE(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CP1_LTE_P2_STATE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_PD_CP1_LTE_P1_STATE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CP1_CEVA_STATE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_PD_CP1_CA5_STATE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_PD_CA53_LIT_MP4_STATE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PWR_STATUS3_DBG */ +#define BITS_PD_MM_CODEC_STATE(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_PD_CA53_BIG_C3_STATE(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_PD_CA53_BIG_C2_STATE(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA53_BIG_C1_STATE(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_PD_CA53_BIG_C0_STATE(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA53_BIG_MP4_STATE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_PD_GPU_C1_STATE(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_PD_GPU_C0_STATE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_SLEEP_CTRL */ +#define BIT_VCP1_FORCE_LIGHT_SLEEP ( BIT(28) ) +#define BIT_VCP0_FORCE_LIGHT_SLEEP ( BIT(27) ) +#define BIT_CP1_FORCE_LIGHT_SLEEP ( BIT(26) ) +#define BIT_CP0_FORCE_LIGHT_SLEEP ( BIT(25) ) +#define BIT_AP_FORCE_LIGHT_SLEEP ( BIT(24) ) +#define BIT_ARM7_FORCE_DEEP_SLEEP ( BIT(21) ) +#define BIT_VCP1_FORCE_DEEP_SLEEP ( BIT(20) ) +#define BIT_VCP0_FORCE_DEEP_SLEEP ( BIT(19) ) +#define BIT_CP1_FORCE_DEEP_SLEEP ( BIT(18) ) +#define BIT_CP0_FORCE_DEEP_SLEEP ( BIT(17) ) +#define BIT_AP_FORCE_DEEP_SLEEP ( BIT(16) ) +#define BIT_VCP1_LIGHT_SLEEP ( BIT(12) ) +#define BIT_VCP0_LIGHT_SLEEP ( BIT(11) ) +#define BIT_CP1_LIGHT_SLEEP ( BIT(10) ) +#define BIT_CP0_LIGHT_SLEEP ( BIT(9) ) +#define BIT_AP_LIGHT_SLEEP ( BIT(8) ) +#define BIT_VCP1_DEEP_SLEEP ( BIT(4) ) +#define BIT_VCP0_DEEP_SLEEP ( BIT(3) ) +#define BIT_CP1_DEEP_SLEEP ( BIT(2) ) +#define BIT_CP0_DEEP_SLEEP ( BIT(1) ) +#define BIT_AP_DEEP_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_DDR_SLEEP_CTRL */ +#define BIT_BUSY_TRANSFER_HWDATA_SEL ( BIT(16) ) +#define BIT_DDR_PUBL_APB_SOFT_RST ( BIT(12) ) +#define BIT_DDR_UMCTL_APB_SOFT_RST ( BIT(11) ) +#define BIT_DDR_PUBL_SOFT_RST ( BIT(10) ) +#define BIT_DDR_PHY_SOFT_RST ( BIT(8) ) +#define BIT_DDR_PHY_AUTO_GATE_EN ( BIT(6) ) +#define BIT_DDR_PUBL_AUTO_GATE_EN ( BIT(5) ) +#define BIT_DDR_UMCTL_AUTO_GATE_EN ( BIT(4) ) +#define BIT_DDR_PHY_EB ( BIT(2) ) +#define BIT_DDR_UMCTL_EB ( BIT(1) ) +#define BIT_DDR_PUBL_EB ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_SLEEP_STATUS */ +#define BITS_ARM7_SLP_STATUS(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_VCP1_SLP_STATUS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_VCP0_SLP_STATUS(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_CP1_SLP_STATUS(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_CP0_SLP_STATUS(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_AP_SLP_STATUS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_DDR_CHN_SLEEP_CTRL0 */ +#define BIT_DDR_CTRL_AXI_LP_EN ( BIT(31) ) +#define BIT_DDR_CTRL_CGM_SEL ( BIT(30) ) +#define BIT_DDR_CHN9_AXI_LP_EN ( BIT(25) ) +#define BIT_DDR_CHN8_AXI_LP_EN ( BIT(24) ) +#define BIT_DDR_CHN7_AXI_LP_EN ( BIT(23) ) +#define BIT_DDR_CHN6_AXI_LP_EN ( BIT(22) ) +#define BIT_DDR_CHN5_AXI_LP_EN ( BIT(21) ) +#define BIT_DDR_CHN4_AXI_LP_EN ( BIT(20) ) +#define BIT_DDR_CHN3_AXI_LP_EN ( BIT(19) ) +#define BIT_DDR_CHN2_AXI_LP_EN ( BIT(18) ) +#define BIT_DDR_CHN1_AXI_LP_EN ( BIT(17) ) +#define BIT_DDR_CHN0_AXI_LP_EN ( BIT(16) ) +#define BIT_DDR_CHN9_CGM_SEL ( BIT(9) ) +#define BIT_DDR_CHN8_CGM_SEL ( BIT(8) ) +#define BIT_DDR_CHN7_CGM_SEL ( BIT(7) ) +#define BIT_DDR_CHN6_CGM_SEL ( BIT(6) ) +#define BIT_DDR_CHN5_CGM_SEL ( BIT(5) ) +#define BIT_DDR_CHN4_CGM_SEL ( BIT(4) ) +#define BIT_DDR_CHN3_CGM_SEL ( BIT(3) ) +#define BIT_DDR_CHN2_CGM_SEL ( BIT(2) ) +#define BIT_DDR_CHN1_CGM_SEL ( BIT(1) ) +#define BIT_DDR_CHN0_CGM_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_DDR_CHN_SLEEP_CTRL1 */ +#define BIT_DDR_CHN9_AXI_STOP_SEL ( BIT(9) ) +#define BIT_DDR_CHN8_AXI_STOP_SEL ( BIT(8) ) +#define BIT_DDR_CHN7_AXI_STOP_SEL ( BIT(7) ) +#define BIT_DDR_CHN6_AXI_STOP_SEL ( BIT(6) ) +#define BIT_DDR_CHN5_AXI_STOP_SEL ( BIT(5) ) +#define BIT_DDR_CHN4_AXI_STOP_SEL ( BIT(4) ) +#define BIT_DDR_CHN3_AXI_STOP_SEL ( BIT(3) ) +#define BIT_DDR_CHN2_AXI_STOP_SEL ( BIT(2) ) +#define BIT_DDR_CHN1_AXI_STOP_SEL ( BIT(1) ) +#define BIT_DDR_CHN0_AXI_STOP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_BIG_C0_CFG */ +#define BIT_CA53_BIG_C0_WAKEUP_EN ( BIT(30) ) +#define BIT_PD_CA53_BIG_C0_PD_SEL ( BIT(29) ) +#define BIT_PD_CA53_BIG_C0_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_CA53_BIG_C0_DSLP_ENA ( BIT(27) ) +#define BIT_PD_CA53_BIG_C0_PWR_RST_CFG ( BIT(26) ) +#define BIT_PD_CA53_BIG_C0_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA53_BIG_C0_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CA53_BIG_C0_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA53_BIG_C0_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA53_BIG_C0_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_BIG_C1_CFG */ +#define BIT_CA53_BIG_C1_WAKEUP_EN ( BIT(30) ) +#define BIT_PD_CA53_BIG_C1_PD_SEL ( BIT(29) ) +#define BIT_PD_CA53_BIG_C1_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_CA53_BIG_C1_DSLP_ENA ( BIT(27) ) +#define BIT_PD_CA53_BIG_C1_PWR_RST_CFG ( BIT(26) ) +#define BIT_PD_CA53_BIG_C1_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA53_BIG_C1_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CA53_BIG_C1_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA53_BIG_C1_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA53_BIG_C1_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_BIG_C2_CFG */ +#define BIT_CA53_BIG_C2_WAKEUP_EN ( BIT(30) ) +#define BIT_PD_CA53_BIG_C2_PD_SEL ( BIT(29) ) +#define BIT_PD_CA53_BIG_C2_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_CA53_BIG_C2_DSLP_ENA ( BIT(27) ) +#define BIT_PD_CA53_BIG_C2_PWR_RST_CFG ( BIT(26) ) +#define BIT_PD_CA53_BIG_C2_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA53_BIG_C2_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CA53_BIG_C2_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA53_BIG_C2_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA53_BIG_C2_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_BIG_C3_CFG */ +#define BIT_CA53_BIG_C3_WAKEUP_EN ( BIT(30) ) +#define BIT_PD_CA53_BIG_C3_PD_SEL ( BIT(29) ) +#define BIT_PD_CA53_BIG_C3_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_CA53_BIG_C3_DSLP_ENA ( BIT(27) ) +#define BIT_PD_CA53_BIG_C3_PWR_RST_CFG ( BIT(26) ) +#define BIT_PD_CA53_BIG_C3_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA53_BIG_C3_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CA53_BIG_C3_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA53_BIG_C3_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA53_BIG_C3_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_BIG_MP4_CFG */ +#define BIT_CA53_BIG_MP4_WAKEUP_EN ( BIT(30) ) +#define BIT_PD_CA53_BIG_MP4_PD_SEL ( BIT(29) ) +#define BIT_PD_CA53_BIG_MP4_DBG_SHUTDOWN_EN ( BIT(28) ) +#define BIT_CA53_BIG_MP4_DSLP_ENA ( BIT(27) ) +#define BIT_PD_CA53_BIG_MP4_FORCE_SHUTDOWN ( BIT(25) ) +#define BIT_PD_CA53_BIG_MP4_AUTO_SHUTDOWN_EN ( BIT(24) ) +#define BITS_PD_CA53_BIG_MP4_PWR_ON_DLY(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_PD_CA53_BIG_MP4_PWR_ON_SEQ_DLY(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_PD_CA53_BIG_MP4_ISO_ON_DLY(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_DDR_OP_MODE_CFG */ +#define BIT_DDR_OPERATE_MODE_BUSY ( BIT(28) ) +#define BIT_DDR_PUBL_RET_EN ( BIT(27) ) +#define BIT_DDR_PHY_ISO_RST_EN ( BIT(26) ) +#define BIT_DDR_UMCTL_RET_EN ( BIT(25) ) +#define BIT_DDR_PHY_AUTO_RET_EN ( BIT(24) ) +#define BITS_DDR_OPERATE_MODE_CNT_LMT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DDR_OPERATE_MODE(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_DDR_OPERATE_MODE_IDLE(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_PMU_APB_DDR_PHY_RET_CFG */ +#define BIT_DDR_UMCTL_SOFT_RST ( BIT(16) ) +#define BIT_DDR_PHY_CKE_RET_EN ( BIT(0) ) +#define BIT_DDR_PHY_CKE_RET_EN BIT_DDR_PHY_CKE_RET_EN + +/* bits definitions for register REG_PMU_APB_26M_SEL_CFG */ +#define BIT_AON_RC_4M_SEL ( BIT(8) ) +#define BIT_GGE_26M_SEL ( BIT(6) ) +#define BIT_PUB_26M_SEL ( BIT(5) ) +#define BIT_AON_26M_SEL ( BIT(4) ) +#define BIT_CP1_26M_SEL ( BIT(2) ) +#define BIT_CP0_26M_SEL ( BIT(1) ) +#define BIT_AP_26M_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_BISR_DONE_STATUS */ +#define BIT_PD_MM_CODEC_BISR_DONE ( BIT(29) ) +#define BIT_PD_CA53_BIG_MP4_BISR_DONE ( BIT(28) ) +#define BIT_PD_CA53_BIG_C3_BISR_DONE ( BIT(27) ) +#define BIT_PD_CA53_BIG_C2_BISR_DONE ( BIT(26) ) +#define BIT_PD_CA53_BIG_C1_BISR_DONE ( BIT(25) ) +#define BIT_PD_CA53_BIG_C0_BISR_DONE ( BIT(24) ) +#define BIT_PD_GPU_C1_BISR_DONE ( BIT(23) ) +#define BIT_PD_GPU_C0_BISR_DONE ( BIT(22) ) +#define BIT_PD_CP1_COMWRAP_BISR_DONE ( BIT(21) ) +#define BIT_PD_CP1_LTE_P2_BISR_DONE ( BIT(20) ) +#define BIT_PD_CP1_LTE_P1_BISR_DONE ( BIT(19) ) +#define BIT_PD_CP1_CEVA_BISR_DONE ( BIT(18) ) +#define BIT_PD_CP1_CA5_BISR_DONE ( BIT(17) ) +#define BIT_PD_CA53_LIT_MP4_BISR_DONE ( BIT(16) ) +#define BIT_PD_CP0_HU3GE_BISR_DONE ( BIT(15) ) +#define BIT_PD_CP0_TD_BISR_DONE ( BIT(14) ) +#define BIT_PD_CP0_GSM_1_BISR_DONE ( BIT(13) ) +#define BIT_PD_CP0_GSM_0_BISR_DONE ( BIT(12) ) +#define BIT_PD_CP0_CEVA_1_BISR_DONE ( BIT(11) ) +#define BIT_PD_CP0_CEVA_0_BISR_DONE ( BIT(10) ) +#define BIT_PD_CP0_ARM9_1_BISR_DONE ( BIT(9) ) +#define BIT_PD_CP0_ARM9_0_BISR_DONE ( BIT(8) ) +#define BIT_PD_MM_TOP_BISR_DONE ( BIT(7) ) +#define BIT_PD_GPU_TOP_BISR_DONE ( BIT(6) ) +#define BIT_PD_AP_SYS_BISR_DONE ( BIT(5) ) +#define BIT_PD_CA53_TOP_BISR_DONE ( BIT(4) ) +#define BIT_PD_CA53_LIT_C3_BISR_DONE ( BIT(3) ) +#define BIT_PD_CA53_LIT_C2_BISR_DONE ( BIT(2) ) +#define BIT_PD_CA53_LIT_C1_BISR_DONE ( BIT(1) ) +#define BIT_PD_CA53_LIT_C0_BISR_DONE ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_BISR_BUSY_STATUS */ +#define BIT_PD_MM_CODEC_BISR_BUSY ( BIT(29) ) +#define BIT_PD_CA53_BIG_MP4_BISR_BUSY ( BIT(28) ) +#define BIT_PD_CA53_BIG_C3_BISR_BUSY ( BIT(27) ) +#define BIT_PD_CA53_BIG_C2_BISR_BUSY ( BIT(26) ) +#define BIT_PD_CA53_BIG_C1_BISR_BUSY ( BIT(25) ) +#define BIT_PD_CA53_BIG_C0_BISR_BUSY ( BIT(24) ) +#define BIT_PD_GPU_C1_BISR_BUSY ( BIT(23) ) +#define BIT_PD_GPU_C0_BISR_BUSY ( BIT(22) ) +#define BIT_PD_CP1_COMWRAP_BISR_BUSY ( BIT(21) ) +#define BIT_PD_CP1_LTE_P2_BISR_BUSY ( BIT(20) ) +#define BIT_PD_CP1_LTE_P1_BISR_BUSY ( BIT(19) ) +#define BIT_PD_CP1_CEVA_BISR_BUSY ( BIT(18) ) +#define BIT_PD_CP1_CA5_BISR_BUSY ( BIT(17) ) +#define BIT_PD_CA53_LIT_MP4_BISR_BUSY ( BIT(16) ) +#define BIT_PD_CP0_HU3GE_BISR_BUSY ( BIT(15) ) +#define BIT_PD_CP0_TD_BISR_BUSY ( BIT(14) ) +#define BIT_PD_CP0_GSM_1_BISR_BUSY ( BIT(13) ) +#define BIT_PD_CP0_GSM_0_BISR_BUSY ( BIT(12) ) +#define BIT_PD_CP0_CEVA_1_BISR_BUSY ( BIT(11) ) +#define BIT_PD_CP0_CEVA_0_BISR_BUSY ( BIT(10) ) +#define BIT_PD_CP0_ARM9_1_BISR_BUSY ( BIT(9) ) +#define BIT_PD_CP0_ARM9_0_BISR_BUSY ( BIT(8) ) +#define BIT_PD_MM_TOP_BISR_BUSY ( BIT(7) ) +#define BIT_PD_GPU_TOP_BISR_BUSY ( BIT(6) ) +#define BIT_PD_AP_SYS_BISR_BUSY ( BIT(5) ) +#define BIT_PD_CA53_TOP_BISR_BUSY ( BIT(4) ) +#define BIT_PD_CA53_LIT_C3_BISR_BUSY ( BIT(3) ) +#define BIT_PD_CA53_LIT_C2_BISR_BUSY ( BIT(2) ) +#define BIT_PD_CA53_LIT_C1_BISR_BUSY ( BIT(1) ) +#define BIT_PD_CA53_LIT_C0_BISR_BUSY ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_BISR_BYP_CFG */ +#define BIT_PD_MM_CODEC_BISR_FORCE_BYP ( BIT(29) ) +#define BIT_PD_CA53_BIG_MP4_BISR_FORCE_BYP ( BIT(28) ) +#define BIT_PD_CA53_BIG_C3_BISR_FORCE_BYP ( BIT(27) ) +#define BIT_PD_CA53_BIG_C2_BISR_FORCE_BYP ( BIT(26) ) +#define BIT_PD_CA53_BIG_C1_BISR_FORCE_BYP ( BIT(25) ) +#define BIT_PD_CA53_BIG_C0_BISR_FORCE_BYP ( BIT(24) ) +#define BIT_PD_GPU_C1_BISR_FORCE_BYP ( BIT(23) ) +#define BIT_PD_GPU_C0_BISR_FORCE_BYP ( BIT(22) ) +#define BIT_PD_CP1_COMWRAP_BISR_FORCE_BYP ( BIT(21) ) +#define BIT_PD_CP1_LTE_P2_BISR_FORCE_BYP ( BIT(20) ) +#define BIT_PD_CP1_LTE_P1_BISR_FORCE_BYP ( BIT(19) ) +#define BIT_PD_CP1_CEVA_BISR_FORCE_BYP ( BIT(18) ) +#define BIT_PD_CP1_CA5_BISR_FORCE_BYP ( BIT(17) ) +#define BIT_PD_CA53_LIT_MP4_BISR_FORCE_BYP ( BIT(16) ) +#define BIT_PD_CP0_HU3GE_BISR_FORCE_BYP ( BIT(15) ) +#define BIT_PD_CP0_TD_BISR_FORCE_BYP ( BIT(14) ) +#define BIT_PD_CP0_GSM_1_BISR_FORCE_BYP ( BIT(13) ) +#define BIT_PD_CP0_GSM_0_BISR_FORCE_BYP ( BIT(12) ) +#define BIT_PD_CP0_CEVA_1_BISR_FORCE_BYP ( BIT(11) ) +#define BIT_PD_CP0_CEVA_0_BISR_FORCE_BYP ( BIT(10) ) +#define BIT_PD_CP0_ARM9_1_BISR_FORCE_BYP ( BIT(9) ) +#define BIT_PD_CP0_ARM9_0_BISR_FORCE_BYP ( BIT(8) ) +#define BIT_PD_MM_TOP_BISR_FORCE_BYP ( BIT(7) ) +#define BIT_PD_GPU_TOP_BISR_FORCE_BYP ( BIT(6) ) +#define BIT_PD_AP_SYS_BISR_FORCE_BYP ( BIT(5) ) +#define BIT_PD_CA53_TOP_BISR_FORCE_BYP ( BIT(4) ) +#define BIT_PD_CA53_LIT_C3_BISR_FORCE_BYP ( BIT(3) ) +#define BIT_PD_CA53_LIT_C2_BISR_FORCE_BYP ( BIT(2) ) +#define BIT_PD_CA53_LIT_C1_BISR_FORCE_BYP ( BIT(1) ) +#define BIT_PD_CA53_LIT_C0_BISR_FORCE_BYP ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_BISR_EN_CFG */ +#define BIT_PD_MM_CODEC_BISR_FORCE_EN ( BIT(29) ) +#define BIT_PD_CA53_BIG_MP4_BISR_FORCE_EN ( BIT(28) ) +#define BIT_PD_CA53_BIG_C3_BISR_FORCE_EN ( BIT(27) ) +#define BIT_PD_CA53_BIG_C2_BISR_FORCE_EN ( BIT(26) ) +#define BIT_PD_CA53_BIG_C1_BISR_FORCE_EN ( BIT(25) ) +#define BIT_PD_CA53_BIG_C0_BISR_FORCE_EN ( BIT(24) ) +#define BIT_PD_GPU_C1_BISR_FORCE_EN ( BIT(23) ) +#define BIT_PD_GPU_C0_BISR_FORCE_EN ( BIT(22) ) +#define BIT_PD_CP1_COMWRAP_BISR_FORCE_EN ( BIT(21) ) +#define BIT_PD_CP1_LTE_P2_BISR_FORCE_EN ( BIT(20) ) +#define BIT_PD_CP1_LTE_P1_BISR_FORCE_EN ( BIT(19) ) +#define BIT_PD_CP1_CEVA_BISR_FORCE_EN ( BIT(18) ) +#define BIT_PD_CP1_CA5_BISR_FORCE_EN ( BIT(17) ) +#define BIT_PD_CA53_LIT_MP4_BISR_FORCE_EN ( BIT(16) ) +#define BIT_PD_CP0_HU3GE_BISR_FORCE_EN ( BIT(15) ) +#define BIT_PD_CP0_TD_BISR_FORCE_EN ( BIT(14) ) +#define BIT_PD_CP0_GSM_1_BISR_FORCE_EN ( BIT(13) ) +#define BIT_PD_CP0_GSM_0_BISR_FORCE_EN ( BIT(12) ) +#define BIT_PD_CP0_CEVA_1_BISR_FORCE_EN ( BIT(11) ) +#define BIT_PD_CP0_CEVA_0_BISR_FORCE_EN ( BIT(10) ) +#define BIT_PD_CP0_ARM9_1_BISR_FORCE_EN ( BIT(9) ) +#define BIT_PD_CP0_ARM9_0_BISR_FORCE_EN ( BIT(8) ) +#define BIT_PD_MM_TOP_BISR_FORCE_EN ( BIT(7) ) +#define BIT_PD_GPU_TOP_BISR_FORCE_EN ( BIT(6) ) +#define BIT_PD_AP_SYS_BISR_FORCE_EN ( BIT(5) ) +#define BIT_PD_CA53_TOP_BISR_FORCE_EN ( BIT(4) ) +#define BIT_PD_CA53_LIT_C3_BISR_FORCE_EN ( BIT(3) ) +#define BIT_PD_CA53_LIT_C2_BISR_FORCE_EN ( BIT(2) ) +#define BIT_PD_CA53_LIT_C1_BISR_FORCE_EN ( BIT(1) ) +#define BIT_PD_CA53_LIT_C0_BISR_FORCE_EN ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG0 */ +#define BITS_CGM_AUTO_GATE_SEL_CFG0(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG1 */ +#define BITS_CGM_AUTO_GATE_SEL_CFG1(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG2 */ +#define BITS_CGM_AUTO_GATE_SEL_CFG2(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG3 */ +#define BITS_CGM_AUTO_GATE_SEL_CFG3(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CGM_FORCE_EN_CFG0 */ +#define BITS_CGM_FORCE_EN_CFG0(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CGM_FORCE_EN_CFG1 */ +#define BITS_CGM_FORCE_EN_CFG1(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CGM_FORCE_EN_CFG2 */ +#define BITS_CGM_FORCE_EN_CFG2(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CGM_FORCE_EN_CFG3 */ +#define BITS_CGM_FORCE_EN_CFG3(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_SLEEP_XTLON_CTRL */ +#define BIT_ARM7_SLEEP_XTL_ON ( BIT(5) ) +#define BIT_VCP1_SLEEP_XTL_ON ( BIT(4) ) +#define BIT_VCP0_SLEEP_XTL_ON ( BIT(3) ) +#define BIT_CP1_SLEEP_XTL_ON ( BIT(2) ) +#define BIT_CP0_SLEEP_XTL_ON ( BIT(1) ) +#define BIT_AP_SLEEP_XTL_ON ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_MEM_SLP_CFG */ +#define BITS_MEM_SLP_CFG(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_MEM_SD_CFG */ +#define BITS_MEM_SD_CFG(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_APCPU_CORE_PU_LOCK */ +#define BIT_PMU_APB_APCPU_C3_PU_LOCK ( BIT(3) ) +#define BIT_PMU_APB_APCPU_C2_PU_LOCK ( BIT(2) ) +#define BIT_PMU_APB_APCPU_C1_PU_LOCK ( BIT(1) ) +#define BIT_PMU_APB_APCPU_C0_PU_LOCK ( BIT(0) ) +#define BIT_PMU_APB_CA7_C3_PU_LOCK BIT_PMU_APB_APCPU_C3_PU_LOCK +#define BIT_PMU_APB_CA7_C2_PU_LOCK BIT_PMU_APB_APCPU_C2_PU_LOCK +#define BIT_PMU_APB_CA7_C1_PU_LOCK BIT_PMU_APB_APCPU_C1_PU_LOCK +#define BIT_PMU_APB_CA7_C0_PU_LOCK BIT_PMU_APB_APCPU_C0_PU_LOCK +/* bits definitions for register REG_PMU_APB_ARM7_HOLD_CGM_EN */ +#define BIT_PD_CP1_CEVA_CGM_HOLD_EN ( BIT(10) ) +#define BIT_PD_CP1_CA5_CGM_HOLD_EN ( BIT(9) ) +#define BIT_PD_CP0_CEVA_1_CGM_HOLD_EN ( BIT(8) ) +#define BIT_PD_CP0_CEVA_0_CGM_HOLD_EN ( BIT(7) ) +#define BIT_PD_CP0_ARM9_1_CGM_HOLD_EN ( BIT(6) ) +#define BIT_PD_CP0_ARM9_0_CGM_HOLD_EN ( BIT(5) ) +#define BIT_PD_CA53_TOP_CMG_HOLD_EN ( BIT(4) ) +#define BIT_PD_CA53_C3_CMG_HOLD_EN ( BIT(3) ) +#define BIT_PD_CA53_C2_CMG_HOLD_EN ( BIT(2) ) +#define BIT_PD_CA53_C1_CMG_HOLD_EN ( BIT(1) ) +#define BIT_PD_CA53_C0_CMG_HOLD_EN ( BIT(0) ) +#define BIT_PD_CA7_TOP_CMG_HOLD_EN BIT_PD_CA53_TOP_CMG_HOLD_EN +#define BIT_PD_CA7_C3_CMG_HOLD_EN BIT_PD_CA53_C3_CMG_HOLD_EN +#define BIT_PD_CA7_C2_CMG_HOLD_EN BIT_PD_CA53_C2_CMG_HOLD_EN +#define BIT_PD_CA7_C1_CMG_HOLD_EN BIT_PD_CA53_C1_CMG_HOLD_EN +#define BIT_PD_CA7_C0_CMG_HOLD_EN BIT_PD_CA53_C0_CMG_HOLD_EN + +/* bits definitions for register REG_PMU_APB_PWR_CNT_WAIT_CFG0 */ +#define BITS_VCP0_PWR_WAIT_CNT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_CP1_PWR_WAIT_CNT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_CP0_PWR_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_AP_PWR_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_PWR_CNT_WAIT_CFG1 */ +#define BITS_ARM7_PWR_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_VCP1_PWR_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_RC0_REL_CFG */ +#define BIT_RC0_ARM7_SEL ( BIT(5) ) +#define BIT_RC0_VCP1_SEL ( BIT(4) ) +#define BIT_RC0_VCP0_SEL ( BIT(3) ) +#define BIT_RC0_CP1_SEL ( BIT(2) ) +#define BIT_RC0_CP0_SEL ( BIT(1) ) +#define BIT_RC0_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_RC1_REL_CFG */ +#define BIT_RC1_ARM7_SEL ( BIT(5) ) +#define BIT_RC1_VCP1_SEL ( BIT(4) ) +#define BIT_RC1_VCP0_SEL ( BIT(3) ) +#define BIT_RC1_CP1_SEL ( BIT(2) ) +#define BIT_RC1_CP0_SEL ( BIT(1) ) +#define BIT_RC1_AP_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_RC_CNT_WAIT_CFG */ +#define BITS_RC1_WAIT_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_RC0_WAIT_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_PMU_APB_MEM_AUTO_SLP_CFG */ +#define BITS_MEM_AUTO_SLP_EN(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_MEM_AUTO_SD_CFG */ +#define BITS_MEM_AUTO_SD_EN(_X_) (_X_) + +/* bits definitions for register REG_PMU_APB_CP0_PD_SHUTDOWN_CFG */ +#define BIT_PD_CP0_HU3GE_VCP1_SEL ( BIT(20) ) +#define BIT_PD_CP0_TD_VCP1_SEL ( BIT(19) ) +#define BIT_PD_CP0_GSM_0_VCP1_SEL ( BIT(18) ) +#define BIT_PD_CP0_CEVA_0_VCP1_SEL ( BIT(17) ) +#define BIT_PD_CP0_ARM9_1_VCP1_SEL ( BIT(16) ) +#define BIT_PD_CP0_ARM9_0_VCP0_SEL ( BIT(8) ) +#define BIT_PD_CP0_HU3GE_CP0_SEL ( BIT(5) ) +#define BIT_PD_CP0_TD_CP0_SEL ( BIT(4) ) +#define BIT_PD_CP0_GSM_0_CP0_SEL ( BIT(3) ) +#define BIT_PD_CP0_CEVA_0_CP0_SEL ( BIT(2) ) +#define BIT_PD_CP0_ARM9_1_CP0_SEL ( BIT(1) ) +#define BIT_PD_CP0_ARM9_0_CP0_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CP1_PD_SHUTDOWN_CFG */ +#define BIT_PD_CP1_COMWRAP_VCP1_SEL ( BIT(20) ) +#define BIT_PD_CP1_CEVA_VCP1_SEL ( BIT(19) ) +#define BIT_PD_CP1_LTE_P2_VCP1_SEL ( BIT(18) ) +#define BIT_PD_CP1_LTE_P1_VCP1_SEL ( BIT(17) ) +#define BIT_PD_CP1_CA5_VCP1_SEL ( BIT(16) ) +#define BIT_PD_CP1_COMWRAP_CP1_SEL ( BIT(4) ) +#define BIT_PD_CP1_CEVA_CP1_SEL ( BIT(3) ) +#define BIT_PD_CP1_LTE_P2_CP1_SEL ( BIT(2) ) +#define BIT_PD_CP1_LTE_P1_CP1_SEL ( BIT(1) ) +#define BIT_PD_CP1_CA5_CP1_SEL ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_WAKEUP_LOCK_EN0 */ +#define BIT_PD_MM_CODEC_WAKEUP_LOCK_EN ( BIT(30) ) +#define BIT_PD_GPU_C1_WAKEUP_LOCK_EN ( BIT(29) ) +#define BIT_PD_GPU_C0_WAKEUP_LOCK_EN ( BIT(28) ) +#define BIT_PD_CA53_LIT_MP4_WAKEUP_LOCK_EN ( BIT(27) ) +#define BIT_VCP1_SYS_WAKEUP_LOCK_EN ( BIT(26) ) +#define BIT_VCP0_SYS_WAKEUP_LOCK_EN ( BIT(25) ) +#define BIT_CP1_SYS_WAKEUP_LOCK_EN ( BIT(24) ) +#define BIT_CP0_SYS_WAKEUP_LOCK_EN ( BIT(23) ) +#define BIT_AP_SYS_WAKEUP_LOCK_EN ( BIT(22) ) +#define BIT_PD_PUB_SYS_WAKEUP_LOCK_EN ( BIT(21) ) +#define BIT_PD_CP1_COMWRAP_WAKEUP_LOCK_EN ( BIT(20) ) +#define BIT_PD_CP1_CEVA_WAKEUP_LOCK_EN ( BIT(19) ) +#define BIT_PD_CP1_LTE_P2_WAKEUP_LOCK_EN ( BIT(18) ) +#define BIT_PD_CP1_LTE_P1_WAKEUP_LOCK_EN ( BIT(17) ) +#define BIT_PD_CP1_CA5_WAKEUP_LOCK_EN ( BIT(16) ) +#define BIT_PD_CP0_CEVA_1_WAKEUP_LOCK_EN ( BIT(15) ) +#define BIT_PD_CP0_CEVA_0_WAKEUP_LOCK_EN ( BIT(14) ) +#define BIT_PD_CP0_TD_WAKEUP_LOCK_EN ( BIT(13) ) +#define BIT_PD_CP0_GSM_1_WAKEUP_LOCK_EN ( BIT(12) ) +#define BIT_PD_CP0_GSM_0_WAKEUP_LOCK_EN ( BIT(11) ) +#define BIT_PD_CP0_HU3GE_WAKEUP_LOCK_EN ( BIT(10) ) +#define BIT_PD_CP0_ARM9_1_WAKEUP_LOCK_EN ( BIT(9) ) +#define BIT_PD_CP0_ARM9_0_WAKEUP_LOCK_EN ( BIT(8) ) +#define BIT_PD_MM_TOP_WAKEUP_LOCK_EN ( BIT(7) ) +#define BIT_PD_GPU_TOP_WAKEUP_LOCK_EN ( BIT(6) ) +#define BIT_PD_AP_SYS_WAKEUP_LOCK_EN ( BIT(5) ) +#define BIT_PD_CA53_TOP_WAKEUP_LOCK_EN ( BIT(4) ) +#define BIT_PD_CA53_LIT_C3_WAKEUP_LOCK_EN ( BIT(3) ) +#define BIT_PD_CA53_LIT_C2_WAKEUP_LOCK_EN ( BIT(2) ) +#define BIT_PD_CA53_LIT_C1_WAKEUP_LOCK_EN ( BIT(1) ) +#define BIT_PD_CA53_LIT_C0_WAKEUP_LOCK_EN ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_WAKEUP_LOCK_EN1 */ +#define BIT_PD_CA53_BIG_MP4_WAKEUP_LOCK_EN ( BIT(4) ) +#define BIT_PD_CA53_BIG_C3_WAKEUP_LOCK_EN ( BIT(3) ) +#define BIT_PD_CA53_BIG_C2_WAKEUP_LOCK_EN ( BIT(2) ) +#define BIT_PD_CA53_BIG_C1_WAKEUP_LOCK_EN ( BIT(1) ) +#define BIT_PD_CA53_BIG_C0_WAKEUP_LOCK_EN ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_LP_AUTO_CTRL */ +#define BIT_RST_DLY_CFG ( BIT(31) ) +#define BIT_EIC_DEEP_SLEEP_SEL ( BIT(30) ) +#define BIT_EIC_LIGHT_SLEEP_SEL ( BIT(29) ) +#define BIT_REDUN_CFG_3 ( BIT(28) ) +#define BIT_REDUN_CFG_2 ( BIT(27) ) +#define BIT_REDUN_CFG_1 ( BIT(26) ) +#define BIT_REDUN_CFG_0 ( BIT(25) ) +#define BIT_ADB_CTRL_EN_BIG ( BIT(8) ) +#define BIT_ADB_CTRL_EN_LIT ( BIT(7) ) +#define BIT_ACINACTM_CTRL ( BIT(6) ) +#define BIT_ACINACTM_BIG ( BIT(5) ) +#define BIT_ACINACTM_LIT ( BIT(4) ) +#define BIT_NIC_LP_CTRL_DISABLE ( BIT(3) ) +#define BIT_CA53_BIG_AUTO_CLK_CTRL_DISABLE ( BIT(2) ) +#define BIT_CA53_LIT_AUTO_CLK_CTRL_DISABLE ( BIT(1) ) +#define BIT_DAP_CA53_CCI_EN ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CA53_LIT_C0_INT_DISABLE */ +#define BIT_CA53_LIT_C0_INT_DISABLE ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CA53_LIT_C1_INT_DISABLE */ +#define BIT_CA53_LIT_C1_INT_DISABLE ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CA53_LIT_C2_INT_DISABLE */ +#define BIT_CA53_LIT_C2_INT_DISABLE ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CA53_LIT_C3_INT_DISABLE */ +#define BIT_CA53_LIT_C3_INT_DISABLE ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CA53_BIG_C0_INT_DISABLE */ +#define BIT_CA53_BIG_C0_INT_DISABLE ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CA53_BIG_C1_INT_DISABLE */ +#define BIT_CA53_BIG_C1_INT_DISABLE ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CA53_BIG_C2_INT_DISABLE */ +#define BIT_CA53_BIG_C2_INT_DISABLE ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_CA53_BIG_C3_INT_DISABLE */ +#define BIT_CA53_BIG_C3_INT_DISABLE ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_PUB_ACC_RDY */ +#define BIT_PUB_ACC_RDY ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_PUB_CLK_RDY */ +#define BIT_PUB_CLK_RDY ( BIT(0) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_LIT_C0_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CA53_LIT_C0_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_LIT_C1_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CA53_LIT_C1_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_LIT_C2_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CA53_LIT_C2_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_LIT_C3_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CA53_LIT_C3_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_TOP_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CA53_TOP_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_AP_SYS_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_AP_SYS_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_GPU_TOP_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_GPU_TOP_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_MM_TOP_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_MM_TOP_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_0_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_ARM9_0_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_1_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_ARM9_1_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_CEVA_0_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_CEVA_0_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_CEVA_1_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_CEVA_1_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_GSM_0_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_GSM_0_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_GSM_1_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_GSM_1_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_TD_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_TD_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP0_HU3GE_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP0_HU3GE_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_CA5_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP1_CA5_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_CEVA_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP1_CEVA_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_LTE_P1_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP1_LTE_P1_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_LTE_P2_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP1_LTE_P2_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CP1_COMWRAP_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CP1_COMWRAP_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_PUB_SYS_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_PUB_SYS_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_GPU_C0_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_GPU_C0_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_GPU_C1_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_GPU_C1_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_LIT_MP4_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CA53_LIT_MP4_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_BIG_C0_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CA53_BIG_C0_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_BIG_C1_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CA53_BIG_C1_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_BIG_C2_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CA53_BIG_C2_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_BIG_C3_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CA53_BIG_C3_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_CA53_BIG_MP4_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_CA53_BIG_MP4_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_PMU_APB_PD_MM_CODEC_SHUTDOWN_MARK_STATUS */ +#define BITS_PD_MM_CODEC_SHUTDOWN_MARK(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_pub_apb.h b/include/soc/sprd/chip_x35lt8/__regs_pub_apb.h new file mode 100644 index 00000000..f018b7dd --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_pub_apb.h @@ -0,0 +1,479 @@ +/* the head file modifier: g 2015-03-19 15:50:04*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_PUB_APB_HEADFILE_H__ +#define __H_REGS_PUB_APB_HEADFILE_H__ __FILE__ + +#define REGS_PUB_APB + +/* registers definitions for PUB_APB */ +#define REG_PUB_APB_BUSMON_CNT_START SCI_ADDR(REGS_PUB_APB_BASE, 0x0000) +#define REG_PUB_APB_BUSMON_CFG SCI_ADDR(REGS_PUB_APB_BASE, 0x0004) +#define REG_PUB_APB_DDR_EB SCI_ADDR(REGS_PUB_APB_BASE, 0x0008) +#define REG_PUB_APB_DDR_SOFT_RST SCI_ADDR(REGS_PUB_APB_BASE, 0x000C) +#define REG_PUB_APB_DDR_QOS_CFG1 SCI_ADDR(REGS_PUB_APB_BASE, 0x0010) +#define REG_PUB_APB_DDR_QOS_CFG2 SCI_ADDR(REGS_PUB_APB_BASE, 0x0014) +#define REG_PUB_APB_DDR_QOS_CFG3 SCI_ADDR(REGS_PUB_APB_BASE, 0x0018) +#define REG_PUB_APB_DDR_MRR_STATUS SCI_ADDR(REGS_PUB_APB_BASE, 0x001C) +#define REG_PUB_APB_DDR_ID2QOS_SEL SCI_ADDR(REGS_PUB_APB_BASE, 0x003C) +#define REG_PUB_APB_DDR_ID2QOS_RCFG0 SCI_ADDR(REGS_PUB_APB_BASE, 0x0040) +#define REG_PUB_APB_DDR_ID2QOS_RCFG1 SCI_ADDR(REGS_PUB_APB_BASE, 0x0044) +#define REG_PUB_APB_DDR_ID2QOS_RCFG2 SCI_ADDR(REGS_PUB_APB_BASE, 0x0048) +#define REG_PUB_APB_DDR_ID2QOS_RCFG3 SCI_ADDR(REGS_PUB_APB_BASE, 0x004c) +#define REG_PUB_APB_DDR_ID2QOS_RCFG4 SCI_ADDR(REGS_PUB_APB_BASE, 0x0050) +#define REG_PUB_APB_DDR_ID2QOS_RCFG5 SCI_ADDR(REGS_PUB_APB_BASE, 0x0054) +#define REG_PUB_APB_DDR_ID2QOS_RCFG6 SCI_ADDR(REGS_PUB_APB_BASE, 0x0058) +#define REG_PUB_APB_DDR_ID2QOS_RCFG7 SCI_ADDR(REGS_PUB_APB_BASE, 0x005c) +#define REG_PUB_APB_DDR_ID2QOS_RCFG8 SCI_ADDR(REGS_PUB_APB_BASE, 0x0060) +#define REG_PUB_APB_DDR_ID2QOS_RCFG9 SCI_ADDR(REGS_PUB_APB_BASE, 0x0064) +#define REG_PUB_APB_DDR_ID2QOS_WCFG0 SCI_ADDR(REGS_PUB_APB_BASE, 0x0080) +#define REG_PUB_APB_DDR_ID2QOS_WCFG1 SCI_ADDR(REGS_PUB_APB_BASE, 0x0084) +#define REG_PUB_APB_DDR_ID2QOS_WCFG2 SCI_ADDR(REGS_PUB_APB_BASE, 0x0088) +#define REG_PUB_APB_DDR_ID2QOS_WCFG3 SCI_ADDR(REGS_PUB_APB_BASE, 0x008c) +#define REG_PUB_APB_DDR_ID2QOS_WCFG4 SCI_ADDR(REGS_PUB_APB_BASE, 0x0090) +#define REG_PUB_APB_DDR_ID2QOS_WCFG5 SCI_ADDR(REGS_PUB_APB_BASE, 0x0094) +#define REG_PUB_APB_DDR_ID2QOS_WCFG6 SCI_ADDR(REGS_PUB_APB_BASE, 0x0098) +#define REG_PUB_APB_DDR_ID2QOS_WCFG7 SCI_ADDR(REGS_PUB_APB_BASE, 0x009c) +#define REG_PUB_APB_DDR_ID2QOS_WCFG8 SCI_ADDR(REGS_PUB_APB_BASE, 0x00a0) +#define REG_PUB_APB_DDR_ID2QOS_WCFG9 SCI_ADDR(REGS_PUB_APB_BASE, 0x00a4) +#define REG_PUB_APB_DFI_TIMEOUT_CFG SCI_ADDR(REGS_PUB_APB_BASE, 0x0100) +#define REG_PUB_APB_DFI_TIMEOUT_STATUS SCI_ADDR(REGS_PUB_APB_BASE, 0x0104) +#define REG_PUB_APB_DFI_TIMEOUT_EN_CNT SCI_ADDR(REGS_PUB_APB_BASE, 0x0108) +#define REG_PUB_APB_DFI_TIMEOUT_VALID_CNT SCI_ADDR(REGS_PUB_APB_BASE, 0x010c) +#define REG_PUB_APB_DMC_PORT_REMAP_EN SCI_ADDR(REGS_PUB_APB_BASE, 0x3000) +#define REG_PUB_APB_DMC_PORTS_MPU_EN SCI_ADDR(REGS_PUB_APB_BASE, 0x3004) +#define REG_PUB_APB_DMC_PORT0_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3008) +#define REG_PUB_APB_DMC_PORT1_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x300C) +#define REG_PUB_APB_DMC_PORT2_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3010) +#define REG_PUB_APB_DMC_PORT3_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3014) +#define REG_PUB_APB_DMC_PORT4_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3018) +#define REG_PUB_APB_DMC_PORT5_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x301C) +#define REG_PUB_APB_DMC_PORT6_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3020) +#define REG_PUB_APB_DMC_PORT7_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3024) +#define REG_PUB_APB_DMC_PORT8_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3028) +#define REG_PUB_APB_DMC_PORT9_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x302C) +#define REG_PUB_APB_DMC_PORT0_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3030) +#define REG_PUB_APB_DMC_PORT1_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3034) +#define REG_PUB_APB_DMC_PORT2_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3038) +#define REG_PUB_APB_DMC_PORT3_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x303C) +#define REG_PUB_APB_DMC_PORT4_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3040) +#define REG_PUB_APB_DMC_PORT5_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3044) +#define REG_PUB_APB_DMC_PORT6_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3048) +#define REG_PUB_APB_DMC_PORT7_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3050) +#define REG_PUB_APB_DMC_PORT8_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3054) +#define REG_PUB_APB_DMC_PORT9_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3058) +#define REG_PUB_APB_DMC_PORT0_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x305C) +#define REG_PUB_APB_DMC_PORT1_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3060) +#define REG_PUB_APB_DMC_PORT2_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3064) +#define REG_PUB_APB_DMC_PORT3_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3068) +#define REG_PUB_APB_DMC_PORT4_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x306C) +#define REG_PUB_APB_DMC_PORT5_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3070) +#define REG_PUB_APB_DMC_PORT6_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3074) +#define REG_PUB_APB_DMC_PORT7_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3078) +#define REG_PUB_APB_DMC_PORT8_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x307C) +#define REG_PUB_APB_DMC_PORT9_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3080) + + + +/* bits definitions for register REG_MM_AHB_RF_BUSMON_CNT_START */ +#define BIT_PUB_BUSMON_CNT_START ( BIT(0) ) + +/* bits definitions for register REG_MM_AHB_RF_BUSMON_CFG */ +#define BIT_PUB_BUSMON9_EB ( BIT(25) ) +#define BIT_PUB_BUSMON8_EB ( BIT(24) ) +#define BIT_PUB_BUSMON7_EB ( BIT(23) ) +#define BIT_PUB_BUSMON6_EB ( BIT(22) ) +#define BIT_PUB_BUSMON5_EB ( BIT(21) ) +#define BIT_PUB_BUSMON4_EB ( BIT(20) ) +#define BIT_PUB_BUSMON3_EB ( BIT(19) ) +#define BIT_PUB_BUSMON2_EB ( BIT(18) ) +#define BIT_PUB_BUSMON1_EB ( BIT(17) ) +#define BIT_PUB_BUSMON0_EB ( BIT(16) ) +#define BIT_PUB_BUSMON9_SOFT_RST ( BIT(9) ) +#define BIT_PUB_BUSMON8_SOFT_RST ( BIT(8) ) +#define BIT_PUB_BUSMON7_SOFT_RST ( BIT(7) ) +#define BIT_PUB_BUSMON6_SOFT_RST ( BIT(6) ) +#define BIT_PUB_BUSMON5_SOFT_RST ( BIT(5) ) +#define BIT_PUB_BUSMON4_SOFT_RST ( BIT(4) ) +#define BIT_PUB_BUSMON3_SOFT_RST ( BIT(3) ) +#define BIT_PUB_BUSMON2_SOFT_RST ( BIT(2) ) +#define BIT_PUB_BUSMON1_SOFT_RST ( BIT(1) ) +#define BIT_PUB_BUSMON0_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_EB */ + +/* bits definitions for register REG_MM_AHB_RF_DDR_SOFT_RST */ + +/* bits definitions for register REG_MM_AHB_RF_DDR_QOS_CFG1 */ +#define BITS_DMC_ARQOS_3(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_3(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_2(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_2(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_1(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_0(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_QOS_CFG2 */ +#define BITS_DMC_ARQOS_7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_7(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_6(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_6(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_5(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_5(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_4(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_QOS_CFG3 */ +#define BITS_DMC_ARQOS_9(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_9(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_8(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_8(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_MRR_STATUS */ +#define BIT_DDRC_CO_RD_MRR_DATA_VALID ( BIT(8) ) +#define BITS_DDRC_CO_RD_MRR_DATA(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_SEL */ +#define BITS_DMC_ID_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) ) +#define BITS_DMC_QOS_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_RCFG0 */ +#define BITS_DMC_ARQOS_0_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_0_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_0_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_0_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_0_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_0_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_0_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_0_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_RCFG1 */ +#define BITS_DMC_ARQOS_1_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_1_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_1_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_1_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_1_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_1_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_1_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_1_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_RCFG2 */ +#define BITS_DMC_ARQOS_2_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_2_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_2_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_2_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_2_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_2_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_2_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_2_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_RCFG3 */ +#define BITS_DMC_ARQOS_3_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_3_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_3_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_3_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_3_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_3_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_3_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_3_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_RCFG4 */ +#define BITS_DMC_ARQOS_4_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_4_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_4_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_4_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_4_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_4_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_4_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_4_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_RCFG5 */ +#define BITS_DMC_ARQOS_5_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_5_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_5_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_5_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_5_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_5_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_5_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_5_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_RCFG6 */ +#define BITS_DMC_ARQOS_6_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_6_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_6_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_6_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_6_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_6_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_6_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_6_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_RCFG7 */ +#define BITS_DMC_ARQOS_7_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_7_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_7_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_7_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_7_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_7_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_7_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_7_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_RCFG8 */ +#define BITS_DMC_ARQOS_8_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_8_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_8_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_8_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_8_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_8_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_8_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_8_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_RCFG9 */ +#define BITS_DMC_ARQOS_9_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_ARQOS_9_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_ARQOS_9_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_ARQOS_9_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_ARQOS_9_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_ARQOS_9_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_ARQOS_9_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_ARQOS_9_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_WCFG0 */ +#define BITS_DMC_AWQOS_0_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_0_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_0_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_0_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_0_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_0_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_0_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_0_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_WCFG1 */ +#define BITS_DMC_AWQOS_1_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_1_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_1_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_1_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_1_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_1_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_1_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_1_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_WCFG2 */ +#define BITS_DMC_AWQOS_2_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_2_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_2_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_2_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_2_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_2_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_2_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_2_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_WCFG3 */ +#define BITS_DMC_AWQOS_3_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_3_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_3_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_3_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_3_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_3_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_3_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_3_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_WCFG4 */ +#define BITS_DMC_AWQOS_4_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_4_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_4_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_4_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_4_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_4_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_4_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_4_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_WCFG5 */ +#define BITS_DMC_AWQOS_5_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_5_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_5_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_5_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_5_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_5_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_5_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_5_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_WCFG6 */ +#define BITS_DMC_AWQOS_6_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_6_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_6_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_6_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_6_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_6_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_6_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_6_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_WCFG7 */ +#define BITS_DMC_AWQOS_7_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_7_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_7_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_7_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_7_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_7_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_7_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_7_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_WCFG8 */ +#define BITS_DMC_AWQOS_8_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_8_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_8_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_8_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_8_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_8_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_8_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_8_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DDR_ID2QOS_WCFG9 */ +#define BITS_DMC_AWQOS_9_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DMC_AWQOS_9_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) ) +#define BITS_DMC_AWQOS_9_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DMC_AWQOS_9_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) +#define BITS_DMC_AWQOS_9_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DMC_AWQOS_9_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) ) +#define BITS_DMC_AWQOS_9_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DMC_AWQOS_9_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DFI_TIMEOUT_CFG */ +#define BITS_DFI_TIMEOUT_THRESHOLD(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DFI_TIMEOUT_CLR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BITS_DFI_TIMEOUT_EN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DFI_TIMEOUT_STATUS */ +#define BITS_DFI_TIMEOUT_STATUS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) ) + +/* bits definitions for register REG_MM_AHB_RF_DFI_TIMEOUT_EN_CNT */ +#define BITS_DFI_TIMEOUT_EN3_CNT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DFI_TIMEOUT_EN2_CNT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DFI_TIMEOUT_EN1_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DFI_TIMEOUT_EN0_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_MM_AHB_RF_DFI_TIMEOUT_VALID_CNT */ +#define BITS_DFI_TIMEOUT_VALID3_CNT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BITS_DFI_TIMEOUT_VALID2_CNT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BITS_DFI_TIMEOUT_VALID1_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BITS_DFI_TIMEOUT_VALID0_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT_REMAP_EN */ +#define BITS_DMC_PORTS_REMAP_EN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORTS_MPU_EN */ +#define BITS_DMC_PORTS_MPU_EN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) ) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT0_ADDR_REMAP */ +#define BITS_DMC_PORT0_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT1_ADDR_REMAP */ +#define BITS_DMC_PORT1_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT2_ADDR_REMAP */ +#define BITS_DMC_PORT2_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT3_ADDR_REMAP */ +#define BITS_DMC_PORT3_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT4_ADDR_REMAP */ +#define BITS_DMC_PORT4_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT5_ADDR_REMAP */ +#define BITS_DMC_PORT5_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT6_ADDR_REMAP */ +#define BITS_DMC_PORT6_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT7_ADDR_REMAP */ +#define BITS_DMC_PORT7_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT8_ADDR_REMAP */ +#define BITS_DMC_PORT8_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT9_ADDR_REMAP */ +#define BITS_DMC_PORT9_ADDR_REMAP(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT0_MPU_RANGE */ +#define BITS_DMC_PORT0_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT1_MPU_RANGE */ +#define BITS_DMC_PORT1_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT2_MPU_RANGE */ +#define BITS_DMC_PORT2_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT3_MPU_RANGE */ +#define BITS_DMC_PORT3_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT4_MPU_RANGE */ +#define BITS_DMC_PORT4_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT5_MPU_RANGE */ +#define BITS_DMC_PORT5_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT6_MPU_RANGE */ +#define BITS_DMC_PORT6_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT7_MPU_RANGE */ +#define BITS_DMC_PORT7_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT8_MPU_RANGE */ +#define BITS_DMC_PORT8_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT9_MPU_RANGE */ +#define BITS_DMC_PORT9_MPU_RANGE(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT0_DUMP_ADDR */ +#define BITS_DMC_PORT0_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT1_DUMP_ADDR */ +#define BITS_DMC_PORT1_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT2_DUMP_ADDR */ +#define BITS_DMC_PORT2_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT3_DUMP_ADDR */ +#define BITS_DMC_PORT3_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT4_DUMP_ADDR */ +#define BITS_DMC_PORT4_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT5_DUMP_ADDR */ +#define BITS_DMC_PORT5_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT6_DUMP_ADDR */ +#define BITS_DMC_PORT6_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT7_DUMP_ADDR */ +#define BITS_DMC_PORT7_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT8_DUMP_ADDR */ +#define BITS_DMC_PORT8_DUMP_ADDR(_X_) (_X_) + +/* bits definitions for register REG_MM_AHB_RF_DMC_PORT9_DUMP_ADDR */ +#define BITS_DMC_PORT9_DUMP_ADDR(_X_) (_X_) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_wcdma_ahb_rf.h b/include/soc/sprd/chip_x35lt8/__regs_wcdma_ahb_rf.h new file mode 100644 index 00000000..84cfa532 --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_wcdma_ahb_rf.h @@ -0,0 +1,125 @@ +/* the head file modifier: g 2015-03-19 17:11:11*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_WCDMA_AHB_RF_HEADFILE_H__ +#define __H_REGS_WCDMA_AHB_RF_HEADFILE_H__ __FILE__ + +#define REGS_WCDMA_AHB_RF + +/* registers definitions for WCDMA_AHB_RF */ +#define REG_WCDMA_AHB_RF_AHB_EB0 SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0000)/*AHB_EB0*/ +#define REG_WCDMA_AHB_RF_AHB_RST0 SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0004)/*AHB_RST0*/ +#define REG_WCDMA_AHB_RF_ARCH_EB_REG SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0018)/*ARCH_EB_REG*/ +#define REG_WCDMA_AHB_RF_AHB_REMAP SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x001C)/*AHB_REMAP*/ +#define REG_WCDMA_AHB_RF_AHB_MISC_CTL SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0020)/*AHB_MISC_CTL*/ +#define REG_WCDMA_AHB_RF_AHB_MTX_PRI_SEL0 SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0024)/*AHB_MTX_PRI_SEL0*/ +#define REG_WCDMA_AHB_RF_AHB_MTX_PRI_SEL1 SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0028)/*AHB_MTX_PRI_SEL1*/ +#define REG_WCDMA_AHB_RF_AHB1_PAUSE SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x002C)/*AHB1_PAUSE*/ +#define REG_WCDMA_AHB_RF_AHB_SLP_CTL SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0034)/*AHB_SLP_CTL*/ +#define REG_WCDMA_AHB_RF_AHB2_SLP_STS SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0038)/*AHB2_SLP_STS*/ +#define REG_WCDMA_AHB_RF_MCU_CLK_CTL SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x003C)/*MCU_CLK_CTL*/ +#define REG_WCDMA_AHB_RF_CHIP_ID SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x01FC)/*CHIP_ID*/ + + + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB_EB0 */ +#define BITS_WCDMA_EN(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) ) +#define BIT_BUSMON0_EN ( BIT(1) ) +#define BIT_SPINLOCK_EN ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB_RST0 */ +#define BIT_WCDMA_SOFT_RST ( BIT(3) ) +#define BIT_BUSMON0_SOFT_RST ( BIT(1) ) +#define BIT_SPINLOCK_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_ARCH_EB_REG */ +#define BIT_AHB_ARCH_EB ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB_REMAP */ +#define BIT_ARM_JTAG_EN_ARM1 ( BIT(1) ) +#define BIT_REMAP ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB_MISC_CTL */ +#define BIT_FORCE_WSYS_ACC_STOP ( BIT(3) ) +#define BIT_W_DMA_LSLP_EN ( BIT(2) ) +#define BIT_BUSMON0_SEL ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB_MTX_PRI_SEL0 */ +#define BITS_ARMMTX_M3TOS0_RND_THR(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) ) +#define BIT_ARMMTX_M3TOS0_ADJ_EN ( BIT(27) ) +#define BIT_ARMMTX_M3TOS0_RND_EN ( BIT(26) ) +#define BITS_ARMMTX_M3TOS0_SEL(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)) ) +#define BITS_ARMMTX_M2TOS0_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M2TOS0_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M2TOS0_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M2TOS0_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M1TOS0_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M1TOS0_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M1TOS0_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M1TOS0_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M0TOS0_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M0TOS0_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M0TOS0_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M0TOS0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB_MTX_PRI_SEL1 */ +#define BITS_ARMMTX_M6TOS0_RND_THR(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) ) +#define BIT_ARMMTX_M6TOS0_ADJ_EN ( BIT(19) ) +#define BIT_ARMMTX_M6TOS0_RND_EN ( BIT(18) ) +#define BITS_ARMMTX_M6TOS0_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) ) +#define BITS_ARMMTX_M5TOS0_RND_THR(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ) +#define BIT_ARMMTX_M5TOS0_ADJ_EN ( BIT(11) ) +#define BIT_ARMMTX_M5TOS0_RND_EN ( BIT(10) ) +#define BITS_ARMMTX_M5TOS0_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) ) +#define BITS_ARMMTX_M4TOS0_RND_THR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) ) +#define BIT_ARMMTX_M4TOS0_ADJ_EN ( BIT(3) ) +#define BIT_ARMMTX_M4TOS0_RND_EN ( BIT(2) ) +#define BITS_ARMMTX_M4TOS0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB1_PAUSE */ +#define BIT_APB1_SLEEP ( BIT(3) ) +#define BIT_MCU1_DEEP_SLEEP_EN ( BIT(2) ) +#define BIT_MCU1_SYS_SLEEP_EN ( BIT(1) ) +#define BIT_MCU1_CORE_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB_SLP_CTL */ +#define BIT_MCUMTX_AUTO_GATE_EN ( BIT(4) ) +#define BIT_MCU_AUTO_GATE_EN ( BIT(3) ) +#define BIT_AHB_AUTO_GATE_EN ( BIT(2) ) +#define BIT_ARM1_AUTO_GATE_EN ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_AHB2_SLP_STS */ +#define BIT_APB1_PERI_SLEEP ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_MCU_CLK_CTL */ +#define BITS_CLK_AHB_DIV(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) ) +#define BITS_CLK_MCU_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) ) +#define BITS_CLK_APB_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) ) +#define BITS_CLK_MCU_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_WCDMA_AHB_RF_CHIP_ID */ +#define BITS_CHIP_ID(_X_) (_X_) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__regs_wcdma_apb_rf.h b/include/soc/sprd/chip_x35lt8/__regs_wcdma_apb_rf.h new file mode 100644 index 00000000..ae6e1ba6 --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__regs_wcdma_apb_rf.h @@ -0,0 +1,79 @@ +/* the head file modifier: g 2015-03-19 15:46:40*/ + +/* +* Copyright (C) 2013 Spreadtrum Communications Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License +* as published by the Free Software Foundation; either version 2 +* of the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +************************************************* +* Automatically generated C header: do not edit * +************************************************* +*/ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, Pls include sci_glb_regs.h" +#endif + + +#ifndef __H_REGS_WCDMA_APB_RF_HEADFILE_H__ +#define __H_REGS_WCDMA_APB_RF_HEADFILE_H__ __FILE__ + +#define REGS_WCDMA_APB_RF + +/* registers definitions for WCDMA_APB_RF */ +#define REG_WCDMA_APB_RF_APB_EB SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0000)/*APB_EB*/ +#define REG_WCDMA_APB_RF_APB_RST SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0004)/*APB_RST*/ +#define REG_WCDMA_APB_RF_APB_SLEEP_ST SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0008)/*APB_SLEEP_ST*/ +#define REG_WCDMA_APB_RF_APB_MCU_RST SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0018)/*APB_MCU_RST*/ +#define REG_WCDMA_APB_RF_APB_CLK_SEL0 SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x001C)/*APB_CLK_SEL0*/ +#define REG_WCDMA_APB_RF_APB_CLK_DIV0 SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0020)/*APB_CLK_DIV0*/ +#define REG_WCDMA_APB_RF_APB_ARCH_EB SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0024)/*APB_ARCH_EB*/ +#define REG_WCDMA_APB_RF_APB_SLP_CTL SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0028)/*APB_SLP_CTL*/ + + + +/* bits definitions for register REG_WCDMA_APB_RF_APB_EB */ +#define BIT_TMR_RTC_EB ( BIT(6) ) +#define BIT_TMR_EB ( BIT(5) ) +#define BIT_SYSTMR_RTC_EB ( BIT(4) ) +#define BIT_SYSTMR_EB ( BIT(3) ) +#define BIT_UART0_EB ( BIT(2) ) +#define BIT_WDG_RTC_EB ( BIT(1) ) +#define BIT_WDG_EB ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_APB_RF_APB_RST */ +#define BIT_TMR_SOFT_RST ( BIT(3) ) +#define BIT_SYSTMR_SOFT_RST ( BIT(2) ) +#define BIT_UART0_SOFT_RST ( BIT(1) ) +#define BIT_WDG_SOFT_RST ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_APB_RF_APB_SLEEP_ST */ +#define BIT_CHIP_SLEEP_REC_CLR ( BIT(1) ) +#define BIT_CHIP_SLEEP_REC ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_APB_RF_APB_MCU_RST */ +#define BIT_MCU_SOFT_RST_SET ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_APB_RF_APB_CLK_SEL0 */ +#define BITS_CLK_UART0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) ) + +/* bits definitions for register REG_WCDMA_APB_RF_APB_CLK_DIV0 */ +#define BITS_CLK_UART0_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) ) + +/* bits definitions for register REG_WCDMA_APB_RF_APB_ARCH_EB */ +#define BIT_RTC_ARCH_EB ( BIT(1) ) +#define BIT_APB_ARCH_EB ( BIT(0) ) + +/* bits definitions for register REG_WCDMA_APB_RF_APB_SLP_CTL */ +#define BIT_APB_PERI_FRC_ON ( BIT(1) ) +#define BIT_APB_PERI_FRC_SLP ( BIT(0) ) + +#endif diff --git a/include/soc/sprd/chip_x35lt8/__sc2723_regulator_map.h b/include/soc/sprd/chip_x35lt8/__sc2723_regulator_map.h new file mode 100644 index 00000000..7879ec63 --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__sc2723_regulator_map.h @@ -0,0 +1,128 @@ +/* + * Copyright (C) 2013 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +/* + * Regulator (0)Name, Regulator (1)Type, Power Off (2)Ctrl and (3)Bit, PWR_SEL (4) and (5) Bit, + * Voltage Trimming (6)Ctrl and (7)Bits, Calibration (8)Ctrl and (9)Bits, + * Voltage (10)Default, Voltage (11)Ctrl and (12)Bits, Voltage Select (13)Count and Voltage (14)List[ ... ...] + */ + + SCI_REGU_REG(vddcore, 0x12, ANA_REG_GLB_LDO_DCDC_PD, BIT(9), ANA_REG_GLB_PWR_SEL, BIT(0), + ANA_REG_GLB_DCDC_CORE_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_DCDC_CTRL15, BIT(14)|BIT(16)|BIT(18)|BIT(19), + 900, ANA_REG_GLB_DCDC_CORE_ADI, BIT(5)|BIT(6)|BIT(7), 8, 1100, 700, 800, 900, 1000, 650, 1200, 1300); + + SCI_REGU_REG(vddarm, 0x12, ANA_REG_GLB_LDO_DCDC_PD, BIT(10), ANA_REG_GLB_PWR_SEL, BIT(2), + ANA_REG_GLB_DCDC_ARM_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_DCDC_CTRL15, BIT(13)|BIT(16)|BIT(18)|BIT(19), + 900, ANA_REG_GLB_DCDC_ARM_ADI, BIT(5)|BIT(6)|BIT(7), 8, 1100, 700, 800, 900, 1000, 650, 1200, 1300); + + SCI_REGU_REG(vddmem, 0x12, ANA_REG_GLB_LDO_DCDC_PD, BIT(11), ANA_REG_GLB_PWR_SEL, BIT(3), + ANA_REG_GLB_DCDC_MEM_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_DCDC_CTRL15, BIT(13)|BIT(14)|BIT(16)|BIT(18)|BIT(19), + 1200, 0, 0, 2, 600, 3125); + + SCI_REGU_REG(vddgen, 0x12, ANA_REG_GLB_LDO_DCDC_PD, BIT(12), ANA_REG_GLB_PWR_SEL, BIT(4), + ANA_REG_GLB_DCDC_GEN_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_DCDC_CTRL15, BIT(15)|BIT(16)|BIT(18)|BIT(19), + 2400, 0, 0, 2, 600, 3125); + + SCI_REGU_REG(vddrf, 0x12, ANA_REG_GLB_LDO_DCDC_PD, BIT(13), ANA_REG_GLB_PWR_SEL, BIT(5), + ANA_REG_GLB_DCDC_RF_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_DCDC_CTRL15, BIT(13)|BIT(15)|BIT(16)|BIT(18)|BIT(19), + 1500, 0, 0, 2, 600, 3125); + + SCI_REGU_REG(vddcon, 0x2, ANA_REG_GLB_LDO_PD_CTRL, BIT(13), 0, 0, + ANA_REG_GLB_DCDC_CON_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_DCDC_CTRL15, BIT(14)|BIT(15)|BIT(16)|BIT(18)|BIT(19), + 1600, 0, 0, 2, 600, 3125); + + SCI_REGU_REG(vddwpa, 0x2, ANA_REG_GLB_LDO_PD_CTRL, BIT(14), 0, 0, + ANA_REG_GLB_DCDC_WPA_ADI, BIT(0)|BIT(1)|BIT(2), ANA_REG_GLB_DCDC_CTRL15, BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(18)|BIT(19), + 0, 0, 0, 0); + + SCI_REGU_REG(vddrf0, 0x10, ANA_REG_GLB_LDO_DCDC_PD, BIT(8), ANA_REG_GLB_PWR_SEL, BIT(11), + ANA_REG_GLB_LDO_V_CTRL0, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), ANA_REG_GLB_LDO_V_CTRL11, BIT(2)|BIT(16)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1150, 6250); + + SCI_REGU_REG(vddemmccore, 0x10, ANA_REG_GLB_LDO_DCDC_PD, BIT(7), ANA_REG_GLB_PWR_SEL, BIT(7), + ANA_REG_GLB_LDO_V_CTRL7, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), ANA_REG_GLB_LDO_V_CTRL11, BIT(5)|BIT(6)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 3000, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddgen1, 0x10, ANA_REG_GLB_LDO_DCDC_PD, BIT(6), ANA_REG_GLB_PWR_SEL, BIT(12), + ANA_REG_GLB_LDO_V_CTRL3, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_V_CTRL11, BIT(0)|BIT(2)|BIT(16)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1150, 6250); + + SCI_REGU_REG(vddgen0, 0x10, ANA_REG_GLB_LDO_DCDC_PD, BIT(4), ANA_REG_GLB_PWR_SEL, BIT(13), + ANA_REG_GLB_LDO_V_CTRL2, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6), ANA_REG_GLB_LDO_V_CTRL11, BIT(1)|BIT(2)|BIT(16)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1150, 6250); + + SCI_REGU_REG(vdddcxo, 0x10, ANA_REG_GLB_LDO_DCDC_PD, BIT(5), ANA_REG_GLB_PWR_SEL, BIT(8), + ANA_REG_GLB_LDO_V_CTRL8, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), ANA_REG_GLB_LDO_V_CTRL11, BIT(7)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vdd25, 0x10, ANA_REG_GLB_LDO_DCDC_PD, BIT(3), ANA_REG_GLB_PWR_SEL, BIT(6), + ANA_REG_GLB_LDO_V_CTRL10, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_LDO_V_CTRL11, BIT(8)|BIT(17)|BIT(18)|BIT(20), + 2800, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vdd28, 0x10, ANA_REG_GLB_LDO_DCDC_PD, BIT(2), ANA_REG_GLB_PWR_SEL, BIT(9), + ANA_REG_GLB_LDO_V_CTRL3, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_LDO_V_CTRL11, BIT(6)|BIT(7)|BIT(10)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 2800, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vdd18, 0x10, ANA_REG_GLB_LDO_DCDC_PD, BIT(1), ANA_REG_GLB_PWR_SEL, BIT(10), + ANA_REG_GLB_LDO_V_CTRL9, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_V_CTRL11, BIT(0)|BIT(16)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1150, 6250); + + SCI_REGU_REG(vddwifipa, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(11), 0, 0, + ANA_REG_GLB_LDO_V_CTRL0, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_LDO_V_CTRL11, BIT(5)|BIT(10)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 3300, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddsdcore, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(10), 0, 0, + ANA_REG_GLB_LDO_V_CTRL6, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), ANA_REG_GLB_LDO_V_CTRL11, BIT(5)|BIT(7)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 3000, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddsdio, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(0), 0, 0, + ANA_REG_GLB_LDO_V_CTRL4, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_LDO_V_CTRL11, BIT(3)|BIT(16)|BIT(18)|BIT(19)|BIT(20), + 3000, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddsim0, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(1), 0, 0, + ANA_REG_GLB_LDO_V_CTRL4, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), ANA_REG_GLB_LDO_V_CTRL11, BIT(8)|BIT(10)|BIT(17)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddsim1, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(2), 0, 0, + ANA_REG_GLB_LDO_V_CTRL5, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_LDO_V_CTRL11, BIT(10)|BIT(17)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddsim2, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(3), 0, 0, + ANA_REG_GLB_LDO_V_CTRL5, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), ANA_REG_GLB_LDO_V_CTRL11, BIT(8)|BIT(9)|BIT(17)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddcama, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(4), 0, 0, + ANA_REG_GLB_LDO_V_CTRL6, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_LDO_V_CTRL11, BIT(9)|BIT(17)|BIT(18)|BIT(20), + 2800, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddcamd, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(5), 0, 0, + ANA_REG_GLB_LDO_V_CTRL1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6), ANA_REG_GLB_LDO_V_CTRL11, BIT(1)|BIT(16)|BIT(18)|BIT(20), + 1500, 0, 0, 2, 1150, 6250); + + SCI_REGU_REG(vddcamio, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(6), 0, 0, + ANA_REG_GLB_LDO_V_CTRL1, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_V_CTRL11, BIT(0)|BIT(1)|BIT(16)|BIT(18)|BIT(20), + 1800, 0, 0, 2, 1150, 6250); + + SCI_REGU_REG(vddcammot, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(7), 0, 0, + ANA_REG_GLB_LDO_V_CTRL7, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_LDO_V_CTRL11, BIT(6)|BIT(16)|BIT(17)|BIT(18)|BIT(20), + 2800, 0, 0, 2, 1200, 10000); + + SCI_REGU_REG(vddusb, 0x0, ANA_REG_GLB_LDO_PD_CTRL, BIT(8), 0, 0, + ANA_REG_GLB_LDO_V_CTRL9, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7), ANA_REG_GLB_LDO_V_CTRL11, BIT(4)|BIT(16)|BIT(18)|BIT(19)|BIT(20), + 3300, 0, 0, 2, 1200, 10000); + diff --git a/include/soc/sprd/chip_x35lt8/__scx35l_clock_tree.h b/include/soc/sprd/chip_x35lt8/__scx35l_clock_tree.h new file mode 100644 index 00000000..992ad053 --- /dev/null +++ b/include/soc/sprd/chip_x35lt8/__scx35l_clock_tree.h @@ -0,0 +1,557 @@ +/* + * Copyright (C) 2013 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#define REG_0X20E0(_o_) SCI_ADDR(SPRD_AHB_BASE, (_o_)) +#define REG_0X2150(_o_) SCI_ADDR(SPRD_APBCKG_BASE, (_o_)) +#define REG_0X402E(_o_) SCI_ADDR(SPRD_AONAPB_BASE, (_o_)) +#define REG_0X402D(_o_) SCI_ADDR(SPRD_AONCKG_BASE, (_o_)) +#define REG_0X6010(_o_) SCI_ADDR(SPRD_GPUAPB_BASE, (_o_)) +#define REG_0X60D0(_o_) SCI_ADDR(SPRD_MMAHB_BASE, (_o_)) +#define REG_0X60E0(_o_) SCI_ADDR(SPRD_MMCKG_BASE, (_o_)) +#define REG_0X7130(_o_) SCI_ADDR(SPRD_APBREG_BASE, (_o_)) + +#define REG_0X402E0044 REG_0X402E(0x0044) +#define REG_0X402E004C REG_0X402E(0x004C) +#define REG_0X402E005C REG_0X402E(0x005C) +#define REG_0X402E0054 REG_0X402E(0x0054) +#define REG_0X402E0064 REG_0X402E(0x0064) +#define REG_0X20E00038 REG_0X20E0(0x0038) +#define REG_0X20E00054 REG_0X20E0(0x0054) +#define REG_0X402D0020 REG_0X402D(0x0020) +#define REG_0X402D002C REG_0X402D(0x002C) +#define REG_0X402D0030 REG_0X402D(0x0030) +#define REG_0X402E0000 REG_0X402E(0x0000) +#define REG_0X402D0034 REG_0X402D(0x0034) +#define REG_0X402E0004 REG_0X402E(0x0004) +#define REG_0X402D0038 REG_0X402D(0x0038) +#define REG_0X402D003C REG_0X402D(0x003C) +#define REG_0X402D0040 REG_0X402D(0x0040) +#define REG_0X402D0044 REG_0X402D(0x0044) +#define REG_0X402D0048 REG_0X402D(0x0048) +#define REG_0X402D004C REG_0X402D(0x004C) +#define REG_0X402D0050 REG_0X402D(0x0050) +#define REG_0X402D0054 REG_0X402D(0x0054) +#define REG_0X402D0058 REG_0X402D(0x0058) +#define REG_0X402D0068 REG_0X402D(0x0068) +#define REG_0X402D006C REG_0X402D(0x006C) +#define REG_0X402D0070 REG_0X402D(0x0070) +#define REG_0X402D0074 REG_0X402D(0x0074) +#define REG_0X402D0078 REG_0X402D(0x0078) +#define REG_0X402D007C REG_0X402D(0x007C) +#define REG_0X402D0080 REG_0X402D(0x0080) +#define REG_0X402D0090 REG_0X402D(0x0090) +#define REG_0X402D0098 REG_0X402D(0x0098) +#define REG_0X402D00C8 REG_0X402D(0x00C8) +#define REG_0X402D00CC REG_0X402D(0x00CC) +#define REG_0X402D00D0 REG_0X402D(0x00D0) +#define REG_0X21500020 REG_0X2150(0x0020) +#define REG_0X21500024 REG_0X2150(0x0024) +#define REG_0X20E00000 REG_0X20E0(0x0000) +#define REG_0X21500028 REG_0X2150(0x0028) +#define REG_0X2150002C REG_0X2150(0x002C) +#define REG_0X21500030 REG_0X2150(0x0030) +#define REG_0X21500034 REG_0X2150(0x0034) +#define REG_0X21500054 REG_0X2150(0x0054) +#define REG_0X21500058 REG_0X2150(0x0058) +#define REG_0X2150005C REG_0X2150(0x005C) +#define REG_0X21500060 REG_0X2150(0x0060) +#define REG_0X21500068 REG_0X2150(0x0068) +#define REG_0X21500070 REG_0X2150(0x0070) +#define REG_0X21500074 REG_0X2150(0x0074) +#define REG_0X2150007C REG_0X2150(0x007C) +#define REG_0X71300000 REG_0X7130(0x0000) +#define REG_0X21500084 REG_0X2150(0x0084) +#define REG_0X21500088 REG_0X2150(0x0088) +#define REG_0X2150008C REG_0X2150(0x008C) +#define REG_0X21500090 REG_0X2150(0x0090) +#define REG_0X21500094 REG_0X2150(0x0094) +#define REG_0X21500098 REG_0X2150(0x0098) +#define REG_0X2150009C REG_0X2150(0x009C) +#define REG_0X215000A0 REG_0X2150(0x00A0) +#define REG_0X215000A4 REG_0X2150(0x00A4) +#define REG_0X215000A8 REG_0X2150(0x00A8) +#define REG_0X215000AC REG_0X2150(0x00AC) +#define REG_0X215000B0 REG_0X2150(0x00B0) +#define REG_0X215000B4 REG_0X2150(0x00B4) +#define REG_0X215000B8 REG_0X2150(0x00B8) +#define REG_0X215000BC REG_0X2150(0x00BC) +#define REG_0X215000C0 REG_0X2150(0x00C0) +#define REG_0X215000C4 REG_0X2150(0x00C4) +#define REG_0X215000C8 REG_0X2150(0x00C8) +#define REG_0X215000CC REG_0X2150(0x00CC) +#define REG_0X60100020 REG_0X6010(0x0020) +#define REG_0X60E00020 REG_0X60E0(0x0020) +#define REG_0X60D00008 REG_0X60D0(0x0008) +#define REG_0X60D00000 REG_0X60D0(0x0000) +#define REG_0X60E00038 REG_0X60E0(0x0038) +#define REG_0X60E00030 REG_0X60E0(0x0030) +#define REG_0X60E00034 REG_0X60E0(0x0034) +#define REG_0X60E00028 REG_0X60E0(0x0028) +#define REG_0X60E00024 REG_0X60E0(0x0024) +#define REG_0X60E0002C REG_0X60E0(0x002C) + +/* + * Clock (0)Name, Clock (1)fixed rate, Clock Enable (2)Ctrl and (3)Bit, + * Clock Divisor (4)Ctrl and (5)Bit, Clock Parent (6)Ctrl and (7)Bit, + * and Parent Select (15)Count and (16)Lists[ ... ...] + */ + +SCI_CLK_ADD(ext_26m, 26000000, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(ext_32k, 32768, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(ext_26m_rf1, 26000000, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(ext_1m, 1000000, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(ext_2m, 2000000, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(ext_4m, 4000000, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_pad, 64000000, 0, 0, + 0, 0, 0, 0, 0); + +SCI_CLK_ADD(clk_mpll, 0, 0, 0, + REG_0X402E0044, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, 0); + +SCI_CLK_ADD(clk_dpll, 0, 0, 0, + REG_0X402E004C, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, 0); + +SCI_CLK_ADD(clk_ltepll, 0, 0, 0, + REG_0X402E005C, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, 0); + +SCI_CLK_ADD(clk_twpll, 0, 0, 0, + REG_0X402E0054, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, 0); + +SCI_CLK_ADD(clk_lvdspll, 0, 0, 0, + REG_0X402E0064, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, 0); + +SCI_CLK_ADD(clk_768m, 0, 0, 0, + 2, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_512m, 0, 0, 0, + 3, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_384m, 0, 0, 0, + 4, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_312m, 0, 0, 0, + 5, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_307m2, 0, 0, 0, + 5, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_256m, 0, 0, 0, + 6, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_192m, 0, 0, 0, + 8, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_153m6, 0, 0, 0, + 10, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_128m, 0, 0, 0, + 12, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_96m, 0, 0, 0, + 16, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_76m8, 0, 0, 0, + 20, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_64m, 0, 0, 0, + 24, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_51m2, 0, 0, 0, + 30, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_48m, 0, 0, 0, + 32, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_38m4, 0, 0, 0, + 40, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_24m, 0, 0, 0, + 64, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_12m, 0, 0, 0, + 128, 0, 0, 0, + 1, &clk_twpll); + +SCI_CLK_ADD(clk_42m_d, 0, 0, 0, + 32, 0, 0, 0, + 1, &clk_dpll); + +SCI_CLK_ADD(clk_56m_m, 0, 0, 0, + 32, 0, 0, 0, + 1, &clk_mpll); + +SCI_CLK_ADD(clk_38m4_lte, 0, 0, 0, + 32, 0, 0, 0, + 1, &clk_ltepll); + +SCI_CLK_ADD(clk_44m_lvds, 0, 0, 0, + 32, 0, 0, 0, + 1, &clk_lvdspll); + +SCI_CLK_ADD(clk_614m4, 0, 0, 0, + 2, 0, 0, 0, + 1, &clk_ltepll); + +SCI_CLK_ADD(clk_mcu, 0, 0, 0, + REG_0X20E00038, BIT(4)|BIT(5)|BIT(6), REG_0X20E00054, BIT(0)|BIT(1)|BIT(2), + 7, &ext_26m, &clk_512m, &clk_768m, &clk_dpll, &clk_ltepll, &clk_twpll, &clk_mpll); + +SCI_CLK_ADD(clk_ca7_core, 0, 0, 0, + 0, 0, 0, 0, + 1, &clk_mcu); + +SCI_CLK_ADD(clk_ca7_axi, 0, 0, 0, + REG_0X20E00038, BIT(8)|BIT(9)|BIT(10), 0, 0, + 1, &clk_mcu); + +SCI_CLK_ADD(clk_ca7_dbg, 0, 0, 0, + REG_0X20E00038, BIT(16)|BIT(17)|BIT(18), 0, 0, + 1, &clk_mcu); + +SCI_CLK_ADD(clk_emc_4x, 0, 0, 0, + REG_0X402D0020, BIT(8)|BIT(9), REG_0X402D0020, BIT(0)|BIT(1)|BIT(2), + 8, &ext_26m, &clk_192m, &clk_307m2, &clk_384m, &clk_512m, &clk_614m4, &clk_768m, &clk_dpll); + +SCI_CLK_ADD(clk_pub_ahb, 0, 0, 0, + REG_0X402D002C, BIT(8)|BIT(9), REG_0X402D002C, BIT(0)|BIT(1), + 4, &ext_26m, &ext_4m, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_aon_apb, 0, 0, 0, + REG_0X402D0030, BIT(8)|BIT(9), REG_0X402D0030, BIT(0)|BIT(1), + 4, &ext_4m, &ext_26m, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_adi, 0, REG_0X402E0000, BIT(16), + 0, 0, REG_0X402D0034, BIT(0)|BIT(1), + 4, &ext_26m, &ext_4m, &clk_38m4, &clk_51m2); + +SCI_CLK_ADD(clk_aux0, 0, REG_0X402E0004, BIT(2), + 0, 0, REG_0X402D0038, BIT(0)|BIT(1)|BIT(2), + 7, &ext_32k, &ext_26m, &ext_26m_rf1, &ext_4m, &clk_42m_d, &clk_48m, &clk_56m_m); + +SCI_CLK_ADD(clk_aux1, 0, REG_0X402E0004, BIT(3), + 0, 0, REG_0X402D003C, BIT(0)|BIT(1)|BIT(2)|BIT(3), + 9, &ext_32k, &ext_26m, &ext_26m_rf1, &ext_4m, &clk_42m_d, &clk_48m, &clk_56m_m, &clk_38m4_lte, &clk_44m_lvds); + +SCI_CLK_ADD(clk_aux2, 0, REG_0X402E0004, BIT(4), + 0, 0, REG_0X402D0040, BIT(0)|BIT(1)|BIT(2)|BIT(3), + 9, &ext_32k, &ext_26m, &ext_26m_rf1, &ext_4m, &clk_42m_d, &clk_48m, &clk_56m_m, &clk_38m4_lte, &clk_44m_lvds); + +SCI_CLK_ADD(clk_probe, 0, REG_0X402E0004, BIT(5), + 0, 0, REG_0X402D0044, BIT(0)|BIT(1)|BIT(2)|BIT(3), + 9, &ext_32k, &ext_26m, &ext_26m_rf1, &ext_4m, &clk_42m_d, &clk_48m, &clk_56m_m, &clk_38m4_lte, &clk_44m_lvds); + +SCI_CLK_ADD(clk_pwm0, 0, REG_0X402E0000, BIT(4), + 0, 0, REG_0X402D0048, BIT(0)|BIT(1), + 4, &ext_32k, &ext_26m, &ext_26m_rf1, &clk_48m); + +SCI_CLK_ADD(clk_pwm1, 0, REG_0X402E0000, BIT(5), + 0, 0, REG_0X402D004C, BIT(0)|BIT(1), + 4, &ext_32k, &ext_26m, &ext_26m_rf1, &clk_48m); + +SCI_CLK_ADD(clk_pwm2, 0, REG_0X402E0000, BIT(6), + 0, 0, REG_0X402D0050, BIT(0)|BIT(1), + 4, &ext_32k, &ext_26m, &ext_26m_rf1, &clk_48m); + +SCI_CLK_ADD(clk_pwm3, 0, REG_0X402E0000, BIT(7), + 0, 0, REG_0X402D0054, BIT(0)|BIT(1), + 4, &ext_32k, &ext_26m, &ext_26m_rf1, &clk_48m); + +SCI_CLK_ADD(clk_efuse, 0, REG_0X402E0000, BIT(13), + 0, 0, REG_0X402D0058, BIT(0), + 1, &ext_26m); + +SCI_CLK_ADD(clk_thm, 0, REG_0X402E0004, BIT(1), + 0, 0, REG_0X402D0068, BIT(0), + 2, &ext_32k, &ext_1m); + +SCI_CLK_ADD(clk_mspi, 0, REG_0X402E0000, BIT(23), + 0, 0, REG_0X402D006C, BIT(0), + 4, &ext_26m, &clk_51m2, &clk_76m8, &clk_96m); + +SCI_CLK_ADD(clk_i2c, 0, REG_0X402E0000, BIT(31), + 0, 0, REG_0X402D0070, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_avs, 0, REG_0X402E0004, BIT(6), + 0, 0, REG_0X402D0074, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_aud, 0, REG_0X402E0000, BIT(18), + 0, 0, REG_0X402D0078, BIT(0), + 1, &ext_26m); + +SCI_CLK_ADD(clk_audif, 0, REG_0X402E0000, BIT(17), + 0, 0, REG_0X402D007C, BIT(0)|BIT(1), + 3, &ext_26m, &clk_38m4, &clk_51m2); + +SCI_CLK_ADD(clk_vbc, 0, REG_0X402E0000, BIT(19), + 0, 0, REG_0X402D0080, BIT(0), + 1, &ext_26m); + +SCI_CLK_ADD(clk_ca7_dap, 0, REG_0X402E0000, BIT(30), + 0, 0, REG_0X402D0090, BIT(0)|BIT(1), + 4, &ext_26m, &clk_76m8, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_ca7_ts, 0, REG_0X402E0000, BIT(28), + 0, 0, REG_0X402D0098, BIT(0)|BIT(1), + 4, &ext_32k, &ext_26m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_djtag_tck, 0, 0, 0, + 0, 0, REG_0X402D00C8, BIT(0), + 3, &ext_26m, &ext_4m, &clk_pad); + +SCI_CLK_ADD(clk_arm7_ahb, 0, 0, 0, + REG_0X402D00CC, BIT(8)|BIT(9), REG_0X402D00CC, BIT(0)|BIT(1), + 4, &ext_4m, &ext_26m, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_ca5_ts, 0, REG_0X402E0004, BIT(26), + 0, 0, REG_0X402D00D0, BIT(0)|BIT(1), + 4, &ext_32k, &ext_26m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_disp_emc, 0, REG_0X402E0004, BIT(11), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_gsp_emc, 0, REG_0X402E0004, BIT(13), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_ap_ahb, 0, 0, 0, + 0, 0, REG_0X21500020, BIT(0)|BIT(1), + 4, &ext_26m, &clk_76m8, &clk_128m, &clk_192m); + +SCI_CLK_ADD(clk_ap_apb, 0, 0, 0, + 0, 0, REG_0X21500024, BIT(0)|BIT(1), + 4, &ext_26m, &clk_64m, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_gsp, 0, REG_0X20E00000, BIT(3), + 0, 0, REG_0X21500028, BIT(0)|BIT(1), + 4, &clk_96m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_dispc0, 0, REG_0X20E00000, BIT(1), + REG_0X2150002C, BIT(8)|BIT(9)|BIT(10), REG_0X2150002C, BIT(0)|BIT(1), + 4, &clk_153m6, &clk_192m, &clk_256m, &clk_307m2); + +SCI_CLK_ADD(clk_dispc0_dbi, 0, 0, 0, + REG_0X21500030, BIT(8)|BIT(9)|BIT(10), REG_0X21500030, BIT(0)|BIT(1), + 4, &clk_128m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_dispc0_dpi, 0, 0, 0, + REG_0X21500034, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), REG_0X21500034, BIT(0)|BIT(1), + 5, &clk_128m, &clk_153m6, &clk_192m, &clk_384m, &clk_pad); + +SCI_CLK_ADD(clk_nandc_2x, 0, REG_0X20E00000, BIT(18), + 0, 0, REG_0X21500054, BIT(0)|BIT(1), + 4, &clk_192m, &clk_256m, &clk_307m2, &clk_384m); + +SCI_CLK_ADD(clk_nandc_ecc, 0, REG_0X20E00000, BIT(19), + 0, 0, REG_0X21500058, BIT(0), + 2, &clk_153m6, &clk_192m); + +SCI_CLK_ADD(clk_sdio0, 0, REG_0X20E00000, BIT(8), + REG_0X2150005C, BIT(8)|BIT(9)|BIT(10), REG_0X2150005C, BIT(0)|BIT(1), + 4, &ext_26m, &clk_256m, &clk_307m2, &clk_384m); + +SCI_CLK_ADD(clk_sdio1, 0, REG_0X20E00000, BIT(9), + 0, 0, REG_0X21500060, BIT(0)|BIT(1), + 4, &clk_48m, &clk_76m8, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_sdio2, 0, REG_0X20E00000, BIT(10), + 0, 0, REG_0X21500068, BIT(0)|BIT(1), + 4, &clk_48m, &clk_76m8, &clk_96m, &clk_128m); + +SCI_CLK_ADD(clk_emmc, 0, REG_0X20E00000, BIT(11), + 0, 0, REG_0X21500070, BIT(0)|BIT(1), + 4, &ext_26m, &clk_256m, &clk_307m2, &clk_384m); + +SCI_CLK_ADD(clk_otg_ref, 0, REG_0X20E00000, BIT(4), + 0, 0, REG_0X21500074, BIT(0), + 2, &clk_12m, &clk_24m); + +SCI_CLK_ADD(clk_hsic_ref, 0, REG_0X20E00000, BIT(2), + 0, 0, REG_0X2150007C, BIT(0), + 2, &clk_12m, &clk_24m); + +SCI_CLK_ADD(clk_uart0, 0, REG_0X71300000, BIT(13), + REG_0X21500084, BIT(8)|BIT(9)|BIT(10), REG_0X21500084, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart1, 0, REG_0X71300000, BIT(14), + REG_0X21500088, BIT(8)|BIT(9)|BIT(10), REG_0X21500088, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart2, 0, REG_0X71300000, BIT(15), + REG_0X2150008C, BIT(8)|BIT(9)|BIT(10), REG_0X2150008C, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart3, 0, REG_0X71300000, BIT(16), + REG_0X21500090, BIT(8)|BIT(9)|BIT(10), REG_0X21500090, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_uart4, 0, REG_0X71300000, BIT(17), + REG_0X21500094, BIT(8)|BIT(9)|BIT(10), REG_0X21500094, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m); + +SCI_CLK_ADD(clk_i2c0, 0, REG_0X71300000, BIT(8), + REG_0X21500098, BIT(8)|BIT(9)|BIT(10), REG_0X21500098, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_i2c1, 0, REG_0X71300000, BIT(9), + REG_0X2150009C, BIT(8)|BIT(9)|BIT(10), REG_0X2150009C, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_i2c2, 0, REG_0X71300000, BIT(10), + REG_0X215000A0, BIT(8)|BIT(9)|BIT(10), REG_0X215000A0, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_i2c3, 0, REG_0X71300000, BIT(11), + REG_0X215000A4, BIT(8)|BIT(9)|BIT(10), REG_0X215000A4, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_i2c4, 0, REG_0X71300000, BIT(12), + REG_0X215000A8, BIT(8)|BIT(9)|BIT(10), REG_0X215000A8, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6); + +SCI_CLK_ADD(clk_spi0, 0, REG_0X71300000, BIT(5), + REG_0X215000AC, BIT(8)|BIT(9)|BIT(10), REG_0X215000AC, BIT(0)|BIT(1), + 5, &ext_26m, &clk_96m, &clk_153m6, &clk_192m, &clk_pad); + +SCI_CLK_ADD(clk_spi1, 0, REG_0X71300000, BIT(6), + REG_0X215000B0, BIT(8)|BIT(9)|BIT(10), REG_0X215000B0, BIT(0)|BIT(1), + 5, &ext_26m, &clk_96m, &clk_153m6, &clk_192m, &clk_pad); + +SCI_CLK_ADD(clk_spi2, 0, REG_0X71300000, BIT(7), + REG_0X215000B4, BIT(8)|BIT(9)|BIT(10), REG_0X215000B4, BIT(0)|BIT(1), + 5, &ext_26m, &clk_96m, &clk_153m6, &clk_192m, &clk_pad); + +SCI_CLK_ADD(clk_iis0, 0, REG_0X71300000, BIT(1), + REG_0X215000B8, BIT(8)|BIT(9)|BIT(10), REG_0X215000B8, BIT(0)|BIT(1), + 4, &ext_26m, &clk_128m, &clk_153m6, &clk_pad); + +SCI_CLK_ADD(clk_iis1, 0, REG_0X71300000, BIT(2), + REG_0X215000BC, BIT(8)|BIT(9)|BIT(10), REG_0X215000BC, BIT(0)|BIT(1), + 4, &ext_26m, &clk_128m, &clk_153m6, &clk_pad); + +SCI_CLK_ADD(clk_iis2, 0, REG_0X71300000, BIT(3), + REG_0X215000C0, BIT(8)|BIT(9)|BIT(10), REG_0X215000C0, BIT(0)|BIT(1), + 4, &ext_26m, &clk_128m, &clk_153m6, &clk_pad); + +SCI_CLK_ADD(clk_iis3, 0, REG_0X71300000, BIT(4), + REG_0X215000C4, BIT(8)|BIT(9)|BIT(10), REG_0X215000C4, BIT(0)|BIT(1), + 4, &ext_26m, &clk_128m, &clk_153m6, &clk_pad); + +SCI_CLK_ADD(clk_zipenc, 0, REG_0X20E00000, BIT(20), + 0, 0, REG_0X215000C8, BIT(0)|BIT(1), + 4, &clk_96m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_zipdec, 0, REG_0X20E00000, BIT(21), + 0, 0, REG_0X215000CC, BIT(0)|BIT(1), + 4, &clk_96m, &clk_153m6, &clk_192m, &clk_256m); + +SCI_CLK_ADD(clk_gpu_i, 0, REG_0X402E0000, BIT(27), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_gpu, 0, REG_0X402E0000, BIT(27), + REG_0X60100020, BIT(8)|BIT(9), REG_0X60100020, BIT(0)|BIT(1)|BIT(2), + 6, &clk_153m6, &clk_192m, &clk_256m, &clk_307m2, &clk_384m, &clk_512m); + +SCI_CLK_ADD(clk_mm_i, 0, REG_0X402E0000, BIT(25), + 0, 0, 0, 0, + 1, &clk_aon_apb); + +SCI_CLK_ADD(clk_mm_ahb, 0, 0, 0, + 0, 0, REG_0X60E00020, BIT(0)|BIT(1), + 4, &ext_26m, &clk_96m, &clk_128m, &clk_153m6); + +SCI_CLK_ADD(clk_mm_axi, 0, REG_0X60D00008, BIT(7), + 0, 0, 0, 0, + 1, &clk_mm_i); + +SCI_CLK_ADD(clk_mm_mtx_axi, 0, REG_0X60D00008, BIT(8), + 0, 0, 0, 0, + 1, &clk_mm_axi); + +SCI_CLK_ADD(clk_mmu, 0, REG_0X60D00000, BIT(7), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_mm_ckg, 0, REG_0X60D00000, BIT(6), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_jpg, 0, REG_0X60D00008, BIT(6), + 0, 0, REG_0X60E00038, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_256m, &clk_312m); + +SCI_CLK_ADD(clk_csi, 0, REG_0X60D00008, BIT(1), + 0, 0, 0, 0, + 1, &clk_mm_ahb); + +SCI_CLK_ADD(clk_dcam_mipi, 0, REG_0X60D00008, BIT(0), + 0, 0, 0, 0, + 1, &clk_csi); + +SCI_CLK_ADD(clk_vsp, 0, REG_0X60D00008, BIT(5), + 0, 0, REG_0X60E00030, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_256m, &clk_312m); + +SCI_CLK_ADD(clk_isp, 0, REG_0X60D00008, BIT(4), + 0, 0, REG_0X60E00034, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_256m, &clk_312m); + +SCI_CLK_ADD(clk_ccir, 0, REG_0X60D00000, BIT(1), + 0, 0, REG_0X60E00028, BIT(16), + 2, &clk_24m, &clk_pad); + +SCI_CLK_ADD(clk_sensor, 0, REG_0X60D00008, BIT(2), + REG_0X60E00024, BIT(8)|BIT(9)|BIT(10), REG_0X60E00024, BIT(0)|BIT(1), + 4, &ext_26m, &clk_48m, &clk_76m8, &clk_96m); + +SCI_CLK_ADD(clk_dcam, 0, REG_0X60D00008, BIT(3), + 0, 0, REG_0X60E0002C, BIT(0)|BIT(1), + 4, &clk_76m8, &clk_128m, &clk_256m, &clk_312m); + |