diff options
| author | Yuval Adam <_@yuv.al> | 2017-08-30 08:25:59 +0000 |
|---|---|---|
| committer | Yuval Adam <_@yuv.al> | 2017-08-30 08:25:59 +0000 |
| commit | 8e4bff4cab0ddac6060645b0715210484d02ff40 (patch) | |
| tree | 3a5c3024371a04692a3a6d9974d001cdff8ebf84 /include/soc/sprd/chip_x20/__regs_mm_clk.h | |
Diffstat (limited to 'include/soc/sprd/chip_x20/__regs_mm_clk.h')
| -rw-r--r-- | include/soc/sprd/chip_x20/__regs_mm_clk.h | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/include/soc/sprd/chip_x20/__regs_mm_clk.h b/include/soc/sprd/chip_x20/__regs_mm_clk.h new file mode 100644 index 00000000..6a3d7e65 --- /dev/null +++ b/include/soc/sprd/chip_x20/__regs_mm_clk.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2012 Spreadtrum Communications Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + ************************************************* + * Automatically generated C header: do not edit * + ************************************************* + */ + +#ifndef __REGS_MM_CLK_H__ +#define __REGS_MM_CLK_H__ + +#ifndef __SCI_GLB_REGS_H__ +#error "Don't include this file directly, include <mach/sci_glb_regs.h>" +#endif + +#define REGS_MM_CLK + +/* registers definitions for controller REGS_MM_CLK */ +#define REG_MM_CLK_MM_AHB_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0020) +#define REG_MM_CLK_SENSOR_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0024) +#define REG_MM_CLK_CCIR_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0028) +#define REG_MM_CLK_DCAM_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x002c) +#define REG_MM_CLK_VSP_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0030) +#define REG_MM_CLK_ISP_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0034) +#define REG_MM_CLK_JPG_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x0038) +#define REG_MM_CLK_VPP_CFG SCI_ADDR(REGS_MM_CLK_BASE, 0x003C) + +/* vars definitions for controller REGS_MM_CLK */ + +#endif //__REGS_MM_CLK_H__ |