Initial file dump from open source releaseHEAD master

author: Yuval Adam <_@yuv.al> 2017-08-30 08:25:59 +0000
committer: Yuval Adam <_@yuv.al> 2017-08-30 08:25:59 +0000
commit: 8e4bff4cab0ddac6060645b0715210484d02ff40 (patch)
tree: 3a5c3024371a04692a3a6d9974d001cdff8ebf84 /include/soc/sprd/chip_x20
25 files changed, 9013 insertions, 0 deletions
diff --git a/include/soc/sprd/chip_x20/__clock_tree.h b/include/soc/sprd/chip_x20/__clock_tree.h
new file mode 100644
index 00000000..23461560
--- /dev/null
+++ b/include/soc/sprd/chip_x20/__clock_tree.h
@@ -0,0 +1,548 @@
+/*
+ * Copyright (C) 2013 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+/*
+ * Clock (0)Name, Clock (1)fixed rate, Clock Enable (2)Ctrl and (3)Bit,
+ * Clock Divisor (4)Ctrl and (5)Bit, Clock Parent (6)Ctrl and (7)Bit,
+ * and Parent Select (15)Count and (16)Lists[ ... ...]
+ */
+
+SCI_CLK_ADD(ext_26m, 26000000, REG_PMU_APB_CGM_AP_EN, BIT(0),
+	0, 0, 0, 0, 0);
+
+SCI_CLK_ADD(ext_32k, 32768, 0, 0,
+	0, 0, 0, 0, 0);
+
+SCI_CLK_ADD(clk_mpll, 0, REG_PMU_APB_CGM_AP_EN, BIT(6),
+	REG_AON_APB_MPLL_CFG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0,
+	1, &ext_26m);
+
+SCI_CLK_ADD(clk_dpll, 0, REG_PMU_APB_CGM_AP_EN, BIT(1),
+	REG_AON_APB_DPLL_CFG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0,
+	1, &ext_26m);
+
+SCI_CLK_ADD(clk_td_sel_i, 0, REG_PMU_APB_TDPLL_REL_CFG, BIT(0),
+	0, 0, 0, 0, 0);
+
+SCI_CLK_ADD(clk_w_sel_i, 0, REG_PMU_APB_WPLL_REL_CFG, BIT(0),
+	0, 0, 0, 0, 0);
+
+SCI_CLK_ADD(clk_c_sel_i, 0, REG_PMU_APB_CPLL_REL_CFG, BIT(0),
+	0, 0, 0, 0, 0);
+
+SCI_CLK_ADD(clk_wifi_sel_i, 0, REG_PMU_APB_WIFIPLL1_REL_CFG, BIT(0),
+	0, 0, 0, 0, 0);
+
+SCI_CLK_ADD(clk_tdpll, 0, REG_PMU_APB_CGM_AP_EN, BIT(3),
+	REG_AON_APB_TDPLL_CFG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0,
+	1, &ext_26m);
+
+SCI_CLK_ADD(clk_wpll, 0, REG_PMU_APB_CGM_AP_EN, BIT(5),
+	REG_AON_APB_WPLL_CFG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0,
+	1, &clk_w_sel_i);
+
+SCI_CLK_ADD(clk_cpll, 0, REG_PMU_APB_CGM_AP_EN, BIT(2),
+	REG_AON_APB_CPLL_CFG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0,
+	1, &clk_c_sel_i);
+
+SCI_CLK_ADD(clk_wifipll, 0, REG_PMU_APB_CGM_AP_EN, BIT(4),
+	REG_AON_APB_WIFIPLL1_CFG1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0,
+	1, &clk_wifi_sel_i);
+
+SCI_CLK_ADD(clk_460m8, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(20),
+	2, 0, 0, 0,
+	1, &clk_wpll);
+
+SCI_CLK_ADD(clk_300m, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(0),
+	3, 0, 0, 0,
+	1, &clk_mpll);
+
+SCI_CLK_ADD(clk_37m5, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(1),
+	24, 0, 0, 0,
+	1, &clk_mpll);
+
+SCI_CLK_ADD(clk_66m, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(2),
+	16, 0, 0, 0,
+	1, &clk_dpll);
+
+SCI_CLK_ADD(clk_51m2_w, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(23),
+	18, 0, 0, 0,
+	1, &clk_wpll);
+
+SCI_CLK_ADD(clk_40m, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(27),
+	22, 0, 0, 0,
+	1, &clk_wifipll);
+
+SCI_CLK_ADD(clk_312m, 0, REG_PMU_APB_CGM_AP_EN, BIT(7),
+	2, 0, 0, 0,
+	1, &clk_cpll);
+
+SCI_CLK_ADD(clk_208m, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(17),
+	3, 0, 0, 0,
+	1, &clk_cpll);
+
+SCI_CLK_ADD(clk_104m, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(18),
+	6, 0, 0, 0,
+	1, &clk_cpll);
+
+SCI_CLK_ADD(clk_52m, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(19),
+	12, 0, 0, 0,
+	1, &clk_cpll);
+
+SCI_CLK_ADD(clk_384m, 0, REG_PMU_APB_CGM_AP_EN, BIT(8),
+	2, 0, 0, 0,
+	1, &clk_tdpll);
+
+SCI_CLK_ADD(clk_192m, 0, REG_PMU_APB_CGM_AP_EN, BIT(10),
+	4, 0, 0, 0,
+	1, &clk_tdpll);
+
+SCI_CLK_ADD(clk_96m, 0, REG_PMU_APB_CGM_AP_EN, BIT(13),
+	8, 0, 0, 0,
+	1, &clk_tdpll);
+
+SCI_CLK_ADD(clk_48m, 0, REG_PMU_APB_CGM_AP_EN, BIT(17),
+	16, 0, 0, 0,
+	1, &clk_tdpll);
+
+SCI_CLK_ADD(clk_24m, 0, REG_PMU_APB_CGM_AP_EN, BIT(18),
+	32, 0, 0, 0,
+	1, &clk_tdpll);
+
+SCI_CLK_ADD(clk_12m, 0, REG_PMU_APB_CGM_AP_EN, BIT(19),
+	64, 0, 0, 0,
+	1, &clk_tdpll);
+
+SCI_CLK_ADD(clk_256m, 0, REG_PMU_APB_CGM_AP_EN, BIT(9),
+	3, 0, 0, 0,
+	1, &clk_tdpll);
+
+SCI_CLK_ADD(clk_128m, 0, REG_PMU_APB_CGM_AP_EN, BIT(12),
+	6, 0, 0, 0,
+	1, &clk_tdpll);
+
+SCI_CLK_ADD(clk_64m, 0, REG_PMU_APB_CGM_AP_EN, BIT(15),
+	12, 0, 0, 0,
+	1, &clk_tdpll);
+
+SCI_CLK_ADD(clk_153m6, 0, REG_PMU_APB_CGM_AP_EN, BIT(11),
+	5, 0, 0, 0,
+	1, &clk_tdpll);
+
+SCI_CLK_ADD(clk_51m2, 0, REG_PMU_APB_CGM_AP_EN, BIT(16),
+	15, 0, 0, 0,
+	1, &clk_tdpll);
+
+SCI_CLK_ADD(clk_76m8, 0, REG_PMU_APB_CGM_AP_EN, BIT(14),
+	10, 0, 0, 0,
+	1, &clk_tdpll);
+
+SCI_CLK_ADD(clk_38m4, 0, REG_PMU_APB_PLL_DIV_EN1, BIT(15),
+	20, 0, 0, 0,
+	1, &clk_tdpll);
+
+SCI_CLK_ADD(clk_mcu, 0, 0, 0,
+	REG_AP_AHB_CA7_CKG_CFG, BIT(4)|BIT(5)|BIT(6), REG_AP_AHB_CA7_CKG_CFG, BIT(0)|BIT(1)|BIT(2),
+	7, &ext_26m, &clk_dpll, &clk_cpll, &clk_tdpll, &clk_wifipll, &clk_wpll, &clk_mpll);
+
+SCI_CLK_ADD(clk_arm, 0, 0, 0,
+	0, 0, 0, 0,
+	1, &clk_mcu);
+
+SCI_CLK_ADD(clk_axi, 0, 0, 0,
+	REG_AP_AHB_CA7_CKG_CFG, BIT(8)|BIT(9)|BIT(10), 0, 0,
+	1, &clk_mcu);
+
+SCI_CLK_ADD(clk_dbg, 0, REG_AP_AHB_MISC_CKG_EN, BIT(8),
+	REG_AP_AHB_CA7_CKG_CFG, BIT(16)|BIT(17)|BIT(18), 0, 0,
+	1, &clk_mcu);
+
+SCI_CLK_ADD(clk_ap_ahb, 0, 0, 0,
+	0, 0, REG_AP_CLK_AP_AHB_CFG, BIT(0)|BIT(1),
+	4, &ext_26m, &clk_76m8, &clk_128m, &clk_192m);
+
+SCI_CLK_ADD(clk_ap_apb, 0, 0, 0,
+	0, 0, REG_AP_CLK_AP_APB_CFG, BIT(0)|BIT(1),
+	4, &ext_26m, &clk_64m, &clk_96m, &clk_128m);
+
+SCI_CLK_ADD(clk_pub_ahb, 0, 0, 0,
+	0, 0, REG_AON_CLK_PUB_AHB_CFG, BIT(0)|BIT(1),
+	4, &ext_26m, &clk_96m, &clk_128m, &clk_153m6);
+
+SCI_CLK_ADD(clk_emc, 0, 0, 0,
+	REG_AON_CLK_EMC_CFG, BIT(8)|BIT(9), REG_AON_CLK_EMC_CFG, BIT(0)|BIT(1),
+	4, &ext_26m, &clk_cpll, &clk_tdpll, &clk_dpll);
+
+SCI_CLK_ADD(clk_aon_apb, 0, 0, 0,
+	REG_AON_CLK_AON_APB_CFG, BIT(8)|BIT(9), REG_AON_CLK_AON_APB_CFG, BIT(0)|BIT(1),
+	4, &ext_26m, &clk_76m8, &clk_96m, &clk_128m);
+
+SCI_CLK_ADD(clk_disp_emc, 0, REG_AON_APB_APB_EB1, BIT(11),
+	0, 0, 0, 0,
+	1, &clk_aon_apb);
+
+SCI_CLK_ADD(clk_gsp_emc, 0, REG_AON_APB_APB_EB1, BIT(13),
+	0, 0, 0, 0,
+	1, &clk_aon_apb);
+
+SCI_CLK_ADD(clk_gsp, 0, REG_AP_AHB_AHB_EB, BIT(3),
+	0, 0, REG_AP_CLK_GSP_CFG, BIT(0)|BIT(1),
+	4, &clk_96m, &clk_153m6, &clk_192m, &clk_256m);
+
+SCI_CLK_ADD(clk_disc0, 0, REG_AP_AHB_AHB_EB, BIT(1),
+	REG_AP_CLK_DISPC0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_DISPC0_CFG, BIT(0)|BIT(1),
+	4, &clk_153m6, &clk_192m, &clk_256m, &clk_312m);
+
+SCI_CLK_ADD(clk_disc0_dbi, 0, REG_AP_AHB_AHB_EB, BIT(1),
+	REG_AP_CLK_DISPC0_DBI_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_DISPC0_DBI_CFG, BIT(0)|BIT(1),
+	4, &clk_128m, &clk_153m6, &clk_192m, &clk_256m);
+
+SCI_CLK_ADD(clk_disc0_dpi, 0, REG_AP_AHB_AHB_EB, BIT(1),
+	REG_AP_CLK_DISPC0_DPI_CFG, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), REG_AP_CLK_DISPC0_DPI_CFG, BIT(0)|BIT(1),
+	4, &clk_128m, &clk_153m6, &clk_192m, &clk_384m);
+
+SCI_CLK_ADD(clk_disc1, 0, REG_AP_AHB_AHB_EB, BIT(2),
+	REG_AP_CLK_DISPC1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_DISPC1_CFG, BIT(0)|BIT(1),
+	4, &clk_153m6, &clk_192m, &clk_256m, &clk_312m);
+
+SCI_CLK_ADD(clk_disc1_dbi, 0, REG_AP_AHB_AHB_EB, BIT(2),
+	REG_AP_CLK_DISPC1_DBI_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_DISPC1_DBI_CFG, BIT(0)|BIT(1),
+	4, &clk_128m, &clk_153m6, &clk_192m, &clk_256m);
+
+SCI_CLK_ADD(clk_disc1_dpi, 0, REG_AP_AHB_AHB_EB, BIT(2),
+	REG_AP_CLK_DISPC1_DPI_CFG, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), REG_AP_CLK_DISPC1_DPI_CFG, BIT(0)|BIT(1),
+	4, &clk_128m, &clk_153m6, &clk_192m, &clk_384m);
+
+/*
+SCI_CLK_ADD(clk_zipdec_emc, 0, REG_AP_AHB_AHB_EB, BIT(21),
+	0, 0, REG_AP_CLK_ZIPENC_CFG, BIT(0)|BIT(1),
+	4, &clk_96m, &clk_153m6, &clk_192m, &clk_256m);
+
+SCI_CLK_ADD(clk_zipenc_emc, 0, REG_AP_AHB_AHB_EB, BIT(20),
+	0, 0, REG_AP_CLK_ZIPENC_CFG, BIT(0)|BIT(1),
+	4, &clk_96m, &clk_153m6, &clk_192m, &clk_256m);
+
+SCI_CLK_ADD(clk_nandc_ecc, 0, REG_AP_AHB_AHB_EB, BIT(19),
+	0, 0, REG_AP_CLK_NANDC_ECC_CFG, BIT(0),
+	2, &clk_153m6, &clk_192m);
+
+*/
+SCI_CLK_ADD(clk_nfc, 0, REG_AP_AHB_AHB_EB, BIT(6),
+	REG_AP_CLK_NFC_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_NFC_CFG, BIT(0)|BIT(1),
+	3, &clk_64m, &clk_128m, &clk_153m6);
+
+SCI_CLK_ADD(clk_sdio0, 0, REG_AP_AHB_AHB_EB, BIT(8),
+	REG_AP_CLK_SDIO0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_SDIO0_CFG, BIT(0)|BIT(1),
+	4, &ext_26m, &clk_256m, &clk_312m, &clk_384m);
+
+SCI_CLK_ADD(clk_sdio1, 0, REG_AP_AHB_AHB_EB, BIT(9),
+	0, 0, REG_AP_CLK_SDIO1_CFG, BIT(0)|BIT(1),
+	4, &clk_48m, &clk_76m8, &clk_96m, &clk_128m);
+
+SCI_CLK_ADD(clk_sdio2, 0, REG_AP_AHB_AHB_EB, BIT(10),
+	0, 0, REG_AP_CLK_SDIO2_CFG, BIT(0)|BIT(1),
+	4, &clk_48m, &clk_76m8, &clk_96m, &clk_128m);
+
+SCI_CLK_ADD(clk_emmc, 0, REG_AP_AHB_AHB_EB, BIT(11),
+	0, 0, REG_AP_CLK_EMMC_CFG, BIT(0)|BIT(1),
+	4, &ext_26m, &clk_256m, &clk_312m, &clk_384m);
+
+SCI_CLK_ADD(clk_gps_tcxo, 64000000, REG_AP_CLK_GPS_TCXO_CFG, BIT(16),
+	0, 0, 0, 0, 0);
+
+SCI_CLK_ADD(clk_gps, 0, REG_AP_AHB_AHB_EB, BIT(12),
+	0, 0, REG_AP_CLK_GPS_CFG, BIT(0),
+	2, &clk_64m, &clk_76m8);
+
+SCI_CLK_ADD(clk_usb_ref, 0, REG_AP_AHB_AHB_EB, BIT(4),
+	0, 0, REG_AP_CLK_USB_REF_CFG, BIT(0),
+	2, &clk_12m, &clk_24m);
+
+SCI_CLK_ADD(clk_uart0, 0, REG_AP_APB_APB_EB, BIT(13),
+	REG_AP_CLK_UART0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_UART0_CFG, BIT(0)|BIT(1),
+	4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m);
+
+SCI_CLK_ADD(clk_uart1, 0, REG_AP_APB_APB_EB, BIT(14),
+	REG_AP_CLK_UART1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_UART1_CFG, BIT(0)|BIT(1),
+	4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m);
+
+SCI_CLK_ADD(clk_uart2, 0, REG_AP_APB_APB_EB, BIT(15),
+	REG_AP_CLK_UART2_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_UART2_CFG, BIT(0)|BIT(1),
+	4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m);
+
+SCI_CLK_ADD(clk_uart3, 0, REG_AP_APB_APB_EB, BIT(16),
+	REG_AP_CLK_UART3_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_UART3_CFG, BIT(0)|BIT(1),
+	4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m);
+
+SCI_CLK_ADD(clk_uart4, 0, REG_AP_APB_APB_EB, BIT(17),
+	REG_AP_CLK_UART4_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_UART4_CFG, BIT(0)|BIT(1),
+	4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m);
+
+SCI_CLK_ADD(clk_i2c0, 0, REG_AP_APB_APB_EB, BIT(8),
+	REG_AP_CLK_I2C0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_I2C0_CFG, BIT(0)|BIT(1),
+	4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6);
+
+SCI_CLK_ADD(clk_i2c1, 0, REG_AP_APB_APB_EB, BIT(9),
+	REG_AP_CLK_I2C1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_I2C1_CFG, BIT(0)|BIT(1),
+	4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6);
+
+SCI_CLK_ADD(clk_i2c2, 0, REG_AP_APB_APB_EB, BIT(10),
+	REG_AP_CLK_I2C2_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_I2C2_CFG, BIT(0)|BIT(1),
+	4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6);
+
+SCI_CLK_ADD(clk_i2c3, 0, REG_AP_APB_APB_EB, BIT(11),
+	REG_AP_CLK_I2C3_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_I2C3_CFG, BIT(0)|BIT(1),
+	4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6);
+
+SCI_CLK_ADD(clk_i2c4, 0, REG_AP_APB_APB_EB, BIT(12),
+	REG_AP_CLK_I2C4_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_I2C4_CFG, BIT(0)|BIT(1),
+	4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6);
+
+SCI_CLK_ADD(clk_spi0, 0, REG_AP_APB_APB_EB, BIT(5),
+	REG_AP_CLK_SPI0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_SPI0_CFG, BIT(0)|BIT(1),
+	4, &ext_26m, &clk_96m, &clk_153m6, &clk_192m);
+
+SCI_CLK_ADD(clk_spi1, 0, REG_AP_APB_APB_EB, BIT(6),
+	REG_AP_CLK_SPI1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_SPI1_CFG, BIT(0)|BIT(1),
+	4, &ext_26m, &clk_96m, &clk_153m6, &clk_192m);
+
+SCI_CLK_ADD(clk_spi2, 0, REG_AP_APB_APB_EB, BIT(7),
+	REG_AP_CLK_SPI2_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_SPI2_CFG, BIT(0)|BIT(1),
+	4, &ext_26m, &clk_96m, &clk_153m6, &clk_192m);
+
+SCI_CLK_ADD(clk_iis0, 0, REG_AP_APB_APB_EB, BIT(1),
+	REG_AP_CLK_IIS0_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_IIS0_CFG, BIT(0)|BIT(1),
+	3, &ext_26m, &clk_128m, &clk_153m6);
+
+SCI_CLK_ADD(clk_iis1, 0, REG_AP_APB_APB_EB, BIT(2),
+	REG_AP_CLK_IIS1_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_IIS1_CFG, BIT(0)|BIT(1),
+	3, &ext_26m, &clk_128m, &clk_153m6);
+
+SCI_CLK_ADD(clk_iis2, 0, REG_AP_APB_APB_EB, BIT(3),
+	REG_AP_CLK_IIS2_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_IIS2_CFG, BIT(0)|BIT(1),
+	3, &ext_26m, &clk_128m, &clk_153m6);
+
+SCI_CLK_ADD(clk_iis3, 0, REG_AP_APB_APB_EB, BIT(4),
+	REG_AP_CLK_IIS3_CFG, BIT(8)|BIT(9)|BIT(10), REG_AP_CLK_IIS3_CFG, BIT(0)|BIT(1),
+	3, &ext_26m, &clk_128m, &clk_153m6);
+
+SCI_CLK_ADD(clk_gpu_top_i, 0, REG_PMU_APB_PD_GPU_TOP_CFG+1, BIT(25),
+	0, 0, 0, 0,
+	1, &clk_aon_apb);
+
+SCI_CLK_ADD(clk_gpu_i, 0, REG_AON_APB_APB_EB0, BIT(27),
+	0, 0, 0, 0,
+	1, &clk_gpu_top_i);
+
+SCI_CLK_ADD(clk_gpu, 0, &clk_gpu_i, 0,
+	REG_GPU_APB_APB_CLK_CTRL, BIT(4)|BIT(5), REG_GPU_APB_APB_CLK_CTRL, BIT(0)|BIT(1)|BIT(2),
+	7, &clk_153m6, &clk_208m, &clk_256m, &clk_300m, &clk_312m, &clk_384m, &clk_460m8);
+
+SCI_CLK_ADD(clk_mm_top_i, 0, REG_PMU_APB_PD_MM_TOP_CFG+1, BIT(25),
+	0, 0, 0, 0,
+	1, &clk_aon_apb);
+
+SCI_CLK_ADD(clk_mm_i, 0, REG_AON_APB_APB_EB0, BIT(25),
+	0, 0, 0, 0,
+	1, &clk_mm_top_i);
+
+SCI_CLK_ADD(clk_mm_ahb, 0, 0, 0,
+	0, 0, REG_MM_CLK_MM_AHB_CFG, BIT(0)|BIT(1),
+	4, &ext_26m, &clk_96m, &clk_128m, &clk_153m6);
+
+SCI_CLK_ADD(clk_mm_mtx_axi, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(8),
+	0, 0, 0, 0,
+	1, &clk_mm_i);
+
+SCI_CLK_ADD(clk_mm_axi, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(7),
+	0, 0, 0, 0,
+	1, &clk_mm_mtx_axi);
+
+SCI_CLK_ADD(clk_mmu, 0, REG_MM_AHB_AHB_EB, BIT(7),
+	0, 0, 0, 0,
+	1, &clk_mm_ahb);
+SCI_CLK_ADD(clk_mm_ckg_i, 0, REG_MM_AHB_AHB_EB, BIT(6),
+	0, 0, 0, 0,
+	1, &clk_mm_i);
+
+SCI_CLK_ADD(clk_jpg_i, 0, REG_MM_AHB_AHB_EB, BIT(5),
+	0, 0, 0, 0,
+	1, &clk_mm_ahb);
+
+SCI_CLK_ADD(clk_jpg_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(6),
+	0, 0, 0, 0,
+	1, &clk_jpg_i);
+
+SCI_CLK_ADD(clk_jpg, 0, &clk_jpg_ckg_i, 0,
+	0, 0, REG_MM_CLK_JPG_CFG, BIT(0)|BIT(1),
+	4, &clk_76m8, &clk_128m, &clk_192m, &clk_256m);
+
+SCI_CLK_ADD(clk_vsp_i, 0, REG_MM_AHB_AHB_EB, BIT(3),
+	0, 0, 0, 0,
+	1, &clk_mm_ahb);
+
+SCI_CLK_ADD(clk_vsp_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(5),
+	0, 0, 0, 0,
+	1, &clk_vsp_i);
+
+SCI_CLK_ADD(clk_vsp, 0, &clk_vsp_ckg_i, 0,
+	0, 0, REG_MM_CLK_VSP_CFG, BIT(0)|BIT(1),
+	4, &clk_76m8, &clk_128m, &clk_192m, &clk_256m);
+
+SCI_CLK_ADD(clk_isp_i, 0, REG_MM_AHB_AHB_EB, BIT(2),
+	0, 0, 0, 0,
+	1, &clk_mm_ahb);
+
+SCI_CLK_ADD(clk_isp_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(4),
+	0, 0, 0, 0,
+	1, &clk_isp_i);
+
+SCI_CLK_ADD(clk_isp, 0, &clk_isp_ckg_i, 0,
+	0, 0, REG_MM_CLK_ISP_CFG, BIT(0)|BIT(1),
+	4, &clk_76m8, &clk_128m, &clk_256m, &clk_312m);
+
+SCI_CLK_ADD(clk_sensor_i, 0, REG_MM_AHB_AHB_EB, BIT(1),
+	0, 0, 0, 0,
+	1, &clk_mm_ahb);
+
+SCI_CLK_ADD(clk_sensor_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(2),
+	0, 0, 0, 0,
+	1, &clk_sensor_i);
+
+SCI_CLK_ADD(clk_sensor, 0, &clk_sensor_ckg_i, 0,
+	REG_MM_CLK_SENSOR_CFG, BIT(8)|BIT(9)|BIT(10), REG_MM_CLK_SENSOR_CFG, BIT(0)|BIT(1),
+	4, &ext_26m, &clk_48m, &clk_76m8, &clk_96m);
+
+SCI_CLK_ADD(clk_ccir_in, 64000000, 0, 0,
+	0, 0, 0, 0, 0);
+
+SCI_CLK_ADD(clk_ccir_i, 0, REG_MM_AHB_AHB_EB, BIT(1),
+	0, 0, 0, 0,
+	1, &clk_mm_ahb);
+
+SCI_CLK_ADD(clk_ccir, 0, &clk_ccir_i, 0,
+	0, 0, REG_MM_CLK_CCIR_CFG, BIT(16),
+	2, &clk_24m, &clk_ccir_in);
+
+SCI_CLK_ADD(clk_dcam_i, 0, REG_MM_AHB_AHB_EB, BIT(0),
+	0, 0, 0, 0,
+	1, &clk_mm_ahb);
+
+SCI_CLK_ADD(clk_dcam_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(3),
+	0, 0, 0, 0,
+	1, &clk_dcam_i);
+
+SCI_CLK_ADD(clk_dcam, 0, &clk_dcam_ckg_i, 0,
+	0, 0, REG_MM_CLK_DCAM_CFG, BIT(0)|BIT(1),
+	4, &clk_76m8, &clk_128m, &clk_256m, &clk_312m);
+
+SCI_CLK_ADD(clk_csi_i, 0, REG_MM_AHB_AHB_EB, BIT(4),
+	0, 0, 0, 0,
+	1, &clk_mm_ahb);
+
+SCI_CLK_ADD(clk_csi_ckg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(1),
+	0, 0, 0, 0,
+	1, &clk_csi_i);
+
+SCI_CLK_ADD(clk_cphy_cfg_i, 0, REG_MM_AHB_GEN_CKG_CFG, BIT(0),
+	0, 0, 0, 0,
+	1, &clk_mm_ahb);
+
+SCI_CLK_ADD(clk_dcam_mipi, 0, &clk_cphy_cfg_i, 0,
+	0, 0, 0, 0,
+	1, &clk_csi_ckg_i);
+
+SCI_CLK_ADD(clk_aud, 0, REG_AON_APB_APB_EB0, BIT(18),
+	0, 0, 0, 0,
+	1, &ext_26m);
+
+SCI_CLK_ADD(clk_audif, 0, REG_AON_APB_APB_EB0, BIT(17),
+	0, 0, REG_AON_CLK_AUDIF_CFG, BIT(0)|BIT(1),
+	3, &ext_26m, &clk_38m4, &clk_51m2);
+
+SCI_CLK_ADD(clk_vbc, 0, REG_AON_APB_APB_EB0, BIT(19),
+	0, 0, 0, 0,
+	1, &ext_26m);
+
+SCI_CLK_ADD(clk_fm_in, 64000000, REG_AON_CLK_FM_CFG, BIT(16),
+	0, 0, 0, 0, 0);
+
+SCI_CLK_ADD(clk_fm, 0, REG_AON_APB_APB_EB0, BIT(1),
+	0, 0, 0, 0,
+	1, &clk_fm_in);
+
+SCI_CLK_ADD(clk_adi, 0, REG_AON_APB_APB_EB0, BIT(16),
+	0, 0, REG_AON_CLK_ADI_CFG, BIT(0)|BIT(1),
+	4, &ext_26m, &clk_38m4, &clk_51m2, &clk_64m);
+
+SCI_CLK_ADD(clk_aux0, 0, REG_AON_APB_APB_EB1, BIT(2),
+	REG_AON_APB_AON_CGM_CFG, BIT(16)|BIT(17)|BIT(18)|BIT(19), REG_AON_APB_AON_CGM_CFG, BIT(0)|BIT(1)|BIT(2)|BIT(3),
+	10, &ext_32k, &ext_26m, &ext_26m, &clk_48m, &clk_52m, &clk_51m2, &clk_37m5, &clk_40m, &clk_66m, &clk_40m);
+
+SCI_CLK_ADD(clk_aux1, 0, REG_AON_APB_APB_EB1, BIT(3),
+	REG_AON_APB_AON_CGM_CFG, BIT(20)|BIT(21)|BIT(22)|BIT(23), REG_AON_APB_AON_CGM_CFG, BIT(4)|BIT(5)|BIT(6)|BIT(7),
+	10, &ext_32k, &ext_26m, &ext_26m, &clk_48m, &clk_52m, &clk_51m2, &clk_37m5, &clk_40m, &clk_66m, &clk_40m);
+
+SCI_CLK_ADD(clk_aux2, 0, REG_AON_APB_APB_EB1, BIT(4),
+	REG_AON_APB_AON_CGM_CFG, BIT(24)|BIT(25)|BIT(26)|BIT(27), REG_AON_APB_AON_CGM_CFG, BIT(8)|BIT(9)|BIT(10)|BIT(11),
+	10, &ext_32k, &ext_26m, &ext_26m, &clk_48m, &clk_52m, &clk_51m2, &clk_37m5, &clk_40m, &clk_66m, &clk_40m);
+
+SCI_CLK_ADD(clk_pwm0, 0, REG_AON_APB_APB_EB0, BIT(4),
+	0, 0, REG_AON_CLK_PWM0_CFG, BIT(0),
+	2, &ext_32k, &ext_26m);
+
+SCI_CLK_ADD(clk_pwm1, 0, REG_AON_APB_APB_EB0, BIT(5),
+	0, 0, REG_AON_CLK_PWM1_CFG, BIT(0),
+	2, &ext_32k, &ext_26m);
+
+SCI_CLK_ADD(clk_pwm2, 0, REG_AON_APB_APB_EB0, BIT(6),
+	0, 0, REG_AON_CLK_PWM2_CFG, BIT(0),
+	2, &ext_32k, &ext_26m);
+
+SCI_CLK_ADD(clk_pwm3, 0, REG_AON_APB_APB_EB0, BIT(7),
+	0, 0, REG_AON_CLK_PWM3_CFG, BIT(0),
+	2, &ext_32k, &ext_26m);
+
+SCI_CLK_ADD(clk_efuse, 0, REG_AON_APB_APB_EB0, BIT(13),
+	0, 0, 0, 0,
+	1, &ext_26m);
+
+SCI_CLK_ADD(clk_ca7_dap, 0, REG_AON_APB_APB_EB0, BIT(30),
+	0, 0, REG_AON_CLK_CA7_DAP_CFG, BIT(0)|BIT(1),
+	4, &ext_26m, &clk_76m8, &clk_128m, &clk_153m6);
+
+SCI_CLK_ADD(clk_ca7_ts, 0, REG_AON_APB_APB_EB0, BIT(28),
+	0, 0, REG_AON_CLK_CA7_TS_CFG, BIT(0)|BIT(1),
+	4, &ext_32k, &ext_26m, &clk_128m, &clk_153m6);
+
+SCI_CLK_ADD(clk_mspi, 0, REG_AON_APB_APB_EB0, BIT(23),
+	0, 0, REG_AON_CLK_MSPI_CFG, BIT(0)|BIT(1),
+	3, &ext_26m, &clk_52m, &clk_76m8, &clk_96m);
+
+SCI_CLK_ADD(clk_i2c, 0, REG_AON_APB_APB_EB0, BIT(31),
+	0, 0, REG_AON_CLK_I2C_CFG, BIT(0)|BIT(1),
+	4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6);
+
+SCI_CLK_ADD(clk_avs0, 0, REG_AON_APB_APB_EB0, BIT(6),
+	0, 0, REG_AON_CLK_AVS0_CFG, BIT(0)|BIT(1),
+	4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m);
+
+SCI_CLK_ADD(clk_avs1, 0, REG_AON_APB_APB_EB0, BIT(7),
+	0, 0, REG_AON_CLK_AVS1_CFG, BIT(0)|BIT(1),
+	4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m);
+
diff --git a/include/soc/sprd/chip_x20/__regs_ada_apb_rf.h b/include/soc/sprd/chip_x20/__regs_ada_apb_rf.h
new file mode 100644
index 00000000..0ca65ecf
--- /dev/null
+++ b/include/soc/sprd/chip_x20/__regs_ada_apb_rf.h
@@ -0,0 +1,177 @@
+/*
+ * Copyright (C) 2014 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+#ifndef __SCI_GLB_REGS_H__
+#error  "Don't include this file directly, Pls include sci_glb_regs.h"
+#endif
+
+
+#ifndef __H_REGS_ADA_APB_RF_HEADFILE_H__
+#define __H_REGS_ADA_APB_RF_HEADFILE_H__ __FILE__
+
+#define	REGS_ADA_APB_RF
+
+/* registers definitions for ADA_APB_RF */
+#define REG_ADA_APB_RF_APB_DAC_CTR0                       SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0000)
+#define REG_ADA_APB_RF_APB_DAC_CTR1                       SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0004)
+#define REG_ADA_APB_RF_APB_DAC_CTR2                       SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0008)
+#define REG_ADA_APB_RF_APB_DAC_CTR3                       SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x000C)
+#define REG_ADA_APB_RF_APB_DAC_CTR4                       SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0010)
+#define REG_ADA_APB_RF_APB_DAC_STS0                       SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0014)
+#define REG_ADA_APB_RF_APB_DAC_STS1                       SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0018)
+#define REG_ADA_APB_RF_APB_ADC0_CTR0                      SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x001C)
+#define REG_ADA_APB_RF_APB_ADC0_CTR1                      SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0020)
+#define REG_ADA_APB_RF_APB_ADC0_CTR2                      SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0024)
+#define REG_ADA_APB_RF_APB_ADC0_CTR3                      SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0028)
+#define REG_ADA_APB_RF_APB_CAL_CTR0                       SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0030)
+#define REG_ADA_APB_RF_APB_CAL_CTR1                       SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0034)
+#define REG_ADA_APB_RF_APB_CAL_CTR3                       SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x003C)
+#define REG_ADA_APB_RF_APB_CAL_STS0                       SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0044)
+#define REG_ADA_APB_RF_APB_CAL_STS1                       SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0048)
+#define REG_ADA_APB_RF_APB_ADA_CTRL0                      SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0054)
+#define REG_ADA_APB_RF_APB_ADA_CTRL1                      SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0058)
+#define REG_ADA_APB_RF_APB_RX_GSM_DFT                     SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x005C)
+#define REG_ADA_APB_RF_APB_RX_3G_DFT                      SCI_ADDR(REGS_ADA_APB_RF_BASE, 0x0060)
+
+
+
+/* bits definitions for register REG_ADA_APB_RF_APB_DAC_CTR0 */
+#define BITS_DAC_PCTRL_1(_X_)                             ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
+#define BIT_DAC_OUT_SEL_1                                 ( BIT(17) )
+#define BIT_DAC_CLK_SEL_1                                 ( BIT(16) )
+#define BITS_DAC_PCTRL_0(_X_)                             ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) )
+#define BIT_DAC_OUT_SEL_0                                 ( BIT(1) )
+#define BIT_DAC_CLK_SEL_0                                 ( BIT(0) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_DAC_CTR1 */
+#define BITS_DAC_WD_OVR(_X_)                              ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DAC_WADDR_OVR(_X_)                           ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_DAC_WLE_OVR                                   ( BIT(2) )
+#define BIT_DAC_W_OVR_I_QN                                ( BIT(1) )
+#define BIT_DAC_W_OVR_EN                                  ( BIT(0) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_DAC_CTR2 */
+#define BITS_DAC_RSV(_X_)                                 ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) )
+#define BIT_DAC_IQ_OUT_MSB_INV                            ( BIT(21) )
+#define BIT_DAC_IQ_IN_MSB_INV                             ( BIT(20) )
+#define BIT_DAC_OVR_EN_CAL                                ( BIT(19) )
+#define BIT_DAC_EN_OOSCAL                                 ( BIT(18) )
+#define BIT_DAC_IQ_SWAP                                   ( BIT(17) )
+#define BIT_DAC_CAL_START                                 ( BIT(16) )
+#define BITS_DAC_OFFSETI(_X_)                             ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DAC_OFFSETQ(_X_)                             ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_DAC_CTR3 */
+#define BITS_DAC_Q_DC(_X_)                                ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) )
+#define BITS_DAC_I_DC(_X_)                                ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_DAC_CTR4 */
+#define BITS_DAC_I_CAL(_X_)                               ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) )
+#define BITS_DAC_Q_CAL(_X_)                               ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_DAC_STS0 */
+#define BITS_DAC_WTI(_X_)                                 ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DAC_WTQ(_X_)                                 ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_DAC_STS1 */
+#define BITS_DAC_DA_STATE(_X_)                            ( (_X_) << 17 & (BIT(17)|BIT(18)) )
+#define BIT_DAC_DONE                                      ( BIT(16) )
+#define BITS_DAC_WQ_OVR(_X_)                              ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_ADC0_CTR0 */
+#define BITS_ADC0_CALRDOUT(_X_)                           ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
+#define BIT_ADC0_CAL_SOFT_RST                             ( BIT(10) )
+#define BIT_ADC0_CALRD                                    ( BIT(9) )
+#define BIT_ADC0_CALEN                                    ( BIT(8) )
+#define BITS_ADC0_CALADDR(_X_)                            ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_ADC0_CTR1 */
+#define BITS_ADC0_DLL_OUT(_X_)                            ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
+#define BITS_ADC0_DLLOOF(_X_)                             ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)) )
+#define BIT_ADC0_IQ_SWAP                                  ( BIT(14) )
+#define BITS_ADC0_DLLIN(_X_)                              ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
+#define BIT_ADC0_IQ_OUT_MSB_INV                           ( BIT(7) )
+#define BIT_ADC0_IQ_IN_MSB_INV                            ( BIT(6) )
+#define BIT_ADC0_DLL_SOFT_RST                             ( BIT(4) )
+#define BIT_ADC0_DLLWR                                    ( BIT(3) )
+#define BIT_ADC0_DLLRD                                    ( BIT(2) )
+#define BIT_ADC0_DLLEN                                    ( BIT(1) )
+#define BIT_ADC0_DEBUG_EN                                 ( BIT(0) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_ADC0_CTR2 */
+#define BITS_ADC0_RSV_0(_X_)                              ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_ADC0_DIG_CLK_SEL_0                            ( BIT(11) )
+#define BIT_ADC0_VCM_SEL_0                                ( BIT(10) )
+#define BITS_ADC0_DELAY_CAP_0(_X_)                        ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ADC0_BIT_SEL_0(_X_)                          ( (_X_) << 6 & (BIT(6)|BIT(7)) )
+#define BITS_ADC0_VREF_SEL_0(_X_)                         ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_ADC0_VREF_BOOST_0(_X_)                       ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_ADC0_QUANT_BOOST_0(_X_)                      ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_ADC0_CTR3 */
+#define BITS_ADC0_RSV_1(_X_)                              ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_ADC0_DIG_CLK_SEL_1                            ( BIT(11) )
+#define BIT_ADC0_VCM_SEL_1                                ( BIT(10) )
+#define BITS_ADC0_DELAY_CAP_1(_X_)                        ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ADC0_BIT_SEL_1(_X_)                          ( (_X_) << 6 & (BIT(6)|BIT(7)) )
+#define BITS_ADC0_VREF_SEL_1(_X_)                         ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_ADC0_VREF_BOOST_1(_X_)                       ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_ADC0_QUANT_BOOST_1(_X_)                      ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_CAL_CTR0 */
+#define BIT_LDO_EN_AUTO_EN                                ( BIT(27) )
+#define BIT_LDO_EN_FRC                                    ( BIT(26) )
+#define BIT_BG_EN_AUTO_EN                                 ( BIT(25) )
+#define BIT_BG_EN_FRC                                     ( BIT(24) )
+#define BITS_ADC_CLK_CAL_DLY(_X_)                         ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_ADA_CAL_WAIT(_X_)                            ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BIT_CLK_ADA_CAL_EN                                ( BIT(6) )
+#define BIT_DAC_PD_CAL                                    ( BIT(5) )
+#define BIT_ADC0_EN_CAL                                   ( BIT(3) )
+#define BIT_ADC0_CAL                                      ( BIT(1) )
+#define BIT_ADA_MODE_SEL                                  ( BIT(0) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_CAL_CTR1 */
+#define BITS_ADC0_Q_DC(_X_)                               ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) )
+#define BITS_ADC0_I_DC(_X_)                               ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_CAL_CTR3 */
+#define BIT_ADA0_CAL_START                                ( BIT(0) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_CAL_STS0 */
+#define BIT_ADA0_CAL_DONE                                 ( BIT(31) )
+#define BITS_ADC0_I_CAL_RESULT(_X_)                       ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_CAL_STS1 */
+#define BITS_ADC0_Q_CAL_RESULT(_X_)                       ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_ADA_CTRL0 */
+#define BITS_ADA_AUTO_CTRL(_X_)                           (_X_)
+
+/* bits definitions for register REG_ADA_APB_RF_APB_ADA_CTRL1 */
+#define BITS_ADA_FRC_CTRL(_X_)                            (_X_)
+
+/* bits definitions for register REG_ADA_APB_RF_APB_RX_GSM_DFT */
+#define BITS_RX_GSM_DFT_Q(_X_)                            ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) )
+#define BITS_RX_GSM_DFT_I(_X_)                            ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
+
+/* bits definitions for register REG_ADA_APB_RF_APB_RX_3G_DFT */
+#define BITS_RX_3G_DFT_Q(_X_)                             ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) )
+#define BITS_RX_3G_DFT_I(_X_)                             ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
+
+#endif
diff --git a/include/soc/sprd/chip_x20/__regs_ahb_rf_cp2.h b/include/soc/sprd/chip_x20/__regs_ahb_rf_cp2.h
new file mode 100644
index 00000000..d7cf335a
--- /dev/null
+++ b/include/soc/sprd/chip_x20/__regs_ahb_rf_cp2.h
@@ -0,0 +1,160 @@
+/*
+ * Copyright (C) 2014 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+#ifndef __SCI_GLB_REGS_H__
+#error  "Don't include this file directly, Pls include sci_glb_regs.h"
+#endif
+
+
+#ifndef __H_REGS_AHB_RF_CP2_HEADFILE_H__
+#define __H_REGS_AHB_RF_CP2_HEADFILE_H__ __FILE__
+
+#define	REGS_AHB_RF_CP2
+
+/* registers definitions for AHB_RF_CP2 */
+#define REG_AHB_RF_CP2_AHB_RST0                           SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x0000)
+#define REG_AHB_RF_CP2_AHB_EB0                            SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x0004)
+#define REG_AHB_RF_CP2_ARCH_EB_REG                        SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x0084)
+#define REG_AHB_RF_CP2_AHB_BUS_CTL0                       SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x00A0)
+#define REG_AHB_RF_CP2_AHB_BUS_CTL1                       SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x00A4)
+#define REG_AHB_RF_CP2_AHB_BUS_CTL2                       SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x00A8)
+#define REG_AHB_RF_CP2_AHB_SYS_CTL0                       SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x00B0)
+#define REG_AHB_RF_CP2_AHB_SYS_CTL3                       SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x00BC)
+#define REG_AHB_RF_CP2_AHB_SLP_CTL0                       SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x00D0)
+#define REG_AHB_RF_CP2_AHB_SLP_CTL1                       SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x00D4)
+#define REG_AHB_RF_CP2_AHB_SLP_CTL2                       SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x00D8)
+#define REG_AHB_RF_CP2_AHB_SYS_CTL6                       SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x00E0)
+#define REG_AHB_RF_CP2_AHB_SLP_STS0                       SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x0100)
+#define REG_AHB_RF_CP2_AHB_MTX_CTL0                       SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x0110)
+#define REG_AHB_RF_CP2_AHB_MTX_CTL1                       SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x0114)
+#define REG_AHB_RF_CP2_AHB_MTX_CTL2                       SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x0118)
+#define REG_AHB_RF_CP2_AHB_MTX_CTL3                       SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x011C)
+#define REG_AHB_RF_CP2_AHB_MTX_CTL4                       SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x0120)
+#define REG_AHB_RF_CP2_AHB_MTX_CTL5                       SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x0124)
+#define REG_AHB_RF_CP2_AHB_MTX_CTL6                       SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x0128)
+#define REG_AHB_RF_CP2_AHB_ARCH_PORT                      SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x0130)
+#define REG_AHB_RF_CP2_AHB_CHIP_ID                        SCI_ADDR(REGS_AHB_RF_CP2_BASE, 0x03FC)
+
+
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_RST0 */
+#define BIT_VPU_SOFT_RST                                  ( BIT(3) )
+#define BIT_RFSBI_SOFT_RST                                ( BIT(2) )
+#define BIT_BUSM_SOFT_RST                                 ( BIT(1) )
+#define BIT_DMA_SOFT_RST                                  ( BIT(0) )
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_EB0 */
+#define BIT_WIFI_DBG_EB                                   ( BIT(4) )
+#define BIT_BUSMON1_EB                                    ( BIT(3) )
+#define BIT_BUSMON0_EB                                    ( BIT(2) )
+#define BIT_RFSBI_EB                                      ( BIT(1) )
+#define BIT_DMA_EB                                        ( BIT(0) )
+
+/* bits definitions for register REG_AHB_RF_CP2_ARCH_EB_REG */
+#define BIT_ARCH_EB                                       ( BIT(0) )
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_BUS_CTL0 */
+#define BIT_M5_PAUSE_HW0_EN                               ( BIT(5) )
+#define BIT_M4_PAUSE_HW0_EN                               ( BIT(4) )
+#define BIT_M3_PAUSE_HW0_EN                               ( BIT(3) )
+#define BIT_M2_PAUSE_HW0_EN                               ( BIT(2) )
+#define BIT_M1_PAUSE_HW0_EN                               ( BIT(1) )
+#define BIT_M0_PAUSE_HW0_EN                               ( BIT(0) )
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_BUS_CTL1 */
+#define BIT_M5_PAUSE_HW1_EN                               ( BIT(5) )
+#define BIT_M4_PAUSE_HW1_EN                               ( BIT(4) )
+#define BIT_M3_PAUSE_HW1_EN                               ( BIT(3) )
+#define BIT_M2_PAUSE_HW1_EN                               ( BIT(2) )
+#define BIT_M1_PAUSE_HW1_EN                               ( BIT(1) )
+#define BIT_M0_PAUSE_HW1_EN                               ( BIT(0) )
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_BUS_CTL2 */
+#define BIT_M5_PAUSE_SW                                   ( BIT(5) )
+#define BIT_M4_PAUSE_SW                                   ( BIT(4) )
+#define BIT_M3_PAUSE_SW                                   ( BIT(3) )
+#define BIT_M2_PAUSE_SW                                   ( BIT(2) )
+#define BIT_M1_PAUSE_SW                                   ( BIT(1) )
+#define BIT_M0_PAUSE_SW                                   ( BIT(0) )
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_SYS_CTL0 */
+#define BITS_WIFI_MON_OUT(_X_)                            ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)) )
+#define BITS_BUSMON1_CHN_SEL(_X_)                         ( (_X_) << 6 & (BIT(6)|BIT(7)) )
+#define BITS_BUSMON0_CHN_SEL(_X_)                         ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_WIFI_MON_SEL(_X_)                            ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_SYS_CTL3 */
+#define BITS_DMA_REQ_HW_SEL(_X_)                          ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) )
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_SLP_CTL0 */
+#define BIT_APB_STOP                                      ( BIT(5) )
+#define BIT_MCU_CORE_SLP                                  ( BIT(1) )
+#define BIT_MCU_FORCE_SYS_SLP                             ( BIT(0) )
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_SLP_CTL1 */
+#define BIT_MCU_LIGHT_SLEEP_EN                            ( BIT(8) )
+#define BIT_DMA_ACT_LIGHT_EN                              ( BIT(7) )
+#define BIT_DMA_SLP_MODE                                  ( BIT(6) )
+#define BIT_MCU_DEEP_SLP_EN                               ( BIT(4) )
+#define BIT_MCU_SYS_SLP_EN                                ( BIT(3) )
+#define BIT_MCU_DMA_WAKE_UP_EN                            ( BIT(2) )
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_SLP_CTL2 */
+#define BITS_DMA_REQ_WAKE_EN(_X_)                         ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) )
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_SYS_CTL6 */
+#define BIT_PTEST                                         ( BIT(0) )
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_SLP_STS0 */
+#define BIT_MTX_M5_STOP                                   ( BIT(5) )
+#define BIT_MTX_M4_STOP                                   ( BIT(4) )
+#define BIT_MTX_M3_STOP                                   ( BIT(3) )
+#define BIT_MTX_M2_STOP                                   ( BIT(2) )
+#define BIT_MTX_M1_STOP                                   ( BIT(1) )
+#define BIT_MTX_M0_STOP                                   ( BIT(0) )
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_MTX_CTL0 */
+#define BITS_MATRIX_CTRL0(_X_)                            (_X_)
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_MTX_CTL1 */
+#define BITS_MATRIX_CTRL1(_X_)                            (_X_)
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_MTX_CTL2 */
+#define BITS_MATRIX_CTRL2(_X_)                            (_X_)
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_MTX_CTL3 */
+#define BITS_MATRIX_CTRL3(_X_)                            (_X_)
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_MTX_CTL4 */
+#define BITS_MATRIX_CTRL4(_X_)                            (_X_)
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_MTX_CTL5 */
+#define BITS_MATRIX_CTRL5(_X_)                            (_X_)
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_MTX_CTL6 */
+#define BITS_MATRIX_CTRL6(_X_)                            (_X_)
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_ARCH_PORT */
+#define BIT_MCU_PROT                                      ( BIT(16) )
+#define BITS_ARCH_PROT_VAL(_X_)                           ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_AHB_RF_CP2_AHB_CHIP_ID */
+#define BITS_ID_BASE(_X_)                                 ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_MX_REG(_X_)                                  ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+#endif
diff --git a/include/soc/sprd/chip_x20/__regs_ana_apb_if.h b/include/soc/sprd/chip_x20/__regs_ana_apb_if.h
new file mode 100644
index 00000000..aac3136d
--- /dev/null
+++ b/include/soc/sprd/chip_x20/__regs_ana_apb_if.h
@@ -0,0 +1,932 @@
+/*
+ * Copyright (C) 2014 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+#ifndef __SCI_GLB_REGS_H__
+#error  "Don't include this file directly, Pls include sci_glb_regs.h"
+#endif
+
+
+#ifndef __H_REGS_ANA_APB_IF_HEADFILE_H__
+#define __H_REGS_ANA_APB_IF_HEADFILE_H__ __FILE__
+
+#define	REGS_ANA_APB_IF
+
+/* registers definitions for ANA_APB_IF */
+#define REG_ANA_APB_IF_ARM_MODULE_EN                      SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0000)
+#define REG_ANA_APB_IF_ARM_CLK_EN                         SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0004)
+#define REG_ANA_APB_IF_RTC_CLK_EN                         SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0008)
+#define REG_ANA_APB_IF_ARM_RST                            SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x000C)
+#define REG_ANA_APB_IF_LDO_DCDC_PD_RTCSET                 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0010)
+#define REG_ANA_APB_IF_LDO_DCDC_PD_RTCCLR                 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0014)
+#define REG_ANA_APB_IF_RTC_CTRL                           SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0018)
+#define REG_ANA_APB_IF_LDO_PD_CTRL                        SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x001C)
+#define REG_ANA_APB_IF_LDO_V_CTRL0                        SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0020)
+#define REG_ANA_APB_IF_LDO_V_CTRL1                        SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0024)
+#define REG_ANA_APB_IF_LDO_V_CTRL2                        SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0028)
+#define REG_ANA_APB_IF_LDO_CAL_CTRL0                      SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x002C)
+#define REG_ANA_APB_IF_LDO_CAL_CTRL1                      SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0030)
+#define REG_ANA_APB_IF_LDO_CAL_CTRL2                      SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0034)
+#define REG_ANA_APB_IF_LDO_CAL_CTRL3                      SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0038)
+#define REG_ANA_APB_IF_LDO_CAL_CTRL4                      SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x003C)
+#define REG_ANA_APB_IF_LDO_CAL_CTRL5                      SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0040)
+#define REG_ANA_APB_IF_LDO_CAL_CTRL6                      SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0044)
+#define REG_ANA_APB_IF_AUXAD_CTL                          SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0048)
+#define REG_ANA_APB_IF_DCDC_CTRL0                         SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x004C)
+#define REG_ANA_APB_IF_DCDC_CTRL1                         SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0050)
+#define REG_ANA_APB_IF_DCDC_CTRL2                         SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0054)
+#define REG_ANA_APB_IF_DCDC_CTRL3                         SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0058)
+#define REG_ANA_APB_IF_DCDC_CTRL4                         SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x005C)
+#define REG_ANA_APB_IF_DCDC_CTRL5                         SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0060)
+#define REG_ANA_APB_IF_DCDC_CTRL6                         SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0064)
+#define REG_ANA_APB_IF_DDR2_CTRL                          SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0068)
+#define REG_ANA_APB_IF_SLP_WAIT_DCDCARM                   SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x006C)
+#define REG_ANA_APB_IF_LDO1828_XTL_CTL                    SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0070)
+#define REG_ANA_APB_IF_LDO_SLP_CTRL0                      SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0074)
+#define REG_ANA_APB_IF_LDO_SLP_CTRL1                      SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0078)
+#define REG_ANA_APB_IF_LDO_SLP_CTRL2                      SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x007C)
+#define REG_ANA_APB_IF_LDO_SLP_CTRL3                      SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0080)
+#define REG_ANA_APB_IF_AUD_SLP_CTRL4                      SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0084)
+#define REG_ANA_APB_IF_DCDC_SLP_CTRL                      SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0088)
+#define REG_ANA_APB_IF_XTL_WAIT_CTRL                      SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x008C)
+#define REG_ANA_APB_IF_FLASH_CTRL                         SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0090)
+#define REG_ANA_APB_IF_WHTLED_CTRL0                       SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0094)
+#define REG_ANA_APB_IF_WHTLED_CTRL1                       SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0098)
+#define REG_ANA_APB_IF_WHTLED_CTRL2                       SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x009C)
+#define REG_ANA_APB_IF_ANA_DRV_CTRL                       SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00A0)
+#define REG_ANA_APB_IF_VIBR_CTRL0                         SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00A4)
+#define REG_ANA_APB_IF_VIBR_CTRL1                         SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00A8)
+#define REG_ANA_APB_IF_VIBR_CTRL2                         SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00AC)
+#define REG_ANA_APB_IF_VIBR_WR_PROT_VALUE                 SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00B0)
+#define REG_ANA_APB_IF_AUDIO_CTRL                         SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00B4)
+#define REG_ANA_APB_IF_CHGR_CTRL0                         SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00B8)
+#define REG_ANA_APB_IF_CHGR_CTRL1                         SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00BC)
+#define REG_ANA_APB_IF_CHGR_CTRL2                         SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00C0)
+#define REG_ANA_APB_IF_CHGR_STATUS                        SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00C4)
+#define REG_ANA_APB_IF_ANA_MIXED_CTRL                     SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00C8)
+#define REG_ANA_APB_IF_PWR_XTL_EN0                        SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00CC)
+#define REG_ANA_APB_IF_PWR_XTL_EN1                        SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00D0)
+#define REG_ANA_APB_IF_PWR_XTL_EN2                        SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00D4)
+#define REG_ANA_APB_IF_PWR_XTL_EN3                        SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00D8)
+#define REG_ANA_APB_IF_PWR_XTL_EN4                        SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00DC)
+#define REG_ANA_APB_IF_PWR_XTL_EN5                        SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00E0)
+#define REG_ANA_APB_IF_ANA_STATUS                         SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00E4)
+#define REG_ANA_APB_IF_POR_RST_MONITOR                    SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00E8)
+#define REG_ANA_APB_IF_WDG_RST_MONITOR                    SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00EC)
+#define REG_ANA_APB_IF_POR_PIN_RST_MONITOR                SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00F0)
+#define REG_ANA_APB_IF_POR_SRC_FLAG                       SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00F4)
+#define REG_ANA_APB_IF_POR_7S_CTRL                        SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00F8)
+#define REG_ANA_APB_IF_INT_DEBUG                          SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x00FC)
+#define REG_ANA_APB_IF_GPI_DEBUG                          SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0100)
+#define REG_ANA_APB_IF_HWRST_RTC                          SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0104)
+#define REG_ANA_APB_IF_CHIP_ID_LOW                        SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0108)
+#define REG_ANA_APB_IF_CHIP_ID_HIGH                       SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x010C)
+#define REG_ANA_APB_IF_ARM_MF_REG                         SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0110)
+#define REG_ANA_APB_IF_AFUSE_CTRL                         SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0114)
+#define REG_ANA_APB_IF_AFUSE_OUT0                         SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0118)
+#define REG_ANA_APB_IF_AFUSE_OUT1                         SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x011C)
+#define REG_ANA_APB_IF_AFUSE_OUT2                         SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0120)
+#define REG_ANA_APB_IF_AFUSE_OUT3                         SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0124)
+#define REG_ANA_APB_IF_CA_CTRL4                           SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0128)
+#define REG_ANA_APB_IF_MCU_WR_PROT_VALUE                  SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x012C)
+#define REG_ANA_APB_IF_MP_PWR_CTRL0                       SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0130 )
+#define REG_ANA_APB_IF_MP_PWR_CTRL1                       SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0134)
+#define REG_ANA_APB_IF_MP_PWR_CTRL2                       SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0138)
+#define REG_ANA_APB_IF_MP_PWR_CTRL3                       SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x013C)
+#define REG_ANA_APB_IF_MP_LDO_CTRL                        SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0140)
+#define REG_ANA_APB_IF_MP_CHG_CTRL                        SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0144)
+#define REG_ANA_APB_IF_MP_MISC_CTRL                       SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0148)
+#define REG_ANA_APB_IF_MP_DCDC_DEDT_CTRL                  SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x014C)
+#define REG_ANA_APB_IF_CA_CTRL0                           SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0150)
+#define REG_ANA_APB_IF_CA_CTRL1                           SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0154)
+#define REG_ANA_APB_IF_CA_CTRL2                           SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0158)
+#define REG_ANA_APB_IF_CA_CTRL3                           SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x015C)
+#define REG_ANA_APB_IF_DCDC_CORE_ADI                      SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0160)
+#define REG_ANA_APB_IF_DCDC_ARM_ADI                       SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0164)
+#define REG_ANA_APB_IF_DCDC_MEM_ADI                       SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0168)
+#define REG_ANA_APB_IF_DCDC_GEN_ADI                       SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x016C)
+#define REG_ANA_APB_IF_DCDC_WRF_ADI                       SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0170)
+#define REG_ANA_APB_IF_DCDC_WPA_ADI                       SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x0174)
+#define REG_ANA_APB_IF_DCDC_WPA_DCM_ADI                   SCI_ADDR(REGS_ANA_APB_IF_BASE, 0x017C)
+
+
+
+/* bits definitions for register REG_ANA_APB_IF_ARM_MODULE_EN */
+#define BIT_ANA_THM_EN                                    ( BIT(12) )
+#define BIT_ANA_BLTC_EN                                   ( BIT(10) )
+#define BIT_ANA_PINREG_EN                                 ( BIT(9) )
+#define BIT_ANA_FGU_EN                                    ( BIT(8) )
+#define BIT_ANA_GPIO_EN                                   ( BIT(7) )
+#define BIT_ANA_ADC_EN                                    ( BIT(6) )
+#define BIT_ANA_HDT_EN                                    ( BIT(5) )
+#define BIT_ANA_AUD_EN                                    ( BIT(4) )
+#define BIT_ANA_EIC_EN                                    ( BIT(3) )
+#define BIT_ANA_WDG_EN                                    ( BIT(2) )
+#define BIT_ANA_RTC_EN                                    ( BIT(1) )
+
+/* bits definitions for register REG_ANA_APB_IF_ARM_CLK_EN */
+#define BIT_ANA_CLK_AUXAD_EN                              ( BIT(9) )
+#define BIT_ANA_CLK_AUXADC_EN                             ( BIT(8) )
+#define BIT_ANA_CLK_AUD_HID_EN                            ( BIT(5) )
+#define BIT_ANA_CLK_AUD_HBD_EN                            ( BIT(4) )
+#define BIT_ANA_CLK_AUD_LOOP_EN                           ( BIT(3) )
+#define BIT_ANA_CLK_AUD_6P5M_EN                           ( BIT(2) )
+#define BIT_ANA_CLK_AUDIF_EN                              ( BIT(1) )
+
+/* bits definitions for register REG_ANA_APB_IF_RTC_CLK_EN */
+#define BIT_ANA_RTC_FLASH_EN                              ( BIT(13) )
+#define BIT_ANA_RTC_THMA_AUTO_EN                          ( BIT(12) )
+#define BIT_ANA_RTC_THMA_EN                               ( BIT(11) )
+#define BIT_ANA_RTC_THM_EN                                ( BIT(10) )
+#define BIT_ANA_RTC_BLTC_EN                               ( BIT(8) )
+#define BIT_ANA_RTC_FGU_EN                                ( BIT(7) )
+#define BIT_ANA_RTC_FGUA_EN                               ( BIT(6) )
+#define BIT_ANA_RTC_VIBR_EN                               ( BIT(5) )
+#define BIT_ANA_RTC_AUD_EN                                ( BIT(4) )
+#define BIT_ANA_RTC_EIC_EN                                ( BIT(3) )
+#define BIT_ANA_RTC_WDG_EN                                ( BIT(2) )
+#define BIT_ANA_RTC_RTC_EN                                ( BIT(1) )
+#define BIT_ANA_RTC_ARCH_EN                               ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_ARM_RST */
+#define BIT_ANA_THMA_SOFT_RST                             ( BIT(14) )
+#define BIT_ANA_THM_SOFT_RST                              ( BIT(13) )
+#define BIT_ANA_AUD_32K_SOFT_RST                          ( BIT(12) )
+#define BIT_ANA_AUDTX_SOFT_RST                            ( BIT(11) )
+#define BIT_ANA_AUDRX_SOFT_RST                            ( BIT(10) )
+#define BIT_ANA_AUD_SOFT_RST                              ( BIT(9) )
+#define BIT_ANA_AUD_HDT_SOFT_RST                          ( BIT(8) )
+#define BIT_ANA_GPIO_SOFT_RST                             ( BIT(7) )
+#define BIT_ANA_ADC_SOFT_RST                              ( BIT(6) )
+#define BIT_ANA_PWM0_SOFT_RST                             ( BIT(5) )
+#define BIT_ANA_FGU_SOFT_RST                              ( BIT(4) )
+#define BIT_ANA_EIC_SOFT_RST                              ( BIT(3) )
+#define BIT_ANA_WDG_SOFT_RST                              ( BIT(2) )
+#define BIT_ANA_RTC_SOFT_RST                              ( BIT(1) )
+#define BIT_ANA_BLTC_SOFT_RST                             ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_DCDC_PD_RTCSET */
+#define BIT_ANA_LDO_AVDD18_PD_RTCSET                      ( BIT(15) )
+#define BIT_ANA_DCDC_OTP_PD_RTCSET                        ( BIT(14) )
+#define BIT_ANA_DCDC_WRF_PD_RTCSET                        ( BIT(13) )
+#define BIT_ANA_DCDC_GEN_PD_RTCSET                        ( BIT(12) )
+#define BIT_ANA_DCDC_MEM_PD_RTCSET                        ( BIT(11) )
+#define BIT_ANA_DCDC_ARM_PD_RTCSET                        ( BIT(10) )
+#define BIT_ANA_DCDC_CORE_PD_RTCSET                       ( BIT(9) )
+#define BIT_ANA_LDO_EMMCCORE_PD_RTCSET                    ( BIT(8) )
+#define BIT_ANA_LDO_EMMCIO_PD_RTCSET                      ( BIT(7) )
+#define BIT_ANA_LDO_RF2_PD_RTCSET                         ( BIT(6) )
+#define BIT_ANA_LDO_RF1_PD_RTCSET                         ( BIT(5) )
+#define BIT_ANA_LDO_RF0_PD_RTCSET                         ( BIT(4) )
+#define BIT_ANA_LDO_VDD25_PD_RTCSET                       ( BIT(3) )
+#define BIT_ANA_LDO_VDD28_PD_RTCSET                       ( BIT(2) )
+#define BIT_ANA_LDO_VDD18_PD_RTCSET                       ( BIT(1) )
+#define BIT_ANA_BG_PD_RTCSET                              ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_DCDC_PD_RTCCLR */
+#define BIT_ANA_LDO_AVDD18_PD_RTCCLR                      ( BIT(15) )
+#define BIT_ANA_DCDC_OTP_PD_RTCCLR                        ( BIT(14) )
+#define BIT_ANA_DCDC_WRF_PD_RTCCLR                        ( BIT(13) )
+#define BIT_ANA_DCDC_GEN_PD_RTCCLR                        ( BIT(12) )
+#define BIT_ANA_DCDC_MEM_PD_RTCCLR                        ( BIT(11) )
+#define BIT_ANA_DCDC_ARM_PD_RTCCLR                        ( BIT(10) )
+#define BIT_ANA_DCDC_CORE_PD_RTCCLR                       ( BIT(9) )
+#define BIT_ANA_LDO_EMMCCORE_PD_RTCCLR                    ( BIT(8) )
+#define BIT_ANA_LDO_EMMCIO_PD_RTCCLR                      ( BIT(7) )
+#define BIT_ANA_LDO_RF2_PD_RTCCLR                         ( BIT(6) )
+#define BIT_ANA_LDO_RF1_PD_RTCCLR                         ( BIT(5) )
+#define BIT_ANA_LDO_RF0_PD_RTCCLR                         ( BIT(4) )
+#define BIT_ANA_LDO_VDD25_PD_RTCCLR                       ( BIT(3) )
+#define BIT_ANA_LDO_VDD28_PD_RTCCLR                       ( BIT(2) )
+#define BIT_ANA_LDO_VDD18_PD_RTCCLR                       ( BIT(1) )
+#define BIT_ANA_BG_PD_RTCCLR                              ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_RTC_CTRL */
+#define BITS_ANA_XOSC32K_CTL_STS(_X_)                     ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BIT_ANA_XOSC32K_CTL_B3_RTCCLR                     ( BIT(7) )
+#define BIT_ANA_XOSC32K_CTL_B2_RTCCLR                     ( BIT(6) )
+#define BIT_ANA_XOSC32K_CTL_B1_RTCCLR                     ( BIT(5) )
+#define BIT_ANA_XOSC32K_CTL_B0_RTCCLR                     ( BIT(4) )
+#define BIT_ANA_XOSC32K_CTL_B3_RTCSET                     ( BIT(3) )
+#define BIT_ANA_XOSC32K_CTL_B2_RTCSET                     ( BIT(2) )
+#define BIT_ANA_XOSC32K_CTL_B1_RTCSET                     ( BIT(1) )
+#define BIT_ANA_XOSC32K_CTL_B0_RTCSET                     ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_PD_CTRL */
+#define BIT_ANA_LDO_LPREF_PD_SW                           ( BIT(12) )
+#define BIT_ANA_DCDC_WPA_PD                               ( BIT(11) )
+#define BIT_ANA_LDO_CLSG_PD                               ( BIT(10) )
+#define BIT_ANA_LDO_USB_PD                                ( BIT(9) )
+#define BIT_ANA_LDO_CAMMOT_PD                             ( BIT(8) )
+#define BIT_ANA_LDO_CAMIO_PD                              ( BIT(7) )
+#define BIT_ANA_LDO_CAMD_PD                               ( BIT(6) )
+#define BIT_ANA_LDO_CAMA_PD                               ( BIT(5) )
+#define BIT_ANA_LDO_SIM2_PD                               ( BIT(4) )
+#define BIT_ANA_LDO_SIM1_PD                               ( BIT(3) )
+#define BIT_ANA_LDO_SIM0_PD                               ( BIT(2) )
+#define BIT_ANA_LDO_SD_PD                                 ( BIT(1) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_V_CTRL0 */
+#define BITS_ANA_LDO_EMMCCORE_V(_X_)                      ( (_X_) << 14 & (BIT(14)|BIT(15)) )
+#define BITS_ANA_LDO_EMMCIO_V(_X_)                        ( (_X_) << 12 & (BIT(12)|BIT(13)) )
+#define BITS_ANA_LDO_RF2_V(_X_)                           ( (_X_) << 10 & (BIT(10)|BIT(11)) )
+#define BITS_ANA_LDO_RF1_V(_X_)                           ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ANA_LDO_RF0_V(_X_)                           ( (_X_) << 6 & (BIT(6)|BIT(7)) )
+#define BITS_ANA_LDO_VDD25_V(_X_)                         ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_ANA_LDO_VDD28_V(_X_)                         ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_ANA_LDO_VDD18_V(_X_)                         ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_V_CTRL1 */
+#define BITS_ANA_LDO_SIM2_V(_X_)                          ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ANA_LDO_SIM1_V(_X_)                          ( (_X_) << 6 & (BIT(6)|BIT(7)) )
+#define BITS_ANA_LDO_SIM0_V(_X_)                          ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_ANA_LDO_SD_V(_X_)                            ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_ANA_LDO_AVDD18_V(_X_)                        ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_V_CTRL2 */
+#define BITS_ANA_VBATBK_RES(_X_)                          ( (_X_) << 14 & (BIT(14)|BIT(15)) )
+#define BITS_ANA_VBATBK_V(_X_)                            ( (_X_) << 12 & (BIT(12)|BIT(13)) )
+#define BITS_ANA_LDO_CLSG_V(_X_)                          ( (_X_) << 10 & (BIT(10)|BIT(11)) )
+#define BITS_ANA_LDO_USB_V(_X_)                           ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ANA_LDO_CAMMOT_V(_X_)                        ( (_X_) << 6 & (BIT(6)|BIT(7)) )
+#define BITS_ANA_LDO_CAMIO_V(_X_)                         ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_ANA_LDO_CAMD_V(_X_)                          ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_ANA_LDO_CAMA_V(_X_)                          ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_CAL_CTRL0 */
+#define BITS_ANA_LDO_VDD25_CAL(_X_)                       ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_ANA_LDO_VDD28_CAL(_X_)                       ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_ANA_LDO_VDD18_CAL(_X_)                       ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_CAL_CTRL1 */
+#define BITS_ANA_LDO_RF2_CAL(_X_)                         ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_ANA_LDO_RF1_CAL(_X_)                         ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_ANA_LDO_RF0_CAL(_X_)                         ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_CAL_CTRL2 */
+#define BITS_ANA_LDO_USB_CAL(_X_)                         ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_ANA_LDO_EMMCCORE_CAL(_X_)                    ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_ANA_LDO_EMMCIO_CAL(_X_)                      ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_CAL_CTRL3 */
+#define BITS_ANA_LDO_SD_CAL(_X_)                          ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_ANA_LDO_AVDD18_CAL(_X_)                      ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_CAL_CTRL4 */
+#define BITS_ANA_LDO_CAMA_CAL(_X_)                        ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_ANA_LDO_SIM2_CAL(_X_)                        ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_ANA_LDO_SIM_CAL(_X_)                         ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_CAL_CTRL5 */
+#define BITS_ANA_LDO_CAMMOT_CAL(_X_)                      ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_ANA_LDO_CAMIO_CAL(_X_)                       ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_ANA_LDO_CAMD_CAL(_X_)                        ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_CAL_CTRL6 */
+#define BITS_ANA_LDOA_CAL_SEL(_X_)                        ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)) )
+#define BITS_ANA_LDOD_CAL_SEL(_X_)                        ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) )
+#define BITS_ANA_LDODCDC_CAL_SEL(_X_)                     ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_ANA_LDO_CLSG_CAL(_X_)                        ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_AUXAD_CTL */
+#define BIT_ANA_AUXAD_CURRENTSEN_EN                       ( BIT(6) )
+#define BIT_ANA_AUXAD_CURRENTSEL                          ( BIT(5) )
+#define BITS_ANA_AUXAD_CURRENT_IBS(_X_)                   ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_CTRL0 */
+#define BIT_ANA_DCDC_CORE_LP_EN                           ( BIT(15) )
+#define BIT_ANA_DCDC_CORE_CL_CTRL                         ( BIT(14) )
+#define BITS_ANA_DCDC_CORE_PDRSLOW(_X_)                   ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
+#define BIT_ANA_DCDC_CORE_PFM                             ( BIT(9) )
+#define BIT_ANA_DCDC_CORE_DCM                             ( BIT(8) )
+#define BIT_ANA_DCDC_ARM_LP_EN                            ( BIT(7) )
+#define BIT_ANA_DCDC_ARM_CL_CTRL                          ( BIT(6) )
+#define BITS_ANA_DCDC_ARM_PDRSLOW(_X_)                    ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+#define BIT_ANA_DCDC_ARM_PFM                              ( BIT(1) )
+#define BIT_ANA_DCDC_ARM_DCM                              ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_CTRL1 */
+#define BIT_ANA_DCDC_MEM_LP_EN                            ( BIT(15) )
+#define BIT_ANA_DCDC_MEM_CL_CTRL                          ( BIT(14) )
+#define BITS_ANA_DCDC_MEM_PDRSLOW(_X_)                    ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
+#define BIT_ANA_DCDC_MEM_PFM                              ( BIT(9) )
+#define BIT_ANA_DCDC_MEM_DCM                              ( BIT(8) )
+#define BIT_ANA_DCDC_GEN_LP_EN                            ( BIT(7) )
+#define BIT_ANA_DCDC_GEN_CL_CTRL                          ( BIT(6) )
+#define BITS_ANA_DCDC_GEN_PDRSLOW(_X_)                    ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+#define BIT_ANA_DCDC_GEN_PFM                              ( BIT(1) )
+#define BIT_ANA_DCDC_GEN_DCM                              ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_CTRL2 */
+#define BIT_ANA_DCDC_BG_LP_EN                             ( BIT(15) )
+#define BIT_ANA_DCDC_OTP_CHIP_PD_FLAG_CLR                 ( BIT(14) )
+#define BIT_ANA_DCDC_OTP_CHIP_PD_FLAG                     ( BIT(13) )
+#define BIT_ANA_DCDC_OTP_AUTO_PD_EN                       ( BIT(12) )
+#define BIT_ANA_DCDC_OTP_VBEOP                            ( BIT(11) )
+#define BITS_ANA_DCDC_OTP_S(_X_)                          ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) )
+#define BIT_ANA_DCDC_WRF_LP_EN                            ( BIT(7) )
+#define BIT_ANA_DCDC_WRF_CL_CTRL                          ( BIT(6) )
+#define BITS_ANA_DCDC_WRF_PDRSLOW(_X_)                    ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+#define BIT_ANA_DCDC_WRF_PFM                              ( BIT(1) )
+#define BIT_ANA_DCDC_WRF_DCM                              ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_CTRL3 */
+#define BIT_ANA_DCDC_WPA_LP_EN                            ( BIT(8) )
+#define BIT_ANA_DCDC_WPA_CL_CTRL                          ( BIT(7) )
+#define BIT_ANA_DCDC_WPA_ZXOP                             ( BIT(6) )
+#define BITS_ANA_DCDC_WPA_PDRSLOW(_X_)                    ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+#define BIT_ANA_DCDC_WPA_PFM                              ( BIT(1) )
+#define BIT_ANA_DCDC_WPA_APTEN                            ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_CTRL4 */
+#define BIT_ANA_DCDC_CORE_OSCSYCEN_SW                     ( BIT(15) )
+#define BIT_ANA_DCDC_CORE_OSCSYCEN_HW_EN                  ( BIT(14) )
+#define BIT_ANA_DCDC_CORE_OSCSYC_DIV_EN                   ( BIT(13) )
+#define BITS_ANA_DCDC_CORE_OSCSYC_DIV(_X_)                ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
+#define BIT_ANA_DCDC_ARM_OSCSYCEN_SW                      ( BIT(7) )
+#define BIT_ANA_DCDC_ARM_OSCSYCEN_HW_EN                   ( BIT(6) )
+#define BIT_ANA_DCDC_ARM_OSCSYC_DIV_EN                    ( BIT(5) )
+#define BITS_ANA_DCDC_ARM_OSCSYC_DIV(_X_)                 ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_CTRL5 */
+#define BIT_ANA_DCDC_MEM_OSCSYCEN_SW                      ( BIT(15) )
+#define BIT_ANA_DCDC_MEM_OSCSYCEN_HW_EN                   ( BIT(14) )
+#define BIT_ANA_DCDC_MEM_OSCSYC_DIV_EN                    ( BIT(13) )
+#define BITS_ANA_DCDC_MEM_OSCSYC_DIV(_X_)                 ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
+#define BIT_ANA_DCDC_GEN_OSCSYCEN_SW                      ( BIT(7) )
+#define BIT_ANA_DCDC_GEN_OSCSYCEN_HW_EN                   ( BIT(6) )
+#define BIT_ANA_DCDC_GEN_OSCSYC_DIV_EN                    ( BIT(5) )
+#define BITS_ANA_DCDC_GEN_OSCSYC_DIV(_X_)                 ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_CTRL6 */
+#define BIT_ANA_DCDC_WPA_OSCSYCEN_SW                      ( BIT(15) )
+#define BIT_ANA_DCDC_WPA_OSCSYCEN_HW_EN                   ( BIT(14) )
+#define BIT_ANA_DCDC_WPA_OSCSYC_DIV_EN                    ( BIT(13) )
+#define BITS_ANA_DCDC_WPA_OSCSYC_DIV(_X_)                 ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
+#define BIT_ANA_DCDC_WRF_OSCSYCEN_SW                      ( BIT(7) )
+#define BIT_ANA_DCDC_WRF_OSCSYCEN_HW_EN                   ( BIT(6) )
+#define BIT_ANA_DCDC_WRF_OSCSYC_DIV_EN                    ( BIT(5) )
+#define BITS_ANA_DCDC_WRF_OSCSYC_DIV(_X_)                 ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_DDR2_CTRL */
+#define BIT_ANA_DDR2_BUF_PD_HW                            ( BIT(9) )
+#define BITS_ANA_DDR2_BUF_S_DS(_X_)                       ( (_X_) << 7 & (BIT(7)|BIT(8)) )
+#define BITS_ANA_DDR2_BUF_CHNS_DS(_X_)                    ( (_X_) << 5 & (BIT(5)|BIT(6)) )
+#define BIT_ANA_DDR2_BUF_PD                               ( BIT(4) )
+#define BITS_ANA_DDR2_BUF_S(_X_)                          ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_ANA_DDR2_BUF_CHNS(_X_)                       ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_ANA_APB_IF_SLP_WAIT_DCDCARM */
+#define BITS_ANA_SLP_IN_WAIT_DCDCARM(_X_)                 ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_ANA_SLP_OUT_WAIT_DCDCARM(_X_)                ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO1828_XTL_CTL */
+#define BIT_ANA_LDO_VDD18_EXT_XTL2_EN                     ( BIT(11) )
+#define BIT_ANA_LDO_VDD18_EXT_XTL1_EN                     ( BIT(10) )
+#define BIT_ANA_LDO_VDD18_EXT_XTL0_EN                     ( BIT(9) )
+#define BIT_ANA_LDO_VDD18_XTL2_EN                         ( BIT(8) )
+#define BIT_ANA_LDO_VDD18_XTL1_EN                         ( BIT(7) )
+#define BIT_ANA_LDO_VDD18_XTL0_EN                         ( BIT(6) )
+#define BIT_ANA_LDO_VDD28_EXT_XTL2_EN                     ( BIT(5) )
+#define BIT_ANA_LDO_VDD28_EXT_XTL1_EN                     ( BIT(4) )
+#define BIT_ANA_LDO_VDD28_EXT_XTL0_EN                     ( BIT(3) )
+#define BIT_ANA_LDO_VDD28_XTL2_EN                         ( BIT(2) )
+#define BIT_ANA_LDO_VDD28_XTL1_EN                         ( BIT(1) )
+#define BIT_ANA_LDO_VDD28_XTL0_EN                         ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_SLP_CTRL0 */
+#define BIT_ANA_SLP_IO_EN                                 ( BIT(15) )
+#define BIT_ANA_SLP_DCDC_OTP_PD_EN                        ( BIT(13) )
+#define BIT_ANA_SLP_DCDCGEN_PD_EN                         ( BIT(12) )
+#define BIT_ANA_SLP_DCDCWPA_PD_EN                         ( BIT(11) )
+#define BIT_ANA_SLP_DCDCWRF_PD_EN                         ( BIT(10) )
+#define BIT_ANA_SLP_DCDCARM_PD_EN                         ( BIT(9) )
+#define BIT_ANA_SLP_LDOEMMCCORE_PD_EN                     ( BIT(7) )
+#define BIT_ANA_SLP_LDOEMMCIO_PD_EN                       ( BIT(6) )
+#define BIT_ANA_SLP_LDORF2_PD_EN                          ( BIT(5) )
+#define BIT_ANA_SLP_LDORF1_PD_EN                          ( BIT(4) )
+#define BIT_ANA_SLP_LDORF0_PD_EN                          ( BIT(3) )
+#define BIT_ANA_SLP_LDOVDD25_PD_EN                        ( BIT(2) )
+#define BIT_ANA_SLP_LDOVDD28_PD_EN                        ( BIT(1) )
+#define BIT_ANA_SLP_LDOVDD18_PD_EN                        ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_SLP_CTRL1 */
+#define BIT_ANA_SLP_LDO_PD_EN                             ( BIT(12) )
+#define BIT_ANA_SLP_LDOLPREF_PD_EN                        ( BIT(11) )
+#define BIT_ANA_SLP_LDOCLSG_PD_EN                         ( BIT(10) )
+#define BIT_ANA_SLP_LDOUSB_PD_EN                          ( BIT(9) )
+#define BIT_ANA_SLP_LDOCAMMOT_PD_EN                       ( BIT(8) )
+#define BIT_ANA_SLP_LDOCAMIO_PD_EN                        ( BIT(7) )
+#define BIT_ANA_SLP_LDOCAMD_PD_EN                         ( BIT(6) )
+#define BIT_ANA_SLP_LDOCAMA_PD_EN                         ( BIT(5) )
+#define BIT_ANA_SLP_LDOSIM2_PD_EN                         ( BIT(4) )
+#define BIT_ANA_SLP_LDOSIM1_PD_EN                         ( BIT(3) )
+#define BIT_ANA_SLP_LDOSIM0_PD_EN                         ( BIT(2) )
+#define BIT_ANA_SLP_LDOSD_PD_EN                           ( BIT(1) )
+#define BIT_ANA_SLP_LDOAVDD18_PD_EN                       ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_SLP_CTRL2 */
+#define BIT_ANA_SLP_DCDC_BG_LP_EN                         ( BIT(15) )
+#define BIT_ANA_SLP_DCDCCORE_LP_EN                        ( BIT(11) )
+#define BIT_ANA_SLP_DCDCMEM_LP_EN                         ( BIT(10) )
+#define BIT_ANA_SLP_DCDCARM_LP_EN                         ( BIT(9) )
+#define BIT_ANA_SLP_DCDCGEN_LP_EN                         ( BIT(8) )
+#define BIT_ANA_SLP_DCDCWPA_LP_EN                         ( BIT(6) )
+#define BIT_ANA_SLP_DCDCWRF_LP_EN                         ( BIT(5) )
+#define BIT_ANA_SLP_LDOEMMCCORE_LP_EN                     ( BIT(4) )
+#define BIT_ANA_SLP_LDOEMMCIO_LP_EN                       ( BIT(3) )
+#define BIT_ANA_SLP_LDORF2_LP_EN                          ( BIT(2) )
+#define BIT_ANA_SLP_LDORF1_LP_EN                          ( BIT(1) )
+#define BIT_ANA_SLP_LDORF0_LP_EN                          ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_LDO_SLP_CTRL3 */
+#define BIT_ANA_SLP_BG_LP_EN                              ( BIT(15) )
+#define BIT_ANA_SLP_LDOVDD25_LP_EN                        ( BIT(13) )
+#define BIT_ANA_SLP_LDOVDD28_LP_EN                        ( BIT(12) )
+#define BIT_ANA_SLP_LDOVDD18_LP_EN                        ( BIT(11) )
+#define BIT_ANA_SLP_LDOCLSG_LP_EN                         ( BIT(10) )
+#define BIT_ANA_SLP_LDOUSB_LP_EN                          ( BIT(9) )
+#define BIT_ANA_SLP_LDOCAMMOT_LP_EN                       ( BIT(8) )
+#define BIT_ANA_SLP_LDOCAMIO_LP_EN                        ( BIT(7) )
+#define BIT_ANA_SLP_LDOCAMD_LP_EN                         ( BIT(6) )
+#define BIT_ANA_SLP_LDOCAMA_LP_EN                         ( BIT(5) )
+#define BIT_ANA_SLP_LDOSIM2_LP_EN                         ( BIT(4) )
+#define BIT_ANA_SLP_LDOSIM1_LP_EN                         ( BIT(3) )
+#define BIT_ANA_SLP_LDOSIM0_LP_EN                         ( BIT(2) )
+#define BIT_ANA_SLP_LDOSD_LP_EN                           ( BIT(1) )
+#define BIT_ANA_SLP_LDOAVDD18_LP_EN                       ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_AUD_SLP_CTRL4 */
+#define BIT_ANA_SLP_AUD_PA_SW_PD_EN                       ( BIT(15) )
+#define BIT_ANA_SLP_AUD_PA_LDO_PD_EN                      ( BIT(14) )
+#define BIT_ANA_SLP_AUD_PA_PD_EN                          ( BIT(13) )
+#define BIT_ANA_SLP_AUD_OVP_PD_PD_EN                      ( BIT(9) )
+#define BIT_ANA_SLP_AUD_OVP_LDO_PD_EN                     ( BIT(8) )
+#define BIT_ANA_SLP_AUD_VB_PD_EN                          ( BIT(7) )
+#define BIT_ANA_SLP_AUD_VBO_PD_EN                         ( BIT(6) )
+#define BIT_ANA_SLP_AUD_HEADMICBIAS_PD_EN                 ( BIT(5) )
+#define BIT_ANA_SLP_AUD_MICBIAS_HV_PD_EN                  ( BIT(2) )
+#define BIT_ANA_SLP_AUD_HEADMIC_PD_EN                     ( BIT(1) )
+#define BIT_ANA_SLP_AUD_PMUR1_PD_EN                       ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_SLP_CTRL */
+#define BITS_ANA_SLP_DCDCCORE_VOL_DROP_CNT(_X_)           ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_ANA_DCDC_CORE_CTL_DS_SW(_X_)                 ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
+
+/* bits definitions for register REG_ANA_APB_IF_XTL_WAIT_CTRL */
+#define BIT_ANA_SLP_XTLBUF_PD_EN                          ( BIT(9) )
+#define BIT_ANA_XTL_EN                                    ( BIT(8) )
+#define BITS_ANA_XTL_WAIT(_X_)                            ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_ANA_APB_IF_FLASH_CTRL */
+#define BIT_ANA_FLASH_PON                                 ( BIT(15) )
+#define BIT_ANA_FLASH_V_HW_EN                             ( BIT(6) )
+#define BITS_ANA_FLASH_V_HW_STEP(_X_)                     ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_ANA_FLASH_V_SW(_X_)                          ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_ANA_APB_IF_WHTLED_CTRL0 */
+#define BIT_ANA_WHTLED_PD_STS                             ( BIT(15) )
+#define BITS_ANA_WHTLED_DC(_X_)                           ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BIT_ANA_WHTLED_BOOST_EN                           ( BIT(8) )
+#define BIT_ANA_WHTLED_SERIES_EN                          ( BIT(7) )
+#define BITS_ANA_WHTLED_V(_X_)                            ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) )
+#define BIT_ANA_WHTLED_PD                                 ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_WHTLED_CTRL1 */
+#define BIT_ANA_LCM_CABC_PWM_SEL                          ( BIT(15) )
+#define BIT_ANA_RTC_PWM0_EN                               ( BIT(14) )
+#define BIT_ANA_PWM0_EN                                   ( BIT(13) )
+#define BITS_ANA_WHTLED_ISET(_X_)                         ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_ANA_WHTLED_FRE_AD(_X_)                       ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)) )
+#define BITS_ANA_WHTLED_CLMIT_OP(_X_)                     ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_ANA_APB_IF_WHTLED_CTRL2 */
+#define BIT_ANA_WHTLED_DIMMING_SEL                        ( BIT(15) )
+#define BIT_ANA_WHTLED_PD_SEL                             ( BIT(14) )
+#define BIT_ANA_WHTLED_DIS_OVST                           ( BIT(13) )
+#define BIT_ANA_WHTLED_DIM_SEL                            ( BIT(12) )
+#define BIT_ANA_WHTLED_DE_BIAS                            ( BIT(11) )
+#define BIT_ANA_WHTLED_BUFF_SHT                           ( BIT(10) )
+#define BITS_ANA_WHTLED_STB_OP(_X_)                       ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BIT_ANA_WHTLED_CAP_OPTION                         ( BIT(7) )
+#define BIT_ANA_WHTLED_OVP_DIS                            ( BIT(6) )
+#define BITS_ANA_WHTLED_REF_DC(_X_)                       ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+
+/* bits definitions for register REG_ANA_APB_IF_ANA_DRV_CTRL */
+#define BIT_ANA_SLP_RGB_PD_EN                             ( BIT(14) )
+#define BIT_ANA_RGB_PD_HW_EN                              ( BIT(13) )
+#define BITS_ANA_RGB_V(_X_)                               ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
+#define BITS_ANA_KPLED_V(_X_)                             ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_ANA_RGB_PD_SW                                 ( BIT(2) )
+#define BIT_ANA_KPLED_PD                                  ( BIT(1) )
+#define BIT_ANA_KPLED_PD_STS                              ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_VIBR_CTRL0 */
+#define BITS_ANA_VIBR_STABLE_V_HW(_X_)                    ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_ANA_VIBR_INIT_V_HW(_X_)                      ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_ANA_VIBR_V_SW(_X_)                           ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_ANA_VIBR_PON                                  ( BIT(2) )
+#define BIT_ANA_VIBR_SW_EN                                ( BIT(1) )
+
+/* bits definitions for register REG_ANA_APB_IF_VIBR_CTRL1 */
+#define BITS_ANA_VIBR_V_CONVERT_CNT_HW(_X_)               ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ANA_APB_IF_VIBR_CTRL2 */
+#define BIT_ANA_VIBR_PWR_ON_STS                           ( BIT(15) )
+#define BIT_ANA_VIBR_HW_FLOW_ERR1                         ( BIT(14) )
+#define BIT_ANA_VIBR_HW_FLOW_ERR1_CLR                     ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_VIBR_WR_PROT_VALUE */
+#define BIT_ANA_VIBR_WR_PROT                              ( BIT(15) )
+#define BITS_ANA_VIBR_WR_PROT_VALUE(_X_)                  ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+
+/* bits definitions for register REG_ANA_APB_IF_AUDIO_CTRL */
+#define BIT_ANA_AUD_SLP_APP_RST_EN                        ( BIT(10) )
+#define BITS_ANA_CLK_AUD_HBD_DIV(_X_)                     ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BIT_ANA_CLK_AUD_LOOP_INV_EN                       ( BIT(4) )
+#define BIT_ANA_CLK_AUDIF_TX_INV_EN                       ( BIT(3) )
+#define BIT_ANA_CLK_AUDIF_RX_INV_EN                       ( BIT(2) )
+#define BIT_ANA_CLK_AUD_6P5M_TX_INV_EN                    ( BIT(1) )
+#define BIT_ANA_CLK_AUD_6P5M_RX_INV_EN                    ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_CHGR_CTRL0 */
+#define BIT_ANA_CHGR_PD_STS                               ( BIT(15) )
+#define BITS_ANA_CHGR_CV_V(_X_)                           ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_ANA_CHGR_END_V(_X_)                          ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_ANA_CHG_PUMP_V(_X_)                          ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BIT_ANA_CHGR_PD_RTCCLR                            ( BIT(1) )
+#define BIT_ANA_CHGR_PD_RTCSET                            ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_CHGR_CTRL1 */
+#define BIT_ANA_DP_DM_SW_EN                               ( BIT(15) )
+#define BITS_ANA_CHGR_CC_I(_X_)                           ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_ANA_VBAT_OVP_V(_X_)                          ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_ANA_VCHG_OVP_V(_X_)                          ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+
+/* bits definitions for register REG_ANA_APB_IF_CHGR_CTRL2 */
+#define BITS_ANA_CHG_PUMP_CAL(_X_)                        ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
+#define BIT_ANA_CHG_PUMP_PD                               ( BIT(8) )
+#define BIT_ANA_CHGR_CC_EN                                ( BIT(1) )
+#define BIT_ANA_RECHG                                     ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_CHGR_STATUS */
+#define BIT_ANA_CHG_DET_DONE                              ( BIT(11) )
+#define BIT_ANA_DP_LOW                                    ( BIT(10) )
+#define BIT_ANA_DCP_DET                                   ( BIT(9) )
+#define BIT_ANA_CHG_DET                                   ( BIT(8) )
+#define BIT_ANA_SDP_INT                                   ( BIT(7) )
+#define BIT_ANA_DCP_INT                                   ( BIT(6) )
+#define BIT_ANA_CDP_INT                                   ( BIT(5) )
+#define BIT_ANA_CHGR_CV_STATUS                            ( BIT(4) )
+#define BIT_ANA_CHGR_ON                                   ( BIT(3) )
+#define BIT_ANA_CHGR_INT                                  ( BIT(2) )
+#define BIT_ANA_VBAT_OVI                                  ( BIT(1) )
+#define BIT_ANA_VCHG_OVI                                  ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_ANA_MIXED_CTRL */
+#define BIT_ANA_PTEST_PD_RTCSET                           ( BIT(15) )
+#define BIT_ANA_THM_CHIP_PD_FLAG                          ( BIT(8) )
+#define BIT_ANA_THM_CHIP_PD_FLAG_CLR                      ( BIT(7) )
+#define BITS_ANA_THM_CAL_SEL(_X_)                         ( (_X_) << 5 & (BIT(5)|BIT(6)) )
+#define BIT_ANA_THM_AUTO_PD_EN                            ( BIT(4) )
+#define BIT_ANA_BG_LP_EN                                  ( BIT(3) )
+#define BITS_ANA_UVHO_T(_X_)                              ( (_X_) << 1 & (BIT(1)|BIT(2)) )
+#define BIT_ANA_UVHO_EN                                   ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_PWR_XTL_EN0 */
+#define BIT_ANA_LDO_XTL_EN                                ( BIT(15) )
+#define BIT_ANA_LDO_RF1_EXT_XTL2_EN                       ( BIT(11) )
+#define BIT_ANA_LDO_RF1_EXT_XTL1_EN                       ( BIT(10) )
+#define BIT_ANA_LDO_RF1_EXT_XTL0_EN                       ( BIT(9) )
+#define BIT_ANA_LDO_RF1_XTL2_EN                           ( BIT(8) )
+#define BIT_ANA_LDO_RF1_XTL1_EN                           ( BIT(7) )
+#define BIT_ANA_LDO_RF1_XTL0_EN                           ( BIT(6) )
+#define BIT_ANA_LDO_RF0_EXT_XTL2_EN                       ( BIT(5) )
+#define BIT_ANA_LDO_RF0_EXT_XTL1_EN                       ( BIT(4) )
+#define BIT_ANA_LDO_RF0_EXT_XTL0_EN                       ( BIT(3) )
+#define BIT_ANA_LDO_RF0_XTL2_EN                           ( BIT(2) )
+#define BIT_ANA_LDO_RF0_XTL1_EN                           ( BIT(1) )
+#define BIT_ANA_LDO_RF0_XTL0_EN                           ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_PWR_XTL_EN1 */
+#define BIT_ANA_LDO_VDD25_EXT_XTL2_EN                     ( BIT(11) )
+#define BIT_ANA_LDO_VDD25_EXT_XTL1_EN                     ( BIT(10) )
+#define BIT_ANA_LDO_VDD25_EXT_XTL0_EN                     ( BIT(9) )
+#define BIT_ANA_LDO_VDD25_XTL2_EN                         ( BIT(8) )
+#define BIT_ANA_LDO_VDD25_XTL1_EN                         ( BIT(7) )
+#define BIT_ANA_LDO_VDD25_XTL0_EN                         ( BIT(6) )
+#define BIT_ANA_LDO_RF2_EXT_XTL2_EN                       ( BIT(5) )
+#define BIT_ANA_LDO_RF2_EXT_XTL1_EN                       ( BIT(4) )
+#define BIT_ANA_LDO_RF2_EXT_XTL0_EN                       ( BIT(3) )
+#define BIT_ANA_LDO_RF2_XTL2_EN                           ( BIT(2) )
+#define BIT_ANA_LDO_RF2_XTL1_EN                           ( BIT(1) )
+#define BIT_ANA_LDO_RF2_XTL0_EN                           ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_PWR_XTL_EN2 */
+#define BIT_ANA_LDO_AVDD18_EXT_XTL2_EN                    ( BIT(11) )
+#define BIT_ANA_LDO_AVDD18_EXT_XTL1_EN                    ( BIT(10) )
+#define BIT_ANA_LDO_AVDD18_EXT_XTL0_EN                    ( BIT(9) )
+#define BIT_ANA_LDO_AVDD18_XTL2_EN                        ( BIT(8) )
+#define BIT_ANA_LDO_AVDD18_XTL1_EN                        ( BIT(7) )
+#define BIT_ANA_LDO_AVDD18_XTL0_EN                        ( BIT(6) )
+#define BIT_ANA_LDO_SIM2_EXT_XTL2_EN                      ( BIT(5) )
+#define BIT_ANA_LDO_SIM2_EXT_XTL1_EN                      ( BIT(4) )
+#define BIT_ANA_LDO_SIM2_EXT_XTL0_EN                      ( BIT(3) )
+#define BIT_ANA_LDO_SIM2_XTL2_EN                          ( BIT(2) )
+#define BIT_ANA_LDO_SIM2_XTL1_EN                          ( BIT(1) )
+#define BIT_ANA_LDO_SIM2_XTL0_EN                          ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_PWR_XTL_EN3 */
+#define BIT_ANA_DCDC_BG_EXT_XTL2_EN                       ( BIT(11) )
+#define BIT_ANA_DCDC_BG_EXT_XTL1_EN                       ( BIT(10) )
+#define BIT_ANA_DCDC_BG_EXT_XTL0_EN                       ( BIT(9) )
+#define BIT_ANA_DCDC_BG_XTL2_EN                           ( BIT(8) )
+#define BIT_ANA_DCDC_BG_XTL1_EN                           ( BIT(7) )
+#define BIT_ANA_DCDC_BG_XTL0_EN                           ( BIT(6) )
+#define BIT_ANA_BG_EXT_XTL2_EN                            ( BIT(5) )
+#define BIT_ANA_BG_EXT_XTL1_EN                            ( BIT(4) )
+#define BIT_ANA_BG_EXT_XTL0_EN                            ( BIT(3) )
+#define BIT_ANA_BG_XTL2_EN                                ( BIT(2) )
+#define BIT_ANA_BG_XTL1_EN                                ( BIT(1) )
+#define BIT_ANA_BG_XTL0_EN                                ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_PWR_XTL_EN4 */
+#define BIT_ANA_DCDC_WRF_XTL2_EN                          ( BIT(14) )
+#define BIT_ANA_DCDC_WRF_XTL1_EN                          ( BIT(13) )
+#define BIT_ANA_DCDC_WRF_XTL0_EN                          ( BIT(12) )
+#define BIT_ANA_DCDC_WPA_XTL2_EN                          ( BIT(11) )
+#define BIT_ANA_DCDC_WPA_XTL1_EN                          ( BIT(10) )
+#define BIT_ANA_DCDC_WPA_XTL0_EN                          ( BIT(9) )
+#define BIT_ANA_DCDC_MEM_XTL2_EN                          ( BIT(8) )
+#define BIT_ANA_DCDC_MEM_XTL1_EN                          ( BIT(7) )
+#define BIT_ANA_DCDC_MEM_XTL0_EN                          ( BIT(6) )
+#define BIT_ANA_DCDC_GEN_XTL2_EN                          ( BIT(5) )
+#define BIT_ANA_DCDC_GEN_XTL1_EN                          ( BIT(4) )
+#define BIT_ANA_DCDC_GEN_XTL0_EN                          ( BIT(3) )
+#define BIT_ANA_DCDC_CORE_XTL2_EN                         ( BIT(2) )
+#define BIT_ANA_DCDC_CORE_XTL1_EN                         ( BIT(1) )
+#define BIT_ANA_DCDC_CORE_XTL0_EN                         ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_PWR_XTL_EN5 */
+#define BIT_ANA_DCDC_WRF_EXT_XTL2_EN                      ( BIT(14) )
+#define BIT_ANA_DCDC_WRF_EXT_XTL1_EN                      ( BIT(13) )
+#define BIT_ANA_DCDC_WRF_EXT_XTL0_EN                      ( BIT(12) )
+#define BIT_ANA_DCDC_WPA_EXT_XTL2_EN                      ( BIT(11) )
+#define BIT_ANA_DCDC_WPA_EXT_XTL1_EN                      ( BIT(10) )
+#define BIT_ANA_DCDC_WPA_EXT_XTL0_EN                      ( BIT(9) )
+#define BIT_ANA_DCDC_MEM_EXT_XTL2_EN                      ( BIT(8) )
+#define BIT_ANA_DCDC_MEM_EXT_XTL1_EN                      ( BIT(7) )
+#define BIT_ANA_DCDC_MEM_EXT_XTL0_EN                      ( BIT(6) )
+#define BIT_ANA_DCDC_GEN_EXT_XTL2_EN                      ( BIT(5) )
+#define BIT_ANA_DCDC_GEN_EXT_XTL1_EN                      ( BIT(4) )
+#define BIT_ANA_DCDC_GEN_EXT_XTL0_EN                      ( BIT(3) )
+#define BIT_ANA_DCDC_CORE_EXT_XTL2_EN                     ( BIT(2) )
+#define BIT_ANA_DCDC_CORE_EXT_XTL1_EN                     ( BIT(1) )
+#define BIT_ANA_DCDC_CORE_EXT_XTL0_EN                     ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_ANA_STATUS */
+#define BIT_ANA_BONDOPT6                                  ( BIT(6) )
+#define BIT_ANA_BONDOPT5                                  ( BIT(5) )
+#define BIT_ANA_BONDOPT4                                  ( BIT(4) )
+#define BIT_ANA_BONDOPT3                                  ( BIT(3) )
+#define BIT_ANA_BONDOPT2                                  ( BIT(2) )
+#define BIT_ANA_BONDOPT1                                  ( BIT(1) )
+#define BIT_ANA_BONDOPT0                                  ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_POR_RST_MONITOR */
+#define BITS_ANA_POR_RST_MONITOR(_X_)                     ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ANA_APB_IF_WDG_RST_MONITOR */
+#define BITS_ANA_WDG_RST_MONITOR(_X_)                     ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ANA_APB_IF_POR_PIN_RST_MONITOR */
+#define BITS_ANA_POR_PIN_RST_MONITOR(_X_)                 ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ANA_APB_IF_POR_SRC_FLAG */
+#define BIT_ANA_POR_SW_FORCE_ON                           ( BIT(15) )
+#define BITS_ANA_POR_SRC_FLAG(_X_)                        ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+
+/* bits definitions for register REG_ANA_APB_IF_POR_7S_CTRL */
+#define BIT_ANA_PBINT_7S_FLAG_CLR                         ( BIT(15) )
+#define BIT_ANA_EXT_RSTN_FLAG_CLR                         ( BIT(14) )
+#define BIT_ANA_CHGR_INT_FLAG_CLR                         ( BIT(13) )
+#define BIT_ANA_PBINT2_FLAG_CLR                           ( BIT(12) )
+#define BIT_ANA_PBINT_FLAG_CLR                            ( BIT(11) )
+#define BIT_ANA_PBINT_7S_RST_SWMODE_RTCSTS                ( BIT(10) )
+#define BIT_ANA_PBINT_7S_RST_SWMODE_RTCCLR                ( BIT(9) )
+#define BIT_ANA_PBINT_7S_RST_SWMODE_RTCSET                ( BIT(8) )
+#define BITS_ANA_PBINT_7S_RST_THRESHOLD(_X_)              ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_ANA_PBINT_7S_RST_DISABLE                      ( BIT(3) )
+#define BIT_ANA_PBINT_7S_RST_MODE_RTCSTS                  ( BIT(2) )
+#define BIT_ANA_PBINT_7S_RST_MODE_RTCCLR                  ( BIT(1) )
+#define BIT_ANA_PBINT_7S_RST_MODE_RTCSET                  ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_INT_DEBUG */
+#define BIT_ANA_OTP_INT_DEB                               ( BIT(10) )
+#define BIT_ANA_THM_INT_DEB                               ( BIT(9) )
+#define BIT_ANA_AUD_PROT_INT_DEB                          ( BIT(8) )
+#define BIT_ANA_AUD_HEADBTN_INT_DEB                       ( BIT(7) )
+#define BIT_ANA_EIC_INT_DEB                               ( BIT(6) )
+#define BIT_ANA_FGU_INT_DEB                               ( BIT(5) )
+#define BIT_ANA_WDG_INT_DEB                               ( BIT(4) )
+#define BIT_ANA_RTC_INT_DEB                               ( BIT(3) )
+#define BIT_ANA_GPIO_INT_DEB                              ( BIT(2) )
+#define BIT_ANA_ADC_INT_DEB                               ( BIT(1) )
+#define BIT_ANA_INT_DEBUG_EN                              ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_GPI_DEBUG */
+#define BIT_ANA_HEAD_INSERT2_DEB                          ( BIT(9) )
+#define BIT_ANA_HEAD_INSERT_DEB                           ( BIT(8) )
+#define BIT_ANA_HEAD_BUTTON_DEB                           ( BIT(7) )
+#define BIT_ANA_PBINT2_DEB                                ( BIT(6) )
+#define BIT_ANA_PBINT_DEB                                 ( BIT(5) )
+#define BIT_ANA_VCHG_OVI_DEB                              ( BIT(4) )
+#define BIT_ANA_VBAT_OVI_DEB                              ( BIT(3) )
+#define BIT_ANA_CHGR_INT_DEB                              ( BIT(2) )
+#define BIT_ANA_GPI_DEBUG_EN                              ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_HWRST_RTC */
+#define BITS_ANA_HWRST_RTC_REG_STS(_X_)                   ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_ANA_HWRST_RTC_REG_SET(_X_)                   ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_ANA_APB_IF_CHIP_ID_LOW */
+#define BITS_ANA_CHIP_ID_LOW(_X_)                         ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ANA_APB_IF_CHIP_ID_HIGH */
+#define BITS_ANA_CHIP_ID_HIGH(_X_)                        ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ANA_APB_IF_ARM_MF_REG */
+#define BITS_ANA_ARM_MF_REG(_X_)                          ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ANA_APB_IF_AFUSE_CTRL */
+#define BIT_ANA_AFUSE_READ_REQ                            ( BIT(7) )
+#define BITS_ANA_AFUSE_READ_DLY(_X_)                      ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) )
+
+/* bits definitions for register REG_ANA_APB_IF_AFUSE_OUT0 */
+#define BITS_ANA_AFUSE_OUT0(_X_)                          ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ANA_APB_IF_AFUSE_OUT1 */
+#define BITS_ANA_AFUSE_OUT1(_X_)                          ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ANA_APB_IF_AFUSE_OUT2 */
+#define BITS_ANA_AFUSE_OUT2(_X_)                          ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ANA_APB_IF_AFUSE_OUT3 */
+#define BITS_ANA_AFUSE_OUT3(_X_)                          ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ANA_APB_IF_CA_CTRL4 */
+#define BIT_ANA_EXT_RSTN_PD_EN                            ( BIT(14) )
+#define BIT_ANA_PB_7S_RST_PD_EN                           ( BIT(13) )
+#define BIT_ANA_WDG_RST_PD_EN                             ( BIT(12) )
+#define BIT_ANA_SW_RST_EMMCIO_PD_EN                       ( BIT(11) )
+#define BIT_ANA_SW_RST_EMMCCORE_PD_EN                     ( BIT(10) )
+#define BITS_ANA_SW_RST_PD_THRESHOLD(_X_)                 ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+
+/* bits definitions for register REG_ANA_APB_IF_MCU_WR_PROT_VALUE */
+#define BIT_ANA_MCU_WR_PROT                               ( BIT(15) )
+#define BITS_ANA_MCU_WR_PROT_VALUE(_X_)                   ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+
+/* bits definitions for register REG_ANA_APB_IF_MP_PWR_CTRL0 */
+#define BIT_ANA_LDO_SIM1_EXT_XTL2_EN                      ( BIT(15) )
+#define BIT_ANA_LDO_SIM1_EXT_XTL1_EN                      ( BIT(14) )
+#define BIT_ANA_LDO_SIM1_EXT_XTL0_EN                      ( BIT(13) )
+#define BIT_ANA_LDO_SIM1_XTL2_EN                          ( BIT(12) )
+#define BIT_ANA_LDO_SIM1_XTL1_EN                          ( BIT(11) )
+#define BIT_ANA_LDO_SIM1_XTL0_EN                          ( BIT(10) )
+#define BIT_ANA_LDO_SIM0_EXT_XTL2_EN                      ( BIT(9) )
+#define BIT_ANA_LDO_SIM0_EXT_XTL1_EN                      ( BIT(8) )
+#define BIT_ANA_LDO_SIM0_EXT_XTL0_EN                      ( BIT(7) )
+#define BIT_ANA_LDO_SIM0_XTL2_EN                          ( BIT(6) )
+#define BIT_ANA_LDO_SIM0_XTL1_EN                          ( BIT(5) )
+#define BIT_ANA_LDO_SIM0_XTL0_EN                          ( BIT(4) )
+#define BIT_ANA_PWR_OFF_SEQ_EN                            ( BIT(3) )
+#define BIT_ANA_DCDC_CORE_SLP_OUT_STEP_EN                 ( BIT(1) )
+#define BIT_ANA_DCDC_CORE_SLP_IN_STEP_EN                  ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_MP_PWR_CTRL1 */
+#define BITS_ANA_DCDC_CORE_CTL_SLP_STEP5(_X_)             ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_ANA_DCDC_CORE_CTL_SLP_STEP4(_X_)             ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_ANA_DCDC_CORE_CTL_SLP_STEP3(_X_)             ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) )
+#define BITS_ANA_DCDC_CORE_CTL_SLP_STEP2(_X_)             ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) )
+#define BITS_ANA_DCDC_CORE_CTL_SLP_STEP1(_X_)             ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
+
+/* bits definitions for register REG_ANA_APB_IF_MP_PWR_CTRL2 */
+#define BITS_ANA_DCDC_CORE_CAL_SLP_STEP3(_X_)             ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_ANA_DCDC_CORE_CAL_SLP_STEP2(_X_)             ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_ANA_DCDC_CORE_CAL_SLP_STEP1(_X_)             ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_MP_PWR_CTRL3 */
+#define BITS_ANA_DCDC_ARM_STBOP(_X_)                      ( (_X_) << 12 & (BIT(12)|BIT(13)) )
+#define BITS_ANA_DCDC_CORE_STBOP(_X_)                     ( (_X_) << 10 & (BIT(10)|BIT(11)) )
+#define BITS_ANA_DCDC_CORE_CAL_SLP_STEP5(_X_)             ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_ANA_DCDC_CORE_CAL_SLP_STEP4(_X_)             ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_MP_LDO_CTRL */
+#define BITS_ANA_LDOD_LP_CAL(_X_)                         ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_ANA_LDOA_LP_CAL(_X_)                         ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_ANA_LDODCDC_LP_CAL(_X_)                      ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_MP_CHG_CTRL */
+#define BIT_ANA_CHGR_INT_EN                               ( BIT(8) )
+#define BIT_ANA_CHGR_DRV                                  ( BIT(5) )
+#define BIT_ANA_CHGR_OSC                                  ( BIT(4) )
+#define BITS_ANA_CHGR_DPM(_X_)                            ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_ANA_CHGR_ITERM(_X_)                          ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_ANA_APB_IF_MP_MISC_CTRL */
+#define BITS_ANA_LDO_RF1_V_BOND(_X_)                      ( (_X_) << 11 & (BIT(11)|BIT(12)) )
+#define BITS_ANA_LDO_VDD25_V_BOND(_X_)                    ( (_X_) << 9 & (BIT(9)|BIT(10)) )
+#define BITS_ANA_DCDC_ARM_CTL_BOND(_X_)                   ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) )
+#define BITS_ANA_DCDC_CORE_CTL_BOND(_X_)                  ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) )
+#define BIT_ANA_DCOFFSET_EN                               ( BIT(2) )
+#define BIT_ANA_CHOP_EN                                   ( BIT(1) )
+#define BIT_ANA_WHTLED_EXT_RES_CTRL                       ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_MP_DCDC_DEDT_CTRL */
+#define BITS_ANA_DCDC_WPA_DEDT_EN(_X_)                    ( (_X_) << 10 & (BIT(10)|BIT(11)) )
+#define BITS_ANA_DCDC_WRF_DEDT_EN(_X_)                    ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ANA_DCDC_GEN_DEDT_EN(_X_)                    ( (_X_) << 6 & (BIT(6)|BIT(7)) )
+#define BITS_ANA_DCDC_MEM_DEDT_EN(_X_)                    ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_ANA_DCDC_ARM_DEDT_EN(_X_)                    ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_ANA_DCDC_CORE_DEDT_EN(_X_)                   ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_ANA_APB_IF_CA_CTRL0 */
+#define BITS_ANA_SD_CLK_P(_X_)                            ( (_X_) << 14 & (BIT(14)|BIT(15)) )
+#define BIT_ANA_SD_CHOP_CAP_EN                            ( BIT(13) )
+#define BIT_ANA_LDO_CAMIO_V_B2                            ( BIT(12) )
+#define BIT_ANA_LDO_CAMIO_EXT_XTL2_EN                     ( BIT(11) )
+#define BIT_ANA_LDO_CAMIO_EXT_XTL1_EN                     ( BIT(10) )
+#define BIT_ANA_LDO_CAMIO_EXT_XTL0_EN                     ( BIT(9) )
+#define BIT_ANA_LDO_CAMIO_XTL2_EN                         ( BIT(8) )
+#define BIT_ANA_LDO_CAMIO_XTL1_EN                         ( BIT(7) )
+#define BIT_ANA_LDO_CAMIO_XTL0_EN                         ( BIT(6) )
+#define BIT_ANA_LDO_CAMD_EXT_XTL2_EN                      ( BIT(5) )
+#define BIT_ANA_LDO_CAMD_EXT_XTL1_EN                      ( BIT(4) )
+#define BIT_ANA_LDO_CAMD_EXT_XTL0_EN                      ( BIT(3) )
+#define BIT_ANA_LDO_CAMD_XTL2_EN                          ( BIT(2) )
+#define BIT_ANA_LDO_CAMD_XTL1_EN                          ( BIT(1) )
+#define BIT_ANA_LDO_CAMD_XTL0_EN                          ( BIT(0) )
+
+/* bits definitions for register REG_ANA_APB_IF_CA_CTRL1 */
+#define BITS_ANA_SMPL_MODE(_X_)                           ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_ANA_APB_IF_CA_CTRL2 */
+#define BIT_ANA_SMPL_PWR_ON_FLAG                          ( BIT(15) )
+#define BIT_ANA_SMPL_MODE_WR_ACK_FLAG                     ( BIT(14) )
+#define BIT_ANA_SMPL_PWR_ON_FLAG_CLR                      ( BIT(13) )
+#define BIT_ANA_SMPL_MODE_WR_ACK_FLAG_CLR                 ( BIT(12) )
+#define BIT_ANA_SMPL_PWR_ON_SET                           ( BIT(11) )
+#define BIT_ANA_SLP_LDOKPLED_PD_EN                        ( BIT(9) )
+#define BIT_ANA_LDO_KPLED_PD                              ( BIT(8) )
+#define BITS_ANA_LDO_KPLED_V(_X_)                         ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_ANA_APB_IF_CA_CTRL3 */
+#define BITS_ANA_VBAT_CRASH_V(_X_)                        ( (_X_) << 14 & (BIT(14)|BIT(15)) )
+#define BIT_ANA_PBINT_7S_AUTO_ON_EN_CLR                   ( BIT(13) )
+#define BIT_ANA_PBINT_7S_AUTO_ON_EN_SET                   ( BIT(12) )
+#define BIT_ANA_VIBR_LDO_EN                               ( BIT(10) )
+#define BIT_ANA_SLP_LDOVIBR_PD_EN                         ( BIT(9) )
+#define BIT_ANA_LDO_VIBR_PD                               ( BIT(8) )
+#define BITS_ANA_LDO_VIBR_V(_X_)                          ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_CORE_ADI */
+#define BITS_ANA_DCDC_CORE_CTL_SW_ADI(_X_)                ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_ANA_DCDC_CORE_CAL_SW_ADI(_X_)                ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_ARM_ADI */
+#define BITS_ANA_DCDC_ARM_CTL_ADI(_X_)                    ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_ANA_DCDC_ARM_CAL_ADI(_X_)                    ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_MEM_ADI */
+#define BIT_ANA_DCDC_MEM_CTL_ADI                          ( BIT(5) )
+#define BITS_ANA_DCDC_MEM_CAL_ADI(_X_)                    ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_GEN_ADI */
+#define BITS_ANA_DCDC_GEN_CTL_ADI(_X_)                    ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_ANA_DCDC_GEN_CAL_ADI(_X_)                    ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_WRF_ADI */
+#define BITS_ANA_DCDC_WRF_CTL_ADI(_X_)                    ( (_X_) << 5 & (BIT(5)|BIT(6)) )
+#define BITS_ANA_DCDC_WRF_CAL_ADI(_X_)                    ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_WPA_ADI */
+#define BITS_ANA_DCDC_WPA_CAL_ADI(_X_)                    ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
+
+/* bits definitions for register REG_ANA_APB_IF_DCDC_WPA_DCM_ADI */
+#define BIT_ANA_DCDC_WPA_DCM_ADI                          ( BIT(0) )
+
+#endif
diff --git a/include/soc/sprd/chip_x20/__regs_ana_sc2713s_glb.h b/include/soc/sprd/chip_x20/__regs_ana_sc2713s_glb.h
new file mode 100644
index 00000000..844a48da
--- /dev/null
+++ b/include/soc/sprd/chip_x20/__regs_ana_sc2713s_glb.h
@@ -0,0 +1,931 @@
+/*
+ * Copyright (C) 2014 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+#ifndef __REGS_ANA_SC2713S_GLB_H__
+#define __REGS_ANA_SC2713S_GLB_H__
+
+#ifndef __SCI_GLB_REGS_H__
+#error  "Don't include this file directly, include <mach/sci_glb_regs.h>"
+#endif
+
+#define ANA_REGS_GLB
+
+/* registers definitions for controller ANA_REGS_GLB */
+#define ANA_REG_GLB_ARM_MODULE_EN       SCI_ADDR(ANA_REGS_GLB_BASE, 0x0000)
+#define ANA_REG_GLB_ARM_CLK_EN          SCI_ADDR(ANA_REGS_GLB_BASE, 0x0004)
+#define ANA_REG_GLB_RTC_CLK_EN          SCI_ADDR(ANA_REGS_GLB_BASE, 0x0008)
+#define ANA_REG_GLB_ARM_RST             SCI_ADDR(ANA_REGS_GLB_BASE, 0x000C)
+#define ANA_REG_GLB_LDO_DCDC_PD_RTCSET  SCI_ADDR(ANA_REGS_GLB_BASE, 0x0010)
+#define ANA_REG_GLB_LDO_DCDC_PD_RTCCLR  SCI_ADDR(ANA_REGS_GLB_BASE, 0x0014)
+#define ANA_REG_GLB_RTC_CTRL            SCI_ADDR(ANA_REGS_GLB_BASE, 0x0018)
+#define ANA_REG_GLB_LDO_PD_CTRL         SCI_ADDR(ANA_REGS_GLB_BASE, 0x001C)
+#define ANA_REG_GLB_LDO_V_CTRL0         SCI_ADDR(ANA_REGS_GLB_BASE, 0x0020)
+#define ANA_REG_GLB_LDO_V_CTRL1         SCI_ADDR(ANA_REGS_GLB_BASE, 0x0024)
+#define ANA_REG_GLB_LDO_V_CTRL2         SCI_ADDR(ANA_REGS_GLB_BASE, 0x0028)
+#define ANA_REG_GLB_LDO_CAL_CTRL0       SCI_ADDR(ANA_REGS_GLB_BASE, 0x002C)
+#define ANA_REG_GLB_LDO_CAL_CTRL1       SCI_ADDR(ANA_REGS_GLB_BASE, 0x0030)
+#define ANA_REG_GLB_LDO_CAL_CTRL2       SCI_ADDR(ANA_REGS_GLB_BASE, 0x0034)
+#define ANA_REG_GLB_LDO_CAL_CTRL3       SCI_ADDR(ANA_REGS_GLB_BASE, 0x0038)
+#define ANA_REG_GLB_LDO_CAL_CTRL4       SCI_ADDR(ANA_REGS_GLB_BASE, 0x003C)
+#define ANA_REG_GLB_LDO_CAL_CTRL5       SCI_ADDR(ANA_REGS_GLB_BASE, 0x0040)
+#define ANA_REG_GLB_LDO_CAL_CTRL6       SCI_ADDR(ANA_REGS_GLB_BASE, 0x0044)
+#define ANA_REG_GLB_AUXAD_CTL           SCI_ADDR(ANA_REGS_GLB_BASE, 0x0048)
+#define ANA_REG_GLB_DCDC_CTRL0          SCI_ADDR(ANA_REGS_GLB_BASE, 0x004C)
+#define ANA_REG_GLB_DCDC_CTRL1          SCI_ADDR(ANA_REGS_GLB_BASE, 0x0050)
+#define ANA_REG_GLB_DCDC_CTRL2          SCI_ADDR(ANA_REGS_GLB_BASE, 0x0054)
+#define ANA_REG_GLB_DCDC_CTRL3          SCI_ADDR(ANA_REGS_GLB_BASE, 0x0058)
+#define ANA_REG_GLB_DCDC_CTRL4          SCI_ADDR(ANA_REGS_GLB_BASE, 0x005C)
+#define ANA_REG_GLB_DCDC_CTRL5          SCI_ADDR(ANA_REGS_GLB_BASE, 0x0060)
+#define ANA_REG_GLB_DCDC_CTRL6          SCI_ADDR(ANA_REGS_GLB_BASE, 0x0064)
+#define ANA_REG_GLB_DDR2_CTRL           SCI_ADDR(ANA_REGS_GLB_BASE, 0x0068)
+#define ANA_REG_GLB_SLP_WAIT_DCDCARM    SCI_ADDR(ANA_REGS_GLB_BASE, 0x006C)
+#define ANA_REG_GLB_LDO1828_XTL_CTL     SCI_ADDR(ANA_REGS_GLB_BASE, 0x0070)
+#define ANA_REG_GLB_LDO_SLP_CTRL0       SCI_ADDR(ANA_REGS_GLB_BASE, 0x0074)
+#define ANA_REG_GLB_LDO_SLP_CTRL1       SCI_ADDR(ANA_REGS_GLB_BASE, 0x0078)
+#define ANA_REG_GLB_LDO_SLP_CTRL2       SCI_ADDR(ANA_REGS_GLB_BASE, 0x007C)
+#define ANA_REG_GLB_LDO_SLP_CTRL3       SCI_ADDR(ANA_REGS_GLB_BASE, 0x0080)
+#define ANA_REG_GLB_AUD_SLP_CTRL4       SCI_ADDR(ANA_REGS_GLB_BASE, 0x0084)
+#define ANA_REG_GLB_DCDC_SLP_CTRL       SCI_ADDR(ANA_REGS_GLB_BASE, 0x0088)
+#define ANA_REG_GLB_XTL_WAIT_CTRL       SCI_ADDR(ANA_REGS_GLB_BASE, 0x008C)
+#define ANA_REG_GLB_FLASH_CTRL          SCI_ADDR(ANA_REGS_GLB_BASE, 0x0090)
+#define ANA_REG_GLB_WHTLED_CTRL0        SCI_ADDR(ANA_REGS_GLB_BASE, 0x0094)
+#define ANA_REG_GLB_WHTLED_CTRL1        SCI_ADDR(ANA_REGS_GLB_BASE, 0x0098)
+#define ANA_REG_GLB_WHTLED_CTRL2        SCI_ADDR(ANA_REGS_GLB_BASE, 0x009C)
+#define ANA_REG_GLB_ANA_DRV_CTRL        SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A0)
+#define ANA_REG_GLB_VIBR_CTRL0          SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A4)
+#define ANA_REG_GLB_VIBR_CTRL1          SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A8)
+#define ANA_REG_GLB_VIBR_CTRL2          SCI_ADDR(ANA_REGS_GLB_BASE, 0x00AC)
+#define ANA_REG_GLB_VIBR_WR_PROT_VALUE  SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B0)
+#define ANA_REG_GLB_AUDIO_CTRL          SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B4)
+#define ANA_REG_GLB_CHGR_CTRL0          SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B8)
+#define ANA_REG_GLB_CHGR_CTRL1          SCI_ADDR(ANA_REGS_GLB_BASE, 0x00BC)
+#define ANA_REG_GLB_CHGR_CTRL2          SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C0)
+#define ANA_REG_GLB_CHGR_STATUS         SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C4)
+#define ANA_REG_GLB_ANA_MIXED_CTRL      SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C8)
+#define ANA_REG_GLB_PWR_XTL_EN0         SCI_ADDR(ANA_REGS_GLB_BASE, 0x00CC)
+#define ANA_REG_GLB_PWR_XTL_EN1         SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D0)
+#define ANA_REG_GLB_PWR_XTL_EN2         SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D4)
+#define ANA_REG_GLB_PWR_XTL_EN3         SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D8)
+#define ANA_REG_GLB_PWR_XTL_EN4         SCI_ADDR(ANA_REGS_GLB_BASE, 0x00DC)
+#define ANA_REG_GLB_PWR_XTL_EN5         SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E0)
+#define ANA_REG_GLB_ANA_STATUS          SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E4)
+#define ANA_REG_GLB_POR_RST_MONITOR     SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E8)
+#define ANA_REG_GLB_WDG_RST_MONITOR     SCI_ADDR(ANA_REGS_GLB_BASE, 0x00EC)
+#define ANA_REG_GLB_POR_PIN_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F0)
+#define ANA_REG_GLB_POR_SRC_FLAG        SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F4)
+#define ANA_REG_GLB_POR_7S_CTRL         SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F8)
+#define ANA_REG_GLB_INT_DEBUG           SCI_ADDR(ANA_REGS_GLB_BASE, 0x00FC)
+#define ANA_REG_GLB_GPI_DEBUG           SCI_ADDR(ANA_REGS_GLB_BASE, 0x0100)
+#define ANA_REG_GLB_HWRST_RTC           SCI_ADDR(ANA_REGS_GLB_BASE, 0x0104)
+#define ANA_REG_GLB_CHIP_ID_LOW         SCI_ADDR(ANA_REGS_GLB_BASE, 0x0108)
+#define ANA_REG_GLB_CHIP_ID_HIGH        SCI_ADDR(ANA_REGS_GLB_BASE, 0x010C)
+#define ANA_REG_GLB_ARM_MF_REG          SCI_ADDR(ANA_REGS_GLB_BASE, 0x0110)
+#define ANA_REG_GLB_AFUSE_CTRL          SCI_ADDR(ANA_REGS_GLB_BASE, 0x0114)
+#define ANA_REG_GLB_AFUSE_OUT0          SCI_ADDR(ANA_REGS_GLB_BASE, 0x0118)
+#define ANA_REG_GLB_AFUSE_OUT1          SCI_ADDR(ANA_REGS_GLB_BASE, 0x011C)
+#define ANA_REG_GLB_AFUSE_OUT2          SCI_ADDR(ANA_REGS_GLB_BASE, 0x0120)
+#define ANA_REG_GLB_AFUSE_OUT3          SCI_ADDR(ANA_REGS_GLB_BASE, 0x0124)
+#define ANA_REG_GLB_CA_CTRL4            SCI_ADDR(ANA_REGS_GLB_BASE, 0x0128)
+#define ANA_REG_GLB_MCU_WR_PROT_VALUE   SCI_ADDR(ANA_REGS_GLB_BASE, 0x012C)
+#define ANA_REG_GLB_MP_PWR_CTRL0        SCI_ADDR(ANA_REGS_GLB_BASE, 0x0130)
+#define ANA_REG_GLB_MP_PWR_CTRL1        SCI_ADDR(ANA_REGS_GLB_BASE, 0x0134)
+#define ANA_REG_GLB_MP_PWR_CTRL2        SCI_ADDR(ANA_REGS_GLB_BASE, 0x0138)
+#define ANA_REG_GLB_MP_PWR_CTRL3        SCI_ADDR(ANA_REGS_GLB_BASE, 0x013C)
+#define ANA_REG_GLB_MP_LDO_CTRL         SCI_ADDR(ANA_REGS_GLB_BASE, 0x0140)
+#define ANA_REG_GLB_MP_CHG_CTRL         SCI_ADDR(ANA_REGS_GLB_BASE, 0x0144)
+#define ANA_REG_GLB_MP_MISC_CTRL        SCI_ADDR(ANA_REGS_GLB_BASE, 0x0148)
+#define ANA_REG_GLB_MP_DCDC_DEDT_CTRL   SCI_ADDR(ANA_REGS_GLB_BASE, 0x014C)
+#define ANA_REG_GLB_CA_CTRL0            SCI_ADDR(ANA_REGS_GLB_BASE, 0x0150)
+#define ANA_REG_GLB_CA_CTRL1            SCI_ADDR(ANA_REGS_GLB_BASE, 0x0154)
+#define ANA_REG_GLB_CA_CTRL2            SCI_ADDR(ANA_REGS_GLB_BASE, 0x0158)
+#define ANA_REG_GLB_CA_CTRL3            SCI_ADDR(ANA_REGS_GLB_BASE, 0x015C)
+#define ANA_REG_GLB_DCDC_CORE_ADI       SCI_ADDR(ANA_REGS_GLB_BASE, 0x0160)
+#define ANA_REG_GLB_DCDC_ARM_ADI        SCI_ADDR(ANA_REGS_GLB_BASE, 0x0164)
+#define ANA_REG_GLB_DCDC_MEM_ADI        SCI_ADDR(ANA_REGS_GLB_BASE, 0x0168)
+#define ANA_REG_GLB_DCDC_GEN_ADI        SCI_ADDR(ANA_REGS_GLB_BASE, 0x016C)
+#define ANA_REG_GLB_DCDC_WRF_ADI        SCI_ADDR(ANA_REGS_GLB_BASE, 0x0170)
+#define ANA_REG_GLB_DCDC_WPA_ADI        SCI_ADDR(ANA_REGS_GLB_BASE, 0x0174)
+#define ANA_REG_GLB_DCDC_WPA_DCM_ADI    SCI_ADDR(ANA_REGS_GLB_BASE, 0x017C)
+
+#define ANA_REG_GLB_LDO_CAL_SEL         SCI_ADDR(ANA_REGS_GLB_BASE, 0x0044)
+
+/* bits definitions for register ANA_REG_GLB_ARM_MODULE_EN */
+#define BIT_ANA_THM_EN                  ( BIT(12) )
+#define BIT_ANA_BLTC_EN                 ( BIT(10) )
+#define BIT_ANA_PINREG_EN               ( BIT(9) )
+#define BIT_ANA_FGU_EN                  ( BIT(8) )
+#define BIT_ANA_GPIO_EN                 ( BIT(7) )
+#define BIT_ANA_ADC_EN                  ( BIT(6) )
+#define BIT_ANA_HDT_EN                  ( BIT(5) )
+#define BIT_ANA_AUD_EN                  ( BIT(4) )
+#define BIT_ANA_EIC_EN                  ( BIT(3) )
+#define BIT_ANA_WDG_EN                  ( BIT(2) )
+#define BIT_ANA_RTC_EN                  ( BIT(1) )
+
+/* bits definitions for register ANA_REG_GLB_ARM_CLK_EN */
+#define BIT_CLK_AUXAD_EN                ( BIT(9) )
+#define BIT_CLK_AUXADC_EN               ( BIT(8) )
+#define BIT_CLK_AUD_HID_EN              ( BIT(5) )
+#define BIT_CLK_AUD_HBD_EN              ( BIT(4) )
+#define BIT_CLK_AUD_LOOP_EN             ( BIT(3) )
+#define BIT_CLK_AUD_6P5M_EN             ( BIT(2) )
+#define BIT_CLK_AUDIF_EN                ( BIT(1) )
+
+/* bits definitions for register ANA_REG_GLB_RTC_CLK_EN */
+#define BIT_RTC_FLASH_EN                ( BIT(13) )
+#define BIT_RTC_THMA_AUTO_EN            ( BIT(12) )
+#define BIT_RTC_THMA_EN                 ( BIT(11) )
+#define BIT_RTC_THM_EN                  ( BIT(10) )
+#define BIT_RTC_BLTC_EN                 ( BIT(8) )
+#define BIT_RTC_FGU_EN                  ( BIT(7) )
+#define BIT_RTC_FGUA_EN                 ( BIT(6) )
+#define BIT_RTC_VIBR_EN                 ( BIT(5) )
+#define BIT_RTC_AUD_EN                  ( BIT(4) )
+#define BIT_RTC_EIC_EN                  ( BIT(3) )
+#define BIT_RTC_WDG_EN                  ( BIT(2) )
+#define BIT_RTC_RTC_EN                  ( BIT(1) )
+#define BIT_RTC_ARCH_EN                 ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_ARM_RST */
+#define BIT_ANA_THMA_SOFT_RST           ( BIT(14) )
+#define BIT_ANA_THM_SOFT_RST            ( BIT(13) )
+#define BIT_ANA_AUD_32K_SOFT_RST        ( BIT(12) )
+#define BIT_ANA_AUDTX_SOFT_RST          ( BIT(11) )
+#define BIT_ANA_AUDRX_SOFT_RST          ( BIT(10) )
+#define BIT_ANA_AUD_SOFT_RST            ( BIT(9) )
+#define BIT_ANA_AUD_HDT_SOFT_RST        ( BIT(8) )
+#define BIT_ANA_GPIO_SOFT_RST           ( BIT(7) )
+#define BIT_ANA_ADC_SOFT_RST            ( BIT(6) )
+#define BIT_ANA_PWM0_SOFT_RST           ( BIT(5) )
+#define BIT_ANA_FGU_SOFT_RST            ( BIT(4) )
+#define BIT_ANA_EIC_SOFT_RST            ( BIT(3) )
+#define BIT_ANA_WDG_SOFT_RST            ( BIT(2) )
+#define BIT_ANA_RTC_SOFT_RST            ( BIT(1) )
+#define BIT_ANA_BLTC_SOFT_RST           ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_LDO_DCDC_PD_RTCSET */
+#define BIT_LDO_AVDD18_PD_RTCSET        ( BIT(15) )
+#define BIT_DCDC_OTP_PD_RTCSET          ( BIT(14) )
+#define BIT_DCDC_WRF_PD_RTCSET          ( BIT(13) )
+#define BIT_DCDC_GEN_PD_RTCSET          ( BIT(12) )
+#define BIT_DCDC_MEM_PD_RTCSET          ( BIT(11) )
+#define BIT_DCDC_ARM_PD_RTCSET          ( BIT(10) )
+#define BIT_DCDC_CORE_PD_RTCSET         ( BIT(9) )
+#define BIT_LDO_EMMCCORE_PD_RTCSET      ( BIT(8) )
+#define BIT_LDO_EMMCIO_PD_RTCSET        ( BIT(7) )
+#define BIT_LDO_RF2_PD_RTCSET           ( BIT(6) )
+#define BIT_LDO_RF1_PD_RTCSET           ( BIT(5) )
+#define BIT_LDO_RF0_PD_RTCSET           ( BIT(4) )
+#define BIT_LDO_VDD25_PD_RTCSET         ( BIT(3) )
+#define BIT_LDO_VDD28_PD_RTCSET         ( BIT(2) )
+#define BIT_LDO_VDD18_PD_RTCSET         ( BIT(1) )
+#define BIT_BG_PD_RTCSET                ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_LDO_DCDC_PD_RTCCLR */
+#define BIT_LDO_AVDD18_PD_RTCCLR        ( BIT(15) )
+#define BIT_DCDC_OTP_PD_RTCCLR          ( BIT(14) )
+#define BIT_DCDC_WRF_PD_RTCCLR          ( BIT(13) )
+#define BIT_DCDC_GEN_PD_RTCCLR          ( BIT(12) )
+#define BIT_DCDC_MEM_PD_RTCCLR          ( BIT(11) )
+#define BIT_DCDC_ARM_PD_RTCCLR          ( BIT(10) )
+#define BIT_DCDC_CORE_PD_RTCCLR         ( BIT(9) )
+#define BIT_LDO_EMMCCORE_PD_RTCCLR      ( BIT(8) )
+#define BIT_LDO_EMMCIO_PD_RTCCLR        ( BIT(7) )
+#define BIT_LDO_RF2_PD_RTCCLR           ( BIT(6) )
+#define BIT_LDO_RF1_PD_RTCCLR           ( BIT(5) )
+#define BIT_LDO_RF0_PD_RTCCLR           ( BIT(4) )
+#define BIT_LDO_VDD25_PD_RTCCLR         ( BIT(3) )
+#define BIT_LDO_VDD28_PD_RTCCLR         ( BIT(2) )
+#define BIT_LDO_VDD18_PD_RTCCLR         ( BIT(1) )
+#define BIT_BG_PD_RTCCLR                ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_RTC_CTRL */
+#define BITS_XOSC32K_CTL_STS(_x_)       ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BIT_XOSC32K_CTL_B3_RTCCLR       ( BIT(7) )
+#define BIT_XOSC32K_CTL_B2_RTCCLR       ( BIT(6) )
+#define BIT_XOSC32K_CTL_B1_RTCCLR       ( BIT(5) )
+#define BIT_XOSC32K_CTL_B0_RTCCLR       ( BIT(4) )
+#define BIT_XOSC32K_CTL_B3_RTCSET       ( BIT(3) )
+#define BIT_XOSC32K_CTL_B2_RTCSET       ( BIT(2) )
+#define BIT_XOSC32K_CTL_B1_RTCSET       ( BIT(1) )
+#define BIT_XOSC32K_CTL_B0_RTCSET       ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_LDO_PD_CTRL */
+#define BIT_LDO_LPREF_PD_SW             ( BIT(12) )
+#define BIT_DCDC_WPA_PD                 ( BIT(11) )
+#define BIT_LDO_CLSG_PD                 ( BIT(10) )
+#define BIT_LDO_USB_PD                  ( BIT(9) )
+#define BIT_LDO_CAMMOT_PD               ( BIT(8) )
+#define BIT_LDO_CAMIO_PD                ( BIT(7) )
+#define BIT_LDO_CAMD_PD                 ( BIT(6) )
+#define BIT_LDO_CAMA_PD                 ( BIT(5) )
+#define BIT_LDO_SIM2_PD                 ( BIT(4) )
+#define BIT_LDO_SIM1_PD                 ( BIT(3) )
+#define BIT_LDO_SIM0_PD                 ( BIT(2) )
+#define BIT_LDO_SD_PD                   ( BIT(1) )
+
+/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL0 */
+#define BITS_LDO_EMMCCORE_V(_x_)        ( (_x_) << 14 & (BIT(14)|BIT(15)) )
+#define BITS_LDO_EMMCIO_V(_x_)          ( (_x_) << 12 & (BIT(12)|BIT(13)) )
+#define BITS_LDO_RF2_V(_x_)             ( (_x_) << 10 & (BIT(10)|BIT(11)) )
+#define BITS_LDO_RF1_V(_x_)             ( (_x_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_LDO_RF0_V(_x_)             ( (_x_) << 6 & (BIT(6)|BIT(7)) )
+#define BITS_LDO_VDD25_V(_x_)           ( (_x_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_LDO_VDD28_V(_x_)           ( (_x_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_LDO_VDD18_V(_x_)           ( (_x_) << 0 & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL1 */
+#define BITS_LDO_SIM2_V(_x_)            ( (_x_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_LDO_SIM1_V(_x_)            ( (_x_) << 6 & (BIT(6)|BIT(7)) )
+#define BITS_LDO_SIM0_V(_x_)            ( (_x_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_LDO_SD_V(_x_)              ( (_x_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_LDO_AVDD18_V(_x_)          ( (_x_) << 0 & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL2 */
+#define BITS_VBATBK_RES(_x_)            ( (_x_) << 14 & (BIT(14)|BIT(15)) )
+#define BITS_VBATBK_V(_x_)              ( (_x_) << 12 & (BIT(12)|BIT(13)) )
+#define BITS_LDO_CLSG_V(_x_)            ( (_x_) << 10 & (BIT(10)|BIT(11)) )
+#define BITS_LDO_USB_V(_x_)             ( (_x_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_LDO_CAMMOT_V(_x_)          ( (_x_) << 6 & (BIT(6)|BIT(7)) )
+#define BITS_LDO_CAMIO_V(_x_)           ( (_x_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_LDO_CAMD_V(_x_)            ( (_x_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_LDO_CAMA_V(_x_)            ( (_x_) << 0 & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL0 */
+#define BITS_LDO_VDD25_CAL(_x_)         ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_LDO_VDD28_CAL(_x_)         ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_LDO_VDD18_CAL(_x_)         ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL1 */
+#define BITS_LDO_RF2_CAL(_x_)           ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_LDO_RF1_CAL(_x_)           ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_LDO_RF0_CAL(_x_)           ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL2 */
+#define BITS_LDO_USB_CAL(_x_)           ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_LDO_EMMCCORE_CAL(_x_)      ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_LDO_EMMCIO_CAL(_x_)        ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL3 */
+#define BITS_LDO_SD_CAL(_x_)            ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_LDO_AVDD18_CAL(_x_)        ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL4 */
+#define BITS_LDO_CAMA_CAL(_x_)          ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_LDO_SIM2_CAL(_x_)          ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_LDO_SIM_CAL(_x_)           ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL5 */
+#define BITS_LDO_CAMMOT_CAL(_x_)        ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_LDO_CAMIO_CAL(_x_)         ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_LDO_CAMD_CAL(_x_)          ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL6 */
+#define BITS_LDOA_CAL_SEL(_x_)          ( (_x_) << 11 & (BIT(11)|BIT(12)|BIT(13)) )
+#define BITS_LDOD_CAL_SEL(_x_)          ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)) )
+#define BITS_LDODCDC_CAL_SEL(_x_)       ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_LDO_CLSG_CAL(_x_)          ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register ANA_REG_GLB_AUXAD_CTL */
+#define BIT_AUXAD_CURRENTSEN_EN         ( BIT(6) )
+#define BIT_AUXAD_CURRENTSEL            ( BIT(5) )
+#define BITS_AUXAD_CURRENT_IBS(_x_)     ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_CTRL0 */
+#define BIT_DCDC_CORE_LP_EN             ( BIT(15) )
+#define BIT_DCDC_CORE_CL_CTRL           ( BIT(14) )
+#define BITS_DCDC_CORE_PDRSLOW(_x_)     ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
+#define BIT_DCDC_CORE_PFM               ( BIT(9) )
+#define BIT_DCDC_CORE_DCM               ( BIT(8) )
+#define BIT_DCDC_ARM_LP_EN              ( BIT(7) )
+#define BIT_DCDC_ARM_CL_CTRL            ( BIT(6) )
+#define BITS_DCDC_ARM_PDRSLOW(_x_)      ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+#define BIT_DCDC_ARM_PFM                ( BIT(1) )
+#define BIT_DCDC_ARM_DCM                ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_CTRL1 */
+#define BIT_DCDC_MEM_LP_EN              ( BIT(15) )
+#define BIT_DCDC_MEM_CL_CTRL            ( BIT(14) )
+#define BITS_DCDC_MEM_PDRSLOW(_x_)      ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
+#define BIT_DCDC_MEM_PFM                ( BIT(9) )
+#define BIT_DCDC_MEM_DCM                ( BIT(8) )
+#define BIT_DCDC_GEN_LP_EN              ( BIT(7) )
+#define BIT_DCDC_GEN_CL_CTRL            ( BIT(6) )
+#define BITS_DCDC_GEN_PDRSLOW(_x_)      ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+#define BIT_DCDC_GEN_PFM                ( BIT(1) )
+#define BIT_DCDC_GEN_DCM                ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_CTRL2 */
+#define BIT_DCDC_BG_LP_EN               ( BIT(15) )
+#define BIT_DCDC_OTP_CHIP_PD_FLAG_CLR   ( BIT(14) )
+#define BIT_DCDC_OTP_CHIP_PD_FLAG       ( BIT(13) )
+#define BIT_DCDC_OTP_AUTO_PD_EN         ( BIT(12) )
+#define BIT_DCDC_OTP_VBEOP              ( BIT(11) )
+#define BITS_DCDC_OTP_S(_x_)            ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)) )
+#define BIT_DCDC_WRF_LP_EN              ( BIT(7) )
+#define BIT_DCDC_WRF_CL_CTRL            ( BIT(6) )
+#define BITS_DCDC_WRF_PDRSLOW(_x_)      ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+#define BIT_DCDC_WRF_PFM                ( BIT(1) )
+#define BIT_DCDC_WRF_DCM                ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_CTRL3 */
+#define BIT_DCDC_WPA_LP_EN              ( BIT(8) )
+#define BIT_DCDC_WPA_CL_CTRL            ( BIT(7) )
+#define BIT_DCDC_WPA_ZXOP               ( BIT(6) )
+#define BITS_DCDC_WPA_PDRSLOW(_x_)      ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+#define BIT_DCDC_WPA_PFM                ( BIT(1) )
+#define BIT_DCDC_WPA_APTEN              ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_CTRL4 */
+#define BIT_DCDC_CORE_OSCSYCEN_SW       ( BIT(15) )
+#define BIT_DCDC_CORE_OSCSYCEN_HW_EN    ( BIT(14) )
+#define BIT_DCDC_CORE_OSCSYC_DIV_EN     ( BIT(13) )
+#define BITS_DCDC_CORE_OSCSYC_DIV(_x_)  ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
+#define BIT_DCDC_ARM_OSCSYCEN_SW        ( BIT(7) )
+#define BIT_DCDC_ARM_OSCSYCEN_HW_EN     ( BIT(6) )
+#define BIT_DCDC_ARM_OSCSYC_DIV_EN      ( BIT(5) )
+#define BITS_DCDC_ARM_OSCSYC_DIV(_x_)   ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_CTRL5 */
+#define BIT_DCDC_MEM_OSCSYCEN_SW        ( BIT(15) )
+#define BIT_DCDC_MEM_OSCSYCEN_HW_EN     ( BIT(14) )
+#define BIT_DCDC_MEM_OSCSYC_DIV_EN      ( BIT(13) )
+#define BITS_DCDC_MEM_OSCSYC_DIV(_x_)   ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
+#define BIT_DCDC_GEN_OSCSYCEN_SW        ( BIT(7) )
+#define BIT_DCDC_GEN_OSCSYCEN_HW_EN     ( BIT(6) )
+#define BIT_DCDC_GEN_OSCSYC_DIV_EN      ( BIT(5) )
+#define BITS_DCDC_GEN_OSCSYC_DIV(_x_)   ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_CTRL6 */
+#define BIT_DCDC_WPA_OSCSYCEN_SW        ( BIT(15) )
+#define BIT_DCDC_WPA_OSCSYCEN_HW_EN     ( BIT(14) )
+#define BIT_DCDC_WPA_OSCSYC_DIV_EN      ( BIT(13) )
+#define BITS_DCDC_WPA_OSCSYC_DIV(_x_)   ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
+#define BIT_DCDC_WRF_OSCSYCEN_SW        ( BIT(7) )
+#define BIT_DCDC_WRF_OSCSYCEN_HW_EN     ( BIT(6) )
+#define BIT_DCDC_WRF_OSCSYC_DIV_EN      ( BIT(5) )
+#define BITS_DCDC_WRF_OSCSYC_DIV(_x_)   ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register ANA_REG_GLB_DDR2_CTRL */
+#define BIT_DDR2_BUF_PD_HW              ( BIT(9) )
+#define BITS_DDR2_BUF_S_DS(_x_)         ( (_x_) << 7 & (BIT(7)|BIT(8)) )
+#define BITS_DDR2_BUF_CHNS_DS(_x_)      ( (_x_) << 5 & (BIT(5)|BIT(6)) )
+#define BIT_DDR2_BUF_PD                 ( BIT(4) )
+#define BITS_DDR2_BUF_S(_x_)            ( (_x_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_DDR2_BUF_CHNS(_x_)         ( (_x_) << 0 & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register ANA_REG_GLB_SLP_WAIT_DCDCARM */
+#define BITS_SLP_IN_WAIT_DCDCARM(_x_)   ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_SLP_OUT_WAIT_DCDCARM(_x_)  ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register ANA_REG_GLB_LDO1828_XTL_CTL */
+#define BIT_LDO_VDD18_EXT_XTL2_EN       ( BIT(11) )
+#define BIT_LDO_VDD18_EXT_XTL1_EN       ( BIT(10) )
+#define BIT_LDO_VDD18_EXT_XTL0_EN       ( BIT(9) )
+#define BIT_LDO_VDD18_XTL2_EN           ( BIT(8) )
+#define BIT_LDO_VDD18_XTL1_EN           ( BIT(7) )
+#define BIT_LDO_VDD18_XTL0_EN           ( BIT(6) )
+#define BIT_LDO_VDD28_EXT_XTL2_EN       ( BIT(5) )
+#define BIT_LDO_VDD28_EXT_XTL1_EN       ( BIT(4) )
+#define BIT_LDO_VDD28_EXT_XTL0_EN       ( BIT(3) )
+#define BIT_LDO_VDD28_XTL2_EN           ( BIT(2) )
+#define BIT_LDO_VDD28_XTL1_EN           ( BIT(1) )
+#define BIT_LDO_VDD28_XTL0_EN           ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_LDO_SLP_CTRL0 */
+#define BIT_SLP_IO_EN                   ( BIT(15) )
+#define BIT_SLP_DCDC_OTP_PD_EN          ( BIT(13) )
+#define BIT_SLP_DCDCGEN_PD_EN           ( BIT(12) )
+#define BIT_SLP_DCDCWPA_PD_EN           ( BIT(11) )
+#define BIT_SLP_DCDCWRF_PD_EN           ( BIT(10) )
+#define BIT_SLP_DCDCARM_PD_EN           ( BIT(9) )
+#define BIT_SLP_LDOEMMCCORE_PD_EN       ( BIT(7) )
+#define BIT_SLP_LDOEMMCIO_PD_EN         ( BIT(6) )
+#define BIT_SLP_LDORF2_PD_EN            ( BIT(5) )
+#define BIT_SLP_LDORF1_PD_EN            ( BIT(4) )
+#define BIT_SLP_LDORF0_PD_EN            ( BIT(3) )
+#define BIT_SLP_LDOVDD25_PD_EN          ( BIT(2) )
+#define BIT_SLP_LDOVDD28_PD_EN          ( BIT(1) )
+#define BIT_SLP_LDOVDD18_PD_EN          ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_LDO_SLP_CTRL1 */
+#define BIT_SLP_LDO_PD_EN               ( BIT(12) )
+#define BIT_SLP_LDOLPREF_PD_EN          ( BIT(11) )
+#define BIT_SLP_LDOCLSG_PD_EN           ( BIT(10) )
+#define BIT_SLP_LDOUSB_PD_EN            ( BIT(9) )
+#define BIT_SLP_LDOCAMMOT_PD_EN         ( BIT(8) )
+#define BIT_SLP_LDOCAMIO_PD_EN          ( BIT(7) )
+#define BIT_SLP_LDOCAMD_PD_EN           ( BIT(6) )
+#define BIT_SLP_LDOCAMA_PD_EN           ( BIT(5) )
+#define BIT_SLP_LDOSIM2_PD_EN           ( BIT(4) )
+#define BIT_SLP_LDOSIM1_PD_EN           ( BIT(3) )
+#define BIT_SLP_LDOSIM0_PD_EN           ( BIT(2) )
+#define BIT_SLP_LDOSD_PD_EN             ( BIT(1) )
+#define BIT_SLP_LDOAVDD18_PD_EN         ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_LDO_SLP_CTRL2 */
+#define BIT_SLP_DCDC_BG_LP_EN           ( BIT(15) )
+#define BIT_SLP_DCDCCORE_LP_EN          ( BIT(11) )
+#define BIT_SLP_DCDCMEM_LP_EN           ( BIT(10) )
+#define BIT_SLP_DCDCARM_LP_EN           ( BIT(9) )
+#define BIT_SLP_DCDCGEN_LP_EN           ( BIT(8) )
+#define BIT_SLP_DCDCWPA_LP_EN           ( BIT(6) )
+#define BIT_SLP_DCDCWRF_LP_EN           ( BIT(5) )
+#define BIT_SLP_LDOEMMCCORE_LP_EN       ( BIT(4) )
+#define BIT_SLP_LDOEMMCIO_LP_EN         ( BIT(3) )
+#define BIT_SLP_LDORF2_LP_EN            ( BIT(2) )
+#define BIT_SLP_LDORF1_LP_EN            ( BIT(1) )
+#define BIT_SLP_LDORF0_LP_EN            ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_LDO_SLP_CTRL3 */
+#define BIT_SLP_BG_LP_EN                ( BIT(15) )
+#define BIT_SLP_LDOVDD25_LP_EN          ( BIT(13) )
+#define BIT_SLP_LDOVDD28_LP_EN          ( BIT(12) )
+#define BIT_SLP_LDOVDD18_LP_EN          ( BIT(11) )
+#define BIT_SLP_LDOCLSG_LP_EN           ( BIT(10) )
+#define BIT_SLP_LDOUSB_LP_EN            ( BIT(9) )
+#define BIT_SLP_LDOCAMMOT_LP_EN         ( BIT(8) )
+#define BIT_SLP_LDOCAMIO_LP_EN          ( BIT(7) )
+#define BIT_SLP_LDOCAMD_LP_EN           ( BIT(6) )
+#define BIT_SLP_LDOCAMA_LP_EN           ( BIT(5) )
+#define BIT_SLP_LDOSIM2_LP_EN           ( BIT(4) )
+#define BIT_SLP_LDOSIM1_LP_EN           ( BIT(3) )
+#define BIT_SLP_LDOSIM0_LP_EN           ( BIT(2) )
+#define BIT_SLP_LDOSD_LP_EN             ( BIT(1) )
+#define BIT_SLP_LDOAVDD18_LP_EN         ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_AUD_SLP_CTRL4 */
+#define BIT_SLP_AUD_PA_SW_PD_EN         ( BIT(15) )
+#define BIT_SLP_AUD_PA_LDO_PD_EN        ( BIT(14) )
+#define BIT_SLP_AUD_PA_PD_EN            ( BIT(13) )
+#define BIT_SLP_AUD_OVP_PD_PD_EN        ( BIT(9) )
+#define BIT_SLP_AUD_OVP_LDO_PD_EN       ( BIT(8) )
+#define BIT_SLP_AUD_VB_PD_EN            ( BIT(7) )
+#define BIT_SLP_AUD_VBO_PD_EN           ( BIT(6) )
+#define BIT_SLP_AUD_HEADMICBIAS_PD_EN   ( BIT(5) )
+#define BIT_SLP_AUD_MICBIAS_HV_PD_EN    ( BIT(2) )
+#define BIT_SLP_AUD_HEADMIC_PD_EN       ( BIT(1) )
+#define BIT_SLP_AUD_PMUR1_PD_EN         ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL */
+#define BITS_SLP_DCDCCORE_VOL_DROP_CNT(_x_)     ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DCDC_CORE_CTL_DS(_x_)      ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) )
+
+/* bits definitions for register ANA_REG_GLB_XTL_WAIT_CTRL */
+#define BIT_SLP_XTLBUF_PD_EN            ( BIT(9) )
+#define BIT_XTL_EN                      ( BIT(8) )
+#define BITS_XTL_WAIT(_x_)              ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register ANA_REG_GLB_FLASH_CTRL */
+#define BIT_FLASH_PON                   ( BIT(15) )
+#define BIT_FLASH_V_HW_EN               ( BIT(6) )
+#define BITS_FLASH_V_HW_STEP(_x_)       ( (_x_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_FLASH_V_SW(_x_)            ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register ANA_REG_GLB_WHTLED_CTRL0 */
+#define BIT_WHTLED_PD_STS               ( BIT(15) )
+#define BITS_WHTLED_DC(_x_)             ( (_x_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BIT_WHTLED_BOOST_EN             ( BIT(8) )
+#define BIT_WHTLED_SERIES_EN            ( BIT(7) )
+#define BITS_WHTLED_V(_x_)              ( (_x_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) )
+#define BIT_WHTLED_PD                   ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_WHTLED_CTRL1 */
+#define BIT_LCM_CABC_PWM_SEL            ( BIT(15) )
+#define BIT_RTC_PWM0_EN                 ( BIT(14) )
+#define BIT_PWM0_EN                     ( BIT(13) )
+#define BITS_WHTLED_ISET(_x_)           ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_WHTLED_FRE_AD(_x_)         ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)) )
+#define BITS_WHTLED_CLMIT_OP(_x_)       ( (_x_) << 0 & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register ANA_REG_GLB_WHTLED_CTRL2 */
+#define BIT_WHTLED_DIMMING_SEL          ( BIT(15) )
+#define BIT_WHTLED_PD_SEL               ( BIT(14) )
+#define BIT_WHTLED_DIS_OVST             ( BIT(13) )
+#define BIT_WHTLED_DIM_SEL              ( BIT(12) )
+#define BIT_WHTLED_DE_BIAS              ( BIT(11) )
+#define BIT_WHTLED_BUFF_SHT             ( BIT(10) )
+#define BITS_WHTLED_STB_OP(_x_)         ( (_x_) << 8 & (BIT(8)|BIT(9)) )
+#define BIT_WHTLED_CAP_OPTION           ( BIT(7) )
+#define BIT_WHTLED_OVP_DIS              ( BIT(6) )
+#define BITS_WHTLED_REF_DC(_x_)         ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+
+/* bits definitions for register ANA_REG_GLB_ANA_DRV_CTRL */
+#define BIT_SLP_RGB_PD_EN               ( BIT(14) )
+#define BIT_RGB_PD_HW_EN                ( BIT(13) )
+#define BITS_RGB_V(_x_)                 ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
+#define BITS_KPLED_V(_x_)               ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_RGB_PD_SW                   ( BIT(2) )
+#define BIT_KPLED_PD                    ( BIT(1) )
+#define BIT_KPLED_PD_STS                ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_VIBR_CTRL0 */
+#define BITS_VIBR_STABLE_V_HW(_x_)      ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_VIBR_INIT_V_HW(_x_)        ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_VIBR_V_SW(_x_)             ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_VIBR_PON                    ( BIT(2) )
+#define BIT_VIBR_SW_EN                  ( BIT(1) )
+
+/* bits definitions for register ANA_REG_GLB_VIBR_CTRL1 */
+#define BITS_VIBR_V_CONVERT_CNT_HW(_x_) ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register ANA_REG_GLB_VIBR_CTRL2 */
+#define BIT_VIBR_PWR_ON_STS             ( BIT(15) )
+#define BIT_VIBR_HW_FLOW_ERR1           ( BIT(14) )
+#define BIT_VIBR_HW_FLOW_ERR1_CLR       ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_VIBR_WR_PROT_VALUE */
+#define BIT_VIBR_WR_PROT                ( BIT(15) )
+#define BITS_VIBR_WR_PROT_VALUE(_x_)    ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+
+/* bits definitions for register ANA_REG_GLB_AUDIO_CTRL */
+#define BIT_AUD_SLP_APP_RST_EN          ( BIT(10) )
+#define BITS_CLK_AUD_HBD_DIV(_x_)       ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BIT_CLK_AUD_LOOP_INV_EN         ( BIT(4) )
+#define BIT_CLK_AUDIF_TX_INV_EN         ( BIT(3) )
+#define BIT_CLK_AUDIF_RX_INV_EN         ( BIT(2) )
+#define BIT_CLK_AUD_6P5M_TX_INV_EN      ( BIT(1) )
+#define BIT_CLK_AUD_6P5M_RX_INV_EN      ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_CHGR_CTRL0 */
+#define BIT_CHGR_PD_STS                 ( BIT(15) )
+#define BITS_CHGR_CV_V(_x_)             ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_CHGR_END_V(_x_)            ( (_x_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_CHG_PUMP_V(_x_)            ( (_x_) << 2 & (BIT(2)|BIT(3)) )
+#define BIT_CHGR_PD_RTCCLR              ( BIT(1) )
+#define BIT_CHGR_PD_RTCSET              ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_CHGR_CTRL1 */
+#define BIT_DP_DM_SW_EN                 ( BIT(15) )
+#define BITS_CHGR_CC_I(_x_)             ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_VBAT_OVP_V(_x_)            ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_VCHG_OVP_V(_x_)            ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+
+/* bits definitions for register ANA_REG_GLB_CHGR_CTRL2 */
+#define BITS_CHG_PUMP_CAL(_x_)          ( (_x_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
+#define BIT_CHG_PUMP_PD                 ( BIT(8) )
+#define BIT_CHGR_CC_EN                  ( BIT(1) )
+#define BIT_RECHG                       ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_CHGR_STATUS */
+#define BIT_CHG_DET_DONE                ( BIT(11) )
+#define BIT_DP_LOW                      ( BIT(10) )
+#define BIT_DCP_DET                     ( BIT(9) )
+#define BIT_CHG_DET                     ( BIT(8) )
+#define BIT_SDP_INT                     ( BIT(7) )
+#define BIT_DCP_INT                     ( BIT(6) )
+#define BIT_CDP_INT                     ( BIT(5) )
+#define BIT_CHGR_CV_STATUS              ( BIT(4) )
+#define BIT_CHGR_ON                     ( BIT(3) )
+#define BIT_CHGR_INT                    ( BIT(2) )
+#define BIT_VBAT_OVI                    ( BIT(1) )
+#define BIT_VCHG_OVI                    ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_ANA_MIXED_CTRL */
+#define BIT_PTEST_PD_RTCSET             ( BIT(15) )
+#define BIT_THM_CHIP_PD_FLAG            ( BIT(8) )
+#define BIT_THM_CHIP_PD_FLAG_CLR        ( BIT(7) )
+#define BITS_THM_CAL_SEL(_x_)           ( (_x_) << 5 & (BIT(5)|BIT(6)) )
+#define BIT_THM_AUTO_PD_EN              ( BIT(4) )
+#define BIT_BG_LP_EN                    ( BIT(3) )
+#define BITS_UVHO_T(_x_)                ( (_x_) << 1 & (BIT(1)|BIT(2)) )
+#define BIT_UVHO_EN                     ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN0 */
+#define BIT_LDO_XTL_EN                  ( BIT(15) )
+#define BIT_LDO_RF1_EXT_XTL2_EN         ( BIT(11) )
+#define BIT_LDO_RF1_EXT_XTL1_EN         ( BIT(10) )
+#define BIT_LDO_RF1_EXT_XTL0_EN         ( BIT(9) )
+#define BIT_LDO_RF1_XTL2_EN             ( BIT(8) )
+#define BIT_LDO_RF1_XTL1_EN             ( BIT(7) )
+#define BIT_LDO_RF1_XTL0_EN             ( BIT(6) )
+#define BIT_LDO_RF0_EXT_XTL2_EN         ( BIT(5) )
+#define BIT_LDO_RF0_EXT_XTL1_EN         ( BIT(4) )
+#define BIT_LDO_RF0_EXT_XTL0_EN         ( BIT(3) )
+#define BIT_LDO_RF0_XTL2_EN             ( BIT(2) )
+#define BIT_LDO_RF0_XTL1_EN             ( BIT(1) )
+#define BIT_LDO_RF0_XTL0_EN             ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN1 */
+#define BIT_LDO_VDD25_EXT_XTL2_EN       ( BIT(11) )
+#define BIT_LDO_VDD25_EXT_XTL1_EN       ( BIT(10) )
+#define BIT_LDO_VDD25_EXT_XTL0_EN       ( BIT(9) )
+#define BIT_LDO_VDD25_XTL2_EN           ( BIT(8) )
+#define BIT_LDO_VDD25_XTL1_EN           ( BIT(7) )
+#define BIT_LDO_VDD25_XTL0_EN           ( BIT(6) )
+#define BIT_LDO_RF2_EXT_XTL2_EN         ( BIT(5) )
+#define BIT_LDO_RF2_EXT_XTL1_EN         ( BIT(4) )
+#define BIT_LDO_RF2_EXT_XTL0_EN         ( BIT(3) )
+#define BIT_LDO_RF2_XTL2_EN             ( BIT(2) )
+#define BIT_LDO_RF2_XTL1_EN             ( BIT(1) )
+#define BIT_LDO_RF2_XTL0_EN             ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN2 */
+#define BIT_LDO_AVDD18_EXT_XTL2_EN      ( BIT(11) )
+#define BIT_LDO_AVDD18_EXT_XTL1_EN      ( BIT(10) )
+#define BIT_LDO_AVDD18_EXT_XTL0_EN      ( BIT(9) )
+#define BIT_LDO_AVDD18_XTL2_EN          ( BIT(8) )
+#define BIT_LDO_AVDD18_XTL1_EN          ( BIT(7) )
+#define BIT_LDO_AVDD18_XTL0_EN          ( BIT(6) )
+#define BIT_LDO_SIM2_EXT_XTL2_EN        ( BIT(5) )
+#define BIT_LDO_SIM2_EXT_XTL1_EN        ( BIT(4) )
+#define BIT_LDO_SIM2_EXT_XTL0_EN        ( BIT(3) )
+#define BIT_LDO_SIM2_XTL2_EN            ( BIT(2) )
+#define BIT_LDO_SIM2_XTL1_EN            ( BIT(1) )
+#define BIT_LDO_SIM2_XTL0_EN            ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN3 */
+#define BIT_DCDC_BG_EXT_XTL2_EN         ( BIT(11) )
+#define BIT_DCDC_BG_EXT_XTL1_EN         ( BIT(10) )
+#define BIT_DCDC_BG_EXT_XTL0_EN         ( BIT(9) )
+#define BIT_DCDC_BG_XTL2_EN             ( BIT(8) )
+#define BIT_DCDC_BG_XTL1_EN             ( BIT(7) )
+#define BIT_DCDC_BG_XTL0_EN             ( BIT(6) )
+#define BIT_BG_EXT_XTL2_EN              ( BIT(5) )
+#define BIT_BG_EXT_XTL1_EN              ( BIT(4) )
+#define BIT_BG_EXT_XTL0_EN              ( BIT(3) )
+#define BIT_BG_XTL2_EN                  ( BIT(2) )
+#define BIT_BG_XTL1_EN                  ( BIT(1) )
+#define BIT_BG_XTL0_EN                  ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN4 */
+#define BIT_DCDC_WRF_XTL2_EN            ( BIT(14) )
+#define BIT_DCDC_WRF_XTL1_EN            ( BIT(13) )
+#define BIT_DCDC_WRF_XTL0_EN            ( BIT(12) )
+#define BIT_DCDC_WPA_XTL2_EN            ( BIT(11) )
+#define BIT_DCDC_WPA_XTL1_EN            ( BIT(10) )
+#define BIT_DCDC_WPA_XTL0_EN            ( BIT(9) )
+#define BIT_DCDC_MEM_XTL2_EN            ( BIT(8) )
+#define BIT_DCDC_MEM_XTL1_EN            ( BIT(7) )
+#define BIT_DCDC_MEM_XTL0_EN            ( BIT(6) )
+#define BIT_DCDC_GEN_XTL2_EN            ( BIT(5) )
+#define BIT_DCDC_GEN_XTL1_EN            ( BIT(4) )
+#define BIT_DCDC_GEN_XTL0_EN            ( BIT(3) )
+#define BIT_DCDC_CORE_XTL2_EN           ( BIT(2) )
+#define BIT_DCDC_CORE_XTL1_EN           ( BIT(1) )
+#define BIT_DCDC_CORE_XTL0_EN           ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN5 */
+#define BIT_DCDC_WRF_EXT_XTL2_EN        ( BIT(14) )
+#define BIT_DCDC_WRF_EXT_XTL1_EN        ( BIT(13) )
+#define BIT_DCDC_WRF_EXT_XTL0_EN        ( BIT(12) )
+#define BIT_DCDC_WPA_EXT_XTL2_EN        ( BIT(11) )
+#define BIT_DCDC_WPA_EXT_XTL1_EN        ( BIT(10) )
+#define BIT_DCDC_WPA_EXT_XTL0_EN        ( BIT(9) )
+#define BIT_DCDC_MEM_EXT_XTL2_EN        ( BIT(8) )
+#define BIT_DCDC_MEM_EXT_XTL1_EN        ( BIT(7) )
+#define BIT_DCDC_MEM_EXT_XTL0_EN        ( BIT(6) )
+#define BIT_DCDC_GEN_EXT_XTL2_EN        ( BIT(5) )
+#define BIT_DCDC_GEN_EXT_XTL1_EN        ( BIT(4) )
+#define BIT_DCDC_GEN_EXT_XTL0_EN        ( BIT(3) )
+#define BIT_DCDC_CORE_EXT_XTL2_EN       ( BIT(2) )
+#define BIT_DCDC_CORE_EXT_XTL1_EN       ( BIT(1) )
+#define BIT_DCDC_CORE_EXT_XTL0_EN       ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_ANA_STATUS */
+#define BIT_BONDOPT6                    ( BIT(6) )
+#define BIT_BONDOPT5                    ( BIT(5) )
+#define BIT_BONDOPT4                    ( BIT(4) )
+#define BIT_BONDOPT3                    ( BIT(3) )
+#define BIT_BONDOPT2                    ( BIT(2) )
+#define BIT_BONDOPT1                    ( BIT(1) )
+#define BIT_BONDOPT0                    ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_POR_RST_MONITOR */
+#define BITS_POR_RST_MONITOR(_x_)       ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register ANA_REG_GLB_WDG_RST_MONITOR */
+#define BITS_WDG_RST_MONITOR(_x_)       ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register ANA_REG_GLB_POR_PIN_RST_MONITOR */
+#define BITS_POR_PIN_RST_MONITOR(_x_)   ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register ANA_REG_GLB_POR_SRC_FLAG */
+#define BIT_POR_SW_FORCE_ON             ( BIT(15) )
+#define BITS_POR_SRC_FLAG(_x_)          ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+
+/* bits definitions for register ANA_REG_GLB_POR_7S_CTRL */
+#define BIT_PBINT_7S_FLAG_CLR           ( BIT(15) )
+#define BIT_EXT_RSTN_FLAG_CLR           ( BIT(14) )
+#define BIT_CHGR_INT_FLAG_CLR           ( BIT(13) )
+#define BIT_PBINT2_FLAG_CLR             ( BIT(12) )
+#define BIT_PBINT_FLAG_CLR              ( BIT(11) )
+#define BIT_PBINT_7S_RST_SWMODE_RTCSTS  ( BIT(10) )
+#define BIT_PBINT_7S_RST_SWMODE_RTCCLR  ( BIT(9) )
+#define BIT_PBINT_7S_RST_SWMODE_RTCSET  ( BIT(8) )
+#define BITS_PBINT_7S_RST_THRESHOLD(_x_)( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_PBINT_7S_RST_DISABLE        ( BIT(3) )
+#define BIT_PBINT_7S_RST_MODE_RTCSTS    ( BIT(2) )
+#define BIT_PBINT_7S_RST_MODE_RTCCLR    ( BIT(1) )
+#define BIT_PBINT_7S_RST_MODE_RTCSET    ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_INT_DEBUG */
+#define BIT_OTP_INT_DEB                 ( BIT(10) )
+#define BIT_THM_INT_DEB                 ( BIT(9) )
+#define BIT_AUD_PROT_INT_DEB            ( BIT(8) )
+#define BIT_AUD_HEADBTN_INT_DEB         ( BIT(7) )
+#define BIT_EIC_INT_DEB                 ( BIT(6) )
+#define BIT_FGU_INT_DEB                 ( BIT(5) )
+#define BIT_WDG_INT_DEB                 ( BIT(4) )
+#define BIT_RTC_INT_DEB                 ( BIT(3) )
+#define BIT_GPIO_INT_DEB                ( BIT(2) )
+#define BIT_ADC_INT_DEB                 ( BIT(1) )
+#define BIT_INT_DEBUG_EN                ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_GPI_DEBUG */
+#define BIT_HEAD_INSERT2_DEB            ( BIT(9) )
+#define BIT_HEAD_INSERT_DEB             ( BIT(8) )
+#define BIT_HEAD_BUTTON_DEB             ( BIT(7) )
+#define BIT_PBINT2_DEB                  ( BIT(6) )
+#define BIT_PBINT_DEB                   ( BIT(5) )
+#define BIT_VCHG_OVI_DEB                ( BIT(4) )
+#define BIT_VBAT_OVI_DEB                ( BIT(3) )
+#define BIT_CHGR_INT_DEB                ( BIT(2) )
+#define BIT_GPI_DEBUG_EN                ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_HWRST_RTC */
+#define BITS_HWRST_RTC_REG_STS(_x_)     ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_HWRST_RTC_REG_SET(_x_)     ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register ANA_REG_GLB_CHIP_ID_LOW */
+#define BITS_CHIP_ID_LOW(_x_)           ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register ANA_REG_GLB_CHIP_ID_HIGH */
+#define BITS_CHIP_ID_HIGH(_x_)          ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register ANA_REG_GLB_ARM_MF_REG */
+#define BITS_ARM_MF_REG(_x_)            ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register ANA_REG_GLB_AFUSE_CTRL */
+#define BIT_AFUSE_READ_REQ              ( BIT(7) )
+#define BITS_AFUSE_READ_DLY(_x_)        ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) )
+
+/* bits definitions for register ANA_REG_GLB_AFUSE_OUT0 */
+#define BITS_AFUSE_OUT0(_x_)            ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register ANA_REG_GLB_AFUSE_OUT1 */
+#define BITS_AFUSE_OUT1(_x_)            ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register ANA_REG_GLB_AFUSE_OUT2 */
+#define BITS_AFUSE_OUT2(_x_)            ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register ANA_REG_GLB_AFUSE_OUT3 */
+#define BITS_AFUSE_OUT3(_x_)            ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register ANA_REG_GLB_CA_CTRL4 */
+#define BIT_EXT_RSTN_PD_EN              ( BIT(14) )
+#define BIT_PB_7S_RST_PD_EN             ( BIT(13) )
+#define BIT_WDG_RST_PD_EN               ( BIT(12) )
+#define BIT_SW_RST_EMMCIO_PD_EN         ( BIT(11) )
+#define BIT_SW_RST_EMMCCORE_PD_EN       ( BIT(10) )
+#define BITS_SW_RST_PD_THRESHOLD(_x_)   ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+
+/* bits definitions for register ANA_REG_GLB_MCU_WR_PROT_VALUE */
+#define BIT_MCU_WR_PROT                 ( BIT(15) )
+#define BITS_MCU_WR_PROT_VALUE(_x_)     ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+
+/* bits definitions for register ANA_REG_GLB_MP_PWR_CTRL0 */
+#define BIT_LDO_SIM1_EXT_XTL2_EN                      ( BIT(15) )
+#define BIT_LDO_SIM1_EXT_XTL1_EN                      ( BIT(14) )
+#define BIT_LDO_SIM1_EXT_XTL0_EN                      ( BIT(13) )
+#define BIT_LDO_SIM1_XTL2_EN                          ( BIT(12) )
+#define BIT_LDO_SIM1_XTL1_EN                          ( BIT(11) )
+#define BIT_LDO_SIM1_XTL0_EN                          ( BIT(10) )
+#define BIT_LDO_SIM0_EXT_XTL2_EN                      ( BIT(9) )
+#define BIT_LDO_SIM0_EXT_XTL1_EN                      ( BIT(8) )
+#define BIT_LDO_SIM0_EXT_XTL0_EN                      ( BIT(7) )
+#define BIT_LDO_SIM0_XTL2_EN                          ( BIT(6) )
+#define BIT_LDO_SIM0_XTL1_EN                          ( BIT(5) )
+#define BIT_LDO_SIM0_XTL0_EN                          ( BIT(4) )
+#define BIT_PWR_OFF_SEQ_EN                            ( BIT(3) )
+#define BIT_DCDC_CORE_SLP_OUT_STEP_EN                 ( BIT(1) )
+#define BIT_DCDC_CORE_SLP_IN_STEP_EN                  ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_MP_PWR_CTRL1 */
+#define BITS_DCDC_CORE_CTL_SLP_STEP5(_x_)             ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_DCDC_CORE_CTL_SLP_STEP4(_x_)             ( (_x_) << 9 & (BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DCDC_CORE_CTL_SLP_STEP3(_x_)             ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)) )
+#define BITS_DCDC_CORE_CTL_SLP_STEP2(_x_)             ( (_x_) << 3 & (BIT(3)|BIT(4)|BIT(5)) )
+#define BITS_DCDC_CORE_CTL_SLP_STEP1(_x_)             ( (_x_) & (BIT(0)|BIT(1)|BIT(2)) )
+
+/* bits definitions for register ANA_REG_GLB_MP_PWR_CTRL2 */
+#define BITS_DCDC_CORE_CAL_SLP_STEP3(_x_)             ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_DCDC_CORE_CAL_SLP_STEP2(_x_)             ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_DCDC_CORE_CAL_SLP_STEP1(_x_)             ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register ANA_REG_GLB_MP_PWR_CTRL3 */
+#define BITS_DCDC_ARM_STBOP(_x_)                      ( (_x_) << 12 & (BIT(12)|BIT(13)) )
+#define BITS_DCDC_CORE_STBOP(_x_)                     ( (_x_) << 10 & (BIT(10)|BIT(11)) )
+#define BITS_DCDC_CORE_CAL_SLP_STEP5(_x_)             ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_DCDC_CORE_CAL_SLP_STEP4(_x_)             ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register ANA_REG_GLB_MP_LDO_CTRL */
+#define BITS_LDOD_LP_CAL(_x_)                         ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_LDOA_LP_CAL(_x_)                         ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_LDODCDC_LP_CAL(_x_)                      ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register ANA_REG_GLB_MP_CHG_CTRL */
+#define BIT_CHGR_INT_EN                               ( BIT(8) )
+#define BIT_CHGR_DRV                                  ( BIT(5) )
+#define BIT_CHGR_OSC                                  ( BIT(4) )
+#define BITS_CHGR_DPM(_x_)                            ( (_x_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_CHGR_ITERM(_x_)                          ( (_x_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register ANA_REG_GLB_MP_MISC_CTRL */
+#define BITS_LDO_RF1_V_BOND(_x_)                      ( (_x_) << 11 & (BIT(11)|BIT(12)) )
+#define BITS_LDO_VDD25_V_BOND(_x_)                    ( (_x_) << 9 & (BIT(9)|BIT(10)) )
+#define BITS_DCDC_ARM_CTL_BOND(_x_)                   ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)) )
+#define BITS_DCDC_CORE_CTL_BOND(_x_)                  ( (_x_) << 3 & (BIT(3)|BIT(4)|BIT(5)) )
+#define BIT_DCOFFSET_EN                               ( BIT(2) )
+#define BIT_CHOP_EN                                   ( BIT(1) )
+#define BIT_WHTLED_EXT_RES_CTRL                       ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_MP_DCDC_DEDT_CTRL */
+#define BITS_DCDC_WPA_DEDT_EN(_x_)                    ( (_x_) << 10 & (BIT(10)|BIT(11)) )
+#define BITS_DCDC_WRF_DEDT_EN(_x_)                    ( (_x_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_DCDC_GEN_DEDT_EN(_x_)                    ( (_x_) << 6 & (BIT(6)|BIT(7)) )
+#define BITS_DCDC_MEM_DEDT_EN(_x_)                    ( (_x_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_DCDC_ARM_DEDT_EN(_x_)                    ( (_x_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_DCDC_CORE_DEDT_EN(_x_)                   ( (_x_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register ANA_REG_GLB_CA_CTRL0 */
+#define BITS_SD_CLK_P(_x_)                            ( (_x_) << 14 & (BIT(14)|BIT(15)) )
+#define BIT_SD_CHOP_CAP_EN                            ( BIT(13) )
+#define BIT_LDO_CAMIO_V_B2                            ( BIT(12) )
+#define BIT_LDO_CAMIO_EXT_XTL2_EN                     ( BIT(11) )
+#define BIT_LDO_CAMIO_EXT_XTL1_EN                     ( BIT(10) )
+#define BIT_LDO_CAMIO_EXT_XTL0_EN                     ( BIT(9) )
+#define BIT_LDO_CAMIO_XTL2_EN                         ( BIT(8) )
+#define BIT_LDO_CAMIO_XTL1_EN                         ( BIT(7) )
+#define BIT_LDO_CAMIO_XTL0_EN                         ( BIT(6) )
+#define BIT_LDO_CAMD_EXT_XTL2_EN                      ( BIT(5) )
+#define BIT_LDO_CAMD_EXT_XTL1_EN                      ( BIT(4) )
+#define BIT_LDO_CAMD_EXT_XTL0_EN                      ( BIT(3) )
+#define BIT_LDO_CAMD_XTL2_EN                          ( BIT(2) )
+#define BIT_LDO_CAMD_XTL1_EN                          ( BIT(1) )
+#define BIT_LDO_CAMD_XTL0_EN                          ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_CA_CTRL1 */
+#define BITS_SMPL_MODE(_x_)                           ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register ANA_REG_GLB_CA_CTRL2 */
+#define BIT_SMPL_PWR_ON_FLAG                          ( BIT(15) )
+#define BIT_SMPL_MODE_WR_ACK_FLAG                     ( BIT(14) )
+#define BIT_SMPL_PWR_ON_FLAG_CLR                      ( BIT(13) )
+#define BIT_SMPL_MODE_WR_ACK_FLAG_CLR                 ( BIT(12) )
+#define BIT_SMPL_PWR_ON_SET                           ( BIT(11) )
+#define BIT_SLP_LDOKPLED_PD_EN                        ( BIT(9) )
+#define BIT_LDO_KPLED_PD                              ( BIT(8) )
+#define BITS_LDO_KPLED_V(_x_)                         ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register ANA_REG_GLB_CA_CTRL3 */
+#define BITS_VBAT_CRASH_V(_x_)                        ( (_x_) << 14 & (BIT(14)|BIT(15)) )
+#define BIT_PBINT_7S_AUTO_ON_EN_CLR                   ( BIT(13) )
+#define BIT_PBINT_7S_AUTO_ON_EN_SET                   ( BIT(12) )
+#define BIT_VIBR_LDO_EN                               ( BIT(10) )
+#define BIT_SLP_LDOVIBR_PD_EN                         ( BIT(9) )
+#define BIT_LDO_VIBR_PD                               ( BIT(8) )
+#define BITS_LDO_VIBR_V(_x_)                          ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_CORE_ADI */
+#define BITS_DCDC_CORE_CTL_ADI(_x_)                   ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DCDC_CORE_CAL_ADI(_x_)                   ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_ARM_ADI */
+#define BITS_DCDC_ARM_CTL_ADI(_x_)                    ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DCDC_ARM_CAL_ADI(_x_)                    ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_MEM_ADI */
+#define BIT_DCDC_MEM_CTL_ADI                          ( BIT(5) )
+#define BITS_DCDC_MEM_CAL_ADI(_x_)                    ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_GEN_ADI */
+#define BITS_DCDC_GEN_CTL_ADI(_x_)                    ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DCDC_GEN_CAL_ADI(_x_)                    ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_WRF_ADI */
+#define BITS_DCDC_WRF_CTL_ADI(_x_)                    ( (_x_) << 5 & (BIT(5)|BIT(6)) )
+#define BITS_DCDC_WRF_CAL_ADI(_x_)                    ( (_x_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_WPA_ADI */
+#define BITS_DCDC_WPA_CAL_ADI(_x_)                    ( (_x_) & (BIT(0)|BIT(1)|BIT(2)) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_WPA_DCM_ADI */
+#define BIT_DCDC_WPA_DCM_ADI                          ( BIT(0) )
+
+#endif /* __REGS_ANA_SC2713S_GLB_H__ */
diff --git a/include/soc/sprd/chip_x20/__regs_ana_sc2723_glb.h b/include/soc/sprd/chip_x20/__regs_ana_sc2723_glb.h
new file mode 100644
index 00000000..f707171c
--- /dev/null
+++ b/include/soc/sprd/chip_x20/__regs_ana_sc2723_glb.h
@@ -0,0 +1,949 @@
+/*
+ * Copyright (C) 2014 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+#ifndef __ANA_REGS_GLB_H__
+#define __ANA_REGS_GLB_H__
+
+#define ANA_REGS_GLB
+
+/* registers definitions for controller ANA_REGS_GLB */
+#define ANA_REG_GLB_ARM_MODULE_EN       SCI_ADDR(ANA_REGS_GLB_BASE, 0x0000)
+#define ANA_REG_GLB_ARM_CLK_EN          SCI_ADDR(ANA_REGS_GLB_BASE, 0x0004)
+#define ANA_REG_GLB_RTC_CLK_EN          SCI_ADDR(ANA_REGS_GLB_BASE, 0x0008)
+#define ANA_REG_GLB_ARM_RST             SCI_ADDR(ANA_REGS_GLB_BASE, 0x000C)
+#define ANA_REG_GLB_LDO_DCDC_PD         SCI_ADDR(ANA_REGS_GLB_BASE, 0x0010)
+#define ANA_REG_GLB_LDO_PD_CTRL         SCI_ADDR(ANA_REGS_GLB_BASE, 0x0014)
+#define ANA_REG_GLB_LDO_V_CTRL0         SCI_ADDR(ANA_REGS_GLB_BASE, 0x0018)
+#define ANA_REG_GLB_LDO_V_CTRL1         SCI_ADDR(ANA_REGS_GLB_BASE, 0x001C)
+#define ANA_REG_GLB_LDO_V_CTRL2         SCI_ADDR(ANA_REGS_GLB_BASE, 0x0020)
+#define ANA_REG_GLB_LDO_V_CTRL3         SCI_ADDR(ANA_REGS_GLB_BASE, 0x0024)
+#define ANA_REG_GLB_LDO_V_CTRL4         SCI_ADDR(ANA_REGS_GLB_BASE, 0x0028)
+#define ANA_REG_GLB_LDO_V_CTRL5         SCI_ADDR(ANA_REGS_GLB_BASE, 0x002C)
+#define ANA_REG_GLB_LDO_V_CTRL6         SCI_ADDR(ANA_REGS_GLB_BASE, 0x0030)
+#define ANA_REG_GLB_LDO_V_CTRL7         SCI_ADDR(ANA_REGS_GLB_BASE, 0x0034)
+#define ANA_REG_GLB_LDO_V_CTRL8         SCI_ADDR(ANA_REGS_GLB_BASE, 0x0038)
+#define ANA_REG_GLB_LDO_V_CTRL9         SCI_ADDR(ANA_REGS_GLB_BASE, 0x003C)
+#define ANA_REG_GLB_LDO_V_CTRL10        SCI_ADDR(ANA_REGS_GLB_BASE, 0x0040)
+#define ANA_REG_GLB_LDO_V_CTRL11        SCI_ADDR(ANA_REGS_GLB_BASE, 0x0044)
+#define ANA_REG_GLB_LDO_LP_CTRL         SCI_ADDR(ANA_REGS_GLB_BASE, 0x0048)
+#define ANA_REG_GLB_DCDC_CTRL0          SCI_ADDR(ANA_REGS_GLB_BASE, 0x004C)
+#define ANA_REG_GLB_DCDC_CTRL1          SCI_ADDR(ANA_REGS_GLB_BASE, 0x0050)
+#define ANA_REG_GLB_DCDC_CTRL2          SCI_ADDR(ANA_REGS_GLB_BASE, 0x0054)
+#define ANA_REG_GLB_DCDC_CTRL3          SCI_ADDR(ANA_REGS_GLB_BASE, 0x0058)
+#define ANA_REG_GLB_DCDC_CTRL4          SCI_ADDR(ANA_REGS_GLB_BASE, 0x005C)
+#define ANA_REG_GLB_DCDC_CTRL5          SCI_ADDR(ANA_REGS_GLB_BASE, 0x0060)
+#define ANA_REG_GLB_DCDC_CTRL6          SCI_ADDR(ANA_REGS_GLB_BASE, 0x0064)
+#define ANA_REG_GLB_DCDC_CTRL7          SCI_ADDR(ANA_REGS_GLB_BASE, 0x0068)
+#define ANA_REG_GLB_DCDC_CTRL8          SCI_ADDR(ANA_REGS_GLB_BASE, 0x006C)
+#define ANA_REG_GLB_DCDC_CTRL9          SCI_ADDR(ANA_REGS_GLB_BASE, 0x0070)
+#define ANA_REG_GLB_DCDC_CTRL10         SCI_ADDR(ANA_REGS_GLB_BASE, 0x0074)
+#define ANA_REG_GLB_DCDC_CTRL11         SCI_ADDR(ANA_REGS_GLB_BASE, 0x0078)
+#define ANA_REG_GLB_DCDC_CTRL12         SCI_ADDR(ANA_REGS_GLB_BASE, 0x007C)
+#define ANA_REG_GLB_DCDC_CTRL13         SCI_ADDR(ANA_REGS_GLB_BASE, 0x0080)
+#define ANA_REG_GLB_DCDC_CTRL14         SCI_ADDR(ANA_REGS_GLB_BASE, 0x0084)
+#define ANA_REG_GLB_DCDC_CTRL15         SCI_ADDR(ANA_REGS_GLB_BASE, 0x0088)
+#define ANA_REG_GLB_SLP_WAIT_DCDCARM    SCI_ADDR(ANA_REGS_GLB_BASE, 0x008C)
+#define ANA_REG_GLB_PWR_SLP_CTRL0       SCI_ADDR(ANA_REGS_GLB_BASE, 0x0090)
+#define ANA_REG_GLB_PWR_SLP_CTRL1       SCI_ADDR(ANA_REGS_GLB_BASE, 0x0094)
+#define ANA_REG_GLB_PWR_SLP_CTRL2       SCI_ADDR(ANA_REGS_GLB_BASE, 0x0098)
+#define ANA_REG_GLB_PWR_SLP_CTRL3       SCI_ADDR(ANA_REGS_GLB_BASE, 0x009C)
+#define ANA_REG_GLB_PWR_SLP_CTRL4       SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A0)
+#define ANA_REG_GLB_AUD_SLP_CTRL        SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A4)
+#define ANA_REG_GLB_DCDC_SLP_CTRL0      SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A8)
+#define ANA_REG_GLB_DCDC_SLP_CTRL1      SCI_ADDR(ANA_REGS_GLB_BASE, 0x00AC)
+#define ANA_REG_GLB_DCDC_SLP_CTRL2      SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B0)
+#define ANA_REG_GLB_DCDC_SLP_CTRL3      SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B4)
+#define ANA_REG_GLB_DCDC_SLP_CTRL4      SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B8)
+#define ANA_REG_GLB_DCDC_SLP_CTRL5      SCI_ADDR(ANA_REGS_GLB_BASE, 0x00BC)
+#define ANA_REG_GLB_PWR_SEL             SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C0)
+#define ANA_REG_GLB_PWR_XTL_EN0         SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C4)
+#define ANA_REG_GLB_PWR_XTL_EN1         SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C8)
+#define ANA_REG_GLB_PWR_XTL_EN2         SCI_ADDR(ANA_REGS_GLB_BASE, 0x00CC)
+#define ANA_REG_GLB_PWR_XTL_EN3         SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D0)
+#define ANA_REG_GLB_32KLESS_CTRL0       SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D4)
+#define ANA_REG_GLB_32KLESS_CTRL1       SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D8)
+#define ANA_REG_GLB_32KLESS_CTRL2       SCI_ADDR(ANA_REGS_GLB_BASE, 0x00DC)
+#define ANA_REG_GLB_32KLESS_CTRL3       SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E0)
+#define ANA_REG_GLB_AUXAD_CTL           SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E4)
+#define ANA_REG_GLB_XTL_WAIT_CTRL       SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E8)
+#define ANA_REG_GLB_RGB_CTRL            SCI_ADDR(ANA_REGS_GLB_BASE, 0x00EC)
+#define ANA_REG_GLB_WHTLED_CTRL         SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F0)
+#define ANA_REG_GLB_KPLED_CTRL          SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F4)
+#define ANA_REG_GLB_VIBR_CTRL0          SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F8)
+#define ANA_REG_GLB_AUDIO_CTRL0         SCI_ADDR(ANA_REGS_GLB_BASE, 0x00FC)
+#define ANA_REG_GLB_AUDIO_CTRL1         SCI_ADDR(ANA_REGS_GLB_BASE, 0x0100)
+#define ANA_REG_GLB_CHGR_CTRL0          SCI_ADDR(ANA_REGS_GLB_BASE, 0x0104)
+#define ANA_REG_GLB_CHGR_CTRL1          SCI_ADDR(ANA_REGS_GLB_BASE, 0x0108)
+#define ANA_REG_GLB_CHGR_CTRL2          SCI_ADDR(ANA_REGS_GLB_BASE, 0x010C)
+#define ANA_REG_GLB_CHGR_DET_FGU_CTRL   SCI_ADDR(ANA_REGS_GLB_BASE, 0x0110)
+#define ANA_REG_GLB_CHGR_STATUS         SCI_ADDR(ANA_REGS_GLB_BASE, 0x0114)
+#define ANA_REG_GLB_MIXED_CTRL0         SCI_ADDR(ANA_REGS_GLB_BASE, 0x0118)
+#define ANA_REG_GLB_MIXED_CTRL1         SCI_ADDR(ANA_REGS_GLB_BASE, 0x011C)
+#define ANA_REG_GLB_SWRST_CTRL          SCI_ADDR(ANA_REGS_GLB_BASE, 0x0120)
+#define ANA_REG_GLB_POR_RST_MONITOR     SCI_ADDR(ANA_REGS_GLB_BASE, 0x0124)
+#define ANA_REG_GLB_WDG_RST_MONITOR     SCI_ADDR(ANA_REGS_GLB_BASE, 0x0128)
+#define ANA_REG_GLB_POR_PIN_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x012C)
+#define ANA_REG_GLB_POR_SRC_FLAG        SCI_ADDR(ANA_REGS_GLB_BASE, 0x0130)
+#define ANA_REG_GLB_POR_7S_CTRL         SCI_ADDR(ANA_REGS_GLB_BASE, 0x0134)
+#define ANA_REG_GLB_HWRST_RTC           SCI_ADDR(ANA_REGS_GLB_BASE, 0x0138)
+#define ANA_REG_GLB_CHIP_ID_LOW         SCI_ADDR(ANA_REGS_GLB_BASE, 0x013C)
+#define ANA_REG_GLB_CHIP_ID_HIGH        SCI_ADDR(ANA_REGS_GLB_BASE, 0x0140)
+#define ANA_REG_GLB_ARM_MF_REG          SCI_ADDR(ANA_REGS_GLB_BASE, 0x0144)
+#define ANA_REG_GLB_ARCH_EN             SCI_ADDR(ANA_REGS_GLB_BASE, 0x0148)
+#define ANA_REG_GLB_MCU_WR_PROT_VALUE   SCI_ADDR(ANA_REGS_GLB_BASE, 0x014C)
+#define ANA_REG_GLB_PWR_WR_PROT_VALUE   SCI_ADDR(ANA_REGS_GLB_BASE, 0x0150)
+#define ANA_REG_GLB_SMPL_CTRL0          SCI_ADDR(ANA_REGS_GLB_BASE, 0x0154)
+#define ANA_REG_GLB_SMPL_CTRL1          SCI_ADDR(ANA_REGS_GLB_BASE, 0x0158)
+#define ANA_REG_GLB_RTC_RST0            SCI_ADDR(ANA_REGS_GLB_BASE, 0x015C)
+#define ANA_REG_GLB_RTC_RST1            SCI_ADDR(ANA_REGS_GLB_BASE, 0x0160)
+#define ANA_REG_GLB_RTC_RST2            SCI_ADDR(ANA_REGS_GLB_BASE, 0x0164)
+#define ANA_REG_GLB_LDO_SHPT_PD1        SCI_ADDR(ANA_REGS_GLB_BASE, 0x0188)
+#define ANA_REG_GLB_LDO_SHPT_PD2        SCI_ADDR(ANA_REGS_GLB_BASE, 0x018C)
+#define ANA_REG_GLB_BATDET_CUR_CTRL     SCI_ADDR(ANA_REGS_GLB_BASE, 0x0190)
+#define ANA_REG_GLB_RTC_CLK_STOP        SCI_ADDR(ANA_REGS_GLB_BASE, 0x0194)
+#define ANA_REG_GLB_VBAT_DROP_CNT       SCI_ADDR(ANA_REGS_GLB_BASE, 0x0198)
+#define ANA_REG_GLB_DCDC_DISCHRG        SCI_ADDR(ANA_REGS_GLB_BASE, 0x019C)
+#define ANA_REG_GLB_DCDC_CORE_ADI       SCI_ADDR(ANA_REGS_GLB_BASE, 0x0200)
+#define ANA_REG_GLB_DCDC_ARM_ADI        SCI_ADDR(ANA_REGS_GLB_BASE, 0x0204)
+#define ANA_REG_GLB_DCDC_MEM_ADI        SCI_ADDR(ANA_REGS_GLB_BASE, 0x0208)
+#define ANA_REG_GLB_DCDC_GEN_ADI        SCI_ADDR(ANA_REGS_GLB_BASE, 0x020C)
+#define ANA_REG_GLB_DCDC_WPA_ADI        SCI_ADDR(ANA_REGS_GLB_BASE, 0x0210)
+#define ANA_REG_GLB_DCDC_WPA_DCM_ADI    SCI_ADDR(ANA_REGS_GLB_BASE, 0x0214)
+#define ANA_REG_GLB_DCDC_CON_ADI        SCI_ADDR(ANA_REGS_GLB_BASE, 0x0218)
+#define ANA_REG_GLB_DCDC_RF_ADI         SCI_ADDR(ANA_REGS_GLB_BASE, 0x021C)
+
+/* bits definitions for register ANA_REG_GLB_ARM_MODULE_EN */
+#define BIT_ANA_IMPD_ADC_EN             ( BIT(12) )
+#define BIT_ANA_THM_EN                  ( BIT(11) )
+#define BIT_ANA_BLTC_EN                 ( BIT(10) )
+#define BIT_ANA_PINREG_EN               ( BIT(9) )
+#define BIT_ANA_FGU_EN                  ( BIT(8) )
+#define BIT_ANA_EFS_EN                  ( BIT(7) )
+#define BIT_ANA_ADC_EN                  ( BIT(6) )
+#define BIT_ANA_HDT_EN                  ( BIT(5) )
+#define BIT_ANA_AUD_EN                  ( BIT(4) )
+#define BIT_ANA_EIC_EN                  ( BIT(3) )
+#define BIT_ANA_WDG_EN                  ( BIT(2) )
+#define BIT_ANA_RTC_EN                  ( BIT(1) )
+#define BIT_ANA_CAL_EN                  ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_ARM_CLK_EN */
+#define BIT_CLK_IMPD_ADC_EN             ( BIT(10) )
+#define BIT_CLK_AUXAD_EN                ( BIT(9) )
+#define BIT_CLK_AUXADC_EN               ( BIT(8) )
+#define BITS_CLK_CAL_SRC_SEL(_x_)       ( (_x_) << 6 & (BIT(6)|BIT(7)) )
+#define BIT_CLK_CAL_EN                  ( BIT(5) )
+#define BIT_CLK_AUD_HID_EN              ( BIT(4) )
+#define BIT_CLK_AUD_HBD_EN              ( BIT(3) )
+#define BIT_CLK_AUD_LOOP_EN             ( BIT(2) )
+#define BIT_CLK_AUD_6P5M_EN             ( BIT(1) )
+#define BIT_CLK_AUDIF_EN                ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_RTC_CLK_EN */
+#define BIT_RTC_EFS_EN                  ( BIT(12) )
+#define BIT_RTC_THMA_AUTO_EN            ( BIT(11) )
+#define BIT_RTC_THMA_EN                 ( BIT(10) )
+#define BIT_RTC_THM_EN                  ( BIT(9) )
+#define BIT_RTC_BLTC_EN                 ( BIT(8) )
+#define BIT_RTC_FGU_EN                  ( BIT(7) )
+#define BIT_RTC_FGUA_EN                 ( BIT(6) )
+#define BIT_RTC_VIBR_EN                 ( BIT(5) )
+#define BIT_RTC_AUD_EN                  ( BIT(4) )
+#define BIT_RTC_EIC_EN                  ( BIT(3) )
+#define BIT_RTC_WDG_EN                  ( BIT(2) )
+#define BIT_RTC_RTC_EN                  ( BIT(1) )
+#define BIT_RTC_ARCH_EN                 ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_ARM_RST */
+#define BIT_ANA_THMA_SOFT_RST           ( BIT(15) )
+#define BIT_ANA_THM_SOFT_RST            ( BIT(14) )
+#define BIT_ANA_BLTC_SOFT_RST           ( BIT(13) )
+#define BIT_ANA_AUD_32K_SOFT_RST        ( BIT(12) )
+#define BIT_ANA_AUDTX_SOFT_RST          ( BIT(11) )
+#define BIT_ANA_AUDRX_SOFT_RST          ( BIT(10) )
+#define BIT_ANA_AUD_SOFT_RST            ( BIT(9) )
+#define BIT_ANA_AUD_HDT_SOFT_RST        ( BIT(8) )
+#define BIT_ANA_EFS_SOFT_RST            ( BIT(7) )
+#define BIT_ANA_ADC_SOFT_RST            ( BIT(6) )
+#define BIT_ANA_PWM0_SOFT_RST           ( BIT(5) )
+#define BIT_ANA_FGU_SOFT_RST            ( BIT(4) )
+#define BIT_ANA_EIC_SOFT_RST            ( BIT(3) )
+#define BIT_ANA_WDG_SOFT_RST            ( BIT(2) )
+#define BIT_ANA_RTC_SOFT_RST            ( BIT(1) )
+#define BIT_ANA_CAL_SOFT_RST            ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_LDO_DCDC_PD */
+#define BIT_LDO_EMM_PD                  ( BIT(15) )
+#define BIT_DCDC_TOPCLK6M_PD            ( BIT(14) )
+#define BIT_DCDC_RF_PD                  ( BIT(13) )
+#define BIT_DCDC_GEN_PD                 ( BIT(12) )
+#define BIT_DCDC_MEM_PD                 ( BIT(11) )
+#define BIT_DCDC_ARM_PD                 ( BIT(10) )
+#define BIT_DCDC_CORE_PD                ( BIT(9) )
+#define BIT_LDO_RF0_PD                  ( BIT(8) )
+#define BIT_LDO_EMMCCORE_PD             ( BIT(7) )
+#define BIT_LDO_GEN1_PD                 ( BIT(6) )
+#define BIT_LDO_DCXO_PD                 ( BIT(5) )
+#define BIT_LDO_GEN0_PD                 ( BIT(4) )
+#define BIT_LDO_VDD25_PD                ( BIT(3) )
+#define BIT_LDO_VDD28_PD                ( BIT(2) )
+#define BIT_LDO_VDD18_PD                ( BIT(1) )
+#define BIT_BG_PD                       ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_LDO_PD_CTRL */
+#define BIT_LDO_LPREF_PD_SW             ( BIT(15) )
+#define BIT_DCDC_WPA_PD                 ( BIT(14) )
+#define BIT_DCDC_CON_PD                 ( BIT(13) )
+#define BIT_LDO_WIFIPA_PD               ( BIT(11) )
+#define BIT_LDO_SDCORE_PD               ( BIT(10) )
+#define BIT_LDO_USB_PD                  ( BIT(8) )
+#define BIT_LDO_CAMMOT_PD               ( BIT(7) )
+#define BIT_LDO_CAMIO_PD                ( BIT(6) )
+#define BIT_LDO_CAMD_PD                 ( BIT(5) )
+#define BIT_LDO_CAMA_PD                 ( BIT(4) )
+#define BIT_LDO_SIM2_PD                 ( BIT(3) )
+#define BIT_LDO_SIM1_PD                 ( BIT(2) )
+#define BIT_LDO_SIM0_PD                 ( BIT(1) )
+#define BIT_LDO_SDIO_PD                 ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL0 */
+#define BITS_LDO_RF0_V(_x_)             ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_LDO_WIFIPA_V(_x_)          ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL1 */
+#define BITS_LDO_CAMIO_V(_x_)           ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_LDO_CAMD_V(_x_)            ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) )
+
+/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL2 */
+#define BITS_LDO_GEN0_V(_x_)            ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) )
+
+/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL3 */
+#define BITS_LDO_GEN1_V(_x_)            ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_LDO_VDD28_V(_x_)           ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL4 */
+#define BITS_LDO_SIM0_V(_x_)            ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_LDO_SDIO_V(_x_)            ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL5 */
+#define BITS_LDO_SIM2_V(_x_)            ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_LDO_SIM1_V(_x_)            ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL6 */
+#define BITS_LDO_SDCORE_V(_x_)          ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_LDO_CAMA_V(_x_)            ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL7 */
+#define BITS_LDO_EMMCCORE_V(_x_)        ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_LDO_CAMMOT_V(_x_)          ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL8 */
+#define BITS_LDO_DCXO_V(_x_)            ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_LDO_DCXO_LP_V(_x_)         ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL9 */
+#define BITS_LDO_VDD18_V(_x_)           ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_LDO_USB_V(_x_)             ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL10 */
+#define BITS_LDO_VDD25_V(_x_)           ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register ANA_REG_GLB_LDO_V_CTRL11 */
+#define BITS_VBATBK_V(_x_)              ( (_x_) << 12 & (BIT(12)|BIT(13)) )
+#define BITS_LDOB_CAL_SEL(_x_)          ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)) )
+#define BITS_LDOA_CAL_SEL                   (_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_LDOD_CAL_SEL(_x_)          ( (_x_) << 3 & (BIT(3)|BIT(4)) )
+#define BITS_LDODCDC_CAL_SEL(_x_)       ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) )
+
+/* bits definitions for register ANA_REG_GLB_LDO_LP_CTRL */
+#define BITS_LDOB_LP_CAL(_x_)           ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_LDOA_LP_CAL(_x_)           ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_LDODCDC_LP_CAL(_x_)        ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_CTRL0 */
+#define BITS_DCDC_CORE_DEADTIME(_x_)    ( (_x_) << 14 & (BIT(14)|BIT(15)) )
+#define BITS_DCDC_CORE_STBOP(_x_)       ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
+#define BITS_DCDC_CORE_PDRSLOW(_x_)     ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_DCDC_CORE_QKRSPS            ( BIT(3) )
+#define BIT_DCDC_CORE_PFM               ( BIT(2) )
+#define BIT_DCDC_CORE_DCM               ( BIT(1) )
+#define BIT_DCDC_CORE_LP_EN             ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_CTRL1 */
+#define BITS_DCDC_MEM_DEADTIME(_x_)     ( (_x_) << 14 & (BIT(14)|BIT(15)) )
+#define BITS_DCDC_MEM_STBOP(_x_)        ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
+#define BITS_DCDC_MEM_PDRSLOW(_x_)      ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_DCDC_MEM_QKRSPS             ( BIT(3) )
+#define BIT_DCDC_MEM_PFM                ( BIT(2) )
+#define BIT_DCDC_MEM_DCM                ( BIT(1) )
+#define BIT_DCDC_MEM_LP_EN              ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_CTRL2 */
+#define BITS_DCDC_GEN_DEADTIME(_x_)     ( (_x_) << 14 & (BIT(14)|BIT(15)) )
+#define BITS_DCDC_GEN_STBOP(_x_)        ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
+#define BITS_DCDC_GEN_PDRSLOW(_x_)      ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_DCDC_GEN_QKRSPS             ( BIT(3) )
+#define BIT_DCDC_GEN_PFM                ( BIT(2) )
+#define BIT_DCDC_GEN_DCM                ( BIT(1) )
+#define BIT_DCDC_GEN_LP_EN              ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_CTRL3 */
+#define BITS_DCDC_ARM_DEADTIME(_x_)     ( (_x_) << 14 & (BIT(14)|BIT(15)) )
+#define BITS_DCDC_ARM_STBOP(_x_)        ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
+#define BITS_DCDC_ARM_PDRSLOW(_x_)      ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_DCDC_ARM_QKRSPS             ( BIT(3) )
+#define BIT_DCDC_ARM_PFM                ( BIT(2) )
+#define BIT_DCDC_ARM_DCM                ( BIT(1) )
+#define BIT_DCDC_ARM_LP_EN              ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_CTRL4 */
+#define BITS_DCDC_WPA_DEADTIME(_x_)     ( (_x_) << 14 & (BIT(14)|BIT(15)) )
+#define BITS_DCDC_WPA_STBOP(_x_)        ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
+#define BITS_DCDC_WPA_PDRSLOW(_x_)      ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_DCDC_WPA_QKRSPS             ( BIT(3) )
+#define BIT_DCDC_WPA_PFM                ( BIT(2) )
+#define BIT_DCDC_WPA_LP_EN              ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_CTRL5 */
+#define BITS_DCDC_RF_DEADTIME(_x_)      ( (_x_) << 14 & (BIT(14)|BIT(15)) )
+#define BITS_DCDC_RF_STBOP(_x_)         ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
+#define BITS_DCDC_RF_PDRSLOW(_x_)       ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_DCDC_RF_QKRSPS              ( BIT(3) )
+#define BIT_DCDC_RF_PFM                 ( BIT(2) )
+#define BIT_DCDC_RF_DCM                 ( BIT(1) )
+#define BIT_DCDC_RF_LP_EN               ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_CTRL6 */
+#define BITS_DCDC_CON_DEADTIME(_x_)     ( (_x_) << 14 & (BIT(14)|BIT(15)) )
+#define BITS_DCDC_CON_STBOP(_x_)        ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
+#define BITS_DCDC_CON_PDRSLOW(_x_)      ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_DCDC_CON_QKRSPS             ( BIT(3) )
+#define BIT_DCDC_CON_PFM                ( BIT(2) )
+#define BIT_DCDC_CON_DCM                ( BIT(1) )
+#define BIT_DCDC_CON_LP_EN              ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_CTRL7 */
+#define BITS_DCDC_MEM_CF(_x_)           ( (_x_) << 12 & (BIT(12)|BIT(13)) )
+#define BITS_DCDC_MEM_PFMAD(_x_)        ( (_x_) << 10 & (BIT(10)|BIT(11)) )
+#define BITS_DCDC_MEM_CL_CTRL(_x_)      ( (_x_) << 8 & (BIT(8)|BIT(9)) )
+#define BIT_DCDC_CORE_DUALSEL           ( BIT(7) )
+#define BIT_DCDC_CORE_MERGEEN           ( BIT(6) )
+#define BITS_DCDC_CORE_CF(_x_)          ( (_x_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_DCDC_CORE_PFMAD(_x_)       ( (_x_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_DCDC_CORE_CL_CTRL(_x_)     ( (_x_) << 0 & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_CTRL8 */
+#define BIT_DCDC_ARM_DUALSEL            ( BIT(15) )
+#define BIT_DCDC_ARM_MERGEEN            ( BIT(14) )
+#define BITS_DCDC_ARM_CF(_x_)           ( (_x_) << 12 & (BIT(12)|BIT(13)) )
+#define BITS_DCDC_ARM_PFMAD(_x_)        ( (_x_) << 10 & (BIT(10)|BIT(11)) )
+#define BITS_DCDC_ARM_CL_CTRL(_x_)      ( (_x_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_DCDC_GEN_CF(_x_)           ( (_x_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_DCDC_GEN_PFMAD(_x_)        ( (_x_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_DCDC_GEN_CL_CTRL(_x_)      ( (_x_) << 0 & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_CTRL9 */
+#define BIT_DCDC_CON_MERGEEN            ( BIT(14) )
+#define BITS_DCDC_CON_CF(_x_)           ( (_x_) << 12 & (BIT(12)|BIT(13)) )
+#define BITS_DCDC_CON_PFMAD(_x_)        ( (_x_) << 10 & (BIT(10)|BIT(11)) )
+#define BITS_DCDC_CON_CL_CTRL(_x_)      ( (_x_) << 8 & (BIT(8)|BIT(9)) )
+#define BIT_DCDC_RF_MERGEEN             ( BIT(6) )
+#define BITS_DCDC_RF_CF(_x_)            ( (_x_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_DCDC_RF_PFMAD(_x_)         ( (_x_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_DCDC_RF_CL_CTRL(_x_)       ( (_x_) << 0 & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_CTRL10 */
+#define BIT_DCDC_WPA_BPOUT_SOFTW        ( BIT(15) )
+#define BITS_DCDC_WPA_VBAT_DIV(_x_)     ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)) )
+#define BIT_DCDC_WPA_BPEN               ( BIT(11) )
+#define BIT_DCDC_WPA_BPMODE             ( BIT(10) )
+#define BIT_DCDC_WPA_DEGEN              ( BIT(9) )
+#define BIT_DCDC_WPA_APTEN              ( BIT(8) )
+#define BITS_DCDC_WPA_DEBC_SEL(_x_)     ( (_x_) << 6 & (BIT(6)|BIT(7)) )
+#define BITS_DCDC_WPA_CF(_x_)           ( (_x_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_DCDC_WPA_PFMAD(_x_)        ( (_x_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_DCDC_WPA_CL_CTRL(_x_)      ( (_x_) << 0 & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_CTRL11 */
+#define BIT_DCDC_3MCLKCAL_EN            ( BIT(13) )
+#define BIT_DCDC_2MCLKCAL_EN            ( BIT(12) )
+#define BITS_DCDC_6MFRECAL_SW(_x_)      ( (_x_) << 7 & (BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DCDC_4MFRECAL_SW(_x_)      ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) )
+#define BIT_DCDC_CLK_SP_SEL             ( BIT(1) )
+#define BIT_DCDC_CLK_SP_EN              ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_CTRL12 */
+#define BIT_DCDC_CORE_OSCSYCEN_SW       ( BIT(15) )
+#define BIT_DCDC_CORE_OSCSYCEN_HW_EN    ( BIT(14) )
+#define BIT_DCDC_CORE_OSCSYC_DIV_EN     ( BIT(13) )
+#define BITS_DCDC_CORE_OSCSYC_DIV(_x_)  ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
+#define BIT_DCDC_ARM_OSCSYCEN_SW        ( BIT(7) )
+#define BIT_DCDC_ARM_OSCSYCEN_HW_EN     ( BIT(6) )
+#define BIT_DCDC_ARM_OSCSYC_DIV_EN      ( BIT(5) )
+#define BITS_DCDC_ARM_OSCSYC_DIV(_x_)   ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_CTRL13 */
+#define BIT_DCDC_MEM_OSCSYCEN_SW        ( BIT(15) )
+#define BIT_DCDC_MEM_OSCSYCEN_HW_EN     ( BIT(14) )
+#define BIT_DCDC_MEM_OSCSYC_DIV_EN      ( BIT(13) )
+#define BITS_DCDC_MEM_OSCSYC_DIV(_x_)   ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
+#define BIT_DCDC_GEN_OSCSYCEN_SW        ( BIT(7) )
+#define BIT_DCDC_GEN_OSCSYCEN_HW_EN     ( BIT(6) )
+#define BIT_DCDC_GEN_OSCSYC_DIV_EN      ( BIT(5) )
+#define BITS_DCDC_GEN_OSCSYC_DIV(_x_)   ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_CTRL14 */
+#define BIT_DCDC_WPA_OSCSYCEN_SW        ( BIT(15) )
+#define BIT_DCDC_WPA_OSCSYCEN_HW_EN     ( BIT(14) )
+#define BIT_DCDC_WPA_OSCSYC_DIV_EN      ( BIT(13) )
+#define BITS_DCDC_WPA_OSCSYC_DIV(_x_)   ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
+#define BIT_DCDC_RF_OSCSYCEN_SW         ( BIT(7) )
+#define BIT_DCDC_RF_OSCSYCEN_HW_EN      ( BIT(6) )
+#define BIT_DCDC_RF_OSCSYC_DIV_EN       ( BIT(5) )
+#define BITS_DCDC_RF_OSCSYC_DIV(_x_)    ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_CTRL15 */
+#define BITS_DCDC_CAL_SEL(_x_)          ( (_x_) << 13 & (BIT(13)|BIT(14)|BIT(15)) )
+#define BIT_DCDC_CON_OSCSYCEN_SW        ( BIT(7) )
+#define BIT_DCDC_CON_OSCSYCEN_HW_EN     ( BIT(6) )
+#define BIT_DCDC_CON_OSCSYC_DIV_EN      ( BIT(5) )
+#define BITS_DCDC_CON_OSCSYC_DIV(_x_)   ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register ANA_REG_GLB_SLP_WAIT_DCDCARM */
+#define BITS_SLP_IN_WAIT_DCDCARM(_x_)   ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_SLP_OUT_WAIT_DCDCARM(_x_)  ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL0 */
+#define BIT_SLP_IO_EN                   ( BIT(15) )
+#define BIT_SLP_DCDCRF_PD_EN            ( BIT(13) )
+#define BIT_SLP_DCDCCON_PD_EN           ( BIT(12) )
+#define BIT_SLP_DCDCGEN_PD_EN           ( BIT(11) )
+#define BIT_SLP_DCDCWPA_PD_EN           ( BIT(10) )
+#define BIT_SLP_DCDCARM_PD_EN           ( BIT(9) )
+#define BIT_SLP_LDOVDD25_PD_EN          ( BIT(8) )
+#define BIT_SLP_LDORF0_PD_EN            ( BIT(7) )
+#define BIT_SLP_LDOEMMCCORE_PD_EN       ( BIT(6) )
+#define BIT_SLP_LDOGEN0_PD_EN           ( BIT(5) )
+#define BIT_SLP_LDODCXO_PD_EN           ( BIT(4) )
+#define BIT_SLP_LDOGEN1_PD_EN           ( BIT(3) )
+#define BIT_SLP_LDOWIFIPA_PD_EN         ( BIT(2) )
+#define BIT_SLP_LDOVDD28_PD_EN          ( BIT(1) )
+#define BIT_SLP_LDOVDD18_PD_EN          ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL1 */
+#define BIT_SLP_LDO_PD_EN               ( BIT(15) )
+#define BIT_SLP_LDOLPREF_PD_EN          ( BIT(14) )
+#define BIT_SLP_LDOSDCORE_PD_EN         ( BIT(9) )
+#define BIT_SLP_LDOUSB_PD_EN            ( BIT(8) )
+#define BIT_SLP_LDOCAMMOT_PD_EN         ( BIT(7) )
+#define BIT_SLP_LDOCAMIO_PD_EN          ( BIT(6) )
+#define BIT_SLP_LDOCAMD_PD_EN           ( BIT(5) )
+#define BIT_SLP_LDOCAMA_PD_EN           ( BIT(4) )
+#define BIT_SLP_LDOSIM2_PD_EN           ( BIT(3) )
+#define BIT_SLP_LDOSIM1_PD_EN           ( BIT(2) )
+#define BIT_SLP_LDOSIM0_PD_EN           ( BIT(1) )
+#define BIT_SLP_LDOSDIO_PD_EN           ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL2 */
+#define BIT_SLP_DCDCRF_LP_EN            ( BIT(14) )
+#define BIT_SLP_DCDCCON_LP_EN           ( BIT(13) )
+#define BIT_SLP_DCDCCORE_LP_EN          ( BIT(12) )
+#define BIT_SLP_DCDCMEM_LP_EN           ( BIT(11) )
+#define BIT_SLP_DCDCARM_LP_EN           ( BIT(10) )
+#define BIT_SLP_DCDCGEN_LP_EN           ( BIT(9) )
+#define BIT_SLP_DCDCWPA_LP_EN           ( BIT(8) )
+#define BIT_SLP_LDORF0_LP_EN            ( BIT(7) )
+#define BIT_SLP_LDOEMMCCORE_LP_EN       ( BIT(6) )
+#define BIT_SLP_LDOGEN0_LP_EN           ( BIT(5) )
+#define BIT_SLP_LDODCXO_LP_EN           ( BIT(4) )
+#define BIT_SLP_LDOGEN1_LP_EN           ( BIT(3) )
+#define BIT_SLP_LDOWIFIPA_LP_EN         ( BIT(2) )
+#define BIT_SLP_LDOVDD28_LP_EN          ( BIT(1) )
+#define BIT_SLP_LDOVDD18_LP_EN          ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL3 */
+#define BIT_SLP_BG_LP_EN                ( BIT(15) )
+#define BIT_LDOVDD25_LP_EN_SW           ( BIT(14) )
+#define BIT_LDOSDCORE_LP_EN_SW          ( BIT(13) )
+#define BIT_LDOUSB_LP_EN_SW             ( BIT(12) )
+#define BIT_SLP_LDOVDD25_LP_EN          ( BIT(10) )
+#define BIT_SLP_LDOSDCORE_LP_EN         ( BIT(9) )
+#define BIT_SLP_LDOUSB_LP_EN            ( BIT(8) )
+#define BIT_SLP_LDOCAMMOT_LP_EN         ( BIT(7) )
+#define BIT_SLP_LDOCAMIO_LP_EN          ( BIT(6) )
+#define BIT_SLP_LDOCAMD_LP_EN           ( BIT(5) )
+#define BIT_SLP_LDOCAMA_LP_EN           ( BIT(4) )
+#define BIT_SLP_LDOSIM2_LP_EN           ( BIT(3) )
+#define BIT_SLP_LDOSIM1_LP_EN           ( BIT(2) )
+#define BIT_SLP_LDOSIM0_LP_EN           ( BIT(1) )
+#define BIT_SLP_LDOSDIO_LP_EN           ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_PWR_SLP_CTRL4 */
+#define BIT_LDOCAMIO_LP_EN_SW           ( BIT(15) )
+#define BIT_LDOCAMMOT_LP_EN_SW          ( BIT(14) )
+#define BIT_LDOCAMD_LP_EN_SW            ( BIT(13) )
+#define BIT_LDOCAMA_LP_EN_SW            ( BIT(12) )
+#define BIT_LDOSIM2_LP_EN_SW            ( BIT(11) )
+#define BIT_LDOSIM1_LP_EN_SW            ( BIT(10) )
+#define BIT_LDOSIM0_LP_EN_SW            ( BIT(9) )
+#define BIT_LDOSDIO_LP_EN_SW            ( BIT(8) )
+#define BIT_LDORF0_LP_EN_SW             ( BIT(7) )
+#define BIT_LDOEMMCCORE_LP_EN_SW        ( BIT(6) )
+#define BIT_LDOGEN0_LP_EN_SW            ( BIT(5) )
+#define BIT_LDODCXO_LP_EN_SW            ( BIT(4) )
+#define BIT_LDOGEN1_LP_EN_SW            ( BIT(3) )
+#define BIT_LDOWIFIPA_LP_EN_SW          ( BIT(2) )
+#define BIT_LDOVDD28_LP_EN_SW           ( BIT(1) )
+#define BIT_LDOVDD18_LP_EN_SW           ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_AUD_SLP_CTRL */
+#define BIT_SLP_AUD_PMUR1_PD_EN         ( BIT(14) )
+#define BIT_SLP_AUD_PA_SW_PD_EN         ( BIT(13) )
+#define BIT_SLP_AUD_PA_LDO_PD_EN        ( BIT(12) )
+#define BIT_SLP_AUD_PA_PD_EN            ( BIT(11) )
+#define BIT_SLP_AUD_OVP_PD_PD_EN        ( BIT(10) )
+#define BIT_SLP_AUD_OVP_LDO_PD_EN       ( BIT(9) )
+#define BIT_SLP_AUD_LDOCG_PD_PD_EN      ( BIT(8) )
+#define BIT_SLP_AUD_VB_PD_EN            ( BIT(7) )
+#define BIT_SLP_AUD_VBO_PD_EN           ( BIT(6) )
+#define BIT_SLP_AUD_HEADMICBIAS_PD_EN   ( BIT(5) )
+#define BIT_SLP_AUD_HEADMIC_SLEEP_PD_EN ( BIT(4) )
+#define BIT_SLP_AUD_PLGPD_PD_EN         ( BIT(3) )
+#define BIT_SLP_AUD_VB_NLEAK_PD         ( BIT(2) )
+#define BITS_SLP_AUD_PMUR0_PD_EN(_x_)   ( (_x_) << 0 & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL0 */
+#define BITS_SLP_DCDCCORE_VOL_DROP_CNT(_x_)( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BIT_PWR_OFF_SEQ_EN              ( BIT(2) )
+#define BIT_DCDC_CORE_SLP_OUT_STEP_EN   ( BIT(1) )
+#define BIT_DCDC_CORE_SLP_IN_STEP_EN    ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL1 */
+#define BITS_DCDC_CORE_CAL_DS_SW(_x_)   ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_DCDC_CORE_CTRL_DS_SW(_x_)  ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL2 */
+#define BITS_DCDC_CORE_CTRL_SLP_STEP3(_x_)( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_DCDC_CORE_CTRL_SLP_STEP2(_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_DCDC_CORE_CTRL_SLP_STEP1(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL3 */
+#define BITS_DCDC_CORE_CTRL_SLP_STEP5(_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_DCDC_CORE_CTRL_SLP_STEP4(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL4 */
+#define BITS_DCDC_CORE_CAL_SLP_STEP3(_x_)( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_DCDC_CORE_CAL_SLP_STEP2(_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_DCDC_CORE_CAL_SLP_STEP1(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL5 */
+#define BITS_DCDC_CORE_CAL_SLP_STEP5(_x_)( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_DCDC_CORE_CAL_SLP_STEP4(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register ANA_REG_GLB_PWR_SEL */
+#define BIT_LDO_GEN0_SW_SEL             ( BIT(13) )
+#define BIT_LDO_GEN1_SW_SEL             ( BIT(12) )
+#define BIT_LDO_RF0_SW_SEL              ( BIT(11) )
+#define BIT_LDO_VDD18_SW_SEL            ( BIT(10) )
+#define BIT_LDO_VDD28_SW_SEL            ( BIT(9) )
+#define BIT_LDO_DCXO_SW_SEL             ( BIT(8) )
+#define BIT_LDO_EMMCCORE_SW_SEL         ( BIT(7) )
+#define BIT_LDO_VDD25_SW_SEL            ( BIT(6) )
+#define BIT_DCDC_RF_SW_SEL              ( BIT(5) )
+#define BIT_DCDC_GEN_SW_SEL             ( BIT(4) )
+#define BIT_DCDC_MEM_SW_SEL             ( BIT(3) )
+#define BIT_DCDC_ARM_SW_SEL             ( BIT(2) )
+#define BIT_DCDC_CORE_SLP_SW_SEL        ( BIT(1) )
+#define BIT_DCDC_CORE_NOR_SW_SEL        ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN0 */
+#define BIT_LDO_XTL_EN                  ( BIT(15) )
+#define BIT_LDO_GEN0_EXT_XTL0_EN        ( BIT(14) )
+#define BIT_LDO_GEN0_XTL1_EN            ( BIT(13) )
+#define BIT_LDO_GEN0_XTL0_EN            ( BIT(12) )
+#define BIT_LDO_GEN1_EXT_XTL0_EN        ( BIT(11) )
+#define BIT_LDO_GEN1_XTL1_EN            ( BIT(10) )
+#define BIT_LDO_GEN1_XTL0_EN            ( BIT(9) )
+#define BIT_LDO_DCXO_EXT_XTL0_EN        ( BIT(8) )
+#define BIT_LDO_DCXO_XTL1_EN            ( BIT(7) )
+#define BIT_LDO_DCXO_XTL0_EN            ( BIT(6) )
+#define BIT_LDO_VDD18_EXT_XTL0_EN       ( BIT(5) )
+#define BIT_LDO_VDD18_XTL1_EN           ( BIT(4) )
+#define BIT_LDO_VDD18_XTL0_EN           ( BIT(3) )
+#define BIT_LDO_VDD28_EXT_XTL0_EN       ( BIT(2) )
+#define BIT_LDO_VDD28_XTL1_EN           ( BIT(1) )
+#define BIT_LDO_VDD28_XTL0_EN           ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN1 */
+#define BIT_LDO_RF0_EXT_XTL0_EN         ( BIT(14) )
+#define BIT_LDO_RF0_XTL1_EN             ( BIT(13) )
+#define BIT_LDO_RF0_XTL0_EN             ( BIT(12) )
+#define BIT_LDO_WIFIPA_EXT_XTL0_EN      ( BIT(11) )
+#define BIT_LDO_WIFIPA_XTL1_EN          ( BIT(10) )
+#define BIT_LDO_WIFIPA_XTL0_EN          ( BIT(9) )
+#define BIT_LDO_SIM2_EXT_XTL0_EN        ( BIT(8) )
+#define BIT_LDO_SIM2_XTL1_EN            ( BIT(7) )
+#define BIT_LDO_SIM2_XTL0_EN            ( BIT(6) )
+#define BIT_LDO_SIM1_EXT_XTL0_EN        ( BIT(5) )
+#define BIT_LDO_SIM1_XTL1_EN            ( BIT(4) )
+#define BIT_LDO_SIM1_XTL0_EN            ( BIT(3) )
+#define BIT_LDO_SIM0_EXT_XTL0_EN        ( BIT(2) )
+#define BIT_LDO_SIM0_XTL1_EN            ( BIT(1) )
+#define BIT_LDO_SIM0_XTL0_EN            ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN2 */
+#define BIT_LDO_VDD25_EXT_XTL0_EN       ( BIT(11) )
+#define BIT_LDO_VDD25_XTL1_EN           ( BIT(10) )
+#define BIT_LDO_VDD25_XTL0_EN           ( BIT(9) )
+#define BIT_DCDC_RF_EXT_XTL0_EN         ( BIT(8) )
+#define BIT_DCDC_RF_XTL1_EN             ( BIT(7) )
+#define BIT_DCDC_RF_XTL0_EN             ( BIT(6) )
+#define BIT_XO_EXT_XTL0_EN              ( BIT(5) )
+#define BIT_XO_XTL1_EN                  ( BIT(4) )
+#define BIT_XO_XTL0_EN                  ( BIT(3) )
+#define BIT_BG_EXT_XTL0_EN              ( BIT(2) )
+#define BIT_BG_XTL1_EN                  ( BIT(1) )
+#define BIT_BG_XTL0_EN                  ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_PWR_XTL_EN3 */
+#define BIT_DCDC_CON_EXT_XTL0_EN        ( BIT(14) )
+#define BIT_DCDC_CON_XTL1_EN            ( BIT(13) )
+#define BIT_DCDC_CON_XTL0_EN            ( BIT(12) )
+#define BIT_DCDC_WPA_EXT_XTL0_EN        ( BIT(11) )
+#define BIT_DCDC_WPA_XTL1_EN            ( BIT(10) )
+#define BIT_DCDC_WPA_XTL0_EN            ( BIT(9) )
+#define BIT_DCDC_MEM_EXT_XTL0_EN        ( BIT(8) )
+#define BIT_DCDC_MEM_XTL1_EN            ( BIT(7) )
+#define BIT_DCDC_MEM_XTL0_EN            ( BIT(6) )
+#define BIT_DCDC_GEN_EXT_XTL0_EN        ( BIT(5) )
+#define BIT_DCDC_GEN_XTL1_EN            ( BIT(4) )
+#define BIT_DCDC_GEN_XTL0_EN            ( BIT(3) )
+#define BIT_DCDC_CORE_EXT_XTL0_EN       ( BIT(2) )
+#define BIT_DCDC_CORE_XTL1_EN           ( BIT(1) )
+#define BIT_DCDC_CORE_XTL0_EN           ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_32KLESS_CTRL0 */
+#define BIT_RC_MODE_WR_ACK_FLAG         ( BIT(14) )
+#define BIT_XO_LOW_CUR_FLAG             ( BIT(13) )
+#define BIT_XO_LOW_CUR_FRC_RTCSET       ( BIT(12) )
+#define BIT_XO_LOW_CUR_FRC_RTCCLR       ( BIT(11) )
+#define BIT_RC_MODE_WR_ACK_FLAG_CLR     ( BIT(10) )
+#define BIT_XO_LOW_CUR_FLAG_CLR         ( BIT(9) )
+#define BIT_XO_LOW_CUR_CNT_CLR          ( BIT(8) )
+#define BIT_LDO_DCXO_LP_PD_RTCSET       ( BIT(7) )
+#define BIT_LDO_DCXO_LP_PD_RTCCLR       ( BIT(6) )
+#define BIT_SLP_XO_LOW_CUR_EN           ( BIT(5) )
+#define BIT_XO_LOW_CUR_EN               ( BIT(3) )
+#define BIT_EXT_32K_PD                  ( BIT(2) )
+#define BIT_RC_32K_SEL                  ( BIT(1) )
+#define BIT_RC_32K_EN                   ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_32KLESS_CTRL1 */
+#define BITS_RC_MODE(_x_)               ( (_x_) << 0 )
+
+/* bits definitions for register ANA_REG_GLB_32KLESS_CTRL2 */
+#define BITS_XO_LOW_CUR_CNT_LOW(_x_)    ( (_x_) << 0 )
+
+/* bits definitions for register ANA_REG_GLB_32KLESS_CTRL3 */
+#define BITS_XO_LOW_CUR_CNT_HIGH(_x_)   ( (_x_) << 0 )
+
+/* bits definitions for register ANA_REG_GLB_AUXAD_CTL */
+#define BIT_AUXAD_CURRENTSEN_EN         ( BIT(6) )
+#define BIT_AUXAD_CURRENTSEL            ( BIT(5) )
+#define BITS_AUXAD_CURRENT_IBS(_x_)     ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register ANA_REG_GLB_XTL_WAIT_CTRL */
+#define BIT_SLP_XTLBUF_PD_EN            ( BIT(9) )
+#define BIT_XTL_EN                      ( BIT(8) )
+#define BITS_XTL_WAIT(_x_)              ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register ANA_REG_GLB_RGB_CTRL */
+#define BIT_RTC_PWM0_EN                 ( BIT(15) )
+#define BIT_PWM0_EN                     ( BIT(14) )
+#define BIT_IB_REX_EN                   ( BIT(12) )
+#define BIT_IB_TRIM_EM_SEL              ( BIT(11) )
+#define BITS_RGB_V(_x_)                 ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) )
+#define BIT_SLP_RGB_PD_EN               ( BIT(2) )
+#define BIT_RGB_PD_HW_EN                ( BIT(1) )
+#define BIT_RGB_PD_SW                   ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_WHTLED_CTRL */
+#define BITS_IB_TRIM(_x_)               ( (_x_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BIT_WHTLED_SERIES_EN            ( BIT(8) )
+#define BIT_WHTLED_PD_SEL               ( BIT(7) )
+#define BITS_WHTLED_V(_x_)              ( (_x_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) )
+#define BIT_WHTLED_PD                   ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_KPLED_CTRL */
+#define BITS_KPLED_V(_x_)               ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BIT_KPLED_PD                    ( BIT(11) )
+#define BIT_KPLED_PULLDOWN_EN           ( BIT(10) )
+#define BIT_SLP_LDOKPLED_PD_EN          ( BIT(9) )
+#define BIT_LDO_KPLED_PD                ( BIT(8) )
+#define BITS_LDO_KPLED_V(_x_)           ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register ANA_REG_GLB_VIBR_CTRL0 */
+#define BITS_CUR_DRV_CAL_SEL(_x_)       ( (_x_) << 12 & (BIT(12)|BIT(13)) )
+#define BIT_VIBR_PULLDOWN_EN            ( BIT(11) )
+#define BIT_VIBR_PULLUP_EN              ( BIT(10) )
+#define BIT_SLP_LDOVIBR_PD_EN           ( BIT(9) )
+#define BIT_LDO_VIBR_PD                 ( BIT(8) )
+#define BITS_LDO_VIBR_V(_x_)            ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register ANA_REG_GLB_AUDIO_CTRL0 */
+#define BIT_AUD_SLP_APP_RST_EN          ( BIT(15) )
+#define BITS_CLK_AUD_HBD_DIV(_x_)       ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
+#define BIT_CLK_AUD_LOOP_INV_EN         ( BIT(4) )
+#define BIT_CLK_AUDIF_TX_INV_EN         ( BIT(3) )
+#define BIT_CLK_AUDIF_RX_INV_EN         ( BIT(2) )
+#define BIT_CLK_AUD_6P5M_TX_INV_EN      ( BIT(1) )
+#define BIT_CLK_AUD_6P5M_RX_INV_EN      ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_AUDIO_CTRL1 */
+#define BIT_IMPD_ADC_SOFT_RST           ( BIT(7) )
+#define BIT_HEAD_INSERT_EIC_EN          ( BIT(6) )
+#define BIT_AUDIO_CHP_CLK_DIV_EN        ( BIT(5) )
+#define BITS_AUDIO_CHP_CLK_DIV(_x_)     ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register ANA_REG_GLB_CHGR_CTRL0 */
+#define BIT_CHGLDO_DIS                  ( BIT(15) )
+#define BITS_CHGR_CV_V(_x_)             ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_CHGR_END_V(_x_)            ( (_x_) << 4 & (BIT(4)|BIT(5)) )
+#define BIT_CHGR_PD                     ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_CHGR_CTRL1 */
+#define BITS_CHGR_CC_I(_x_)             ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_VBAT_OVP_V(_x_)            ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_VCHG_OVP_V(_x_)            ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+
+/* bits definitions for register ANA_REG_GLB_CHGR_CTRL2 */
+#define BIT_CHGR_INT_EN                 ( BIT(15) )
+#define BIT_CHGR_DRV                    ( BIT(7) )
+#define BIT_CHGR_OSC                    ( BIT(6) )
+#define BITS_CHGR_DPM(_x_)              ( (_x_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_CHGR_ITERM(_x_)            ( (_x_) << 2 & (BIT(2)|BIT(3)) )
+#define BIT_CHGR_CC_EN                  ( BIT(1) )
+#define BIT_RECHG                       ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_CHGR_DET_FGU_CTRL */
+#define BIT_FGUA_SOFT_RST               ( BIT(13) )
+#define BIT_LDO_FGU_PD                  ( BIT(12) )
+#define BIT_SD_CHOP_CAP_EN              ( BIT(8) )
+#define BITS_SD_CLK_P(_x_)              ( (_x_) << 6 & (BIT(6)|BIT(7)) )
+#define BIT_SD_DCOFFSET_EN              ( BIT(5) )
+#define BIT_SD_CHOP_EN                  ( BIT(4) )
+#define BIT_DP_DM_AUX_EN                ( BIT(1) )
+#define BIT_DP_DM_SW_EN                 ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_CHGR_STATUS */
+#define BIT_CHG_DET_DONE                ( BIT(11) )
+#define BIT_DP_LOW                      ( BIT(10) )
+#define BIT_DCP_DET                     ( BIT(9) )
+#define BIT_CHG_DET                     ( BIT(8) )
+#define BIT_SDP_INT                     ( BIT(7) )
+#define BIT_DCP_INT                     ( BIT(6) )
+#define BIT_CDP_INT                     ( BIT(5) )
+#define BIT_CHGR_CV_STATUS              ( BIT(4) )
+#define BIT_CHGR_ON                     ( BIT(3) )
+#define BIT_CHGR_INT                    ( BIT(2) )
+#define BIT_VBAT_OVI                    ( BIT(1) )
+#define BIT_VCHG_OVI                    ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_MIXED_CTRL0 */
+#define BIT_PTEST_PD_RTCSET             ( BIT(15) )
+#define BIT_DCDC_V_CTRL_MODE            ( BIT(14) )
+#define BIT_LDO_RAMP_EN                 ( BIT(13) )
+#define BIT_BG_LP_EN                    ( BIT(12) )
+#define BITS_VBAT_CRASH_V(_x_)          ( (_x_) << 10 & (BIT(10)|BIT(11)) )
+#define BIT_OVLO_EN                     ( BIT(9) )
+#define BITS_OVLO_CAL(_x_)              ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) )
+#define BITS_OVLO_V(_x_)                ( (_x_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_OVLO_T(_x_)                ( (_x_) << 0 & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register ANA_REG_GLB_MIXED_CTRL1 */
+#define BITS_XOSC32K_CTL(_x_)           ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_BATON_T(_x_)               ( (_x_) << 10 & (BIT(10)|BIT(11)) )
+#define BIT_BATDET_LDO_SEL              ( BIT(9) )
+#define BIT_THM_CHIP_PD_FLAG            ( BIT(8) )
+#define BIT_THM_CHIP_PD_FLAG_CLR        ( BIT(7) )
+#define BITS_THM_CAL_SEL(_x_)           ( (_x_) << 5 & (BIT(5)|BIT(6)) )
+#define BIT_THM_AUTO_PD_EN              ( BIT(4) )
+#define BIT_ALL_GPI_DEB                 ( BIT(3) )
+#define BIT_GPI_DEBUG_EN                ( BIT(2) )
+#define BIT_ALL_INT_DEB                 ( BIT(1) )
+#define BIT_INT_DEBUG_EN                ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_SWRST_CTRL */
+#define BIT_POR_RTC_PD                  ( BIT(15) )
+#define BITS_POR_RTC_I(_x_)             ( (_x_) << 13 & (BIT(13)|BIT(14)) )
+#define BIT_SW_RST_GEN1_PD_EN           ( BIT(12) )
+#define BIT_SW_RST_GEN0_PD_EN           ( BIT(11) )
+#define BIT_EXT_RSTN_PD_EN              ( BIT(10) )
+#define BIT_PB_7S_RST_PD_EN             ( BIT(9) )
+#define BIT_SW_RST_EMMCCORE_PD_EN       ( BIT(8) )
+#define BIT_KEY2_7S_RST_EN              ( BIT(7) )
+#define BIT_WDG_RST_PD_EN               ( BIT(6) )
+#define BITS_SW_RST_PD_THRESHOLD(_x_)   ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register ANA_REG_GLB_POR_RST_MONITOR */
+#define BITS_POR_RST_MONITOR(_x_)       ( (_x_) << 0 )
+
+/* bits definitions for register ANA_REG_GLB_WDG_RST_MONITOR */
+#define BITS_WDG_RST_MONITOR(_x_)       ( (_x_) << 0 )
+
+/* bits definitions for register ANA_REG_GLB_POR_PIN_RST_MONITOR */
+#define BITS_POR_PIN_RST_MONITOR(_x_)   ( (_x_) << 0 )
+
+/* bits definitions for register ANA_REG_GLB_POR_SRC_FLAG */
+#define BIT_POR_SW_FORCE_ON             ( BIT(15) )
+#define BITS_POR_SRC_FLAG(_x_)          ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+
+/* bits definitions for register ANA_REG_GLB_POR_7S_CTRL */
+#define BIT_PBINT_7S_FLAG_CLR           ( BIT(15) )
+#define BIT_EXT_RSTN_FLAG_CLR           ( BIT(14) )
+#define BIT_CHGR_INT_FLAG_CLR           ( BIT(13) )
+#define BIT_PBINT2_FLAG_CLR             ( BIT(12) )
+#define BIT_PBINT_FLAG_CLR              ( BIT(11) )
+#define BIT_PBINT_7S_RST_SWMODE         ( BIT(8) )
+#define BITS_PBINT_7S_RST_THRESHOLD(_x_)( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_PBINT_7S_AUTO_ON_EN         ( BIT(2) )
+#define BIT_PBINT_7S_RST_DISABLE        ( BIT(1) )
+#define BIT_PBINT_7S_RST_MODE           ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_HWRST_RTC */
+#define BITS_HWRST_RTC_REG_STS(_x_)     ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_HWRST_RTC_REG_SET(_x_)     ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register ANA_REG_GLB_CHIP_ID_LOW */
+#define BITS_CHIP_ID_LOW(_x_)           ( (_x_) << 0 )
+
+/* bits definitions for register ANA_REG_GLB_CHIP_ID_HIGH */
+#define BITS_CHIP_ID_HIGH(_x_)          ( (_x_) << 0 )
+
+/* bits definitions for register ANA_REG_GLB_ARM_MF_REG */
+#define BITS_ARM_MF_REG(_x_)            ( (_x_) << 0 )
+
+/* bits definitions for register ANA_REG_GLB_ARCH_EN */
+#define BIT_ARCH_EN                     ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_MCU_WR_PROT_VALUE */
+#define BIT_MCU_WR_PROT                 ( BIT(15) )
+#define BITS_MCU_WR_PROT_VALUE(_x_)     ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+
+/* bits definitions for register ANA_REG_GLB_PWR_WR_PROT_VALUE */
+#define BIT_PWR_WR_PROT                 ( BIT(15) )
+#define BITS_PWR_WR_PROT_VALUE(_x_)     ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+
+/* bits definitions for register ANA_REG_GLB_SMPL_CTRL0 */
+#define BITS_SMPL_MODE(_x_)             ( (_x_) << 0 )
+
+/* bits definitions for register ANA_REG_GLB_SMPL_CTRL1 */
+#define BIT_SMPL_PWR_ON_FLAG            ( BIT(15) )
+#define BIT_SMPL_MODE_WR_ACK_FLAG       ( BIT(14) )
+#define BIT_SMPL_PWR_ON_FLAG_CLR        ( BIT(13) )
+#define BIT_SMPL_MODE_WR_ACK_FLAG_CLR   ( BIT(12) )
+#define BIT_SMPL_PWR_ON_SET             ( BIT(11) )
+#define BIT_SMPL_EN                     ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_RTC_RST0 */
+#define BITS_RTC_CLK_FLAG_SET(_x_)      ( (_x_) << 15 & (BIT(15)) )
+
+/* bits definitions for register ANA_REG_GLB_RTC_RST1 */
+#define BITS_RTC_CLK_FLAG_CLR(_x_)      ( (_x_) << 15 & (BIT(15)) )
+
+/* bits definitions for register ANA_REG_GLB_RTC_RST2 */
+#define BITS_RTC_CLK_FLAG_RTC(_x_)      ( (_x_) << 15 & (BIT(15)) )
+
+/* bits definitions for register ANA_REG_GLB_LDO_SHPT_PD1 */
+#define BIT_LDO_USB_SHPT_PD             ( BIT(12) )
+#define BIT_LDO_DCXO_SHPT_PD            ( BIT(11) )
+#define BIT_LDO_WIFIPA_SHPT_PD          ( BIT(10) )
+#define BIT_LDO_VDD25_SHPT_PD           ( BIT(9) )
+#define BIT_LDO_VDD28_SHPT_PD           ( BIT(8) )
+#define BIT_LDO_SDIO_SHPT_PD            ( BIT(7) )
+#define BIT_LDO_SDCORE_SHPT_PD          ( BIT(6) )
+#define BIT_LDO_EMMCCORE_SHPT_PD        ( BIT(5) )
+#define BIT_LDO_SIM2_SHPT_PD            ( BIT(4) )
+#define BIT_LDO_SIM1_SHPT_PD            ( BIT(3) )
+#define BIT_LDO_SIM0_SHPT_PD            ( BIT(2) )
+#define BIT_LDO_CAMMOT_SHPT_PD          ( BIT(1) )
+#define BIT_LDO_CAMA_SHPT_PD            ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_LDO_SHPT_PD2 */
+#define BIT_LDO_RF0_SHPT_PD             ( BIT(7) )
+#define BIT_LDO_GEN1_SHPT_PD            ( BIT(6) )
+#define BIT_LDO_GEN0_SHPT_PD            ( BIT(5) )
+#define BIT_LDO_CAMD_SHPT_PD            ( BIT(4) )
+#define BIT_LDO_VDD18_SHPT_PD           ( BIT(3) )
+#define BIT_LDO_CAMIO_SHPT_PD           ( BIT(2) )
+#define BIT_LDO_KPLED_SHPT_PD           ( BIT(1) )
+#define BIT_LDO_VIBR_SHPT_PD            ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_BATDET_CUR_CTRL */
+#define BIT_BATDET_CUR_EN               ( BIT(4) )
+#define BITS_BATDET_CUR_I(_x_)          ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register ANA_REG_GLB_RTC_CLK_STOP */
+#define BIT_RTC_CLK_STOP_FLAG           ( BIT(7) )
+#define BITS_RTC_CLK_STOP_THRESHOLD(_x_)( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) )
+
+/* bits definitions for register ANA_REG_GLB_VBAT_DROP_CNT */
+#define BITS_VBAT_DROP_CNT(_x_)         ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_DISCHRG */
+#define BITS_DCDC_ARM_DISCHRG(_x_)      ( (_x_) << 12 & (BIT(12)|BIT(13)) )
+#define BITS_DCDC_CORE_DISCHRG(_x_)     ( (_x_) << 10 & (BIT(10)|BIT(11)) )
+#define BITS_DCDC_MEM_DISCHRG(_x_)      ( (_x_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_DCDC_GEN_DISCHRG(_x_)      ( (_x_) << 6 & (BIT(6)|BIT(7)) )
+#define BITS_DCDC_RF_DISCHRG(_x_)       ( (_x_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_DCDC_CON_DISCHRG(_x_)      ( (_x_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_DCDC_WPA_DISCHRG(_x_)      ( (_x_) << 0 & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_CORE_ADI */
+#define BITS_DCDC_CORE_CTL_SW_ADI(_x_)  ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_DCDC_CORE_CAL_SW_ADI(_x_)  ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_ARM_ADI */
+#define BITS_DCDC_ARM_CTL_ADI(_x_)      ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_DCDC_ARM_CAL_ADI(_x_)      ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_MEM_ADI */
+#define BITS_DCDC_MEM_CTRL_ADI(_x_)     ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_DCDC_MEM_CAL_ADI(_x_)      ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_GEN_ADI */
+#define BITS_DCDC_GEN_CTRL_ADI(_x_)     ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_DCDC_GEN_CAL_ADI(_x_)      ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_WPA_ADI */
+#define BITS_DCDC_WPA_CAL_ADI(_x_)      ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_WPA_DCM_ADI */
+#define BIT_DCDC_WPA_DCM_ADI            ( BIT(0) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_CON_ADI */
+#define BITS_DCDC_CON_CTRL_ADI(_x_)     ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_DCDC_CON_CAL_ADI(_x_)      ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register ANA_REG_GLB_DCDC_RF_ADI */
+#define BITS_DCDC_RF_CTRL_ADI(_x_)      ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_DCDC_RF_CAL_ADI(_x_)       ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* vars definitions for controller ANA_REGS_GLB */
+
+#endif /* __ANA_REGS_GLB_H__ */
diff --git a/include/soc/sprd/chip_x20/__regs_aon_apb.h b/include/soc/sprd/chip_x20/__regs_aon_apb.h
new file mode 100644
index 00000000..e7996dfc
--- /dev/null
+++ b/include/soc/sprd/chip_x20/__regs_aon_apb.h
@@ -0,0 +1,715 @@
+/* the head file modifier:     ang   2015-01-12 21:07:29*/
+
+/*  
+* Copyright (C) 2013 Spreadtrum Communications Inc.  
+*
+* This program is free software; you can redistribute it and/or  
+* modify it under the terms of the GNU General Public License 
+* as published by the Free Software Foundation; either version 2 
+* of the License, or (at your option) any later version.  
+* 
+* This program is distributed in the hope that it will be useful, 
+* but WITHOUT ANY WARRANTY; without even the implied warranty of 
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the  
+* GNU General Public License for more details.  
+* 
+*************************************************  
+* Automatically generated C header: do not edit *  
+*************************************************  
+*/  
+
+#ifndef __SCI_GLB_REGS_H__  
+#error  "Don't include this file directly, Pls include sci_glb_regs.h" 
+#endif 
+
+
+#ifndef __H_REGS_AON_APB_HEADFILE_H__
+#define __H_REGS_AON_APB_HEADFILE_H__ __FILE__
+
+#define  REGS_AON_APB
+
+/* registers definitions for AON_APB */
+#define REG_AON_APB_APB_EB0				SCI_ADDR(REGS_AON_APB_BASE, 0x0000)/*AHB_EB0*/
+#define REG_AON_APB_APB_EB1				SCI_ADDR(REGS_AON_APB_BASE, 0x0004)/*AHB_EB1*/
+#define REG_AON_APB_APB_RST0				SCI_ADDR(REGS_AON_APB_BASE, 0x0008)/*AHB_RST0*/
+#define REG_AON_APB_APB_RST1				SCI_ADDR(REGS_AON_APB_BASE, 0x000C)/*AHB_RST1*/
+#define REG_AON_APB_APB_RTC_EB				SCI_ADDR(REGS_AON_APB_BASE, 0x0010)/*APB_RTC_EB*/
+#define REG_AON_APB_REC_26MHZ_BUF_CFG			SCI_ADDR(REGS_AON_APB_BASE, 0x0014)/*REC_26MHZ_BUF_CFG*/
+#define REG_AON_APB_SINDRV_CTRL				SCI_ADDR(REGS_AON_APB_BASE, 0x0018)/*SINDRV_CTRL*/
+#define REG_AON_APB_ADA_SEL_CTRL			SCI_ADDR(REGS_AON_APB_BASE, 0x001C)/*ADA_SEL_CTRL*/
+#define REG_AON_APB_VBC_CTRL				SCI_ADDR(REGS_AON_APB_BASE, 0x0020)/*VBC_CTRL*/
+#define REG_AON_APB_PWR_CTRL				SCI_ADDR(REGS_AON_APB_BASE, 0x0024)/*PWR_CTRL*/
+#define REG_AON_APB_TS_CFG				SCI_ADDR(REGS_AON_APB_BASE, 0x0028)/*TS_CFG*/
+#define REG_AON_APB_BOOT_MODE				SCI_ADDR(REGS_AON_APB_BASE, 0x002C)/*BOOT_MODE*/
+#define REG_AON_APB_BB_BG_CTRL				SCI_ADDR(REGS_AON_APB_BASE, 0x0030)/*BB_BG_CTRL*/
+#define REG_AON_APB_CP_ARM_JTAG_CTRL			SCI_ADDR(REGS_AON_APB_BASE, 0x0034)/*CP_ARM_JTAG_CTRL*/
+#define REG_AON_APB_PLL_SOFT_CNT_DONE			SCI_ADDR(REGS_AON_APB_BASE, 0x0038)/*PLL_SOFT_CNT_DONE*/
+#define REG_AON_APB_DCXO_LC_REG0			SCI_ADDR(REGS_AON_APB_BASE, 0x003C)/*DCXO_LC_REG0*/
+#define REG_AON_APB_DCXO_LC_REG1			SCI_ADDR(REGS_AON_APB_BASE, 0x0040)/*DCXO_LC_REG1*/
+#define REG_AON_APB_DSI_PHY_CTRL			SCI_ADDR(REGS_AON_APB_BASE, 0x0048)/*DSI_PHY_CTRL*/
+#define REG_AON_APB_CSI0_PHY_CTRL			SCI_ADDR(REGS_AON_APB_BASE, 0x004C)/*CSI0_PHY_CTRL*/
+#define REG_AON_APB_CSI1_PHY_CTRL			SCI_ADDR(REGS_AON_APB_BASE, 0x0050)/*CSI1_PHY_CTRL*/
+#define REG_AON_APB_FUNC_TEST_BOOT_ADDR			SCI_ADDR(REGS_AON_APB_BASE, 0x0054)/*FUNC_TEST_BOOT_ADDR*/
+#define REG_AON_APB_RINGOSC_CTRL			SCI_ADDR(REGS_AON_APB_BASE, 0x0058)/*RINGOSC_CTRL*/
+#define REG_AON_APB_RINGOSC_OBS_CNT			SCI_ADDR(REGS_AON_APB_BASE, 0x005C)/*RINGOSC_OBS_CNT*/
+#define REG_AON_APB_DDR_ZQ_CONTROL			SCI_ADDR(REGS_AON_APB_BASE, 0x0060)/*DDR_ZQ_CONTROL*/
+#define REG_AON_APB_WBT_BG_CTRL				SCI_ADDR(REGS_AON_APB_BASE, 0x0064)/*WBT_BG_CTRL*/
+#define REG_AON_APB_CLK_DMC_CFG				SCI_ADDR(REGS_AON_APB_BASE, 0x0080)/*CLK_DMC_CFG*/
+#define REG_AON_APB_SOFT_DFS_CTRL			SCI_ADDR(REGS_AON_APB_BASE, 0x0084)/*SOFT_DFS_CTRL*/
+#define REG_AON_APB_CLK26M_CFG				SCI_ADDR(REGS_AON_APB_BASE, 0x0088)/*CLK26M_CFG*/
+#define REG_AON_APB_HARD_DFS_CTRL_LO			SCI_ADDR(REGS_AON_APB_BASE, 0x0090)/*HARD_DFS_CTRL_LO*/
+#define REG_AON_APB_HARD_DFS_CTRL_HI			SCI_ADDR(REGS_AON_APB_BASE, 0x0094)/*HARD_DFS_CTRL_HI*/
+#define REG_AON_APB_AON_CHIP_ID				SCI_ADDR(REGS_AON_APB_BASE, 0x00FC)/*AON_CHIP_ID*/
+#define REG_AON_APB_MPLL_CFG				SCI_ADDR(REGS_AON_APB_BASE, 0x3000)/*MPLL_CFG*/
+#define REG_AON_APB_DPLL_CFG				SCI_ADDR(REGS_AON_APB_BASE, 0x3004)/*DPLL_CFG*/
+#define REG_AON_APB_TDPLL_CFG				SCI_ADDR(REGS_AON_APB_BASE, 0x3008)/*TDPLL_CFG*/
+#define REG_AON_APB_CPLL_CFG				SCI_ADDR(REGS_AON_APB_BASE, 0x300C)/*CPLL_CFG*/
+#define REG_AON_APB_WIFIPLL0_CFG			SCI_ADDR(REGS_AON_APB_BASE, 0x3010)/*WIFIPLL0_CFG*/
+#define REG_AON_APB_WIFIPLL1_CFG			SCI_ADDR(REGS_AON_APB_BASE, 0x3014)/*WIFIPLL1_CFG*/
+#define REG_AON_APB_WPLL_CFG0				SCI_ADDR(REGS_AON_APB_BASE, 0x3018)/*WPLL_CFG0*/
+#define REG_AON_APB_WPLL_CFG1				SCI_ADDR(REGS_AON_APB_BASE, 0x301C)/*WPLL_CFG1*/
+#define REG_AON_APB_AON_CGM_CFG				SCI_ADDR(REGS_AON_APB_BASE, 0x3020)/*AON_CGM_CFG*/
+#define REG_AON_APB_CP0_ADDR_REMAP_CTRL0		SCI_ADDR(REGS_AON_APB_BASE, 0x3024)/*CP0_ADDR_REMAP_CTRL0*/
+#define REG_AON_APB_CP0_ADDR_REMAP_CTRL1		SCI_ADDR(REGS_AON_APB_BASE, 0x3028)/*CP0_ADDR_REMAP_CTRL1*/
+#define REG_AON_APB_CP1_ADDR_REMAP_CTRL0		SCI_ADDR(REGS_AON_APB_BASE, 0x302C)/*CP1_ADDR_REMAP_CTRL0*/
+#define REG_AON_APB_CP1_ADDR_REMAP_CTRL1		SCI_ADDR(REGS_AON_APB_BASE, 0x3030)/*CP1_ADDR_REMAP_CTRL1*/
+#define REG_AON_APB_CP2_ADDR_REMAP_CTRL0		SCI_ADDR(REGS_AON_APB_BASE, 0x3034)/*CP2_ADDR_REMAP_CTRL0*/
+#define REG_AON_APB_CP2_ADDR_REMAP_CTRL1		SCI_ADDR(REGS_AON_APB_BASE, 0x3038)/*CP2_ADDR_REMAP_CTRL1*/
+#define REG_AON_APB_IO_DLY_CTRL				SCI_ADDR(REGS_AON_APB_BASE, 0x303C)/*IO_DLY_CTRL*/
+#define REG_AON_APB_AP_WPROT_EN				SCI_ADDR(REGS_AON_APB_BASE, 0x3040)/*AP_WPROT_EN*/
+#define REG_AON_APB_CP0_WPROT_EN			SCI_ADDR(REGS_AON_APB_BASE, 0x3044)/*CP0_WPROT_EN*/
+#define REG_AON_APB_CP1_WPROT_EN			SCI_ADDR(REGS_AON_APB_BASE, 0x3048)/*CP1_WPROT_EN*/
+#define REG_AON_APB_CP2_WPROT_EN			SCI_ADDR(REGS_AON_APB_BASE, 0x304C)/*CP2_WPROT_EN*/
+#define REG_AON_APB_PMU_RST_MONITOR			SCI_ADDR(REGS_AON_APB_BASE, 0x3050)/*PMU_RST_MONITOR*/
+#define REG_AON_APB_THM_RST_MONITOR			SCI_ADDR(REGS_AON_APB_BASE, 0x3054)/*THM_RST_MONITOR*/
+#define REG_AON_APB_AP_RST_MONITOR			SCI_ADDR(REGS_AON_APB_BASE, 0x3058)/*AP_RST_MONITOR*/
+#define REG_AON_APB_CA7_RST_MONITOR			SCI_ADDR(REGS_AON_APB_BASE, 0x305C)/*CA7_RST_MONITOR*/
+#define REG_AON_APB_BOND_OPT0				SCI_ADDR(REGS_AON_APB_BASE, 0x3060)/*BOND_OPT0*/
+#define REG_AON_APB_BOND_OPT1				SCI_ADDR(REGS_AON_APB_BASE, 0x3064)/*BOND_OPT1*/
+#define REG_AON_APB_RES_REG0				SCI_ADDR(REGS_AON_APB_BASE, 0x3068)/*RES_REG0*/
+#define REG_AON_APB_RES_REG1				SCI_ADDR(REGS_AON_APB_BASE, 0x306C)/*RES_REG1*/
+#define REG_AON_APB_MPLL_CFG1				SCI_ADDR(REGS_AON_APB_BASE, 0x3070)/*MPLL_CFG1*/
+#define REG_AON_APB_DPLL_CFG1				SCI_ADDR(REGS_AON_APB_BASE, 0x3074)/*DPLL_CFG1*/
+#define REG_AON_APB_TDPLL_CFG1				SCI_ADDR(REGS_AON_APB_BASE, 0x3078)/*TDPLL_CFG1*/
+#define REG_AON_APB_CPLL_CFG1				SCI_ADDR(REGS_AON_APB_BASE, 0x307C)/*CPLL_CFG1*/
+#define REG_AON_APB_WIFIPLL1_CFG1			SCI_ADDR(REGS_AON_APB_BASE, 0x3080)/*WIFIPLL1_CFG1*/
+#define REG_AON_APB_WIFIPLL2_CFG1			SCI_ADDR(REGS_AON_APB_BASE, 0x3084)/*WIFIPLL2_CFG1*/
+#define REG_AON_APB_AON_QOS_CFG				SCI_ADDR(REGS_AON_APB_BASE, 0x3088)/*AON_QOS_CFG*/
+#define REG_AON_APB_BB_LDO_CAL_START			SCI_ADDR(REGS_AON_APB_BASE, 0x308C)/*BB_LDO_CAL_START*/
+#define REG_AON_APB_WBT_BG_LDO				SCI_ADDR(REGS_AON_APB_BASE, 0x3090)/*WBT_BG_LDO*/
+#define REG_AON_APB_ANA_BB_MISC				SCI_ADDR(REGS_AON_APB_BASE, 0x3094)/*ANA_BB_MISC*/
+#define REG_AON_APB_DJTAG_MUX_SEL			SCI_ADDR(REGS_AON_APB_BASE, 0x3098)/*DJTAG_MUX_SEL*/
+#define REG_AON_APB_BBPLL_RESERVED_0			SCI_ADDR(REGS_AON_APB_BASE, 0x309C)/*BBPLL_RESERVED_0*/
+#define REG_AON_APB_BBPLL_RESERVED_1			SCI_ADDR(REGS_AON_APB_BASE, 0x30A0)/*BBPLL_RESERVED_1*/
+#define REG_AON_APB_RPLL_CFG0				SCI_ADDR(REGS_AON_APB_BASE, 0x30A4)/*RPLL_CFG0*/
+#define REG_AON_APB_AON_DEBUG_CFG			SCI_ADDR(REGS_AON_APB_BASE, 0x30A8)/*AON_DEBUG_CFG*/
+
+
+
+/* bits definitions for register REG_AON_APB_APB_EB0 */
+#define BIT_I2C_EB						( BIT(31) )
+#define BIT_CA7_DAP_EB						( BIT(30) )
+#define BIT_CA7_TS1_EB						( BIT(29) )
+#define BIT_CA7_TS0_EB						( BIT(28) )
+#define BIT_GPU_EB						( BIT(27) )
+#define BIT_AON_CKG_EB                                        ( BIT(26) )
+#define BIT_MM_EB						( BIT(25) )
+#define BIT_AP_WDG_EB						( BIT(24) )
+#define BIT_MSPI_EB						( BIT(23) )
+#define BIT_SPLK_EB						( BIT(22) )
+#define BIT_IPI_EB						( BIT(21) )
+#define BIT_PIN_EB						( BIT(20) )
+#define BIT_VBC_EB						( BIT(19) )
+#define BIT_AUD_EB						( BIT(18) )
+#define BIT_AUDIF_EB						( BIT(17) )
+#define BIT_ADI_EB						( BIT(16) )
+#define BIT_INTC_EB						( BIT(15) )
+#define BIT_EIC_EB						( BIT(14) )
+#define BIT_EFUSE_EB						( BIT(13) )
+#define BIT_AP_TMR0_EB						( BIT(12) )
+#define BIT_AON_TMR_EB						( BIT(11) )
+#define BIT_AP_SYST_EB						( BIT(10) )
+#define BIT_AON_SYST_EB						( BIT(9) )
+#define BIT_KPD_EB						( BIT(8) )
+#define BIT_PWM3_EB						( BIT(7) )
+#define BIT_PWM2_EB						( BIT(6) )
+#define BIT_PWM1_EB						( BIT(5) )
+#define BIT_PWM0_EB						( BIT(4) )
+#define BIT_GPIO_EB						( BIT(3) )
+#define BIT_TPC_EB						( BIT(2) )
+#define BIT_FM_EB						( BIT(1) )
+#define BIT_ADC_EB						( BIT(0) )
+
+/* bits definitions for register REG_AON_APB_APB_EB1 */
+#define BIT_EMC_REF_CKG_EN					( BIT(20) )
+#define BIT_DJTAG_EB						( BIT(19) )
+#define BIT_RINGOSC_EB						( BIT(18) )
+#define BIT_PUB_REG_EB						( BIT(17) )
+#define BIT_DMC_EB						( BIT(16) )
+#define BIT_RFTI_SBI_EB						( BIT(15) )
+#define BIT_MDAR_EB						( BIT(14) )
+#define BIT_GSP_EMC_EB						( BIT(13) )
+#define BIT_ZIP_EMC_EB						( BIT(12) )
+#define BIT_DISP_EMC_EB						( BIT(11) )
+#define BIT_AP_TMR2_EB						( BIT(10) )
+#define BIT_AP_TMR1_EB						( BIT(9) )
+#define BIT_CA7_WDG_EB						( BIT(8) )
+#define BIT_AVS1_EB						( BIT(7) )
+#define BIT_AVS0_EB						( BIT(6) )
+#define BIT_PROBE_EB						( BIT(5) )
+#define BIT_AUX2_EB						( BIT(4) )
+#define BIT_AUX1_EB						( BIT(3) )
+#define BIT_AUX0_EB						( BIT(2) )
+#define BIT_THM_EB						( BIT(1) )
+#define BIT_PMU_EB						( BIT(0) )
+
+/* bits definitions for register REG_AON_APB_APB_RST0 */
+#define BIT_I2C_SOFT_RST					( BIT(30) )
+#define BIT_CA7_TS1_SOFT_RST					( BIT(29) )
+#define BIT_CA7_TS0_SOFT_RST					( BIT(28) )
+#define BIT_DAP_MTX_SOFT_RST					( BIT(27) )
+#define BIT_MSPI1_SOFT_RST					( BIT(26) )
+#define BIT_MSPI0_SOFT_RST					( BIT(25) )
+#define BIT_SPLK_SOFT_RST					( BIT(24) )
+#define BIT_IPI_SOFT_RST					( BIT(23) )
+#define BIT_AON_CKG_SOFT_RST                                  ( BIT(22) )
+#define BIT_PIN_SOFT_RST					( BIT(21) )
+#define BIT_VBC_SOFT_RST					( BIT(20) )
+#define BIT_AUD_SOFT_RST					( BIT(19) )
+#define BIT_AUDIF_SOFT_RST					( BIT(18) )
+#define BIT_ADI_SOFT_RST					( BIT(17) )
+#define BIT_INTC_SOFT_RST					( BIT(16) )
+#define BIT_EIC_SOFT_RST					( BIT(15) )
+#define BIT_EFUSE_SOFT_RST					( BIT(14) )
+#define BIT_AP_WDG_SOFT_RST					( BIT(13) )
+#define BIT_AP_TMR0_SOFT_RST					( BIT(12) )
+#define BIT_AON_TMR_SOFT_RST					( BIT(11) )
+#define BIT_AP_SYST_SOFT_RST					( BIT(10) )
+#define BIT_AON_SYST_SOFT_RST					( BIT(9) )
+#define BIT_KPD_SOFT_RST					( BIT(8) )
+#define BIT_PWM3_SOFT_RST					( BIT(7) )
+#define BIT_PWM2_SOFT_RST					( BIT(6) )
+#define BIT_PWM1_SOFT_RST					( BIT(5) )
+#define BIT_PWM0_SOFT_RST					( BIT(4) )
+#define BIT_GPIO_SOFT_RST					( BIT(3) )
+#define BIT_TPC_SOFT_RST					( BIT(2) )
+#define BIT_FM_SOFT_RST						( BIT(1) )
+#define BIT_ADC_SOFT_RST					( BIT(0) )
+
+/* bits definitions for register REG_AON_APB_APB_RST1 */
+#define BIT_PUB_DJTAG_SOFT_RST					( BIT(23) )
+#define BIT_GPU_DJTAG_SOFT_RST					( BIT(22) )
+#define BIT_MM_DJTAG_SOFT_RST					( BIT(21) )
+#define BIT_CP2_DJTAG_SOFT_RST					( BIT(20) )
+#define BIT_CP0_DJTAG_SOFT_RST					( BIT(19) )
+#define BIT_AP_DJTAG_SOFT_RST					( BIT(18) )
+#define BIT_AON_DJTAG_SOFT_RST					( BIT(17) )
+#define BIT_LVDSRF_CALI_SOFT_RST				( BIT(16) )
+#define BIT_LTH_SOFT_RST					( BIT(15) )
+#define BIT_RINGOSC_SOFT_RST					( BIT(14) )
+#define BIT_RFTI_SBI_SOFT_RST					( BIT(13) )
+#define BIT_MDAR_SOFT_RST					( BIT(12) )
+#define BIT_BB_CAL_SOFT_RST					( BIT(11) )
+#define BIT_DCXO_LC_SOFT_RST					( BIT(10) )
+#define BIT_AP_TMR2_SOFT_RST					( BIT(9) )
+#define BIT_AP_TMR1_SOFT_RST					( BIT(8) )
+#define BIT_CA7_WDG_SOFT_RST					( BIT(7) )
+#define BIT_AVS1_SOFT_RST					( BIT(6) )
+#define BIT_AVS0_SOFT_RST					( BIT(5) )
+#define BIT_DMC_PHY_SOFT_RST					( BIT(4) )
+#define BIT_GPU_THMA_SOFT_RST					( BIT(3) )
+#define BIT_ARM_THMA_SOFT_RST					( BIT(2) )
+#define BIT_THM_SOFT_RST					( BIT(1) )
+#define BIT_PMU_SOFT_RST					( BIT(0) )
+
+/* bits definitions for register REG_AON_APB_APB_RTC_EB */
+#define BIT_BB_CAL_RTC_EB					( BIT(18) )
+#define BIT_DCXO_LC_RTC_EB					( BIT(17) )
+#define BIT_AP_TMR2_RTC_EB					( BIT(16) )
+#define BIT_AP_TMR1_RTC_EB					( BIT(15) )
+#define BIT_GPU_THMA_RTC_AUTO_EN				( BIT(14) )
+#define BIT_ARM_THMA_RTC_AUTO_EN				( BIT(13) )
+#define BIT_GPU_THMA_RTC_EB					( BIT(12) )
+#define BIT_ARM_THMA_RTC_EB					( BIT(11) )
+#define BIT_THM_RTC_EB						( BIT(10) )
+#define BIT_CA7_WDG_RTC_EB					( BIT(9) )
+#define BIT_AP_WDG_RTC_EB					( BIT(8) )
+#define BIT_EIC_RTCDV5_EB					( BIT(7) )
+#define BIT_EIC_RTC_EB						( BIT(6) )
+#define BIT_AP_TMR0_RTC_EB					( BIT(5) )
+#define BIT_AON_TMR_RTC_EB					( BIT(4) )
+#define BIT_AP_SYST_RTC_EB					( BIT(3) )
+#define BIT_AON_SYST_RTC_EB					( BIT(2) )
+#define BIT_KPD_RTC_EB						( BIT(1) )
+#define BIT_ARCH_RTC_EB						( BIT(0) )
+
+/* bits definitions for register REG_AON_APB_REC_26MHZ_BUF_CFG */
+#define BITS_PLL_PROBE_SEL(_X_)					( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
+#define BIT_REC_26MHZ_1_FORCE_PD				( BIT(5) )
+#define BIT_REC_26MHZ_1_CUR_SEL					( BIT(4) )
+#define BIT_REC_26MHZ_0_CUR_SEL					( BIT(0) )
+
+/* bits definitions for register REG_AON_APB_SINDRV_CTRL */
+#define BITS_SINDRV_LVL(_X_)					( (_X_) << 3 & (BIT(3)|BIT(4)) )
+#define BIT_SINDRV_CLIP_MODE					( BIT(2) )
+#define BIT_SINDRV_ENA_SQUARE					( BIT(1) )
+#define BIT_SINDRV_ENA						( BIT(0) )
+
+/* bits definitions for register REG_AON_APB_ADA_SEL_CTRL */
+#define BIT_RAM_TD_MODE_SEL					( BIT(4) )
+#define BIT_TW_MODE_SEL						( BIT(3) )
+#define BIT_WGADC_DIV_EN					( BIT(2) )
+#define BIT_AFCDAC_SYS_SEL					( BIT(1) )
+#define BIT_APCDAC_SYS_SEL					( BIT(0) )
+
+/* bits definitions for register REG_AON_APB_VBC_CTRL */
+#define BIT_AUDIF_CKG_AUTO_EN					( BIT(20) )
+#define BITS_AUD_INT_SYS_SEL(_X_)				( (_X_) << 18 & (BIT(18)|BIT(19)) )
+#define BITS_VBC_AFIFO_INT_SYS_SEL(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_VBC_AD23_INT_SYS_SEL(_X_)				( (_X_) << 14 & (BIT(14)|BIT(15)) )
+#define BITS_VBC_AD01_INT_SYS_SEL(_X_)				( (_X_) << 12 & (BIT(12)|BIT(13)) )
+#define BITS_VBC_DA01_INT_SYS_SEL(_X_)				( (_X_) << 10 & (BIT(10)|BIT(11)) )
+#define BITS_VBC_AD23_DMA_SYS_SEL(_X_)				( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_VBC_AD01_DMA_SYS_SEL(_X_)				( (_X_) << 6 & (BIT(6)|BIT(7)) )
+#define BITS_VBC_DA01_DMA_SYS_SEL(_X_)				( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BIT_VBC_INT_CP0_ARM_SEL					( BIT(3) )
+#define BIT_VBC_INT_CP1_ARM_SEL					( BIT(2) )
+#define BIT_VBC_DMA_CP0_ARM_SEL					( BIT(1) )
+#define BIT_VBC_DMA_CP1_ARM_SEL					( BIT(0) )
+
+/* bits definitions for register REG_AON_APB_PWR_CTRL */
+#define BIT_DSI_PHY_PD_S					( BIT(15) )
+#define BIT_CSI1_PHY_PD_S					( BIT(14) )
+#define BIT_CSI0_PHY_PD_S					( BIT(13) )
+#define BIT_DSI_PHY_PD						( BIT(12) )
+#define BIT_CSI1_PHY_PD						( BIT(11) )
+#define BIT_CSI0_PHY_PD						( BIT(10) )
+#define BIT_CA7_TS1_STOP					( BIT(9) )
+#define BIT_CA7_TS0_STOP					( BIT(8) )
+#define BIT_EFUSE_BIST_PWR_ON					( BIT(3) )
+#define BIT_FORCE_DSI_PHY_SHUTDOWNZ				( BIT(2) )
+#define BIT_FORCE_CSI_PHY_SHUTDOWNZ				( BIT(1) )
+#define BIT_USB_PHY_PD						( BIT(0) )
+
+/* bits definitions for register REG_AON_APB_TS_CFG */
+#define BIT_CSYSACK_TS_LP_2					( BIT(13) )
+#define BIT_CSYSREQ_TS_LP_2					( BIT(12) )
+#define BIT_CSYSACK_TS_LP_1					( BIT(11) )
+#define BIT_CSYSREQ_TS_LP_1					( BIT(10) )
+#define BIT_CSYSACK_TS_LP_0					( BIT(9) )
+#define BIT_CSYSREQ_TS_LP_0					( BIT(8) )
+#define BIT_EVENTACK_RESTARTREQ_TS01				( BIT(4) )
+#define BIT_EVENT_RESTARTREQ_TS01				( BIT(1) )
+#define BIT_EVENT_HALTREQ_TS01					( BIT(0) )
+
+/* bits definitions for register REG_AON_APB_BOOT_MODE */
+#define BIT_WPLL_OVR_FREQ_SEL					( BIT(12) )
+#define BIT_PTEST_FUNC_ATSPEED_SEL				( BIT(8) )
+#define BIT_PTEST_FUNC_MODE					( BIT(7) )
+#define BIT_PTEST_FUNC_DMA_MODE					( BIT(6) )
+#define BIT_USB_DLOAD_EN					( BIT(4) )
+#define BIT_ARM_BOOT_MD3					( BIT(3) )
+#define BIT_ARM_BOOT_MD2					( BIT(2) )
+#define BIT_ARM_BOOT_MD1					( BIT(1) )
+#define BIT_ARM_BOOT_MD0					( BIT(0) )
+
+/* bits definitions for register REG_AON_APB_BB_BG_CTRL */
+#define BIT_BB_CON_BG						( BIT(22) )
+#define BITS_BB_BG_RSV(_X_)					( (_X_) << 20 & (BIT(20)|BIT(21)) )
+#define BITS_BB_LDO_V(_X_)					( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BIT_BB_BG_RBIAS_EN					( BIT(15) )
+#define BIT_BB_BG_IEXT_IB_EN					( BIT(14) )
+#define BITS_BB_LDO_REFCTRL(_X_)				( (_X_) << 12 & (BIT(12)|BIT(13)) )
+#define BIT_BB_LDO_AUTO_PD_EN					( BIT(11) )
+#define BIT_BB_LDO_SLP_PD_EN					( BIT(10) )
+#define BIT_BB_LDO_FORCE_ON					( BIT(9) )
+#define BIT_BB_LDO_FORCE_PD					( BIT(8) )
+#define BIT_BB_BG_AUTO_PD_EN					( BIT(3) )
+#define BIT_BB_BG_SLP_PD_EN					( BIT(2) )
+#define BIT_BB_BG_FORCE_ON					( BIT(1) )
+#define BIT_BB_BG_FORCE_PD					( BIT(0) )
+
+/* bits definitions for register REG_AON_APB_CP_ARM_JTAG_CTRL */
+#define BITS_CP_ARM_JTAG_PIN_SEL(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
+
+/* bits definitions for register REG_AON_APB_PLL_SOFT_CNT_DONE */
+#define BIT_XTLBUF1_SOFT_CNT_DONE				( BIT(9) )
+#define BIT_XTLBUF0_SOFT_CNT_DONE				( BIT(8) )
+#define BIT_WIFIPLL2_SOFT_CNT_DONE				( BIT(6) )
+#define BIT_WIFIPLL1_SOFT_CNT_DONE				( BIT(5) )
+#define BIT_CPLL_SOFT_CNT_DONE					( BIT(4) )
+#define BIT_WPLL_SOFT_CNT_DONE					( BIT(3) )
+#define BIT_TDPLL_SOFT_CNT_DONE					( BIT(2) )
+#define BIT_DPLL_SOFT_CNT_DONE					( BIT(1) )
+#define BIT_MPLL_SOFT_CNT_DONE					( BIT(0) )
+
+/* bits definitions for register REG_AON_APB_DCXO_LC_REG0 */
+#define BIT_DCXO_LC_FLAG					( BIT(8) )
+#define BIT_DCXO_LC_FLAG_CLR					( BIT(1) )
+#define BIT_DCXO_LC_CNT_CLR					( BIT(0) )
+
+/* bits definitions for register REG_AON_APB_DCXO_LC_REG1 */
+#define BITS_DCXO_LC_CNT(_X_)					(_X_)
+
+/* bits definitions for register REG_AON_APB_DSI_PHY_CTRL */
+#define BIT_DSI_PHY_IF_SEL					( BIT(24) )
+#define BITS_DSI_PHY_TRIMBG(_X_)				( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DSI_PHY_TX_RCTL(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DSI_PHY_RESERVED(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_AON_APB_CSI0_PHY_CTRL */
+#define BIT_CSI0_PHY_IF_SEL					( BIT(24) )
+#define BITS_CSI0_PHY_RX_RCTL(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_CSI0_PHY_RESERVED(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_AON_APB_CSI1_PHY_CTRL */
+#define BIT_CSI1_PHY_IF_SEL					( BIT(24) )
+#define BITS_CSI1_PHY_RX_RCTL(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_CSI1_PHY_RESERVED(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_AON_APB_FUNC_TEST_BOOT_ADDR */
+#define BITS_FUNC_TEST_BOOT_ADDR(_X_)				(_X_)
+
+/* bits definitions for register REG_AON_APB_RINGOSC_CTRL */
+#define BITS_RINGOSC_CNT_CLK_NUM(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) )
+#define BIT_AP_RINGOSC_EN_CA7_TOP				( BIT(15) )
+#define BIT_AP_RINGOSC_EN_AP_TOP				( BIT(14) )
+#define BITS_AP_RINGOSC_CTRL(_X_)				( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
+#define BITS_RINGOSC_CTRL(_X_)					( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_AON_APB_RINGOSC_OBS_CNT */
+#define BIT_RINGOSC_OBS_CNT_OVERFLOW				( BIT(16) )
+#define BITS_RINGOSC_OBS_CNT(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_AON_APB_DDR_ZQ_CONTROL */
+#define BIT_DDR_ZQ_CALOVER					( BIT(17) )
+#define BIT_DDR_ZQ_PD						( BIT(16) )
+#define BIT_DDR_ZQ_CAL						( BIT(15) )
+#define BITS_DDR_ZQ_ZPROG(_X_)					( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_DDR_ZQ_DRVP(_X_)					( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_DDR_ZQ_DRVN(_X_)					( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_AON_APB_WBT_BG_CTRL */
+#define BIT_WBT_LDO_CAL_RST					( BIT(25) )
+#define BIT_WBT_LDO_CAL_START					( BIT(24) )
+#define BIT_WBT_LDO_CAL_CLK					( BIT(23) )
+#define BIT_WBT_CON_BG						( BIT(22) )
+#define BITS_WBT_LDO_V(_X_)					( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)|BIT(21)) )
+#define BIT_WBT_BG_RBIAS_EN					( BIT(17) )
+#define BIT_WBT_BG_IEXT_IB_EN					( BIT(16) )
+#define BIT_WBT_LDO_AUTO_PD_EN					( BIT(11) )
+#define BIT_WBT_LDO_SLP_PD_EN					( BIT(10) )
+#define BIT_WBT_LDO_FORCE_ON					( BIT(9) )
+#define BIT_WBT_LDO_FORCE_PD					( BIT(8) )
+#define BIT_WBT_BG_AUTO_PD_EN					( BIT(3) )
+#define BIT_WBT_BG_SLP_PD_EN					( BIT(2) )
+#define BIT_WBT_BG_FORCE_ON					( BIT(1) )
+#define BIT_WBT_BG_FORCE_PD					( BIT(0) )
+
+/* bits definitions for register REG_AON_APB_CLK_DMC_CFG */
+#define BITS_CLK_DMC_DIV(_X_)					( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) )
+#define BITS_CLK_DMC_SEL(_X_)					( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_AON_APB_SOFT_DFS_CTRL */
+#define BITS_PUB_DFS_SW_SWITCH_PERIOD(_X_)			( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PUB_DFS_SW_RATIO(_X_)				( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
+#define BITS_PUB_DFS_SW_FRQ_SEL(_X_)				( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BIT_PUB_DFS_SW_RESP					( BIT(3) )
+#define BIT_PUB_DFS_SW_ACK					( BIT(2) )
+#define BIT_PUB_DFS_SW_REQ					( BIT(1) )
+#define BIT_PUB_DFS_SW_ENABLE					( BIT(0) )
+
+/* bits definitions for register REG_AON_APB_CLK26M_CFG */
+#define BIT_CLKBAK_EN						( BIT(4) )
+#define BIT_CLK26MHZ_A2D_1_SEL					( BIT(3) )
+#define BIT_CLK26MHZ_A2D_0_SEL					( BIT(2) )
+#define BITS_CLK26M_SEL(_X_)					( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_AON_APB_HARD_DFS_CTRL_LO */
+#define BITS_PUB_DFS_HW_INITIAL_FREQ(_X_)			( (_X_) << 3 & (BIT(3)|BIT(4)) )
+#define BIT_PUB_DFS_HW_STOP					( BIT(2) )
+#define BIT_PUB_DFS_HW_START					( BIT(1) )
+#define BIT_PUB_DFS_HW_ENABLE					( BIT(0) )
+
+/* bits definitions for register REG_AON_APB_HARD_DFS_CTRL_HI */
+#define BITS_PUB_DFS_HW_SWITCH_PERIOD(_X_)			( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_PUB_DFS_HW_F3_RATIO(_X_)				( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_PUB_DFS_HW_F2_RATIO(_X_)				( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_PUB_DFS_HW_F1_RATIO(_X_)				( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BITS_PUB_DFS_HW_F0_RATIO(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
+
+/* bits definitions for register REG_AON_APB_AON_CHIP_ID */
+#define BITS_AON_CHIP_ID(_X_)					(_X_)
+
+/* bits definitions for register REG_AON_APB_MPLL_CFG */
+#define BITS_MPLL_REFIN(_X_)					( (_X_) << 24 & (BIT(24)|BIT(25)) )
+#define BITS_MPLL_LPF(_X_)					( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
+#define BITS_MPLL_IBIAS(_X_)					( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_MPLL_N(_X_)					( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
+
+/* bits definitions for register REG_AON_APB_DPLL_CFG */
+#define BITS_DPLL_REFIN(_X_)					( (_X_) << 24 & (BIT(24)|BIT(25)) )
+#define BITS_DPLL_LPF(_X_)					( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
+#define BITS_DPLL_IBIAS(_X_)					( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_DPLL_N(_X_)					( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
+
+/* bits definitions for register REG_AON_APB_TDPLL_CFG */
+#define BIT_TDPLL_DIV5_FORCE_PD					( BIT(31) )
+#define BIT_TDPLL_DIV3_FORCE_PD					( BIT(30) )
+#define BIT_TDPLL_DIV2_FORCE_PD					( BIT(29) )
+#define BIT_TDPLL_DIV5_PD_AUTO					( BIT(28) )
+#define BIT_TDPLL_DIV3_PD_AUTO					( BIT(27) )
+#define BIT_TDPLL_DIV2_PD_AUTO					( BIT(26) )
+#define BITS_TDPLL_REFIN(_X_)					( (_X_) << 24 & (BIT(24)|BIT(25)) )
+#define BITS_TDPLL_LPF(_X_)					( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
+#define BITS_TDPLL_IBIAS(_X_)					( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_TDPLL_N(_X_)					( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
+
+/* bits definitions for register REG_AON_APB_CPLL_CFG */
+#define BITS_CPLL_REFIN(_X_)					( (_X_) << 24 & (BIT(24)|BIT(25)) )
+#define BITS_CPLL_LPF(_X_)					( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
+#define BITS_CPLL_IBIAS(_X_)					( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_CPLL_N(_X_)					( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
+
+/* bits definitions for register REG_AON_APB_WIFIPLL0_CFG */
+#define BITS_WIFIPLL1_REFIN(_X_)				( (_X_) << 24 & (BIT(24)|BIT(25)) )
+#define BITS_WIFIPLL1_LPF(_X_)					( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
+#define BITS_WIFIPLL1_IBIAS(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_WIFIPLL1_N(_X_)					( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
+
+/* bits definitions for register REG_AON_APB_WIFIPLL1_CFG */
+#define BITS_WIFIPLL2_REFIN(_X_)				( (_X_) << 24 & (BIT(24)|BIT(25)) )
+#define BITS_WIFIPLL2_LPF(_X_)					( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
+#define BITS_WIFIPLL2_IBIAS(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_WIFIPLL2_N(_X_)					( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
+
+/* bits definitions for register REG_AON_APB_WPLL_CFG0 */
+#define BITS_WPLL_REFIN(_X_)					( (_X_) << 24 & (BIT(24)|BIT(25)) )
+#define BITS_WPLL_LPF(_X_)					( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
+#define BITS_WPLL_IBIAS(_X_)					( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_WPLL_N(_X_)					( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
+
+/* bits definitions for register REG_AON_APB_WPLL_CFG1 */
+#define BITS_WPLL_KINT(_X_)					( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_WPLL_DIV_S						( BIT(10) )
+#define BITS_WPLL_RSV(_X_)					( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BIT_WPLL_MOD_EN						( BIT(7) )
+#define BIT_WPLL_SDM_EN						( BIT(6) )
+#define BITS_WPLL_NINT(_X_)					( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+
+/* bits definitions for register REG_AON_APB_AON_CGM_CFG */
+#define BITS_PROBE_CKG_DIV(_X_)					( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_AUX2_CKG_DIV(_X_)					( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_AUX1_CKG_DIV(_X_)					( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_AUX0_CKG_DIV(_X_)					( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_PROBE_CKG_SEL(_X_)					( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_AUX2_CKG_SEL(_X_)					( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_AUX1_CKG_SEL(_X_)					( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_AUX0_CKG_SEL(_X_)					( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_AON_APB_CP0_ADDR_REMAP_CTRL0 */
+#define BITS_CP0_ADDR_B7_REMAP(_X_)				( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_CP0_ADDR_B6_REMAP(_X_)				( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_CP0_ADDR_B5_REMAP(_X_)				( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_CP0_ADDR_B4_REMAP(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_CP0_ADDR_B3_REMAP(_X_)				( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_CP0_ADDR_B2_REMAP(_X_)				( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_CP0_ADDR_B1_REMAP(_X_)				( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_CP0_ADDR_B0_REMAP(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_AON_APB_CP0_ADDR_REMAP_CTRL1 */
+#define BIT_CP0_PUB_IRAM_B8_PROT_EN				( BIT(12) )
+#define BIT_CP0_PUB_IRAM_B7_PROT_EN				( BIT(11) )
+#define BIT_CP0_PUB_IRAM_B6_PROT_EN				( BIT(10) )
+#define BIT_CP0_PUB_IRAM_B5_PROT_EN				( BIT(9) )
+#define BIT_CP0_PUB_IRAM_B4_PROT_EN				( BIT(8) )
+#define BIT_CP0_PUB_IRAM_B3_PROT_EN				( BIT(7) )
+#define BIT_CP0_PUB_IRAM_B2_PROT_EN				( BIT(6) )
+#define BIT_CP0_PUB_IRAM_B1_PROT_EN				( BIT(5) )
+#define BIT_CP0_PUB_IRAM_B0_PROT_EN				( BIT(4) )
+#define BITS_CP0_ADDR_B8_REMAP(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_AON_APB_CP1_ADDR_REMAP_CTRL0 */
+#define BITS_CP1_ADDR_B7_REMAP(_X_)				( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_CP1_ADDR_B6_REMAP(_X_)				( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_CP1_ADDR_B5_REMAP(_X_)				( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_CP1_ADDR_B4_REMAP(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_CP1_ADDR_B3_REMAP(_X_)				( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_CP1_ADDR_B2_REMAP(_X_)				( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_CP1_ADDR_B1_REMAP(_X_)				( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_CP1_ADDR_B0_REMAP(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_AON_APB_CP1_ADDR_REMAP_CTRL1 */
+#define BIT_CP1_PUB_IRAM_B8_PROT_EN				( BIT(12) )
+#define BIT_CP1_PUB_IRAM_B7_PROT_EN				( BIT(11) )
+#define BIT_CP1_PUB_IRAM_B6_PROT_EN				( BIT(10) )
+#define BIT_CP1_PUB_IRAM_B5_PROT_EN				( BIT(9) )
+#define BIT_CP1_PUB_IRAM_B4_PROT_EN				( BIT(8) )
+#define BIT_CP1_PUB_IRAM_B3_PROT_EN				( BIT(7) )
+#define BIT_CP1_PUB_IRAM_B2_PROT_EN				( BIT(6) )
+#define BIT_CP1_PUB_IRAM_B1_PROT_EN				( BIT(5) )
+#define BIT_CP1_PUB_IRAM_B0_PROT_EN				( BIT(4) )
+#define BITS_CP1_ADDR_B8_REMAP(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_AON_APB_CP2_ADDR_REMAP_CTRL0 */
+#define BITS_CP2_ADDR_B7_REMAP(_X_)				( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_CP2_ADDR_B6_REMAP(_X_)				( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_CP2_ADDR_B5_REMAP(_X_)				( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_CP2_ADDR_B4_REMAP(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_CP2_ADDR_B3_REMAP(_X_)				( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_CP2_ADDR_B2_REMAP(_X_)				( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_CP2_ADDR_B1_REMAP(_X_)				( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_CP2_ADDR_B0_REMAP(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_AON_APB_CP2_ADDR_REMAP_CTRL1 */
+#define BIT_CP2_PUB_IRAM_B8_PROT_EN				( BIT(12) )
+#define BIT_CP2_PUB_IRAM_B7_PROT_EN				( BIT(11) )
+#define BIT_CP2_PUB_IRAM_B6_PROT_EN				( BIT(10) )
+#define BIT_CP2_PUB_IRAM_B5_PROT_EN				( BIT(9) )
+#define BIT_CP2_PUB_IRAM_B4_PROT_EN				( BIT(8) )
+#define BIT_CP2_PUB_IRAM_B3_PROT_EN				( BIT(7) )
+#define BIT_CP2_PUB_IRAM_B2_PROT_EN				( BIT(6) )
+#define BIT_CP2_PUB_IRAM_B1_PROT_EN				( BIT(5) )
+#define BIT_CP2_PUB_IRAM_B0_PROT_EN				( BIT(4) )
+#define BITS_CP2_ADDR_B8_REMAP(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_AON_APB_IO_DLY_CTRL */
+#define BITS_CLK_CCIR_DLY_SEL(_X_)				( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_CLK_CP1DSP_DLY_SEL(_X_)				( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_CLK_CP0DSP_DLY_SEL(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_AON_APB_AP_WPROT_EN */
+#define BITS_AP_AWADDR_WPROT_EN(_X_)				(_X_)
+
+/* bits definitions for register REG_AON_APB_CP0_WPROT_EN */
+#define BITS_CP0_AWADDR_WPROT_EN(_X_)				(_X_)
+
+/* bits definitions for register REG_AON_APB_CP1_WPROT_EN */
+#define BITS_CP1_AWADDR_WPROT_EN(_X_)				(_X_)
+
+/* bits definitions for register REG_AON_APB_CP2_WPROT_EN */
+#define BITS_CP2_AWADDR_WPROT_EN(_X_)				(_X_)
+
+/* bits definitions for register REG_AON_APB_PMU_RST_MONITOR */
+#define BITS_PMU_RST_MONITOR(_X_)				(_X_)
+
+/* bits definitions for register REG_AON_APB_THM_RST_MONITOR */
+#define BITS_THM_RST_MONITOR(_X_)				(_X_)
+
+/* bits definitions for register REG_AON_APB_AP_RST_MONITOR */
+#define BITS_AP_RST_MONITOR(_X_)				(_X_)
+
+/* bits definitions for register REG_AON_APB_CA7_RST_MONITOR */
+#define BITS_CA7_RST_MONITOR(_X_)				(_X_)
+
+/* bits definitions for register REG_AON_APB_BOND_OPT0 */
+#define BITS_BOND_OPTION0(_X_)					(_X_)
+
+/* bits definitions for register REG_AON_APB_BOND_OPT1 */
+#define BITS_BOND_OPTION1(_X_)					(_X_)
+
+/* bits definitions for register REG_AON_APB_RES_REG0 */
+#define BITS_RES_REG0(_X_)					(_X_)
+
+/* bits definitions for register REG_AON_APB_RES_REG1 */
+#define BITS_RES_REG1(_X_)					(_X_)
+
+/* bits definitions for register REG_AON_APB_MPLL_CFG1 */
+#define BITS_MPLL_KINT(_X_)					( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_MPLL_DIV_S						( BIT(10) )
+#define BITS_MPLL_RSV(_X_)					( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BIT_MPLL_MOD_EN						( BIT(7) )
+#define BIT_MPLL_SDM_EN						( BIT(6) )
+#define BITS_MPLL_NINT(_X_)					( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+
+/* bits definitions for register REG_AON_APB_DPLL_CFG1 */
+#define BITS_DPLL_KINT(_X_)					( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_DPLL_DIV_S						( BIT(10) )
+#define BITS_DPLL_RSV(_X_)					( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BIT_DPLL_MOD_EN						( BIT(7) )
+#define BIT_DPLL_SDM_EN						( BIT(6) )
+#define BITS_DPLL_NINT(_X_)					( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+
+/* bits definitions for register REG_AON_APB_TDPLL_CFG1 */
+#define BITS_TDPLL_KINT(_X_)					( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_TDPLL_DIV_S						( BIT(10) )
+#define BITS_TDPLL_RSV(_X_)					( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BIT_TDPLL_MOD_EN					( BIT(7) )
+#define BIT_TDPLL_SDM_EN					( BIT(6) )
+#define BITS_TDPLL_NINT(_X_)					( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+
+/* bits definitions for register REG_AON_APB_CPLL_CFG1 */
+#define BITS_CPLL_KINT(_X_)					( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_CPLL_DIV_S						( BIT(10) )
+#define BITS_CPLL_RSV(_X_)					( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BIT_CPLL_MOD_EN						( BIT(7) )
+#define BIT_CPLL_SDM_EN						( BIT(6) )
+#define BITS_CPLL_NINT(_X_)					( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+
+/* bits definitions for register REG_AON_APB_WIFIPLL1_CFG1 */
+#define BITS_WIFIPLL1_KINT(_X_)					( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_WIFIPLL1_DIV_S					( BIT(10) )
+#define BITS_WIFIPLL1_RSV(_X_)					( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BIT_WIFIPLL1_MOD_EN					( BIT(7) )
+#define BIT_WIFIPLL1_SDM_EN					( BIT(6) )
+#define BITS_WIFIPLL1_NINT(_X_)					( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+
+/* bits definitions for register REG_AON_APB_WIFIPLL2_CFG1 */
+#define BITS_WIFIPLL2_KINT(_X_)					( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_WIFIPLL2_DIV_S					( BIT(10) )
+#define BITS_WIFIPLL2_RSV(_X_)					( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BIT_WIFIPLL2_MOD_EN					( BIT(7) )
+#define BIT_WIFIPLL2_SDM_EN					( BIT(6) )
+#define BITS_WIFIPLL2_NINT(_X_)					( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+
+/* bits definitions for register REG_AON_APB_AON_QOS_CFG */
+#define BITS_QOS_R_GPU(_X_)					( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_QOS_W_GPU(_X_)					( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_QOS_R_GSP(_X_)					( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_QOS_W_GSP(_X_)					( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_AON_APB_BB_LDO_CAL_START */
+#define BIT_BB_LDO_CAL_START					( BIT(0) )
+
+/* bits definitions for register REG_AON_APB_WBT_BG_LDO */
+#define BITS_WBT_BG_RESERVED(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_WBT_RESERVED(_X_)					( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_AON_APB_ANA_BB_MISC */
+#define BITS_ANA_BB_RESERVED(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_AON_APB_DJTAG_MUX_SEL */
+#define BIT_DJTAG_AON_SEL					( BIT(6) )
+#define BIT_DJTAG_PUB_SEL					( BIT(5) )
+#define BIT_DJTAG_CP2_SEL					( BIT(4) )
+#define BIT_DJTAG_CP0_SEL					( BIT(3) )
+#define BIT_DJTAG_GPU_SEL					( BIT(2) )
+#define BIT_DJTAG_MM_SEL					( BIT(1) )
+#define BIT_DJTAG_AP_SEL					( BIT(0) )
+
+/* bits definitions for register REG_AON_APB_BBPLL_RESERVED_0 */
+#define BITS_WPLL_RESERVED(_X_)					( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_TDPLL_RESERVED(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_MPLL_RESERVED(_X_)					( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_CPLL_RESERVED(_X_)					( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_AON_APB_BBPLL_RESERVED_1 */
+#define BITS_LVDSRF_LVPLL_RESERVED(_X_)				( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_RPLL_RESERVED(_X_)					( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_AON_APB_RPLL_CFG0 */
+#define BIT_LVDS_LVPLL_REF_SEL_CTRL				( BIT(10) )
+#define BIT_LVDS_LVPLL_REF_SEL					( BIT(9) )
+#define BITS_RPLL_PD_CTRL(_X_)					( (_X_) << 7 & (BIT(7)|BIT(8)) )
+#define BIT_RPLL_RST_CTRL					( BIT(6) )
+#define BIT_BBPLL_REFCLK_SEL_CTRL				( BIT(5) )
+#define BIT_RPLL_26MTESTOUT_EN					( BIT(4) )
+#define BIT_CLK26MHZ_MUXTUNE_EN					( BIT(3) )
+#define BIT_BBPLL_REFCLK_SEL					( BIT(2) )
+#define BIT_RPLL_RST						( BIT(1) )
+#define BIT_RPLL_PD						( BIT(0) )
+
+/* bits definitions for register REG_AON_APB_AON_DEBUG_CFG */
+#define BITS_AON_DEBUG_SEL(_X_)					( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+#endif
diff --git a/include/soc/sprd/chip_x20/__regs_aon_clk.h b/include/soc/sprd/chip_x20/__regs_aon_clk.h
new file mode 100644
index 00000000..9f93b73c
--- /dev/null
+++ b/include/soc/sprd/chip_x20/__regs_aon_clk.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2012 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+#ifndef __REGS_AON_CLK_H__
+#define __REGS_AON_CLK_H__
+
+#ifndef __SCI_GLB_REGS_H__
+#error  "Don't include this file directly, include <mach/sci_glb_regs.h>"
+#endif
+
+#define REGS_AON_CLK
+
+/* registers definitions for controller REGS_AON_CLK */
+#define REG_AON_CLK_PUB_AHB_CFG         SCI_ADDR(REGS_AON_CLK_BASE, 0x0020)
+#define REG_AON_CLK_EMC_CFG             SCI_ADDR(REGS_AON_CLK_BASE, 0x0024)
+#define REG_AON_CLK_AON_APB_CFG         SCI_ADDR(REGS_AON_CLK_BASE, 0x0028)
+#define REG_AON_CLK_AUDIF_CFG           SCI_ADDR(REGS_AON_CLK_BASE, 0x002c)
+#define REG_AON_CLK_FM_CFG              SCI_ADDR(REGS_AON_CLK_BASE, 0x0030)
+#define REG_AON_CLK_ADI_CFG             SCI_ADDR(REGS_AON_CLK_BASE, 0x0034)
+#define REG_AON_CLK_PWM0_CFG            SCI_ADDR(REGS_AON_CLK_BASE, 0x0038)
+#define REG_AON_CLK_PWM1_CFG            SCI_ADDR(REGS_AON_CLK_BASE, 0x003c)
+#define REG_AON_CLK_PWM2_CFG            SCI_ADDR(REGS_AON_CLK_BASE, 0x0040)
+#define REG_AON_CLK_PWM3_CFG            SCI_ADDR(REGS_AON_CLK_BASE, 0x0044)
+#define REG_AON_CLK_THM_CFG            SCI_ADDR(REGS_AON_CLK_BASE, 0x0048)
+#define REG_AON_CLK_CA7_DAP_CFG         SCI_ADDR(REGS_AON_CLK_BASE, 0x004C)
+#define REG_AON_CLK_CA7_TS_CFG          SCI_ADDR(REGS_AON_CLK_BASE, 0x0050)
+#define REG_AON_CLK_MSPI_CFG            SCI_ADDR(REGS_AON_CLK_BASE, 0x0054)
+#define REG_AON_CLK_I2C_CFG             SCI_ADDR(REGS_AON_CLK_BASE, 0x0058)
+#define REG_AON_CLK_RFTI_SBI_CFG        SCI_ADDR(REGS_AON_CLK_BASE, 0x005C)
+#define REG_AON_CLK_AVS0_CFG            SCI_ADDR(REGS_AON_CLK_BASE, 0x0060)
+#define REG_AON_CLK_AVS1_CFG            SCI_ADDR(REGS_AON_CLK_BASE, 0x0064)
+#define REG_AON_CLK_DJTAG_TCK_CFG       SCI_ADDR(REGS_AON_CLK_BASE, 0x0068)
+
+
+/* vars definitions for controller REGS_AON_CLK */
+
+#endif //__REGS_AON_CLK_H__
diff --git a/include/soc/sprd/chip_x20/__regs_ap_ahb.h b/include/soc/sprd/chip_x20/__regs_ap_ahb.h
new file mode 100644
index 00000000..b300b1a5
--- /dev/null
+++ b/include/soc/sprd/chip_x20/__regs_ap_ahb.h
@@ -0,0 +1,395 @@
+/* the head file modifier:     ang   2015-01-13 20:46:24*/
+
+/*  
+* Copyright (C) 2013 Spreadtrum Communications Inc.  
+*
+* This program is free software; you can redistribute it and/or  
+* modify it under the terms of the GNU General Public License 
+* as published by the Free Software Foundation; either version 2 
+* of the License, or (at your option) any later version.  
+* 
+* This program is distributed in the hope that it will be useful, 
+* but WITHOUT ANY WARRANTY; without even the implied warranty of 
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the  
+* GNU General Public License for more details.  
+* 
+*************************************************  
+* Automatically generated C header: do not edit *  
+*************************************************  
+*/  
+
+#ifndef __SCI_GLB_REGS_H__  
+#error  "Don't include this file directly, Pls include sci_glb_regs.h" 
+#endif 
+
+
+#ifndef __H_REGS_AP_AHB_HEADFILE_H__
+#define __H_REGS_AP_AHB_HEADFILE_H__ __FILE__
+
+#define  REGS_AP_AHB
+
+/* registers definitions for AP_AHB */
+#define REG_AP_AHB_AHB_EB				SCI_ADDR(REGS_AP_AHB_BASE, 0x0000)/*AHB_EB*/
+#define REG_AP_AHB_AHB_RST				SCI_ADDR(REGS_AP_AHB_BASE, 0x0004)/*AHB_RST*/
+#define REG_AP_AHB_CA7_RST_SET				SCI_ADDR(REGS_AP_AHB_BASE, 0x0008)/*CA7_RST_SET*/
+#define REG_AP_AHB_AP_SYS_FORCE_SLEEP_CFG		SCI_ADDR(REGS_AP_AHB_BASE, 0x000C)/*AP_SYS_FORCE_SLEEP_CFG*/
+#define REG_AP_AHB_AP_SYS_AUTO_SLEEP_CFG		SCI_ADDR(REGS_AP_AHB_BASE, 0x0010)/*AP_SYS_AUTO_SLEEP_CFG*/
+#define REG_AP_AHB_HOLDING_PEN				SCI_ADDR(REGS_AP_AHB_BASE, 0x0014)/*HOLDING_PEN*/
+#define REG_AP_AHB_JMP_ADDR_CA7_C0			SCI_ADDR(REGS_AP_AHB_BASE, 0x0018)/*JMP_ADDR_CA7_C0*/
+#define REG_AP_AHB_JMP_ADDR_CA7_C1			SCI_ADDR(REGS_AP_AHB_BASE, 0x001C)/*JMP_ADDR_CA7_C1*/
+#define REG_AP_AHB_JMP_ADDR_CA7_C2			SCI_ADDR(REGS_AP_AHB_BASE, 0x0020)/*JMP_ADDR_CA7_C2*/
+#define REG_AP_AHB_JMP_ADDR_CA7_C3			SCI_ADDR(REGS_AP_AHB_BASE, 0x0024)/*JMP_ADDR_CA7_C3*/
+#define REG_AP_AHB_CA7_C0_PU_LOCK			SCI_ADDR(REGS_AP_AHB_BASE, 0x0028)/*CA7_C0_PU_LOCK*/
+#define REG_AP_AHB_CA7_C1_PU_LOCK			SCI_ADDR(REGS_AP_AHB_BASE, 0x002C)/*CA7_C1_PU_LOCK*/
+#define REG_AP_AHB_CA7_C2_PU_LOCK			SCI_ADDR(REGS_AP_AHB_BASE, 0x0030)/*CA7_C2_PU_LOCK*/
+#define REG_AP_AHB_CA7_C3_PU_LOCK			SCI_ADDR(REGS_AP_AHB_BASE, 0x0034)/*CA7_C3_PU_LOCK*/
+#define REG_AP_AHB_CA7_CKG_CFG				SCI_ADDR(REGS_AP_AHB_BASE, 0x3000)/*CA7_CKG_CFG*/
+#define REG_AP_AHB_MCU_PAUSE				SCI_ADDR(REGS_AP_AHB_BASE, 0x3004)/*MCU_PAUSE*/
+#define REG_AP_AHB_MISC_CKG_EN				SCI_ADDR(REGS_AP_AHB_BASE, 0x3008)/*MISC_CKG_EN*/
+#define REG_AP_AHB_MISC_CFG				SCI_ADDR(REGS_AP_AHB_BASE, 0x300C)/*MISC_CFG*/
+#define REG_AP_AHB_AP_MTX_S3_PRIO0			SCI_ADDR(REGS_AP_AHB_BASE, 0x3010)/*AP_MTX_S3_PRIO0*/
+#define REG_AP_AHB_AP_MTX_S3_PRIO1			SCI_ADDR(REGS_AP_AHB_BASE, 0x3014)/*AP_MTX_S3_PRIO1*/
+#define REG_AP_AHB_AP_MTX_S3_PRIO2			SCI_ADDR(REGS_AP_AHB_BASE, 0x3018)/*AP_MTX_S3_PRIO2*/
+#define REG_AP_AHB_AP_MTX_S2_PRIO0			SCI_ADDR(REGS_AP_AHB_BASE, 0x301C)/*AP_MTX_S2_PRIO0*/
+#define REG_AP_AHB_AP_MTX_S1_PRIO0			SCI_ADDR(REGS_AP_AHB_BASE, 0x3020)/*AP_MTX_S1_PRIO0*/
+#define REG_AP_AHB_AP_MTX_S0_PRIO0			SCI_ADDR(REGS_AP_AHB_BASE, 0x3024)/*AP_MTX_S0_PRIO0*/
+#define REG_AP_AHB_AP_MTX_S0_PRIO1			SCI_ADDR(REGS_AP_AHB_BASE, 0x3028)/*AP_MTX_S0_PRIO1*/
+#define REG_AP_AHB_AP_MTX_S0_PRIO2			SCI_ADDR(REGS_AP_AHB_BASE, 0x302C)/*AP_MTX_S0_PRIO2*/
+#define REG_AP_AHB_AP_MAIN_MTX_HPROT_CFG		SCI_ADDR(REGS_AP_AHB_BASE, 0x3030)/*AP_MAIN_MTX_HPROT_CFG*/
+#define REG_AP_AHB_CA7_STANDBY_STATUS			SCI_ADDR(REGS_AP_AHB_BASE, 0x3034)/*CA7_STANDBY_STATUS*/
+#define REG_AP_AHB_NANC_CLK_CFG				SCI_ADDR(REGS_AP_AHB_BASE, 0x3038)/*NANDC_CLK_CFG*/
+#define REG_AP_AHB_LVDS_CFG				SCI_ADDR(REGS_AP_AHB_BASE, 0x303C)/*LVDS_CFG*/
+#define REG_AP_AHB_LVDS_PLL_CFG0			SCI_ADDR(REGS_AP_AHB_BASE, 0x3040)/*LVDS_PLL_CFG0*/
+#define REG_AP_AHB_LVDS_PLL_CFG1			SCI_ADDR(REGS_AP_AHB_BASE, 0x3044)/*LVDS_PLL_CFG1*/
+#define REG_AP_AHB_CA7_C0_AUTO_FORCE_SHUTDOWN_EN	SCI_ADDR(REGS_AP_AHB_BASE, 0x3048)/*CA7_C0_AUTO_FORCE_SHUTDOWN_EN*/
+#define REG_AP_AHB_CA7_C1_AUTO_FORCE_SHUTDOWN_EN	SCI_ADDR(REGS_AP_AHB_BASE, 0x304C)/*CA7_C1_AUTO_FORCE_SHUTDOWN_EN*/
+#define REG_AP_AHB_CA7_C2_AUTO_FORCE_SHUTDOWN_EN	SCI_ADDR(REGS_AP_AHB_BASE, 0x3050)/*CA7_C2_AUTO_FORCE_SHUTDOWN_EN*/
+#define REG_AP_AHB_CA7_C3_AUTO_FORCE_SHUTDOWN_EN	SCI_ADDR(REGS_AP_AHB_BASE, 0x3054)/*CA7_C3_AUTO_FORCE_SHUTDOWN_EN*/
+#define REG_AP_AHB_AP_QOS_CFG				SCI_ADDR(REGS_AP_AHB_BASE, 0x3058)/*AP_QOS_CFG*/
+#define REG_AP_AHB_CHIP_ID				SCI_ADDR(REGS_AP_AHB_BASE, 0x30FC)/*CHIP_ID*/
+
+
+
+/* bits definitions for register REG_AP_AHB_AHB_EB */
+#define BIT_LVDS_EB						( BIT(22) )
+#define BIT_ZIPDEC_EB						( BIT(21) )
+#define BIT_ZIPENC_EB						( BIT(20) )
+#define BIT_NANDC_ECC_EB					( BIT(19) )
+#define BIT_NANDC_2X_EB						( BIT(18) )
+#define BIT_NANDC_EB						( BIT(17) )
+#define BIT_BUSMON2_EB						( BIT(16) )
+#define BIT_BUSMON1_EB						( BIT(15) )
+#define BIT_BUSMON0_EB						( BIT(14) )
+#define BIT_SPINLOCK_EB						( BIT(13) )
+#define BIT_GPS_EB						( BIT(12) )
+#define BIT_EMMC_EB						( BIT(11) )
+#define BIT_SDIO2_EB						( BIT(10) )
+#define BIT_SDIO1_EB						( BIT(9) )
+#define BIT_SDIO0_EB						( BIT(8) )
+#define BIT_DRM_EB						( BIT(7) )
+#define BIT_NFC_EB						( BIT(6) )
+#define BIT_DMA_EB						( BIT(5) )
+#define BIT_USB_EB						( BIT(4) )
+#define BIT_GSP_EB						( BIT(3) )
+#define BIT_DISPC1_EB						( BIT(2) )
+#define BIT_DISPC0_EB						( BIT(1) )
+#define BIT_DSI_EB						( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_AHB_RST */
+#define BIT_LVDS_SOFT_RST					( BIT(25) )
+#define BIT_ZIP_MTX_SOFT_RST					( BIT(24) )
+#define BIT_ZIPDEC_SOFT_RST					( BIT(23) )
+#define BIT_ZIPENC_SOFT_RST					( BIT(22) )
+#define BIT_NANDC_SOFT_RST					( BIT(20) )
+#define BIT_BUSMON2_SOFT_RST					( BIT(19) )
+#define BIT_BUSMON1_SOFT_RST					( BIT(18) )
+#define BIT_BUSMON0_SOFT_RST					( BIT(17) )
+#define BIT_SPINLOCK_SOFT_RST					( BIT(16) )
+#define BIT_GPS_SOFT_RST					( BIT(15) )
+#define BIT_EMMC_SOFT_RST					( BIT(14) )
+#define BIT_SDIO2_SOFT_RST					( BIT(13) )
+#define BIT_SDIO1_SOFT_RST					( BIT(12) )
+#define BIT_SDIO0_SOFT_RST					( BIT(11) )
+#define BIT_DRM_SOFT_RST					( BIT(10) )
+#define BIT_NFC_SOFT_RST					( BIT(9) )
+#define BIT_DMA_SOFT_RST					( BIT(8) )
+#define BIT_USB_PHY_SOFT_RST					( BIT(7) )
+#define BIT_USB_UTMI_SOFT_RST					( BIT(6) )
+#define BIT_USB_SOFT_RST					( BIT(5) )
+#define BIT_DISP_MTX_SOFT_RST					( BIT(4) )
+#define BIT_GSP_SOFT_RST					( BIT(3) )
+#define BIT_DISPC1_SOFT_RST					( BIT(2) )
+#define BIT_DISPC0_SOFT_RST					( BIT(1) )
+#define BIT_DSI_SOFT_RST					( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_CA7_RST_SET */
+#define BIT_CA7_CS_DBG_SOFT_RST					( BIT(14) )
+#define BIT_CA7_L2_SOFT_RST					( BIT(13) )
+#define BIT_CA7_SOCDBG_SOFT_RST					( BIT(12) )
+#define BITS_CA7_ETM_SOFT_RST(_X_)				( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_CA7_DBG_SOFT_RST(_X_)				( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_CA7_CORE_SOFT_RST(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_AP_AHB_AP_SYS_FORCE_SLEEP_CFG */
+#define BIT_AP_PERI_FORCE_ON					( BIT(2) )
+#define BIT_AP_PERI_FORCE_SLP					( BIT(1) )
+#define BIT_AP_APB_SLEEP					( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_AP_SYS_AUTO_SLEEP_CFG */
+#define BIT_GSP_CKG_FORCE_EN					( BIT(9) )
+#define BIT_GSP_AUTO_GATE_EN					( BIT(8) )
+#define BIT_AP_AHB_AUTO_GATE_EN					( BIT(5) )
+#define BIT_AP_EMC_AUTO_GATE_EN					( BIT(4) )
+#define BIT_CA7_EMC_AUTO_GATE_EN				( BIT(3) )
+#define BIT_CA7_DBG_FORCE_SLEEP					( BIT(2) )
+#define BIT_CA7_DBG_AUTO_GATE_EN				( BIT(1) )
+#define BIT_CA7_CORE_AUTO_GATE_EN				( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_HOLDING_PEN */
+#define BITS_HOLDING_PEN(_X_)					(_X_)
+
+/* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C0 */
+#define BITS_JMP_ADDR_CA7_C0(_X_)				(_X_)
+
+/* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C1 */
+#define BITS_JMP_ADDR_CA7_C1(_X_)				(_X_)
+
+/* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C2 */
+#define BITS_JMP_ADDR_CA7_C2(_X_)				(_X_)
+
+/* bits definitions for register REG_AP_AHB_JMP_ADDR_CA7_C3 */
+#define BITS_JMP_ADDR_CA7_C3(_X_)				(_X_)
+
+/* bits definitions for register REG_AP_AHB_CA7_C0_PU_LOCK */
+#define BIT_CA7_C0_PU_LOCK					( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_CA7_C1_PU_LOCK */
+#define BIT_CA7_C1_PU_LOCK					( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_CA7_C2_PU_LOCK */
+#define BIT_CA7_C2_PU_LOCK					( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_CA7_C3_PU_LOCK */
+#define BIT_CA7_C3_PU_LOCK					( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_CA7_CKG_CFG */
+#define BITS_CA7_DBG_CKG_DIV(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)) )
+#define BITS_CA7_AXI_CKG_DIV(_X_)				( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) )
+#define BITS_CA7_MCU_CKG_DIV(_X_)				( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) )
+#define BITS_CA7_MCU_CKG_SEL(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
+
+/* bits definitions for register REG_AP_AHB_MCU_PAUSE */
+#define BIT_DMA_ACT_LIGHT_EN					( BIT(5) )
+#define BIT_MCU_SLEEP_FOLLOW_CA7_EN				( BIT(4) )
+#define BIT_MCU_LIGHT_SLEEP_EN					( BIT(3) )
+#define BIT_MCU_DEEP_SLEEP_EN					( BIT(2) )
+#define BIT_MCU_SYS_SLEEP_EN					( BIT(1) )
+#define BIT_MCU_CORE_SLEEP					( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_MISC_CKG_EN */
+#define BIT_GPS_TCXO_INV_SEL					( BIT(13) )
+#define BIT_GPS_26M_INV_SEL					( BIT(12) )
+#define BIT_ASHB_CA7_DBG_VLD					( BIT(9) )
+#define BIT_ASHB_CA7_DBG_EN					( BIT(8) )
+#define BIT_DISP_TMC_CKG_EN					( BIT(4) )
+#define BIT_DPHY_REF_CKG_EN					( BIT(1) )
+#define BIT_DPHY_CFG_CKG_EN					( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_MISC_CFG */
+#define BITS_EMMC_SLOT_SEL(_X_)					( (_X_) << 18 & (BIT(18)|BIT(19)) )
+#define BITS_SDIO0_SLOT_SEL(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_BUSMON2_CHN_SEL(_X_)				( (_X_) << 10 & (BIT(10)|BIT(11)) )
+#define BITS_BUSMON1_CHN_SEL(_X_)				( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BIT_BUSMON0_CHN_SEL					( BIT(4) )
+#define BITS_SDIO2_SLOT_SEL(_X_)				( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_SDIO1_SLOT_SEL(_X_)				( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_AP_AHB_AP_MTX_S3_PRIO0 */
+#define BITS_PRI_M6TOS3_RND_THR(_X_)				( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_PRI_M6TOS3_SEL(_X_)				( (_X_) << 26 & (BIT(26)|BIT(27)) )
+#define BIT_PRI_M6TOS3_RND_EN					( BIT(25) )
+#define BIT_PRI_M6TOS3_ADJ_EN					( BIT(24) )
+#define BITS_PRI_M7TOS3_RND_THR(_X_)				( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PRI_M7TOS3_SEL(_X_)				( (_X_) << 18 & (BIT(18)|BIT(19)) )
+#define BIT_PRI_M7TOS3_RND_EN					( BIT(17) )
+#define BIT_PRI_M7TOS3_ADJ_EN					( BIT(16) )
+#define BITS_PRI_M8TOS3_RND_THR(_X_)				( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PRI_M8TOS3_SEL(_X_)				( (_X_) << 10 & (BIT(10)|BIT(11)) )
+#define BIT_PRI_M8TOS3_RND_EN					( BIT(9) )
+#define BIT_PRI_M8TOS3_ADJ_EN					( BIT(8) )
+#define BITS_PRI_M9TOS3_RND_THR(_X_)				( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_PRI_M9TOS3_SEL(_X_)				( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BIT_PRI_M9TOS3_RND_EN					( BIT(1) )
+#define BIT_PRI_M9TOS3_ADJ_EN					( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_AP_MTX_S3_PRIO1 */
+#define BITS_PRI_M2TOS3_RND_THR(_X_)				( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_PRI_M2TOS3_SEL(_X_)				( (_X_) << 26 & (BIT(26)|BIT(27)) )
+#define BIT_PRI_M2TOS3_RND_EN					( BIT(25) )
+#define BIT_PRI_M2TOS3_ADJ_EN					( BIT(24) )
+#define BITS_PRI_M3TOS3_RND_THR(_X_)				( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PRI_M3TOS3_SEL(_X_)				( (_X_) << 18 & (BIT(18)|BIT(19)) )
+#define BIT_PRI_M3TOS3_RND_EN					( BIT(17) )
+#define BIT_PRI_M3TOS3_ADJ_EN					( BIT(16) )
+#define BITS_PRI_M4TOS3_RND_THR(_X_)				( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PRI_M4TOS3_SEL(_X_)				( (_X_) << 10 & (BIT(10)|BIT(11)) )
+#define BIT_PRI_M4TOS3_RND_EN					( BIT(9) )
+#define BIT_PRI_M4TOS3_ADJ_EN					( BIT(8) )
+#define BITS_PRI_M5TOS3_RND_THR(_X_)				( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_PRI_M5TOS3_SEL(_X_)				( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BIT_PRI_M5TOS3_RND_EN					( BIT(1) )
+#define BIT_PRI_M5TOS3_ADJ_EN					( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_AP_MTX_S3_PRIO2 */
+#define BITS_PRI_M0TOS3_RND_THR(_X_)				( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_PRI_M0TOS3_SEL(_X_)				( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BIT_PRI_M0TOS3_RND_EN					( BIT(1) )
+#define BIT_PRI_M0TOS3_ADJ_EN					( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_AP_MTX_S2_PRIO0 */
+#define BITS_PRI_M0TOS2_RND_THR(_X_)				( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_PRI_M0TOS2_SEL(_X_)				( (_X_) << 26 & (BIT(26)|BIT(27)) )
+#define BIT_PRI_M0TOS2_RND_EN					( BIT(25) )
+#define BIT_PRI_M0TOS2_ADJ_EN					( BIT(24) )
+#define BITS_PRI_M1TOS2_RND_THR(_X_)				( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PRI_M1TOS2_SEL(_X_)				( (_X_) << 18 & (BIT(18)|BIT(19)) )
+#define BIT_PRI_M1TOS2_RND_EN					( BIT(17) )
+#define BIT_PRI_M1TOS2_ADJ_EN					( BIT(16) )
+#define BITS_PRI_M2TOS2_RND_THR(_X_)				( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PRI_M2TOS2_SEL(_X_)				( (_X_) << 10 & (BIT(10)|BIT(11)) )
+#define BIT_PRI_M2TOS2_RND_EN					( BIT(9) )
+#define BIT_PRI_M2TOS2_ADJ_EN					( BIT(8) )
+#define BITS_PRI_M3TOS2_RND_THR(_X_)				( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_PRI_M3TOS2_SEL(_X_)				( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BIT_PRI_M3TOS2_RND_EN					( BIT(1) )
+#define BIT_PRI_M3TOS2_ADJ_EN					( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_AP_MTX_S1_PRIO0 */
+#define BITS_PRI_M0TOS1_RND_THR(_X_)				( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_PRI_M0TOS1_SEL(_X_)				( (_X_) << 26 & (BIT(26)|BIT(27)) )
+#define BIT_PRI_M0TOS1_RND_EN					( BIT(25) )
+#define BIT_PRI_M0TOS1_ADJ_EN					( BIT(24) )
+#define BITS_PRI_M2TOS1_RND_THR(_X_)				( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PRI_M2TOS1_SEL(_X_)				( (_X_) << 18 & (BIT(18)|BIT(19)) )
+#define BIT_PRI_M2TOS1_RND_EN					( BIT(17) )
+#define BIT_PRI_M2TOS1_ADJ_EN					( BIT(16) )
+#define BITS_PRI_M3TOS1_RND_THR(_X_)				( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PRI_M3TOS1_SEL(_X_)				( (_X_) << 10 & (BIT(10)|BIT(11)) )
+#define BIT_PRI_M3TOS1_RND_EN					( BIT(9) )
+#define BIT_PRI_M3TOS1_ADJ_EN					( BIT(8) )
+#define BITS_PRI_M8TOS1_RND_THR(_X_)				( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_PRI_M8TOS1_SEL(_X_)				( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BIT_PRI_M8TOS1_RND_EN					( BIT(1) )
+#define BIT_PRI_M8TOS1_ADJ_EN					( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_AP_MTX_S0_PRIO0 */
+#define BITS_PRI_M0TOS0_RND_THR(_X_)				( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_PRI_M0TOS0_SEL(_X_)				( (_X_) << 26 & (BIT(26)|BIT(27)) )
+#define BIT_PRI_M0TOS0_RND_EN					( BIT(25) )
+#define BIT_PRI_M0TOS0_ADJ_EN					( BIT(24) )
+#define BITS_PRI_M1TOS0_RND_THR(_X_)				( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PRI_M1TOS0_SEL(_X_)				( (_X_) << 18 & (BIT(18)|BIT(19)) )
+#define BIT_PRI_M1TOS0_RND_EN					( BIT(17) )
+#define BIT_PRI_M1TOS0_ADJ_EN					( BIT(16) )
+#define BITS_PRI_M2TOS0_RND_THR(_X_)				( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PRI_M2TOS0_SEL(_X_)				( (_X_) << 10 & (BIT(10)|BIT(11)) )
+#define BIT_PRI_M2TOS0_RND_EN					( BIT(9) )
+#define BIT_PRI_M2TOS0_ADJ_EN					( BIT(8) )
+#define BITS_PRI_M3TOS0_RND_THR(_X_)				( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_PRI_M3TOS0_SEL(_X_)				( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BIT_PRI_M3TOS0_RND_EN					( BIT(1) )
+#define BIT_PRI_M3TOS0_ADJ_EN					( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_AP_MTX_S0_PRIO1 */
+#define BITS_PRI_M4TOS1_RND_THR(_X_)				( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_PRI_M4TOS1_SEL(_X_)				( (_X_) << 26 & (BIT(26)|BIT(27)) )
+#define BIT_PRI_M4TOS1_RND_EN					( BIT(25) )
+#define BIT_PRI_M4TOS1_ADJ_EN					( BIT(24) )
+#define BITS_PRI_M5TOS1_RND_THR(_X_)				( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PRI_M5TOS1_SEL(_X_)				( (_X_) << 18 & (BIT(18)|BIT(19)) )
+#define BIT_PRI_M5TOS1_RND_EN					( BIT(17) )
+#define BIT_PRI_M5TOS1_ADJ_EN					( BIT(16) )
+#define BITS_PRI_M6TOS1_RND_THR(_X_)				( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PRI_M6TOS1_SEL(_X_)				( (_X_) << 10 & (BIT(10)|BIT(11)) )
+#define BIT_PRI_M6TOS1_RND_EN					( BIT(9) )
+#define BIT_PRI_M6TOS1_ADJ_EN					( BIT(8) )
+#define BITS_PRI_M7TOS1_RND_THR(_X_)				( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_PRI_M7TOS1_SEL(_X_)				( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BIT_PRI_M7TOS1_RND_EN					( BIT(1) )
+#define BIT_PRI_M7TOS1_ADJ_EN					( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_AP_MTX_S0_PRIO2 */
+#define BITS_PRI_M9TOS1_RND_THR(_X_)				( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_PRI_M9TOS1_SEL(_X_)				( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BIT_PRI_M9TOS1_RND_EN					( BIT(1) )
+#define BIT_PRI_M9TOS1_ADJ_EN					( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_AP_MAIN_MTX_HPROT_CFG */
+#define BITS_HPROT_NFC(_X_)					( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_HPROT_EMMC(_X_)					( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_HPROT_SDIO2(_X_)					( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_HPROT_SDIO1(_X_)					( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_HPROT_SDIO0(_X_)					( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_HPROT_DMAW(_X_)					( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_HPROT_DMAR(_X_)					( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_AP_AHB_CA7_STANDBY_STATUS */
+#define BIT_CA7_STANDBYWFIL2					( BIT(12) )
+#define BITS_CA7_ETMSTANDBYWFX(_X_)				( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_CA7_STANDBYWFE(_X_)				( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_CA7_STANDBYWFI(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_AP_AHB_NANC_CLK_CFG */
+#define BITS_CLK_NANDC_SEL(_X_)					( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_CLK_NANDC2X_DIV(_X_)				( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_CLK_NANDC2X_SEL(_X_)				( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_AP_AHB_LVDS_CFG */
+#define BITS_LVDS_TXCLKDATA(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)) )
+#define BITS_LVDS_TXCOM(_X_)					( (_X_) << 12 & (BIT(12)|BIT(13)) )
+#define BITS_LVDS_TXSLEW(_X_)					( (_X_) << 10 & (BIT(10)|BIT(11)) )
+#define BITS_LVDS_TXSW(_X_)					( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_LVDS_TXRERSER(_X_)					( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_LVDS_PRE_EMP(_X_)					( (_X_) << 1 & (BIT(1)|BIT(2)) )
+#define BIT_LVDS_TXPD						( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_LVDS_PLL_CFG0 */
+#define BIT_LPLL_LOCK_DET					( BIT(31) )
+#define BITS_LPLL_POST_DIV(_X_)					( (_X_) << 26 & (BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
+#define BITS_LPLL_REFIN(_X_)					( (_X_) << 24 & (BIT(24)|BIT(25)) )
+#define BITS_LPLL_LPF(_X_)					( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
+#define BIT_LPLL_DIV_S						( BIT(18) )
+#define BITS_LPLL_IBIAS(_X_)					( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_LPLLN(_X_)						( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
+
+/* bits definitions for register REG_AP_AHB_LVDS_PLL_CFG1 */
+#define BITS_LPLL_KINT(_X_)					( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_LPLL_RSV(_X_)					( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BIT_LPLL_MOD_EN						( BIT(7) )
+#define BIT_LPLL_SDM_EN						( BIT(6) )
+#define BITS_LPLL_NINT(_X_)					( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+
+/* bits definitions for register REG_AP_AHB_CA7_C0_AUTO_FORCE_SHUTDOWN_EN */
+#define BIT_CA7_C0_AUTO_FORCE_SHUTDOWN_EN			( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_CA7_C1_AUTO_FORCE_SHUTDOWN_EN */
+#define BIT_CA7_C1_AUTO_FORCE_SHUTDOWN_EN			( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_CA7_C2_AUTO_FORCE_SHUTDOWN_EN */
+#define BIT_CA7_C2_AUTO_FORCE_SHUTDOWN_EN			( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_CA7_C3_AUTO_FORCE_SHUTDOWN_EN */
+#define BIT_CA7_C3_AUTO_FORCE_SHUTDOWN_EN			( BIT(0) )
+
+/* bits definitions for register REG_AP_AHB_AP_QOS_CFG */
+#define BITS_QOS_R_TMC(_X_)					( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_QOS_W_TMC(_X_)					( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_QOS_R_DISPC1(_X_)					( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_QOS_W_DISPC1(_X_)					( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_QOS_R_DISPC0(_X_)					( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_QOS_W_DISPC0(_X_)					( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_AP_AHB_CHIP_ID */
+#define BITS_CHIP_ID(_X_)					(_X_)
+
+#endif
diff --git a/include/soc/sprd/chip_x20/__regs_ap_apb.h b/include/soc/sprd/chip_x20/__regs_ap_apb.h
new file mode 100644
index 00000000..7e35a991
--- /dev/null
+++ b/include/soc/sprd/chip_x20/__regs_ap_apb.h
@@ -0,0 +1,148 @@
+/* the head file modifier:     ang   2015-01-13 20:47:26*/
+
+/*  
+* Copyright (C) 2013 Spreadtrum Communications Inc.  
+*
+* This program is free software; you can redistribute it and/or  
+* modify it under the terms of the GNU General Public License 
+* as published by the Free Software Foundation; either version 2 
+* of the License, or (at your option) any later version.  
+* 
+* This program is distributed in the hope that it will be useful, 
+* but WITHOUT ANY WARRANTY; without even the implied warranty of 
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the  
+* GNU General Public License for more details.  
+* 
+*************************************************  
+* Automatically generated C header: do not edit *  
+*************************************************  
+*/  
+
+#ifndef __SCI_GLB_REGS_H__  
+#error  "Don't include this file directly, Pls include sci_glb_regs.h" 
+#endif 
+
+
+#ifndef __H_REGS_AP_APB_HEADFILE_H__
+#define __H_REGS_AP_APB_HEADFILE_H__ __FILE__
+
+#define  REGS_AP_APB
+
+/* registers definitions for AP_APB */
+#define REG_AP_APB_APB_EB				SCI_ADDR(REGS_AP_APB_BASE, 0x0000)/*AHB_EB*/
+#define REG_AP_APB_APB_RST				SCI_ADDR(REGS_AP_APB_BASE, 0x0004)/*AHB_RST*/
+#define REG_AP_APB_USB_CTRL0				SCI_ADDR(REGS_AP_APB_BASE, 0x0010)/*USB_PHY_TUNE*/
+#define REG_AP_APB_USB_CTRL1				SCI_ADDR(REGS_AP_APB_BASE, 0x0014)/*USB_PHY_TUNE*/
+#define REG_AP_APB_LVDS_DISP_CTRL0			SCI_ADDR(REGS_AP_APB_BASE, 0x0018)/*MISC_CKG_EN*/
+#define REG_AP_APB_USB_PHY_TEST				SCI_ADDR(REGS_AP_APB_BASE, 0x3004)/*MISC_CKG_EN*/
+#define REG_AP_APB_USB_PHY_CTRL				SCI_ADDR(REGS_AP_APB_BASE, 0x3008)/*USB_PHY_CTRL*/
+#define REG_AP_APB_APB_MISC_CTRL			SCI_ADDR(REGS_AP_APB_BASE, 0x300C)/*APB_MISC_CTRL*/
+
+
+
+/* bits definitions for register REG_AP_APB_APB_EB */
+#define BIT_INTC3_EB						( BIT(22) )
+#define BIT_INTC2_EB						( BIT(21) )
+#define BIT_INTC1_EB						( BIT(20) )
+#define BIT_INTC0_EB						( BIT(19) )
+#define BIT_AP_CKG_EB                                        ( BIT(18) )
+#define BIT_UART4_EB						( BIT(17) )
+#define BIT_UART3_EB						( BIT(16) )
+#define BIT_UART2_EB						( BIT(15) )
+#define BIT_UART1_EB						( BIT(14) )
+#define BIT_UART0_EB						( BIT(13) )
+#define BIT_I2C4_EB						( BIT(12) )
+#define BIT_I2C3_EB						( BIT(11) )
+#define BIT_I2C2_EB						( BIT(10) )
+#define BIT_I2C1_EB						( BIT(9) )
+#define BIT_I2C0_EB						( BIT(8) )
+#define BIT_SPI2_EB						( BIT(7) )
+#define BIT_SPI1_EB						( BIT(6) )
+#define BIT_SPI0_EB						( BIT(5) )
+#define BIT_IIS3_EB						( BIT(4) )
+#define BIT_IIS2_EB						( BIT(3) )
+#define BIT_IIS1_EB						( BIT(2) )
+#define BIT_IIS0_EB						( BIT(1) )
+#define BIT_SIM0_EB						( BIT(0) )
+
+/* bits definitions for register REG_AP_APB_APB_RST */
+#define BIT_INTC3_SOFT_RST					( BIT(22) )
+#define BIT_INTC2_SOFT_RST					( BIT(21) )
+#define BIT_INTC1_SOFT_RST					( BIT(20) )
+#define BIT_INTC0_SOFT_RST					( BIT(19) )
+#define BIT_CKG_SOFT_RST					( BIT(18) )
+#define BIT_UART4_SOFT_RST					( BIT(17) )
+#define BIT_UART3_SOFT_RST					( BIT(16) )
+#define BIT_UART2_SOFT_RST					( BIT(15) )
+#define BIT_UART1_SOFT_RST					( BIT(14) )
+#define BIT_UART0_SOFT_RST					( BIT(13) )
+#define BIT_I2C4_SOFT_RST					( BIT(12) )
+#define BIT_I2C3_SOFT_RST					( BIT(11) )
+#define BIT_I2C2_SOFT_RST					( BIT(10) )
+#define BIT_I2C1_SOFT_RST					( BIT(9) )
+#define BIT_I2C0_SOFT_RST					( BIT(8) )
+#define BIT_SPI2_SOFT_RST					( BIT(7) )
+#define BIT_SPI1_SOFT_RST					( BIT(6) )
+#define BIT_SPI0_SOFT_RST					( BIT(5) )
+#define BIT_IIS3_SOFT_RST					( BIT(4) )
+#define BIT_IIS2_SOFT_RST					( BIT(3) )
+#define BIT_IIS1_SOFT_RST					( BIT(2) )
+#define BIT_IIS0_SOFT_RST					( BIT(1) )
+#define BIT_SIM0_SOFT_RST					( BIT(0) )
+
+/* bits definitions for register REG_AP_APB_USB_CTRL0 */
+#define BITS_USB20_TUNEHSAMP(_X_)				( (_X_) << 30 & (BIT(30)|BIT(31)) )
+#define BITS_USB20_TUNEPLLS(_X_)				( (_X_) << 28 & (BIT(28)|BIT(29)) )
+#define BITS_USB20_TUNERISE(_X_)				( (_X_) << 26 & (BIT(26)|BIT(27)) )
+#define BITS_USB20_TUNESQ(_X_)					( (_X_) << 23 & (BIT(23)|BIT(24)|BIT(25)) )
+#define BITS_USB20_TUNEDSC(_X_)					( (_X_) << 21 & (BIT(21)|BIT(22)) )
+#define BITS_USB20_TUNEOTG(_X_)					( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) )
+#define BIT_USB20_TXBITSTUFFENABLE				( BIT(17) )
+#define BIT_USB20_TXBITSTUFFENABLEH				( BIT(16) )
+#define BITS_USB20_RESERVED(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_AP_APB_USB_CTRL1 */
+#define BIT_HSIC_PLLON						( BIT(16) )
+#define BIT_USB20_REXTENABLE					( BIT(15) )
+#define BIT_USB20_S_ID						( BIT(14) )
+#define BITS_USB20_TF12KRES(_X_)				( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
+#define BITS_USB20_TFHSRES(_X_)					( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_USB20_TUNEEQ(_X_)					( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
+
+/* bits definitions for register REG_AP_APB_LVDS_DISP_CTRL0 */
+#define BIT_LVDSDIS_OFF_CL					( BIT(14) )
+#define BIT_LVDSDIS_OFF_OCT					( BIT(13) )
+#define BITS_LVDSDIS_TXPD(_X_)					( (_X_) << 7 & (BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
+#define BITS_LVDSDIS_TXIMP(_X_)					( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) )
+#define BITS_LVDSDIS_TXRESERVED(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_AP_APB_USB_PHY_TEST */
+#define BIT_ATERESET						( BIT(31) )
+#define BIT_VBUS_VALID_EXT_SEL					( BIT(26) )
+#define BIT_VBUS_VALID_EXT					( BIT(25) )
+#define BIT_OTGDISABLE						( BIT(24) )
+#define BIT_TESTBURNIN						( BIT(21) )
+#define BIT_LOOPBACKENB						( BIT(20) )
+#define BITS_TESTDATAOUT(_X_)					( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_VATESTENB(_X_)					( (_X_) << 14 & (BIT(14)|BIT(15)) )
+#define BIT_TESTCLK						( BIT(13) )
+#define BIT_TESTDATAOUTSEL					( BIT(12) )
+#define BITS_TESTADDR(_X_)					( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_TESTDATAIN(_X_)					( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_AP_APB_USB_PHY_CTRL */
+#define BITS_SS_SCALEDOWNMODE(_X_)				( (_X_) << 25 & (BIT(25)|BIT(26)) )
+#define BIT_TXBITSTUFFENH					( BIT(23) )
+#define BIT_TXBITSTUFFEN					( BIT(22) )
+#define BIT_DMPULLDOWN						( BIT(21) )
+#define BIT_DPPULLDOWN						( BIT(20) )
+#define BIT_DMPULLUP						( BIT(9) )
+#define BIT_COMMONONN						( BIT(8) )
+#define BITS_REFCLKSEL(_X_)					( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_FSEL(_X_)						( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
+
+/* bits definitions for register REG_AP_APB_APB_MISC_CTRL */
+#define BIT_SIM_CLK_POLARITY					( BIT(1) )
+#define BIT_FMARK_POLARITY_INV					( BIT(0) )
+
+#endif
diff --git a/include/soc/sprd/chip_x20/__regs_ap_clk.h b/include/soc/sprd/chip_x20/__regs_ap_clk.h
new file mode 100644
index 00000000..379b3de0
--- /dev/null
+++ b/include/soc/sprd/chip_x20/__regs_ap_clk.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2012 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+#ifndef __REGS_AP_CLK_H__
+#define __REGS_AP_CLK_H__
+
+#ifndef __SCI_GLB_REGS_H__
+#error  "Don't include this file directly, include <mach/sci_glb_regs.h>"
+#endif
+
+#define REGS_AP_CLK
+
+/* registers definitions for controller REGS_AP_CLK */
+#define REG_AP_CLK_AP_AHB_CFG           SCI_ADDR(REGS_AP_CLK_BASE, 0x0020)
+#define REG_AP_CLK_AP_APB_CFG           SCI_ADDR(REGS_AP_CLK_BASE, 0x0024)
+#define REG_AP_CLK_GSP_CFG              SCI_ADDR(REGS_AP_CLK_BASE, 0x0028)
+#define REG_AP_CLK_DISPC0_CFG           SCI_ADDR(REGS_AP_CLK_BASE, 0x002c)
+#define REG_AP_CLK_DISPC0_DBI_CFG       SCI_ADDR(REGS_AP_CLK_BASE, 0x0030)
+#define REG_AP_CLK_DISPC0_DPI_CFG       SCI_ADDR(REGS_AP_CLK_BASE, 0x0034)
+#define REG_AP_CLK_DISPC1_CFG           SCI_ADDR(REGS_AP_CLK_BASE, 0x0038)
+#define REG_AP_CLK_DISPC1_DBI_CFG       SCI_ADDR(REGS_AP_CLK_BASE, 0x003c)
+#define REG_AP_CLK_DISPC1_DPI_CFG       SCI_ADDR(REGS_AP_CLK_BASE, 0x0040)
+#define REG_AP_CLK_NFC_CFG              SCI_ADDR(REGS_AP_CLK_BASE, 0x0044)
+#define REG_AP_CLK_SDIO0_CFG            SCI_ADDR(REGS_AP_CLK_BASE, 0x0048)
+#define REG_AP_CLK_SDIO1_CFG            SCI_ADDR(REGS_AP_CLK_BASE, 0x004c)
+#define REG_AP_CLK_SDIO2_CFG            SCI_ADDR(REGS_AP_CLK_BASE, 0x0050)
+#define REG_AP_CLK_EMMC_CFG             SCI_ADDR(REGS_AP_CLK_BASE, 0x0054)
+#define REG_AP_CLK_GPS_CFG              SCI_ADDR(REGS_AP_CLK_BASE, 0x0058)
+#define REG_AP_CLK_GPS_TCXO_CFG         SCI_ADDR(REGS_AP_CLK_BASE, 0x005c)
+#define REG_AP_CLK_USB_REF_CFG          SCI_ADDR(REGS_AP_CLK_BASE, 0x0060)
+#define REG_AP_CLK_UART0_CFG            SCI_ADDR(REGS_AP_CLK_BASE, 0x0064)
+#define REG_AP_CLK_UART1_CFG            SCI_ADDR(REGS_AP_CLK_BASE, 0x0068)
+#define REG_AP_CLK_UART2_CFG            SCI_ADDR(REGS_AP_CLK_BASE, 0x006c)
+#define REG_AP_CLK_UART3_CFG            SCI_ADDR(REGS_AP_CLK_BASE, 0x0070)
+#define REG_AP_CLK_UART4_CFG            SCI_ADDR(REGS_AP_CLK_BASE, 0x0074)
+#define REG_AP_CLK_I2C0_CFG             SCI_ADDR(REGS_AP_CLK_BASE, 0x0078)
+#define REG_AP_CLK_I2C1_CFG             SCI_ADDR(REGS_AP_CLK_BASE, 0x007c)
+#define REG_AP_CLK_I2C2_CFG             SCI_ADDR(REGS_AP_CLK_BASE, 0x0080)
+#define REG_AP_CLK_I2C3_CFG             SCI_ADDR(REGS_AP_CLK_BASE, 0x0084)
+#define REG_AP_CLK_I2C4_CFG             SCI_ADDR(REGS_AP_CLK_BASE, 0x0088)
+#define REG_AP_CLK_SPI0_CFG             SCI_ADDR(REGS_AP_CLK_BASE, 0x008c)
+#define REG_AP_CLK_SPI1_CFG             SCI_ADDR(REGS_AP_CLK_BASE, 0x0090)
+#define REG_AP_CLK_SPI2_CFG             SCI_ADDR(REGS_AP_CLK_BASE, 0x0094)
+#define REG_AP_CLK_IIS0_CFG             SCI_ADDR(REGS_AP_CLK_BASE, 0x0098)
+#define REG_AP_CLK_IIS1_CFG             SCI_ADDR(REGS_AP_CLK_BASE, 0x009c)
+#define REG_AP_CLK_IIS2_CFG             SCI_ADDR(REGS_AP_CLK_BASE, 0x00a0)
+#define REG_AP_CLK_IIS3_CFG             SCI_ADDR(REGS_AP_CLK_BASE, 0x00a4)
+#define REG_AP_CLK_ZIPENC_CFG           SCI_ADDR(REGS_AP_CLK_BASE, 0x00a8)
+#define REG_AP_CLK_ZIPDEC_CFG           SCI_ADDR(REGS_AP_CLK_BASE, 0x00ac)
+
+/* vars definitions for controller REGS_AP_CLK */
+
+#endif //__REGS_AP_CLK_H__
diff --git a/include/soc/sprd/chip_x20/__regs_apb_rf_cp2.h b/include/soc/sprd/chip_x20/__regs_apb_rf_cp2.h
new file mode 100644
index 00000000..edddb5f5
--- /dev/null
+++ b/include/soc/sprd/chip_x20/__regs_apb_rf_cp2.h
@@ -0,0 +1,454 @@
+/*
+ * Copyright (C) 2014 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+#ifndef __SCI_GLB_REGS_H__
+#error  "Don't include this file directly, Pls include sci_glb_regs.h"
+#endif
+
+
+#ifndef __H_REGS_APB_RF_CP2_HEADFILE_H__
+#define __H_REGS_APB_RF_CP2_HEADFILE_H__ __FILE__
+
+#define	REGS_APB_RF_CP2
+
+/* registers definitions for APB_RF_CP2 */
+#define REG_APB_RF_CP2_APB_RST                            SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0000)
+#define REG_APB_RF_CP2_MCU_SOFT_RST                       SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0004)
+#define REG_APB_RF_CP2_APB_EB                             SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0018)
+#define REG_APB_RF_CP2_APB_EB1                            SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x001C)
+#define REG_APB_RF_CP2_APB_CLK_CTL0                       SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0020)
+#define REG_APB_RF_CP2_APB_CLK_CTL1                       SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0024)
+#define REG_APB_RF_CP2_APB_SLP_CTL0                       SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0030)
+#define REG_APB_RF_CP2_APB_INT_STS0                       SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0034)
+#define REG_APB_RF_CP2_APB_INT_SET_CLR0                   SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0038)
+#define REG_APB_RF_CP2_WIFI_BUF_BASE                      SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x003C)
+#define REG_APB_RF_CP2_CLK_TOP_CTRL0                      SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0040)
+#define REG_APB_RF_CP2_CLK_TOP_CTRL1                      SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0044)
+#define REG_APB_RF_CP2_FPGADEBUG                          SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0048)
+#define REG_APB_RF_CP2_APB_BT_DAC_CTR0                    SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0050)
+#define REG_APB_RF_CP2_APB_BT_DAC_CTR1                    SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0054)
+#define REG_APB_RF_CP2_APB_BT_DAC_CTR2                    SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0058)
+#define REG_APB_RF_CP2_APB_BT_DAC_STS0                    SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x005C)
+#define REG_APB_RF_CP2_APB_BT_DAC_STS1                    SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0060)
+#define REG_APB_RF_CP2_APB_BT_ADC_CTR0                    SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0064)
+#define REG_APB_RF_CP2_APB_BT_ADC_CTR1                    SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0068)
+#define REG_APB_RF_CP2_APB_BT_ADC_CTR2                    SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x006C)
+#define REG_APB_RF_CP2_WIFI_SYS0                          SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0070)
+#define REG_APB_RF_CP2_WIFI_SYS1                          SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0074)
+#define REG_APB_RF_CP2_APB_WIFI_ADC_CTR0                  SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0078)
+#define REG_APB_RF_CP2_APB_WIFI_ADC_CTR1                  SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x007C)
+#define REG_APB_RF_CP2_ARM7_RDATA_FROM_ARM9               SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0080)
+#define REG_APB_RF_CP2_ARM7_WDATA_TO_ARM9                 SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0084)
+#define REG_APB_RF_CP2_CP2_BB_CTRL                        SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0088)
+#define REG_APB_RF_CP2_WIFI_BT_CFG0                       SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0090)
+#define REG_APB_RF_CP2_WIFI_BT_CFG1                       SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0094)
+#define REG_APB_RF_CP2_WIFI_BT_CFG2                       SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0098)
+#define REG_APB_RF_CP2_WIFI_BT_CFG3                       SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x009C)
+#define REG_APB_RF_CP2_WIFI_DFT_CTRTL0                    SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00A0)
+#define REG_APB_RF_CP2_WIFI_DFT_CTRTL1                    SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00A4)
+#define REG_APB_RF_CP2_WIFI_DFT_CTRTL2                    SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00A8)
+#define REG_APB_RF_CP2_WB_ADA_CTRTL0                      SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00B0)
+#define REG_APB_RF_CP2_WB_ADA_CTRTL1                      SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00B4)
+#define REG_APB_RF_CP2_WB_ADA_CTRTL2                      SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00B8)
+#define REG_APB_RF_CP2_WB_ADA_CTRTL3                      SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00BC)
+#define REG_APB_RF_CP2_WB_ADA_RESULT0                     SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00C0)
+#define REG_APB_RF_CP2_WB_ADA_RESULT1                     SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00C4)
+#define REG_APB_RF_CP2_WB_ADA_RESULT2                     SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00C8)
+#define REG_APB_RF_CP2_WB_ADA_RESULT3                     SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00CC)
+#define REG_APB_RF_CP2_WB_DBG_RESULT0                     SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00D0)
+#define REG_APB_RF_CP2_WB_DBG_RESULT1                     SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00D4)
+#define REG_APB_RF_CP2_WB_DAC_DBG_DAT                     SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00D8)
+#define REG_APB_RF_CP2_BT_FUNC_DBG                        SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x00DC)
+#define REG_APB_RF_CP2_APB_ARCH_PORT                      SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0100)
+#define REG_APB_RF_CP2_IN_AXI_ADDR                        SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0104)
+#define REG_APB_RF_CP2_IN_CFG_SIZE                        SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0108)
+#define REG_APB_RF_CP2_APB_MISC_CTL                       SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0200)
+#define REG_APB_RF_CP2_APB_MISC_CTL1                      SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0204)
+#define REG_APB_RF_CP2_WIFI_SARADC_CTRL0                  SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0208)
+#define REG_APB_RF_CP2_WIFI_SARADC_CTRL1                  SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x020C)
+#define REG_APB_RF_CP2_BT_SARADC_CTRL1                    SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0210)
+#define REG_APB_RF_CP2_BT_SARADC_CTRL2                    SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0214)
+#define REG_APB_RF_CP2_WBT_DAC_CTRL0                      SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0218)
+#define REG_APB_RF_CP2_WBT_ANA_STS0                       SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x022C)
+#define REG_APB_RF_CP2_WBT_ANA_STS1                       SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0230)
+#define REG_APB_RF_CP2_WIFI_CTRL0                         SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0234)
+#define REG_APB_RF_CP2_WIFI_DAC_DFT                       SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x0238)
+#define REG_APB_RF_CP2_WIFI_ADC_DFT                       SCI_ADDR(REGS_APB_RF_CP2_BASE, 0x023C)
+
+
+
+/* bits definitions for register REG_APB_RF_CP2_APB_RST */
+#define BIT_PHY_SOFT_RST                                  ( BIT(20) )
+#define BIT_MAC_SOFT_RST                                  ( BIT(19) )
+#define BIT_GPIO_SOFT_RST                                 ( BIT(18) )
+#define BIT_ADI_SOFT_RST                                  ( BIT(17) )
+#define BIT_VBC_SOFT_RST                                  ( BIT(16) )
+#define BIT_AUD_SOFT_RST                                  ( BIT(15) )
+#define BIT_VPU_SOFT_RST                                  ( BIT(14) )
+#define BIT_FM_SOFT_RST                                   ( BIT(13) )
+#define BIT_IPI_SOFT_RST                                  ( BIT(12) )
+#define BIT_WIFI_SOFT_RST                                 ( BIT(11) )
+#define BIT_IIS_SOFT_RST                                  ( BIT(10) )
+#define BIT_EIC_SOFT_RST                                  ( BIT(9) )
+#define BIT_BT_SOFT_RST                                   ( BIT(8) )
+#define BIT_WDG_SOFT_RST                                  ( BIT(7) )
+#define BIT_TMR1_SOFT_RST                                 ( BIT(6) )
+#define BIT_TMR0_SOFT_RST                                 ( BIT(5) )
+#define BIT_SYST_SOFT_RST                                 ( BIT(4) )
+#define BIT_UART1_SOFT_RST                                ( BIT(3) )
+#define BIT_UART0_SOFT_RST                                ( BIT(2) )
+
+/* bits definitions for register REG_APB_RF_CP2_MCU_SOFT_RST */
+#define BIT_MCU_SOFT_RST_SET                              ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_EB */
+#define BIT_GPIO_EB                                       ( BIT(24) )
+#define BIT_ADI_EB                                        ( BIT(23) )
+#define BIT_VBC_EB                                        ( BIT(22) )
+#define BIT_AUD_EB                                        ( BIT(21) )
+#define BIT_VPU_EB                                        ( BIT(20) )
+#define BIT_FM_EB                                         ( BIT(19) )
+#define BIT_IPI_EB                                        ( BIT(18) )
+#define BIT_WIFI_EB                                       ( BIT(17) )
+#define BIT_IIS_EB                                        ( BIT(16) )
+#define BIT_EIC_RTCDV5_EB                                 ( BIT(15) )
+#define BIT_EIC_EB                                        ( BIT(14) )
+#define BIT_BT_RTC_EB                                     ( BIT(13) )
+#define BIT_TMR1_RTC_EB                                   ( BIT(12) )
+#define BIT_TMR0_RTC_EB                                   ( BIT(11) )
+#define BIT_SYST_RTC_EB                                   ( BIT(10) )
+#define BIT_WDG_RTC_EB                                    ( BIT(9) )
+#define BIT_BT_EB                                         ( BIT(8) )
+#define BIT_WDG_EB                                        ( BIT(7) )
+#define BIT_TMR1_EB                                       ( BIT(6) )
+#define BIT_TMR0_EB                                       ( BIT(5) )
+#define BIT_SYST_EB                                       ( BIT(4) )
+#define BIT_UART1_EB                                      ( BIT(3) )
+#define BIT_UART0_EB                                      ( BIT(2) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_EB1 */
+#define BIT_APB_ARCH_RTC_EB                               ( BIT(1) )
+#define BIT_APB_ARCH_EB                                   ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_CLK_CTL0 */
+#define BITS_CLK_WTDAC_CTRL(_X_)                          ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_CLK_BT_26M_SRC_SEL                            ( BIT(19) )
+#define BITS_CLK_BT_DA_SEL(_X_)                           ( (_X_) << 17 & (BIT(17)|BIT(18)) )
+#define BITS_CLK_BT_AD_SEL(_X_)                           ( (_X_) << 15 & (BIT(15)|BIT(16)) )
+#define BITS_CLK_UART0_SEL(_X_)                           ( (_X_) << 13 & (BIT(13)|BIT(14)) )
+#define BIT_CLK_BT_26M_SEL                                ( BIT(12) )
+#define BIT_CLK_BT_24M_SEL                                ( BIT(11) )
+#define BITS_CLK_IIS_SEL(_X_)                             ( (_X_) << 9 & (BIT(9)|BIT(10)) )
+#define BITS_CLK_VPU_SEL(_X_)                             ( (_X_) << 7 & (BIT(7)|BIT(8)) )
+#define BITS_CLK_UART1_SEL(_X_)                           ( (_X_) << 5 & (BIT(5)|BIT(6)) )
+#define BIT_CLK_WIFI_120M_EN                              ( BIT(4) )
+#define BIT_CLK_WIFI_26M_EN                               ( BIT(3) )
+#define BIT_CLK_WIFI_80M_EN                               ( BIT(2) )
+#define BIT_CLK_WIFI_44M_EN                               ( BIT(1) )
+#define BIT_CLK_WIFI_40M_EN                               ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_CLK_CTL1 */
+#define BITS_CLK_IIS_DIV(_X_)                             ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_SLP_CTL0 */
+#define BIT_APB_FORCE_ON                                  ( BIT(2) )
+#define BIT_APB_FORCE_SLEEP                               ( BIT(1) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_INT_STS0 */
+#define BIT_ARM9_FRQ                                      ( BIT(3) )
+#define BIT_ARM9_IRQ                                      ( BIT(2) )
+#define BIT_ARM7_MCU_FRQ                                  ( BIT(1) )
+#define BIT_ARM7_MCU_IRQ                                  ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_INT_SET_CLR0 */
+#define BIT_ARM9_FRQ_CLR                                  ( BIT(3) )
+#define BIT_ARM9_IRQ_CLR                                  ( BIT(2) )
+#define BIT_ARM7_MCU_FRQ_SET                              ( BIT(1) )
+#define BIT_ARM7_MCU_IRQ_SET                              ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_BUF_BASE */
+#define BITS_WIFI_BUF_BASE(_X_)                           (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_CLK_TOP_CTRL0 */
+#define BITS_CLK_TOP_CTRL0(_X_)                           (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_CLK_TOP_CTRL1 */
+#define BITS_CLK_TOP_CTRL1(_X_)                           (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_FPGADEBUG */
+#define BITS_FPGADEBUG(_X_)                               (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_APB_BT_DAC_CTR0 */
+#define BITS_BT_DAC_BG_CTR(_X_)                           ( (_X_) << 30 & (BIT(30)|BIT(31)) )
+#define BIT_BT_DAC_EN_ADC                                 ( BIT(26) )
+#define BIT_BT_DAC_CLK_SEL                                ( BIT(25) )
+#define BIT_BT_DAC_EN_MIDRANGE                            ( BIT(24) )
+#define BITS_BT_DAC_Q_DC(_X_)                             ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_BT_DAC_I_DC(_X_)                             ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_BT_DAC_CTR1 */
+#define BITS_BT_DAC_SEL(_X_)                              ( (_X_) << 29 & (BIT(29)|BIT(30)) )
+#define BIT_BT_DAC_BOOSTI_EN                              ( BIT(28) )
+#define BITS_BT_DAC_CFG(_X_)                              ( (_X_) << 25 & (BIT(25)|BIT(26)|BIT(27)) )
+#define BIT_BT_DAC_CAL_CLK_SEL                            ( BIT(24) )
+#define BIT_BT_DAC_PD                                     ( BIT(23) )
+#define BITS_BT_DAC_WADDR_OVR(_X_)                        ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)|BIT(22)) )
+#define BIT_BT_DAC_WLE_OVR                                ( BIT(18) )
+#define BITS_BT_DAC_WD_OVR(_X_)                           ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)) )
+#define BIT_BT_DAC_W_OVR_I_QN                             ( BIT(1) )
+#define BIT_BT_DAC_W_OVR_EN                               ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_BT_DAC_CTR2 */
+#define BIT_BB_BG_EN                                      ( BIT(21) )
+#define BIT_BB_LDO_EN                                     ( BIT(20) )
+#define BIT_BT_DAC_OVR_EN_CAL                             ( BIT(19) )
+#define BIT_BT_DAC_EN_OOSCAL                              ( BIT(18) )
+#define BIT_BT_DAC_IQ_SWAP                                ( BIT(17) )
+#define BIT_BT_DAC_CAL_START                              ( BIT(16) )
+#define BITS_BT_DAC_OFFSETI(_X_)                          ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_BT_DAC_OFFSETQ(_X_)                          ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_BT_DAC_STS0 */
+#define BITS_BT_DAC_WTI(_X_)                              ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_BT_DAC_WTQ(_X_)                              ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_BT_DAC_STS1 */
+#define BITS_BT_DAC_DA_STATE(_X_)                         ( (_X_) << 17 & (BIT(17)|BIT(18)) )
+#define BIT_BT_DAC_DONE                                   ( BIT(16) )
+#define BITS_BT_DAC_WQ_OVR(_X_)                           ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_BT_ADC_CTR0 */
+#define BITS_BT_ADC_SARSPD(_X_)                           ( (_X_) << 25 & (BIT(25)|BIT(26)) )
+#define BITS_BT_ADC_CMPSPD(_X_)                           ( (_X_) << 23 & (BIT(23)|BIT(24)) )
+#define BITS_BT_ADC_ADJ(_X_)                              ( (_X_) << 7 & (BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)) )
+#define BITS_BT_ADC_REFBIAS(_X_)                          ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) )
+#define BITS_BT_ADC_CMPBIAS(_X_)                          ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BIT_BT_ADC_MODE                                   ( BIT(1) )
+#define BIT_BT_ADC_EN                                     ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_BT_ADC_CTR1 */
+#define BIT_BT_ADC_CAL                                    ( BIT(18) )
+#define BITS_BT_ADC_DUTY(_X_)                             ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) )
+#define BITS_BT_ADC_DLL_D(_X_)                            ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BIT_BT_ADC_DLL_RD                                 ( BIT(8) )
+#define BIT_BT_ADC_DLL_SUG                                ( BIT(7) )
+#define BITS_BT_ADC_DLL_SET(_X_)                          ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) )
+#define BIT_BT_ADC_DLL_OVR                                ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_BT_ADC_CTR2 */
+#define BITS_BT_PTA_SL(_X_)                               ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BIT_BT_CTRL                                       ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_SYS0 */
+#define BITS_WIFIMAB_CTRL(_X_)                            ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_WIFISAB_CTRL(_X_)                            ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_SYS1 */
+#define BITS_WIFIMAB_STS(_X_)                             ( (_X_) << 14 & (BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_WIFISAB_STS(_X_)                             ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_WIFI_ADC_CTR0 */
+#define BITS_WIFI_ADC_SARSPD(_X_)                         ( (_X_) << 25 & (BIT(25)|BIT(26)) )
+#define BITS_WIFI_ADC_CMPSPD(_X_)                         ( (_X_) << 23 & (BIT(23)|BIT(24)) )
+#define BITS_WIFI_ADC_ADJ(_X_)                            ( (_X_) << 7 & (BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)) )
+#define BITS_WIFI_ADC_REFBIAS(_X_)                        ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) )
+#define BITS_WIFI_ADC_CMPBIAS(_X_)                        ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BIT_WIFI_ADC_MODE                                 ( BIT(1) )
+#define BIT_WIFI_ADC_EN                                   ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_WIFI_ADC_CTR1 */
+#define BIT_WIFI_ADC_CAL                                  ( BIT(18) )
+#define BITS_WIFI_ADC_DUTY(_X_)                           ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) )
+#define BITS_WIFI_ADC_DLL_D(_X_)                          ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BIT_WIFI_ADC_DLL_RD                               ( BIT(8) )
+#define BIT_WIFI_ADC_DLL_SUG                              ( BIT(7) )
+#define BITS_WIFI_ADC_DLL_SET(_X_)                        ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) )
+#define BIT_WIFI_ADC_DLL_OVR                              ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_ARM7_RDATA_FROM_ARM9 */
+#define BITS_ARM7_RDATA_FROM_ARM9(_X_)                    (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_ARM7_WDATA_TO_ARM9 */
+#define BITS_ARM7_WDATA_TO_ARM9(_X_)                      (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_CP2_BB_CTRL */
+#define BITS_BB_LOCAL_CTRL(_X_)                           ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_BT_CFG0 */
+#define BITS_WIFI_BT_CFG0(_X_)                            (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_BT_CFG1 */
+#define BITS_WIFI_BT_CFG1(_X_)                            (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_BT_CFG2 */
+#define BITS_WIFI_BT_CFG2(_X_)                            (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_BT_CFG3 */
+#define BITS_WIFI_BT_CFG3(_X_)                            (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_DFT_CTRTL0 */
+#define BITS_WIFI_DFT_CTRTL0(_X_)                         (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_DFT_CTRTL1 */
+#define BITS_WIFI_DFT_CTRTL1(_X_)                         (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_DFT_CTRTL2 */
+#define BITS_WIFI_DFT_CTRTL2(_X_)                         (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WB_ADA_CTRTL0 */
+#define BITS_WB_ADA_CTRTL0(_X_)                           (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WB_ADA_CTRTL1 */
+#define BITS_WB_ADA_CTRTL1(_X_)                           (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WB_ADA_CTRTL2 */
+#define BITS_WB_ADA_CTRTL2(_X_)                           (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WB_ADA_CTRTL3 */
+#define BITS_WB_ADA_CTRTL3(_X_)                           (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WB_ADA_RESULT0 */
+#define BITS_WB_ADA_RESULT0(_X_)                          (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WB_ADA_RESULT1 */
+#define BITS_WB_ADA_RESULT1(_X_)                          (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WB_ADA_RESULT2 */
+#define BITS_WB_ADA_RESULT2(_X_)                          (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WB_ADA_RESULT3 */
+#define BITS_WB_ADA_RESULT3(_X_)                          (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WB_DBG_RESULT0 */
+#define BITS_WB_DBG_RESULT0(_X_)                          (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WB_DBG_RESULT1 */
+#define BITS_WB_DBG_RESULT1(_X_)                          (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WB_DAC_DBG_DAT */
+#define BITS_WBDAC_IQ_TEST_DAT(_X_)                       (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_BT_FUNC_DBG */
+#define BITS_BT_FUNC_DBG(_X_)                             (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_APB_ARCH_PORT */
+#define BIT_MCU_PROT_GLB                                  ( BIT(16) )
+#define BITS_MCU_PROT_CHECK(_X_)                          ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_APB_RF_CP2_IN_AXI_ADDR */
+#define BITS_IN_AXI_ADDR(_X_)                             (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_IN_CFG_SIZE */
+#define BITS_IN_CFG_SIZE(_X_)                             (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_APB_MISC_CTL */
+#define BIT_FPGA_SPI_SEL                                  ( BIT(16) )
+#define BIT_TEST_DBG_MODE3                                ( BIT(10) )
+#define BIT_TEST_DBG_MODE2                                ( BIT(9) )
+#define BIT_TEST_DBG_MODE1                                ( BIT(8) )
+#define BIT_TEST_DBG_MODE0                                ( BIT(7) )
+#define BIT_BT_MAHB_SLEEP_EN                              ( BIT(6) )
+#define BIT_DSP2BT_IND                                    ( BIT(5) )
+#define BIT_ROM_CLK_FORCE_EN                              ( BIT(4) )
+#define BIT_ARM7_JTAG_EN                                  ( BIT(3) )
+#define BITS_ARM7_CACHE_SIZE(_X_)                         ( (_X_) << 1 & (BIT(1)|BIT(2)) )
+#define BIT_ARM7_CACHE_EN                                 ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_APB_MISC_CTL1 */
+#define BITS_ARM7_HWRST1_REG(_X_)                         ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_SARADC_CTRL0 */
+#define BIT_WIFI_SARAD_CLK_SEL                            ( BIT(26) )
+#define BIT_WIFI_SARAD_DEBUG_EN                           ( BIT(25) )
+#define BITS_WIFI_SARAD_CALADDR(_X_)                      ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) )
+#define BIT_WIFI_SARAD_CALEN                              ( BIT(18) )
+#define BIT_WIFI_SARAD_CALRD                              ( BIT(17) )
+#define BIT_WIFI_SARAD_CAL_RSTN                           ( BIT(16) )
+#define BIT_WIFI_SARAD_DLLEN                              ( BIT(15) )
+#define BITS_WIFI_SARAD_DLLIN(_X_)                        ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_WIFI_SARAD_DLLOOF(_X_)                       ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) )
+#define BIT_WIFI_SARAD_DLLRD                              ( BIT(2) )
+#define BIT_WIFI_SARAD_DLLWR                              ( BIT(1) )
+#define BIT_WIFI_SARAD_DLL_RSTN                           ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_SARADC_CTRL1 */
+#define BITS_WIFI_SARAD_QUANT_BOOST(_X_)                  ( (_X_) << 27 & (BIT(27)|BIT(28)) )
+#define BITS_WIFI_SARAD_VREF_BOOST(_X_)                   ( (_X_) << 25 & (BIT(25)|BIT(26)) )
+#define BITS_WIFI_SARAD_VREF_SEL(_X_)                     ( (_X_) << 23 & (BIT(23)|BIT(24)) )
+#define BITS_WIFI_SARAD_BIT_SEL(_X_)                      ( (_X_) << 21 & (BIT(21)|BIT(22)) )
+#define BITS_WIFI_SARAD_DELAY_CAP(_X_)                    ( (_X_) << 19 & (BIT(19)|BIT(20)) )
+#define BIT_WIFI_SARAD_VCM_SEL                            ( BIT(18) )
+#define BIT_WIFI_SARAD_DIG_CLK_SEL                        ( BIT(17) )
+#define BIT_WIFI_SARAD_CAL                                ( BIT(16) )
+#define BITS_WIFI_SARAD_RESERVE(_X_)                      ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_APB_RF_CP2_BT_SARADC_CTRL1 */
+#define BIT_BT_SARAD_PD                                   ( BIT(27) )
+#define BIT_BT_SARAD_ADCS_EN                              ( BIT(26) )
+#define BIT_BT_SARAD_DEBUG_EN                             ( BIT(25) )
+#define BITS_BT_SARAD_CALADDR(_X_)                        ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) )
+#define BIT_BT_SARAD_CALEN                                ( BIT(18) )
+#define BIT_BT_SARAD_CALRD                                ( BIT(17) )
+#define BIT_BT_SARAD_CAL_RSTN                             ( BIT(16) )
+#define BIT_BT_SARAD_DLLEN                                ( BIT(15) )
+#define BITS_BT_SARAD_DLLIN(_X_)                          ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_BT_SARAD_DLLOOF(_X_)                         ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) )
+#define BIT_BT_SARAD_DLLRD                                ( BIT(2) )
+#define BIT_BT_SARAD_DLLWR                                ( BIT(1) )
+#define BIT_BT_SARAD_DLL_RSTN                             ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_BT_SARADC_CTRL2 */
+#define BITS_BT_SARAD_QUANT_BOOST(_X_)                    ( (_X_) << 27 & (BIT(27)|BIT(28)) )
+#define BITS_BT_SARAD_VREF_BOOST(_X_)                     ( (_X_) << 25 & (BIT(25)|BIT(26)) )
+#define BITS_BT_SARAD_VREF_SEL(_X_)                       ( (_X_) << 23 & (BIT(23)|BIT(24)) )
+#define BITS_BT_SARAD_BIT_SEL(_X_)                        ( (_X_) << 21 & (BIT(21)|BIT(22)) )
+#define BITS_BT_SARAD_DELAY_CAP(_X_)                      ( (_X_) << 19 & (BIT(19)|BIT(20)) )
+#define BIT_BT_SARAD_VCM_SEL                              ( BIT(18) )
+#define BIT_BT_SARAD_DIG_CLK_SEL                          ( BIT(17) )
+#define BIT_BT_SARAD_CAL                                  ( BIT(16) )
+#define BITS_BT_SARAD_RESERVE(_X_)                        ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_APB_RF_CP2_WBT_DAC_CTRL0 */
+#define BIT_WBT_DAC_SOFT_RST                              ( BIT(8) )
+#define BITS_WBT_DAC_PCTRL(_X_)                           ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) )
+#define BITS_WBT_DAC_RESERVE(_X_)                         ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_APB_RF_CP2_WBT_ANA_STS0 */
+#define BITS_WIFI_SARAD_CALRDOUT(_X_)                     ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_WIFI_SARAD_DLL_OUT(_X_)                      ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+
+/* bits definitions for register REG_APB_RF_CP2_WBT_ANA_STS1 */
+#define BIT_WIFIPLL2_LOCK_DONE                            ( BIT(21) )
+#define BIT_WIFIPLL1_LOCK_DONE                            ( BIT(20) )
+#define BITS_BT_SARAD_CALRDOUT(_X_)                       ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_BT_SARAD_DLL_OUT(_X_)                        ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_CTRL0 */
+#define BITS_WIFI_IN_CAP_SWT(_X_)                         ( (_X_) << 14 & (BIT(14)|BIT(15)) )
+#define BITS_WIFI_SLEEP_CFG(_X_)                          ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
+#define BIT_WB_EN_B_RG                                    ( BIT(2) )
+#define BIT_WB_EN_A_RG                                    ( BIT(1) )
+#define BIT_WB_EN_SEL                                     ( BIT(0) )
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_DAC_DFT */
+#define BITS_WIFI_DAC_DFT(_X_)                            (_X_)
+
+/* bits definitions for register REG_APB_RF_CP2_WIFI_ADC_DFT */
+#define BITS_WIFI_ADC_DFT(_X_)                            (_X_)
+
+#endif
diff --git a/include/soc/sprd/chip_x20/__regs_avs_apb.h b/include/soc/sprd/chip_x20/__regs_avs_apb.h
new file mode 100644
index 00000000..e5153c36
--- /dev/null
+++ b/include/soc/sprd/chip_x20/__regs_avs_apb.h
@@ -0,0 +1,165 @@
+/*
+ * Copyright (C) 2014 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+#ifndef __SCI_GLB_REGS_H__
+#error  "Don't include this file directly, Pls include sci_glb_regs.h"
+#endif
+
+
+#ifndef __H_REGS_AVS_APB_HEADFILE_H__
+#define __H_REGS_AVS_APB_HEADFILE_H__ __FILE__
+
+#define	REGS_AVS_APB
+
+/* registers definitions for AVS_APB */
+#define REG_AVS_APB_AVS_TUNE_LMT_CFG                      SCI_ADDR(REGS_AVS_APB_BASE, 0x0000)
+#define REG_AVS_APB_AVS_TUNE_STATUS                       SCI_ADDR(REGS_AVS_APB_BASE, 0x0004)
+#define REG_AVS_APB_AVS_CFG                               SCI_ADDR(REGS_AVS_APB_BASE, 0x0008)
+#define REG_AVS_APB_AVS_TUNE_STEP_CFG                     SCI_ADDR(REGS_AVS_APB_BASE, 0x000C)
+#define REG_AVS_APB_AVS_WAIT_CFG                          SCI_ADDR(REGS_AVS_APB_BASE, 0x0010)
+#define REG_AVS_APB_AVS_INT_CFG                           SCI_ADDR(REGS_AVS_APB_BASE, 0x0014)
+#define REG_AVS_APB_AVS_START_SINGLE_ACT                  SCI_ADDR(REGS_AVS_APB_BASE, 0x0018)
+#define REG_AVS_APB_AVS_START_REPEAT_ACT                  SCI_ADDR(REGS_AVS_APB_BASE, 0x001C)
+#define REG_AVS_APB_AVS_HPM_EN                            SCI_ADDR(REGS_AVS_APB_BASE, 0x0020)
+#define REG_AVS_APB_AVS_HPM_RPT_ANLS                      SCI_ADDR(REGS_AVS_APB_BASE, 0x0024)
+#define REG_AVS_APB_AVS_HPM_RPT_VLD_STATUS_0              SCI_ADDR(REGS_AVS_APB_BASE, 0x0028)
+#define REG_AVS_APB_AVS_HPM_RPT_VLD_STATUS_1              SCI_ADDR(REGS_AVS_APB_BASE, 0x002C)
+#define REG_AVS_APB_AVS_HPM_RPT_VLD_STATUS_2              SCI_ADDR(REGS_AVS_APB_BASE, 0x0030)
+#define REG_AVS_APB_AVS_HPM_RPT_VLD_STATUS_3              SCI_ADDR(REGS_AVS_APB_BASE, 0x0034)
+#define REG_AVS_APB_AVS_HPM_DLY_WIND_SEL                  SCI_ADDR(REGS_AVS_APB_BASE, 0x0038)
+#define REG_AVS_APB_FSM_STS                               SCI_ADDR(REGS_AVS_APB_BASE, 0x0040)
+
+
+
+/* bits definitions for register REG_AVS_APB_AVS_TUNE_LMT_CFG */
+#define BITS_VOLT_TUNE_VAL_MAX(_X_)                       ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_VOLT_TUNE_VAL_MIN(_X_)                       ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_AVS_APB_AVS_TUNE_STATUS */
+#define BITS_VOLT_TUNE_VAL(_X_)                           ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_VOLT_OBS_VAL(_X_)                            ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_AVS_APB_AVS_CFG */
+#define BIT_HPM15_RPT_CHKSUM_ERR_EN                       ( BIT(31) )
+#define BIT_HPM14_RPT_CHKSUM_ERR_EN                       ( BIT(30) )
+#define BIT_HPM13_RPT_CHKSUM_ERR_EN                       ( BIT(29) )
+#define BIT_HPM12_RPT_CHKSUM_ERR_EN                       ( BIT(28) )
+#define BIT_HPM11_RPT_CHKSUM_ERR_EN                       ( BIT(27) )
+#define BIT_HPM10_RPT_CHKSUM_ERR_EN                       ( BIT(26) )
+#define BIT_HPM9_RPT_CHKSUM_ERR_EN                        ( BIT(25) )
+#define BIT_HPM8_RPT_CHKSUM_ERR_EN                        ( BIT(24) )
+#define BIT_HPM7_RPT_CHKSUM_ERR_EN                        ( BIT(23) )
+#define BIT_HPM6_RPT_CHKSUM_ERR_EN                        ( BIT(22) )
+#define BIT_HPM5_RPT_CHKSUM_ERR_EN                        ( BIT(21) )
+#define BIT_HPM4_RPT_CHKSUM_ERR_EN                        ( BIT(20) )
+#define BIT_HPM3_RPT_CHKSUM_ERR_EN                        ( BIT(19) )
+#define BIT_HPM2_RPT_CHKSUM_ERR_EN                        ( BIT(18) )
+#define BIT_HPM1_RPT_CHKSUM_ERR_EN                        ( BIT(17) )
+#define BIT_HPM0_RPT_CHKSUM_ERR_EN                        ( BIT(16) )
+#define BIT_PAUSE_OCCUR_ERR_EN                            ( BIT(8) )
+#define BIT_VOLT_TUNE_FORBIDEN                            ( BIT(4) )
+#define BIT_VOLT_OBS_FORBIDEN                             ( BIT(0) )
+
+/* bits definitions for register REG_AVS_APB_AVS_TUNE_STEP_CFG */
+#define BITS_VOLT_TUNE_DOWN_STEP(_X_)                     ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) )
+#define BITS_VOLT_TUNE_UP_STEP(_X_)                       ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) )
+
+/* bits definitions for register REG_AVS_APB_AVS_WAIT_CFG */
+#define BITS_RND_INTVAL_WAIT_NUM(_X_)                     ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_VOLT_STB_WAIT_NUM(_X_)                       ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_AVS_APB_AVS_INT_CFG */
+#define BIT_INT_RPT_FORMAT_ERR_CLR                        ( BIT(14) )
+#define BIT_INT_RPT_ANLS_ERR_CLR                          ( BIT(13) )
+#define BIT_INT_VOLT_TUNE_ERR_CLR                         ( BIT(12) )
+#define BIT_INT_RPT_FORMAT_ERR_MASK_STATUS                ( BIT(10) )
+#define BIT_INT_RPT_ANLS_ERR_MASK_STATUS                  ( BIT(9) )
+#define BIT_INT_VOLT_TUNE_ERR_MASK_STATUS                 ( BIT(8) )
+#define BIT_INT_RPT_FORMAT_ERR_RAW_STATUS                 ( BIT(6) )
+#define BIT_INT_RPT_ANLS_ERR_RAW_STATUS                   ( BIT(5) )
+#define BIT_INT_VOLT_TUNE_ERR_RAW_STATUS                  ( BIT(4) )
+#define BIT_INT_RPT_FORMAT_ERR_EN                         ( BIT(2) )
+#define BIT_INT_RPT_ANLS_ERR_EN                           ( BIT(1) )
+#define BIT_INT_VOLT_TUNE_ERR_EN                          ( BIT(0) )
+
+/* bits definitions for register REG_AVS_APB_AVS_START_SINGLE_ACT */
+#define BIT_AVS_START_SINGLE_ACT                          ( BIT(0) )
+
+/* bits definitions for register REG_AVS_APB_AVS_START_REPEAT_ACT */
+#define BIT_AVS_START_REPEAT_ACT                          ( BIT(0) )
+
+/* bits definitions for register REG_AVS_APB_AVS_HPM_EN */
+#define BIT_HPM15_EN                                      ( BIT(15) )
+#define BIT_HPM14_EN                                      ( BIT(14) )
+#define BIT_HPM13_EN                                      ( BIT(13) )
+#define BIT_HPM12_EN                                      ( BIT(12) )
+#define BIT_HPM11_EN                                      ( BIT(11) )
+#define BIT_HPM10_EN                                      ( BIT(10) )
+#define BIT_HPM9_EN                                       ( BIT(9) )
+#define BIT_HPM8_EN                                       ( BIT(8) )
+#define BIT_HPM7_EN                                       ( BIT(7) )
+#define BIT_HPM6_EN                                       ( BIT(6) )
+#define BIT_HPM5_EN                                       ( BIT(5) )
+#define BIT_HPM4_EN                                       ( BIT(4) )
+#define BIT_HPM3_EN                                       ( BIT(3) )
+#define BIT_HPM2_EN                                       ( BIT(2) )
+#define BIT_HPM1_EN                                       ( BIT(1) )
+#define BIT_HPM0_EN                                       ( BIT(0) )
+
+/* bits definitions for register REG_AVS_APB_AVS_HPM_RPT_ANLS */
+#define BITS_HPM_RPT_FF_ANLS(_X_)                         ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_HPM_RPT_7F_ANLS(_X_)                         ( (_X_) << 14 & (BIT(14)|BIT(15)) )
+#define BITS_HPM_RPT_3F_ANLS(_X_)                         ( (_X_) << 12 & (BIT(12)|BIT(13)) )
+#define BITS_HPM_RPT_1F_ANLS(_X_)                         ( (_X_) << 10 & (BIT(10)|BIT(11)) )
+#define BITS_HPM_RPT_0F_ANLS(_X_)                         ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_HPM_RPT_07_ANLS(_X_)                         ( (_X_) << 6 & (BIT(6)|BIT(7)) )
+#define BITS_HPM_RPT_03_ANLS(_X_)                         ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_HPM_RPT_01_ANLS(_X_)                         ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_HPM_RPT_00_ANLS(_X_)                         ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_AVS_APB_AVS_HPM_RPT_VLD_STATUS_0 */
+#define BITS_HPM3_RPT_VLD(_X_)                            ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_HPM2_RPT_VLD(_X_)                            ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_HPM1_RPT_VLD(_X_)                            ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_HPM0_RPT_VLD(_X_)                            ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_AVS_APB_AVS_HPM_RPT_VLD_STATUS_1 */
+#define BITS_HPM7_RPT_VLD(_X_)                            ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_HPM6_RPT_VLD(_X_)                            ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_HPM5_RPT_VLD(_X_)                            ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_HPM4_RPT_VLD(_X_)                            ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_AVS_APB_AVS_HPM_RPT_VLD_STATUS_2 */
+#define BITS_HPM11_RPT_VLD(_X_)                           ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_HPM10_RPT_VLD(_X_)                           ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_HPM9_RPT_VLD(_X_)                            ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_HPM8_RPT_VLD(_X_)                            ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_AVS_APB_AVS_HPM_RPT_VLD_STATUS_3 */
+#define BITS_HPM15_RPT_VLD(_X_)                           ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_HPM14_RPT_VLD(_X_)                           ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_HPM13_RPT_VLD(_X_)                           ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_HPM12_RPT_VLD(_X_)                           ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_AVS_APB_AVS_HPM_DLY_WIND_SEL */
+#define BITS_DLY_WIND_SEL(_X_)                            ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_AVS_APB_FSM_STS */
+#define BITS_AVS_FSM_STS(_X_)                             ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+#endif
diff --git a/include/soc/sprd/chip_x20/__regs_cp_ahb_rf.h b/include/soc/sprd/chip_x20/__regs_cp_ahb_rf.h
new file mode 100644
index 00000000..1ed8bbcd
--- /dev/null
+++ b/include/soc/sprd/chip_x20/__regs_cp_ahb_rf.h
@@ -0,0 +1,273 @@
+/*
+ * Copyright (C) 2014 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+#ifndef __SCI_GLB_REGS_H__
+#error  "Don't include this file directly, Pls include sci_glb_regs.h"
+#endif
+
+
+#ifndef __H_REGS_CP_AHB_RF_HEADFILE_H__
+#define __H_REGS_CP_AHB_RF_HEADFILE_H__ __FILE__
+
+#define	REGS_CP_AHB_RF
+
+/* registers definitions for CP_AHB_RF */
+#define REG_CP_AHB_RF_AHB_EB0_STS                         SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0008)
+#define REG_CP_AHB_RF_AHB_RST0_STS                        SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0014)
+#define REG_CP_AHB_RF_ARCH_EB                             SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0018)
+#define REG_CP_AHB_RF_AHB_REMAP                           SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x001C)
+#define REG_CP_AHB_RF_AHB_MISC_CTL                        SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0020)
+#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL0                    SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0024)
+#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL1                    SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0028)
+#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL2                    SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x002C)
+#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL3                    SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0030)
+#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL4                    SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0034)
+#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL5                    SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0038)
+#define REG_CP_AHB_RF_AHB_MTX_PRI_SEL6                    SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x003C)
+#define REG_CP_AHB_RF_AHB_PAUSE                           SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0040)
+#define REG_CP_AHB_RF_AHB_SLP_CTL                         SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0044)
+#define REG_CP_AHB_RF_AHB_SLP_STS                         SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0048)
+#define REG_CP_AHB_RF_MCU_CLK_CTL                         SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x004C)
+#define REG_CP_AHB_RF_DSP_CTL                             SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0050)
+#define REG_CP_AHB_RF_DSP_BOOT_VECTOR                     SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0054)
+#define REG_CP_AHB_RF_DSP_RST                             SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0058)
+#define REG_CP_AHB_RF_DSP_JTAG_CTL                        SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x005C)
+#define REG_CP_AHB_RF_MCU_C2C_SEMA                        SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x0060)
+#define REG_CP_AHB_RF_CHIP_ID                             SCI_ADDR(REGS_CP_AHB_RF_BASE, 0x01FC)
+
+
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_EB0_STS */
+#define BIT_LZMA_EN                                       ( BIT(11) )
+#define BIT_WCDMA_EN5                                     ( BIT(9) )
+#define BIT_WCDMA_EN4                                     ( BIT(8) )
+#define BIT_WCDMA_EN3                                     ( BIT(7) )
+#define BIT_WCDMA_EN2                                     ( BIT(6) )
+#define BIT_WCDMA_EN1                                     ( BIT(5) )
+#define BIT_WCDMA_EN0                                     ( BIT(4) )
+#define BIT_BUSMON2_EN                                    ( BIT(3) )
+#define BIT_BUSMON1_EN                                    ( BIT(2) )
+#define BIT_BUSMON0_EN                                    ( BIT(1) )
+#define BIT_DMA_EN                                        ( BIT(0) )
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_RST0_STS */
+#define BIT_LZMA_SOFT_RST                                 ( BIT(8) )
+#define BIT_WSYS_SOFT_RST                                 ( BIT(6) )
+#define BIT_ARM2_SOFT_RST                                 ( BIT(5) )
+#define BIT_ARM1_SOFT_RST                                 ( BIT(4) )
+#define BIT_BUSMON2_SOFT_RST                              ( BIT(3) )
+#define BIT_BUSMON1_SOFT_RST                              ( BIT(2) )
+#define BIT_BUSMON0_SOFT_RST                              ( BIT(1) )
+#define BIT_DMA_SOFT_RST                                  ( BIT(0) )
+
+/* bits definitions for register REG_CP_AHB_RF_ARCH_EB */
+#define BIT_AHB_ARCH_EB                                   ( BIT(0) )
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_REMAP */
+#define BIT_PTEST_FUNC_ATSPEED_SEL                        ( BIT(2) )
+#define BIT_PTEST_FUNC_MODE                               ( BIT(1) )
+#define BIT_REMAP                                         ( BIT(0) )
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_MISC_CTL */
+#define BITS_LZMA_M_PROT(_X_)                             ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMA_W_PROT(_X_)                              ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMA_R_PROT(_X_)                              ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_MCU_SHM_CTRL(_X_)                            ( (_X_) << 6 & (BIT(6)|BIT(7)) )
+#define BIT_RF_SWT_AUTO_EN                                ( BIT(1) )
+#define BIT_WCDMA_ASHB_EN                                 ( BIT(0) )
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL0 */
+#define BITS_ARMMTX_M3TOS0_RND_THR(_X_)                   ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_ARMMTX_M3TOS0_ADJ_EN                          ( BIT(27) )
+#define BIT_ARMMTX_M3TOS0_RND_EN                          ( BIT(26) )
+#define BITS_ARMMTX_M3TOS0_SEL(_X_)                       ( (_X_) << 24 & (BIT(24)|BIT(25)) )
+#define BITS_ARMMTX_M2TOS0_RND_THR(_X_)                   ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BIT_ARMMTX_M2TOS0_ADJ_EN                          ( BIT(19) )
+#define BIT_ARMMTX_M2TOS0_RND_EN                          ( BIT(18) )
+#define BITS_ARMMTX_M2TOS0_SEL(_X_)                       ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_ARMMTX_M1TOS0_RND_THR(_X_)                   ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BIT_ARMMTX_M1TOS0_ADJ_EN                          ( BIT(11) )
+#define BIT_ARMMTX_M1TOS0_RND_EN                          ( BIT(10) )
+#define BITS_ARMMTX_M1TOS0_SEL(_X_)                       ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ARMMTX_M0TOS0_RND_THR(_X_)                   ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_ARMMTX_M0TOS0_ADJ_EN                          ( BIT(3) )
+#define BIT_ARMMTX_M0TOS0_RND_EN                          ( BIT(2) )
+#define BITS_ARMMTX_M0TOS0_SEL(_X_)                       ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL1 */
+#define BITS_ARMMTX_M3TOS1_RND_THR(_X_)                   ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_ARMMTX_M3TOS1_ADJ_EN                          ( BIT(27) )
+#define BIT_ARMMTX_M3TOS1_RND_EN                          ( BIT(26) )
+#define BITS_ARMMTX_M3TOS1_SEL(_X_)                       ( (_X_) << 24 & (BIT(24)|BIT(25)) )
+#define BITS_ARMMTX_M2TOS1_RND_THR(_X_)                   ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BIT_ARMMTX_M2TOS1_ADJ_EN                          ( BIT(19) )
+#define BIT_ARMMTX_M2TOS1_RND_EN                          ( BIT(18) )
+#define BITS_ARMMTX_M2TOS1_SEL(_X_)                       ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_ARMMTX_M1TOS1_RND_THR(_X_)                   ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BIT_ARMMTX_M1TOS1_ADJ_EN                          ( BIT(11) )
+#define BIT_ARMMTX_M1TOS1_RND_EN                          ( BIT(10) )
+#define BITS_ARMMTX_M1TOS1_SEL(_X_)                       ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ARMMTX_M0TOS1_RND_THR(_X_)                   ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_ARMMTX_M0TOS1_ADJ_EN                          ( BIT(3) )
+#define BIT_ARMMTX_M0TOS1_RND_EN                          ( BIT(2) )
+#define BITS_ARMMTX_M0TOS1_SEL(_X_)                       ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL2 */
+#define BITS_ARMMTX_M1TOS2_RND_THR(_X_)                   ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_ARMMTX_M1TOS2_ADJ_EN                          ( BIT(27) )
+#define BIT_ARMMTX_M1TOS2_RND_EN                          ( BIT(26) )
+#define BITS_ARMMTX_M1TOS2_SEL(_X_)                       ( (_X_) << 24 & (BIT(24)|BIT(25)) )
+#define BITS_ARMMTX_M0TOS2_RND_THR(_X_)                   ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BIT_ARMMTX_M0TOS2_ADJ_EN                          ( BIT(19) )
+#define BIT_ARMMTX_M0TOS2_RND_EN                          ( BIT(18) )
+#define BITS_ARMMTX_M0TOS2_SEL(_X_)                       ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_ARMMTX_M5TOS1_RND_THR(_X_)                   ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BIT_ARMMTX_M5TOS1_ADJ_EN                          ( BIT(11) )
+#define BIT_ARMMTX_M5TOS1_RND_EN                          ( BIT(10) )
+#define BITS_ARMMTX_M5TOS1_SEL(_X_)                       ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ARMMTX_M4TOS1_RND_THR(_X_)                   ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_ARMMTX_M4TOS1_ADJ_EN                          ( BIT(3) )
+#define BIT_ARMMTX_M4TOS1_RND_EN                          ( BIT(2) )
+#define BITS_ARMMTX_M4TOS1_SEL(_X_)                       ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL3 */
+#define BITS_ARMMTX_M5TOS2_RND_THR(_X_)                   ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_ARMMTX_M5TOS2_ADJ_EN                          ( BIT(27) )
+#define BIT_ARMMTX_M5TOS2_RND_EN                          ( BIT(26) )
+#define BITS_ARMMTX_M5TOS2_SEL(_X_)                       ( (_X_) << 24 & (BIT(24)|BIT(25)) )
+#define BITS_ARMMTX_M5TOS4_RND_THR(_X_)                   ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BIT_ARMMTX_M5TOS4_ADJ_EN                          ( BIT(19) )
+#define BIT_ARMMTX_M5TOS4_RND_EN                          ( BIT(18) )
+#define BITS_ARMMTX_M5TOS4_SEL(_X_)                       ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_ARMMTX_M3TOS2_RND_THR(_X_)                   ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BIT_ARMMTX_M3TOS2_ADJ_EN                          ( BIT(11) )
+#define BIT_ARMMTX_M3TOS2_RND_EN                          ( BIT(10) )
+#define BITS_ARMMTX_M3TOS2_SEL(_X_)                       ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ARMMTX_M2TOS2_RND_THR(_X_)                   ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_ARMMTX_M2TOS2_ADJ_EN                          ( BIT(3) )
+#define BIT_ARMMTX_M2TOS2_RND_EN                          ( BIT(2) )
+#define BITS_ARMMTX_M2TOS2_SEL(_X_)                       ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL4 */
+#define BITS_ARMMTX_M4TOS3_RND_THR(_X_)                   ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BIT_ARMMTX_M4TOS3_ADJ_EN                          ( BIT(19) )
+#define BIT_ARMMTX_M4TOS3_RND_EN                          ( BIT(18) )
+#define BITS_ARMMTX_M4TOS3_SEL(_X_)                       ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_ARMMTX_M1TOS3_RND_THR(_X_)                   ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BIT_ARMMTX_M1TOS3_ADJ_EN                          ( BIT(11) )
+#define BIT_ARMMTX_M1TOS3_RND_EN                          ( BIT(10) )
+#define BITS_ARMMTX_M1TOS3_SEL(_X_)                       ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ARMMTX_M0TOS3_RND_THR(_X_)                   ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_ARMMTX_M0TOS3_ADJ_EN                          ( BIT(3) )
+#define BIT_ARMMTX_M0TOS3_RND_EN                          ( BIT(2) )
+#define BITS_ARMMTX_M0TOS3_SEL(_X_)                       ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL5 */
+#define BITS_ARMMTX_M4TOS0_RND_THR(_X_)                   ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_ARMMTX_M4TOS0_ADJ_EN                          ( BIT(27) )
+#define BIT_ARMMTX_M4TOS0_RND_EN                          ( BIT(26) )
+#define BITS_ARMMTX_M4TOS0_SEL(_X_)                       ( (_X_) << 24 & (BIT(24)|BIT(25)) )
+#define BITS_ARMMTX_M4TOS4_RND_THR(_X_)                   ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BIT_ARMMTX_M4TOS4_ADJ_EN                          ( BIT(19) )
+#define BIT_ARMMTX_M4TOS4_RND_EN                          ( BIT(18) )
+#define BITS_ARMMTX_M4TOS4_SEL(_X_)                       ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_ARMMTX_M1TOS4_RND_THR(_X_)                   ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BIT_ARMMTX_M1TOS4_ADJ_EN                          ( BIT(11) )
+#define BIT_ARMMTX_M1TOS4_RND_EN                          ( BIT(10) )
+#define BITS_ARMMTX_M1TOS4_SEL(_X_)                       ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ARMMTX_M0TOS4_RND_THR(_X_)                   ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_ARMMTX_M0TOS4_ADJ_EN                          ( BIT(3) )
+#define BIT_ARMMTX_M0TOS4_RND_EN                          ( BIT(2) )
+#define BITS_ARMMTX_M0TOS4_SEL(_X_)                       ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_MTX_PRI_SEL6 */
+#define BITS_ARMMTX_M3TOS5_RND_THR(_X_)                   ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_ARMMTX_M3TOS5_ADJ_EN                          ( BIT(27) )
+#define BIT_ARMMTX_M3TOS5_RND_EN                          ( BIT(26) )
+#define BITS_ARMMTX_M3TOS5_SEL(_X_)                       ( (_X_) << 24 & (BIT(24)|BIT(25)) )
+#define BITS_ARMMTX_M2TOS5_RND_THR(_X_)                   ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BIT_ARMMTX_M2TOS5_ADJ_EN                          ( BIT(19) )
+#define BIT_ARMMTX_M2TOS5_RND_EN                          ( BIT(18) )
+#define BITS_ARMMTX_M2TOS5_SEL(_X_)                       ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_ARMMTX_M1TOS5_RND_THR(_X_)                   ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BIT_ARMMTX_M1TOS5_ADJ_EN                          ( BIT(11) )
+#define BIT_ARMMTX_M1TOS5_RND_EN                          ( BIT(10) )
+#define BITS_ARMMTX_M1TOS5_SEL(_X_)                       ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ARMMTX_M0TOS5_RND_THR(_X_)                   ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_ARMMTX_M0TOS5_ADJ_EN                          ( BIT(3) )
+#define BIT_ARMMTX_M0TOS5_RND_EN                          ( BIT(2) )
+#define BITS_ARMMTX_M0TOS5_SEL(_X_)                       ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_PAUSE */
+#define BIT_MCU_LIGHT_SLEEP_EN                            ( BIT(4) )
+#define BIT_APB_SLEEP                                     ( BIT(3) )
+#define BIT_MCU_DEEP_SLEEP_EN                             ( BIT(2) )
+#define BIT_MCU_SYS_SLEEP_EN                              ( BIT(1) )
+#define BIT_MCU_CORE_SLEEP                                ( BIT(0) )
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_SLP_CTL */
+#define BIT_ARM_DAHB_SLEEP_EN                             ( BIT(4) )
+#define BIT_MCUMTX_AUTO_GATE_EN                           ( BIT(3) )
+#define BIT_MCU_AUTO_GATE_EN                              ( BIT(2) )
+#define BIT_AHB_AUTO_GATE_EN                              ( BIT(1) )
+#define BIT_ARM_AUTO_GATE_EN                              ( BIT(0) )
+
+/* bits definitions for register REG_CP_AHB_RF_AHB_SLP_STS */
+#define BIT_APB_PERI_SLEEP                                ( BIT(3) )
+#define BIT_DSP_MAHB_SLEEP_EN                             ( BIT(2) )
+#define BIT_DMA_BUSY                                      ( BIT(1) )
+#define BIT_EMC_SLEEP                                     ( BIT(0) )
+
+/* bits definitions for register REG_CP_AHB_RF_MCU_CLK_CTL */
+#define BITS_CLK_LZMA_SEL(_X_)                            ( (_X_) << 22 & (BIT(22)|BIT(23)) )
+#define BIT_CLK_CP_DBG_SEL                                ( BIT(21) )
+#define BIT_CLK_MCU_DBG_SEL                               ( BIT(20) )
+#define BITS_CLK_COM_DBG_SEL(_X_)                         ( (_X_) << 18 & (BIT(18)|BIT(19)) )
+#define BITS_CLK_SYS_DBG_SEL(_X_)                         ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_CLK_AHB_DIV(_X_)                             ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_CLK_MCU_DIV(_X_)                             ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) )
+#define BITS_CLK_APB_SEL(_X_)                             ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_CLK_MCU_SEL(_X_)                             ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
+
+/* bits definitions for register REG_CP_AHB_RF_DSP_CTL */
+#define BIT_ASHB_ARMTODSP_EN                              ( BIT(2) )
+#define BIT_FRC_CLK_DSP_EN                                ( BIT(1) )
+#define BIT_DSP_BOOT_EN                                   ( BIT(0) )
+
+/* bits definitions for register REG_CP_AHB_RF_DSP_BOOT_VECTOR */
+#define BITS_DSP_BOOT_VECTOR(_X_)                         (_X_)
+
+/* bits definitions for register REG_CP_AHB_RF_DSP_RST */
+#define BIT_DSP_SYS_SRST                                  ( BIT(1) )
+#define BIT_DSP_CORE_SRST_N                               ( BIT(0) )
+
+/* bits definitions for register REG_CP_AHB_RF_DSP_JTAG_CTL */
+#define BIT_CEVA_SW_JTAG_ENA                              ( BIT(8) )
+#define BIT_STDO                                          ( BIT(4) )
+#define BIT_STCK                                          ( BIT(3) )
+#define BIT_STMS                                          ( BIT(2) )
+#define BIT_STDI                                          ( BIT(1) )
+#define BIT_STRTCK                                        ( BIT(0) )
+
+/* bits definitions for register REG_CP_AHB_RF_MCU_C2C_SEMA */
+#define BITS_MCU_C2C_SEMA(_X_)                            ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_CP_AHB_RF_CHIP_ID */
+#define BITS_CHIP_ID(_X_)                                 (_X_)
+
+#endif
diff --git a/include/soc/sprd/chip_x20/__regs_cp_apb_rf.h b/include/soc/sprd/chip_x20/__regs_cp_apb_rf.h
new file mode 100644
index 00000000..37a4d057
--- /dev/null
+++ b/include/soc/sprd/chip_x20/__regs_cp_apb_rf.h
@@ -0,0 +1,203 @@
+/*
+ * Copyright (C) 2014 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+#ifndef __SCI_GLB_REGS_H__
+#error  "Don't include this file directly, Pls include sci_glb_regs.h"
+#endif
+
+
+#ifndef __H_REGS_CP_APB_RF_HEADFILE_H__
+#define __H_REGS_CP_APB_RF_HEADFILE_H__ __FILE__
+
+#define	REGS_CP_APB_RF
+
+/* registers definitions for CP_APB_RF */
+#define REG_CP_APB_RF_APB_EB0_STS                         SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0008)
+#define REG_CP_APB_RF_APB_RST0_STS                        SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0014)
+#define REG_CP_APB_RF_APB_MCU_RST                         SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0018)
+#define REG_CP_APB_RF_APB_CLK_SEL0                        SCI_ADDR(REGS_CP_APB_RF_BASE, 0x001C)
+#define REG_CP_APB_RF_APB_CLK_DIV0                        SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0020)
+#define REG_CP_APB_RF_APB_ARCH_EB                         SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0024)
+#define REG_CP_APB_RF_APB_MISC_CTL0                       SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0028)
+#define REG_CP_APB_RF_APB_MISC_CTL1                       SCI_ADDR(REGS_CP_APB_RF_BASE, 0x002C)
+#define REG_CP_APB_RF_APB_PIN_SEL                         SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0040)
+#define REG_CP_APB_RF_APB_SLP_CTL                         SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0044)
+#define REG_CP_APB_RF_APB_WSYS_STS                        SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0048)
+#define REG_CP_APB_RF_APB_SLP_STS                         SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0050)
+#define REG_CP_APB_RF_APB_ROM_PD_CTL                      SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0054)
+#define REG_CP_APB_RF_APB_BUS_CTL0                        SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0058)
+#define REG_CP_APB_RF_APB_DSP_INT_CLR                     SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0074)
+#define REG_CP_APB_RF_APB_MISC_INT_STS                    SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0078)
+#define REG_CP_APB_RF_APB_HWRST                           SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0080)
+#define REG_CP_APB_RF_APB_ARM_BOOT_ADDR                   SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0084)
+
+
+
+/* bits definitions for register REG_CP_APB_RF_APB_EB0_STS */
+#define BIT_ADA_EB                                        ( BIT(18) )
+#define BIT_RFFE_EB                                       ( BIT(17) )
+#define BIT_EPT_EB                                        ( BIT(16) )
+#define BIT_GPIO_EB                                       ( BIT(15) )
+#define BIT_TMR_RTC_EB                                    ( BIT(14) )
+#define BIT_TMR_EB                                        ( BIT(13) )
+#define BIT_SYSTMR_RTC_EB                                 ( BIT(12) )
+#define BIT_SYSTMR_EB                                     ( BIT(11) )
+#define BIT_IIS3_EB                                       ( BIT(10) )
+#define BIT_IIS2_EB                                       ( BIT(9) )
+#define BIT_IIS1_EB                                       ( BIT(8) )
+#define BIT_IIS0_EB                                       ( BIT(7) )
+#define BIT_SIM2_EB                                       ( BIT(6) )
+#define BIT_SIM1_EB                                       ( BIT(5) )
+#define BIT_SIM0_EB                                       ( BIT(4) )
+#define BIT_UART1_EB                                      ( BIT(3) )
+#define BIT_UART0_EB                                      ( BIT(2) )
+#define BIT_WDG_RTC_EB                                    ( BIT(1) )
+#define BIT_WDG_EB                                        ( BIT(0) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_RST0_STS */
+#define BIT_ADA_TX_SOFT_RST                               ( BIT(18) )
+#define BIT_ADA_RX_SOFT_RST                               ( BIT(17) )
+#define BIT_ADA_SOFT_RST                                  ( BIT(16) )
+#define BIT_RFFE_SOFT_RST                                 ( BIT(15) )
+#define BIT_MCU_DSP_RST                                   ( BIT(14) )
+#define BIT_EPT_SOFT_RST                                  ( BIT(13) )
+#define BIT_GPIO_SOFT_RST                                 ( BIT(12) )
+#define BIT_TMR_SOFT_RST                                  ( BIT(11) )
+#define BIT_SYSTMR_SOFT_RST                               ( BIT(10) )
+#define BIT_IIS3_SOFT_RST                                 ( BIT(9) )
+#define BIT_IIS2_SOFT_RST                                 ( BIT(8) )
+#define BIT_IIS1_SOFT_RST                                 ( BIT(7) )
+#define BIT_IIS0_SOFT_RST                                 ( BIT(6) )
+#define BIT_SIM2_SOFT_RST                                 ( BIT(5) )
+#define BIT_SIM1_SOFT_RST                                 ( BIT(4) )
+#define BIT_SIM0_SOFT_RST                                 ( BIT(3) )
+#define BIT_UART1_SOFT_RST                                ( BIT(2) )
+#define BIT_UART0_SOFT_RST                                ( BIT(1) )
+#define BIT_WDG_SOFT_RST                                  ( BIT(0) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_MCU_RST */
+#define BIT_MCU_SOFT_RST_SET                              ( BIT(0) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_CLK_SEL0 */
+#define BITS_CLK_IIS3_SEL(_X_)                            ( (_X_) << 10 & (BIT(10)|BIT(11)) )
+#define BITS_CLK_IIS2_SEL(_X_)                            ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_CLK_IIS1_SEL(_X_)                            ( (_X_) << 6 & (BIT(6)|BIT(7)) )
+#define BITS_CLK_IIS0_SEL(_X_)                            ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_CLK_UART1_SEL(_X_)                           ( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_CLK_UART0_SEL(_X_)                           ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_CLK_DIV0 */
+#define BITS_CLK_IIS2_DIV(_X_)                            ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
+#define BITS_CLK_IIS1_DIV(_X_)                            ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)) )
+#define BITS_CLK_IIS0_DIV(_X_)                            ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
+#define BITS_CLK_UART1_DIV(_X_)                           ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) )
+#define BITS_CLK_UART0_DIV(_X_)                           ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_ARCH_EB */
+#define BITS_CLK_IIS3_DIV(_X_)                            ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
+#define BIT_RTC_ARCH_EB                                   ( BIT(1) )
+#define BIT_APB_ARCH_EB                                   ( BIT(0) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_MISC_CTL0 */
+#define BIT_ALL_CLK_EN                                    ( BIT(28) )
+#define BIT_DMA_LSLP_EN                                   ( BIT(27) )
+#define BIT_WAKEUP_XTL_EN_3G_W                            ( BIT(26) )
+#define BIT_WAKEUP_XTL_EN_2G                              ( BIT(25) )
+#define BIT_ARM_JTAG_EN                                   ( BIT(24) )
+#define BIT_WAKEUP_XTL_EN_3G_TD                           ( BIT(23) )
+#define BITS_ARM_FRC_STOP(_X_)                            ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_MISC_CTL1 */
+#define BITS_BUFON_CTRL(_X_)                              ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) )
+#define BIT_SIM2_CLK_POLARITY                             ( BIT(3) )
+#define BIT_SIM1_CLK_POLARITY                             ( BIT(2) )
+#define BIT_SIM0_CLK_POLARITY                             ( BIT(1) )
+#define BIT_ROM_CLK_EN                                    ( BIT(0) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_PIN_SEL */
+#define BIT_DJTAG_PIN_IN_SEL                              ( BIT(0) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_SLP_CTL */
+#define BIT_APB_PERI_FRC_ON                               ( BIT(20) )
+#define BIT_APB_PERI_FRC_SLP                              ( BIT(16) )
+#define BIT_MCU_XTLEN_AUTOPD_EN                           ( BIT(12) )
+#define BIT_CHIP_SLP_ARM_CLR                              ( BIT(4) )
+#define BIT_MCU_FORCE_WSYS_LT_STOP                        ( BIT(2) )
+#define BIT_MCU_FORCE_WSYS_STOP                           ( BIT(1) )
+#define BIT_MCU_FORCE_DEEP_SLEEP                          ( BIT(0) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_WSYS_STS */
+#define BITS_DEEP_SLP_DBG(_X_)                            ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_WSYS_STATUS(_X_)                             ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_SLP_STS */
+#define BIT_DSP_MAHB_SLEEP_EN                             ( BIT(28) )
+#define BIT_MCU_PERI_STOP                                 ( BIT(27) )
+#define BIT_DSP_PERI_STOP                                 ( BIT(26) )
+#define BIT_ECC_CKG_EN                                    ( BIT(25) )
+#define BIT_QBC_CKG_EN                                    ( BIT(24) )
+#define BIT_DSP_DPLL_EN                                   ( BIT(23) )
+#define BIT_DSP_TDPLL_EN                                  ( BIT(22) )
+#define BIT_DSP_MPLL_EN                                   ( BIT(21) )
+#define BIT_STC_TMR_AUTOPD_XTL_EN                         ( BIT(20) )
+#define BIT_RFT_TMR_AUTOPD_XTL_EN                         ( BIT(19) )
+#define BIT_STC_TMR_AUTOPD_RF_EN                          ( BIT(18) )
+#define BIT_RFT_TMR_AUTOPD_RF_EN                          ( BIT(17) )
+#define BIT_CHIP_SLEEP_REC_ARM                            ( BIT(16) )
+#define BIT_DSP_CORE_STOP                                 ( BIT(15) )
+#define BIT_DSP_MTX_STOP                                  ( BIT(14) )
+#define BIT_DSP_AHB_STOP                                  ( BIT(13) )
+#define BIT_DSP_SYS_STOP                                  ( BIT(12) )
+#define BIT_DSP_DEEP_STOP                                 ( BIT(11) )
+#define BIT_ASHB_DSPTOARM_EN                              ( BIT(10) )
+#define BIT_ASHB_ARMTODSP_VALID                           ( BIT(9) )
+#define BIT_EMC_STOP_CH3                                  ( BIT(8) )
+#define BIT_EMC_STOP_CH4                                  ( BIT(7) )
+#define BIT_EMC_STOP_CH5                                  ( BIT(6) )
+#define BIT_FRC_WAKE_EN                                   ( BIT(5) )
+#define BIT_TMR_WAKE_AFC                                  ( BIT(4) )
+#define BIT_SCH_SLEEP                                     ( BIT(3) )
+#define BIT_DSP_STOP                                      ( BIT(2) )
+#define BIT_MCU_STOP                                      ( BIT(1) )
+#define BIT_EMC_STOP                                      ( BIT(0) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_ROM_PD_CTL */
+#define BIT_ROM_FORCE_ON                                  ( BIT(0) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_BUS_CTL0 */
+#define BIT_ADA_CTRL_SEL                                  ( BIT(6) )
+#define BIT_RFFE_CTRL_SEL                                 ( BIT(5) )
+#define BIT_IIS3_CTRL_SEL                                 ( BIT(4) )
+#define BIT_IIS2_CTRL_SEL                                 ( BIT(3) )
+#define BIT_IIS1_CTRL_SEL                                 ( BIT(2) )
+#define BIT_IIS0_CTRL_SEL                                 ( BIT(1) )
+#define BIT_UART1_CTRL_SEL                                ( BIT(0) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_DSP_INT_CLR */
+#define BIT_RFT_INT_CLR                                   ( BIT(2) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_MISC_INT_STS */
+#define BIT_RFT_INT                                       ( BIT(2) )
+
+/* bits definitions for register REG_CP_APB_RF_APB_HWRST */
+#define BITS_HWRST_REG(_X_)                               (_X_)
+
+/* bits definitions for register REG_CP_APB_RF_APB_ARM_BOOT_ADDR */
+#define BITS_ARMBOOT_ADDR(_X_)                            ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+#endif
diff --git a/include/soc/sprd/chip_x20/__regs_gpu_apb_rf.h b/include/soc/sprd/chip_x20/__regs_gpu_apb_rf.h
new file mode 100644
index 00000000..653b935b
--- /dev/null
+++ b/include/soc/sprd/chip_x20/__regs_gpu_apb_rf.h
@@ -0,0 +1,44 @@
+/* the head file modifier:     ang   2015-01-13 20:56:47*/
+
+/*  
+* Copyright (C) 2013 Spreadtrum Communications Inc.  
+*
+* This program is free software; you can redistribute it and/or  
+* modify it under the terms of the GNU General Public License 
+* as published by the Free Software Foundation; either version 2 
+* of the License, or (at your option) any later version.  
+* 
+* This program is distributed in the hope that it will be useful, 
+* but WITHOUT ANY WARRANTY; without even the implied warranty of 
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the  
+* GNU General Public License for more details.  
+* 
+*************************************************  
+* Automatically generated C header: do not edit *  
+*************************************************  
+*/  
+
+#ifndef __SCI_GLB_REGS_H__  
+#error  "Don't include this file directly, Pls include sci_glb_regs.h" 
+#endif 
+
+
+#ifndef __H_REGS_GPU_APB_HEADFILE_H__
+#define __H_REGS_GPU_APB_HEADFILE_H__ __FILE__
+
+#define  REGS_GPU_APB
+
+/* registers definitions for GPU_APB */
+#define REG_GPU_APB_APB_RST				SCI_ADDR(REGS_GPU_APB_BASE, 0x0000)/*APB_RST*/
+#define REG_GPU_APB_APB_CLK_CTRL			SCI_ADDR(REGS_GPU_APB_BASE, 0x0004)/*APB_CLK_CTRL*/
+
+
+
+/* bits definitions for register REG_GPU_APB_APB_RST */
+#define BIT_GPU_SOFT_RST					( BIT(0) )
+
+/* bits definitions for register REG_GPU_APB_APB_CLK_CTRL */
+#define BITS_CLK_GPU_DIV(_X_)					( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_CLK_GPU_SEL(_X_)					( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
+
+#endif
diff --git a/include/soc/sprd/chip_x20/__regs_mm_ahb_rf.h b/include/soc/sprd/chip_x20/__regs_mm_ahb_rf.h
new file mode 100644
index 00000000..57b83d30
--- /dev/null
+++ b/include/soc/sprd/chip_x20/__regs_mm_ahb_rf.h
@@ -0,0 +1,102 @@
+/* the head file modifier:     ang   2015-01-13 20:58:18*/
+
+/*  
+* Copyright (C) 2013 Spreadtrum Communications Inc.  
+*
+* This program is free software; you can redistribute it and/or  
+* modify it under the terms of the GNU General Public License 
+* as published by the Free Software Foundation; either version 2 
+* of the License, or (at your option) any later version.  
+* 
+* This program is distributed in the hope that it will be useful, 
+* but WITHOUT ANY WARRANTY; without even the implied warranty of 
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the  
+* GNU General Public License for more details.  
+* 
+*************************************************  
+* Automatically generated C header: do not edit *  
+*************************************************  
+*/  
+
+#ifndef __SCI_GLB_REGS_H__  
+#error  "Don't include this file directly, Pls include sci_glb_regs.h" 
+#endif 
+
+
+#ifndef __H_REGS_MM_AHB_HEADFILE_H__
+#define __H_REGS_MM_AHB_HEADFILE_H__ __FILE__
+
+#define  REGS_MM_AHB
+
+/* registers definitions for MM_AHB */
+#define REG_MM_AHB_AHB_EB				SCI_ADDR(REGS_MM_AHB_BASE, 0x0000)/*AHB_EB*/
+#define REG_MM_AHB_AHB_RST				SCI_ADDR(REGS_MM_AHB_BASE, 0x0004)/*AHB_RST*/
+#define REG_MM_AHB_GEN_CKG_CFG				SCI_ADDR(REGS_MM_AHB_BASE, 0x0008)/*GEN_CKG_CFG*/
+#define REG_MM_AHB_MIPI_CSI2_CTRL			SCI_ADDR(REGS_MM_AHB_BASE, 0x000C)/*MIPI_CSI2_CTRL*/
+#define REG_MM_AHB_MM_QOS_CFG_0				SCI_ADDR(REGS_MM_AHB_BASE, 0x0010)/*MM_QOS_CFG_0*/
+#define REG_MM_AHB_MM_QOS_CFG_1				SCI_ADDR(REGS_MM_AHB_BASE, 0x0014)/*MM_QOS_CFG_1*/
+
+
+
+/* bits definitions for register REG_MM_AHB_AHB_EB */
+#define BIT_VPP_EB						( BIT(8) )
+#define BIT_MMU_EB						( BIT(7) )
+#define BIT_MM_CKG_EB                                        ( BIT(6) )
+#define BIT_JPG_EB						( BIT(5) )
+#define BIT_CSI_EB						( BIT(4) )
+#define BIT_VSP_EB						( BIT(3) )
+#define BIT_ISP_EB						( BIT(2) )
+#define BIT_CCIR_EB						( BIT(1) )
+#define BIT_DCAM_EB						( BIT(0) )
+
+/* bits definitions for register REG_MM_AHB_AHB_RST */
+#define BIT_VPP_SOFT_RST					( BIT(15) )
+#define BIT_MMU_SOFT_RST					( BIT(14) )
+#define BIT_MM_CKG_SOFT_RST                                  ( BIT(13) )
+#define BIT_MM_MTX_SOFT_RST					( BIT(12) )
+#define BIT_OR1200_SOFT_RST					( BIT(11) )
+#define BIT_ROT_SOFT_RST					( BIT(10) )
+#define BIT_CAM2_SOFT_RST					( BIT(9) )
+#define BIT_CAM1_SOFT_RST					( BIT(8) )
+#define BIT_CAM0_SOFT_RST					( BIT(7) )
+#define BIT_JPG_SOFT_RST					( BIT(6) )
+#define BIT_CSI_SOFT_RST					( BIT(5) )
+#define BIT_VSP_SOFT_RST					( BIT(4) )
+#define BIT_ISP_CFG_SOFT_RST					( BIT(3) )
+#define BIT_ISP_LOG_SOFT_RST					( BIT(2) )
+#define BIT_CCIR_SOFT_RST					( BIT(1) )
+#define BIT_DCAM_SOFT_RST					( BIT(0) )
+
+/* bits definitions for register REG_MM_AHB_GEN_CKG_CFG */
+#define BIT_VPP_AXI_CKG_EN					( BIT(9) )
+#define BIT_MM_MTX_AXI_CKG_EN					( BIT(8) )
+#define BIT_MM_AXI_CKG_EN					( BIT(7) )
+#define BIT_JPG_AXI_CKG_EN					( BIT(6) )
+#define BIT_VSP_AXI_CKG_EN					( BIT(5) )
+#define BIT_ISP_AXI_CKG_EN					( BIT(4) )
+#define BIT_DCAM_AXI_CKG_EN					( BIT(3) )
+#define BIT_SENSOR_CKG_EN					( BIT(2) )
+#define BIT_MIPI_CSI_CKG_EN					( BIT(1) )
+#define BIT_CPHY_CFG_CKG_EN					( BIT(0) )
+
+/* bits definitions for register REG_MM_AHB_MIPI_CSI2_CTRL */
+#define BITS_MIPI_CPHY_SAMPLE_SEL(_X_)				( (_X_) << 3 & (BIT(3)|BIT(4)) )
+#define BIT_MIPI_CPHY_SYNC_MODE					( BIT(2) )
+#define BIT_MIPI_CPHY_TEST_CTL					( BIT(1) )
+#define BIT_MIPI_CPHY_SEL					( BIT(0) )
+
+/* bits definitions for register REG_MM_AHB_MM_QOS_CFG_0 */
+#define BITS_QOS_R_DCAM(_X_)					( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_QOS_W_DCAM(_X_)					( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_QOS_R_JPG(_X_)					( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_QOS_W_JPG(_X_)					( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_QOS_R_ISP(_X_)					( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_QOS_W_ISP(_X_)					( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_QOS_R_VSP(_X_)					( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_QOS_W_VSP(_X_)					( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_MM_AHB_MM_QOS_CFG_1 */
+#define BITS_QOS_R_VPP(_X_)					( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_QOS_W_VPP(_X_)					( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+#endif
diff --git a/include/soc/sprd/chip_x20/__regs_mm_clk.h b/include/soc/sprd/chip_x20/__regs_mm_clk.h
new file mode 100644
index 00000000..6a3d7e65
--- /dev/null
+++ b/include/soc/sprd/chip_x20/__regs_mm_clk.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2012 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+#ifndef __REGS_MM_CLK_H__
+#define __REGS_MM_CLK_H__
+
+#ifndef __SCI_GLB_REGS_H__
+#error  "Don't include this file directly, include <mach/sci_glb_regs.h>"
+#endif
+
+#define REGS_MM_CLK
+
+/* registers definitions for controller REGS_MM_CLK */
+#define REG_MM_CLK_MM_AHB_CFG           SCI_ADDR(REGS_MM_CLK_BASE, 0x0020)
+#define REG_MM_CLK_SENSOR_CFG           SCI_ADDR(REGS_MM_CLK_BASE, 0x0024)
+#define REG_MM_CLK_CCIR_CFG             SCI_ADDR(REGS_MM_CLK_BASE, 0x0028)
+#define REG_MM_CLK_DCAM_CFG             SCI_ADDR(REGS_MM_CLK_BASE, 0x002c)
+#define REG_MM_CLK_VSP_CFG              SCI_ADDR(REGS_MM_CLK_BASE, 0x0030)
+#define REG_MM_CLK_ISP_CFG              SCI_ADDR(REGS_MM_CLK_BASE, 0x0034)
+#define REG_MM_CLK_JPG_CFG              SCI_ADDR(REGS_MM_CLK_BASE, 0x0038)
+#define REG_MM_CLK_VPP_CFG              SCI_ADDR(REGS_MM_CLK_BASE, 0x003C)
+
+/* vars definitions for controller REGS_MM_CLK */
+
+#endif //__REGS_MM_CLK_H__
diff --git a/include/soc/sprd/chip_x20/__regs_pinmap.h b/include/soc/sprd/chip_x20/__regs_pinmap.h
new file mode 100755
index 00000000..49ab259a
--- /dev/null
+++ b/include/soc/sprd/chip_x20/__regs_pinmap.h
@@ -0,0 +1,274 @@
+#ifndef __ASM_ARM_ARCH_PINMAP_H
+#error  "Don't include this file directly, Pls include pinmap.h"
+#endif
+
+#ifndef _REGS_PINMAP_H_
+#define _REGS_PINMAP_H_
+
+#define CTL_PIN_BASE			(SPRD_PIN_BASE)
+
+/* registers definitions for controller CTL_PIN */
+#define REG_PIN_CTRL0                   ( 0x0000 )
+#define REG_PIN_CTRL1                   ( 0x0004 )
+#define REG_PIN_CTRL2                   ( 0x0008 )
+#define REG_PIN_CTRL3                   ( 0x000c )
+#define REG_PIN_CTRL4                   ( 0x0010 )
+#define REG_PIN_CTRL5                   ( 0x0014 )
+
+#define REG_PIN_TRACECLK                ( 0x0020 )
+#define REG_PIN_TRACECTRL               ( 0x0024 )
+#define REG_PIN_TRACEDAT0               ( 0x0028 )
+#define REG_PIN_TRACEDAT1               ( 0x002c )
+#define REG_PIN_TRACEDAT2               ( 0x0030 )
+#define REG_PIN_TRACEDAT3               ( 0x0034 )
+#define REG_PIN_TRACEDAT4               ( 0x0038 )
+#define REG_PIN_TRACEDAT5               ( 0x003c )
+#define REG_PIN_TRACEDAT6               ( 0x0040 )
+#define REG_PIN_TRACEDAT7               ( 0x0044 )
+#define REG_PIN_U0TXD                   ( 0x0048 )
+#define REG_PIN_U0RXD                   ( 0x004c )
+#define REG_PIN_U0CTS                   ( 0x0050 )
+#define REG_PIN_U0RTS                   ( 0x0054 )
+#define REG_PIN_U1TXD                   ( 0x0058 )
+#define REG_PIN_U1RXD                   ( 0x005c )
+#define REG_PIN_U2TXD                   ( 0x0060 )
+#define REG_PIN_U2RXD                   ( 0x0064 )
+#define REG_PIN_U3TXD                   ( 0x0068 )
+#define REG_PIN_U3RXD                   ( 0x006c )
+#define REG_PIN_U3CTS                   ( 0x0070 )
+#define REG_PIN_U3RTS                   ( 0x0074 )
+#define REG_PIN_CP2_RFCTL0              ( 0x0078 )
+#define REG_PIN_CP2_RFCTL1              ( 0x007c )
+#define REG_PIN_CP2_RFCTL2              ( 0x0080 )
+#define REG_PIN_WIFI_AGCGAIN3           ( 0x0084 )
+#define REG_PIN_WIFI_AGCGAIN4           ( 0x0088 )
+#define REG_PIN_WIFI_AGCGAIN5           ( 0x008c )
+#define REG_PIN_WIFI_AGCGAIN6           ( 0x0090 )
+#define REG_PIN_RFSDA0                  ( 0x0094 )
+#define REG_PIN_RFSCK0                  ( 0x0098 )
+#define REG_PIN_RFSEN0                  ( 0x009c )
+#define REG_PIN_RFSDA1                  ( 0x00a0 )
+#define REG_PIN_RFSCK1                  ( 0x00a4 )
+#define REG_PIN_RFSEN1                  ( 0x00a8 )
+#define REG_PIN_CP1_RFCTL0              ( 0x00ac )
+#define REG_PIN_CP1_RFCTL1              ( 0x00b0 )
+#define REG_PIN_CP1_RFCTL2              ( 0x00b4 )
+#define REG_PIN_CP1_RFCTL3              ( 0x00b8 )
+#define REG_PIN_CP1_RFCTL4              ( 0x00bc )
+#define REG_PIN_CP1_RFCTL5              ( 0x00c0 )
+#define REG_PIN_CP1_RFCTL6              ( 0x00c4 )
+#define REG_PIN_CP1_RFCTL7              ( 0x00c8 )
+#define REG_PIN_CP1_RFCTL8              ( 0x00cc )
+#define REG_PIN_CP1_RFCTL9              ( 0x00d0 )
+#define REG_PIN_CP1_RFCTL10             ( 0x00d4 )
+#define REG_PIN_CP1_RFCTL11             ( 0x00d8 )
+#define REG_PIN_CP1_RFCTL12             ( 0x00dc )
+#define REG_PIN_CP1_RFCTL13             ( 0x00e0 )
+#define REG_PIN_CP1_RFCTL14             ( 0x00e4 )
+#define REG_PIN_CP1_RFCTL15             ( 0x00e8 )
+#define REG_PIN_CP0_RFCTL0              ( 0x00ec )
+#define REG_PIN_CP0_RFCTL1              ( 0x00f0 )
+#define REG_PIN_CP0_RFCTL2              ( 0x00f4 )
+#define REG_PIN_CP0_RFCTL3              ( 0x00f8 )
+#define REG_PIN_CP0_RFCTL4              ( 0x00fc )
+#define REG_PIN_CP0_RFCTL5              ( 0x0100 )
+#define REG_PIN_CP0_RFCTL6              ( 0x0104 )
+#define REG_PIN_CP0_RFCTL7              ( 0x0108 )
+#define REG_PIN_XTLEN                   ( 0x010c )
+#define REG_PIN_SCL3                    ( 0x0110 )
+#define REG_PIN_SDA3                    ( 0x0114 )
+#define REG_PIN_SPI0_CSN                ( 0x0118 )
+#define REG_PIN_SPI0_DO                 ( 0x011c )
+#define REG_PIN_SPI0_DI                 ( 0x0120 )
+#define REG_PIN_SPI0_CLK                ( 0x0124 )
+#define REG_PIN_EXTINT0                 ( 0x0128 )
+#define REG_PIN_EXTINT1                 ( 0x012c )
+#define REG_PIN_SCL1                    ( 0x0130 )
+#define REG_PIN_SDA1                    ( 0x0134 )
+#define REG_PIN_SIMCLK0                 ( 0x0138 )
+#define REG_PIN_SIMDA0                  ( 0x013c )
+#define REG_PIN_SIMRST0                 ( 0x0140 )
+#define REG_PIN_SIMCLK1                 ( 0x0144 )
+#define REG_PIN_SIMDA1                  ( 0x0148 )
+#define REG_PIN_SIMRST1                 ( 0x014c )
+#define REG_PIN_SIMCLK2                 ( 0x0150 )
+#define REG_PIN_SIMDA2                  ( 0x0154 )
+#define REG_PIN_SIMRST2                 ( 0x0158 )
+#define REG_PIN_MEMS_MIC_CLK0           ( 0x015c )
+#define REG_PIN_MEMS_MIC_DATA0          ( 0x0160 )
+#define REG_PIN_MEMS_MIC_CLK1           ( 0x0164 )
+#define REG_PIN_MEMS_MIC_DATA1          ( 0x0168 )
+#define REG_PIN_SD1_CLK                 ( 0x016c )
+#define REG_PIN_SD1_CMD                 ( 0x0170 )
+#define REG_PIN_SD1_D0                  ( 0x0174 )
+#define REG_PIN_SD1_D1                  ( 0x0178 )
+#define REG_PIN_SD1_D2                  ( 0x017c )
+#define REG_PIN_SD1_D3                  ( 0x0180 )
+#define REG_PIN_SD0_D3                  ( 0x0184 )
+#define REG_PIN_SD0_D2                  ( 0x0188 )
+#define REG_PIN_SD0_CMD                 ( 0x018c )
+#define REG_PIN_SD0_D0                  ( 0x0190 )
+#define REG_PIN_SD0_D1                  ( 0x0194 )
+#define REG_PIN_SD0_CLK1                ( 0x0198 )
+#define REG_PIN_SD0_CLK0                ( 0x019c )
+#define REG_PIN_PTEST                   ( 0x01a0 )
+#define REG_PIN_ANA_INT                 ( 0x01a4 )
+#define REG_PIN_EXT_RST_B               ( 0x01a8 )
+#define REG_PIN_CHIP_SLEEP              ( 0x01ac )
+#define REG_PIN_XTL_BUF_EN0             ( 0x01b0 )
+#define REG_PIN_XTL_BUF_EN1             ( 0x01b4 )
+#define REG_PIN_XTL_BUF_EN2             ( 0x01b8 )
+#define REG_PIN_CLK_32K                 ( 0x01bc )
+#define REG_PIN_AUD_SCLK                ( 0x01c0 )
+#define REG_PIN_AUD_DANGL               ( 0x01c4 )
+#define REG_PIN_AUD_DANGR               ( 0x01c8 )
+#define REG_PIN_AUD_ADD0                ( 0x01cc )
+#define REG_PIN_AUD_ADSYNC              ( 0x01d0 )
+#define REG_PIN_AUD_DAD1                ( 0x01d4 )
+#define REG_PIN_AUD_DAD0                ( 0x01d8 )
+#define REG_PIN_AUD_DASYNC              ( 0x01dc )
+#define REG_PIN_ADI_D                   ( 0x01e0 )
+#define REG_PIN_ADI_SYNC                ( 0x01e4 )
+#define REG_PIN_ADI_SCLK                ( 0x01e8 )
+#define REG_PIN_LCD_CSN1                ( 0x01ec )
+#define REG_PIN_LCD_CSN0                ( 0x01f0 )
+#define REG_PIN_LCD_RSTN                ( 0x01f4 )
+#define REG_PIN_LCD_CD                  ( 0x01f8 )
+#define REG_PIN_LCD_FMARK               ( 0x01fc )
+#define REG_PIN_LCD_WRN                 ( 0x0200 )
+#define REG_PIN_LCD_RDN                 ( 0x0204 )
+#define REG_PIN_LCD_D0                  ( 0x0208 )
+#define REG_PIN_LCD_D1                  ( 0x020c )
+#define REG_PIN_LCD_D2                  ( 0x0210 )
+#define REG_PIN_LCD_D3                  ( 0x0214 )
+#define REG_PIN_LCD_D4                  ( 0x0218 )
+#define REG_PIN_LCD_D5                  ( 0x021c )
+#define REG_PIN_LCD_D6                  ( 0x0220 )
+#define REG_PIN_LCD_D7                  ( 0x0224 )
+#define REG_PIN_LCD_D8                  ( 0x0228 )
+#define REG_PIN_LCD_D9                  ( 0x022c )
+#define REG_PIN_LCD_D10                 ( 0x0230 )
+#define REG_PIN_LCD_D11                 ( 0x0234 )
+#define REG_PIN_LCD_D12                 ( 0x0238 )
+#define REG_PIN_LCD_D13                 ( 0x023c )
+#define REG_PIN_LCD_D14                 ( 0x0240 )
+#define REG_PIN_LCD_D15                 ( 0x0244 )
+#define REG_PIN_LCD_D16                 ( 0x0248 )
+#define REG_PIN_LCD_D17                 ( 0x024c )
+#define REG_PIN_LCD_D18                 ( 0x0250 )
+#define REG_PIN_LCD_D19                 ( 0x0254 )
+#define REG_PIN_LCD_D20                 ( 0x0258 )
+#define REG_PIN_LCD_D21                 ( 0x025c )
+#define REG_PIN_LCD_D22                 ( 0x0260 )
+#define REG_PIN_LCD_D23                 ( 0x0264 )
+#define REG_PIN_SPI2_CSN                ( 0x0268 )
+#define REG_PIN_SPI2_DO                 ( 0x026c )
+#define REG_PIN_SPI2_DI                 ( 0x0270 )
+#define REG_PIN_SPI2_CLK                ( 0x0274 )
+#define REG_PIN_EMMC_CLK                ( 0x0278 )
+#define REG_PIN_EMMC_CMD                ( 0x027c )
+#define REG_PIN_EMMC_D0                 ( 0x0280 )
+#define REG_PIN_EMMC_D1                 ( 0x0284 )
+#define REG_PIN_EMMC_D2                 ( 0x0288 )
+#define REG_PIN_EMMC_D3                 ( 0x028c )
+#define REG_PIN_EMMC_D4                 ( 0x0290 )
+#define REG_PIN_EMMC_D5                 ( 0x0294 )
+#define REG_PIN_EMMC_D6                 ( 0x0298 )
+#define REG_PIN_EMMC_D7                 ( 0x029c )
+#define REG_PIN_EMMC_RST                ( 0x02a0 )
+#define REG_PIN_NFWPN                   ( 0x02a4 )
+#define REG_PIN_NFRB                    ( 0x02a8 )
+#define REG_PIN_NFCLE                   ( 0x02ac )
+#define REG_PIN_NFALE                   ( 0x02b0 )
+#define REG_PIN_NFCEN0                  ( 0x02b4 )
+#define REG_PIN_NFCEN1                  ( 0x02b8 )
+#define REG_PIN_NFREN                   ( 0x02bc )
+#define REG_PIN_NFWEN                   ( 0x02c0 )
+#define REG_PIN_NFD0                    ( 0x02c4 )
+#define REG_PIN_NFD1                    ( 0x02c8 )
+#define REG_PIN_NFD2                    ( 0x02cc )
+#define REG_PIN_NFD3                    ( 0x02d0 )
+#define REG_PIN_NFD4                    ( 0x02d4 )
+#define REG_PIN_NFD5                    ( 0x02d8 )
+#define REG_PIN_NFD6                    ( 0x02dc )
+#define REG_PIN_NFD7                    ( 0x02e0 )
+#define REG_PIN_NFD8                    ( 0x02e4 )
+#define REG_PIN_NFD9                    ( 0x02e8 )
+#define REG_PIN_NFD10                   ( 0x02ec )
+#define REG_PIN_NFD11                   ( 0x02f0 )
+#define REG_PIN_NFD12                   ( 0x02f4 )
+#define REG_PIN_NFD13                   ( 0x02f8 )
+#define REG_PIN_NFD14                   ( 0x02fc )
+#define REG_PIN_NFD15                   ( 0x0300 )
+#define REG_PIN_CCIRCK0                 ( 0x0304 )
+#define REG_PIN_CCIRCK1                 ( 0x0308 )
+#define REG_PIN_CCIRMCLK                ( 0x030c )
+#define REG_PIN_CCIRHS                  ( 0x0310 )
+#define REG_PIN_CCIRVS                  ( 0x0314 )
+#define REG_PIN_CCIRD0                  ( 0x0318 )
+#define REG_PIN_CCIRD1                  ( 0x031c )
+#define REG_PIN_CCIRD2                  ( 0x0320 )
+#define REG_PIN_CCIRD3                  ( 0x0324 )
+#define REG_PIN_CCIRD4                  ( 0x0328 )
+#define REG_PIN_CCIRD5                  ( 0x032c )
+#define REG_PIN_CCIRD6                  ( 0x0330 )
+#define REG_PIN_CCIRD7                  ( 0x0334 )
+#define REG_PIN_CCIRD8                  ( 0x0338 )
+#define REG_PIN_CCIRD9                  ( 0x033c )
+#define REG_PIN_CCIRRST                 ( 0x0340 )
+#define REG_PIN_CCIRPD1                 ( 0x0344 )
+#define REG_PIN_CCIRPD0                 ( 0x0348 )
+#define REG_PIN_SCL0                    ( 0x034c )
+#define REG_PIN_SDA0                    ( 0x0350 )
+#define REG_PIN_KEYOUT0                 ( 0x0354 )
+#define REG_PIN_KEYOUT1                 ( 0x0358 )
+#define REG_PIN_KEYOUT2                 ( 0x035c )
+#define REG_PIN_KEYIN0                  ( 0x0360 )
+#define REG_PIN_KEYIN1                  ( 0x0364 )
+#define REG_PIN_KEYIN2                  ( 0x0368 )
+#define REG_PIN_SCL2                    ( 0x036c )
+#define REG_PIN_SDA2                    ( 0x0370 )
+#define REG_PIN_CLK_AUX0                ( 0x0374 )
+#define REG_PIN_IIS0DI                  ( 0x0378 )
+#define REG_PIN_IIS0DO                  ( 0x037c )
+#define REG_PIN_IIS0CLK                 ( 0x0380 )
+#define REG_PIN_IIS0LRCK                ( 0x0384 )
+#define REG_PIN_IIS0MCK                 ( 0x0388 )
+#define REG_PIN_IIS1DI                  ( 0x038c )
+#define REG_PIN_IIS1DO                  ( 0x0390 )
+#define REG_PIN_IIS1CLK                 ( 0x0394 )
+#define REG_PIN_IIS1LRCK                ( 0x0398 )
+#define REG_PIN_IIS1MCK                 ( 0x039c )
+#define REG_PIN_MTDO                    ( 0x03a0 )
+#define REG_PIN_MTDI                    ( 0x03a4 )
+#define REG_PIN_MTCK                    ( 0x03a8 )
+#define REG_PIN_MTMS                    ( 0x03ac )
+#define REG_PIN_MTRST_N                 ( 0x03b0 )
+
+
+
+/* bits definitions for register REG_PIN_XXX */
+#define BITS_PIN_DS(_x_)                ( ((_x_) << 18) & (BIT_18|BIT_19|BIT_20|BIT_21) )
+#define BIT_PIN_SLP_AP                  ( BIT_13 )
+#define BIT_PIN_SLP_CP0                 ( BIT_14 )
+#define BIT_PIN_SLP_CP1                 ( BIT_15 )
+#define BIT_PIN_SLP_CP2                 ( BIT_16 )
+#define BITS_PIN_SLP(_x_)               ( ((_x_) << 13) & (BIT_13|BIT_14|BIT_15|BIT_16) )
+#define BIT_PIN_WPU_SEL                 ( BIT_12 )
+#define BIT_PIN_WPU                     ( BIT_7 )
+#define BIT_PIN_WPD                     ( BIT_6 )
+#define BITS_PIN_AF(_x_)                ( ((_x_) << 4) & (BIT_4|BIT_5) )
+#define BIT_PIN_SLP_WPU                 ( BIT_3 )
+#define BIT_PIN_SLP_WPD                 ( BIT_2 )
+#define BIT_PIN_SLP_IE                  ( BIT_1 )
+#define BIT_PIN_SLP_OE                  ( BIT_0 )
+
+/* vars definitions for controller CTL_PIN */
+#define BIT_PIN_NUL                     ( 0 )
+#define BIT_PIN_SLP_NUL                 ( 0 )
+#define BIT_PIN_SLP_Z                   ( 0 )
+#define BIT_PIN_WPU_SEL                 ( BIT_12 )
+#define BIT_PIN_WPUS                    ( BIT_12 )
+#define BIT_PIN_NULL                    ( 0 )
+
+#endif
diff --git a/include/soc/sprd/chip_x20/__regs_pmu_apb.h b/include/soc/sprd/chip_x20/__regs_pmu_apb.h
new file mode 100644
index 00000000..017347f0
--- /dev/null
+++ b/include/soc/sprd/chip_x20/__regs_pmu_apb.h
@@ -0,0 +1,1032 @@
+/* the head file modifier:     ang   2015-01-13 19:49:27*/
+
+/*  
+* Copyright (C) 2013 Spreadtrum Communications Inc.  
+*
+* This program is free software; you can redistribute it and/or  
+* modify it under the terms of the GNU General Public License 
+* as published by the Free Software Foundation; either version 2 
+* of the License, or (at your option) any later version.  
+* 
+* This program is distributed in the hope that it will be useful, 
+* but WITHOUT ANY WARRANTY; without even the implied warranty of 
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the  
+* GNU General Public License for more details.  
+* 
+*************************************************  
+* Automatically generated C header: do not edit *  
+*************************************************  
+*/  
+
+#ifndef __SCI_GLB_REGS_H__  
+#error  "Don't include this file directly, Pls include sci_glb_regs.h" 
+#endif 
+
+
+#ifndef __H_REGS_PMU_APB_HEADFILE_H__
+#define __H_REGS_PMU_APB_HEADFILE_H__ __FILE__
+
+#define  REGS_PMU_APB
+
+/* registers definitions for PMU_APB */
+#define REG_PMU_APB_PD_CA7_TOP_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0000)/*PD_CA7_TOP_CFG*/
+#define REG_PMU_APB_PD_CA7_C0_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0004)/*PD_CA7_C0_CFG*/
+#define REG_PMU_APB_PD_CA7_C1_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0008)/*PD_CA7_C1_CFG*/
+#define REG_PMU_APB_PD_CA7_C2_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x000C)/*PD_CA7_C2_CFG*/
+#define REG_PMU_APB_PD_CA7_C3_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0010)/*PD_CA7_C3_CFG*/
+#define REG_PMU_APB_PD_AP_DISP_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0014)/*PD_AP_DISP_CFG*/
+#define REG_PMU_APB_PD_AP_SYS_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0018)/*PD_AP_SYS_CFG*/
+#define REG_PMU_APB_PD_MM_TOP_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x001C)/*PD_MM_TOP_CFG*/
+#define REG_PMU_APB_PD_GPU_TOP_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0020)/*PD_GPU_TOP_CFG*/
+#define REG_PMU_APB_PD_CP0_ARM9_0_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0024)/*PD_CP0_ARM9_0_CFG*/
+#define REG_PMU_APB_PD_CP0_ARM9_1_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0028)/*PD_CP0_ARM9_1_CFG*/
+#define REG_PMU_APB_PD_CP0_ARM9_2_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x002C)/*PD_CP0_ARM9_2_CFG*/
+#define REG_PMU_APB_PD_CP0_HU3GE_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0030)/*PD_CP0_HU3GE_CFG*/
+#define REG_PMU_APB_PD_CP0_GSM_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0034)/*PD_CP0_GSM_CFG*/
+#define REG_PMU_APB_PD_CP0_TD_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0038)/*PD_CP0_TD_CFG*/
+#define REG_PMU_APB_PD_CP0_CEVA_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x003C)/*PD_CP0_CEVA_CFG*/
+#define REG_PMU_APB_PD_CP0_HARQ_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0040)/*PD_CP0_HARQ_CFG*/
+#define REG_PMU_APB_PD_CP0_SYS_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0044)/*PD_CP0_SYS_CFG*/
+#define REG_PMU_APB_PD_CP1_ARM9_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0048)/*PD_CP1_ARM9_CFG*/
+#define REG_PMU_APB_PD_CP1_GSM_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x004C)/*PD_CP1_GSM_CFG*/
+#define REG_PMU_APB_PD_CP1_TD_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0050)/*PD_CP1_TD_CFG*/
+#define REG_PMU_APB_PD_CP1_L1RAM_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0054)/*PD_CP1_L1RAM_CFG*/
+#define REG_PMU_APB_PD_CP1_SYS_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0058)/*PD_CP1_SYS_CFG*/
+#define REG_PMU_APB_PD_CP2_ARM9_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x005C)/*PD_CP2_ARM9_CFG*/
+#define REG_PMU_APB_PD_CP2_WIFI_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0060)/*PD_CP2_WIFI_CFG*/
+#define REG_PMU_APB_AP_WAKEUP_POR_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0064)/*AP_WAKEUP_POR_CFG*/
+#define REG_PMU_APB_PD_CP2_SYS_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0068)/*PD_CP2_SYS_CFG*/
+#define REG_PMU_APB_PD_PUB_SYS_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x006C)/*PD_PUB_SYS_CFG*/
+#define REG_PMU_APB_XTL_WAIT_CNT			SCI_ADDR(REGS_PMU_APB_BASE, 0x0070)/*XTL_WAIT_CNT*/
+#define REG_PMU_APB_XTLBUF_WAIT_CNT			SCI_ADDR(REGS_PMU_APB_BASE, 0x0074)/*XTLBUF_WAIT_CNT*/
+#define REG_PMU_APB_PLL_WAIT_CNT1			SCI_ADDR(REGS_PMU_APB_BASE, 0x0078)/*PLL_WAIT_CNT1*/
+#define REG_PMU_APB_PLL_WAIT_CNT2			SCI_ADDR(REGS_PMU_APB_BASE, 0x007C)/*PLL_WAIT_CNT2*/
+#define REG_PMU_APB_XTL0_REL_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0080)/*XTL0_REL_CFG*/
+#define REG_PMU_APB_XTL1_REL_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0084)/*XTL1_REL_CFG*/
+#define REG_PMU_APB_XTL2_REL_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0088)/*XTL1_REL_CFG*/
+#define REG_PMU_APB_XTLBUF0_REL_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x008C)/*XTLBUF0_REL_CFG*/
+#define REG_PMU_APB_XTLBUF1_REL_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0090)/*XTLBUF1_REL_CFG*/
+#define REG_PMU_APB_MPLL_REL_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0094)/*MPLL_REL_CFG*/
+#define REG_PMU_APB_DPLL_REL_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0098)/*DPLL_REL_CFG*/
+#define REG_PMU_APB_TDPLL_REL_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x009C)/*TDPLL_REL_CFG*/
+#define REG_PMU_APB_WPLL_REL_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x00A0)/*WPLL_REL_CFG*/
+#define REG_PMU_APB_CPLL_REL_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x00A4)/*CPLL_REL_CFG*/
+#define REG_PMU_APB_WIFIPLL1_REL_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x00A8)/*WIFIPLL1_REL_CFG*/
+#define REG_PMU_APB_WIFIPLL2_REL_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x00AC)/*WIFIPLL2_REL_CFG*/
+#define REG_PMU_APB_CP_SOFT_RST				SCI_ADDR(REGS_PMU_APB_BASE, 0x00B0)/*CP_SOFT_RST*/
+#define REG_PMU_APB_CP_SLP_STATUS_DBG0			SCI_ADDR(REGS_PMU_APB_BASE, 0x00B4)/*CP_SLP_STATUS_DBG0*/
+#define REG_PMU_APB_CP_SLP_STATUS_DBG1			SCI_ADDR(REGS_PMU_APB_BASE, 0x00B8)/*CP_SLP_STATUS_DBG1*/
+#define REG_PMU_APB_PWR_STATUS0_DBG			SCI_ADDR(REGS_PMU_APB_BASE, 0x00BC)/*PWR_STATUS0_DBG*/
+#define REG_PMU_APB_PWR_STATUS1_DBG			SCI_ADDR(REGS_PMU_APB_BASE, 0x00C0)/*PWR_STATUS1_DBG*/
+#define REG_PMU_APB_PWR_STATUS2_DBG			SCI_ADDR(REGS_PMU_APB_BASE, 0x00C4)/*PWR_STATUS2_DBG*/
+#define REG_PMU_APB_PWR_STATUS3_DBG			SCI_ADDR(REGS_PMU_APB_BASE, 0x00C8)/*PWR_STATUS3_DBG*/
+#define REG_PMU_APB_SLEEP_CTRL				SCI_ADDR(REGS_PMU_APB_BASE, 0x00CC)/*SLEEP_CTRL*/
+#define REG_PMU_APB_DDR_SLEEP_CTRL			SCI_ADDR(REGS_PMU_APB_BASE, 0x00D0)/*DDR_SLEEP_CTRL*/
+#define REG_PMU_APB_SLEEP_STATUS			SCI_ADDR(REGS_PMU_APB_BASE, 0x00D4)/*SLEEP_STATUS*/
+#define REG_PMU_APB_PLL_DIV_AUTO_GATE_EN		SCI_ADDR(REGS_PMU_APB_BASE, 0x00D8)/*PLL_DIV_AUTO_GATE_EN*/
+#define REG_PMU_APB_PLL_DIV_EN1				SCI_ADDR(REGS_PMU_APB_BASE, 0x00DC)/*PLL_DIV_EN1*/
+#define REG_PMU_APB_PLL_DIV_EN2				SCI_ADDR(REGS_PMU_APB_BASE, 0x00E0)/*PLL_DIV_EN2*/
+#define REG_PMU_APB_CA7_TOP_CFG				SCI_ADDR(REGS_PMU_APB_BASE, 0x00E4)/*CA7_TOP_CFG*/
+#define REG_PMU_APB_CA7_C0_CFG				SCI_ADDR(REGS_PMU_APB_BASE, 0x00E8)/*CA7_C0_CFG*/
+#define REG_PMU_APB_CA7_C1_CFG				SCI_ADDR(REGS_PMU_APB_BASE, 0x00EC)/*CA7_C1_CFG*/
+#define REG_PMU_APB_CA7_C2_CFG				SCI_ADDR(REGS_PMU_APB_BASE, 0x00F0)/*CA7_C2_CFG*/
+#define REG_PMU_APB_CA7_C3_CFG				SCI_ADDR(REGS_PMU_APB_BASE, 0x00F4)/*CA7_C3_CFG*/
+#define REG_PMU_APB_DDR_CHN_SLEEP_CTRL0			SCI_ADDR(REGS_PMU_APB_BASE, 0x00F8)/*DDR_CHN_SLEEP_CTRL0*/
+#define REG_PMU_APB_DDR_CHN_SLEEP_CTRL1			SCI_ADDR(REGS_PMU_APB_BASE, 0x00FC)/*DDR_CHN_SLEEP_CTRL1*/
+#define REG_PMU_APB_BISR_CFG				SCI_ADDR(REGS_PMU_APB_BASE, 0x0100)/*BISR_CFG*/
+#define REG_PMU_APB_CGM_AP_AUTO_GATE_EN			SCI_ADDR(REGS_PMU_APB_BASE, 0x0104)/*CGM_AP_AUTO_GATE_EN*/
+#define REG_PMU_APB_CGM_GPU_MM_AUTO_GATE_EN		SCI_ADDR(REGS_PMU_APB_BASE, 0x0108)/*CGM_GPU_MM_AUTO_GATE_EN*/
+#define REG_PMU_APB_CGM_CP0_AUTO_GATE_EN		SCI_ADDR(REGS_PMU_APB_BASE, 0x010C)/*CGM_CP0_AUTO_GATE_EN*/
+#define REG_PMU_APB_CGM_CP1_AUTO_GATE_EN		SCI_ADDR(REGS_PMU_APB_BASE, 0x0110)/*CGM_CP1_AUTO_GATE_EN*/
+#define REG_PMU_APB_CGM_CP2_AUTO_GATE_EN		SCI_ADDR(REGS_PMU_APB_BASE, 0x0114)/*CGM_CP2_AUTO_GATE_EN*/
+#define REG_PMU_APB_CGM_AP_EN				SCI_ADDR(REGS_PMU_APB_BASE, 0x0118)/*CGM_AP_EN*/
+#define REG_PMU_APB_CGM_GPU_MM_EN			SCI_ADDR(REGS_PMU_APB_BASE, 0x011C)/*CGM_GPU_MM_EN*/
+#define REG_PMU_APB_CGM_CP0_EN				SCI_ADDR(REGS_PMU_APB_BASE, 0x0120)/*CGM_CP0_EN*/
+#define REG_PMU_APB_CGM_CP1_EN				SCI_ADDR(REGS_PMU_APB_BASE, 0x0124)/*CGM_CP1_EN*/
+#define REG_PMU_APB_CGM_CP2_EN				SCI_ADDR(REGS_PMU_APB_BASE, 0x0128)/*CGM_CP2_EN*/
+#define REG_PMU_APB_DDR_OP_MODE_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x012C)/*DDR_OP_MODE_CFG*/
+#define REG_PMU_APB_DDR_PHY_RET_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0130)/*DDR_PHY_RET_CFG*/
+#define REG_PMU_APB_26M_SEL_CFG				SCI_ADDR(REGS_PMU_APB_BASE, 0x0134)/*26M_SEL_CFG*/
+#define REG_PMU_APB_MEM_PD_CFG0				SCI_ADDR(REGS_PMU_APB_BASE, 0x0138)/*MEM_PD_CFG0*/
+#define REG_PMU_APB_MEM_PD_CFG1				SCI_ADDR(REGS_PMU_APB_BASE, 0x013C)/*MEM_PD_CFG1*/
+#define REG_PMU_APB_PD_DDR_PUBL_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0140)/*PD_DDR_PUBL_CFG*/
+#define REG_PMU_APB_PD_DDR_PHY_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0144)/*PD_DDR_PHY_CFG*/
+#define REG_PMU_APB_BISR_CFG2				SCI_ADDR(REGS_PMU_APB_BASE, 0x0148)/*BISR_CFG2*/
+#define REG_PMU_APB_DEBUG_PD0				SCI_ADDR(REGS_PMU_APB_BASE, 0x014C)/*DEBUG_PD0*/
+#define REG_PMU_APB_DEBUG_PD1				SCI_ADDR(REGS_PMU_APB_BASE, 0x0150)/*DEBUG_PD1*/
+#define REG_PMU_APB_DEBUG_PD2				SCI_ADDR(REGS_PMU_APB_BASE, 0x0154)/*DEBUG_PD2*/
+#define REG_PMU_APB_DEBUG_PD3				SCI_ADDR(REGS_PMU_APB_BASE, 0x0158)/*DEBUG_PD3*/
+#define REG_PMU_APB_INT_DISABLE				SCI_ADDR(REGS_PMU_APB_BASE, 0x015C)/*INT_DIABLE*/
+#define REG_PMU_APB_PMU_DEBUG_CFG			SCI_ADDR(REGS_PMU_APB_BASE, 0x0160)/*PMU_DEBUG_CFG*/
+
+
+
+/* bits definitions for register REG_PMU_APB_PD_CA7_TOP_CFG */
+#define BIT_PD_CA7_TOP_DBG_SHUTDOWN_EN				( BIT(28) )
+#define BIT_PD_CA7_TOP_FORCE_SHUTDOWN				( BIT(25) )
+#define BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN				( BIT(24) )
+#define BITS_PD_CA7_TOP_PWR_ON_DLY(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(_X_)			( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CA7_TOP_ISO_ON_DLY(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_CA7_C0_CFG */
+#define BIT_PD_CA7_C0_DBG_SHUTDOWN_EN				( BIT(28) )
+#define BIT_PD_CA7_C0_FORCE_SHUTDOWN				( BIT(25) )
+#define BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN				( BIT(24) )
+#define BITS_PD_CA7_C0_PWR_ON_DLY(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(_X_)			( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CA7_C0_ISO_ON_DLY(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_CA7_C1_CFG */
+#define BIT_PD_CA7_C1_DBG_SHUTDOWN_EN				( BIT(28) )
+#define BIT_PD_CA7_C1_FORCE_SHUTDOWN				( BIT(25) )
+#define BIT_PD_CA7_C1_AUTO_SHUTDOWN_EN				( BIT(24) )
+#define BITS_PD_CA7_C1_PWR_ON_DLY(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(_X_)			( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CA7_C1_ISO_ON_DLY(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_CA7_C2_CFG */
+#define BIT_PD_CA7_C2_DBG_SHUTDOWN_EN				( BIT(28) )
+#define BIT_PD_CA7_C2_FORCE_SHUTDOWN				( BIT(25) )
+#define BIT_PD_CA7_C2_AUTO_SHUTDOWN_EN				( BIT(24) )
+#define BITS_PD_CA7_C2_PWR_ON_DLY(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(_X_)			( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CA7_C2_ISO_ON_DLY(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_CA7_C3_CFG */
+#define BIT_PD_CA7_C3_DBG_SHUTDOWN_EN				( BIT(28) )
+#define BIT_PD_CA7_C3_FORCE_SHUTDOWN				( BIT(25) )
+#define BIT_PD_CA7_C3_AUTO_SHUTDOWN_EN				( BIT(24) )
+#define BITS_PD_CA7_C3_PWR_ON_DLY(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(_X_)			( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CA7_C3_ISO_ON_DLY(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_AP_DISP_CFG */
+
+/* bits definitions for register REG_PMU_APB_PD_AP_SYS_CFG */
+#define BIT_PD_AP_SYS_FORCE_SHUTDOWN				( BIT(25) )
+#define BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN				( BIT(24) )
+#define BITS_PD_AP_SYS_PWR_ON_DLY(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(_X_)			( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_AP_SYS_ISO_ON_DLY(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_MM_TOP_CFG */
+#define BIT_PD_MM_TOP_FORCE_SHUTDOWN				( BIT(25) )
+#define BIT_PD_MM_TOP_AUTO_SHUTDOWN_EN				( BIT(24) )
+#define BITS_PD_MM_TOP_PWR_ON_DLY(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(_X_)			( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_MM_TOP_ISO_ON_DLY(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_GPU_TOP_CFG */
+#define BIT_PD_GPU_TOP_FORCE_SHUTDOWN				( BIT(25) )
+#define BIT_PD_GPU_TOP_AUTO_SHUTDOWN_EN				( BIT(24) )
+#define BITS_PD_GPU_TOP_PWR_ON_DLY(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(_X_)			( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_GPU_TOP_ISO_ON_DLY(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_0_CFG */
+#define BIT_PD_CP0_ARM9_0_FORCE_SHUTDOWN			( BIT(25) )
+#define BIT_PD_CP0_ARM9_0_AUTO_SHUTDOWN_EN			( BIT(24) )
+#define BITS_PD_CP0_ARM9_0_PWR_ON_DLY(_X_)			( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CP0_ARM9_0_PWR_ON_SEQ_DLY(_X_)			( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CP0_ARM9_0_ISO_ON_DLY(_X_)			( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_1_CFG */
+#define BIT_PD_CP0_ARM9_1_FORCE_SHUTDOWN			( BIT(25) )
+#define BIT_PD_CP0_ARM9_1_AUTO_SHUTDOWN_EN			( BIT(24) )
+#define BITS_PD_CP0_ARM9_1_PWR_ON_DLY(_X_)			( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CP0_ARM9_1_PWR_ON_SEQ_DLY(_X_)			( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CP0_ARM9_1_ISO_ON_DLY(_X_)			( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_2_CFG */
+#define BIT_PD_CP0_ARM9_2_FORCE_SHUTDOWN			( BIT(25) )
+#define BIT_PD_CP0_ARM9_2_AUTO_SHUTDOWN_EN			( BIT(24) )
+#define BITS_PD_CP0_ARM9_2_PWR_ON_DLY(_X_)			( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CP0_ARM9_2_PWR_ON_SEQ_DLY(_X_)			( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CP0_ARM9_2_ISO_ON_DLY(_X_)			( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_CP0_HU3GE_CFG */
+#define BIT_PD_CP0_HU3GE_FORCE_SHUTDOWN				( BIT(25) )
+#define BIT_PD_CP0_HU3GE_AUTO_SHUTDOWN_EN			( BIT(24) )
+#define BITS_PD_CP0_HU3GE_PWR_ON_DLY(_X_)			( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CP0_HU3GE_PWR_ON_SEQ_DLY(_X_)			( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CP0_HU3GE_ISO_ON_DLY(_X_)			( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_CP0_GSM_CFG */
+#define BIT_PD_CP0_GSM_FORCE_SHUTDOWN				( BIT(25) )
+#define BIT_PD_CP0_GSM_AUTO_SHUTDOWN_EN				( BIT(24) )
+#define BITS_PD_CP0_GSM_PWR_ON_DLY(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CP0_GSM_PWR_ON_SEQ_DLY(_X_)			( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CP0_GSM_ISO_ON_DLY(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_CP0_TD_CFG */
+#define BIT_PD_CP0_TD_FORCE_SHUTDOWN				( BIT(25) )
+#define BIT_PD_CP0_TD_AUTO_SHUTDOWN_EN				( BIT(24) )
+#define BITS_PD_CP0_TD_PWR_ON_DLY(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CP0_TD_PWR_ON_SEQ_DLY(_X_)			( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CP0_TD_ISO_ON_DLY(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_CP0_CEVA_CFG */
+#define BIT_PD_CP0_CEVA_FORCE_SHUTDOWN				( BIT(25) )
+#define BIT_PD_CP0_CEVA_AUTO_SHUTDOWN_EN			( BIT(24) )
+#define BITS_PD_CP0_CEVA_PWR_ON_DLY(_X_)			( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CP0_CEVA_PWR_ON_SEQ_DLY(_X_)			( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CP0_CEVA_ISO_ON_DLY(_X_)			( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_CP0_HARQ_CFG */
+#define BIT_PD_CP0_HARQ_FORCE_SHUTDOWN				( BIT(25) )
+#define BIT_PD_CP0_HARQ_AUTO_SHUTDOWN_EN			( BIT(24) )
+#define BITS_PD_CP0_HARQ_PWR_ON_DLY(_X_)			( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CP0_HARQ_PWR_ON_SEQ_DLY(_X_)			( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CP0_HARQ_ISO_ON_DLY(_X_)			( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_CP0_SYS_CFG */
+#define BIT_CP0_FORCE_DEEP_SLEEP				( BIT(28) )
+#define BIT_PD_CP0_SYS_FORCE_SHUTDOWN				( BIT(25) )
+#define BITS_PD_CP0_SYS_PWR_ON_DLY(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CP0_SYS_PWR_ON_SEQ_DLY(_X_)			( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CP0_SYS_ISO_ON_DLY(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_CP1_ARM9_CFG */
+#define BIT_PD_CP1_ARM9_FORCE_SHUTDOWN				( BIT(25) )
+#define BIT_PD_CP1_ARM9_AUTO_SHUTDOWN_EN			( BIT(24) )
+#define BITS_PD_CP1_ARM9_PWR_ON_DLY(_X_)			( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CP1_ARM9_PWR_ON_SEQ_DLY(_X_)			( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CP1_ARM9_ISO_ON_DLY(_X_)			( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_CP1_GSM_CFG */
+#define BIT_PD_CP1_GSM_FORCE_SHUTDOWN				( BIT(25) )
+#define BIT_PD_CP1_GSM_AUTO_SHUTDOWN_EN				( BIT(24) )
+#define BITS_PD_CP1_GSM_PWR_ON_DLY(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CP1_GSM_PWR_ON_SEQ_DLY(_X_)			( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CP1_GSM_ISO_ON_DLY(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_CP1_TD_CFG */
+#define BIT_PD_CP1_TD_FORCE_SHUTDOWN				( BIT(25) )
+#define BIT_PD_CP1_TD_AUTO_SHUTDOWN_EN				( BIT(24) )
+#define BITS_PD_CP1_TD_PWR_ON_DLY(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CP1_TD_PWR_ON_SEQ_DLY(_X_)			( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CP1_TD_ISO_ON_DLY(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_CP1_L1RAM_CFG */
+#define BIT_PD_CP1_L1RAM_FORCE_SHUTDOWN				( BIT(25) )
+#define BIT_PD_CP1_L1RAM_AUTO_SHUTDOWN_EN			( BIT(24) )
+#define BITS_PD_CP1_L1RAM_PWR_ON_DLY(_X_)			( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CP1_L1RAM_PWR_ON_SEQ_DLY(_X_)			( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CP1_L1RAM_ISO_ON_DLY(_X_)			( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_CP1_SYS_CFG */
+#define BIT_CP1_FORCE_DEEP_SLEEP				( BIT(28) )
+#define BIT_PD_CP1_SYS_FORCE_SHUTDOWN				( BIT(25) )
+#define BITS_PD_CP1_SYS_PWR_ON_DLY(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CP1_SYS_PWR_ON_SEQ_DLY(_X_)			( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CP1_SYS_ISO_ON_DLY(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_CP2_ARM9_CFG */
+#define BIT_PD_CP2_ARM9_FORCE_SHUTDOWN				( BIT(25) )
+#define BIT_PD_CP2_ARM9_AUTO_SHUTDOWN_EN			( BIT(24) )
+#define BITS_PD_CP2_ARM9_PWR_ON_DLY(_X_)			( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CP2_ARM9_PWR_ON_SEQ_DLY(_X_)			( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CP2_ARM9_ISO_ON_DLY(_X_)			( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_CP2_WIFI_CFG */
+#define BIT_PD_CP2_WIFI_FORCE_SHUTDOWN				( BIT(25) )
+#define BIT_PD_CP2_WIFI_AUTO_SHUTDOWN_EN			( BIT(24) )
+#define BITS_PD_CP2_WIFI_PWR_ON_DLY(_X_)			( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CP2_WIFI_PWR_ON_SEQ_DLY(_X_)			( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CP2_WIFI_ISO_ON_DLY(_X_)			( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_AP_WAKEUP_POR_CFG */
+#define BIT_AP_WAKEUP_POR_N					( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_PD_CP2_SYS_CFG */
+#define BIT_CP2_FORCE_DEEP_SLEEP				( BIT(28) )
+#define BIT_PD_CP2_SYS_FORCE_SHUTDOWN				( BIT(25) )
+#define BITS_PD_CP2_SYS_PWR_ON_DLY(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CP2_SYS_PWR_ON_SEQ_DLY(_X_)			( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CP2_SYS_ISO_ON_DLY(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_PUB_SYS_CFG */
+#define BIT_PD_PUB_SYS_FORCE_SHUTDOWN				( BIT(25) )
+#define BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN				( BIT(24) )
+#define BITS_PD_PUB_SYS_PWR_ON_DLY(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(_X_)			( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_PUB_SYS_ISO_ON_DLY(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_XTL_WAIT_CNT */
+#define BITS_XTL1_WAIT_CNT(_X_)					( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_XTL0_WAIT_CNT(_X_)					( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_XTLBUF_WAIT_CNT */
+#define BITS_XTLBUF1_WAIT_CNT(_X_)				( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_XTLBUF0_WAIT_CNT(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PLL_WAIT_CNT1 */
+#define BITS_WPLL_WAIT_CNT(_X_)					( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_TDPLL_WAIT_CNT(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DPLL_WAIT_CNT(_X_)					( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_MPLL_WAIT_CNT(_X_)					( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PLL_WAIT_CNT2 */
+#define BITS_WIFIPLL2_WAIT_CNT(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_WIFIPLL1_WAIT_CNT(_X_)				( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_CPLL_WAIT_CNT(_X_)					( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_XTL0_REL_CFG */
+#define BIT_XTL0_CP2_SEL					( BIT(3) )
+#define BIT_XTL0_CP1_SEL					( BIT(2) )
+#define BIT_XTL0_CP0_SEL					( BIT(1) )
+#define BIT_XTL0_AP_SEL						( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_XTL1_REL_CFG */
+#define BIT_XTL1_CP2_SEL					( BIT(3) )
+#define BIT_XTL1_CP1_SEL					( BIT(2) )
+#define BIT_XTL1_CP0_SEL					( BIT(1) )
+#define BIT_XTL1_AP_SEL						( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_XTL2_REL_CFG */
+#define BIT_XTL2_CP2_SEL					( BIT(3) )
+#define BIT_XTL2_CP1_SEL					( BIT(2) )
+#define BIT_XTL2_CP0_SEL					( BIT(1) )
+#define BIT_XTL2_AP_SEL						( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_XTLBUF0_REL_CFG */
+#define BIT_XTLBUF0_CP2_SEL					( BIT(3) )
+#define BIT_XTLBUF0_CP1_SEL					( BIT(2) )
+#define BIT_XTLBUF0_CP0_SEL					( BIT(1) )
+#define BIT_XTLBUF0_AP_SEL					( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_XTLBUF1_REL_CFG */
+#define BIT_XTLBUF1_CP2_SEL					( BIT(3) )
+#define BIT_XTLBUF1_CP1_SEL					( BIT(2) )
+#define BIT_XTLBUF1_CP0_SEL					( BIT(1) )
+#define BIT_XTLBUF1_AP_SEL					( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_MPLL_REL_CFG */
+#define BIT_MPLL_REF_SEL					( BIT(4) )
+#define BIT_MPLL_CP2_SEL					( BIT(3) )
+#define BIT_MPLL_CP1_SEL					( BIT(2) )
+#define BIT_MPLL_CP0_SEL					( BIT(1) )
+#define BIT_MPLL_AP_SEL						( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_DPLL_REL_CFG */
+#define BIT_DPLL_REF_SEL					( BIT(4) )
+#define BIT_DPLL_CP2_SEL					( BIT(3) )
+#define BIT_DPLL_CP1_SEL					( BIT(2) )
+#define BIT_DPLL_CP0_SEL					( BIT(1) )
+#define BIT_DPLL_AP_SEL						( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_TDPLL_REL_CFG */
+#define BIT_TDPLL_REF_SEL					( BIT(4) )
+#define BIT_TDPLL_CP2_SEL					( BIT(3) )
+#define BIT_TDPLL_CP1_SEL					( BIT(2) )
+#define BIT_TDPLL_CP0_SEL					( BIT(1) )
+#define BIT_TDPLL_AP_SEL					( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_WPLL_REL_CFG */
+#define BIT_WPLL_REF_SEL					( BIT(4) )
+#define BIT_WPLL_CP2_SEL					( BIT(3) )
+#define BIT_WPLL_CP1_SEL					( BIT(2) )
+#define BIT_WPLL_CP0_SEL					( BIT(1) )
+#define BIT_WPLL_AP_SEL						( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_CPLL_REL_CFG */
+#define BIT_CPLL_REF_SEL					( BIT(4) )
+#define BIT_CPLL_CP2_SEL					( BIT(3) )
+#define BIT_CPLL_CP1_SEL					( BIT(2) )
+#define BIT_CPLL_CP0_SEL					( BIT(1) )
+#define BIT_CPLL_AP_SEL						( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_WIFIPLL1_REL_CFG */
+#define BIT_WIFIPLL1_REF_SEL					( BIT(4) )
+#define BIT_WIFIPLL1_CP2_SEL					( BIT(3) )
+#define BIT_WIFIPLL1_CP1_SEL					( BIT(2) )
+#define BIT_WIFIPLL1_CP0_SEL					( BIT(1) )
+#define BIT_WIFIPLL1_AP_SEL					( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_WIFIPLL2_REL_CFG */
+#define BIT_WIFIPLL2_REF_SEL					( BIT(4) )
+#define BIT_WIFIPLL2_CP2_SEL					( BIT(3) )
+#define BIT_WIFIPLL2_CP1_SEL					( BIT(2) )
+#define BIT_WIFIPLL2_CP0_SEL					( BIT(1) )
+#define BIT_WIFIPLL2_AP_SEL					( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_CP_SOFT_RST */
+#define BIT_PUB_SOFT_RST					( BIT(6) )
+#define BIT_AP_SOFT_RST						( BIT(5) )
+#define BIT_GPU_SOFT_RST					( BIT(4) )
+#define BIT_MM_SOFT_RST						( BIT(3) )
+#define BIT_CP2_SOFT_RST					( BIT(2) )
+#define BIT_CP1_SOFT_RST					( BIT(1) )
+#define BIT_CP0_SOFT_RST					( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_CP_SLP_STATUS_DBG0 */
+#define BITS_CP1_DEEP_SLP_DBG(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_CP0_DEEP_SLP_DBG(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_PMU_APB_CP_SLP_STATUS_DBG1 */
+#define BITS_CP2_DEEP_SLP_DBG(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+
+/* bits definitions for register REG_PMU_APB_PWR_STATUS0_DBG */
+#define BITS_PD_MM_TOP_STATE(_X_)				( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_PD_GPU_TOP_STATE(_X_)				( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_PD_CA7_C3_STATE(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_PD_CA7_C2_STATE(_X_)				( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CA7_C1_STATE(_X_)				( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_PD_CA7_C0_STATE(_X_)				( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_PD_CA7_TOP_STATE(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PMU_APB_PWR_STATUS1_DBG */
+#define BITS_PD_CP0_SYS_STATE(_X_)				( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_PD_CP0_GSM_STATE(_X_)				( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CP0_HU3GE_STATE(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_PD_CP0_ARM9_2_STATE(_X_)				( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CP0_ARM9_1_STATE(_X_)				( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_PD_CP0_ARM9_0_STATE(_X_)				( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_PD_AP_SYS_STATE(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PMU_APB_PWR_STATUS2_DBG */
+#define BITS_PD_CP2_WIFI_STATE(_X_)				( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_PD_CP2_ARM9_STATE(_X_)				( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CP1_SYS_STATE(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_PD_CP1_L1RAM_STATE(_X_)				( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_CP1_TD_STATE(_X_)				( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_PD_CP1_GSM_STATE(_X_)				( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_PD_CP1_ARM9_STATE(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PMU_APB_PWR_STATUS3_DBG */
+#define BITS_PD_CP0_HARQ_STATE(_X_)				( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_PD_CP0_CEVA_STATE(_X_)				( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_CP0_TD_STATE(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_PD_DDR_PHY_STATE(_X_)				( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_DDR_PUBL_STATE(_X_)				( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_PD_PUB_SYS_STATE(_X_)				( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_PD_CP2_SYS_STATE(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PMU_APB_SLEEP_CTRL */
+#define BIT_CP0_FORCE_SLEEP					( BIT(12) )
+#define BIT_CP2_SLEEP_XTL_ON					( BIT(11) )
+#define BIT_CP1_SLEEP_XTL_ON					( BIT(10) )
+#define BIT_CP0_SLEEP_XTL_ON					( BIT(9) )
+#define BIT_AP_SLEEP_XTL_ON					( BIT(8) )
+#define BIT_DISP_DEEP_SLEEP					( BIT(6) )
+#define BIT_GPU_DEEP_SLEEP					( BIT(5) )
+#define BIT_MM_DEEP_SLEEP					( BIT(4) )
+#define BIT_CP2_DEEP_SLEEP					( BIT(3) )
+#define BIT_CP1_DEEP_SLEEP					( BIT(2) )
+#define BIT_CP0_DEEP_SLEEP					( BIT(1) )
+#define BIT_AP_DEEP_SLEEP					( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_DDR_SLEEP_CTRL */
+#define BIT_DDR_PUBL_APB_SOFT_RST				( BIT(12) )
+#define BIT_DDR_UMCTL_APB_SOFT_RST				( BIT(11) )
+#define BIT_DDR_PUBL_SOFT_RST					( BIT(10) )
+#define BIT_DDR_UMCTL_SOFT_RST					( BIT(9) )
+#define BIT_DDR_PHY_SOFT_RST					( BIT(8) )
+#define BIT_DDR_PHY_AUTO_GATE_EN				( BIT(6) )
+#define BIT_DDR_PUBL_AUTO_GATE_EN				( BIT(5) )
+#define BIT_DDR_UMCTL_AUTO_GATE_EN				( BIT(4) )
+#define BIT_DDR_PHY_EB						( BIT(2) )
+#define BIT_DDR_UMCTL_EB					( BIT(1) )
+#define BIT_DDR_PUBL_EB						( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_SLEEP_STATUS */
+#define BITS_CP2_SLP_STATUS(_X_)				( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_CP1_SLP_STATUS(_X_)				( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_CP0_SLP_STATUS(_X_)				( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_AP_SLP_STATUS(_X_)					( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PMU_APB_PLL_DIV_AUTO_GATE_EN */
+#define BIT_WIFIPLL2_DIV_AUTO_GATE_EN				( BIT(6) )
+#define BIT_WIFIPLL1_DIV_AUTO_GATE_EN				( BIT(5) )
+#define BIT_WPLL_DIV_AUTO_GATE_EN				( BIT(4) )
+#define BIT_TDPLL_DIV_AUTO_GATE_EN				( BIT(3) )
+#define BIT_CPLL_DIV_AUTO_GATE_EN				( BIT(2) )
+#define BIT_DPLL_DIV_AUTO_GATE_EN				( BIT(1) )
+#define BIT_MPLL_DIV_AUTO_GATE_EN				( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_PLL_DIV_EN1 */
+#define BIT_WIFIPLL2_80M_EN					( BIT(31) )
+#define BIT_WIFIPLL2_160M_EN					( BIT(30) )
+#define BIT_WIFIPLL2_120M_EN					( BIT(29) )
+#define BIT_WIFIPLL1_20M_EN					( BIT(28) )
+#define BIT_WIFIPLL1_40M_EN					( BIT(27) )
+#define BIT_WIFIPLL1_80M_EN					( BIT(26) )
+#define BIT_WIFIPLL1_44M_EN					( BIT(25) )
+#define BIT_WPLL_76M8_EN					( BIT(24) )
+#define BIT_WPLL_51M2_EN					( BIT(23) )
+#define BIT_WPLL_102M4_EN					( BIT(22) )
+#define BIT_WPLL_307M2_EN					( BIT(21) )
+#define BIT_WPLL_460M8_EN					( BIT(20) )
+#define BIT_CPLL_52M_EN						( BIT(19) )
+#define BIT_CPLL_104M_EN					( BIT(18) )
+#define BIT_CPLL_208M_EN					( BIT(17) )
+#define BIT_CPLL_312M_EN					( BIT(16) )
+#define BIT_TDPLL_38M4_EN					( BIT(15) )
+#define BIT_TDPLL_76M8_EN					( BIT(14) )
+#define BIT_TDPLL_51M2_EN					( BIT(13) )
+#define BIT_TDPLL_153M6_EN					( BIT(12) )
+#define BIT_TDPLL_64M_EN					( BIT(11) )
+#define BIT_TDPLL_128M_EN					( BIT(10) )
+#define BIT_TDPLL_256M_EN					( BIT(9) )
+#define BIT_TDPLL_12M_EN					( BIT(8) )
+#define BIT_TDPLL_24M_EN					( BIT(7) )
+#define BIT_TDPLL_48M_EN					( BIT(6) )
+#define BIT_TDPLL_96M_EN					( BIT(5) )
+#define BIT_TDPLL_192M_EN					( BIT(4) )
+#define BIT_TDPLL_384M_EN					( BIT(3) )
+#define BIT_DPLL_44M_EN						( BIT(2) )
+#define BIT_MPLL_37M5_EN					( BIT(1) )
+#define BIT_MPLL_300M_EN					( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_PLL_DIV_EN2 */
+#define BIT_DPLL_533M_EN					( BIT(2) )
+#define BIT_WIFIPLL2_20M_EN					( BIT(1) )
+#define BIT_WIFIPLL2_40M_EN					( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_CA7_TOP_CFG */
+#define BIT_CA7_L2RSTDISABLE					( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_CA7_C0_CFG */
+#define BIT_CA7_VINITHI_C0					( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_CA7_C1_CFG */
+#define BIT_CA7_VINITHI_C1					( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_CA7_C2_CFG */
+#define BIT_CA7_VINITHI_C2					( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_CA7_C3_CFG */
+#define BIT_CA7_VINITHI_C3					( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_DDR_CHN_SLEEP_CTRL0 */
+#define BIT_DDR_CTRL_AXI_LP_EN					( BIT(31) )
+#define BIT_DDR_CTRL_CGM_SEL					( BIT(30) )
+#define BIT_DDR_CHN9_AXI_LP_EN					( BIT(25) )
+#define BIT_DDR_CHN8_AXI_LP_EN					( BIT(24) )
+#define BIT_DDR_CHN7_AXI_LP_EN					( BIT(23) )
+#define BIT_DDR_CHN6_AXI_LP_EN					( BIT(22) )
+#define BIT_DDR_CHN5_AXI_LP_EN					( BIT(21) )
+#define BIT_DDR_CHN4_AXI_LP_EN					( BIT(20) )
+#define BIT_DDR_CHN3_AXI_LP_EN					( BIT(19) )
+#define BIT_DDR_CHN2_AXI_LP_EN					( BIT(18) )
+#define BIT_DDR_CHN1_AXI_LP_EN					( BIT(17) )
+#define BIT_DDR_CHN0_AXI_LP_EN					( BIT(16) )
+#define BIT_DDR_CHN9_CGM_SEL					( BIT(9) )
+#define BIT_DDR_CHN8_CGM_SEL					( BIT(8) )
+#define BIT_DDR_CHN7_CGM_SEL					( BIT(7) )
+#define BIT_DDR_CHN6_CGM_SEL					( BIT(6) )
+#define BIT_DDR_CHN5_CGM_SEL					( BIT(5) )
+#define BIT_DDR_CHN4_CGM_SEL					( BIT(4) )
+#define BIT_DDR_CHN3_CGM_SEL					( BIT(3) )
+#define BIT_DDR_CHN2_CGM_SEL					( BIT(2) )
+#define BIT_DDR_CHN1_CGM_SEL					( BIT(1) )
+#define BIT_DDR_CHN0_CGM_SEL					( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_DDR_CHN_SLEEP_CTRL1 */
+#define BIT_DDR_CHN9_AXI_STOP_SEL				( BIT(9) )
+#define BIT_DDR_CHN8_AXI_STOP_SEL				( BIT(8) )
+#define BIT_DDR_CHN7_AXI_STOP_SEL				( BIT(7) )
+#define BIT_DDR_CHN6_AXI_STOP_SEL				( BIT(6) )
+#define BIT_DDR_CHN5_AXI_STOP_SEL				( BIT(5) )
+#define BIT_DDR_CHN4_AXI_STOP_SEL				( BIT(4) )
+#define BIT_DDR_CHN3_AXI_STOP_SEL				( BIT(3) )
+#define BIT_DDR_CHN2_AXI_STOP_SEL				( BIT(2) )
+#define BIT_DDR_CHN1_AXI_STOP_SEL				( BIT(1) )
+#define BIT_DDR_CHN0_AXI_STOP_SEL				( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_BISR_CFG */
+#define BIT_PD_CP0_CEVA_BISR_DONE				( BIT(31) )
+#define BIT_PD_CP0_TD_BISR_DONE					( BIT(30) )
+#define BIT_PD_CP1_TD_BISR_DONE					( BIT(29) )
+#define BIT_PD_CP1_SYS_BISR_DONE				( BIT(28) )
+#define BIT_PD_CP0_HU3GE_BISR_DONE				( BIT(27) )
+#define BIT_PD_CP0_SYS_BISR_DONE				( BIT(26) )
+#define BIT_PD_MM_TOP_BISR_DONE					( BIT(25) )
+#define BIT_PD_GPU_TOP_BISR_DONE				( BIT(24) )
+#define BIT_PD_CP0_CEVA_BISR_BUSY				( BIT(23) )
+#define BIT_PD_CP0_TD_BISR_BUSY					( BIT(22) )
+#define BIT_PD_CP1_TD_BISR_BUSY					( BIT(21) )
+#define BIT_PD_CP1_SYS_BISR_BUSY				( BIT(20) )
+#define BIT_PD_CP0_HU3GE_BISR_BUSY				( BIT(19) )
+#define BIT_PD_CP0_SYS_BISR_BUSY				( BIT(18) )
+#define BIT_PD_MM_TOP_BISR_BUSY					( BIT(17) )
+#define BIT_PD_GPU_TOP_BISR_BUSY				( BIT(16) )
+#define BIT_PD_CP0_CEVA_BISR_FORCE_EN				( BIT(15) )
+#define BIT_PD_CP0_TD_BISR_FORCE_EN				( BIT(14) )
+#define BIT_PD_CP1_TD_BISR_FORCE_EN				( BIT(13) )
+#define BIT_PD_CP1_SYS_BISR_FORCE_EN				( BIT(12) )
+#define BIT_PD_CP0_HU3GE_BISR_FORCE_EN				( BIT(11) )
+#define BIT_PD_CP0_SYS_BISR_FORCE_EN				( BIT(10) )
+#define BIT_PD_MM_TOP_BISR_FORCE_EN				( BIT(9) )
+#define BIT_PD_GPU_TOP_BISR_FORCE_EN				( BIT(8) )
+#define BIT_PD_CP1_TD_BISR_FORCE_BYP				( BIT(7) )
+#define BIT_PD_CP0_CEVA_BISR_FORCE_BYP				( BIT(6) )
+#define BIT_PD_CP0_TD_BISR_FORCE_BYP				( BIT(5) )
+#define BIT_PD_CP1_SYS_BISR_FORCE_BYP				( BIT(4) )
+#define BIT_PD_CP0_HU3GE_BISR_FORCE_BYP				( BIT(3) )
+#define BIT_PD_CP0_SYS_BISR_FORCE_BYP				( BIT(2) )
+#define BIT_PD_MM_TOP_BISR_FORCE_BYP				( BIT(1) )
+#define BIT_PD_GPU_TOP_BISR_FORCE_BYP				( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_CGM_AP_AUTO_GATE_EN */
+#define BIT_CGM_307M2_AP_AUTO_GATE_EN				( BIT(21) )
+#define BIT_CGM_208M_AP_AUTO_GATE_EN				( BIT(20) )
+#define BIT_CGM_12M_AP_AUTO_GATE_EN				( BIT(19) )
+#define BIT_CGM_24M_AP_AUTO_GATE_EN				( BIT(18) )
+#define BIT_CGM_48M_AP_AUTO_GATE_EN				( BIT(17) )
+#define BIT_CGM_51M2_AP_AUTO_GATE_EN				( BIT(16) )
+#define BIT_CGM_64M_AP_AUTO_GATE_EN				( BIT(15) )
+#define BIT_CGM_76M8_AP_AUTO_GATE_EN				( BIT(14) )
+#define BIT_CGM_96M_AP_AUTO_GATE_EN				( BIT(13) )
+#define BIT_CGM_128M_AP_AUTO_GATE_EN				( BIT(12) )
+#define BIT_CGM_153M6_AP_AUTO_GATE_EN				( BIT(11) )
+#define BIT_CGM_192M_AP_AUTO_GATE_EN				( BIT(10) )
+#define BIT_CGM_256M_AP_AUTO_GATE_EN				( BIT(9) )
+#define BIT_CGM_384M_AP_AUTO_GATE_EN				( BIT(8) )
+#define BIT_CGM_312M_AP_AUTO_GATE_EN				( BIT(7) )
+#define BIT_CGM_MPLL_AP_AUTO_GATE_EN				( BIT(6) )
+#define BIT_CGM_WPLL_AP_AUTO_GATE_EN				( BIT(5) )
+#define BIT_CGM_WIFIPLL1_AP_AUTO_GATE_EN			( BIT(4) )
+#define BIT_CGM_TDPLL_AP_AUTO_GATE_EN				( BIT(3) )
+#define BIT_CGM_CPLL_AP_AUTO_GATE_EN				( BIT(2) )
+#define BIT_CGM_DPLL_AP_AUTO_GATE_EN				( BIT(1) )
+#define BIT_CGM_26M_AP_AUTO_GATE_EN				( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_CGM_GPU_MM_AUTO_GATE_EN */
+#define BIT_CGM_312M_MM_AUTO_GATE_EN				( BIT(27) )
+#define BIT_CGM_12M_MM_AUTO_GATE_EN				( BIT(26) )
+#define BIT_CGM_24M_MM_AUTO_GATE_EN				( BIT(25) )
+#define BIT_CGM_48M_MM_AUTO_GATE_EN				( BIT(24) )
+#define BIT_CGM_64M_MM_AUTO_GATE_EN				( BIT(23) )
+#define BIT_CGM_76M8_MM_AUTO_GATE_EN				( BIT(22) )
+#define BIT_CGM_96M_MM_AUTO_GATE_EN				( BIT(21) )
+#define BIT_CGM_128M_MM_AUTO_GATE_EN				( BIT(20) )
+#define BIT_CGM_153M6_MM_AUTO_GATE_EN				( BIT(19) )
+#define BIT_CGM_192M_MM_AUTO_GATE_EN				( BIT(18) )
+#define BIT_CGM_256M_MM_AUTO_GATE_EN				( BIT(17) )
+#define BIT_CGM_26M_MM_AUTO_GATE_EN				( BIT(16) )
+#define BIT_CGM_153_6M_GPU_AUTO_GATE_EN				( BIT(6) )
+#define BIT_CGM_384M_GPU_AUTO_GATE_EN				( BIT(5) )
+#define BIT_CGM_460_8M_GPU_AUTO_GATE_EN				( BIT(4) )
+#define BIT_CGM_256M_GPU_AUTO_GATE_EN				( BIT(3) )
+#define BIT_CGM_208M_GPU_AUTO_GATE_EN				( BIT(2) )
+#define BIT_CGM_312M_GPU_AUTO_GATE_EN				( BIT(1) )
+#define BIT_CGM_512M_GPU_AUTO_GATE_EN				( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_CGM_CP0_AUTO_GATE_EN */
+#define BIT_CGM_312M_CP0_AUTO_GATE_EN				( BIT(16) )
+#define BIT_CGM_208M_CP0_AUTO_GATE_EN				( BIT(15) )
+#define BIT_CGM_256M_CP0_AUTO_GATE_EN				( BIT(14) )
+#define BIT_CGM_460M8_CP0W_AUTO_GATE_EN				( BIT(13) )
+#define BIT_CGM_307M2_CP0W_AUTO_GATE_EN				( BIT(12) )
+#define BIT_CGM_51M2_CP0W_AUTO_GATE_EN				( BIT(11) )
+#define BIT_CGM_76M8_CP0W_AUTO_GATE_EN				( BIT(10) )
+#define BIT_CGM_102M4_CP0W_AUTO_GATE_EN				( BIT(9) )
+#define BIT_CGM_192M_CP0_AUTO_GATE_EN				( BIT(8) )
+#define BIT_CGM_51M2_CP0_AUTO_GATE_EN				( BIT(7) )
+#define BIT_CGM_76M8_CP0_AUTO_GATE_EN				( BIT(6) )
+#define BIT_CGM_153M6_CP0_AUTO_GATE_EN				( BIT(5) )
+#define BIT_CGM_48M_CP0_AUTO_GATE_EN				( BIT(4) )
+#define BIT_CGM_64M_CP0_AUTO_GATE_EN				( BIT(3) )
+#define BIT_CGM_96M_CP0_AUTO_GATE_EN				( BIT(2) )
+#define BIT_CGM_128M_CP0_AUTO_GATE_EN				( BIT(1) )
+#define BIT_CGM_26M_CP0_AUTO_GATE_EN				( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_CGM_CP1_AUTO_GATE_EN */
+#define BIT_CGM_312M_CP1_AUTO_GATE_EN				( BIT(10) )
+#define BIT_CGM_256M_CP1_AUTO_GATE_EN				( BIT(9) )
+#define BIT_CGM_192M_CP1_AUTO_GATE_EN				( BIT(8) )
+#define BIT_CGM_51M2_CP1_AUTO_GATE_EN				( BIT(7) )
+#define BIT_CGM_76M8_CP1_AUTO_GATE_EN				( BIT(6) )
+#define BIT_CGM_153M6_CP1_AUTO_GATE_EN				( BIT(5) )
+#define BIT_CGM_48M_CP1_AUTO_GATE_EN				( BIT(4) )
+#define BIT_CGM_96M_CP1_AUTO_GATE_EN				( BIT(3) )
+#define BIT_CGM_64M_CP1_AUTO_GATE_EN				( BIT(2) )
+#define BIT_CGM_128M_CP1_AUTO_GATE_EN				( BIT(1) )
+#define BIT_CGM_26M_CP1_AUTO_GATE_EN				( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_CGM_CP2_AUTO_GATE_EN */
+#define BIT_CGM_153M6_CP2_AUTO_GATE_EN				( BIT(12) )
+#define BIT_CGM_20M_CP2WF2_AUTO_GATE_EN				( BIT(11) )
+#define BIT_CGM_80M_CP2WF2_AUTO_GATE_EN				( BIT(10) )
+#define BIT_CGM_120M_CP2WF2_AUTO_GATE_EN			( BIT(9) )
+#define BIT_CGM_160M_CP2WF2_AUTO_GATE_EN			( BIT(8) )
+#define BIT_CGM_20M_CP2WF1_AUTO_GATE_EN				( BIT(7) )
+#define BIT_CGM_44M_CP2WF1_AUTO_GATE_EN				( BIT(6) )
+#define BIT_CGM_80M_CP2WF1_AUTO_GATE_EN				( BIT(5) )
+#define BIT_CGM_256M_CP2_AUTO_GATE_EN				( BIT(4) )
+#define BIT_CGM_104M_CP2_AUTO_GATE_EN				( BIT(3) )
+#define BIT_CGM_208M_CP2_AUTO_GATE_EN				( BIT(2) )
+#define BIT_CGM_312M_CP2_AUTO_GATE_EN				( BIT(1) )
+#define BIT_CGM_26M_CP2_AUTO_GATE_EN				( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_CGM_AP_EN */
+#define BIT_CGM_307M2_AP_EN					( BIT(21) )
+#define BIT_CGM_208M_AP_EN					( BIT(20) )
+#define BIT_CGM_12M_AP_EN					( BIT(19) )
+#define BIT_CGM_24M_AP_EN					( BIT(18) )
+#define BIT_CGM_48M_AP_EN					( BIT(17) )
+#define BIT_CGM_51M2_AP_EN					( BIT(16) )
+#define BIT_CGM_64M_AP_EN					( BIT(15) )
+#define BIT_CGM_76M8_AP_EN					( BIT(14) )
+#define BIT_CGM_96M_AP_EN					( BIT(13) )
+#define BIT_CGM_128M_AP_EN					( BIT(12) )
+#define BIT_CGM_153M6_AP_EN					( BIT(11) )
+#define BIT_CGM_192M_AP_EN					( BIT(10) )
+#define BIT_CGM_256M_AP_EN					( BIT(9) )
+#define BIT_CGM_384M_AP_EN					( BIT(8) )
+#define BIT_CGM_312M_AP_EN					( BIT(7) )
+#define BIT_CGM_MPLL_AP_EN					( BIT(6) )
+#define BIT_CGM_WPLL_AP_EN					( BIT(5) )
+#define BIT_CGM_WIFIPLL1_AP_EN					( BIT(4) )
+#define BIT_CGM_TDPLL_AP_EN					( BIT(3) )
+#define BIT_CGM_CPLL_AP_EN					( BIT(2) )
+#define BIT_CGM_DPLL_AP_EN					( BIT(1) )
+#define BIT_CGM_26M_AP_EN					( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_CGM_GPU_MM_EN */
+#define BIT_CGM_312M_MM_EN					( BIT(27) )
+#define BIT_CGM_12M_MM_EN					( BIT(26) )
+#define BIT_CGM_24M_MM_EN					( BIT(25) )
+#define BIT_CGM_48M_MM_EN					( BIT(24) )
+#define BIT_CGM_64M_MM_EN					( BIT(23) )
+#define BIT_CGM_76M8_MM_EN					( BIT(22) )
+#define BIT_CGM_96M_MM_EN					( BIT(21) )
+#define BIT_CGM_128M_MM_EN					( BIT(20) )
+#define BIT_CGM_153M6_MM_EN					( BIT(19) )
+#define BIT_CGM_192M_MM_EN					( BIT(18) )
+#define BIT_CGM_256M_MM_EN					( BIT(17) )
+#define BIT_CGM_26M_MM_EN					( BIT(16) )
+#define BIT_CGM_153_6M_GPU_EN					( BIT(6) )
+#define BIT_CGM_384M_GPU_EN					( BIT(5) )
+#define BIT_CGM_460_8M_GPU_EN					( BIT(4) )
+#define BIT_CGM_256M_GPU_EN					( BIT(3) )
+#define BIT_CGM_208M_GPU_EN					( BIT(2) )
+#define BIT_CGM_312M_GPU_EN					( BIT(1) )
+#define BIT_CGM_512M_GPU_EN					( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_CGM_CP0_EN */
+#define BIT_CGM_312M_CP0_EN					( BIT(16) )
+#define BIT_CGM_208M_CP0_EN					( BIT(15) )
+#define BIT_CGM_256M_CP0_EN					( BIT(14) )
+#define BIT_CGM_460M8_CP0W_EN					( BIT(13) )
+#define BIT_CGM_307M2_CP0W_EN					( BIT(12) )
+#define BIT_CGM_51M2_CP0W_EN					( BIT(11) )
+#define BIT_CGM_76M8_CP0W_EN					( BIT(10) )
+#define BIT_CGM_102M4_CP0W_EN					( BIT(9) )
+#define BIT_CGM_192M_CP0_EN					( BIT(8) )
+#define BIT_CGM_51M2_CP0_EN					( BIT(7) )
+#define BIT_CGM_76M8_CP0_EN					( BIT(6) )
+#define BIT_CGM_153M6_CP0_EN					( BIT(5) )
+#define BIT_CGM_48M_CP0_EN					( BIT(4) )
+#define BIT_CGM_64M_CP0_EN					( BIT(3) )
+#define BIT_CGM_96M_CP0_EN					( BIT(2) )
+#define BIT_CGM_128M_CP0_EN					( BIT(1) )
+#define BIT_CGM_26M_CP0_EN					( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_CGM_CP1_EN */
+#define BIT_CGM_312M_CP1_EN					( BIT(10) )
+#define BIT_CGM_256M_CP1_EN					( BIT(9) )
+#define BIT_CGM_192M_CP1_EN					( BIT(8) )
+#define BIT_CGM_51M2_CP1_EN					( BIT(7) )
+#define BIT_CGM_76M8_CP1_EN					( BIT(6) )
+#define BIT_CGM_153M6_CP1_EN					( BIT(5) )
+#define BIT_CGM_48M_CP1_EN					( BIT(4) )
+#define BIT_CGM_96M_CP1_EN					( BIT(3) )
+#define BIT_CGM_64M_CP1_EN					( BIT(2) )
+#define BIT_CGM_128M_CP1_EN					( BIT(1) )
+#define BIT_CGM_26M_CP1_EN					( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_CGM_CP2_EN */
+#define BIT_CGM_153M6_CP2_EN					( BIT(12) )
+#define BIT_CGM_20M_CP2WF2_EN					( BIT(11) )
+#define BIT_CGM_80M_CP2WF2_EN					( BIT(10) )
+#define BIT_CGM_120M_CP2WF2_EN					( BIT(9) )
+#define BIT_CGM_160M_CP2WF2_EN					( BIT(8) )
+#define BIT_CGM_20M_CP2WF1_EN					( BIT(7) )
+#define BIT_CGM_44M_CP2WF1_EN					( BIT(6) )
+#define BIT_CGM_80M_CP2WF1_EN					( BIT(5) )
+#define BIT_CGM_256M_CP2_EN					( BIT(4) )
+#define BIT_CGM_104M_CP2_EN					( BIT(3) )
+#define BIT_CGM_208M_CP2_EN					( BIT(2) )
+#define BIT_CGM_312M_CP2_EN					( BIT(1) )
+#define BIT_CGM_26M_CP2_EN					( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_DDR_OP_MODE_CFG */
+#define BIT_DDR_PHY_RET_EN					( BIT(28) )
+#define BIT_DDR_PUBL_RET_EN					( BIT(27) )
+#define BIT_DDR_PHY_ISO_RST_EN					( BIT(26) )
+#define BIT_DDR_UMCTL_RET_EN					( BIT(25) )
+#define BIT_DDR_PHY_AUTO_RET_EN					( BIT(24) )
+#define BITS_DDR_OPERATE_MODE_CNT_LMT(_X_)			( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DDR_OPERATE_MODE(_X_)				( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) )
+#define BITS_DDR_OPERATE_MODE_IDLE(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
+
+/* bits definitions for register REG_PMU_APB_DDR_PHY_RET_CFG */
+#define BIT_DDR_PHY_CKE_RET_EN					( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_26M_SEL_CFG */
+#define BIT_CLK26MHZ_REF_1_SEL					( BIT(10) )
+#define BIT_AON_MEM_PD_EN_CP2					( BIT(9) )
+#define BIT_AON_MEM_PD_EN_CP0					( BIT(8) )
+#define BIT_AON_MEM_PD_EN_AP					( BIT(7) )
+#define BIT_LPLL_REF_SEL					( BIT(6) )
+#define BIT_PUB_26M_SEL						( BIT(5) )
+#define BIT_AON_26M_SEL						( BIT(4) )
+#define BIT_CP2_26M_SEL						( BIT(3) )
+#define BIT_CP1_26M_SEL						( BIT(2) )
+#define BIT_CP0_26M_SEL						( BIT(1) )
+#define BIT_AP_26M_SEL						( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_MEM_PD_CFG0 */
+#define BITS_CP0_W_MEM_PD_CFG_HARQ(_X_)				( (_X_) << 24 & (BIT(24)|BIT(25)) )
+#define BITS_CP0_W_MEM_PD_CFG_UART1(_X_)			( (_X_) << 22 & (BIT(22)|BIT(23)) )
+#define BITS_CP0_W_MEM_PD_CFG_UART0(_X_)			( (_X_) << 20 & (BIT(20)|BIT(21)) )
+#define BITS_CP0_W_MEM_PD_CFG_IRAM(_X_)				( (_X_) << 18 & (BIT(18)|BIT(19)) )
+#define BITS_CP0_W_MEM_PD_CFG_PERIF(_X_)			( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_AON_MEM_PD_CFG_IRAM(_X_)				( (_X_) << 14 & (BIT(14)|BIT(15)) )
+#define BITS_AON_MEM_PD_CFG_IMC3(_X_)				( (_X_) << 12 & (BIT(12)|BIT(13)) )
+#define BITS_AON_MEM_PD_CFG_IMC2(_X_)				( (_X_) << 10 & (BIT(10)|BIT(11)) )
+#define BITS_AON_MEM_PD_CFG_IMC1(_X_)				( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_AON_MEM_PD_CFG_IMC0(_X_)				( (_X_) << 6 & (BIT(6)|BIT(7)) )
+#define BITS_AON_MEM_PD_CFG_VBC(_X_)				( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_AON_MEM_PD_CFG_AUD(_X_)				( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_AON_MEM_PD_CFG_FM(_X_)				( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_PMU_APB_MEM_PD_CFG1 */
+#define BITS_CP0_DSP_MEM_PD_CFG_DMA(_X_)			( (_X_) << 24 & (BIT(24)|BIT(25)) )
+#define BITS_CP0_DSP_MEM_PD_CFG_SHM(_X_)			( (_X_) << 22 & (BIT(22)|BIT(23)) )
+#define BITS_CP0_DSP_MEM_PD_CFG_RFT(_X_)			( (_X_) << 20 & (BIT(20)|BIT(21)) )
+#define BITS_CP0_DSP_MEM_PD_CFG_STC(_X_)			( (_X_) << 18 & (BIT(18)|BIT(19)) )
+#define BITS_CP0_ARM_MEM_PD_CFG_IIS3(_X_)			( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_CP0_ARM_MEM_PD_CFG_IIS2(_X_)			( (_X_) << 14 & (BIT(14)|BIT(15)) )
+#define BITS_CP0_ARM_MEM_PD_CFG_IIS1(_X_)			( (_X_) << 12 & (BIT(12)|BIT(13)) )
+#define BITS_CP0_ARM_MEM_PD_CFG_IIS0(_X_)			( (_X_) << 10 & (BIT(10)|BIT(11)) )
+#define BITS_CP0_ARM_MEM_PD_CFG_UART1(_X_)			( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_CP0_ARM_MEM_PD_CFG_UART0(_X_)			( (_X_) << 6 & (BIT(6)|BIT(7)) )
+#define BITS_CP0_ARM_MEM_PD_CFG_EPT(_X_)			( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_CP0_ARM_MEM_PD_CFG_LZMA(_X_)			( (_X_) << 2 & (BIT(2)|BIT(3)) )
+#define BITS_CP0_ARM_MEM_PD_CFG_DMA(_X_)			( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_PMU_APB_PD_DDR_PUBL_CFG */
+#define BIT_PD_DDR_PUBL_FORCE_SHUTDOWN				( BIT(25) )
+#define BIT_PD_DDR_PUBL_AUTO_SHUTDOWN_EN			( BIT(24) )
+#define BITS_PD_DDR_PUBL_PWR_ON_DLY(_X_)			( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_DDR_PUBL_PWR_ON_SEQ_DLY(_X_)			( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_DDR_PUBL_ISO_ON_DLY(_X_)			( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_PD_DDR_PHY_CFG */
+#define BIT_PD_DDR_PHY_FORCE_SHUTDOWN				( BIT(25) )
+#define BIT_PD_DDR_PHY_AUTO_SHUTDOWN_EN				( BIT(24) )
+#define BITS_PD_DDR_PHY_PWR_ON_DLY(_X_)				( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_PD_DDR_PHY_PWR_ON_SEQ_DLY(_X_)			( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_PD_DDR_PHY_ISO_ON_DLY(_X_)				( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PMU_APB_BISR_CFG2 */
+#define BIT_PD_CA7_TOP_BISR_DONE				( BIT(15) )
+#define BIT_PD_CA7_TOP_BISR_BUSY				( BIT(14) )
+#define BIT_PD_CA7_TOP_BISR_FORCE_EN				( BIT(13) )
+#define BIT_PD_CA7_TOP_BISR_FORCE_BYP				( BIT(12) )
+#define BIT_PD_CP0_HARQ_BISR_DONE				( BIT(11) )
+#define BIT_PD_CP0_HARQ_BISR_BUSY				( BIT(10) )
+#define BIT_PD_CP0_HARQ_BISR_FORCE_EN				( BIT(9) )
+#define BIT_PD_CP0_HARQ_BISR_FORCE_BYP				( BIT(8) )
+#define BIT_PD_CP2_WIFI_BISR_DONE				( BIT(7) )
+#define BIT_PD_AP_SYS_BISR_DONE					( BIT(6) )
+#define BIT_PD_CP2_WIFI_BISR_BUSY				( BIT(5) )
+#define BIT_PD_AP_SYS_BISR_BUSY					( BIT(4) )
+#define BIT_PD_CP2_WIFI_BISR_FORCE_EN				( BIT(3) )
+#define BIT_PD_AP_SYS_BISR_FORCE_EN				( BIT(2) )
+#define BIT_PD_CP2_WIFI_BISR_FORCE_BYP				( BIT(1) )
+#define BIT_PD_AP_SYS_BISR_FORCE_BYP				( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_DEBUG_PD0 */
+#define BIT_PD_DDR_PHY_SHUTDOWN_D_B				( BIT(27) )
+#define BIT_PD_DDR_PUBL_SHUTDOWN_D_B				( BIT(26) )
+#define BIT_PD_PUB_SYS_SHUTDOWN_D_B				( BIT(25) )
+#define BIT_PD_CP2_WIFI_SHUTDOWN_D_B				( BIT(24) )
+#define BIT_PD_CP2_ARM9_SHUTDOWN_D_B				( BIT(23) )
+#define BIT_PD_CP2_SYS_SHUTDOWN_D_B				( BIT(22) )
+#define BIT_PD_CP1_L1RAM_SHUTDOWN_D_B				( BIT(21) )
+#define BIT_PD_CP1_TD_SHUTDOWN_D_B				( BIT(20) )
+#define BIT_PD_CP1_GSM_SHUTDOWN_D_B				( BIT(19) )
+#define BIT_PD_CP1_ARM9_SHUTDOWN_D_B				( BIT(18) )
+#define BIT_PD_CP1_SYS_SHUTDOWN_D_B				( BIT(17) )
+#define BIT_PD_CP0_CEVA_SHUTDOWN_D_B				( BIT(16) )
+#define BIT_PD_CP0_TD_SHUTDOWN_D_B				( BIT(15) )
+#define BIT_PD_CP0_GSM_SHUTDOWN_D_B				( BIT(14) )
+#define BIT_PD_CP0_HARQ_SHUTDOWN_D_B				( BIT(13) )
+#define BIT_PD_CP0_HU3GE_SHUTDOWN_D_B				( BIT(12) )
+#define BIT_PD_CP0_ARM9_2_SHUTDOWN_D_B				( BIT(11) )
+#define BIT_PD_CP0_ARM9_1_SHUTDOWN_D_B				( BIT(10) )
+#define BIT_PD_CP0_ARM9_0_SHUTDOWN_D_B				( BIT(9) )
+#define BIT_PD_CP0_SYS_SHUTDOWN_D_B				( BIT(8) )
+#define BIT_PD_GPU_TOP_SHUTDOWN_D_B				( BIT(7) )
+#define BIT_PD_MM_TOP_SHUTDOWN_D_B				( BIT(6) )
+#define BIT_PD_CA7_C3_SHUTDOWN_D_B				( BIT(5) )
+#define BIT_PD_CA7_C2_SHUTDOWN_D_B				( BIT(4) )
+#define BIT_PD_CA7_C1_SHUTDOWN_D_B				( BIT(3) )
+#define BIT_PD_CA7_C0_SHUTDOWN_D_B				( BIT(2) )
+#define BIT_PD_CA7_TOP_SHUTDOWN_D_B				( BIT(1) )
+#define BIT_PD_AP_SYS_SHUTDOWN_D_B				( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_DEBUG_PD1 */
+#define BIT_PD_DDR_PHY_SHUTDOWN_M_B				( BIT(27) )
+#define BIT_PD_DDR_PUBL_SHUTDOWN_M_B				( BIT(26) )
+#define BIT_PD_PUB_SYS_SHUTDOWN_M_B				( BIT(25) )
+#define BIT_PD_CP2_WIFI_SHUTDOWN_M_B				( BIT(24) )
+#define BIT_PD_CP2_ARM9_SHUTDOWN_M_B				( BIT(23) )
+#define BIT_PD_CP2_SYS_SHUTDOWN_M_B				( BIT(22) )
+#define BIT_PD_CP1_L1RAM_SHUTDOWN_M_B				( BIT(21) )
+#define BIT_PD_CP1_TD_SHUTDOWN_M_B				( BIT(20) )
+#define BIT_PD_CP1_GSM_SHUTDOWN_M_B				( BIT(19) )
+#define BIT_PD_CP1_ARM9_SHUTDOWN_M_B				( BIT(18) )
+#define BIT_PD_CP1_SYS_SHUTDOWN_M_B				( BIT(17) )
+#define BIT_PD_CP0_CEVA_SHUTDOWN_M_B				( BIT(16) )
+#define BIT_PD_CP0_TD_SHUTDOWN_M_B				( BIT(15) )
+#define BIT_PD_CP0_GSM_SHUTDOWN_M_B				( BIT(14) )
+#define BIT_PD_CP0_HARQ_SHUTDOWN_M_B				( BIT(13) )
+#define BIT_PD_CP0_HU3GE_SHUTDOWN_M_B				( BIT(12) )
+#define BIT_PD_CP0_ARM9_2_SHUTDOWN_M_B				( BIT(11) )
+#define BIT_PD_CP0_ARM9_1_SHUTDOWN_M_B				( BIT(10) )
+#define BIT_PD_CP0_ARM9_0_SHUTDOWN_M_B				( BIT(9) )
+#define BIT_PD_CP0_SYS_SHUTDOWN_M_B				( BIT(8) )
+#define BIT_PD_GPU_TOP_SHUTDOWN_M_B				( BIT(7) )
+#define BIT_PD_MM_TOP_SHUTDOWN_M_B				( BIT(6) )
+#define BIT_PD_CA7_C3_SHUTDOWN_M_B				( BIT(5) )
+#define BIT_PD_CA7_C2_SHUTDOWN_M_B				( BIT(4) )
+#define BIT_PD_CA7_C1_SHUTDOWN_M_B				( BIT(3) )
+#define BIT_PD_CA7_C0_SHUTDOWN_M_B				( BIT(2) )
+#define BIT_PD_CA7_TOP_SHUTDOWN_M_B				( BIT(1) )
+#define BIT_PD_AP_SYS_SHUTDOWN_M_B				( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_DEBUG_PD2 */
+#define BIT_PD_DDR_PHY_ACK_M					( BIT(27) )
+#define BIT_PD_DDR_PUBL_ACK_M					( BIT(26) )
+#define BIT_PD_PUB_SYS_ACK_M					( BIT(25) )
+#define BIT_PD_CP2_WIFI_ACK_M					( BIT(24) )
+#define BIT_PD_CP2_ARM9_ACK_M					( BIT(23) )
+#define BIT_PD_CP2_SYS_ACK_M					( BIT(22) )
+#define BIT_PD_CP1_L1RAM_ACK_M					( BIT(21) )
+#define BIT_PD_CP1_TD_ACK_M					( BIT(20) )
+#define BIT_PD_CP1_GSM_ACK_M					( BIT(19) )
+#define BIT_PD_CP1_ARM9_ACK_M					( BIT(18) )
+#define BIT_PD_CP1_SYS_ACK_M					( BIT(17) )
+#define BIT_PD_CP0_CEVA_ACK_M					( BIT(16) )
+#define BIT_PD_CP0_TD_ACK_M					( BIT(15) )
+#define BIT_PD_CP0_GSM_ACK_M					( BIT(14) )
+#define BIT_PD_CP0_HARQ_ACK_M					( BIT(13) )
+#define BIT_PD_CP0_HU3GE_ACK_M					( BIT(12) )
+#define BIT_PD_CP0_ARM9_2_ACK_M					( BIT(11) )
+#define BIT_PD_CP0_ARM9_1_ACK_M					( BIT(10) )
+#define BIT_PD_CP0_ARM9_0_ACK_M					( BIT(9) )
+#define BIT_PD_CP0_SYS_ACK_M					( BIT(8) )
+#define BIT_PD_GPU_TOP_ACK_M					( BIT(7) )
+#define BIT_PD_MM_TOP_ACK_M					( BIT(6) )
+#define BIT_PD_CA7_C3_ACK_M					( BIT(5) )
+#define BIT_PD_CA7_C2_ACK_M					( BIT(4) )
+#define BIT_PD_CA7_C1_ACK_M					( BIT(3) )
+#define BIT_PD_CA7_C0_ACK_M					( BIT(2) )
+#define BIT_PD_CA7_TOP_ACK_M					( BIT(1) )
+#define BIT_PD_AP_SYS_ACK_M					( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_DEBUG_PD3 */
+#define BIT_PD_DDR_PHY_ACK_D					( BIT(27) )
+#define BIT_PD_DDR_PUBL_ACK_D					( BIT(26) )
+#define BIT_PD_PUB_SYS_ACK_D					( BIT(25) )
+#define BIT_PD_CP2_WIFI_ACK_D					( BIT(24) )
+#define BIT_PD_CP2_ARM9_ACK_D					( BIT(23) )
+#define BIT_PD_CP2_SYS_ACK_D					( BIT(22) )
+#define BIT_PD_CP1_L1RAM_ACK_D					( BIT(21) )
+#define BIT_PD_CP1_TD_ACK_D					( BIT(20) )
+#define BIT_PD_CP1_GSM_ACK_D					( BIT(19) )
+#define BIT_PD_CP1_ARM9_ACK_D					( BIT(18) )
+#define BIT_PD_CP1_SYS_ACK_D					( BIT(17) )
+#define BIT_PD_CP0_CEVA_ACK_D					( BIT(16) )
+#define BIT_PD_CP0_TD_ACK_D					( BIT(15) )
+#define BIT_PD_CP0_GSM_ACK_D					( BIT(14) )
+#define BIT_PD_CP0_HARQ_ACK_D					( BIT(13) )
+#define BIT_PD_CP0_HU3GE_ACK_D					( BIT(12) )
+#define BIT_PD_CP0_ARM9_2_ACK_D					( BIT(11) )
+#define BIT_PD_CP0_ARM9_1_ACK_D					( BIT(10) )
+#define BIT_PD_CP0_ARM9_0_ACK_D					( BIT(9) )
+#define BIT_PD_CP0_SYS_ACK_D					( BIT(8) )
+#define BIT_PD_GPU_TOP_ACK_D					( BIT(7) )
+#define BIT_PD_MM_TOP_ACK_D					( BIT(6) )
+#define BIT_PD_CA7_C3_ACK_D					( BIT(5) )
+#define BIT_PD_CA7_C2_ACK_D					( BIT(4) )
+#define BIT_PD_CA7_C1_ACK_D					( BIT(3) )
+#define BIT_PD_CA7_C0_ACK_D					( BIT(2) )
+#define BIT_PD_CA7_TOP_ACK_D					( BIT(1) )
+#define BIT_PD_AP_SYS_ACK_D					( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_INT_DISABLE */
+#define BIT_CP2_INT_DISABLE					( BIT(2) )
+#define BIT_CP0_INT_DISABLE					( BIT(1) )
+#define BIT_AP_INT_DISABLE					( BIT(0) )
+
+/* bits definitions for register REG_PMU_APB_PMU_DEBUG_CFG */
+#define BITS_PMU_DEBUG_SEL(_X_)					( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+#endif
diff --git a/include/soc/sprd/chip_x20/__regs_pub_apb.h b/include/soc/sprd/chip_x20/__regs_pub_apb.h
new file mode 100644
index 00000000..be6df61d
--- /dev/null
+++ b/include/soc/sprd/chip_x20/__regs_pub_apb.h
@@ -0,0 +1,477 @@
+/*
+ * Copyright (C) 2014 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+#ifndef __SCI_GLB_REGS_H__
+#error  "Don't include this file directly, Pls include sci_glb_regs.h"
+#endif
+
+
+#ifndef __H_REGS_PUB_APB_HEADFILE_H__
+#define __H_REGS_PUB_APB_HEADFILE_H__ __FILE__
+
+#define	REGS_PUB_APB
+
+/* registers definitions for PUB_APB */
+#define REG_PUB_APB_BUSMON_CNT_START                      SCI_ADDR(REGS_PUB_APB_BASE, 0x0000)
+#define REG_PUB_APB_BUSMON_CFG                            SCI_ADDR(REGS_PUB_APB_BASE, 0x0004)
+#define REG_PUB_APB_DDR_EB                                SCI_ADDR(REGS_PUB_APB_BASE, 0x0008)
+#define REG_PUB_APB_DDR_SOFT_RST                          SCI_ADDR(REGS_PUB_APB_BASE, 0x000C)
+#define REG_PUB_APB_DDR_QOS_CFG1                          SCI_ADDR(REGS_PUB_APB_BASE, 0x0010)
+#define REG_PUB_APB_DDR_QOS_CFG2                          SCI_ADDR(REGS_PUB_APB_BASE, 0x0014)
+#define REG_PUB_APB_DDR_QOS_CFG3                          SCI_ADDR(REGS_PUB_APB_BASE, 0x0018)
+#define REG_PUB_APB_DDR_MRR_STATUS                        SCI_ADDR(REGS_PUB_APB_BASE, 0x001C)
+#define REG_PUB_APB_DDR_ID2QOS_SEL                        SCI_ADDR(REGS_PUB_APB_BASE, 0x003C)
+#define REG_PUB_APB_DDR_ID2QOS_RCFG0                      SCI_ADDR(REGS_PUB_APB_BASE, 0x0040)
+#define REG_PUB_APB_DDR_ID2QOS_RCFG1                      SCI_ADDR(REGS_PUB_APB_BASE, 0x0044)
+#define REG_PUB_APB_DDR_ID2QOS_RCFG2                      SCI_ADDR(REGS_PUB_APB_BASE, 0x0048)
+#define REG_PUB_APB_DDR_ID2QOS_RCFG3                      SCI_ADDR(REGS_PUB_APB_BASE, 0x004c)
+#define REG_PUB_APB_DDR_ID2QOS_RCFG4                      SCI_ADDR(REGS_PUB_APB_BASE, 0x0050)
+#define REG_PUB_APB_DDR_ID2QOS_RCFG5                      SCI_ADDR(REGS_PUB_APB_BASE, 0x0054)
+#define REG_PUB_APB_DDR_ID2QOS_RCFG6                      SCI_ADDR(REGS_PUB_APB_BASE, 0x0058)
+#define REG_PUB_APB_DDR_ID2QOS_RCFG7                      SCI_ADDR(REGS_PUB_APB_BASE, 0x005c)
+#define REG_PUB_APB_DDR_ID2QOS_RCFG8                      SCI_ADDR(REGS_PUB_APB_BASE, 0x0060)
+#define REG_PUB_APB_DDR_ID2QOS_RCFG9                      SCI_ADDR(REGS_PUB_APB_BASE, 0x0064)
+#define REG_PUB_APB_DDR_ID2QOS_WCFG0                      SCI_ADDR(REGS_PUB_APB_BASE, 0x0080)
+#define REG_PUB_APB_DDR_ID2QOS_WCFG1                      SCI_ADDR(REGS_PUB_APB_BASE, 0x0084)
+#define REG_PUB_APB_DDR_ID2QOS_WCFG2                      SCI_ADDR(REGS_PUB_APB_BASE, 0x0088)
+#define REG_PUB_APB_DDR_ID2QOS_WCFG3                      SCI_ADDR(REGS_PUB_APB_BASE, 0x008c)
+#define REG_PUB_APB_DDR_ID2QOS_WCFG4                      SCI_ADDR(REGS_PUB_APB_BASE, 0x0090)
+#define REG_PUB_APB_DDR_ID2QOS_WCFG5                      SCI_ADDR(REGS_PUB_APB_BASE, 0x0094)
+#define REG_PUB_APB_DDR_ID2QOS_WCFG6                      SCI_ADDR(REGS_PUB_APB_BASE, 0x0098)
+#define REG_PUB_APB_DDR_ID2QOS_WCFG7                      SCI_ADDR(REGS_PUB_APB_BASE, 0x009c)
+#define REG_PUB_APB_DDR_ID2QOS_WCFG8                      SCI_ADDR(REGS_PUB_APB_BASE, 0x00a0)
+#define REG_PUB_APB_DDR_ID2QOS_WCFG9                      SCI_ADDR(REGS_PUB_APB_BASE, 0x00a4)
+#define REG_PUB_APB_DFI_TIMEOUT_CFG                       SCI_ADDR(REGS_PUB_APB_BASE, 0x0100)
+#define REG_PUB_APB_DFI_TIMEOUT_STATUS                    SCI_ADDR(REGS_PUB_APB_BASE, 0x0104)
+#define REG_PUB_APB_DFI_TIMEOUT_EN_CNT                    SCI_ADDR(REGS_PUB_APB_BASE, 0x0108)
+#define REG_PUB_APB_DFI_TIMEOUT_VALID_CNT                 SCI_ADDR(REGS_PUB_APB_BASE, 0x010c)
+#define REG_PUB_APB_DMC_PORT_REMAP_EN                     SCI_ADDR(REGS_PUB_APB_BASE, 0x3000)
+#define REG_PUB_APB_DMC_PORTS_MPU_EN                      SCI_ADDR(REGS_PUB_APB_BASE, 0x3004)
+#define REG_PUB_APB_DMC_PORT0_ADDR_REMAP                  SCI_ADDR(REGS_PUB_APB_BASE, 0x3008)
+#define REG_PUB_APB_DMC_PORT1_ADDR_REMAP                  SCI_ADDR(REGS_PUB_APB_BASE, 0x300C)
+#define REG_PUB_APB_DMC_PORT2_ADDR_REMAP                  SCI_ADDR(REGS_PUB_APB_BASE, 0x3010)
+#define REG_PUB_APB_DMC_PORT3_ADDR_REMAP                  SCI_ADDR(REGS_PUB_APB_BASE, 0x3014)
+#define REG_PUB_APB_DMC_PORT4_ADDR_REMAP                  SCI_ADDR(REGS_PUB_APB_BASE, 0x3018)
+#define REG_PUB_APB_DMC_PORT5_ADDR_REMAP                  SCI_ADDR(REGS_PUB_APB_BASE, 0x301C)
+#define REG_PUB_APB_DMC_PORT6_ADDR_REMAP                  SCI_ADDR(REGS_PUB_APB_BASE, 0x3020)
+#define REG_PUB_APB_DMC_PORT7_ADDR_REMAP                  SCI_ADDR(REGS_PUB_APB_BASE, 0x3024)
+#define REG_PUB_APB_DMC_PORT8_ADDR_REMAP                  SCI_ADDR(REGS_PUB_APB_BASE, 0x3028)
+#define REG_PUB_APB_DMC_PORT9_ADDR_REMAP                  SCI_ADDR(REGS_PUB_APB_BASE, 0x302C)
+#define REG_PUB_APB_DMC_PORT0_MPU_RANGE                   SCI_ADDR(REGS_PUB_APB_BASE, 0x3030)
+#define REG_PUB_APB_DMC_PORT1_MPU_RANGE                   SCI_ADDR(REGS_PUB_APB_BASE, 0x3034)
+#define REG_PUB_APB_DMC_PORT2_MPU_RANGE                   SCI_ADDR(REGS_PUB_APB_BASE, 0x3038)
+#define REG_PUB_APB_DMC_PORT3_MPU_RANGE                   SCI_ADDR(REGS_PUB_APB_BASE, 0x303C)
+#define REG_PUB_APB_DMC_PORT4_MPU_RANGE                   SCI_ADDR(REGS_PUB_APB_BASE, 0x3040)
+#define REG_PUB_APB_DMC_PORT5_MPU_RANGE                   SCI_ADDR(REGS_PUB_APB_BASE, 0x3044)
+#define REG_PUB_APB_DMC_PORT6_MPU_RANGE                   SCI_ADDR(REGS_PUB_APB_BASE, 0x3048)
+#define REG_PUB_APB_DMC_PORT7_MPU_RANGE                   SCI_ADDR(REGS_PUB_APB_BASE, 0x3050)
+#define REG_PUB_APB_DMC_PORT8_MPU_RANGE                   SCI_ADDR(REGS_PUB_APB_BASE, 0x3054)
+#define REG_PUB_APB_DMC_PORT9_MPU_RANGE                   SCI_ADDR(REGS_PUB_APB_BASE, 0x3058)
+#define REG_PUB_APB_DMC_PORT0_DUMP_ADDR                   SCI_ADDR(REGS_PUB_APB_BASE, 0x305C)
+#define REG_PUB_APB_DMC_PORT1_DUMP_ADDR                   SCI_ADDR(REGS_PUB_APB_BASE, 0x3060)
+#define REG_PUB_APB_DMC_PORT2_DUMP_ADDR                   SCI_ADDR(REGS_PUB_APB_BASE, 0x3064)
+#define REG_PUB_APB_DMC_PORT3_DUMP_ADDR                   SCI_ADDR(REGS_PUB_APB_BASE, 0x3068)
+#define REG_PUB_APB_DMC_PORT4_DUMP_ADDR                   SCI_ADDR(REGS_PUB_APB_BASE, 0x306C)
+#define REG_PUB_APB_DMC_PORT5_DUMP_ADDR                   SCI_ADDR(REGS_PUB_APB_BASE, 0x3070)
+#define REG_PUB_APB_DMC_PORT6_DUMP_ADDR                   SCI_ADDR(REGS_PUB_APB_BASE, 0x3074)
+#define REG_PUB_APB_DMC_PORT7_DUMP_ADDR                   SCI_ADDR(REGS_PUB_APB_BASE, 0x3078)
+#define REG_PUB_APB_DMC_PORT8_DUMP_ADDR                   SCI_ADDR(REGS_PUB_APB_BASE, 0x307C)
+#define REG_PUB_APB_DMC_PORT9_DUMP_ADDR                   SCI_ADDR(REGS_PUB_APB_BASE, 0x3080)
+
+
+
+/* bits definitions for register REG_PUB_APB_BUSMON_CNT_START */
+#define BIT_PUB_BUSMON_CNT_START                          ( BIT(0) )
+
+/* bits definitions for register REG_PUB_APB_BUSMON_CFG */
+#define BIT_PUB_BUSMON9_EB                                ( BIT(25) )
+#define BIT_PUB_BUSMON8_EB                                ( BIT(24) )
+#define BIT_PUB_BUSMON7_EB                                ( BIT(23) )
+#define BIT_PUB_BUSMON6_EB                                ( BIT(22) )
+#define BIT_PUB_BUSMON5_EB                                ( BIT(21) )
+#define BIT_PUB_BUSMON4_EB                                ( BIT(20) )
+#define BIT_PUB_BUSMON3_EB                                ( BIT(19) )
+#define BIT_PUB_BUSMON2_EB                                ( BIT(18) )
+#define BIT_PUB_BUSMON1_EB                                ( BIT(17) )
+#define BIT_PUB_BUSMON0_EB                                ( BIT(16) )
+#define BIT_PUB_BUSMON9_SOFT_RST                          ( BIT(9) )
+#define BIT_PUB_BUSMON8_SOFT_RST                          ( BIT(8) )
+#define BIT_PUB_BUSMON7_SOFT_RST                          ( BIT(7) )
+#define BIT_PUB_BUSMON6_SOFT_RST                          ( BIT(6) )
+#define BIT_PUB_BUSMON5_SOFT_RST                          ( BIT(5) )
+#define BIT_PUB_BUSMON4_SOFT_RST                          ( BIT(4) )
+#define BIT_PUB_BUSMON3_SOFT_RST                          ( BIT(3) )
+#define BIT_PUB_BUSMON2_SOFT_RST                          ( BIT(2) )
+#define BIT_PUB_BUSMON1_SOFT_RST                          ( BIT(1) )
+#define BIT_PUB_BUSMON0_SOFT_RST                          ( BIT(0) )
+
+/* bits definitions for register REG_PUB_APB_DDR_EB */
+
+/* bits definitions for register REG_PUB_APB_DDR_SOFT_RST */
+
+/* bits definitions for register REG_PUB_APB_DDR_QOS_CFG1 */
+#define BITS_DMC_ARQOS_3(_X_)                             ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_AWQOS_3(_X_)                             ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_ARQOS_2(_X_)                             ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_AWQOS_2(_X_)                             ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_ARQOS_1(_X_)                             ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_AWQOS_1(_X_)                             ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_ARQOS_0(_X_)                             ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_AWQOS_0(_X_)                             ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_QOS_CFG2 */
+#define BITS_DMC_ARQOS_7(_X_)                             ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_AWQOS_7(_X_)                             ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_ARQOS_6(_X_)                             ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_AWQOS_6(_X_)                             ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_ARQOS_5(_X_)                             ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_AWQOS_5(_X_)                             ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_ARQOS_4(_X_)                             ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_AWQOS_4(_X_)                             ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_QOS_CFG3 */
+#define BITS_DMC_ARQOS_9(_X_)                             ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_AWQOS_9(_X_)                             ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_ARQOS_8(_X_)                             ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_AWQOS_8(_X_)                             ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_MRR_STATUS */
+#define BIT_DDRC_CO_RD_MRR_DATA_VALID                     ( BIT(8) )
+#define BITS_DDRC_CO_RD_MRR_DATA(_X_)                     ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_SEL */
+#define BITS_DMC_ID_SEL(_X_)                              ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) )
+#define BITS_DMC_QOS_SEL(_X_)                             ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG0 */
+#define BITS_DMC_ARQOS_0_ID7(_X_)                         ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_ARQOS_0_ID6(_X_)                         ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_ARQOS_0_ID5(_X_)                         ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_ARQOS_0_ID4(_X_)                         ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_ARQOS_0_ID3(_X_)                         ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_ARQOS_0_ID2(_X_)                         ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_ARQOS_0_ID1(_X_)                         ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_ARQOS_0_ID0(_X_)                         ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG1 */
+#define BITS_DMC_ARQOS_1_ID7(_X_)                         ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_ARQOS_1_ID6(_X_)                         ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_ARQOS_1_ID5(_X_)                         ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_ARQOS_1_ID4(_X_)                         ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_ARQOS_1_ID3(_X_)                         ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_ARQOS_1_ID2(_X_)                         ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_ARQOS_1_ID1(_X_)                         ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_ARQOS_1_ID0(_X_)                         ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG2 */
+#define BITS_DMC_ARQOS_2_ID7(_X_)                         ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_ARQOS_2_ID6(_X_)                         ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_ARQOS_2_ID5(_X_)                         ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_ARQOS_2_ID4(_X_)                         ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_ARQOS_2_ID3(_X_)                         ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_ARQOS_2_ID2(_X_)                         ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_ARQOS_2_ID1(_X_)                         ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_ARQOS_2_ID0(_X_)                         ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG3 */
+#define BITS_DMC_ARQOS_3_ID7(_X_)                         ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_ARQOS_3_ID6(_X_)                         ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_ARQOS_3_ID5(_X_)                         ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_ARQOS_3_ID4(_X_)                         ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_ARQOS_3_ID3(_X_)                         ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_ARQOS_3_ID2(_X_)                         ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_ARQOS_3_ID1(_X_)                         ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_ARQOS_3_ID0(_X_)                         ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG4 */
+#define BITS_DMC_ARQOS_4_ID7(_X_)                         ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_ARQOS_4_ID6(_X_)                         ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_ARQOS_4_ID5(_X_)                         ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_ARQOS_4_ID4(_X_)                         ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_ARQOS_4_ID3(_X_)                         ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_ARQOS_4_ID2(_X_)                         ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_ARQOS_4_ID1(_X_)                         ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_ARQOS_4_ID0(_X_)                         ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG5 */
+#define BITS_DMC_ARQOS_5_ID7(_X_)                         ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_ARQOS_5_ID6(_X_)                         ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_ARQOS_5_ID5(_X_)                         ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_ARQOS_5_ID4(_X_)                         ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_ARQOS_5_ID3(_X_)                         ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_ARQOS_5_ID2(_X_)                         ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_ARQOS_5_ID1(_X_)                         ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_ARQOS_5_ID0(_X_)                         ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG6 */
+#define BITS_DMC_ARQOS_6_ID7(_X_)                         ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_ARQOS_6_ID6(_X_)                         ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_ARQOS_6_ID5(_X_)                         ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_ARQOS_6_ID4(_X_)                         ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_ARQOS_6_ID3(_X_)                         ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_ARQOS_6_ID2(_X_)                         ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_ARQOS_6_ID1(_X_)                         ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_ARQOS_6_ID0(_X_)                         ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG7 */
+#define BITS_DMC_ARQOS_7_ID7(_X_)                         ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_ARQOS_7_ID6(_X_)                         ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_ARQOS_7_ID5(_X_)                         ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_ARQOS_7_ID4(_X_)                         ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_ARQOS_7_ID3(_X_)                         ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_ARQOS_7_ID2(_X_)                         ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_ARQOS_7_ID1(_X_)                         ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_ARQOS_7_ID0(_X_)                         ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG8 */
+#define BITS_DMC_ARQOS_8_ID7(_X_)                         ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_ARQOS_8_ID6(_X_)                         ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_ARQOS_8_ID5(_X_)                         ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_ARQOS_8_ID4(_X_)                         ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_ARQOS_8_ID3(_X_)                         ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_ARQOS_8_ID2(_X_)                         ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_ARQOS_8_ID1(_X_)                         ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_ARQOS_8_ID0(_X_)                         ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG9 */
+#define BITS_DMC_ARQOS_9_ID7(_X_)                         ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_ARQOS_9_ID6(_X_)                         ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_ARQOS_9_ID5(_X_)                         ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_ARQOS_9_ID4(_X_)                         ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_ARQOS_9_ID3(_X_)                         ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_ARQOS_9_ID2(_X_)                         ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_ARQOS_9_ID1(_X_)                         ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_ARQOS_9_ID0(_X_)                         ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG0 */
+#define BITS_DMC_AWQOS_0_ID7(_X_)                         ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_AWQOS_0_ID6(_X_)                         ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_AWQOS_0_ID5(_X_)                         ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_AWQOS_0_ID4(_X_)                         ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_AWQOS_0_ID3(_X_)                         ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_AWQOS_0_ID2(_X_)                         ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_AWQOS_0_ID1(_X_)                         ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_AWQOS_0_ID0(_X_)                         ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG1 */
+#define BITS_DMC_AWQOS_1_ID7(_X_)                         ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_AWQOS_1_ID6(_X_)                         ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_AWQOS_1_ID5(_X_)                         ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_AWQOS_1_ID4(_X_)                         ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_AWQOS_1_ID3(_X_)                         ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_AWQOS_1_ID2(_X_)                         ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_AWQOS_1_ID1(_X_)                         ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_AWQOS_1_ID0(_X_)                         ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG2 */
+#define BITS_DMC_AWQOS_2_ID7(_X_)                         ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_AWQOS_2_ID6(_X_)                         ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_AWQOS_2_ID5(_X_)                         ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_AWQOS_2_ID4(_X_)                         ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_AWQOS_2_ID3(_X_)                         ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_AWQOS_2_ID2(_X_)                         ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_AWQOS_2_ID1(_X_)                         ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_AWQOS_2_ID0(_X_)                         ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG3 */
+#define BITS_DMC_AWQOS_3_ID7(_X_)                         ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_AWQOS_3_ID6(_X_)                         ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_AWQOS_3_ID5(_X_)                         ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_AWQOS_3_ID4(_X_)                         ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_AWQOS_3_ID3(_X_)                         ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_AWQOS_3_ID2(_X_)                         ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_AWQOS_3_ID1(_X_)                         ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_AWQOS_3_ID0(_X_)                         ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG4 */
+#define BITS_DMC_AWQOS_4_ID7(_X_)                         ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_AWQOS_4_ID6(_X_)                         ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_AWQOS_4_ID5(_X_)                         ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_AWQOS_4_ID4(_X_)                         ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_AWQOS_4_ID3(_X_)                         ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_AWQOS_4_ID2(_X_)                         ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_AWQOS_4_ID1(_X_)                         ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_AWQOS_4_ID0(_X_)                         ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG5 */
+#define BITS_DMC_AWQOS_5_ID7(_X_)                         ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_AWQOS_5_ID6(_X_)                         ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_AWQOS_5_ID5(_X_)                         ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_AWQOS_5_ID4(_X_)                         ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_AWQOS_5_ID3(_X_)                         ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_AWQOS_5_ID2(_X_)                         ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_AWQOS_5_ID1(_X_)                         ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_AWQOS_5_ID0(_X_)                         ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG6 */
+#define BITS_DMC_AWQOS_6_ID7(_X_)                         ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_AWQOS_6_ID6(_X_)                         ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_AWQOS_6_ID5(_X_)                         ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_AWQOS_6_ID4(_X_)                         ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_AWQOS_6_ID3(_X_)                         ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_AWQOS_6_ID2(_X_)                         ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_AWQOS_6_ID1(_X_)                         ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_AWQOS_6_ID0(_X_)                         ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG7 */
+#define BITS_DMC_AWQOS_7_ID7(_X_)                         ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_AWQOS_7_ID6(_X_)                         ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_AWQOS_7_ID5(_X_)                         ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_AWQOS_7_ID4(_X_)                         ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_AWQOS_7_ID3(_X_)                         ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_AWQOS_7_ID2(_X_)                         ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_AWQOS_7_ID1(_X_)                         ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_AWQOS_7_ID0(_X_)                         ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG8 */
+#define BITS_DMC_AWQOS_8_ID7(_X_)                         ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_AWQOS_8_ID6(_X_)                         ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_AWQOS_8_ID5(_X_)                         ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_AWQOS_8_ID4(_X_)                         ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_AWQOS_8_ID3(_X_)                         ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_AWQOS_8_ID2(_X_)                         ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_AWQOS_8_ID1(_X_)                         ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_AWQOS_8_ID0(_X_)                         ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG9 */
+#define BITS_DMC_AWQOS_9_ID7(_X_)                         ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DMC_AWQOS_9_ID6(_X_)                         ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
+#define BITS_DMC_AWQOS_9_ID5(_X_)                         ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DMC_AWQOS_9_ID4(_X_)                         ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+#define BITS_DMC_AWQOS_9_ID3(_X_)                         ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DMC_AWQOS_9_ID2(_X_)                         ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
+#define BITS_DMC_AWQOS_9_ID1(_X_)                         ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DMC_AWQOS_9_ID0(_X_)                         ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DFI_TIMEOUT_CFG */
+#define BITS_DFI_TIMEOUT_THRESHOLD(_X_)                   ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DFI_TIMEOUT_CLR(_X_)                         ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BITS_DFI_TIMEOUT_EN(_X_)                          ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DFI_TIMEOUT_STATUS */
+#define BITS_DFI_TIMEOUT_STATUS(_X_)                      ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
+
+/* bits definitions for register REG_PUB_APB_DFI_TIMEOUT_EN_CNT */
+#define BITS_DFI_TIMEOUT_EN3_CNT(_X_)                     ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DFI_TIMEOUT_EN2_CNT(_X_)                     ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DFI_TIMEOUT_EN1_CNT(_X_)                     ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DFI_TIMEOUT_EN0_CNT(_X_)                     ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PUB_APB_DFI_TIMEOUT_VALID_CNT */
+#define BITS_DFI_TIMEOUT_VALID3_CNT(_X_)                  ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BITS_DFI_TIMEOUT_VALID2_CNT(_X_)                  ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BITS_DFI_TIMEOUT_VALID1_CNT(_X_)                  ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BITS_DFI_TIMEOUT_VALID0_CNT(_X_)                  ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT_REMAP_EN */
+#define BITS_DMC_PORTS_REMAP_EN(_X_)                      ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+
+/* bits definitions for register REG_PUB_APB_DMC_PORTS_MPU_EN */
+#define BITS_DMC_PORTS_MPU_EN(_X_)                        ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT0_ADDR_REMAP */
+#define BITS_DMC_PORT0_ADDR_REMAP(_X_)                    (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT1_ADDR_REMAP */
+#define BITS_DMC_PORT1_ADDR_REMAP(_X_)                    (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT2_ADDR_REMAP */
+#define BITS_DMC_PORT2_ADDR_REMAP(_X_)                    (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT3_ADDR_REMAP */
+#define BITS_DMC_PORT3_ADDR_REMAP(_X_)                    (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT4_ADDR_REMAP */
+#define BITS_DMC_PORT4_ADDR_REMAP(_X_)                    (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT5_ADDR_REMAP */
+#define BITS_DMC_PORT5_ADDR_REMAP(_X_)                    (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT6_ADDR_REMAP */
+#define BITS_DMC_PORT6_ADDR_REMAP(_X_)                    (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT7_ADDR_REMAP */
+#define BITS_DMC_PORT7_ADDR_REMAP(_X_)                    (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT8_ADDR_REMAP */
+#define BITS_DMC_PORT8_ADDR_REMAP(_X_)                    (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT9_ADDR_REMAP */
+#define BITS_DMC_PORT9_ADDR_REMAP(_X_)                    (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT0_MPU_RANGE */
+#define BITS_DMC_PORT0_MPU_RANGE(_X_)                     (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT1_MPU_RANGE */
+#define BITS_DMC_PORT1_MPU_RANGE(_X_)                     (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT2_MPU_RANGE */
+#define BITS_DMC_PORT2_MPU_RANGE(_X_)                     (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT3_MPU_RANGE */
+#define BITS_DMC_PORT3_MPU_RANGE(_X_)                     (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT4_MPU_RANGE */
+#define BITS_DMC_PORT4_MPU_RANGE(_X_)                     (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT5_MPU_RANGE */
+#define BITS_DMC_PORT5_MPU_RANGE(_X_)                     (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT6_MPU_RANGE */
+#define BITS_DMC_PORT6_MPU_RANGE(_X_)                     (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT7_MPU_RANGE */
+#define BITS_DMC_PORT7_MPU_RANGE(_X_)                     (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT8_MPU_RANGE */
+#define BITS_DMC_PORT8_MPU_RANGE(_X_)                     (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT9_MPU_RANGE */
+#define BITS_DMC_PORT9_MPU_RANGE(_X_)                     (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT0_DUMP_ADDR */
+#define BITS_DMC_PORT0_DUMP_ADDR(_X_)                     (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT1_DUMP_ADDR */
+#define BITS_DMC_PORT1_DUMP_ADDR(_X_)                     (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT2_DUMP_ADDR */
+#define BITS_DMC_PORT2_DUMP_ADDR(_X_)                     (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT3_DUMP_ADDR */
+#define BITS_DMC_PORT3_DUMP_ADDR(_X_)                     (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT4_DUMP_ADDR */
+#define BITS_DMC_PORT4_DUMP_ADDR(_X_)                     (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT5_DUMP_ADDR */
+#define BITS_DMC_PORT5_DUMP_ADDR(_X_)                     (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT6_DUMP_ADDR */
+#define BITS_DMC_PORT6_DUMP_ADDR(_X_)                     (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT7_DUMP_ADDR */
+#define BITS_DMC_PORT7_DUMP_ADDR(_X_)                     (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT8_DUMP_ADDR */
+#define BITS_DMC_PORT8_DUMP_ADDR(_X_)                     (_X_)
+
+/* bits definitions for register REG_PUB_APB_DMC_PORT9_DUMP_ADDR */
+#define BITS_DMC_PORT9_DUMP_ADDR(_X_)                     (_X_)
+
+#endif
diff --git a/include/soc/sprd/chip_x20/__regs_wcdma_ahb_rf.h b/include/soc/sprd/chip_x20/__regs_wcdma_ahb_rf.h
new file mode 100644
index 00000000..1be075b6
--- /dev/null
+++ b/include/soc/sprd/chip_x20/__regs_wcdma_ahb_rf.h
@@ -0,0 +1,136 @@
+/*
+ * Copyright (C) 2014 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+#ifndef __SCI_GLB_REGS_H__
+#error  "Don't include this file directly, Pls include sci_glb_regs.h"
+#endif
+
+
+#ifndef __H_REGS_WCDMA_AHB_RF_HEADFILE_H__
+#define __H_REGS_WCDMA_AHB_RF_HEADFILE_H__ __FILE__
+
+#define	REGS_WCDMA_AHB_RF
+
+/* registers definitions for WCDMA_AHB_RF */
+#define REG_WCDMA_AHB_RF_AHB_EB0                          SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0000)
+#define REG_WCDMA_AHB_RF_AHB_RST0                         SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0004)
+#define REG_WCDMA_AHB_RF_ARCH_EB_REG                      SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0018)
+#define REG_WCDMA_AHB_RF_AHB_REMAP                        SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x001C)
+#define REG_WCDMA_AHB_RF_AHB_MISC_CTL                     SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0020)
+#define REG_WCDMA_AHB_RF_AHB_MTX_PRI_SEL0                 SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0024)
+#define REG_WCDMA_AHB_RF_AHB_MTX_PRI_SEL1                 SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0028)
+#define REG_WCDMA_AHB_RF_AHB1_PAUSE                       SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x002C)
+#define REG_WCDMA_AHB_RF_AHB2_PAUSE                       SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0030)
+#define REG_WCDMA_AHB_RF_AHB_SLP_CTL                      SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0034)
+#define REG_WCDMA_AHB_RF_AHB2_SLP_STS                     SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x0038)
+#define REG_WCDMA_AHB_RF_MCU_CLK_CTL                      SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x003C)
+#define REG_WCDMA_AHB_RF_CHIP_ID                          SCI_ADDR(REGS_WCDMA_AHB_RF_BASE, 0x01FC)
+
+
+
+/* bits definitions for register REG_WCDMA_AHB_RF_AHB_EB0 */
+#define BITS_WCDMA_EN(_X_)                                ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
+#define BIT_BUSMON1_EN                                    ( BIT(2) )
+#define BIT_BUSMON0_EN                                    ( BIT(1) )
+#define BIT_SPINLOCK_EN                                   ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_AHB_RF_AHB_RST0 */
+#define BIT_WCDMA_SOFT_RST                                ( BIT(3) )
+#define BIT_BUSMON1_SOFT_RST                              ( BIT(2) )
+#define BIT_BUSMON0_SOFT_RST                              ( BIT(1) )
+#define BIT_SPINLOCK_SOFT_RST                             ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_AHB_RF_ARCH_EB_REG */
+#define BIT_AHB_ARCH_EB                                   ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_AHB_RF_AHB_REMAP */
+#define BIT_ARM_JTAG_EN_ARM2                              ( BIT(2) )
+#define BIT_ARM_JTAG_EN_ARM1                              ( BIT(1) )
+#define BIT_REMAP                                         ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_AHB_RF_AHB_MISC_CTL */
+#define BIT_FORCE_WSYS_ACC_STOP                           ( BIT(3) )
+#define BIT_W_DMA_LSLP_EN                                 ( BIT(2) )
+#define BIT_BUSMON1_SEL                                   ( BIT(1) )
+#define BIT_BUSMON0_SEL                                   ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_AHB_RF_AHB_MTX_PRI_SEL0 */
+#define BITS_ARMMTX_M3TOS0_RND_THR(_X_)                   ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
+#define BIT_ARMMTX_M3TOS0_ADJ_EN                          ( BIT(27) )
+#define BIT_ARMMTX_M3TOS0_RND_EN                          ( BIT(26) )
+#define BITS_ARMMTX_M3TOS0_SEL(_X_)                       ( (_X_) << 24 & (BIT(24)|BIT(25)) )
+#define BITS_ARMMTX_M2TOS0_RND_THR(_X_)                   ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BIT_ARMMTX_M2TOS0_ADJ_EN                          ( BIT(19) )
+#define BIT_ARMMTX_M2TOS0_RND_EN                          ( BIT(18) )
+#define BITS_ARMMTX_M2TOS0_SEL(_X_)                       ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_ARMMTX_M1TOS0_RND_THR(_X_)                   ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BIT_ARMMTX_M1TOS0_ADJ_EN                          ( BIT(11) )
+#define BIT_ARMMTX_M1TOS0_RND_EN                          ( BIT(10) )
+#define BITS_ARMMTX_M1TOS0_SEL(_X_)                       ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ARMMTX_M0TOS0_RND_THR(_X_)                   ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_ARMMTX_M0TOS0_ADJ_EN                          ( BIT(3) )
+#define BIT_ARMMTX_M0TOS0_RND_EN                          ( BIT(2) )
+#define BITS_ARMMTX_M0TOS0_SEL(_X_)                       ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_WCDMA_AHB_RF_AHB_MTX_PRI_SEL1 */
+#define BITS_ARMMTX_M6TOS0_RND_THR(_X_)                   ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
+#define BIT_ARMMTX_M6TOS0_ADJ_EN                          ( BIT(19) )
+#define BIT_ARMMTX_M6TOS0_RND_EN                          ( BIT(18) )
+#define BITS_ARMMTX_M6TOS0_SEL(_X_)                       ( (_X_) << 16 & (BIT(16)|BIT(17)) )
+#define BITS_ARMMTX_M5TOS0_RND_THR(_X_)                   ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
+#define BIT_ARMMTX_M5TOS0_ADJ_EN                          ( BIT(11) )
+#define BIT_ARMMTX_M5TOS0_RND_EN                          ( BIT(10) )
+#define BITS_ARMMTX_M5TOS0_SEL(_X_)                       ( (_X_) << 8 & (BIT(8)|BIT(9)) )
+#define BITS_ARMMTX_M4TOS0_RND_THR(_X_)                   ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
+#define BIT_ARMMTX_M4TOS0_ADJ_EN                          ( BIT(3) )
+#define BIT_ARMMTX_M4TOS0_RND_EN                          ( BIT(2) )
+#define BITS_ARMMTX_M4TOS0_SEL(_X_)                       ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_WCDMA_AHB_RF_AHB1_PAUSE */
+#define BIT_APB1_SLEEP                                    ( BIT(3) )
+#define BIT_MCU1_DEEP_SLEEP_EN                            ( BIT(2) )
+#define BIT_MCU1_SYS_SLEEP_EN                             ( BIT(1) )
+#define BIT_MCU1_CORE_SLEEP                               ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_AHB_RF_AHB2_PAUSE */
+#define BIT_APB2_SLEEP                                    ( BIT(3) )
+#define BIT_MCU2_DEEP_SLEEP_EN                            ( BIT(2) )
+#define BIT_MCU2_SYS_SLEEP_EN                             ( BIT(1) )
+#define BIT_MCU2_CORE_SLEEP                               ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_AHB_RF_AHB_SLP_CTL */
+#define BIT_MCUMTX_AUTO_GATE_EN                           ( BIT(4) )
+#define BIT_MCU_AUTO_GATE_EN                              ( BIT(3) )
+#define BIT_AHB_AUTO_GATE_EN                              ( BIT(2) )
+#define BIT_ARM2_AUTO_GATE_EN                             ( BIT(1) )
+#define BIT_ARM1_AUTO_GATE_EN                             ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_AHB_RF_AHB2_SLP_STS */
+#define BIT_APB2_PERI_SLEEP                               ( BIT(1) )
+#define BIT_APB1_PERI_SLEEP                               ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_AHB_RF_MCU_CLK_CTL */
+#define BITS_CLK_AHB_DIV(_X_)                             ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) )
+#define BITS_CLK_MCU_DIV(_X_)                             ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) )
+#define BITS_CLK_APB_SEL(_X_)                             ( (_X_) << 4 & (BIT(4)|BIT(5)) )
+#define BITS_CLK_MCU_SEL(_X_)                             ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_WCDMA_AHB_RF_CHIP_ID */
+#define BITS_CHIP_ID(_X_)                                 (_X_)
+
+#endif
diff --git a/include/soc/sprd/chip_x20/__regs_wcdma_apb_rf.h b/include/soc/sprd/chip_x20/__regs_wcdma_apb_rf.h
new file mode 100644
index 00000000..4249f10d
--- /dev/null
+++ b/include/soc/sprd/chip_x20/__regs_wcdma_apb_rf.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2014 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+#ifndef __SCI_GLB_REGS_H__
+#error  "Don't include this file directly, Pls include sci_glb_regs.h"
+#endif
+
+
+#ifndef __H_REGS_WCDMA_APB_RF_HEADFILE_H__
+#define __H_REGS_WCDMA_APB_RF_HEADFILE_H__ __FILE__
+
+#define	REGS_WCDMA_APB_RF
+
+/* registers definitions for WCDMA_APB_RF */
+#define REG_WCDMA_APB_RF_APB_EB                           SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0000)
+#define REG_WCDMA_APB_RF_APB_RST                          SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0004)
+#define REG_WCDMA_APB_RF_APB_SLEEP_ST                     SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0008)
+#define REG_WCDMA_APB_RF_APB_MCU_RST                      SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0018)
+#define REG_WCDMA_APB_RF_APB_CLK_SEL0                     SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x001C)
+#define REG_WCDMA_APB_RF_APB_CLK_DIV0                     SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0020)
+#define REG_WCDMA_APB_RF_APB_ARCH_EB                      SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0024)
+#define REG_WCDMA_APB_RF_APB_SLP_CTL                      SCI_ADDR(REGS_WCDMA_APB_RF_BASE, 0x0028)
+
+
+
+/* bits definitions for register REG_WCDMA_APB_RF_APB_EB */
+#define BIT_TMR_RTC_EB                                    ( BIT(6) )
+#define BIT_TMR_EB                                        ( BIT(5) )
+#define BIT_SYSTMR_RTC_EB                                 ( BIT(4) )
+#define BIT_SYSTMR_EB                                     ( BIT(3) )
+#define BIT_UART0_EB                                      ( BIT(2) )
+#define BIT_WDG_RTC_EB                                    ( BIT(1) )
+#define BIT_WDG_EB                                        ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_APB_RF_APB_RST */
+#define BIT_TMR_SOFT_RST                                  ( BIT(3) )
+#define BIT_SYSTMR_SOFT_RST                               ( BIT(2) )
+#define BIT_UART0_SOFT_RST                                ( BIT(1) )
+#define BIT_WDG_SOFT_RST                                  ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_APB_RF_APB_SLEEP_ST */
+#define BIT_CHIP_SLEEP_REC_CLR                            ( BIT(1) )
+#define BIT_CHIP_SLEEP_REC                                ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_APB_RF_APB_MCU_RST */
+#define BIT_MCU_SOFT_RST_SET                              ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_APB_RF_APB_CLK_SEL0 */
+#define BITS_CLK_UART0_SEL(_X_)                           ( (_X_) & (BIT(0)|BIT(1)) )
+
+/* bits definitions for register REG_WCDMA_APB_RF_APB_CLK_DIV0 */
+#define BITS_CLK_UART0_DIV(_X_)                           ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
+
+/* bits definitions for register REG_WCDMA_APB_RF_APB_ARCH_EB */
+#define BIT_RTC_ARCH_EB                                   ( BIT(1) )
+#define BIT_APB_ARCH_EB                                   ( BIT(0) )
+
+/* bits definitions for register REG_WCDMA_APB_RF_APB_SLP_CTL */
+#define BIT_APB_PERI_FRC_ON                               ( BIT(1) )
+#define BIT_APB_PERI_FRC_SLP                              ( BIT(0) )
+
+#endif
diff --git a/include/soc/sprd/chip_x20/__sc2723s_regulator_map.h b/include/soc/sprd/chip_x20/__sc2723s_regulator_map.h
new file mode 100755
index 00000000..5ef090a1
--- /dev/null
+++ b/include/soc/sprd/chip_x20/__sc2723s_regulator_map.h
@@ -0,0 +1,174 @@
+/*
+ * Copyright (C) 2013 Spreadtrum Communications Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *************************************************
+ * Automatically generated C header: do not edit *
+ *************************************************
+ */
+
+/*
+ * Regulator (0)Name, Regulator (1)Type, Power Off (2)Ctrl and (3)Bit, Power On (4)Ctrl and (5)Bit, Sleep (6)Ctrl and (7)Bit,
+ * Voltage Trimming (8)Ctrl and (9)Bits, Calibration (10)Ctrl and (11)Bits,
+ * Voltage (12)Default, Voltage (13)Ctrl and (14)Bits, Voltage Select (15)Count and Voltage (16)List[ ... ...]
+ */
+
+#if 0
+	/* BONDOPT6 = 0 --> 45nm process */
+    SCI_REGU_REG(vddcore, 2, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(9), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(9), 0, 0,
+	ANA_REG_GLB_DCDC_CORE_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(16)|BIT(18)|BIT(19),
+	1100, ANA_REG_GLB_DCDC_CORE_ADI, BIT(5)|BIT(6)|BIT(7), 8, 1100, 700, 800, 900, 1000, 650, 1200, 1300);
+
+    SCI_REGU_REG(vddarm, 2, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(10), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(10), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(9),
+	ANA_REG_GLB_DCDC_ARM_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(17)|BIT(18)|BIT(19),
+	1100, ANA_REG_GLB_DCDC_ARM_ADI, BIT(5)|BIT(6)|BIT(7), 8, 1100, 700, 800, 900, 1000, 650, 1200, 1300);
+#else
+	/* BONDOPT6 = 1 --> 28nm process */
+	SCI_REGU_REG(vddcore, 2, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(9), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(9), 0, 0,
+	ANA_REG_GLB_DCDC_CORE_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(16)|BIT(18)|BIT(19),
+	900, ANA_REG_GLB_MP_MISC_CTRL, BIT(3)|BIT(4)|BIT(5), 8, 1100, 700, 800, 900, 1000, 650, 1200, 1300);
+
+	SCI_REGU_REG(vddarm, 2, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(10), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(10), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(9),
+	ANA_REG_GLB_DCDC_ARM_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(17)|BIT(18)|BIT(19),
+	900, ANA_REG_GLB_MP_MISC_CTRL, BIT(6)|BIT(7)|BIT(8), 8, 1100, 700, 800, 900, 1000, 650, 1200, 1300);
+#endif
+
+    SCI_REGU_REG(vddmem, 2, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(11), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(11), 0, 0,
+	ANA_REG_GLB_DCDC_MEM_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(16)|BIT(17)|BIT(18)|BIT(19),
+	1200, ANA_REG_GLB_DCDC_MEM_ADI, BIT(5), 2, 1200, 1250);
+
+    SCI_REGU_REG(vddgen, 2, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(12), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(12), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(12),
+	ANA_REG_GLB_DCDC_GEN_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(20),
+	2400, ANA_REG_GLB_DCDC_GEN_ADI, BIT(5)|BIT(6)|BIT(7), 8, 2200, 1800, 1900, 2000, 2100, 2300, 2400, 2500);
+
+    SCI_REGU_REG(vddwpa, 2, ANA_REG_GLB_LDO_PD_CTRL, BIT(11), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL0, BIT(11),
+	ANA_REG_GLB_DCDC_WPA_ADI, BIT(0)|BIT(1)|BIT(2), ANA_REG_GLB_LDO_CAL_SEL, BIT(16)|BIT(20),
+	0, 0, 0, 0);
+
+#if 1
+	/* BONDOPT4 = 0 */
+    SCI_REGU_REG(vddwrf, 2, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(13), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(13), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(10),
+	ANA_REG_GLB_DCDC_WRF_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(17)|BIT(20),
+	1500, ANA_REG_GLB_DCDC_WRF_ADI, BIT(5)|BIT(6), 4, 1300, 1400, 1500, 1600);
+#else
+	/* BONDOPT4 = 1 */
+	SCI_REGU_REG(vddwrf, 2, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(13), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(13), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(10),
+	ANA_REG_GLB_DCDC_WRF_ADI, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(17)|BIT(20),
+	2800, ANA_REG_GLB_DCDC_WRF_ADI, BIT(5)|BIT(6), 4, 2600, 2700, 2800, 2900);
+#endif
+
+    SCI_REGU_REG(vdd18, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(1), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(1), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(0),
+	ANA_REG_GLB_LDO_CAL_CTRL0, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(6)|BIT(7)|BIT(17)|BIT(18)|BIT(20),
+	1800, ANA_REG_GLB_LDO_V_CTRL0, BIT(0)|BIT(1), 4, 1500, 1800, 1300, 1200);
+
+    SCI_REGU_REG(vdd28, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(2), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(2), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(1),
+	ANA_REG_GLB_LDO_CAL_CTRL0, BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_LDO_CAL_SEL, BIT(8)|BIT(10)|BIT(16)|BIT(18)|BIT(20),
+	0, ANA_REG_GLB_LDO_V_CTRL0, BIT(2)|BIT(3), 4, 2800, 3000, 2650, 1800);
+
+#if 0
+	/* BONDOPT6 = 0 --> 45nm process */
+    SCI_REGU_REG(vdd25, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(3), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(3), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(2),
+	ANA_REG_GLB_LDO_CAL_CTRL0, BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_CAL_SEL, BIT(9)|BIT(10)|BIT(16)|BIT(18)|BIT(20),
+	2500, ANA_REG_GLB_LDO_V_CTRL0, BIT(4)|BIT(5), 4, 2500, 2750, 3000, 2900);
+#else
+	/* BONDOPT6 = 1 --> 28nm process */
+	SCI_REGU_REG(vdd25, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(3), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(3), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(2),
+	ANA_REG_GLB_LDO_CAL_CTRL0, BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_CAL_SEL, BIT(9)|BIT(10)|BIT(16)|BIT(18)|BIT(20),
+	1800, ANA_REG_GLB_MP_MISC_CTRL, BIT(9)|BIT(10), 4, 2500, 2750, 1800, 1900);
+#endif
+
+    SCI_REGU_REG(vddrf0, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(4), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(4), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(3),
+	ANA_REG_GLB_LDO_CAL_CTRL1, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(11)|BIT(13)|BIT(16)|BIT(17)|BIT(18)|BIT(20),
+	2850, ANA_REG_GLB_LDO_V_CTRL0, BIT(6)|BIT(7), 4, 2850, 2950, 2500, 1800);
+
+#if 1
+	/* BONDOPT4 = 0 */
+    SCI_REGU_REG(vddrf1, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(5), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(5), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(4),
+	ANA_REG_GLB_LDO_CAL_CTRL1, BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_LDO_CAL_SEL, BIT(13)|BIT(16)|BIT(17)|BIT(18)|BIT(20),
+	1200, ANA_REG_GLB_MP_MISC_CTRL, BIT(11)|BIT(12), 4, 2850, 1800, 1500, 1200);
+#else
+	/* BONDOPT4 = 1 */
+	SCI_REGU_REG(vddrf1, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(5), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(5), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(4),
+	ANA_REG_GLB_LDO_CAL_CTRL1, BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_LDO_CAL_SEL, BIT(13)|BIT(16)|BIT(17)|BIT(18)|BIT(20),
+	2850, ANA_REG_GLB_LDO_V_CTRL0, BIT(8)|BIT(9), 4, 2850, 1800, 1500, 1200);
+#endif
+
+    SCI_REGU_REG(vddrf2, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(6), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(6), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(5),
+	ANA_REG_GLB_LDO_CAL_CTRL1, BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_CAL_SEL, BIT(11)|BIT(12)|BIT(16)|BIT(17)|BIT(18)|BIT(20),
+	2850, ANA_REG_GLB_LDO_V_CTRL0, BIT(10)|BIT(11), 4, 2850, 1800, 1500, 1200);
+
+    SCI_REGU_REG(vddemmcio, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(7), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(7), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(6),
+	ANA_REG_GLB_LDO_CAL_CTRL2, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(7)|BIT(17)|BIT(18)|BIT(20),
+	1800, ANA_REG_GLB_LDO_V_CTRL0, BIT(12)|BIT(13), 4, 1500, 1800, 1300, 1200);
+
+    SCI_REGU_REG(vddemmccore, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(8), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(8), ANA_REG_GLB_LDO_SLP_CTRL0, BIT(7),
+	ANA_REG_GLB_LDO_CAL_CTRL2, BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_LDO_CAL_SEL, BIT(10)|BIT(16)|BIT(18)|BIT(20),
+	3000, ANA_REG_GLB_LDO_V_CTRL0, BIT(14)|BIT(15), 4, 2800, 3000, 2500, 1800);
+
+    SCI_REGU_REG(avdd18, 0, ANA_REG_GLB_LDO_DCDC_PD_RTCSET, BIT(15), ANA_REG_GLB_LDO_DCDC_PD_RTCCLR, BIT(15), ANA_REG_GLB_LDO_SLP_CTRL1, BIT(0),
+	ANA_REG_GLB_LDO_CAL_CTRL3, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(5)|BIT(7)|BIT(17)|BIT(18)|BIT(20),
+	1800, ANA_REG_GLB_LDO_V_CTRL1, BIT(0)|BIT(1), 4, 1500, 1800, 1300, 1200);
+
+    SCI_REGU_REG(vddsd, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(1), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(1),
+	ANA_REG_GLB_LDO_CAL_CTRL3, BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_LDO_CAL_SEL, BIT(11)|BIT(16)|BIT(17)|BIT(18)|BIT(20),
+	2800, ANA_REG_GLB_LDO_V_CTRL1, BIT(2)|BIT(3), 4, 2800, 3000, 2500, 1800);
+
+    SCI_REGU_REG(vddsim0, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(2), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(2),
+	ANA_REG_GLB_LDO_CAL_CTRL4, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(9)|BIT(16)|BIT(18)|BIT(20),
+	1800, ANA_REG_GLB_LDO_V_CTRL1, BIT(4)|BIT(5), 4, 1800, 2900, 3000, 3100);
+
+    SCI_REGU_REG(vddsim1, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(3), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(3),
+	ANA_REG_GLB_LDO_CAL_CTRL4, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(9)|BIT(16)|BIT(18)|BIT(20),
+	1800, ANA_REG_GLB_LDO_V_CTRL1, BIT(6)|BIT(7), 4, 1800, 2900, 3000, 3100);
+
+    SCI_REGU_REG(vddsim2, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(4), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(4),
+	ANA_REG_GLB_LDO_CAL_CTRL4, BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_LDO_CAL_SEL, BIT(8)|BIT(9)|BIT(16)|BIT(18)|BIT(20),
+	1800, ANA_REG_GLB_LDO_V_CTRL1, BIT(8)|BIT(9), 4, 2800, 3000, 2500, 1800);
+
+    SCI_REGU_REG(vddcama, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(5), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(5),
+	ANA_REG_GLB_LDO_CAL_CTRL4, BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_CAL_SEL, BIT(12)|BIT(16)|BIT(17)|BIT(18)|BIT(20),
+	2800, ANA_REG_GLB_LDO_V_CTRL2, BIT(0)|BIT(1), 4, 2800, 3000, 2500, 1800);
+
+    SCI_REGU_REG(vddcamd, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(6), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(6),
+	ANA_REG_GLB_LDO_CAL_CTRL5, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(5)|BIT(6)|BIT(17)|BIT(18)|BIT(20),
+	1500, ANA_REG_GLB_LDO_V_CTRL2, BIT(2)|BIT(3), 4, 1500, 1800, 1300, 1200);
+
+#ifdef CONFIG_REGULATOR_SUPPORT_CAMIO_1200MV
+	SCI_REGU_REG(vddcamio, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(7), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(7),
+	ANA_REG_GLB_LDO_CAL_CTRL5, BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_LDO_CAL_SEL, BIT(5)|BIT(17)|BIT(18)|BIT(20),
+	1200, ANA_REG_GLB_LDO_V_CTRL2, BIT(4)|BIT(5), 4, 1100, 1200, 1300, 1600);
+#else
+    SCI_REGU_REG(vddcamio, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(7), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(7),
+	ANA_REG_GLB_LDO_CAL_CTRL5, BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9), ANA_REG_GLB_LDO_CAL_SEL, BIT(5)|BIT(17)|BIT(18)|BIT(20),
+	1800, ANA_REG_GLB_LDO_V_CTRL2, BIT(4)|BIT(5), 4, 1500, 1800, 2500, 2800);
+#endif
+
+    SCI_REGU_REG(vddcammot, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(8), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(8),
+	ANA_REG_GLB_LDO_CAL_CTRL5, BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_CAL_SEL, BIT(12)|BIT(13)|BIT(16)|BIT(17)|BIT(18)|BIT(20),
+	2800, ANA_REG_GLB_LDO_V_CTRL2, BIT(6)|BIT(7), 4, 3000, 3300, 2800, 1800);
+
+    SCI_REGU_REG(vddusb, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(9), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(9),
+	ANA_REG_GLB_LDO_CAL_CTRL2, BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14), ANA_REG_GLB_LDO_CAL_SEL, BIT(8)|BIT(9)|BIT(10)|BIT(16)|BIT(18)|BIT(20),
+	3300, ANA_REG_GLB_LDO_V_CTRL2, BIT(8)|BIT(9), 4, 3300, 3400, 3200, 3100);
+
+    SCI_REGU_REG(vddclsg, 0, ANA_REG_GLB_LDO_PD_CTRL, BIT(10), 0, 0, ANA_REG_GLB_LDO_SLP_CTRL1, BIT(10),
+	ANA_REG_GLB_LDO_CAL_CTRL6, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4), ANA_REG_GLB_LDO_CAL_SEL, BIT(6)|BIT(17)|BIT(18)|BIT(20),
+	0, ANA_REG_GLB_LDO_V_CTRL2, BIT(10)|BIT(11), 4, 1500, 1800, 1300, 1200);
+
+    SCI_REGU_REG(chg_pump, 0, ANA_REG_GLB_CHGR_CTRL2, BIT(8), 0, 0, 0, 0,
+	ANA_REG_GLB_CHGR_CTRL2, BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13), 0, 0,
+	5000, ANA_REG_GLB_CHGR_CTRL0, BIT(2)|BIT(3), 4, 5000, 5200, 5300, 4800);
+
+    SCI_REGU_REG(led_flash, 4, 0, 0, ANA_REG_GLB_FLASH_CTRL, BIT(15), 0, 0,
+	ANA_REG_GLB_FLASH_CTRL, BIT(4)|BIT(5)|BIT(6), 0, 0,
+	4000, ANA_REG_GLB_FLASH_CTRL, BIT(0)|BIT(1)|BIT(2)|BIT(3), 0);
+
diff --git a/include/soc/sprd/chip_x20/dram_phy_28nm.h b/include/soc/sprd/chip_x20/dram_phy_28nm.h
new file mode 100644
index 00000000..8fce6e9f
--- /dev/null
+++ b/include/soc/sprd/chip_x20/dram_phy_28nm.h
@@ -0,0 +1,487 @@
+#ifndef _DRAM_PHY_28NM_H_
+#define _DRAM_PHY_28NM_H_
+
+#define __LPDDR2_BL__	8	/*4,8,16*/
+
+#define NS2CLK_T(ns,clk)	(((clk)*(ns)+9999)/10000)
+#define MAX(x,y)			(((x) > (y)) ? (x) : (y))
+
+#ifndef BIT
+#define BIT(x)				(1 << (x))
+#endif
+
+typedef enum
+{
+	/*lpddr1 type*/
+	DRAM_LPDDR1		= 0x000,
+	/*lpddr2 type*/
+	DRAM_LPDDR2		= 0x100,
+	/*lpddr3 type*/
+	DRAM_LPDDR3		= 0x200,
+	/*ddr2 type*/
+	DRAM_DDR2		= 0x300,
+	/*ddr3 type*/
+	DRAM_DDR3		= 0x400,
+}DRAM_TYPE_E;
+
+typedef enum{
+	CLK_24MHZ	= 24,
+	CLK_26MHZ	= 26,
+	CLK_38_4MHZ	= 38,
+	CLK_48MHZ	= 48,
+	CLK_64MHZ	= 64,
+	CLK_76_8MHZ	= 77,
+	CLK_96MHZ	= 96,
+	CLK_100MHZ	= 100,
+	CLK_153_6MHZ	= 154,
+	CLK_150MHZ	= 150,
+	CLK_166MHZ	= 166,
+	CLK_192MHZ	= 192,
+	CLK_200MHZ	= 200,
+	CLK_250MHZ	= 250,
+	CLK_267MHZ	= 267,
+	CLK_300MHZ	= 300,
+	CLK_332MHZ	= 332,
+	CLK_333MHZ	= 333,
+	CLK_384MHZ	= 384,
+	CLK_400MHZ	= 400,
+	CLK_427MHZ	= 427,
+	CLK_450MHZ	= 450,
+	CLK_464MHZ	= 464,
+	CLK_466MHZ	= 466,
+	CLK_467MHZ	= 467,
+	CLK_500MHZ	= 500,
+	CLK_525MHZ	= 525,
+	CLK_533MHZ	= 533,
+	CLK_537MHZ	= 537,
+	CLK_540MHZ	= 540,
+	CLK_550MHZ	= 550,
+	CLK_800MHZ	= 800,
+	CLK_1000MHZ	= 1000,
+	EMC_CLK_400MHZ	= 400,
+	EMC_CLK_450MHZ	= 450,
+	EMC_CLK_500MHZ	= 500
+}CLK_TYPE_E;
+
+typedef enum
+{
+	CAP_1CS_2G_X32,
+	CAP_1CS_4G_X32,
+	CAP_2CS_2G_X32,
+	CAP_2CS_3G_X32,
+	CAP_2CS_4G_X32,
+	CAP_2CS_5G_X32,
+	CAP_2CS_6G_X32,
+	CAP_2CS_8G_X32,
+	CAP_2CS_12G_X32,
+	CAP_2CS_16G_X32,
+	CAP_1CS_2G_X8_4P,
+	CAP_1CS_4G_X16_2P
+}DRAM_CAP_SIZE_E;
+
+typedef enum
+{
+	DRAM_BT_SEQ = 0, //burst type = sequential(default)
+	DRAM_BT_INTER= 1 //burst type = interleaved
+}DRAM_BURSTTYPE_E;
+
+typedef enum
+{
+	DRAM_WRAP   = 0, //warp mode
+	DRAM_NOWRAP = 1  //no warp mode
+}DRAM_WC_E;
+
+typedef enum
+{
+/*Driver strength for lpddr1*/
+	LPDDR1_DS_FULL,
+	LPDDR1_DS_HALF,
+	LPDDR1_DS_QUARTER,
+	LPDDR1_DS_OCTANT,
+	LPDDR1_DS_THREE_QUATERS,
+/*Driver strength for lpddr2*/
+	LPDDR2_DS_34R3 = 0x01,
+	LPDDR2_DS_40R  = 0x02,
+	LPDDR2_DS_48R  = 0x03,
+	LPDDR2_DS_60R  = 0x04,
+	LPDDR2_DS_68R6 = 0x05,
+	LPDDR2_DS_80R  = 0x06,
+	LPDDR2_DS_120R = 0x07,
+/*Driver strength for ddr3*/
+	DDR3_DS_40R    = 0x00,
+	DDR3_DS_34R3   = 0x01
+}MEM_IODS_E;
+
+typedef enum
+{
+	UMCTL2_PORT_MIN     = 0,
+	UMCTL2_PORT_AP      = 0,
+	UMCTL2_PORT_MM      = 1,
+	UMCTL2_PORT_GPU     = 2,
+	UMCTL2_PORT_CP2_P0  = 3,
+	UMCTL2_PORT_CP1     = 4,
+	UMCTL2_PORT_AP_MTX  = 5,
+	UMCTL2_PORT_CP0     = 6,
+	UMCTL2_PORT_CP2_P1  = 7,
+	UMCTL2_PORT_CP0_MTX = 8,	
+	UMCTL2_PORT_DSP     = 9,
+	UMCTL2_PORT_MAX     = 10
+}UMCTL2_PORT_ID_E;
+
+typedef enum
+{
+	OPERATION_MODE_INIT   = 0x0,
+	OPERATION_MODE_NORMAL = 0x1,
+	OPERATION_MODE_PD     = 0x2,
+	OPERATION_MODE_SR     = 0x3,
+	OPERATION_MODE_DPD    = 0x4
+}OPERATION_MODE_E;
+
+typedef struct
+{
+	unsigned int tREFI;		/*average refresh interval time between each row normal=7800ns*/
+	unsigned int tMRD;		/*lpddr1:set lpddr2:sbz ddr3:set*/
+	unsigned int tRAS;		/*lpddr1:set lpddr2:set ddr3:set*/
+	unsigned int tRC;		/*lpddr1:set lpddr2:set ddr3:set*/
+	unsigned int tRFC;		/*lpddr1:set lpddr2:set ddr3:set*/
+	unsigned int tRCD;		/*lpddr1:set lpddr2:set ddr3:set*/
+	unsigned int tRP;		/*lpddr1:set lpddr2:set ddr3:set*/
+	unsigned int tRRD;		/*lpddr1:set lpddr2:set ddr3:set*/
+	unsigned int tWR;		/*lpddr1:set lpddr2:set ddr3:set*/
+	unsigned int tWTR;		/*lpddr1:set lpddr2:set ddr3:set*/
+	unsigned int tXSR;		/*lpddr1:set lpddr2:set ddr3:sbz*/
+	unsigned int tXP;		/*lpddr1:set lpddr2:set ddr3:set*/
+	unsigned int tCKE;		/*lpddr1:set lpddr2:set ddr3:set*/
+	unsigned int tRFCab;		/*lpddr1:sbz lpddr2:set ddr3:sbz*/
+	unsigned int tRFCpb;		/*lpddr1:sbz lpddr2:set ddr3:sbz*/
+	unsigned int tZQINIT;		/*lpddr1:sbz lpddr2:set ddr3:set*/
+	unsigned int tZQCL;		/*lpddr1:sbz lpddr2:set ddr3:sbz*/
+	unsigned int tZQCS;		/*lpddr1:sbz lpddr2:set ddr3:set*/
+	unsigned int tZQreset;		/*lpddr1:sbz lpddr2:set ddr3:sbz*/
+	unsigned int tZQoper;		/*lpddr1:sbz lpddr2:sbz ddr3:set*/
+	unsigned int tCKESR;		/*lpddr1:sbz lpddr2:set ddr3:sbz*/
+	unsigned int tCCD;		/*lpddr1:sbz lpddr2:set ddr3:set*/
+	unsigned int tRTP;		/*lpddr1:sbz lpddr2:set ddr3:set*/
+	unsigned int tFAW;		/*lpddr1:sbz lpddr2:set ddr3:set*/
+	unsigned int tDPD;		/*lpddr1:sbz lpddr2:set ddr3:sbz*/
+	unsigned int tDQSCK;		/*lpddr1:sbz lpddr2:set ddr3:set*/
+	unsigned int tDQSCKmax;		/*lpddr1:sbz lpddr2:set ddr3:sbz*/
+	unsigned int tMRW;		/*lpddr1:sbz lpddr2:set ddr3:sbz*/
+	unsigned int tMRR;		/*lpddr1:sbz lpddr2:set ddr3:sbz*/
+	unsigned int tDLLK;		/*lpddr1:sbz lpddr2:sbz ddr3:set*/
+	unsigned int tMOD;		/*lpddr1:sbz lpddr2:sbz ddr3:set*/
+	unsigned int tXS;		/*lpddr1:sbz lpddr2:sbz ddr3:set*/
+	unsigned int tCKSRE;		/*lpddr1:sbz lpddr2:sbz ddr3:set*/
+	unsigned int tCKSRX;		/*lpddr1:sbz lpddr2:sbz ddr3:set*/
+	unsigned int cntRDMode;
+	unsigned int cntRDDLY;
+	unsigned int cntDQSGX;
+	unsigned int cntPGWAIT;
+	unsigned int cntZQDIV;
+}DDR_ACTIMING_T;
+
+typedef struct
+{
+	DRAM_TYPE_E 	dram_type;
+	DRAM_CAP_SIZE_E	cap;
+	unsigned int	cs_num;		/*ranks number*/
+	unsigned int	bank_num;	/*banks number*/
+	unsigned int	io_width;	/*bus width*/
+	unsigned int	bt;		/*burst type*/
+	unsigned int	wc;		/*wrap control*/
+	unsigned int	bl;		/*burst length*/
+	unsigned int	rl;		/*read cas latency*/
+	unsigned int	wl;		/*write cas latency*/
+	unsigned int	al;		/*ddr2 ddr3 only Posted CAS additive latency*/
+	DDR_ACTIMING_T	*ac_timing;
+	DDR_ACTIMING_T	*native_ac_timing;
+}DRAM_INFO_T;
+
+typedef struct
+{
+	volatile unsigned int umctl_mstr;	/* 0x0000 master register*/
+	volatile unsigned int umctl_stat;	/* 0x0004 operating mode status*/
+	volatile unsigned int umctl_resv0[2];	/* 0x0008 ~ 0x000c*/
+	volatile unsigned int umctl_mrctrl[2];	/* 0x0010 ~ 0x0014 mode register control*/
+	volatile unsigned int umctl_mrstat;	/* 0x0018 mode register status*/
+	volatile unsigned int umctl_resv1;	/* 0x001c */
+	volatile unsigned int umctl_derateen;	/* 0x0020 temperature derate enable*/
+	volatile unsigned int umctl_derateint;	/* 0x0024 temperature derate interval*/
+	volatile unsigned int umctl_resv2[2];	/* 0x0028 ~ 0x002c */
+	volatile unsigned int umctl_pwrctl;	/* 0x0030 low power control*/
+	volatile unsigned int umctl_pwrtmg;	/* 0x0034 low power timing*/
+	volatile unsigned int umctl_hwlpctl;	/* 0x0038 hardware low power control*/
+	volatile unsigned int umctl_resv3[5];	/* 0x003c ~ 0x004c */
+	volatile unsigned int umctl_rfshctl[3];	/* 0x0050 ~ 0x0058 refresh control*/
+	volatile unsigned int umctl_resv4;	/* 0x005c */
+	volatile unsigned int umctl_rfshctl3;	/* 0x0060 refresh control*/
+	volatile unsigned int umctl_rfshtmg;	/* 0x0064 refresh timing*/
+	volatile unsigned int umctl_resv5[2];	/* 0x0068 ~ 0x006c */
+	volatile unsigned int umctl_ecccfg[2];	/* 0x0070 ~ 0x0074 ecc configruation*/
+	volatile unsigned int umctl_eccstat;	/* 0x0078 ecc status*/
+	volatile unsigned int umctl_eccclr;	/* 0x007c ecc clear*/
+	volatile unsigned int umctl_eccerrcnt;	/* 0x0080 ecc error count*/
+	volatile unsigned int umctl_ecccaddr[2];/* 0x0084 ~ 0x0088 ecc corrected error address*/
+	volatile unsigned int umctl_ecccsyn[3];	/* 0x008c ~ 0x0094 ecc corrected syndrome*/
+	volatile unsigned int umctl_eccbitmask[3];	/* 0x0098 ~ 0x00a0 ecc corrected data bit mask*/
+	volatile unsigned int umctl_eccuaddr[2];/* 0x00a4 ~ 0x00a8 ecc unorrected error address*/
+	volatile unsigned int umctl_eccusyn[3];	/* 0x00ac ~ 0x00b4 ecc uncorrected syndrome*/
+	volatile unsigned int umctl_eccpoisonaddr[2];	/* 0x00b8 ~ 0x00bc ecc data poisoning address*/
+	volatile unsigned int umctl_parctl;	/* 0x00c0 parity control*/
+	volatile unsigned int umctl_parstat;	/* 0x00c4 parity status*/
+	volatile unsigned int umctl_resv6[2];	/* 0x00c8 ~ 0x00cc */
+	volatile unsigned int umctl_init[8];	/* 0x00d0 ~ 0x00ec sdram initialization*/
+	volatile unsigned int umctl_dimmctl;	/* 0x00f0 dimm control*/
+	volatile unsigned int umctl_rankctl;	/* 0x00f4 rank control*/
+	volatile unsigned int umctl_resv7[2];	/* 0x00f8 ~ 0x00fc*/
+	volatile unsigned int umctl_dramtmg[12];/* 0x0100 ~ 0x012c sdram timing*/
+	volatile unsigned int umctl_resv8[20];	/* 0x0130 ~ 0x017c */
+	volatile unsigned int umctl_zqctl[3];	/* 0x0180 ~ 0x0188 zq control*/
+	volatile unsigned int umctl_zqstat;	/* 0x018c zq status*/
+	volatile unsigned int umctl_dfitmg[2];	/* 0x0190 ~ 0x0194 dfi timing*/
+	volatile unsigned int umctl_dfilpcfg[2];/* 0x0198 ~ 0x019c dfi low power configruation*/
+	volatile unsigned int umctl_dfiupd[4];	/* 0x01a0 ~ 0x01ac dfi update*/
+	volatile unsigned int umctl_dfimisc;	/* 0x01b0 dfi miscellaneous control*/
+	volatile unsigned int umctl_resv9[3];	/* 0x01b4 ~ 0x01bc */
+	volatile unsigned int umctl_dbictl;	/* 0x01c0 dm/dbi control*/
+	volatile unsigned int umctl_resv10[3];	/* 0x01c4 ~ 0x01cc */
+	volatile unsigned int umctl_trainctl[3];/* 0x01d0 ~ 0x01d8 phy eval training control*/
+	volatile unsigned int umctl_trainstat;	/* 0x01dc phy eval training status */	
+	volatile unsigned int umctl_resv11[8];	/* 0x01e0 ~ 0x01fc */
+	volatile unsigned int umctl_addrmap[9];	/* 0x0200 ~ 0x0220 address map */
+	volatile unsigned int umctl_resv12[7];	/* 0x0224 ~ 0x023c */
+	volatile unsigned int umctl_odtcfg;	/* 0x0240 odt configruation */
+	volatile unsigned int umctl_odtmap;	/* 0x0244 odt/rank map */	
+	volatile unsigned int umctl_resv13[2];	/* 0x0248 ~ 0x024c */
+	volatile unsigned int umctl_sched;	/* 0x0250 scheduler control */
+	volatile unsigned int umctl_resv14;	/* 0x0254 */
+	volatile unsigned int umctl_perfhpr[2];	/* 0x0258 ~ 0x025c high priority read*/
+	volatile unsigned int umctl_perflpr[2];	/* 0x0260 ~ 0x0264 low priority read */
+	volatile unsigned int umctl_perfwr[2];	/* 0x0268 ~ 0x026c write cam */
+	volatile unsigned int umctl_resv15[36];	/* 0x0270 ~ 0x02fc */
+	volatile unsigned int umctl_dbg[2];	/* 0x0300 ~ 0x0304 debug*/
+	volatile unsigned int umctl_dbgcam;	/* 0x0308 cam debug*/
+	volatile unsigned int umctl_dbgcmd;	/* 0x030c cam debug*/
+	volatile unsigned int umctl_dbgstat;	/* 0x0310 cam debug*/
+	volatile unsigned int umctl_resv16[58];	/* 0x0314 ~ 0x03f8 */
+	volatile unsigned int umctl_pstat;	/* 0x03fc */
+	volatile unsigned int umctl_pccfg;	/* 0x0400 port common configruation*/
+	volatile unsigned int umctl_pcfgr0;	/* 0x0404 port 0 configruation read */
+	volatile unsigned int umctl_pcfgw0;	/* 0x0408 port 0 configruation write*/
+	volatile unsigned int umctl_pcfgc0;	/* 0x040c port 0 common configruation*/
+	volatile unsigned int umctl_pcfgidmaskch0_0;	/* 0x0410 channel 0 port 0 configruation*/
+	volatile unsigned int umctl_pcfgidvaluech0_0;	/* 0x0414 channel 0 port 0 configruation*/
+	volatile unsigned int umctl_resv17[30];	/* 0x0418 ~ 0x048c */
+	volatile unsigned int umctl_pctrl0;	/* 0x0490 port control */	
+}DMC_UMCTL_REG_INFO_T,*DMC_UMCTL_REG_INFO_PTR_T;
+
+/* UMCTL STAT [0x0004] */
+#define BIT_STAT_SELFREF_TYPE				( BIT(5) | BIT(4) )
+#define BIT_STAT_OP_MODE					( BIT(2) | BIT(1) | BIT(0) )
+
+/* UMCTL low power control [0x0030] */
+#define BIT_PWRCTL_SELFREF_SW				( BIT(5) )
+#define BIT_PWRCTL_MPSM_EN					( BIT(4) )
+#define BIT_PWRCTL_DFICLK_DIS				( BIT(3) )
+#define BIT_PWRCTL_DEEPPD_EN				( BIT(2) )
+#define BIT_PWRCTL_PD_EN						( BIT(1) )
+#define BIT_PWRCTL_SELFREF_EN				( BIT(0) )
+
+/* UMCTL DBG1 */
+#define BIT_DBG1_DIS_DQ						( BIT(0) )
+
+/* UMCTL DBGCAM [0x0308] */
+#define BIT_DBGCAM_WR_PP_EPTY				( BIT(29) )
+#define BIT_DBGCAM_RD_PP_EPTY				( BIT(28) )
+#define BIT_DBGCAM_WR_Q_EPTY				( BIT(26) )
+#define BIT_DBGCAM_RD_Q_EPTY				( BIT(25) )
+#define BIT_DBGCAM_STALL						( BIT(24) )
+
+/* DFI_MISC */
+#define BIT_DFIMISC_PHY_DBI_MODE				( BIT(1) )
+#define BIT_DFIMISC_DFI_COMP_EN				( BIT(0) )
+
+/* RFSHCTL3 [0x0060] */
+#define BIT_RFSHCTL3_RF_MODE				( BIT(6) | BIT(5) | BIT(4) )
+#define BIT_RFSHCTL3_RF_LL					( BIT(1) )
+#define BIT_RFSHCTL3_DIS_AUTO_RF				( BIT(0) )
+
+typedef struct
+{
+	volatile unsigned int publ_ridr;	/* 0x0000 revision identification*/
+	volatile unsigned int publ_pir;		/* 0x0004 phy initialization*/
+	volatile unsigned int publ_pgcr[4];	/* 0x0008 ~ 0x0014 phy general configruation*/
+	volatile unsigned int publ_pgsr[2];	/* 0x0018 ~ 0x001c phy general status*/
+	volatile unsigned int publ_pllcr;	/* 0x0020 pll control*/
+	volatile unsigned int publ_ptr[5];	/* 0x0024 ~ 0x0034 phy timing*/
+	volatile unsigned int publ_acmdlr;	/* 0x0038 ac master delay line*/
+	volatile unsigned int publ_aclcdlr;	/* 0x003c ac local calibrated delay line*/
+	volatile unsigned int publ_acbdlr[10];	/* 0x0040 ~ 0x0064 ac bit delay line*/
+	volatile unsigned int publ_aciocr[6];	/* 0x0068 ~ 0x007c ac i/o configruation*/
+	volatile unsigned int publ_dxccr;	/* 0x0080 datx8 common configruation*/
+	volatile unsigned int publ_dsgcr;	/* 0x0084 datx8 system general configruation*/
+	volatile unsigned int publ_dcr;		/* 0x0088 dram configruation*/
+	volatile unsigned int publ_dtpr[4];	/* 0x008c ~ 0x0098 dram timing parameters*/
+	volatile unsigned int publ_mr[4];	/* 0x009c ~ 0x00a8 mode register*/
+	volatile unsigned int publ_odtcr;	/* 0x00ac odt configruation*/
+	volatile unsigned int publ_dtcr;	/* 0x00b0 data training configruation*/
+	volatile unsigned int publ_dtar[4];	/* 0x00b4 ~ 0x00c0 data training address*/
+	volatile unsigned int publ_dtdr[2];	/* 0x00c4 ~ 0x00c8 data training data*/	
+	volatile unsigned int publ_dtedr[2];	/* 0x00cc ~ 0x00d0 data training address */
+	volatile unsigned int publ_rdimmgcr[2];	/* 0x00d4 ~ 0x00d8 rdimm general configruation*/
+	volatile unsigned int publ_rdimmcr[2];	/* 0x00dc ~ 0x00e0 rdimm control*/
+	volatile unsigned int publ_gpr[2];	/* 0x00e4 ~ 0x00e8 general purpose*/
+	volatile unsigned int publ_catr[2];	/* 0x00ec ~ 0x00f0 catr*/	
+	volatile unsigned int publ_dqsdr;	/* 0x00f4 dqs drift detection */
+	volatile unsigned int publ_dtmr[2];	/* 0x00f8 ~ 0x00fc data training mask*/
+	volatile unsigned int publ_resv0[32];	/* 0x0100 ~ 0x017c */
+	volatile unsigned int publ_dcuar;	/* 0x0180 DCU address*/
+	volatile unsigned int publ_dcudr;	/* 0x0184 DCU data*/
+	volatile unsigned int publ_dcurr;	/* 0x0188 DCU run*/
+	volatile unsigned int publ_dculr;	/* 0x018c DCU loop*/
+	volatile unsigned int publ_dcugcr;	/* 0x0190 DCU general configruation*/
+	volatile unsigned int publ_dcutpr;	/* 0x0194 DCU timing parameters*/
+	volatile unsigned int publ_dcusr[2];	/* 0x0198 ~ 0x019c DCU status*/
+	volatile unsigned int publ_resv1[8];	/* 0x01a0 ~ 0x01bc */
+	volatile unsigned int publ_bistrr;	/* 0x01c0 BIST run*/
+	volatile unsigned int publ_bistwcr;	/* 0x01c4 BIST word count*/
+	volatile unsigned int publ_bistmskr[3];	/* 0x01c8 ~ 0x01d0 BIST mask*/
+	volatile unsigned int publ_bistlsr;	/* 0x01d4 BIST LFSR seed*/
+	volatile unsigned int publ_bistar[3];	/* 0x01d8 ~ 0x01e0 BIST address*/
+	volatile unsigned int publ_bistudpr;	/* 0x01e4 BIST User data pattern*/
+	volatile unsigned int publ_bistgsr;	/* 0x01e8 BIST general status*/
+	volatile unsigned int publ_bistwer;	/* 0x01ec BIST word error*/
+	volatile unsigned int publ_bistber[4];	/* 0x01f0 ~ 0x01fc BIST bit error*/
+	volatile unsigned int publ_bistwcsr;	/* 0x0200 BIST word count status*/
+	volatile unsigned int publ_bistfwr[3];	/* 0x0204 ~ 0x020c BIST fail word*/
+	volatile unsigned int publ_resv2[10];	/* 0x0210 ~ 0x0234 catr*/
+	volatile unsigned int publ_iovcr[2];	/* 0x0238 ~ 0x023c IO VREF control*/
+	volatile unsigned int publ_zqcr;	/* 0x0240 zq impedance control*/
+	volatile unsigned int publ_zq0pr;	/* 0x0244 zq impedance program*/
+	volatile unsigned int publ_zq0dr;	/* 0x0248 zq impedance data*/
+	volatile unsigned int publ_zq0sr;	/* 0x024c zq impedance status*/
+	volatile unsigned int publ_resv3;	/* 0x0250 */
+	volatile unsigned int publ_zq1pr;	/* 0x0254 zq impedance program*/
+	volatile unsigned int publ_zq1dr;	/* 0x0258 zq impedance data*/
+	volatile unsigned int publ_zq1sr;	/* 0x025c zq impedance status*/
+	volatile unsigned int publ_resv4;	/* 0x0260 */
+	volatile unsigned int publ_zq2pr;	/* 0x0264 zq impedance program*/
+	volatile unsigned int publ_zq2dr;	/* 0x0268 zq impedance data*/
+	volatile unsigned int publ_zq2sr;	/* 0x026c zq impedance status*/
+	volatile unsigned int publ_resv5;	/* 0x0270 */
+	volatile unsigned int publ_zq3pr;	/* 0x0274 zq impedance program*/
+	volatile unsigned int publ_zq3dr;	/* 0x0278 zq impedance data*/
+	volatile unsigned int publ_zq3sr;	/* 0x027c zq impedance status*/	
+	volatile unsigned int publ_dx0gcr[4];	/* 0x0280 ~ 0x028c datx8 general config*/
+	volatile unsigned int publ_dx0gsr[3];	/* 0x0290 ~ 0x0298 datx8 general status*/
+	volatile unsigned int publ_dx0bdlr[7];	/* 0x029c ~ 0x02b4 datx8 bit delay line*/
+	volatile unsigned int publ_dx0lcdlr[3];	/* 0x02b8 ~ 0x02c0 datx8 local cal*/
+	volatile unsigned int publ_dx0mdlr;	/* 0x02c4 datx8 master delay line*/
+	volatile unsigned int publ_dx0gtr;	/* 0x02c8 datx8 general timing*/
+	volatile unsigned int publ_resv6[13];	/* 0x02cc ~ 0x02fc */
+	volatile unsigned int publ_dx1gcr[4];	/* 0x0300 ~ 0x030c datx8 general config*/
+	volatile unsigned int publ_dx1gsr[3];	/* 0x0310 ~ 0x0318 datx8 general status*/
+	volatile unsigned int publ_dx1bdlr[7];	/* 0x031c ~ 0x0334 datx8 bit delay line*/
+	volatile unsigned int publ_dx1lcdlr[3];	/* 0x0338 ~ 0x0340 datx8 local cal*/
+	volatile unsigned int publ_dx1mdlr;	/* 0x0344 datx8 master delay line*/
+	volatile unsigned int publ_dx1gtr;	/* 0x0348 datx8 general timing*/
+	volatile unsigned int publ_resv7[13];	/* 0x034c ~ 0x037c */
+	volatile unsigned int publ_dx2gcr[4];	/* 0x0380 ~ 0x038c datx8 general config*/
+	volatile unsigned int publ_dx2gsr[3];	/* 0x0390 ~ 0x0398 datx8 general status*/
+	volatile unsigned int publ_dx2bdlr[7];	/* 0x039c ~ 0x03b4 datx8 bit delay line*/
+	volatile unsigned int publ_dx2lcdlr[3];	/* 0x03b8 ~ 0x03c0 datx8 local cal*/
+	volatile unsigned int publ_dx2mdlr;	/* 0x03c4 datx8 master delay line*/
+	volatile unsigned int publ_dx2gtr;	/* 0x03c8 datx8 general timing*/
+	volatile unsigned int publ_resv8[13];	/* 0x03cc ~ 0x03fc */
+	volatile unsigned int publ_dx3gcr[4];	/* 0x0400 ~ 0x040c datx8 general config*/
+	volatile unsigned int publ_dx3gsr[3];	/* 0x0410 ~ 0x0418 datx8 general status*/
+	volatile unsigned int publ_dx3bdlr[7];	/* 0x041c ~ 0x0434 datx8 bit delay line*/
+	volatile unsigned int publ_dx3lcdlr[3];	/* 0x0438 ~ 0x0440 datx8 local cal*/
+	volatile unsigned int publ_dx3mdlr;	/* 0x0444 datx8 master delay line*/
+	volatile unsigned int publ_dx3gtr;	/* 0x0448 datx8 general timing*/
+	volatile unsigned int publ_resv9[13];	/* 0x044c ~ 0x047c */
+	volatile unsigned int publ_dx4gcr[4];	/* 0x0480 ~ 0x048c datx8 general config*/
+	volatile unsigned int publ_dx4gsr[3];	/* 0x0490 ~ 0x0498 datx8 general status*/
+	volatile unsigned int publ_dx4bdlr[7];	/* 0x049c ~ 0x04b4 datx8 bit delay line*/
+	volatile unsigned int publ_dx4lcdlr[3];	/* 0x04b8 ~ 0x04c0 datx8 local cal*/
+	volatile unsigned int publ_dx4mdlr;	/* 0x04c4 datx8 master delay line*/
+	volatile unsigned int publ_dx4gtr;	/* 0x04c8 datx8 general timing*/
+	volatile unsigned int publ_resv10[13];	/* 0x04cc ~ 0x04fc */
+	volatile unsigned int publ_dx5gcr[4];	/* 0x0500 ~ 0x050c datx8 general config*/
+	volatile unsigned int publ_dx5gsr[3];	/* 0x0510 ~ 0x0518 datx8 general status*/
+	volatile unsigned int publ_dx5bdlr[7];	/* 0x051c ~ 0x0534 datx8 bit delay line*/
+	volatile unsigned int publ_dx5lcdlr[3];	/* 0x0538 ~ 0x0540 datx8 local cal*/
+	volatile unsigned int publ_dx5mdlr;	/* 0x0544 datx8 master delay line*/
+	volatile unsigned int publ_dx5gtr;	/* 0x0548 datx8 general timing*/
+	volatile unsigned int publ_resv11[13];	/* 0x054c ~ 0x057c */
+	volatile unsigned int publ_dx6gcr[4];	/* 0x0580 ~ 0x058c datx8 general config*/
+	volatile unsigned int publ_dx6gsr[3];	/* 0x0590 ~ 0x0598 datx8 general status*/
+	volatile unsigned int publ_dx6bdlr[7];	/* 0x059c ~ 0x05b4 datx8 bit delay line*/
+	volatile unsigned int publ_dx6lcdlr[3];	/* 0x05b8 ~ 0x05c0 datx8 local cal*/
+	volatile unsigned int publ_dx6mdlr;	/* 0x05c4 datx8 master delay line*/
+	volatile unsigned int publ_dx6gtr;	/* 0x05c8 datx8 general timing*/
+	volatile unsigned int publ_resv12[13];	/* 0x05cc ~ 0x05fc */
+	volatile unsigned int publ_dx7gcr[4];	/* 0x0600 ~ 0x060c datx8 general config*/
+	volatile unsigned int publ_dx7gsr[3];	/* 0x0610 ~ 0x0618 datx8 general status*/
+	volatile unsigned int publ_dx7bdlr[7];	/* 0x061c ~ 0x0634 datx8 bit delay line*/
+	volatile unsigned int publ_dx7lcdlr[3];	/* 0x0638 ~ 0x0640 datx8 local cal*/
+	volatile unsigned int publ_dx7mdlr;	/* 0x0644 datx8 master delay line*/
+	volatile unsigned int publ_dx7gtr;	/* 0x0648 datx8 general timing*/
+	volatile unsigned int publ_resv13[13];	/* 0x064c ~ 0x067c */
+	volatile unsigned int publ_dx8gcr[4];	/* 0x0680 ~ 0x068c datx8 general config*/
+	volatile unsigned int publ_dx8gsr[3];	/* 0x0690 ~ 0x0698 datx8 general status*/
+	volatile unsigned int publ_dx8bdlr[7];	/* 0x069c ~ 0x06b4 datx8 bit delay line*/
+	volatile unsigned int publ_dx8lcdlr[3];	/* 0x06b8 ~ 0x06c0 datx8 local cal*/
+	volatile unsigned int publ_dx8mdlr;	/* 0x06c4 datx8 master delay line*/
+	volatile unsigned int publ_dx8gtr;	/* 0x06c8 datx8 general timing*/
+	volatile unsigned int publ_resv14[13];	/* 0x06cc ~ 0x06fc */
+}DMC_PUBL_REG_INFO_T,*DMC_PUBL_REG_INFO_PTR_T;
+
+/* PUBL DSGCR */
+#define BIT_DSGCR_PUREN						( BIT(0) )
+#define BIT_DSGCR_BDISEN						( BIT(1) )
+#define BIT_DSGCR_ZUEN						( BIT(2) )
+#define BIT_DSGCR_LPIOPD						( BIT(3) )
+#define BIT_DSGCR_LPPLLPD					( BIT(4) )
+#define BIT_DSGCR_CUAEN						( BIT(5) )
+#define BIT_DSGCR_DQSGX						( BIT(6) | BIT(7) )
+#define BIT_DSGCR_PUAD						( BIT(8) | BIT(9) | BIT(10) | BIT(11) )
+#define BIT_DSGCR_DTOODT					( BIT(12) )
+#define BIT_DSGCR_DTOPDO					( BIT(13) )
+#define BIT_DSGCR_DTOPDR					( BIT(14) )
+#define BIT_DSGCR_DTOIOM					( BIT(15) )
+#define BIT_DSGCR_DTOOE						( BIT(16) )
+#define BIT_DSGCR_ATOAE						( BIT(17) )
+#define BIT_DSGCR_RPMODE					( BIT(18) )
+#define BIT_DSGCR_SDRMODE					( BIT(19) | BIT(20) )
+
+/* PUBL PIR [0x0004] */
+#define BIT_PIR_INIT							( BIT(0) )
+#define BIT_PIR_ZCAL							( BIT(1) )
+#define BIT_PIR_CA							( BIT(2) )
+#define BIT_PIR_PLLINIT						( BIT(4) )
+#define BIT_PIR_DCAL							( BIT(5) )
+#define BIT_PIR_PHYRST						( BIT(6) )
+#define BIT_PIR_DRAMRST						( BIT(7) )
+#define BIT_PIR_DRAMINIT						( BIT(8) )
+#define BIT_PIR_WL							( BIT(9) )
+#define BIT_PIR_QSGATE						( BIT(10) )
+#define BIT_PIR_WLADJ							( BIT(11) )
+#define BIT_PIR_RDDSKW						( BIT(12) )
+#define BIT_PIR_WDDSKW						( BIT(13) )
+#define BIT_PIR_RDEYE							( BIT(14) )
+#define BIT_PIR_WDEYE						( BIT(15) )
+#define BIT_PIR_ICPC							( BIT(16) )
+#define BIT_PIR_PLLBYP						( BIT(17) )
+#define BIT_PIR_CTLDINIT						( BIT(18) )
+#define BIT_PIR_RDIMMINIT						( BIT(19) )
+#define BIT_PIR_CLRSR							( BIT(27) )
+#define BIT_PIR_LOOKBYP						( BIT(28) )
+#define BIT_PIR_DCALBYP						( BIT(29) )
+#define BIT_PIR_ZCALBYP						( BIT(30) )
+#define BIT_PIR_INITBYP						( BIT(31) )
+
+
+//#define EMC_FREQ_AUTO_TEST
+
+#endif
author	Yuval Adam <_@yuv.al>	2017-08-30 08:25:59 +0000
committer	Yuval Adam <_@yuv.al>	2017-08-30 08:25:59 +0000
commit	8e4bff4cab0ddac6060645b0715210484d02ff40 (patch)
tree	3a5c3024371a04692a3a6d9974d001cdff8ebf84 /include/soc/sprd/chip_x20