diff options
Diffstat (limited to 'arch/arm64/boot/dts/sprd_sp9836aea_fpga.dts')
| -rw-r--r-- | arch/arm64/boot/dts/sprd_sp9836aea_fpga.dts | 675 |
1 files changed, 675 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/sprd_sp9836aea_fpga.dts b/arch/arm64/boot/dts/sprd_sp9836aea_fpga.dts new file mode 100644 index 00000000..be7a6029 --- /dev/null +++ b/arch/arm64/boot/dts/sprd_sp9836aea_fpga.dts @@ -0,0 +1,675 @@ +/* + * SPREADTRUM Ltd. + * + * TSharkL DTS + */ + +/dts-v1/; + +/memreserve/ 0x80000000 0x00010000; +/memreserve/ 0x8a800000 0x600000; + +/* memory reserved for ION(carveout mm)*/ +/memreserve/ 0x98800000 0x7100000; + +/* memory reserved for ION(overlay)*/ +/memreserve/ 0x9f900000 0x700000; /* 7MK */ + +/include/ "sc2723-regulators.dtsi" +/include/ "sprd-battery.dtsi" +/* **** FPGA needn't clk **** *\ +include "scx35l64-clocks.dtsi" +\* ************************** */ + +/ { + model = "scx35l64"; + compatible = "sprd,TsharkL"; + sprd,sc-id = <8830 1 0x20000>; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { + bootargs = "earlyprintk=sprd_uart,0x70000000"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0 0x80000000 0 0x20000000>; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + lcd0 = &fb0; + hwspinlock0 = &hwspinlock0; + hwspinlock1 = &hwspinlock1; + }; + + gic: interrupt-controller@12001000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0x12001000 0 0x1000>, + <0 0x12002000 0 0x1000>; + }; + + intc:interrupt-controller@71400000 { + compatible = "sprd,intc"; + #interrupt-cells = <0>; + interrupt-controller; + reg = <0 0x71400000 0 0x1000>, + <0 0x71500000 0 0x1000>, + <0 0x71600000 0 0x1000>, + <0 0x71700000 0 0x1000>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, + <1 14 0xff01>, + <1 11 0xff01>, + <1 10 0xff01>; + clock-frequency = <26000000>; + }; + + sprd_timer { + compatible = "sprd,sharkl64-timer"; + reg = <0 0x40050000 0 0x20>; /*aon GPTIMER0 */ + interrupts = <0 28 0x0>; + clock-frequency = <32768>; + }; + + sprd_ap_system_timer { + reg = <0 0x40230000 0 0x20>; + interrupts = <0 31 0x0>; + }; + + uart0: uart@70000000 { + compatible = "sprd,serial"; + reg = <0 0x70000000 0 0x100>; + interrupts = <0 2 0xf04>; + }; + + uart1: uart@70100000 { + compatible = "sprd,serial"; + reg = <0 0x70100000 0 0x100>; + interrupts = <0 3 0xf04>; + }; + sprd_backlight { + compatible = "sprd,sprd_backlight"; + start = <3>; + end = <3>; + flags = <0x100>; + }; + sprd_pwm_bl { + compatible = "sprd,sprd_pwm_bl"; + reg =<0 0x40260000 0 0xf>; + }; + hwspinlock0: hwspinlock0@20c00000{ + compatible = "sprd,sprd-hwspinlock"; + reg = <0 0x20c00000 0 0x1000>; + }; + hwspinlock1: hwspinlock1@40060000{ + compatible = "sprd,sprd-hwspinlock"; + reg = <0 0x40060000 0 0x1000>; + status = "ok"; + }; + watchdog { + compatible = "sprd,watchdog"; + reg = <0 0X40290000 0 0x1000>; + }; + + d_eic_gpio: gpio@40210000 { + compatible = "sprd,d-eic-gpio"; + reg = <0 0x40210000 0 0x1000>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-cells = <2>; + gpiobase = <288>; + ngpios = <16>; + interrupts = <0 37 0x0>; + }; + + d_gpio_gpio: gpio@40280000 { + compatible = "sprd,d-gpio-gpio"; + reg = <0 0x40280000 0 0x1000>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-cells = <2>; + gpiobase = <0>; + ngpios = <256>; + interrupts = <0 35 0x0>; + }; + + sdhci3: sdhci@20600000 { + compatible = "sprd,sdhci-shark"; + interrupts = <0 60 0x0>; + reg = <0 0x20600000 0 0x1000>; + id = <3>; + bus-width = <8>; + max-frequency = <384000000>; + keep-power-in-suspend = <1>; + non-removable = <1>; + caps = <0x80000000>; + caps2 = <0x202>; + quirks = <0x21009001>; //SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | SDHCI_QUIRK_BROKEN_CARD_DETECTION | SDHCI_QUIRK_CLOCK_BEFORE_RESET + quirks2 = <0x8>; //SDHCI_QUIRK2_PRESET_VALUE_BROKEN + host-caps-mask = <0x03000000>; + // vdd-vmmc = "vddemmccore"; + // vdd-vqmmc = "vddemmcio"; + vdd-vmmc = "vddemmccore"; + vdd-vqmmc = "vddgen1"; + clock-names = "clk_emmc"; + clocks = <&clk_emmc>, <&clk_384m>; + enb-bit = <0x800>; + rst-bit = <0x4000>; + write-delay = <0x04>; + read-pos-delay = <0x04>; + read-neg-delay = <0x04>; + keep-power = <0>; + runtime = <1>; + }; + + sdhci0: sdhci@20300000 { + compatible = "sprd,sdhci-shark"; + interrupts = <0 57 0x0>; + reg = <0 0x20300000 0 0x1000>; + id = <0>; + bus-width = <4>; + max-frequency = <384000000>; + keep-power-in-suspend = <1>; + caps = <0x80000000>; + caps2 = <0x202>; + quirks = <0x21009001>; //SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | SDHCI_QUIRK_BROKEN_CARD_DETECTION | SDHCI_QUIRK_CLOCK_BEFORE_RESET + quirks2 = <0x8>; //SDHCI_QUIRK2_PRESET_VALUE_BROKEN + host-caps-mask = <0x05000000>; + vdd-vmmc = "vddsdcore"; + vdd-vqmmc = "vddsdio"; + vqmmc-voltage-level = <3000000>; + cd-gpios = <71>; + clock-names = "clk_sdio0"; + clocks = <&clk_sdio0>, <&clk_384m>; + enb-bit = <0x100>; + rst-bit = <0x800>; + keep-power = <0>; + runtime = <1>; + }; + sdhci1: sdhci@20400000 { + compatible = "sprd,sdhci-shark"; + interrupts = <0 58 0x0>; + reg = <0 0x20400000 0 0x1000>; + id = <1>; + bus-width = <4>; + max-frequency = <96000000>; + keep-power-in-suspend = <1>; + cap-power-off-card = <1>; + caps = <0x80000000>; + quirks = <0x21009001>; //SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | SDHCI_QUIRK_BROKEN_CARD_DETECTION | SDHCI_QUIRK_CLOCK_BEFORE_RESET + quirks2 = <0x8>; //SDHCI_QUIRK2_PRESET_VALUE_BROKEN + clock-names = "clk_sdio1"; + clocks = <&clk_sdio1>, <&clk_96m>; + enb-bit = <0x200>; + rst-bit = <0x1000>; + keep-power = <0>; + runtime = <1>; + }; + + + adi: adi_bus { + compatible = "sprd,adi-bus"; + interrupts = <0 38 0x0>; + reg = <0 0x40038000 0 0x1000>; + interrupt-controller; + sprd,irqnums = <11>; + #interrupt-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x100 0 0x40038100 0x80>; + + keyboard_backlight { + compatible = "sprd,keyboard-backlight"; + }; + a_eic_gpio: gpio@100{ + compatible = "sprd,a-eic-gpio"; + reg = <0x100 0x80>; /* adi reg */ + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-cells = <2>; + gpiobase = <304>; + ngpios = <16>; + interrupt-parent = <&adi>; + interrupts = <5 0x0>; /* ext irq 5 */ + }; + sprd_eic_keys { + compatible = "sprd,sprd-eic-keys"; + key_power { + label = "Power Key"; + linux,code = <116>; + gpios = <&a_eic_gpio 2 0>; + debounce-interval = <2>; + gpio-key,wakeup; + }; + }; + }; + gpio_keys { + compatible = "gpio-keys"; + input-name = "sprd-gpio-keys"; + key_volumedown { + label = "Volumedown Key"; + linux,code = <114>; + gpios = <&d_gpio_gpio 124 1>; + debounce-interval = <2>; + gpio-key,wakeup; + }; + key_volumeup { + label = "Volumeup Key"; + linux,code = <115>; + gpios = <&d_gpio_gpio 125 1>; + debounce-interval = <2>; + gpio-key,wakeup; + }; + }; + + usb: usb@20200000{ + compatible = "sprd,usb"; + interrupts = <0 55 0x0>; + ngpios = <1>; + gpios = <&a_eic_gpio 0 0>; + reg = <0 0x20200000 0 0x1000>; + tune_value = <0x44073e33>; + usb-supply = <&vddusb>; + #address-cells = <1>; + #size-cells = <0>; + }; + sprd_thermal: sprd_thermal@402F0000{ + compatible = "sprd,sprd-thermal"; + id = <0>; + interrupts = <0 26 0x0>; + reg = <0 0x402F0000 0 0x1000>; + trip_points_active = <105>; + trip_points_critical = <114>; + trip_num = <5>; + }; + i2c0: i2c@70500000{ + compatible = "sprd,i2c"; + interrupts = <0 11 0x0>; + reg = <0 0x70500000 0 0x1000>; + #clock-names = "clk_i2c0"; + #address-cells = <1>; + #size-cells = <0>; + sensor_main@0x3c { + compatible = "sprd,sensor_main"; + reg = <0x3c>; + }; + sensor_sub@0x21 { + compatible = "sprd,sensor_sub"; + reg = <0x21>; + }; + }; + sprd-io-base { + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 1 0>; + ahb { + compatible = "sprd,ahb"; + reg = <0 0x20e00000 0 0x40000>; + }; + apbckg { + compatible = "sprd,apbckg"; + reg = <0 0x21500000 0 0x1000>; + }; + hwlock0 { + compatible = "sprd,hwlock0"; + reg = <0 0x20d00000 0 0x1000>; + }; + pub_apb { + compatible = "sprd,pub_apb"; + reg = <0 0x30020000 0 0x10000>; + }; + aon_apb { + compatible = "sprd,aon_apb"; + reg = <0 0x402e0000 0 0x40000>; + }; + pmu_apb { + compatible = "sprd,pmu_apb"; + reg = <0 0x402b0000 0 0x40000>; + }; + mm_ahb { + compatible = "sprd,mm_ahb"; + reg = <0 0x60d00000 0 0x10000>; + }; + mm_clk { + compatible = "sprd,mm_clk"; + reg = <0 0x60e00000 0 0x1000>; + }; + ap_ckg { + compatible = "sprd,ap_ckg"; + reg = <0 0x71200000 0 0x40000>; + }; + ap_apb { + compatible = "sprd,ap_apb"; + reg = <0 0x71300000 0 0x40000>; + }; + gpu_apb { + compatible = "sprd,gpu_apb"; + reg = <0 0x60100000 0 0x1000>; + }; + adi { + compatible = "sprd,adi"; + reg = <0 0x40030000 0 0x10000>; + }; + adi_slave { + compatible = "sprd,adi_slave"; + reg = <0 0x40038000 0 0x1000>; + }; + adc { + compatible = "sprd,adc"; + reg = <0 0x40038300 0 0x1000>; + }; + dma { + compatible = "sprd,dma"; + reg = <0 0x20100000 0 0x4000>; + interrupts = <0 50 0x0>; + }; + mailbox { + compatible = "sprd,mailbox"; + reg = <0 0x400a0000 0 0x10000>; + }; + rtc { + compatible = "sprd,rtc"; + reg = <0 0x40038080 0 0x80>; + interrupts = <0 2 0x0>; + }; + axibm0 { + compatible = "sprd,axibm0"; + reg = <0 0x30040000 0 0x20000>; + interrupts = <0 86 0x0>; + }; + i2c0: i2c@70500000{ + compatible = "sprd,i2c"; + interrupts = <0 11 0x0>; + reg = <0 0x70500000 0 0x1000>; + //address-cells = <1>; + //size-cells = <0>; + //clock-names = "clk_i2c0"; + sensor_main@0x3c { + compatible = "sprd,sensor_main"; + reg = <0x3c>; + }; + sensor_sub@0x21 { + compatible = "sprd,sensor_sub"; + reg = <0x21>; + }; + }; + i2c1: i2c@70600000{ + compatible = "sprd,i2c"; + interrupts = <0 12 0x0>; + reg = <0 0x70600000 0 0x1000>; + //clock-names = "clk_i2c1"; + }; + i2c2: i2c@70700000{ + compatible = "sprd,i2c"; + interrupts = <0 13 0x0>; + reg = <0 0x70700000 0 0x1000>; + //clock-names = "clk_i2c2"; + }; + i2c3: i2c@70800000{ + compatible = "sprd,i2c"; + interrupts = <0 14 0x0>; + reg = <0 0x70800000 0 0x1000>; + //clock-names = "clk_i2c3"; + }; + i2c4: i2c@70900000{ + compatible = "sprd,i2c"; + interrupts = <0 15 0x0>; + reg = <0 0x70900000 0 0x1000>; + //clock-names = "clk_i2c4"; + }; + + spi0: spi0@70a00000{ + compatible = "sprd,sprd-spi"; + interrupts = <0 7 0x0>; + reg = <0 0x70a00000 0 0x1000>; + //clock-names = "clk_spi0"; + }; + spi1: spi1@70b00000{ + compatible = "sprd,sprd-spi"; + interrupts = <0 8 0x0>; + reg = <0 0x70b00000 0 0x1000>; + //clock-names = "clk_spi1"; + }; + spi2: spi2@70c00000{ + compatible = "sprd,sprd-spi"; + interrupts = <0 9 0x0>; + reg = <0 0x70c00000 0 0x1000>; + //clock-names = "clk_spi2"; + }; + d_eic_gpio { + compatible = "sprd,d-eic-gpio"; + reg = <0 0x40210000 0 0x1000>; + }; + d_gpio_gpio { + compatible = "sprd,d-gpio-gpio"; + reg = <0 0x40280000 0 0x1000>; + }; + aon_dma { + compatible = "sprd,aon_dma"; + reg = <0 0x40100000 0 0x1000>; + interrupts = <0 50 0x0>; + }; + pwm { + compatible = "sprd,pwm"; + reg = <0 0x40260000 0 0x1000>; + }; + }; + + sprd_dcam { + compatible = "sprd,sprd_dcam"; + reg = <0 0x60800000 0 0x100000>; + interrupts = <0 45 0>; + }; + sprd_scale { + compatible = "sprd,sprd_scale"; + }; + sprd_rotation { + compatible = "sprd,sprd_rotation"; + }; + sprd_sensor { + compatible = "sprd,sprd_sensor"; + reg = <0 0x60c00000 0 0x100000>; + gpios = <&d_gpio_gpio 45 0 /*main reset*/ + &d_gpio_gpio 47 0 /*main powerdown*/ + &d_gpio_gpio 44 0 /*sub reset*/ + &d_gpio_gpio 46 0>; /*sub powerdown*/ + }; + sprd_isp { + compatible = "sprd,sprd_isp"; + reg = <0 0x60a00000 0 0x100000>; + }; + sprd_dma_copy { + compatible = "sprd,sprd_dma_copy"; + }; + + fb0: fb@20800000 { + compatible = "sprd,sprdfb"; + reg = <0 0x20800000 0 0x1000>, + <0 0x21800000 0 0x1000>; + interrupts = <0 46 0x0>, + <0 48 0x0>, + <0 49 0x0>; +/* + clock-names = "dispc_clk_parent", "dispc_dbi_clk_parent", "dispc_dpi_clk_parent", "dispc_emc_clk_parent", "dispc_clk", "dispc_dbi_clk", "dispc_dpi_clk", "dispc_emc_clk", "fb_spi_clock", "fb_spi_clock_parent"; + //clocks = <&clk_256m>, <&clk_256m>, <&clk_384m>, <&clk_aon_apb>, <&clk_dispc0>, <&clk_dispc0_dbi>, <&clk_dispc0_dpi>, <&clk_disp_emc>, <&clk_spi2>, <&ext_26m>; + clock-src = <256000000 256000000 384000000>; + dpi_clk_div = <7>; +*/ + sprd,fb_use_reservemem; + sprd,fb_mem = <0x8a800000 0x600000>; + + }; + + gsp@20a00000 { + compatible = "sprd,gsp"; + reg = <0 0x20a00000 0 0x1000>; + interrupts = <0 51 0x0>; +/* + clock-names = "clk_gsp", "clk_gsp_emc", "clk_gsp_parent", "clk_aon_apb"; + clocks = <&clk_gsp>, <&clk_gsp_emc>, <&clk_256m>, <&clk_aon_apb>; +*/ + gsp_mmu_ctrl_base = <0x20b08000>; + }; + + + gpu { + compatible = "sprd,mali-utgard"; + mali_pp_core_number = <4>; + interrupt-names = "mali_gp_irq", + "mali_gp_mmu_irq", + "mali_pp0_irq", + "mali_pp0_mmu_irq", + "mali_pp1_irq", + "mali_pp1_mmu_irq"; + reg-names = "mali_l2", + "mali_gp", + "mali_gp_mmu", + "mali_pp0", + "mali_pp0_mmu", + "mali_pp1", + "mali_pp1_mmu", + "mali_pmu"; + interrupts = <0 39 0x0>, // MALI_GP_IRQ, + <0 39 0x0>, // MALI_GP_MMU_IRQ, + <0 39 0x0>, // MALI_PP0_IRQ, + <0 39 0x0>, // MALI_PP0_MMU_IRQ, + <0 39 0x0>, // MALI_PP1_IRQ, + <0 39 0x0>; // MALI_PP1_MMU_IRQ, + reg = <0 0x60001000 0 0x200>,// MALI_L2,MALI_GPU_RESOURCE_L2(base_addr + 0x1000) + <0 0x60000000 0 0x100>,// MALI_GP, + <0 0x60003000 0 0x100>,// MALI_GP_MMU, + <0 0x60008000 0 0x1100>,// MALI_PP0, + <0 0x60004000 0 0x100>,// MALI_PP0_MMU, + <0 0x6000A000 0 0x1100>,// MALI_PP1, + <0 0x60005000 0 0x100>;// MALI_PP1_MMU, + /* <0x60002000 0x100>; //MALI_PMU, + clock-names = "clk_gpu_axi","clk_gpu","clk_153m6","clk_208m","clk_256m","clk_312m","clk_384m","clk_460m8"; + clocks = <&clk_gpu_axi>,<&clk_gpu>,<&clk_153m6>,<&clk_208m>,<&clk_256m>,<&clk_312m>,<&clk_384m>,<&clk_460m8>; +*/ + }; + + ion { + compatible = "sprd,ion-sprd"; + #address-cells = <1>; + #size-cells = <0>; + + sprd,ion-heap@1 { + reg = <1>; /* SYSTEM */ + reg-names = "ion_heap_system"; + sprd,ion-heap-type = <0>; /* SYSTEM */ + sprd,ion-heap-mem = <0x0 0x0>; + }; + + sprd,ion-heap@2 { + reg = <2>; /* MM */ + reg-names = "ion_heap_carveout_mm"; + sprd,ion-heap-type = <2>; /* carveout mm */ + sprd,ion-heap-mem = <0x98800000 0x7100000>; + }; + + sprd,ion-heap@3 { + reg = <3>; /* OVERLAY */ + reg-names = "ion_heap_carveout_overlay"; + sprd,ion-heap-type = <2>; /* CARVEOUT */ + sprd,ion-heap-mem = <0x9f900000 0x700000>; /* 7M */ + }; + }; + + sprd_iommu0: sprd_iommu@20b00000 { + compatible = "sprd,sprd_iommu";//gsp + func-name = "sprd_iommu_gsp"; + reg = <0 0x10000000 0 0x2000000>, //iova + <0 0x20b00000 0 0x8000>, //pgt + <0 0x20b08000 0 0x8000>; //ctrl_reg + reg_name = "iova","pgt","ctrl_reg"; + clock-names = "clk_gsp_emc","clk_153m6","clk_gsp"; + //clocks = <&clk_gsp_emc>, <&clk_153m6>,<&clk_gsp>; + status = "ok"; + }; + + sprd_iommu1: sprd_iommu@60f00000 { + compatible = "sprd,sprd_iommu";//mm + func-name = "sprd_iommu_mm"; + reg = <0 0x20000000 0 0x8000000>, //iova + <0 0x60f00000 0 0x20000>, //pgt + <0 0x60f20000 0 0x2000>; //ctrl_reg + reg_name = "iova","pgt","ctrl_reg"; + clock-names = "clk_mmu","clk_mm_i"; + //clocks = <&clk_mmu>,<&clk_mm>; + status = "ok"; + + }; + + sprd_vsp: sprd_vsp@60900000{ + compatible = "sprd,sprd_vsp"; + reg = <0 0x60900000 0 0xc000>; + interrupts = <0 43 0x0>; + clock-names = "clk_mm_i", "clk_vsp", "clk_parent_0", "clk_parent_1", "clk_parent_2", "clk_parent_3"; + //clocks = <&clk_mm>, <&clk_vsp>, <&clk_307m2>, <&clk_256m>, <&clk_128m>, <&clk_96m>; + clock-parent-info = <2 4>; + version = <6>; + }; + sprd_jpg { + compatible = "sprd,sprd_jpg"; + reg = <0 0x60B00000 0 0x8000>; + interrupts = <0 42 0x0>; + //clock-names = "clk_mm_i","clk_jpg"; + //clocks = <&clk_mm>, <&clk_jpg>; + }; + +}; |