diff options
Diffstat (limited to 'arch/arm64/boot')
31 files changed, 17454 insertions, 0 deletions
diff --git a/arch/arm64/boot/.gitignore b/arch/arm64/boot/.gitignore new file mode 100644 index 00000000..eb355113 --- /dev/null +++ b/arch/arm64/boot/.gitignore @@ -0,0 +1,3 @@ +Image +Image.gz +Image.gz-dtb diff --git a/arch/arm64/boot/Makefile b/arch/arm64/boot/Makefile new file mode 100644 index 00000000..df519849 --- /dev/null +++ b/arch/arm64/boot/Makefile @@ -0,0 +1,44 @@ +# +# arch/arm64/boot/Makefile +# +# This file is included by the global makefile so that you can add your own +# architecture-specific flags and dependencies. +# +# This file is subject to the terms and conditions of the GNU General Public +# License. See the file "COPYING" in the main directory of this archive +# for more details. +# +# Copyright (C) 2012, ARM Ltd. +# Author: Will Deacon <will.deacon@arm.com> +# +# Based on the ia64 boot/Makefile. +# + +include $(srctree)/arch/arm64/boot/dts/Makefile + +targets := Image Image.gz + +DTB_NAMES := $(subst $\",,$(CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES)) +ifneq ($(DTB_NAMES),) +DTB_LIST := $(addsuffix .dtb,$(DTB_NAMES)) +else +DTB_LIST := $(dtb-y) +endif +DTB_OBJS := $(addprefix $(obj)/dts/,$(DTB_LIST)) + +$(obj)/Image: vmlinux FORCE + $(call if_changed,objcopy) + +$(obj)/Image.gz: $(obj)/Image FORCE + $(call if_changed,gzip) + +$(obj)/Image.gz-dtb: $(obj)/Image.gz $(DTB_OBJS) FORCE + $(call if_changed,cat) + +install: $(obj)/Image + $(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \ + $(obj)/Image System.map "$(INSTALL_PATH)" + +zinstall: $(obj)/Image.gz + $(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \ + $(obj)/Image.gz System.map "$(INSTALL_PATH)" diff --git a/arch/arm64/boot/dts/.gitignore b/arch/arm64/boot/dts/.gitignore new file mode 100644 index 00000000..b60ed208 --- /dev/null +++ b/arch/arm64/boot/dts/.gitignore @@ -0,0 +1 @@ +*.dtb diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile new file mode 100644 index 00000000..ed8c38b0 --- /dev/null +++ b/arch/arm64/boot/dts/Makefile @@ -0,0 +1,30 @@ +dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb +dtb-$(CONFIG_MACH_SP9836AEA_FPGA) += sprd_sp9836aea_fpga.dtb +dtb-$(CONFIG_MACH_SP9836AEA_4MOD) += sprd_sp9836aea_4mod.dtb +dtb-$(CONFIG_MACH_SP9836AEA_3MOD) += sprd_sp9836aea_3mod.dtb +dtb-$(CONFIG_MACH_SP9838AEA_5MOD) += sprd_sp9838aea_5mod.dtb +dtb-$(CONFIG_MACH_SP9838AEA_POWER_DEBUG) += sprd_sp9838aea_power_debug.dtb +dtb-$(CONFIG_MACH_SP9838AEA_8CORE_LIGHT_SLEEP) += sprd_sp9838aea_8core_light_sleep.dtb +dtb-$(CONFIG_MACH_SP9838AEA_FHD) += sprd_sp9838aea_fhd.dtb +dtb-$(CONFIG_MACH_SS_SHARKLT8) += sprd_ss_sharklt8.dtb +dtb-$(CONFIG_MACH_SS_SHARKLT8LIGHTSLEEP) += sprd_ss_sharklt8lightsleep.dtb +dtb-$(CONFIG_MACH_SP9838AEA_FPGA) += sprd_sp9838aea_fpga.dtb + +dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb \ + fvp-base-gicv2-psci.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb +dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb + +targets += dtbs + +DTB_NAMES := $(subst $\",,$(CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES)) +ifneq ($(DTB_NAMES),) +DTB_LIST := $(addsuffix .dtb,$(DTB_NAMES)) +else +DTB_LIST := $(dtb-y) +endif +targets += $(DTB_LIST) + +dtbs: $(addprefix $(obj)/, $(DTB_LIST)) + +clean-files := dts/*.dtb *.dtb diff --git a/arch/arm64/boot/dts/apm-mustang.dts b/arch/arm64/boot/dts/apm-mustang.dts new file mode 100644 index 00000000..6541962f --- /dev/null +++ b/arch/arm64/boot/dts/apm-mustang.dts @@ -0,0 +1,30 @@ +/* + * dts file for AppliedMicro (APM) Mustang Board + * + * Copyright (C) 2013, Applied Micro Circuits Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +/dts-v1/; + +/include/ "apm-storm.dtsi" + +/ { + model = "APM X-Gene Mustang board"; + compatible = "apm,mustang", "apm,xgene-storm"; + + chosen { }; + + memory { + device_type = "memory"; + reg = < 0x1 0x00000000 0x0 0x80000000 >; /* Updated by bootloader */ + }; +}; + +&serial0 { + status = "ok"; +}; diff --git a/arch/arm64/boot/dts/apm-storm.dtsi b/arch/arm64/boot/dts/apm-storm.dtsi new file mode 100644 index 00000000..42edf193 --- /dev/null +++ b/arch/arm64/boot/dts/apm-storm.dtsi @@ -0,0 +1,398 @@ +/* + * dts file for AppliedMicro (APM) X-Gene Storm SOC + * + * Copyright (C) 2013, Applied Micro Circuits Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +/ { + compatible = "apm,xgene-storm"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@000 { + device_type = "cpu"; + compatible = "apm,potenza", "arm,armv8"; + reg = <0x0 0x000>; + enable-method = "spin-table"; + cpu-release-addr = <0x1 0x0000fff8>; + }; + cpu@001 { + device_type = "cpu"; + compatible = "apm,potenza", "arm,armv8"; + reg = <0x0 0x001>; + enable-method = "spin-table"; + cpu-release-addr = <0x1 0x0000fff8>; + }; + cpu@100 { + device_type = "cpu"; + compatible = "apm,potenza", "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "spin-table"; + cpu-release-addr = <0x1 0x0000fff8>; + }; + cpu@101 { + device_type = "cpu"; + compatible = "apm,potenza", "arm,armv8"; + reg = <0x0 0x101>; + enable-method = "spin-table"; + cpu-release-addr = <0x1 0x0000fff8>; + }; + cpu@200 { + device_type = "cpu"; + compatible = "apm,potenza", "arm,armv8"; + reg = <0x0 0x200>; + enable-method = "spin-table"; + cpu-release-addr = <0x1 0x0000fff8>; + }; + cpu@201 { + device_type = "cpu"; + compatible = "apm,potenza", "arm,armv8"; + reg = <0x0 0x201>; + enable-method = "spin-table"; + cpu-release-addr = <0x1 0x0000fff8>; + }; + cpu@300 { + device_type = "cpu"; + compatible = "apm,potenza", "arm,armv8"; + reg = <0x0 0x300>; + enable-method = "spin-table"; + cpu-release-addr = <0x1 0x0000fff8>; + }; + cpu@301 { + device_type = "cpu"; + compatible = "apm,potenza", "arm,armv8"; + reg = <0x0 0x301>; + enable-method = "spin-table"; + cpu-release-addr = <0x1 0x0000fff8>; + }; + }; + + gic: interrupt-controller@78010000 { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */ + <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */ + <0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */ + <0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */ + interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */ + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 0 0xff01>, /* Secure Phys IRQ */ + <1 13 0xff01>, /* Non-secure Phys IRQ */ + <1 14 0xff01>, /* Virt IRQ */ + <1 15 0xff01>; /* Hyp IRQ */ + clock-frequency = <50000000>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks { + #address-cells = <2>; + #size-cells = <2>; + ranges; + refclk: refclk { + compatible = "fixed-clock"; + #clock-cells = <1>; + clock-frequency = <100000000>; + clock-output-names = "refclk"; + }; + + pcppll: pcppll@17000100 { + compatible = "apm,xgene-pcppll-clock"; + #clock-cells = <1>; + clocks = <&refclk 0>; + clock-names = "pcppll"; + reg = <0x0 0x17000100 0x0 0x1000>; + clock-output-names = "pcppll"; + type = <0>; + }; + + socpll: socpll@17000120 { + compatible = "apm,xgene-socpll-clock"; + #clock-cells = <1>; + clocks = <&refclk 0>; + clock-names = "socpll"; + reg = <0x0 0x17000120 0x0 0x1000>; + clock-output-names = "socpll"; + type = <1>; + }; + + socplldiv2: socplldiv2 { + compatible = "fixed-factor-clock"; + #clock-cells = <1>; + clocks = <&socpll 0>; + clock-names = "socplldiv2"; + clock-mult = <1>; + clock-div = <2>; + clock-output-names = "socplldiv2"; + }; + + qmlclk: qmlclk { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + clock-names = "qmlclk"; + reg = <0x0 0x1703C000 0x0 0x1000>; + reg-names = "csr-reg"; + clock-output-names = "qmlclk"; + }; + + ethclk: ethclk { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + clock-names = "ethclk"; + reg = <0x0 0x17000000 0x0 0x1000>; + reg-names = "div-reg"; + divider-offset = <0x238>; + divider-width = <0x9>; + divider-shift = <0x0>; + clock-output-names = "ethclk"; + }; + + eth8clk: eth8clk { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <ðclk 0>; + clock-names = "eth8clk"; + reg = <0x0 0x1702C000 0x0 0x1000>; + reg-names = "csr-reg"; + clock-output-names = "eth8clk"; + }; + + sataphy1clk: sataphy1clk@1f21c000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + reg = <0x0 0x1f21c000 0x0 0x1000>; + reg-names = "csr-reg"; + clock-output-names = "sataphy1clk"; + status = "disabled"; + csr-offset = <0x4>; + csr-mask = <0x00>; + enable-offset = <0x0>; + enable-mask = <0x06>; + }; + + sataphy2clk: sataphy1clk@1f22c000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + reg = <0x0 0x1f22c000 0x0 0x1000>; + reg-names = "csr-reg"; + clock-output-names = "sataphy2clk"; + status = "ok"; + csr-offset = <0x4>; + csr-mask = <0x3a>; + enable-offset = <0x0>; + enable-mask = <0x06>; + }; + + sataphy3clk: sataphy1clk@1f23c000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + reg = <0x0 0x1f23c000 0x0 0x1000>; + reg-names = "csr-reg"; + clock-output-names = "sataphy3clk"; + status = "ok"; + csr-offset = <0x4>; + csr-mask = <0x3a>; + enable-offset = <0x0>; + enable-mask = <0x06>; + }; + + sata01clk: sata01clk@1f21c000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + reg = <0x0 0x1f21c000 0x0 0x1000>; + reg-names = "csr-reg"; + clock-output-names = "sata01clk"; + csr-offset = <0x4>; + csr-mask = <0x05>; + enable-offset = <0x0>; + enable-mask = <0x39>; + }; + + sata23clk: sata23clk@1f22c000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + reg = <0x0 0x1f22c000 0x0 0x1000>; + reg-names = "csr-reg"; + clock-output-names = "sata23clk"; + csr-offset = <0x4>; + csr-mask = <0x05>; + enable-offset = <0x0>; + enable-mask = <0x39>; + }; + + sata45clk: sata45clk@1f23c000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + reg = <0x0 0x1f23c000 0x0 0x1000>; + reg-names = "csr-reg"; + clock-output-names = "sata45clk"; + csr-offset = <0x4>; + csr-mask = <0x05>; + enable-offset = <0x0>; + enable-mask = <0x39>; + }; + + rtcclk: rtcclk@17000000 { + compatible = "apm,xgene-device-clock"; + #clock-cells = <1>; + clocks = <&socplldiv2 0>; + reg = <0x0 0x17000000 0x0 0x2000>; + reg-names = "csr-reg"; + csr-offset = <0xc>; + csr-mask = <0x2>; + enable-offset = <0x10>; + enable-mask = <0x2>; + clock-output-names = "rtcclk"; + }; + }; + + serial0: serial@1c020000 { + status = "disabled"; + device_type = "serial"; + compatible = "ns16550a"; + reg = <0 0x1c020000 0x0 0x1000>; + reg-shift = <2>; + clock-frequency = <10000000>; /* Updated by bootloader */ + interrupt-parent = <&gic>; + interrupts = <0x0 0x4c 0x4>; + }; + + serial1: serial@1c021000 { + status = "disabled"; + device_type = "serial"; + compatible = "ns16550a"; + reg = <0 0x1c021000 0x0 0x1000>; + reg-shift = <2>; + clock-frequency = <10000000>; /* Updated by bootloader */ + interrupt-parent = <&gic>; + interrupts = <0x0 0x4d 0x4>; + }; + + serial2: serial@1c022000 { + status = "disabled"; + device_type = "serial"; + compatible = "ns16550a"; + reg = <0 0x1c022000 0x0 0x1000>; + reg-shift = <2>; + clock-frequency = <10000000>; /* Updated by bootloader */ + interrupt-parent = <&gic>; + interrupts = <0x0 0x4e 0x4>; + }; + + serial3: serial@1c023000 { + status = "disabled"; + device_type = "serial"; + compatible = "ns16550a"; + reg = <0 0x1c023000 0x0 0x1000>; + reg-shift = <2>; + clock-frequency = <10000000>; /* Updated by bootloader */ + interrupt-parent = <&gic>; + interrupts = <0x0 0x4f 0x4>; + }; + + phy1: phy@1f21a000 { + compatible = "apm,xgene-phy"; + reg = <0x0 0x1f21a000 0x0 0x100>; + #phy-cells = <1>; + clocks = <&sataphy1clk 0>; + status = "disabled"; + apm,tx-boost-gain = <30 30 30 30 30 30>; + apm,tx-eye-tuning = <2 10 10 2 10 10>; + }; + + phy2: phy@1f22a000 { + compatible = "apm,xgene-phy"; + reg = <0x0 0x1f22a000 0x0 0x100>; + #phy-cells = <1>; + clocks = <&sataphy2clk 0>; + status = "ok"; + apm,tx-boost-gain = <30 30 30 30 30 30>; + apm,tx-eye-tuning = <1 10 10 2 10 10>; + }; + + phy3: phy@1f23a000 { + compatible = "apm,xgene-phy"; + reg = <0x0 0x1f23a000 0x0 0x100>; + #phy-cells = <1>; + clocks = <&sataphy3clk 0>; + status = "ok"; + apm,tx-boost-gain = <31 31 31 31 31 31>; + apm,tx-eye-tuning = <2 10 10 2 10 10>; + }; + + sata1: sata@1a000000 { + compatible = "apm,xgene-ahci"; + reg = <0x0 0x1a000000 0x0 0x1000>, + <0x0 0x1f210000 0x0 0x1000>, + <0x0 0x1f21d000 0x0 0x1000>, + <0x0 0x1f21e000 0x0 0x1000>, + <0x0 0x1f217000 0x0 0x1000>; + interrupts = <0x0 0x86 0x4>; + status = "disabled"; + clocks = <&sata01clk 0>; + phys = <&phy1 0>; + phy-names = "sata-phy"; + }; + + sata2: sata@1a400000 { + compatible = "apm,xgene-ahci"; + reg = <0x0 0x1a400000 0x0 0x1000>, + <0x0 0x1f220000 0x0 0x1000>, + <0x0 0x1f22d000 0x0 0x1000>, + <0x0 0x1f22e000 0x0 0x1000>, + <0x0 0x1f227000 0x0 0x1000>; + interrupts = <0x0 0x87 0x4>; + status = "ok"; + clocks = <&sata23clk 0>; + phys = <&phy2 0>; + phy-names = "sata-phy"; + }; + + sata3: sata@1a800000 { + compatible = "apm,xgene-ahci"; + reg = <0x0 0x1a800000 0x0 0x1000>, + <0x0 0x1f230000 0x0 0x1000>, + <0x0 0x1f23d000 0x0 0x1000>, + <0x0 0x1f23e000 0x0 0x1000>; + interrupts = <0x0 0x88 0x4>; + status = "ok"; + clocks = <&sata45clk 0>; + phys = <&phy3 0>; + phy-names = "sata-phy"; + }; + + rtc: rtc@10510000 { + compatible = "apm,xgene-rtc"; + reg = <0x0 0x10510000 0x0 0x400>; + interrupts = <0x0 0x46 0x4>; + #clock-cells = <1>; + clocks = <&rtcclk 0>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/clcd-panels.dtsi b/arch/arm64/boot/dts/clcd-panels.dtsi new file mode 100644 index 00000000..0b0ff6ea --- /dev/null +++ b/arch/arm64/boot/dts/clcd-panels.dtsi @@ -0,0 +1,52 @@ +/* + * ARM Ltd. Versatile Express + * + */ + +/ { + panels { + panel@0 { + compatible = "panel"; + mode = "VGA"; + refresh = <60>; + xres = <640>; + yres = <480>; + pixclock = <39721>; + left_margin = <40>; + right_margin = <24>; + upper_margin = <32>; + lower_margin = <11>; + hsync_len = <96>; + vsync_len = <2>; + sync = <0>; + vmode = "FB_VMODE_NONINTERLACED"; + + tim2 = "TIM2_BCD", "TIM2_IPC"; + cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)"; + caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888"; + bpp = <16>; + }; + + panel@1 { + compatible = "panel"; + mode = "XVGA"; + refresh = <60>; + xres = <1024>; + yres = <768>; + pixclock = <15748>; + left_margin = <152>; + right_margin = <48>; + upper_margin = <23>; + lower_margin = <3>; + hsync_len = <104>; + vsync_len = <4>; + sync = <0>; + vmode = "FB_VMODE_NONINTERLACED"; + + tim2 = "TIM2_BCD", "TIM2_IPC"; + cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)"; + caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888"; + bpp = <16>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/foundation-v8.dts b/arch/arm64/boot/dts/foundation-v8.dts new file mode 100644 index 00000000..519c4b2c --- /dev/null +++ b/arch/arm64/boot/dts/foundation-v8.dts @@ -0,0 +1,232 @@ +/* + * ARM Ltd. + * + * ARMv8 Foundation model DTS + */ + +/dts-v1/; + +/memreserve/ 0x80000000 0x00010000; + +/ { + model = "Foundation-v8A"; + compatible = "arm,foundation-aarch64", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x80000000>, + <0x00000008 0x80000000 0 0x80000000>; + }; + + gic: interrupt-controller@2c001000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x2c001000 0 0x1000>, + <0x0 0x2c002000 0 0x1000>, + <0x0 0x2c004000 0 0x2000>, + <0x0 0x2c006000 0 0x2000>; + interrupts = <1 9 0xf04>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, + <1 14 0xff01>, + <1 11 0xff01>, + <1 10 0xff01>; + clock-frequency = <100000000>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 60 4>, + <0 61 4>, + <0 62 4>, + <0 63 4>; + }; + + smb { + compatible = "arm,vexpress,v2m-p1", "simple-bus"; + arm,v2m-memory-map = "rs1"; + #address-cells = <2>; /* SMB chipselect number and offset */ + #size-cells = <1>; + + ranges = <0 0 0 0x08000000 0x04000000>, + <1 0 0 0x14000000 0x04000000>, + <2 0 0 0x18000000 0x04000000>, + <3 0 0 0x1c000000 0x04000000>, + <4 0 0 0x0c000000 0x04000000>, + <5 0 0 0x10000000 0x04000000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 63>; + interrupt-map = <0 0 0 &gic 0 0 4>, + <0 0 1 &gic 0 1 4>, + <0 0 2 &gic 0 2 4>, + <0 0 3 &gic 0 3 4>, + <0 0 4 &gic 0 4 4>, + <0 0 5 &gic 0 5 4>, + <0 0 6 &gic 0 6 4>, + <0 0 7 &gic 0 7 4>, + <0 0 8 &gic 0 8 4>, + <0 0 9 &gic 0 9 4>, + <0 0 10 &gic 0 10 4>, + <0 0 11 &gic 0 11 4>, + <0 0 12 &gic 0 12 4>, + <0 0 13 &gic 0 13 4>, + <0 0 14 &gic 0 14 4>, + <0 0 15 &gic 0 15 4>, + <0 0 16 &gic 0 16 4>, + <0 0 17 &gic 0 17 4>, + <0 0 18 &gic 0 18 4>, + <0 0 19 &gic 0 19 4>, + <0 0 20 &gic 0 20 4>, + <0 0 21 &gic 0 21 4>, + <0 0 22 &gic 0 22 4>, + <0 0 23 &gic 0 23 4>, + <0 0 24 &gic 0 24 4>, + <0 0 25 &gic 0 25 4>, + <0 0 26 &gic 0 26 4>, + <0 0 27 &gic 0 27 4>, + <0 0 28 &gic 0 28 4>, + <0 0 29 &gic 0 29 4>, + <0 0 30 &gic 0 30 4>, + <0 0 31 &gic 0 31 4>, + <0 0 32 &gic 0 32 4>, + <0 0 33 &gic 0 33 4>, + <0 0 34 &gic 0 34 4>, + <0 0 35 &gic 0 35 4>, + <0 0 36 &gic 0 36 4>, + <0 0 37 &gic 0 37 4>, + <0 0 38 &gic 0 38 4>, + <0 0 39 &gic 0 39 4>, + <0 0 40 &gic 0 40 4>, + <0 0 41 &gic 0 41 4>, + <0 0 42 &gic 0 42 4>; + + ethernet@2,02000000 { + compatible = "smsc,lan91c111"; + reg = <2 0x02000000 0x10000>; + interrupts = <15>; + }; + + v2m_clk24mhz: clk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "v2m:clk24mhz"; + }; + + v2m_refclk1mhz: refclk1mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + clock-output-names = "v2m:refclk1mhz"; + }; + + v2m_refclk32khz: refclk32khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "v2m:refclk32khz"; + }; + + iofpga@3,00000000 { + compatible = "arm,amba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 3 0 0x200000>; + + v2m_sysreg: sysreg@010000 { + compatible = "arm,vexpress-sysreg"; + reg = <0x010000 0x1000>; + }; + + v2m_serial0: uart@090000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x090000 0x1000>; + interrupts = <5>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial1: uart@0a0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0a0000 0x1000>; + interrupts = <6>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial2: uart@0b0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0b0000 0x1000>; + interrupts = <7>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial3: uart@0c0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0c0000 0x1000>; + interrupts = <8>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + virtio_block@0130000 { + compatible = "virtio,mmio"; + reg = <0x130000 0x1000>; + interrupts = <42>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/fvp-base-gicv2-psci.dts b/arch/arm64/boot/dts/fvp-base-gicv2-psci.dts new file mode 100644 index 00000000..ed55571e --- /dev/null +++ b/arch/arm64/boot/dts/fvp-base-gicv2-psci.dts @@ -0,0 +1,294 @@ +/* + * Copyright (c) 2013, ARM Limited. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +/memreserve/ 0x80000000 0x00010000; + +/ { +}; + +/ { + model = "FVP Base"; + compatible = "arm,vfp-base", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + }; + + psci { + compatible = "arm,psci"; + method = "smc"; + cpu_suspend = <0x84000001>; + cpu_off = <0x84000002>; + cpu_on = <0xc4000003>; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + idle-states { + entry-method = "arm,psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + entry-method-param = <0x0010000>; + entry-latency-us = <40>; + exit-latency-us = <100>; + min-residency-us = <150>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + entry-method-param = <0x1010000>; + entry-latency-us = <500>; + exit-latency-us = <1000>; + min-residency-us = <2500>; + }; + }; + + big0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + clock-frequency = <1000000>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + big1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + clock-frequency = <1000000>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + big2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + clock-frequency = <1000000>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + big3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + clock-frequency = <1000000>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + little0: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + clock-frequency = <1000000>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + little1: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x101>; + enable-method = "psci"; + clock-frequency = <1000000>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + little2: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x102>; + enable-method = "psci"; + clock-frequency = <1000000>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + little3: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x103>; + enable-method = "psci"; + clock-frequency = <1000000>; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&big0>; + }; + core1 { + cpu = <&big1>; + }; + core2 { + cpu = <&big2>; + }; + core3 { + cpu = <&big3>; + }; + }; + cluster1 { + core0 { + cpu = <&little0>; + }; + core1 { + cpu = <&little1>; + }; + core2 { + cpu = <&little2>; + }; + core3 { + cpu = <&little3>; + }; + }; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x80000000>, + <0x00000008 0x80000000 0 0x80000000>; + }; + + gic: interrupt-controller@2f000000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x2f000000 0 0x10000>, + <0x0 0x2c000000 0 0x2000>, + <0x0 0x2c010000 0 0x2000>, + <0x0 0x2c02F000 0 0x2000>; + interrupts = <1 9 0xf04>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, + <1 14 0xff01>, + <1 11 0xff01>, + <1 10 0xff01>; + clock-frequency = <100000000>; + }; + + timer@2a810000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x2a810000 0x0 0x10000>; + clock-frequency = <100000000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + frame@2a820000 { + frame-number = <0>; + interrupts = <0 25 4>; + reg = <0x0 0x2a820000 0x0 0x10000>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 60 4>, + <0 61 4>, + <0 62 4>, + <0 63 4>; + }; + + smb { + compatible = "simple-bus"; + + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0 0x08000000 0x04000000>, + <1 0 0 0x14000000 0x04000000>, + <2 0 0 0x18000000 0x04000000>, + <3 0 0 0x1c000000 0x04000000>, + <4 0 0 0x0c000000 0x04000000>, + <5 0 0 0x10000000 0x04000000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 63>; + interrupt-map = <0 0 0 &gic 0 0 4>, + <0 0 1 &gic 0 1 4>, + <0 0 2 &gic 0 2 4>, + <0 0 3 &gic 0 3 4>, + <0 0 4 &gic 0 4 4>, + <0 0 5 &gic 0 5 4>, + <0 0 6 &gic 0 6 4>, + <0 0 7 &gic 0 7 4>, + <0 0 8 &gic 0 8 4>, + <0 0 9 &gic 0 9 4>, + <0 0 10 &gic 0 10 4>, + <0 0 11 &gic 0 11 4>, + <0 0 12 &gic 0 12 4>, + <0 0 13 &gic 0 13 4>, + <0 0 14 &gic 0 14 4>, + <0 0 15 &gic 0 15 4>, + <0 0 16 &gic 0 16 4>, + <0 0 17 &gic 0 17 4>, + <0 0 18 &gic 0 18 4>, + <0 0 19 &gic 0 19 4>, + <0 0 20 &gic 0 20 4>, + <0 0 21 &gic 0 21 4>, + <0 0 22 &gic 0 22 4>, + <0 0 23 &gic 0 23 4>, + <0 0 24 &gic 0 24 4>, + <0 0 25 &gic 0 25 4>, + <0 0 26 &gic 0 26 4>, + <0 0 27 &gic 0 27 4>, + <0 0 28 &gic 0 28 4>, + <0 0 29 &gic 0 29 4>, + <0 0 30 &gic 0 30 4>, + <0 0 31 &gic 0 31 4>, + <0 0 32 &gic 0 32 4>, + <0 0 33 &gic 0 33 4>, + <0 0 34 &gic 0 34 4>, + <0 0 35 &gic 0 35 4>, + <0 0 36 &gic 0 36 4>, + <0 0 37 &gic 0 37 4>, + <0 0 38 &gic 0 38 4>, + <0 0 39 &gic 0 39 4>, + <0 0 40 &gic 0 40 4>, + <0 0 41 &gic 0 41 4>, + <0 0 42 &gic 0 42 4>; + + /include/ "rtsm_ve-motherboard.dtsi" + }; +}; + +/include/ "clcd-panels.dtsi" diff --git a/arch/arm64/boot/dts/juno.dts b/arch/arm64/boot/dts/juno.dts new file mode 100644 index 00000000..f260d702 --- /dev/null +++ b/arch/arm64/boot/dts/juno.dts @@ -0,0 +1,498 @@ +/* + * ARM Ltd. Juno Plaform + * + * Fast Models FVP v2 support + */ + +/dts-v1/; + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + model = "Juno"; + compatible = "arm,juno", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &soc_uart0; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + }; + + cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x101>; + enable-method = "psci"; + }; + + cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x102>; + enable-method = "psci"; + }; + + cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x103>; + enable-method = "psci"; + }; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a57","arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a57","arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0x0 0x7f000000>, + <0x00000008 0x80000000 0x1 0x80000000>; + }; + + /* memory@14000000 { + device_type = "memory"; + reg = <0x00000000 0x14000000 0x0 0x02000000>; + }; */ + + gic: interrupt-controller@2c001000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x2c010000 0 0x1000>, + <0x0 0x2c02f000 0 0x1000>, + <0x0 0x2c04f000 0 0x2000>, + <0x0 0x2c06f000 0 0x2000>; + interrupts = <GIC_PPI 9 0xf04>; + }; + + msi0: msi@2c1c0000 { + compatible = "arm,gic-msi"; + reg = <0x0 0x2c1c0000 0 0x10000 + 0x0 0x2c1d0000 0 0x10000 + 0x0 0x2c1e0000 0 0x10000 + 0x0 0x2c1f0000 0 0x10000>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 0xff01>, + <GIC_PPI 14 0xff01>, + <GIC_PPI 11 0xff01>, + <GIC_PPI 10 0xff01>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_SPI 60 4>, + <GIC_SPI 61 4>, + <GIC_SPI 62 4>, + <GIC_SPI 63 4>; + }; + + psci { + compatible = "arm,psci"; + method = "smc"; + cpu_suspend = <0xC4000001>; + cpu_off = <0x84000002>; + cpu_on = <0xC4000003>; + migrate = <0xC4000005>; + }; + + pci0: pci@30000000 { + compatible = "arm,pcie-xr3"; + device_type = "pci"; + reg = <0 0x7ff30000 0 0x1000 + 0 0x7ff20000 0 0x10000 + 0 0x40000000 0 0x10000000>; + bus-range = <0 255>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x00 0x5ff00000 0x0 0x00100000 + 0x02000000 0x0 0x00000000 0x40 0x00000000 0x0 0x80000000 + 0x42000000 0x0 0x80000000 0x40 0x80000000 0x0 0x80000000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic 0 136 4 + 0 0 0 2 &gic 0 137 4 + 0 0 0 3 &gic 0 138 4 + 0 0 0 4 &gic 0 139 4>; + }; + + scpi: scpi@2b1f0000 { + compatible = "arm,scpi-mhu"; + reg = <0x0 0x2b1f0000 0x0 0x10000>, /* MHU registers */ + <0x0 0x2e000000 0x0 0x10000>; /* Payload area */ + interrupts = <0 36 4>, /* low priority interrupt */ + <0 35 4>, /* high priority interrupt */ + <0 37 4>; /* secure channel interrupt */ + #clock-cells = <1>; + clock-output-names = "a57", "a53", "gpu", "hdlcd0", "hdlcd1"; + }; + + hdlcd0_osc: scpi_osc@3 { + compatible = "arm,scpi-osc"; + #clock-cells = <0>; + clocks = <&scpi 3>; + frequency-range = <23000000 210000000>; + clock-output-names = "pxlclk0"; + }; + + hdlcd1_osc: scpi_osc@4 { + compatible = "arm,scpi-osc"; + #clock-cells = <0>; + clocks = <&scpi 4>; + frequency-range = <23000000 210000000>; + clock-output-names = "pxlclk1"; + }; + + soc_uartclk: refclk72738khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <7273800>; + clock-output-names = "juno:uartclk"; + }; + + soc_refclk24mhz: clk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "juno:clk24mhz"; + }; + + mb_eth25mhz: clk25mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "ethclk25mhz"; + }; + + soc_usb48mhz: clk48mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + clock-output-names = "clk48mhz"; + }; + + soc_smc50mhz: clk50mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "smc_clk"; + }; + + soc_refclk100mhz: refclk100mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "apb_pclk"; + }; + + soc_faxiclk: refclk533mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <533000000>; + clock-output-names = "faxi_clk"; + }; + + soc_fixed_3v3: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + memory-controller@7ffd0000 { + compatible = "arm,pl354", "arm,primecell"; + reg = <0 0x7ffd0000 0 0x1000>; + interrupts = <0 86 4>, + <0 87 4>; + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + chip5-memwidth = <16>; + }; + + dma0: dma@0x7ff00000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0x7ff00000 0 0x1000>; + interrupts = <0 95 4>, + <0 88 4>, + <0 89 4>, + <0 90 4>, + <0 91 4>, + <0 108 4>, + <0 109 4>, + <0 110 4>, + <0 111 4>; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + clocks = <&soc_faxiclk>; + clock-names = "apb_pclk"; + }; + + soc_uart0: uart@7ff80000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x7ff80000 0x0 0x1000>; + interrupts = <0 83 4>; + clocks = <&soc_uartclk>, <&soc_refclk100mhz>; + clock-names = "uartclk", "apb_pclk"; + dmas = <&dma0 1 + &dma0 2>; + dma-names = "rx", "tx"; + }; + + /* this UART is reserved for secure software. + soc_uart1: uart@7ff70000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x7ff70000 0x0 0x1000>; + interrupts = <0 84 4>; + clocks = <&soc_uartclk>, <&soc_refclk100mhz>; + clock-names = "uartclk", "apb_pclk"; + }; */ + + ulpi_phy: phy@0 { + compatible = "phy-ulpi-generic"; + reg = <0x0 0x94 0x0 0x4>; + phy-id = <0>; + }; + + ehci@7ffc0000 { + compatible = "snps,ehci-h20ahb"; + /* compatible = "arm,h20ahb-ehci"; */ + reg = <0x0 0x7ffc0000 0x0 0x10000>; + interrupts = <0 117 4>; + clocks = <&soc_usb48mhz>; + clock-names = "otg"; + phys = <&ulpi_phy>; + }; + + ohci@0x7ffb0000 { + compatible = "generic-ohci"; + reg = <0x0 0x7ffb0000 0x0 0x10000>; + interrupts = <0 116 4>; + clocks = <&soc_usb48mhz>; + clock-names = "otg"; + }; + + i2c@0x7ffa0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x0 0x7ffa0000 0x0 0x1000>; + interrupts = <0 104 4>; + clock-frequency = <400000>; + i2c-sda-hold-time-ns = <500>; + clocks = <&soc_smc50mhz>; + + dvi0: dvi-transmitter@70 { + compatible = "nxp,tda998x"; + reg = <0x70>; + }; + + dvi1: dvi-transmitter@71 { + compatible = "nxp,tda998x"; + reg = <0x71>; + }; + }; + + /* mmci@1c050000 { + compatible = "arm,pl180", "arm,primecell"; + reg = <0x0 0x1c050000 0x0 0x1000>; + interrupts = <0 73 4>, + <0 74 4>; + max-frequency = <12000000>; + vmmc-supply = <&soc_fixed_3v3>; + clocks = <&soc_refclk24mhz>, <&soc_refclk100mhz>; + clock-names = "mclk", "apb_pclk"; + }; */ + + hdlcd@7ff60000 { + compatible = "arm,hdlcd"; + reg = <0 0x7ff60000 0 0x1000>; + interrupts = <0 85 4>; + clocks = <&hdlcd0_osc>; + clock-names = "pxlclk"; + i2c-slave = <&dvi0>; + + /* display-timings { + native-mode = <&timing0>; + timing0: timing@0 { + /* 1024 x 768 framebufer, standard VGA timings * / + clock-frequency = <65000>; + hactive = <1024>; + vactive = <768>; + hfront-porch = <24>; + hback-porch = <160>; + hsync-len = <136>; + vfront-porch = <3>; + vback-porch = <29>; + vsync-len = <6>; + }; + }; */ + }; + + hdlcd@7ff50000 { + compatible = "arm,hdlcd"; + reg = <0 0x7ff50000 0 0x1000>; + interrupts = <0 93 4>; + clocks = <&hdlcd1_osc>; + clock-names = "pxlclk"; + i2c-slave = <&dvi1>; + + display-timings { + native-mode = <&timing1>; + timing1: timing@1 { + /* 1024 x 768 framebufer, standard VGA timings */ + clock-frequency = <65000>; + hactive = <1024>; + vactive = <768>; + hfront-porch = <24>; + hback-porch = <160>; + hsync-len = <136>; + vfront-porch = <3>; + vback-porch = <29>; + vsync-len = <6>; + }; + }; + }; + + smb { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0 0x08000000 0x04000000>, + <1 0 0 0x14000000 0x04000000>, + <2 0 0 0x18000000 0x04000000>, + <3 0 0 0x1c000000 0x04000000>, + <4 0 0 0x0c000000 0x04000000>, + <5 0 0 0x10000000 0x04000000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 15>; + interrupt-map = <0 0 0 &gic 0 68 4>, + <0 0 1 &gic 0 69 4>, + <0 0 2 &gic 0 70 4>, + <0 0 3 &gic 0 160 4>, + <0 0 4 &gic 0 161 4>, + <0 0 5 &gic 0 162 4>, + <0 0 6 &gic 0 163 4>, + <0 0 7 &gic 0 164 4>, + <0 0 8 &gic 0 165 4>, + <0 0 9 &gic 0 166 4>, + <0 0 10 &gic 0 167 4>, + <0 0 11 &gic 0 168 4>, + <0 0 12 &gic 0 169 4>; + + motherboard { + model = "V2M-Juno"; + arm,hbi = <0x252>; + arm,vexpress,site = <0>; + arm,v2m-memory-map = "rs1"; + compatible = "arm,vexpress,v2p-p1", "simple-bus"; + #address-cells = <2>; /* SMB chipselect number and offset */ + #size-cells = <1>; + #interrupt-cells = <1>; + ranges; + + usb@5,00000000 { + compatible = "nxp,usb-isp1763"; + reg = <5 0x00000000 0x20000>; + bus-width = <16>; + interrupts = <4>; + }; + + ethernet@2,00000000 { + compatible = "smsc,lan9118", "smsc,lan9115"; + reg = <2 0x00000000 0x10000>; + interrupts = <3>; + phy-mode = "mii"; + reg-io-width = <4>; + smsc,irq-active-high; + smsc,irq-push-pull; + clocks = <&mb_eth25mhz>; + vdd33a-supply = <&soc_fixed_3v3>; /* change this */ + vddvario-supply = <&soc_fixed_3v3>; /* and this */ + }; + + iofpga@3,00000000 { + compatible = "arm,amba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 3 0 0x200000>; + + kmi@060000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x060000 0x1000>; + interrupts = <8>; + clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + kmi@070000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x070000 0x1000>; + interrupts = <8>; + clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + wdt@0f0000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0f0000 0x10000>; + interrupts = <7>; + clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>; + clock-names = "wdogclk", "apb_pclk"; + }; + + v2m_timer01: timer@110000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x110000 0x10000>; + interrupts = <9>; + clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>; + clock-names = "timclken1", "apb_pclk"; + }; + + v2m_timer23: timer@120000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x120000 0x10000>; + interrupts = <9>; + clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>; + clock-names = "timclken1", "apb_pclk"; + }; + + rtc@170000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x170000 0x10000>; + interrupts = <0>; + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rtsm_ve-aemv8a.dts b/arch/arm64/boot/dts/rtsm_ve-aemv8a.dts new file mode 100644 index 00000000..28ed4ba3 --- /dev/null +++ b/arch/arm64/boot/dts/rtsm_ve-aemv8a.dts @@ -0,0 +1,194 @@ +/* + * ARM Ltd. Fast Models + * + * Architecture Envelope Model (AEM) ARMv8-A + * ARMAEMv8AMPCT + * + * RTSM_VE_AEMv8A.lisa + */ + +/dts-v1/; + +/memreserve/ 0x80000000 0x00010000; + +/ { + model = "RTSM_VE_AEMv8A"; + compatible = "arm,rtsm_ve,aemv8a", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + }; + + psci { + compatible = "arm,psci"; + method = "smc"; + /* + * Function IDs usage and compliancy with PSCI v0.2 still + * under discussion. Current IDs should be considered + * temporary for demonstration purposes. + */ + cpu_suspend = <0x84000001>; + cpu_off = <0x84000002>; + cpu_on = <0x84000003>; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + idle-states { + entry-method = "arm,psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + entry-method-param = <0x0010000>; + entry-latency-us = <40>; + exit-latency-us = <100>; + min-residency-us = <150>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + entry-method-param = <0x1010000>; + entry-latency-us = <500>; + exit-latency-us = <1000>; + min-residency-us = <2500>; + }; + }; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x80000000>, + <0x00000008 0x80000000 0 0x80000000>; + }; + + gic: interrupt-controller@2c001000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x2c001000 0 0x1000>, + <0x0 0x2c002000 0 0x1000>, + <0x0 0x2c004000 0 0x2000>, + <0x0 0x2c006000 0 0x2000>; + interrupts = <1 9 0xf04>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, + <1 14 0xff01>, + <1 11 0xff01>, + <1 10 0xff01>; + clock-frequency = <100000000>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 60 4>, + <0 61 4>, + <0 62 4>, + <0 63 4>; + }; + + smb { + compatible = "simple-bus"; + + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0 0x08000000 0x04000000>, + <1 0 0 0x14000000 0x04000000>, + <2 0 0 0x18000000 0x04000000>, + <3 0 0 0x1c000000 0x04000000>, + <4 0 0 0x0c000000 0x04000000>, + <5 0 0 0x10000000 0x04000000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 63>; + interrupt-map = <0 0 0 &gic 0 0 4>, + <0 0 1 &gic 0 1 4>, + <0 0 2 &gic 0 2 4>, + <0 0 3 &gic 0 3 4>, + <0 0 4 &gic 0 4 4>, + <0 0 5 &gic 0 5 4>, + <0 0 6 &gic 0 6 4>, + <0 0 7 &gic 0 7 4>, + <0 0 8 &gic 0 8 4>, + <0 0 9 &gic 0 9 4>, + <0 0 10 &gic 0 10 4>, + <0 0 11 &gic 0 11 4>, + <0 0 12 &gic 0 12 4>, + <0 0 13 &gic 0 13 4>, + <0 0 14 &gic 0 14 4>, + <0 0 15 &gic 0 15 4>, + <0 0 16 &gic 0 16 4>, + <0 0 17 &gic 0 17 4>, + <0 0 18 &gic 0 18 4>, + <0 0 19 &gic 0 19 4>, + <0 0 20 &gic 0 20 4>, + <0 0 21 &gic 0 21 4>, + <0 0 22 &gic 0 22 4>, + <0 0 23 &gic 0 23 4>, + <0 0 24 &gic 0 24 4>, + <0 0 25 &gic 0 25 4>, + <0 0 26 &gic 0 26 4>, + <0 0 27 &gic 0 27 4>, + <0 0 28 &gic 0 28 4>, + <0 0 29 &gic 0 29 4>, + <0 0 30 &gic 0 30 4>, + <0 0 31 &gic 0 31 4>, + <0 0 32 &gic 0 32 4>, + <0 0 33 &gic 0 33 4>, + <0 0 34 &gic 0 34 4>, + <0 0 35 &gic 0 35 4>, + <0 0 36 &gic 0 36 4>, + <0 0 37 &gic 0 37 4>, + <0 0 38 &gic 0 38 4>, + <0 0 39 &gic 0 39 4>, + <0 0 40 &gic 0 40 4>, + <0 0 41 &gic 0 41 4>, + <0 0 42 &gic 0 42 4>; + + /include/ "rtsm_ve-motherboard.dtsi" + }; +}; + +/include/ "clcd-panels.dtsi" diff --git a/arch/arm64/boot/dts/rtsm_ve-motherboard.dtsi b/arch/arm64/boot/dts/rtsm_ve-motherboard.dtsi new file mode 100644 index 00000000..b683d470 --- /dev/null +++ b/arch/arm64/boot/dts/rtsm_ve-motherboard.dtsi @@ -0,0 +1,243 @@ +/* + * ARM Ltd. Fast Models + * + * Versatile Express (VE) system model + * Motherboard component + * + * VEMotherBoard.lisa + */ + + motherboard { + arm,v2m-memory-map = "rs1"; + compatible = "arm,vexpress,v2m-p1", "simple-bus"; + #address-cells = <2>; /* SMB chipselect number and offset */ + #size-cells = <1>; + #interrupt-cells = <1>; + ranges; + + flash@0,00000000 { + compatible = "arm,vexpress-flash", "cfi-flash"; + reg = <0 0x00000000 0x04000000>, + <4 0x00000000 0x04000000>; + bank-width = <4>; + }; + + vram@2,00000000 { + compatible = "arm,vexpress-vram"; + reg = <2 0x00000000 0x00800000>; + }; + + ethernet@2,02000000 { + compatible = "smsc,lan91c111"; + reg = <2 0x02000000 0x10000>; + interrupts = <15>; + }; + + v2m_clk24mhz: clk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "v2m:clk24mhz"; + }; + + v2m_refclk1mhz: refclk1mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + clock-output-names = "v2m:refclk1mhz"; + }; + + v2m_refclk32khz: refclk32khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "v2m:refclk32khz"; + }; + + iofpga@3,00000000 { + compatible = "arm,amba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 3 0 0x200000>; + + v2m_sysreg: sysreg@010000 { + compatible = "arm,vexpress-sysreg"; + reg = <0x010000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + }; + + v2m_sysctl: sysctl@020000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x020000 0x1000>; + clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>; + clock-names = "refclk", "timclk", "apb_pclk"; + #clock-cells = <1>; + clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; + }; + + aaci@040000 { + compatible = "arm,pl041", "arm,primecell"; + reg = <0x040000 0x1000>; + interrupts = <11>; + clocks = <&v2m_clk24mhz>; + clock-names = "apb_pclk"; + }; + + mmci@050000 { + compatible = "arm,pl180", "arm,primecell"; + reg = <0x050000 0x1000>; + interrupts = <9 10>; + cd-gpios = <&v2m_sysreg 0 0>; + wp-gpios = <&v2m_sysreg 1 0>; + max-frequency = <12000000>; + vmmc-supply = <&v2m_fixed_3v3>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "mclk", "apb_pclk"; + }; + + kmi@060000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x060000 0x1000>; + interrupts = <12>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + kmi@070000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x070000 0x1000>; + interrupts = <13>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + v2m_serial0: uart@090000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x090000 0x1000>; + interrupts = <5>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial1: uart@0a0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0a0000 0x1000>; + interrupts = <6>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial2: uart@0b0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0b0000 0x1000>; + interrupts = <7>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial3: uart@0c0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0c0000 0x1000>; + interrupts = <8>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + wdt@0f0000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0f0000 0x1000>; + interrupts = <0>; + clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>; + clock-names = "wdogclk", "apb_pclk"; + }; + + v2m_timer01: timer@110000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x110000 0x1000>; + interrupts = <2>; + clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + v2m_timer23: timer@120000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x120000 0x1000>; + interrupts = <3>; + clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + rtc@170000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x170000 0x1000>; + interrupts = <4>; + clocks = <&v2m_clk24mhz>; + clock-names = "apb_pclk"; + }; + + clcd@1f0000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x1f0000 0x1000>; + interrupts = <14>; + clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>; + clock-names = "clcdclk", "apb_pclk"; + mode = "XVGA"; + use_dma = <0>; + framebuffer = <0x18000000 0x00180000>; + }; + + virtio_block@0130000 { + compatible = "virtio,mmio"; + reg = <0x130000 0x200>; + interrupts = <42>; + }; + }; + + v2m_fixed_3v3: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + mcc { + compatible = "arm,vexpress,config-bus", "simple-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; + + v2m_oscclk1: osc@1 { + /* CLCD clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 1>; + freq-range = <23750000 63500000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk1"; + }; + + reset@0 { + compatible = "arm,vexpress-reset"; + arm,vexpress-sysreg,func = <5 0>; + }; + + muxfpga@0 { + compatible = "arm,vexpress-muxfpga"; + arm,vexpress-sysreg,func = <7 0>; + }; + + shutdown@0 { + compatible = "arm,vexpress-shutdown"; + arm,vexpress-sysreg,func = <8 0>; + }; + + reboot@0 { + compatible = "arm,vexpress-reboot"; + arm,vexpress-sysreg,func = <9 0>; + }; + + dvimode@0 { + compatible = "arm,vexpress-dvimode"; + arm,vexpress-sysreg,func = <11 0>; + }; + }; + }; diff --git a/arch/arm64/boot/dts/sc2723-regulators.dtsi b/arch/arm64/boot/dts/sc2723-regulators.dtsi new file mode 100644 index 00000000..777b6ce1 --- /dev/null +++ b/arch/arm64/boot/dts/sc2723-regulators.dtsi @@ -0,0 +1,367 @@ +/ { + + regulators { + compatible = "sprd,sc2723-regulator"; + #address-cells = <1>; + #size-cells = <1>; + + dummy { + }; + + vddcore: vddcore { + regulator-name = "vddcore"; + reg = <0x40038810 0x200 0x40038a00 0x3ff 0x400388c0 0x1>; /* pd reg && vol trm reg && otp_sel_reg */ + regulator-cal-channel = <0x40038888 0x4000 0xd>; + regulator-default-microvolt = <900000>; + regulator-step-microvolt = <3125>; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3125000>; + regulator-microvolt-offset = <0>; + hide-offset = <1000>; /*kernel hide_offset = hide-offset - 1000*/ + default-on; + dcdc; + }; + + vddarm: vddarm { + regulator-name = "vddarm"; + reg = <0x40038810 0x400 0x40038a04 0x3ff 0x400388c0 0x4>; /* pd reg && vol trm reg && otp_sel_reg */ + regulator-cal-channel = <0x40038888 0x2000 0xd>; + regulator-default-microvolt = <900000>; + regulator-step-microvolt = <3125>; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3125000>; + regulator-microvolt-offset = <0>; + hide-offset = <1000>; /*kernel hide_offset = hide-offset - 1000*/ + default-on; + dcdc; + }; + + vddmem: vddmem { + regulator-name = "vddmem"; + reg = <0x40038810 0x800 0x40038a08 0x3ff 0x400388c0 0x8>; /* pd reg && vol trm reg && otp_sel_reg */ + regulator-cal-channel = <0x40038888 0x6000 0xd>; + regulator-default-microvolt = <1200000>; + regulator-step-microvolt = <3125>; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3125000>; + regulator-microvolt-offset = <0>; + hide-offset = <1000>; /*kernel hide_offset = hide-offset - 1000*/ + /* default-on; */ + dcdc; + }; + + vddgen: vddgen { + regulator-name = "vddgen"; + reg = <0x40038810 0x1000 0x40038a0c 0x3ff 0x400388c0 0x10>; /* pd reg && vol trm reg && otp_sel_reg */ + regulator-cal-channel = <0x40038888 0x8000 0xd>; + regulator-default-microvolt = <2400000>; + regulator-step-microvolt = <3125>; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3125000>; + regulator-microvolt-offset = <0>; + hide-offset = <1000>; /*kernel hide_offset = hide-offset - 1000*/ + default-on; + dcdc; + }; + + vddrf: vddrf { + regulator-name = "vddrf"; + reg = <0x40038810 0x2000 0x40038a1c 0x3ff 0x400388c0 0x20>; /* pd reg && vol trm reg && otp_sel_reg */ + regulator-cal-channel = <0x40038888 0xa000 0xd>; + regulator-default-microvolt = <1500000>; + regulator-step-microvolt = <3125>; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3125000>; + regulator-microvolt-offset = <0>; + hide-offset = <1000>; /*kernel hide_offset = hide-offset - 1000*/ + default-on; + dcdc; + }; + + vddwpa: vddwpa { + regulator-name = "vddwpa"; + reg = <0x40038814 0x4000 0x40038a10 0x7 0 0>; /* pd reg && vol trm reg && otp_sel_reg */ + regulator-cal-channel = <0x40038888 0xe000 0xd>; + regulator-step-microvolt = <3125>; + regulator-min-microvolt = <3125000>; + regulator-max-microvolt = <3400000>; + regulator-microvolt-offset = <0>; + hide-offset = <1000>; /*kernel hide_offset = hide-offset - 1000*/ + dcdc; + }; + + vddcon: vddcon { + regulator-name = "vddcon"; + reg = <0x40038814 0x2000 0x40038a18 0x3ff 0 0>; /* pd reg && vol trm reg && otp_sel_reg */ + regulator-cal-channel = <0x40038888 0xc000 0xd>; + regulator-default-microvolt = <1600000>; + regulator-step-microvolt = <3125>; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3125000>; + regulator-microvolt-offset = <0>; + hide-offset = <1000>; /*kernel hide_offset = hide-offset - 1000*/ + dcdc; + }; + + vddrf0: vddrf0 { + regulator-name = "vddrf0"; + reg = <0x40038810 0x100 0x40038818 0xff00 0x400388c0 0x800>; /* pd reg && vol trm reg && otp_sel_reg */ + regulator-cal-channel = <0x40038844 0x4 0x15>; + regulator-default-microvolt = <1800000>; + regulator-step-microvolt = <6250>; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <2750000>; + regulator-microvolt-offset = <0>; + hide-offset = <1000>; /*kernel hide_offset = hide-offset - 1000*/ + default-on; + }; + + vddemmccore: vddemmccore { + regulator-name = "vddemmccore"; + reg = <0x40038810 0x80 0x40038834 0xff00 0x400388c0 0x80>; /* pd reg && vol trm reg && otp_sel_reg */ + regulator-cal-channel = <0x40038844 0x60 0x17>; + regulator-default-microvolt = <3000000>; + regulator-step-microvolt = <10000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3760000>; + regulator-microvolt-offset = <0>; + hide-offset = <1000>; /*kernel hide_offset = hide-offset - 1000*/ + default-on; + }; + + vddgen1: vddgen1 { + regulator-name = "vddgen1"; + reg = <0x40038810 0x40 0x40038824 0x7f00 0x400388c0 0x1000>; /* pd reg && vol trm reg && otp_sel_reg */ + regulator-cal-channel = <0x40038844 0x5 0x15>; + regulator-default-microvolt = <1800000>; + regulator-step-microvolt = <6250>; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1950000>; + regulator-microvolt-offset = <0>; + hide-offset = <1000>; /*kernel hide_offset = hide-offset - 1000*/ + default-on; + }; + + vddgen0: vddgen0 { + regulator-name = "vddgen0"; + reg = <0x40038810 0x10 0x40038820 0x7f 0x400388c0 0x2000>; /* pd reg && vol trm reg && otp_sel_reg */ + regulator-cal-channel = <0x40038844 0x6 0x15>; + regulator-default-microvolt = <1800000>; + regulator-step-microvolt = <6250>; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1950000>; + regulator-microvolt-offset = <0>; + hide-offset = <1000>; /*kernel hide_offset = hide-offset - 1000*/ + default-on; + }; + + vdddcxo: vdddcxo { + regulator-name = "vdddcxo"; + reg = <0x40038810 0x20 0x40038838 0xff00 0x400388c0 0x100>; /* pd reg && vol trm reg && otp_sel_reg */ + regulator-cal-channel = <0x40038844 0x80 0x17>; + regulator-default-microvolt = <1800000>; + regulator-step-microvolt = <10000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3760000>; + regulator-microvolt-offset = <0>; + hide-offset = <1000>; /*kernel hide_offset = hide-offset - 1000*/ + default-on; + }; + + vdd25: vdd25 { + regulator-name = "vdd25"; + reg = <0x40038810 0x8 0x40038840 0xff 0x400388c0 0x40>; /* pd reg && vol trm reg && otp_sel_reg */ + regulator-cal-channel = <0x40038844 0x100 0x16>; + regulator-default-microvolt = <2800000>; + regulator-step-microvolt = <10000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3760000>; + regulator-microvolt-offset = <0>; + hide-offset = <1000>; /*kernel hide_offset = hide-offset - 1000*/ + /* default-on; */ + }; + + vdd28: vdd28 { + regulator-name = "vdd28"; + reg = <0x40038810 0x4 0x40038824 0xff 0x400388c0 0x200>; /* pd reg && vol trm reg && otp_sel_reg */ + regulator-cal-channel = <0x40038844 0xc0 0x17>; + regulator-default-microvolt = <2800000>; + regulator-step-microvolt = <10000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3760000>; + regulator-microvolt-offset = <0>; + hide-offset = <1000>; /*kernel hide_offset = hide-offset - 1000*/ + default-on; + }; + + vdd18: vdd18 { + regulator-name = "vdd18"; + reg = <0x40038810 0x2 0x4003883c 0x7f00 0x400388c0 0x400>; /* pd reg && vol trm reg && otp_sel_reg */ + regulator-cal-channel = <0x40038844 0x1 0x15>; + regulator-default-microvolt = <1800000>; + regulator-step-microvolt = <6250>; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1950000>; + regulator-microvolt-offset = <0>; + hide-offset = <1000>; /*kernel hide_offset = hide-offset - 1000*/ + default-on; + }; + + vddwifipa: vddwifipa { + regulator-name = "vddwifipa"; + reg = <0x40038814 0x800 0x40038818 0xff 0 0>; /* pd reg && vol trm reg && otp_sel_reg */ + regulator-cal-channel = <0x40038844 0x20 0x17>; + regulator-default-microvolt = <3300000>; + regulator-step-microvolt = <10000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3760000>; + regulator-microvolt-offset = <0>; + hide-offset = <1000>; /*kernel hide_offset = hide-offset - 1000*/ + }; + + vddsdcore: vddsdcore { + regulator-name = "vddsdcore"; + reg = <0x40038814 0x400 0x40038830 0xff00 0 0>; /* pd reg && vol trm reg && otp_sel_reg */ + regulator-cal-channel = <0x40038844 0xa0 0x17>; + regulator-default-microvolt = <3000000>; + regulator-step-microvolt = <10000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3760000>; + regulator-microvolt-offset = <0>; + hide-offset = <1000>; /*kernel hide_offset = hide-offset - 1000*/ + }; + + vddsdio: vddsdio { + regulator-name = "vddsdio"; + reg = <0x40038814 0x1 0x40038828 0xff 0 0>; /* pd reg && vol trm reg && otp_sel_reg */ + regulator-cal-channel = <0x40038844 0x8 0x1d>; + regulator-default-microvolt = <3000000>; + regulator-step-microvolt = <10000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3760000>; + regulator-microvolt-offset = <0>; + hide-offset = <1000>; /*kernel hide_offset = hide-offset - 1000*/ + }; + + vddsim0: vddsim0 { + regulator-name = "vddsim0"; + reg = <0x40038814 0x2 0x40038828 0xff00 0 0>; /* pd reg && vol trm reg && otp_sel_reg */ + regulator-cal-channel = <0x40038844 0x500 0x16>; + regulator-default-microvolt = <1800000>; + regulator-step-microvolt = <10000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3760000>; + regulator-microvolt-offset = <0>; + hide-offset = <1000>; /*kernel hide_offset = hide-offset - 1000*/ + }; + + vddsim1: vddsim1 { + regulator-name = "vddsim1"; + reg = <0x40038814 0x4 0x4003882c 0xff 0 0>; /* pd reg && vol trm reg && otp_sel_reg */ + regulator-cal-channel = <0x40038844 0x400 0x16>; + regulator-default-microvolt = <1800000>; + regulator-step-microvolt = <10000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3760000>; + regulator-microvolt-offset = <0>; + hide-offset = <1000>; /*kernel hide_offset = hide-offset - 1000*/ + }; + + vddsim2: vddsim2 { + regulator-name = "vddsim2"; + reg = <0x40038814 0x8 0x4003882c 0xff00 0 0>; /* pd reg && vol trm reg && otp_sel_reg */ + regulator-cal-channel = <0x40038844 0x300 0x16>; + regulator-default-microvolt = <1800000>; + regulator-step-microvolt = <10000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3760000>; + regulator-microvolt-offset = <0>; + hide-offset = <1000>; /*kernel hide_offset = hide-offset - 1000*/ + }; + + vddcama: vddcama { + regulator-name = "vddcama"; + reg = <0x40038814 0x10 0x40038830 0xff 0 0>; /* pd reg && vol trm reg && otp_sel_reg */ + regulator-cal-channel = <0x40038844 0x200 0x16>; + regulator-default-microvolt = <2800000>; + regulator-step-microvolt = <10000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3760000>; + regulator-microvolt-offset = <0>; + hide-offset = <1000>; /*kernel hide_offset = hide-offset - 1000*/ + }; + + vddcamd: vddcamd { + regulator-name = "vddcamd"; + reg = <0x40038814 0x20 0x4003881c 0x7f 0 0>; /* pd reg && vol trm reg && otp_sel_reg */ + regulator-cal-channel = <0x40038844 0x2 0x15>; + regulator-default-microvolt = <1500000>; + regulator-step-microvolt = <6250>; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1950000>; + regulator-microvolt-offset = <0>; + hide-offset = <1000>; /*kernel hide_offset = hide-offset - 1000*/ + }; + + vddcamio: vddcamio { + regulator-name = "vddcamio"; + reg = <0x40038814 0x40 0x4003881c 0x7f00 0 0>; /* pd reg && vol trm reg && otp_sel_reg */ + regulator-cal-channel = <0x40038844 0x3 0x15>; + regulator-default-microvolt = <1800000>; + regulator-step-microvolt = <6250>; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1950000>; + regulator-microvolt-offset = <0>; + hide-offset = <1000>; /*kernel hide_offset = hide-offset - 1000*/ + }; + + vddcammot: vddcammot { + regulator-name = "vddcammot"; + reg = <0x40038814 0x80 0x40038834 0xff 0 0>; /* pd reg && vol trm reg && otp_sel_reg */ + regulator-cal-channel = <0x40038844 0x40 0x17>; + regulator-default-microvolt = <2800000>; + regulator-step-microvolt = <10000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3760000>; + regulator-microvolt-offset = <0>; + hide-offset = <1000>; /*kernel hide_offset = hide-offset - 1000*/ + }; + + vddusb: vddusb { + regulator-name = "vddusb"; + reg = <0x40038814 0x100 0x4003883c 0xff 0 0>; /* pd reg && vol trm reg && otp_sel_reg */ + regulator-cal-channel = <0x40038844 0x10 0x1d>; + regulator-default-microvolt = <3300000>; + regulator-step-microvolt = <10000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3760000>; + regulator-microvolt-offset = <0>; + hide-offset = <1000>; /*kernel hide_offset = hide-offset - 1000*/ + }; + + vddkpled: vddkpled { + regulator-name = "vddkpled"; + reg = <0x400388f4 0x100 0x400388f4 0xff 0 0>; /* pd reg && vol trm reg && otp_sel_reg */ + regulator-cal-channel = <0x400388f8 0x3000 0x18>; + regulator-default-microvolt = <3300000>; + regulator-step-microvolt = <10000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3760000>; + regulator-microvolt-offset = <0>; + hide-offset = <1000>; /*kernel hide_offset = hide-offset - 1000*/ + }; + + vddvibr: vddvibr { + regulator-name = "vddvibr"; + reg = <0x400388f8 0x100 0x400388f8 0xff 0 0>; /* pd reg && vol trm reg && otp_sel_reg */ + regulator-cal-channel = <0x400388f8 0x2000 0x18>; + regulator-default-microvolt = <3000000>; + regulator-step-microvolt = <10000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3760000>; + regulator-microvolt-offset = <0>; + hide-offset = <1000>; /*kernel hide_offset = hide-offset - 1000*/ + }; + }; + +}; diff --git a/arch/arm64/boot/dts/scx35l64-clocks.dtsi b/arch/arm64/boot/dts/scx35l64-clocks.dtsi new file mode 100644 index 00000000..04ab2fe7 --- /dev/null +++ b/arch/arm64/boot/dts/scx35l64-clocks.dtsi @@ -0,0 +1,905 @@ +/ { + + clks: clocks { + compatible = "sprd,scx35l64-clocks"; + #address-cells = <1>; + #size-cells = <1>; + + ext_26m: ext_26m { + compatible = "sprd,fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "ext_26m"; + }; + + ext_32k: ext_32k { + compatible = "sprd,fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ext_32k"; + }; + + ext_26m_rf1: ext_26m_rf1 { + compatible = "sprd,fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "ext_26m_rf1"; + }; + + ext_1m: ext_1m { + compatible = "sprd,fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + clock-output-names = "ext_1m"; + }; + + ext_2m: ext_2m { + compatible = "sprd,fixed-clock"; + #clock-cells = <0>; + clock-frequency = <2000000>; + clock-output-names = "ext_2m"; + }; + + ext_4m: ext_4m { + compatible = "sprd,fixed-clock"; + #clock-cells = <0>; + clock-frequency = <4000000>; + clock-output-names = "ext_4m"; + }; + + clk_pad: clk_pad { + compatible = "sprd,fixed-clock"; + #clock-cells = <0>; + clock-frequency = <64000000>; + clock-output-names = "clk_pad"; + }; + + clk_mpll: clk_mpll { + compatible = "sprd,adjustable-pll-clock"; + #clock-cells = <0>; + reg = <0x402e0044 0x7ff 0x402b0094 0x1>; /* mult reg and prepare reg */ + clock-output-names = "clk_mpll"; + }; + + clk_dpll: clk_dpll { + compatible = "sprd,adjustable-pll-clock"; + #clock-cells = <0>; + reg = <0x402e004c 0x7ff 0x402b0098 0x1>; /* mult reg and prepare reg */ + clock-output-names = "clk_dpll"; + }; + + clk_ltepll: clk_ltepll { + compatible = "sprd,adjustable-pll-clock"; + #clock-cells = <0>; + reg = <0x402e005c 0x7ff 0x402b009c 0x1>; /* mult reg and prepare reg */ + clock-output-names = "clk_ltepll"; + }; + + clk_twpll: clk_twpll { + compatible = "sprd,adjustable-pll-clock"; + #clock-cells = <0>; + reg = <0x402e0054 0x7ff 0x402b00a0 0x1>; /* mult reg and prepare reg */ + clock-output-names = "clk_twpll"; + }; + + clk_lvdspll: clk_lvdspll { + compatible = "sprd,adjustable-pll-clock"; + #clock-cells = <0>; + reg = <0x402e0064 0x7ff 0x402b00a4 0x1>; /* mult reg and prepare reg */ + clock-output-names = "clk_lvdspll"; + }; + + clk_768m: clk_768m { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <2>; + clocks = <&clk_twpll>; + clock-output-names = "clk_768m"; + }; + + clk_512m: clk_512m { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <3>; + clocks = <&clk_twpll>; + clock-output-names = "clk_512m"; + }; + + clk_384m: clk_384m { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <4>; + clocks = <&clk_twpll>; + clock-output-names = "clk_384m"; + }; + + clk_312m: clk_312m { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <5>; + clocks = <&clk_twpll>; + clock-output-names = "clk_312m"; + }; + + clk_307m2: clk_307m2 { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <5>; + clocks = <&clk_twpll>; + clock-output-names = "clk_307m2"; + }; + + clk_256m: clk_256m { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <6>; + clocks = <&clk_twpll>; + clock-output-names = "clk_256m"; + }; + + clk_192m: clk_192m { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <8>; + clocks = <&clk_twpll>; + clock-output-names = "clk_192m"; + }; + + clk_153m6: clk_153m6 { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <10>; + clocks = <&clk_twpll>; + clock-output-names = "clk_153m6"; + }; + + clk_128m: clk_128m { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <12>; + clocks = <&clk_twpll>; + clock-output-names = "clk_128m"; + }; + + clk_96m: clk_96m { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <16>; + clocks = <&clk_twpll>; + clock-output-names = "clk_96m"; + }; + + clk_76m8: clk_76m8 { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <20>; + clocks = <&clk_twpll>; + clock-output-names = "clk_76m8"; + }; + + clk_64m: clk_64m { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <24>; + clocks = <&clk_twpll>; + clock-output-names = "clk_64m"; + }; + + clk_51m2: clk_51m2 { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <30>; + clocks = <&clk_twpll>; + clock-output-names = "clk_51m2"; + }; + + clk_48m: clk_48m { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <32>; + clocks = <&clk_twpll>; + clock-output-names = "clk_48m"; + }; + + clk_38m4: clk_38m4 { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <40>; + clocks = <&clk_twpll>; + clock-output-names = "clk_38m4"; + }; + + clk_24m: clk_24m { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <64>; + clocks = <&clk_twpll>; + clock-output-names = "clk_24m"; + }; + + clk_12m: clk_12m { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <128>; + clocks = <&clk_twpll>; + clock-output-names = "clk_12m"; + }; + + clk_42m_d: clk_42m_d { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <32>; + clocks = <&clk_dpll>; + clock-output-names = "clk_42m_d"; + }; + + clk_56m_m: clk_56m_m { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <32>; + clocks = <&clk_mpll>; + clock-output-names = "clk_56m_m"; + }; + + clk_38m4_lte: clk_38m4_lte { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <32>; + clocks = <&clk_ltepll>; + clock-output-names = "clk_38m4_lte"; + }; + + clk_44m_lvds: clk_44m_lvds { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <32>; + clocks = <&clk_lvdspll>; + clock-output-names = "clk_44m_lvds"; + }; + + clk_614m4: clk_614m4 { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <2>; + clocks = <&clk_ltepll>; + clock-output-names = "clk_614m4"; + }; + + clk_mcu: clk_mcu { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x20e00054 0x7 0x20e00038 0x70>; /* select reg and divider reg */ + clocks = <&ext_26m>, <&clk_512m>, <&clk_768m>, <&clk_dpll>, <&clk_ltepll>, <&clk_twpll>, <&clk_mpll>; + clock-output-names = "clk_mcu"; + }; + + clk_ca7_axi: clk_ca7_axi { + compatible = "sprd,divider-clock"; + #clock-cells = <0>; + reg = <0x20e00038 0x700>; /* divider reg */ + clocks = <&clk_mcu>; + clock-output-names = "clk_ca7_axi"; + }; + + clk_ca7_dbg: clk_ca7_dbg { + compatible = "sprd,divider-clock"; + #clock-cells = <0>; + reg = <0x20e00038 0x70000>; /* divider reg */ + clocks = <&clk_mcu>; + clock-output-names = "clk_ca7_dbg"; + }; + + clk_pub_ahb: clk_pub_ahb { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x402d0020 0x3 0x402d0020 0x300>; /* select reg and divider reg */ + clocks = <&ext_26m>, <&ext_4m>, <&clk_96m>, <&clk_128m>; + clock-output-names = "clk_pub_ahb"; + }; + + clk_aon_apb: clk_aon_apb { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x402d0024 0x3 0x402d0024 0x300>; /* select reg and divider reg */ + clocks = <&ext_4m>, <&ext_26m>, <&clk_96m>, <&clk_128m>; + clock-output-names = "clk_aon_apb"; + }; + + clk_adi: clk_adi { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x402d0028 0x3 0x402e0000 0x10000>; /* select reg and enable reg */ + clocks = <&ext_26m>, <&ext_4m>, <&clk_38m4>, <&clk_51m2>; + clock-output-names = "clk_adi"; + }; + + clk_aux0: clk_aux0 { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x402e0088 0xf 0x402e0004 0x4>; /* select reg and enable reg */ + clocks = <&ext_32k>, <&ext_26m>, <&ext_26m_rf1>, <&ext_4m>, <&clk_42m_d>, <&clk_48m>, <&clk_56m_m>; + clock-output-names = "clk_aux0"; + }; + + clk_aux1: clk_aux1 { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x402d0088 0xf0 0x402e0004 0x8>; /* select reg and enable reg */ + clocks = <&ext_32k>, <&ext_26m>, <&ext_26m_rf1>, <&ext_4m>, <&clk_42m_d>, <&clk_48m>, <&clk_56m_m>, <&clk_38m4_lte>, <&clk_44m_lvds>; + clock-output-names = "clk_aux1"; + }; + + clk_aux2: clk_aux2 { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x402d0088 0xf00 0x402e0004 0x10>; /* select reg and enable reg */ + clocks = <&ext_32k>, <&ext_26m>, <&ext_26m_rf1>, <&ext_4m>, <&clk_42m_d>, <&clk_48m>, <&clk_56m_m>, <&clk_38m4_lte>, <&clk_44m_lvds>; + clock-output-names = "clk_aux2"; + }; + + clk_pwm0: clk_pwm0 { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x402d002c 0x3 0x402e0000 0x10>; /* select reg and enable reg */ + clocks = <&ext_32k>, <&ext_26m>, <&ext_26m_rf1>, <&clk_48m>; + clock-output-names = "clk_pwm0"; + }; + + clk_pwm1: clk_pwm1 { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x402d0030 0x3 0x402e0000 0x20>; /* select reg and enable reg */ + clocks = <&ext_32k>, <&ext_26m>, <&ext_26m_rf1>, <&clk_48m>; + clock-output-names = "clk_pwm1"; + }; + + clk_pwm2: clk_pwm2 { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x402d0034 0x3 0x402e0000 0x40>; /* select reg and enable reg */ + clocks = <&ext_32k>, <&ext_26m>, <&ext_26m_rf1>, <&clk_48m>; + clock-output-names = "clk_pwm2"; + }; + + clk_pwm3: clk_pwm3 { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x402d0038 0x3 0x402e0000 0x80>; /* select reg and enable reg */ + clocks = <&ext_32k>, <&ext_26m>, <&ext_26m_rf1>, <&clk_48m>; + clock-output-names = "clk_pwm3"; + }; + + clk_thm: clk_thm { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x402d0040 0x1 0x402e0004 0x2>; /* select reg and enable reg */ + clocks = <&ext_32k>, <&ext_1m>; + clock-output-names = "clk_thm"; + }; + + clk_mspi: clk_mspi { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x402d0044 0x3 0x402e0000 0x800000>; /* select reg and enable reg */ + clocks = <&ext_26m>, <&clk_51m2>, <&clk_76m8>, <&clk_96m>; + clock-output-names = "clk_mspi"; + }; + + clk_i2c: clk_i2c { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x402d0048 0x3 0x402e0000 0x80000000>; /* select reg and enable reg */ + clocks = <&ext_26m>, <&clk_48m>, <&clk_51m2>, <&clk_153m6>; + clock-output-names = "clk_i2c"; + }; + + clk_avs: clk_avs { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x402d004c 0x3 0x402e0004 0x40>; /* select reg and enable reg */ + clocks = <&ext_26m>, <&clk_48m>, <&clk_51m2>, <&clk_96m>; + clock-output-names = "clk_avs"; + }; + + clk_audif: clk_audif { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x402d0050 0x3 0x402e0000 0x20000>; /* select reg and enable reg */ + clocks = <&ext_26m>, <&clk_38m4>, <&clk_51m2>; + clock-output-names = "clk_audif"; + }; + + clk_ca7_dap: clk_ca7_dap { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x402d0054 0x3 0x402e0000 0x40000000>; /* select reg and enable reg */ + clocks = <&ext_26m>, <&clk_76m8>, <&clk_128m>, <&clk_153m6>; + clock-output-names = "clk_ca7_dap"; + }; + + clk_emc: clk_emc { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x402d0058 0x7 0x402d0058 0x700>; /* select reg and divider reg */ + clocks = <&ext_26m>, <&clk_192m>, <&clk_307m2>, <&clk_384m>, <&clk_512m>, <&clk_614m4>, <&clk_768m>, <&clk_dpll>; + clock-output-names = "clk_emc"; + }; + + clk_ca7_ts: clk_ca7_ts { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x402d005c 0x3 0x402e0000 0x10000000>; /* select reg and enable reg */ + clocks = <&ext_32k>, <&ext_26m>, <&clk_128m>, <&clk_153m6>; + clock-output-names = "clk_ca7_ts"; + }; + + clk_djtag_tck: clk_djtag_tck { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x402d0060 0x1>; /* select reg */ + clocks = <&ext_26m>, <&ext_4m>; + clock-output-names = "clk_djtag_tck"; + }; + + clk_arm7_ahb: clk_arm7_ahb { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x402d0064 0x3 0x402d0064 0x300>; /* select reg and divider reg */ + clocks = <&ext_4m>, <&ext_26m>, <&clk_96m>, <&clk_128m>; + clock-output-names = "clk_arm7_ahb"; + }; + + clk_ca5_ts: clk_ca5_ts { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x402d0068 0x3 0x402e0004 0x4000000>; /* select reg and enable reg */ + clocks = <&ext_32k>, <&ext_26m>, <&clk_128m>, <&clk_153m6>; + clock-output-names = "clk_ca5_ts"; + }; + + clk_disp_emc: clk_disp_emc { + compatible = "sprd,gate-clock"; + #clock-cells = <0>; + reg = <0x402e0004 0x800>; /* enable reg */ + clocks = <&clk_aon_apb>; + clock-output-names = "clk_disp_emc"; + }; + + clk_gsp_emc: clk_gsp_emc { + compatible = "sprd,gate-clock"; + #clock-cells = <0>; + reg = <0x402e0004 0x2000>; /* enable reg */ + clocks = <&clk_aon_apb>; + clock-output-names = "clk_gsp_emc"; + }; + + clk_ap_ahb: clk_ap_ahb { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x21500020 0x3>; /* select reg */ + clocks = <&ext_26m>, <&clk_76m8>, <&clk_128m>, <&clk_192m>; + clock-output-names = "clk_ap_ahb"; + }; + + clk_ap_apb: clk_ap_apb { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x21500024 0x3>; /* select reg */ + clocks = <&ext_26m>, <&clk_64m>, <&clk_96m>, <&clk_128m>; + clock-output-names = "clk_ap_apb"; + }; + + clk_gsp: clk_gsp { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x21500028 0x3 0x20e00000 0x8>; /* select reg and enable reg */ + clocks = <&clk_96m>, <&clk_153m6>, <&clk_192m>, <&clk_256m>; + clock-output-names = "clk_gsp"; + }; + + clk_dispc0: clk_dispc0 { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x2150002c 0x3 0x2150002c 0x700 0x20e00000 0x2>; /* select reg and divider reg and enable reg */ + clocks = <&clk_153m6>, <&clk_192m>, <&clk_256m>, <&clk_307m2>; + clock-output-names = "clk_dispc0"; + }; + + clk_dispc0_dbi: clk_dispc0_dbi { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x21500030 0x3 0x21500030 0x700>; /* select reg and divider reg */ + clocks = <&clk_128m>, <&clk_153m6>, <&clk_192m>, <&clk_256m>; + clock-output-names = "clk_dispc0_dbi"; + }; + + clk_dispc0_dpi: clk_dispc0_dpi { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x21500034 0x3 0x21500034 0xff00>; /* select reg and divider reg */ + clocks = <&clk_128m>, <&clk_153m6>, <&clk_192m>, <&clk_384m>; + clock-output-names = "clk_dispc0_dpi"; + }; + + clk_nandc_ecc: clk_nandc_ecc { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x21500038 0x1 0x20e00000 0x80000 0x20e00000 0x20000>; /* select reg and ckg enable reg and prepare reg */ + clocks = <&clk_153m6>, <&clk_192m>; + clock-output-names = "clk_nandc_ecc"; + }; + + clk_nandc_2x: clk_nandc_2x { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x20e03038 0x3 0x20e03038 0xc 0x20e00000 0xe0000>; /* select reg and divider reg and enable reg */ + clocks = <&clk_192m>, <&clk_256m>, <&clk_307m2>, <&clk_384m>; + clock-output-names = "clk_nandc_2x"; + }; + + clk_sdio0: clk_sdio0 { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x2150003c 0x3 0x2150003c 0x700 0x20e00000 0x100>; /* select reg and divider reg and enable reg */ + clocks = <&ext_26m>, <&clk_256m>, <&clk_307m2>, <&clk_384m>; + clock-output-names = "clk_sdio0"; + }; + + clk_sdio1: clk_sdio1 { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x21500040 0x3 0x20e00000 0x200>; /* select reg and enable reg */ + clocks = <&clk_48m>, <&clk_76m8>, <&clk_96m>, <&clk_128m>; + clock-output-names = "clk_sdio1"; + }; + + clk_sdio2: clk_sdio2 { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x21500044 0x3 0x20e00000 0x400>; /* select reg and enable reg */ + clocks = <&clk_48m>, <&clk_76m8>, <&clk_96m>, <&clk_128m>; + clock-output-names = "clk_sdio2"; + }; + + clk_emmc: clk_emmc { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x21500048 0x3 0x20e00000 0x800>; /* select reg and enable reg */ + clocks = <&ext_26m>, <&clk_256m>, <&clk_307m2>, <&clk_384m>; + clock-output-names = "clk_emmc"; + }; + + clk_otg_ref: clk_otg_ref { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x2150004c 0x1 0x20e00000 0x10>; /* select reg and enable reg */ + clocks = <&clk_12m>, <&clk_24m>; + clock-output-names = "clk_otg_ref"; + }; + + clk_hsic_ref: clk_hsic_ref { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x21500050 0x1 0x20e00000 0x4>; /* select reg and enable reg */ + clocks = <&clk_12m>, <&clk_24m>; + clock-output-names = "clk_hsic_ref"; + }; + + clk_uart0: clk_uart0 { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x21500054 0x3 0x21500054 0x700 0x71300000 0x2000>; /* select reg and divider reg and enable reg */ + clocks = <&ext_26m>, <&clk_48m>, <&clk_51m2>, <&clk_96m>; + clock-output-names = "clk_uart0"; + }; + + clk_uart1: clk_uart1 { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x21500058 0x3 0x21500058 0x700 0x71300000 0x4000>; /* select reg and divider reg and enable reg */ + clocks = <&ext_26m>, <&clk_48m>, <&clk_51m2>, <&clk_96m>; + clock-output-names = "clk_uart1"; + }; + + clk_uart2: clk_uart2 { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x2150005c 0x3 0x2150005c 0x700 0x71300000 0x8000>; /* select reg and divider reg and enable reg */ + clocks = <&ext_26m>, <&clk_48m>, <&clk_51m2>, <&clk_96m>; + clock-output-names = "clk_uart2"; + }; + + clk_uart3: clk_uart3 { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x21500060 0x3 0x21500060 0x700 0x71300000 0x10000>; /* select reg and divider reg and enable reg */ + clocks = <&ext_26m>, <&clk_48m>, <&clk_51m2>, <&clk_96m>; + clock-output-names = "clk_uart3"; + }; + + clk_uart4: clk_uart4 { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x21500064 0x3 0x21500064 0x700 0x71300000 0x20000>; /* select reg and divider reg and enable reg */ + clocks = <&ext_26m>, <&clk_48m>, <&clk_51m2>, <&clk_96m>; + clock-output-names = "clk_uart4"; + }; + + clk_i2c0: clk_i2c0 { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x21500068 0x3 0x21500068 0x700 0x71300000 0x100>; /* select reg and divider reg and enable reg */ + clocks = <&ext_26m>, <&clk_48m>, <&clk_51m2>, <&clk_153m6>; + clock-output-names = "clk_i2c0"; + }; + + clk_i2c1: clk_i2c1 { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x2150006c 0x3 0x2150006c 0x700 0x71300000 0x200>; /* select reg and divider reg and enable reg */ + clocks = <&ext_26m>, <&clk_48m>, <&clk_51m2>, <&clk_153m6>; + clock-output-names = "clk_i2c1"; + }; + + clk_i2c2: clk_i2c2 { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x21500070 0x3 0x21500070 0x700 0x71300000 0x400>; /* select reg and divider reg and enable reg */ + clocks = <&ext_26m>, <&clk_48m>, <&clk_51m2>, <&clk_153m6>; + clock-output-names = "clk_i2c2"; + }; + + clk_i2c3: clk_i2c3 { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x21500074 0x3 0x21500074 0x700 0x71300000 0x800>; /* select reg and divider reg and enable reg */ + clocks = <&ext_26m>, <&clk_48m>, <&clk_51m2>, <&clk_153m6>; + clock-output-names = "clk_i2c3"; + }; + + clk_i2c4: clk_i2c4 { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x21500078 0x3 0x21500078 0x700 0x71300000 0x1000>; /* select reg and divider reg and enable reg */ + clocks = <&ext_26m>, <&clk_48m>, <&clk_51m2>, <&clk_153m6>; + clock-output-names = "clk_i2c4"; + }; + + clk_spi0: clk_spi0 { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x2150007c 0x3 0x2150007c 0x700 0x71300000 0x20>; /* select reg and divider reg and enable reg */ + clocks = <&ext_26m>, <&clk_96m>, <&clk_153m6>, <&clk_192m>; + clock-output-names = "clk_spi0"; + }; + + clk_spi1: clk_spi1 { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x21500080 0x3 0x21500080 0x700 0x71300000 0x40>; /* select reg and divider reg and enable reg */ + clocks = <&ext_26m>, <&clk_96m>, <&clk_153m6>, <&clk_192m>; + clock-output-names = "clk_spi1"; + }; + + clk_spi2: clk_spi2 { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x21500084 0x3 0x21500084 0x700 0x71300000 0x80>; /* select reg and divider reg and enable reg */ + clocks = <&ext_26m>, <&clk_96m>, <&clk_153m6>, <&clk_192m>; + clock-output-names = "clk_spi2"; + }; + + clk_iis0: clk_iis0 { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x21500088 0x3 0x21500088 0x700 0x71300000 0x2>; /* select reg and divider reg and enable reg */ + clocks = <&ext_26m>, <&clk_128m>, <&clk_153m6>; + clock-output-names = "clk_iis0"; + }; + + clk_iis1: clk_iis1 { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x2150008c 0x3 0x2150008c 0x700 0x71300000 0x4>; /* select reg and divider reg and enable reg */ + clocks = <&ext_26m>, <&clk_128m>, <&clk_153m6>; + clock-output-names = "clk_iis1"; + }; + + clk_iis2: clk_iis2 { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x21500090 0x3 0x21500090 0x700 0x71300000 0x8>; /* select reg and divider reg and enable reg */ + clocks = <&ext_26m>, <&clk_128m>, <&clk_153m6>; + clock-output-names = "clk_iis2"; + }; + + clk_iis3: clk_iis3 { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x21500094 0x3 0x21500094 0x700 0x71300000 0x10>; /* select reg and divider reg and enable reg */ + clocks = <&ext_26m>, <&clk_128m>, <&clk_153m6>; + clock-output-names = "clk_iis3"; + }; + + clk_zipenc: clk_zipenc { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x21500098 0x3 0x20e00000 0x100000>; /* select reg and enable reg */ + clocks = <&clk_96m>, <&clk_153m6>, <&clk_192m>, <&clk_256m>; + clock-output-names = "clk_zipenc"; + }; + + clk_zipdec: clk_zipdec { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x2150009c 0x3 0x20e00000 0x200000>; /* select reg and enable reg */ + clocks = <&clk_96m>, <&clk_153m6>, <&clk_192m>, <&clk_256m>; + clock-output-names = "clk_zipdec"; + }; + + clk_gpu_axi: clk_gpu_axi { + compatible = "sprd,gate-clock"; + #clock-cells = <0>; + reg = <0x402e0000 0x8000000 0x402b0021 0x2000000>;/* enable reg and prepare reg */ + clocks = <&clk_aon_apb>; + clock-output-names = "clk_gpu_axi"; + }; + + clk_gpu: clk_gpu { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x60100004 0x7 0x60100004 0x30>; /* select reg and divider reg */ + clocks = <&clk_153m6>, <&clk_192m>, <&clk_256m>, <&clk_307m2>, <&clk_384m>, <&clk_512m>; + clock-output-names = "clk_gpu"; + }; + + clk_mm: clk_mm { + compatible = "sprd,gate-clock"; + #clock-cells = <0>; + reg = <0x402e0000 0x2000000 0x402b001d 0x2000000>; /* enable reg and prepare reg */ + clocks = <&clk_aon_apb>; + clock-output-names = "clk_mm"; + }; + + clk_mm_ahb: clk_mm_ahb { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x60e00020 0x3>; /* select reg */ + clocks = <&ext_26m>, <&clk_96m>, <&clk_128m>, <&clk_153m6>; + clock-output-names = "clk_mm_ahb"; + mm-domain; + }; + + clk_mm_axi: clk_mm_axi { + compatible = "sprd,gate-clock"; + #clock-cells = <0>; + reg = <0x60d00008 0x80>; /* enable reg */ + clocks = <&clk_mm>; + clock-output-names = "clk_mm_axi"; + mm-domain; + }; + + clk_mm_mtx_axi: clk_mm_mtx_axi { + compatible = "sprd,gate-clock"; + #clock-cells = <0>; + reg = <0x60d00008 0x100>; /* enable reg */ + clocks = <&clk_mm_axi>; + clock-output-names = "clk_mm_mtx_axi"; + mm-domain; + }; + + clk_mmu: clk_mmu { + compatible = "sprd,gate-clock"; + #clock-cells = <0>; + reg = <0x60d00000 0x80>; /* enable reg */ + clocks = <&clk_mm_ahb>; + clock-output-names = "clk_mmu"; + mm-domain; + }; + + clk_mm_ckg: clk_mm_ckg { + compatible = "sprd,gate-clock"; + #clock-cells = <0>; + reg = <0x60d00000 0x40>; /* enable reg */ + clocks = <&clk_mm_ahb>; + clock-output-names = "clk_mm_ckg"; + mm-domain; + }; + + clk_jpg: clk_jpg { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x60e00038 0x3 0x60d00008 0x40 0x60d00000 0x20>; /* select reg and ckg enable reg and prepare reg */ + clocks = <&clk_76m8>, <&clk_128m>, <&clk_256m>, <&clk_312m>; + clock-output-names = "clk_jpg"; + mm-domain; + }; + + clk_csi: clk_csi { + compatible = "sprd,gate-clock"; + #clock-cells = <0>; + reg = <0x60d00008 0x2 0x60d00000 0x10>; /* enable reg and prepare reg */ + clocks = <&clk_mm_ahb>; + clock-output-names = "clk_csi"; + mm-domain; + }; + + clk_dcam_mipi: clk_dcam_mipi { + compatible = "sprd,gate-clock"; + #clock-cells = <0>; + reg = <0x60d00008 0x1>; /* enable reg */ + clocks = <&clk_csi>; + clock-output-names = "clk_dcam_mipi"; + mm-domain; + }; + + clk_vsp: clk_vsp { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x60e00030 0x3 0x60d00008 0x20 0x60d00000 0x8>; /* select reg and ckg enable reg and prepare reg */ + clocks = <&clk_76m8>, <&clk_128m>, <&clk_256m>, <&clk_312m>; + clock-output-names = "clk_vsp"; + mm-domain; + }; + + clk_isp: clk_isp { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x60e00034 0x3 0x60d00008 0x10 0x60d00000 0x4>; /* select reg and ckg enable reg and prepare reg */ + clocks = <&clk_76m8>, <&clk_128m>, <&clk_256m>, <&clk_312m>; + clock-output-names = "clk_isp"; + mm-domain; + }; + + clk_ccir: clk_ccir { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x60e00028 0x10000 0x60d00000 0x2>; /* select reg and enable reg */ + clocks = <&clk_24m>, <&clk_pad>; + clock-output-names = "clk_ccir"; + mm-domain; + }; + + clk_sensor: clk_sensor { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x60e00024 0x3 0x60e00024 0x700 0x60d00008 0x4>; /* select reg and divider reg and enable reg */ + clocks = <&ext_26m>, <&clk_48m>, <&clk_76m8>, <&clk_96m>; + clock-output-names = "clk_sensor"; + mm-domain; + }; + + clk_dcam: clk_dcam { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x60e0002c 0x3 0x60d00008 0x8 0x60d00000 0x1>; /* select reg and ckg enable reg and prepare reg */ + clocks = <&clk_76m8>, <&clk_128m>, <&clk_256m>, <&clk_312m>; + clock-output-names = "clk_dcam"; + mm-domain; + }; + + }; + +}; diff --git a/arch/arm64/boot/dts/scx35lt8-clocks.dtsi b/arch/arm64/boot/dts/scx35lt8-clocks.dtsi new file mode 100644 index 00000000..3f2f79c8 --- /dev/null +++ b/arch/arm64/boot/dts/scx35lt8-clocks.dtsi @@ -0,0 +1,1025 @@ +/ { + + clks: clocks { + compatible = "sprd,scx35l64-clocks"; + #address-cells = <1>; + #size-cells = <1>; + + ext_26m: ext_26m { + compatible = "sprd,fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "ext_26m"; + }; + + ext_32k: ext_32k { + compatible = "sprd,fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ext_32k"; + }; + + ext_26m_rf1: ext_26m_rf1 { + compatible = "sprd,fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "ext_26m_rf1"; + }; + + ext_1m: ext_1m { + compatible = "sprd,fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + clock-output-names = "ext_1m"; + }; + + ext_2m: ext_2m { + compatible = "sprd,fixed-clock"; + #clock-cells = <0>; + clock-frequency = <2000000>; + clock-output-names = "ext_2m"; + }; + + ext_4m: ext_4m { + compatible = "sprd,fixed-clock"; + #clock-cells = <0>; + clock-frequency = <4000000>; + clock-output-names = "ext_4m"; + }; + + clk_pad: clk_pad { + compatible = "sprd,fixed-clock"; + #clock-cells = <0>; + clock-frequency = <64000000>; + clock-output-names = "clk_pad"; + }; + + clk_mpll: clk_mpll { + compatible = "sprd,adjustable-pll-clock"; + #clock-cells = <0>; + reg = <0x402e0044 0x7ff 0x402b00a8 0x1>; /* mult reg and prepare reg */ + clock-output-names = "clk_mpll"; + }; + + clk_dpll: clk_dpll { + compatible = "sprd,adjustable-pll-clock"; + #clock-cells = <0>; + reg = <0x402e004c 0x7ff 0x402b0098 0x1>; /* mult reg and prepare reg */ + clock-output-names = "clk_dpll"; + }; + + clk_ltepll: clk_ltepll { + compatible = "sprd,adjustable-pll-clock"; + #clock-cells = <0>; + reg = <0x402e005c 0x7ff 0x402b009c 0x1>; /* mult reg and prepare reg */ + clock-output-names = "clk_ltepll"; + }; + + clk_twpll: clk_twpll { + compatible = "sprd,adjustable-pll-clock"; + #clock-cells = <0>; + reg = <0x402e0054 0x7ff 0x402b00a0 0x1>; /* mult reg and prepare reg */ + clock-output-names = "clk_twpll"; + }; + + clk_lvdspll: clk_lvdspll { + compatible = "sprd,adjustable-pll-clock"; + #clock-cells = <0>; + reg = <0x402e0064 0x7ff 0x402b00a4 0x1>; /* mult reg and prepare reg */ + clock-output-names = "clk_lvdspll"; + }; + + clk_mpll0: clk_mpll0 { + compatible = "sprd,adjustable-pll-clock"; + #clock-cells = <0>; + reg = <0x402e0140 0x7ff 0x402b0094 0x1>; /* mult reg and prepare reg */ + clock-output-names = "clk_mpll0"; + }; + + clk_gpll: clk_gpll { + compatible = "sprd,adjustable-pll-clock"; + #clock-cells = <0>; + reg = <0x402e0148 0x7ff 0x402b0089 0x1>; /* mult reg and prepare reg */ + clock-output-names = "clk_gpll"; + }; + + clk_usbpll: clk_usbpll { + compatible = "sprd,adjustable-pll-clock"; + #clock-cells = <0>; + reg = <0x402e0150 0x7ff 0x402b0089 0x2>; /* mult reg and prepare reg */ + clock-output-names = "clk_usbpll"; + }; + + clk_768m: clk_768m { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <2>; + clocks = <&clk_twpll>; + clock-output-names = "clk_768m"; + }; + + clk_512m: clk_512m { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <3>; + clocks = <&clk_twpll>; + clock-output-names = "clk_512m"; + }; + + clk_384m: clk_384m { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <4>; + clocks = <&clk_twpll>; + clock-output-names = "clk_384m"; + }; + + clk_312m: clk_312m { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <5>; + clocks = <&clk_twpll>; + clock-output-names = "clk_312m"; + }; + + clk_307m2: clk_307m2 { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <5>; + clocks = <&clk_twpll>; + clock-output-names = "clk_307m2"; + }; + + clk_256m: clk_256m { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <6>; + clocks = <&clk_twpll>; + clock-output-names = "clk_256m"; + }; + + clk_192m: clk_192m { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <8>; + clocks = <&clk_twpll>; + clock-output-names = "clk_192m"; + }; + + clk_153m6: clk_153m6 { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <10>; + clocks = <&clk_twpll>; + clock-output-names = "clk_153m6"; + }; + + clk_128m: clk_128m { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <12>; + clocks = <&clk_twpll>; + clock-output-names = "clk_128m"; + }; + + clk_96m: clk_96m { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <16>; + clocks = <&clk_twpll>; + clock-output-names = "clk_96m"; + }; + + clk_76m8: clk_76m8 { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <20>; + clocks = <&clk_twpll>; + clock-output-names = "clk_76m8"; + }; + + clk_64m: clk_64m { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <24>; + clocks = <&clk_twpll>; + clock-output-names = "clk_64m"; + }; + + clk_51m2: clk_51m2 { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <30>; + clocks = <&clk_twpll>; + clock-output-names = "clk_51m2"; + }; + + clk_48m: clk_48m { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <32>; + clocks = <&clk_twpll>; + clock-output-names = "clk_48m"; + }; + + clk_38m4: clk_38m4 { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <40>; + clocks = <&clk_twpll>; + clock-output-names = "clk_38m4"; + }; + + clk_24m: clk_24m { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <64>; + clocks = <&clk_twpll>; + clock-output-names = "clk_24m"; + }; + + clk_12m: clk_12m { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <128>; + clocks = <&clk_twpll>; + clock-output-names = "clk_12m"; + }; + + clk_42m_d: clk_42m_d { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <32>; + clocks = <&clk_dpll>; + clock-output-names = "clk_42m_d"; + }; + + clk_56m_m: clk_56m_m { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <32>; + clocks = <&clk_mpll>; + clock-output-names = "clk_56m_m"; + }; + + clk_38m4_lte: clk_38m4_lte { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <32>; + clocks = <&clk_ltepll>; + clock-output-names = "clk_38m4_lte"; + }; + + clk_44m_lvds: clk_44m_lvds { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <32>; + clocks = <&clk_lvdspll>; + clock-output-names = "clk_44m_lvds"; + }; + + clk_614m4: clk_614m4 { + compatible = "sprd,fixed-factor-clock"; + #clock-cells = <0>; + clock-mult = <1>; + clock-div = <2>; + clocks = <&clk_ltepll>; + clock-output-names = "clk_614m4"; + }; + + clk_big_mcu: clk_big_mcu { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x20e00054 0x7 0x20e00038 0x0e>; /* select reg and divider reg */ + clocks = <&ext_26m>, <&clk_512m>, <&clk_768m>, <&clk_dpll>, <&clk_ltepll>, <&clk_twpll>, <&clk_mpll>; + clock-output-names = "clk_big_mcu"; + }; + + clk_little_mcu: clk_little_mcu { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x20e00054 0x38 0x20e00038 0x70>; /* select reg and divider reg */ + clocks = <&ext_26m>, <&clk_512m>, <&clk_768m>, <&clk_dpll>, <&clk_ltepll>, <&clk_twpll>, <&clk_mpll0>; + clock-output-names = "clk_little_mcu"; + }; + + clk_ca7_big_axi: clk_ca7_big_axi { + compatible = "sprd,divider-clock"; + #clock-cells = <0>; + reg = <0x20e00038 0x700>; /* divider reg */ + clocks = <&clk_big_mcu>; + clock-output-names = "clk_ca7_big_axi"; + }; + + clk_ca7_little_axi: clk_ca7_little_axi { + compatible = "sprd,divider-clock"; + #clock-cells = <0>; + reg = <0x20e00038 0x3800>; /* divider reg */ + clocks = <&clk_little_mcu>; + clock-output-names = "clk_ca7_little_axi"; + }; + + clk_ca7_big_dbg: clk_ca7_big_dbg { + compatible = "sprd,divider-clock"; + #clock-cells = <0>; + reg = <0x20e00038 0x1c000>; /* divider reg */ + clocks = <&clk_big_mcu>; + clock-output-names = "clk_ca7_big_dbg"; + }; + + clk_ca7_little_dbg: clk_ca7_little_dbg { + compatible = "sprd,divider-clock"; + #clock-cells = <0>; + reg = <0x20e00038 0xe0000>; /* divider reg */ + clocks = <&clk_little_mcu>; + clock-output-names = "clk_ca7_little_dbg"; + }; + + clk_gic: clk_gic { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x20e00060 0x3 0x20e00060 0xc 0x20e0005c 0x1>; /* select reg and divider reg and enable reg */ + clocks = <&ext_26m>, <&clk_384m>, <&clk_512m>, <&clk_ltepll>; + clock-output-names = "clk_gic"; + }; + + clk_pub_ahb: clk_pub_ahb { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x402d0020 0x3 0x402d0020 0x300>; /* select reg and divider reg */ + clocks = <&ext_26m>, <&ext_4m>, <&clk_96m>, <&clk_128m>; + clock-output-names = "clk_pub_ahb"; + }; + + clk_aon_apb: clk_aon_apb { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x402d0024 0x3 0x402d0024 0x300>; /* select reg and divider reg */ + clocks = <&ext_4m>, <&ext_26m>, <&clk_96m>, <&clk_128m>; + clock-output-names = "clk_aon_apb"; + }; + + clk_adi: clk_adi { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x402d0028 0x3 0x402e0000 0x10000>; /* select reg and enable reg */ + clocks = <&ext_26m>, <&ext_4m>, <&clk_38m4>, <&clk_51m2>; + clock-output-names = "clk_adi"; + }; + + clk_aux0: clk_aux0 { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x402e0088 0xf 0x402e0004 0x4>; /* select reg and enable reg */ + clocks = <&ext_32k>, <&ext_26m>, <&ext_26m_rf1>, <&ext_4m>, <&clk_42m_d>, <&clk_48m>, <&clk_56m_m>; + clock-output-names = "clk_aux0"; + }; + + clk_aux1: clk_aux1 { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x402d0088 0xf0 0x402e0004 0x8>; /* select reg and enable reg */ + clocks = <&ext_32k>, <&ext_26m>, <&ext_26m_rf1>, <&ext_4m>, <&clk_42m_d>, <&clk_48m>, <&clk_56m_m>, <&clk_38m4_lte>, <&clk_44m_lvds>; + clock-output-names = "clk_aux1"; + }; + + clk_aux2: clk_aux2 { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x402d0088 0xf00 0x402e0004 0x10>; /* select reg and enable reg */ + clocks = <&ext_32k>, <&ext_26m>, <&ext_26m_rf1>, <&ext_4m>, <&clk_42m_d>, <&clk_48m>, <&clk_56m_m>, <&clk_38m4_lte>, <&clk_44m_lvds>; + clock-output-names = "clk_aux2"; + }; + + clk_pwm0: clk_pwm0 { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x402d002c 0x3 0x402e0000 0x10>; /* select reg and enable reg */ + clocks = <&ext_32k>, <&ext_26m>, <&ext_26m_rf1>, <&clk_48m>; + clock-output-names = "clk_pwm0"; + }; + + clk_pwm1: clk_pwm1 { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x402d0030 0x3 0x402e0000 0x20>; /* select reg and enable reg */ + clocks = <&ext_32k>, <&ext_26m>, <&ext_26m_rf1>, <&clk_48m>; + clock-output-names = "clk_pwm1"; + }; + + clk_pwm2: clk_pwm2 { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x402d0034 0x3 0x402e0000 0x40>; /* select reg and enable reg */ + clocks = <&ext_32k>, <&ext_26m>, <&ext_26m_rf1>, <&clk_48m>; + clock-output-names = "clk_pwm2"; + }; + + clk_pwm3: clk_pwm3 { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x402d0038 0x3 0x402e0000 0x80>; /* select reg and enable reg */ + clocks = <&ext_32k>, <&ext_26m>, <&ext_26m_rf1>, <&clk_48m>; + clock-output-names = "clk_pwm3"; + }; + + clk_thm: clk_thm { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x402d0040 0x1 0x402e0004 0x2>; /* select reg and enable reg */ + clocks = <&ext_32k>, <&ext_1m>; + clock-output-names = "clk_thm"; + }; + + clk_mspi: clk_mspi { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x402d0044 0x3 0x402e0000 0x800000>; /* select reg and enable reg */ + clocks = <&ext_26m>, <&clk_51m2>, <&clk_76m8>, <&clk_96m>; + clock-output-names = "clk_mspi"; + }; + + clk_i2c: clk_i2c { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x402d0048 0x3 0x402e0000 0x80000000>; /* select reg and enable reg */ + clocks = <&ext_26m>, <&clk_48m>, <&clk_51m2>, <&clk_153m6>; + clock-output-names = "clk_i2c"; + }; + + clk_ca53_big_avs: clk_ca53_big_avs { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x402d006c 0x3 0x402e0004 0x10000000>; /* select reg and enable reg */ + clocks = <&ext_26m>, <&clk_48m>, <&clk_51m2>, <&clk_96m>; + clock-output-names = "clk_ca53_big_avs"; + }; + + clk_ca53_lit_avs: clk_ca53_lit_avs { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x402d0070 0x3 0x402e0004 0x20000000>; /* select reg and enable reg */ + clocks = <&ext_26m>, <&clk_48m>, <&clk_51m2>, <&clk_96m>; + clock-output-names = "clk_ca53_lit_avs"; + }; + + clk_gpu_avs: clk_gpu_avs { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x402d004c 0x3 0x402e0004 0x40>; /* select reg and enable reg */ + clocks = <&ext_26m>, <&clk_48m>, <&clk_51m2>, <&clk_96m>; + clock-output-names = "clk_gpu_avs"; + }; + + clk_audif: clk_audif { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x402d0050 0x3 0x402e0000 0x20000>; /* select reg and enable reg */ + clocks = <&ext_26m>, <&clk_38m4>, <&clk_51m2>; + clock-output-names = "clk_audif"; + }; + + clk_ca7_dap: clk_ca7_dap { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x402d0054 0x3 0x402e0000 0x40000000>; /* select reg and enable reg */ + clocks = <&ext_26m>, <&clk_76m8>, <&clk_128m>, <&clk_153m6>; + clock-output-names = "clk_ca7_dap"; + }; + + clk_ca7_ts: clk_ca7_ts { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x402d005c 0x3 0x402e0000 0x10000000>; /* select reg and enable reg */ + clocks = <&ext_32k>, <&ext_26m>, <&clk_128m>, <&clk_153m6>; + clock-output-names = "clk_ca7_ts"; + }; + + clk_djtag_tck: clk_djtag_tck { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x402d0060 0x1>; /* select reg */ + clocks = <&ext_26m>, <&ext_4m>; + clock-output-names = "clk_djtag_tck"; + }; + + clk_arm7_ahb: clk_arm7_ahb { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x402d0064 0x3 0x402d0064 0x300>; /* select reg and divider reg */ + clocks = <&ext_4m>, <&ext_26m>, <&clk_96m>, <&clk_128m>; + clock-output-names = "clk_arm7_ahb"; + }; + + clk_cci: clk_cci { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x402d0074 0x3 0x402d0074 0x300 0x402e0004 0x80>; /* select reg and divider reg and enable reg*/ + clocks = <&ext_26m>, <&clk_384m>, <&clk_512m>, <&clk_614m4>; + clock-output-names = "clk_cci"; + }; + + clk_cssys: clk_cssys { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x402d0078 0x3 0x402d0078 0x300 0x402e0004 0x40000000>; /* select reg and divider reg and enable reg*/ + clocks = <&ext_26m>, <&clk_384m>, <&clk_512m>, <&clk_614m4>; + clock-output-names = "clk_cssys"; + }; + + clk_ca5_ts: clk_ca5_ts { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x402d0068 0x3 0x402e0004 0x4000000>; /* select reg and enable reg */ + clocks = <&ext_32k>, <&ext_26m>, <&clk_128m>, <&clk_153m6>; + clock-output-names = "clk_ca5_ts"; + }; + + clk_disp_emc: clk_disp_emc { + compatible = "sprd,gate-clock"; + #clock-cells = <0>; + reg = <0x402e0004 0x800>; /* enable reg */ + clocks = <&clk_aon_apb>; + clock-output-names = "clk_disp_emc"; + }; + + clk_gsp_emc: clk_gsp_emc { + compatible = "sprd,gate-clock"; + #clock-cells = <0>; + reg = <0x402e0004 0x2000>; /* enable reg */ + clocks = <&clk_aon_apb>; + clock-output-names = "clk_gsp_emc"; + }; + + clk_ap_ahb: clk_ap_ahb { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x21500020 0x3>; /* select reg */ + clocks = <&ext_26m>, <&clk_76m8>, <&clk_128m>, <&clk_192m>; + clock-output-names = "clk_ap_ahb"; + }; + + clk_ap_apb: clk_ap_apb { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x21500024 0x3>; /* select reg */ + clocks = <&ext_26m>, <&clk_64m>, <&clk_96m>, <&clk_128m>; + clock-output-names = "clk_ap_apb"; + }; + + clk_gsp0: clk_gsp0 { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x21500028 0x3 0x20e00000 0x8 0x20e0304d 0x1>; /* select reg and ckg enable reg and prepare reg */ + clocks = <&clk_96m>, <&clk_153m6>, <&clk_192m>, <&clk_256m>; + clock-output-names = "clk_gsp0"; + }; + + clk_gsp1: clk_gsp1 { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x215000a0 0x3 0x20e00000 0x8 0x20e0304c 0x1>; /* select reg and ckg enable reg and prepare reg */ + clocks = <&clk_96m>, <&clk_153m6>, <&clk_256m>, <&clk_307m2>; + clock-output-names = "clk_gsp1"; + }; + + clk_dispc0: clk_dispc0 { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x2150002c 0x3 0x2150002c 0x700 0x20e00000 0x2>; /* select reg and divider reg and enable reg */ + clocks = <&clk_153m6>, <&clk_192m>, <&clk_256m>, <&clk_307m2>; + clock-output-names = "clk_dispc0"; + }; + + clk_dispc0_dbi: clk_dispc0_dbi { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x21500030 0x3 0x21500030 0x700>; /* select reg and divider reg */ + clocks = <&clk_128m>, <&clk_153m6>, <&clk_192m>, <&clk_256m>; + clock-output-names = "clk_dispc0_dbi"; + }; + + clk_dispc0_dpi: clk_dispc0_dpi { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x21500034 0x3 0x21500034 0xff00>; /* select reg and divider reg */ + clocks = <&clk_128m>, <&clk_153m6>, <&clk_192m>, <&clk_384m>; + clock-output-names = "clk_dispc0_dpi"; + }; + + clk_nandc_ecc: clk_nandc_ecc { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x21500038 0x1 0x20e00000 0x80000 0x20e00000 0x20000>; /* select reg and ckg enable reg and prepare reg */ + clocks = <&clk_153m6>, <&clk_192m>; + clock-output-names = "clk_nandc_ecc"; + }; + + clk_nandc_2x: clk_nandc_2x { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x20e03038 0x3 0x20e03038 0xc 0x20e00000 0xe0000>; /* select reg and divider reg and enable reg */ + clocks = <&clk_192m>, <&clk_256m>, <&clk_307m2>, <&clk_384m>; + clock-output-names = "clk_nandc_2x"; + }; + + clk_sdio0: clk_sdio0 { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x2150003c 0x3 0x2150003c 0x700 0x20e00000 0x100>; /* select reg and divider reg and enable reg */ + clocks = <&ext_26m>, <&clk_256m>, <&clk_307m2>, <&clk_192m>; + clock-output-names = "clk_sdio0"; + }; + + clk_sdio1: clk_sdio1 { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x21500040 0x3 0x20e00000 0x200>; /* select reg and enable reg */ + clocks = <&clk_48m>, <&clk_76m8>, <&clk_96m>, <&clk_128m>; + clock-output-names = "clk_sdio1"; + }; + + clk_sdio2: clk_sdio2 { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x21500044 0x3 0x20e00000 0x400>; /* select reg and enable reg */ + clocks = <&clk_48m>, <&clk_76m8>, <&clk_96m>, <&clk_128m>; + clock-output-names = "clk_sdio2"; + }; + + clk_emmc: clk_emmc { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x21500048 0x3 0x20e00000 0x800>; /* select reg and enable reg */ + clocks = <&ext_26m>, <&clk_256m>, <&clk_307m2>, <&clk_192m>; + clock-output-names = "clk_emmc"; + }; + + clk_otg_ref: clk_otg_ref { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x2150004c 0x1 0x20e00000 0x10>; /* select reg and enable reg */ + clocks = <&clk_12m>, <&clk_24m>; + clock-output-names = "clk_otg_ref"; + }; + + clk_hsic_ref: clk_hsic_ref { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x21500050 0x1 0x20e00000 0x4>; /* select reg and enable reg */ + clocks = <&clk_12m>, <&clk_24m>; + clock-output-names = "clk_hsic_ref"; + }; + + clk_uart0: clk_uart0 { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x21500054 0x3 0x21500054 0x700 0x71300000 0x2000>; /* select reg and divider reg and enable reg */ + clocks = <&ext_26m>, <&clk_48m>, <&clk_51m2>, <&clk_96m>; + clock-output-names = "clk_uart0"; + }; + + clk_uart1: clk_uart1 { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x21500058 0x3 0x21500058 0x700 0x71300000 0x4000>; /* select reg and divider reg and enable reg */ + clocks = <&ext_26m>, <&clk_48m>, <&clk_51m2>, <&clk_96m>; + clock-output-names = "clk_uart1"; + }; + + clk_uart2: clk_uart2 { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x2150005c 0x3 0x2150005c 0x700 0x71300000 0x8000>; /* select reg and divider reg and enable reg */ + clocks = <&ext_26m>, <&clk_48m>, <&clk_51m2>, <&clk_96m>; + clock-output-names = "clk_uart2"; + }; + + clk_uart3: clk_uart3 { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x21500060 0x3 0x21500060 0x700 0x71300000 0x10000>; /* select reg and divider reg and enable reg */ + clocks = <&ext_26m>, <&clk_48m>, <&clk_51m2>, <&clk_96m>; + clock-output-names = "clk_uart3"; + }; + + clk_uart4: clk_uart4 { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x21500064 0x3 0x21500064 0x700 0x71300000 0x20000>; /* select reg and divider reg and enable reg */ + clocks = <&ext_26m>, <&clk_48m>, <&clk_51m2>, <&clk_96m>; + clock-output-names = "clk_uart4"; + }; + + clk_i2c0: clk_i2c0 { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x21500068 0x3 0x21500068 0x700 0x71300000 0x100>; /* select reg and divider reg and enable reg */ + clocks = <&ext_26m>, <&clk_48m>, <&clk_51m2>, <&clk_153m6>; + clock-output-names = "clk_i2c0"; + }; + + clk_i2c1: clk_i2c1 { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x2150006c 0x3 0x2150006c 0x700 0x71300000 0x200>; /* select reg and divider reg and enable reg */ + clocks = <&ext_26m>, <&clk_48m>, <&clk_51m2>, <&clk_153m6>; + clock-output-names = "clk_i2c1"; + }; + + clk_i2c2: clk_i2c2 { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x21500070 0x3 0x21500070 0x700 0x71300000 0x400>; /* select reg and divider reg and enable reg */ + clocks = <&ext_26m>, <&clk_48m>, <&clk_51m2>, <&clk_153m6>; + clock-output-names = "clk_i2c2"; + }; + + clk_i2c3: clk_i2c3 { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x21500074 0x3 0x21500074 0x700 0x71300000 0x800>; /* select reg and divider reg and enable reg */ + clocks = <&ext_26m>, <&clk_48m>, <&clk_51m2>, <&clk_153m6>; + clock-output-names = "clk_i2c3"; + }; + + clk_i2c4: clk_i2c4 { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x21500078 0x3 0x21500078 0x700 0x71300000 0x1000>; /* select reg and divider reg and enable reg */ + clocks = <&ext_26m>, <&clk_48m>, <&clk_51m2>, <&clk_153m6>; + clock-output-names = "clk_i2c4"; + }; + + clk_spi0: clk_spi0 { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x2150007c 0x3 0x2150007c 0x700 0x71300000 0x20>; /* select reg and divider reg and enable reg */ + clocks = <&ext_26m>, <&clk_96m>, <&clk_153m6>, <&clk_192m>; + clock-output-names = "clk_spi0"; + }; + + clk_spi1: clk_spi1 { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x21500080 0x3 0x21500080 0x700 0x71300000 0x40>; /* select reg and divider reg and enable reg */ + clocks = <&ext_26m>, <&clk_96m>, <&clk_153m6>, <&clk_192m>; + clock-output-names = "clk_spi1"; + }; + + clk_spi2: clk_spi2 { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x21500084 0x3 0x21500084 0x700 0x71300000 0x80>; /* select reg and divider reg and enable reg */ + clocks = <&ext_26m>, <&clk_96m>, <&clk_153m6>, <&clk_192m>; + clock-output-names = "clk_spi2"; + }; + + clk_iis0: clk_iis0 { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x21500088 0x3 0x21500088 0x700 0x71300000 0x2>; /* select reg and divider reg and enable reg */ + clocks = <&ext_26m>, <&clk_128m>, <&clk_153m6>; + clock-output-names = "clk_iis0"; + }; + + clk_iis1: clk_iis1 { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x2150008c 0x3 0x2150008c 0x700 0x71300000 0x4>; /* select reg and divider reg and enable reg */ + clocks = <&ext_26m>, <&clk_128m>, <&clk_153m6>; + clock-output-names = "clk_iis1"; + }; + + clk_iis2: clk_iis2 { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x21500090 0x3 0x21500090 0x700 0x71300000 0x8>; /* select reg and divider reg and enable reg */ + clocks = <&ext_26m>, <&clk_128m>, <&clk_153m6>; + clock-output-names = "clk_iis2"; + }; + + clk_iis3: clk_iis3 { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x21500094 0x3 0x21500094 0x700 0x71300000 0x10>; /* select reg and divider reg and enable reg */ + clocks = <&ext_26m>, <&clk_128m>, <&clk_153m6>; + clock-output-names = "clk_iis3"; + }; + + clk_zipenc: clk_zipenc { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x21500098 0x3 0x20e00000 0x100000>; /* select reg and enable reg */ + clocks = <&clk_96m>, <&clk_153m6>, <&clk_192m>, <&clk_256m>; + clock-output-names = "clk_zipenc"; + }; + + clk_zipdec: clk_zipdec { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x2150009c 0x3 0x20e00000 0x200000>; /* select reg and enable reg */ + clocks = <&clk_96m>, <&clk_153m6>, <&clk_192m>, <&clk_256m>; + clock-output-names = "clk_zipdec"; + }; + + clk_gpu_axi: clk_gpu_axi { + compatible = "sprd,gate-clock"; + #clock-cells = <0>; + reg = <0x402e0000 0x8000000 0x402b0021 0x2000000>;/* enable reg and prepare reg */ + clocks = <&clk_aon_apb>; + clock-output-names = "clk_gpu_axi"; + }; + + clk_gpu: clk_gpu { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x60100004 0x7 0x60100004 0x30>; /* select reg and divider reg */ + clocks = <&clk_153m6>, <&clk_192m>, <&clk_256m>, <&clk_307m2>, <&clk_384m>, <&clk_gpll>; + clock-output-names = "clk_gpu"; + }; + + clk_mm: clk_mm { + compatible = "sprd,gate-clock"; + #clock-cells = <0>; + reg = <0x402e0000 0x2000000 0x402b001d 0x2000000>; /* enable reg and prepare reg */ + clocks = <&clk_aon_apb>; + clock-output-names = "clk_mm"; + }; + + clk_coda7_cc: clk_coda7_cc { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x62000008 0x30 0x62000004 0x2 0x402e0004 0x80000000>; /* select reg and ckg enable reg */ + clocks = <&clk_76m8>, <&clk_128m>, <&clk_153m6>, <&clk_192m>; + clock-output-names = "clk_coda7_cc"; + mm_domain; + }; + + clk_coda7_axi: clk_coda7_axi { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x62000008 0x300 0x62000004 0x1 0x402e0004 0x80000000>;/* select reg and ckg enable reg */ + clocks = <&clk_76m8>, <&clk_128m>, <&clk_153m6>, <&clk_192m>; + clock-output-names = "clk_coda7_axi"; + mm_domain; + }; + + clk_coda7_apb: clk_coda7_apb { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x62000008 0x3 0x62000004 0x10 0x402e0004 0x80000000>; /* select reg*/ + clocks = <&ext_26m>, <&clk_76m8>, <&clk_96m>, <&clk_128m>; + clock-output-names = "clk_coda7_apb"; + mm_domain; + }; + + clk_mm_ahb: clk_mm_ahb { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x60e00020 0x3>; /* select reg */ + clocks = <&ext_26m>, <&clk_96m>, <&clk_128m>, <&clk_153m6>; + clock-output-names = "clk_mm_ahb"; + mm-domain; + }; + + clk_mm_axi: clk_mm_axi { + compatible = "sprd,gate-clock"; + #clock-cells = <0>; + reg = <0x60d00008 0x80>; /* enable reg */ + clocks = <&clk_mm>; + clock-output-names = "clk_mm_axi"; + mm-domain; + }; + + clk_mm_mtx_axi: clk_mm_mtx_axi { + compatible = "sprd,gate-clock"; + #clock-cells = <0>; + reg = <0x60d00008 0x100>; /* enable reg */ + clocks = <&clk_mm_axi>; + clock-output-names = "clk_mm_mtx_axi"; + mm-domain; + }; + + clk_mmu: clk_mmu { + compatible = "sprd,gate-clock"; + #clock-cells = <0>; + reg = <0x60d00000 0x80>; /* enable reg */ + clocks = <&clk_mm_ahb>; + clock-output-names = "clk_mmu"; + mm-domain; + }; + + clk_mm_ckg: clk_mm_ckg { + compatible = "sprd,gate-clock"; + #clock-cells = <0>; + reg = <0x60d00000 0x40>; /* enable reg */ + clocks = <&clk_mm_ahb>; + clock-output-names = "clk_mm_ckg"; + mm-domain; + }; + + clk_jpg: clk_jpg { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x60e00038 0x3 0x60d00008 0x40 0x60d00000 0x20>; /* select reg and ckg enable reg and prepare reg */ + clocks = <&clk_96m>, <&clk_128m>, <&clk_256m>, <&clk_312m>; + clock-output-names = "clk_jpg"; + mm-domain; + }; + + clk_vpp: clk_vpp { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x60e0003c 0x3 0x60d00008 0x200 0x60d00000 0x100>; /* select reg and ckg enable reg and prepare reg */ + clocks = <&clk_96m>, <&clk_128m>, <&clk_153m6>, <&clk_256m>; + clock-output-names = "clk_vpp"; + mm-domain; + }; + + clk_csi: clk_csi { + compatible = "sprd,gate-clock"; + #clock-cells = <0>; + reg = <0x60d00008 0x2 0x60d00000 0x10>; /* enable reg and prepare reg */ + clocks = <&clk_mm_ahb>; + clock-output-names = "clk_csi"; + mm-domain; + }; + + clk_dcam_mipi: clk_dcam_mipi { + compatible = "sprd,gate-clock"; + #clock-cells = <0>; + reg = <0x60d00008 0x1>; /* enable reg */ + clocks = <&clk_csi>; + clock-output-names = "clk_dcam_mipi"; + mm-domain; + }; + + clk_vsp: clk_vsp { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x60e00030 0x3 0x60d00008 0x20 0x60d00000 0x8>; /* select reg and ckg enable reg and prepare reg */ + clocks = <&clk_96m>, <&clk_128m>, <&clk_256m>, <&clk_307m2>; + clock-output-names = "clk_vsp"; + mm-domain; + }; + + clk_isp: clk_isp { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x60e00034 0x3 0x60d00008 0x10 0x60d00000 0x4>; /* select reg and ckg enable reg and prepare reg */ + clocks = <&clk_128m>, <&clk_256m>, <&clk_384m>, <&clk_usbpll>; + clock-output-names = "clk_isp"; + mm-domain; + }; + + clk_ccir: clk_ccir { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x60e00028 0x10000 0x60d00000 0x2>; /* select reg and enable reg */ + clocks = <&clk_24m>, <&clk_pad>; + clock-output-names = "clk_ccir"; + mm-domain; + }; + + clk_sensor: clk_sensor { + compatible = "sprd,composite-dev-clock"; + #clock-cells = <0>; + reg = <0x60e00024 0x3 0x60e00024 0x700 0x60d00008 0x4>; /* select reg and divider reg and enable reg */ + clocks = <&ext_26m>, <&clk_48m>, <&clk_76m8>, <&clk_96m>; + clock-output-names = "clk_sensor"; + mm-domain; + }; + + clk_dcam: clk_dcam { + compatible = "sprd,muxed-clock"; + #clock-cells = <0>; + reg = <0x60e0002c 0x3 0x60d00008 0x8 0x60d00000 0x1>; /* select reg and ckg enable reg and prepare reg */ + clocks = <&clk_96m>, <&clk_128m>, <&clk_256m>, <&clk_312m>; + clock-output-names = "clk_dcam"; + mm-domain; + }; + }; + +}; diff --git a/arch/arm64/boot/dts/skeleton.dtsi b/arch/arm64/boot/dts/skeleton.dtsi new file mode 100644 index 00000000..f9988cd7 --- /dev/null +++ b/arch/arm64/boot/dts/skeleton.dtsi @@ -0,0 +1,18 @@ +/* + * Skeleton device tree; the bare minimum needed to boot; just include and + * add a compatible value. The bootloader will typically populate the memory + * node. + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + chosen { }; + aliases { }; + memory { + #address-cells = <1>; + #size-cells = <1>; + device_type = "memory"; + reg = <0 0>; + }; +}; diff --git a/arch/arm64/boot/dts/sprd-battery.dtsi b/arch/arm64/boot/dts/sprd-battery.dtsi new file mode 100644 index 00000000..6be651d5 --- /dev/null +++ b/arch/arm64/boot/dts/sprd-battery.dtsi @@ -0,0 +1,90 @@ +/* +* Copyright (C) 2013 Spreadtrum Communication Incorporated +* http://www.spreadtrum.com/ +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +*/ + +/* This is the sprd battery default DTS */ + +/ { + sprd_battery: sprd_battery { + compatible = "sprd,sprd-battery"; + gpios = <&a_eic_gpio 0 0 /* chg int */ + &a_eic_gpio 4 0 /* cv state */ + &a_eic_gpio 6 0>; /* chg ovi */ + chg-end-vol-h = <4225>; + chg-end-vol-pure = <4200>; + chg-end-vol-l = <4190>; + chg-bat-safety-vol = <4280>; + rechg-vol = <4131>; + adp-cdp-cur = <700>; + adp-dcp-cur = <700>; + adp-sdp-cur = <450>; + ovp-stop = <6500>; + ovp-restart = <5800>; + chg-timeout = <21600>; + chgtimeout-show-full = <0>; + chg-rechg-timeout = <5400>; + chg-cv-timeout = <3600>; + chg-eoc-level = <3>; + cccv-default = <0>; + chg-end-cur = <80>; + otp-high-stop = <1600>; + otp-high-restart = <1550>; + otp-low-stop = <950>; + otp-low-restart = <1000>; + chg-polling-time = <30>; + chg-polling-time-fast = <1>; + bat-polling-time = <15>; + bat-polling-time-fast = <15>; + cap-one-per-time = <30>; + cap-valid-range-poweron = <0>; + temp-support = <0>; + temp-adc-ch = <3>; + temp-adc-scale = <1>; + temp-adc-sample-cnt = <15>; + temp-table-mode = <1>; + temp-comp-res = <30>; /*30mohm,if temp-table-mode = <1>, use it*/ + temp-tab-size = <19>; + temp-tab-val = <1084 1072 1055 1033 1008 977 + 938 897 850 798 742 686 + 628 571 513 459 410 362 318>; + temp-tab-temp = <750 800 850 900 950 1000 /* temperature + 1000,750 = 1000 + (-250)*/ + 1050 1100 1150 1200 1250 1300 + 1350 1400 1450 1500 1550 1600 1650>; + fgu-mode = <1>; + alm-soc = <5>; + alm-vol = <3600>; + soft-vbat-uvlo = <3100>; + rint = <250>; + cnom = <1500>; + rsense-real = <215>; + rsense-spec = <200>; + relax-current = <50>; + fgu-cal-ajust = <0>; + ocv-tab-size = <21>; + ocv-tab-vol = <4185 4113 4066 4022 3983 3949 3917 3889 3864 3835 3805 3787 3777 3773 3770 3765 3752 3724 3680 3605 3400>; + ocv-tab-cap = <100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0>; + cnom-temp-tab = <1020 1800 /*value = 1000 + temp*/ + 1010 1300 + 1000 1070 + 990 1000>; + rint-temp-tab = <1020 200 /*value = 1000 + temp*/ + 1010 450 + 1000 650 + 990 1100>; + sprd_chg: sprd_chg{ + compatible = "sprd,sprd_chg"; + interrupt-parent = <&gic>; + interrupts = <0 120 0x0>; + }; + sprd_fgu: sprd_fgu{ + compatible = "sprd,sprd_fgu"; + interrupt-parent = <&adi>; + interrupts = <4 0x0>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/sprd-scx35lt8_common.dtsi b/arch/arm64/boot/dts/sprd-scx35lt8_common.dtsi new file mode 100644 index 00000000..59164f98 --- /dev/null +++ b/arch/arm64/boot/dts/sprd-scx35lt8_common.dtsi @@ -0,0 +1,1269 @@ +/* +* Copyright (C) 2013 Spreadtrum Communication Incorporated +* http://www.spreadtrum.com/ +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +*/ + +/include/ "sc2723-regulators.dtsi" +/include/ "sprd-sound.dtsi" +/include/ "scx35lt8-clocks.dtsi" + +/ { + model = "scx35l64"; + compatible = "sprd,SharkLT8"; + sprd,sc-id = <8830 1 0x20000>; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + core1 { + cpu = <&CPU5>; + }; + core2 { + cpu = <&CPU6>; + }; + core3 { + cpu = <&CPU7>; + }; + }; + }; + + CPU0: cpu@530000 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530000>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD>; + clocks = <&clk_little_mcu>; + cpu0-supply = <&vddarm>; + operating-points = < + /* kHz uV */ + 1000000 900000 + 800000 900000 + 750000 900000 + 600000 900000 + 533000 900000 + 400000 900000 + 200000 900000 + >; + }; + + CPU1: cpu@530001 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530001>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD>; + }; + + CPU2: cpu@530002 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530002>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD>; + }; + + CPU3: cpu@530003 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530003>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD>; + }; + + CPU4: cpu@530100 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530100>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD>; + clocks = <&clk_big_mcu>; + cpu0-supply = <&vddbigarm>; + operating-points = < + /* kHz uV */ + 1500000 1050000 + 1420000 1050000 + 1350000 1050000 + 1200000 900000 + 1100000 900000 + 1000000 900000 + 960000 900000 + >; + }; + + CPU5: cpu@530101 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530101>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD>; + }; + + CPU6: cpu@530102 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530102>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD>; + }; + + CPU7: cpu@530103 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530103>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD>; + }; + + idle-states{ + entry-method = "arm,psci"; + LIGHT_SLEEP: light_sleep { + compatible = "arm,idle-state"; + exit-latency-us = <10>; + min-residency-us = <50>; + entry-method-param = <0x00000001>; + }; + CORE_PD: core_pd { + compatible = "arm,idle-state"; + exit-latency-us = <1070>; + min-residency-us = <5000>; + entry-method-param = <0x00010002>; + }; + CLUSTER_PD: cluster_pd { + compatible = "arm,idle-state"; + exit-latency-us = <2000>; + min-residency-us = <8000>; + entry-method-param = <0x01010003>; + }; + TOP_PD: top_pd { + compatible = "arm,idle-state"; + exit-latency-us = <2300>; + min-residency-us = <10000>; + entry-method-param = <0x01010004>; + }; + DEEP_SLEEP: deep_sleep { + compatible = "arm,idle-state"; + exit-latency-us = <4100>; + min-residency-us = <6500>; + entry-method-param = <0x01010005>; + }; + }; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + lcd0 = &fb0; + hwspinlock0 = &hwspinlock0; + hwspinlock1 = &hwspinlock1; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 92 4>, + <0 93 4>, + <0 94 4>, + <0 95 4>; + }; + + psci { + compatible = "arm,psci"; + method = "smc"; + cpu_on = <0xc4000003>; + cpu_off = <0x84000002>; + cpu_suspend = <0xc4000001>; + }; + + gic: interrupt-controller@12001000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0x12001000 0 0x1000>, + <0 0x12002000 0 0x1000>; + }; + + intc:interrupt-controller@71400000 { + compatible = "sprd,intc"; + #interrupt-cells = <0>; + interrupt-controller; + reg = <0 0x71400000 0 0x1000>, + <0 0x71500000 0 0x1000>, + <0 0x71600000 0 0x1000>, + <0 0x71700000 0 0x1000>, + <0 0x40200000 0 0x1000>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, + <1 14 0xff01>, + <1 11 0xff01>, + <1 10 0xff01>; + clock-frequency = <26000000>; + }; + + sprd_timer { + compatible = "sprd,sharkl64-timer"; + reg = <0 0x40050000 0 0x20>; /*aon GPTIMER0 */ + interrupts = <0 28 0x0>; + clock-frequency = <32768>; + }; + + sprd_ap_system_timer { + reg = <0 0x40230000 0 0x20>; + interrupts = <0 31 0x0>; + }; + + clock: clockdevice { + compatible = "sprd,scx35l64-clocks"; + #clock-cells = <1>; + }; + + d_eic_gpio: gpio@40210000 { + compatible = "sprd,d-eic-gpio"; + reg = <0 0x40210000 0 0x1000>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-cells = <2>; + gpiobase = <288>; + ngpios = <16>; + interrupts = <0 37 0x0>; + }; + + d_gpio_gpio: gpio@40280000 { + compatible = "sprd,d-gpio-gpio"; + reg = <0 0x40280000 0 0x1000>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-cells = <2>; + gpiobase = <0>; + ngpios = <256>; + interrupts = <0 35 0x0>; + }; + + uart0: uart@70000000 { + compatible = "sprd,serial"; + interrupts = <0 2 0xf04>; + reg = <0 0x70000000 0 0x1000>; + clock-names = "clk_uart0"; + clocks = <&clock 60>; + sprdclk = <48000000>; + sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP"; + }; + + uart1: uart@70100000 { + compatible = "sprd,serial"; + interrupts = <0 3 0xf04>; + reg = <0 0x70100000 0 0x1000>; + clock-names = "clk_uart1"; + clocks = <&clock 61>; + sprdclk = <26000000>; + sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP"; + }; + + uart2: uart@70200000 { + compatible = "sprd,serial"; + interrupts = <0 4 0xf04>; + reg = <0 0x70200000 0 0x1000>; + clock-names = "clk_uart2"; + clocks = <&clock 62>; + sprdclk = <26000000>; + sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP"; + }; + + uart3: uart@70300000 { + compatible = "sprd,serial"; + interrupts = <0 5 0xf04>; + reg = <0 0x70300000 0 0x1000>; + clock-names = "clk_uart3"; + clocks = <&clock 63>; + sprdclk = <26000000>; + sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP"; + }; + + hwspinlock0: hwspinlock0@20c00000{ + compatible = "sprd,sprd-hwspinlock"; + reg = <0 0x20c00000 0 0x1000>; + }; + + hwspinlock1: hwspinlock1@40060000{ + compatible = "sprd,sprd-hwspinlock"; + reg = <0 0x40060000 0 0x1000>; + status = "ok"; + }; + + watchdog { + compatible = "sprd,watchdog"; + reg = <0 0X40290000 0 0x1000>; + }; + + sdios{ + #address-cells = <2>; + #size-cells = <2>; + ranges; + sdio3: sdio@20600000{ + compatible = "sprd,sdhost-3.0"; + reg = <0 0x20600000 0 0x1000>; + interrupts = <0 60 0x0>; + sprd,name = "sdio_emmc"; + /*detect_gpio = <-1>; */ + SD_Pwr_Name = "vddemmccore"; + _1_8V_signal_Name = "vddgen0"; + signal_default_Voltage = <1800000>; + ocr_avail = <0x00040000>; + clocks = <&clk_emmc>, <&clk_192m>; + base_clk = <192000000>; + caps = <0xC00F8D47>; + caps2 = <0x202>; + pm_caps = <0x4>; + writeDelay = <0x3E>; + readPosDelay = <0xA>; + readNegDelay = <0xA>; + }; + + sdio0: sdio@20300000{ + compatible = "sprd,sdhost-3.0"; + reg = <0 0x20300000 0 0x1000>; + interrupts = <0 57 0x0>; + sprd,name = "sdio_sd"; + detect_gpio = <35>; + SD_Pwr_Name = "vddsdcore"; + _1_8V_signal_Name = "vddsdio"; + signal_default_Voltage = <3000000>; + ocr_avail = <0x00040000>; + clocks = <&clk_sdio0>, <&clk_192m>; + base_clk = <192000000>; + caps = <0xC0020407>; + caps2 = <0x200>; + pm_caps = <0x4>; + writeDelay = <0x3>; + readPosDelay = <0x3>; + readNegDelay = <0x3>; + }; + + + sdio1: sdio@20400000{ + compatible = "sprd,sdhost-3.0"; + reg = <0 0x20400000 0 0x1000>; + interrupts = <0 58 0x0>; + sprd,name = "sdio_wifi"; + /* detect_gpio = <-1>; */ + /* SD_Pwr_Name = "vddsdcore"; */ + /* _1_8V_signal_Name = "vddsdio";*/ + /* signal_default_Voltage = <3000000>; */ + ocr_avail = <0x00360080>; + clocks = <&clk_sdio1>, <&clk_76m8>; + base_clk = <76000000>; + caps = <0xC00FA407>; + caps2 = <0x0>; + pm_caps = <0x5>; + writeDelay = <0x03>; + readPosDelay = <0x03>; + readNegDelay = <0x03>; + }; + }; + + adic:adic { + compatible = "sprd,adi"; + reg = <0 0x40030000 0 0x10000>; + }; + + adi: adi_bus { + compatible = "sprd,adi-bus"; + interrupts = <0 38 0x0>; + reg = <0 0x40038000 0 0x1000>; + interrupt-controller; + sprd,irqnums = <11>; + #interrupt-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x100 0 0x40038100 0x80>, + <0x440 0 0x40038440 0x40>, + <0x800 0 0x40038800 0xff>; + + a_eic_gpio: gpio@100{ + compatible = "sprd,a-eic-gpio"; + reg = <0x100 0x80>; /* adi reg */ + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-cells = <2>; + gpiobase = <304>; + ngpios = <16>; + interrupt-parent = <&adi>; + interrupts = <5 0x0>; /* ext irq 5 */ + }; + + rtc@80{ + compatible = "sprd,rtc"; + reg = <0X80 0x80>; + interrupt-parent = <&adi>; + interrupts = <2 0x0>; + }; + }; + + usb: usb@20200000{ + compatible = "sprd,usb"; + interrupts = <0 55 0x0>; + ngpios = <1>; + gpios = <&a_eic_gpio 0 0>; + reg = <0 0x20200000 0 0x1000>; + tune_value = <0x0005af33>; + usb-supply = <&vddusb>; + #address-cells = <1>; + #size-cells = <0>; + }; + + sprd_thermal: thermal@402F0000{ + compatible = "sprd,sprd-thermal"; + id = <0>; + interrupts = <0 26 0x0>; + reg = <0 0x402F0000 0 0x1000>; + trip_points_active = <90 100>; + trip_points_lowoff = <0 75>; + trip_points_critical = <100>; + trip_num = <3>; + }; + + sprd_thermal1:thermal1@402F0000 { + compatible = "sprd,sprd-thermal"; + id = <1>; + interrupts = <0 26 0x0>; + reg = <0 0x402F0000 0 0x1000>; + trip_points_active = <100>; + trip_points_lowoff = <90>; + trip_points_critical = <100>; + trip_num = <2>; + }; + + sprd_thermal2: thermal@40038280{ + compatible = "sprd,sprd-thermal"; + id = <2>; + interrupt-parent = <&adi>; + interrupts = <9 0x0>; + reg = <0 0x40038280 0 0x1000>; + trip_points_active = <110>; + trip_points_lowoff = <90>; + trip_points_critical = <110>; + trip_num = <2>; + }; + + adc: adc@40038300{ + compatible = "sprd,sprd-adc"; + reg = <0x40038300 0x1000>; + }; + + i2c0: i2c@70500000{ + compatible = "sprd,i2c"; + interrupts = <0 11 0x0>; + reg = <0 0x70500000 0 0x1000>; + clock-names = "clk_i2c0"; + clocks = <&clk_i2c0>; + #address-cells = <1>; + #size-cells = <0>; + }; + little_cpu_cooling{ + compatible = "sprd,sprd-cpu-cooling"; + id = <0>; + cluster = <0>; + max_freq = <1000000 1000000>; + max_core = <4 1>; + state_num = <2>; + }; + big_cpu_cooling{ + compatible = "sprd,sprd-cpu-cooling"; + id = <1>; + cluster = <1>; + max_freq = <1500000 1200000>; + max_core = <4 0>; + state_num = <2>; + }; + + i2c1: i2c@70600000{ + compatible = "sprd,i2c"; + interrupts = <0 12 0x0>; + reg = <0 0x70600000 0 0x1000>; + clock-names = "clk_i2c1"; + clocks = <&clk_i2c1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@70700000{ + compatible = "sprd,i2c"; + interrupts = <0 13 0x0>; + reg = <0 0x70700000 0 0x1000>; + clock-names = "clk_i2c2"; + clocks = <&clk_i2c2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c3: i2c@70800000{ + compatible = "sprd,i2c"; + interrupts = <0 14 0x0>; + reg = <0 0x70800000 0 0x1000>; + clock-names = "clk_i2c3"; + clocks = <&clk_i2c3>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c4: i2c@70900000{ + compatible = "sprd,i2c"; + interrupts = <0 15 0x0>; + reg = <0 0x70900000 0 0x1000>; + clock-names = "clk_i2c4"; + clocks = <&clk_i2c4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi0: spi0@70a00000{ + compatible = "sprd,sprd-spi"; + interrupts = <0 7 0x0>; + reg = <0 0x70a00000 0 0x1000>; + clock-names = "clk_spi0"; + }; + + spi1: spi1@70b00000{ + compatible = "sprd,sprd-spi"; + interrupts = <0 8 0x0>; + reg = <0 0x70b00000 0 0x1000>; + clock-names = "clk_spi1"; + }; + + spi2: spi2@70c00000{ + compatible = "sprd,sprd-spi"; + interrupts = <0 9 0x0>; + reg = <0 0x70c00000 0 0x1000>; + clock-names = "clk_spi2"; + }; + + dma: dma-controller@20100000 { + compatible = "sprd,sharkl64-dma"; + #dma-cells = <1>; + #dma-channels = <64>; + sprd,aon-offset = <32>; + reg = <0 0x20100000 0 0x4000>, /* ap reg */ + <0 0x40100000 0 0x4000>; /* aon reg */ + interrupts = <0 50 0x0>, /* ap int */ + <0 70 0x0>; /* aon int */ + }; + + sprd-io-base { + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 1 0>; + ahb { + compatible = "sprd,ahb"; + reg = <0 0x20e00000 0 0x40000>; + }; + apbckg { + compatible = "sprd,apbckg"; + reg = <0 0x21500000 0 0x1000>; + }; + hwlock0 { + compatible = "sprd,hwlock0"; + reg = <0 0x20d00000 0 0x1000>; + }; + pub_apb { + compatible = "sprd,pub_apb"; + reg = <0 0x30020000 0 0x10000>; + }; + aon_apb { + compatible = "sprd,aon_apb"; + reg = <0 0x402e0000 0 0x40000>; + }; + pmu_apb { + compatible = "sprd,pmu_apb"; + reg = <0 0x402b0000 0 0x40000>; + }; + mm_ahb { + compatible = "sprd,mm_ahb"; + reg = <0 0x60d00000 0 0x10000>; + }; + mm_clk { + compatible = "sprd,mm_clk"; + reg = <0 0x60e00000 0 0x1000>; + }; + codecahb { + compatible = "sprd,codecahb"; + reg = <0 0x62000000 0 0x1000>; + }; + ap_ckg { + compatible = "sprd,ap_ckg"; + reg = <0 0x71200000 0 0x40000>; + }; + ap_apb { + compatible = "sprd,ap_apb"; + reg = <0 0x71300000 0 0x40000>; + }; + gpu_apb { + compatible = "sprd,gpu_apb"; + reg = <0 0x60100000 0 0x1000>; + }; + adi { + compatible = "sprd,adi"; + reg = <0 0x40030000 0 0x10000>; + }; + adi_slave { + compatible = "sprd,adi_slave"; + reg = <0 0x40038000 0 0x1000>; + }; + + mailbox { + compatible = "sprd,mailbox"; + reg = <0 0x400a0000 0 0x10000>; + }; + uart0 { + compatible = "sprd,uart0"; + reg = <0 0x70000000 0 0x1000>; + }; + uart1 { + compatible = "sprd,uart1"; + reg = <0 0x70100000 0 0x1000>; + }; + uart2 { + compatible = "sprd,uart2"; + reg = <0 0x70200000 0 0x1000>; + }; + uart3 { + compatible = "sprd,uart3"; + reg = <0 0x70300000 0 0x1000>; + }; + uart4 { + compatible = "sprd,uart4"; + reg = <0 0x70400000 0 0x1000>; + }; + axibm0 { + compatible = "sprd,axibm0"; + reg = <0 0x30040000 0 0x20000>; + interrupts = <0 86 0x0>; + }; + d_eic_gpio { + compatible = "sprd,d-eic-gpio"; + reg = <0 0x40210000 0 0x1000>; + }; + d_gpio_gpio { + compatible = "sprd,d-gpio-gpio"; + reg = <0 0x40280000 0 0x1000>; + }; + aon_dma { + compatible = "sprd,aon_dma"; + reg = <0 0x40100000 0 0x1000>; + interrupts = <0 50 0x0>; + }; + pwm { + compatible = "sprd,pwm"; + reg = <0 0x40260000 0 0x1000>; + }; + core { + compatible = "sprd,core"; + reg = <0 0x12000000 0 0x10000>; + }; + int { + compatible = "sprd,int"; + reg = <0 0x40200000 0 0x1000>; + }; + intc0 { + compatible = "sprd,intc0"; + reg = <0 0x71400000 0 0x1000>; + }; + intc1 { + compatible = "sprd,intc1"; + reg = <0 0x71500000 0 0x1000>; + }; + intc2 { + compatible = "sprd,intc2"; + reg = <0 0x71600000 0 0x1000>; + }; + intc3 { + compatible = "sprd,intc3"; + reg = <0 0x71700000 0 0x1000>; + }; + send_mbox { + compatible = "sprd,send_mbox"; + reg = <0 0x400a0000 0 0x1000>; + }; + recv_mbox { + compatible = "sprd,recv_mbox"; + reg = <0 0x400a8000 0 0x1000>; + }; + uidefuse { + compatible = "sprd,uidefuse"; + reg = <0 0x40240000 0 0x1000>; + }; + isp { + compatible = "sprd,isp"; + reg = <0 0x60a00000 0 0x8000>; + }; + csi2 { + compatible = "sprd,csi2"; + reg = <0 0x60c00000 0 0x1000>; + }; + ipi { + compatible = "sprd,ipi"; + reg = <0 0x402c0000 0 0x1000>; + }; + dcam { + compatible = "sprd,dcam"; + reg = <0 0x60800000 0 0x10000>; + }; + syscnt { + compatible = "sprd,syscnt"; + reg = <0 0x40230000 0 0x1000>; + }; + dma0 { + compatible = "sprd,dma0"; + reg = <0 0x20100000 0 0x4000>; + }; + pub { + compatible = "sprd,pub"; + reg = <0 0x30020000 0 0x10000>; + }; + pin { + compatible = "sprd,pin"; + reg = <0 0x402a0000 0 0x1000>; + }; + aonckg { + compatible = "sprd,aonckg"; + reg = <0 0x402d0000 0 0x1000>; + }; + lpddr2 { + compatible = "sprd,lpddr2"; + reg = <0 0x30000000 0 0x1000>; + }; + }; + + sprd_dcam { + compatible = "sprd,sprd_dcam"; + interrupts = <0 45 0>; + reg = <0 0x60800000 0 0x100000>; + clock-names = "clk_mm_i","clk_dcam"; + clocks = <&clk_mm>, <&clk_dcam>; + }; + + sprd_scale { + compatible = "sprd,sprd_scale"; + }; + + sprd_rotation { + compatible = "sprd,sprd_rotation"; + }; + + l_sprd_sensor: sprd_sensor { + compatible = "sprd,sprd_sensor"; + reg = <0 0x60c00000 0 0x100000>; + clock-names ="clk_mm_i","clk_sensor","clk_ccir","clk_dcam","clk_dcam_mipi"; + clocks = <&clk_mm>,<&clk_sensor>,<&clk_ccir>,<&clk_dcam>,<&clk_dcam_mipi>; + }; + + sprd_isp { + compatible = "sprd,sprd_isp"; + reg = <0 0x60a00000 0 0x100000>; + clock-names = "clk_mm_i","clk_isp"; + clocks = <&clk_mm>, <&clk_isp>; + }; + + sprd_dma_copy { + compatible = "sprd,sprd_dma_copy"; + }; + + fb0: fb@20800000 { + compatible = "sprd,sprdfb"; + reg = <0 0x20800000 0 0x1000>, + <0 0x21800000 0 0x1000>; + interrupts = <0 46 0x0>, + <0 48 0x0>, + <0 49 0x0>; + clock-names = "dispc_clk_parent", "dispc_dbi_clk_parent", "dispc_dpi_clk_parent", "dispc_emc_clk_parent", "dispc_clk", "dispc_dbi_clk", "dispc_dpi_clk", "dispc_emc_clk", "fb_spi_clock", "fb_spi_clock_parent"; + clocks = <&clk_256m>, <&clk_256m>, <&clk_384m>, <&clk_aon_apb>, <&clk_dispc0>, <&clk_dispc0_dbi>, <&clk_dispc0_dpi>, <&clk_disp_emc>, <&clk_spi2>, <&ext_26m>; + clock-src = <256000000 256000000 384000000>; + dpi_clk_div = <7>; + sprd,fb_use_reservemem; + }; + + gsp@20a00000 { + compatible = "sprd,gsp"; + reg = <0 0x20a00000 0 0x1000>; + interrupts = <0 51 0x0>; + clock-names = "clk_gsp0", "clk_gsp_emc", "clk_gsp_parent", "clk_aon_apb"; + clocks = <&clk_gsp0>, <&clk_gsp_emc>, <&clk_256m>, <&clk_aon_apb>; + gsp_mmu_ctrl_base = <0x20b08000>; + }; + + /*sharLT8 gspn initializer */ + gspn:gspn@0x20A00000 { + compatible = "sprd,gspn"; + reg = <0 0x71500000 0 0x1000>, // arm interrupt ctl reg + <0 0x20E00000 0 0x1000>, //gspn module enable ctl reg base + <0 0x20E00004 0 0x1000>, //gspn module reset ctl reg base + <0 0x20E0304C 0 0x1000>, //[0] gsp/gspn select reg base, 0:gsp; 1:gspn + <0 0x402e00fc 0 0x1000>; //[0] ap chip id reg addr + gspn0:gspn@0x20A00000 { + core_id = <0>; + gspn_en_rst_bit = <0x00000008>;//bit3 + mmu_en_rst_bit = <0x00000008>;//bit3 + auto_gate_bit = <0x00000100>;//bit8 + force_gate_bit = <0x00000200>;//bit9 + emc_en_bit = <0x00000008>;//bit3 + reg = <0 0x20A00000 0 0x1000>, //gspn module ctl reg + <0 0x20B08000 0 0x1000>, //iommu ctl reg,64MB,page size 4KB + <0 0x215000a0 0 0x1000>, //gspn clock source select ctl reg base + <0 0x20E00010 0 0x1000>, //gspn clock auto-gate/force-gate ctl reg base + <0 0x20E00000 0 0x1000>; //gspn emc clock ctl reg base + interrupts = <0 51 0x0>; + clock-names = "clk_gsp1", "clk_gsp_emc", "clk_gsp_parent", "clk_aon_apb"; + clocks = <&clk_gsp1>, <&clk_gsp_emc>, <&clk_307m2>, <&clk_aon_apb>; + }; + }; + + sipc: sipc@0x87800000 { + compatible = "sprd,sipc"; + reg = <0 0x87800000 0 0x5B0000>; /* <SMEM SIZE>*/ + //#interrupt-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + ranges =<0x09600000 0 0x89600000 0x4600000>, + <0x07800000 0 0x87800000 0x5B0000>, + <0x0dbff000 0 0x8dbff000 0x1000>; + sipc_lte@0x09600000 { + sprd,name = "sipc-lte"; + sprd,dst = <5>; + /* it's unnecessary to config IPI info upon mailbox arch */ + mailbox,core = <7>; + reg = <0x09600000 0x4600000>, /* <CP_start_addr size> */ + <0x07800000 0x5B0000>, /* <SMEM_phy_addr total_size> */ + <0x0dbff000 0x1000>; /* smsg ring buffer <base size> */ + }; + }; + + sctrl_pmic{ + compatible = "sprd,sctrl"; + sprd,name = "sctrl_pmic"; + sprd,dst = <6>; + sprd,channel= <1>; + sprd,ringnr = <1>; + /* it's unnecessary to config IPI info upon mailbox arch */ + mailbox,core = <1>; + sprd,ringbase = <0x5000b000>; /*SMSG ring mem base phy address*/ + sprd,size-rxbuf = <0x0400>; /* 2*1024*/ + sprd,size-txbuf = <0x0400>; /* 2*1024 */ + }; + + saudio_lte{ + compatible = "sprd,saudio"; + sprd,saudio-dst-id = <5>; /* SIPC_ID_LTE */ + sprd,ctrl_channel = <10>; /* SMSG_CH_VBC */ + sprd,playback_channel = <11>; /* SMSG_CH_PLAYBACK */ + sprd,capture_channel = <12>; /* SMSG_CH_CAPTURE */ + sprd,monitor_channel = <13>; /*SMSG_CH_MONITOR_AUDIO */ + sprd,saudio-names = "saudiolte"; + }; + + saudio_voip{ + compatible = "sprd,saudio"; + sprd,saudio-dst-id = <5>; /* SIPC_ID_LTE */ + sprd,ctrl_channel = <14>; /* SMSG_CH_CTRL_VOIP */ + sprd,playback_channel = <15>; /* SMSG_CH_PLAYBACK_VOIP */ + sprd,capture_channel = <16>; /* SMSG_CH_CAPTURE_VOIP */ + sprd,monitor_channel = <17>; /*SMSG_CH_MONITOR_VOIP */ + sprd,saudio-names = "saudiovoip"; + }; + + /* LTE modem virtual devices */ + spipe_lte { + compatible = "sprd,spipe"; + sprd,name = "spipe_lte"; + sprd,dst = <5>; + sprd,channel = <4>; + sprd,ringnr = <9>; + sprd,size-rxbuf = <0x1000>; /* 4*1024 */ + sprd,size-txbuf = <0x1000>; /* 4*1024 */ + }; + + slog_lte { + compatible = "sprd,spipe"; + sprd,name = "slog_lte"; + sprd,dst = <5>; + sprd,channel = <5>; + sprd,ringnr = <1>; + sprd,size-rxbuf = <0x40000>; /* 256*1024*/ + sprd,size-txbuf = <0x8000>; /* 32*1024 */ + }; + + sdiag_lte { + compatible = "sprd,spipe"; + sprd,name = "sdiag_lte"; + sprd,dst = <5>; + sprd,channel = <21>; + sprd,ringnr = <1>; + sprd,size-rxbuf = <0x40000>; /* 256*1024*/ + sprd,size-txbuf = <0x8000>; /* 32*1024 */ + }; + + stty_lte { + compatible = "sprd,spipe"; + sprd,name = "stty_lte"; + sprd,dst = <5>; + sprd,channel = <6>; + sprd,ringnr = <32>; + sprd,size-rxbuf = <0x0800>; /* 2*1024*/ + sprd,size-txbuf = <0x0800>; /* 2*1024 */ + }; + + seth0_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte0"; + sprd,dst = <5>; + sprd,channel = <7>; + sprd,blknum = <256>; + }; + + seth1_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte1"; + sprd,dst = <5>; + sprd,channel = <8>; + sprd,blknum = <256>; + }; + + seth2_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte2"; + sprd,dst = <5>; + sprd,channel = <9>; + sprd,blknum = <256>; + }; + + seth3_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte3"; + sprd,dst = <5>; + sprd,channel = <18>; + sprd,blknum = <256>; + }; + + seth4_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte4"; + sprd,dst = <5>; + sprd,channel = <19>; + sprd,blknum = <256>; + }; + + seth5_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte5"; + sprd,dst = <5>; + sprd,channel = <20>; + sprd,blknum = <256>; + }; + + scproc_arm7: scproc@0x50800000 { + compatible = "sprd,scproc"; + sprd,name = "cppmic"; + sprd,ctrl-reg = <0x114 0xff 0xb0 0xff>; /* <shut_down deep_sleep reset get_status> */ + sprd,ctrl-mask = <0x01 0xfffffffe 0x100 0xf0000>; /* masks <> */ + sprd,iram-data = <0xe59f0000 0xe12fff10 0x0>; /* 3rd param equals modem_addr*/ + reg = <0 0x50800000 0 0x8000>, /* <CP_start_addr total_size> = <+128M 26M> */ + <0 0x50800000 0 0x0>, /* <iram1_base size> */ + <0 0x402e0000 0 0x400>, /* <aon_apb_base size> */ + <0 0x402b0000 0 0x100>, /* <pmu_base size> */ + <0 0x402b0000 0 0x100>, /* <pmu_base size> */ + <0 0x402b0000 0 0x100>; /* <pmu_base size> */ + #address-cells = <1>; + #size-cells = <1>; + /* segnr=1 */ + ranges = <0x0 0 0x50800000 0x8000>; + modem@0x0 { + cproc,name = "modem"; + reg = <0x0 0x8000>; /* <modem_addr size> */ + }; + }; + + scproc_cp1: scproc@0x89600000 { + compatible = "sprd,scproc"; + sprd,name = "cptl"; + sprd,ctrl-reg = <0x0c 0xff 0xb0 0x78>; /* <shut_down deep_sleep reset get_status> */ + sprd,ctrl-mask = <0x00300000 0x10000000 0x02 0x1>; /* masks <> */ + sprd,iram-data = <0xe59f0000 0xe12fff10 0x8ae00000>; /* 3rd param equals modem_addr*/ + reg = <0 0x89600000 0 0x5300000>, /* <CP_start_addr total_size> = <+128M 83M> */ + <0 0x50001000 0 0x0c>, /* <iram1_base size> */ + <0 0x402e0000 0 0x100>, /* <aon_apb_base size> */ + <0 0x402b0000 0 0x100>, /* <pmu_base size> */ + <0 0x402b0000 0 0x100>, /* <pmu_base size> */ + <0 0x402b0000 0 0x100>; /* <pmu_base size> */ + interrupts = <0 84 0x0>; /* cp1_wdg_int */ + #address-cells = <1>; + #size-cells = <1>; + /* segnr=4 */ + ranges = <0x1800000 0 0x8ae00000 0x02E00000>, + <0x0020000 0 0x89620000 0x002E0000>, + <0x0300000 0 0x89900000 0x1C0000>, + <0x4900000 0 0x8df00000 0xA00000>; + modem@0x1800000 { + cproc,name = "modem"; + reg = <0x1800000 0x02E00000>; /* <modem_addr size> */ + }; + dsp@0x20000 { + cproc,name = "tgdsp"; + reg = <0x20000 0x002e0000>; /* <dsp_addr size>*/ + }; + dsp@0x300000 { + cproc,name = "ldsp"; + reg = <0x300000 0x1c0000>; /* <dsp_addr size>*/ + }; + modem@0x4900000 { + cproc,name = "warm"; + reg = <0x4900000 0xA00000>; /* <modem_addr size>*/ + }; + }; + + dmac: dmac@20100000 { + compatible = "sprd,sprd-dma"; + interrupts = <0 50 0x0>; + reg = <0 0x20100000 0 0x4000>; + }; + + gpu: gpu@60000000 { + compatible = "sprd,mali-midgard"; + reg = <0 0x60000000 0 0x4000>; + interrupts = <0 39 0x4>, <0 39 0x4>, <0 39 0x4>; + interrupt-names = "JOB", "MMU", "GPU"; + + clocks = <&clk_gpu_axi>,<&clk_gpu>,<&clk_153m6>, <&clk_192m>, <&clk_256m>, <&clk_307m2>, <&clk_384m>, <&clk_gpll>; + clock-names = "clk_gpu_axi","clk_gpu","clk_153m6","clk_192m","clk_256m","clk_307m2","clk_384m","clk_gpll"; + + freq-list-len = <4>; + freq-lists = <153600 2 1>, <256000 4 1>, <384000 6 1>, <512000 7 1>; + freq-default = <3>; + freq-9 = <3>; + freq-8 = <3>; + freq-7 = <1>; + freq-5 = <0>; + freq-range-max = <3>; + freq-range-min = <0>; + }; + + l_ion: ion { + compatible = "sprd,ion-sprd"; + #address-cells = <1>; + #size-cells = <0>; + + sprd,ion-heap@1 { + reg = <1>; /* SYSTEM */ + reg-names = "ion_heap_system"; + sprd,ion-heap-type = <0>; /* SYSTEM */ + }; + + sprd,ion-heap@2 { + reg = <2>; /* MM */ + reg-names = "ion_heap_carveout_mm"; + sprd,ion-heap-type = <0>; /* carveout mm */ + }; + + sprd,ion-heap@3 { + reg = <3>; /* OVERLAY */ + reg-names = "ion_heap_carveout_overlay"; + sprd,ion-heap-type = <2>; /* CARVEOUT */ + }; + + sprd,ion-heap@4 { + reg = <4>; /* FB */ + reg-names = "ion_heap_carveout_fb"; + sprd,ion-heap-type = <2>; /* CARVEOUT */ + }; + }; + + sprd_iommu0: sprd_iommu@20b00000 { + compatible = "sprd,sprd_iommu"; //gsp + func-name = "sprd_iommu_gsp"; + reg = <0 0x10000000 0 0x2000000>, //iova + <0 0x20b00000 0 0x8000>, //pgt + <0 0x20b08000 0 0x8000>; //ctrl_reg + reg_name = "iova","pgt","ctrl_reg"; + clock-names = "clk_gsp_emc","clk_153m6","clk_gsp0"; + clocks = <&clk_gsp_emc>, <&clk_153m6>,<&clk_gsp0>; + status = "ok"; + }; + + sprd_iommu1: sprd_iommu@60f00000 { + compatible = "sprd,sprd_iommu"; //mm + func-name = "sprd_iommu_mm"; + reg = <0 0x20000000 0 0x8000000>, //iova + <0 0x60f00000 0 0x20000>, //pgt + <0 0x60f20000 0 0x2000>; //ctrl_reg + reg_name = "iova","pgt","ctrl_reg"; + clock-names = "clk_mmu","clk_mm_i"; + clocks = <&clk_mmu>,<&clk_mm>; + status = "ok"; + }; + + sprd_vsp: sprd_vsp@60900000{ + compatible = "sprd,sprd_vsp"; + reg = <0 0x60900000 0 0xc000>; + interrupts = <0 43 0x0>; + clock-names = "clk_mm_i", "clk_vsp", "clk_parent_0", "clk_parent_1", "clk_parent_2", "clk_parent_3"; + clocks = <&clk_mm>, <&clk_vsp>, <&clk_307m2>, <&clk_256m>, <&clk_128m>, <&clk_96m>; + clock-parent-info = <2 4>; + version = <7>; + }; + + sprd_vpp@61000000{ + compatible = "sprd,sprd_vpp"; + reg = <0 0x61000000 0 0x4000>; + interrupts = <0 43 0x0>; + clock-names = "clk_mm_i","clk_vpp","clk_256m","clk_153m6","clk_128m","clk_96m"; + clocks = <&clk_mm>, <&clk_vpp>, <&clk_256m>, <&clk_153m6>, <&clk_128m>, <&clk_96m>; + clock-parent-info = <2 4>; + }; + + sprd_coda7l@62100000{ + compatible = "sprd,sprd_coda7l"; + reg = <0 0x62100000 0 0x4000>; + interrupts = <0 43 0x0>; + clock-names = "clk_mm_i","clk_coda7_axi","clk_coda7_cc","clk_coda7_apb", + "clk_192m","clk_153m6","clk_128m","clk_76m8", + "clk_128m","clk_96m","clk_76m8","ext_26m"; + clocks = <&clk_mm>, <&clk_coda7_axi>, <&clk_coda7_cc>, <&clk_coda7_apb>, + <&clk_192m>, <&clk_153m6>, <&clk_128m>, <&clk_76m8>, + <&clk_128m>, <&clk_96m>, <&clk_76m8>, <&ext_26m>; + clock-parent-info = <4 4>; + power-regs-info = <0x402b0044 0 0x402b00c8 0xf0000000>; + }; + + sprd_jpg { + compatible = "sprd,sprd_jpg"; + reg = <0 0x60b00000 0 0x8000>; + interrupts = <0 42 0x0>; + clock-names = "clk_mm_i","clk_jpg"; + clocks = <&clk_mm>, <&clk_jpg>; + }; + + sprd_bm { + compatible = "sprd,sprd_bm"; + reg = <0 0x30040000 0 0xA0000 + 0 0x20F00000 0 0x300000>; + interrupts = <0 86 0x0>; + sprd,bm_status = <1>; + sprd,bm_count = <10 11>; + sprd,cpu_chn = <0 1>; + sprd,disp_chn = <1 1>; + sprd,gpu_chn = <2 1>; + sprd,ap_zip_chn = <3 1>; + sprd,mm_chn = <4 1>; + sprd,cp0_arm0_1_chn = <5 1>; + sprd,cp0_dsp_chn = <6 0>; + sprd,cp1_lte_chn = <7 1>; + sprd,cp1_dsp_chn = <8 1>; + sprd,cp1_arm_chn = <9 1>; + sprd,ap_dap_chn = <0 0>; + sprd,ap_cpu_chn = <0 1>; + sprd,ap_dma_r_chn = <0 2>; + sprd,ap_dma_w_chn = <0 3>; + sprd,ap_sdio_0_chn = <1 0>; + sprd,ap_sdio_1_chn = <1 1>; + sprd,ap_sdio_2_chn = <1 2>; + sprd,ap_emmc_chn = <1 3>; + sprd,ap_nandc_chn = <2 0>; + sprd,ap_otg_chn = <2 1>; + sprd,ap_hsic_chn = <2 2>; + }; + + wdt@40290000 { + compatible = "sprd,sprd-wdt"; + reg = <0 0x40290000 0 0x1000>, + <0 0x40310000 0 0x1000>; + interrupts = <0 124 0x0>; + }; +}; + +&vbc_r2p0 { + status = "okay"; +}; + +&sprd_codec { + status = "okay"; + sprd,audio_power_ver = <4>; +}; + +&i2s0 { + sprd,config_type = "pcm"; + sprd,slave_timeout = <0xF11>; + sprd,_hw_port = <0>; + sprd,fs = <8000>; + sprd,bus_type = <1>; + sprd,rtx_mode = <3>; + sprd,byte_per_chan = <1>; + sprd,slave_mode = <0>; + sprd,lsb = <0>; + sprd,lrck = <0>; + sprd,low_for_left = <1>; + sprd,clk_inv = <0>; + sprd,pcm_short_frame = <1>; + sprd,pcm_slot = <0x1>; + sprd,pcm_cycle = <1>; + sprd,tx_watermark = <12>; + sprd,rx_watermark = <20>; + status = "okay"; +}; + +&i2s1 { + status = "okay"; +}; + +&i2s2 { + status = "okay"; +}; + +&i2s3 { + status = "okay"; +}; + +&i2s_sound { + sprd,i2s = <&i2s0>, <&i2s1>, <&i2s2>, <&i2s3>; +}; + diff --git a/arch/arm64/boot/dts/sprd-sharklt8.dts b/arch/arm64/boot/dts/sprd-sharklt8.dts new file mode 100644 index 00000000..0538b9dc --- /dev/null +++ b/arch/arm64/boot/dts/sprd-sharklt8.dts @@ -0,0 +1,251 @@ +/* + * SPREADTRUM Ltd. + * + * SharkLT8 DTS + */ + +/dts-v1/; + +/memreserve/ 0x80000000 0x00010000; +/memreserve/ 0x8a800000 0x600000; + +/* memory reserved for ION(carveout mm)*/ +/memreserve/ 0x98800000 0x7100000; + +/* memory reserved for ION(overlay)*/ +/memreserve/ 0x9f900000 0x700000; /* 7MK */ + +/include/ "sprd-battery.dtsi" + +/ { + model = "scx35lt8"; + compatible = "sprd,SharkLT8"; + sprd,sc-id = <8830 1 0x20000>; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { + bootargs = "earlyprintk=sprd_uart,0x70000000"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0 0x80000000 0 0x20000000>; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + hwspinlock0 = &hwspinlock0; + hwspinlock1 = &hwspinlock1; + }; + + gic: interrupt-controller@12001000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0x12001000 0 0x1000>, + <0 0x12002000 0 0x1000>; + }; + + intc:interrupt-controller@71400000 { + compatible = "sprd,intc"; + #interrupt-cells = <0>; + interrupt-controller; + reg = <0 0x71400000 0 0x1000>, + <0 0x71500000 0 0x1000>, + <0 0x71600000 0 0x1000>, + <0 0x71700000 0 0x1000>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, + <1 14 0xff01>, + <1 11 0xff01>, + <1 10 0xff01>; + clock-frequency = <26000000>; + }; + + sprd_timer { + compatible = "sprd,sharkl64-timer"; + reg = <0 0x40050000 0 0x20>; /*aon GPTIMER0 */ + interrupts = <0 28 0x0>; + clock-frequency = <32768>; + }; + + uart0: uart@70000000 { + compatible = "sprd,serial"; + reg = <0 0x70000000 0 0x100>; + interrupts = <0 2 0xf04>; + }; + + uart1: uart@70100000 { + compatible = "sprd,serial"; + reg = <0 0x70100000 0 0x100>; + interrupts = <0 3 0xf04>; + }; + hwspinlock0: hwspinlock0@20c00000{ + compatible = "sprd,sprd-hwspinlock"; + reg = <0 0x20c00000 0 0x1000>; + }; + hwspinlock1: hwspinlock1@40060000{ + compatible = "sprd,sprd-hwspinlock"; + reg = <0 0x40060000 0 0x1000>; + status = "ok"; + }; + + adi: adi_bus { + compatible = "sprd,adi-bus"; + interrupts = <0 38 0x0>; + reg = <0 0x40038000 0 0x1000>; + interrupt-controller; + sprd,irqnums = <11>; + #interrupt-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x100 0 0x40038100 0x80>; + + keyboard_backlight { + compatible = "sprd,keyboard-backlight"; + }; + a_eic_gpio: gpio@100{ + compatible = "sprd,a-eic-gpio"; + reg = <0x100 0x80>; /* adi reg */ + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-cells = <2>; + gpiobase = <304>; + ngpios = <16>; + interrupt-parent = <&adi>; + interrupts = <5 0x0>; /* ext irq 5 */ + }; + sprd_eic_keys { + compatible = "sprd,sprd-eic-keys"; + key_power { + label = "Power Key"; + linux,code = <116>; + gpios = <&a_eic_gpio 2 0>; + debounce-interval = <2>; + gpio-key,wakeup; + }; + }; + }; + sprd-io-base { + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 1 0>; + ahb { + compatible = "sprd,ahb"; + reg = <0 0x20e00000 0 0x40000>; + }; + apbckg { + compatible = "sprd,apbckg"; + reg = <0 0x21500000 0 0x1000>; + }; + hwlock0 { + compatible = "sprd,hwlock0"; + reg = <0 0x20d00000 0 0x1000>; + }; + pub_apb { + compatible = "sprd,pub_apb"; + reg = <0 0x30020000 0 0x10000>; + }; + aon_apb { + compatible = "sprd,aon_apb"; + reg = <0 0x402e0000 0 0x40000>; + }; + pmu_apb { + compatible = "sprd,pmu_apb"; + reg = <0 0x402b0000 0 0x40000>; + }; + mm_ahb { + compatible = "sprd,mm_ahb"; + reg = <0 0x60d00000 0 0x10000>; + }; + mm_clk { + compatible = "sprd,mm_clk"; + reg = <0 0x60e00000 0 0x1000>; + }; + ap_ckg { + compatible = "sprd,ap_ckg"; + reg = <0 0x71200000 0 0x40000>; + }; + ap_apb { + compatible = "sprd,ap_apb"; + reg = <0 0x71300000 0 0x40000>; + }; + gpu_apb { + compatible = "sprd,gpu_apb"; + reg = <0 0x60100000 0 0x1000>; + }; + adi { + compatible = "sprd,adi"; + reg = <0 0x40030000 0 0x10000>; + }; + adi_slave { + compatible = "sprd,adi_slave"; + reg = <0 0x40038000 0 0x1000>; + }; + adc { + compatible = "sprd,adc"; + reg = <0 0x40038300 0 0x1000>; + }; + dma { + compatible = "sprd,dma"; + reg = <0 0x20100000 0 0x4000>; + interrupts = <0 50 0x0>; + }; + mailbox { + compatible = "sprd,mailbox"; + reg = <0 0x400a0000 0 0x10000>; + }; + rtc { + compatible = "sprd,rtc"; + reg = <0 0x40038080 0 0x80>; + interrupts = <0 2 0x0>; + }; + axibm0 { + compatible = "sprd,axibm0"; + reg = <0 0x30040000 0 0x20000>; + interrupts = <0 86 0x0>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/sprd-sound.dtsi b/arch/arm64/boot/dts/sprd-sound.dtsi new file mode 100644 index 00000000..364939ac --- /dev/null +++ b/arch/arm64/boot/dts/sprd-sound.dtsi @@ -0,0 +1,150 @@ +/* +* Copyright (C) 2013 Spreadtrum Communication Incorporated +* http://www.spreadtrum.com/ +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +*/ + +/* This is the sprd audio default DTS */ + +/ { + sprd-audio-devices { + compatible = "sprd,sound"; + #address-cells = <1>; + #size-cells = <1>; + + /* 1. codecs */ + sprd_codec: sprd-codec { + compatible = "sprd,sprd-codec"; + status = "disable"; + sprd,def_da_fs = <44100>; + sprd,ap_irq = <164>; + sprd,dp_irq = <52>; + sprd,reg_dp = <0x40000000 0x2000>; + }; + + sprd_codec_v3: sprd-codec-v3 { + compatible = "sprd,sprd-codec-v3"; + status = "disable"; + sprd,def_da_fs = <44100>; + sprd,ap_irq = <164>; + sprd,dp_irq = <52>; + sprd,reg_dp = <0x40000000 0x2000>; + }; + + sprd_codec_v1: sprd-codec-v1 { + compatible = "sprd,sprd-codec-v1"; + status = "disable"; + sprd,def_da_fs = <44100>; + sprd,ap_irq = <103>; + sprd,dp_irq = <63>; + }; + + null_codec: null-codec { + compatible = "sprd,null-codec"; + }; + + /* 2. cpu-dais */ + vbc_r2p0: vbc-r2p0 { + compatible = "sprd,vbc-r2p0"; + status = "disable"; + sprd,reg_vbc = <0X40020000 0x20000>; + }; + + vbc_r1p0: vbc-r1p0 { + compatible = "sprd,vbc-r1p0"; + status = "disable"; + }; + + vaudio: vaudio { + compatible = "sprd,vaudio"; + }; + + pcm_def_config: bt-i2s-config { + sprd,def_pcm_config; + }; + + i2s_def_config: fm-i2s-config { + }; + + i2s0: i2s@0 { + compatible = "sprd,i2s"; + status = "disable"; + sprd,dai_name = "i2s_bt_sco0"; + sprd,id = <0>; + sprd,hw_port = <0>; + sprd,base = <0x70D00000 0x100000>; + sprd,dma_rx_no = <3>; + sprd,dma_tx_no = <4>; + }; + + i2s1: i2s@1 { + compatible = "sprd,i2s"; + status = "disable"; + sprd,dai_name = "i2s_bt_sco1"; + sprd,id = <1>; + sprd,hw_port = <1>; + sprd,base = <0x70E00000 0x100000>; + sprd,dma_rx_no = <5>; + sprd,dma_tx_no = <6>; + }; + + i2s2: i2s@2 { + compatible = "sprd,i2s"; + status = "disable"; + sprd,dai_name = "i2s_bt_sco2"; + sprd,id = <2>; + sprd,hw_port = <2>; + sprd,base = <0x70F00000 0x100000>; + sprd,dma_rx_no = <7>; + sprd,dma_tx_no = <8>; + }; + + i2s3: i2s@3 { + compatible = "sprd,i2s"; + status = "disable"; + sprd,dai_name = "i2s_bt_sco3"; + sprd,id = <3>; + sprd,hw_port = <3>; + sprd,base = <0x71000000 0x100000>; + sprd,dma_rx_no = <9>; + sprd,dma_tx_no = <10>; + }; + + /* 3. platform */ + sprd_pcm: sprd-pcm-audio { + compatible = "sprd,sprd-pcm"; + }; + + /* 4. machine */ + vbc_sound0: sound@0 { + compatible = "sprd,vbc-r2p0-sprd-codec"; + sprd,model = "sprdphone"; + sprd,vaudio = <&vaudio>; + sprd,vbc = <&vbc_r2p0>; + sprd,codec = <&sprd_codec>; + sprd,pcm = <&sprd_pcm>; + }; + + vbc_sound1: sound@1 { + compatible = "sprd,vbc-r2p0-sprd-codec-v3"; + sprd,model = "sprdphone"; + sprd,vaudio = <&vaudio>; + sprd,vbc = <&vbc_r2p0>; + sprd,codec = <&sprd_codec_v3>; + sprd,pcm = <&sprd_pcm>; + }; + + i2s_sound: sound@2 { + compatible = "sprd,i2s-null-codec"; + sprd,model = "all-i2s"; + sprd,i2s = <&i2s0>, <&i2s1>, <&i2s2>, <&i2s3>; + sprd,codec = <&null_codec>; + sprd,pcm = <&sprd_pcm>; + }; + + }; + +}; diff --git a/arch/arm64/boot/dts/sprd_sp9836aea_3mod.dts b/arch/arm64/boot/dts/sprd_sp9836aea_3mod.dts new file mode 100644 index 00000000..05554f2b --- /dev/null +++ b/arch/arm64/boot/dts/sprd_sp9836aea_3mod.dts @@ -0,0 +1,1324 @@ +/* + * SPREADTRUM Ltd.clock-cells +sprd_rotation + * + * SharkL64 3mod refphone DTS + */ + +/dts-v1/; + +/* memory reserved for SMEM */ +/memreserve/ 0x87800000 0x540000; /* Offset:120M, Size:5M+256K */ + + + +/* memory reserved for LTE modem */ +/memreserve/ 0x89600000 0x4000000; /* Offset:150M, Size:64M*/ + +/* memory reserved for fb */ +/memreserve/ 0x9F74F000 0x4B1000; /* 480*854*4*3, 4K alignment*/ + +/* memory reserved for ION */ +/memreserve/ 0x9FC00000 0x400000; /* 480*854*4*2, 1M alignment*/ + +/* memory reserved for smp */ +/memreserve/ 0x9F700000 0x1000; /* size 4K*/ + +/include/ "sc2723-regulators.dtsi" +/include/ "sprd-sound.dtsi" +/include/ "sprd-battery.dtsi" +/include/ "scx35l64-clocks.dtsi" + +/ { + model = "scx35l64"; + compatible = "sprd,TsharkL"; + sprd,sc-id = <8830 1 0x20000>; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { + bootargs = "earlyprintk=sprd_uart,0x70100000 loglevel=7 console=ttyS1,115200n8"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP>; + }; + cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP>; + }; + idle-states{ + entry-method = "arm,psci"; + LIGHT_SLEEP: light_sleep { + compatible = "arm,idle-state"; + exit-latency-us = <100>; + min-residency-us = <500>; + entry-method-param = <0x00000001>; + }; + CORE_PD: core_pd { + compatible = "arm,idle-state"; + exit-latency-us = <1070>; + min-residency-us = <1600>; + entry-method-param = <0x00010002>; + }; + CLUSTER_PD: cluster_pd { + compatible = "arm,idle-state"; + exit-latency-us = <1100>; + min-residency-us = <2500>; + entry-method-param = <0x01010003>; + }; + DEEP_SLEEP: deep_sleep { + compatible = "arm,idle-state"; + exit-latency-us = <4100>; + min-residency-us = <6500>; + entry-method-param = <0x01010004>; + }; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0 0x80000000 0 0x40000000>; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + lcd0 = &fb0; + hwspinlock0 = &hwspinlock0; + hwspinlock1 = &hwspinlock1; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 92 4>, + <0 93 4>, + <0 94 4>, + <0 95 4>; + }; + + psci { + compatible = "arm,psci"; + method = "smc"; + cpu_on = <0xc4000003>; + cpu_off = <0x84000002>; + cpu_suspend = <0xc4000001>; + }; + + gic: interrupt-controller@12001000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0x12001000 0 0x1000>, + <0 0x12002000 0 0x1000>; + }; + + intc:interrupt-controller@71400000 { + compatible = "sprd,intc"; + #interrupt-cells = <0>; + interrupt-controller; + reg = <0 0x71400000 0 0x1000>, + <0 0x71500000 0 0x1000>, + <0 0x71600000 0 0x1000>, + <0 0x71700000 0 0x1000>, + <0 0x40200000 0 0x1000>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, + <1 14 0xff01>, + <1 11 0xff01>, + <1 10 0xff01>; + clock-frequency = <26000000>; + }; + + sprd_timer { + compatible = "sprd,sharkl64-timer"; + reg = <0 0x40050000 0 0x20>; /*aon GPTIMER0 */ + interrupts = <0 28 0x0>; + clock-frequency = <32768>; + }; + + sprd_ap_system_timer { + reg = <0 0x40230000 0 0x20>; + interrupts = <0 31 0x0>; + }; + + clock: clockdevice { + compatible = "sprd,scx35l64-clocks"; + #clock-cells = <1>; + }; + + d_eic_gpio: gpio@40210000 { + compatible = "sprd,d-eic-gpio"; + reg = <0 0x40210000 0 0x1000>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-cells = <2>; + gpiobase = <288>; + ngpios = <16>; + interrupts = <0 37 0x0>; + }; + + d_gpio_gpio: gpio@40280000 { + compatible = "sprd,d-gpio-gpio"; + reg = <0 0x40280000 0 0x1000>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-cells = <2>; + gpiobase = <0>; + ngpios = <256>; + interrupts = <0 35 0x0>; + }; + + uart0: uart@70000000 { + compatible = "sprd,serial"; + interrupts = <0 2 0xf04>; + reg = <0 0x70000000 0 0x1000>; + clock-names = "clk_uart0"; + clocks = <&clock 60>; + sprdclk = <48000000>; + sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP"; + + }; + + uart1: uart@70100000 { + compatible = "sprd,serial"; + interrupts = <0 3 0xf04>; + reg = <0 0x70100000 0 0x1000>; + clock-names = "clk_uart1"; + clocks = <&clock 61>; + sprdclk = <26000000>; + sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP"; + + }; + + uart2: uart@70200000 { + compatible = "sprd,serial"; + interrupts = <0 4 0xf04>; + reg = <0 0x70200000 0 0x1000>; + clock-names = "clk_uart2"; + clocks = <&clock 62>; + sprdclk = <26000000>; + sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP"; + }; + + uart3: uart@70300000 { + compatible = "sprd,serial"; + interrupts = <0 5 0xf04>; + reg = <0 0x70300000 0 0x1000>; + clock-names = "clk_uart3"; + clocks = <&clock 63>; + sprdclk = <26000000>; + sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP"; + }; + + hwspinlock0: hwspinlock0@20c00000{ + compatible = "sprd,sprd-hwspinlock"; + reg = <0 0x20c00000 0 0x1000>; + }; + + hwspinlock1: hwspinlock1@40060000{ + compatible = "sprd,sprd-hwspinlock"; + reg = <0 0x40060000 0 0x1000>; + status = "ok"; + }; + + watchdog { + compatible = "sprd,watchdog"; + reg = <0 0X40290000 0 0x1000>; + }; + + pinctrl { + compatible = "sprd,pinctrl"; + reg = <0 0x402a0000 0 0x1000>; + pwr_domain = "vdd28", + "vdd28", + "vddsim0", + "vddsim1", + "vddsim2", + "vddsdio", + "vdd18"; + ctrl_desc = <0x10 0 1 + 0x10 1 1 + 0x10 2 1 + 0x10 3 1 + 0x10 4 1 + 0x10 5 1 + 0x10 6 1>; + }; + + sdios{ + #address-cells = <2>; + #size-cells = <2>; + ranges; + sdio3: sdio@20600000{ + compatible = "sprd,sdhost-3.0"; + reg = <0 0x20600000 0 0x1000>; + interrupts = <0 60 0x0>; + sprd,name = "sdio_emmc"; + /*detect_gpio = <-1>; */ + SD_Pwr_Name = "vddemmccore"; + _1_8V_signal_Name = "vddgen1"; + signal_default_Voltage = <1800000>; + ocr_avail = <0x00040000>; + clocks = <&clk_emmc>, <&clk_384m>; + base_clk = <384000000>; + caps = <0xC00F8D47>; + caps2 = <0x202>; + pm_caps = <0x4>; + writeDelay = <0x3E>; + readPosDelay = <0xA>; + readNegDelay = <0xA>; + }; + + sdio0: sdio@20300000{ + compatible = "sprd,sdhost-3.0"; + reg = <0 0x20300000 0 0x1000>; + interrupts = <0 57 0x0>; + sprd,name = "sdio_sd"; + detect_gpio = <141>; + SD_Pwr_Name = "vddsdcore"; + /* _1_8V_signal_Name = "vddsdio"; */ + signal_default_Voltage = <3000000>; + ocr_avail = <0x00040000>; + clocks = <&clk_sdio0>, <&clk_384m>; + base_clk = <384000000>; + caps = <0xC0000407>; + caps2 = <0x200>; + pm_caps = <0x4>; + writeDelay = <0x3>; + readPosDelay = <0x3>; + readNegDelay = <0x3>; + }; + + + sdio1: sdio@20400000{ + compatible = "sprd,sdhost-3.0"; + reg = <0 0x20400000 0 0x1000>; + interrupts = <0 58 0x0>; + sprd,name = "sdio_wifi"; + /* detect_gpio = <-1>; */ + /* SD_Pwr_Name = "vddsdcore"; */ + /* _1_8V_signal_Name = "vddsdio";*/ + /* signal_default_Voltage = <3000000>; */ + ocr_avail = <0x00360080>; + clocks = <&clk_sdio1>, <&clk_76m8>; + base_clk = <96000000>; + caps = <0xC00FA407>; + caps2 = <0x0>; + pm_caps = <0x5>; + writeDelay = <0x03>; + readPosDelay = <0x03>; + readNegDelay = <0x03>; + }; + }; + + adic:adic { + compatible = "sprd,adi"; + reg = <0 0x40030000 0 0x10000>; + }; + + adi: adi_bus { + compatible = "sprd,adi-bus"; + interrupts = <0 38 0x0>; + reg = <0 0x40038000 0 0x1000>; + interrupt-controller; + sprd,irqnums = <11>; + #interrupt-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x100 0 0x40038100 0x80>; + + keyboard_backlight { + compatible = "sprd,keyboard-backlight"; + }; + a_eic_gpio: gpio@100{ + compatible = "sprd,a-eic-gpio"; + reg = <0x100 0x80>; /* adi reg */ + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-cells = <2>; + gpiobase = <304>; + ngpios = <16>; + interrupt-parent = <&adi>; + interrupts = <5 0x0>; /* ext irq 5 */ + }; + sprd_eic_keys { + compatible = "sprd,sprd-eic-keys"; + input-name = "sprd-eic-keys"; + key_power { + label = "Power Key"; + linux,code = <116>; + gpios = <&a_eic_gpio 2 0>; + debounce-interval = <2>; + gpio-key,wakeup; + }; + }; + + headset_sprd_sc2723 { + compatible = "sprd,headset_sprd_sc2723"; + gpio_switch = <0>; + gpio_detect = <312>; + gpio_button = <307>; + irq_trigger_level_detect = <1>; + irq_trigger_level_button = <1>; + adc_threshold_3pole_detect = <300>; + adc_threshold_4pole_detect = <3270>; + irq_threshold_buttont = <1>; + voltage_headmicbias = <3000000>; + nbuttons = <3>; + headset_buttons_media { + adc_min = <0>; + adc_max = <550>; + code = <226>; + type = <0>; + }; + + headset_buttons_up { + adc_min = <551>; + adc_max = <1114>; + code = <115>; + type = <0>; + }; + headset_buttons_down { + adc_min = <1115>; + adc_max =<3000>; + code = <114>; + type = <0>; + }; + }; + + rtc@80{ + compatible = "sprd,rtc"; + reg = <0X80 0x80>; + interrupt-parent = <&adi>; + interrupts = <2 0x0>; + }; + }; + + sprd_pwm_bl { + compatible = "sprd,sprd_pwm_bl"; + brightness_max = <255>; + brightness_min = <0>; + pwm_index = <2>; + gpio_ctrl_pin = <0>; + gpio_active_level = <0>; + reg =<0 0x40260000 0 0xf>; + }; + + gpio_keys { + compatible = "gpio-keys"; + input-name = "sprd-gpio-keys"; + key_volumedown { + label = "Volumedown Key"; + linux,code = <114>; + gpios = <&d_gpio_gpio 124 1>; + debounce-interval = <2>; + gpio-key,wakeup; + }; + key_volumeup { + label = "Volumeup Key"; + linux,code = <115>; + gpios = <&d_gpio_gpio 125 1>; + debounce-interval = <2>; + gpio-key,wakeup; + }; + }; + + sprd_backlight { + compatible = "sprd,sprd_backlight"; + start = <3>; + end = <3>; + flags = <0x100>; + }; + + rfkill { + compatible = "broadcom,rfkill"; + gpios = <&d_gpio_gpio 131 0 /* power */ + &d_gpio_gpio 122 0>; /* reset */ + }; + bluesleep { + compatible = "broadcom,bluesleep"; + bt-wake-gpio = <&d_gpio_gpio 132 0>; + host-wake-gpio = <&d_gpio_gpio 133 0>; + }; + + usb: usb@20200000{ + compatible = "sprd,usb"; + interrupts = <0 55 0x0>; + ngpios = <1>; + gpios = <&a_eic_gpio 0 0>; + reg = <0 0x20200000 0 0x1000>; + tune_value = <0x44073e33>; + usb-supply = <&vddusb>; + #address-cells = <1>; + #size-cells = <0>; + }; + sprd_thermal: thermal@402F0000{ + compatible = "sprd,sprd-thermal"; + id = <0>; + interrupts = <0 26 0x0>; + reg = <0 0x402F0000 0 0x1000>; + trip_points_active = <65 69 95 110>; + trip_points_lowoff = <0 57 60 80>; + trip_points_critical = <110>; + trip_num = <5>; + }; + sprd_thermal1:thermal1@402F0000 { + compatible = "sprd,sprd-thermal"; + id = <1>; + interrupts = <0 26 0x0>; + reg = <0 0x402F0000 0 0x1000>; + trip_points_active = <110>; + trip_points_lowoff = <90>; + trip_points_critical = <110>; + trip_num = <2>; + }; + sprd_thermal2: thermal@40038280{ + compatible = "sprd,sprd-thermal"; + id = <2>; + interrupt-parent = <&adi>; + interrupts = <9 0x0>; + reg = <0 0x40038280 0 0x1000>; + trip_points_active = <110>; + trip_points_lowoff = <90>; + trip_points_critical = <110>; + trip_num = <2>; + }; + + adc: adc@40038300{ + compatible = "sprd,sprd-adc"; + reg = <0x40038300 0x1000>; + }; + i2c0: i2c@70500000{ + compatible = "sprd,i2c"; + interrupts = <0 11 0x0>; + reg = <0 0x70500000 0 0x1000>; + clock-names = "clk_i2c0"; + clocks = <&clk_i2c0>; + #address-cells = <1>; + #size-cells = <0>; + sensor_main@0x3c { + compatible = "sprd,sensor_main"; + reg = <0x3c>; + }; + sensor_sub@0x21 { + compatible = "sprd,sensor_sub"; + reg = <0x21>; + }; + }; + + i2c1: i2c@70600000{ + compatible = "sprd,i2c"; + interrupts = <0 12 0x0>; + reg = <0 0x70600000 0 0x1000>; + clock-names = "clk_i2c1"; + clocks = <&clk_i2c1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@70700000{ + compatible = "sprd,i2c"; + interrupts = <0 13 0x0>; + reg = <0 0x70700000 0 0x1000>; + clock-names = "clk_i2c2"; + clocks = <&clk_i2c2>; + #address-cells = <1>; + #size-cells = <0>; + + lis3dh_acc@18{ + compatible = "ST,lis3dh_acc"; + reg = <0x18>; + poll_interval = <10>; + min_interval = <10>; + g_range = <0>; + axis_map_x = <0>; + axis_map_y = <1>; + axis_map_z = <2>; + negate_x = <1>; + negate_y = <1>; + negate_z = <0>; + }; + ltr_558als@23{ + compatible = "LITEON,ltr_558als"; + reg = <0x23>; + gpios = <&d_gpio_gpio 140 0>; + }; + epl2182_pls@49{ + compatible = "ELAN,epl2182_pls"; + reg = <0x49>; + gpios = <&d_gpio_gpio 140 0>; + }; + }; + + i2c3: i2c@70800000{ + compatible = "sprd,i2c"; + interrupts = <0 14 0x0>; + reg = <0 0x70800000 0 0x1000>; + clock-names = "clk_i2c3"; + clocks = <&clk_i2c3>; + #address-cells = <1>; + #size-cells = <0>; + + focaltech_ts@38{ + compatible = "focaltech,focaltech_ts"; + reg = <0x38>; + gpios = <&d_gpio_gpio 145 0 + &d_gpio_gpio 144 0>; + vdd_name = "vdd28"; + virtualkeys = <80 900 60 45 + 240 900 60 45 + 400 900 60 45>; + TP_MAX_X = <480>; + TP_MAX_Y = <800>; + }; + msg2138_ts@26{ + compatible = "Mstar,msg2138_ts"; + reg = <0x26>; + gpios = <&d_gpio_gpio 145 0 + &d_gpio_gpio 144 0>; + vdd_name = "vdd28"; + virtualkeys = <256 1068 64 64 + 128 1068 64 64 + 192 1068 64 64>; + TP_MAX_X = <480>; + TP_MAX_Y = <800>; + }; + }; + + i2c4: i2c@70900000{ + compatible = "sprd,i2c"; + interrupts = <0 15 0x0>; + reg = <0 0x70900000 0 0x1000>; + clock-names = "clk_i2c4"; + clocks = <&clk_i2c4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi0: spi0@70a00000{ + compatible = "sprd,sprd-spi"; + interrupts = <0 7 0x0>; + reg = <0 0x70a00000 0 0x1000>; + clock-names = "clk_spi0"; + }; + + spi1: spi1@70b00000{ + compatible = "sprd,sprd-spi"; + interrupts = <0 8 0x0>; + reg = <0 0x70b00000 0 0x1000>; + clock-names = "clk_spi1"; + }; + + spi2: spi2@70c00000{ + compatible = "sprd,sprd-spi"; + interrupts = <0 9 0x0>; + reg = <0 0x70c00000 0 0x1000>; + clock-names = "clk_spi2"; + }; + + dma: dma-controller@20100000 { + compatible = "sprd,sharkl64-dma"; + #dma-cells = <1>; + #dma-channels = <64>; + sprd,aon-offset = <32>; + reg = <0 0x20100000 0 0x4000>, /* ap reg */ + <0 0x40100000 0 0x4000>; /* aon reg */ + interrupts = <0 50 0x0>, /* ap int */ + <0 70 0x0>; /* aon int */ + }; + + sprd-io-base { + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 1 0>; + ahb { + compatible = "sprd,ahb"; + reg = <0 0x20e00000 0 0x40000>; + }; + apbckg { + compatible = "sprd,apbckg"; + reg = <0 0x21500000 0 0x1000>; + }; + hwlock0 { + compatible = "sprd,hwlock0"; + reg = <0 0x20d00000 0 0x1000>; + }; + pub_apb { + compatible = "sprd,pub_apb"; + reg = <0 0x30020000 0 0x10000>; + }; + aon_apb { + compatible = "sprd,aon_apb"; + reg = <0 0x402e0000 0 0x40000>; + }; + pmu_apb { + compatible = "sprd,pmu_apb"; + reg = <0 0x402b0000 0 0x40000>; + }; + mm_ahb { + compatible = "sprd,mm_ahb"; + reg = <0 0x60d00000 0 0x10000>; + }; + mm_clk { + compatible = "sprd,mm_clk"; + reg = <0 0x60e00000 0 0x1000>; + }; + ap_ckg { + compatible = "sprd,ap_ckg"; + reg = <0 0x71200000 0 0x40000>; + }; + ap_apb { + compatible = "sprd,ap_apb"; + reg = <0 0x71300000 0 0x40000>; + }; + gpu_apb { + compatible = "sprd,gpu_apb"; + reg = <0 0x60100000 0 0x1000>; + }; + adi { + compatible = "sprd,adi"; + reg = <0 0x40030000 0 0x10000>; + }; + adi_slave { + compatible = "sprd,adi_slave"; + reg = <0 0x40038000 0 0x1000>; + }; + + mailbox { + compatible = "sprd,mailbox"; + reg = <0 0x400a0000 0 0x10000>; + }; + uart0 { + compatible = "sprd,uart0"; + reg = <0 0x70000000 0 0x1000>; + }; + uart1 { + compatible = "sprd,uart1"; + reg = <0 0x70100000 0 0x1000>; + }; + uart2 { + compatible = "sprd,uart2"; + reg = <0 0x70200000 0 0x1000>; + }; + uart3 { + compatible = "sprd,uart3"; + reg = <0 0x70300000 0 0x1000>; + }; + uart4 { + compatible = "sprd,uart4"; + reg = <0 0x70400000 0 0x1000>; + }; + axibm0 { + compatible = "sprd,axibm0"; + reg = <0 0x30040000 0 0x20000>; + interrupts = <0 86 0x0>; + }; + d_eic_gpio { + compatible = "sprd,d-eic-gpio"; + reg = <0 0x40210000 0 0x1000>; + }; + d_gpio_gpio { + compatible = "sprd,d-gpio-gpio"; + reg = <0 0x40280000 0 0x1000>; + }; + aon_dma { + compatible = "sprd,aon_dma"; + reg = <0 0x40100000 0 0x1000>; + interrupts = <0 50 0x0>; + }; + pwm { + compatible = "sprd,pwm"; + reg = <0 0x40260000 0 0x1000>; + }; + core { + compatible = "sprd,core"; + reg = <0 0x12000000 0 0x10000>; + }; + int { + compatible = "sprd,int"; + reg = <0 0x40200000 0 0x1000>; + }; + intc0 { + compatible = "sprd,intc0"; + reg = <0 0x71400000 0 0x1000>; + }; + intc1 { + compatible = "sprd,intc1"; + reg = <0 0x71500000 0 0x1000>; + }; + intc2 { + compatible = "sprd,intc2"; + reg = <0 0x71600000 0 0x1000>; + }; + intc3 { + compatible = "sprd,intc3"; + reg = <0 0x71700000 0 0x1000>; + }; + send_mbox { + compatible = "sprd,send_mbox"; + reg = <0 0x400a0000 0 0x1000>; + }; + recv_mbox { + compatible = "sprd,recv_mbox"; + reg = <0 0x400a8000 0 0x1000>; + }; + uidefuse { + compatible = "sprd,uidefuse"; + reg = <0 0x40240000 0 0x1000>; + }; + isp { + compatible = "sprd,isp"; + reg = <0 0x60a00000 0 0x8000>; + }; + csi2 { + compatible = "sprd,csi2"; + reg = <0 0x60c00000 0 0x1000>; + }; + ipi { + compatible = "sprd,ipi"; + reg = <0 0x402c0000 0 0x1000>; + }; + dcam { + compatible = "sprd,dcam"; + reg = <0 0x60800000 0 0x10000>; + }; + syscnt { + compatible = "sprd,syscnt"; + reg = <0 0x40230000 0 0x1000>; + }; + dma0 { + compatible = "sprd,dma0"; + reg = <0 0x20100000 0 0x4000>; + }; + pub { + compatible = "sprd,pub"; + reg = <0 0x30020000 0 0x10000>; + }; + pin { + compatible = "sprd,pin"; + reg = <0 0x402a0000 0 0x1000>; + }; + aonckg { + compatible = "sprd,aonckg"; + reg = <0 0x402d0000 0 0x1000>; + }; + lpddr2 { + compatible = "sprd,lpddr2"; + reg = <0 0x30000000 0 0x1000>; + }; + }; + + sprd_dcam { + compatible = "sprd,sprd_dcam"; + interrupts = <0 45 0>; + reg = <0 0x60800000 0 0x100000>; + clock-names = "clk_mm_i","clk_dcam"; + clocks = <&clk_mm>, <&clk_dcam>; + }; + + sprd_scale { + compatible = "sprd,sprd_scale"; + }; + + sprd_rotation { + compatible = "sprd,sprd_rotation"; + }; + + sprd_sensor { + compatible = "sprd,sprd_sensor"; + reg = <0 0x60c00000 0 0x100000>; + gpios = <&d_gpio_gpio 45 0 /*main reset*/ + &d_gpio_gpio 47 0 /*main powerdown*/ + &d_gpio_gpio 44 0 /*sub reset*/ + &d_gpio_gpio 46 0 + &d_gpio_gpio 0 0 /*main core voltage*/ + &d_gpio_gpio 0 0 + &d_gpio_gpio 0 0 + &d_gpio_gpio 0 0>; /*sub powerdown*/ + clock-names ="clk_mm_i","clk_sensor","clk_ccir","clk_dcam","clk_dcam_mipi"; + clocks = <&clk_mm>,<&clk_sensor>,<&clk_ccir>,<&clk_dcam>,<&clk_dcam_mipi>; + }; + + sprd_isp { + compatible = "sprd,sprd_isp"; + reg = <0 0x60a00000 0 0x100000>; + clock-names = "clk_mm_i","clk_isp"; + clocks = <&clk_mm>, <&clk_isp>; + }; + + sprd_dma_copy { + compatible = "sprd,sprd_dma_copy"; + }; + + fb0: fb@20800000 { + compatible = "sprd,sprdfb"; + reg = <0 0x20800000 0 0x1000>, + <0 0x21800000 0 0x1000>; + interrupts = <0 46 0x0>, + <0 48 0x0>, + <0 49 0x0>; + clock-names = "dispc_clk_parent", "dispc_dbi_clk_parent", "dispc_dpi_clk_parent", "dispc_emc_clk_parent", "dispc_clk", "dispc_dbi_clk", "dispc_dpi_clk", "dispc_emc_clk", "fb_spi_clock", "fb_spi_clock_parent"; + clocks = <&clk_256m>, <&clk_256m>, <&clk_384m>, <&clk_aon_apb>, <&clk_dispc0>, <&clk_dispc0_dbi>, <&clk_dispc0_dpi>, <&clk_disp_emc>, <&clk_spi2>, <&ext_26m>; + clock-src = <256000000 256000000 384000000>; + dpi_clk_div = <7>; + sprd,fb_use_reservemem; + sprd,fb_mem = <0x9F74F000 0x4B1000>; + }; + + gsp@20a00000 { + compatible = "sprd,gsp"; + reg = <0 0x20a00000 0 0x1000>; + interrupts = <0 51 0x0>; + clock-names = "clk_gsp", "clk_gsp_emc", "clk_gsp_parent", "clk_aon_apb"; + clocks = <&clk_gsp>, <&clk_gsp_emc>, <&clk_256m>, <&clk_aon_apb>; + gsp_mmu_ctrl_base = <0x20b08000>; + }; + + sprd_fm: sprd_fm@40270000{ + compatible = "sprd,sprd_fm"; + reg = <0 0x40270000 0 0x1000>; + }; + + sipc: sipc@0x87800000 { + compatible = "sprd,sipc"; + reg = <0 0x87800000 0 0x540000>; /* <SMEM SIZE>*/ + //#interrupt-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + ranges =<0x09600000 0 0x89600000 0x4000000>, + <0x07800000 0 0x87800000 0x540000>, + <0x0d5ff000 0 0x8d5ff000 0x1000>; + sipc_lte@0x09600000 { + sprd,name = "sipc-lte"; + sprd,dst = <5>; + /* it's unnecessary to config IPI info upon mailbox arch */ + mailbox,core = <7>; + reg = <0x09600000 0x4000000> , /* <CP_start_addr size> */ + <0x07800000 0x540000>, /* <SMEM_phy_addr total_size> */ + <0x0d5ff000 0x1000>; /* smsg ring buffer <base size> */ + }; + }; + + sctrl_pmic{ + compatible = "sprd,sctrl"; + sprd,name = "sctrl_pmic"; + sprd,dst = <6>; + sprd,channel= <1>; + sprd,ringnr = <1>; + /* it's unnecessary to config IPI info upon mailbox arch */ + mailbox,core = <1>; + sprd,ringbase = <0x5000b000>; /*SMSG ring mem base phy address*/ + sprd,size-rxbuf = <0x0400>; /* 2*1024*/ + sprd,size-txbuf = <0x0400>; /* 2*1024 */ + }; + + saudio_lte{ + compatible = "sprd,saudio"; + sprd,saudio-dst-id = <5>; /* SIPC_ID_LTE */ + sprd,ctrl_channel = <10>; /* SMSG_CH_VBC */ + sprd,playback_channel = <11>; /* SMSG_CH_PLAYBACK */ + sprd,capture_channel = <12>; /* SMSG_CH_CAPTURE */ + sprd,monitor_channel = <13>; /*SMSG_CH_MONITOR_AUDIO */ + sprd,saudio-names = "saudiolte"; + }; + + saudio_voip{ + compatible = "sprd,saudio"; + sprd,saudio-dst-id = <5>; /* SIPC_ID_LTE */ + sprd,ctrl_channel = <14>; /* SMSG_CH_CTRL_VOIP */ + sprd,playback_channel = <15>; /* SMSG_CH_PLAYBACK_VOIP */ + sprd,capture_channel = <16>; /* SMSG_CH_CAPTURE_VOIP */ + sprd,monitor_channel = <17>; /*SMSG_CH_MONITOR_VOIP */ + sprd,saudio-names = "saudiovoip"; + }; + + /* LTE modem virtual devices */ + spipe_lte { + compatible = "sprd,spipe"; + sprd,name = "spipe_lte"; + sprd,dst = <5>; + sprd,channel = <4>; + sprd,ringnr = <9>; + sprd,size-rxbuf = <0x1000>; /* 4*1024 */ + sprd,size-txbuf = <0x1000>; /* 4*1024 */ + }; + + slog_lte { + compatible = "sprd,spipe"; + sprd,name = "slog_lte"; + sprd,dst = <5>; + sprd,channel = <5>; + sprd,ringnr = <1>; + sprd,size-rxbuf = <0x40000>; /* 256*1024*/ + sprd,size-txbuf = <0x8000>; /* 32*1024 */ + }; + + stty_lte { + compatible = "sprd,spipe"; + sprd,name = "stty_lte"; + sprd,dst = <5>; + sprd,channel = <6>; + sprd,ringnr = <32>; + sprd,size-rxbuf = <0x0800>; /* 2*1024*/ + sprd,size-txbuf = <0x0800>; /* 2*1024 */ + }; + + seth0_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte0"; + sprd,dst = <5>; + sprd,channel = <7>; + sprd,blknum = <256>; + }; + + seth1_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte1"; + sprd,dst = <5>; + sprd,channel = <8>; + sprd,blknum = <256>; + }; + + seth2_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte2"; + sprd,dst = <5>; + sprd,channel = <9>; + sprd,blknum = <256>; + }; + + seth3_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte3"; + sprd,dst = <5>; + sprd,channel = <18>; + sprd,blknum = <256>; + }; + + seth4_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte4"; + sprd,dst = <5>; + sprd,channel = <19>; + sprd,blknum = <256>; + }; + + seth5_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte5"; + sprd,dst = <5>; + sprd,channel = <20>; + sprd,blknum = <256>; + }; + scproc_arm7: scproc@0x50800000 { + compatible = "sprd,scproc"; + sprd,name = "cppmic"; + sprd,ctrl-reg = <0x114 0xff 0xb0 0xff>; /* <shut_down deep_sleep reset get_status> */ + sprd,ctrl-mask = <0x01 0xfffffffe 0x100 0xf0000>; /* masks <> */ + sprd,iram-data = <0xe59f0000 0xe12fff10 0x0>; /* 3rd param equals modem_addr*/ + reg = <0 0x50800000 0 0x8000>, /* <CP_start_addr total_size> = <+128M 26M> */ + <0 0x50800000 0 0x0>, /* <iram1_base size> */ + <0 0x402e0000 0 0x400>, /* <aon_apb_base size> */ + <0 0x402b0000 0 0x100>, /* <pmu_base size> */ + <0 0x402b0000 0 0x100>, /* <pmu_base size> */ + <0 0x402b0000 0 0x100>; /* <pmu_base size> */ + #address-cells = <1>; + #size-cells = <1>; + /* segnr=1 */ + ranges = <0x0 0 0x50800000 0x8000>; + modem@0x0 { + cproc,name = "modem"; + reg = <0x0 0x8000>; /* <modem_addr size> */ + }; + }; + + scproc_cp1: scproc@0x89600000 { + compatible = "sprd,scproc"; + sprd,name = "cptl"; + sprd,ctrl-reg = <0x0c 0xff 0xb0 0x78>; /* <shut_down deep_sleep reset get_status> */ + sprd,ctrl-mask = <0x00300000 0x10000000 0x02 0x1>; /* masks <> */ + sprd,iram-data = <0xe59f0000 0xe12fff10 0x8ae00000>; /* 3rd param equals modem_addr*/ + reg = <0 0x89600000 0 0x4000000>, /* <CP_start_addr total_size> = <+128M 26M> */ + <0 0x50001000 0 0x0c>, /* <iram1_base size> */ + <0 0x402e0000 0 0x100>, /* <aon_apb_base size> */ + <0 0x402b0000 0 0x100>, /* <pmu_base size> */ + <0 0x402b0000 0 0x100>, /* <pmu_base size> */ + <0 0x402b0000 0 0x100>; /* <pmu_base size> */ + interrupts = <0 84 0x0>; /* cp1_wdg_int */ + #address-cells = <1>; + #size-cells = <1>; + /* segnr=2 */ + ranges = <0x1800000 0 0x8ae00000 0x03100000>, + <0x20000 0 0x89620000 0x00320000>; + modem@0x1800000 { + cproc,name = "modem"; + reg = <0x1800000 0x31000000>; /* <modem_addr size> */ + }; + dsp@0x20000 { + cproc,name = "tgdsp"; + reg = <0x20000 0x002e0000>; /* <dsp_addr size>*/ + }; + dsp@0x300000 { + cproc,name = "ldsp"; + reg = <0x300000 0x1c0000>; /* <dsp_addr size>*/ + }; + }; + + itm_wlan{ + compatible = "sprd,itm_wlan"; + }; + + dmac: dmac@20100000 { + compatible = "sprd,sprd-dma"; + interrupts = <0 50 0x0>; + reg = <0 0x20100000 0 0x4000>; + }; + + gpu@60000000 { + compatible = "arm,mali-400", "arm,mali-utgard"; + reg = <0 0x60000000 0 0x10000>; + interrupts = <0 39 0>, <0 39 0>, <0 39 0>, <0 39 0>, <0 39 0>, <0 39 0>, <0 39 0>; + interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1", "IRQPMU"; + + clocks = <&clk_gpu_axi>,<&clk_gpu>,<&clk_153m6>,<&clk_192m>,<&clk_256m>,<&clk_307m2>,<&clk_384m>,<&clk_512m>; + clock-names = "clk_gpu_axi","clk_gpu","clk_153m6","clk_192m","clk_256m","clk_307m2","clk_384m","clk_512m"; + + freq-list-len = <6>; + freq-lists = <64000 4 4>, <102400 5 3>, <153600 2 1>, <256000 4 1>, <384000 6 1>, <512000 7 1>; + freq-default = <3>; + freq-9 = <4>; + freq-8 = <3>; + freq-7 = <2>; + freq-5 = <0>; + freq-0 = <4>; + }; + + ion { + compatible = "sprd,ion-sprd"; + #address-cells = <1>; + #size-cells = <0>; + + sprd,ion-heap@1 { + reg = <1>; /* SYSTEM */ + reg-names = "ion_heap_system"; + sprd,ion-heap-type = <0>; /* SYSTEM */ + sprd,ion-heap-mem = <0x0 0x0>; + }; + + sprd,ion-heap@2 { + reg = <2>; /* MM */ + reg-names = "ion_heap_carveout_mm"; + sprd,ion-heap-type = <0>; /* carveout mm */ + sprd,ion-heap-mem = <0x9864F000 0x7100000>; + }; + + sprd,ion-heap@3 { + reg = <3>; /* OVERLAY */ + reg-names = "ion_heap_carveout_overlay"; + sprd,ion-heap-type = <2>; /* CARVEOUT */ + sprd,ion-heap-mem = <0x9FC00000 0x400000>; /* 480*854*4*2, 1M alignment */ + }; + }; + + sprd_iommu0: sprd_iommu@20b00000 { + compatible = "sprd,sprd_iommu";//gsp + func-name = "sprd_iommu_gsp"; + reg = <0 0x10000000 0 0x2000000>, //iova + <0 0x20b00000 0 0x8000>, //pgt + <0 0x20b08000 0 0x8000>; //ctrl_reg + reg_name = "iova","pgt","ctrl_reg"; + clock-names = "clk_gsp_emc","clk_153m6","clk_gsp"; + clocks = <&clk_gsp_emc>, <&clk_153m6>,<&clk_gsp>; + status = "ok"; + }; + + sprd_iommu1: sprd_iommu@60f00000 { + compatible = "sprd,sprd_iommu";//mm + func-name = "sprd_iommu_mm"; + reg = <0 0x20000000 0 0x8000000>, //iova + <0 0x60f00000 0 0x20000>, //pgt + <0 0x60f20000 0 0x2000>; //ctrl_reg + reg_name = "iova","pgt","ctrl_reg"; + clock-names = "clk_mmu","clk_mm_i"; + clocks = <&clk_mmu>,<&clk_mm>; + status = "ok"; + }; + + sprd_vsp: sprd_vsp@60900000{ + compatible = "sprd,sprd_vsp"; + reg = <0 0x60900000 0 0xc000>; + interrupts = <0 43 0x0>; + clock-names = "clk_mm_i", "clk_vsp", "clk_parent_0", "clk_parent_1", "clk_parent_2", "clk_parent_3"; + clocks = <&clk_mm>, <&clk_vsp>, <&clk_307m2>, <&clk_256m>, <&clk_128m>, <&clk_96m>; + clock-parent-info = <2 4>; + version = <6>; + }; + + sprd_jpg { + compatible = "sprd,sprd_jpg"; + reg = <0 0x60b00000 0 0x8000>; + interrupts = <0 42 0x0>; + clock-names = "clk_mm_i","clk_jpg"; + clocks = <&clk_mm>, <&clk_jpg>; + }; + sprd_bm { + compatible = "sprd,sprd_bm"; + reg = <0 0x30040000 0 0xA0000 + 0 0x20F00000 0 0x300000>; + interrupts = <0 86 0x0>; + sprd,bm_status = <1>; + sprd,bm_count = <10 11>; + sprd,cpu_chn = <0>; + sprd,disp_chn = <1>; + sprd,gpu_chn = <2>; + sprd,ap_zip_chn = <3>; + sprd,mm_chn = <4>; + sprd,cp0_arm1_chn = <5>; + sprd,cp0_dsp_chn = <6>; + sprd,cp1_lte_chn = <7>; + sprd,cp1_dsp_chn = <8>; + sprd,cp1_arm_chn = <9>; + sprd,ap_dap_chn = <0 0>; + sprd,ap_cpu_chn = <0 1>; + sprd,ap_dma_w_chn = <0 2>; + sprd,ap_dma_r_chn = <0 3>; + sprd,ap_sdio_0_chn = <1 0>; + sprd,ap_sdio_1_chn = <1 1>; + sprd,ap_sdio_2_chn = <1 2>; + sprd,ap_emmc_chn = <1 3>; + sprd,ap_nandc_chn = <2 0>; + sprd,ap_otg_chn = <2 1>; + sprd,ap_hsic_chn = <2 2>; + }; + wdt@40290000 { + compatible = "sprd,sprd-wdt"; + reg = <0 0x40290000 0 0x1000>, + <0 0x40310000 0 0x1000>; + interrupts = <0 124 0x0>; + }; + + sprd-marlin { + compatible = "sprd,marlin"; + gpios = <&d_gpio_gpio 97 0 /*marlin gpio0 */ + &d_gpio_gpio 132 0 /*marlin gpio1 */ + &d_gpio_gpio 133 0 /*marlin gpio2 */ + &d_gpio_gpio 94 0 /*marlin gpio3 */ + &d_gpio_gpio 122 0>; /*marlin reset*/ + cp-rfctl-offset = <0x244>; /*coex func. marlin gpio3*/ + vdd-download = "vddcon"; /*vdd 1.6v*/ + vdd-pa = "vddwifipa"; /*vdd 3.3v*/ + clk-name = "clk_aux0"; /*clk 32k*/ + sdhci-name = "sdio_wifi"; + }; +}; + +&vbc_r2p0 { + status = "okay"; +}; + +&sprd_codec { + status = "okay"; + sprd,audio_power_ver = <4>; +}; + +&i2s0 { + sprd,config_type = "pcm"; + sprd,slave_timeout = <0xF11>; + sprd,_hw_port = <0>; + sprd,fs = <8000>; + sprd,bus_type = <1>; + sprd,rtx_mode = <3>; + sprd,byte_per_chan = <1>; + sprd,slave_mode = <0>; + sprd,lsb = <0>; + sprd,lrck = <0>; + sprd,low_for_left = <1>; + sprd,clk_inv = <0>; + sprd,pcm_short_frame = <1>; + sprd,pcm_slot = <0x1>; + sprd,pcm_cycle = <1>; + sprd,tx_watermark = <12>; + sprd,rx_watermark = <20>; + status = "okay"; +}; + +&i2s1 { + status = "okay"; +}; + +&i2s2 { + status = "okay"; +}; + +&i2s3 { + status = "okay"; +}; + +&i2s_sound { + sprd,i2s = <&i2s0>, <&i2s1>, <&i2s2>, <&i2s3>; +}; + +&sprd_battery { + gpios = <&a_eic_gpio 0 0 /* chg int */ + &a_eic_gpio 4 0 /* cv state */ + &a_eic_gpio 6 0 /* chg ovi */ + &a_eic_gpio 9 0>; /* battery detect */ + + fgu-mode = <0>; + alm-soc = <5>; + alm-vol = <3500>; + soft-vbat-uvlo = <3100>; + rint = <250>; + cnom = <1900>; + rsense-real = <230>; + rsense-spec = <200>; + relax-current = <50>; + fgu-cal-ajust = <0>; + ocv-tab-size = <21>; + ocv-tab-vol = <4168 4113 4076 4016 3973 3953 3924 3894 3851 3821 3802 3789 3780 3777 3771 3758 3738 3703 3684 3609 3400>; + ocv-tab-cap = <100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0>; +}; diff --git a/arch/arm64/boot/dts/sprd_sp9836aea_4mod.dts b/arch/arm64/boot/dts/sprd_sp9836aea_4mod.dts new file mode 100644 index 00000000..eb318beb --- /dev/null +++ b/arch/arm64/boot/dts/sprd_sp9836aea_4mod.dts @@ -0,0 +1,1344 @@ +/* + * SPREADTRUM Ltd.clock-cells +sprd_rotation + * + * SharkL64 4mod refphone DTS + */ + +/dts-v1/; + +/* memory reserved for SMEM */ +/memreserve/ 0x87800000 0x5B0000; /* Offset:120M, Size:5M+256K */ + +/* memory reserved for WARM modem */ +/memreserve/ 0x8d900000 0xD00000; /* Offset:217M, Size:13M */ + +/* memory reserved for LTE modem */ +/memreserve/ 0x89600000 0x4300000; /* Offset:150M, Size:67M*/ + +/* memory reserved for fb */ +/memreserve/ 0x9F74F000 0x4B1000; /* 480*854*4*3, 4K alignment*/ + +/* memory reserved for ION */ +/memreserve/ 0x9FC00000 0x400000; /* 480*854*4*2, 1M alignment*/ + +/* memory reserved for smp */ +/memreserve/ 0x9F700000 0x1000; /* size 4K*/ + +/include/ "sc2723-regulators.dtsi" +/include/ "sprd-sound.dtsi" +/include/ "sprd-battery.dtsi" +/include/ "scx35l64-clocks.dtsi" + +/ { + model = "scx35l64"; + compatible = "sprd,TsharkL"; + sprd,sc-id = <8830 1 0x20000>; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { + bootargs = "earlyprintk=sprd_uart,0x70100000 loglevel=7 console=ttyS1,115200n8"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP>; + }; + cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP>; + }; + idle-states{ + entry-method = "arm,psci"; + LIGHT_SLEEP: light_sleep { + compatible = "arm,idle-state"; + exit-latency-us = <100>; + min-residency-us = <500>; + entry-method-param = <0x00000001>; + }; + CORE_PD: core_pd { + compatible = "arm,idle-state"; + exit-latency-us = <1070>; + min-residency-us = <1600>; + entry-method-param = <0x00010002>; + }; + CLUSTER_PD: cluster_pd { + compatible = "arm,idle-state"; + exit-latency-us = <1100>; + min-residency-us = <2500>; + entry-method-param = <0x01010003>; + }; + DEEP_SLEEP: deep_sleep { + compatible = "arm,idle-state"; + exit-latency-us = <4100>; + min-residency-us = <6500>; + entry-method-param = <0x01010004>; + }; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0 0x80000000 0 0x40000000>; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + lcd0 = &fb0; + hwspinlock0 = &hwspinlock0; + hwspinlock1 = &hwspinlock1; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 92 4>, + <0 93 4>, + <0 94 4>, + <0 95 4>; + }; + + psci { + compatible = "arm,psci"; + method = "smc"; + cpu_on = <0xc4000003>; + cpu_off = <0x84000002>; + cpu_suspend = <0xc4000001>; + }; + + gic: interrupt-controller@12001000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0x12001000 0 0x1000>, + <0 0x12002000 0 0x1000>; + }; + + intc:interrupt-controller@71400000 { + compatible = "sprd,intc"; + #interrupt-cells = <0>; + interrupt-controller; + reg = <0 0x71400000 0 0x1000>, + <0 0x71500000 0 0x1000>, + <0 0x71600000 0 0x1000>, + <0 0x71700000 0 0x1000>, + <0 0x40200000 0 0x1000>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, + <1 14 0xff01>, + <1 11 0xff01>, + <1 10 0xff01>; + clock-frequency = <26000000>; + }; + + sprd_timer { + compatible = "sprd,sharkl64-timer"; + reg = <0 0x40050000 0 0x20>; /*aon GPTIMER0 */ + interrupts = <0 28 0x0>; + clock-frequency = <32768>; + }; + + sprd_ap_system_timer { + reg = <0 0x40230000 0 0x20>; + interrupts = <0 31 0x0>; + }; + + clock: clockdevice { + compatible = "sprd,scx35l64-clocks"; + #clock-cells = <1>; + }; + + d_eic_gpio: gpio@40210000 { + compatible = "sprd,d-eic-gpio"; + reg = <0 0x40210000 0 0x1000>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-cells = <2>; + gpiobase = <288>; + ngpios = <16>; + interrupts = <0 37 0x0>; + }; + + d_gpio_gpio: gpio@40280000 { + compatible = "sprd,d-gpio-gpio"; + reg = <0 0x40280000 0 0x1000>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-cells = <2>; + gpiobase = <0>; + ngpios = <256>; + interrupts = <0 35 0x0>; + }; + + uart0: uart@70000000 { + compatible = "sprd,serial"; + interrupts = <0 2 0xf04>; + reg = <0 0x70000000 0 0x1000>; + clock-names = "clk_uart0"; + clocks = <&clock 60>; + sprdclk = <48000000>; + sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP"; + + }; + + uart1: uart@70100000 { + compatible = "sprd,serial"; + interrupts = <0 3 0xf04>; + reg = <0 0x70100000 0 0x1000>; + clock-names = "clk_uart1"; + clocks = <&clock 61>; + sprdclk = <26000000>; + sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP"; + + }; + + uart2: uart@70200000 { + compatible = "sprd,serial"; + interrupts = <0 4 0xf04>; + reg = <0 0x70200000 0 0x1000>; + clock-names = "clk_uart2"; + clocks = <&clock 62>; + sprdclk = <26000000>; + sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP"; + }; + + uart3: uart@70300000 { + compatible = "sprd,serial"; + interrupts = <0 5 0xf04>; + reg = <0 0x70300000 0 0x1000>; + clock-names = "clk_uart3"; + clocks = <&clock 63>; + sprdclk = <26000000>; + sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP"; + }; + + hwspinlock0: hwspinlock0@20c00000{ + compatible = "sprd,sprd-hwspinlock"; + reg = <0 0x20c00000 0 0x1000>; + hwspinlock_cnt = <32>; + }; + + hwspinlock1: hwspinlock1@40060000{ + compatible = "sprd,sprd-hwspinlock"; + reg = <0 0x40060000 0 0x1000>; + hwspinlock_cnt = <32>; + status = "ok"; + }; + + watchdog { + compatible = "sprd,watchdog"; + reg = <0 0X40290000 0 0x1000>; + }; + + pinctrl { + compatible = "sprd,pinctrl"; + reg = <0 0x402a0000 0 0x1000>; + pwr_domain = "vdd28", + "vdd28", + "vddsim0", + "vddsim1", + "vddsim2", + "vddsdio", + "vdd18"; + ctrl_desc = <0x10 0 1 + 0x10 1 1 + 0x10 2 1 + 0x10 3 1 + 0x10 4 1 + 0x10 5 1 + 0x10 6 1>; + }; + + sdios{ + #address-cells = <2>; + #size-cells = <2>; + ranges; + sdio3: sdio@20600000{ + compatible = "sprd,sdhost-3.0"; + reg = <0 0x20600000 0 0x1000>; + interrupts = <0 60 0x0>; + sprd,name = "sdio_emmc"; + /*detect_gpio = <-1>; */ + SD_Pwr_Name = "vddemmccore"; + _1_8V_signal_Name = "vddgen1"; + signal_default_Voltage = <1800000>; + ocr_avail = <0x00040000>; + clocks = <&clk_emmc>, <&clk_384m>; + base_clk = <384000000>; + caps = <0xC00F8D47>; + caps2 = <0x202>; + pm_caps = <0x4>; + writeDelay = <0x3E>; + readPosDelay = <0xA>; + readNegDelay = <0xA>; + }; + + sdio0: sdio@20300000{ + compatible = "sprd,sdhost-3.0"; + reg = <0 0x20300000 0 0x1000>; + interrupts = <0 57 0x0>; + sprd,name = "sdio_sd"; + detect_gpio = <141>; + SD_Pwr_Name = "vddsdcore"; + /* _1_8V_signal_Name = "vddsdio"; */ + signal_default_Voltage = <3000000>; + ocr_avail = <0x00040000>; + clocks = <&clk_sdio0>, <&clk_384m>; + base_clk = <384000000>; + caps = <0xC0000407>; + caps2 = <0x200>; + pm_caps = <0x4>; + writeDelay = <0x3>; + readPosDelay = <0x3>; + readNegDelay = <0x3>; + }; + + + sdio1: sdio@20400000{ + compatible = "sprd,sdhost-3.0"; + reg = <0 0x20400000 0 0x1000>; + interrupts = <0 58 0x0>; + sprd,name = "sdio_wifi"; + /* detect_gpio = <-1>; */ + /* SD_Pwr_Name = "vddsdcore"; */ + /* _1_8V_signal_Name = "vddsdio";*/ + /* signal_default_Voltage = <3000000>; */ + ocr_avail = <0x00360080>; + clocks = <&clk_sdio1>, <&clk_76m8>; + base_clk = <96000000>; + caps = <0xC00FA407>; + caps2 = <0x0>; + pm_caps = <0x5>; + writeDelay = <0x03>; + readPosDelay = <0x03>; + readNegDelay = <0x03>; + }; + }; + + adic:adic { + compatible = "sprd,adi"; + reg = <0 0x40030000 0 0x10000>; + }; + + adi: adi_bus { + compatible = "sprd,adi-bus"; + interrupts = <0 38 0x0>; + reg = <0 0x40038000 0 0x1000>; + interrupt-controller; + sprd,irqnums = <11>; + #interrupt-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x100 0 0x40038100 0x80>; + + keyboard_backlight { + compatible = "sprd,keyboard-backlight"; + }; + a_eic_gpio: gpio@100{ + compatible = "sprd,a-eic-gpio"; + reg = <0x100 0x80>; /* adi reg */ + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-cells = <2>; + gpiobase = <304>; + ngpios = <16>; + interrupt-parent = <&adi>; + interrupts = <5 0x0>; /* ext irq 5 */ + }; + sprd_eic_keys { + compatible = "sprd,sprd-eic-keys"; + input-name = "sprd-eic-keys"; + key_power { + label = "Power Key"; + linux,code = <116>; + gpios = <&a_eic_gpio 2 0>; + debounce-interval = <2>; + gpio-key,wakeup; + }; + }; + + headset_sprd_sc2723 { + compatible = "sprd,headset_sprd_sc2723"; + gpio_switch = <0>; + gpio_detect = <312>; + gpio_button = <307>; + irq_trigger_level_detect = <1>; + irq_trigger_level_button = <1>; + adc_threshold_3pole_detect = <300>; + adc_threshold_4pole_detect = <3270>; + irq_threshold_buttont = <1>; + voltage_headmicbias = <3000000>; + nbuttons = <3>; + headset_buttons_media { + adc_min = <0>; + adc_max = <550>; + code = <226>; + type = <0>; + }; + + headset_buttons_up { + adc_min = <551>; + adc_max = <1114>; + code = <115>; + type = <0>; + }; + headset_buttons_down { + adc_min = <1115>; + adc_max =<3000>; + code = <114>; + type = <0>; + }; + }; + + rtc@80{ + compatible = "sprd,rtc"; + reg = <0X80 0x80>; + interrupt-parent = <&adi>; + interrupts = <2 0x0>; + }; + }; + + sprd_pwm_bl { + compatible = "sprd,sprd_pwm_bl"; + brightness_max = <255>; + brightness_min = <0>; + pwm_index = <2>; + gpio_ctrl_pin = <0>; + gpio_active_level = <0>; + reg =<0 0x40260000 0 0xf>; + }; + + gpio_keys { + compatible = "gpio-keys"; + input-name = "sprd-gpio-keys"; + key_volumedown { + label = "Volumedown Key"; + linux,code = <114>; + gpios = <&d_gpio_gpio 124 1>; + debounce-interval = <2>; + gpio-key,wakeup; + }; + key_volumeup { + label = "Volumeup Key"; + linux,code = <115>; + gpios = <&d_gpio_gpio 125 1>; + debounce-interval = <2>; + gpio-key,wakeup; + }; + }; + + sprd_backlight { + compatible = "sprd,sprd_backlight"; + start = <3>; + end = <3>; + flags = <0x100>; + }; + + rfkill { + compatible = "broadcom,rfkill"; + gpios = <&d_gpio_gpio 131 0 /* power */ + &d_gpio_gpio 122 0>; /* reset */ + }; + bluesleep { + compatible = "broadcom,bluesleep"; + bt-wake-gpio = <&d_gpio_gpio 132 0>; + host-wake-gpio = <&d_gpio_gpio 133 0>; + }; + + usb: usb@20200000{ + compatible = "sprd,usb"; + interrupts = <0 55 0x0>; + ngpios = <1>; + gpios = <&a_eic_gpio 0 0>; + reg = <0 0x20200000 0 0x1000>; + tune_value = <0x44073e33>; + usb-supply = <&vddusb>; + #address-cells = <1>; + #size-cells = <0>; + }; + sprd_thermal: thermal@402F0000{ + compatible = "sprd,sprd-thermal"; + id = <0>; + interrupts = <0 26 0x0>; + reg = <0 0x402F0000 0 0x1000>; + trip_points_active = <65 69 95 110>; + trip_points_lowoff = <0 57 60 80>; + trip_points_critical = <110>; + trip_num = <5>; + }; + sprd_thermal1:thermal1@402F0000 { + compatible = "sprd,sprd-thermal"; + id = <1>; + interrupts = <0 26 0x0>; + reg = <0 0x402F0000 0 0x1000>; + trip_points_active = <110>; + trip_points_lowoff = <90>; + trip_points_critical = <110>; + trip_num = <2>; + }; + sprd_thermal2: thermal@40038280{ + compatible = "sprd,sprd-thermal"; + id = <2>; + interrupt-parent = <&adi>; + interrupts = <9 0x0>; + reg = <0 0x40038280 0 0x1000>; + trip_points_active = <110>; + trip_points_lowoff = <90>; + trip_points_critical = <110>; + trip_num = <2>; + }; + + adc: adc@40038300{ + compatible = "sprd,sprd-adc"; + reg = <0x40038300 0x1000>; + }; + i2c0: i2c@70500000{ + compatible = "sprd,i2c"; + interrupts = <0 11 0x0>; + reg = <0 0x70500000 0 0x1000>; + clock-names = "clk_i2c0"; + clocks = <&clk_i2c0>; + #address-cells = <1>; + #size-cells = <0>; + sensor_main@0x3c { + compatible = "sprd,sensor_main"; + reg = <0x3c>; + }; + sensor_sub@0x21 { + compatible = "sprd,sensor_sub"; + reg = <0x21>; + }; + }; + + i2c1: i2c@70600000{ + compatible = "sprd,i2c"; + interrupts = <0 12 0x0>; + reg = <0 0x70600000 0 0x1000>; + clock-names = "clk_i2c1"; + clocks = <&clk_i2c1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@70700000{ + compatible = "sprd,i2c"; + interrupts = <0 13 0x0>; + reg = <0 0x70700000 0 0x1000>; + clock-names = "clk_i2c2"; + clocks = <&clk_i2c2>; + #address-cells = <1>; + #size-cells = <0>; + + lis3dh_acc@18{ + compatible = "ST,lis3dh_acc"; + reg = <0x18>; + poll_interval = <10>; + min_interval = <10>; + g_range = <0>; + axis_map_x = <0>; + axis_map_y = <1>; + axis_map_z = <2>; + negate_x = <1>; + negate_y = <1>; + negate_z = <0>; + }; + ltr_558als@23{ + compatible = "LITEON,ltr_558als"; + reg = <0x23>; + gpios = <&d_gpio_gpio 140 0>; + }; + epl2182_pls@49{ + compatible = "ELAN,epl2182_pls"; + reg = <0x49>; + gpios = <&d_gpio_gpio 140 0>; + }; + }; + + i2c3: i2c@70800000{ + compatible = "sprd,i2c"; + interrupts = <0 14 0x0>; + reg = <0 0x70800000 0 0x1000>; + clock-names = "clk_i2c3"; + clocks = <&clk_i2c3>; + #address-cells = <1>; + #size-cells = <0>; + + focaltech_ts@38{ + compatible = "focaltech,focaltech_ts"; + reg = <0x38>; + gpios = <&d_gpio_gpio 145 0 + &d_gpio_gpio 144 0>; + vdd_name = "vdd28"; + virtualkeys = <80 900 60 45 + 240 900 60 45 + 400 900 60 45>; + TP_MAX_X = <480>; + TP_MAX_Y = <800>; + }; + msg2138_ts@26{ + compatible = "Mstar,msg2138_ts"; + reg = <0x26>; + gpios = <&d_gpio_gpio 145 0 + &d_gpio_gpio 144 0>; + vdd_name = "vdd28"; + virtualkeys = <256 1068 64 64 + 128 1068 64 64 + 192 1068 64 64>; + TP_MAX_X = <480>; + TP_MAX_Y = <800>; + }; + }; + + i2c4: i2c@70900000{ + compatible = "sprd,i2c"; + interrupts = <0 15 0x0>; + reg = <0 0x70900000 0 0x1000>; + clock-names = "clk_i2c4"; + clocks = <&clk_i2c4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi0: spi0@70a00000{ + compatible = "sprd,sprd-spi"; + interrupts = <0 7 0x0>; + reg = <0 0x70a00000 0 0x1000>; + clock-names = "clk_spi0"; + }; + + spi1: spi1@70b00000{ + compatible = "sprd,sprd-spi"; + interrupts = <0 8 0x0>; + reg = <0 0x70b00000 0 0x1000>; + clock-names = "clk_spi1"; + }; + + spi2: spi2@70c00000{ + compatible = "sprd,sprd-spi"; + interrupts = <0 9 0x0>; + reg = <0 0x70c00000 0 0x1000>; + clock-names = "clk_spi2"; + }; + + dma: dma-controller@20100000 { + compatible = "sprd,sharkl64-dma"; + #dma-cells = <1>; + #dma-channels = <64>; + sprd,aon-offset = <32>; + reg = <0 0x20100000 0 0x4000>, /* ap reg */ + <0 0x40100000 0 0x4000>; /* aon reg */ + interrupts = <0 50 0x0>, /* ap int */ + <0 70 0x0>; /* aon int */ + }; + + sprd-io-base { + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 1 0>; + ahb { + compatible = "sprd,ahb"; + reg = <0 0x20e00000 0 0x40000>; + }; + apbckg { + compatible = "sprd,apbckg"; + reg = <0 0x21500000 0 0x1000>; + }; + hwlock0 { + compatible = "sprd,hwlock0"; + reg = <0 0x20d00000 0 0x1000>; + }; + pub_apb { + compatible = "sprd,pub_apb"; + reg = <0 0x30020000 0 0x10000>; + }; + aon_apb { + compatible = "sprd,aon_apb"; + reg = <0 0x402e0000 0 0x40000>; + }; + pmu_apb { + compatible = "sprd,pmu_apb"; + reg = <0 0x402b0000 0 0x40000>; + }; + mm_ahb { + compatible = "sprd,mm_ahb"; + reg = <0 0x60d00000 0 0x10000>; + }; + mm_clk { + compatible = "sprd,mm_clk"; + reg = <0 0x60e00000 0 0x1000>; + }; + ap_ckg { + compatible = "sprd,ap_ckg"; + reg = <0 0x71200000 0 0x40000>; + }; + ap_apb { + compatible = "sprd,ap_apb"; + reg = <0 0x71300000 0 0x40000>; + }; + gpu_apb { + compatible = "sprd,gpu_apb"; + reg = <0 0x60100000 0 0x1000>; + }; + adi { + compatible = "sprd,adi"; + reg = <0 0x40030000 0 0x10000>; + }; + adi_slave { + compatible = "sprd,adi_slave"; + reg = <0 0x40038000 0 0x1000>; + }; + mailbox { + compatible = "sprd,mailbox"; + reg = <0 0x400a0000 0 0x10000>; + }; + uart0 { + compatible = "sprd,uart0"; + reg = <0 0x70000000 0 0x1000>; + }; + uart1 { + compatible = "sprd,uart1"; + reg = <0 0x70100000 0 0x1000>; + }; + uart2 { + compatible = "sprd,uart2"; + reg = <0 0x70200000 0 0x1000>; + }; + uart3 { + compatible = "sprd,uart3"; + reg = <0 0x70300000 0 0x1000>; + }; + uart4 { + compatible = "sprd,uart4"; + reg = <0 0x70400000 0 0x1000>; + }; + axibm0 { + compatible = "sprd,axibm0"; + reg = <0 0x30040000 0 0x20000>; + interrupts = <0 86 0x0>; + }; + d_eic_gpio { + compatible = "sprd,d-eic-gpio"; + reg = <0 0x40210000 0 0x1000>; + }; + d_gpio_gpio { + compatible = "sprd,d-gpio-gpio"; + reg = <0 0x40280000 0 0x1000>; + }; + aon_dma { + compatible = "sprd,aon_dma"; + reg = <0 0x40100000 0 0x1000>; + interrupts = <0 50 0x0>; + }; + pwm { + compatible = "sprd,pwm"; + reg = <0 0x40260000 0 0x1000>; + }; + core { + compatible = "sprd,core"; + reg = <0 0x12000000 0 0x10000>; + }; + int { + compatible = "sprd,int"; + reg = <0 0x40200000 0 0x1000>; + }; + intc0 { + compatible = "sprd,intc0"; + reg = <0 0x71400000 0 0x1000>; + }; + intc1 { + compatible = "sprd,intc1"; + reg = <0 0x71500000 0 0x1000>; + }; + intc2 { + compatible = "sprd,intc2"; + reg = <0 0x71600000 0 0x1000>; + }; + intc3 { + compatible = "sprd,intc3"; + reg = <0 0x71700000 0 0x1000>; + }; + send_mbox { + compatible = "sprd,send_mbox"; + reg = <0 0x400a0000 0 0x1000>; + }; + recv_mbox { + compatible = "sprd,recv_mbox"; + reg = <0 0x400a8000 0 0x1000>; + }; + uidefuse { + compatible = "sprd,uidefuse"; + reg = <0 0x40240000 0 0x1000>; + }; + isp { + compatible = "sprd,isp"; + reg = <0 0x60a00000 0 0x8000>; + }; + csi2 { + compatible = "sprd,csi2"; + reg = <0 0x60c00000 0 0x1000>; + }; + ipi { + compatible = "sprd,ipi"; + reg = <0 0x402c0000 0 0x1000>; + }; + dcam { + compatible = "sprd,dcam"; + reg = <0 0x60800000 0 0x10000>; + }; + syscnt { + compatible = "sprd,syscnt"; + reg = <0 0x40230000 0 0x1000>; + }; + dma0 { + compatible = "sprd,dma0"; + reg = <0 0x20100000 0 0x4000>; + }; + pub { + compatible = "sprd,pub"; + reg = <0 0x30020000 0 0x10000>; + }; + pin { + compatible = "sprd,pin"; + reg = <0 0x402a0000 0 0x1000>; + }; + aonckg { + compatible = "sprd,aonckg"; + reg = <0 0x402d0000 0 0x1000>; + }; + lpddr2 { + compatible = "sprd,lpddr2"; + reg = <0 0x30000000 0 0x1000>; + }; + }; + + sprd_dcam { + compatible = "sprd,sprd_dcam"; + interrupts = <0 45 0>; + reg = <0 0x60800000 0 0x100000>; + clock-names = "clk_mm_i","clk_dcam"; + clocks = <&clk_mm>, <&clk_dcam>; + }; + + sprd_scale { + compatible = "sprd,sprd_scale"; + }; + + sprd_rotation { + compatible = "sprd,sprd_rotation"; + }; + + sprd_sensor { + compatible = "sprd,sprd_sensor"; + reg = <0 0x60c00000 0 0x100000>; + gpios = <&d_gpio_gpio 45 0 /*main reset*/ + &d_gpio_gpio 47 0 /*main powerdown*/ + &d_gpio_gpio 44 0 /*sub reset*/ + &d_gpio_gpio 46 0 + &d_gpio_gpio 0 0 /*main core voltage*/ + &d_gpio_gpio 0 0 + &d_gpio_gpio 0 0 + &d_gpio_gpio 0 0>; /*sub powerdown*/ + clock-names ="clk_mm_i","clk_sensor","clk_ccir","clk_dcam","clk_dcam_mipi"; + clocks = <&clk_mm>,<&clk_sensor>,<&clk_ccir>,<&clk_dcam>,<&clk_dcam_mipi>; + }; + + sprd_isp { + compatible = "sprd,sprd_isp"; + reg = <0 0x60a00000 0 0x100000>; + clock-names = "clk_mm_i","clk_isp"; + clocks = <&clk_mm>, <&clk_isp>; + }; + + sprd_dma_copy { + compatible = "sprd,sprd_dma_copy"; + }; + + fb0: fb@20800000 { + compatible = "sprd,sprdfb"; + reg = <0 0x20800000 0 0x1000>, + <0 0x21800000 0 0x1000>; + interrupts = <0 46 0x0>, + <0 48 0x0>, + <0 49 0x0>; + clock-names = "dispc_clk_parent", "dispc_dbi_clk_parent", "dispc_dpi_clk_parent", "dispc_emc_clk_parent", "dispc_clk", "dispc_dbi_clk", "dispc_dpi_clk", "dispc_emc_clk", "fb_spi_clock", "fb_spi_clock_parent"; + clocks = <&clk_256m>, <&clk_256m>, <&clk_384m>, <&clk_aon_apb>, <&clk_dispc0>, <&clk_dispc0_dbi>, <&clk_dispc0_dpi>, <&clk_disp_emc>, <&clk_spi2>, <&ext_26m>; + clock-src = <256000000 256000000 384000000>; + dpi_clk_div = <7>; + sprd,fb_use_reservemem; + sprd,fb_mem = <0x9F74F000 0x4B1000>; + }; + + gsp@20a00000 { + compatible = "sprd,gsp"; + reg = <0 0x20a00000 0 0x1000>; + interrupts = <0 51 0x0>; + clock-names = "clk_gsp", "clk_gsp_emc", "clk_gsp_parent", "clk_aon_apb"; + clocks = <&clk_gsp>, <&clk_gsp_emc>, <&clk_256m>, <&clk_aon_apb>; + gsp_mmu_ctrl_base = <0x20b08000>; + }; + + sprd_fm: sprd_fm@40270000{ + compatible = "sprd,sprd_fm"; + reg = <0 0x40270000 0 0x1000>; + }; + + sipc: sipc@0x87800000 { + compatible = "sprd,sipc"; + reg = <0 0x87800000 0 0x5B0000>; /* <SMEM SIZE>*/ + //#interrupt-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + ranges =<0x09600000 0 0x89600000 0x4300000>, + <0x07800000 0 0x87800000 0x5B0000>, + <0x0d8ff000 0 0x8d8ff000 0x1000>; + + sipc_lte@0x09600000 { + sprd,name = "sipc-lte"; + sprd,dst = <5>; + /* it's unnecessary to config IPI info upon mailbox arch */ + mailbox,core = <7>; + reg = <0x09600000 0x4300000> , /* <CP_start_addr size> */ + <0x07800000 0x5B0000>, /* <SMEM_phy_addr total_size> */ + <0x0d8ff000 0x1000>; /* smsg ring buffer <base size> */ + }; + }; + + sctrl_pmic{ + compatible = "sprd,sctrl"; + sprd,name = "sctrl_pmic"; + sprd,dst = <6>; + sprd,channel= <1>; + sprd,ringnr = <1>; + /* it's unnecessary to config IPI info upon mailbox arch */ + mailbox,core = <1>; + sprd,ringbase = <0x5000b000>; /*SMSG ring mem base phy address*/ + sprd,size-rxbuf = <0x0400>; /* 2*1024*/ + sprd,size-txbuf = <0x0400>; /* 2*1024 */ + }; + + saudio_lte{ + compatible = "sprd,saudio"; + sprd,saudio-dst-id = <5>; /* SIPC_ID_LTE */ + sprd,ctrl_channel = <10>; /* SMSG_CH_VBC */ + sprd,playback_channel = <11>; /* SMSG_CH_PLAYBACK */ + sprd,capture_channel = <12>; /* SMSG_CH_CAPTURE */ + sprd,monitor_channel = <13>; /*SMSG_CH_MONITOR_AUDIO */ + sprd,saudio-names = "saudiolte"; + }; + + saudio_voip{ + compatible = "sprd,saudio"; + sprd,saudio-dst-id = <5>; /* SIPC_ID_LTE */ + sprd,ctrl_channel = <14>; /* SMSG_CH_CTRL_VOIP */ + sprd,playback_channel = <15>; /* SMSG_CH_PLAYBACK_VOIP */ + sprd,capture_channel = <16>; /* SMSG_CH_CAPTURE_VOIP */ + sprd,monitor_channel = <17>; /*SMSG_CH_MONITOR_VOIP */ + sprd,saudio-names = "saudiovoip"; + }; + + /* LTE modem virtual devices */ + spipe_lte { + compatible = "sprd,spipe"; + sprd,name = "spipe_lte"; + sprd,dst = <5>; + sprd,channel = <4>; + sprd,ringnr = <9>; + sprd,size-rxbuf = <0x1000>; /* 4*1024 */ + sprd,size-txbuf = <0x1000>; /* 4*1024 */ + }; + + slog_lte { + compatible = "sprd,spipe"; + sprd,name = "slog_lte"; + sprd,dst = <5>; + sprd,channel = <5>; + sprd,ringnr = <1>; + sprd,size-rxbuf = <0x40000>; /* 256*1024*/ + sprd,size-txbuf = <0x8000>; /* 32*1024 */ + }; + + sdiag_lte { + compatible = "sprd,spipe"; + sprd,name = "sdiag_lte"; + sprd,dst = <5>; + sprd,channel = <21>; + sprd,ringnr = <1>; + sprd,size-rxbuf = <0x40000>; /* 256*1024*/ + sprd,size-txbuf = <0x8000>; /* 32*1024 */ + }; + + stty_lte { + compatible = "sprd,spipe"; + sprd,name = "stty_lte"; + sprd,dst = <5>; + sprd,channel = <6>; + sprd,ringnr = <32>; + sprd,size-rxbuf = <0x0800>; /* 2*1024*/ + sprd,size-txbuf = <0x0800>; /* 2*1024 */ + }; + + seth0_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte0"; + sprd,dst = <5>; + sprd,channel = <7>; + sprd,blknum = <256>; + }; + + seth1_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte1"; + sprd,dst = <5>; + sprd,channel = <8>; + sprd,blknum = <256>; + }; + + seth2_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte2"; + sprd,dst = <5>; + sprd,channel = <9>; + sprd,blknum = <256>; + }; + + seth3_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte3"; + sprd,dst = <5>; + sprd,channel = <18>; + sprd,blknum = <256>; + }; + + seth4_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte4"; + sprd,dst = <5>; + sprd,channel = <19>; + sprd,blknum = <256>; + }; + + seth5_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte5"; + sprd,dst = <5>; + sprd,channel = <20>; + sprd,blknum = <256>; + }; + scproc_arm7: scproc@0x50800000 { + compatible = "sprd,scproc"; + sprd,name = "cppmic"; + sprd,ctrl-reg = <0x114 0xff 0xb0 0xff>; /* <shut_down deep_sleep reset get_status> */ + sprd,ctrl-mask = <0x01 0xfffffffe 0x100 0xf0000>; /* masks <> */ + sprd,iram-data = <0xe59f0000 0xe12fff10 0x0>; /* 3rd param equals modem_addr*/ + reg = <0 0x50800000 0 0x8000>, /* <CP_start_addr total_size> = <+128M 26M> */ + <0 0x50800000 0 0x0>, /* <iram1_base size> */ + <0 0x402e0000 0 0x400>, /* <aon_apb_base size> */ + <0 0x402b0000 0 0x100>, /* <pmu_base size> */ + <0 0x402b0000 0 0x100>, /* <pmu_base size> */ + <0 0x402b0000 0 0x100>; /* <pmu_base size> */ + #address-cells = <1>; + #size-cells = <1>; + /* segnr=1 */ + ranges = <0x0 0 0x50800000 0x8000>; + modem@0x0 { + cproc,name = "modem"; + reg = <0x0 0x8000>; /* <modem_addr size> */ + }; + }; + + scproc_cp1: scproc@0x89600000 { + compatible = "sprd,scproc"; + sprd,name = "cptl"; + sprd,ctrl-reg = <0x0c 0xff 0xb0 0x78>; /* <shut_down deep_sleep reset get_status> */ + sprd,ctrl-mask = <0x00300000 0x10000000 0x02 0x1>; /* masks <> */ + sprd,iram-data = <0xe59f0000 0xe12fff10 0x8ae00000>; /* 3rd param equals modem_addr*/ + reg = <0 0x89600000 0 0x5000000>, /* <CP_start_addr total_size> = <+128M 88M> */ + <0 0x50001000 0 0x0c>, /* <iram1_base size> */ + <0 0x402e0000 0 0x100>, /* <aon_apb_base size> */ + <0 0x402b0000 0 0x100>, /* <pmu_base size> */ + <0 0x402b0000 0 0x100>, /* <pmu_base size> */ + <0 0x402b0000 0 0x100>; /* <pmu_base size> */ + interrupts = <0 84 0x0>; /* cp1_wdg_int */ + #address-cells = <1>; + #size-cells = <1>; + /* segnr=4 */ + ranges = <0x1800000 0 0x8ae00000 0x02b00000>, + <0x0020000 0 0x89620000 0x002e0000>, + <0x0300000 0 0x89900000 0x001c0000>, + <0x4600000 0 0x8dc00000 0x00A00000>; + modem@0x1800000 { + cproc,name = "modem"; + reg = <0x1800000 0x02b00000>; /* <modem_addr size> */ + }; + dsp@0x20000 { + cproc,name = "tgdsp"; + reg = <0x20000 0x002e0000>; /* <dsp_addr size>*/ + }; + dsp@0x300000 { + cproc,name = "ldsp"; + reg = <0x300000 0x1c0000>; /* <dsp_addr size>*/ + }; + modem@0x4600000 { + cproc,name = "warm"; + reg = <0x4600000 0x00A00000>; /* <modem_addr size> */ + }; + }; + + itm_wlan{ + compatible = "sprd,itm_wlan"; + }; + + dmac: dmac@20100000 { + compatible = "sprd,sprd-dma"; + interrupts = <0 50 0x0>; + reg = <0 0x20100000 0 0x4000>; + }; + + gpu@60000000 { + compatible = "arm,mali-400", "arm,mali-utgard"; + reg = <0 0x60000000 0 0x10000>; + interrupts = <0 39 0>, <0 39 0>, <0 39 0>, <0 39 0>, <0 39 0>, <0 39 0>, <0 39 0>; + interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1", "IRQPMU"; + + clocks = <&clk_gpu_axi>,<&clk_gpu>,<&clk_153m6>,<&clk_192m>,<&clk_256m>,<&clk_307m2>,<&clk_384m>,<&clk_512m>; + clock-names = "clk_gpu_axi","clk_gpu","clk_153m6","clk_192m","clk_256m","clk_307m2","clk_384m","clk_512m"; + + freq-list-len = <6>; + freq-lists = <64000 4 4>, <102400 5 3>, <153600 2 1>, <256000 4 1>, <384000 6 1>, <512000 7 1>; + freq-default = <3>; + freq-9 = <4>; + freq-8 = <3>; + freq-7 = <2>; + freq-5 = <0>; + freq-0 = <4>; + }; + + ion { + compatible = "sprd,ion-sprd"; + #address-cells = <1>; + #size-cells = <0>; + + sprd,ion-heap@1 { + reg = <1>; /* SYSTEM */ + reg-names = "ion_heap_system"; + sprd,ion-heap-type = <0>; /* SYSTEM */ + sprd,ion-heap-mem = <0x0 0x0>; + }; + + sprd,ion-heap@2 { + reg = <2>; /* MM */ + reg-names = "ion_heap_carveout_mm"; + sprd,ion-heap-type = <0>; /* carveout mm */ + sprd,ion-heap-mem = <0x9864F000 0x7100000>; + }; + + sprd,ion-heap@3 { + reg = <3>; /* OVERLAY */ + reg-names = "ion_heap_carveout_overlay"; + sprd,ion-heap-type = <2>; /* CARVEOUT */ + sprd,ion-heap-mem = <0x9FC00000 0x400000>; /* 480*854*4*2, 1M alignment */ + }; + }; + + sprd_iommu0: sprd_iommu@20b00000 { + compatible = "sprd,sprd_iommu";//gsp + func-name = "sprd_iommu_gsp"; + reg = <0 0x10000000 0 0x2000000>, //iova + <0 0x20b00000 0 0x8000>, //pgt + <0 0x20b08000 0 0x8000>; //ctrl_reg + reg_name = "iova","pgt","ctrl_reg"; + clock-names = "clk_gsp_emc","clk_153m6","clk_gsp"; + clocks = <&clk_gsp_emc>, <&clk_153m6>,<&clk_gsp>; + status = "ok"; + }; + + sprd_iommu1: sprd_iommu@60f00000 { + compatible = "sprd,sprd_iommu";//mm + func-name = "sprd_iommu_mm"; + reg = <0 0x20000000 0 0x8000000>, //iova + <0 0x60f00000 0 0x20000>, //pgt + <0 0x60f20000 0 0x2000>; //ctrl_reg + reg_name = "iova","pgt","ctrl_reg"; + clock-names = "clk_mmu","clk_mm_i"; + clocks = <&clk_mmu>,<&clk_mm>; + status = "ok"; + }; + + sprd_vsp: sprd_vsp@60900000{ + compatible = "sprd,sprd_vsp"; + reg = <0 0x60900000 0 0xc000>; + interrupts = <0 43 0x0>; + clock-names = "clk_mm_i", "clk_vsp", "clk_parent_0", "clk_parent_1", "clk_parent_2", "clk_parent_3"; + clocks = <&clk_mm>, <&clk_vsp>, <&clk_307m2>, <&clk_256m>, <&clk_128m>, <&clk_96m>; + clock-parent-info = <2 4>; + version = <6>; + }; + + sprd_jpg { + compatible = "sprd,sprd_jpg"; + reg = <0 0x60b00000 0 0x8000>; + interrupts = <0 42 0x0>; + clock-names = "clk_mm_i","clk_jpg"; + clocks = <&clk_mm>, <&clk_jpg>; + version = <6>; + }; + sprd_bm { + compatible = "sprd,sprd_bm"; + reg = <0 0x30040000 0 0xA0000 + 0 0x20F00000 0 0x300000>; + interrupts = <0 86 0x0>; + sprd,bm_status = <1>; + sprd,bm_count = <10 11>; + sprd,cpu_chn = <0>; + sprd,disp_chn = <1>; + sprd,gpu_chn = <2>; + sprd,ap_zip_chn = <3>; + sprd,mm_chn = <4>; + sprd,cp0_arm1_chn = <5>; + sprd,cp0_dsp_chn = <6>; + sprd,cp1_lte_chn = <7>; + sprd,cp1_dsp_chn = <8>; + sprd,cp1_arm_chn = <9>; + sprd,ap_dap_chn = <0 0>; + sprd,ap_cpu_chn = <0 1>; + sprd,ap_dma_w_chn = <0 2>; + sprd,ap_dma_r_chn = <0 3>; + sprd,ap_sdio_0_chn = <1 0>; + sprd,ap_sdio_1_chn = <1 1>; + sprd,ap_sdio_2_chn = <1 2>; + sprd,ap_emmc_chn = <1 3>; + sprd,ap_nandc_chn = <2 0>; + sprd,ap_otg_chn = <2 1>; + sprd,ap_hsic_chn = <2 2>; + }; + wdt@40290000 { + compatible = "sprd,sprd-wdt"; + reg = <0 0x40290000 0 0x1000>, + <0 0x40310000 0 0x1000>; + interrupts = <0 124 0x0>; + }; + + sprd-marlin { + compatible = "sprd,marlin"; + gpios = <&d_gpio_gpio 97 0 /*marlin gpio0 */ + &d_gpio_gpio 132 0 /*marlin gpio1 */ + &d_gpio_gpio 133 0 /*marlin gpio2 */ + &d_gpio_gpio 131 0 /*marlin gpio3 */ + &d_gpio_gpio 122 0>; /*marlin reset*/ + cp-rfctl-offset = <0x27c>; /*coex func. marlin gpio3*/ + vdd-download = "vddcon"; /*vdd 1.6v*/ + vdd-pa = "vddwifipa"; /*vdd 3.3v*/ + clk-name = "clk_aux0"; /*clk 32k*/ + sdhci-name = "sdio_wifi"; + }; +}; + +&vbc_r2p0 { + status = "okay"; +}; + +&sprd_codec { + status = "okay"; + sprd,audio_power_ver = <4>; +}; + +&i2s0 { + sprd,config_type = "pcm"; + sprd,slave_timeout = <0xF11>; + sprd,_hw_port = <0>; + sprd,fs = <8000>; + sprd,bus_type = <1>; + sprd,rtx_mode = <3>; + sprd,byte_per_chan = <1>; + sprd,slave_mode = <0>; + sprd,lsb = <0>; + sprd,lrck = <0>; + sprd,low_for_left = <1>; + sprd,clk_inv = <0>; + sprd,pcm_short_frame = <1>; + sprd,pcm_slot = <0x1>; + sprd,pcm_cycle = <1>; + sprd,tx_watermark = <12>; + sprd,rx_watermark = <20>; + status = "okay"; +}; + +&i2s1 { + status = "okay"; +}; + +&i2s2 { + status = "okay"; +}; + +&i2s3 { + status = "okay"; +}; + +&i2s_sound { + sprd,i2s = <&i2s0>, <&i2s1>, <&i2s2>, <&i2s3>; +}; + +&sprd_battery { + gpios = <&a_eic_gpio 0 0 /* chg int */ + &a_eic_gpio 4 0 /* cv state */ + &a_eic_gpio 6 0 /* chg ovi */ + &a_eic_gpio 9 0>; /* battery detect */ + + fgu-mode = <0>; + alm-soc = <5>; + alm-vol = <3500>; + soft-vbat-uvlo = <3100>; + rint = <250>; + cnom = <1900>; + rsense-real = <230>; + rsense-spec = <200>; + relax-current = <50>; + fgu-cal-ajust = <0>; + ocv-tab-size = <21>; + ocv-tab-vol = <4168 4113 4076 4016 3973 3953 3924 3894 3851 3821 3802 3789 3780 3777 3771 3758 3738 3703 3684 3609 3400>; + ocv-tab-cap = <100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0>; +}; diff --git a/arch/arm64/boot/dts/sprd_sp9836aea_fpga.dts b/arch/arm64/boot/dts/sprd_sp9836aea_fpga.dts new file mode 100644 index 00000000..be7a6029 --- /dev/null +++ b/arch/arm64/boot/dts/sprd_sp9836aea_fpga.dts @@ -0,0 +1,675 @@ +/* + * SPREADTRUM Ltd. + * + * TSharkL DTS + */ + +/dts-v1/; + +/memreserve/ 0x80000000 0x00010000; +/memreserve/ 0x8a800000 0x600000; + +/* memory reserved for ION(carveout mm)*/ +/memreserve/ 0x98800000 0x7100000; + +/* memory reserved for ION(overlay)*/ +/memreserve/ 0x9f900000 0x700000; /* 7MK */ + +/include/ "sc2723-regulators.dtsi" +/include/ "sprd-battery.dtsi" +/* **** FPGA needn't clk **** *\ +include "scx35l64-clocks.dtsi" +\* ************************** */ + +/ { + model = "scx35l64"; + compatible = "sprd,TsharkL"; + sprd,sc-id = <8830 1 0x20000>; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { + bootargs = "earlyprintk=sprd_uart,0x70000000"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x8000fff8>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0 0x80000000 0 0x20000000>; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + lcd0 = &fb0; + hwspinlock0 = &hwspinlock0; + hwspinlock1 = &hwspinlock1; + }; + + gic: interrupt-controller@12001000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0x12001000 0 0x1000>, + <0 0x12002000 0 0x1000>; + }; + + intc:interrupt-controller@71400000 { + compatible = "sprd,intc"; + #interrupt-cells = <0>; + interrupt-controller; + reg = <0 0x71400000 0 0x1000>, + <0 0x71500000 0 0x1000>, + <0 0x71600000 0 0x1000>, + <0 0x71700000 0 0x1000>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, + <1 14 0xff01>, + <1 11 0xff01>, + <1 10 0xff01>; + clock-frequency = <26000000>; + }; + + sprd_timer { + compatible = "sprd,sharkl64-timer"; + reg = <0 0x40050000 0 0x20>; /*aon GPTIMER0 */ + interrupts = <0 28 0x0>; + clock-frequency = <32768>; + }; + + sprd_ap_system_timer { + reg = <0 0x40230000 0 0x20>; + interrupts = <0 31 0x0>; + }; + + uart0: uart@70000000 { + compatible = "sprd,serial"; + reg = <0 0x70000000 0 0x100>; + interrupts = <0 2 0xf04>; + }; + + uart1: uart@70100000 { + compatible = "sprd,serial"; + reg = <0 0x70100000 0 0x100>; + interrupts = <0 3 0xf04>; + }; + sprd_backlight { + compatible = "sprd,sprd_backlight"; + start = <3>; + end = <3>; + flags = <0x100>; + }; + sprd_pwm_bl { + compatible = "sprd,sprd_pwm_bl"; + reg =<0 0x40260000 0 0xf>; + }; + hwspinlock0: hwspinlock0@20c00000{ + compatible = "sprd,sprd-hwspinlock"; + reg = <0 0x20c00000 0 0x1000>; + }; + hwspinlock1: hwspinlock1@40060000{ + compatible = "sprd,sprd-hwspinlock"; + reg = <0 0x40060000 0 0x1000>; + status = "ok"; + }; + watchdog { + compatible = "sprd,watchdog"; + reg = <0 0X40290000 0 0x1000>; + }; + + d_eic_gpio: gpio@40210000 { + compatible = "sprd,d-eic-gpio"; + reg = <0 0x40210000 0 0x1000>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-cells = <2>; + gpiobase = <288>; + ngpios = <16>; + interrupts = <0 37 0x0>; + }; + + d_gpio_gpio: gpio@40280000 { + compatible = "sprd,d-gpio-gpio"; + reg = <0 0x40280000 0 0x1000>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-cells = <2>; + gpiobase = <0>; + ngpios = <256>; + interrupts = <0 35 0x0>; + }; + + sdhci3: sdhci@20600000 { + compatible = "sprd,sdhci-shark"; + interrupts = <0 60 0x0>; + reg = <0 0x20600000 0 0x1000>; + id = <3>; + bus-width = <8>; + max-frequency = <384000000>; + keep-power-in-suspend = <1>; + non-removable = <1>; + caps = <0x80000000>; + caps2 = <0x202>; + quirks = <0x21009001>; //SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | SDHCI_QUIRK_BROKEN_CARD_DETECTION | SDHCI_QUIRK_CLOCK_BEFORE_RESET + quirks2 = <0x8>; //SDHCI_QUIRK2_PRESET_VALUE_BROKEN + host-caps-mask = <0x03000000>; + // vdd-vmmc = "vddemmccore"; + // vdd-vqmmc = "vddemmcio"; + vdd-vmmc = "vddemmccore"; + vdd-vqmmc = "vddgen1"; + clock-names = "clk_emmc"; + clocks = <&clk_emmc>, <&clk_384m>; + enb-bit = <0x800>; + rst-bit = <0x4000>; + write-delay = <0x04>; + read-pos-delay = <0x04>; + read-neg-delay = <0x04>; + keep-power = <0>; + runtime = <1>; + }; + + sdhci0: sdhci@20300000 { + compatible = "sprd,sdhci-shark"; + interrupts = <0 57 0x0>; + reg = <0 0x20300000 0 0x1000>; + id = <0>; + bus-width = <4>; + max-frequency = <384000000>; + keep-power-in-suspend = <1>; + caps = <0x80000000>; + caps2 = <0x202>; + quirks = <0x21009001>; //SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | SDHCI_QUIRK_BROKEN_CARD_DETECTION | SDHCI_QUIRK_CLOCK_BEFORE_RESET + quirks2 = <0x8>; //SDHCI_QUIRK2_PRESET_VALUE_BROKEN + host-caps-mask = <0x05000000>; + vdd-vmmc = "vddsdcore"; + vdd-vqmmc = "vddsdio"; + vqmmc-voltage-level = <3000000>; + cd-gpios = <71>; + clock-names = "clk_sdio0"; + clocks = <&clk_sdio0>, <&clk_384m>; + enb-bit = <0x100>; + rst-bit = <0x800>; + keep-power = <0>; + runtime = <1>; + }; + sdhci1: sdhci@20400000 { + compatible = "sprd,sdhci-shark"; + interrupts = <0 58 0x0>; + reg = <0 0x20400000 0 0x1000>; + id = <1>; + bus-width = <4>; + max-frequency = <96000000>; + keep-power-in-suspend = <1>; + cap-power-off-card = <1>; + caps = <0x80000000>; + quirks = <0x21009001>; //SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | SDHCI_QUIRK_BROKEN_CARD_DETECTION | SDHCI_QUIRK_CLOCK_BEFORE_RESET + quirks2 = <0x8>; //SDHCI_QUIRK2_PRESET_VALUE_BROKEN + clock-names = "clk_sdio1"; + clocks = <&clk_sdio1>, <&clk_96m>; + enb-bit = <0x200>; + rst-bit = <0x1000>; + keep-power = <0>; + runtime = <1>; + }; + + + adi: adi_bus { + compatible = "sprd,adi-bus"; + interrupts = <0 38 0x0>; + reg = <0 0x40038000 0 0x1000>; + interrupt-controller; + sprd,irqnums = <11>; + #interrupt-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x100 0 0x40038100 0x80>; + + keyboard_backlight { + compatible = "sprd,keyboard-backlight"; + }; + a_eic_gpio: gpio@100{ + compatible = "sprd,a-eic-gpio"; + reg = <0x100 0x80>; /* adi reg */ + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-cells = <2>; + gpiobase = <304>; + ngpios = <16>; + interrupt-parent = <&adi>; + interrupts = <5 0x0>; /* ext irq 5 */ + }; + sprd_eic_keys { + compatible = "sprd,sprd-eic-keys"; + key_power { + label = "Power Key"; + linux,code = <116>; + gpios = <&a_eic_gpio 2 0>; + debounce-interval = <2>; + gpio-key,wakeup; + }; + }; + }; + gpio_keys { + compatible = "gpio-keys"; + input-name = "sprd-gpio-keys"; + key_volumedown { + label = "Volumedown Key"; + linux,code = <114>; + gpios = <&d_gpio_gpio 124 1>; + debounce-interval = <2>; + gpio-key,wakeup; + }; + key_volumeup { + label = "Volumeup Key"; + linux,code = <115>; + gpios = <&d_gpio_gpio 125 1>; + debounce-interval = <2>; + gpio-key,wakeup; + }; + }; + + usb: usb@20200000{ + compatible = "sprd,usb"; + interrupts = <0 55 0x0>; + ngpios = <1>; + gpios = <&a_eic_gpio 0 0>; + reg = <0 0x20200000 0 0x1000>; + tune_value = <0x44073e33>; + usb-supply = <&vddusb>; + #address-cells = <1>; + #size-cells = <0>; + }; + sprd_thermal: sprd_thermal@402F0000{ + compatible = "sprd,sprd-thermal"; + id = <0>; + interrupts = <0 26 0x0>; + reg = <0 0x402F0000 0 0x1000>; + trip_points_active = <105>; + trip_points_critical = <114>; + trip_num = <5>; + }; + i2c0: i2c@70500000{ + compatible = "sprd,i2c"; + interrupts = <0 11 0x0>; + reg = <0 0x70500000 0 0x1000>; + #clock-names = "clk_i2c0"; + #address-cells = <1>; + #size-cells = <0>; + sensor_main@0x3c { + compatible = "sprd,sensor_main"; + reg = <0x3c>; + }; + sensor_sub@0x21 { + compatible = "sprd,sensor_sub"; + reg = <0x21>; + }; + }; + sprd-io-base { + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 1 0>; + ahb { + compatible = "sprd,ahb"; + reg = <0 0x20e00000 0 0x40000>; + }; + apbckg { + compatible = "sprd,apbckg"; + reg = <0 0x21500000 0 0x1000>; + }; + hwlock0 { + compatible = "sprd,hwlock0"; + reg = <0 0x20d00000 0 0x1000>; + }; + pub_apb { + compatible = "sprd,pub_apb"; + reg = <0 0x30020000 0 0x10000>; + }; + aon_apb { + compatible = "sprd,aon_apb"; + reg = <0 0x402e0000 0 0x40000>; + }; + pmu_apb { + compatible = "sprd,pmu_apb"; + reg = <0 0x402b0000 0 0x40000>; + }; + mm_ahb { + compatible = "sprd,mm_ahb"; + reg = <0 0x60d00000 0 0x10000>; + }; + mm_clk { + compatible = "sprd,mm_clk"; + reg = <0 0x60e00000 0 0x1000>; + }; + ap_ckg { + compatible = "sprd,ap_ckg"; + reg = <0 0x71200000 0 0x40000>; + }; + ap_apb { + compatible = "sprd,ap_apb"; + reg = <0 0x71300000 0 0x40000>; + }; + gpu_apb { + compatible = "sprd,gpu_apb"; + reg = <0 0x60100000 0 0x1000>; + }; + adi { + compatible = "sprd,adi"; + reg = <0 0x40030000 0 0x10000>; + }; + adi_slave { + compatible = "sprd,adi_slave"; + reg = <0 0x40038000 0 0x1000>; + }; + adc { + compatible = "sprd,adc"; + reg = <0 0x40038300 0 0x1000>; + }; + dma { + compatible = "sprd,dma"; + reg = <0 0x20100000 0 0x4000>; + interrupts = <0 50 0x0>; + }; + mailbox { + compatible = "sprd,mailbox"; + reg = <0 0x400a0000 0 0x10000>; + }; + rtc { + compatible = "sprd,rtc"; + reg = <0 0x40038080 0 0x80>; + interrupts = <0 2 0x0>; + }; + axibm0 { + compatible = "sprd,axibm0"; + reg = <0 0x30040000 0 0x20000>; + interrupts = <0 86 0x0>; + }; + i2c0: i2c@70500000{ + compatible = "sprd,i2c"; + interrupts = <0 11 0x0>; + reg = <0 0x70500000 0 0x1000>; + //address-cells = <1>; + //size-cells = <0>; + //clock-names = "clk_i2c0"; + sensor_main@0x3c { + compatible = "sprd,sensor_main"; + reg = <0x3c>; + }; + sensor_sub@0x21 { + compatible = "sprd,sensor_sub"; + reg = <0x21>; + }; + }; + i2c1: i2c@70600000{ + compatible = "sprd,i2c"; + interrupts = <0 12 0x0>; + reg = <0 0x70600000 0 0x1000>; + //clock-names = "clk_i2c1"; + }; + i2c2: i2c@70700000{ + compatible = "sprd,i2c"; + interrupts = <0 13 0x0>; + reg = <0 0x70700000 0 0x1000>; + //clock-names = "clk_i2c2"; + }; + i2c3: i2c@70800000{ + compatible = "sprd,i2c"; + interrupts = <0 14 0x0>; + reg = <0 0x70800000 0 0x1000>; + //clock-names = "clk_i2c3"; + }; + i2c4: i2c@70900000{ + compatible = "sprd,i2c"; + interrupts = <0 15 0x0>; + reg = <0 0x70900000 0 0x1000>; + //clock-names = "clk_i2c4"; + }; + + spi0: spi0@70a00000{ + compatible = "sprd,sprd-spi"; + interrupts = <0 7 0x0>; + reg = <0 0x70a00000 0 0x1000>; + //clock-names = "clk_spi0"; + }; + spi1: spi1@70b00000{ + compatible = "sprd,sprd-spi"; + interrupts = <0 8 0x0>; + reg = <0 0x70b00000 0 0x1000>; + //clock-names = "clk_spi1"; + }; + spi2: spi2@70c00000{ + compatible = "sprd,sprd-spi"; + interrupts = <0 9 0x0>; + reg = <0 0x70c00000 0 0x1000>; + //clock-names = "clk_spi2"; + }; + d_eic_gpio { + compatible = "sprd,d-eic-gpio"; + reg = <0 0x40210000 0 0x1000>; + }; + d_gpio_gpio { + compatible = "sprd,d-gpio-gpio"; + reg = <0 0x40280000 0 0x1000>; + }; + aon_dma { + compatible = "sprd,aon_dma"; + reg = <0 0x40100000 0 0x1000>; + interrupts = <0 50 0x0>; + }; + pwm { + compatible = "sprd,pwm"; + reg = <0 0x40260000 0 0x1000>; + }; + }; + + sprd_dcam { + compatible = "sprd,sprd_dcam"; + reg = <0 0x60800000 0 0x100000>; + interrupts = <0 45 0>; + }; + sprd_scale { + compatible = "sprd,sprd_scale"; + }; + sprd_rotation { + compatible = "sprd,sprd_rotation"; + }; + sprd_sensor { + compatible = "sprd,sprd_sensor"; + reg = <0 0x60c00000 0 0x100000>; + gpios = <&d_gpio_gpio 45 0 /*main reset*/ + &d_gpio_gpio 47 0 /*main powerdown*/ + &d_gpio_gpio 44 0 /*sub reset*/ + &d_gpio_gpio 46 0>; /*sub powerdown*/ + }; + sprd_isp { + compatible = "sprd,sprd_isp"; + reg = <0 0x60a00000 0 0x100000>; + }; + sprd_dma_copy { + compatible = "sprd,sprd_dma_copy"; + }; + + fb0: fb@20800000 { + compatible = "sprd,sprdfb"; + reg = <0 0x20800000 0 0x1000>, + <0 0x21800000 0 0x1000>; + interrupts = <0 46 0x0>, + <0 48 0x0>, + <0 49 0x0>; +/* + clock-names = "dispc_clk_parent", "dispc_dbi_clk_parent", "dispc_dpi_clk_parent", "dispc_emc_clk_parent", "dispc_clk", "dispc_dbi_clk", "dispc_dpi_clk", "dispc_emc_clk", "fb_spi_clock", "fb_spi_clock_parent"; + //clocks = <&clk_256m>, <&clk_256m>, <&clk_384m>, <&clk_aon_apb>, <&clk_dispc0>, <&clk_dispc0_dbi>, <&clk_dispc0_dpi>, <&clk_disp_emc>, <&clk_spi2>, <&ext_26m>; + clock-src = <256000000 256000000 384000000>; + dpi_clk_div = <7>; +*/ + sprd,fb_use_reservemem; + sprd,fb_mem = <0x8a800000 0x600000>; + + }; + + gsp@20a00000 { + compatible = "sprd,gsp"; + reg = <0 0x20a00000 0 0x1000>; + interrupts = <0 51 0x0>; +/* + clock-names = "clk_gsp", "clk_gsp_emc", "clk_gsp_parent", "clk_aon_apb"; + clocks = <&clk_gsp>, <&clk_gsp_emc>, <&clk_256m>, <&clk_aon_apb>; +*/ + gsp_mmu_ctrl_base = <0x20b08000>; + }; + + + gpu { + compatible = "sprd,mali-utgard"; + mali_pp_core_number = <4>; + interrupt-names = "mali_gp_irq", + "mali_gp_mmu_irq", + "mali_pp0_irq", + "mali_pp0_mmu_irq", + "mali_pp1_irq", + "mali_pp1_mmu_irq"; + reg-names = "mali_l2", + "mali_gp", + "mali_gp_mmu", + "mali_pp0", + "mali_pp0_mmu", + "mali_pp1", + "mali_pp1_mmu", + "mali_pmu"; + interrupts = <0 39 0x0>, // MALI_GP_IRQ, + <0 39 0x0>, // MALI_GP_MMU_IRQ, + <0 39 0x0>, // MALI_PP0_IRQ, + <0 39 0x0>, // MALI_PP0_MMU_IRQ, + <0 39 0x0>, // MALI_PP1_IRQ, + <0 39 0x0>; // MALI_PP1_MMU_IRQ, + reg = <0 0x60001000 0 0x200>,// MALI_L2,MALI_GPU_RESOURCE_L2(base_addr + 0x1000) + <0 0x60000000 0 0x100>,// MALI_GP, + <0 0x60003000 0 0x100>,// MALI_GP_MMU, + <0 0x60008000 0 0x1100>,// MALI_PP0, + <0 0x60004000 0 0x100>,// MALI_PP0_MMU, + <0 0x6000A000 0 0x1100>,// MALI_PP1, + <0 0x60005000 0 0x100>;// MALI_PP1_MMU, + /* <0x60002000 0x100>; //MALI_PMU, + clock-names = "clk_gpu_axi","clk_gpu","clk_153m6","clk_208m","clk_256m","clk_312m","clk_384m","clk_460m8"; + clocks = <&clk_gpu_axi>,<&clk_gpu>,<&clk_153m6>,<&clk_208m>,<&clk_256m>,<&clk_312m>,<&clk_384m>,<&clk_460m8>; +*/ + }; + + ion { + compatible = "sprd,ion-sprd"; + #address-cells = <1>; + #size-cells = <0>; + + sprd,ion-heap@1 { + reg = <1>; /* SYSTEM */ + reg-names = "ion_heap_system"; + sprd,ion-heap-type = <0>; /* SYSTEM */ + sprd,ion-heap-mem = <0x0 0x0>; + }; + + sprd,ion-heap@2 { + reg = <2>; /* MM */ + reg-names = "ion_heap_carveout_mm"; + sprd,ion-heap-type = <2>; /* carveout mm */ + sprd,ion-heap-mem = <0x98800000 0x7100000>; + }; + + sprd,ion-heap@3 { + reg = <3>; /* OVERLAY */ + reg-names = "ion_heap_carveout_overlay"; + sprd,ion-heap-type = <2>; /* CARVEOUT */ + sprd,ion-heap-mem = <0x9f900000 0x700000>; /* 7M */ + }; + }; + + sprd_iommu0: sprd_iommu@20b00000 { + compatible = "sprd,sprd_iommu";//gsp + func-name = "sprd_iommu_gsp"; + reg = <0 0x10000000 0 0x2000000>, //iova + <0 0x20b00000 0 0x8000>, //pgt + <0 0x20b08000 0 0x8000>; //ctrl_reg + reg_name = "iova","pgt","ctrl_reg"; + clock-names = "clk_gsp_emc","clk_153m6","clk_gsp"; + //clocks = <&clk_gsp_emc>, <&clk_153m6>,<&clk_gsp>; + status = "ok"; + }; + + sprd_iommu1: sprd_iommu@60f00000 { + compatible = "sprd,sprd_iommu";//mm + func-name = "sprd_iommu_mm"; + reg = <0 0x20000000 0 0x8000000>, //iova + <0 0x60f00000 0 0x20000>, //pgt + <0 0x60f20000 0 0x2000>; //ctrl_reg + reg_name = "iova","pgt","ctrl_reg"; + clock-names = "clk_mmu","clk_mm_i"; + //clocks = <&clk_mmu>,<&clk_mm>; + status = "ok"; + + }; + + sprd_vsp: sprd_vsp@60900000{ + compatible = "sprd,sprd_vsp"; + reg = <0 0x60900000 0 0xc000>; + interrupts = <0 43 0x0>; + clock-names = "clk_mm_i", "clk_vsp", "clk_parent_0", "clk_parent_1", "clk_parent_2", "clk_parent_3"; + //clocks = <&clk_mm>, <&clk_vsp>, <&clk_307m2>, <&clk_256m>, <&clk_128m>, <&clk_96m>; + clock-parent-info = <2 4>; + version = <6>; + }; + sprd_jpg { + compatible = "sprd,sprd_jpg"; + reg = <0 0x60B00000 0 0x8000>; + interrupts = <0 42 0x0>; + //clock-names = "clk_mm_i","clk_jpg"; + //clocks = <&clk_mm>, <&clk_jpg>; + }; + +}; diff --git a/arch/arm64/boot/dts/sprd_sp9838aea_5mod.dts b/arch/arm64/boot/dts/sprd_sp9838aea_5mod.dts new file mode 100644 index 00000000..ea18cbdd --- /dev/null +++ b/arch/arm64/boot/dts/sprd_sp9838aea_5mod.dts @@ -0,0 +1,1592 @@ +/* + * SPREADTRUM Ltd.clock-cells +sprd_rotation + * + * SharkLT8 5mod refphone DTS + */ + +/dts-v1/; + +/* memory reserved for SMEM */ +/memreserve/ 0x87800000 0x5B0000; /* Offset:120M, Size:5M+256K */ + +/* memory reserved for WARM modem */ +/memreserve/ 0x8DC00000 0xD00000; /* Offset:220M, Size:13M*/ + +/* memory reserved for LTE modem */ +/memreserve/ 0x89600000 0x4600000; /* Offset:150M, Size:70M*/ + +/* memory reserved for fb */ +/memreserve/ 0x9ED74000 0xA8C000; /* 1280*720*4*3, 4K alignment*/ + +/* memory reserved for ION */ +/memreserve/ 0x9F800000 0x800000; /* 1280*720*4*2, 1M alignment*/ + +/* memory reserved for smp */ +/memreserve/ 0x9F700000 0x1000; /* size 4K*/ + +/include/ "sc2723-regulators.dtsi" +/include/ "sprd-sound.dtsi" +/include/ "sprd-battery.dtsi" +/include/ "scx35lt8-clocks.dtsi" + +/ { + model = "scx35l64"; + compatible = "sprd,SharkLT8"; + sprd,sc-id = <8830 1 0x20000>; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { + bootargs = "earlyprintk=sprd_uart,0x70100000 loglevel=1 console=ttyS1,115200n8"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + core1 { + cpu = <&CPU5>; + }; + core2 { + cpu = <&CPU6>; + }; + core3 { + cpu = <&CPU7>; + }; + }; + }; + + CPU0: cpu@530000 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530000>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD &CLUSTER_PD &TOP_PD>; + clocks = <&clk_little_mcu>; + cpu0-supply = <&vddarm>; + operating-points = < + /* kHz uV */ + 1000000 900000 + 800000 900000 + 750000 900000 + 600000 900000 + 533000 900000 + 400000 900000 + 200000 900000 + >; + }; + + CPU1: cpu@530001 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530001>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD &CLUSTER_PD &TOP_PD>; + }; + + CPU2: cpu@530002 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530002>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD &CLUSTER_PD &TOP_PD>; + }; + + CPU3: cpu@530003 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530003>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD &CLUSTER_PD &TOP_PD>; + }; + + CPU4: cpu@530100 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530100>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD &CLUSTER_PD &TOP_PD>; + clocks = <&clk_big_mcu>; + cpu0-supply = <&vddbigarm>; + operating-points = < + /* kHz uV */ + 1500000 1050000 + 1420000 1050000 + 1350000 1050000 + 1200000 900000 + 1100000 900000 + 1000000 900000 + 960000 900000 + >; + }; + + CPU5: cpu@530101 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530101>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD &CLUSTER_PD &TOP_PD>; + }; + + CPU6: cpu@530102 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530102>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD &CLUSTER_PD &TOP_PD>; + }; + + CPU7: cpu@530103 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530103>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD &CLUSTER_PD &TOP_PD>; + }; + + idle-states{ + entry-method = "arm,psci"; + LIGHT_SLEEP: light_sleep { + compatible = "arm,idle-state"; + exit-latency-us = <10>; + min-residency-us = <50>; + entry-method-param = <0x00000001>; + }; + CORE_PD: core_pd { + compatible = "arm,idle-state"; + exit-latency-us = <1070>; + min-residency-us = <5000>; + entry-method-param = <0x00010002>; + }; + CLUSTER_PD: cluster_pd { + compatible = "arm,idle-state"; + exit-latency-us = <2000>; + min-residency-us = <8000>; + entry-method-param = <0x01010003>; + }; + TOP_PD: top_pd { + compatible = "arm,idle-state"; + exit-latency-us = <2300>; + min-residency-us = <10000>; + entry-method-param = <0x01010004>; + }; + DEEP_SLEEP: deep_sleep { + compatible = "arm,idle-state"; + exit-latency-us = <4100>; + min-residency-us = <6500>; + entry-method-param = <0x01010005>; + }; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0 0x80000000 0 0x40000000>; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + lcd0 = &fb0; + hwspinlock0 = &hwspinlock0; + hwspinlock1 = &hwspinlock1; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 92 4>, + <0 93 4>, + <0 94 4>, + <0 95 4>; + }; + + psci { + compatible = "arm,psci"; + method = "smc"; + cpu_on = <0xc4000003>; + cpu_off = <0x84000002>; + cpu_suspend = <0xc4000001>; + }; + + gic: interrupt-controller@12001000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0x12001000 0 0x1000>, + <0 0x12002000 0 0x1000>; + }; + + intc:interrupt-controller@71400000 { + compatible = "sprd,intc"; + #interrupt-cells = <0>; + interrupt-controller; + reg = <0 0x71400000 0 0x1000>, + <0 0x71500000 0 0x1000>, + <0 0x71600000 0 0x1000>, + <0 0x71700000 0 0x1000>, + <0 0x40200000 0 0x1000>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, + <1 14 0xff01>, + <1 11 0xff01>, + <1 10 0xff01>; + clock-frequency = <26000000>; + }; + + sprd_timer { + compatible = "sprd,sharkl64-timer"; + reg = <0 0x40050000 0 0x20>; /*aon GPTIMER0 */ + interrupts = <0 28 0x0>; + clock-frequency = <32768>; + }; + + sprd_ap_system_timer { + reg = <0 0x40230000 0 0x20>; + interrupts = <0 31 0x0>; + }; + + clock: clockdevice { + compatible = "sprd,scx35l64-clocks"; + #clock-cells = <1>; + }; + + d_eic_gpio: gpio@40210000 { + compatible = "sprd,d-eic-gpio"; + reg = <0 0x40210000 0 0x1000>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-cells = <2>; + gpiobase = <288>; + ngpios = <16>; + interrupts = <0 37 0x0>; + }; + + d_gpio_gpio: gpio@40280000 { + compatible = "sprd,d-gpio-gpio"; + reg = <0 0x40280000 0 0x1000>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-cells = <2>; + gpiobase = <0>; + ngpios = <256>; + interrupts = <0 35 0x0>; + }; + + uart0: uart@70000000 { + compatible = "sprd,serial"; + interrupts = <0 2 0xf04>; + reg = <0 0x70000000 0 0x1000>; + clock-names = "clk_uart0"; + clocks = <&clock 60>; + sprdclk = <48000000>; + sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP"; + + }; + + uart1: uart@70100000 { + compatible = "sprd,serial"; + interrupts = <0 3 0xf04>; + reg = <0 0x70100000 0 0x1000>; + clock-names = "clk_uart1"; + clocks = <&clock 61>; + sprdclk = <26000000>; + sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP"; + + }; + + uart2: uart@70200000 { + compatible = "sprd,serial"; + interrupts = <0 4 0xf04>; + reg = <0 0x70200000 0 0x1000>; + clock-names = "clk_uart2"; + clocks = <&clock 62>; + sprdclk = <26000000>; + sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP"; + }; + + uart3: uart@70300000 { + compatible = "sprd,serial"; + interrupts = <0 5 0xf04>; + reg = <0 0x70300000 0 0x1000>; + clock-names = "clk_uart3"; + clocks = <&clock 63>; + sprdclk = <26000000>; + sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP"; + }; + + hwspinlock0: hwspinlock0@20c00000{ + compatible = "sprd,sprd-hwspinlock"; + reg = <0 0x20c00000 0 0x1000>; + }; + + hwspinlock1: hwspinlock1@40060000{ + compatible = "sprd,sprd-hwspinlock"; + reg = <0 0x40060000 0 0x1000>; + status = "ok"; + }; + + watchdog { + compatible = "sprd,watchdog"; + reg = <0 0X40290000 0 0x1000>; + }; + + pinctrl { + compatible = "sprd,pinctrl"; + reg = <0 0x402a0000 0 0x1000>; + pwr_domain = "vdd28", + "vdd18", + "vddsim0", + "vddsim1", + "vddsim2", + "vddsdio", + "vdd18"; + ctrl_desc = <0x10 0 1 + 0x10 1 1 + 0x10 2 1 + 0x10 3 1 + 0x10 4 1 + 0x10 5 1 + 0x10 6 1>; + }; + + sdios{ + #address-cells = <2>; + #size-cells = <2>; + ranges; + sdio3: sdio@20600000{ + compatible = "sprd,sdhost-3.0"; + reg = <0 0x20600000 0 0x1000>; + interrupts = <0 60 0x0>; + sprd,name = "sdio_emmc"; + /*detect_gpio = <-1>; */ + SD_Pwr_Name = "vddemmccore"; + _1_8V_signal_Name = "vddgen0"; + signal_default_Voltage = <1800000>; + ocr_avail = <0x00040000>; + clocks = <&clk_emmc>, <&clk_192m>; + base_clk = <192000000>; + caps = <0xC00F8D47>; + caps2 = <0x202>; + pm_caps = <0x4>; + writeDelay = <0x3E>; + readPosDelay = <0xA>; + readNegDelay = <0xA>; + }; + + sdio0: sdio@20300000{ + compatible = "sprd,sdhost-3.0"; + reg = <0 0x20300000 0 0x1000>; + interrupts = <0 57 0x0>; + sprd,name = "sdio_sd"; + detect_gpio = <141>; + SD_Pwr_Name = "vddsdcore"; + _1_8V_signal_Name = "vddsdio"; + signal_default_Voltage = <3000000>; + ocr_avail = <0x00040000>; + clocks = <&clk_sdio0>, <&clk_192m>; + base_clk = <192000000>; + caps = <0xC0020407>; + caps2 = <0x200>; + pm_caps = <0x4>; + writeDelay = <0x3>; + readPosDelay = <0x3>; + readNegDelay = <0x3>; + }; + + + sdio1: sdio@20400000{ + compatible = "sprd,sdhost-3.0"; + reg = <0 0x20400000 0 0x1000>; + interrupts = <0 58 0x0>; + sprd,name = "sdio_wifi"; + /* detect_gpio = <-1>; */ + /* SD_Pwr_Name = "vddsdcore"; */ + /* _1_8V_signal_Name = "vddsdio";*/ + /* signal_default_Voltage = <3000000>; */ + ocr_avail = <0x00360080>; + clocks = <&clk_sdio1>, <&clk_76m8>; + base_clk = <76000000>; + caps = <0xC00FA407>; + caps2 = <0x0>; + pm_caps = <0x5>; + writeDelay = <0x03>; + readPosDelay = <0x03>; + readNegDelay = <0x03>; + }; + }; + + adic:adic { + compatible = "sprd,adi"; + reg = <0 0x40030000 0 0x10000>; + }; + + adi: adi_bus { + compatible = "sprd,adi-bus"; + interrupts = <0 38 0x0>; + reg = <0 0x40038000 0 0x1000>; + interrupt-controller; + sprd,irqnums = <11>; + #interrupt-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x100 0 0x40038100 0x80>, + <0x440 0 0x40038440 0x40>, + <0x800 0 0x40038800 0xff>; + + keyboard_backlight { + compatible = "sprd,keyboard-backlight"; + }; + + sprd_kpled_2723 { + compatible = "sprd,sprd-kpled-2723"; + brightness_max = <255>; + brightness_min = <0>; + run_mode = <1>; + }; + + leds_sprd_bltc_rgb { + compatible = "sprd,sprd-leds-bltc-rgb"; + reg = <0x440 0x40>, + <0x800 0xff>; + }; + + a_eic_gpio: gpio@100{ + compatible = "sprd,a-eic-gpio"; + reg = <0x100 0x80>; /* adi reg */ + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-cells = <2>; + gpiobase = <304>; + ngpios = <16>; + interrupt-parent = <&adi>; + interrupts = <5 0x0>; /* ext irq 5 */ + }; + sprd_eic_keys { + compatible = "sprd,sprd-eic-keys"; + input-name = "sprd-eic-keys"; + key_power { + label = "Power Key"; + linux,code = <116>; + gpios = <&a_eic_gpio 2 0>; + debounce-interval = <2>; + gpio-key,wakeup; + }; + key_volumeup { + label = "Volumeup Key"; + linux,code = <115>; + gpios = <&a_eic_gpio 10 0>; + debounce-interval = <2>; + gpio-key,wakeup; + }; + }; + + headset_sprd_sc2723 { + compatible = "sprd,headset_sprd_sc2723"; + gpio_switch = <0>; + gpio_detect = <312>; + gpio_button = <307>; + irq_trigger_level_detect = <1>; + irq_trigger_level_button = <1>; + adc_threshold_3pole_detect = <2650>; + adc_threshold_4pole_detect = <2651>; + irq_threshold_buttont = <1>; + voltage_headmicbias = <3000000>; + nbuttons = <3>; + headset_buttons_media { + adc_min = <0>; + adc_max = <430>; + code = <226>; + type = <0>; + }; + + headset_buttons_up { + adc_min = <431>; + adc_max = <860>; + code = <115>; + type = <0>; + }; + headset_buttons_down { + adc_min = <861>; + adc_max =<1900>; + code = <114>; + type = <0>; + }; + }; + + rtc@80{ + compatible = "sprd,rtc"; + reg = <0X80 0x80>; + interrupt-parent = <&adi>; + interrupts = <2 0x0>; + }; + }; + + sprd_pwm_bl { + compatible = "sprd,sprd_pwm_bl"; + brightness_max = <255>; + brightness_min = <0>; + pwm_index = <2>; + gpio_ctrl_pin = <0>; + gpio_active_level = <0>; + reg =<0 0x40260000 0 0xf>; + }; + + gpio_keys { + compatible = "gpio-keys"; + input-name = "sprd-gpio-keys"; + key_volumedown { + label = "Volumedown Key"; + linux,code = <114>; + gpios = <&d_gpio_gpio 124 1>; + debounce-interval = <2>; + gpio-key,wakeup; + }; +/* + key_volumeup { + label = "Volumeup Key"; + linux,code = <115>; + gpios = <&d_gpio_gpio 125 1>; + debounce-interval = <2>; + gpio-key,wakeup; + }; +*/ + key_camerafocus { + label = "Camerafocus Key"; + linux,code = <0x210>; + gpios = <&d_gpio_gpio 121 0>; + debounce-interval = <2>; + gpio-key,wakeup; + }; + key_camera { + label = "Camera Key"; + linux,code = <212>; + gpios = <&d_gpio_gpio 122 0>; + debounce-interval = <2>; + gpio-key,wakeup; + }; + }; + + sprd_backlight { + compatible = "sprd,sprd_backlight"; + start = <3>; + end = <3>; + flags = <0x100>; + }; + + rfkill { + compatible = "broadcom,rfkill"; + gpios = <&d_gpio_gpio 131 0 /* power */ + &d_gpio_gpio 122 0>; /* reset */ + }; + bluesleep { + compatible = "broadcom,bluesleep"; + bt-wake-gpio = <&d_gpio_gpio 132 0>; + host-wake-gpio = <&d_gpio_gpio 133 0>; + }; + + usb: usb@20200000{ + compatible = "sprd,usb"; + interrupts = <0 55 0x0>; + ngpios = <1>; + gpios = <&a_eic_gpio 0 0>; + reg = <0 0x20200000 0 0x1000>; + tune_value = <0x0005af33>; + usb-supply = <&vddusb>; + #address-cells = <1>; + #size-cells = <0>; + }; + sprd_thermal: thermal@402F0000{ + compatible = "sprd,sprd-thermal"; + id = <0>; + interrupts = <0 26 0x0>; + reg = <0 0x402F0000 0 0x1000>; + trip_points_active = <90 100>; + trip_points_lowoff = <0 75>; + trip_points_critical = <100>; + trip_num = <3>; + cool_num = <2>; + cooling-names = "thermal-cpufreq-0","thermal-cpufreq-1"; + }; + sprd_thermal1:thermal1@402F0000 { + compatible = "sprd,sprd-thermal"; + id = <1>; + interrupts = <0 26 0x0>; + reg = <0 0x402F0000 0 0x1000>; + trip_points_active = <100>; + trip_points_lowoff = <90>; + trip_points_critical = <100>; + trip_num = <2>; + }; + sprd_thermal2: thermal@40038280{ + compatible = "sprd,sprd-thermal"; + id = <2>; + interrupt-parent = <&adi>; + interrupts = <9 0x0>; + reg = <0 0x40038280 0 0x1000>; + trip_points_active = <110>; + trip_points_lowoff = <90>; + trip_points_critical = <110>; + trip_num = <2>; + }; + sprd_board_thermal: board-thermal{ + compatible = "sprd,board-thermal"; + id = <3>; + trip_points_active = <100>; + trip_points_lowoff = <90>; + trip_points_critical = <100>; + trip_num = <2>; + temp_inteval=<2>; + temp-support = <1>; + temp-adc-ch = <2>; + temp-adc-scale = <1>; + temp-adc-sample-cnt = <15>; + temp-table-mode = <1>; + temp-tab-size = <16>; + temp-tab-val = <1122 1094 1049 983 892 779 + 654 528 413 316 238 178 + 133 100 75 57>; + temp-tab-temp = <965 975 985 995 1005 1015 /* temperature + 1000,750 = 1000 + (-250)*/ + 1025 1035 1045 1055 1065 1075 + 1085 1095 1105 1115>; + + }; + adc: adc@40038300{ + compatible = "sprd,sprd-adc"; + reg = <0x40038300 0x1000>; + }; + i2c0: i2c@70500000{ + compatible = "sprd,i2c"; + interrupts = <0 11 0x0>; + reg = <0 0x70500000 0 0x1000>; + clock-names = "clk_i2c0"; + clocks = <&clk_i2c0>; + #address-cells = <1>; + #size-cells = <0>; + sensor_main@0x3c { + compatible = "sprd,sensor_main"; + reg = <0x3c>; + }; + sensor_sub@0x21 { + compatible = "sprd,sensor_sub"; + reg = <0x21>; + }; + }; + little_cpu_cooling{ + compatible = "sprd,sprd-cpu-cooling"; + id = <0>; + cluster = <0>; + max_freq = <1000000 1000000>; + max_core = <4 1>; + state_num = <2>; + }; + big_cpu_cooling{ + compatible = "sprd,sprd-cpu-cooling"; + id = <1>; + cluster = <1>; + max_freq = <1500000 1200000>; + max_core = <4 0>; + state_num = <2>; + }; + + i2c1: i2c@70600000{ + compatible = "sprd,i2c"; + interrupts = <0 12 0x0>; + reg = <0 0x70600000 0 0x1000>; + clock-names = "clk_i2c1"; + clocks = <&clk_i2c1>; + #address-cells = <1>; + #size-cells = <0>; + fairchild_fan53555@60{ + compatible = "fairchild,fairchild_fan53555"; + reg = <0x60>; + vddbigarm: vddbigarm { + regulator-name = "vddbigarm"; + regulator-default-microvolt = <1020000>;/*1050000*/ + regulator-step-microvolt = <10000>;/* 10 * 1000 uV */ + regulator-min-microvolt = <600000>;/* 600 * 1000 uV */ + regulator-max-microvolt = <1230000>;/*(600 + 10 * 0x3F) * 1000 uV*/ + }; + }; + }; + + i2c2: i2c@70700000{ + compatible = "sprd,i2c"; + interrupts = <0 13 0x0>; + reg = <0 0x70700000 0 0x1000>; + clock-names = "clk_i2c2"; + clocks = <&clk_i2c2>; + #address-cells = <1>; + #size-cells = <0>; + + lis3dh_acc@18{ + compatible = "ST,lis3dh_acc"; + reg = <0x18>; + poll_interval = <10>; + min_interval = <10>; + g_range = <0>; + axis_map_x = <1>; + axis_map_y = <0>; + axis_map_z = <2>; + negate_x = <0>; + negate_y = <1>; + negate_z = <0>; + }; + ltr_558als@23{ + compatible = "LITEON,ltr_558als"; + reg = <0x23>; + gpios = <&d_gpio_gpio 140 0>; + }; + epl259x_pls@49{ + compatible = "ELAN,epl259x_pls"; + reg = <0x49>; + gpios = <&d_gpio_gpio 140 0>; + }; + + }; + + i2c3: i2c@70800000{ + compatible = "sprd,i2c"; + interrupts = <0 14 0x0>; + reg = <0 0x70800000 0 0x1000>; + clock-names = "clk_i2c3"; + clocks = <&clk_i2c3>; + #address-cells = <1>; + #size-cells = <0>; + + focaltech_ts@38{ + compatible = "focaltech,focaltech_ts"; + reg = <0x38>; + gpios = <&d_gpio_gpio 145 0 + &d_gpio_gpio 144 0>; + vdd_name = "vdd18"; + virtualkeys = <580 1350 60 45 + 360 1350 60 45 + 160 1350 60 45>; + TP_MAX_X = <720>; + TP_MAX_Y = <1280>; + }; + msg2138_ts@26{ + compatible = "Mstar,msg2138_ts"; + reg = <0x26>; + gpios = <&d_gpio_gpio 145 0 + &d_gpio_gpio 144 0>; + vdd_name = "vdd28"; + virtualkeys = <256 1068 64 64 + 128 1068 64 64 + 192 1068 64 64>; + TP_MAX_X = <480>; + TP_MAX_Y = <800>; + }; + }; + + i2c4: i2c@70900000{ + compatible = "sprd,i2c"; + interrupts = <0 15 0x0>; + reg = <0 0x70900000 0 0x1000>; + clock-names = "clk_i2c4"; + clocks = <&clk_i2c4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi0: spi0@70a00000{ + compatible = "sprd,sprd-spi"; + interrupts = <0 7 0x0>; + reg = <0 0x70a00000 0 0x1000>; + clock-names = "clk_spi0"; + }; + + spi1: spi1@70b00000{ + compatible = "sprd,sprd-spi"; + interrupts = <0 8 0x0>; + reg = <0 0x70b00000 0 0x1000>; + clock-names = "clk_spi1"; + }; + + spi2: spi2@70c00000{ + compatible = "sprd,sprd-spi"; + interrupts = <0 9 0x0>; + reg = <0 0x70c00000 0 0x1000>; + clock-names = "clk_spi2"; + }; + + dma: dma-controller@20100000 { + compatible = "sprd,sharkl64-dma"; + #dma-cells = <1>; + #dma-channels = <64>; + sprd,aon-offset = <32>; + reg = <0 0x20100000 0 0x4000>, /* ap reg */ + <0 0x40100000 0 0x4000>; /* aon reg */ + interrupts = <0 50 0x0>, /* ap int */ + <0 70 0x0>; /* aon int */ + }; + + sprd-io-base { + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 1 0>; + ahb { + compatible = "sprd,ahb"; + reg = <0 0x20e00000 0 0x40000>; + }; + apbckg { + compatible = "sprd,apbckg"; + reg = <0 0x21500000 0 0x1000>; + }; + hwlock0 { + compatible = "sprd,hwlock0"; + reg = <0 0x20d00000 0 0x1000>; + }; + pub_apb { + compatible = "sprd,pub_apb"; + reg = <0 0x30020000 0 0x10000>; + }; + aon_apb { + compatible = "sprd,aon_apb"; + reg = <0 0x402e0000 0 0x40000>; + }; + pmu_apb { + compatible = "sprd,pmu_apb"; + reg = <0 0x402b0000 0 0x40000>; + }; + mm_ahb { + compatible = "sprd,mm_ahb"; + reg = <0 0x60d00000 0 0x10000>; + }; + mm_clk { + compatible = "sprd,mm_clk"; + reg = <0 0x60e00000 0 0x1000>; + }; + codecahb { + compatible = "sprd,codecahb"; + reg = <0 0x62000000 0 0x1000>; + }; + ap_ckg { + compatible = "sprd,ap_ckg"; + reg = <0 0x71200000 0 0x40000>; + }; + ap_apb { + compatible = "sprd,ap_apb"; + reg = <0 0x71300000 0 0x40000>; + }; + gpu_apb { + compatible = "sprd,gpu_apb"; + reg = <0 0x60100000 0 0x1000>; + }; + adi { + compatible = "sprd,adi"; + reg = <0 0x40030000 0 0x10000>; + }; + adi_slave { + compatible = "sprd,adi_slave"; + reg = <0 0x40038000 0 0x1000>; + }; + + mailbox { + compatible = "sprd,mailbox"; + reg = <0 0x400a0000 0 0x10000>; + }; + uart0 { + compatible = "sprd,uart0"; + reg = <0 0x70000000 0 0x1000>; + }; + uart1 { + compatible = "sprd,uart1"; + reg = <0 0x70100000 0 0x1000>; + }; + uart2 { + compatible = "sprd,uart2"; + reg = <0 0x70200000 0 0x1000>; + }; + uart3 { + compatible = "sprd,uart3"; + reg = <0 0x70300000 0 0x1000>; + }; + uart4 { + compatible = "sprd,uart4"; + reg = <0 0x70400000 0 0x1000>; + }; + axibm0 { + compatible = "sprd,axibm0"; + reg = <0 0x30040000 0 0x20000>; + interrupts = <0 86 0x0>; + }; + d_eic_gpio { + compatible = "sprd,d-eic-gpio"; + reg = <0 0x40210000 0 0x1000>; + }; + d_gpio_gpio { + compatible = "sprd,d-gpio-gpio"; + reg = <0 0x40280000 0 0x1000>; + }; + aon_dma { + compatible = "sprd,aon_dma"; + reg = <0 0x40100000 0 0x1000>; + interrupts = <0 50 0x0>; + }; + pwm { + compatible = "sprd,pwm"; + reg = <0 0x40260000 0 0x1000>; + }; + core { + compatible = "sprd,core"; + reg = <0 0x12000000 0 0x10000>; + }; + int { + compatible = "sprd,int"; + reg = <0 0x40200000 0 0x1000>; + }; + intc0 { + compatible = "sprd,intc0"; + reg = <0 0x71400000 0 0x1000>; + }; + intc1 { + compatible = "sprd,intc1"; + reg = <0 0x71500000 0 0x1000>; + }; + intc2 { + compatible = "sprd,intc2"; + reg = <0 0x71600000 0 0x1000>; + }; + intc3 { + compatible = "sprd,intc3"; + reg = <0 0x71700000 0 0x1000>; + }; + send_mbox { + compatible = "sprd,send_mbox"; + reg = <0 0x400a0000 0 0x1000>; + }; + recv_mbox { + compatible = "sprd,recv_mbox"; + reg = <0 0x400a8000 0 0x1000>; + }; + uidefuse { + compatible = "sprd,uidefuse"; + reg = <0 0x40240000 0 0x1000>; + }; + isp { + compatible = "sprd,isp"; + reg = <0 0x60a00000 0 0x8000>; + }; + csi2 { + compatible = "sprd,csi2"; + reg = <0 0x60c00000 0 0x1000>; + }; + ipi { + compatible = "sprd,ipi"; + reg = <0 0x402c0000 0 0x1000>; + }; + dcam { + compatible = "sprd,dcam"; + reg = <0 0x60800000 0 0x10000>; + }; + syscnt { + compatible = "sprd,syscnt"; + reg = <0 0x40230000 0 0x1000>; + }; + dma0 { + compatible = "sprd,dma0"; + reg = <0 0x20100000 0 0x4000>; + }; + pub { + compatible = "sprd,pub"; + reg = <0 0x30020000 0 0x10000>; + }; + pin { + compatible = "sprd,pin"; + reg = <0 0x402a0000 0 0x1000>; + }; + aonckg { + compatible = "sprd,aonckg"; + reg = <0 0x402d0000 0 0x1000>; + }; + lpddr2 { + compatible = "sprd,lpddr2"; + reg = <0 0x30000000 0 0x1000>; + }; + }; + + sprd_dcam { + compatible = "sprd,sprd_dcam"; + interrupts = <0 45 0>; + reg = <0 0x60800000 0 0x100000>; + clock-names = "clk_mm_i","clk_dcam"; + clocks = <&clk_mm>, <&clk_dcam>; + }; + + sprd_scale { + compatible = "sprd,sprd_scale"; + }; + + sprd_rotation { + compatible = "sprd,sprd_rotation"; + }; + + sprd_sensor { + compatible = "sprd,sprd_sensor"; + reg = <0 0x60c00000 0 0x100000>; + gpios = <&d_gpio_gpio 44 0 /*main reset*/ + &d_gpio_gpio 46 0 /*main powerdown*/ + &d_gpio_gpio 45 0 /*sub reset*/ + &d_gpio_gpio 47 0 + &d_gpio_gpio 0 0 /*main core voltage*/ + &d_gpio_gpio 0 0 + &d_gpio_gpio 0 0 + &d_gpio_gpio 0 0>; /*sub powerdown*/ + clock-names ="clk_mm_i","clk_sensor","clk_ccir","clk_dcam","clk_dcam_mipi"; + clocks = <&clk_mm>,<&clk_sensor>,<&clk_ccir>,<&clk_dcam>,<&clk_dcam_mipi>; + }; + + sprd_isp { + compatible = "sprd,sprd_isp"; + reg = <0 0x60a00000 0 0x100000>; + clock-names = "clk_mm_i","clk_isp"; + clocks = <&clk_mm>, <&clk_isp>; + }; + + sprd_dma_copy { + compatible = "sprd,sprd_dma_copy"; + }; + + fb0: fb@20800000 { + compatible = "sprd,sprdfb"; + reg = <0 0x20800000 0 0x1000>, + <0 0x21800000 0 0x1000>; + interrupts = <0 46 0x0>, + <0 48 0x0>, + <0 49 0x0>; + clock-names = "dispc_clk_parent", "dispc_dbi_clk_parent", "dispc_dpi_clk_parent", "dispc_emc_clk_parent", "dispc_clk", "dispc_dbi_clk", "dispc_dpi_clk", "dispc_emc_clk", "fb_spi_clock", "fb_spi_clock_parent"; + clocks = <&clk_256m>, <&clk_256m>, <&clk_384m>, <&clk_aon_apb>, <&clk_dispc0>, <&clk_dispc0_dbi>, <&clk_dispc0_dpi>, <&clk_disp_emc>, <&clk_spi2>, <&ext_26m>; + clock-src = <256000000 256000000 384000000>; + dpi_clk_div = <7>; + sprd,fb_use_reservemem; + sprd,fb_mem = <0x9ED74000 0xA8C000>; + }; + + gsp@20a00000 { + compatible = "sprd,gsp"; + reg = <0 0x20a00000 0 0x1000>; + interrupts = <0 51 0x0>; + clock-names = "clk_gsp0", "clk_gsp_emc", "clk_gsp_parent", "clk_aon_apb"; + clocks = <&clk_gsp0>, <&clk_gsp_emc>, <&clk_256m>, <&clk_aon_apb>; + gsp_mmu_ctrl_base = <0x20b08000>; + }; + + /*sharLT8 gspn initializer */ + gspn:gspn@0x20A00000 { + compatible = "sprd,gspn"; + reg = <0 0x71500000 0 0x1000>, // arm interrupt ctl reg + <0 0x20E00000 0 0x1000>, //gspn module enable ctl reg base + <0 0x20E00004 0 0x1000>, //gspn module reset ctl reg base + <0 0x20E0304C 0 0x1000>, //[0] gsp/gspn select reg base, 0:gsp; 1:gspn + <0 0x402e00fc 0 0x1000>; //[0] ap chip id reg addr + gspn0:gspn@0x20A00000 { + core_id = <0>; + gspn_en_rst_bit = <0x00000008>;//bit3 + mmu_en_rst_bit = <0x00000008>;//bit3 + auto_gate_bit = <0x00000100>;//bit8 + force_gate_bit = <0x00000200>;//bit9 + emc_en_bit = <0x00000008>;//bit3 + reg = <0 0x20A00000 0 0x1000>, //gspn module ctl reg + <0 0x20B08000 0 0x1000>, //iommu ctl reg,64MB,page size 4KB + <0 0x215000a0 0 0x1000>, //gspn clock source select ctl reg base + <0 0x20E00010 0 0x1000>, //gspn clock auto-gate/force-gate ctl reg base + <0 0x20E00000 0 0x1000>; //gspn emc clock ctl reg base + interrupts = <0 51 0x0>; + clock-names = "clk_gsp1", "clk_gsp_emc", "clk_gsp_parent", "clk_aon_apb"; + clocks = <&clk_gsp1>, <&clk_gsp_emc>, <&clk_307m2>, <&clk_aon_apb>; + }; + }; + + sprd_fm: sprd_fm@40270000{ + compatible = "sprd,sprd_fm"; + reg = <0 0x40270000 0 0x1000>; + }; + + sipc: sipc@0x87800000 { + compatible = "sprd,sipc"; + reg = <0 0x87800000 0 0x5B0000>; /* <SMEM SIZE>*/ + //#interrupt-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + ranges =<0x09600000 0 0x89600000 0x4600000>, + <0x07800000 0 0x87800000 0x5B0000>, + <0x0dbff000 0 0x8dbff000 0x1000>, + <0x5000c000 0 0x5000c000 0x1000>; + sipc_lte@0x09600000 { + sprd,name = "sipc-lte"; + sprd,dst = <5>; + /* it's unnecessary to config IPI info upon mailbox arch */ + mailbox,core = <7>; + reg = <0x09600000 0x4600000> , /* <CP_start_addr size> */ + <0x07800000 0x5B0000>, /* <SMEM_phy_addr total_size> */ + <0x0dbff000 0x1000>; /* smsg ring buffer <base size> */ + }; + sipc_pmsys@0x5000c000 { + sprd,name = "sipc-pmsys"; + sprd,dst = <6>; + /* it's unnecessary to config IPI info upon mailbox arch */ + mailbox,core = <1>; + reg = <0x5000c000 0x1000>; /* smsg ring buffer <base size> */ + }; + }; + + saudio_lte{ + compatible = "sprd,saudio"; + sprd,saudio-dst-id = <5>; /* SIPC_ID_LTE */ + sprd,ctrl_channel = <10>; /* SMSG_CH_VBC */ + sprd,playback_channel = <11>; /* SMSG_CH_PLAYBACK */ + sprd,capture_channel = <12>; /* SMSG_CH_CAPTURE */ + sprd,monitor_channel = <13>; /*SMSG_CH_MONITOR_AUDIO */ + sprd,saudio-names = "saudiolte"; + }; + + saudio_voip{ + compatible = "sprd,saudio"; + sprd,saudio-dst-id = <5>; /* SIPC_ID_LTE */ + sprd,ctrl_channel = <14>; /* SMSG_CH_CTRL_VOIP */ + sprd,playback_channel = <15>; /* SMSG_CH_PLAYBACK_VOIP */ + sprd,capture_channel = <16>; /* SMSG_CH_CAPTURE_VOIP */ + sprd,monitor_channel = <17>; /*SMSG_CH_MONITOR_VOIP */ + sprd,saudio-names = "saudiovoip"; + }; + + /* LTE modem virtual devices */ + spipe_lte { + compatible = "sprd,spipe"; + sprd,name = "spipe_lte"; + sprd,dst = <5>; + sprd,channel = <4>; + sprd,ringnr = <9>; + sprd,size-rxbuf = <0x1000>; /* 4*1024 */ + sprd,size-txbuf = <0x1000>; /* 4*1024 */ + }; + + slog_lte { + compatible = "sprd,spipe"; + sprd,name = "slog_lte"; + sprd,dst = <5>; + sprd,channel = <5>; + sprd,ringnr = <1>; + sprd,size-rxbuf = <0x40000>; /* 256*1024*/ + sprd,size-txbuf = <0x8000>; /* 32*1024 */ + }; + + sdiag_lte { + compatible = "sprd,spipe"; + sprd,name = "sdiag_lte"; + sprd,dst = <5>; + sprd,channel = <21>; + sprd,ringnr = <1>; + sprd,size-rxbuf = <0x40000>; /* 256*1024*/ + sprd,size-txbuf = <0x8000>; /* 32*1024 */ + }; + + stty_lte { + compatible = "sprd,spipe"; + sprd,name = "stty_lte"; + sprd,dst = <5>; + sprd,channel = <6>; + sprd,ringnr = <32>; + sprd,size-rxbuf = <0x0800>; /* 2*1024*/ + sprd,size-txbuf = <0x0800>; /* 2*1024 */ + }; + + seth0_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte0"; + sprd,dst = <5>; + sprd,channel = <7>; + sprd,blknum = <256>; + }; + + seth1_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte1"; + sprd,dst = <5>; + sprd,channel = <8>; + sprd,blknum = <256>; + }; + + seth2_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte2"; + sprd,dst = <5>; + sprd,channel = <9>; + sprd,blknum = <256>; + }; + + seth3_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte3"; + sprd,dst = <5>; + sprd,channel = <18>; + sprd,blknum = <256>; + }; + + seth4_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte4"; + sprd,dst = <5>; + sprd,channel = <19>; + sprd,blknum = <256>; + }; + + seth5_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte5"; + sprd,dst = <5>; + sprd,channel = <20>; + sprd,blknum = <256>; + }; + scproc_arm7: scproc@0x50800000 { + compatible = "sprd,scproc"; + sprd,name = "cppmic"; + sprd,ctrl-reg = <0x114 0xff 0xb0 0xff>; /* <shut_down deep_sleep reset get_status> */ + sprd,ctrl-mask = <0x01 0xfffffffe 0x100 0xf0000>; /* masks <> */ + sprd,iram-data = <0xe59f0000 0xe12fff10 0x0>; /* 3rd param equals modem_addr*/ + reg = <0 0x50800000 0 0x8000>, /* <CP_start_addr total_size> = <+128M 26M> */ + <0 0x50800000 0 0x0>, /* <iram1_base size> */ + <0 0x402e0000 0 0x400>, /* <aon_apb_base size> */ + <0 0x402b0000 0 0x100>, /* <pmu_base size> */ + <0 0x402b0000 0 0x100>, /* <pmu_base size> */ + <0 0x402b0000 0 0x100>; /* <pmu_base size> */ + #address-cells = <1>; + #size-cells = <1>; + /* segnr=1 */ + ranges = <0x0 0 0x50800000 0x8000>; + modem@0x0 { + cproc,name = "modem"; + reg = <0x0 0x8000>; /* <modem_addr size> */ + }; + }; + + scproc_cp1: scproc@0x89600000 { + compatible = "sprd,scproc"; + sprd,name = "cptl"; + sprd,ctrl-reg = <0x0c 0xff 0xb0 0x78>; /* <shut_down deep_sleep reset get_status> */ + sprd,ctrl-mask = <0x00300000 0x10000000 0x02 0x1>; /* masks <> */ + sprd,iram-data = <0xe59f0000 0xe12fff10 0x8ae00000>; /* 3rd param equals modem_addr*/ + reg = <0 0x89600000 0 0x5300000>, /* <CP_start_addr total_size> = <+128M 83M> */ + <0 0x50001000 0 0x0c>, /* <iram1_base size> */ + <0 0x402e0000 0 0x100>, /* <aon_apb_base size> */ + <0 0x402b0000 0 0x100>, /* <pmu_base size> */ + <0 0x402b0000 0 0x100>, /* <pmu_base size> */ + <0 0x402b0000 0 0x100>; /* <pmu_base size> */ + interrupts = <0 84 0x0>; /* cp1_wdg_int */ + #address-cells = <1>; + #size-cells = <1>; + /* segnr=4 */ + ranges = <0x1800000 0 0x8ae00000 0x02E00000>, + <0x0020000 0 0x89620000 0x002E0000>, + <0x0300000 0 0x89900000 0x1C0000>, + <0x4900000 0 0x8df00000 0xA00000>; + modem@0x1800000 { + cproc,name = "modem"; + reg = <0x1800000 0x02E00000>; /* <modem_addr size> */ + }; + dsp@0x20000 { + cproc,name = "tgdsp"; + reg = <0x20000 0x002e0000>; /* <dsp_addr size>*/ + }; + dsp@0x300000 { + cproc,name = "ldsp"; + reg = <0x300000 0x1c0000>; /* <dsp_addr size>*/ + }; + modem@0x4900000 { + cproc,name = "warm"; + reg = <0x4900000 0xA00000>; /* <modem_addr size>*/ + }; + }; + + itm_wlan{ + compatible = "sprd,itm_wlan"; + }; + + dmac: dmac@20100000 { + compatible = "sprd,sprd-dma"; + interrupts = <0 50 0x0>; + reg = <0 0x20100000 0 0x4000>; + }; + + gpu: gpu@60000000 { + compatible = "sprd,mali-midgard"; + reg = <0 0x60000000 0 0x4000>; + interrupts = <0 39 0x4>, <0 39 0x4>, <0 39 0x4>; + interrupt-names = "JOB", "MMU", "GPU"; + + clocks = <&clk_gpu_axi>,<&clk_gpu>,<&clk_153m6>, <&clk_192m>, <&clk_256m>, <&clk_307m2>, <&clk_384m>, <&clk_gpll>; + clock-names = "clk_gpu_axi","clk_gpu","clk_153m6","clk_192m","clk_256m","clk_307m2","clk_384m","clk_gpll"; + + freq-list-len = <4>; + freq-lists = <153600 2 1>, <256000 4 1>, <384000 6 1>, <512000 7 1>; + freq-default = <3>; + freq-9 = <3>; + freq-8 = <3>; + freq-7 = <1>; + freq-5 = <0>; + freq-range-max = <3>; + freq-range-min = <0>; + }; + + ion { + compatible = "sprd,ion-sprd"; + #address-cells = <1>; + #size-cells = <0>; + + sprd,ion-heap@1 { + reg = <1>; /* SYSTEM */ + reg-names = "ion_heap_system"; + sprd,ion-heap-type = <0>; /* SYSTEM */ + sprd,ion-heap-mem = <0x0 0x0>; + }; + + sprd,ion-heap@2 { + reg = <2>; /* MM */ + reg-names = "ion_heap_carveout_mm"; + sprd,ion-heap-type = <0>; /* carveout mm */ + sprd,ion-heap-mem = <0x9864F000 0x7100000>; + }; + + sprd,ion-heap@3 { + reg = <3>; /* OVERLAY */ + reg-names = "ion_heap_carveout_overlay"; + sprd,ion-heap-type = <2>; /* CARVEOUT */ + sprd,ion-heap-mem = <0x9F800000 0x800000>; /* 480*854*4*2, 1M alignment */ + }; + + sprd,ion-heap@4 { + reg = <4>; /* FB */ + reg-names = "ion_heap_carveout_fb"; + sprd,ion-heap-type = <2>; /* CARVEOUT */ + sprd,ion-heap-mem = <0x9ED74000 0xA8C000>; + }; + }; + + sprd_iommu0: sprd_iommu@20b00000 { + compatible = "sprd,sprd_iommu";//gsp + func-name = "sprd_iommu_gsp"; + reg = <0 0x10000000 0 0x2000000>, //iova + <0 0x20b00000 0 0x8000>, //pgt + <0 0x20b08000 0 0x8000>; //ctrl_reg + reg_name = "iova","pgt","ctrl_reg"; + clock-names = "clk_gsp_emc","clk_153m6","clk_gsp0"; + clocks = <&clk_gsp_emc>, <&clk_153m6>,<&clk_gsp0>; + status = "ok"; + }; + + sprd_iommu1: sprd_iommu@60f00000 { + compatible = "sprd,sprd_iommu";//mm + func-name = "sprd_iommu_mm"; + reg = <0 0x20000000 0 0x8000000>, //iova + <0 0x60f00000 0 0x20000>, //pgt + <0 0x60f20000 0 0x2000>; //ctrl_reg + reg_name = "iova","pgt","ctrl_reg"; + clock-names = "clk_mmu","clk_mm_i"; + clocks = <&clk_mmu>,<&clk_mm>; + status = "ok"; + }; + + sprd_vsp: sprd_vsp@60900000{ + compatible = "sprd,sprd_vsp"; + reg = <0 0x60900000 0 0xc000>; + interrupts = <0 43 0x0>; + clock-names = "clk_mm_i", "clk_vsp", "clk_parent_0", "clk_parent_1", "clk_parent_2", "clk_parent_3"; + clocks = <&clk_mm>, <&clk_vsp>, <&clk_307m2>, <&clk_256m>, <&clk_128m>, <&clk_96m>; + clock-parent-info = <2 4>; + version = <7>; + }; + + sprd_vpp@61000000{ + compatible = "sprd,sprd_vpp"; + reg = <0 0x61000000 0 0x4000>; + interrupts = <0 43 0x0>; + clock-names = "clk_mm_i","clk_vpp","clk_256m","clk_153m6","clk_128m","clk_96m"; + clocks = <&clk_mm>, <&clk_vpp>, <&clk_256m>, <&clk_153m6>, <&clk_128m>, <&clk_96m>; + clock-parent-info = <2 4>; + }; + + sprd_coda7l@62100000{ + compatible = "sprd,sprd_coda7l"; + reg = <0 0x62100000 0 0x4000>; + interrupts = <0 43 0x0>; + clock-names = "clk_mm_i","clk_coda7_axi","clk_coda7_cc","clk_coda7_apb", + "clk_192m","clk_153m6","clk_128m","clk_76m8", + "clk_128m","clk_96m","clk_76m8","ext_26m"; + clocks = <&clk_mm>, <&clk_coda7_axi>, <&clk_coda7_cc>, <&clk_coda7_apb>, + <&clk_192m>, <&clk_153m6>, <&clk_128m>, <&clk_76m8>, + <&clk_128m>, <&clk_96m>, <&clk_76m8>, <&ext_26m>; + clock-parent-info = <4 4>; + power-regs-info = <0x402b0044 0 0x402b00c8 0xf0000000>; + }; + + + sprd_jpg { + compatible = "sprd,sprd_jpg"; + reg = <0 0x60b00000 0 0x8000>; + interrupts = <0 42 0x0>; + clock-names = "clk_mm_i","clk_jpg"; + clocks = <&clk_mm>, <&clk_jpg>; + }; + sprd_bm { + compatible = "sprd,sprd_bm"; + reg = <0 0x30040000 0 0xA0000 + 0 0x20F00000 0 0x300000>; + interrupts = <0 86 0x0>; + sprd,bm_status = <1>; + sprd,bm_count = <10 11>; + sprd,cpu_chn = <0 1>; + sprd,disp_chn = <1 1>; + sprd,gpu_chn = <2 1>; + sprd,ap_zip_chn = <3 1>; + sprd,mm_chn = <4 1>; + sprd,cp0_arm0_1_chn = <5 1>; + sprd,cp0_dsp_chn = <6 0>; + sprd,cp1_lte_chn = <7 1>; + sprd,cp1_dsp_chn = <8 1>; + sprd,cp1_arm_chn = <9 1>; + sprd,ap_dap_chn = <0 0>; + sprd,ap_cpu_chn = <0 1>; + sprd,ap_dma_r_chn = <0 2>; + sprd,ap_dma_w_chn = <0 3>; + sprd,ap_sdio_0_chn = <1 0>; + sprd,ap_sdio_1_chn = <1 1>; + sprd,ap_sdio_2_chn = <1 2>; + sprd,ap_emmc_chn = <1 3>; + sprd,ap_nandc_chn = <2 0>; + sprd,ap_otg_chn = <2 1>; + sprd,ap_hsic_chn = <2 2>; + }; + wdt@40290000 { + compatible = "sprd,sprd-wdt"; + reg = <0 0x40290000 0 0x1000>, + <0 0x40310000 0 0x1000>; + interrupts = <0 124 0x0>; + }; + sprd-marlin { + compatible = "sprd,marlin"; + gpios = <&d_gpio_gpio 97 0 /*marlin gpio0 */ + &d_gpio_gpio 132 0 /*marlin gpio1 */ + &d_gpio_gpio 133 0 /*marlin gpio2 */ + &d_gpio_gpio 94 0 /*marlin gpio3 */ + &d_gpio_gpio 130 0>; /*marlin reset*/ + cp-rfctl-offset = <0x244>; /*coex func. marlin gpio3*/ + vdd-download = "vddcon"; /*vdd 1.6v*/ + vdd-pa = "vddwifipa"; /*vdd 3.3v*/ + clk-name = "clk_aux0"; /*clk 32k*/ + sdhci-name = "sdio_wifi"; + }; + +}; + +&vbc_r2p0 { + status = "okay"; +}; + +&sprd_codec { + status = "okay"; + sprd,audio_power_ver = <4>; +}; + +&i2s0 { + sprd,config_type = "pcm"; + sprd,slave_timeout = <0xF11>; + sprd,_hw_port = <0>; + sprd,fs = <8000>; + sprd,bus_type = <1>; + sprd,rtx_mode = <3>; + sprd,byte_per_chan = <1>; + sprd,slave_mode = <0>; + sprd,lsb = <0>; + sprd,lrck = <0>; + sprd,low_for_left = <1>; + sprd,clk_inv = <0>; + sprd,pcm_short_frame = <1>; + sprd,pcm_slot = <0x1>; + sprd,pcm_cycle = <1>; + sprd,tx_watermark = <12>; + sprd,rx_watermark = <20>; + status = "okay"; +}; + +&i2s1 { + status = "okay"; +}; + +&i2s2 { + status = "okay"; +}; + +&i2s3 { + status = "okay"; +}; + +&i2s_sound { + sprd,i2s = <&i2s0>, <&i2s1>, <&i2s2>, <&i2s3>; +}; + +&sprd_battery { + gpios = <&a_eic_gpio 0 0 /* chg int */ + &a_eic_gpio 4 0 /* cv state */ + &a_eic_gpio 6 0 /* chg ovi */ + &a_eic_gpio 9 0>; /* battery detect */ + + chg-end-vol-h = <4375>; + chg-end-vol-pure = <4350>; + chg-end-vol-l = <4340>; + chg-bat-safety-vol = <4430>; + rechg-vol = <4260>; + + fgu-mode = <0>; + alm-soc = <5>; + alm-vol = <3500>; + soft-vbat-uvlo = <3100>; + rint = <200>; + cnom = <2100>; + rsense-real = <118>; + rsense-spec = <200>; + relax-current = <50>; + fgu-cal-ajust = <0>; + ocv-tab-size = <21>; + ocv-tab-vol = <4318 4254 4198 4145 4094 4052 3987 3955 3902 3865 3838 3817 3800 3785 3769 3752 3733 3706 3691 3588 3400>; + ocv-tab-cap = <100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0>; +}; diff --git a/arch/arm64/boot/dts/sprd_sp9838aea_8core_light_sleep.dts b/arch/arm64/boot/dts/sprd_sp9838aea_8core_light_sleep.dts new file mode 100644 index 00000000..89d88ac6 --- /dev/null +++ b/arch/arm64/boot/dts/sprd_sp9838aea_8core_light_sleep.dts @@ -0,0 +1,1596 @@ +/* + * SPREADTRUM Ltd.clock-cells +sprd_rotation + * + * SharkLT8 5mod refphone DTS + */ + +/dts-v1/; + +/* memory reserved for SMEM */ +/memreserve/ 0x87800000 0x5B0000; /* Offset:120M, Size:5M+256K */ + +/* memory reserved for WARM modem */ +/memreserve/ 0x8DC00000 0xD00000; /* Offset:220M, Size:13M*/ + +/* memory reserved for LTE modem */ +/memreserve/ 0x89600000 0x4600000; /* Offset:150M, Size:70M*/ + +/* memory reserved for fb */ +/memreserve/ 0x9ED74000 0xA8C000; /* 1280*720*4*3, 4K alignment*/ + +/* memory reserved for ION */ +/memreserve/ 0x9F800000 0x800000; /* 1280*720*4*2, 1M alignment*/ + +/* memory reserved for smp */ +/memreserve/ 0x9F700000 0x1000; /* size 4K*/ + +/include/ "sc2723-regulators.dtsi" +/include/ "sprd-sound.dtsi" +/include/ "sprd-battery.dtsi" +/include/ "scx35lt8-clocks.dtsi" + +/ { + model = "scx35l64"; + compatible = "sprd,SharkLT8"; + sprd,sc-id = <8830 1 0x20000>; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { + bootargs = "earlyprintk=sprd_uart,0x70100000 loglevel=1 console=ttyS1,115200n8"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + core1 { + cpu = <&CPU5>; + }; + core2 { + cpu = <&CPU6>; + }; + core3 { + cpu = <&CPU7>; + }; + }; + }; + + CPU0: cpu@530000 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530000>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD &CLUSTER_PD>; + clocks = <&clk_little_mcu>; + cpu0-supply = <&vddarm>; + operating-points = < + /* kHz uV */ + 1000000 900000 + 800000 900000 + 750000 900000 + 600000 900000 + 533000 900000 + 400000 900000 + 200000 900000 + >; + }; + + CPU1: cpu@530001 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530001>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD &CLUSTER_PD>; + }; + + CPU2: cpu@530002 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530002>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD &CLUSTER_PD>; + }; + + CPU3: cpu@530003 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530003>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD &CLUSTER_PD>; + }; + + CPU4: cpu@530100 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530100>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD &CLUSTER_PD>; + clocks = <&clk_big_mcu>; + cpu0-supply = <&vddbigarm>; + operating-points = < + /* kHz uV */ + 1500000 1050000 + 1420000 1050000 + 1350000 1050000 + 1200000 900000 + 1100000 900000 + 1000000 900000 + 960000 900000 + >; + }; + + CPU5: cpu@530101 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530101>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD &CLUSTER_PD>; + }; + + CPU6: cpu@530102 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530102>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD &CLUSTER_PD>; + }; + + CPU7: cpu@530103 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530103>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD &CLUSTER_PD>; + }; + + idle-states{ + entry-method = "arm,psci"; + LIGHT_SLEEP: light_sleep { + compatible = "arm,idle-state"; + exit-latency-us = <100>; + min-residency-us = <500>; + entry-method-param = <0x00000001>; + }; + CORE_PD: core_pd { + compatible = "arm,idle-state"; + exit-latency-us = <1070>; + min-residency-us = <5000>; + entry-method-param = <0x00010002>; + }; + CLUSTER_PD: cluster_pd { + compatible = "arm,idle-state"; + exit-latency-us = <2000>; + min-residency-us = <8000>; + entry-method-param = <0x01010003>; + }; + TOP_PD: top_pd { + compatible = "arm,idle-state"; + exit-latency-us = <2000>; + min-residency-us = <5000>; + entry-method-param = <0x01010004>; + }; + DEEP_SLEEP: deep_sleep { + compatible = "arm,idle-state"; + exit-latency-us = <4100>; + min-residency-us = <6500>; + entry-method-param = <0x01010005>; + }; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0 0x80000000 0 0x40000000>; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + lcd0 = &fb0; + hwspinlock0 = &hwspinlock0; + hwspinlock1 = &hwspinlock1; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 92 4>, + <0 93 4>, + <0 94 4>, + <0 95 4>; + }; + + psci { + compatible = "arm,psci"; + method = "smc"; + cpu_on = <0xc4000003>; + cpu_off = <0x84000002>; + cpu_suspend = <0xc4000001>; + }; + + gic: interrupt-controller@12001000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0x12001000 0 0x1000>, + <0 0x12002000 0 0x1000>; + }; + + intc:interrupt-controller@71400000 { + compatible = "sprd,intc"; + #interrupt-cells = <0>; + interrupt-controller; + reg = <0 0x71400000 0 0x1000>, + <0 0x71500000 0 0x1000>, + <0 0x71600000 0 0x1000>, + <0 0x71700000 0 0x1000>, + <0 0x40200000 0 0x1000>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, + <1 14 0xff01>, + <1 11 0xff01>, + <1 10 0xff01>; + clock-frequency = <26000000>; + }; + + sprd_timer { + compatible = "sprd,sharkl64-timer"; + reg = <0 0x40050000 0 0x20>; /*aon GPTIMER0 */ + interrupts = <0 28 0x0>; + clock-frequency = <32768>; + }; + + sprd_ap_system_timer { + reg = <0 0x40230000 0 0x20>; + interrupts = <0 31 0x0>; + }; + + clock: clockdevice { + compatible = "sprd,scx35l64-clocks"; + #clock-cells = <1>; + }; + + d_eic_gpio: gpio@40210000 { + compatible = "sprd,d-eic-gpio"; + reg = <0 0x40210000 0 0x1000>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-cells = <2>; + gpiobase = <288>; + ngpios = <16>; + interrupts = <0 37 0x0>; + }; + + d_gpio_gpio: gpio@40280000 { + compatible = "sprd,d-gpio-gpio"; + reg = <0 0x40280000 0 0x1000>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-cells = <2>; + gpiobase = <0>; + ngpios = <256>; + interrupts = <0 35 0x0>; + }; + + uart0: uart@70000000 { + compatible = "sprd,serial"; + interrupts = <0 2 0xf04>; + reg = <0 0x70000000 0 0x1000>; + clock-names = "clk_uart0"; + clocks = <&clock 60>; + sprdclk = <48000000>; + sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP"; + + }; + + uart1: uart@70100000 { + compatible = "sprd,serial"; + interrupts = <0 3 0xf04>; + reg = <0 0x70100000 0 0x1000>; + clock-names = "clk_uart1"; + clocks = <&clock 61>; + sprdclk = <26000000>; + sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP"; + + }; + + uart2: uart@70200000 { + compatible = "sprd,serial"; + interrupts = <0 4 0xf04>; + reg = <0 0x70200000 0 0x1000>; + clock-names = "clk_uart2"; + clocks = <&clock 62>; + sprdclk = <26000000>; + sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP"; + }; + + uart3: uart@70300000 { + compatible = "sprd,serial"; + interrupts = <0 5 0xf04>; + reg = <0 0x70300000 0 0x1000>; + clock-names = "clk_uart3"; + clocks = <&clock 63>; + sprdclk = <26000000>; + sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP"; + }; + + hwspinlock0: hwspinlock0@20c00000{ + compatible = "sprd,sprd-hwspinlock"; + reg = <0 0x20c00000 0 0x1000>; + }; + + hwspinlock1: hwspinlock1@40060000{ + compatible = "sprd,sprd-hwspinlock"; + reg = <0 0x40060000 0 0x1000>; + status = "ok"; + }; + + watchdog { + compatible = "sprd,watchdog"; + reg = <0 0X40290000 0 0x1000>; + }; + + pinctrl { + compatible = "sprd,pinctrl"; + reg = <0 0x402a0000 0 0x1000>; + pwr_domain = "vdd28", + "vdd18", + "vddsim0", + "vddsim1", + "vddsim2", + "vddsdio", + "vdd18"; + ctrl_desc = <0x10 0 1 + 0x10 1 1 + 0x10 2 1 + 0x10 3 1 + 0x10 4 1 + 0x10 5 1 + 0x10 6 1>; + }; + + sdios{ + #address-cells = <2>; + #size-cells = <2>; + ranges; + sdio3: sdio@20600000{ + compatible = "sprd,sdhost-3.0"; + reg = <0 0x20600000 0 0x1000>; + interrupts = <0 60 0x0>; + sprd,name = "sdio_emmc"; + /*detect_gpio = <-1>; */ + SD_Pwr_Name = "vddemmccore"; + _1_8V_signal_Name = "vddgen0"; + signal_default_Voltage = <1800000>; + ocr_avail = <0x00040000>; + clocks = <&clk_emmc>, <&clk_192m>; + base_clk = <192000000>; + caps = <0xC00F8D47>; + caps2 = <0x202>; + pm_caps = <0x4>; + writeDelay = <0x3E>; + readPosDelay = <0xA>; + readNegDelay = <0xA>; + }; + + sdio0: sdio@20300000{ + compatible = "sprd,sdhost-3.0"; + reg = <0 0x20300000 0 0x1000>; + interrupts = <0 57 0x0>; + sprd,name = "sdio_sd"; + detect_gpio = <141>; + SD_Pwr_Name = "vddsdcore"; + _1_8V_signal_Name = "vddsdio"; + signal_default_Voltage = <3000000>; + ocr_avail = <0x00040000>; + clocks = <&clk_sdio0>, <&clk_192m>; + base_clk = <192000000>; + caps = <0xC0020407>; + caps2 = <0x200>; + pm_caps = <0x4>; + writeDelay = <0x3>; + readPosDelay = <0x3>; + readNegDelay = <0x3>; + }; + + + sdio1: sdio@20400000{ + compatible = "sprd,sdhost-3.0"; + reg = <0 0x20400000 0 0x1000>; + interrupts = <0 58 0x0>; + sprd,name = "sdio_wifi"; + /* detect_gpio = <-1>; */ + /* SD_Pwr_Name = "vddsdcore"; */ + /* _1_8V_signal_Name = "vddsdio";*/ + /* signal_default_Voltage = <3000000>; */ + ocr_avail = <0x00360080>; + clocks = <&clk_sdio1>, <&clk_76m8>; + base_clk = <76000000>; + caps = <0xC00FA407>; + caps2 = <0x0>; + pm_caps = <0x5>; + writeDelay = <0x03>; + readPosDelay = <0x03>; + readNegDelay = <0x03>; + }; + }; + + adic:adic { + compatible = "sprd,adi"; + reg = <0 0x40030000 0 0x10000>; + }; + + adi: adi_bus { + compatible = "sprd,adi-bus"; + interrupts = <0 38 0x0>; + reg = <0 0x40038000 0 0x1000>; + interrupt-controller; + sprd,irqnums = <11>; + #interrupt-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x100 0 0x40038100 0x80>, + <0x440 0 0x40038440 0x40>, + <0x800 0 0x40038800 0xff>; + + keyboard_backlight { + compatible = "sprd,keyboard-backlight"; + }; + + sprd_kpled_2723 { + compatible = "sprd,sprd-kpled-2723"; + brightness_max = <255>; + brightness_min = <0>; + run_mode = <1>; + }; + + leds_sprd_bltc_rgb { + compatible = "sprd,sprd-leds-bltc-rgb"; + reg = <0x440 0x40>, + <0x800 0xff>; + }; + + a_eic_gpio: gpio@100{ + compatible = "sprd,a-eic-gpio"; + reg = <0x100 0x80>; /* adi reg */ + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-cells = <2>; + gpiobase = <304>; + ngpios = <16>; + interrupt-parent = <&adi>; + interrupts = <5 0x0>; /* ext irq 5 */ + }; + sprd_eic_keys { + compatible = "sprd,sprd-eic-keys"; + input-name = "sprd-eic-keys"; + key_power { + label = "Power Key"; + linux,code = <116>; + gpios = <&a_eic_gpio 2 0>; + debounce-interval = <2>; + gpio-key,wakeup; + }; + key_volumeup { + label = "Volumeup Key"; + linux,code = <115>; + gpios = <&a_eic_gpio 10 0>; + debounce-interval = <2>; + gpio-key,wakeup; + }; + }; + + headset_sprd_sc2723 { + compatible = "sprd,headset_sprd_sc2723"; + gpio_switch = <0>; + gpio_detect = <312>; + gpio_button = <307>; + irq_trigger_level_detect = <1>; + irq_trigger_level_button = <1>; + adc_threshold_3pole_detect = <2650>; + adc_threshold_4pole_detect = <2651>; + irq_threshold_buttont = <1>; + voltage_headmicbias = <3000000>; + nbuttons = <3>; + headset_buttons_media { + adc_min = <0>; + adc_max = <430>; + code = <226>; + type = <0>; + }; + + headset_buttons_up { + adc_min = <431>; + adc_max = <860>; + code = <115>; + type = <0>; + }; + headset_buttons_down { + adc_min = <861>; + adc_max =<1900>; + code = <114>; + type = <0>; + }; + }; + + rtc@80{ + compatible = "sprd,rtc"; + reg = <0X80 0x80>; + interrupt-parent = <&adi>; + interrupts = <2 0x0>; + }; + }; + + sprd_pwm_bl { + compatible = "sprd,sprd_pwm_bl"; + brightness_max = <255>; + brightness_min = <0>; + pwm_index = <2>; + gpio_ctrl_pin = <0>; + gpio_active_level = <0>; + reg =<0 0x40260000 0 0xf>; + }; + + gpio_keys { + compatible = "gpio-keys"; + input-name = "sprd-gpio-keys"; + key_volumedown { + label = "Volumedown Key"; + linux,code = <114>; + gpios = <&d_gpio_gpio 124 1>; + debounce-interval = <2>; + gpio-key,wakeup; + }; +/* + key_volumeup { + label = "Volumeup Key"; + linux,code = <115>; + gpios = <&d_gpio_gpio 125 1>; + debounce-interval = <2>; + gpio-key,wakeup; + }; +*/ + key_camerafocus { + label = "Camerafocus Key"; + linux,code = <0x210>; + gpios = <&d_gpio_gpio 121 0>; + debounce-interval = <2>; + gpio-key,wakeup; + }; + key_camera { + label = "Camera Key"; + linux,code = <212>; + gpios = <&d_gpio_gpio 122 0>; + debounce-interval = <2>; + gpio-key,wakeup; + }; + }; + + sprd_backlight { + compatible = "sprd,sprd_backlight"; + start = <3>; + end = <3>; + flags = <0x100>; + }; + + rfkill { + compatible = "broadcom,rfkill"; + gpios = <&d_gpio_gpio 131 0 /* power */ + &d_gpio_gpio 122 0>; /* reset */ + }; + bluesleep { + compatible = "broadcom,bluesleep"; + bt-wake-gpio = <&d_gpio_gpio 132 0>; + host-wake-gpio = <&d_gpio_gpio 133 0>; + }; + + usb: usb@20200000{ + compatible = "sprd,usb"; + interrupts = <0 55 0x0>; + ngpios = <1>; + gpios = <&a_eic_gpio 0 0>; + reg = <0 0x20200000 0 0x1000>; + tune_value = <0x0005af33>; + usb-supply = <&vddusb>; + #address-cells = <1>; + #size-cells = <0>; + }; + sprd_thermal: thermal@402F0000{ + compatible = "sprd,sprd-thermal"; + id = <0>; + interrupts = <0 26 0x0>; + reg = <0 0x402F0000 0 0x1000>; + trip_points_active = <65 69 95 110>; + trip_points_lowoff = <0 57 60 80>; + trip_points_critical = <100>; + trip_num = <5>; + cool_num = <2>; + cooling-names = "thermal-cpufreq-0","thermal-cpufreq-1"; + }; + sprd_thermal1:thermal1@402F0000 { + compatible = "sprd,sprd-thermal"; + id = <1>; + interrupts = <0 26 0x0>; + reg = <0 0x402F0000 0 0x1000>; + trip_points_active = <100>; + trip_points_lowoff = <90>; + trip_points_critical = <100>; + trip_num = <2>; + }; + sprd_thermal2: thermal@40038280{ + compatible = "sprd,sprd-thermal"; + id = <2>; + interrupt-parent = <&adi>; + interrupts = <9 0x0>; + reg = <0 0x40038280 0 0x1000>; + trip_points_active = <110>; + trip_points_lowoff = <90>; + trip_points_critical = <110>; + trip_num = <2>; + }; + sprd_board_thermal: board-thermal{ + compatible = "sprd,board-thermal"; + id = <3>; + trip_points_active = <100>; + trip_points_lowoff = <90>; + trip_points_critical = <100>; + trip_num = <2>; + temp_inteval=<2>; + temp-support = <1>; + temp-adc-ch = <2>; + temp-adc-scale = <1>; + temp-adc-sample-cnt = <15>; + temp-table-mode = <1>; + temp-tab-size = <16>; + temp-tab-val = <1122 1094 1049 983 892 779 + 654 528 413 316 238 178 + 133 100 75 57>; + temp-tab-temp = <965 975 985 995 1005 1015 /* temperature + 1000,750 = 1000 + (-250)*/ + 1025 1035 1045 1055 1065 1075 + 1085 1095 1105 1115>; + + }; + adc: adc@40038300{ + compatible = "sprd,sprd-adc"; + reg = <0x40038300 0x1000>; + }; + i2c0: i2c@70500000{ + compatible = "sprd,i2c"; + interrupts = <0 11 0x0>; + reg = <0 0x70500000 0 0x1000>; + clock-names = "clk_i2c0"; + clocks = <&clk_i2c0>; + #address-cells = <1>; + #size-cells = <0>; + sensor_main@0x3c { + compatible = "sprd,sensor_main"; + reg = <0x3c>; + }; + sensor_sub@0x21 { + compatible = "sprd,sensor_sub"; + reg = <0x21>; + }; + }; + little_cpu_cooling{ + compatible = "sprd,sprd-cpu-cooling"; + id = <0>; + cluster = <0>; + max_freq = <1000000 1000000>; + max_core = <4 1>; + state_num = <2>; + }; + big_cpu_cooling{ + compatible = "sprd,sprd-cpu-cooling"; + id = <1>; + cluster = <1>; + max_freq = <1500000 1200000>; + max_core = <4 0>; + state_num = <2>; + }; + + i2c1: i2c@70600000{ + compatible = "sprd,i2c"; + interrupts = <0 12 0x0>; + reg = <0 0x70600000 0 0x1000>; + clock-names = "clk_i2c1"; + clocks = <&clk_i2c1>; + #address-cells = <1>; + #size-cells = <0>; + fairchild_fan53555@60{ + compatible = "fairchild,fairchild_fan53555"; + reg = <0x60>; + vddbigarm: vddbigarm { + regulator-name = "vddbigarm"; + regulator-default-microvolt = <1020000>;/*1050000*/ + regulator-step-microvolt = <10000>;/* 10 * 1000 uV */ + regulator-min-microvolt = <600000>;/* 600 * 1000 uV */ + regulator-max-microvolt = <1230000>;/*(600 + 10 * 0x3F) * 1000 uV*/ + }; + }; + }; + + i2c2: i2c@70700000{ + compatible = "sprd,i2c"; + interrupts = <0 13 0x0>; + reg = <0 0x70700000 0 0x1000>; + clock-names = "clk_i2c2"; + clocks = <&clk_i2c2>; + #address-cells = <1>; + #size-cells = <0>; + + lis3dh_acc@18{ + compatible = "ST,lis3dh_acc"; + reg = <0x18>; + poll_interval = <10>; + min_interval = <10>; + g_range = <0>; + axis_map_x = <1>; + axis_map_y = <0>; + axis_map_z = <2>; + negate_x = <0>; + negate_y = <1>; + negate_z = <0>; + }; + ltr_558als@23{ + compatible = "LITEON,ltr_558als"; + reg = <0x23>; + gpios = <&d_gpio_gpio 140 0>; + }; + epl259x_pls@49{ + compatible = "ELAN,epl259x_pls"; + reg = <0x49>; + gpios = <&d_gpio_gpio 140 0>; + }; + + }; + + i2c3: i2c@70800000{ + compatible = "sprd,i2c"; + interrupts = <0 14 0x0>; + reg = <0 0x70800000 0 0x1000>; + clock-names = "clk_i2c3"; + clocks = <&clk_i2c3>; + #address-cells = <1>; + #size-cells = <0>; + + focaltech_ts@38{ + compatible = "focaltech,focaltech_ts"; + reg = <0x38>; + gpios = <&d_gpio_gpio 145 0 + &d_gpio_gpio 144 0>; + vdd_name = "vdd18"; + virtualkeys = <580 1350 60 45 + 360 1350 60 45 + 160 1350 60 45>; + TP_MAX_X = <720>; + TP_MAX_Y = <1280>; + }; + msg2138_ts@26{ + compatible = "Mstar,msg2138_ts"; + reg = <0x26>; + gpios = <&d_gpio_gpio 145 0 + &d_gpio_gpio 144 0>; + vdd_name = "vdd28"; + virtualkeys = <256 1068 64 64 + 128 1068 64 64 + 192 1068 64 64>; + TP_MAX_X = <480>; + TP_MAX_Y = <800>; + }; + }; + + i2c4: i2c@70900000{ + compatible = "sprd,i2c"; + interrupts = <0 15 0x0>; + reg = <0 0x70900000 0 0x1000>; + clock-names = "clk_i2c4"; + clocks = <&clk_i2c4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi0: spi0@70a00000{ + compatible = "sprd,sprd-spi"; + interrupts = <0 7 0x0>; + reg = <0 0x70a00000 0 0x1000>; + clock-names = "clk_spi0"; + }; + + spi1: spi1@70b00000{ + compatible = "sprd,sprd-spi"; + interrupts = <0 8 0x0>; + reg = <0 0x70b00000 0 0x1000>; + clock-names = "clk_spi1"; + }; + + spi2: spi2@70c00000{ + compatible = "sprd,sprd-spi"; + interrupts = <0 9 0x0>; + reg = <0 0x70c00000 0 0x1000>; + clock-names = "clk_spi2"; + }; + + dma: dma-controller@20100000 { + compatible = "sprd,sharkl64-dma"; + #dma-cells = <1>; + #dma-channels = <64>; + sprd,aon-offset = <32>; + reg = <0 0x20100000 0 0x4000>, /* ap reg */ + <0 0x40100000 0 0x4000>; /* aon reg */ + interrupts = <0 50 0x0>, /* ap int */ + <0 70 0x0>; /* aon int */ + }; + + sprd-io-base { + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 1 0>; + ahb { + compatible = "sprd,ahb"; + reg = <0 0x20e00000 0 0x40000>; + }; + apbckg { + compatible = "sprd,apbckg"; + reg = <0 0x21500000 0 0x1000>; + }; + hwlock0 { + compatible = "sprd,hwlock0"; + reg = <0 0x20d00000 0 0x1000>; + }; + pub_apb { + compatible = "sprd,pub_apb"; + reg = <0 0x30020000 0 0x10000>; + }; + aon_apb { + compatible = "sprd,aon_apb"; + reg = <0 0x402e0000 0 0x40000>; + }; + pmu_apb { + compatible = "sprd,pmu_apb"; + reg = <0 0x402b0000 0 0x40000>; + }; + mm_ahb { + compatible = "sprd,mm_ahb"; + reg = <0 0x60d00000 0 0x10000>; + }; + mm_clk { + compatible = "sprd,mm_clk"; + reg = <0 0x60e00000 0 0x1000>; + }; + codecahb { + compatible = "sprd,codecahb"; + reg = <0 0x62000000 0 0x1000>; + }; + ap_ckg { + compatible = "sprd,ap_ckg"; + reg = <0 0x71200000 0 0x40000>; + }; + ap_apb { + compatible = "sprd,ap_apb"; + reg = <0 0x71300000 0 0x40000>; + }; + gpu_apb { + compatible = "sprd,gpu_apb"; + reg = <0 0x60100000 0 0x1000>; + }; + adi { + compatible = "sprd,adi"; + reg = <0 0x40030000 0 0x10000>; + }; + adi_slave { + compatible = "sprd,adi_slave"; + reg = <0 0x40038000 0 0x1000>; + }; + + mailbox { + compatible = "sprd,mailbox"; + reg = <0 0x400a0000 0 0x10000>; + }; + uart0 { + compatible = "sprd,uart0"; + reg = <0 0x70000000 0 0x1000>; + }; + uart1 { + compatible = "sprd,uart1"; + reg = <0 0x70100000 0 0x1000>; + }; + uart2 { + compatible = "sprd,uart2"; + reg = <0 0x70200000 0 0x1000>; + }; + uart3 { + compatible = "sprd,uart3"; + reg = <0 0x70300000 0 0x1000>; + }; + uart4 { + compatible = "sprd,uart4"; + reg = <0 0x70400000 0 0x1000>; + }; + axibm0 { + compatible = "sprd,axibm0"; + reg = <0 0x30040000 0 0x20000>; + interrupts = <0 86 0x0>; + }; + d_eic_gpio { + compatible = "sprd,d-eic-gpio"; + reg = <0 0x40210000 0 0x1000>; + }; + d_gpio_gpio { + compatible = "sprd,d-gpio-gpio"; + reg = <0 0x40280000 0 0x1000>; + }; + aon_dma { + compatible = "sprd,aon_dma"; + reg = <0 0x40100000 0 0x1000>; + interrupts = <0 50 0x0>; + }; + pwm { + compatible = "sprd,pwm"; + reg = <0 0x40260000 0 0x1000>; + }; + core { + compatible = "sprd,core"; + reg = <0 0x12000000 0 0x10000>; + }; + int { + compatible = "sprd,int"; + reg = <0 0x40200000 0 0x1000>; + }; + intc0 { + compatible = "sprd,intc0"; + reg = <0 0x71400000 0 0x1000>; + }; + intc1 { + compatible = "sprd,intc1"; + reg = <0 0x71500000 0 0x1000>; + }; + intc2 { + compatible = "sprd,intc2"; + reg = <0 0x71600000 0 0x1000>; + }; + intc3 { + compatible = "sprd,intc3"; + reg = <0 0x71700000 0 0x1000>; + }; + send_mbox { + compatible = "sprd,send_mbox"; + reg = <0 0x400a0000 0 0x1000>; + }; + recv_mbox { + compatible = "sprd,recv_mbox"; + reg = <0 0x400a8000 0 0x1000>; + }; + uidefuse { + compatible = "sprd,uidefuse"; + reg = <0 0x40240000 0 0x1000>; + }; + isp { + compatible = "sprd,isp"; + reg = <0 0x60a00000 0 0x8000>; + }; + csi2 { + compatible = "sprd,csi2"; + reg = <0 0x60c00000 0 0x1000>; + }; + ipi { + compatible = "sprd,ipi"; + reg = <0 0x402c0000 0 0x1000>; + }; + dcam { + compatible = "sprd,dcam"; + reg = <0 0x60800000 0 0x10000>; + }; + syscnt { + compatible = "sprd,syscnt"; + reg = <0 0x40230000 0 0x1000>; + }; + dma0 { + compatible = "sprd,dma0"; + reg = <0 0x20100000 0 0x4000>; + }; + pub { + compatible = "sprd,pub"; + reg = <0 0x30020000 0 0x10000>; + }; + pin { + compatible = "sprd,pin"; + reg = <0 0x402a0000 0 0x1000>; + }; + aonckg { + compatible = "sprd,aonckg"; + reg = <0 0x402d0000 0 0x1000>; + }; + lpddr2 { + compatible = "sprd,lpddr2"; + reg = <0 0x30000000 0 0x1000>; + }; + }; + + sprd_dcam { + compatible = "sprd,sprd_dcam"; + interrupts = <0 45 0>; + reg = <0 0x60800000 0 0x100000>; + clock-names = "clk_mm_i","clk_dcam"; + clocks = <&clk_mm>, <&clk_dcam>; + }; + + sprd_scale { + compatible = "sprd,sprd_scale"; + }; + + sprd_rotation { + compatible = "sprd,sprd_rotation"; + }; + + sprd_sensor { + compatible = "sprd,sprd_sensor"; + reg = <0 0x60c00000 0 0x100000>; + gpios = <&d_gpio_gpio 44 0 /*main reset*/ + &d_gpio_gpio 46 0 /*main powerdown*/ + &d_gpio_gpio 45 0 /*sub reset*/ + &d_gpio_gpio 47 0 + &d_gpio_gpio 0 0 /*main core voltage*/ + &d_gpio_gpio 0 0 + &d_gpio_gpio 0 0 + &d_gpio_gpio 0 0>; /*sub powerdown*/ + clock-names ="clk_mm_i","clk_sensor","clk_ccir","clk_dcam","clk_dcam_mipi"; + clocks = <&clk_mm>,<&clk_sensor>,<&clk_ccir>,<&clk_dcam>,<&clk_dcam_mipi>; + }; + + sprd_isp { + compatible = "sprd,sprd_isp"; + reg = <0 0x60a00000 0 0x100000>; + clock-names = "clk_mm_i","clk_isp"; + clocks = <&clk_mm>, <&clk_isp>; + }; + + sprd_dma_copy { + compatible = "sprd,sprd_dma_copy"; + }; + + fb0: fb@20800000 { + compatible = "sprd,sprdfb"; + reg = <0 0x20800000 0 0x1000>, + <0 0x21800000 0 0x1000>; + interrupts = <0 46 0x0>, + <0 48 0x0>, + <0 49 0x0>; + clock-names = "dispc_clk_parent", "dispc_dbi_clk_parent", "dispc_dpi_clk_parent", "dispc_emc_clk_parent", "dispc_clk", "dispc_dbi_clk", "dispc_dpi_clk", "dispc_emc_clk", "fb_spi_clock", "fb_spi_clock_parent"; + clocks = <&clk_256m>, <&clk_256m>, <&clk_384m>, <&clk_aon_apb>, <&clk_dispc0>, <&clk_dispc0_dbi>, <&clk_dispc0_dpi>, <&clk_disp_emc>, <&clk_spi2>, <&ext_26m>; + clock-src = <256000000 256000000 384000000>; + dpi_clk_div = <7>; + sprd,fb_use_reservemem; + sprd,fb_mem = <0x9ED74000 0xA8C000>; + }; + + gsp@20a00000 { + compatible = "sprd,gsp"; + reg = <0 0x20a00000 0 0x1000>; + interrupts = <0 51 0x0>; + clock-names = "clk_gsp0", "clk_gsp_emc", "clk_gsp_parent", "clk_aon_apb"; + clocks = <&clk_gsp0>, <&clk_gsp_emc>, <&clk_256m>, <&clk_aon_apb>; + gsp_mmu_ctrl_base = <0x20b08000>; + }; + + /*sharLT8 gspn initializer */ + gspn:gspn@0x20A00000 { + compatible = "sprd,gspn"; + reg = <0x71500000 0x1000>, // arm interrupt ctl reg + <0x20E00000 0x1000>, //gspn module enable ctl reg base + <0x20E00004 0x1000>, //gspn module reset ctl reg base + <0x20E0304C 0x1000>, //[0] gsp/gspn select reg base, 0:gsp; 1:gspn + <0x402e00fc 0x1000>; //[0] ap chip id reg addr + gspn0:gspn@0x20A00000 { + core_id = <0>; + gspn_en_rst_bit = <0x00000008>;//bit3 + mmu_en_rst_bit = <0x00000008>;//bit3 + auto_gate_bit = <0x00000100>;//bit8 + force_gate_bit = <0x00000200>;//bit9 + emc_en_bit = <0x00000008>;//bit3 + reg = <0x20A00000 0x1000>, //gspn module ctl reg + <0x20B10000 0x1000>, //iommu ctl reg,64MB,page size 4KB + <0x21500028 0x1000>, //gspn clock source select ctl reg base + <0x20E00010 0x1000>, //gspn clock auto-gate/force-gate ctl reg base + <0x20E00000 0x1000>; //gspn emc clock ctl reg base + interrupts = <0 51 0x0>; + clock-names = "clk_gsp", "clk_gsp_emc", "clk_gsp_parent", "clk_aon_apb"; + //clocks = <&clk_gsp>, <&clk_gsp_emc>, <&clk_256m>, <&clk_aon_apb>; + }; + }; + + sprd_fm: sprd_fm@40270000{ + compatible = "sprd,sprd_fm"; + reg = <0 0x40270000 0 0x1000>; + }; + + sipc: sipc@0x87800000 { + compatible = "sprd,sipc"; + reg = <0 0x87800000 0 0x5B0000>; /* <SMEM SIZE>*/ + //#interrupt-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + ranges =<0x09600000 0 0x89600000 0x4600000>, + <0x07800000 0 0x87800000 0x5B0000>, + <0x0dbff000 0 0x8dbff000 0x1000>; + sipc_lte@0x09600000 { + sprd,name = "sipc-lte"; + sprd,dst = <5>; + /* it's unnecessary to config IPI info upon mailbox arch */ + mailbox,core = <7>; + reg = <0x09600000 0x4600000> , /* <CP_start_addr size> */ + <0x07800000 0x5B0000>, /* <SMEM_phy_addr total_size> */ + <0x0dbff000 0x1000>; /* smsg ring buffer <base size> */ + }; + }; + + sctrl_pmic{ + compatible = "sprd,sctrl"; + sprd,name = "sctrl_pmic"; + sprd,dst = <6>; + sprd,channel= <1>; + sprd,ringnr = <1>; + /* it's unnecessary to config IPI info upon mailbox arch */ + mailbox,core = <1>; + sprd,ringbase = <0x5000b000>; /*SMSG ring mem base phy address*/ + sprd,size-rxbuf = <0x0400>; /* 2*1024*/ + sprd,size-txbuf = <0x0400>; /* 2*1024 */ + }; + + saudio_lte{ + compatible = "sprd,saudio"; + sprd,saudio-dst-id = <5>; /* SIPC_ID_LTE */ + sprd,ctrl_channel = <10>; /* SMSG_CH_VBC */ + sprd,playback_channel = <11>; /* SMSG_CH_PLAYBACK */ + sprd,capture_channel = <12>; /* SMSG_CH_CAPTURE */ + sprd,monitor_channel = <13>; /*SMSG_CH_MONITOR_AUDIO */ + sprd,saudio-names = "saudiolte"; + }; + + saudio_voip{ + compatible = "sprd,saudio"; + sprd,saudio-dst-id = <5>; /* SIPC_ID_LTE */ + sprd,ctrl_channel = <14>; /* SMSG_CH_CTRL_VOIP */ + sprd,playback_channel = <15>; /* SMSG_CH_PLAYBACK_VOIP */ + sprd,capture_channel = <16>; /* SMSG_CH_CAPTURE_VOIP */ + sprd,monitor_channel = <17>; /*SMSG_CH_MONITOR_VOIP */ + sprd,saudio-names = "saudiovoip"; + }; + + /* LTE modem virtual devices */ + spipe_lte { + compatible = "sprd,spipe"; + sprd,name = "spipe_lte"; + sprd,dst = <5>; + sprd,channel = <4>; + sprd,ringnr = <9>; + sprd,size-rxbuf = <0x1000>; /* 4*1024 */ + sprd,size-txbuf = <0x1000>; /* 4*1024 */ + }; + + slog_lte { + compatible = "sprd,spipe"; + sprd,name = "slog_lte"; + sprd,dst = <5>; + sprd,channel = <5>; + sprd,ringnr = <1>; + sprd,size-rxbuf = <0x40000>; /* 256*1024*/ + sprd,size-txbuf = <0x8000>; /* 32*1024 */ + }; + + sdiag_lte { + compatible = "sprd,spipe"; + sprd,name = "sdiag_lte"; + sprd,dst = <5>; + sprd,channel = <21>; + sprd,ringnr = <1>; + sprd,size-rxbuf = <0x40000>; /* 256*1024*/ + sprd,size-txbuf = <0x8000>; /* 32*1024 */ + }; + + stty_lte { + compatible = "sprd,spipe"; + sprd,name = "stty_lte"; + sprd,dst = <5>; + sprd,channel = <6>; + sprd,ringnr = <32>; + sprd,size-rxbuf = <0x0800>; /* 2*1024*/ + sprd,size-txbuf = <0x0800>; /* 2*1024 */ + }; + + seth0_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte0"; + sprd,dst = <5>; + sprd,channel = <7>; + sprd,blknum = <256>; + }; + + seth1_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte1"; + sprd,dst = <5>; + sprd,channel = <8>; + sprd,blknum = <256>; + }; + + seth2_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte2"; + sprd,dst = <5>; + sprd,channel = <9>; + sprd,blknum = <256>; + }; + + seth3_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte3"; + sprd,dst = <5>; + sprd,channel = <18>; + sprd,blknum = <256>; + }; + + seth4_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte4"; + sprd,dst = <5>; + sprd,channel = <19>; + sprd,blknum = <256>; + }; + + seth5_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte5"; + sprd,dst = <5>; + sprd,channel = <20>; + sprd,blknum = <256>; + }; + scproc_arm7: scproc@0x50800000 { + compatible = "sprd,scproc"; + sprd,name = "cppmic"; + sprd,ctrl-reg = <0x114 0xff 0xb0 0xff>; /* <shut_down deep_sleep reset get_status> */ + sprd,ctrl-mask = <0x01 0xfffffffe 0x100 0xf0000>; /* masks <> */ + sprd,iram-data = <0xe59f0000 0xe12fff10 0x0>; /* 3rd param equals modem_addr*/ + reg = <0 0x50800000 0 0x8000>, /* <CP_start_addr total_size> = <+128M 26M> */ + <0 0x50800000 0 0x0>, /* <iram1_base size> */ + <0 0x402e0000 0 0x400>, /* <aon_apb_base size> */ + <0 0x402b0000 0 0x100>, /* <pmu_base size> */ + <0 0x402b0000 0 0x100>, /* <pmu_base size> */ + <0 0x402b0000 0 0x100>; /* <pmu_base size> */ + #address-cells = <1>; + #size-cells = <1>; + /* segnr=1 */ + ranges = <0x0 0 0x50800000 0x8000>; + modem@0x0 { + cproc,name = "modem"; + reg = <0x0 0x8000>; /* <modem_addr size> */ + }; + }; + + scproc_cp1: scproc@0x89600000 { + compatible = "sprd,scproc"; + sprd,name = "cptl"; + sprd,ctrl-reg = <0x0c 0xff 0xb0 0x78>; /* <shut_down deep_sleep reset get_status> */ + sprd,ctrl-mask = <0x00300000 0x10000000 0x02 0x1>; /* masks <> */ + sprd,iram-data = <0xe59f0000 0xe12fff10 0x8ae00000>; /* 3rd param equals modem_addr*/ + reg = <0 0x89600000 0 0x5300000>, /* <CP_start_addr total_size> = <+128M 83M> */ + <0 0x50001000 0 0x0c>, /* <iram1_base size> */ + <0 0x402e0000 0 0x100>, /* <aon_apb_base size> */ + <0 0x402b0000 0 0x100>, /* <pmu_base size> */ + <0 0x402b0000 0 0x100>, /* <pmu_base size> */ + <0 0x402b0000 0 0x100>; /* <pmu_base size> */ + interrupts = <0 84 0x0>; /* cp1_wdg_int */ + #address-cells = <1>; + #size-cells = <1>; + /* segnr=4 */ + ranges = <0x1800000 0 0x8ae00000 0x02E00000>, + <0x0020000 0 0x89620000 0x002E0000>, + <0x0300000 0 0x89900000 0x1C0000>, + <0x4900000 0 0x8df00000 0xA00000>; + modem@0x1800000 { + cproc,name = "modem"; + reg = <0x1800000 0x02E00000>; /* <modem_addr size> */ + }; + dsp@0x20000 { + cproc,name = "tgdsp"; + reg = <0x20000 0x002e0000>; /* <dsp_addr size>*/ + }; + dsp@0x300000 { + cproc,name = "ldsp"; + reg = <0x300000 0x1c0000>; /* <dsp_addr size>*/ + }; + modem@0x4900000 { + cproc,name = "warm"; + reg = <0x4900000 0xA00000>; /* <modem_addr size>*/ + }; + }; + + itm_wlan{ + compatible = "sprd,itm_wlan"; + }; + + dmac: dmac@20100000 { + compatible = "sprd,sprd-dma"; + interrupts = <0 50 0x0>; + reg = <0 0x20100000 0 0x4000>; + }; + + gpu: gpu@60000000 { + compatible = "sprd,mali-midgard"; + reg = <0 0x60000000 0 0x4000>; + interrupts = <0 39 0x4>, <0 39 0x4>, <0 39 0x4>; + interrupt-names = "JOB", "MMU", "GPU"; + + clocks = <&clk_gpu_axi>,<&clk_gpu>,<&clk_153m6>, <&clk_192m>, <&clk_256m>, <&clk_307m2>, <&clk_384m>, <&clk_gpll>; + clock-names = "clk_gpu_axi","clk_gpu","clk_153m6","clk_192m","clk_256m","clk_307m2","clk_384m","clk_gpll"; + + freq-list-len = <4>; + freq-lists = <153600 2 1>, <256000 4 1>, <384000 6 1>, <512000 7 1>; + freq-default = <3>; + freq-9 = <3>; + freq-8 = <3>; + freq-7 = <1>; + freq-5 = <0>; + freq-range-max = <3>; + freq-range-min = <0>; + }; + + ion { + compatible = "sprd,ion-sprd"; + #address-cells = <1>; + #size-cells = <0>; + + sprd,ion-heap@1 { + reg = <1>; /* SYSTEM */ + reg-names = "ion_heap_system"; + sprd,ion-heap-type = <0>; /* SYSTEM */ + sprd,ion-heap-mem = <0x0 0x0>; + }; + + sprd,ion-heap@2 { + reg = <2>; /* MM */ + reg-names = "ion_heap_carveout_mm"; + sprd,ion-heap-type = <0>; /* carveout mm */ + sprd,ion-heap-mem = <0x9864F000 0x7100000>; + }; + + sprd,ion-heap@3 { + reg = <3>; /* OVERLAY */ + reg-names = "ion_heap_carveout_overlay"; + sprd,ion-heap-type = <2>; /* CARVEOUT */ + sprd,ion-heap-mem = <0x9F800000 0x800000>; /* 480*854*4*2, 1M alignment */ + }; + + sprd,ion-heap@4 { + reg = <4>; /* FB */ + reg-names = "ion_heap_carveout_fb"; + sprd,ion-heap-type = <2>; /* CARVEOUT */ + sprd,ion-heap-mem = <0x9ED74000 0xA8C000>; + }; + }; + + sprd_iommu0: sprd_iommu@20b00000 { + compatible = "sprd,sprd_iommu";//gsp + func-name = "sprd_iommu_gsp"; + reg = <0 0x10000000 0 0x2000000>, //iova + <0 0x20b00000 0 0x8000>, //pgt + <0 0x20b08000 0 0x8000>; //ctrl_reg + reg_name = "iova","pgt","ctrl_reg"; + clock-names = "clk_gsp_emc","clk_153m6","clk_gsp0"; + clocks = <&clk_gsp_emc>, <&clk_153m6>,<&clk_gsp0>; + status = "ok"; + }; + + sprd_iommu1: sprd_iommu@60f00000 { + compatible = "sprd,sprd_iommu";//mm + func-name = "sprd_iommu_mm"; + reg = <0 0x20000000 0 0x8000000>, //iova + <0 0x60f00000 0 0x20000>, //pgt + <0 0x60f20000 0 0x2000>; //ctrl_reg + reg_name = "iova","pgt","ctrl_reg"; + clock-names = "clk_mmu","clk_mm_i"; + clocks = <&clk_mmu>,<&clk_mm>; + status = "ok"; + }; + + sprd_vsp: sprd_vsp@60900000{ + compatible = "sprd,sprd_vsp"; + reg = <0 0x60900000 0 0xc000>; + interrupts = <0 43 0x0>; + clock-names = "clk_mm_i", "clk_vsp", "clk_parent_0", "clk_parent_1", "clk_parent_2", "clk_parent_3"; + clocks = <&clk_mm>, <&clk_vsp>, <&clk_307m2>, <&clk_256m>, <&clk_128m>, <&clk_96m>; + clock-parent-info = <2 4>; + version = <7>; + }; + + sprd_vpp@61000000{ + compatible = "sprd,sprd_vpp"; + reg = <0 0x61000000 0 0x4000>; + interrupts = <0 43 0x0>; + clock-names = "clk_mm_i","clk_vpp","clk_256m","clk_153m6","clk_128m","clk_96m"; + clocks = <&clk_mm>, <&clk_vpp>, <&clk_256m>, <&clk_153m6>, <&clk_128m>, <&clk_96m>; + clock-parent-info = <2 4>; + }; + + sprd_coda7l@62100000{ + compatible = "sprd,sprd_coda7l"; + reg = <0 0x62100000 0 0x4000>; + interrupts = <0 43 0x0>; + clock-names = "clk_mm_i","clk_coda7_axi","clk_coda7_cc","clk_coda7_apb", + "clk_192m","clk_153m6","clk_128m","clk_76m8", + "clk_128m","clk_96m","clk_76m8","ext_26m"; + clocks = <&clk_mm>, <&clk_coda7_axi>, <&clk_coda7_cc>, <&clk_coda7_apb>, + <&clk_192m>, <&clk_153m6>, <&clk_128m>, <&clk_76m8>, + <&clk_128m>, <&clk_96m>, <&clk_76m8>, <&ext_26m>; + clock-parent-info = <4 4>; + power-regs-info = <0x402b0044 0 0x402b00c8 0xf0000000>; + }; + + sprd_jpg { + compatible = "sprd,sprd_jpg"; + reg = <0 0x60b00000 0 0x8000>; + interrupts = <0 42 0x0>; + clock-names = "clk_mm_i","clk_jpg"; + clocks = <&clk_mm>, <&clk_jpg>; + }; + sprd_bm { + compatible = "sprd,sprd_bm"; + reg = <0 0x30040000 0 0xA0000 + 0 0x20F00000 0 0x300000>; + interrupts = <0 86 0x0>; + sprd,bm_status = <1>; + sprd,bm_count = <10 11>; + sprd,cpu_chn = <0 1>; + sprd,disp_chn = <1 1>; + sprd,gpu_chn = <2 1>; + sprd,ap_zip_chn = <3 1>; + sprd,mm_chn = <4 1>; + sprd,cp0_arm0_1_chn = <5 1>; + sprd,cp0_dsp_chn = <6 0>; + sprd,cp1_lte_chn = <7 1>; + sprd,cp1_dsp_chn = <8 1>; + sprd,cp1_arm_chn = <9 1>; + sprd,ap_dap_chn = <0 0>; + sprd,ap_cpu_chn = <0 1>; + sprd,ap_dma_r_chn = <0 2>; + sprd,ap_dma_w_chn = <0 3>; + sprd,ap_sdio_0_chn = <1 0>; + sprd,ap_sdio_1_chn = <1 1>; + sprd,ap_sdio_2_chn = <1 2>; + sprd,ap_emmc_chn = <1 3>; + sprd,ap_nandc_chn = <2 0>; + sprd,ap_otg_chn = <2 1>; + sprd,ap_hsic_chn = <2 2>; + }; + wdt@40290000 { + compatible = "sprd,sprd-wdt"; + reg = <0 0x40290000 0 0x1000>, + <0 0x40310000 0 0x1000>; + interrupts = <0 124 0x0>; + }; + sprd-marlin { + compatible = "sprd,marlin"; + gpios = <&d_gpio_gpio 97 0 /*marlin gpio0 */ + &d_gpio_gpio 132 0 /*marlin gpio1 */ + &d_gpio_gpio 133 0 /*marlin gpio2 */ + &d_gpio_gpio 94 0 /*marlin gpio3 */ + &d_gpio_gpio 130 0>; /*marlin reset*/ + cp-rfctl-offset = <0x244>; /*coex func. marlin gpio3*/ + vdd-download = "vddcon"; /*vdd 1.6v*/ + vdd-pa = "vddwifipa"; /*vdd 3.3v*/ + clk-name = "clk_aux0"; /*clk 32k*/ + sdhci-name = "sdio_wifi"; + }; + +}; + +&vbc_r2p0 { + status = "okay"; +}; + +&sprd_codec { + status = "okay"; + sprd,audio_power_ver = <4>; +}; + +&i2s0 { + sprd,config_type = "pcm"; + sprd,slave_timeout = <0xF11>; + sprd,_hw_port = <0>; + sprd,fs = <8000>; + sprd,bus_type = <1>; + sprd,rtx_mode = <3>; + sprd,byte_per_chan = <1>; + sprd,slave_mode = <0>; + sprd,lsb = <0>; + sprd,lrck = <0>; + sprd,low_for_left = <1>; + sprd,clk_inv = <0>; + sprd,pcm_short_frame = <1>; + sprd,pcm_slot = <0x1>; + sprd,pcm_cycle = <1>; + sprd,tx_watermark = <12>; + sprd,rx_watermark = <20>; + status = "okay"; +}; + +&i2s1 { + status = "okay"; +}; + +&i2s2 { + status = "okay"; +}; + +&i2s3 { + status = "okay"; +}; + +&i2s_sound { + sprd,i2s = <&i2s0>, <&i2s1>, <&i2s2>, <&i2s3>; +}; + +&sprd_battery { + gpios = <&a_eic_gpio 0 0 /* chg int */ + &a_eic_gpio 4 0 /* cv state */ + &a_eic_gpio 6 0 /* chg ovi */ + &a_eic_gpio 9 0>; /* battery detect */ + + chg-end-vol-h = <4375>; + chg-end-vol-pure = <4350>; + chg-end-vol-l = <4340>; + chg-bat-safety-vol = <4430>; + rechg-vol = <4260>; + + fgu-mode = <0>; + alm-soc = <5>; + alm-vol = <3500>; + soft-vbat-uvlo = <3100>; + rint = <200>; + cnom = <2100>; + rsense-real = <118>; + rsense-spec = <200>; + relax-current = <50>; + fgu-cal-ajust = <0>; + ocv-tab-size = <21>; + ocv-tab-vol = <4318 4254 4198 4145 4094 4052 3987 3955 3902 3865 3838 3817 3800 3785 3769 3752 3733 3706 3691 3588 3400>; + ocv-tab-cap = <100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0>; +}; diff --git a/arch/arm64/boot/dts/sprd_sp9838aea_fhd.dts b/arch/arm64/boot/dts/sprd_sp9838aea_fhd.dts new file mode 100644 index 00000000..55a1fea8 --- /dev/null +++ b/arch/arm64/boot/dts/sprd_sp9838aea_fhd.dts @@ -0,0 +1,1589 @@ +/* + * SPREADTRUM Ltd.clock-cells +sprd_rotation + * + * SharkLT8 5mod refphone DTS + */ + +/dts-v1/; + +/* memory reserved for SMEM */ +/memreserve/ 0x87800000 0x5B0000; /* Offset:120M, Size:5M+256K */ + +/* memory reserved for WARM modem */ +/memreserve/ 0x8DC00000 0xD00000; /* Offset:220M, Size:13M*/ + +/* memory reserved for LTE modem */ +/memreserve/ 0x89600000 0x4600000; /* Offset:150M, Size:70M*/ + +/* memory reserved for fb */ +/memreserve/ 0x9D845000 0x17BB000; /* 1920*1080*4*3, 4K alignment*/ + +/* memory reserved for ION */ +/memreserve/ 0x9F000000 0x1000000; /* 1920*1080*4*2, 1M alignment*/ + +/* memory reserved for smp */ +/memreserve/ 0x9F700000 0x1000; /* size 4K*/ + +/include/ "sc2723-regulators.dtsi" +/include/ "sprd-sound.dtsi" +/include/ "sprd-battery.dtsi" +/include/ "scx35lt8-clocks.dtsi" + +/ { + model = "scx35l64"; + compatible = "sprd,SharkLT8"; + sprd,sc-id = <8830 1 0x20000>; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { + bootargs = "earlyprintk=sprd_uart,0x70100000 loglevel=1 console=ttyS1,115200n8"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + core1 { + cpu = <&CPU5>; + }; + core2 { + cpu = <&CPU6>; + }; + core3 { + cpu = <&CPU7>; + }; + }; + }; + + CPU0: cpu@530000 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530000>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD>; + clocks = <&clk_little_mcu>; + cpu0-supply = <&vddarm>; + operating-points = < + /* kHz uV */ + 1000000 900000 + 800000 900000 + 750000 900000 + 600000 900000 + 533000 900000 + 400000 900000 + 200000 900000 + >; + }; + + CPU1: cpu@530001 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530001>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD>; + }; + + CPU2: cpu@530002 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530002>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD>; + }; + + CPU3: cpu@530003 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530003>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD>; + }; + + CPU4: cpu@530100 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530100>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD>; + clocks = <&clk_big_mcu>; + cpu0-supply = <&vddbigarm>; + operating-points = < + /* kHz uV */ + 1500000 1050000 + 1420000 1050000 + 1350000 1050000 + 1200000 900000 + 1100000 900000 + 1000000 900000 + 960000 900000 + >; + }; + + CPU5: cpu@530101 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530101>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD>; + }; + + CPU6: cpu@530102 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530102>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD>; + }; + + CPU7: cpu@530103 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530103>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD>; + }; + + idle-states{ + entry-method = "arm,psci"; + LIGHT_SLEEP: light_sleep { + compatible = "arm,idle-state"; + exit-latency-us = <100>; + min-residency-us = <500>; + entry-method-param = <0x00000001>; + }; + CORE_PD: core_pd { + compatible = "arm,idle-state"; + exit-latency-us = <1070>; + min-residency-us = <5000>; + entry-method-param = <0x00010002>; + }; + CLUSTER_PD: cluster_pd { + compatible = "arm,idle-state"; + exit-latency-us = <2000>; + min-residency-us = <8000>; + entry-method-param = <0x01010003>; + }; + TOP_PD: top_pd { + compatible = "arm,idle-state"; + exit-latency-us = <2000>; + min-residency-us = <5000>; + entry-method-param = <0x01010004>; + }; + DEEP_SLEEP: deep_sleep { + compatible = "arm,idle-state"; + exit-latency-us = <4100>; + min-residency-us = <6500>; + entry-method-param = <0x01010005>; + }; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0 0x80000000 0 0x40000000>; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + lcd0 = &fb0; + hwspinlock0 = &hwspinlock0; + hwspinlock1 = &hwspinlock1; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 92 4>, + <0 93 4>, + <0 94 4>, + <0 95 4>; + }; + + psci { + compatible = "arm,psci"; + method = "smc"; + cpu_on = <0xc4000003>; + cpu_off = <0x84000002>; + cpu_suspend = <0xc4000001>; + }; + + gic: interrupt-controller@12001000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0x12001000 0 0x1000>, + <0 0x12002000 0 0x1000>; + }; + + intc:interrupt-controller@71400000 { + compatible = "sprd,intc"; + #interrupt-cells = <0>; + interrupt-controller; + reg = <0 0x71400000 0 0x1000>, + <0 0x71500000 0 0x1000>, + <0 0x71600000 0 0x1000>, + <0 0x71700000 0 0x1000>, + <0 0x40200000 0 0x1000>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, + <1 14 0xff01>, + <1 11 0xff01>, + <1 10 0xff01>; + clock-frequency = <26000000>; + }; + + sprd_timer { + compatible = "sprd,sharkl64-timer"; + reg = <0 0x40050000 0 0x20>; /*aon GPTIMER0 */ + interrupts = <0 28 0x0>; + clock-frequency = <32768>; + }; + + sprd_ap_system_timer { + reg = <0 0x40230000 0 0x20>; + interrupts = <0 31 0x0>; + }; + + clock: clockdevice { + compatible = "sprd,scx35l64-clocks"; + #clock-cells = <1>; + }; + + d_eic_gpio: gpio@40210000 { + compatible = "sprd,d-eic-gpio"; + reg = <0 0x40210000 0 0x1000>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-cells = <2>; + gpiobase = <288>; + ngpios = <16>; + interrupts = <0 37 0x0>; + }; + + d_gpio_gpio: gpio@40280000 { + compatible = "sprd,d-gpio-gpio"; + reg = <0 0x40280000 0 0x1000>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-cells = <2>; + gpiobase = <0>; + ngpios = <256>; + interrupts = <0 35 0x0>; + }; + + uart0: uart@70000000 { + compatible = "sprd,serial"; + interrupts = <0 2 0xf04>; + reg = <0 0x70000000 0 0x1000>; + clock-names = "clk_uart0"; + clocks = <&clock 60>; + sprdclk = <48000000>; + sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP"; + + }; + + uart1: uart@70100000 { + compatible = "sprd,serial"; + interrupts = <0 3 0xf04>; + reg = <0 0x70100000 0 0x1000>; + clock-names = "clk_uart1"; + clocks = <&clock 61>; + sprdclk = <26000000>; + sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP"; + + }; + + uart2: uart@70200000 { + compatible = "sprd,serial"; + interrupts = <0 4 0xf04>; + reg = <0 0x70200000 0 0x1000>; + clock-names = "clk_uart2"; + clocks = <&clock 62>; + sprdclk = <26000000>; + sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP"; + }; + + uart3: uart@70300000 { + compatible = "sprd,serial"; + interrupts = <0 5 0xf04>; + reg = <0 0x70300000 0 0x1000>; + clock-names = "clk_uart3"; + clocks = <&clock 63>; + sprdclk = <26000000>; + sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP"; + }; + + hwspinlock0: hwspinlock0@20c00000{ + compatible = "sprd,sprd-hwspinlock"; + reg = <0 0x20c00000 0 0x1000>; + }; + + hwspinlock1: hwspinlock1@40060000{ + compatible = "sprd,sprd-hwspinlock"; + reg = <0 0x40060000 0 0x1000>; + status = "ok"; + }; + + watchdog { + compatible = "sprd,watchdog"; + reg = <0 0X40290000 0 0x1000>; + }; + + pinctrl { + compatible = "sprd,pinctrl"; + reg = <0 0x402a0000 0 0x1000>; + pwr_domain = "vdd28", + "vdd18", + "vddsim0", + "vddsim1", + "vddsim2", + "vddsdio", + "vdd18"; + ctrl_desc = <0x10 0 1 + 0x10 1 1 + 0x10 2 1 + 0x10 3 1 + 0x10 4 1 + 0x10 5 1 + 0x10 6 1>; + }; + + sdios{ + #address-cells = <2>; + #size-cells = <2>; + ranges; + sdio3: sdio@20600000{ + compatible = "sprd,sdhost-3.0"; + reg = <0 0x20600000 0 0x1000>; + interrupts = <0 60 0x0>; + sprd,name = "sdio_emmc"; + /*detect_gpio = <-1>; */ + SD_Pwr_Name = "vddemmccore"; + _1_8V_signal_Name = "vddgen0"; + signal_default_Voltage = <1800000>; + ocr_avail = <0x00040000>; + clocks = <&clk_emmc>, <&clk_192m>; + base_clk = <192000000>; + caps = <0xC00F8D47>; + caps2 = <0x202>; + pm_caps = <0x4>; + writeDelay = <0x3E>; + readPosDelay = <0xA>; + readNegDelay = <0xA>; + }; + + sdio0: sdio@20300000{ + compatible = "sprd,sdhost-3.0"; + reg = <0 0x20300000 0 0x1000>; + interrupts = <0 57 0x0>; + sprd,name = "sdio_sd"; + detect_gpio = <141>; + SD_Pwr_Name = "vddsdcore"; + _1_8V_signal_Name = "vddsdio"; + signal_default_Voltage = <3000000>; + ocr_avail = <0x00040000>; + clocks = <&clk_sdio0>, <&clk_192m>; + base_clk = <192000000>; + caps = <0xC0020407>; + caps2 = <0x200>; + pm_caps = <0x4>; + writeDelay = <0x3>; + readPosDelay = <0x3>; + readNegDelay = <0x3>; + }; + + + sdio1: sdio@20400000{ + compatible = "sprd,sdhost-3.0"; + reg = <0 0x20400000 0 0x1000>; + interrupts = <0 58 0x0>; + sprd,name = "sdio_wifi"; + /* detect_gpio = <-1>; */ + /* SD_Pwr_Name = "vddsdcore"; */ + /* _1_8V_signal_Name = "vddsdio";*/ + /* signal_default_Voltage = <3000000>; */ + ocr_avail = <0x00360080>; + clocks = <&clk_sdio1>, <&clk_76m8>; + base_clk = <76000000>; + caps = <0xC00FA407>; + caps2 = <0x0>; + pm_caps = <0x5>; + writeDelay = <0x03>; + readPosDelay = <0x03>; + readNegDelay = <0x03>; + }; + }; + + adic:adic { + compatible = "sprd,adi"; + reg = <0 0x40030000 0 0x10000>; + }; + + adi: adi_bus { + compatible = "sprd,adi-bus"; + interrupts = <0 38 0x0>; + reg = <0 0x40038000 0 0x1000>; + interrupt-controller; + sprd,irqnums = <11>; + #interrupt-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x100 0 0x40038100 0x80>, + <0x440 0 0x40038440 0x40>, + <0x800 0 0x40038800 0xff>; + + keyboard_backlight { + compatible = "sprd,keyboard-backlight"; + }; + + sprd_kpled_2723 { + compatible = "sprd,sprd-kpled-2723"; + brightness_max = <255>; + brightness_min = <0>; + run_mode = <1>; + }; + + leds_sprd_bltc_rgb { + compatible = "sprd,sprd-leds-bltc-rgb"; + reg = <0x440 0x40>, + <0x800 0xff>; + }; + + a_eic_gpio: gpio@100{ + compatible = "sprd,a-eic-gpio"; + reg = <0x100 0x80>; /* adi reg */ + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-cells = <2>; + gpiobase = <304>; + ngpios = <16>; + interrupt-parent = <&adi>; + interrupts = <5 0x0>; /* ext irq 5 */ + }; + sprd_eic_keys { + compatible = "sprd,sprd-eic-keys"; + input-name = "sprd-eic-keys"; + key_power { + label = "Power Key"; + linux,code = <116>; + gpios = <&a_eic_gpio 2 0>; + debounce-interval = <2>; + gpio-key,wakeup; + }; + key_volumeup { + label = "Volumeup Key"; + linux,code = <115>; + gpios = <&a_eic_gpio 10 0>; + debounce-interval = <2>; + gpio-key,wakeup; + }; + }; + + headset_sprd_sc2723 { + compatible = "sprd,headset_sprd_sc2723"; + gpio_switch = <0>; + gpio_detect = <312>; + gpio_button = <307>; + irq_trigger_level_detect = <1>; + irq_trigger_level_button = <1>; + adc_threshold_3pole_detect = <2650>; + adc_threshold_4pole_detect = <2651>; + irq_threshold_buttont = <1>; + voltage_headmicbias = <3000000>; + nbuttons = <3>; + headset_buttons_media { + adc_min = <0>; + adc_max = <430>; + code = <226>; + type = <0>; + }; + + headset_buttons_up { + adc_min = <431>; + adc_max = <860>; + code = <115>; + type = <0>; + }; + headset_buttons_down { + adc_min = <861>; + adc_max =<1900>; + code = <114>; + type = <0>; + }; + }; + + rtc@80{ + compatible = "sprd,rtc"; + reg = <0X80 0x80>; + interrupt-parent = <&adi>; + interrupts = <2 0x0>; + }; + }; + + sprd_pwm_bl { + compatible = "sprd,sprd_pwm_bl"; + brightness_max = <255>; + brightness_min = <0>; + pwm_index = <2>; + gpio_ctrl_pin = <0>; + gpio_active_level = <0>; + reg =<0 0x40260000 0 0xf>; + }; + + gpio_keys { + compatible = "gpio-keys"; + input-name = "sprd-gpio-keys"; + key_volumedown { + label = "Volumedown Key"; + linux,code = <114>; + gpios = <&d_gpio_gpio 124 1>; + debounce-interval = <2>; + gpio-key,wakeup; + }; +/* + key_volumeup { + label = "Volumeup Key"; + linux,code = <115>; + gpios = <&d_gpio_gpio 125 1>; + debounce-interval = <2>; + gpio-key,wakeup; + }; +*/ + key_camerafocus { + label = "Camerafocus Key"; + linux,code = <0x210>; + gpios = <&d_gpio_gpio 121 0>; + debounce-interval = <2>; + gpio-key,wakeup; + }; + key_camera { + label = "Camera Key"; + linux,code = <212>; + gpios = <&d_gpio_gpio 122 0>; + debounce-interval = <2>; + gpio-key,wakeup; + }; + }; + + sprd_backlight { + compatible = "sprd,sprd_backlight"; + start = <3>; + end = <3>; + flags = <0x100>; + }; + + rfkill { + compatible = "broadcom,rfkill"; + gpios = <&d_gpio_gpio 131 0 /* power */ + &d_gpio_gpio 122 0>; /* reset */ + }; + bluesleep { + compatible = "broadcom,bluesleep"; + bt-wake-gpio = <&d_gpio_gpio 132 0>; + host-wake-gpio = <&d_gpio_gpio 133 0>; + }; + + usb: usb@20200000{ + compatible = "sprd,usb"; + interrupts = <0 55 0x0>; + ngpios = <1>; + gpios = <&a_eic_gpio 0 0>; + reg = <0 0x20200000 0 0x1000>; + tune_value = <0x0005af33>; + usb-supply = <&vddusb>; + #address-cells = <1>; + #size-cells = <0>; + }; + sprd_thermal: thermal@402F0000{ + compatible = "sprd,sprd-thermal"; + id = <0>; + interrupts = <0 26 0x0>; + reg = <0 0x402F0000 0 0x1000>; + trip_points_active = <65 69 95 110>; + trip_points_lowoff = <0 57 60 80>; + trip_points_critical = <100>; + trip_num = <5>; + cool_num = <2>; + cooling-names = "thermal-cpufreq-0","thermal-cpufreq-1"; + }; + sprd_thermal1:thermal1@402F0000 { + compatible = "sprd,sprd-thermal"; + id = <1>; + interrupts = <0 26 0x0>; + reg = <0 0x402F0000 0 0x1000>; + trip_points_active = <100>; + trip_points_lowoff = <90>; + trip_points_critical = <100>; + trip_num = <2>; + }; + sprd_thermal2: thermal@40038280{ + compatible = "sprd,sprd-thermal"; + id = <2>; + interrupt-parent = <&adi>; + interrupts = <9 0x0>; + reg = <0 0x40038280 0 0x1000>; + trip_points_active = <110>; + trip_points_lowoff = <90>; + trip_points_critical = <110>; + trip_num = <2>; + }; + sprd_board_thermal: board-thermal{ + compatible = "sprd,board-thermal"; + id = <3>; + trip_points_active = <100>; + trip_points_lowoff = <90>; + trip_points_critical = <100>; + trip_num = <2>; + temp_inteval=<2>; + temp-support = <1>; + temp-adc-ch = <2>; + temp-adc-scale = <1>; + temp-adc-sample-cnt = <15>; + temp-table-mode = <1>; + temp-tab-size = <16>; + temp-tab-val = <1122 1094 1049 983 892 779 + 654 528 413 316 238 178 + 133 100 75 57>; + temp-tab-temp = <965 975 985 995 1005 1015 /* temperature + 1000,750 = 1000 + (-250)*/ + 1025 1035 1045 1055 1065 1075 + 1085 1095 1105 1115>; + + }; + adc: adc@40038300{ + compatible = "sprd,sprd-adc"; + reg = <0x40038300 0x1000>; + }; + i2c0: i2c@70500000{ + compatible = "sprd,i2c"; + interrupts = <0 11 0x0>; + reg = <0 0x70500000 0 0x1000>; + clock-names = "clk_i2c0"; + clocks = <&clk_i2c0>; + #address-cells = <1>; + #size-cells = <0>; + sensor_main@0x3c { + compatible = "sprd,sensor_main"; + reg = <0x3c>; + }; + sensor_sub@0x21 { + compatible = "sprd,sensor_sub"; + reg = <0x21>; + }; + }; + little_cpu_cooling{ + compatible = "sprd,sprd-cpu-cooling"; + id = <0>; + cluster = <0>; + max_freq = <1000000 1000000>; + max_core = <4 1>; + state_num = <2>; + }; + big_cpu_cooling{ + compatible = "sprd,sprd-cpu-cooling"; + id = <1>; + cluster = <1>; + max_freq = <1500000 1200000>; + max_core = <4 0>; + state_num = <2>; + }; + + i2c1: i2c@70600000{ + compatible = "sprd,i2c"; + interrupts = <0 12 0x0>; + reg = <0 0x70600000 0 0x1000>; + clock-names = "clk_i2c1"; + clocks = <&clk_i2c1>; + #address-cells = <1>; + #size-cells = <0>; + fairchild_fan53555@60{ + compatible = "fairchild,fairchild_fan53555"; + reg = <0x60>; + vddbigarm: vddbigarm { + regulator-name = "vddbigarm"; + regulator-default-microvolt = <1020000>;/*1050000*/ + regulator-step-microvolt = <10000>;/* 10 * 1000 uV */ + regulator-min-microvolt = <600000>;/* 600 * 1000 uV */ + regulator-max-microvolt = <1230000>;/*(600 + 10 * 0x3F) * 1000 uV*/ + }; + }; + }; + + i2c2: i2c@70700000{ + compatible = "sprd,i2c"; + interrupts = <0 13 0x0>; + reg = <0 0x70700000 0 0x1000>; + clock-names = "clk_i2c2"; + clocks = <&clk_i2c2>; + #address-cells = <1>; + #size-cells = <0>; + + lis3dh_acc@18{ + compatible = "ST,lis3dh_acc"; + reg = <0x18>; + poll_interval = <10>; + min_interval = <10>; + g_range = <0>; + axis_map_x = <1>; + axis_map_y = <0>; + axis_map_z = <2>; + negate_x = <0>; + negate_y = <1>; + negate_z = <0>; + }; + ltr_558als@23{ + compatible = "LITEON,ltr_558als"; + reg = <0x23>; + gpios = <&d_gpio_gpio 140 0>; + }; + epl259x_pls@49{ + compatible = "ELAN,epl259x_pls"; + reg = <0x49>; + gpios = <&d_gpio_gpio 140 0>; + }; + + }; + + i2c3: i2c@70800000{ + compatible = "sprd,i2c"; + interrupts = <0 14 0x0>; + reg = <0 0x70800000 0 0x1000>; + clock-names = "clk_i2c3"; + clocks = <&clk_i2c3>; + #address-cells = <1>; + #size-cells = <0>; + + focaltech_ts@38{ + compatible = "focaltech,focaltech_ts"; + reg = <0x38>; + gpios = <&d_gpio_gpio 145 0 + &d_gpio_gpio 144 0>; + vdd_name = "vdd18"; + virtualkeys = <580 1350 60 45 + 360 1350 60 45 + 160 1350 60 45>; + TP_MAX_X = <720>; + TP_MAX_Y = <1280>; + }; + msg2138_ts@26{ + compatible = "Mstar,msg2138_ts"; + reg = <0x26>; + gpios = <&d_gpio_gpio 145 0 + &d_gpio_gpio 144 0>; + vdd_name = "vdd28"; + virtualkeys = <256 1068 64 64 + 128 1068 64 64 + 192 1068 64 64>; + TP_MAX_X = <480>; + TP_MAX_Y = <800>; + }; + }; + + i2c4: i2c@70900000{ + compatible = "sprd,i2c"; + interrupts = <0 15 0x0>; + reg = <0 0x70900000 0 0x1000>; + clock-names = "clk_i2c4"; + clocks = <&clk_i2c4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi0: spi0@70a00000{ + compatible = "sprd,sprd-spi"; + interrupts = <0 7 0x0>; + reg = <0 0x70a00000 0 0x1000>; + clock-names = "clk_spi0"; + }; + + spi1: spi1@70b00000{ + compatible = "sprd,sprd-spi"; + interrupts = <0 8 0x0>; + reg = <0 0x70b00000 0 0x1000>; + clock-names = "clk_spi1"; + }; + + spi2: spi2@70c00000{ + compatible = "sprd,sprd-spi"; + interrupts = <0 9 0x0>; + reg = <0 0x70c00000 0 0x1000>; + clock-names = "clk_spi2"; + }; + + dma: dma-controller@20100000 { + compatible = "sprd,sharkl64-dma"; + #dma-cells = <1>; + #dma-channels = <64>; + sprd,aon-offset = <32>; + reg = <0 0x20100000 0 0x4000>, /* ap reg */ + <0 0x40100000 0 0x4000>; /* aon reg */ + interrupts = <0 50 0x0>, /* ap int */ + <0 70 0x0>; /* aon int */ + }; + + sprd-io-base { + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 1 0>; + ahb { + compatible = "sprd,ahb"; + reg = <0 0x20e00000 0 0x40000>; + }; + apbckg { + compatible = "sprd,apbckg"; + reg = <0 0x21500000 0 0x1000>; + }; + hwlock0 { + compatible = "sprd,hwlock0"; + reg = <0 0x20d00000 0 0x1000>; + }; + pub_apb { + compatible = "sprd,pub_apb"; + reg = <0 0x30020000 0 0x10000>; + }; + aon_apb { + compatible = "sprd,aon_apb"; + reg = <0 0x402e0000 0 0x40000>; + }; + pmu_apb { + compatible = "sprd,pmu_apb"; + reg = <0 0x402b0000 0 0x40000>; + }; + mm_ahb { + compatible = "sprd,mm_ahb"; + reg = <0 0x60d00000 0 0x10000>; + }; + mm_clk { + compatible = "sprd,mm_clk"; + reg = <0 0x60e00000 0 0x1000>; + }; + codecahb { + compatible = "sprd,codecahb"; + reg = <0 0x62000000 0 0x1000>; + }; + ap_ckg { + compatible = "sprd,ap_ckg"; + reg = <0 0x71200000 0 0x40000>; + }; + ap_apb { + compatible = "sprd,ap_apb"; + reg = <0 0x71300000 0 0x40000>; + }; + gpu_apb { + compatible = "sprd,gpu_apb"; + reg = <0 0x60100000 0 0x1000>; + }; + adi { + compatible = "sprd,adi"; + reg = <0 0x40030000 0 0x10000>; + }; + adi_slave { + compatible = "sprd,adi_slave"; + reg = <0 0x40038000 0 0x1000>; + }; + + mailbox { + compatible = "sprd,mailbox"; + reg = <0 0x400a0000 0 0x10000>; + }; + uart0 { + compatible = "sprd,uart0"; + reg = <0 0x70000000 0 0x1000>; + }; + uart1 { + compatible = "sprd,uart1"; + reg = <0 0x70100000 0 0x1000>; + }; + uart2 { + compatible = "sprd,uart2"; + reg = <0 0x70200000 0 0x1000>; + }; + uart3 { + compatible = "sprd,uart3"; + reg = <0 0x70300000 0 0x1000>; + }; + uart4 { + compatible = "sprd,uart4"; + reg = <0 0x70400000 0 0x1000>; + }; + axibm0 { + compatible = "sprd,axibm0"; + reg = <0 0x30040000 0 0x20000>; + interrupts = <0 86 0x0>; + }; + d_eic_gpio { + compatible = "sprd,d-eic-gpio"; + reg = <0 0x40210000 0 0x1000>; + }; + d_gpio_gpio { + compatible = "sprd,d-gpio-gpio"; + reg = <0 0x40280000 0 0x1000>; + }; + aon_dma { + compatible = "sprd,aon_dma"; + reg = <0 0x40100000 0 0x1000>; + interrupts = <0 50 0x0>; + }; + pwm { + compatible = "sprd,pwm"; + reg = <0 0x40260000 0 0x1000>; + }; + core { + compatible = "sprd,core"; + reg = <0 0x12000000 0 0x10000>; + }; + int { + compatible = "sprd,int"; + reg = <0 0x40200000 0 0x1000>; + }; + intc0 { + compatible = "sprd,intc0"; + reg = <0 0x71400000 0 0x1000>; + }; + intc1 { + compatible = "sprd,intc1"; + reg = <0 0x71500000 0 0x1000>; + }; + intc2 { + compatible = "sprd,intc2"; + reg = <0 0x71600000 0 0x1000>; + }; + intc3 { + compatible = "sprd,intc3"; + reg = <0 0x71700000 0 0x1000>; + }; + send_mbox { + compatible = "sprd,send_mbox"; + reg = <0 0x400a0000 0 0x1000>; + }; + recv_mbox { + compatible = "sprd,recv_mbox"; + reg = <0 0x400a8000 0 0x1000>; + }; + uidefuse { + compatible = "sprd,uidefuse"; + reg = <0 0x40240000 0 0x1000>; + }; + isp { + compatible = "sprd,isp"; + reg = <0 0x60a00000 0 0x8000>; + }; + csi2 { + compatible = "sprd,csi2"; + reg = <0 0x60c00000 0 0x1000>; + }; + ipi { + compatible = "sprd,ipi"; + reg = <0 0x402c0000 0 0x1000>; + }; + dcam { + compatible = "sprd,dcam"; + reg = <0 0x60800000 0 0x10000>; + }; + syscnt { + compatible = "sprd,syscnt"; + reg = <0 0x40230000 0 0x1000>; + }; + dma0 { + compatible = "sprd,dma0"; + reg = <0 0x20100000 0 0x4000>; + }; + pub { + compatible = "sprd,pub"; + reg = <0 0x30020000 0 0x10000>; + }; + pin { + compatible = "sprd,pin"; + reg = <0 0x402a0000 0 0x1000>; + }; + aonckg { + compatible = "sprd,aonckg"; + reg = <0 0x402d0000 0 0x1000>; + }; + lpddr2 { + compatible = "sprd,lpddr2"; + reg = <0 0x30000000 0 0x1000>; + }; + }; + + sprd_dcam { + compatible = "sprd,sprd_dcam"; + interrupts = <0 45 0>; + reg = <0 0x60800000 0 0x100000>; + clock-names = "clk_mm_i","clk_dcam"; + clocks = <&clk_mm>, <&clk_dcam>; + }; + + sprd_scale { + compatible = "sprd,sprd_scale"; + }; + + sprd_rotation { + compatible = "sprd,sprd_rotation"; + }; + + sprd_sensor { + compatible = "sprd,sprd_sensor"; + reg = <0 0x60c00000 0 0x100000>; + gpios = <&d_gpio_gpio 44 0 /*main reset*/ + &d_gpio_gpio 46 0 /*main powerdown*/ + &d_gpio_gpio 45 0 /*sub reset*/ + &d_gpio_gpio 47 0 + &d_gpio_gpio 0 0 /*main core voltage*/ + &d_gpio_gpio 0 0 + &d_gpio_gpio 0 0 + &d_gpio_gpio 0 0>; /*sub powerdown*/ + clock-names ="clk_mm_i","clk_sensor","clk_ccir","clk_dcam","clk_dcam_mipi"; + clocks = <&clk_mm>,<&clk_sensor>,<&clk_ccir>,<&clk_dcam>,<&clk_dcam_mipi>; + }; + + sprd_isp { + compatible = "sprd,sprd_isp"; + reg = <0 0x60a00000 0 0x100000>; + clock-names = "clk_mm_i","clk_isp"; + clocks = <&clk_mm>, <&clk_isp>; + }; + + sprd_dma_copy { + compatible = "sprd,sprd_dma_copy"; + }; + + fb0: fb@20800000 { + compatible = "sprd,sprdfb"; + reg = <0 0x20800000 0 0x1000>, + <0 0x21800000 0 0x1000>; + interrupts = <0 46 0x0>, + <0 48 0x0>, + <0 49 0x0>; + clock-names = "dispc_clk_parent", "dispc_dbi_clk_parent", "dispc_dpi_clk_parent", "dispc_emc_clk_parent", "dispc_clk", "dispc_dbi_clk", "dispc_dpi_clk", "dispc_emc_clk", "fb_spi_clock", "fb_spi_clock_parent"; + clocks = <&clk_256m>, <&clk_256m>, <&clk_384m>, <&clk_aon_apb>, <&clk_dispc0>, <&clk_dispc0_dbi>, <&clk_dispc0_dpi>, <&clk_disp_emc>, <&clk_spi2>, <&ext_26m>; + clock-src = <256000000 256000000 384000000>; + dpi_clk_div = <7>; + sprd,fb_use_reservemem; + sprd,fb_mem = <0x9D845000 0x17BB000>; + }; + + gsp@20a00000 { + compatible = "sprd,gsp"; + reg = <0 0x20a00000 0 0x1000>; + interrupts = <0 51 0x0>; + clock-names = "clk_gsp0", "clk_gsp_emc", "clk_gsp_parent", "clk_aon_apb"; + clocks = <&clk_gsp0>, <&clk_gsp_emc>, <&clk_256m>, <&clk_aon_apb>; + gsp_mmu_ctrl_base = <0x20b08000>; + }; + + /*sharLT8 gspn initializer */ + gspn:gspn@0x20A00000 { + compatible = "sprd,gspn"; + reg = <0x71500000 0x1000>, // arm interrupt ctl reg + <0x20E00000 0x1000>, //gspn module enable ctl reg base + <0x20E00004 0x1000>, //gspn module reset ctl reg base + <0x20E0304C 0x1000>, //[0] gsp/gspn select reg base, 0:gsp; 1:gspn + <0x402e00fc 0x1000>; //[0] ap chip id reg addr + gspn0:gspn@0x20A00000 { + core_id = <0>; + gspn_en_rst_bit = <0x00000008>;//bit3 + mmu_en_rst_bit = <0x00000008>;//bit3 + auto_gate_bit = <0x00000100>;//bit8 + force_gate_bit = <0x00000200>;//bit9 + emc_en_bit = <0x00000008>;//bit3 + reg = <0x20A00000 0x1000>, //gspn module ctl reg + <0x20B10000 0x1000>, //iommu ctl reg,64MB,page size 4KB + <0x21500028 0x1000>, //gspn clock source select ctl reg base + <0x20E00010 0x1000>, //gspn clock auto-gate/force-gate ctl reg base + <0x20E00000 0x1000>; //gspn emc clock ctl reg base + interrupts = <0 51 0x0>; + clock-names = "clk_gsp", "clk_gsp_emc", "clk_gsp_parent", "clk_aon_apb"; + //clocks = <&clk_gsp>, <&clk_gsp_emc>, <&clk_256m>, <&clk_aon_apb>; + }; + }; + + sprd_fm: sprd_fm@40270000{ + compatible = "sprd,sprd_fm"; + reg = <0 0x40270000 0 0x1000>; + }; + + sipc: sipc@0x87800000 { + compatible = "sprd,sipc"; + reg = <0 0x87800000 0 0x5B0000>; /* <SMEM SIZE>*/ + //#interrupt-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + ranges =<0x09600000 0 0x89600000 0x4600000>, + <0x07800000 0 0x87800000 0x5B0000>, + <0x0dbff000 0 0x8dbff000 0x1000>; + sipc_lte@0x09600000 { + sprd,name = "sipc-lte"; + sprd,dst = <5>; + /* it's unnecessary to config IPI info upon mailbox arch */ + mailbox,core = <7>; + reg = <0x09600000 0x4600000> , /* <CP_start_addr size> */ + <0x07800000 0x5B0000>, /* <SMEM_phy_addr total_size> */ + <0x0dbff000 0x1000>; /* smsg ring buffer <base size> */ + }; + }; + + sctrl_pmic{ + compatible = "sprd,sctrl"; + sprd,name = "sctrl_pmic"; + sprd,dst = <6>; + sprd,channel= <1>; + sprd,ringnr = <1>; + /* it's unnecessary to config IPI info upon mailbox arch */ + mailbox,core = <1>; + sprd,ringbase = <0x5000b000>; /*SMSG ring mem base phy address*/ + sprd,size-rxbuf = <0x0400>; /* 2*1024*/ + sprd,size-txbuf = <0x0400>; /* 2*1024 */ + }; + + saudio_lte{ + compatible = "sprd,saudio"; + sprd,saudio-dst-id = <5>; /* SIPC_ID_LTE */ + sprd,ctrl_channel = <10>; /* SMSG_CH_VBC */ + sprd,playback_channel = <11>; /* SMSG_CH_PLAYBACK */ + sprd,capture_channel = <12>; /* SMSG_CH_CAPTURE */ + sprd,monitor_channel = <13>; /*SMSG_CH_MONITOR_AUDIO */ + sprd,saudio-names = "saudiolte"; + }; + + saudio_voip{ + compatible = "sprd,saudio"; + sprd,saudio-dst-id = <5>; /* SIPC_ID_LTE */ + sprd,ctrl_channel = <14>; /* SMSG_CH_CTRL_VOIP */ + sprd,playback_channel = <15>; /* SMSG_CH_PLAYBACK_VOIP */ + sprd,capture_channel = <16>; /* SMSG_CH_CAPTURE_VOIP */ + sprd,monitor_channel = <17>; /*SMSG_CH_MONITOR_VOIP */ + sprd,saudio-names = "saudiovoip"; + }; + + /* LTE modem virtual devices */ + spipe_lte { + compatible = "sprd,spipe"; + sprd,name = "spipe_lte"; + sprd,dst = <5>; + sprd,channel = <4>; + sprd,ringnr = <9>; + sprd,size-rxbuf = <0x1000>; /* 4*1024 */ + sprd,size-txbuf = <0x1000>; /* 4*1024 */ + }; + + slog_lte { + compatible = "sprd,spipe"; + sprd,name = "slog_lte"; + sprd,dst = <5>; + sprd,channel = <5>; + sprd,ringnr = <1>; + sprd,size-rxbuf = <0x40000>; /* 256*1024*/ + sprd,size-txbuf = <0x8000>; /* 32*1024 */ + }; + + sdiag_lte { + compatible = "sprd,spipe"; + sprd,name = "sdiag_lte"; + sprd,dst = <5>; + sprd,channel = <21>; + sprd,ringnr = <1>; + sprd,size-rxbuf = <0x40000>; /* 256*1024*/ + sprd,size-txbuf = <0x8000>; /* 32*1024 */ + }; + + stty_lte { + compatible = "sprd,spipe"; + sprd,name = "stty_lte"; + sprd,dst = <5>; + sprd,channel = <6>; + sprd,ringnr = <32>; + sprd,size-rxbuf = <0x0800>; /* 2*1024*/ + sprd,size-txbuf = <0x0800>; /* 2*1024 */ + }; + + seth0_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte0"; + sprd,dst = <5>; + sprd,channel = <7>; + sprd,blknum = <256>; + }; + + seth1_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte1"; + sprd,dst = <5>; + sprd,channel = <8>; + sprd,blknum = <256>; + }; + + seth2_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte2"; + sprd,dst = <5>; + sprd,channel = <9>; + sprd,blknum = <256>; + }; + + seth3_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte3"; + sprd,dst = <5>; + sprd,channel = <18>; + sprd,blknum = <256>; + }; + + seth4_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte4"; + sprd,dst = <5>; + sprd,channel = <19>; + sprd,blknum = <256>; + }; + + seth5_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte5"; + sprd,dst = <5>; + sprd,channel = <20>; + sprd,blknum = <256>; + }; + scproc_arm7: scproc@0x50800000 { + compatible = "sprd,scproc"; + sprd,name = "cppmic"; + sprd,ctrl-reg = <0x114 0xff 0xb0 0xff>; /* <shut_down deep_sleep reset get_status> */ + sprd,ctrl-mask = <0x01 0xfffffffe 0x100 0xf0000>; /* masks <> */ + sprd,iram-data = <0xe59f0000 0xe12fff10 0x0>; /* 3rd param equals modem_addr*/ + reg = <0 0x50800000 0 0x8000>, /* <CP_start_addr total_size> = <+128M 26M> */ + <0 0x50800000 0 0x0>, /* <iram1_base size> */ + <0 0x402e0000 0 0x400>, /* <aon_apb_base size> */ + <0 0x402b0000 0 0x100>, /* <pmu_base size> */ + <0 0x402b0000 0 0x100>, /* <pmu_base size> */ + <0 0x402b0000 0 0x100>; /* <pmu_base size> */ + #address-cells = <1>; + #size-cells = <1>; + /* segnr=1 */ + ranges = <0x0 0 0x50800000 0x8000>; + modem@0x0 { + cproc,name = "modem"; + reg = <0x0 0x8000>; /* <modem_addr size> */ + }; + }; + + scproc_cp1: scproc@0x89600000 { + compatible = "sprd,scproc"; + sprd,name = "cptl"; + sprd,ctrl-reg = <0x0c 0xff 0xb0 0x78>; /* <shut_down deep_sleep reset get_status> */ + sprd,ctrl-mask = <0x00300000 0x10000000 0x02 0x1>; /* masks <> */ + sprd,iram-data = <0xe59f0000 0xe12fff10 0x8ae00000>; /* 3rd param equals modem_addr*/ + reg = <0 0x89600000 0 0x5300000>, /* <CP_start_addr total_size> = <+128M 83M> */ + <0 0x50001000 0 0x0c>, /* <iram1_base size> */ + <0 0x402e0000 0 0x100>, /* <aon_apb_base size> */ + <0 0x402b0000 0 0x100>, /* <pmu_base size> */ + <0 0x402b0000 0 0x100>, /* <pmu_base size> */ + <0 0x402b0000 0 0x100>; /* <pmu_base size> */ + interrupts = <0 84 0x0>; /* cp1_wdg_int */ + #address-cells = <1>; + #size-cells = <1>; + /* segnr=4 */ + ranges = <0x1800000 0 0x8ae00000 0x02E00000>, + <0x0020000 0 0x89620000 0x002E0000>, + <0x0300000 0 0x89900000 0x1C0000>, + <0x4900000 0 0x8df00000 0xA00000>; + modem@0x1800000 { + cproc,name = "modem"; + reg = <0x1800000 0x02E00000>; /* <modem_addr size> */ + }; + dsp@0x20000 { + cproc,name = "tgdsp"; + reg = <0x20000 0x002e0000>; /* <dsp_addr size>*/ + }; + dsp@0x300000 { + cproc,name = "ldsp"; + reg = <0x300000 0x1c0000>; /* <dsp_addr size>*/ + }; + modem@0x4900000 { + cproc,name = "warm"; + reg = <0x4900000 0xA00000>; /* <modem_addr size>*/ + }; + }; + + itm_wlan{ + compatible = "sprd,itm_wlan"; + }; + + dmac: dmac@20100000 { + compatible = "sprd,sprd-dma"; + interrupts = <0 50 0x0>; + reg = <0 0x20100000 0 0x4000>; + }; + + gpu: gpu@60000000 { + compatible = "sprd,mali-midgard"; + reg = <0 0x60000000 0 0x4000>; + interrupts = <0 39 0x4>, <0 39 0x4>, <0 39 0x4>; + interrupt-names = "JOB", "MMU", "GPU"; + + clocks = <&clk_gpu_axi>,<&clk_gpu>,<&clk_153m6>, <&clk_192m>, <&clk_256m>, <&clk_307m2>, <&clk_384m>, <&clk_gpll>; + clock-names = "clk_gpu_axi","clk_gpu","clk_153m6","clk_192m","clk_256m","clk_307m2","clk_384m","clk_gpll"; + + freq-list-len = <4>; + freq-lists = <153600 2 1>, <256000 4 1>, <384000 6 1>, <512000 7 1>; + freq-default = <3>; + freq-9 = <3>; + freq-8 = <3>; + freq-7 = <1>; + freq-5 = <0>; + freq-range-max = <3>; + freq-range-min = <0>; + }; + + ion { + compatible = "sprd,ion-sprd"; + #address-cells = <1>; + #size-cells = <0>; + + sprd,ion-heap@1 { + reg = <1>; /* SYSTEM */ + reg-names = "ion_heap_system"; + sprd,ion-heap-type = <0>; /* SYSTEM */ + sprd,ion-heap-mem = <0x0 0x0>; + }; + + sprd,ion-heap@2 { + reg = <2>; /* MM */ + reg-names = "ion_heap_carveout_mm"; + sprd,ion-heap-type = <0>; /* carveout mm */ + sprd,ion-heap-mem = <0x9864F000 0x7100000>; + }; + + sprd,ion-heap@3 { + reg = <3>; /* OVERLAY */ + reg-names = "ion_heap_carveout_overlay"; + sprd,ion-heap-type = <2>; /* CARVEOUT */ + sprd,ion-heap-mem = <0x9F000000 0x1000000>; /* 1920*1080*4*2, 1M alignment */ + }; + + sprd,ion-heap@4 { + reg = <4>; /* FB */ + reg-names = "ion_heap_carveout_fb"; + sprd,ion-heap-type = <2>; /* CARVEOUT */ + sprd,ion-heap-mem = <0x9D845000 0x17BB000>; + }; + }; + + sprd_iommu0: sprd_iommu@20b00000 { + compatible = "sprd,sprd_iommu";//gsp + func-name = "sprd_iommu_gsp"; + reg = <0 0x10000000 0 0x2000000>, //iova + <0 0x20b00000 0 0x8000>, //pgt + <0 0x20b08000 0 0x8000>; //ctrl_reg + reg_name = "iova","pgt","ctrl_reg"; + clock-names = "clk_gsp_emc","clk_153m6","clk_gsp0"; + clocks = <&clk_gsp_emc>, <&clk_153m6>,<&clk_gsp0>; + status = "ok"; + }; + + sprd_iommu1: sprd_iommu@60f00000 { + compatible = "sprd,sprd_iommu";//mm + func-name = "sprd_iommu_mm"; + reg = <0 0x20000000 0 0x8000000>, //iova + <0 0x60f00000 0 0x20000>, //pgt + <0 0x60f20000 0 0x2000>; //ctrl_reg + reg_name = "iova","pgt","ctrl_reg"; + clock-names = "clk_mmu","clk_mm_i"; + clocks = <&clk_mmu>,<&clk_mm>; + status = "ok"; + }; + + sprd_vsp: sprd_vsp@60900000{ + compatible = "sprd,sprd_vsp"; + reg = <0 0x60900000 0 0xc000>; + interrupts = <0 43 0x0>; + clock-names = "clk_mm_i", "clk_vsp", "clk_parent_0", "clk_parent_1", "clk_parent_2", "clk_parent_3"; + clocks = <&clk_mm>, <&clk_vsp>, <&clk_307m2>, <&clk_256m>, <&clk_128m>, <&clk_96m>; + clock-parent-info = <2 4>; + version = <7>; + }; + + sprd_vpp@61000000{ + compatible = "sprd,sprd_vpp"; + reg = <0 0x61000000 0 0x4000>; + interrupts = <0 43 0x0>; + clock-names = "clk_mm_i","clk_vpp"; + clocks = <&clk_mm>, <&clk_vpp>; + }; + + sprd_coda7l@62100000{ + compatible = "sprd,sprd_coda7l"; + reg = <0 0x62100000 0 0x4000>; + interrupts = <0 43 0x0>; + clock-names = "clk_mm_i","clk_coda7_axi","clk_coda7_cc","clk_coda7_apb"; + clocks = <&clk_mm>, <&clk_coda7_axi>, <&clk_coda7_cc>, <&clk_coda7_apb>; + }; + + sprd_jpg { + compatible = "sprd,sprd_jpg"; + reg = <0 0x60b00000 0 0x8000>; + interrupts = <0 42 0x0>; + clock-names = "clk_mm_i","clk_jpg"; + clocks = <&clk_mm>, <&clk_jpg>; + }; + sprd_bm { + compatible = "sprd,sprd_bm"; + reg = <0 0x30040000 0 0xA0000 + 0 0x20F00000 0 0x300000>; + interrupts = <0 86 0x0>; + sprd,bm_status = <1>; + sprd,bm_count = <10 11>; + sprd,cpu_chn = <0 1>; + sprd,disp_chn = <1 1>; + sprd,gpu_chn = <2 1>; + sprd,ap_zip_chn = <3 1>; + sprd,mm_chn = <4 1>; + sprd,cp0_arm0_1_chn = <5 1>; + sprd,cp0_dsp_chn = <6 0>; + sprd,cp1_lte_chn = <7 1>; + sprd,cp1_dsp_chn = <8 1>; + sprd,cp1_arm_chn = <9 1>; + sprd,ap_dap_chn = <0 0>; + sprd,ap_cpu_chn = <0 1>; + sprd,ap_dma_r_chn = <0 2>; + sprd,ap_dma_w_chn = <0 3>; + sprd,ap_sdio_0_chn = <1 0>; + sprd,ap_sdio_1_chn = <1 1>; + sprd,ap_sdio_2_chn = <1 2>; + sprd,ap_emmc_chn = <1 3>; + sprd,ap_nandc_chn = <2 0>; + sprd,ap_otg_chn = <2 1>; + sprd,ap_hsic_chn = <2 2>; + }; + wdt@40290000 { + compatible = "sprd,sprd-wdt"; + reg = <0 0x40290000 0 0x1000>, + <0 0x40310000 0 0x1000>; + interrupts = <0 124 0x0>; + }; + sprd-marlin { + compatible = "sprd,marlin"; + gpios = <&d_gpio_gpio 97 0 /*marlin gpio0 */ + &d_gpio_gpio 132 0 /*marlin gpio1 */ + &d_gpio_gpio 133 0 /*marlin gpio2 */ + &d_gpio_gpio 94 0 /*marlin gpio3 */ + &d_gpio_gpio 130 0>; /*marlin reset*/ + cp-rfctl-offset = <0x244>; /*coex func. marlin gpio3*/ + vdd-download = "vddcon"; /*vdd 1.6v*/ + vdd-pa = "vddwifipa"; /*vdd 3.3v*/ + clk-name = "clk_aux0"; /*clk 32k*/ + sdhci-name = "sdio_wifi"; + }; + +}; + +&vbc_r2p0 { + status = "okay"; +}; + +&sprd_codec { + status = "okay"; + sprd,audio_power_ver = <4>; +}; + +&i2s0 { + sprd,config_type = "pcm"; + sprd,slave_timeout = <0xF11>; + sprd,_hw_port = <0>; + sprd,fs = <8000>; + sprd,bus_type = <1>; + sprd,rtx_mode = <3>; + sprd,byte_per_chan = <1>; + sprd,slave_mode = <0>; + sprd,lsb = <0>; + sprd,lrck = <0>; + sprd,low_for_left = <1>; + sprd,clk_inv = <0>; + sprd,pcm_short_frame = <1>; + sprd,pcm_slot = <0x1>; + sprd,pcm_cycle = <1>; + sprd,tx_watermark = <12>; + sprd,rx_watermark = <20>; + status = "okay"; +}; + +&i2s1 { + status = "okay"; +}; + +&i2s2 { + status = "okay"; +}; + +&i2s3 { + status = "okay"; +}; + +&i2s_sound { + sprd,i2s = <&i2s0>, <&i2s1>, <&i2s2>, <&i2s3>; +}; + +&sprd_battery { + gpios = <&a_eic_gpio 0 0 /* chg int */ + &a_eic_gpio 4 0 /* cv state */ + &a_eic_gpio 6 0 /* chg ovi */ + &a_eic_gpio 9 0>; /* battery detect */ + + chg-end-vol-h = <4375>; + chg-end-vol-pure = <4350>; + chg-end-vol-l = <4340>; + chg-bat-safety-vol = <4430>; + rechg-vol = <4260>; + + fgu-mode = <0>; + alm-soc = <5>; + alm-vol = <3500>; + soft-vbat-uvlo = <3100>; + rint = <200>; + cnom = <2100>; + rsense-real = <118>; + rsense-spec = <200>; + relax-current = <50>; + fgu-cal-ajust = <0>; + ocv-tab-size = <21>; + ocv-tab-vol = <4318 4254 4198 4145 4094 4052 3987 3955 3902 3865 3838 3817 3800 3785 3769 3752 3733 3706 3691 3588 3400>; + ocv-tab-cap = <100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0>; +}; diff --git a/arch/arm64/boot/dts/sprd_sp9838aea_fpga.dts b/arch/arm64/boot/dts/sprd_sp9838aea_fpga.dts new file mode 100755 index 00000000..08b4078f --- /dev/null +++ b/arch/arm64/boot/dts/sprd_sp9838aea_fpga.dts @@ -0,0 +1,650 @@ +/* + * SPREADTRUM Ltd.clock-cells +sprd_rotation + * + * SharkLT8 5mod fpga DTS + */ + +/dts-v1/; + +/* memory reserved for SMEM */ +/memreserve/ 0x87800000 0x5B0000; /* Offset:120M, Size:5M+256K */ + +/* memory reserved for WARM modem */ +/memreserve/ 0x8DC00000 0xD00000; /* Offset:217M, Size:13M*/ + +/* memory reserved for LTE modem */ +/memreserve/ 0x89600000 0x4600000; /* Offset:150M, Size:70M*/ + +/* memory reserved for fb */ +/memreserve/ 0x9F74F000 0x4B1000; /* 480*854*4*3, 4K alignment*/ + +/* memory reserved for ION(carveout mm)*/ +/memreserve/ 0x98800000 0x7100000; + +/* memory reserved for ION(overlay)*/ +/memreserve/ 0x9f900000 0x700000; /* 7MB */ + + +/include/ "sprd-battery.dtsi" + +/ { + model = "scx35l64"; + compatible = "sprd,SharkLT8"; + sprd,sc-id = <8830 1 0x20000>; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { + bootargs = "earlyprintk=sprd_uart,0x70100000 loglevel=7 console=ttyS1,115200n8"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@530000 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530000>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD>; + }; + + cpu@530001 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530001>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD>; + }; + + cpu@530002 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530002>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD>; + }; + + cpu@530003 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530003>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD>; + }; + + cpu@530100 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530100>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD>; + }; + + cpu@530101 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530101>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD>; + }; + + cpu@530102 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530102>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD>; + }; + + cpu@530103 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530103>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD>; + }; + idle-states{ + entry-method = "arm,psci"; + LIGHT_SLEEP: light_sleep { + compatible = "arm,idle-state"; + exit-latency-us = <100>; + min-residency-us = <500>; + entry-method-param = <0x00000001>; + }; + CORE_PD: core_pd { + compatible = "arm,idle-state"; + exit-latency-us = <1070>; + min-residency-us = <1600>; + entry-method-param = <0x00010002>; + }; + CLUSTER_PD: cluster_pd { + compatible = "arm,idle-state"; + exit-latency-us = <1100>; + min-residency-us = <2500>; + entry-method-param = <0x01010003>; + }; + DEEP_SLEEP: deep_sleep { + compatible = "arm,idle-state"; + exit-latency-us = <4100>; + min-residency-us = <6500>; + entry-method-param = <0x01010004>; + }; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0 0x80000000 0 0x20000000>; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + lcd0 = &fb0; + hwspinlock0 = &hwspinlock0; + hwspinlock1 = &hwspinlock1; + }; + + intc:interrupt-controller@71400000 { + compatible = "sprd,intc"; + #interrupt-cells = <0>; + interrupt-controller; + reg = <0 0x71400000 0 0x1000>, + <0 0x71500000 0 0x1000>, + <0 0x71600000 0 0x1000>, + <0 0x71700000 0 0x1000>; + }; + + gic: interrupt-controller@12001000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0x12001000 0 0x1000>, + <0 0x12002000 0 0x1000>; + }; + + psci { + compatible = "arm,psci"; + method = "smc"; + cpu_on = <0xc4000003>; + cpu_off = <0x84000002>; + cpu_suspend = <0xc4000001>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, + <1 14 0xff01>, + <1 11 0xff01>, + <1 10 0xff01>; + clock-frequency = <26000000>; + }; + + sprd_timer { + compatible = "sprd,sharkl64-timer"; + reg = <0 0x40050000 0 0x20>; /*aon GPTIMER0 */ + interrupts = <0 28 0x0>; + clock-frequency = <32768>; + }; + + sprd_ap_system_timer { + reg = <0 0x40230000 0 0x20>; + interrupts = <0 31 0x0>; + }; + uart0: uart@70000000 { + compatible = "sprd,serial"; + reg = <0 0x70000000 0 0x100>; + interrupts = <0 2 0xf04>; + }; + + uart1: uart@70100000 { + compatible = "sprd,serial"; + reg = <0 0x70100000 0 0x100>; + interrupts = <0 3 0xf04>; + }; + hwspinlock0: hwspinlock0@20c00000{ + compatible = "sprd,sprd-hwspinlock"; + reg = <0 0x20c00000 0 0x1000>; + }; + hwspinlock1: hwspinlock1@40060000{ + compatible = "sprd,sprd-hwspinlock"; + reg = <0 0x40060000 0 0x1000>; + status = "ok"; + }; + + watchdog { + compatible = "sprd,watchdog"; + reg = <0 0X40290000 0 0x1000>; + }; + + d_eic_gpio: gpio@40210000 { + compatible = "sprd,d-eic-gpio"; + reg = <0 0x40210000 0 0x1000>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-cells = <2>; + gpiobase = <288>; + ngpios = <16>; + interrupts = <0 37 0x0>; + }; + + d_gpio_gpio: gpio@40280000 { + compatible = "sprd,d-gpio-gpio"; + reg = <0 0x40280000 0 0x1000>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-cells = <2>; + gpiobase = <0>; + ngpios = <256>; + interrupts = <0 35 0x0>; + }; + + sdhci3: sdhci@20600000 { + compatible = "sprd,sdhci-shark"; + interrupts = <0 60 0x0>; + reg = <0 0x20600000 0 0x1000>; + id = <3>; + bus-width = <8>; + max-frequency = <384000000>; + keep-power-in-suspend = <1>; + non-removable = <1>; + caps = <0x80000000>; + caps2 = <0x202>; + quirks = <0x21009001>; //SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | SDHCI_QUIRK_BROKEN_CARD_DETECTION | SDHCI_QUIRK_CLOCK_BEFORE_RESET + quirks2 = <0x8>; //SDHCI_QUIRK2_PRESET_VALUE_BROKEN + host-caps-mask = <0x03000000>; + vdd-vmmc = "vddemmccore"; + vdd-vqmmc = "vddgen1"; + // clock-names = "clk_emmc"; + // clocks = <&clk_emmc>, <&clk_384m>; + enb-bit = <0x800>; + rst-bit = <0x4000>; + write-delay = <0x04>; + read-pos-delay = <0x04>; + read-neg-delay = <0x04>; + keep-power = <0>; + runtime = <1>; + }; + + + adi: adi_bus { + compatible = "sprd,adi-bus"; + interrupts = <0 38 0x0>; + reg = <0 0x40038000 0 0x1000>; + interrupt-controller; + sprd,irqnums = <11>; + #interrupt-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x100 0 0x40038100 0x80>; + + keyboard_backlight { + compatible = "sprd,keyboard-backlight"; + }; + a_eic_gpio: gpio@100{ + compatible = "sprd,a-eic-gpio"; + reg = <0x100 0x80>; /* adi reg */ + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-cells = <2>; + gpiobase = <304>; + ngpios = <16>; + interrupt-parent = <&adi>; + interrupts = <5 0x0>; /* ext irq 5 */ + }; + sprd_eic_keys { + compatible = "sprd,sprd-eic-keys"; + input-name = "sprd-eic-keys"; + key_power { + label = "Power Key"; + linux,code = <116>; + gpios = <&a_eic_gpio 2 0>; + debounce-interval = <2>; + gpio-key,wakeup; + }; + }; + }; + vddusb: vddusb { + regulator-name = "vddusb"; + reg = <0x40038814 0x100 0x4003883c 0xff 0 0>; /* pd reg && vol trm reg && otp_sel_reg */ + regulator-cal-channel = <0x40038844 0x10 0x1d>; + regulator-default-microvolt = <3300000>; + regulator-step-microvolt = <10000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3760000>; + regulator-microvolt-offset = <0>; + }; + usb: usb@20200000{ + compatible = "sprd,usb"; + interrupts = <0 55 0x0>; + ngpios = <1>; + gpios = <&a_eic_gpio 0 0>; + reg = <0 0x20200000 0 0x1000>; + tune_value = <0x44073e33>; + usb-supply = <&vddusb>; + #address-cells = <1>; + #size-cells = <0>; + }; + sprd-io-base { + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 1 0>; + ahb { + compatible = "sprd,ahb"; + reg = <0 0x20e00000 0 0x40000>; + }; + apbckg { + compatible = "sprd,apbckg"; + reg = <0 0x21500000 0 0x1000>; + }; + hwlock0 { + compatible = "sprd,hwlock0"; + reg = <0 0x20d00000 0 0x1000>; + }; + pub_apb { + compatible = "sprd,pub_apb"; + reg = <0 0x30020000 0 0x10000>; + }; + aon_apb { + compatible = "sprd,aon_apb"; + reg = <0 0x402e0000 0 0x40000>; + }; + pmu_apb { + compatible = "sprd,pmu_apb"; + reg = <0 0x402b0000 0 0x40000>; + }; + mm_ahb { + compatible = "sprd,mm_ahb"; + reg = <0 0x60d00000 0 0x10000>; + }; + mm_clk { + compatible = "sprd,mm_clk"; + reg = <0 0x60e00000 0 0x1000>; + }; + ap_ckg { + compatible = "sprd,ap_ckg"; + reg = <0 0x71200000 0 0x40000>; + }; + ap_apb { + compatible = "sprd,ap_apb"; + reg = <0 0x71300000 0 0x40000>; + }; + gpu_apb { + compatible = "sprd,gpu_apb"; + reg = <0 0x60100000 0 0x1000>; + }; + adi { + compatible = "sprd,adi"; + reg = <0 0x40030000 0 0x10000>; + }; + adi_slave { + compatible = "sprd,adi_slave"; + reg = <0 0x40038000 0 0x1000>; + }; + adc { + compatible = "sprd,adc"; + reg = <0 0x40038300 0 0x1000>; + }; + dma { + compatible = "sprd,dma"; + reg = <0 0x20100000 0 0x4000>; + interrupts = <0 50 0x0>; + }; + mailbox { + compatible = "sprd,mailbox"; + reg = <0 0x400a0000 0 0x10000>; + }; + rtc { + compatible = "sprd,rtc"; + reg = <0 0x40038080 0 0x80>; + interrupts = <0 2 0x0>; + }; + axibm0 { + compatible = "sprd,axibm0"; + reg = <0 0x30040000 0 0x20000>; + interrupts = <0 86 0x0>; + }; + }; + fb0: fb@20800000 { + compatible = "sprd,sprdfb"; + reg = <0 0x20800000 0 0x1000>, + <0 0x21800000 0 0x1000>; + interrupts = <0 46 0x0>, + <0 48 0x0>, + <0 49 0x0>; +/* + clock-names = "dispc_clk_parent", "dispc_dbi_clk_parent", "dispc_dpi_clk_parent", "dispc_emc_clk_parent", "dispc_clk", "dispc_dbi_clk", "dispc_dpi_clk", "dispc_emc_clk", "fb_spi_clock", "fb_spi_clock_parent"; + //clocks = <&clk_256m>, <&clk_256m>, <&clk_384m>, <&clk_aon_apb>, <&clk_dispc0>, <&clk_dispc0_dbi>, <&clk_dispc0_dpi>, <&clk_disp_emc>, <&clk_spi2>, <&ext_26m>; + clock-src = <256000000 256000000 384000000>; + dpi_clk_div = <7>; +*/ + sprd,fb_use_reservemem; + sprd,fb_mem = <0x8a800000 0x600000>; + + }; + + ion { + compatible = "sprd,ion-sprd"; + #address-cells = <1>; + #size-cells = <0>; + + sprd,ion-heap@1 { + reg = <1>; /* SYSTEM */ + reg-names = "ion_heap_system"; + sprd,ion-heap-type = <0>; /* SYSTEM */ + sprd,ion-heap-mem = <0x0 0x0>; + }; + sprd,ion-heap@2 { + reg = <2>; /* MM */ + reg-names = "ion_heap_carveout_mm"; + sprd,ion-heap-type = <2>; /* carveout mm */ + sprd,ion-heap-mem = <0x98800000 0x7100000>; + }; + sprd,ion-heap@3 { + reg = <3>; /* OVERLAY */ + reg-names = "ion_heap_carveout_overlay"; + sprd,ion-heap-type = <2>; /* CARVEOUT */ + sprd,ion-heap-mem = <0x9f900000 0x700000>; /* 7M */ + }; + }; + sipc: sipc@0x87800000 { + compatible = "sprd,sipc"; + reg = <0 0x87800000 0 0x5B0000>; /* <SMEM SIZE>*/ + //#interrupt-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + ranges =<0x09600000 0 0x89600000 0x4600000>, + <0x07800000 0 0x87800000 0x5B0000>, + <0x0dbff000 0 0x8dbff000 0x1000>; + sipc_lte@0x09600000 { + sprd,name = "sipc-lte"; + sprd,dst = <5>; + /* it's unnecessary to config IPI info upon mailbox arch */ + mailbox,core = <7>; + reg = <0x09600000 0x4600000> , /* <CP_start_addr size> */ + <0x07800000 0x5B0000>, /* <SMEM_phy_addr total_size> */ + <0x0dbff000 0x1000>; /* smsg ring buffer <base size> */ + }; + }; + + /* LTE modem virtual devices */ + spipe_lte { + compatible = "sprd,spipe"; + sprd,name = "spipe_lte"; + sprd,dst = <5>; + sprd,channel = <4>; + sprd,ringnr = <9>; + sprd,size-rxbuf = <0x1000>; /* 4*1024 */ + sprd,size-txbuf = <0x1000>; /* 4*1024 */ + }; + + slog_lte { + compatible = "sprd,spipe"; + sprd,name = "slog_lte"; + sprd,dst = <5>; + sprd,channel = <5>; + sprd,ringnr = <1>; + sprd,size-rxbuf = <0x40000>; /* 256*1024*/ + sprd,size-txbuf = <0x8000>; /* 32*1024 */ + }; + + sdiag_lte { + compatible = "sprd,spipe"; + sprd,name = "sdiag_lte"; + sprd,dst = <5>; + sprd,channel = <21>; + sprd,ringnr = <1>; + sprd,size-rxbuf = <0x40000>; /* 256*1024*/ + sprd,size-txbuf = <0x8000>; /* 32*1024 */ + }; + + stty_lte { + compatible = "sprd,spipe"; + sprd,name = "stty_lte"; + sprd,dst = <5>; + sprd,channel = <6>; + sprd,ringnr = <32>; + sprd,size-rxbuf = <0x0800>; /* 2*1024*/ + sprd,size-txbuf = <0x0800>; /* 2*1024 */ + }; + + seth0_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte0"; + sprd,dst = <5>; + sprd,channel = <7>; + sprd,blknum = <256>; + }; + + seth1_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte1"; + sprd,dst = <5>; + sprd,channel = <8>; + sprd,blknum = <256>; + }; + + seth2_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte2"; + sprd,dst = <5>; + sprd,channel = <9>; + sprd,blknum = <256>; + }; + + seth3_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte3"; + sprd,dst = <5>; + sprd,channel = <18>; + sprd,blknum = <256>; + }; + + seth4_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte4"; + sprd,dst = <5>; + sprd,channel = <19>; + sprd,blknum = <256>; + }; + + seth5_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte5"; + sprd,dst = <5>; + sprd,channel = <20>; + sprd,blknum = <256>; + }; + scproc_arm7: scproc@0x50800000 { + compatible = "sprd,scproc"; + sprd,name = "cppmic"; + sprd,ctrl-reg = <0x114 0xff 0xb0 0xff>; /* <shut_down deep_sleep reset get_status> */ + sprd,ctrl-mask = <0x01 0xfffffffe 0x100 0xf0000>; /* masks <> */ + sprd,iram-data = <0xe59f0000 0xe12fff10 0x0>; /* 3rd param equals modem_addr*/ + reg = <0 0x50800000 0 0x8000>, /* <CP_start_addr total_size> = <+128M 26M> */ + <0 0x50800000 0 0x0>, /* <iram1_base size> */ + <0 0x402e0000 0 0x400>, /* <aon_apb_base size> */ + <0 0x402b0000 0 0x100>, /* <pmu_base size> */ + <0 0x402b0000 0 0x100>, /* <pmu_base size> */ + <0 0x402b0000 0 0x100>; /* <pmu_base size> */ + #address-cells = <1>; + #size-cells = <1>; + /* segnr=1 */ + ranges = <0x0 0 0x50800000 0x8000>; + modem@0x0 { + cproc,name = "modem"; + reg = <0x0 0x8000>; /* <modem_addr size> */ + }; + }; + + scproc_cp1: scproc@0x89600000 { + compatible = "sprd,scproc"; + sprd,name = "cptl"; + sprd,ctrl-reg = <0x0c 0xff 0xb0 0x78>; /* <shut_down deep_sleep reset get_status> */ + sprd,ctrl-mask = <0x00300000 0x10000000 0x02 0x1>; /* masks <> */ + sprd,iram-data = <0xe59f0000 0xe12fff10 0x8ae00000>; /* 3rd param equals modem_addr*/ + reg = <0 0x89600000 0 0x5300000>, /* <CP_start_addr total_size> = <+128M 83M> */ + <0 0x50001000 0 0x0c>, /* <iram1_base size> */ + <0 0x402e0000 0 0x100>, /* <aon_apb_base size> */ + <0 0x402b0000 0 0x100>, /* <pmu_base size> */ + <0 0x402b0000 0 0x100>, /* <pmu_base size> */ + <0 0x402b0000 0 0x100>; /* <pmu_base size> */ + interrupts = <0 84 0x0>; /* cp1_wdg_int */ + #address-cells = <1>; + #size-cells = <1>; + /* segnr=4 */ + ranges = <0x1800000 0 0x8ae00000 0x02E00000>, + <0x0020000 0 0x89620000 0x002E0000>, + <0x0300000 0 0x89900000 0x1C0000>, + <0x4900000 0 0x8df00000 0xA00000>; + modem@0x1800000 { + cproc,name = "modem"; + reg = <0x1800000 0x02E00000>; /* <modem_addr size> */ + }; + dsp@0x20000 { + cproc,name = "tgdsp"; + reg = <0x20000 0x002e0000>; /* <dsp_addr size>*/ + }; + dsp@0x300000 { + cproc,name = "ldsp"; + reg = <0x300000 0x1c0000>; /* <dsp_addr size>*/ + }; + modem@0x4900000 { + cproc,name = "warm"; + reg = <0x4900000 0xA00000>; /* <modem_addr size>*/ + }; + }; + + ion { + compatible = "sprd,ion-sprd"; + #address-cells = <1>; + #size-cells = <0>; + + sprd,ion-heap@1 { + reg = <1>; /* SYSTEM */ + reg-names = "ion_heap_system"; + sprd,ion-heap-type = <0>; /* SYSTEM */ + sprd,ion-heap-mem = <0x0 0x0>; + }; + sprd,ion-heap@2 { + reg = <2>; /* MM */ + reg-names = "ion_heap_carveout_mm"; + sprd,ion-heap-type = <2>; /* carveout mm */ + sprd,ion-heap-mem = <0x98800000 0x7100000>; + }; + sprd,ion-heap@3 { + reg = <3>; /* OVERLAY */ + reg-names = "ion_heap_carveout_overlay"; + sprd,ion-heap-type = <2>; /* CARVEOUT */ + sprd,ion-heap-mem = <0x9f900000 0x700000>; /* 7M */ + }; + }; +}; diff --git a/arch/arm64/boot/dts/sprd_sp9838aea_power_debug.dts b/arch/arm64/boot/dts/sprd_sp9838aea_power_debug.dts new file mode 100644 index 00000000..89d88ac6 --- /dev/null +++ b/arch/arm64/boot/dts/sprd_sp9838aea_power_debug.dts @@ -0,0 +1,1596 @@ +/* + * SPREADTRUM Ltd.clock-cells +sprd_rotation + * + * SharkLT8 5mod refphone DTS + */ + +/dts-v1/; + +/* memory reserved for SMEM */ +/memreserve/ 0x87800000 0x5B0000; /* Offset:120M, Size:5M+256K */ + +/* memory reserved for WARM modem */ +/memreserve/ 0x8DC00000 0xD00000; /* Offset:220M, Size:13M*/ + +/* memory reserved for LTE modem */ +/memreserve/ 0x89600000 0x4600000; /* Offset:150M, Size:70M*/ + +/* memory reserved for fb */ +/memreserve/ 0x9ED74000 0xA8C000; /* 1280*720*4*3, 4K alignment*/ + +/* memory reserved for ION */ +/memreserve/ 0x9F800000 0x800000; /* 1280*720*4*2, 1M alignment*/ + +/* memory reserved for smp */ +/memreserve/ 0x9F700000 0x1000; /* size 4K*/ + +/include/ "sc2723-regulators.dtsi" +/include/ "sprd-sound.dtsi" +/include/ "sprd-battery.dtsi" +/include/ "scx35lt8-clocks.dtsi" + +/ { + model = "scx35l64"; + compatible = "sprd,SharkLT8"; + sprd,sc-id = <8830 1 0x20000>; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { + bootargs = "earlyprintk=sprd_uart,0x70100000 loglevel=1 console=ttyS1,115200n8"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + core1 { + cpu = <&CPU5>; + }; + core2 { + cpu = <&CPU6>; + }; + core3 { + cpu = <&CPU7>; + }; + }; + }; + + CPU0: cpu@530000 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530000>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD &CLUSTER_PD>; + clocks = <&clk_little_mcu>; + cpu0-supply = <&vddarm>; + operating-points = < + /* kHz uV */ + 1000000 900000 + 800000 900000 + 750000 900000 + 600000 900000 + 533000 900000 + 400000 900000 + 200000 900000 + >; + }; + + CPU1: cpu@530001 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530001>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD &CLUSTER_PD>; + }; + + CPU2: cpu@530002 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530002>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD &CLUSTER_PD>; + }; + + CPU3: cpu@530003 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530003>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD &CLUSTER_PD>; + }; + + CPU4: cpu@530100 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530100>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD &CLUSTER_PD>; + clocks = <&clk_big_mcu>; + cpu0-supply = <&vddbigarm>; + operating-points = < + /* kHz uV */ + 1500000 1050000 + 1420000 1050000 + 1350000 1050000 + 1200000 900000 + 1100000 900000 + 1000000 900000 + 960000 900000 + >; + }; + + CPU5: cpu@530101 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530101>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD &CLUSTER_PD>; + }; + + CPU6: cpu@530102 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530102>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD &CLUSTER_PD>; + }; + + CPU7: cpu@530103 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x530103>; + enable-method = "psci"; + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD &CLUSTER_PD>; + }; + + idle-states{ + entry-method = "arm,psci"; + LIGHT_SLEEP: light_sleep { + compatible = "arm,idle-state"; + exit-latency-us = <100>; + min-residency-us = <500>; + entry-method-param = <0x00000001>; + }; + CORE_PD: core_pd { + compatible = "arm,idle-state"; + exit-latency-us = <1070>; + min-residency-us = <5000>; + entry-method-param = <0x00010002>; + }; + CLUSTER_PD: cluster_pd { + compatible = "arm,idle-state"; + exit-latency-us = <2000>; + min-residency-us = <8000>; + entry-method-param = <0x01010003>; + }; + TOP_PD: top_pd { + compatible = "arm,idle-state"; + exit-latency-us = <2000>; + min-residency-us = <5000>; + entry-method-param = <0x01010004>; + }; + DEEP_SLEEP: deep_sleep { + compatible = "arm,idle-state"; + exit-latency-us = <4100>; + min-residency-us = <6500>; + entry-method-param = <0x01010005>; + }; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0 0x80000000 0 0x40000000>; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + lcd0 = &fb0; + hwspinlock0 = &hwspinlock0; + hwspinlock1 = &hwspinlock1; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 92 4>, + <0 93 4>, + <0 94 4>, + <0 95 4>; + }; + + psci { + compatible = "arm,psci"; + method = "smc"; + cpu_on = <0xc4000003>; + cpu_off = <0x84000002>; + cpu_suspend = <0xc4000001>; + }; + + gic: interrupt-controller@12001000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0x12001000 0 0x1000>, + <0 0x12002000 0 0x1000>; + }; + + intc:interrupt-controller@71400000 { + compatible = "sprd,intc"; + #interrupt-cells = <0>; + interrupt-controller; + reg = <0 0x71400000 0 0x1000>, + <0 0x71500000 0 0x1000>, + <0 0x71600000 0 0x1000>, + <0 0x71700000 0 0x1000>, + <0 0x40200000 0 0x1000>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, + <1 14 0xff01>, + <1 11 0xff01>, + <1 10 0xff01>; + clock-frequency = <26000000>; + }; + + sprd_timer { + compatible = "sprd,sharkl64-timer"; + reg = <0 0x40050000 0 0x20>; /*aon GPTIMER0 */ + interrupts = <0 28 0x0>; + clock-frequency = <32768>; + }; + + sprd_ap_system_timer { + reg = <0 0x40230000 0 0x20>; + interrupts = <0 31 0x0>; + }; + + clock: clockdevice { + compatible = "sprd,scx35l64-clocks"; + #clock-cells = <1>; + }; + + d_eic_gpio: gpio@40210000 { + compatible = "sprd,d-eic-gpio"; + reg = <0 0x40210000 0 0x1000>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-cells = <2>; + gpiobase = <288>; + ngpios = <16>; + interrupts = <0 37 0x0>; + }; + + d_gpio_gpio: gpio@40280000 { + compatible = "sprd,d-gpio-gpio"; + reg = <0 0x40280000 0 0x1000>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-cells = <2>; + gpiobase = <0>; + ngpios = <256>; + interrupts = <0 35 0x0>; + }; + + uart0: uart@70000000 { + compatible = "sprd,serial"; + interrupts = <0 2 0xf04>; + reg = <0 0x70000000 0 0x1000>; + clock-names = "clk_uart0"; + clocks = <&clock 60>; + sprdclk = <48000000>; + sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP"; + + }; + + uart1: uart@70100000 { + compatible = "sprd,serial"; + interrupts = <0 3 0xf04>; + reg = <0 0x70100000 0 0x1000>; + clock-names = "clk_uart1"; + clocks = <&clock 61>; + sprdclk = <26000000>; + sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP"; + + }; + + uart2: uart@70200000 { + compatible = "sprd,serial"; + interrupts = <0 4 0xf04>; + reg = <0 0x70200000 0 0x1000>; + clock-names = "clk_uart2"; + clocks = <&clock 62>; + sprdclk = <26000000>; + sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP"; + }; + + uart3: uart@70300000 { + compatible = "sprd,serial"; + interrupts = <0 5 0xf04>; + reg = <0 0x70300000 0 0x1000>; + clock-names = "clk_uart3"; + clocks = <&clock 63>; + sprdclk = <26000000>; + sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP"; + }; + + hwspinlock0: hwspinlock0@20c00000{ + compatible = "sprd,sprd-hwspinlock"; + reg = <0 0x20c00000 0 0x1000>; + }; + + hwspinlock1: hwspinlock1@40060000{ + compatible = "sprd,sprd-hwspinlock"; + reg = <0 0x40060000 0 0x1000>; + status = "ok"; + }; + + watchdog { + compatible = "sprd,watchdog"; + reg = <0 0X40290000 0 0x1000>; + }; + + pinctrl { + compatible = "sprd,pinctrl"; + reg = <0 0x402a0000 0 0x1000>; + pwr_domain = "vdd28", + "vdd18", + "vddsim0", + "vddsim1", + "vddsim2", + "vddsdio", + "vdd18"; + ctrl_desc = <0x10 0 1 + 0x10 1 1 + 0x10 2 1 + 0x10 3 1 + 0x10 4 1 + 0x10 5 1 + 0x10 6 1>; + }; + + sdios{ + #address-cells = <2>; + #size-cells = <2>; + ranges; + sdio3: sdio@20600000{ + compatible = "sprd,sdhost-3.0"; + reg = <0 0x20600000 0 0x1000>; + interrupts = <0 60 0x0>; + sprd,name = "sdio_emmc"; + /*detect_gpio = <-1>; */ + SD_Pwr_Name = "vddemmccore"; + _1_8V_signal_Name = "vddgen0"; + signal_default_Voltage = <1800000>; + ocr_avail = <0x00040000>; + clocks = <&clk_emmc>, <&clk_192m>; + base_clk = <192000000>; + caps = <0xC00F8D47>; + caps2 = <0x202>; + pm_caps = <0x4>; + writeDelay = <0x3E>; + readPosDelay = <0xA>; + readNegDelay = <0xA>; + }; + + sdio0: sdio@20300000{ + compatible = "sprd,sdhost-3.0"; + reg = <0 0x20300000 0 0x1000>; + interrupts = <0 57 0x0>; + sprd,name = "sdio_sd"; + detect_gpio = <141>; + SD_Pwr_Name = "vddsdcore"; + _1_8V_signal_Name = "vddsdio"; + signal_default_Voltage = <3000000>; + ocr_avail = <0x00040000>; + clocks = <&clk_sdio0>, <&clk_192m>; + base_clk = <192000000>; + caps = <0xC0020407>; + caps2 = <0x200>; + pm_caps = <0x4>; + writeDelay = <0x3>; + readPosDelay = <0x3>; + readNegDelay = <0x3>; + }; + + + sdio1: sdio@20400000{ + compatible = "sprd,sdhost-3.0"; + reg = <0 0x20400000 0 0x1000>; + interrupts = <0 58 0x0>; + sprd,name = "sdio_wifi"; + /* detect_gpio = <-1>; */ + /* SD_Pwr_Name = "vddsdcore"; */ + /* _1_8V_signal_Name = "vddsdio";*/ + /* signal_default_Voltage = <3000000>; */ + ocr_avail = <0x00360080>; + clocks = <&clk_sdio1>, <&clk_76m8>; + base_clk = <76000000>; + caps = <0xC00FA407>; + caps2 = <0x0>; + pm_caps = <0x5>; + writeDelay = <0x03>; + readPosDelay = <0x03>; + readNegDelay = <0x03>; + }; + }; + + adic:adic { + compatible = "sprd,adi"; + reg = <0 0x40030000 0 0x10000>; + }; + + adi: adi_bus { + compatible = "sprd,adi-bus"; + interrupts = <0 38 0x0>; + reg = <0 0x40038000 0 0x1000>; + interrupt-controller; + sprd,irqnums = <11>; + #interrupt-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x100 0 0x40038100 0x80>, + <0x440 0 0x40038440 0x40>, + <0x800 0 0x40038800 0xff>; + + keyboard_backlight { + compatible = "sprd,keyboard-backlight"; + }; + + sprd_kpled_2723 { + compatible = "sprd,sprd-kpled-2723"; + brightness_max = <255>; + brightness_min = <0>; + run_mode = <1>; + }; + + leds_sprd_bltc_rgb { + compatible = "sprd,sprd-leds-bltc-rgb"; + reg = <0x440 0x40>, + <0x800 0xff>; + }; + + a_eic_gpio: gpio@100{ + compatible = "sprd,a-eic-gpio"; + reg = <0x100 0x80>; /* adi reg */ + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #gpio-cells = <2>; + gpiobase = <304>; + ngpios = <16>; + interrupt-parent = <&adi>; + interrupts = <5 0x0>; /* ext irq 5 */ + }; + sprd_eic_keys { + compatible = "sprd,sprd-eic-keys"; + input-name = "sprd-eic-keys"; + key_power { + label = "Power Key"; + linux,code = <116>; + gpios = <&a_eic_gpio 2 0>; + debounce-interval = <2>; + gpio-key,wakeup; + }; + key_volumeup { + label = "Volumeup Key"; + linux,code = <115>; + gpios = <&a_eic_gpio 10 0>; + debounce-interval = <2>; + gpio-key,wakeup; + }; + }; + + headset_sprd_sc2723 { + compatible = "sprd,headset_sprd_sc2723"; + gpio_switch = <0>; + gpio_detect = <312>; + gpio_button = <307>; + irq_trigger_level_detect = <1>; + irq_trigger_level_button = <1>; + adc_threshold_3pole_detect = <2650>; + adc_threshold_4pole_detect = <2651>; + irq_threshold_buttont = <1>; + voltage_headmicbias = <3000000>; + nbuttons = <3>; + headset_buttons_media { + adc_min = <0>; + adc_max = <430>; + code = <226>; + type = <0>; + }; + + headset_buttons_up { + adc_min = <431>; + adc_max = <860>; + code = <115>; + type = <0>; + }; + headset_buttons_down { + adc_min = <861>; + adc_max =<1900>; + code = <114>; + type = <0>; + }; + }; + + rtc@80{ + compatible = "sprd,rtc"; + reg = <0X80 0x80>; + interrupt-parent = <&adi>; + interrupts = <2 0x0>; + }; + }; + + sprd_pwm_bl { + compatible = "sprd,sprd_pwm_bl"; + brightness_max = <255>; + brightness_min = <0>; + pwm_index = <2>; + gpio_ctrl_pin = <0>; + gpio_active_level = <0>; + reg =<0 0x40260000 0 0xf>; + }; + + gpio_keys { + compatible = "gpio-keys"; + input-name = "sprd-gpio-keys"; + key_volumedown { + label = "Volumedown Key"; + linux,code = <114>; + gpios = <&d_gpio_gpio 124 1>; + debounce-interval = <2>; + gpio-key,wakeup; + }; +/* + key_volumeup { + label = "Volumeup Key"; + linux,code = <115>; + gpios = <&d_gpio_gpio 125 1>; + debounce-interval = <2>; + gpio-key,wakeup; + }; +*/ + key_camerafocus { + label = "Camerafocus Key"; + linux,code = <0x210>; + gpios = <&d_gpio_gpio 121 0>; + debounce-interval = <2>; + gpio-key,wakeup; + }; + key_camera { + label = "Camera Key"; + linux,code = <212>; + gpios = <&d_gpio_gpio 122 0>; + debounce-interval = <2>; + gpio-key,wakeup; + }; + }; + + sprd_backlight { + compatible = "sprd,sprd_backlight"; + start = <3>; + end = <3>; + flags = <0x100>; + }; + + rfkill { + compatible = "broadcom,rfkill"; + gpios = <&d_gpio_gpio 131 0 /* power */ + &d_gpio_gpio 122 0>; /* reset */ + }; + bluesleep { + compatible = "broadcom,bluesleep"; + bt-wake-gpio = <&d_gpio_gpio 132 0>; + host-wake-gpio = <&d_gpio_gpio 133 0>; + }; + + usb: usb@20200000{ + compatible = "sprd,usb"; + interrupts = <0 55 0x0>; + ngpios = <1>; + gpios = <&a_eic_gpio 0 0>; + reg = <0 0x20200000 0 0x1000>; + tune_value = <0x0005af33>; + usb-supply = <&vddusb>; + #address-cells = <1>; + #size-cells = <0>; + }; + sprd_thermal: thermal@402F0000{ + compatible = "sprd,sprd-thermal"; + id = <0>; + interrupts = <0 26 0x0>; + reg = <0 0x402F0000 0 0x1000>; + trip_points_active = <65 69 95 110>; + trip_points_lowoff = <0 57 60 80>; + trip_points_critical = <100>; + trip_num = <5>; + cool_num = <2>; + cooling-names = "thermal-cpufreq-0","thermal-cpufreq-1"; + }; + sprd_thermal1:thermal1@402F0000 { + compatible = "sprd,sprd-thermal"; + id = <1>; + interrupts = <0 26 0x0>; + reg = <0 0x402F0000 0 0x1000>; + trip_points_active = <100>; + trip_points_lowoff = <90>; + trip_points_critical = <100>; + trip_num = <2>; + }; + sprd_thermal2: thermal@40038280{ + compatible = "sprd,sprd-thermal"; + id = <2>; + interrupt-parent = <&adi>; + interrupts = <9 0x0>; + reg = <0 0x40038280 0 0x1000>; + trip_points_active = <110>; + trip_points_lowoff = <90>; + trip_points_critical = <110>; + trip_num = <2>; + }; + sprd_board_thermal: board-thermal{ + compatible = "sprd,board-thermal"; + id = <3>; + trip_points_active = <100>; + trip_points_lowoff = <90>; + trip_points_critical = <100>; + trip_num = <2>; + temp_inteval=<2>; + temp-support = <1>; + temp-adc-ch = <2>; + temp-adc-scale = <1>; + temp-adc-sample-cnt = <15>; + temp-table-mode = <1>; + temp-tab-size = <16>; + temp-tab-val = <1122 1094 1049 983 892 779 + 654 528 413 316 238 178 + 133 100 75 57>; + temp-tab-temp = <965 975 985 995 1005 1015 /* temperature + 1000,750 = 1000 + (-250)*/ + 1025 1035 1045 1055 1065 1075 + 1085 1095 1105 1115>; + + }; + adc: adc@40038300{ + compatible = "sprd,sprd-adc"; + reg = <0x40038300 0x1000>; + }; + i2c0: i2c@70500000{ + compatible = "sprd,i2c"; + interrupts = <0 11 0x0>; + reg = <0 0x70500000 0 0x1000>; + clock-names = "clk_i2c0"; + clocks = <&clk_i2c0>; + #address-cells = <1>; + #size-cells = <0>; + sensor_main@0x3c { + compatible = "sprd,sensor_main"; + reg = <0x3c>; + }; + sensor_sub@0x21 { + compatible = "sprd,sensor_sub"; + reg = <0x21>; + }; + }; + little_cpu_cooling{ + compatible = "sprd,sprd-cpu-cooling"; + id = <0>; + cluster = <0>; + max_freq = <1000000 1000000>; + max_core = <4 1>; + state_num = <2>; + }; + big_cpu_cooling{ + compatible = "sprd,sprd-cpu-cooling"; + id = <1>; + cluster = <1>; + max_freq = <1500000 1200000>; + max_core = <4 0>; + state_num = <2>; + }; + + i2c1: i2c@70600000{ + compatible = "sprd,i2c"; + interrupts = <0 12 0x0>; + reg = <0 0x70600000 0 0x1000>; + clock-names = "clk_i2c1"; + clocks = <&clk_i2c1>; + #address-cells = <1>; + #size-cells = <0>; + fairchild_fan53555@60{ + compatible = "fairchild,fairchild_fan53555"; + reg = <0x60>; + vddbigarm: vddbigarm { + regulator-name = "vddbigarm"; + regulator-default-microvolt = <1020000>;/*1050000*/ + regulator-step-microvolt = <10000>;/* 10 * 1000 uV */ + regulator-min-microvolt = <600000>;/* 600 * 1000 uV */ + regulator-max-microvolt = <1230000>;/*(600 + 10 * 0x3F) * 1000 uV*/ + }; + }; + }; + + i2c2: i2c@70700000{ + compatible = "sprd,i2c"; + interrupts = <0 13 0x0>; + reg = <0 0x70700000 0 0x1000>; + clock-names = "clk_i2c2"; + clocks = <&clk_i2c2>; + #address-cells = <1>; + #size-cells = <0>; + + lis3dh_acc@18{ + compatible = "ST,lis3dh_acc"; + reg = <0x18>; + poll_interval = <10>; + min_interval = <10>; + g_range = <0>; + axis_map_x = <1>; + axis_map_y = <0>; + axis_map_z = <2>; + negate_x = <0>; + negate_y = <1>; + negate_z = <0>; + }; + ltr_558als@23{ + compatible = "LITEON,ltr_558als"; + reg = <0x23>; + gpios = <&d_gpio_gpio 140 0>; + }; + epl259x_pls@49{ + compatible = "ELAN,epl259x_pls"; + reg = <0x49>; + gpios = <&d_gpio_gpio 140 0>; + }; + + }; + + i2c3: i2c@70800000{ + compatible = "sprd,i2c"; + interrupts = <0 14 0x0>; + reg = <0 0x70800000 0 0x1000>; + clock-names = "clk_i2c3"; + clocks = <&clk_i2c3>; + #address-cells = <1>; + #size-cells = <0>; + + focaltech_ts@38{ + compatible = "focaltech,focaltech_ts"; + reg = <0x38>; + gpios = <&d_gpio_gpio 145 0 + &d_gpio_gpio 144 0>; + vdd_name = "vdd18"; + virtualkeys = <580 1350 60 45 + 360 1350 60 45 + 160 1350 60 45>; + TP_MAX_X = <720>; + TP_MAX_Y = <1280>; + }; + msg2138_ts@26{ + compatible = "Mstar,msg2138_ts"; + reg = <0x26>; + gpios = <&d_gpio_gpio 145 0 + &d_gpio_gpio 144 0>; + vdd_name = "vdd28"; + virtualkeys = <256 1068 64 64 + 128 1068 64 64 + 192 1068 64 64>; + TP_MAX_X = <480>; + TP_MAX_Y = <800>; + }; + }; + + i2c4: i2c@70900000{ + compatible = "sprd,i2c"; + interrupts = <0 15 0x0>; + reg = <0 0x70900000 0 0x1000>; + clock-names = "clk_i2c4"; + clocks = <&clk_i2c4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi0: spi0@70a00000{ + compatible = "sprd,sprd-spi"; + interrupts = <0 7 0x0>; + reg = <0 0x70a00000 0 0x1000>; + clock-names = "clk_spi0"; + }; + + spi1: spi1@70b00000{ + compatible = "sprd,sprd-spi"; + interrupts = <0 8 0x0>; + reg = <0 0x70b00000 0 0x1000>; + clock-names = "clk_spi1"; + }; + + spi2: spi2@70c00000{ + compatible = "sprd,sprd-spi"; + interrupts = <0 9 0x0>; + reg = <0 0x70c00000 0 0x1000>; + clock-names = "clk_spi2"; + }; + + dma: dma-controller@20100000 { + compatible = "sprd,sharkl64-dma"; + #dma-cells = <1>; + #dma-channels = <64>; + sprd,aon-offset = <32>; + reg = <0 0x20100000 0 0x4000>, /* ap reg */ + <0 0x40100000 0 0x4000>; /* aon reg */ + interrupts = <0 50 0x0>, /* ap int */ + <0 70 0x0>; /* aon int */ + }; + + sprd-io-base { + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 1 0>; + ahb { + compatible = "sprd,ahb"; + reg = <0 0x20e00000 0 0x40000>; + }; + apbckg { + compatible = "sprd,apbckg"; + reg = <0 0x21500000 0 0x1000>; + }; + hwlock0 { + compatible = "sprd,hwlock0"; + reg = <0 0x20d00000 0 0x1000>; + }; + pub_apb { + compatible = "sprd,pub_apb"; + reg = <0 0x30020000 0 0x10000>; + }; + aon_apb { + compatible = "sprd,aon_apb"; + reg = <0 0x402e0000 0 0x40000>; + }; + pmu_apb { + compatible = "sprd,pmu_apb"; + reg = <0 0x402b0000 0 0x40000>; + }; + mm_ahb { + compatible = "sprd,mm_ahb"; + reg = <0 0x60d00000 0 0x10000>; + }; + mm_clk { + compatible = "sprd,mm_clk"; + reg = <0 0x60e00000 0 0x1000>; + }; + codecahb { + compatible = "sprd,codecahb"; + reg = <0 0x62000000 0 0x1000>; + }; + ap_ckg { + compatible = "sprd,ap_ckg"; + reg = <0 0x71200000 0 0x40000>; + }; + ap_apb { + compatible = "sprd,ap_apb"; + reg = <0 0x71300000 0 0x40000>; + }; + gpu_apb { + compatible = "sprd,gpu_apb"; + reg = <0 0x60100000 0 0x1000>; + }; + adi { + compatible = "sprd,adi"; + reg = <0 0x40030000 0 0x10000>; + }; + adi_slave { + compatible = "sprd,adi_slave"; + reg = <0 0x40038000 0 0x1000>; + }; + + mailbox { + compatible = "sprd,mailbox"; + reg = <0 0x400a0000 0 0x10000>; + }; + uart0 { + compatible = "sprd,uart0"; + reg = <0 0x70000000 0 0x1000>; + }; + uart1 { + compatible = "sprd,uart1"; + reg = <0 0x70100000 0 0x1000>; + }; + uart2 { + compatible = "sprd,uart2"; + reg = <0 0x70200000 0 0x1000>; + }; + uart3 { + compatible = "sprd,uart3"; + reg = <0 0x70300000 0 0x1000>; + }; + uart4 { + compatible = "sprd,uart4"; + reg = <0 0x70400000 0 0x1000>; + }; + axibm0 { + compatible = "sprd,axibm0"; + reg = <0 0x30040000 0 0x20000>; + interrupts = <0 86 0x0>; + }; + d_eic_gpio { + compatible = "sprd,d-eic-gpio"; + reg = <0 0x40210000 0 0x1000>; + }; + d_gpio_gpio { + compatible = "sprd,d-gpio-gpio"; + reg = <0 0x40280000 0 0x1000>; + }; + aon_dma { + compatible = "sprd,aon_dma"; + reg = <0 0x40100000 0 0x1000>; + interrupts = <0 50 0x0>; + }; + pwm { + compatible = "sprd,pwm"; + reg = <0 0x40260000 0 0x1000>; + }; + core { + compatible = "sprd,core"; + reg = <0 0x12000000 0 0x10000>; + }; + int { + compatible = "sprd,int"; + reg = <0 0x40200000 0 0x1000>; + }; + intc0 { + compatible = "sprd,intc0"; + reg = <0 0x71400000 0 0x1000>; + }; + intc1 { + compatible = "sprd,intc1"; + reg = <0 0x71500000 0 0x1000>; + }; + intc2 { + compatible = "sprd,intc2"; + reg = <0 0x71600000 0 0x1000>; + }; + intc3 { + compatible = "sprd,intc3"; + reg = <0 0x71700000 0 0x1000>; + }; + send_mbox { + compatible = "sprd,send_mbox"; + reg = <0 0x400a0000 0 0x1000>; + }; + recv_mbox { + compatible = "sprd,recv_mbox"; + reg = <0 0x400a8000 0 0x1000>; + }; + uidefuse { + compatible = "sprd,uidefuse"; + reg = <0 0x40240000 0 0x1000>; + }; + isp { + compatible = "sprd,isp"; + reg = <0 0x60a00000 0 0x8000>; + }; + csi2 { + compatible = "sprd,csi2"; + reg = <0 0x60c00000 0 0x1000>; + }; + ipi { + compatible = "sprd,ipi"; + reg = <0 0x402c0000 0 0x1000>; + }; + dcam { + compatible = "sprd,dcam"; + reg = <0 0x60800000 0 0x10000>; + }; + syscnt { + compatible = "sprd,syscnt"; + reg = <0 0x40230000 0 0x1000>; + }; + dma0 { + compatible = "sprd,dma0"; + reg = <0 0x20100000 0 0x4000>; + }; + pub { + compatible = "sprd,pub"; + reg = <0 0x30020000 0 0x10000>; + }; + pin { + compatible = "sprd,pin"; + reg = <0 0x402a0000 0 0x1000>; + }; + aonckg { + compatible = "sprd,aonckg"; + reg = <0 0x402d0000 0 0x1000>; + }; + lpddr2 { + compatible = "sprd,lpddr2"; + reg = <0 0x30000000 0 0x1000>; + }; + }; + + sprd_dcam { + compatible = "sprd,sprd_dcam"; + interrupts = <0 45 0>; + reg = <0 0x60800000 0 0x100000>; + clock-names = "clk_mm_i","clk_dcam"; + clocks = <&clk_mm>, <&clk_dcam>; + }; + + sprd_scale { + compatible = "sprd,sprd_scale"; + }; + + sprd_rotation { + compatible = "sprd,sprd_rotation"; + }; + + sprd_sensor { + compatible = "sprd,sprd_sensor"; + reg = <0 0x60c00000 0 0x100000>; + gpios = <&d_gpio_gpio 44 0 /*main reset*/ + &d_gpio_gpio 46 0 /*main powerdown*/ + &d_gpio_gpio 45 0 /*sub reset*/ + &d_gpio_gpio 47 0 + &d_gpio_gpio 0 0 /*main core voltage*/ + &d_gpio_gpio 0 0 + &d_gpio_gpio 0 0 + &d_gpio_gpio 0 0>; /*sub powerdown*/ + clock-names ="clk_mm_i","clk_sensor","clk_ccir","clk_dcam","clk_dcam_mipi"; + clocks = <&clk_mm>,<&clk_sensor>,<&clk_ccir>,<&clk_dcam>,<&clk_dcam_mipi>; + }; + + sprd_isp { + compatible = "sprd,sprd_isp"; + reg = <0 0x60a00000 0 0x100000>; + clock-names = "clk_mm_i","clk_isp"; + clocks = <&clk_mm>, <&clk_isp>; + }; + + sprd_dma_copy { + compatible = "sprd,sprd_dma_copy"; + }; + + fb0: fb@20800000 { + compatible = "sprd,sprdfb"; + reg = <0 0x20800000 0 0x1000>, + <0 0x21800000 0 0x1000>; + interrupts = <0 46 0x0>, + <0 48 0x0>, + <0 49 0x0>; + clock-names = "dispc_clk_parent", "dispc_dbi_clk_parent", "dispc_dpi_clk_parent", "dispc_emc_clk_parent", "dispc_clk", "dispc_dbi_clk", "dispc_dpi_clk", "dispc_emc_clk", "fb_spi_clock", "fb_spi_clock_parent"; + clocks = <&clk_256m>, <&clk_256m>, <&clk_384m>, <&clk_aon_apb>, <&clk_dispc0>, <&clk_dispc0_dbi>, <&clk_dispc0_dpi>, <&clk_disp_emc>, <&clk_spi2>, <&ext_26m>; + clock-src = <256000000 256000000 384000000>; + dpi_clk_div = <7>; + sprd,fb_use_reservemem; + sprd,fb_mem = <0x9ED74000 0xA8C000>; + }; + + gsp@20a00000 { + compatible = "sprd,gsp"; + reg = <0 0x20a00000 0 0x1000>; + interrupts = <0 51 0x0>; + clock-names = "clk_gsp0", "clk_gsp_emc", "clk_gsp_parent", "clk_aon_apb"; + clocks = <&clk_gsp0>, <&clk_gsp_emc>, <&clk_256m>, <&clk_aon_apb>; + gsp_mmu_ctrl_base = <0x20b08000>; + }; + + /*sharLT8 gspn initializer */ + gspn:gspn@0x20A00000 { + compatible = "sprd,gspn"; + reg = <0x71500000 0x1000>, // arm interrupt ctl reg + <0x20E00000 0x1000>, //gspn module enable ctl reg base + <0x20E00004 0x1000>, //gspn module reset ctl reg base + <0x20E0304C 0x1000>, //[0] gsp/gspn select reg base, 0:gsp; 1:gspn + <0x402e00fc 0x1000>; //[0] ap chip id reg addr + gspn0:gspn@0x20A00000 { + core_id = <0>; + gspn_en_rst_bit = <0x00000008>;//bit3 + mmu_en_rst_bit = <0x00000008>;//bit3 + auto_gate_bit = <0x00000100>;//bit8 + force_gate_bit = <0x00000200>;//bit9 + emc_en_bit = <0x00000008>;//bit3 + reg = <0x20A00000 0x1000>, //gspn module ctl reg + <0x20B10000 0x1000>, //iommu ctl reg,64MB,page size 4KB + <0x21500028 0x1000>, //gspn clock source select ctl reg base + <0x20E00010 0x1000>, //gspn clock auto-gate/force-gate ctl reg base + <0x20E00000 0x1000>; //gspn emc clock ctl reg base + interrupts = <0 51 0x0>; + clock-names = "clk_gsp", "clk_gsp_emc", "clk_gsp_parent", "clk_aon_apb"; + //clocks = <&clk_gsp>, <&clk_gsp_emc>, <&clk_256m>, <&clk_aon_apb>; + }; + }; + + sprd_fm: sprd_fm@40270000{ + compatible = "sprd,sprd_fm"; + reg = <0 0x40270000 0 0x1000>; + }; + + sipc: sipc@0x87800000 { + compatible = "sprd,sipc"; + reg = <0 0x87800000 0 0x5B0000>; /* <SMEM SIZE>*/ + //#interrupt-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + ranges =<0x09600000 0 0x89600000 0x4600000>, + <0x07800000 0 0x87800000 0x5B0000>, + <0x0dbff000 0 0x8dbff000 0x1000>; + sipc_lte@0x09600000 { + sprd,name = "sipc-lte"; + sprd,dst = <5>; + /* it's unnecessary to config IPI info upon mailbox arch */ + mailbox,core = <7>; + reg = <0x09600000 0x4600000> , /* <CP_start_addr size> */ + <0x07800000 0x5B0000>, /* <SMEM_phy_addr total_size> */ + <0x0dbff000 0x1000>; /* smsg ring buffer <base size> */ + }; + }; + + sctrl_pmic{ + compatible = "sprd,sctrl"; + sprd,name = "sctrl_pmic"; + sprd,dst = <6>; + sprd,channel= <1>; + sprd,ringnr = <1>; + /* it's unnecessary to config IPI info upon mailbox arch */ + mailbox,core = <1>; + sprd,ringbase = <0x5000b000>; /*SMSG ring mem base phy address*/ + sprd,size-rxbuf = <0x0400>; /* 2*1024*/ + sprd,size-txbuf = <0x0400>; /* 2*1024 */ + }; + + saudio_lte{ + compatible = "sprd,saudio"; + sprd,saudio-dst-id = <5>; /* SIPC_ID_LTE */ + sprd,ctrl_channel = <10>; /* SMSG_CH_VBC */ + sprd,playback_channel = <11>; /* SMSG_CH_PLAYBACK */ + sprd,capture_channel = <12>; /* SMSG_CH_CAPTURE */ + sprd,monitor_channel = <13>; /*SMSG_CH_MONITOR_AUDIO */ + sprd,saudio-names = "saudiolte"; + }; + + saudio_voip{ + compatible = "sprd,saudio"; + sprd,saudio-dst-id = <5>; /* SIPC_ID_LTE */ + sprd,ctrl_channel = <14>; /* SMSG_CH_CTRL_VOIP */ + sprd,playback_channel = <15>; /* SMSG_CH_PLAYBACK_VOIP */ + sprd,capture_channel = <16>; /* SMSG_CH_CAPTURE_VOIP */ + sprd,monitor_channel = <17>; /*SMSG_CH_MONITOR_VOIP */ + sprd,saudio-names = "saudiovoip"; + }; + + /* LTE modem virtual devices */ + spipe_lte { + compatible = "sprd,spipe"; + sprd,name = "spipe_lte"; + sprd,dst = <5>; + sprd,channel = <4>; + sprd,ringnr = <9>; + sprd,size-rxbuf = <0x1000>; /* 4*1024 */ + sprd,size-txbuf = <0x1000>; /* 4*1024 */ + }; + + slog_lte { + compatible = "sprd,spipe"; + sprd,name = "slog_lte"; + sprd,dst = <5>; + sprd,channel = <5>; + sprd,ringnr = <1>; + sprd,size-rxbuf = <0x40000>; /* 256*1024*/ + sprd,size-txbuf = <0x8000>; /* 32*1024 */ + }; + + sdiag_lte { + compatible = "sprd,spipe"; + sprd,name = "sdiag_lte"; + sprd,dst = <5>; + sprd,channel = <21>; + sprd,ringnr = <1>; + sprd,size-rxbuf = <0x40000>; /* 256*1024*/ + sprd,size-txbuf = <0x8000>; /* 32*1024 */ + }; + + stty_lte { + compatible = "sprd,spipe"; + sprd,name = "stty_lte"; + sprd,dst = <5>; + sprd,channel = <6>; + sprd,ringnr = <32>; + sprd,size-rxbuf = <0x0800>; /* 2*1024*/ + sprd,size-txbuf = <0x0800>; /* 2*1024 */ + }; + + seth0_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte0"; + sprd,dst = <5>; + sprd,channel = <7>; + sprd,blknum = <256>; + }; + + seth1_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte1"; + sprd,dst = <5>; + sprd,channel = <8>; + sprd,blknum = <256>; + }; + + seth2_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte2"; + sprd,dst = <5>; + sprd,channel = <9>; + sprd,blknum = <256>; + }; + + seth3_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte3"; + sprd,dst = <5>; + sprd,channel = <18>; + sprd,blknum = <256>; + }; + + seth4_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte4"; + sprd,dst = <5>; + sprd,channel = <19>; + sprd,blknum = <256>; + }; + + seth5_lte { + compatible = "sprd,seth"; + sprd,name = "seth_lte5"; + sprd,dst = <5>; + sprd,channel = <20>; + sprd,blknum = <256>; + }; + scproc_arm7: scproc@0x50800000 { + compatible = "sprd,scproc"; + sprd,name = "cppmic"; + sprd,ctrl-reg = <0x114 0xff 0xb0 0xff>; /* <shut_down deep_sleep reset get_status> */ + sprd,ctrl-mask = <0x01 0xfffffffe 0x100 0xf0000>; /* masks <> */ + sprd,iram-data = <0xe59f0000 0xe12fff10 0x0>; /* 3rd param equals modem_addr*/ + reg = <0 0x50800000 0 0x8000>, /* <CP_start_addr total_size> = <+128M 26M> */ + <0 0x50800000 0 0x0>, /* <iram1_base size> */ + <0 0x402e0000 0 0x400>, /* <aon_apb_base size> */ + <0 0x402b0000 0 0x100>, /* <pmu_base size> */ + <0 0x402b0000 0 0x100>, /* <pmu_base size> */ + <0 0x402b0000 0 0x100>; /* <pmu_base size> */ + #address-cells = <1>; + #size-cells = <1>; + /* segnr=1 */ + ranges = <0x0 0 0x50800000 0x8000>; + modem@0x0 { + cproc,name = "modem"; + reg = <0x0 0x8000>; /* <modem_addr size> */ + }; + }; + + scproc_cp1: scproc@0x89600000 { + compatible = "sprd,scproc"; + sprd,name = "cptl"; + sprd,ctrl-reg = <0x0c 0xff 0xb0 0x78>; /* <shut_down deep_sleep reset get_status> */ + sprd,ctrl-mask = <0x00300000 0x10000000 0x02 0x1>; /* masks <> */ + sprd,iram-data = <0xe59f0000 0xe12fff10 0x8ae00000>; /* 3rd param equals modem_addr*/ + reg = <0 0x89600000 0 0x5300000>, /* <CP_start_addr total_size> = <+128M 83M> */ + <0 0x50001000 0 0x0c>, /* <iram1_base size> */ + <0 0x402e0000 0 0x100>, /* <aon_apb_base size> */ + <0 0x402b0000 0 0x100>, /* <pmu_base size> */ + <0 0x402b0000 0 0x100>, /* <pmu_base size> */ + <0 0x402b0000 0 0x100>; /* <pmu_base size> */ + interrupts = <0 84 0x0>; /* cp1_wdg_int */ + #address-cells = <1>; + #size-cells = <1>; + /* segnr=4 */ + ranges = <0x1800000 0 0x8ae00000 0x02E00000>, + <0x0020000 0 0x89620000 0x002E0000>, + <0x0300000 0 0x89900000 0x1C0000>, + <0x4900000 0 0x8df00000 0xA00000>; + modem@0x1800000 { + cproc,name = "modem"; + reg = <0x1800000 0x02E00000>; /* <modem_addr size> */ + }; + dsp@0x20000 { + cproc,name = "tgdsp"; + reg = <0x20000 0x002e0000>; /* <dsp_addr size>*/ + }; + dsp@0x300000 { + cproc,name = "ldsp"; + reg = <0x300000 0x1c0000>; /* <dsp_addr size>*/ + }; + modem@0x4900000 { + cproc,name = "warm"; + reg = <0x4900000 0xA00000>; /* <modem_addr size>*/ + }; + }; + + itm_wlan{ + compatible = "sprd,itm_wlan"; + }; + + dmac: dmac@20100000 { + compatible = "sprd,sprd-dma"; + interrupts = <0 50 0x0>; + reg = <0 0x20100000 0 0x4000>; + }; + + gpu: gpu@60000000 { + compatible = "sprd,mali-midgard"; + reg = <0 0x60000000 0 0x4000>; + interrupts = <0 39 0x4>, <0 39 0x4>, <0 39 0x4>; + interrupt-names = "JOB", "MMU", "GPU"; + + clocks = <&clk_gpu_axi>,<&clk_gpu>,<&clk_153m6>, <&clk_192m>, <&clk_256m>, <&clk_307m2>, <&clk_384m>, <&clk_gpll>; + clock-names = "clk_gpu_axi","clk_gpu","clk_153m6","clk_192m","clk_256m","clk_307m2","clk_384m","clk_gpll"; + + freq-list-len = <4>; + freq-lists = <153600 2 1>, <256000 4 1>, <384000 6 1>, <512000 7 1>; + freq-default = <3>; + freq-9 = <3>; + freq-8 = <3>; + freq-7 = <1>; + freq-5 = <0>; + freq-range-max = <3>; + freq-range-min = <0>; + }; + + ion { + compatible = "sprd,ion-sprd"; + #address-cells = <1>; + #size-cells = <0>; + + sprd,ion-heap@1 { + reg = <1>; /* SYSTEM */ + reg-names = "ion_heap_system"; + sprd,ion-heap-type = <0>; /* SYSTEM */ + sprd,ion-heap-mem = <0x0 0x0>; + }; + + sprd,ion-heap@2 { + reg = <2>; /* MM */ + reg-names = "ion_heap_carveout_mm"; + sprd,ion-heap-type = <0>; /* carveout mm */ + sprd,ion-heap-mem = <0x9864F000 0x7100000>; + }; + + sprd,ion-heap@3 { + reg = <3>; /* OVERLAY */ + reg-names = "ion_heap_carveout_overlay"; + sprd,ion-heap-type = <2>; /* CARVEOUT */ + sprd,ion-heap-mem = <0x9F800000 0x800000>; /* 480*854*4*2, 1M alignment */ + }; + + sprd,ion-heap@4 { + reg = <4>; /* FB */ + reg-names = "ion_heap_carveout_fb"; + sprd,ion-heap-type = <2>; /* CARVEOUT */ + sprd,ion-heap-mem = <0x9ED74000 0xA8C000>; + }; + }; + + sprd_iommu0: sprd_iommu@20b00000 { + compatible = "sprd,sprd_iommu";//gsp + func-name = "sprd_iommu_gsp"; + reg = <0 0x10000000 0 0x2000000>, //iova + <0 0x20b00000 0 0x8000>, //pgt + <0 0x20b08000 0 0x8000>; //ctrl_reg + reg_name = "iova","pgt","ctrl_reg"; + clock-names = "clk_gsp_emc","clk_153m6","clk_gsp0"; + clocks = <&clk_gsp_emc>, <&clk_153m6>,<&clk_gsp0>; + status = "ok"; + }; + + sprd_iommu1: sprd_iommu@60f00000 { + compatible = "sprd,sprd_iommu";//mm + func-name = "sprd_iommu_mm"; + reg = <0 0x20000000 0 0x8000000>, //iova + <0 0x60f00000 0 0x20000>, //pgt + <0 0x60f20000 0 0x2000>; //ctrl_reg + reg_name = "iova","pgt","ctrl_reg"; + clock-names = "clk_mmu","clk_mm_i"; + clocks = <&clk_mmu>,<&clk_mm>; + status = "ok"; + }; + + sprd_vsp: sprd_vsp@60900000{ + compatible = "sprd,sprd_vsp"; + reg = <0 0x60900000 0 0xc000>; + interrupts = <0 43 0x0>; + clock-names = "clk_mm_i", "clk_vsp", "clk_parent_0", "clk_parent_1", "clk_parent_2", "clk_parent_3"; + clocks = <&clk_mm>, <&clk_vsp>, <&clk_307m2>, <&clk_256m>, <&clk_128m>, <&clk_96m>; + clock-parent-info = <2 4>; + version = <7>; + }; + + sprd_vpp@61000000{ + compatible = "sprd,sprd_vpp"; + reg = <0 0x61000000 0 0x4000>; + interrupts = <0 43 0x0>; + clock-names = "clk_mm_i","clk_vpp","clk_256m","clk_153m6","clk_128m","clk_96m"; + clocks = <&clk_mm>, <&clk_vpp>, <&clk_256m>, <&clk_153m6>, <&clk_128m>, <&clk_96m>; + clock-parent-info = <2 4>; + }; + + sprd_coda7l@62100000{ + compatible = "sprd,sprd_coda7l"; + reg = <0 0x62100000 0 0x4000>; + interrupts = <0 43 0x0>; + clock-names = "clk_mm_i","clk_coda7_axi","clk_coda7_cc","clk_coda7_apb", + "clk_192m","clk_153m6","clk_128m","clk_76m8", + "clk_128m","clk_96m","clk_76m8","ext_26m"; + clocks = <&clk_mm>, <&clk_coda7_axi>, <&clk_coda7_cc>, <&clk_coda7_apb>, + <&clk_192m>, <&clk_153m6>, <&clk_128m>, <&clk_76m8>, + <&clk_128m>, <&clk_96m>, <&clk_76m8>, <&ext_26m>; + clock-parent-info = <4 4>; + power-regs-info = <0x402b0044 0 0x402b00c8 0xf0000000>; + }; + + sprd_jpg { + compatible = "sprd,sprd_jpg"; + reg = <0 0x60b00000 0 0x8000>; + interrupts = <0 42 0x0>; + clock-names = "clk_mm_i","clk_jpg"; + clocks = <&clk_mm>, <&clk_jpg>; + }; + sprd_bm { + compatible = "sprd,sprd_bm"; + reg = <0 0x30040000 0 0xA0000 + 0 0x20F00000 0 0x300000>; + interrupts = <0 86 0x0>; + sprd,bm_status = <1>; + sprd,bm_count = <10 11>; + sprd,cpu_chn = <0 1>; + sprd,disp_chn = <1 1>; + sprd,gpu_chn = <2 1>; + sprd,ap_zip_chn = <3 1>; + sprd,mm_chn = <4 1>; + sprd,cp0_arm0_1_chn = <5 1>; + sprd,cp0_dsp_chn = <6 0>; + sprd,cp1_lte_chn = <7 1>; + sprd,cp1_dsp_chn = <8 1>; + sprd,cp1_arm_chn = <9 1>; + sprd,ap_dap_chn = <0 0>; + sprd,ap_cpu_chn = <0 1>; + sprd,ap_dma_r_chn = <0 2>; + sprd,ap_dma_w_chn = <0 3>; + sprd,ap_sdio_0_chn = <1 0>; + sprd,ap_sdio_1_chn = <1 1>; + sprd,ap_sdio_2_chn = <1 2>; + sprd,ap_emmc_chn = <1 3>; + sprd,ap_nandc_chn = <2 0>; + sprd,ap_otg_chn = <2 1>; + sprd,ap_hsic_chn = <2 2>; + }; + wdt@40290000 { + compatible = "sprd,sprd-wdt"; + reg = <0 0x40290000 0 0x1000>, + <0 0x40310000 0 0x1000>; + interrupts = <0 124 0x0>; + }; + sprd-marlin { + compatible = "sprd,marlin"; + gpios = <&d_gpio_gpio 97 0 /*marlin gpio0 */ + &d_gpio_gpio 132 0 /*marlin gpio1 */ + &d_gpio_gpio 133 0 /*marlin gpio2 */ + &d_gpio_gpio 94 0 /*marlin gpio3 */ + &d_gpio_gpio 130 0>; /*marlin reset*/ + cp-rfctl-offset = <0x244>; /*coex func. marlin gpio3*/ + vdd-download = "vddcon"; /*vdd 1.6v*/ + vdd-pa = "vddwifipa"; /*vdd 3.3v*/ + clk-name = "clk_aux0"; /*clk 32k*/ + sdhci-name = "sdio_wifi"; + }; + +}; + +&vbc_r2p0 { + status = "okay"; +}; + +&sprd_codec { + status = "okay"; + sprd,audio_power_ver = <4>; +}; + +&i2s0 { + sprd,config_type = "pcm"; + sprd,slave_timeout = <0xF11>; + sprd,_hw_port = <0>; + sprd,fs = <8000>; + sprd,bus_type = <1>; + sprd,rtx_mode = <3>; + sprd,byte_per_chan = <1>; + sprd,slave_mode = <0>; + sprd,lsb = <0>; + sprd,lrck = <0>; + sprd,low_for_left = <1>; + sprd,clk_inv = <0>; + sprd,pcm_short_frame = <1>; + sprd,pcm_slot = <0x1>; + sprd,pcm_cycle = <1>; + sprd,tx_watermark = <12>; + sprd,rx_watermark = <20>; + status = "okay"; +}; + +&i2s1 { + status = "okay"; +}; + +&i2s2 { + status = "okay"; +}; + +&i2s3 { + status = "okay"; +}; + +&i2s_sound { + sprd,i2s = <&i2s0>, <&i2s1>, <&i2s2>, <&i2s3>; +}; + +&sprd_battery { + gpios = <&a_eic_gpio 0 0 /* chg int */ + &a_eic_gpio 4 0 /* cv state */ + &a_eic_gpio 6 0 /* chg ovi */ + &a_eic_gpio 9 0>; /* battery detect */ + + chg-end-vol-h = <4375>; + chg-end-vol-pure = <4350>; + chg-end-vol-l = <4340>; + chg-bat-safety-vol = <4430>; + rechg-vol = <4260>; + + fgu-mode = <0>; + alm-soc = <5>; + alm-vol = <3500>; + soft-vbat-uvlo = <3100>; + rint = <200>; + cnom = <2100>; + rsense-real = <118>; + rsense-spec = <200>; + relax-current = <50>; + fgu-cal-ajust = <0>; + ocv-tab-size = <21>; + ocv-tab-vol = <4318 4254 4198 4145 4094 4052 3987 3955 3902 3865 3838 3817 3800 3785 3769 3752 3733 3706 3691 3588 3400>; + ocv-tab-cap = <100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0>; +}; diff --git a/arch/arm64/boot/dts/sprd_ss_sharklt8.dts b/arch/arm64/boot/dts/sprd_ss_sharklt8.dts new file mode 100644 index 00000000..6e592ae9 --- /dev/null +++ b/arch/arm64/boot/dts/sprd_ss_sharklt8.dts @@ -0,0 +1,459 @@ +/* + * SPREADTRUM Ltd.clock-cells +sprd_rotation + * + * SharkLT8 5mod refphone DTS + */ + +/dts-v1/; + +/* memory reserved for SMEM */ +/memreserve/ 0x87800000 0x5B0000; /* Offset:120M, Size:5M+256K */ + +/* memory reserved for WARM modem */ +/memreserve/ 0x8DC00000 0xD00000; /* Offset:220M, Size:13M*/ + +/* memory reserved for LTE modem */ +/memreserve/ 0x89600000 0x4600000; /* Offset:150M, Size:70M*/ + +/* memory reserved for fb */ +/memreserve/ 0x9ED74000 0xA8C000; /* 1280*720*4*3, 4K alignment*/ + +/* memory reserved for ION */ +/memreserve/ 0x9F800000 0x800000; /* 1280*720*4*2, 1M alignment*/ + +/* memory reserved for smp */ +/memreserve/ 0x9F700000 0x1000; /* size 4K*/ + +/include/ "sprd-scx35lt8_common.dtsi" + +/ { + chosen { + bootargs = "earlyprintk=sprd_uart,0x70100000 loglevel=1"; + }; + + aliases { + i2c_gpio5 = &i2c_gpio5; + i2c_gpio6 = &i2c_gpio6; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0 0x80000000 0 0x60000000>; + }; + + pinctrl { + compatible = "sprd,pinctrl"; + reg = <0 0x402a0000 0 0x1000>; + pwr_domain = "vdd18", + "vdd18", + "vddsim0", + "vddsim1", + "vdd18", + "vddsdio", + "vdd18"; + ctrl_desc = <0x10 0 1 + 0x10 1 1 + 0x10 2 1 + 0x10 3 1 + 0x10 4 1 + 0x10 5 1 + 0x10 6 1>; + }; + + sec-fuelgauge { + compatible = "samsung,sec-fuelgauge"; + capacity-max = <1000>; + capacity-max-margin = <1000>; + capacity-min = <10>; + fg-irq-attr = <0>; + fuel-alert-soc = <1000>; + temp_adc_channel = <0>; + chg_bat_safety_vol = <4600>; + soft_vbat_uvlo = <3050>; + vmode = <0>; /* 1=Voltage mode, 0=mixed mode */ + alm_soc = <5>; /* SOC alm level %*/ + alm_vbat = <3500>; /* Vbat alm level mV*/ + rint = <160>; /*battery internal impedance*/ + cnom = <2000>; /* nominal capacity in mAh */ + rsense_real = <206>; /* sense resistor 0.1mOhm from real environment*/ + rsense_spec = <200>; /* sense resistor 0.1mOhm from specification*/ + relax_current = <50>; /* current for relaxation in mA (< C/20) */ + cal_ajust = <0>; /* ajust calibration data */ + ocv_table = <4355 100 + 4332 95 + 4277 90 + 4221 85 + 4166 80 + 4113 75 + 4063 70 + 4018 65 + 3977 60 + 3933 55 + 3881 50 + 3850 45 + 3826 40 + 3807 35 + 3791 30 + 3778 25 + 3762 20 + 3742 15 + 3711 10 + 3683 5 + 3400 0>; + + sprd_fgu: sprd_fgu{ + compatible = "sprd,sprd_fgu"; + interrupt-parent = <&adi>; + interrupts = <4 0x0>; + }; + }; + + sec-battery { + compatible = "samsung,sec-battery"; + battery,vendor = "SDI SDI"; + battery,charger_name = "sec-charger"; + battery,fuelgauge_name = "sec-fuelgauge"; + battery,technology = <2>; /* POWER_SUPPLY_TECHNOLOGY_LION */ + battery,chip_vendor = "SPRD"; + battery,temp_adc_type = <1>; /* SEC_BATTERY_ADC_TYPE_AP */ + battery,polling_time = <10 30 30 30 3600>; + battery,adc_check_count = <5>; + battery,cable_check_type = <5>; /* SEC_BATTERY_CABLE_CHECK_PSY */ + battery,cable_source_type = <3>; /* SEC_BATTERY_CABLE_SOURCE_EXTERNAL */ + battery,event_waiting_time = <600>; + battery,polling_type = <1>; /* SEC_BATTERY_MONITOR_ALARM */ + battery,monitor_initial_count = <3>; + battery,battery_check_type = <5>; /* SEC_BATTERY_CHECK_CHARGER */ + battery,check_count = <0>; + battery,check_adc_max = <1440>; + battery,check_adc_min = <0>; + battery,ovp_uvlo_check_type = <3>; /* SEC_BATTERY_OVP_UVLO_CHGPOLLING */ + battery,thermal_source = <2>; /* SEC_BATTERY_THERMAL_SOURCE_ADC */ + battery,temp_table_adc = <501 615 738 795 846 956 1065 1088 1180 1307 1392 1477 1627 1777 1922 2098 + 2144 2182 2212 2260 2302 2452 2555>; + battery,temp_table_data = <700 650 600 580 550 500 460 450 400 350 300 250 200 150 100 + 50 20 0 (-20) (-50) (-70) (-150) (-200)>; + battery,temp_check_type = <2>; /* SEC_BATTERY_TEMP_CHECK_TEMP */ + battery,temp_check_count = <1>; + battery,temp_high_threshold_event = <600>; + battery,temp_high_recovery_event = <460>; + battery,temp_low_threshold_event = <(-50)>; + battery,temp_low_recovery_event = <0>; + battery,temp_high_threshold_normal = <600>; + battery,temp_high_recovery_normal = <460>; + battery,temp_low_threshold_normal = <(-50)>; + battery,temp_low_recovery_normal = <0>; + battery,temp_high_threshold_lpm = <600>; + battery,temp_high_recovery_lpm = <460>; + battery,temp_low_threshold_lpm = <(-50)>; + battery,temp_low_recovery_lpm = <0>; + battery,full_check_type = <7>; /* SEC_BATTERY_FULLCHARGED_CHGPSY */ + battery,full_check_type_2nd = <3>; /* SEC_BATTERY_FULLCHARGED_TIME */ + battery,full_check_count = <1>; + battery,chg_gpio_full_check = <0>; + battery,chg_polarity_full_check = <1>; + battery,full_condition_type = <13>; + battery,full_condition_soc = <95>; + battery,full_condition_vcell = <4200>; + battery,recharge_check_count = <1>; + battery,recharge_condition_type = <4>; /* SEC_BATTERY_RECHARGE_CONDITION_VCELL */ + battery,recharge_condition_soc = <95>; + battery,recharge_condition_vcell = <4350>; + battery,charging_total_time = <21600>; + battery,recharging_total_time = <5400>; + battery,charging_reset_time = <0>; + + /* Charger */ +// charger,vbus_ctrl_gpio = <&d_gpio_gpio 64 0x00>; + battery,input_current_limit = <700 460 460 700 460 700 700 460 460 700 700 700 700 460 700 300 700 700 300 700 700 460 460>; + battery,fast_charging_current = <975 0 975 975 975 975 975 975 0 975 975 975 975 (-1) 975 975 975 975 975 975 975 0 0>; + battery,full_check_current_1st = <175 0 175 175 175 175 175 175 0 175 175 175 175 0 175 175 175 175 175 175 175 0 0>; + battery,full_check_current_2nd = <1800 0 1800 1800 1800 1800 1800 1800 0 1800 1800 1800 1800 0 1800 1800 1800 1800 1800 1800 1800 0 0>; + }; + + i2c_gpio5: i2c_gpio@1 { /* cam af eep */ + compatible = "i2c-gpio"; + #address-cells = <1>; + #size-cells = <0>; + gpios = <&d_gpio_gpio 41 0 /* sda */ + &d_gpio_gpio 40 0 >; /* scl */ + i2c-gpio,delay-us = <10>; /* ~100 kHz */ + i2c-gpio,timeout-ms = <0>; + status = "okay"; + + sensor_i2c_vcm0@6A { + compatible = "sprd,sensor_i2c_vcm0"; + reg = <0x6A>; + }; + }; + + i2c_gpio6: i2c_gpio@11 { /* LCD BL */ + compatible = "i2c-gpio"; + reg = <0x11>; + //ti,en-gpio = <&gpio0 54 0>; /* GPIO for EN pin */ + #address-cells = <1>; + #size-cells = <0>; + gpios = <&d_gpio_gpio 16 0 /* sda */ + &d_gpio_gpio 15 0 >; /* scl */ + i2c-gpio,delay-us = <10>; /* ~100 kHz */ + i2c-gpio,timeout-ms = <0>; + status = "okay"; + + lm3632@11 { + compatible = "ti,lm3632"; + reg = <0x11>; + /* GPIO for EN pin */ +// ti,en-gpio = <&d_gpio_gpio 54 0>; + /* Backlight mode is PWM, two strings used */ + backlight { + compatible = "ti,lm3632-backlight"; + bl-name = "sprd_backlight"; + full-strings-used; + pwm-period = <10000>; + pwm-max-brightness = <1637>; /* 20mA */ + /* PWM controller for lm3632 backlight */ +// pwms = <&pwm3943 0 10000>; + pwm-names = "lm3632-backlight"; + }; + }; + }; + + + sprd_pwm_bl { + compatible = "sprd,sprd_pwm_bl"; + brightness_max = <255>; + brightness_min = <0>; + pwm_index = <2>; + //gpio_ctrl_pin = <54>; + gpio_active_level = <0>; + reg =<0 0x40260000 0 0xf>; + }; + +/* + sprd_backlight { + compatible = "sprd,sprd_backlight"; + start = <3>; + end = <3>; + flags = <0x100>; + }; +*/ + + keypad@40250000{ + compatible = "sprd,sci-keypad"; + reg = <0 0x40250000 0 0x1000>; + gpios = <&a_eic_gpio 2 0>; + interrupts = <0 36 0x0>; + sprd,keypad-num-rows = <2>; + sprd,keypad-num-columns = <2>; + sprd,keypad-rows-choose-hw = <0x30000>; + sprd,keypad-cols-choose-hw = <0x300>; + sprd,debounce_time = <5000>; + linux,keypad-no-autorepeat; + sprd,support_long_key; + + key_volume_up { + keypad,row = <0>; + keypad,column = <0>; + linux,code = <115>; + }; + + key_home { + keypad,row = <0>; + keypad,column = <1>; + linux,code = <102>; + }; + }; + + gps { + compatible = "lsi,s5n6420"; + gps-pwr-en = <&d_gpio_gpio 11 0>; /*GPS_PWON*/ + gps-reset = <&d_gpio_gpio 134 0>; /*GPS_RESET*/ + gps-regulator = "vddcamd"; + }; + + sprd_fm: sprd_fm@40270000{ + compatible = "sprd,sprd_fm"; + reg = <0 0x40270000 0 0x1000>; + }; + +/* + itm_wlan{ + compatible = "sprd,itm_wlan"; + }; +*/ + + sprd-marlin { + compatible = "sprd,marlin"; + gpios = <&d_gpio_gpio 14 0 /*marlin gpio0 */ + &d_gpio_gpio 130 0 /*marlin gpio1 */ + &d_gpio_gpio 133 0 /*marlin gpio2 */ + &d_gpio_gpio 94 0 /*marlin gpio3 */ + &d_gpio_gpio 131 0>; /*marlin reset*/ + cp-rfctl-offset = <0x244>; /*coex func. marlin gpio3*/ + vdd-download = "vddcon"; /*vdd 1.6v*/ + vdd-pa = "vddwifipa"; /*vdd 3.3v*/ + clk-name = "clk_aux0"; /*clk 32k*/ + sdhci-name = "sdio_wifi"; + }; +}; + +&adi { +/* + keyboard_backlight { + compatible = "sprd,keyboard-backlight"; + }; + + leds_sprd_bltc_rgb { + compatible = "sprd,sprd-leds-bltc-rgb"; + reg = <0x440 0x40>, + <0x800 0xff>; + }; +*/ + + sprd_eic_keys { + compatible = "sprd,sprd-eic-keys"; + input-name = "sprd-eic-keys"; + + key_volumedown { + label = "Volumeup Key"; + linux,code = <114>; + gpios = <&a_eic_gpio 10 0>; + debounce-interval = <2>; + gpio-key,wakeup; + }; + }; + + headset_sprd_sc2723 { + compatible = "sprd,headset_sprd_sc2723"; + gpio_switch = <0>; + gpio_detect = <92>; + gpio_button = <97>; + irq_trigger_level_detect = <0>; + irq_trigger_level_button = <0>; + adc_threshold_3pole_detect = <300>; + adc_threshold_4pole_detect = <3270>; + irq_threshold_buttont = <1>; + voltage_headmicbias = <3000000>; + nbuttons = <3>; + + headset_buttons_media { + adc_min = <0>; + adc_max = <550>; + code = <226>; + type = <0>; + }; + + headset_buttons_up { + adc_min = <551>; + adc_max = <1114>; + code = <115>; + type = <0>; + }; + + headset_buttons_down { + adc_min = <1115>; + adc_max =<3000>; + code = <114>; + type = <0>; + }; + }; +}; + +&i2c0 { + sensor_main@0x3c { + compatible = "sprd,sensor_main"; + reg = <0x3c>; + }; + + sensor_sub@0x21 { + compatible = "sprd,sensor_sub"; + reg = <0x21>; + }; +}; + +&i2c1 { + fairchild_fan53555@60{ + compatible = "fairchild,fairchild_fan53555"; + reg = <0x60>; + vddbigarm: vddbigarm { + regulator-name = "vddbigarm"; + regulator-default-microvolt = <1020000>;/*1050000*/ + regulator-step-microvolt = <10000>;/* 10 * 1000 uV */ + regulator-min-microvolt = <600000>;/* 600 * 1000 uV */ + regulator-max-microvolt = <1230000>;/*(600 + 10 * 0x3F) * 1000 uV*/ + }; + }; + + sm5701-i2c@49 { + compatible = "sm,sm5701"; + reg = <0x49>; + + chargermfd { + charger { + compatible = "sm,sm5701-charger"; + chgen-gpio = <&d_gpio_gpio 55 0>; + chgirq-gpio = <&d_gpio_gpio 145 0>; + chg-float-voltage = <4400>; + }; + }; + + leds_sm5701 { + compatible = "sm,leds_sm5701"; + flashen-gpio = <&d_gpio_gpio 47 0>; + flashtorch-gpio = <&d_gpio_gpio 156 0>; + }; + }; +}; + +&i2c3 { + ist30xx_ts@50 { + compatible = "Imagis,IST30XXC"; + reg = <0x50>; + gpios = <&d_gpio_gpio 144 0>; + tsp_pwr_name = "vddsim2"; + }; +}; + +&i2c4 { + sm5504@14 { + compatible = "SiliconMitus,sm5504"; + reg = <0x14>; + interrupt-parent = <&d_gpio_gpio>; + sm5504,irq-gpio = <&d_gpio_gpio 143 0>; + }; +}; + +&l_sprd_sensor { + gpios = <&d_gpio_gpio 44 0 /*main reset*/ + &d_gpio_gpio 0 0 /*main powerdown*/ + &d_gpio_gpio 45 0 /*sub reset*/ + &d_gpio_gpio 0 0 /*sub powerdown*/ + &d_gpio_gpio 139 0 /*main core voltage*/ + &d_gpio_gpio 0 0 + &d_gpio_gpio 0 0 + &d_gpio_gpio 0 0>; +}; + +&fb0 { + sprd,fb_mem = <0x9ED74000 0xA8C000>; +}; + +&l_ion { + sprd,ion-heap@1 { + sprd,ion-heap-mem = <0x0 0x0>; + }; + + sprd,ion-heap@2 { + sprd,ion-heap-mem = <0x9864F000 0x7100000>; + }; + + sprd,ion-heap@3 { + sprd,ion-heap-mem = <0x9F800000 0x800000>; /* 480*854*4*2, 1M alignment */ + }; + + sprd,ion-heap@4 { + sprd,ion-heap-mem = <0x9ED74000 0xA8C000>; + }; +}; + diff --git a/arch/arm64/boot/dts/sprd_ss_sharklt8lightsleep.dts b/arch/arm64/boot/dts/sprd_ss_sharklt8lightsleep.dts new file mode 100644 index 00000000..97497667 --- /dev/null +++ b/arch/arm64/boot/dts/sprd_ss_sharklt8lightsleep.dts @@ -0,0 +1,489 @@ +/* + * SPREADTRUM Ltd.clock-cells +sprd_rotation + * + * SharkLT8 5mod refphone DTS + */ + +/dts-v1/; + +/* memory reserved for SMEM */ +/memreserve/ 0x87800000 0x5B0000; /* Offset:120M, Size:5M+256K */ + +/* memory reserved for WARM modem */ +/memreserve/ 0x8DC00000 0xD00000; /* Offset:220M, Size:13M*/ + +/* memory reserved for LTE modem */ +/memreserve/ 0x89600000 0x4600000; /* Offset:150M, Size:70M*/ + +/* memory reserved for fb */ +/memreserve/ 0x9ED74000 0xA8C000; /* 1280*720*4*3, 4K alignment*/ + +/* memory reserved for ION */ +/memreserve/ 0x9F800000 0x800000; /* 1280*720*4*2, 1M alignment*/ + +/* memory reserved for smp */ +/memreserve/ 0x9F700000 0x1000; /* size 4K*/ + +/include/ "sprd-scx35lt8_common.dtsi" + +/ { + chosen { + bootargs = "earlyprintk=sprd_uart,0x70100000"; + }; + + aliases { + i2c_gpio5 = &i2c_gpio5; + i2c_gpio6 = &i2c_gpio6; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0 0x80000000 0 0x60000000>; + }; + + pinctrl { + compatible = "sprd,pinctrl"; + reg = <0 0x402a0000 0 0x1000>; + pwr_domain = "vdd18", + "vdd18", + "vddsim0", + "vddsim1", + "vdd18", + "vddsdio", + "vdd18"; + ctrl_desc = <0x10 0 1 + 0x10 1 1 + 0x10 2 1 + 0x10 3 1 + 0x10 4 1 + 0x10 5 1 + 0x10 6 1>; + }; + + sec-fuelgauge { + compatible = "samsung,sec-fuelgauge"; + capacity-max = <1000>; + capacity-max-margin = <1000>; + capacity-min = <10>; + fg-irq-attr = <0>; + fuel-alert-soc = <1000>; + temp_adc_channel = <0>; + chg_bat_safety_vol = <4600>; + soft_vbat_uvlo = <3050>; + vmode = <0>; /* 1=Voltage mode, 0=mixed mode */ + alm_soc = <5>; /* SOC alm level %*/ + alm_vbat = <3500>; /* Vbat alm level mV*/ + rint = <160>; /*battery internal impedance*/ + cnom = <2000>; /* nominal capacity in mAh */ + rsense_real = <206>; /* sense resistor 0.1mOhm from real environment*/ + rsense_spec = <200>; /* sense resistor 0.1mOhm from specification*/ + relax_current = <50>; /* current for relaxation in mA (< C/20) */ + cal_ajust = <0>; /* ajust calibration data */ + ocv_table = <4355 100 + 4332 95 + 4277 90 + 4221 85 + 4166 80 + 4113 75 + 4063 70 + 4018 65 + 3977 60 + 3933 55 + 3881 50 + 3850 45 + 3826 40 + 3807 35 + 3791 30 + 3778 25 + 3762 20 + 3742 15 + 3711 10 + 3683 5 + 3400 0>; + + sprd_fgu: sprd_fgu{ + compatible = "sprd,sprd_fgu"; + interrupt-parent = <&adi>; + interrupts = <4 0x0>; + }; + }; + + sec-battery { + compatible = "samsung,sec-battery"; + battery,vendor = "SDI SDI"; + battery,charger_name = "sec-charger"; + battery,fuelgauge_name = "sec-fuelgauge"; + battery,technology = <2>; /* POWER_SUPPLY_TECHNOLOGY_LION */ + battery,chip_vendor = "SPRD"; + battery,temp_adc_type = <1>; /* SEC_BATTERY_ADC_TYPE_AP */ + battery,polling_time = <10 30 30 30 3600>; + battery,adc_check_count = <5>; + battery,cable_check_type = <5>; /* SEC_BATTERY_CABLE_CHECK_PSY */ + battery,cable_source_type = <3>; /* SEC_BATTERY_CABLE_SOURCE_EXTERNAL */ + battery,event_waiting_time = <600>; + battery,polling_type = <1>; /* SEC_BATTERY_MONITOR_ALARM */ + battery,monitor_initial_count = <3>; + battery,battery_check_type = <5>; /* SEC_BATTERY_CHECK_CHARGER */ + battery,check_count = <0>; + battery,check_adc_max = <1440>; + battery,check_adc_min = <0>; + battery,ovp_uvlo_check_type = <3>; /* SEC_BATTERY_OVP_UVLO_CHGPOLLING */ + battery,thermal_source = <2>; /* SEC_BATTERY_THERMAL_SOURCE_ADC */ + battery,temp_table_adc = <501 615 738 795 846 956 1065 1088 1180 1307 1392 1477 1627 1777 1922 2098 + 2144 2182 2212 2260 2302 2452 2555>; + battery,temp_table_data = <700 650 600 580 550 500 460 450 400 350 300 250 200 150 100 + 50 20 0 (-20) (-50) (-70) (-150) (-200)>; + battery,temp_check_type = <2>; /* SEC_BATTERY_TEMP_CHECK_TEMP */ + battery,temp_check_count = <1>; + battery,temp_high_threshold_event = <600>; + battery,temp_high_recovery_event = <460>; + battery,temp_low_threshold_event = <(-50)>; + battery,temp_low_recovery_event = <0>; + battery,temp_high_threshold_normal = <600>; + battery,temp_high_recovery_normal = <460>; + battery,temp_low_threshold_normal = <(-50)>; + battery,temp_low_recovery_normal = <0>; + battery,temp_high_threshold_lpm = <600>; + battery,temp_high_recovery_lpm = <460>; + battery,temp_low_threshold_lpm = <(-50)>; + battery,temp_low_recovery_lpm = <0>; + battery,full_check_type = <7>; /* SEC_BATTERY_FULLCHARGED_CHGPSY */ + battery,full_check_type_2nd = <3>; /* SEC_BATTERY_FULLCHARGED_TIME */ + battery,full_check_count = <1>; + battery,chg_gpio_full_check = <0>; + battery,chg_polarity_full_check = <1>; + battery,full_condition_type = <13>; + battery,full_condition_soc = <95>; + battery,full_condition_vcell = <4200>; + battery,recharge_check_count = <1>; + battery,recharge_condition_type = <4>; /* SEC_BATTERY_RECHARGE_CONDITION_VCELL */ + battery,recharge_condition_soc = <95>; + battery,recharge_condition_vcell = <4350>; + battery,charging_total_time = <21600>; + battery,recharging_total_time = <5400>; + battery,charging_reset_time = <0>; + + /* Charger */ +// charger,vbus_ctrl_gpio = <&d_gpio_gpio 64 0x00>; + battery,input_current_limit = <700 460 460 700 460 700 700 460 460 700 700 700 700 460 700 300 700 700 300 700 700 460 460>; + battery,fast_charging_current = <975 0 975 975 975 975 975 975 0 975 975 975 975 (-1) 975 975 975 975 975 975 975 0 0>; + battery,full_check_current_1st = <175 0 175 175 175 175 175 175 0 175 175 175 175 0 175 175 175 175 175 175 175 0 0>; + battery,full_check_current_2nd = <1800 0 1800 1800 1800 1800 1800 1800 0 1800 1800 1800 1800 0 1800 1800 1800 1800 1800 1800 1800 0 0>; + }; + + i2c_gpio5: i2c_gpio@1 { /* cam af eep */ + compatible = "i2c-gpio"; + #address-cells = <1>; + #size-cells = <0>; + gpios = <&d_gpio_gpio 41 0 /* sda */ + &d_gpio_gpio 40 0 >; /* scl */ + i2c-gpio,delay-us = <10>; /* ~100 kHz */ + i2c-gpio,timeout-ms = <0>; + status = "okay"; + + sensor_i2c_vcm0@6A { + compatible = "sprd,sensor_i2c_vcm0"; + reg = <0x6A>; + }; + }; + + i2c_gpio6: i2c_gpio@11 { /* LCD BL */ + compatible = "i2c-gpio"; + reg = <0x11>; + //ti,en-gpio = <&gpio0 54 0>; /* GPIO for EN pin */ + #address-cells = <1>; + #size-cells = <0>; + gpios = <&d_gpio_gpio 16 0 /* sda */ + &d_gpio_gpio 15 0 >; /* scl */ + i2c-gpio,delay-us = <10>; /* ~100 kHz */ + i2c-gpio,timeout-ms = <0>; + status = "okay"; + + lm3632@11 { + compatible = "ti,lm3632"; + reg = <0x11>; + /* GPIO for EN pin */ +// ti,en-gpio = <&d_gpio_gpio 54 0>; + /* Backlight mode is PWM, two strings used */ + backlight { + compatible = "ti,lm3632-backlight"; + bl-name = "sprd_backlight"; + full-strings-used; + pwm-period = <10000>; + pwm-max-brightness = <1637>; /* 20mA */ + /* PWM controller for lm3632 backlight */ +// pwms = <&pwm3943 0 10000>; + pwm-names = "lm3632-backlight"; + }; + }; + }; + + + sprd_pwm_bl { + compatible = "sprd,sprd_pwm_bl"; + brightness_max = <255>; + brightness_min = <0>; + pwm_index = <2>; + //gpio_ctrl_pin = <54>; + gpio_active_level = <0>; + reg =<0 0x40260000 0 0xf>; + }; + +/* + sprd_backlight { + compatible = "sprd,sprd_backlight"; + start = <3>; + end = <3>; + flags = <0x100>; + }; +*/ + + keypad@40250000{ + compatible = "sprd,sci-keypad"; + reg = <0 0x40250000 0 0x1000>; + gpios = <&a_eic_gpio 2 0>; + interrupts = <0 36 0x0>; + sprd,keypad-num-rows = <2>; + sprd,keypad-num-columns = <2>; + sprd,keypad-rows-choose-hw = <0x30000>; + sprd,keypad-cols-choose-hw = <0x300>; + sprd,debounce_time = <5000>; + linux,keypad-no-autorepeat; + sprd,support_long_key; + + key_volume_up { + keypad,row = <0>; + keypad,column = <0>; + linux,code = <115>; + }; + + key_home { + keypad,row = <0>; + keypad,column = <1>; + linux,code = <102>; + }; + }; + + gps { + compatible = "lsi,s5n6420"; + gps-pwr-en = <&d_gpio_gpio 11 0>; /*GPS_PWON*/ + gps-reset = <&d_gpio_gpio 134 0>; /*GPS_RESET*/ + gps-regulator = "vddcamd"; + }; + + sprd_fm: sprd_fm@40270000{ + compatible = "sprd,sprd_fm"; + reg = <0 0x40270000 0 0x1000>; + }; + +/* + itm_wlan{ + compatible = "sprd,itm_wlan"; + }; +*/ + + sprd-marlin { + compatible = "sprd,marlin"; + gpios = <&d_gpio_gpio 14 0 /*marlin gpio0 */ + &d_gpio_gpio 130 0 /*marlin gpio1 */ + &d_gpio_gpio 133 0 /*marlin gpio2 */ + &d_gpio_gpio 94 0 /*marlin gpio3 */ + &d_gpio_gpio 131 0>; /*marlin reset*/ + cp-rfctl-offset = <0x244>; /*coex func. marlin gpio3*/ + vdd-download = "vddcon"; /*vdd 1.6v*/ + vdd-pa = "vddwifipa"; /*vdd 3.3v*/ + clk-name = "clk_aux0"; /*clk 32k*/ + sdhci-name = "sdio_wifi"; + }; +}; + +&adi { +/* + keyboard_backlight { + compatible = "sprd,keyboard-backlight"; + }; + + leds_sprd_bltc_rgb { + compatible = "sprd,sprd-leds-bltc-rgb"; + reg = <0x440 0x40>, + <0x800 0xff>; + }; +*/ + + sprd_eic_keys { + compatible = "sprd,sprd-eic-keys"; + input-name = "sprd-eic-keys"; + + key_volumedown { + label = "Volumeup Key"; + linux,code = <114>; + gpios = <&a_eic_gpio 10 0>; + debounce-interval = <2>; + gpio-key,wakeup; + }; + }; + + headset_sprd_sc2723 { + compatible = "sprd,headset_sprd_sc2723"; + gpio_switch = <0>; + gpio_detect = <92>; + gpio_button = <97>; + irq_trigger_level_detect = <0>; + irq_trigger_level_button = <0>; + adc_threshold_3pole_detect = <300>; + adc_threshold_4pole_detect = <3270>; + irq_threshold_buttont = <1>; + voltage_headmicbias = <3000000>; + nbuttons = <3>; + + headset_buttons_media { + adc_min = <0>; + adc_max = <550>; + code = <226>; + type = <0>; + }; + + headset_buttons_up { + adc_min = <551>; + adc_max = <1114>; + code = <115>; + type = <0>; + }; + + headset_buttons_down { + adc_min = <1115>; + adc_max =<3000>; + code = <114>; + type = <0>; + }; + }; +}; + +&i2c0 { + sensor_main@0x3c { + compatible = "sprd,sensor_main"; + reg = <0x3c>; + }; + + sensor_sub@0x21 { + compatible = "sprd,sensor_sub"; + reg = <0x21>; + }; +}; + +&i2c1 { + fairchild_fan53555@60{ + compatible = "fairchild,fairchild_fan53555"; + reg = <0x60>; + vddbigarm: vddbigarm { + regulator-name = "vddbigarm"; + regulator-default-microvolt = <1020000>;/*1050000*/ + regulator-step-microvolt = <10000>;/* 10 * 1000 uV */ + regulator-min-microvolt = <600000>;/* 600 * 1000 uV */ + regulator-max-microvolt = <1230000>;/*(600 + 10 * 0x3F) * 1000 uV*/ + }; + }; + + sm5701-i2c@49 { + compatible = "sm,sm5701"; + reg = <0x49>; + + chargermfd { + charger { + compatible = "sm,sm5701-charger"; + chgen-gpio = <&d_gpio_gpio 55 0>; + chgirq-gpio = <&d_gpio_gpio 145 0>; + chg-float-voltage = <4400>; + }; + }; + + leds_sm5701 { + compatible = "sm,leds_sm5701"; + flashen-gpio = <&d_gpio_gpio 47 0>; + flashtorch-gpio = <&d_gpio_gpio 156 0>; + }; + }; +}; + +&i2c3 { + ist30xx_ts@50 { + compatible = "Imagis,IST30XXC"; + reg = <0x50>; + gpios = <&d_gpio_gpio 144 0>; + tsp_pwr_name = "vddsim2"; + }; +}; + +&i2c4 { + sm5504@14 { + compatible = "SiliconMitus,sm5504"; + reg = <0x14>; + interrupt-parent = <&d_gpio_gpio>; + sm5504,irq-gpio = <&d_gpio_gpio 143 0>; + }; +}; + +&l_sprd_sensor { + gpios = <&d_gpio_gpio 44 0 /*main reset*/ + &d_gpio_gpio 0 0 /*main powerdown*/ + &d_gpio_gpio 45 0 /*sub reset*/ + &d_gpio_gpio 0 0 /*sub powerdown*/ + &d_gpio_gpio 139 0 /*main core voltage*/ + &d_gpio_gpio 0 0 + &d_gpio_gpio 0 0 + &d_gpio_gpio 0 0>; +}; + +&fb0 { + sprd,fb_mem = <0x9ED74000 0xA8C000>; +}; + +&l_ion { + sprd,ion-heap@1 { + sprd,ion-heap-mem = <0x0 0x0>; + }; + + sprd,ion-heap@2 { + sprd,ion-heap-mem = <0x9864F000 0x7100000>; + }; + + sprd,ion-heap@3 { + sprd,ion-heap-mem = <0x9F800000 0x800000>; /* 480*854*4*2, 1M alignment */ + }; + + sprd,ion-heap@4 { + sprd,ion-heap-mem = <0x9ED74000 0xA8C000>; + }; +}; +&CPU0 { + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD &CLUSTER_PD>; +}; + +&CPU1 { + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD &CLUSTER_PD>; +}; + +&CPU2 { + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD &CLUSTER_PD>; +}; + +&CPU3 { + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD &CLUSTER_PD>; +}; + +&CPU4 { + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD &CLUSTER_PD>; +}; + +&CPU5 { + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD &CLUSTER_PD>; +}; + +&CPU6 { + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD &CLUSTER_PD>; +}; + +&CPU7 { + cpu-idle-states = <&LIGHT_SLEEP &CORE_PD &CLUSTER_PD>; +}; diff --git a/arch/arm64/boot/install.sh b/arch/arm64/boot/install.sh new file mode 100644 index 00000000..12ed78aa --- /dev/null +++ b/arch/arm64/boot/install.sh @@ -0,0 +1,46 @@ +#!/bin/sh +# +# arch/arm64/boot/install.sh +# +# This file is subject to the terms and conditions of the GNU General Public +# License. See the file "COPYING" in the main directory of this archive +# for more details. +# +# Copyright (C) 1995 by Linus Torvalds +# +# Adapted from code in arch/i386/boot/Makefile by H. Peter Anvin +# Adapted from code in arch/i386/boot/install.sh by Russell King +# +# "make install" script for the AArch64 Linux port +# +# Arguments: +# $1 - kernel version +# $2 - kernel image file +# $3 - kernel map file +# $4 - default install path (blank if root directory) +# + +# User may have a custom install script +if [ -x ~/bin/${INSTALLKERNEL} ]; then exec ~/bin/${INSTALLKERNEL} "$@"; fi +if [ -x /sbin/${INSTALLKERNEL} ]; then exec /sbin/${INSTALLKERNEL} "$@"; fi + +if [ "$(basename $2)" = "Image.gz" ]; then +# Compressed install + echo "Installing compressed kernel" + base=vmlinuz +else +# Normal install + echo "Installing normal kernel" + base=vmlinux +fi + +if [ -f $4/$base-$1 ]; then + mv $4/$base-$1 $4/$base-$1.old +fi +cat $2 > $4/$base-$1 + +# Install system map file +if [ -f $4/System.map-$1 ]; then + mv $4/System.map-$1 $4/System.map-$1.old +fi +cp $3 $4/System.map-$1 |