Initial file dump from open source releaseHEADmaster

1 files changed, 274 insertions, 0 deletions

diff --git a/include/soc/sprd/chip_x30g/__regs_pinmap.h b/include/soc/sprd/chip_x30g/__regs_pinmap.h
new file mode 100755
index 00000000..49ab259a
--- /dev/null
+++ b/include/soc/sprd/chip_x30g/__regs_pinmap.h
@@ -0,0 +1,274 @@
+#ifndef __ASM_ARM_ARCH_PINMAP_H
+#error  "Don't include this file directly, Pls include pinmap.h"
+#endif
+
+#ifndef _REGS_PINMAP_H_
+#define _REGS_PINMAP_H_
+
+#define CTL_PIN_BASE			(SPRD_PIN_BASE)
+
+/* registers definitions for controller CTL_PIN */
+#define REG_PIN_CTRL0                   ( 0x0000 )
+#define REG_PIN_CTRL1                   ( 0x0004 )
+#define REG_PIN_CTRL2                   ( 0x0008 )
+#define REG_PIN_CTRL3                   ( 0x000c )
+#define REG_PIN_CTRL4                   ( 0x0010 )
+#define REG_PIN_CTRL5                   ( 0x0014 )
+
+#define REG_PIN_TRACECLK                ( 0x0020 )
+#define REG_PIN_TRACECTRL               ( 0x0024 )
+#define REG_PIN_TRACEDAT0               ( 0x0028 )
+#define REG_PIN_TRACEDAT1               ( 0x002c )
+#define REG_PIN_TRACEDAT2               ( 0x0030 )
+#define REG_PIN_TRACEDAT3               ( 0x0034 )
+#define REG_PIN_TRACEDAT4               ( 0x0038 )
+#define REG_PIN_TRACEDAT5               ( 0x003c )
+#define REG_PIN_TRACEDAT6               ( 0x0040 )
+#define REG_PIN_TRACEDAT7               ( 0x0044 )
+#define REG_PIN_U0TXD                   ( 0x0048 )
+#define REG_PIN_U0RXD                   ( 0x004c )
+#define REG_PIN_U0CTS                   ( 0x0050 )
+#define REG_PIN_U0RTS                   ( 0x0054 )
+#define REG_PIN_U1TXD                   ( 0x0058 )
+#define REG_PIN_U1RXD                   ( 0x005c )
+#define REG_PIN_U2TXD                   ( 0x0060 )
+#define REG_PIN_U2RXD                   ( 0x0064 )
+#define REG_PIN_U3TXD                   ( 0x0068 )
+#define REG_PIN_U3RXD                   ( 0x006c )
+#define REG_PIN_U3CTS                   ( 0x0070 )
+#define REG_PIN_U3RTS                   ( 0x0074 )
+#define REG_PIN_CP2_RFCTL0              ( 0x0078 )
+#define REG_PIN_CP2_RFCTL1              ( 0x007c )
+#define REG_PIN_CP2_RFCTL2              ( 0x0080 )
+#define REG_PIN_WIFI_AGCGAIN3           ( 0x0084 )
+#define REG_PIN_WIFI_AGCGAIN4           ( 0x0088 )
+#define REG_PIN_WIFI_AGCGAIN5           ( 0x008c )
+#define REG_PIN_WIFI_AGCGAIN6           ( 0x0090 )
+#define REG_PIN_RFSDA0                  ( 0x0094 )
+#define REG_PIN_RFSCK0                  ( 0x0098 )
+#define REG_PIN_RFSEN0                  ( 0x009c )
+#define REG_PIN_RFSDA1                  ( 0x00a0 )
+#define REG_PIN_RFSCK1                  ( 0x00a4 )
+#define REG_PIN_RFSEN1                  ( 0x00a8 )
+#define REG_PIN_CP1_RFCTL0              ( 0x00ac )
+#define REG_PIN_CP1_RFCTL1              ( 0x00b0 )
+#define REG_PIN_CP1_RFCTL2              ( 0x00b4 )
+#define REG_PIN_CP1_RFCTL3              ( 0x00b8 )
+#define REG_PIN_CP1_RFCTL4              ( 0x00bc )
+#define REG_PIN_CP1_RFCTL5              ( 0x00c0 )
+#define REG_PIN_CP1_RFCTL6              ( 0x00c4 )
+#define REG_PIN_CP1_RFCTL7              ( 0x00c8 )
+#define REG_PIN_CP1_RFCTL8              ( 0x00cc )
+#define REG_PIN_CP1_RFCTL9              ( 0x00d0 )
+#define REG_PIN_CP1_RFCTL10             ( 0x00d4 )
+#define REG_PIN_CP1_RFCTL11             ( 0x00d8 )
+#define REG_PIN_CP1_RFCTL12             ( 0x00dc )
+#define REG_PIN_CP1_RFCTL13             ( 0x00e0 )
+#define REG_PIN_CP1_RFCTL14             ( 0x00e4 )
+#define REG_PIN_CP1_RFCTL15             ( 0x00e8 )
+#define REG_PIN_CP0_RFCTL0              ( 0x00ec )
+#define REG_PIN_CP0_RFCTL1              ( 0x00f0 )
+#define REG_PIN_CP0_RFCTL2              ( 0x00f4 )
+#define REG_PIN_CP0_RFCTL3              ( 0x00f8 )
+#define REG_PIN_CP0_RFCTL4              ( 0x00fc )
+#define REG_PIN_CP0_RFCTL5              ( 0x0100 )
+#define REG_PIN_CP0_RFCTL6              ( 0x0104 )
+#define REG_PIN_CP0_RFCTL7              ( 0x0108 )
+#define REG_PIN_XTLEN                   ( 0x010c )
+#define REG_PIN_SCL3                    ( 0x0110 )
+#define REG_PIN_SDA3                    ( 0x0114 )
+#define REG_PIN_SPI0_CSN                ( 0x0118 )
+#define REG_PIN_SPI0_DO                 ( 0x011c )
+#define REG_PIN_SPI0_DI                 ( 0x0120 )
+#define REG_PIN_SPI0_CLK                ( 0x0124 )
+#define REG_PIN_EXTINT0                 ( 0x0128 )
+#define REG_PIN_EXTINT1                 ( 0x012c )
+#define REG_PIN_SCL1                    ( 0x0130 )
+#define REG_PIN_SDA1                    ( 0x0134 )
+#define REG_PIN_SIMCLK0                 ( 0x0138 )
+#define REG_PIN_SIMDA0                  ( 0x013c )
+#define REG_PIN_SIMRST0                 ( 0x0140 )
+#define REG_PIN_SIMCLK1                 ( 0x0144 )
+#define REG_PIN_SIMDA1                  ( 0x0148 )
+#define REG_PIN_SIMRST1                 ( 0x014c )
+#define REG_PIN_SIMCLK2                 ( 0x0150 )
+#define REG_PIN_SIMDA2                  ( 0x0154 )
+#define REG_PIN_SIMRST2                 ( 0x0158 )
+#define REG_PIN_MEMS_MIC_CLK0           ( 0x015c )
+#define REG_PIN_MEMS_MIC_DATA0          ( 0x0160 )
+#define REG_PIN_MEMS_MIC_CLK1           ( 0x0164 )
+#define REG_PIN_MEMS_MIC_DATA1          ( 0x0168 )
+#define REG_PIN_SD1_CLK                 ( 0x016c )
+#define REG_PIN_SD1_CMD                 ( 0x0170 )
+#define REG_PIN_SD1_D0                  ( 0x0174 )
+#define REG_PIN_SD1_D1                  ( 0x0178 )
+#define REG_PIN_SD1_D2                  ( 0x017c )
+#define REG_PIN_SD1_D3                  ( 0x0180 )
+#define REG_PIN_SD0_D3                  ( 0x0184 )
+#define REG_PIN_SD0_D2                  ( 0x0188 )
+#define REG_PIN_SD0_CMD                 ( 0x018c )
+#define REG_PIN_SD0_D0                  ( 0x0190 )
+#define REG_PIN_SD0_D1                  ( 0x0194 )
+#define REG_PIN_SD0_CLK1                ( 0x0198 )
+#define REG_PIN_SD0_CLK0                ( 0x019c )
+#define REG_PIN_PTEST                   ( 0x01a0 )
+#define REG_PIN_ANA_INT                 ( 0x01a4 )
+#define REG_PIN_EXT_RST_B               ( 0x01a8 )
+#define REG_PIN_CHIP_SLEEP              ( 0x01ac )
+#define REG_PIN_XTL_BUF_EN0             ( 0x01b0 )
+#define REG_PIN_XTL_BUF_EN1             ( 0x01b4 )
+#define REG_PIN_XTL_BUF_EN2             ( 0x01b8 )
+#define REG_PIN_CLK_32K                 ( 0x01bc )
+#define REG_PIN_AUD_SCLK                ( 0x01c0 )
+#define REG_PIN_AUD_DANGL               ( 0x01c4 )
+#define REG_PIN_AUD_DANGR               ( 0x01c8 )
+#define REG_PIN_AUD_ADD0                ( 0x01cc )
+#define REG_PIN_AUD_ADSYNC              ( 0x01d0 )
+#define REG_PIN_AUD_DAD1                ( 0x01d4 )
+#define REG_PIN_AUD_DAD0                ( 0x01d8 )
+#define REG_PIN_AUD_DASYNC              ( 0x01dc )
+#define REG_PIN_ADI_D                   ( 0x01e0 )
+#define REG_PIN_ADI_SYNC                ( 0x01e4 )
+#define REG_PIN_ADI_SCLK                ( 0x01e8 )
+#define REG_PIN_LCD_CSN1                ( 0x01ec )
+#define REG_PIN_LCD_CSN0                ( 0x01f0 )
+#define REG_PIN_LCD_RSTN                ( 0x01f4 )
+#define REG_PIN_LCD_CD                  ( 0x01f8 )
+#define REG_PIN_LCD_FMARK               ( 0x01fc )
+#define REG_PIN_LCD_WRN                 ( 0x0200 )
+#define REG_PIN_LCD_RDN                 ( 0x0204 )
+#define REG_PIN_LCD_D0                  ( 0x0208 )
+#define REG_PIN_LCD_D1                  ( 0x020c )
+#define REG_PIN_LCD_D2                  ( 0x0210 )
+#define REG_PIN_LCD_D3                  ( 0x0214 )
+#define REG_PIN_LCD_D4                  ( 0x0218 )
+#define REG_PIN_LCD_D5                  ( 0x021c )
+#define REG_PIN_LCD_D6                  ( 0x0220 )
+#define REG_PIN_LCD_D7                  ( 0x0224 )
+#define REG_PIN_LCD_D8                  ( 0x0228 )
+#define REG_PIN_LCD_D9                  ( 0x022c )
+#define REG_PIN_LCD_D10                 ( 0x0230 )
+#define REG_PIN_LCD_D11                 ( 0x0234 )
+#define REG_PIN_LCD_D12                 ( 0x0238 )
+#define REG_PIN_LCD_D13                 ( 0x023c )
+#define REG_PIN_LCD_D14                 ( 0x0240 )
+#define REG_PIN_LCD_D15                 ( 0x0244 )
+#define REG_PIN_LCD_D16                 ( 0x0248 )
+#define REG_PIN_LCD_D17                 ( 0x024c )
+#define REG_PIN_LCD_D18                 ( 0x0250 )
+#define REG_PIN_LCD_D19                 ( 0x0254 )
+#define REG_PIN_LCD_D20                 ( 0x0258 )
+#define REG_PIN_LCD_D21                 ( 0x025c )
+#define REG_PIN_LCD_D22                 ( 0x0260 )
+#define REG_PIN_LCD_D23                 ( 0x0264 )
+#define REG_PIN_SPI2_CSN                ( 0x0268 )
+#define REG_PIN_SPI2_DO                 ( 0x026c )
+#define REG_PIN_SPI2_DI                 ( 0x0270 )
+#define REG_PIN_SPI2_CLK                ( 0x0274 )
+#define REG_PIN_EMMC_CLK                ( 0x0278 )
+#define REG_PIN_EMMC_CMD                ( 0x027c )
+#define REG_PIN_EMMC_D0                 ( 0x0280 )
+#define REG_PIN_EMMC_D1                 ( 0x0284 )
+#define REG_PIN_EMMC_D2                 ( 0x0288 )
+#define REG_PIN_EMMC_D3                 ( 0x028c )
+#define REG_PIN_EMMC_D4                 ( 0x0290 )
+#define REG_PIN_EMMC_D5                 ( 0x0294 )
+#define REG_PIN_EMMC_D6                 ( 0x0298 )
+#define REG_PIN_EMMC_D7                 ( 0x029c )
+#define REG_PIN_EMMC_RST                ( 0x02a0 )
+#define REG_PIN_NFWPN                   ( 0x02a4 )
+#define REG_PIN_NFRB                    ( 0x02a8 )
+#define REG_PIN_NFCLE                   ( 0x02ac )
+#define REG_PIN_NFALE                   ( 0x02b0 )
+#define REG_PIN_NFCEN0                  ( 0x02b4 )
+#define REG_PIN_NFCEN1                  ( 0x02b8 )
+#define REG_PIN_NFREN                   ( 0x02bc )
+#define REG_PIN_NFWEN                   ( 0x02c0 )
+#define REG_PIN_NFD0                    ( 0x02c4 )
+#define REG_PIN_NFD1                    ( 0x02c8 )
+#define REG_PIN_NFD2                    ( 0x02cc )
+#define REG_PIN_NFD3                    ( 0x02d0 )
+#define REG_PIN_NFD4                    ( 0x02d4 )
+#define REG_PIN_NFD5                    ( 0x02d8 )
+#define REG_PIN_NFD6                    ( 0x02dc )
+#define REG_PIN_NFD7                    ( 0x02e0 )
+#define REG_PIN_NFD8                    ( 0x02e4 )
+#define REG_PIN_NFD9                    ( 0x02e8 )
+#define REG_PIN_NFD10                   ( 0x02ec )
+#define REG_PIN_NFD11                   ( 0x02f0 )
+#define REG_PIN_NFD12                   ( 0x02f4 )
+#define REG_PIN_NFD13                   ( 0x02f8 )
+#define REG_PIN_NFD14                   ( 0x02fc )
+#define REG_PIN_NFD15                   ( 0x0300 )
+#define REG_PIN_CCIRCK0                 ( 0x0304 )
+#define REG_PIN_CCIRCK1                 ( 0x0308 )
+#define REG_PIN_CCIRMCLK                ( 0x030c )
+#define REG_PIN_CCIRHS                  ( 0x0310 )
+#define REG_PIN_CCIRVS                  ( 0x0314 )
+#define REG_PIN_CCIRD0                  ( 0x0318 )
+#define REG_PIN_CCIRD1                  ( 0x031c )
+#define REG_PIN_CCIRD2                  ( 0x0320 )
+#define REG_PIN_CCIRD3                  ( 0x0324 )
+#define REG_PIN_CCIRD4                  ( 0x0328 )
+#define REG_PIN_CCIRD5                  ( 0x032c )
+#define REG_PIN_CCIRD6                  ( 0x0330 )
+#define REG_PIN_CCIRD7                  ( 0x0334 )
+#define REG_PIN_CCIRD8                  ( 0x0338 )
+#define REG_PIN_CCIRD9                  ( 0x033c )
+#define REG_PIN_CCIRRST                 ( 0x0340 )
+#define REG_PIN_CCIRPD1                 ( 0x0344 )
+#define REG_PIN_CCIRPD0                 ( 0x0348 )
+#define REG_PIN_SCL0                    ( 0x034c )
+#define REG_PIN_SDA0                    ( 0x0350 )
+#define REG_PIN_KEYOUT0                 ( 0x0354 )
+#define REG_PIN_KEYOUT1                 ( 0x0358 )
+#define REG_PIN_KEYOUT2                 ( 0x035c )
+#define REG_PIN_KEYIN0                  ( 0x0360 )
+#define REG_PIN_KEYIN1                  ( 0x0364 )
+#define REG_PIN_KEYIN2                  ( 0x0368 )
+#define REG_PIN_SCL2                    ( 0x036c )
+#define REG_PIN_SDA2                    ( 0x0370 )
+#define REG_PIN_CLK_AUX0                ( 0x0374 )
+#define REG_PIN_IIS0DI                  ( 0x0378 )
+#define REG_PIN_IIS0DO                  ( 0x037c )
+#define REG_PIN_IIS0CLK                 ( 0x0380 )
+#define REG_PIN_IIS0LRCK                ( 0x0384 )
+#define REG_PIN_IIS0MCK                 ( 0x0388 )
+#define REG_PIN_IIS1DI                  ( 0x038c )
+#define REG_PIN_IIS1DO                  ( 0x0390 )
+#define REG_PIN_IIS1CLK                 ( 0x0394 )
+#define REG_PIN_IIS1LRCK                ( 0x0398 )
+#define REG_PIN_IIS1MCK                 ( 0x039c )
+#define REG_PIN_MTDO                    ( 0x03a0 )
+#define REG_PIN_MTDI                    ( 0x03a4 )
+#define REG_PIN_MTCK                    ( 0x03a8 )
+#define REG_PIN_MTMS                    ( 0x03ac )
+#define REG_PIN_MTRST_N                 ( 0x03b0 )
+
+
+
+/* bits definitions for register REG_PIN_XXX */
+#define BITS_PIN_DS(_x_)                ( ((_x_) << 18) & (BIT_18|BIT_19|BIT_20|BIT_21) )
+#define BIT_PIN_SLP_AP                  ( BIT_13 )
+#define BIT_PIN_SLP_CP0                 ( BIT_14 )
+#define BIT_PIN_SLP_CP1                 ( BIT_15 )
+#define BIT_PIN_SLP_CP2                 ( BIT_16 )
+#define BITS_PIN_SLP(_x_)               ( ((_x_) << 13) & (BIT_13|BIT_14|BIT_15|BIT_16) )
+#define BIT_PIN_WPU_SEL                 ( BIT_12 )
+#define BIT_PIN_WPU                     ( BIT_7 )
+#define BIT_PIN_WPD                     ( BIT_6 )
+#define BITS_PIN_AF(_x_)                ( ((_x_) << 4) & (BIT_4|BIT_5) )
+#define BIT_PIN_SLP_WPU                 ( BIT_3 )
+#define BIT_PIN_SLP_WPD                 ( BIT_2 )
+#define BIT_PIN_SLP_IE                  ( BIT_1 )
+#define BIT_PIN_SLP_OE                  ( BIT_0 )
+
+/* vars definitions for controller CTL_PIN */
+#define BIT_PIN_NUL                     ( 0 )
+#define BIT_PIN_SLP_NUL                 ( 0 )
+#define BIT_PIN_SLP_Z                   ( 0 )
+#define BIT_PIN_WPU_SEL                 ( BIT_12 )
+#define BIT_PIN_WPUS                    ( BIT_12 )
+#define BIT_PIN_NULL                    ( 0 )
+
+#endif