Initial file dump from open source releaseHEADmaster

7 files changed, 492 insertions, 0 deletions

diff --git a/arch/arm/mach-sc/include/mach/__irqs-sc8830.h b/arch/arm/mach-sc/include/mach/__irqs-sc8830.h
new file mode 100644
index 00000000..58609d8a
--- /dev/null
+++ b/arch/arm/mach-sc/include/mach/__irqs-sc8830.h
@@ -0,0 +1,229 @@
+/*
+ * Copyright (C) 2012 Spreadtrum Communications Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_SPRD_IRQS_SCX35_H
+#define __ASM_ARCH_SPRD_IRQS_SCX35_H
+
+#ifndef __ASM_ARCH_SCI_IRQS_H
+#error  "Don't include this file directly, include <mach/irqs.h>"
+#endif
+
+#define IRQ_GIC_START			(32)
+#if defined(CONFIG_ARCH_SCX15) || defined(CONFIG_ARCH_SCX30G)
+#define NR_SCI_PHY_IRQS			(IRQ_GIC_START + 127)
+#else
+#define NR_SCI_PHY_IRQS			(IRQ_GIC_START + 125)
+#endif
+
+#define SCI_IRQ(_X_)			(IRQ_GIC_START + (_X_))
+#define SCI_EXT_IRQ(_X_)		(NR_SCI_PHY_IRQS + (_X_))
+
+#define IRQ_SPECIAL_LATCH		SCI_IRQ(0)
+#define IRQ_SOFT_TRIGGED0_INT		SCI_IRQ(1)
+#define IRQ_SER0_INT			SCI_IRQ(2)
+#define IRQ_SER1_INT			SCI_IRQ(3)
+#define IRQ_SER2_INT			SCI_IRQ(4)
+#define IRQ_SER3_INT			SCI_IRQ(5)
+#define IRQ_SER4_INT			SCI_IRQ(6)
+#define IRQ_SPI0_INT			SCI_IRQ(7)
+#define IRQ_SPI1_INT			SCI_IRQ(8)
+#define IRQ_SPI2_INT			SCI_IRQ(9)
+#define IRQ_SIM0_INT 			SCI_IRQ(10)
+#define IRQ_I2C0_INT 			SCI_IRQ(11)
+#define IRQ_I2C1_INT 			SCI_IRQ(12)
+#define IRQ_I2C2_INT 			SCI_IRQ(13)
+#define IRQ_I2C3_INT 			SCI_IRQ(14)
+#define IRQ_I2C4_INT 			SCI_IRQ(15)
+#define IRQ_IIS0_INT			SCI_IRQ(16)
+#define IRQ_IIS1_INT			SCI_IRQ(17)
+#define IRQ_IIS2_INT			SCI_IRQ(18)
+#define IRQ_IIS3_INT			SCI_IRQ(19)
+#define IRQ_REQ_AUD_INT			SCI_IRQ(20)
+#define IRQ_REQ_AUD_VBC_AFIFO_INT			SCI_IRQ(21)
+#define IRQ_REQ_AUD_VBC_DA_INT			SCI_IRQ(22)
+#define IRQ_REQ_AUD_VBC_AD01_INT			SCI_IRQ(23)
+#define IRQ_REQ_AUD_VBC_AD23_INT			SCI_IRQ(24)
+#define IRQ_ADI_INT			SCI_IRQ(25)
+#define IRQ_THM_INT			SCI_IRQ(26)
+#define IRQ_FM_INT			SCI_IRQ(27)
+#define IRQ_AONTMR0_INT			SCI_IRQ(28)
+#define IRQ_APTMR0_INT			SCI_IRQ(29)
+#define IRQ_AONSYST_INT			SCI_IRQ(30)
+#define IRQ_APSYST_INT			SCI_IRQ(31)
+
+#define IRQ_AONI2C_INT			SCI_IRQ(34)
+#define IRQ_GPIO_INT			SCI_IRQ(35)
+#define IRQ_KPD_INT			SCI_IRQ(36)
+#define IRQ_EIC_INT			SCI_IRQ(37)
+#define IRQ_ANA_INT			SCI_IRQ(38)
+#define IRQ_GPU_INT			SCI_IRQ(39)
+#define IRQ_CSI_INT0			SCI_IRQ(40)
+#define IRQ_CSI_INT1			SCI_IRQ(41)
+#define IRQ_JPG_INT			SCI_IRQ(42)
+#define IRQ_VSP_INT			SCI_IRQ(43)
+#define IRQ_ISP_INT			SCI_IRQ(44)
+#define IRQ_DCAM_INT			SCI_IRQ(45)
+#define IRQ_DISPC0_INT			SCI_IRQ(46)
+#define IRQ_DISPC1_INT			SCI_IRQ(47)
+#define IRQ_DSI0_INT			SCI_IRQ(48)
+#define IRQ_DSI1_INT			SCI_IRQ(49)
+#define IRQ_DSI2_INT			SCI_IRQ(47)
+//#define IRQ_DMA_INT			SCI_IRQ(50)
+#define IRQ_GSP_INT			SCI_IRQ(51)
+#define IRQ_GPS_INT			SCI_IRQ(52)
+#define IRQ_GPS_RTCEXP_INT			SCI_IRQ(53)
+#define IRQ_GPS_WAKEUP_INT			SCI_IRQ(54)
+#define IRQ_USBD_INT			SCI_IRQ(55)
+#define IRQ_NFC_INT			SCI_IRQ(56)
+#define IRQ_SDIO0_INT			SCI_IRQ(57)
+#define IRQ_SDIO1_INT			SCI_IRQ(58)
+#define IRQ_SDIO2_INT			SCI_IRQ(59)
+#define IRQ_EMMC_INT			SCI_IRQ(60)
+#define IRQ_BM0_INT			SCI_IRQ(61)
+#define IRQ_BM1_INT			SCI_IRQ(62)
+#define IRQ_BM2_INT			SCI_IRQ(63)
+#define IRQ_DRM_INT			SCI_IRQ(66)
+#define IRQ_CP0_DSP_INT			SCI_IRQ(67)
+#define IRQ_CP0_MCU0_INT			SCI_IRQ(68)
+#define IRQ_CP0_MCU1_INT			SCI_IRQ(69)
+#define IRQ_CP1_DSP_INT			SCI_IRQ(70)
+#define IRQ_CP1_MCU0_INT			SCI_IRQ(71)
+#define IRQ_CP1_MCU1_INT			SCI_IRQ(72)
+#define IRQ_CP2_INT0_INT			SCI_IRQ(73)
+#define IRQ_CP2_INT1_INT			SCI_IRQ(74)
+#define IRQ_CP0_DSP_FIQ_INT			SCI_IRQ(75)
+#define IRQ_CP0_MCU_FIQ0_INT			SCI_IRQ(76)
+#define IRQ_CP0_MCU_FIQ1_INT			SCI_IRQ(77)
+#define IRQ_CP1_MCU_FIQ_INT			SCI_IRQ(78)
+#if 0
+#define IRQ_NFC_INT			SCI_IRQ(79)
+#define IRQ_NFC_INT			SCI_IRQ(80)
+#define IRQ_NFC_INT			SCI_IRQ(81)
+#define IRQ_NFC_INT			SCI_IRQ(82)
+#endif
+#define IRQ_CP0_WDG_INT			SCI_IRQ(83)
+#define IRQ_CP1_WDG_INT			SCI_IRQ(84)
+#define IRQ_CP2_WDG_INT			SCI_IRQ(85)
+#define IRQ_AXI_BM_PUB_INT		SCI_IRQ(86)
+#if 0
+#define IRQ_NFC_INT			SCI_IRQ(86)
+#define IRQ_NFC_INT			SCI_IRQ(87)
+#define IRQ_NFC_INT			SCI_IRQ(88)
+#define IRQ_NFC_INT			SCI_IRQ(89)
+#define IRQ_NFC_INT			SCI_IRQ(90)
+#define IRQ_NFC_INT			SCI_IRQ(91)
+#endif
+#define IRQ_NPMUIRQ0_INT			SCI_IRQ(92)
+#define IRQ_NPMUIRQ1_INT			SCI_IRQ(93)
+#define IRQ_NPMUIRQ2_INT			SCI_IRQ(94)
+#define IRQ_NPMUIRQ3_INT			SCI_IRQ(95)
+#define IRQ_CA7COM0_INT			SCI_IRQ(98)
+#define IRQ_CA7COM1_INT			SCI_IRQ(99)
+#define IRQ_CA7COM2_INT			SCI_IRQ(100)
+#define IRQ_CA7COM3_INT			SCI_IRQ(101)
+#define IRQ_NCNTV0_INT			SCI_IRQ(102)
+#define IRQ_NCNTV1_INT			SCI_IRQ(103)
+#define IRQ_NCNTV2_INT			SCI_IRQ(104)
+#define IRQ_NCNTV3_INT			SCI_IRQ(105)
+#define IRQ_NCNTHP0_INT			SCI_IRQ(106)
+#define IRQ_NCNTHP1_INT			SCI_IRQ(107)
+#define IRQ_NCNTHP2_INT			SCI_IRQ(108)
+#define IRQ_NCNTHP3_INT			SCI_IRQ(109)
+#define IRQ_NCNTPN0_INT			SCI_IRQ(110)
+#define IRQ_NCNTPN1_INT			SCI_IRQ(111)
+#define IRQ_NCNTPN2_INT			SCI_IRQ(112)
+#define IRQ_NCNTPN3_INT			SCI_IRQ(113)
+#define IRQ_NCNTPS0_INT			SCI_IRQ(114)
+#define IRQ_NCNTPS1_INT			SCI_IRQ(115)
+#define IRQ_NCNTPS2_INT			SCI_IRQ(116)
+#define IRQ_NCNTPS3_INT			SCI_IRQ(117)
+#define IRQ_APTMR1_INT			SCI_IRQ(118)
+#define IRQ_APTMR2_INT			SCI_IRQ(119)
+#define IRQ_APTMR3_INT			SCI_IRQ(120)
+#define IRQ_APTMR4_INT			SCI_IRQ(121)
+#define IRQ_AVS_INT				SCI_IRQ(122)
+#define IRQ_APWDG_INT			SCI_IRQ(123)
+#define IRQ_CA7WDG_INT			SCI_IRQ(124)
+#if defined(CONFIG_ARCH_SCX15) || defined(CONFIG_ARCH_SCX30G)
+#define IRQ_ZIPDEC_INT			SCI_IRQ(125)
+#define IRQ_ZIPENC_INT			SCI_IRQ(126)
+#endif
+
+#define IRQ_SIPC_CPW			IRQ_CP0_MCU0_INT
+#ifdef CONFIG_ARCH_SCX30G
+#define IRQ_SIPC_CPT 			IRQ_CP0_MCU0_INT
+#else
+#define IRQ_SIPC_CPT			IRQ_CP1_MCU0_INT
+#endif
+#define IRQ_SIPC_WCN			IRQ_CP2_INT0_INT
+
+
+/* translate gic irq number(user using ) to intc number */
+#define SCI_GET_INTC_IRQ(_IRQ_NUM_)	((_IRQ_NUM_) - IRQ_GIC_START)
+#define SCI_INTC_IRQ_BIT(_IRQ_NUM_)	((SCI_GET_INTC_IRQ(_IRQ_NUM_)<IRQ_GIC_START)	? \
+					(1<<SCI_GET_INTC_IRQ(_IRQ_NUM_))		: \
+					(1<<(SCI_GET_INTC_IRQ(_IRQ_NUM_)-IRQ_GIC_START)))
+
+/* analog die interrupt number */
+#define IRQ_ANA_ADC_INT			SCI_EXT_IRQ(0)
+#if defined(CONFIG_ARCH_SCX15)
+#define IRQ_ANA_GPIO_INT		-1
+#else
+#define IRQ_ANA_GPIO_INT		SCI_EXT_IRQ(1)
+#endif
+#define IRQ_ANA_RTC_INT			SCI_EXT_IRQ(2)
+#define IRQ_ANA_WDG_INT			SCI_EXT_IRQ(3)
+#define IRQ_ANA_FGU_INT			SCI_EXT_IRQ(4)
+#define IRQ_ANA_EIC_INT			SCI_EXT_IRQ(5)
+#define IRQ_ANA_AUD_HEAD_BUTTON_INT		SCI_EXT_IRQ(6)
+#define IRQ_ANA_AUD_PROTECT_INT			SCI_EXT_IRQ(7)
+#if defined(CONFIG_ARCH_SCX15)
+#define IRQ_ANA_CAL_INT			SCI_EXT_IRQ(8)
+#define IRQ_ANA_TPC_INT			SCI_EXT_IRQ(9)
+#define NR_ANA_IRQS			(10)
+#else
+#define IRQ_ANA_THM_OTP_INT			SCI_EXT_IRQ(9)
+#define IRQ_ANA_DCD_OTP_INT			SCI_EXT_IRQ(10)/*bit9 is reserved in adie intc*/
+#define NR_ANA_IRQS			(11)
+#endif
+
+#define IRQ_ANA_INT_START		IRQ_ANA_ADC_INT
+
+#if defined(CONFIG_ARCH_SCX15)
+#define GPIO_IRQ_START			SCI_EXT_IRQ(10)
+#define NR_GPIO_IRQS	( 320 )
+#else
+/* sc8830 gpio&eic pin interrupt number, total is 320, which is bigger than 256 */
+#define GPIO_IRQ_START			SCI_EXT_IRQ(11)
+#define NR_GPIO_IRQS	( 320 )
+#endif
+
+#if (defined(CONFIG_EIRQ_NUM) && CONFIG_EIRQ_NUM)
+#ifndef CONFIG_SPARSE_IRQ
+/* For external irq region desc request */
+#define __NR_IRQS			(NR_SCI_PHY_IRQS + NR_ANA_IRQS + NR_GPIO_IRQS)
+#define NR_IRQS				(__NR_IRQS + CONFIG_EIRQ_NUM)
+#else
+#error 'Dont support CONFIG_EIRQ_NUM & CONFIG_SPARSE_IRQ coexist'
+#endif /* CONFIG_SPARSE_IRQ */
+#else
+#define NR_IRQS				(NR_SCI_PHY_IRQS + NR_ANA_IRQS + NR_GPIO_IRQS)
+#endif /* CONFIG_EIRQ_NUM */
+#define FIQ_START	(0)
+#define NR_FIQS		(NR_SCI_PHY_IRQS)
+
+
+/* redefined some MACROS for module code*/
+#define IRQ_TIMER1_INT			IRQ_AONTMR0_INT
+#define IRQ_ANA_AUD_INT			IRQ_ANA_AUD_PROTECT_INT
+#endif
diff --git a/arch/arm/mach-sc/include/mach/debug-macro.S b/arch/arm/mach-sc/include/mach/debug-macro.S
new file mode 100644
index 00000000..d7394ea9
--- /dev/null
+++ b/arch/arm/mach-sc/include/mach/debug-macro.S
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2012 Spreadtrum Communications Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "hardware.h"
+
+	.macro  addruart,rp, rv, tmp
+	ldr \rp, =LL_DEBUG_UART_PHYS
+	ldr \rv, =LL_DEBUG_UART_BASE
+	.endm
+
+	.macro	senduart,rd,rx
+	and	\rd,\rd,#0xFF
+	str	\rd, [\rx, #0x00]
+	.endm
+
+	.macro	waituart,rd,rx
+	@ wait for TX_READY
+1:	ldr	\rd, [\rx, #0x0C]
+	mov	\rd,\rd,lsr #8
+	and	\rd,\rd,#0xFF
+	teq	\rd, #0x00
+	bne	1b
+	.endm
+
+	.macro	busyuart,rd,rx
+	@ wait for TX_READY
+2:	ldr	\rd, [\rx, #0x0C]
+	mov	\rd,\rd,lsr #8
+	and	\rd,\rd,#0xFF
+	teq	\rd, #0x00
+	bne	2b
+	.endm
diff --git a/arch/arm/mach-sc/include/mach/gpio.h b/arch/arm/mach-sc/include/mach/gpio.h
new file mode 100755
index 00000000..6a85491c
--- /dev/null
+++ b/arch/arm/mach-sc/include/mach/gpio.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (C) 2012 Spreadtrum Communications Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARM_ARCH_GPIO_H
+#define __ASM_ARM_ARCH_GPIO_H
+
+/*
+ * SC8825 GPIO&EIC bank and number summary:
+ *
+ * Bank	  From	  To	NR	Type
+ * 1	  0   ~	  15		16	EIC
+ * 2	  16  ~	  271	256	GPIO
+ * 3	  272 ~	  287	16	ANA EIC
+ * 4	  288 ~	  319	32	ANA GPIO
+ */
+
+#ifdef CONFIG_ARCH_SCX35
+#define	D_GPIO_START	0
+#define	D_GPIO_NR		256
+
+#define	A_GPIO_START	( D_GPIO_START + D_GPIO_NR )
+#if defined(CONFIG_ARCH_SCX15)
+#define	A_GPIO_NR		0
+#else
+#define	A_GPIO_NR		32
+#endif
+
+#define	D_EIC_START		( A_GPIO_START + A_GPIO_NR)
+#define	D_EIC_NR		16
+
+#define	A_EIC_START		( D_EIC_START + D_EIC_NR )
+#define	A_EIC_NR		16
+#else
+#define	D_EIC_START		0
+#define	D_EIC_NR		16
+
+#define	D_GPIO_START	( D_EIC_START + D_EIC_NR )
+#define	D_GPIO_NR		256
+
+#define	A_EIC_START		( D_GPIO_START + D_GPIO_NR )
+#define	A_EIC_NR		16
+
+#define	A_GPIO_START	( A_EIC_START + A_EIC_NR )
+#define	A_GPIO_NR		32
+#endif
+
+#define ARCH_NR_GPIOS	( D_EIC_NR + D_GPIO_NR + A_EIC_NR + A_GPIO_NR )
+
+#ifdef CONFIG_64BIT
+#include <asm-generic/gpio.h>
+#include <soc/sprd/irqs.h>
+#else
+#include <asm-generic/gpio.h>
+#include <mach/irqs.h>
+#endif
+
+#define gpio_get_value  __gpio_get_value
+#define gpio_set_value  __gpio_set_value
+#define gpio_cansleep   __gpio_cansleep
+#define gpio_to_irq     __gpio_to_irq
+
+
+/* Digital GPIO/EIC base address */
+#define CTL_GPIO_BASE          (SPRD_GPIO_BASE)
+#define CTL_EIC_BASE           (SPRD_EIC_BASE)
+
+/* Analog GPIO/EIC base address */
+
+#if defined(CONFIG_ARCH_SCX35)
+#define ANA_CTL_EIC_BASE	   (ANA_EIC_BASE)
+#define ANA_CTL_GPIO_BASE      (ANA_GPIO_INT_BASE)
+#else
+#define ANA_CTL_EIC_BASE       (SPRD_MISC_BASE + 0x0100)
+#define ANA_CTL_GPIO_BASE      (SPRD_MISC_BASE + 0x0480)
+#endif
+
+
+enum {
+       ENUM_ID_D_GPIO = 0,
+       ENUM_ID_D_EIC,
+       ENUM_ID_A_GPIO,
+       ENUM_ID_A_EIC,
+
+       ENUM_ID_END_NR,
+};
+
+struct eic_gpio_resource {
+       int irq;
+       int base_addr;
+       int chip_base;
+       int chip_ngpio;
+};
+
+static inline int irq_to_gpio(int irq)
+{
+	return irq - GPIO_IRQ_START;
+}
+
+#endif
diff --git a/arch/arm/mach-sc/include/mach/io.h b/arch/arm/mach-sc/include/mach/io.h
new file mode 100644
index 00000000..a023948b
--- /dev/null
+++ b/arch/arm/mach-sc/include/mach/io.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2012 Spreadtrum Communications Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#include <asm/system.h>
+#include <asm/io.h>
+
+#define IO_SPACE_LIMIT		0xffffffff
+
+#define __io(a)			((void __iomem *)(a))
+#define __mem_pci(a)		(a)
+
+#endif
diff --git a/arch/arm/mach-sc/include/mach/irqs.h b/arch/arm/mach-sc/include/mach/irqs.h
new file mode 100755
index 00000000..54ce8732
--- /dev/null
+++ b/arch/arm/mach-sc/include/mach/irqs.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2012 Spreadtrum Communications Inc.
+ * 
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_SCI_IRQS_H
+#define __ASM_ARCH_SCI_IRQS_H
+
+#if defined(CONFIG_ARCH_SCX35)
+#include "__irqs-sc8830.h"
+#elif defined(CONFIG_ARCH_SC8825)
+#include "__irqs-sc8825.h"
+#else
+#error "Unknown architecture specification"
+#endif
+
+#ifndef __ASSEMBLY__
+
+//	/*raw interrupt intc interrupt enable */
+//	void sci_intc_unmask(u32 irq);
+//	/*raw interrupt intc interrupt disable */
+//	void sci_intc_mask(u32 irq);
+
+#endif
+
+#endif
diff --git a/arch/arm/mach-sc/include/mach/timex.h b/arch/arm/mach-sc/include/mach/timex.h
new file mode 100644
index 00000000..26298250
--- /dev/null
+++ b/arch/arm/mach-sc/include/mach/timex.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2012 Spreadtrum Communications Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H __FILE__
+
+#define CLOCK_TICK_RATE		32768
+
+#endif
diff --git a/arch/arm/mach-sc/include/mach/uncompress.h b/arch/arm/mach-sc/include/mach/uncompress.h
new file mode 100644
index 00000000..89d7a9d4
--- /dev/null
+++ b/arch/arm/mach-sc/include/mach/uncompress.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2012 Spreadtrum Communications Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+
+#include <soc/sprd/hardware.h>
+
+static inline void putc(int c)
+{
+}
+
+static inline void flush(void)
+{
+}
+
+static inline void arch_decomp_setup(void)
+{
+}
+
+static inline void arch_decomp_wdog(void)
+{
+}
+#endif