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| author | Yuval Adam <_@yuv.al> | 2025-08-29 20:08:34 +0200 |
|---|---|---|
| committer | Yuval Adam <_@yuv.al> | 2025-08-29 20:08:34 +0200 |
| commit | 417ec05cc68242b72ce1260153051e07da4d8240 (patch) | |
| tree | 39219877121a602a7748cb9ba4709e8b972dabd1 /platform_alchitry_pt.py | |
| parent | d096f707822967aa99d37605198fc9acd5f6a90d (diff) | |
Cleanup things
Diffstat (limited to 'platform_alchitry_pt.py')
| -rw-r--r-- | platform_alchitry_pt.py | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/platform_alchitry_pt.py b/platform_alchitry_pt.py index 0b9d814..d7e5f0e 100644 --- a/platform_alchitry_pt.py +++ b/platform_alchitry_pt.py @@ -74,8 +74,6 @@ class AlchitryPtPlatform(XilinxPlatform): import subprocess import os - vivado_path = os.path.expanduser("~/Xilinx/2025.1/Vivado/bin/vivado") - with products.extract("{}.bit".format(name)) as bitstream_filename: # Create TCL script for programming tcl_content = f""" @@ -96,5 +94,5 @@ exit f.write(tcl_content) # Run vivado to program the FPGA - subprocess.run([vivado_path, "-mode", "batch", "-source", tcl_script], + subprocess.run(["vivado", "-mode", "batch", "-source", tcl_script], cwd="build", check=True)
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