diff options
| -rw-r--r-- | .gitignore | 24 | ||||
| -rw-r--r-- | README.md | 50 | ||||
| -rw-r--r-- | build_and_program.py | 16 | ||||
| -rw-r--r-- | list_targets.tcl | 8 | ||||
| -rw-r--r-- | platform_alchitry_pt.py | 4 | ||||
| -rw-r--r-- | test_connection.tcl | 7 |
6 files changed, 47 insertions, 62 deletions
@@ -1,7 +1,25 @@ -.venv/ +# Build artifacts build/ +.Xil/ -__pycache__ +# Python +__pycache__/ +*.py[cod] +*$py.class +.venv/ +# Vivado +*.jou *.log -*.jou
\ No newline at end of file +*.str +vivado*.backup.* +*.cache/ +*.hw/ +*.ip_user_files/ +*.runs/ +*.sim/ +*.srcs/ + +# Temporary files +*.tmp +*.temp
\ No newline at end of file @@ -4,22 +4,29 @@ A basic Amaranth HDL blinky example for the Alchitry Pt v2 development board wit ## Requirements -- Python 3.12+ +- Python 3.13+ - uv package manager -- Xilinx Vivado 2025.1 (installed at `~/Xilinx/2025.1/Vivado/`) +- Xilinx Vivado (with `vivado` command in PATH) - Alchitry Pt v2 board connected via USB ## Setup -1. Install dependencies: -```bash -uv sync -``` +1. **Install Python dependencies:** + ```bash + uv sync + ``` -2. Set up Vivado environment (add to your shell profile): -```bash -export PATH="$HOME/Xilinx/2025.1/Vivado/bin:$PATH" -``` +2. **Install udev rules for USB access:** + ```bash + sudo cp 99-alchitry-xilinx.rules /etc/udev/rules.d/ + sudo udevadm control --reload-rules + sudo udevadm trigger + ``` + +3. **Ensure Vivado is in PATH:** + ```bash + export PATH="/path/to/vivado/bin:$PATH" + ``` ## Usage @@ -48,26 +55,19 @@ platform.build(Blinky(), do_program=False) " ``` -### Manual Programming - -If you need to program manually after building: -```bash -cd build -vivado -mode batch -source program_fpga.tcl -``` - ## Files - `blinky.py` - Main blinky example that blinks LED 0 -- `platform_alchitry_pt.py` - Alchitry Pt v2 platform definition with pin mappings -- `pyproject.toml` - Project dependencies (Amaranth HDL) +- `platform_alchitry_pt.py` - Alchitry Pt v2 platform definition with official pin mappings +- `pyproject.toml` - Project dependencies +- `99-alchitry-xilinx.rules` - udev rules for USB programming access ## Hardware Details - **FPGA**: XC7A100T-2FGG484I (Artix-7, 484-pin BGA, speed grade -2) -- **Clock**: 100 MHz oscillator on pin N14 -- **LEDs**: 8 LEDs (pins K13, K16, L15, L14, M16, M14, M12, N16) -- **Reset**: Active-low reset button on pin P6 -- **IO**: 48 general purpose IO pins available +- **Clock**: 100 MHz oscillator on pin W19 +- **LEDs**: 8 LEDs (pins P19, P20, T21, R19, V22, U21, T20, W20) +- **Reset**: Active-low reset button on pin N15 +- **IO**: 32 general purpose IO pins from A/B/C banks -The example uses a 24-bit counter clocked at 100 MHz, with the MSB driving LED 0 for a blink rate of approximately 12 Hz. +Pin mappings are sourced from official Alchitry Labs V2 hardware definitions. diff --git a/build_and_program.py b/build_and_program.py deleted file mode 100644 index ba6c139..0000000 --- a/build_and_program.py +++ /dev/null @@ -1,16 +0,0 @@ -#!/usr/bin/env python3 - -import os -import sys - -# Add Vivado to PATH -vivado_bin = os.path.expanduser("~/Xilinx/2025.1/Vivado/bin") -os.environ["PATH"] = vivado_bin + ":" + os.environ.get("PATH", "") - -# Now run the original blinky script -from blinky import Blinky -from platform_alchitry_pt import AlchitryPtPlatform - -if __name__ == "__main__": - platform = AlchitryPtPlatform() - platform.build(Blinky(), do_program=True)
\ No newline at end of file diff --git a/list_targets.tcl b/list_targets.tcl deleted file mode 100644 index 5cbbc4c..0000000 --- a/list_targets.tcl +++ /dev/null @@ -1,8 +0,0 @@ -open_hw_manager -connect_hw_server -puts "Available targets:" -foreach target [get_hw_targets] { - puts "Target: $target" -} -close_hw_manager -exit
\ No newline at end of file diff --git a/platform_alchitry_pt.py b/platform_alchitry_pt.py index 0b9d814..d7e5f0e 100644 --- a/platform_alchitry_pt.py +++ b/platform_alchitry_pt.py @@ -74,8 +74,6 @@ class AlchitryPtPlatform(XilinxPlatform): import subprocess import os - vivado_path = os.path.expanduser("~/Xilinx/2025.1/Vivado/bin/vivado") - with products.extract("{}.bit".format(name)) as bitstream_filename: # Create TCL script for programming tcl_content = f""" @@ -96,5 +94,5 @@ exit f.write(tcl_content) # Run vivado to program the FPGA - subprocess.run([vivado_path, "-mode", "batch", "-source", tcl_script], + subprocess.run(["vivado", "-mode", "batch", "-source", tcl_script], cwd="build", check=True)
\ No newline at end of file diff --git a/test_connection.tcl b/test_connection.tcl deleted file mode 100644 index f2858c0..0000000 --- a/test_connection.tcl +++ /dev/null @@ -1,7 +0,0 @@ -open_hw_manager -connect_hw_server -open_hw_target -get_hw_targets -get_hw_devices -close_hw_manager -exit
\ No newline at end of file |