path: root/include/soc/sprd/chip_x20l/__regs_mdar_apb_rf.h

/*
 * Copyright (C) 2014 Spreadtrum Communications Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 *************************************************
 * Automatically generated C header: do not edit *
 *************************************************
 */

#ifndef __SCI_GLB_REGS_H__
#error  "Don't include this file directly, Pls include sci_glb_regs.h"
#endif


#ifndef __H_REGS_MDAR_APB_RF_HEADFILE_H__
#define __H_REGS_MDAR_APB_RF_HEADFILE_H__ __FILE__

#define	REGS_MDAR_APB_RF

/* registers definitions for MDAR_APB_RF */
#define REG_MDAR_APB_RF_MDAR_CFG0                         SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0000)
#define REG_MDAR_APB_RF_MDAR_CFG1                         SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0004)
#define REG_MDAR_APB_RF_MDAR_CFG3                         SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x000C)
#define REG_MDAR_APB_RF_MDAR_DAC1_CTR1                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0010)
#define REG_MDAR_APB_RF_MDAR_DAC1_CTR2                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0014)
#define REG_MDAR_APB_RF_MDAR_DAC1_CTR3                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0018)
#define REG_MDAR_APB_RF_MDAR_DAC1_CTR4                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x001C)
#define REG_MDAR_APB_RF_MDAR_DAC1_STS0                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0020)
#define REG_MDAR_APB_RF_MDAR_DAC1_STS1                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0024)
#define REG_MDAR_APB_RF_MDAR_CAL1_CTR0                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0028)
#define REG_MDAR_APB_RF_MDAR_CAL1_CTR1                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x002C)
#define REG_MDAR_APB_RF_MDAR_CAL1_CTR3                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0030)
#define REG_MDAR_APB_RF_MDAR_CAL1_STS0                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0034)
#define REG_MDAR_APB_RF_MDAR_CAL1_STS1                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0038)
#define REG_MDAR_APB_RF_MDAR_DAC1_CTR00                   SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x003C)
#define REG_MDAR_APB_RF_MDAR_DAC1_CTR10                   SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0040)
#define REG_MDAR_APB_RF_MDAR_ADC1_CTR0                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0044)
#define REG_MDAR_APB_RF_MDAR_ADC1_CTR00                   SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0048)
#define REG_MDAR_APB_RF_MDAR_ADC1_CTR01                   SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x004C)
#define REG_MDAR_APB_RF_MDAR_ADC1_CTR02                   SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0050)
#define REG_MDAR_APB_RF_MDAR_ADC1_CTR10                   SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0054)
#define REG_MDAR_APB_RF_MDAR_ADC1_CTR11                   SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0058)
#define REG_MDAR_APB_RF_MDAR_ADC1_CTR12                   SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x005C)
#define REG_MDAR_APB_RF_MDAR_ADC1_CTR20                   SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0060)
#define REG_MDAR_APB_RF_MDAR_ADC1_CTR21                   SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0064)
#define REG_MDAR_APB_RF_MDAR_ADC1_CTR22                   SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0068)
#define REG_MDAR_APB_RF_MDAR_DAC2_CTR1                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0070)
#define REG_MDAR_APB_RF_MDAR_DAC2_CTR2                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0074)
#define REG_MDAR_APB_RF_MDAR_DAC2_CTR3                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0078)
#define REG_MDAR_APB_RF_MDAR_DAC2_CTR4                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x007C)
#define REG_MDAR_APB_RF_MDAR_DAC2_STS0                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0080)
#define REG_MDAR_APB_RF_MDAR_DAC2_STS1                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0084)
#define REG_MDAR_APB_RF_MDAR_CAL2_CTR0                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0088)
#define REG_MDAR_APB_RF_MDAR_CAL2_CTR1                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x008C)
#define REG_MDAR_APB_RF_MDAR_CAL2_CTR3                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0090)
#define REG_MDAR_APB_RF_MDAR_CAL2_STS0                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0094)
#define REG_MDAR_APB_RF_MDAR_CAL2_STS1                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0098)
#define REG_MDAR_APB_RF_MDAR_DAC2_CTR00                   SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x009C)
#define REG_MDAR_APB_RF_MDAR_DAC2_CTR10                   SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00A0)
#define REG_MDAR_APB_RF_MDAR_ADC2_CTR0                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00A4)
#define REG_MDAR_APB_RF_MDAR_ADC2_CTR00                   SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00A8)
#define REG_MDAR_APB_RF_MDAR_ADC2_CTR01                   SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00AC)
#define REG_MDAR_APB_RF_MDAR_ADC2_CTR02                   SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00B0)
#define REG_MDAR_APB_RF_MDAR_ADC2_CTR10                   SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00B4)
#define REG_MDAR_APB_RF_MDAR_ADC2_CTR11                   SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00B8)
#define REG_MDAR_APB_RF_MDAR_ADC2_CTR12                   SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00BC)
#define REG_MDAR_APB_RF_MDAR_ADC2_CTR20                   SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00C0)
#define REG_MDAR_APB_RF_MDAR_ADC2_CTR21                   SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00C4)
#define REG_MDAR_APB_RF_MDAR_ADC2_CTR22                   SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00C8)
#define REG_MDAR_APB_RF_MDAR_DAC3_CTR1                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00D0)
#define REG_MDAR_APB_RF_MDAR_DAC3_CTR2                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00D4)
#define REG_MDAR_APB_RF_MDAR_DAC3_CTR3                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00D8)
#define REG_MDAR_APB_RF_MDAR_DAC3_CTR4                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00DC)
#define REG_MDAR_APB_RF_MDAR_DAC3_STS0                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00E0)
#define REG_MDAR_APB_RF_MDAR_DAC3_STS1                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00E4)
#define REG_MDAR_APB_RF_MDAR_CAL3_CTR0                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00E8)
#define REG_MDAR_APB_RF_MDAR_CAL3_CTR1                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00EC)
#define REG_MDAR_APB_RF_MDAR_CAL3_CTR3                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00F0)
#define REG_MDAR_APB_RF_MDAR_CAL3_STS0                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00F4)
#define REG_MDAR_APB_RF_MDAR_CAL3_STS1                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00F8)
#define REG_MDAR_APB_RF_MDAR_DAC3_CTR00                   SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x00FC)
#define REG_MDAR_APB_RF_MDAR_DAC3_CTR10                   SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0100)
#define REG_MDAR_APB_RF_MDAR_ADC3_CTR0                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0104)
#define REG_MDAR_APB_RF_MDAR_ADC3_CTR00                   SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0108)
#define REG_MDAR_APB_RF_MDAR_ADC3_CTR01                   SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x010C)
#define REG_MDAR_APB_RF_MDAR_ADC3_CTR02                   SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0110)
#define REG_MDAR_APB_RF_MDAR_ADC3_CTR10                   SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0114)
#define REG_MDAR_APB_RF_MDAR_ADC3_CTR11                   SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0118)
#define REG_MDAR_APB_RF_MDAR_ADC3_CTR12                   SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x011C)
#define REG_MDAR_APB_RF_MDAR_ADC3_CTR20                   SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0120)
#define REG_MDAR_APB_RF_MDAR_ADC3_CTR21                   SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0124)
#define REG_MDAR_APB_RF_MDAR_ADC3_CTR22                   SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0128)
#define REG_MDAR_APB_RF_MDAR_AFCDAC1_CFG                  SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x012C)
#define REG_MDAR_APB_RF_MDAR_AFCDAC2_CFG                  SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0130)
#define REG_MDAR_APB_RF_MDAR_APCDAC1_CFG                  SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0134)
#define REG_MDAR_APB_RF_MDAR_APCDAC2_CFG                  SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0138)
#define REG_MDAR_APB_RF_MDAR_RFSPI_CFG                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x13C)
#define REG_MDAR_APB_RF_MDAR_RFMIPI_CFG                   SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x140)
#define REG_MDAR_APB_RF_MDAR_APCDAC_OUTSEL                SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x144)
#define REG_MDAR_APB_RF_MDAR_CLASH_CHK                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x148)
#define REG_MDAR_APB_RF_MDAR_CLASH_SNAP                   SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x14C)
#define REG_MDAR_APB_RF_MDAR_CLASH_STATUS1                SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x150)
#define REG_MDAR_APB_RF_MDAR_CLASH_STATUS2                SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x154)
#define REG_MDAR_APB_RF_MDAR_CLASH_STATUS3                SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x158)
#define REG_MDAR_APB_RF_MDAR_EXTRA_CFG0                   SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x160)
#define REG_MDAR_APB_RF_MDAR_EXTRA_CFG1                   SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x164)
#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF0                SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x168)
#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF1                SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x16C)
#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF2                SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x170)
#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF3                SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x174)
#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF4                SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x178)
#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF5                SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x17C)
#define REG_MDAR_APB_RF_MDAR_RFCTRL15_INF6                SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x180)
#define REG_MDAR_APB_RF_MDAR_CFG4                         SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0184)
#define REG_MDAR_APB_RF_MDAR_CFG5                         SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0188)
#define REG_MDAR_APB_RF_MDAR_CFG6                         SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x018C)
#define REG_MDAR_APB_RF_MDAR_CFG7                         SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0190)
#define REG_MDAR_APB_RF_MDAR_CFG8                         SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0194)
#define REG_MDAR_APB_RF_MDAR_CFG9                         SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x0198)
#define REG_MDAR_APB_RF_MDAR_CFG10                        SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x019C)
#define REG_MDAR_APB_RF_MDAR_CFG11                        SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x01B0)
#define REG_MDAR_APB_RF_MDAR_CFG12                        SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x01B4)
#define REG_MDAR_APB_RF_MDAR_CFG13                        SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x01B8)
#define REG_MDAR_APB_RF_MDAR_CFG14                        SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x01BC)
#define REG_MDAR_APB_RF_MDAR_CFG15                        SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1C0)
#define REG_MDAR_APB_RF_MDAR_IMB_CFG10                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1C4)
#define REG_MDAR_APB_RF_MDAR_IMB_CFG11                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1C8)
#define REG_MDAR_APB_RF_MDAR_IMB_CFG12                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1CC)
#define REG_MDAR_APB_RF_MDAR_IMB_CFG13                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1D0)
#define REG_MDAR_APB_RF_MDAR_IMB_CFG14                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1D4)
#define REG_MDAR_APB_RF_MDAR_IMB_CFG20                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1D8)
#define REG_MDAR_APB_RF_MDAR_IMB_CFG21                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1DC)
#define REG_MDAR_APB_RF_MDAR_IMB_CFG22                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1E0)
#define REG_MDAR_APB_RF_MDAR_IMB_CFG23                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1E4)
#define REG_MDAR_APB_RF_MDAR_IMB_CFG24                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1E8)
#define REG_MDAR_APB_RF_MDAR_IMB_CFG30                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1EC)
#define REG_MDAR_APB_RF_MDAR_IMB_CFG31                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1F0)
#define REG_MDAR_APB_RF_MDAR_IMB_CFG32                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1F4)
#define REG_MDAR_APB_RF_MDAR_IMB_CFG33                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1F8)
#define REG_MDAR_APB_RF_MDAR_IMB_CFG34                    SCI_ADDR(REGS_MDAR_APB_RF_BASE, 0x1FC)



/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG0 */
#define BIT_MDAR_ADA_MODE                                 ( BIT(31) )
#define BITS_ADC3_CHANNEL_SSET(_X_)                       ( (_X_) << 26 & (BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) )
#define BITS_ADC2_CHANNEL_SSET(_X_)                       ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) )
#define BITS_ADC1_CHANNEL_SSET(_X_)                       ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)) )
#define BIT_MDAR_WTG_MODE                                 ( BIT(15) )
#define BITS_ADC3_CHANNEL_MASK(_X_)                       ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
#define BITS_ADC2_CHANNEL_MASK(_X_)                       ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
#define BITS_ADC1_CHANNEL_MASK(_X_)                       ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG1 */
#define BITS_DAC3_CHANNEL_SSET(_X_)                       ( (_X_) << 26 & (BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) )
#define BITS_DAC2_CHANNEL_SSET(_X_)                       ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) )
#define BITS_DAC1_CHANNEL_SSET(_X_)                       ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)) )
#define BITS_DAC3_CHANNEL_MASK(_X_)                       ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
#define BITS_DAC2_CHANNEL_MASK(_X_)                       ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
#define BITS_DAC1_CHANNEL_MASK(_X_)                       ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG3 */
#define BITS_DACX_SBC_SET(_X_)                            ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
#define BITS_ADCX_SBC_SET(_X_)                            ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_CTR1 */
#define BITS_DAC1_WD_OVR(_X_)                             ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
#define BITS_DAC1_WADDR_OVR(_X_)                          ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
#define BIT_DAC1_WLE_OVR                                  ( BIT(2) )
#define BIT_DAC1_W_OVR_I_QN                               ( BIT(1) )
#define BIT_DAC1_W_OVR_EN                                 ( BIT(0) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_CTR2 */
#define BIT_DAC1_AUTO_RST                                 ( BIT(23) )
#define BIT_DAC1_SOFT_RST                                 ( BIT(22) )
#define BIT_DAC1_OSBC                                     ( BIT(21) )
#define BIT_DAC1_ISBC                                     ( BIT(20) )
#define BIT_DAC1_OVR_EN_CAL                               ( BIT(19) )
#define BIT_DAC1_EN_OOSCAL                                ( BIT(18) )
#define BIT_DAC1_IQSWAP                                   ( BIT(17) )
#define BIT_DAC1_CAL_START                                ( BIT(16) )
#define BITS_DAC1_OFFSETI(_X_)                            ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BITS_DAC1_OFFSETQ(_X_)                            ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_CTR3 */
#define BITS_DAC1_Q_DC(_X_)                               ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
#define BITS_DAC1_I_DC(_X_)                               ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_CTR4 */
#define BITS_DAC1_I_CAL(_X_)                              ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
#define BITS_DAC1_Q_CAL(_X_)                              ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_STS0 */
#define BITS_DAC1_WTI(_X_)                                ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
#define BITS_DAC1_WTQ(_X_)                                ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_STS1 */
#define BITS_DAC1_DA_STATE(_X_)                           ( (_X_) << 17 & (BIT(17)|BIT(18)) )
#define BIT_DAC1_DONE                                     ( BIT(16) )
#define BITS_DAC1_WQ_OVR(_X_)                             ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL1_CTR0 */
#define BITS_ADC1_CLK_CAL_DLY(_X_)                        ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BITS_ADA1_CAL_WAIT(_X_)                           ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_CLK_ADA1_CAL_EN                               ( BIT(6) )
#define BIT_DAC1_PD_CAL                                   ( BIT(5) )
#define BIT_ADC1_EN_CAL                                   ( BIT(3) )
#define BIT_ADC1_CAL                                      ( BIT(1) )
#define BIT_ADA1_MODE_SEL                                 ( BIT(0) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL1_CTR1 */
#define BITS_ADC1_Q_DC(_X_)                               ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) )
#define BITS_ADC1_I_DC(_X_)                               ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL1_CTR3 */
#define BIT_ADA1_CAL_START                                ( BIT(0) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL1_STS0 */
#define BIT_ADA1_CAL_DONE                                 ( BIT(31) )
#define BITS_ADC1_CAL_I_SUM(_X_)                          ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL1_STS1 */
#define BITS_ADC1_CAL_Q_SUM(_X_)                          ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_CTR00 */
#define BIT_DAC1_OUT_SEL_2                                ( BIT(26) )
#define BITS_DAC1_RSV_2(_X_)                              ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) )
#define BITS_DAC1_PCTRL_2(_X_)                            ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)) )
#define BIT_DAC1_CLK_SEL_2                                ( BIT(18) )
#define BIT_DAC1_OUT_SEL_1                                ( BIT(17) )
#define BITS_DAC1_RSV_1(_X_)                              ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)) )
#define BITS_DAC1_PCTRL_1(_X_)                            ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) )
#define BIT_DAC1_CLK_SEL_1                                ( BIT(9) )
#define BIT_DAC1_OUT_SEL_0                                ( BIT(8) )
#define BITS_DAC1_RSV_0(_X_)                              ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
#define BITS_DAC1_PCTRL_0(_X_)                            ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)) )
#define BIT_DAC1_CLK_SEL_0                                ( BIT(0) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC1_CTR10 */
#define BIT_DAC1_OUT_SEL_5                                ( BIT(26) )
#define BITS_DAC1_RSV_5(_X_)                              ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) )
#define BITS_DAC1_PCTRL_5(_X_)                            ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)) )
#define BIT_DAC1_CLK_SEL_5                                ( BIT(18) )
#define BIT_DAC1_OUT_SEL_4                                ( BIT(17) )
#define BITS_DAC1_RSV_4(_X_)                              ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)) )
#define BITS_DAC1_PCTRL_4(_X_)                            ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) )
#define BIT_DAC1_CLK_SEL_4                                ( BIT(9) )
#define BIT_DAC1_OUT_SEL_3                                ( BIT(8) )
#define BITS_DAC1_RSV_3(_X_)                              ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
#define BITS_DAC1_PCTRL_3(_X_)                            ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)) )
#define BIT_DAC1_CLK_SEL_3                                ( BIT(0) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR0 */
#define BIT_ADC1_SOFT_RST                                 ( BIT(31) )
#define BITS_ADC1_DLL_OUT(_X_)                            ( (_X_) << 25 & (BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) )
#define BITS_ADC1_CALRDOUT(_X_)                           ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) )
#define BIT_ADC1_DLL_SOFT_RST                             ( BIT(10) )
#define BIT_ADC1_CAL_SOFT_RST                             ( BIT(9) )
#define BIT_ADC1_CALRD                                    ( BIT(8) )
#define BIT_ADC1_CALEN                                    ( BIT(7) )
#define BITS_ADC1_CALADDR(_X_)                            ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) )
#define BIT_ADC1_DEBUG_EN                                 ( BIT(0) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR00 */
#define BITS_ADC1_RSV_1(_X_)                              ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
#define BITS_ADC1_RSV_0(_X_)                              ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR01 */
#define BIT_ADC1_DIG_CLK_SEL_0                            ( BIT(30) )
#define BIT_ADC1_VCM_SEL_0                                ( BIT(29) )
#define BITS_ADC1_DELAY_CAP_0(_X_)                        ( (_X_) << 27 & (BIT(27)|BIT(28)) )
#define BITS_ADC1_BIT_SEL_0(_X_)                          ( (_X_) << 25 & (BIT(25)|BIT(26)) )
#define BITS_ADC1_VREF_SEL_0(_X_)                         ( (_X_) << 23 & (BIT(23)|BIT(24)) )
#define BITS_ADC1_VREF_BOOST_0(_X_)                       ( (_X_) << 21 & (BIT(21)|BIT(22)) )
#define BITS_ADC1_QUANT_BOOST_0(_X_)                      ( (_X_) << 19 & (BIT(19)|BIT(20)) )
#define BIT_ADC1_DLLRD_0                                  ( BIT(18) )
#define BIT_ADC1_DLLWR_0                                  ( BIT(17) )
#define BIT_ADC1_DLLEN_0                                  ( BIT(16) )
#define BIT_ADC1_CSBC                                     ( BIT(15) )
#define BIT_ADC1_IQSWAP                                   ( BIT(14) )
#define BITS_ADC1_DLLOOF_0(_X_)                           ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
#define BIT_ADC1_OSBC                                     ( BIT(7) )
#define BIT_ADC1_ISBC                                     ( BIT(6) )
#define BITS_ADC1_DLLIN_0(_X_)                            ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR02 */
#define BIT_ADC1_DIG_CLK_SEL_1                            ( BIT(30) )
#define BIT_ADC1_VCM_SEL_1                                ( BIT(29) )
#define BITS_ADC1_DELAY_CAP_1(_X_)                        ( (_X_) << 27 & (BIT(27)|BIT(28)) )
#define BITS_ADC1_BIT_SEL_1(_X_)                          ( (_X_) << 25 & (BIT(25)|BIT(26)) )
#define BITS_ADC1_VREF_SEL_1(_X_)                         ( (_X_) << 23 & (BIT(23)|BIT(24)) )
#define BITS_ADC1_VREF_BOOST_1(_X_)                       ( (_X_) << 21 & (BIT(21)|BIT(22)) )
#define BITS_ADC1_QUANT_BOOST_1(_X_)                      ( (_X_) << 19 & (BIT(19)|BIT(20)) )
#define BIT_ADC1_DLLRD_1                                  ( BIT(18) )
#define BIT_ADC1_DLLWR_1                                  ( BIT(17) )
#define BIT_ADC1_DLLEN_1                                  ( BIT(16) )
#define BITS_ADC1_DLLOOF_1(_X_)                           ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
#define BITS_ADC1_DLLIN_1(_X_)                            ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR10 */
#define BITS_ADC1_RSV_3(_X_)                              ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
#define BITS_ADC1_RSV_2(_X_)                              ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR11 */
#define BIT_ADC1_DIG_CLK_SEL_2                            ( BIT(30) )
#define BIT_ADC1_VCM_SEL_2                                ( BIT(29) )
#define BITS_ADC1_DELAY_CAP_2(_X_)                        ( (_X_) << 27 & (BIT(27)|BIT(28)) )
#define BITS_ADC1_BIT_SEL_2(_X_)                          ( (_X_) << 25 & (BIT(25)|BIT(26)) )
#define BITS_ADC1_VREF_SEL_2(_X_)                         ( (_X_) << 23 & (BIT(23)|BIT(24)) )
#define BITS_ADC1_VREF_BOOST_2(_X_)                       ( (_X_) << 21 & (BIT(21)|BIT(22)) )
#define BITS_ADC1_QUANT_BOOST_2(_X_)                      ( (_X_) << 19 & (BIT(19)|BIT(20)) )
#define BIT_ADC1_DLLRD_2                                  ( BIT(18) )
#define BIT_ADC1_DLLWR_2                                  ( BIT(17) )
#define BIT_ADC1_DLLEN_2                                  ( BIT(16) )
#define BITS_ADC1_DLLOOF_2(_X_)                           ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
#define BITS_ADC1_DLLIN_2(_X_)                            ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR12 */
#define BIT_ADC1_DIG_CLK_SEL_3                            ( BIT(30) )
#define BIT_ADC1_VCM_SEL_3                                ( BIT(29) )
#define BITS_ADC1_DELAY_CAP_3(_X_)                        ( (_X_) << 27 & (BIT(27)|BIT(28)) )
#define BITS_ADC1_BIT_SEL_3(_X_)                          ( (_X_) << 25 & (BIT(25)|BIT(26)) )
#define BITS_ADC1_VREF_SEL_3(_X_)                         ( (_X_) << 23 & (BIT(23)|BIT(24)) )
#define BITS_ADC1_VREF_BOOST_3(_X_)                       ( (_X_) << 21 & (BIT(21)|BIT(22)) )
#define BITS_ADC1_QUANT_BOOST_3(_X_)                      ( (_X_) << 19 & (BIT(19)|BIT(20)) )
#define BIT_ADC1_DLLRD_3                                  ( BIT(18) )
#define BIT_ADC1_DLLWR_3                                  ( BIT(17) )
#define BIT_ADC1_DLLEN_3                                  ( BIT(16) )
#define BITS_ADC1_DLLOOF_3(_X_)                           ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
#define BITS_ADC1_DLLIN_3(_X_)                            ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR20 */
#define BITS_ADC1_RSV_5(_X_)                              ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
#define BITS_ADC1_RSV_4(_X_)                              ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR21 */
#define BIT_ADC1_DIG_CLK_SEL_4                            ( BIT(30) )
#define BIT_ADC1_VCM_SEL_4                                ( BIT(29) )
#define BITS_ADC1_DELAY_CAP_4(_X_)                        ( (_X_) << 27 & (BIT(27)|BIT(28)) )
#define BITS_ADC1_BIT_SEL_4(_X_)                          ( (_X_) << 25 & (BIT(25)|BIT(26)) )
#define BITS_ADC1_VREF_SEL_4(_X_)                         ( (_X_) << 23 & (BIT(23)|BIT(24)) )
#define BITS_ADC1_VREF_BOOST_4(_X_)                       ( (_X_) << 21 & (BIT(21)|BIT(22)) )
#define BITS_ADC1_QUANT_BOOST_4(_X_)                      ( (_X_) << 19 & (BIT(19)|BIT(20)) )
#define BIT_ADC1_DLLRD_4                                  ( BIT(18) )
#define BIT_ADC1_DLLWR_4                                  ( BIT(17) )
#define BIT_ADC1_DLLEN_4                                  ( BIT(16) )
#define BITS_ADC1_DLLOOF_4(_X_)                           ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
#define BITS_ADC1_DLLIN_4(_X_)                            ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC1_CTR22 */
#define BIT_ADC1_DIG_CLK_SEL_5                            ( BIT(30) )
#define BIT_ADC1_VCM_SEL_5                                ( BIT(29) )
#define BITS_ADC1_DELAY_CAP_5(_X_)                        ( (_X_) << 27 & (BIT(27)|BIT(28)) )
#define BITS_ADC1_BIT_SEL_5(_X_)                          ( (_X_) << 25 & (BIT(25)|BIT(26)) )
#define BITS_ADC1_VREF_SEL_5(_X_)                         ( (_X_) << 23 & (BIT(23)|BIT(24)) )
#define BITS_ADC1_VREF_BOOST_5(_X_)                       ( (_X_) << 21 & (BIT(21)|BIT(22)) )
#define BITS_ADC1_QUANT_BOOST_5(_X_)                      ( (_X_) << 19 & (BIT(19)|BIT(20)) )
#define BIT_ADC1_DLLRD_5                                  ( BIT(18) )
#define BIT_ADC1_DLLWR_5                                  ( BIT(17) )
#define BIT_ADC1_DLLEN_5                                  ( BIT(16) )
#define BITS_ADC1_DLLOOF_5(_X_)                           ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
#define BITS_ADC1_DLLIN_5(_X_)                            ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_CTR1 */
#define BITS_DAC2_WD_OVR(_X_)                             ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
#define BITS_DAC2_WADDR_OVR(_X_)                          ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
#define BIT_DAC2_WLE_OVR                                  ( BIT(2) )
#define BIT_DAC2_W_OVR_I_QN                               ( BIT(1) )
#define BIT_DAC2_W_OVR_EN                                 ( BIT(0) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_CTR2 */
#define BIT_DAC2_AUTO_RST                                 ( BIT(23) )
#define BIT_DAC2_SOFT_RST                                 ( BIT(22) )
#define BIT_DAC2_OSBC                                     ( BIT(21) )
#define BIT_DAC2_ISBC                                     ( BIT(20) )
#define BIT_DAC2_OVR_EN_CAL                               ( BIT(19) )
#define BIT_DAC2_EN_OOSCAL                                ( BIT(18) )
#define BIT_DAC2_IQSWAP                                   ( BIT(17) )
#define BIT_DAC2_CAL_START                                ( BIT(16) )
#define BITS_DAC2_OFFSETI(_X_)                            ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BITS_DAC2_OFFSETQ(_X_)                            ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_CTR3 */
#define BITS_DAC2_Q_DC(_X_)                               ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
#define BITS_DAC2_I_DC(_X_)                               ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_CTR4 */
#define BITS_DAC2_I_CAL(_X_)                              ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
#define BITS_DAC2_Q_CAL(_X_)                              ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_STS0 */
#define BITS_DAC2_WTI(_X_)                                ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
#define BITS_DAC2_WTQ(_X_)                                ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_STS1 */
#define BITS_DAC2_DA_STATE(_X_)                           ( (_X_) << 17 & (BIT(17)|BIT(18)) )
#define BIT_DAC2_DONE                                     ( BIT(16) )
#define BITS_DAC2_WQ_OVR(_X_)                             ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL2_CTR0 */
#define BITS_ADC2_CLK_CAL_DLY(_X_)                        ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BITS_ADA2_CAL_WAIT(_X_)                           ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_CLK_ADA2_CAL_EN                               ( BIT(6) )
#define BIT_DAC2_PD_CAL                                   ( BIT(5) )
#define BIT_ADC2_EN_CAL                                   ( BIT(3) )
#define BIT_ADC2_CAL                                      ( BIT(1) )
#define BIT_ADA2_MODE_SEL                                 ( BIT(0) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL2_CTR1 */
#define BITS_ADC2_Q_DC(_X_)                               ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) )
#define BITS_ADC2_I_DC(_X_)                               ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL2_CTR3 */
#define BIT_ADA2_CAL_START                                ( BIT(0) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL2_STS0 */
#define BIT_ADA2_CAL_DONE                                 ( BIT(31) )
#define BITS_ADC2_CAL_I_SUM(_X_)                          ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL2_STS1 */
#define BITS_ADC2_CAL_Q_SUM(_X_)                          ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_CTR00 */
#define BIT_DAC2_OUT_SEL_2                                ( BIT(26) )
#define BITS_DAC2_RSV_2(_X_)                              ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) )
#define BITS_DAC2_PCTRL_2(_X_)                            ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)) )
#define BIT_DAC2_CLK_SEL_2                                ( BIT(18) )
#define BIT_DAC2_OUT_SEL_1                                ( BIT(17) )
#define BITS_DAC2_RSV_1(_X_)                              ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)) )
#define BITS_DAC2_PCTRL_1(_X_)                            ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) )
#define BIT_DAC2_CLK_SEL_1                                ( BIT(9) )
#define BIT_DAC2_OUT_SEL_0                                ( BIT(8) )
#define BITS_DAC2_RSV_0(_X_)                              ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
#define BITS_DAC2_PCTRL_0(_X_)                            ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)) )
#define BIT_DAC2_CLK_SEL_0                                ( BIT(0) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC2_CTR10 */
#define BIT_DAC2_OUT_SEL_5                                ( BIT(26) )
#define BITS_DAC2_RSV_5(_X_)                              ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) )
#define BITS_DAC2_PCTRL_5(_X_)                            ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)) )
#define BIT_DAC2_CLK_SEL_5                                ( BIT(18) )
#define BIT_DAC2_OUT_SEL_4                                ( BIT(17) )
#define BITS_DAC2_RSV_4(_X_)                              ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)) )
#define BITS_DAC2_PCTRL_4(_X_)                            ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) )
#define BIT_DAC2_CLK_SEL_4                                ( BIT(9) )
#define BIT_DAC2_OUT_SEL_3                                ( BIT(8) )
#define BITS_DAC2_RSV_3(_X_)                              ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
#define BITS_DAC2_PCTRL_3(_X_)                            ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)) )
#define BIT_DAC2_CLK_SEL_3                                ( BIT(0) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR0 */
#define BIT_ADC2_SOFT_RST                                 ( BIT(31) )
#define BITS_ADC2_DLL_OUT(_X_)                            ( (_X_) << 25 & (BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) )
#define BITS_ADC2_CALRDOUT(_X_)                           ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) )
#define BIT_ADC2_DLL_SOFT_RST                             ( BIT(10) )
#define BIT_ADC2_CAL_SOFT_RST                             ( BIT(9) )
#define BIT_ADC2_CALRD                                    ( BIT(8) )
#define BIT_ADC2_CALEN                                    ( BIT(7) )
#define BITS_ADC2_CALADDR(_X_)                            ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) )
#define BIT_ADC2_DEBUG_EN                                 ( BIT(0) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR00 */
#define BITS_ADC2_RSV_1(_X_)                              ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
#define BITS_ADC2_RSV_0(_X_)                              ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR01 */
#define BIT_ADC2_DIG_CLK_SEL_0                            ( BIT(30) )
#define BIT_ADC2_VCM_SEL_0                                ( BIT(29) )
#define BITS_ADC2_DELAY_CAP_0(_X_)                        ( (_X_) << 27 & (BIT(27)|BIT(28)) )
#define BITS_ADC2_BIT_SEL_0(_X_)                          ( (_X_) << 25 & (BIT(25)|BIT(26)) )
#define BITS_ADC2_VREF_SEL_0(_X_)                         ( (_X_) << 23 & (BIT(23)|BIT(24)) )
#define BITS_ADC2_VREF_BOOST_0(_X_)                       ( (_X_) << 21 & (BIT(21)|BIT(22)) )
#define BITS_ADC2_QUANT_BOOST_0(_X_)                      ( (_X_) << 19 & (BIT(19)|BIT(20)) )
#define BIT_ADC2_DLLRD_0                                  ( BIT(18) )
#define BIT_ADC2_DLLWR_0                                  ( BIT(17) )
#define BIT_ADC2_DLLEN_0                                  ( BIT(16) )
#define BIT_ADC2_CSBC                                     ( BIT(15) )
#define BIT_ADC2_IQSWAP                                   ( BIT(14) )
#define BITS_ADC2_DLLOOF_0(_X_)                           ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
#define BIT_ADC2_OSBC                                     ( BIT(7) )
#define BIT_ADC2_ISBC                                     ( BIT(6) )
#define BITS_ADC2_DLLIN_0(_X_)                            ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR02 */
#define BIT_ADC2_DIG_CLK_SEL_1                            ( BIT(30) )
#define BIT_ADC2_VCM_SEL_1                                ( BIT(29) )
#define BITS_ADC2_DELAY_CAP_1(_X_)                        ( (_X_) << 27 & (BIT(27)|BIT(28)) )
#define BITS_ADC2_BIT_SEL_1(_X_)                          ( (_X_) << 25 & (BIT(25)|BIT(26)) )
#define BITS_ADC2_VREF_SEL_1(_X_)                         ( (_X_) << 23 & (BIT(23)|BIT(24)) )
#define BITS_ADC2_VREF_BOOST_1(_X_)                       ( (_X_) << 21 & (BIT(21)|BIT(22)) )
#define BITS_ADC2_QUANT_BOOST_1(_X_)                      ( (_X_) << 19 & (BIT(19)|BIT(20)) )
#define BIT_ADC2_DLLRD_1                                  ( BIT(18) )
#define BIT_ADC2_DLLWR_1                                  ( BIT(17) )
#define BIT_ADC2_DLLEN_1                                  ( BIT(16) )
#define BITS_ADC2_DLLOOF_1(_X_)                           ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
#define BITS_ADC2_DLLIN_1(_X_)                            ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR10 */
#define BITS_ADC2_RSV_3(_X_)                              ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
#define BITS_ADC2_RSV_2(_X_)                              ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR11 */
#define BIT_ADC2_DIG_CLK_SEL_2                            ( BIT(30) )
#define BIT_ADC2_VCM_SEL_2                                ( BIT(29) )
#define BITS_ADC2_DELAY_CAP_2(_X_)                        ( (_X_) << 27 & (BIT(27)|BIT(28)) )
#define BITS_ADC2_BIT_SEL_2(_X_)                          ( (_X_) << 25 & (BIT(25)|BIT(26)) )
#define BITS_ADC2_VREF_SEL_2(_X_)                         ( (_X_) << 23 & (BIT(23)|BIT(24)) )
#define BITS_ADC2_VREF_BOOST_2(_X_)                       ( (_X_) << 21 & (BIT(21)|BIT(22)) )
#define BITS_ADC2_QUANT_BOOST_2(_X_)                      ( (_X_) << 19 & (BIT(19)|BIT(20)) )
#define BIT_ADC2_DLLRD_2                                  ( BIT(18) )
#define BIT_ADC2_DLLWR_2                                  ( BIT(17) )
#define BIT_ADC2_DLLEN_2                                  ( BIT(16) )
#define BITS_ADC2_DLLOOF_2(_X_)                           ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
#define BITS_ADC2_DLLIN_2(_X_)                            ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR12 */
#define BIT_ADC2_DIG_CLK_SEL_3                            ( BIT(30) )
#define BIT_ADC2_VCM_SEL_3                                ( BIT(29) )
#define BITS_ADC2_DELAY_CAP_3(_X_)                        ( (_X_) << 27 & (BIT(27)|BIT(28)) )
#define BITS_ADC2_BIT_SEL_3(_X_)                          ( (_X_) << 25 & (BIT(25)|BIT(26)) )
#define BITS_ADC2_VREF_SEL_3(_X_)                         ( (_X_) << 23 & (BIT(23)|BIT(24)) )
#define BITS_ADC2_VREF_BOOST_3(_X_)                       ( (_X_) << 21 & (BIT(21)|BIT(22)) )
#define BITS_ADC2_QUANT_BOOST_3(_X_)                      ( (_X_) << 19 & (BIT(19)|BIT(20)) )
#define BIT_ADC2_DLLRD_3                                  ( BIT(18) )
#define BIT_ADC2_DLLWR_3                                  ( BIT(17) )
#define BIT_ADC2_DLLEN_3                                  ( BIT(16) )
#define BITS_ADC2_DLLOOF_3(_X_)                           ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
#define BITS_ADC2_DLLIN_3(_X_)                            ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR20 */
#define BITS_ADC2_RSV_5(_X_)                              ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
#define BITS_ADC2_RSV_4(_X_)                              ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR21 */
#define BIT_ADC2_DIG_CLK_SEL_4                            ( BIT(30) )
#define BIT_ADC2_VCM_SEL_4                                ( BIT(29) )
#define BITS_ADC2_DELAY_CAP_4(_X_)                        ( (_X_) << 27 & (BIT(27)|BIT(28)) )
#define BITS_ADC2_BIT_SEL_4(_X_)                          ( (_X_) << 25 & (BIT(25)|BIT(26)) )
#define BITS_ADC2_VREF_SEL_4(_X_)                         ( (_X_) << 23 & (BIT(23)|BIT(24)) )
#define BITS_ADC2_VREF_BOOST_4(_X_)                       ( (_X_) << 21 & (BIT(21)|BIT(22)) )
#define BITS_ADC2_QUANT_BOOST_4(_X_)                      ( (_X_) << 19 & (BIT(19)|BIT(20)) )
#define BIT_ADC2_DLLRD_4                                  ( BIT(18) )
#define BIT_ADC2_DLLWR_4                                  ( BIT(17) )
#define BIT_ADC2_DLLEN_4                                  ( BIT(16) )
#define BITS_ADC2_DLLOOF_4(_X_)                           ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
#define BITS_ADC2_DLLIN_4(_X_)                            ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC2_CTR22 */
#define BIT_ADC2_DIG_CLK_SEL_5                            ( BIT(30) )
#define BIT_ADC2_VCM_SEL_5                                ( BIT(29) )
#define BITS_ADC2_DELAY_CAP_5(_X_)                        ( (_X_) << 27 & (BIT(27)|BIT(28)) )
#define BITS_ADC2_BIT_SEL_5(_X_)                          ( (_X_) << 25 & (BIT(25)|BIT(26)) )
#define BITS_ADC2_VREF_SEL_5(_X_)                         ( (_X_) << 23 & (BIT(23)|BIT(24)) )
#define BITS_ADC2_VREF_BOOST_5(_X_)                       ( (_X_) << 21 & (BIT(21)|BIT(22)) )
#define BITS_ADC2_QUANT_BOOST_5(_X_)                      ( (_X_) << 19 & (BIT(19)|BIT(20)) )
#define BIT_ADC2_DLLRD_5                                  ( BIT(18) )
#define BIT_ADC2_DLLWR_5                                  ( BIT(17) )
#define BIT_ADC2_DLLEN_5                                  ( BIT(16) )
#define BITS_ADC2_DLLOOF_5(_X_)                           ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
#define BITS_ADC2_DLLIN_5(_X_)                            ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_CTR1 */
#define BITS_DAC3_WD_OVR(_X_)                             ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
#define BITS_DAC3_WADDR_OVR(_X_)                          ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
#define BIT_DAC3_WLE_OVR                                  ( BIT(2) )
#define BIT_DAC3_W_OVR_I_QN                               ( BIT(1) )
#define BIT_DAC3_W_OVR_EN                                 ( BIT(0) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_CTR2 */
#define BIT_DAC3_AUTO_RST                                 ( BIT(23) )
#define BIT_DAC3_SOFT_RST                                 ( BIT(22) )
#define BIT_DAC3_OSBC                                     ( BIT(21) )
#define BIT_DAC3_ISBC                                     ( BIT(20) )
#define BIT_DAC3_OVR_EN_CAL                               ( BIT(19) )
#define BIT_DAC3_EN_OOSCAL                                ( BIT(18) )
#define BIT_DAC3_IQSWAP                                   ( BIT(17) )
#define BIT_DAC3_CAL_START                                ( BIT(16) )
#define BITS_DAC3_OFFSETI(_X_)                            ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BITS_DAC3_OFFSETQ(_X_)                            ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_CTR3 */
#define BITS_DAC3_Q_DC(_X_)                               ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
#define BITS_DAC3_I_DC(_X_)                               ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_CTR4 */
#define BITS_DAC3_I_CAL(_X_)                              ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
#define BITS_DAC3_Q_CAL(_X_)                              ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_STS0 */
#define BITS_DAC3_WTI(_X_)                                ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
#define BITS_DAC3_WTQ(_X_)                                ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_STS1 */
#define BITS_DAC3_DA_STATE(_X_)                           ( (_X_) << 17 & (BIT(17)|BIT(18)) )
#define BIT_DAC3_DONE                                     ( BIT(16) )
#define BITS_DAC3_WQ_OVR(_X_)                             ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL3_CTR0 */
#define BITS_ADC3_CLK_CAL_DLY(_X_)                        ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
#define BITS_ADA3_CAL_WAIT(_X_)                           ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_CLK_ADA3_CAL_EN                               ( BIT(6) )
#define BIT_DAC3_PD_CAL                                   ( BIT(5) )
#define BIT_ADC3_EN_CAL                                   ( BIT(3) )
#define BIT_ADC3_CAL                                      ( BIT(1) )
#define BIT_ADA3_MODE_SEL                                 ( BIT(0) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL3_CTR1 */
#define BITS_ADC3_Q_DC(_X_)                               ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)) )
#define BITS_ADC3_I_DC(_X_)                               ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL3_CTR3 */
#define BIT_ADA3_CAL_START                                ( BIT(0) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL3_STS0 */
#define BIT_ADA3_CAL_DONE                                 ( BIT(31) )
#define BITS_ADC3_CAL_I_SUM(_X_)                          ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_CAL3_STS1 */
#define BITS_ADC3_CAL_Q_SUM(_X_)                          ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_CTR00 */
#define BIT_DAC3_OUT_SEL_2                                ( BIT(26) )
#define BITS_DAC3_RSV_2(_X_)                              ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) )
#define BITS_DAC3_PCTRL_2(_X_)                            ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)) )
#define BIT_DAC3_CLK_SEL_2                                ( BIT(18) )
#define BIT_DAC3_OUT_SEL_1                                ( BIT(17) )
#define BITS_DAC3_RSV_1(_X_)                              ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)) )
#define BITS_DAC3_PCTRL_1(_X_)                            ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) )
#define BIT_DAC3_CLK_SEL_1                                ( BIT(9) )
#define BIT_DAC3_OUT_SEL_0                                ( BIT(8) )
#define BITS_DAC3_RSV_0(_X_)                              ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
#define BITS_DAC3_PCTRL_0(_X_)                            ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)) )
#define BIT_DAC3_CLK_SEL_0                                ( BIT(0) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_DAC3_CTR10 */
#define BIT_DAC3_OUT_SEL_5                                ( BIT(26) )
#define BITS_DAC3_RSV_5(_X_)                              ( (_X_) << 22 & (BIT(22)|BIT(23)|BIT(24)|BIT(25)) )
#define BITS_DAC3_PCTRL_5(_X_)                            ( (_X_) << 19 & (BIT(19)|BIT(20)|BIT(21)) )
#define BIT_DAC3_CLK_SEL_5                                ( BIT(18) )
#define BIT_DAC3_OUT_SEL_4                                ( BIT(17) )
#define BITS_DAC3_RSV_4(_X_)                              ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)|BIT(16)) )
#define BITS_DAC3_PCTRL_4(_X_)                            ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) )
#define BIT_DAC3_CLK_SEL_4                                ( BIT(9) )
#define BIT_DAC3_OUT_SEL_3                                ( BIT(8) )
#define BITS_DAC3_RSV_3(_X_)                              ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
#define BITS_DAC3_PCTRL_3(_X_)                            ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)) )
#define BIT_DAC3_CLK_SEL_3                                ( BIT(0) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR0 */
#define BIT_ADC3_SOFT_RST                                 ( BIT(31) )
#define BITS_ADC3_DLL_OUT(_X_)                            ( (_X_) << 25 & (BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) )
#define BITS_ADC3_CALRDOUT(_X_)                           ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) )
#define BIT_ADC3_DLL_SOFT_RST                             ( BIT(10) )
#define BIT_ADC3_CAL_SOFT_RST                             ( BIT(9) )
#define BIT_ADC3_CALRD                                    ( BIT(8) )
#define BIT_ADC3_CALEN                                    ( BIT(7) )
#define BITS_ADC3_CALADDR(_X_)                            ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) )
#define BIT_ADC3_DEBUG_EN                                 ( BIT(0) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR00 */
#define BITS_ADC3_RSV_1(_X_)                              ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
#define BITS_ADC3_RSV_0(_X_)                              ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR01 */
#define BIT_ADC3_DIG_CLK_SEL_0                            ( BIT(30) )
#define BIT_ADC3_VCM_SEL_0                                ( BIT(29) )
#define BITS_ADC3_DELAY_CAP_0(_X_)                        ( (_X_) << 27 & (BIT(27)|BIT(28)) )
#define BITS_ADC3_BIT_SEL_0(_X_)                          ( (_X_) << 25 & (BIT(25)|BIT(26)) )
#define BITS_ADC3_VREF_SEL_0(_X_)                         ( (_X_) << 23 & (BIT(23)|BIT(24)) )
#define BITS_ADC3_VREF_BOOST_0(_X_)                       ( (_X_) << 21 & (BIT(21)|BIT(22)) )
#define BITS_ADC3_QUANT_BOOST_0(_X_)                      ( (_X_) << 19 & (BIT(19)|BIT(20)) )
#define BIT_ADC3_DLLRD_0                                  ( BIT(18) )
#define BIT_ADC3_DLLWR_0                                  ( BIT(17) )
#define BIT_ADC3_DLLEN_0                                  ( BIT(16) )
#define BIT_ADC3_CSBC                                     ( BIT(15) )
#define BIT_ADC3_IQSWAP                                   ( BIT(14) )
#define BITS_ADC3_DLLOOF_0(_X_)                           ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
#define BIT_ADC3_OSBC                                     ( BIT(7) )
#define BIT_ADC3_ISBC                                     ( BIT(6) )
#define BITS_ADC3_DLLIN_0(_X_)                            ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR02 */
#define BIT_ADC3_DIG_CLK_SEL_1                            ( BIT(30) )
#define BIT_ADC3_VCM_SEL_1                                ( BIT(29) )
#define BITS_ADC3_DELAY_CAP_1(_X_)                        ( (_X_) << 27 & (BIT(27)|BIT(28)) )
#define BITS_ADC3_BIT_SEL_1(_X_)                          ( (_X_) << 25 & (BIT(25)|BIT(26)) )
#define BITS_ADC3_VREF_SEL_1(_X_)                         ( (_X_) << 23 & (BIT(23)|BIT(24)) )
#define BITS_ADC3_VREF_BOOST_1(_X_)                       ( (_X_) << 21 & (BIT(21)|BIT(22)) )
#define BITS_ADC3_QUANT_BOOST_1(_X_)                      ( (_X_) << 19 & (BIT(19)|BIT(20)) )
#define BIT_ADC3_DLLRD_1                                  ( BIT(18) )
#define BIT_ADC3_DLLWR_1                                  ( BIT(17) )
#define BIT_ADC3_DLLEN_1                                  ( BIT(16) )
#define BITS_ADC3_DLLOOF_1(_X_)                           ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
#define BITS_ADC3_DLLIN_1(_X_)                            ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR10 */
#define BITS_ADC3_RSV_3(_X_)                              ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
#define BITS_ADC3_RSV_2(_X_)                              ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR11 */
#define BIT_ADC3_DIG_CLK_SEL_2                            ( BIT(30) )
#define BIT_ADC3_VCM_SEL_2                                ( BIT(29) )
#define BITS_ADC3_DELAY_CAP_2(_X_)                        ( (_X_) << 27 & (BIT(27)|BIT(28)) )
#define BITS_ADC3_BIT_SEL_2(_X_)                          ( (_X_) << 25 & (BIT(25)|BIT(26)) )
#define BITS_ADC3_VREF_SEL_2(_X_)                         ( (_X_) << 23 & (BIT(23)|BIT(24)) )
#define BITS_ADC3_VREF_BOOST_2(_X_)                       ( (_X_) << 21 & (BIT(21)|BIT(22)) )
#define BITS_ADC3_QUANT_BOOST_2(_X_)                      ( (_X_) << 19 & (BIT(19)|BIT(20)) )
#define BIT_ADC3_DLLRD_2                                  ( BIT(18) )
#define BIT_ADC3_DLLWR_2                                  ( BIT(17) )
#define BIT_ADC3_DLLEN_2                                  ( BIT(16) )
#define BITS_ADC3_DLLOOF_2(_X_)                           ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
#define BITS_ADC3_DLLIN_2(_X_)                            ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR12 */
#define BIT_ADC3_DIG_CLK_SEL_3                            ( BIT(30) )
#define BIT_ADC3_VCM_SEL_3                                ( BIT(29) )
#define BITS_ADC3_DELAY_CAP_3(_X_)                        ( (_X_) << 27 & (BIT(27)|BIT(28)) )
#define BITS_ADC3_BIT_SEL_3(_X_)                          ( (_X_) << 25 & (BIT(25)|BIT(26)) )
#define BITS_ADC3_VREF_SEL_3(_X_)                         ( (_X_) << 23 & (BIT(23)|BIT(24)) )
#define BITS_ADC3_VREF_BOOST_3(_X_)                       ( (_X_) << 21 & (BIT(21)|BIT(22)) )
#define BITS_ADC3_QUANT_BOOST_3(_X_)                      ( (_X_) << 19 & (BIT(19)|BIT(20)) )
#define BIT_ADC3_DLLRD_3                                  ( BIT(18) )
#define BIT_ADC3_DLLWR_3                                  ( BIT(17) )
#define BIT_ADC3_DLLEN_3                                  ( BIT(16) )
#define BITS_ADC3_DLLOOF_3(_X_)                           ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
#define BITS_ADC3_DLLIN_3(_X_)                            ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR20 */
#define BITS_ADC3_RSV_5(_X_)                              ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
#define BITS_ADC3_RSV_4(_X_)                              ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR21 */
#define BIT_ADC3_DIG_CLK_SEL_4                            ( BIT(30) )
#define BIT_ADC3_VCM_SEL_4                                ( BIT(29) )
#define BITS_ADC3_DELAY_CAP_4(_X_)                        ( (_X_) << 27 & (BIT(27)|BIT(28)) )
#define BITS_ADC3_BIT_SEL_4(_X_)                          ( (_X_) << 25 & (BIT(25)|BIT(26)) )
#define BITS_ADC3_VREF_SEL_4(_X_)                         ( (_X_) << 23 & (BIT(23)|BIT(24)) )
#define BITS_ADC3_VREF_BOOST_4(_X_)                       ( (_X_) << 21 & (BIT(21)|BIT(22)) )
#define BITS_ADC3_QUANT_BOOST_4(_X_)                      ( (_X_) << 19 & (BIT(19)|BIT(20)) )
#define BIT_ADC3_DLLRD_4                                  ( BIT(18) )
#define BIT_ADC3_DLLWR_4                                  ( BIT(17) )
#define BIT_ADC3_DLLEN_4                                  ( BIT(16) )
#define BITS_ADC3_DLLOOF_4(_X_)                           ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
#define BITS_ADC3_DLLIN_4(_X_)                            ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_ADC3_CTR22 */
#define BIT_ADC3_DIG_CLK_SEL_5                            ( BIT(30) )
#define BIT_ADC3_VCM_SEL_5                                ( BIT(29) )
#define BITS_ADC3_DELAY_CAP_5(_X_)                        ( (_X_) << 27 & (BIT(27)|BIT(28)) )
#define BITS_ADC3_BIT_SEL_5(_X_)                          ( (_X_) << 25 & (BIT(25)|BIT(26)) )
#define BITS_ADC3_VREF_SEL_5(_X_)                         ( (_X_) << 23 & (BIT(23)|BIT(24)) )
#define BITS_ADC3_VREF_BOOST_5(_X_)                       ( (_X_) << 21 & (BIT(21)|BIT(22)) )
#define BITS_ADC3_QUANT_BOOST_5(_X_)                      ( (_X_) << 19 & (BIT(19)|BIT(20)) )
#define BIT_ADC3_DLLRD_5                                  ( BIT(18) )
#define BIT_ADC3_DLLWR_5                                  ( BIT(17) )
#define BIT_ADC3_DLLEN_5                                  ( BIT(16) )
#define BITS_ADC3_DLLOOF_5(_X_)                           ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
#define BITS_ADC3_DLLIN_5(_X_)                            ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_AFCDAC1_CFG */
#define BITS_AFCDAC1_CHANNEL_MASK(_X_)                    ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)) )
#define BITS_AFCDAC1_CHANNEL_SSET(_X_)                    ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) )
#define BIT_AFCDAC1_LOW_V_CON_SST                         ( BIT(23) )
#define BIT_AFCDAC1_BP_RES_SST                            ( BIT(20) )
#define BITS_AFCDAC1_G_SST(_X_)                           ( (_X_) << 18 & (BIT(18)|BIT(19)) )
#define BITS_AFCDAC1_CTL_SST(_X_)                         ( (_X_) << 16 & (BIT(16)|BIT(17)) )
#define BIT_AFCDAC1_PD_SST                                ( BIT(15) )
#define BITS_AFCDAC1_D_SST(_X_)                           ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_AFCDAC2_CFG */
#define BITS_AFCDAC2_CHANNEL_MASK(_X_)                    ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)) )
#define BITS_AFCDAC2_CHANNEL_SSET(_X_)                    ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) )
#define BIT_AFCDAC2_LOW_V_CON_SST                         ( BIT(23) )
#define BIT_AFCDAC2_BP_RES_SST                            ( BIT(20) )
#define BITS_AFCDAC2_G_SST(_X_)                           ( (_X_) << 18 & (BIT(18)|BIT(19)) )
#define BITS_AFCDAC2_CTL_SST(_X_)                         ( (_X_) << 16 & (BIT(16)|BIT(17)) )
#define BIT_AFCDAC2_PD_SST                                ( BIT(15) )
#define BITS_AFCDAC2_D_SST(_X_)                           ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_APCDAC1_CFG */
#define BITS_APCDAC1_CHANNEL_MASK(_X_)                    ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)) )
#define BITS_APCDAC1_CHANNEL_SSET(_X_)                    ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) )
#define BIT_APCDAC1_LOW_V_CON_SST                         ( BIT(23) )
#define BITS_APCDAC1_OUTSEL_SST(_X_)                      ( (_X_) << 21 & (BIT(21)|BIT(22)) )
#define BIT_APCDAC1_BP_RES_SST                            ( BIT(20) )
#define BITS_APCDAC1_G_SST(_X_)                           ( (_X_) << 18 & (BIT(18)|BIT(19)) )
#define BITS_APCDAC1_CTL_SST(_X_)                         ( (_X_) << 16 & (BIT(16)|BIT(17)) )
#define BIT_APCDAC1_PD_SST                                ( BIT(15) )
#define BIT_APCDAC1_SEL_SST                               ( BIT(14) )
#define BITS_APCDAC1_D_SST(_X_)                           ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_APCDAC2_CFG */
#define BITS_APCDAC2_CHANNEL_MASK(_X_)                    ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)) )
#define BITS_APCDAC2_CHANNEL_SSET(_X_)                    ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) )
#define BIT_APCDAC2_LOW_V_CON_SST                         ( BIT(23) )
#define BITS_APCDAC2_OUTSEL_SST(_X_)                      ( (_X_) << 21 & (BIT(21)|BIT(22)) )
#define BIT_APCDAC2_BP_RES_SST                            ( BIT(20) )
#define BITS_APCDAC2_G_SST(_X_)                           ( (_X_) << 18 & (BIT(18)|BIT(19)) )
#define BITS_APCDAC2_CTL_SST(_X_)                         ( (_X_) << 16 & (BIT(16)|BIT(17)) )
#define BIT_APCDAC2_PD_SST                                ( BIT(15) )
#define BIT_APCDAC2_SEL_SST                               ( BIT(14) )
#define BITS_APCDAC2_D_SST(_X_)                           ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFSPI_CFG */
#define BITS_RFSBI2_CHANNEL_MASK(_X_)                     ( (_X_) << 29 & (BIT(29)|BIT(30)|BIT(31)) )
#define BITS_RFSBI2_CHANNEL_SSET(_X_)                     ( (_X_) << 26 & (BIT(26)|BIT(27)|BIT(28)) )
#define BIT_RFSBI2_IDATA_SST                              ( BIT(25) )
#define BIT_RFSBI2_ODATA_SST                              ( BIT(24) )
#define BIT_RFSBI2_DATA_OE_SST                            ( BIT(23) )
#define BIT_RFSBI2_DATA_IE_SST                            ( BIT(22) )
#define BIT_RFSBI2_CLK_SST                                ( BIT(21) )
#define BIT_RFSBI2_CLK_OE_SST                             ( BIT(20) )
#define BIT_RFSBI2_EN0_SST                                ( BIT(19) )
#define BIT_RFSBI2_EN0_OE_SST                             ( BIT(18) )
#define BIT_RFSBI2_EN1_SST                                ( BIT(17) )
#define BIT_RFSBI2_EN1_OE_SST                             ( BIT(16) )
#define BITS_RFSBI1_CHANNEL_MASK(_X_)                     ( (_X_) << 13 & (BIT(13)|BIT(14)|BIT(15)) )
#define BITS_RFSBI1_CHANNEL_SSET(_X_)                     ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)) )
#define BIT_RFSBI1_IDATA_SST                              ( BIT(9) )
#define BIT_RFSBI1_ODATA_SST                              ( BIT(8) )
#define BIT_RFSBI1_DATA_OE_SST                            ( BIT(7) )
#define BIT_RFSBI1_DATA_IE_SST                            ( BIT(6) )
#define BIT_RFSBI1_CLK_SST                                ( BIT(5) )
#define BIT_RFSBI1_CLK_OE_SST                             ( BIT(4) )
#define BIT_RFSBI1_EN0_SST                                ( BIT(3) )
#define BIT_RFSBI1_EN0_OE_SST                             ( BIT(2) )
#define BIT_RFSBI1_EN1_SST                                ( BIT(1) )
#define BIT_RFSBI1_EN1_OE_SST                             ( BIT(0) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFMIPI_CFG */
#define BITS_RFMIPI2_CHANNEL_MASK(_X_)                    ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)) )
#define BITS_RFMIPI2_CHANNEL_SSET(_X_)                    ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) )
#define BIT_PAD_OUT_RFFE2_CLK_SST                         ( BIT(20) )
#define BIT_PAD_OUT_RFFE2_DATA_SST                        ( BIT(19) )
#define BIT_PAD_IN_RFFE2_DATA_SST                         ( BIT(18) )
#define BIT_PAD_OE_RFFE2_DATA_SST                         ( BIT(17) )
#define BIT_PAD_IE_RFFE2_DATA_SST                         ( BIT(16) )
#define BITS_RFMIPI1_CHANNEL_MASK(_X_)                    ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) )
#define BITS_RFMIPI1_CHANNEL_SSET(_X_)                    ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) )
#define BIT_PAD_OUT_RFFE1_CLK_SST                         ( BIT(4) )
#define BIT_PAD_OUT_RFFE1_DATA_SST                        ( BIT(3) )
#define BIT_PAD_IN_RFFE1_DATA_SST                         ( BIT(2) )
#define BIT_PAD_OE_RFFE1_DATA_SST                         ( BIT(1) )
#define BIT_PAD_IE_RFFE1_DATA_SST                         ( BIT(0) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_APCDAC_OUTSEL */
#define BIT_AFCDAC_LOW_V_CON_GGE                          ( BIT(31) )
#define BIT_AFCDAC_LOW_V_CON_WG                           ( BIT(30) )
#define BIT_AFCDAC_LOW_V_CON_WD                           ( BIT(29) )
#define BIT_AFCDAC_LOW_V_CON_TG                           ( BIT(28) )
#define BIT_AFCDAC_LOW_V_CON_TD                           ( BIT(27) )
#define BIT_AFCDAC_LOW_V_CON_LTE                          ( BIT(26) )
#define BITS_APCDACX_G3_SST(_X_)                          ( (_X_) << 24 & (BIT(24)|BIT(25)) )
#define BITS_APCDACX_G2_SST(_X_)                          ( (_X_) << 22 & (BIT(22)|BIT(23)) )
#define BITS_APCDACX_G1_SST(_X_)                          ( (_X_) << 20 & (BIT(20)|BIT(21)) )
#define BITS_APCDACX_G0_SST(_X_)                          ( (_X_) << 18 & (BIT(18)|BIT(19)) )
#define BIT_APCDAC_LOW_V_CON_GGE                          ( BIT(17) )
#define BIT_APCDAC_LOW_V_CON_WG                           ( BIT(16) )
#define BIT_APCDAC_LOW_V_CON_WD                           ( BIT(15) )
#define BIT_APCDAC_LOW_V_CON_TG                           ( BIT(14) )
#define BIT_APCDAC_LOW_V_CON_TD                           ( BIT(13) )
#define BIT_APCDAC_LOW_V_CON_LTE                          ( BIT(12) )
#define BITS_APCDAC_OUTSEL_GGE(_X_)                       ( (_X_) << 10 & (BIT(10)|BIT(11)) )
#define BITS_APCDAC_OUTSEL_WG(_X_)                        ( (_X_) << 8 & (BIT(8)|BIT(9)) )
#define BITS_APCDAC_OUTSEL_WD(_X_)                        ( (_X_) << 6 & (BIT(6)|BIT(7)) )
#define BITS_APCDAC_OUTSEL_TG(_X_)                        ( (_X_) << 4 & (BIT(4)|BIT(5)) )
#define BITS_APCDAC_OUTSEL_TD(_X_)                        ( (_X_) << 2 & (BIT(2)|BIT(3)) )
#define BITS_APCDAC_OUTSEL_LTE(_X_)                       ( (_X_) & (BIT(0)|BIT(1)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_CLASH_CHK */
#define BIT_RFSBI2_CLASH_CHK_INTRP_EN                     ( BIT(29) )
#define BIT_RFSBI1_CLASH_CHK_INTRP_EN                     ( BIT(28) )
#define BIT_RFMIPI2_CLASH_CHK_INTRP_EN                    ( BIT(27) )
#define BIT_RFMIPI1_CLASH_CHK_INTRP_EN                    ( BIT(26) )
#define BIT_APCDAC2_CLASH_CHK_INTRP_EN                    ( BIT(25) )
#define BIT_APCDAC1_CLASH_CHK_INTRP_EN                    ( BIT(24) )
#define BIT_AFCDAC2_CLASH_CHK_INTRP_EN                    ( BIT(23) )
#define BIT_AFCDAC1_CLASH_CHK_INTRP_EN                    ( BIT(22) )
#define BIT_ADA3_TX_CLASH_CHK_INTRP_EN                    ( BIT(21) )
#define BIT_ADA3_RX_CLASH_CHK_INTRP_EN                    ( BIT(20) )
#define BIT_ADA2_TX_CLASH_CHK_INTRP_EN                    ( BIT(19) )
#define BIT_ADA2_RX_CLASH_CHK_INTRP_EN                    ( BIT(18) )
#define BIT_ADA1_TX_CLASH_CHK_INTRP_EN                    ( BIT(17) )
#define BIT_ADA1_RX_CLASH_CHK_INTRP_EN                    ( BIT(16) )
#define BIT_CHK_CLASH_STFREE                              ( BIT(8) )
#define BIT_CHK_CLASH_CLR                                 ( BIT(7) )
#define BIT_CHK_CLASH_RTC_SNAP_MODE                       ( BIT(4) )
#define BIT_CHK_CLASH_RTC_SNAP_EDGE                       ( BIT(3) )
#define BIT_CHK_CLASH_RTC_SNAP_INTRP_TYPE                 ( BIT(2) )
#define BIT_CHK_CLASH_RTC_SNAP_INTRP_CLR                  ( BIT(1) )
#define BIT_CHK_CLASH_RTC_SNAP_INTRP                      ( BIT(0) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_CLASH_SNAP */
#define BITS_CHK_CLASH_RTC_SNAP_TIME(_X_)                 (_X_)

/* bits definitions for register REG_MDAR_APB_RF_MDAR_CLASH_STATUS1 */
#define BITS_CHK_CLASH_ADA3_TX_CHANNEL_SEL(_X_)           ( (_X_) << 25 & (BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
#define BITS_CHK_CLASH_ADA3_RX_CHANNEL_SEL(_X_)           ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) )
#define BITS_CHK_CLASH_ADA2_TX_CHANNEL_SEL(_X_)           ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
#define BITS_CHK_CLASH_ADA2_RX_CHANNEL_SEL(_X_)           ( (_X_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
#define BITS_CHK_CLASH_ADA1_TX_CHANNEL_SEL(_X_)           ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
#define BITS_CHK_CLASH_ADA1_RX_CHANNEL_SEL(_X_)           ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_CLASH_STATUS2 */
#define BITS_CHK_CLASH_APCDAC2_CHANNEL_SEL(_X_)           ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)) )
#define BITS_CHK_CLASH_APCDAC1_CHANNEL_SEL(_X_)           ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) )
#define BITS_CHK_CLASH_AFCDAC2_CHANNEL_SEL(_X_)           ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) )
#define BITS_CHK_CLASH_AFCDAC1_CHANNEL_SEL(_X_)           ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_CLASH_STATUS3 */
#define BITS_CHK_CLASH_RFSBI2_CHANNEL_SEL(_X_)            ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)) )
#define BITS_CHK_CLASH_RFSBI1_CHANNEL_SEL(_X_)            ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) )
#define BITS_CHK_CLASH_RFMIPI2_CHANNEL_SEL(_X_)           ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) )
#define BITS_CHK_CLASH_RFMIPI1_CHANNEL_SEL(_X_)           ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_EXTRA_CFG0 */
#define BITS_APT_DCM2_EXTRA_CFG(_X_)                      ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
#define BIT_APT_DCM2_ADI_EN                               ( BIT(23) )
#define BITS_APT_DCM2_CHANNEL_SSET(_X_)                   ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
#define BIT_APT_DCM2_SST                                  ( BIT(19) )
#define BITS_APT_DCM2_CHANNEL_MASK(_X_)                   ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)) )
#define BITS_APT_DCM1_EXTRA_CFG(_X_)                      ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
#define BIT_APT_DCM1_ADI_EN                               ( BIT(7) )
#define BITS_APT_DCM1_CHANNEL_SSET(_X_)                   ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) )
#define BIT_APT_DCM1_SST                                  ( BIT(3) )
#define BITS_APT_DCM1_CHANNEL_MASK(_X_)                   ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_EXTRA_CFG1 */
#define BITS_MDAR_EXTRA_CFG1(_X_)                         ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
#define BIT_MDAR_EXTRA_CFG1_2                             ( BIT(12) )
#define BIT_MDAR_EXTRA_CFG1_1                             ( BIT(11) )
#define BIT_MDAR_EXTRA_CFG1_0                             ( BIT(10) )
#define BITS_MDAR_BB_LDO_REFCTRL(_X_)                     ( (_X_) << 8 & (BIT(8)|BIT(9)) )
#define BIT_MDAR_BB_LDO_SLEEP_PD_EN                       ( BIT(6) )
#define BIT_MDAR_BB_LDO_FORCE_ON                          ( BIT(5) )
#define BIT_MDAR_BB_LDO_FORCE_PD                          ( BIT(4) )
#define BIT_MDAR_BB_BG_SLEEP_PD_EN                        ( BIT(2) )
#define BIT_MDAR_BB_BG_FORCE_ON                           ( BIT(1) )
#define BIT_MDAR_BB_BG_FORCE_PD                           ( BIT(0) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF0 */
#define BITS_CHK_CLASH_RFCTRL15_CHX_SEL(_X_)              ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
#define BIT_RFCTRL15_CHK_INTRP_EN                         ( BIT(16) )
#define BIT_RFCTRL15_RTC_REFRESH                          ( BIT(12) )
#define BIT_RFCTRL15_SNAP_REFRESH                         ( BIT(8) )
#define BITS_RFCTRL15_SSET(_X_)                           ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) )
#define BITS_RFCTRL15_MASK(_X_)                           ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF1 */
#define BITS_RFCTRL15_CH0_SNAP1_RTC_TIME(_X_)             (_X_)

/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF2 */
#define BITS_RFCTRL15_CH0_SNAP0_RTC_TIME(_X_)             (_X_)

/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF3 */
#define BITS_RFCTRL15_CH1_SNAP1_RTC_TIME(_X_)             (_X_)

/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF4 */
#define BITS_RFCTRL15_CH1_SNAP0_RTC_TIME(_X_)             (_X_)

/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF5 */
#define BITS_RFCTRL15_CH2_SNAP1_RTC_TIME(_X_)             (_X_)

/* bits definitions for register REG_MDAR_APB_RF_MDAR_RFCTRL15_INF6 */
#define BITS_RFCTRL15_CH2_SNAP0_RTC_TIME(_X_)             (_X_)

/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG4 */
#define BITS_RFCTRL_CHANNEL_MASK3(_X_)                    ( (_X_) << 27 & (BIT(27)|BIT(28)|BIT(29)) )
#define BITS_RFCTRL_CHANNEL_MASK2(_X_)                    ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) )
#define BITS_RFCTRL_CHANNEL_MASK1(_X_)                    ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) )
#define BITS_RFCTRL_CHANNEL_MASK0(_X_)                    ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) )
#define BITS_RFCTRL150_SST(_X_)                           ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG5 */
#define BITS_RFCTRL_CHANNEL_MASK13(_X_)                   ( (_X_) << 27 & (BIT(27)|BIT(28)|BIT(29)) )
#define BITS_RFCTRL_CHANNEL_MASK12(_X_)                   ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) )
#define BITS_RFCTRL_CHANNEL_MASK11(_X_)                   ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) )
#define BITS_RFCTRL_CHANNEL_MASK10(_X_)                   ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) )
#define BITS_RFCTRL_CHANNEL_MASK9(_X_)                    ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) )
#define BITS_RFCTRL_CHANNEL_MASK8(_X_)                    ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) )
#define BITS_RFCTRL_CHANNEL_MASK7(_X_)                    ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)) )
#define BITS_RFCTRL_CHANNEL_MASK6(_X_)                    ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) )
#define BITS_RFCTRL_CHANNEL_MASK5(_X_)                    ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) )
#define BITS_RFCTRL_CHANNEL_MASK4(_X_)                    ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG6 */
#define BITS_RFCTRL_CHANNEL_SSET7(_X_)                    ( (_X_) << 27 & (BIT(27)|BIT(28)|BIT(29)) )
#define BITS_RFCTRL_CHANNEL_SSET6(_X_)                    ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) )
#define BITS_RFCTRL_CHANNEL_SSET5(_X_)                    ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) )
#define BITS_RFCTRL_CHANNEL_SSET4(_X_)                    ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) )
#define BITS_RFCTRL_CHANNEL_SSET3(_X_)                    ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) )
#define BITS_RFCTRL_CHANNEL_SSET2(_X_)                    ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) )
#define BITS_RFCTRL_CHANNEL_SSET1(_X_)                    ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)) )
#define BITS_RFCTRL_CHANNEL_SSET0(_X_)                    ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) )
#define BITS_RFCTRL_CHANNEL_MASK15(_X_)                   ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) )
#define BITS_RFCTRL_CHANNEL_MASK14(_X_)                   ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG7 */
#define BITS_RFCTRL_CHANNEL_SSET15(_X_)                   ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) )
#define BITS_RFCTRL_CHANNEL_SSET14(_X_)                   ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) )
#define BITS_RFCTRL_CHANNEL_SSET13(_X_)                   ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) )
#define BITS_RFCTRL_CHANNEL_SSET12(_X_)                   ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) )
#define BITS_RFCTRL_CHANNEL_SSET11(_X_)                   ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)) )
#define BITS_RFCTRL_CHANNEL_SSET10(_X_)                   ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) )
#define BITS_RFCTRL_CHANNEL_SSET9(_X_)                    ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) )
#define BITS_RFCTRL_CHANNEL_SSET8(_X_)                    ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG8 */
#define BITS_RFCTRL_CHANNEL_MASK19(_X_)                   ( (_X_) << 27 & (BIT(27)|BIT(28)|BIT(29)) )
#define BITS_RFCTRL_CHANNEL_MASK18(_X_)                   ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) )
#define BITS_RFCTRL_CHANNEL_MASK17(_X_)                   ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) )
#define BITS_RFCTRL_CHANNEL_MASK16(_X_)                   ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) )
#define BITS_RFCTRL3130_SST(_X_)                          ( (_X_) << 14 & (BIT(14)|BIT(15)) )
#define BITS_RFCTRL2916_SST(_X_)                          ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG9 */
#define BITS_RFCTRL_CHANNEL_MASK29(_X_)                   ( (_X_) << 27 & (BIT(27)|BIT(28)|BIT(29)) )
#define BITS_RFCTRL_CHANNEL_MASK28(_X_)                   ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) )
#define BITS_RFCTRL_CHANNEL_MASK27(_X_)                   ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) )
#define BITS_RFCTRL_CHANNEL_MASK26(_X_)                   ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) )
#define BITS_RFCTRL_CHANNEL_MASK25(_X_)                   ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) )
#define BITS_RFCTRL_CHANNEL_MASK24(_X_)                   ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) )
#define BITS_RFCTRL_CHANNEL_MASK23(_X_)                   ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)) )
#define BITS_RFCTRL_CHANNEL_MASK22(_X_)                   ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) )
#define BITS_RFCTRL_CHANNEL_MASK21(_X_)                   ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) )
#define BITS_RFCTRL_CHANNEL_MASK20(_X_)                   ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG10 */
#define BITS_RFCTRL_CHANNEL_SSET23(_X_)                   ( (_X_) << 27 & (BIT(27)|BIT(28)|BIT(29)) )
#define BITS_RFCTRL_CHANNEL_SSET22(_X_)                   ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)) )
#define BITS_RFCTRL_CHANNEL_SSET21(_X_)                   ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) )
#define BITS_RFCTRL_CHANNEL_SSET20(_X_)                   ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) )
#define BITS_RFCTRL_CHANNEL_SSET19(_X_)                   ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) )
#define BITS_RFCTRL_CHANNEL_SSET18(_X_)                   ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) )
#define BITS_RFCTRL_CHANNEL_SSET17(_X_)                   ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)) )
#define BITS_RFCTRL_CHANNEL_SSET16(_X_)                   ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) )
#define BITS_RFCTRL_CHANNEL_MASK31(_X_)                   ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) )
#define BITS_RFCTRL_CHANNEL_MASK30(_X_)                   ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG11 */
#define BITS_RFCTRL_CHANNEL_SSET31(_X_)                   ( (_X_) << 21 & (BIT(21)|BIT(22)|BIT(23)) )
#define BITS_RFCTRL_CHANNEL_SSET30(_X_)                   ( (_X_) << 18 & (BIT(18)|BIT(19)|BIT(20)) )
#define BITS_RFCTRL_CHANNEL_SSET29(_X_)                   ( (_X_) << 15 & (BIT(15)|BIT(16)|BIT(17)) )
#define BITS_RFCTRL_CHANNEL_SSET28(_X_)                   ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)) )
#define BITS_RFCTRL_CHANNEL_SSET27(_X_)                   ( (_X_) << 9 & (BIT(9)|BIT(10)|BIT(11)) )
#define BITS_RFCTRL_CHANNEL_SSET26(_X_)                   ( (_X_) << 6 & (BIT(6)|BIT(7)|BIT(8)) )
#define BITS_RFCTRL_CHANNEL_SSET25(_X_)                   ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)) )
#define BITS_RFCTRL_CHANNEL_SSET24(_X_)                   ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG12 */
#define BITS_RFCTRL_WTGCFGH(_X_)                          ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) )
#define BITS_RFCTRL_WTGCFGL(_X_)                          ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG13 */
#define BITS_RFCTRL_GGECFGH(_X_)                          ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)) )
#define BITS_RFCTRL_GGECFGL(_X_)                          ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG14 */
#define BITS_MDAR_CFG14(_X_)                              (_X_)

/* bits definitions for register REG_MDAR_APB_RF_MDAR_CFG15 */
#define BITS_MDAR_ANALOG_BB_RSV(_X_)                      ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG10 */
#define BIT_ADC1_IMBP_CLK_SEL_5                           ( BIT(21) )
#define BIT_ADC1_IMBP_CLK_SEL_4                           ( BIT(20) )
#define BIT_ADC1_IMBP_CLK_SEL_3                           ( BIT(19) )
#define BIT_ADC1_IMBP_CLK_SEL_2                           ( BIT(18) )
#define BIT_ADC1_IMBP_CLK_SEL_1                           ( BIT(17) )
#define BIT_ADC1_IMBP_CLK_SEL_0                           ( BIT(16) )
#define BIT_DAC1_IMBP_BYPASS_5                            ( BIT(13) )
#define BIT_DAC1_IMBP_BYPASS_4                            ( BIT(12) )
#define BIT_DAC1_IMBP_BYPASS_3                            ( BIT(11) )
#define BIT_DAC1_IMBP_BYPASS_2                            ( BIT(10) )
#define BIT_DAC1_IMBP_BYPASS_1                            ( BIT(9) )
#define BIT_DAC1_IMBP_BYPASS_0                            ( BIT(8) )
#define BIT_ADC1_IMBP_BYPASS_5                            ( BIT(5) )
#define BIT_ADC1_IMBP_BYPASS_4                            ( BIT(4) )
#define BIT_ADC1_IMBP_BYPASS_3                            ( BIT(3) )
#define BIT_ADC1_IMBP_BYPASS_2                            ( BIT(2) )
#define BIT_ADC1_IMBP_BYPASS_1                            ( BIT(1) )
#define BIT_ADC1_IMBP_BYPASS_0                            ( BIT(0) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG11 */
#define BITS_ADC1_BAL_B(_X_)                              ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
#define BITS_ADC1_BAL_A(_X_)                              ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG12 */
#define BITS_ADC1_BAL_D(_X_)                              ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
#define BITS_ADC1_BAL_C(_X_)                              ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG13 */
#define BITS_DAC1_BAL_B(_X_)                              ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
#define BITS_DAC1_BAL_A(_X_)                              ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG14 */
#define BITS_DAC1_BAL_D(_X_)                              ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
#define BITS_DAC1_BAL_C(_X_)                              ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG20 */
#define BIT_ADC2_IMBP_CLK_SEL_5                           ( BIT(21) )
#define BIT_ADC2_IMBP_CLK_SEL_4                           ( BIT(20) )
#define BIT_ADC2_IMBP_CLK_SEL_3                           ( BIT(19) )
#define BIT_ADC2_IMBP_CLK_SEL_2                           ( BIT(18) )
#define BIT_ADC2_IMBP_CLK_SEL_1                           ( BIT(17) )
#define BIT_ADC2_IMBP_CLK_SEL_0                           ( BIT(16) )
#define BIT_DAC2_IMBP_BYPASS_5                            ( BIT(13) )
#define BIT_DAC2_IMBP_BYPASS_4                            ( BIT(12) )
#define BIT_DAC2_IMBP_BYPASS_3                            ( BIT(11) )
#define BIT_DAC2_IMBP_BYPASS_2                            ( BIT(10) )
#define BIT_DAC2_IMBP_BYPASS_1                            ( BIT(9) )
#define BIT_DAC2_IMBP_BYPASS_0                            ( BIT(8) )
#define BIT_ADC2_IMBP_BYPASS_5                            ( BIT(5) )
#define BIT_ADC2_IMBP_BYPASS_4                            ( BIT(4) )
#define BIT_ADC2_IMBP_BYPASS_3                            ( BIT(3) )
#define BIT_ADC2_IMBP_BYPASS_2                            ( BIT(2) )
#define BIT_ADC2_IMBP_BYPASS_1                            ( BIT(1) )
#define BIT_ADC2_IMBP_BYPASS_0                            ( BIT(0) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG21 */
#define BITS_ADC2_BAL_B(_X_)                              ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
#define BITS_ADC2_BAL_A(_X_)                              ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG22 */
#define BITS_ADC2_BAL_D(_X_)                              ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
#define BITS_ADC2_BAL_C(_X_)                              ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG23 */
#define BITS_DAC2_BAL_B(_X_)                              ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
#define BITS_DAC2_BAL_A(_X_)                              ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG24 */
#define BITS_DAC2_BAL_D(_X_)                              ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
#define BITS_DAC2_BAL_C(_X_)                              ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG30 */
#define BIT_ADC3_IMBP_CLK_SEL_5                           ( BIT(21) )
#define BIT_ADC3_IMBP_CLK_SEL_4                           ( BIT(20) )
#define BIT_ADC3_IMBP_CLK_SEL_3                           ( BIT(19) )
#define BIT_ADC3_IMBP_CLK_SEL_2                           ( BIT(18) )
#define BIT_ADC3_IMBP_CLK_SEL_1                           ( BIT(17) )
#define BIT_ADC3_IMBP_CLK_SEL_0                           ( BIT(16) )
#define BIT_DAC3_IMBP_BYPASS_5                            ( BIT(13) )
#define BIT_DAC3_IMBP_BYPASS_4                            ( BIT(12) )
#define BIT_DAC3_IMBP_BYPASS_3                            ( BIT(11) )
#define BIT_DAC3_IMBP_BYPASS_2                            ( BIT(10) )
#define BIT_DAC3_IMBP_BYPASS_1                            ( BIT(9) )
#define BIT_DAC3_IMBP_BYPASS_0                            ( BIT(8) )
#define BIT_ADC3_IMBP_BYPASS_5                            ( BIT(5) )
#define BIT_ADC3_IMBP_BYPASS_4                            ( BIT(4) )
#define BIT_ADC3_IMBP_BYPASS_3                            ( BIT(3) )
#define BIT_ADC3_IMBP_BYPASS_2                            ( BIT(2) )
#define BIT_ADC3_IMBP_BYPASS_1                            ( BIT(1) )
#define BIT_ADC3_IMBP_BYPASS_0                            ( BIT(0) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG31 */
#define BITS_ADC3_BAL_B(_X_)                              ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
#define BITS_ADC3_BAL_A(_X_)                              ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG32 */
#define BITS_ADC3_BAL_D(_X_)                              ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
#define BITS_ADC3_BAL_C(_X_)                              ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG33 */
#define BITS_DAC3_BAL_B(_X_)                              ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
#define BITS_DAC3_BAL_A(_X_)                              ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )

/* bits definitions for register REG_MDAR_APB_RF_MDAR_IMB_CFG34 */
#define BITS_DAC3_BAL_D(_X_)                              ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
#define BITS_DAC3_BAL_C(_X_)                              ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )

#endif