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/*
* Copyright (C) 2012 Spreadtrum Communications Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*************************************************
* Automatically generated C header: do not edit *
*************************************************
*/
#ifndef __REGS_AON_CLK_H__
#define __REGS_AON_CLK_H__
#ifndef __SCI_GLB_REGS_H__
#error "Don't include this file directly, include <mach/sci_glb_regs.h>"
#endif
#define REGS_AON_CLK
/* registers definitions for controller REGS_AON_CLK */
#define REG_AON_CLK_PUB_AHB_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0020)
#define REG_AON_CLK_EMC_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0024)
#define REG_AON_CLK_AON_APB_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0028)
#define REG_AON_CLK_AUDIF_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x002c)
#define REG_AON_CLK_FM_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0030)
#define REG_AON_CLK_ADI_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0034)
#define REG_AON_CLK_PWM0_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0038)
#define REG_AON_CLK_PWM1_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x003c)
#define REG_AON_CLK_PWM2_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0040)
#define REG_AON_CLK_PWM3_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0044)
#define REG_AON_CLK_THM_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0048)
#define REG_AON_CLK_CA7_DAP_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x004C)
#define REG_AON_CLK_CA7_TS_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0050)
#define REG_AON_CLK_MSPI_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0054)
#define REG_AON_CLK_I2C_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0058)
#define REG_AON_CLK_RFTI_SBI_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x005C)
#define REG_AON_CLK_AVS0_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0060)
#define REG_AON_CLK_AVS1_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0064)
#define REG_AON_CLK_DJTAG_TCK_CFG SCI_ADDR(REGS_AON_CLK_BASE, 0x0068)
/* vars definitions for controller REGS_AON_CLK */
#endif //__REGS_AON_CLK_H__
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