1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
|
/******************************************************************************
* LEGAL NOTICE *
* *
* USE OF THIS SOFTWARE (including any copy or compiled version thereof) AND *
* DOCUMENTATION IS SUBJECT TO THE SOFTWARE LICENSE AND RESTRICTIONS AND THE *
* WARRANTY DISLCAIMER SET FORTH IN LEGAL_NOTICE.TXT FILE. IF YOU DO NOT *
* FULLY ACCEPT THE TERMS, YOU MAY NOT INSTALL OR OTHERWISE USE THE SOFTWARE *
* OR DOCUMENTATION. *
* NOTWITHSTANDING ANYTHING TO THE CONTRARY IN THIS NOTICE, INSTALLING OR *
* OTHERISE USING THE SOFTWARE OR DOCUMENTATION INDICATES YOUR ACCEPTANCE OF *
* THE LICENSE TERMS AS STATED. *
* *
******************************************************************************/
#include <linux/kthread.h>
#include <linux/signal.h>
#include <soc/sprd/board.h>
#include <soc/sprd/hardware.h>
#include <soc/sprd/dma.h>
#include <linux/slab.h>
#include "CgCpu.h"
#include "platform.h"
#ifndef CGCORE_ACCESS_VIA_SPI
#define INVALIDE_DMA_CHN (-1)
static struct sci_dma_cfg *cfg_list;
static struct reg_cfg_addr cfg_addr;
static int node_size;
static int cg_GpsDma_channel = INVALIDE_DMA_CHN;
static char *CgGps_Dev_name = "CgGps_Dev";
extern void clear_buf_data(void);
extern void CCgCpuDmaHandle(int irq,void* dev_id);
TCgReturnCode CgCpuDmaCreate(U32 aDmaChannel, U32 aIpDataSourceAddress)
{
DBG_FUNC_NAME("CgCpuDmaCreate");
DBGMSG("entry");
if(cg_GpsDma_channel == INVALIDE_DMA_CHN)
{
cg_GpsDma_channel = sci_dma_request(CgGps_Dev_name, FULL_DMA_CHN);
if(cg_GpsDma_channel < 0)
{
printk("CgCpuDmaCreate fail err code = %d\n",cg_GpsDma_channel);
return cg_GpsDma_channel;
}
printk("CgCpuDmaCreate succ chn = %d\n",cg_GpsDma_channel);
}
return ECgOk;
}
TCgReturnCode CgCpuDmaDestroy(U32 aDmaChannel, U32 aIpDataSourceAddress)
{
int rc;
printk("%s cg_GpsDma_channel:%d\n",__func__,cg_GpsDma_channel);
if(cg_GpsDma_channel != INVALIDE_DMA_CHN)
{
rc = sci_dma_stop(cg_GpsDma_channel, DMA_GPS);
if(rc < 0)
{
printk("CgCpuDmaDestroy stop chn fail, chn num = %d, err code = %d\n",cg_GpsDma_channel,rc);
}
rc = sci_dma_free(cg_GpsDma_channel);
if(rc < 0)
{
printk("CgCpuDmaDestroy free chn fail, chn num = %d, err code = %d\n",cg_GpsDma_channel,rc);
}
cg_GpsDma_channel = INVALIDE_DMA_CHN;
}
return ECgOk ;
}
TCgReturnCode CgCpuDmaIsReady(U32 aDmaChannel)
{
TCgReturnCode rc = ECgOk;
DBG_FUNC_NAME("CgCpuDmaIsReady");
DBGMSG("entry");
return rc;
}
TCgReturnCode CgCpuDmaStop(U32 aDmaChannel)
{
int rc;
if(cfg_list != NULL)
{
kfree(cfg_list);
cfg_list = NULL;
}
if(cfg_addr.virt_addr)
{
dma_free_coherent(NULL, sizeof(struct sci_dma_cfg) * node_size, (void *)cfg_addr.virt_addr, cfg_addr.phys_addr);
cfg_addr.virt_addr = 0;
cfg_addr.phys_addr = 0;
node_size = 0;
}
rc = sci_dma_stop(cg_GpsDma_channel, DMA_GPS);
if(rc < 0)
{
printk("CgCpuDmaStop stop chn fail, chn num = %d, err code = %d\n",cg_GpsDma_channel,rc);
}
return ECgOk;
}
TCgReturnCode CgCpuDmaCurCount(U32 aDmaChannel, U32 *apCount)
{
TCgReturnCode rc = ECgOk;
DBG_FUNC_NAME("CgCpuDmaCurCount");
DBGMSG("entry");
return rc;
}
// Get the DMA channel requested bytes count.
TCgReturnCode CgCpuDmaRequestedCount(U32 aDmaChannel, U32 *apCount)
{
TCgReturnCode rc = ECgOk;
DBG_FUNC_NAME("CgCpuDmaRequestedCount");
DBGMSG("entry");
return rc;
}
TCgReturnCode CgCpuDmaStart(U32 aDmaChannel)
{
int rc;
printk("%s\n",__func__);
CgCpuCacheSync();
rc = sci_dma_start(cg_GpsDma_channel, DMA_GPS);
if(rc < 0)
{
printk("CgCpuDmaStart start chn fail, chn num = %d, err code = %d\n",cg_GpsDma_channel,rc);
}
//CgCpuCacheSync();
return ECgOk;
}
// Configure DMA to read data from GPS device.
TCgReturnCode CgCpuDmaSetupFromGps(TCgCpuDmaTask *apDmaTask, U32 aDmaTaskCount, U32 aDmaChannel, U32 aDeviceAddress)
{
dma_addr_t cfg_p;
void * cfg_v;
int i,ret;
clear_buf_data();
if(aDmaTaskCount == 0)
{
return ECgBadArgument;
}
if(cfg_list != NULL)
{
kfree(cfg_list);
cfg_list = NULL;
}
if(cfg_addr.virt_addr != 0)
{
dma_free_coherent(NULL, sizeof(struct sci_dma_cfg) * node_size, (void *)cfg_addr.virt_addr, cfg_addr.phys_addr);
cfg_addr.virt_addr = 0;
cfg_addr.phys_addr = 0;
node_size = 0;
}
node_size = aDmaTaskCount;
if(cfg_list == NULL)
{
cfg_list = kzalloc(sizeof(struct sci_dma_cfg) * node_size, GFP_KERNEL);
if (!cfg_list) {
printk("alloc memory failed!\n");
return -ENOMEM;
}
}
cfg_v = dma_alloc_coherent(NULL, sizeof(struct sci_dma_cfg) * node_size,
&cfg_p, GFP_KERNEL);
if (!cfg_v) {
printk("alloc cfg list mem failed!\n");
return -ENOMEM;
}
cfg_addr.phys_addr = (u32)cfg_p;
cfg_addr.virt_addr = (u32)cfg_v;
/*must init the config with 0x0*/
memset((void *)cfg_list, 0x0, sizeof(struct sci_dma_cfg) * node_size);
for (i = 0; i < node_size; i++) {
/*the data width, byte short or word*/
cfg_list[i].datawidth = WORD_WIDTH;
cfg_list[i].src_step = 4;
cfg_list[i].des_step = 4;
cfg_list[i].wrap_ptr = 0x21c0007c;
cfg_list[i].wrap_to = 0x21c00070;
cfg_list[i].fragmens_len = 16;
/* request mode:
* when receive an hardware or software dma request
* the dma will transfer a fragment, block or a transcation data
*/
cfg_list[i].req_mode = FRAG_REQ_MODE;
cfg_list[i].src_addr = aDeviceAddress;
cfg_list[i].des_addr = apDmaTask[i].address;
cfg_list[i].block_len = apDmaTask[i].length >= 65536 ? 65536 :apDmaTask[i].length;
cfg_list[i].transcation_len = apDmaTask[i].length;
//printk("\n cfg_list[%d].block_len = %d\n",i,cfg_list[i].block_len);
//printk("\n cfg_list[%d].transcation_len = %d\n",i,cfg_list[i].transcation_len);
//printk("\n cfg_list[%d].src_addr = 0x%x\n",i,cfg_list[i].src_addr);
//printk("\n cfg_list[%d].des_addr = 0x%x\n",i,cfg_list[i].des_addr);
}
/*indicate this the last node*/
cfg_list[node_size - 1].is_end = 1;
ret = sci_dma_config(cg_GpsDma_channel, cfg_list, node_size, &cfg_addr);
if (ret < 0) {
printk("dma config failed!\n");
}
sci_dma_register_irqhandle(cg_GpsDma_channel,TRANS_DONE,CCgCpuDmaHandle,NULL);
return ECgOk;
}
#else
TCgReturnCode CgCpuDmaCreate(U32 aDmaChannel, U32 aIpDataSourceAddress)
{
return ECgOk;
}
TCgReturnCode CgCpuDmaDestroy(U32 aDmaChannel, U32 aIpDataSourceAddress)
{
return ECgOk ;
}
TCgReturnCode CgCpuDmaIsReady(U32 aDmaChannel)
{
return ECgOk;
}
TCgReturnCode CgCpuDmaStop(U32 aDmaChannel)
{
return ECgOk;
}
TCgReturnCode CgCpuDmaCurCount(U32 aDmaChannel, U32 *apCount)
{
return ECgOk;
}
TCgReturnCode CgCpuDmaRequestedCount(U32 aDmaChannel, U32 *apCount)
{
return ECgOk;
}
TCgReturnCode CgCpuDmaStart(U32 aDmaChannel)
{
return ECgOk;
}
TCgReturnCode CgCpuDmaSetupFromGps(TCgCpuDmaTask *apDmaTask, U32 aDmaTaskCount, U32 aDmaChannel, U32 aDeviceAddress)
{
return ECgOk;
}
#endif
#ifdef TRACE_ON
void DbgStatDMA(const char *aTitle)
{
//DBG_FUNC_NAME("DbgStatDMA");
//DBGMSG1("%s", aTitle);
}
#endif
|
