Initial file dump from open source releaseHEADmaster

13 files changed, 2283 insertions, 0 deletions

diff --git a/drivers/media/sprd_sensor/csi2/csi_access.c b/drivers/media/sprd_sensor/csi2/csi_access.c
new file mode 100644
index 00000000..9a37476f
--- /dev/null
+++ b/drivers/media/sprd_sensor/csi2/csi_access.c
@@ -0,0 +1,26 @@
+/*
+ *  access.c
+ *
+ *  Created on: Jun 25, 2010
+ *      Author: klabadi & dlopo
+ */
+#include "csi_types.h"
+#include "csi_access.h"
+#include "csi_log.h"
+
+static u32 * access_base_addr = 0;
+int access_init(u32 * base_addr)
+{
+    access_base_addr = base_addr;
+    return 0;
+}
+
+u32 access_read(u16 addr)
+{
+    return access_base_addr[addr];
+}
+
+void access_write(u32 data, u16 addr)
+{
+    access_base_addr[addr] = data;
+}
\ No newline at end of file
diff --git a/drivers/media/sprd_sensor/csi2/csi_access.h b/drivers/media/sprd_sensor/csi2/csi_access.h
new file mode 100644
index 00000000..6c9e8ee9
--- /dev/null
+++ b/drivers/media/sprd_sensor/csi2/csi_access.h
@@ -0,0 +1,17 @@
+/*
+ * access.h
+ *
+ *  Created on: Jun 25, 2010
+ *      Author: klabadi & dlopo
+ */
+
+#ifndef ACCESS_H_
+#define ACCESS_H_
+
+#include <linux/types.h>
+int access_init(u32 * base_addr);
+u32 access_read(u16 addr);
+
+void access_write(u32 data, u16 addr);
+
+#endif /* ACCESS_H_ */
\ No newline at end of file
diff --git a/drivers/media/sprd_sensor/csi2/csi_api.c b/drivers/media/sprd_sensor/csi2/csi_api.c
new file mode 100644
index 00000000..12af2bf6
--- /dev/null
+++ b/drivers/media/sprd_sensor/csi2/csi_api.c
@@ -0,0 +1,730 @@
+#include <linux/kernel.h>
+#include <linux/semaphore.h>
+#include <linux/delay.h>
+#include <linux/vmalloc.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <soc/sprd/sci_glb_regs.h>
+
+#ifndef CONFIG_64BIT
+#include <mach/irqs.h>
+#include <soc/sprd/globalregs.h>
+#include <soc/sprd/hardware.h>
+#else
+#include <soc/sprd/irqs.h>
+#endif
+#include "parse_hwinfo.h"
+#include <soc/sprd/sci.h>
+
+#include "csi_api.h"
+#include "csi_log.h"
+
+#define CSI2_EB              (SPRD_MMAHB_BASE)
+#define CSI2_EB_BIT          (1 << 4)
+#define CSI2_RST             (SPRD_MMAHB_BASE + 0x4)
+#define CSI2_RST_BIT         (1 << 5)
+
+#if defined(CONFIG_SC_FPGA) && defined(CONFIG_MACH_SP7720EA)
+extern void usc28c_csi_init(void);
+#endif
+void csi_api_event1_handler(int irq, void *handle);
+void csi_api_event2_handler(int irq, void *handle);
+
+
+static void csi_phy_power_down(u32 phy_id, u32 is_eb)
+{
+#if IS_ENABLED(VERSION3T) || IS_ENABLED(VERSION3D)
+	/*bit0: phya ; bit1: phyb*/
+	if (is_eb) {
+		if (0x03 == (phy_id & 0x03)) {
+			sci_glb_set(REG_AON_APB_PWR_CTRL, (BIT_CSI0_PHY_PD | BIT_CSI1_PHY_PD));
+		} else {
+			if (0x01 == (phy_id & 0x01)) {
+				sci_glb_set(REG_AON_APB_PWR_CTRL, BIT_CSI0_PHY_PD);
+			}
+
+			if (0x02 == (phy_id & 0x02)) {
+				sci_glb_set(REG_AON_APB_PWR_CTRL, BIT_CSI1_PHY_PD);
+			}
+		}
+	} else {
+		if (0x03 == (phy_id & 0x03)) {
+			sci_glb_clr(REG_AON_APB_PWR_CTRL, (BIT_CSI0_PHY_PD | BIT_CSI1_PHY_PD));
+		} else {
+			if (0x01 == (phy_id & 0x01)) {
+				sci_glb_clr(REG_AON_APB_PWR_CTRL, BIT_CSI0_PHY_PD);
+			}
+
+			if (0x02 == (phy_id & 0x02)) {
+				sci_glb_clr(REG_AON_APB_PWR_CTRL, BIT_CSI1_PHY_PD);
+			}
+		}
+	}
+#elif IS_ENABLED(VERSION3L)
+	/*bit0: phya ; bit1: phyb*/
+	if (is_eb) {
+		if (0x03 == (phy_id & 0x03)) {
+			printk("csi phy erro: scx35l does not support the combination of phya & phyb\n");
+		} else {
+			if (0x01 == (phy_id & 0x01)) {
+				sci_glb_set(REG_AON_APB_PWR_CTRL, (3 << 12));
+			}
+
+			if (0x02 == (phy_id & 0x02)) {
+				sci_glb_set(REG_AON_APB_PWR_CTRL, (3 << 10));
+			}
+		}
+	} else {
+		if (0x03 == (phy_id & 0x03)) {
+			printk("csi phy erro: scx35l does not support the combination of phya & phyb\n");
+		} else {
+			if (0x01 == (phy_id & 0x01)) {
+				sci_glb_clr(REG_AON_APB_PWR_CTRL, (1 << 13));
+				udelay(500);
+				sci_glb_clr(REG_AON_APB_PWR_CTRL, (1 << 12));
+			}
+
+			if (0x02 == (phy_id & 0x02)) {
+				sci_glb_clr(REG_AON_APB_PWR_CTRL, (1 << 11));
+				udelay(500);
+				sci_glb_clr(REG_AON_APB_PWR_CTRL, (1 << 10));
+			}
+		}
+	}
+#endif
+}
+
+static void csi_enable(void)
+{
+	sci_glb_set(CSI2_EB, CSI2_EB_BIT);
+	sci_glb_set(CSI2_RST, CSI2_RST_BIT);
+	udelay(1);
+	sci_glb_clr(CSI2_RST, CSI2_RST_BIT);
+}
+
+int csi_api_malloc(void **handle)
+{
+	int ret = 0;
+	struct csi_context *csi_handle = NULL;
+	csi_handle = (struct csi_context *)vzalloc(sizeof(struct csi_context));
+	if (NULL == handle) {
+		printk("vzalloc fail,no mem");
+		return -1;
+	}
+	csi_handle->g_csi2_irq = 0x12000034;
+	spin_lock_init(&csi_handle->csi2_lock);
+	*handle = csi_handle;
+
+	return ret;
+}
+
+void csi_api_free(void *handle)
+{
+	if (handle != NULL) {
+		vfree(handle);
+		handle = NULL;
+	}
+}
+
+u8 csi_api_init(u32 bps_per_lane, u32 phy_id)
+{
+	csi_error_t e = SUCCESS;
+    u64 base_address = CSI2_BASE;
+
+#if defined(CONFIG_SC_FPGA) && defined(CONFIG_MACH_SP7720EA)
+	usc28c_csi_init();
+#endif
+
+    do {
+		csi_phy_power_down(phy_id, 0);
+		csi_enable();
+		e = csi_init(base_address);
+		if(e != SUCCESS) {
+			LOG_ERROR("Unable to initialise driver");
+			break;
+		}
+		dphy_init(bps_per_lane, phy_id);
+    }while(0);
+
+    return e;
+}
+
+u8 csi_api_start(void *handle)
+{
+	csi_error_t e = SUCCESS;
+	int         ret = 0;
+	struct csi_context *csi_handle = handle;
+
+	if (NULL == handle) {
+		printk("handle null\n");
+		return ERR_UNDEFINED;
+	}
+	do {
+		/* set only one lane (lane 0) as active (ON) */
+		e = csi_set_on_lanes(1);
+		if(e != SUCCESS) {
+			LOG_ERROR("Unable to set lanes");
+			csi_close();
+			break;
+		}
+		LOG_DEBUG("Lane set OK");
+		e = csi_shut_down_phy(0);
+		if(e != SUCCESS) {
+			LOG_ERROR("Unable to bring up PHY");
+			csi_close();
+			break;
+		}
+		LOG_DEBUG("PHY power up OK");
+
+		e = csi_reset_phy();
+		if(e != SUCCESS) {
+			LOG_ERROR("Unable to reset PHY");
+			csi_close();
+			break;
+		}
+		LOG_DEBUG("PHY reset OK");
+
+		e = csi_reset_controller();
+		if(e != SUCCESS) {
+			LOG_ERROR("Unable to reset controller");
+			csi_close();
+			break;
+		}
+		/* MASK all interrupts */
+		csi_event_disable(0xffffffff, 1);
+		csi_event_disable(0xffffffff, 2);
+		ret = request_irq(IRQ_CSI_INT0,
+				(irq_handler_t)csi_api_event1_handler,
+				IRQF_SHARED,
+				"CSI2_0",
+				(void *)csi_handle);
+		if (ret) {
+			e = ERR_UNDEFINED;
+			break;
+		}
+
+		ret = request_irq(IRQ_CSI_INT1,
+				(irq_handler_t)csi_api_event2_handler,
+				IRQF_SHARED,
+				"CSI2_1",
+				(void *)csi_handle);
+		if (ret) {
+			e = ERR_UNDEFINED;
+			break;
+		}
+
+	} while(0);
+
+	return e;
+}
+
+u8 csi_api_close(void *handle, u32 phy_id)
+{
+	struct csi_context *csi_handle = handle;
+	if (NULL == handle) {
+		printk("handle null\n");
+		return ERR_UNDEFINED;
+	}
+	LOG_DEBUG("exit");
+	csi_api_unregister_all_events(handle);
+	csi_shut_down_phy(1);
+	free_irq(IRQ_CSI_INT0, &csi_handle->g_csi2_irq);
+	free_irq(IRQ_CSI_INT1, &csi_handle->g_csi2_irq);
+	csi_close();
+	csi_phy_power_down(phy_id, 1);
+
+	return SUCCESS;
+}
+
+u8 csi_api_set_on_lanes(u8 no_of_lanes)
+{
+    return csi_set_on_lanes(no_of_lanes);
+}
+
+u8 csi_api_get_on_lanes()
+{
+    return csi_get_on_lanes();
+}
+
+csi_lane_state_t csi_api_get_clk_state()
+{
+    return csi_clk_state();
+}
+
+csi_lane_state_t csi_api_get_lane_state(u8 lane)
+{
+    return csi_lane_module_state(lane);
+}
+
+static u32 csi_api_event_map(u8 event, u8 vc_lane)
+{
+	switch((csi_event_t)(event)) {
+	case ERR_PHY_TX_START:
+		return (0x1 << (event + vc_lane));
+	case ERR_FRAME_BOUNDARY_MATCH:
+		return (0x1 << (event + vc_lane));
+	case ERR_FRAME_SEQUENCE:
+		return (0x1 << (event + vc_lane));
+	case ERR_CRC_DURING_FRAME:
+		return (0x1 << (event + vc_lane));
+	case ERR_LINE_CRC:
+		return (0x1 << (24 + vc_lane));
+	case ERR_DOUBLE_ECC:
+		return (0x1 << 28);
+	case ERR_PHY_ESCAPE_ENTRY:
+		return (0x1 << (0 + vc_lane));
+	case ERR_ECC_SINGLE:
+		return (0x1 << (8 + vc_lane));
+	case ERR_UNSUPPORTED_DATA_TYPE:
+		return (0x1 << (12 + vc_lane));
+	case MAX_EVENT:
+		break;
+	default:
+		break;
+	}
+	switch((csi_line_event_t)(event)) {
+	case ERR_LINE_BOUNDARY_MATCH:
+		return (0x1 << (16 + (vc_lane % 4)));
+	case ERR_LINE_SEQUENCE:
+		return (0x1 << (20 + (vc_lane % 4)));
+	default:
+		break;
+	}
+	/* writing the following value affects nothing */
+	return 0x80000000;
+}
+
+u8 csi_api_register_event(void *handle, csi_event_t event, u8 vc_lane, handler_t handler)
+{
+	/* the VC_LANE value is the lane number ONLY in PHY ERRORS
+	  * e rest are all virtual channels number except for
+	  * double ECC, where VC is unknown
+	  */
+	u8 e = SUCCESS;
+	struct csi_context *csi_handle = handle;
+	if (NULL == handle) {
+		printk("handle null\n");
+		return ERR_UNDEFINED;
+	}
+	/* the maximum */
+	if (vc_lane < 4) {
+		switch(event) {
+		case ERR_PHY_TX_START:
+				LOG_WARNING("the lane value depends on the synthesis defines");
+				LOG_WARNING("make sure this value does not exceed these defines");
+		case ERR_FRAME_BOUNDARY_MATCH:
+		case ERR_FRAME_SEQUENCE:
+		case ERR_CRC_DURING_FRAME:
+		case ERR_LINE_CRC:
+		case ERR_DOUBLE_ECC:
+			e = csi_event_enable(csi_api_event_map(event, vc_lane), 1);
+			break;
+
+		case ERR_PHY_ESCAPE_ENTRY:
+			LOG_WARNING("the lane value depends on the synthesis defines");
+			LOG_WARNING("make sure this value does not exceed these defines");
+		case ERR_ECC_SINGLE:
+		case ERR_UNSUPPORTED_DATA_TYPE:
+			e = csi_event_enable(csi_api_event_map(event, vc_lane), 2);
+			break;
+
+		default:
+			e = ERROR_EVENT_TYPE_INVALID;
+			break;
+		}
+	} else {
+		e = ERROR_VC_LANE_OUT_OF_BOUND;
+	}
+	if (e == SUCCESS) {
+		csi_handle->csi_api_event_registry[event + vc_lane] = handler;
+	}
+
+	return e;
+}
+
+u8 csi_api_unregister_event(void *handle, csi_event_t event, u8 vc_lane)
+{
+	csi_error_t e = SUCCESS;
+	struct csi_context *csi_handle = handle;
+	if (NULL == handle) {
+		printk("handle null\n");
+		return ERR_UNDEFINED;
+	}
+	/* the maximum */
+    if (vc_lane < 4) {
+		switch(event) {
+		case ERR_PHY_TX_START:
+			LOG_WARNING("the lane value depends on the synthesis defines");
+			LOG_WARNING("make sure this value does not exceed these defines");
+		case ERR_FRAME_BOUNDARY_MATCH:
+		case ERR_FRAME_SEQUENCE:
+		case ERR_CRC_DURING_FRAME:
+		case ERR_LINE_CRC:
+		case ERR_DOUBLE_ECC:
+			e = csi_event_disable(csi_api_event_map(event, vc_lane), 1);
+			break;
+
+		case ERR_PHY_ESCAPE_ENTRY:
+			LOG_WARNING("the lane value depends on the synthesis defines");
+			LOG_WARNING("make sure this value does not exceed these defines");
+		case ERR_ECC_SINGLE:
+		case ERR_UNSUPPORTED_DATA_TYPE:
+			e = csi_event_disable(csi_api_event_map(event, vc_lane), 2);
+			break;
+
+		default:
+			e = ERROR_EVENT_TYPE_INVALID;
+			break;
+
+		}
+    } else {
+        e = ERROR_VC_LANE_OUT_OF_BOUND;
+    }
+    if (e == SUCCESS) {
+        csi_handle->csi_api_event_registry[event + vc_lane] = NULL;
+    }
+
+    return e;
+}
+
+u8 csi_api_register_line_event(void *handle, u8 vc, csi_data_type_t data_type, csi_line_event_t line_event, handler_t handler)
+{
+	u8 id = 0;
+	int counter = 0;
+	int first_slot = -1;
+	int already_registered = 0;
+	u8 e = SUCCESS;
+	struct csi_context *csi_handle = handle;
+	if (NULL == handle) {
+		printk("handle null\n");
+		return ERR_UNDEFINED;
+	}
+
+	if ((data_type < NULL_PACKET)
+	|| ((data_type > EMBEDDED_8BIT_NON_IMAGE_DATA) && (data_type < YUV420_8BIT))
+	|| ((data_type > RGB888) && (data_type < RAW6))
+	|| ((data_type > RAW14) && (data_type < USER_DEFINED_8BIT_DATA_TYPE_1 ))
+	|| (data_type > USER_DEFINED_8BIT_DATA_TYPE_8)) {
+		/* wrong data type - not long packet */
+		return ERROR_DATA_TYPE_INVALID;
+	}
+	/* the maximum */
+	if (vc > 3) {
+		return ERROR_VC_LANE_OUT_OF_BOUND;
+	}
+	id = (u8)((vc << 6)) | (u8)(data_type);
+
+	for (counter = 0; counter < 8; counter++) {
+		if (csi_get_registered_line_event(counter) == 0) {
+			/* first empty slot to register event */
+			first_slot = counter;
+			break;
+		}
+		if (id == csi_get_registered_line_event(counter)) {
+			LOG_WARNING("already registered line/datatype");
+			already_registered = 1;
+			first_slot = counter; /* no need to register it again */
+								/* but NOT that there are no slots!*/
+			break;
+		}
+	}
+	/* if not all slots are taken */
+	if (first_slot != -1) {
+		/* un-mask (whether registered or not) */
+		e = csi_event_enable(csi_api_event_map(line_event, first_slot), (first_slot / 4 == 1)? 2: 1);
+		if (e == SUCCESS) {
+			/* if not already registered */
+			if (already_registered != 1) {
+				e = csi_register_line_event(vc, data_type, first_slot);
+				if (csi_handle->csi_api_event_registry[line_event + first_slot] != NULL) {
+					LOG_WARNING("already registered event and callback (overwriting!)");
+				}
+			}
+			/* register callback */
+			csi_handle->csi_api_event_registry[line_event + first_slot] = handler;
+		}
+	} else {
+		LOG_WARNING("all slots are taken");
+		e = ERROR_SLOTS_FULL;
+	}
+
+	return e;
+}
+
+u8 csi_api_unregister_line_event(void *handle, u8 vc, csi_data_type_t data_type, csi_line_event_t line_event)
+{
+	u8 id = 0;
+	int counter = 0;
+	int replace_slot = -1;
+	int last_slot = -1;
+	u8 vc_new = 0;
+	csi_data_type_t dt_new;
+	csi_line_event_t other_line_event;
+	struct csi_context *csi_handle = handle;
+	if (NULL == handle) {
+		printk("handle null\n");
+		return ERR_UNDEFINED;
+	}
+
+	if ((data_type < NULL_PACKET)
+	|| ((data_type > EMBEDDED_8BIT_NON_IMAGE_DATA) && (data_type < YUV420_8BIT))
+	|| ((data_type > RGB888) && (data_type < RAW6))
+	|| ((data_type > RAW14) && (data_type < USER_DEFINED_8BIT_DATA_TYPE_1 ))
+	|| (data_type > USER_DEFINED_8BIT_DATA_TYPE_8)) {
+		/* wrong data type - not long packet */
+		return ERROR_DATA_TYPE_INVALID;
+	}
+	/* the maximum */
+	if (vc > 3) {
+		return ERROR_VC_LANE_OUT_OF_BOUND;
+	}
+	if (line_event == ERR_LINE_BOUNDARY_MATCH) {
+		other_line_event = ERR_LINE_SEQUENCE;
+	} else if (line_event == ERR_LINE_SEQUENCE) {
+		other_line_event = ERR_LINE_BOUNDARY_MATCH;
+	} else {
+		return ERROR_DATA_TYPE_INVALID;
+	}
+	id = (vc << 6) | data_type;
+	for (counter = 0; counter < 8; counter++) {
+		if (id == csi_get_registered_line_event(counter)) {
+			replace_slot = counter;
+		}
+		if (csi_get_registered_line_event(counter) == 0) {
+			last_slot = counter - 1;
+			break;
+		}
+	}
+	if (replace_slot == -1) {
+		return ERROR_NOT_REGISTERED;
+	}
+	if (last_slot == -1) {
+		last_slot = 7; /* the very last entry */
+	}
+	vc_new = csi_get_registered_line_event(last_slot) >> 6;
+	dt_new = (csi_get_registered_line_event(last_slot) << 2) >> 2;
+
+	if ((csi_handle->csi_api_event_registry[other_line_event + replace_slot] == NULL) && (last_slot != replace_slot)) {
+		/* swap IDI with last registered if its NOT the last entry*/
+		/* copy the last to (over) the one to be deleted*/
+		csi_register_line_event(vc_new, dt_new, replace_slot);
+		/* now that last registered is copied to a new location, unregister old location */
+		csi_event_disable(csi_api_event_map(line_event, last_slot), (last_slot / 4 == 1)? 2: 1);
+		/* swap event registry */
+		csi_handle->csi_api_event_registry[line_event + replace_slot] = csi_handle->csi_api_event_registry[line_event + last_slot];
+		/* mask last slot */
+		if (csi_handle->csi_api_event_registry[other_line_event + last_slot] != NULL) {
+			/* swap event registry - the other possible line event of the last slot */
+			csi_handle->csi_api_event_registry[other_line_event + replace_slot] = csi_handle->csi_api_event_registry[other_line_event + last_slot];
+			/* mask last slot, other line event!*/
+			csi_event_disable(csi_api_event_map(other_line_event, last_slot), (last_slot / 4 == 1)? 2: 1);
+			/* un mask other line event */
+			csi_event_enable(csi_api_event_map(other_line_event, replace_slot), (replace_slot / 4 == 1)? 2: 1);
+		}
+		csi_unregister_line_event(last_slot);
+	} else {
+		/* remove from event registry */
+		csi_handle->csi_api_event_registry[line_event + replace_slot] = NULL;
+		/* mask */
+		csi_event_disable(csi_api_event_map(line_event, replace_slot), (replace_slot / 4 == 1)? 2: 1);
+
+		if ((csi_handle->csi_api_event_registry[other_line_event + replace_slot] == NULL) && (last_slot == replace_slot)) {  /* if it is last entry */
+			csi_unregister_line_event(last_slot);
+		}
+	}
+
+	return SUCCESS;
+}
+
+void csi_api_event1_handler(int irq, void *handle)
+{
+	u32 source = 0;
+	unsigned long flag;
+	struct csi_context *csi_handle = handle;
+	if (NULL == handle) {
+		printk("handle null\n");
+		return;
+	}
+
+	source = csi_event_get_source(1);
+	spin_lock_irqsave(&csi_handle->csi2_lock,flag);
+	if (NULL != csi_handle->isr_cb) {
+		(*csi_handle->isr_cb)(1, source, csi_handle->u_data);
+	}
+	spin_unlock_irqrestore(&csi_handle->csi2_lock, flag);
+
+	return;
+#if 0
+	if (source > 0) {   /* map to enumerator csi_event_t or csi_line_event_t */
+		if ((source & (0xf << 0)) > 0) {
+			tmp = ERR_PHY_TX_START + ((source & 0xf) >> 1);
+		}
+		if ((source & (0xf << 4)) > 0) {
+			tmp = ERR_FRAME_BOUNDARY_MATCH + ((source & 0xf0) >> 5);
+		}
+		if ((source & (0xf << 8)) > 0) {
+			tmp = ERR_FRAME_SEQUENCE + ((source & (0xf << 8)) >> 9);
+		}
+		if ((source & (0xf << 12)) > 0) {
+			tmp = ERR_CRC_DURING_FRAME + ((source & (0xf << 12)) >> 13);
+		}
+		if ((source & (0xf << 16)) > 0) {
+			tmp = ERR_LINE_BOUNDARY_MATCH + ((source & (0xf << 16)) >> 17);
+		}
+		if ((source & (0xf << 20)) > 0) {
+			tmp = ERR_LINE_SEQUENCE + ((source & (0xf << 20)) >> 21);
+		}
+		if ((source & (0xf << 24)) > 0) {
+			tmp = ERR_LINE_CRC + ((source & (0xf << 24)) >> 25);
+		}
+		if ((source & (0xf << 28)) > 0) {
+			tmp = ERR_DOUBLE_ECC;
+		}
+		/* call callback if valid */
+		if (tmp != 0x80000000) {
+			if (csi_api_event_registry[tmp] != NULL) {
+				csi_api_event_registry[tmp](param);
+			}
+		}
+	}
+#endif
+}
+
+void csi_api_event2_handler(int irq, void *handle)
+{
+	u32 source = 0;
+	unsigned long flag;
+	struct csi_context *csi_handle = handle;
+	if (NULL == handle) {
+		printk("handle null\n");
+		return ;
+	}
+
+	source = csi_event_get_source(2);
+	spin_lock_irqsave(&csi_handle->csi2_lock, flag);
+	if (csi_handle->isr_cb) {
+		(*csi_handle->isr_cb)(2, source, csi_handle->u_data);
+	}
+	spin_unlock_irqrestore(&csi_handle->csi2_lock, flag);
+
+	return;
+
+#if 0
+	source = csi_event_get_source(2);
+
+	if (source > 0) {
+		/* map to enumerator csi_event_t or csi_line_event_t */
+		if ((source & (0xf << 0)) > 0) {
+			tmp = ERR_PHY_ESCAPE_ENTRY + ((source & 0xf) >> 1);
+		}
+
+		if ((source & (0xf << 4)) > 0) {
+			; /* error discarded */
+		}
+
+		if ((source & (0xf << 8)) > 0) {
+			tmp = ERR_ECC_SINGLE + ((source & (0xf << 8)) >> 9);
+		}
+		if ((source & (0xf << 12)) > 0) {
+			tmp = ERR_UNSUPPORTED_DATA_TYPE + ((source & (0xf << 12)) >> 13);
+		}
+		if ((source & (0xf << 16)) > 0) {
+			tmp = ERR_LINE_BOUNDARY_MATCH + 4 + ((source & (0xf << 16)) >> 17);
+			/* 4 added because its in ERR2. ERR1 already has 4 */
+		}
+		if ((source & (0xf << 20)) > 0) {
+			tmp = ERR_LINE_SEQUENCE + 4 + ((source & (0xf << 20)) >> 21);
+		}
+		/* call callback if valid */
+		if (tmp != 0x80000000) {
+			if (csi_api_event_registry[tmp] != NULL) {
+				csi_api_event_registry[tmp](param);
+			}
+		}
+	}
+#endif
+}
+
+u8 csi_api_unregister_all_events(void *handle)
+{
+	u8 e = SUCCESS;
+	u8 counter = 0;
+	struct csi_context *csi_handle = handle;
+	if (NULL == handle) {
+		printk("handle null\n");
+		return -1;
+	}
+
+	e = csi_event_disable(0xffffffff, 1);
+	e = csi_event_disable(0xffffffff, 2);
+	if (e == SUCCESS) {
+		for (counter = 0; counter < 8; counter++) {
+			e = csi_unregister_line_event(counter);
+		}
+		for (counter = (u8)(ERR_PHY_TX_START); counter < (u8)(MAX_EVENT); counter++) {
+			csi_handle->csi_api_event_registry[counter] = NULL;
+		}
+	}
+
+	return e;
+}
+
+u8 csi_api_shut_down_phy(u8 shutdown)
+{
+	return csi_shut_down_phy(shutdown);
+}
+
+u8 csi_api_reset_phy()
+{
+	return csi_reset_phy();
+}
+
+u8 csi_api_reset_controller()
+{
+	return csi_reset_controller();
+}
+
+u8 csi_api_core_write(csi_registers_t address, u32 data)
+{
+	return csi_core_write(address, data);
+}
+
+u32 csi_api_core_read(csi_registers_t address)
+{
+	return csi_core_read(address);
+}
+
+int csi_reg_isr(void *handle, csi2_isr_func user_func, void* user_data)
+{
+	unsigned long                flag;
+	struct csi_context *csi_handle = handle;
+	if (NULL == handle) {
+		printk("handle null\n");
+		return ERR_UNDEFINED;
+	}
+
+	spin_lock_irqsave(&csi_handle->csi2_lock, flag);
+	csi_handle->isr_cb = user_func;
+	csi_handle->u_data = user_data;
+	spin_unlock_irqrestore(&csi_handle->csi2_lock, flag);
+
+	return 0;
+}
+
+int csi_read_registers(u32* reg_buf, u32 *buf_len)
+{
+	u32                *reg_addr = (u32*)CSI2_BASE;
+
+	if (NULL == reg_buf || NULL == buf_len || 0 != (*buf_len % 4)) {
+		return -1;
+	}
+
+	while (buf_len != 0 && reg_addr < (u64)(CSI2_BASE + SPRD_CSI2_REG_SIZE)) {
+		*reg_buf++ = *(volatile u32*)reg_addr++;
+		*buf_len -= 4;
+	}
+
+	*buf_len = SPRD_CSI2_REG_SIZE;
+
+	return 0;
+}
diff --git a/drivers/media/sprd_sensor/csi2/csi_api.h b/drivers/media/sprd_sensor/csi2/csi_api.h
new file mode 100644
index 00000000..b49bee7a
--- /dev/null
+++ b/drivers/media/sprd_sensor/csi2/csi_api.h
@@ -0,0 +1,79 @@
+/*
+ * csi_driver
+ * 12/05/2010
+ * Synopsys Inc. PT02
+ */
+
+#ifndef CSI_API_H_
+#define CSI_API_H_
+
+#include "csi_types.h"
+#include "csi_driver.h"
+#include <linux/spinlock.h>
+
+#define SPRD_CSI2_REG_SIZE             0x40
+
+typedef int (*csi2_isr_func)(u32 err_id, u32 err_status, void* u_data);
+
+/* enumerators index the handler array rather than masks */
+typedef enum
+{
+    ERR_PHY_TX_START = 0,
+    ERR_FRAME_BOUNDARY_MATCH = 4,
+    ERR_FRAME_SEQUENCE = 8,
+    ERR_CRC_DURING_FRAME = 12,
+    ERR_LINE_CRC = 16,
+    ERR_DOUBLE_ECC = 20,
+    ERR_PHY_ESCAPE_ENTRY = 21,
+    ERR_ECC_SINGLE = 25,
+    ERR_UNSUPPORTED_DATA_TYPE = 29,
+    MAX_EVENT = 49
+} csi_event_t;
+typedef enum
+{
+    ERR_LINE_BOUNDARY_MATCH = 33,
+    ERR_LINE_SEQUENCE = 41
+} csi_line_event_t;
+typedef enum
+{
+    ERROR_VC_LANE_OUT_OF_BOUND =    0xCA,
+    ERROR_EVENT_TYPE_INVALID = 0xC9,
+    ERROR_DATA_TYPE_INVALID = 0xC8,
+    ERROR_SLOTS_FULL = 0xC7,
+    ERROR_ALREADY_REGISTERED = 0xC6,
+    ERROR_NOT_REGISTERED = 0xC5
+} csi_api_error_t;
+
+struct csi_context {
+	u32                g_csi2_irq;
+	csi2_isr_func      isr_cb;
+	void              *u_data;
+	spinlock_t         csi2_lock;
+	handler_t          csi_api_event_registry[MAX_EVENT];
+};
+
+int csi_api_malloc(void **handle);
+void csi_api_free(void *handle);
+u8 csi_api_init(u32 bps_per_lane, u32 phy_id);
+u8 csi_api_start(void *handle);
+//u8 csi_api_start(u32 base_address);
+u8 csi_api_close(void *handle, u32 phy_id);
+u8 csi_api_set_on_lanes(u8 no_of_lanes);
+u8 csi_api_get_on_lanes(void);
+csi_lane_state_t csi_api_get_clk_state(void);
+csi_lane_state_t csi_api_get_lane_state(u8 lane);
+u8 csi_api_register_line_event(void *handle, u8 vc, csi_data_type_t data_type, csi_line_event_t line_event, handler_t handler);
+u8 csi_api_unregister_line_event(void *handle, u8 vc, csi_data_type_t data_type, csi_line_event_t line_event);
+u8 csi_api_register_event(void *handle, csi_event_t event, u8 vc_lane, handler_t handler);
+u8 csi_api_unregister_event(void *handle, csi_event_t event, u8 vc_lane);
+u8 csi_api_unregister_all_events(void *handle);
+u8 csi_api_shut_down_phy(u8 shutdown);
+u8 csi_api_reset_phy(void);
+u8 csi_api_reset_controller(void);
+u8 csi_api_core_write(csi_registers_t address, u32 data);
+u32 csi_api_core_read(csi_registers_t address);
+int csi_reg_isr(void *handle, csi2_isr_func user_func, void* user_data);
+int csi_read_registers(uint32_t* reg_buf, uint32_t *buf_len);
+
+#endif /* CSI_API_H_ */
+
diff --git a/drivers/media/sprd_sensor/csi2/csi_api_null.c b/drivers/media/sprd_sensor/csi2/csi_api_null.c
new file mode 100755
index 00000000..56b7556f
--- /dev/null
+++ b/drivers/media/sprd_sensor/csi2/csi_api_null.c
@@ -0,0 +1,130 @@
+#include <linux/kernel.h>
+#include <linux/semaphore.h>
+#include <linux/delay.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+
+
+#include "csi_api.h"
+#include "csi_log.h"
+
+void csi_api_event1_handler(int irq, void *handle);
+void csi_api_event2_handler(int irq, void *handle);
+int csi_api_malloc(void **handle)
+{
+	return ERR_NOT_COMPATIBLE;
+}
+
+void csi_api_free(void *handle)
+{
+}
+u8 csi_api_init(u32 bps_per_lane, u32 phy_id)
+{
+	return ERR_NOT_COMPATIBLE;
+}
+u8 csi_api_start(void *handle)
+{
+	return ERR_NOT_COMPATIBLE;
+}
+u8 csi_api_close(void *handle, u32 phy_id)
+{
+	return ERR_NOT_COMPATIBLE;
+}
+u8 csi_api_set_on_lanes(u8 no_of_lanes)
+{
+	return ERR_NOT_COMPATIBLE;
+}
+
+u8 csi_api_get_on_lanes()
+{
+	return ERR_NOT_COMPATIBLE;
+}
+csi_lane_state_t csi_api_get_clk_state()
+{
+	return ERR_NOT_COMPATIBLE;
+}
+csi_lane_state_t csi_api_get_lane_state(u8 lane)
+{
+	return ERR_NOT_COMPATIBLE;
+}
+u8 csi_api_register_event(void *handle, csi_event_t event, u8 vc_lane, handler_t handler)
+{
+	return ERR_NOT_COMPATIBLE;
+}
+u8 csi_api_unregister_event(void *handle, csi_event_t event, u8 vc_lane)
+{
+	return ERR_NOT_COMPATIBLE;
+}
+u8 csi_api_register_line_event(void *handle, u8 vc, csi_data_type_t data_type, csi_line_event_t line_event, handler_t handler)
+{
+	return ERR_NOT_COMPATIBLE;
+}
+u8 csi_api_unregister_line_event(void *handle, u8 vc, csi_data_type_t data_type, csi_line_event_t line_event)
+{
+	return ERR_NOT_COMPATIBLE;
+}
+void csi_api_event1_handler(int irq, void *handle)
+{
+	return ERR_NOT_COMPATIBLE;
+}
+void csi_api_event2_handler(int irq, void *handle)
+{
+	return ERR_NOT_COMPATIBLE;
+}
+u8 csi_api_unregister_all_events(void *handle)
+{
+	return ERR_NOT_COMPATIBLE;
+}
+u8 csi_api_shut_down_phy(u8 shutdown)
+{
+	return ERR_NOT_COMPATIBLE;
+}
+u8 csi_api_reset_phy()
+{
+	return ERR_NOT_COMPATIBLE;
+}
+u8 csi_api_reset_controller()
+{
+	return ERR_NOT_COMPATIBLE;
+}
+u8 csi_api_core_write(csi_registers_t address, u32 data)
+{
+	return ERR_NOT_COMPATIBLE;
+}
+u32 csi_api_core_read(csi_registers_t address)
+{
+	return ERR_NOT_COMPATIBLE;
+}
+
+int csi_reg_isr(void *handle, csi2_isr_func user_func, void* user_data)
+{
+	unsigned long                flag;
+	struct csi_context *csi_handle = handle;
+	if (NULL == handle) {
+		printk("handle null\n");
+		return ERR_UNDEFINED;
+	}
+
+	spin_lock_irqsave(&csi_handle->csi2_lock, flag);
+	csi_handle->isr_cb = user_func;
+	csi_handle->u_data = user_data;
+	spin_unlock_irqrestore(&csi_handle->csi2_lock, flag);
+	return 0;
+}
+
+int csi_read_registers(u32* reg_buf, u32 *buf_len)
+{
+	u32                *reg_addr = (u32*)CSI2_BASE;
+
+	if (NULL == reg_buf || NULL == buf_len || 0 != (*buf_len % 4)) {
+		return -1;
+	}
+
+	while (buf_len != 0 && (u32)reg_addr < (CSI2_BASE + SPRD_CSI2_REG_SIZE)) {
+		*reg_buf++ = *(volatile u32*)reg_addr++;
+		*buf_len -= 4;
+	}
+
+	*buf_len = SPRD_CSI2_REG_SIZE;
+	return 0;
+}
diff --git a/drivers/media/sprd_sensor/csi2/csi_driver.c b/drivers/media/sprd_sensor/csi2/csi_driver.c
new file mode 100644
index 00000000..dc4c922c
--- /dev/null
+++ b/drivers/media/sprd_sensor/csi2/csi_driver.c
@@ -0,0 +1,502 @@
+#include <linux/delay.h>
+#include "csi_driver.h"
+#include "csi_access.h"
+#include "csi_log.h"
+#ifndef CONFIG_64BIT
+#include <soc/sprd/hardware.h>
+#else
+#include "parse_hwinfo.h"
+#endif
+#include <soc/sprd/sci.h>
+
+
+static int csi_core_initialized = 0;
+
+static const struct csi_pclk_cfg csi_pclk_setting[CSI_PCLK_CFG_COUNTER] = {
+	{80,    90,   0x00, 4},
+	{90,   100, 0x10, 4},
+	{100, 110, 0x20, 4},
+	{110, 130, 0x01, 6},
+	{130, 140, 0x11, 6},
+	{140, 150, 0x21, 6},
+	{150, 170, 0x02, 9},
+	{170, 180, 0x12, 9},
+	{180, 200, 0x22, 9},
+	{200, 220, 0x03, 10},
+	{220, 240, 0x13, 10},
+	{240, 250, 0x23, 10},
+	{250, 270, 0x04, 13},
+	{270, 300, 0x14, 13},
+	{300, 330, 0x05, 17},
+	{330, 360, 0x15, 17},
+	{360, 400, 0x25, 17},
+#ifdef IS_ENABLED(VERSION3T) || IS_ENABLED(VERSION3D)
+	{400, 450, 0x06, 25},
+	{450, 500, 0x16, 26},
+#elif IS_ENABLED(VERSION3L)
+	{400, 450, 0x06, 23},
+	{450, 500, 0x16, 23},
+#endif
+	{500, 550, 0x07, 28},
+	{550, 600, 0x17, 28},
+	{600, 650, 0x08, 33},
+	{650, 700, 0x18, 33},
+	{700, 750, 0x09, 38},
+	{750, 800, 0x19, 38},
+	{800, 850, 0x29, 38},
+	{850, 900, 0x39, 38},
+	{900, 950, 0x0A, 52},
+	{950, 1000, 0x1A, 52}
+};
+
+#if IS_ENABLED(VERSION3T)
+static void dpy_ab_clr(void)
+{
+	sci_glb_clr(SPRD_MMAHB_BASE + 0x000C, 0x1F);
+}
+
+static void dpy_a_enable(void)
+{
+	sci_glb_clr(SPRD_MMAHB_BASE + 0x000C, 0x07);
+	sci_glb_set(SPRD_MMAHB_BASE + 0x000C, 0x0C);
+}
+
+static void dpy_b_enable(void)
+{
+	sci_glb_clr(SPRD_MMAHB_BASE + 0x000C, 0x07);
+	sci_glb_set(SPRD_MMAHB_BASE + 0x000C, 0x0F);
+}
+
+static void dpy_c_enable(void)
+{
+
+}
+
+static void dpy_ab_sync(void)
+{
+	sci_glb_clr(SPRD_MMAHB_BASE + 0x000C, 0x07);
+}
+#elif IS_ENABLED(VERSION3D)
+static void dpy_ab_clr(void)
+{
+	sci_glb_clr(SPRD_MMAHB_BASE + 0x000C, 0x3F);
+}
+
+static void dpy_a_enable(void)
+{
+	sci_glb_clr(SPRD_MMAHB_BASE + 0x000C, 0x07);
+	sci_glb_set(SPRD_MMAHB_BASE + 0x000C, 0x0C);
+}
+
+static void dpy_b_enable(void)
+{
+	sci_glb_clr(SPRD_MMAHB_BASE + 0x000C, 0x07);
+	sci_glb_set(SPRD_MMAHB_BASE + 0x000C, 0x0F);
+}
+
+static void dpy_c_enable(void)
+{
+	sci_glb_clr(SPRD_MMAHB_BASE + 0x000C, 0x3F);
+	sci_glb_set(SPRD_MMAHB_BASE + 0x000C, 0x2C);
+}
+
+static void dpy_ab_sync(void)
+{
+	sci_glb_clr(SPRD_MMAHB_BASE + 0x000C, 0x07);
+}
+#else IS_ENABLED(VERSION3L)
+static void dpy_ab_clr(void)
+{
+}
+static void dpy_a_enable(void)
+{
+	sci_glb_clr(SPRD_MMAHB_BASE + 0x000C, 0x01);
+}
+static void dpy_b_enable(void)
+{
+	sci_glb_set(SPRD_MMAHB_BASE + 0x000C, 0x01);
+}
+
+static void dpy_c_enable(void)
+{
+}
+
+static void dpy_ab_sync(void)
+{
+}
+#endif
+
+static void dphy_write(u8 test_code, u8 test_data, u8* test_out)
+{
+	u32 temp = 0xffffff00;
+
+	csi_core_write_part(PHY_TST_CRTL1, 0, PHY_TESTEN, 1); //phy_testen = 0
+	udelay(1);
+	csi_core_write_part(PHY_TST_CRTL0,1, PHY_TESTCLK, 1); //phy_testclk = 1
+	udelay(1);
+	csi_core_write_part(PHY_TST_CRTL1, test_code, PHY_TESTDIN, PHY_TESTDIN_W); //phy_testdin
+	udelay(1);
+	csi_core_write_part(PHY_TST_CRTL1, 1, PHY_TESTEN, 1);//phy_testen = 1
+	udelay(1);
+	csi_core_write_part(PHY_TST_CRTL0, 0, PHY_TESTCLK, 1);//phy_testclk = 0
+	udelay(1);
+	temp = csi_core_read_part(PHY_TST_CRTL1, PHY_TESTDOUT,PHY_TESTDOUT_W);
+	*test_out = (u8)temp;
+	udelay(1);
+	csi_core_write_part(PHY_TST_CRTL1, 0, PHY_TESTEN, 1); //phy_testen = 0
+	udelay(1);
+	csi_core_write_part(PHY_TST_CRTL1, test_data, PHY_TESTDIN, PHY_TESTDIN_W);//phy_testdin
+	udelay(1);
+	csi_core_write_part(PHY_TST_CRTL0,1, PHY_TESTCLK, 1);//phy_testclk = 1
+	udelay(1);
+}
+
+static void dphy_cfg_start(void)
+{
+	csi_core_write_part(PHY_TST_CRTL1, 0, PHY_TESTEN, 1); //phy_testen = 0
+	udelay(1);
+	csi_core_write_part(PHY_TST_CRTL0,1, PHY_TESTCLK, 1); //phy_testclk = 1
+	udelay(1);
+}
+
+static void dphy_cfg_done(void)
+{
+	csi_core_write_part(PHY_TST_CRTL1, 0, PHY_TESTEN, 1); //phy_testen = 0
+	udelay(1);
+	csi_core_write_part(PHY_TST_CRTL0,1, PHY_TESTCLK, 1); //phy_testclk = 1
+	udelay(1);
+	csi_core_write_part(PHY_TST_CRTL1, 0, PHY_TESTDIN, PHY_TESTDIN_W);//phy_testdin
+	udelay(1);
+	csi_core_write_part(PHY_TST_CRTL1, 1, PHY_TESTEN, 1);//phy_testen = 1
+	udelay(1);
+	csi_core_write_part(PHY_TST_CRTL0, 0, PHY_TESTCLK, 1);//phy_testclk = 0
+	udelay(1);
+}
+
+static void csi_get_pclk_cfg(u32 bps_per_lane, struct csi_pclk_cfg *csi_pclk_cfg_ptr)
+{
+	u32 i = 0;
+	int rtn = -1;
+
+	for (i =0 ; i < CSI_PCLK_CFG_COUNTER; i++) {
+		if ( bps_per_lane >= csi_pclk_setting[i].pclk_start && bps_per_lane < csi_pclk_setting[i].pclk_end) {
+			csi_pclk_cfg_ptr->hsfreqrange = csi_pclk_setting[i].hsfreqrange;
+			csi_pclk_cfg_ptr->hsrxthssettle = csi_pclk_setting[i].hsrxthssettle;
+			rtn = 0;
+			break;
+		}
+	}
+
+	if (rtn) {
+		csi_pclk_cfg_ptr->hsfreqrange = csi_pclk_setting[CSI_PCLK_CFG_COUNTER -2].hsfreqrange;
+		csi_pclk_cfg_ptr->hsrxthssettle = csi_pclk_setting[CSI_PCLK_CFG_COUNTER -2].hsrxthssettle;
+	}
+}
+
+static void dphy_init_common(u32 bps_per_lane, u32 phy_id, u32 rx_mode)
+{
+	u8 temp = 0;
+	struct csi_pclk_cfg csi_pclk_cfg_val = {0, 0, 0, 0};
+
+	csi_core_write_part(PHY_SHUTDOWNZ,  0, 0, 1);
+	csi_core_write_part(DPHY_RSTZ, 0, 0, 1);
+	csi_core_write_part(PHY_TST_CRTL0, 1, PHY_TESTCLR, 1);
+	udelay(1);
+	csi_core_write_part(PHY_TST_CRTL0, 0, PHY_TESTCLR, 1);
+	udelay(1);
+	dphy_cfg_start();
+
+#if defined(CONFIG_MACH_SP7720EA)
+#if defined(CONFIG_SC_FPGA)
+	sci_glb_write(SPRD_GPIO_BASE + 0x0008, 0xd, -1UL);
+	dphy_write(0x30, 0xc0, &temp);
+#endif
+	dphy_write(0x37, 0x03, &temp);
+	//LOG_DEBUG2 ("%04x default  reg value: %04x\r\n", 0x37, temp);
+	dphy_write(0x47, 0x03, &temp);
+	//LOG_DEBUG2 ("%04x default  reg value: %04x\r\n", 0x47, temp);
+	dphy_write(0x57, 0x03, &temp);
+	//LOG_DEBUG2 ("%04x default  reg value: %04x\r\n", 0x57, temp);
+	dphy_write(0x67, 0x03, &temp);
+	dphy_write(0x77, 0x03, &temp);
+#else
+	csi_get_pclk_cfg(bps_per_lane, &csi_pclk_cfg_val);
+
+#if IS_ENABLED(VERSION3L) || IS_ENABLED(VERSION3T) || IS_ENABLED(VERSION3D)
+	if (0x03 == phy_id) {
+		if (0x00 == rx_mode) {
+			dphy_write(0x34, 0x14, &temp);
+		} else {
+			dphy_write(0x34, 0xA0, &temp);
+		}
+	} else {
+		dphy_write(0x34, 0x14, &temp);
+	}
+#else
+	dphy_write(0x34, 0x14, &temp);
+#endif
+
+	dphy_write(0x44, (((csi_pclk_cfg_val.hsfreqrange & 0x3F) << 1) & 0x7E), &temp);
+	dphy_write(0x75, (0x80 | (csi_pclk_cfg_val.hsrxthssettle & 0x7F)), &temp);
+	dphy_write(0x54, 0x14, &temp);
+	dphy_write(0x64, 0x14, &temp);
+	dphy_write(0x74, 0x14, &temp);
+#endif
+	dphy_cfg_done();
+}
+
+void dphy_init(u32 bps_per_lane, u32 phy_id)
+{
+#if IS_ENABLED(VERSION3L) || IS_ENABLED(VERSION3T) || IS_ENABLED(VERSION3D)
+	dpy_ab_clr();
+
+	if (phy_id & 0x01) {
+		dpy_a_enable();
+		dphy_init_common(bps_per_lane, phy_id, 0);
+	}
+
+	if (phy_id & 0x02) {
+		dpy_b_enable();
+		dphy_init_common(bps_per_lane, phy_id, 1);
+	}
+
+	if (0x03 == (phy_id & 0x03)) {
+		dpy_ab_sync();
+	}
+
+	if (phy_id & 0x04) {
+		dpy_c_enable();
+		dphy_init_common(bps_per_lane, phy_id, 0);
+	}
+
+#else
+	dphy_init_common(bps_per_lane, phy_id, 0);
+#endif
+}
+
+u8 csi_init(u64 base_address)
+{
+    csi_error_t e = SUCCESS;
+    do {
+		if (csi_core_initialized == 0) {
+			access_init((u32*)base_address);
+			if (csi_core_read(VERSION) == (u32)(CURRENT_VERSION)) {
+				csi_core_initialized = 1;
+				break;
+			} else {
+				LOG_ERROR("Driver not compatible with core");
+				e = ERR_NOT_COMPATIBLE;
+				break;
+			}
+		} else {
+			LOG_ERROR("driver already initialised");
+			e = ERR_ALREADY_INIT;
+			break;
+		}
+    } while(0);
+
+    return e;
+}
+
+u8 csi_close()
+{
+	csi_shut_down_phy(1);
+	csi_reset_controller();
+	csi_core_initialized = 0;
+	return SUCCESS;
+}
+
+u8 csi_get_on_lanes()
+{
+	return (csi_core_read_part(N_LANES, 0, 2) + 1);
+}
+
+u8 csi_set_on_lanes(u8 lanes)
+{
+	return csi_core_write_part(N_LANES, (lanes - 1), 0, 2);
+}
+
+u8 csi_shut_down_phy(u8 shutdown)
+{
+	LOG_DEBUG2("shutdown", shutdown);
+	/*  active low - bit 0 */
+	return csi_core_write_part(PHY_SHUTDOWNZ, shutdown? 0: 1, 0, 1);
+}
+
+u8 csi_reset_phy()
+{
+	/*  active low - bit 0 */
+	int retVal = 0xffff;
+	retVal = csi_core_write_part(DPHY_RSTZ, 0, 0, 1);
+	switch (retVal) {
+	case SUCCESS:
+		return csi_core_write_part(DPHY_RSTZ, 1, 0, 1);
+		break;
+	case ERR_NOT_INIT:
+		LOG_ERROR("Driver not initialized");
+		return retVal;
+		break;
+	default:
+		LOG_ERROR("Undefined error");
+		return ERR_UNDEFINED;
+		break;
+	}
+}
+
+u8 csi_reset_controller()
+{
+	/*  active low - bit 0 */
+	int retVal = 0xffff;
+	retVal = csi_core_write_part(CSI2_RESETN, 0, 0, 1);
+	switch (retVal) {
+	case SUCCESS:
+		return csi_core_write_part(CSI2_RESETN, 1, 0, 1);
+		break;
+	case ERR_NOT_INIT:
+		LOG_ERROR("Driver not initialized");
+		return retVal;
+		break;
+	default:
+		LOG_ERROR("Undefined error");
+		return ERR_UNDEFINED;
+		break;
+	}
+}
+
+csi_lane_state_t csi_lane_module_state(u8 lane)
+{
+    if (lane < csi_core_read_part(N_LANES, 0, 2) + 1) {
+        if (csi_core_read_part(PHY_STATE, lane, 1)) {
+            return CSI_LANE_ULTRA_LOW_POWER;
+        }
+        else if (csi_core_read_part(PHY_STATE, (lane + 4), 1)) {
+            return CSI_LANE_STOP;
+        }
+        return CSI_LANE_ON;
+    } else {
+        LOG_WARNING("Lane switched off");
+        return CSI_LANE_OFF;
+    }
+}
+
+csi_lane_state_t csi_clk_state()
+{
+	if (!csi_core_read_part(PHY_STATE, 9, 1)) {
+		return CSI_LANE_ULTRA_LOW_POWER;
+	} else if (csi_core_read_part(PHY_STATE, 10, 1)) {
+		return CSI_LANE_STOP;
+	} else if (csi_core_read_part(PHY_STATE, 8, 1)) {
+		return CSI_LANE_HIGH_SPEED;
+	}
+
+	return CSI_LANE_ON;
+}
+
+u8 csi_payload_bypass(u8 on)
+{
+	return csi_core_write_part(PHY_STATE, on? 1: 0, 11, 1);
+}
+
+u8 csi_register_line_event(u8 virtual_channel_no, csi_data_type_t data_type, u8 offset)
+{
+	u8 id = 0;
+	csi_registers_t reg_offset = 0;
+	LOG_TRACE();
+	if ((virtual_channel_no > 4) || (offset > 8)) {
+		return ERR_OUT_OF_BOUND;
+	}
+	id = (virtual_channel_no << 6) | data_type;
+
+	reg_offset = ((offset / 4) == 1) ? DATA_IDS_2: DATA_IDS_1;
+
+	return csi_core_write_part(reg_offset, id, (offset * 8), 8);
+}
+u8 csi_unregister_line_event(u8 offset)
+{
+	csi_registers_t reg_offset = 0;
+	LOG_TRACE();
+	if (offset > 8) {
+		return ERR_OUT_OF_BOUND;
+	}
+	reg_offset = ((offset / 4) == 1) ? DATA_IDS_2: DATA_IDS_1;
+	return csi_core_write_part(reg_offset, 0x00, (offset * 8), 8);
+}
+
+u8 csi_get_registered_line_event(u8 offset)
+{
+	csi_registers_t reg_offset = 0;
+	LOG_TRACE();
+	if (offset > 8) {
+		return ERR_OUT_OF_BOUND;
+	}
+	reg_offset = ((offset / 4) == 1) ? DATA_IDS_2: DATA_IDS_1;
+	return (u8)csi_core_read_part(reg_offset, (offset * 8), 8);
+}
+
+u8 csi_event_disable(u32 mask, u8 err_reg_no)
+{
+	switch (err_reg_no) {
+	case 1:
+		return csi_core_write(MASK1, mask | csi_core_read(MASK1));
+	case 2:
+		return csi_core_write(MASK2, mask | csi_core_read(MASK2));
+	default:
+		return ERR_OUT_OF_BOUND;
+	}
+}
+
+u8 csi_event_enable(u32 mask, u8 err_reg_no)
+{
+	switch (err_reg_no) {
+	case 1:
+		return csi_core_write(MASK1, (~mask) & csi_core_read(MASK1));
+	case 2:
+		return csi_core_write(MASK2, (~mask) & csi_core_read(MASK2));
+	default:
+		return ERR_OUT_OF_BOUND;
+	}
+}
+u32 csi_event_get_source(u8 err_reg_no)
+{
+	switch (err_reg_no) {
+	case 1:
+		return csi_core_read(ERR1);
+	case 2:
+		return csi_core_read(ERR2);
+	default:
+		return ERR_OUT_OF_BOUND;
+	}
+}
+
+/*  register methods */
+u32 csi_core_read(csi_registers_t address)
+{
+	return access_read(address>>2);
+}
+
+u8 csi_core_write(csi_registers_t address, u32 data)
+{
+	if (csi_core_initialized == 0) {
+		LOG_ERROR("driver not initialised");
+		return ERR_NOT_INIT;
+	}
+	LOG_DEBUG3("write", data, address>>2);
+	access_write(data, address>>2);
+
+	return SUCCESS;
+}
+
+u8 csi_core_write_part(csi_registers_t address, u32 data, u8 shift, u8 width)
+{
+	u32 mask = (1 << width) - 1;
+	u32 temp = csi_core_read(address);
+	temp &= ~(mask << shift);
+	temp |= (data & mask) << shift;
+	return csi_core_write(address, temp);
+}
+
+u32 csi_core_read_part(csi_registers_t address, u8 shift, u8 width)
+{
+	return (csi_core_read(address) >> shift) & ((1 << width) - 1);
+}
+
diff --git a/drivers/media/sprd_sensor/csi2/csi_driver.h b/drivers/media/sprd_sensor/csi2/csi_driver.h
new file mode 100644
index 00000000..dbe2648a
--- /dev/null
+++ b/drivers/media/sprd_sensor/csi2/csi_driver.h
@@ -0,0 +1,136 @@
+/*
+ * csi_driver
+ * 12/05/2010
+ * Synopsys Inc. PT02
+ */
+
+#ifndef CSI_DRIVER_H_
+#define CSI_DRIVER_H_
+
+#include "csi_types.h"
+
+//#define CURRENT_VERSION 0x3130302A
+#ifdef __SIMULATOR__
+#define CURRENT_VERSION 0
+#else // __SIMULATOR__
+
+#define CURRENT_VERSION 0x3130332A
+
+#endif // __SIMULATOR__
+
+#define PHY_TESTCLR 0
+#define PHY_TESTCLK 1
+#define PHY_TESTDIN 0
+#define PHY_TESTDOUT 8
+#define PHY_TESTEN 16
+
+#define PHY_TESTDIN_W 8
+#define PHY_TESTDOUT_W 8
+
+#define CSI_PCLK_CFG_COUNTER 29
+
+typedef enum
+{
+    VERSION =       0x00,
+    N_LANES =       0x04,
+    PHY_SHUTDOWNZ = 0x08,
+    DPHY_RSTZ =     0x0C,
+    CSI2_RESETN =   0x10,
+    PHY_STATE =     0x14,
+    DATA_IDS_1 =    0x18,
+    DATA_IDS_2 =    0x1C,
+    ERR1 =          0x20,
+    ERR2 =          0x24,
+    MASK1 =         0x28,
+    MASK2 =         0x2C,
+    PHY_TST_CRTL0 = 0x30,
+    PHY_TST_CRTL1 = 0x34
+} csi_registers_t;
+
+typedef enum
+{
+    CSI_LANE_OFF = 0,
+    CSI_LANE_ON,
+    CSI_LANE_ULTRA_LOW_POWER,
+    CSI_LANE_STOP,
+    CSI_LANE_HIGH_SPEED
+} csi_lane_state_t;
+
+typedef enum
+{
+    ERR_NOT_INIT = 0xFE,
+    ERR_ALREADY_INIT = 0xFD,
+    ERR_NOT_COMPATIBLE = 0xFC,
+    ERR_UNDEFINED = 0xFB,
+    ERR_OUT_OF_BOUND = 0xFA,
+    SUCCESS = 0
+} csi_error_t;
+
+typedef enum
+{
+    NULL_PACKET = 0x10,
+    BLANKING_DATA = 0x11,
+    EMBEDDED_8BIT_NON_IMAGE_DATA = 0x12,
+    YUV420_8BIT = 0x18,
+    YUV420_10BIT = 0x19,
+    LEGACY_YUV420_8BIT = 0x1A,
+    YUV420_8BIT_CHROMA_SHIFTED = 0x1C,
+    YUV420_10BIT_CHROMA_SHIFTED = 0x1D,
+    YUV422_8BIT = 0x1E,
+    YUV422_10BIT = 0x1F,
+    RGB444 = 0x20,
+    RGB555 = 0x21,
+    RGB565 = 0x22,
+    RGB666 = 0x23,
+    RGB888 = 0x24,
+    RAW6 = 0x28,
+    RAW7 = 0x29,
+    RAW8 = 0x2A,
+    RAW10 = 0x2B,
+    RAW12 = 0x2C,
+    RAW14 = 0x2D,
+    USER_DEFINED_8BIT_DATA_TYPE_1 = 0x30,
+    USER_DEFINED_8BIT_DATA_TYPE_2 = 0x31,
+    USER_DEFINED_8BIT_DATA_TYPE_3 = 0x32,
+    USER_DEFINED_8BIT_DATA_TYPE_4 = 0x33,
+    USER_DEFINED_8BIT_DATA_TYPE_5 = 0x34,
+    USER_DEFINED_8BIT_DATA_TYPE_6 = 0x35,
+    USER_DEFINED_8BIT_DATA_TYPE_7 = 0x36,
+    USER_DEFINED_8BIT_DATA_TYPE_8 = 0x37
+} csi_data_type_t;
+
+struct csi_pclk_cfg {
+	u32 pclk_start;
+	u32 pclk_end;
+	u8    hsfreqrange;
+	u8    hsrxthssettle;
+};
+
+void dphy_init(u32 bps_per_lane, u32 phy_id);
+u8 csi_init(u64 base_address);
+u8 csi_close(void);
+u8 csi_get_on_lanes(void);
+u8 csi_set_on_lanes(u8 lanes);
+u8 csi_shut_down_phy(u8 shutdown);
+u8 csi_reset_phy(void);
+u8 csi_reset_controller(void);
+csi_lane_state_t csi_lane_module_state(u8 lane);
+csi_lane_state_t csi_clk_state(void);
+u8 csi_payload_bypass(u8 on);
+u8 csi_register_line_event(u8 virtual_channel_no, csi_data_type_t data_type, u8 offset);
+u8 csi_unregister_line_event(u8 offset);
+u8 csi_get_registered_line_event(u8 offset);
+u8 csi_event_disable(u32 mask, u8 err_reg_no);
+u8 csi_event_enable(u32 mask, u8 err_reg_no);
+u32 csi_event_get_source(u8 err_reg_no);
+
+/******************************************************************************
+ * register access methods
+******************************************************************************/
+u32 csi_core_read(csi_registers_t address);
+u8 csi_core_write(csi_registers_t address, u32 data);
+u8 csi_core_write_part(csi_registers_t address, u32 data, u8 shift, u8 width);
+u32 csi_core_read_part(csi_registers_t address, u8 shift, u8 width);
+
+#endif /* CSI_DRIVER_H_ */
+
diff --git a/drivers/media/sprd_sensor/csi2/csi_log.c b/drivers/media/sprd_sensor/csi2/csi_log.c
new file mode 100644
index 00000000..38dd0589
--- /dev/null
+++ b/drivers/media/sprd_sensor/csi2/csi_log.c
@@ -0,0 +1,177 @@
+/*
+ * log.c
+ *
+ *  Created on: Jun 25, 2010
+ *      Author: klabadi & dlopo
+ */
+#include <linux/kernel.h>
+#include "csi_log.h"
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+static log_verbose_t log_verbose = VERBOSE_NOTICE;
+static log_numeric_t log_numeric = NUMERIC_HEX;
+static unsigned log_verbose_write = 0;
+
+void log_set_verbose(log_verbose_t verbose)
+{
+    log_verbose = verbose;
+}
+
+void log_set_numeric(log_numeric_t numeric)
+{
+    log_numeric = numeric;
+}
+
+void log_set_verbose_write(unsigned state)
+{
+    log_verbose_write = state;
+}
+
+void log_print_write(unsigned a, unsigned b)
+{
+    if (log_verbose_write == 1)
+    {
+        if (log_numeric == NUMERIC_DEC)
+        {
+            printk("%d, %d\n", a, b);
+        }
+        else
+        {
+            printk("0x%x, 0x%x\n", a, b);
+        }
+    }
+}
+
+void log_print0(log_verbose_t verbose, const char* function_name)
+{
+    if (verbose == VERBOSE_ERROR)
+    {
+        printk("ERROR: ");
+    }
+    if (verbose == VERBOSE_WARN)
+    {
+        printk("WARNING: ");
+    }
+    if (verbose <= log_verbose)
+    {
+        printk("%s\n", function_name);
+    }
+}
+
+void log_print1(log_verbose_t verbose, const char* function_name, const char* a)
+{
+    if (verbose == VERBOSE_ERROR)
+    {
+        printk("ERROR: ");
+    }
+    if (verbose == VERBOSE_WARN)
+    {
+        printk("WARNING: ");
+    }
+    if (verbose <= log_verbose)
+    {
+        printk("%s: %s\n", function_name, a);
+    }
+}
+
+void log_print2(log_verbose_t verbose, const char* function_name, const char* a,
+        unsigned b)
+{
+    if (verbose == VERBOSE_ERROR)
+    {
+        printk("ERROR: ");
+    }
+    if (verbose == VERBOSE_WARN)
+    {
+        printk("WARNING: ");
+    }
+    if (verbose <= log_verbose)
+    {
+        if (log_numeric == NUMERIC_DEC)
+        {
+            printk("%s: %s, %d\n", function_name, a, b);
+        }
+        else
+        {
+            printk("%s: %s, 0x%x\n", function_name, a, b);
+        }
+    }
+}
+
+void log_print3(log_verbose_t verbose, const char* function_name, const char* a,
+        unsigned b, unsigned c)
+{
+    if (verbose == VERBOSE_ERROR)
+    {
+        printk("ERROR: ");
+    }
+    if (verbose == VERBOSE_WARN)
+    {
+        printk("WARNING: ");
+    }
+    if (verbose <= log_verbose)
+    {
+        if (log_numeric == NUMERIC_DEC)
+        {
+            printk("%s: %s, %d, %d\n", function_name, a, b, c);
+        }
+        else
+        {
+            printk("%s: %s, 0x%x, 0x%x\n", function_name, a, b, c);
+        }
+    }
+}
+
+void log_print_int(log_verbose_t verbose, const char* a, unsigned b)
+{
+    if (verbose <= log_verbose)
+    {
+        if (log_numeric == NUMERIC_DEC)
+        {
+            printk("%s: %d\n", a, b);
+        }
+        else
+        {
+            printk("%s: 0x%x\n", a, b);
+        }
+    }
+}
+
+void log_print_int2(log_verbose_t verbose, const char* a, unsigned b,
+        unsigned c)
+{
+    if (verbose <= log_verbose)
+    {
+        if (log_numeric == NUMERIC_DEC)
+        {
+            printk("%s: %d, %d\n", a, b, c);
+        }
+        else
+        {
+            printk("%s: 0x%x, 0x%x\n", a, b, c);
+        }
+    }
+}
+
+void log_print_int3(log_verbose_t verbose, const char* a, unsigned b,
+        unsigned c, unsigned d)
+{
+    if (verbose <= log_verbose)
+    {
+        if (log_numeric == NUMERIC_DEC)
+        {
+            printk("%s: %d, %d, %d\n", a, b, c, d);
+        }
+        else
+        {
+            printk("%s: 0x%x, 0x%x, 0x%x\n", a, b, c, d);
+        }
+    }
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/drivers/media/sprd_sensor/csi2/csi_log.h b/drivers/media/sprd_sensor/csi2/csi_log.h
new file mode 100644
index 00000000..ff7c073a
--- /dev/null
+++ b/drivers/media/sprd_sensor/csi2/csi_log.h
@@ -0,0 +1,78 @@
+/*
+ * log.h
+ *
+ *  Created on: Jun 25, 2010
+ *      Author: klabadi & dlopo
+ */
+
+#ifndef LOG_H_
+#define LOG_H_
+
+#define __FUNCTION__ (__func__)
+
+typedef enum
+{
+    VERBOSE_ERROR = 0,
+    VERBOSE_WARN,
+    VERBOSE_NOTICE,
+    VERBOSE_DEBUG,
+    VERBOSE_TRACE
+} log_verbose_t;
+
+typedef enum
+{
+    NUMERIC_DEC = 0, NUMERIC_HEX
+} log_numeric_t;
+
+void log_set_verbose(log_verbose_t verbose);
+void log_set_numeric(log_numeric_t numeric);
+void log_set_verbose_write(unsigned state);
+
+void log_print_write(unsigned a, unsigned b);
+
+void log_print0(log_verbose_t verbose, const char* function_name);
+
+void log_print1(log_verbose_t verbose, const char* function_name, const char* a);
+
+void log_print2(log_verbose_t verbose, const char* function_name, const char* a,
+        unsigned b);
+
+void log_print3(log_verbose_t verbose, const char* function_name, const char* a,
+        unsigned b, unsigned c);
+
+void log_print_int(log_verbose_t verbose, const char* a, unsigned b);
+
+void log_print_int2(log_verbose_t verbose, const char* a, unsigned b,
+        unsigned c);
+
+void log_print_int3(log_verbose_t verbose, const char* a, unsigned b,
+        unsigned c, unsigned d);
+
+#define LOG_ASSERT(x, a)        while (!(x)) { LOG_ERROR(a); exit(-1); }
+#define LOG_EXIT(a)             do { LOG_ERROR(a); exit(-1); } while (0)
+#define LOG_WRITE(a, b)         log_print_write((a), (b))
+
+#define LOG_ERROR(a)            log_print1(VERBOSE_ERROR,  __FUNCTION__, (a))
+#define LOG_ERROR2(a, b)        log_print2(VERBOSE_ERROR,  __FUNCTION__, (a), (b))
+#define LOG_ERROR3(a, b, c)     log_print3(VERBOSE_ERROR,  __FUNCTION__, (a), (b), (c))
+#define LOG_WARNING(a)          log_print1(VERBOSE_WARN,   __FUNCTION__, (a))
+#define LOG_WARNING2(a, b)      log_print2(VERBOSE_WARN,   __FUNCTION__, (a), (b))
+#define LOG_WARNING3(a, b, c)   log_print3(VERBOSE_WARN,   __FUNCTION__, (a), (b), (c))
+#define LOG_NOTICE(a)           log_print1(VERBOSE_NOTICE, __FUNCTION__, (a))
+#define LOG_NOTICE2(a, b)       log_print2(VERBOSE_NOTICE, __FUNCTION__, (a), (b))
+#define LOG_NOTICE3(a, b, c)    log_print3(VERBOSE_NOTICE, __FUNCTION__, (a), (b), (c))
+#define LOG_DEBUG(a)            log_print1(VERBOSE_DEBUG,  __FUNCTION__, (a))
+#define LOG_DEBUG2(a, b)        log_print2(VERBOSE_DEBUG,  __FUNCTION__, (a), (b))
+#define LOG_DEBUG3(a, b, c)     log_print3(VERBOSE_DEBUG,  __FUNCTION__, (a), (b), (c))
+#define LOG_TRACE()             log_print0(VERBOSE_TRACE,  __FUNCTION__)
+#define LOG_TRACE1(a)           log_print_int(VERBOSE_TRACE,  __FUNCTION__, (a))
+#define LOG_TRACE2(a, b)        log_print_int2(VERBOSE_TRACE,  __FUNCTION__, (a), (b))
+#define LOG_TRACE3(a, b, c)     log_print3(VERBOSE_TRACE,  __FUNCTION__, (a), (b), (c))
+
+#define LOG_MENU(a)                 log_print0(VERBOSE_NOTICE, (a))
+#define LOG_MENUSTR(a, b)           log_print1(VERBOSE_NOTICE, (a), (b))
+#define LOG_MENUINT(a, b)           log_print_int(VERBOSE_NOTICE, (a),(b))
+#define LOG_MENUINT2(a, b, c)       log_print_int2(VERBOSE_NOTICE, (a),(b), (c))
+#define LOG_MENUINT3(a, b, c, d)    log_print_int3(VERBOSE_NOTICE, (a),(b), (c), (d))
+
+#endif /* LOG_H_ */
diff --git a/drivers/media/sprd_sensor/csi2/csi_system.c b/drivers/media/sprd_sensor/csi2/csi_system.c
new file mode 100644
index 00000000..408983e7
--- /dev/null
+++ b/drivers/media/sprd_sensor/csi2/csi_system.c
@@ -0,0 +1,84 @@
+/*
+ * system.c
+ *
+ *  Created on: Jun 25, 2010
+ *      Author: klabadi & dlopo
+ *
+ *
+ *  @note: this file should be re-written to match the environment the
+ *  API is running on
+ */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+#include "csi_system.h"
+#include "csi_log.h"
+
+void system_sleep_ms(unsigned ms)
+{
+
+}
+
+int system_thread_create(void* handle, thread_t p_func, void* param)
+{
+    return 0;
+}
+int system_thread_destruct(void* handle)
+{
+    return 0;
+}
+
+int system_start(thread_t thread)
+{
+    return 1;
+}
+
+static unsigned system_interrupt_map(interrupt_id_t id)
+{
+    return ~0;
+}
+
+int system_interrupt_disable(interrupt_id_t id)
+{
+    if (system_interrupt_map(id) != (unsigned) (~0))
+    {
+        return 0;
+    }
+    LOG_ERROR("Interrupt not mapped");
+    return 0;
+}
+
+int system_interrupt_enable(interrupt_id_t id)
+{
+    if (system_interrupt_map(id) != (unsigned) (~0))
+    {
+        return 0;
+    }
+    LOG_ERROR("Interrupt not mapped");
+    return 0;
+}
+
+int system_interrupt_acknowledge(interrupt_id_t id)
+{
+    if (system_interrupt_map(id) != (unsigned) (~0))
+    {
+        return 0;
+    }
+    LOG_ERROR("Interrupt not mapped");
+    return 0;
+}
+int system_interrupt_handler_register(interrupt_id_t id, handler_t handler,
+        void * param)
+{
+    return 0;
+}
+
+int system_interrupt_handler_unregister(interrupt_id_t id)
+{
+    return 0;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/drivers/media/sprd_sensor/csi2/csi_system.h b/drivers/media/sprd_sensor/csi2/csi_system.h
new file mode 100644
index 00000000..21f19886
--- /dev/null
+++ b/drivers/media/sprd_sensor/csi2/csi_system.h
@@ -0,0 +1,28 @@
+/*
+ * system.h
+ *
+ *  Created on: Jun 25, 2010
+ *      Author: klabadi & dlopo
+ */
+
+#ifndef SYSTEM_H_
+#define SYSTEM_H_
+
+#include "csi_types.h"
+
+typedef enum
+{
+    CSI_INT_ERR1 = 1, CSI_INT_ERR2
+} interrupt_id_t;
+void system_sleep_ms(unsigned ms);
+int system_thread_create(void* handle, thread_t p_func, void* param);
+int system_thread_destruct(void* handle);
+int system_start(thread_t thread);
+int system_interrupt_disable(interrupt_id_t id);
+int system_interrupt_enable(interrupt_id_t id);
+int system_interrupt_acknowledge(interrupt_id_t id);
+int system_interrupt_handler_register(interrupt_id_t id, handler_t handler, void * param);
+int system_interrupt_handler_unregister(interrupt_id_t id);
+
+
+#endif /* SYSTEM_H_ */
\ No newline at end of file
diff --git a/drivers/media/sprd_sensor/csi2/csi_types.h b/drivers/media/sprd_sensor/csi2/csi_types.h
new file mode 100644
index 00000000..d7c9031d
--- /dev/null
+++ b/drivers/media/sprd_sensor/csi2/csi_types.h
@@ -0,0 +1,15 @@
+/*
+ * types.h
+ *
+ * Created on: Aug 25, 2010
+ * Author: klabadi & dlopo
+ */
+
+#ifndef TYPES_H_
+#define TYPES_H_
+#include <linux/types.h>
+
+typedef void (*handler_t)(void *);
+typedef void* (*thread_t)(void *);
+
+#endif /* TYPES_H_ */
\ No newline at end of file
diff --git a/drivers/media/sprd_sensor/csi2/usc28c_init.c b/drivers/media/sprd_sensor/csi2/usc28c_init.c
new file mode 100644
index 00000000..c0e2071a
--- /dev/null
+++ b/drivers/media/sprd_sensor/csi2/usc28c_init.c
@@ -0,0 +1,281 @@
+
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+#ifndef CONFIG_64BIT
+#include <soc/sprd/hardware.h>
+#else
+#include "parse_hwinfo.h"
+#endif
+
+#define CTL_BASE_ENABLE_USC28C_CSI     0x403f0008
+
+#define pr_info                        printk
+
+#define ARM_GPIO_BASE_CNT              (192)
+
+#define SPI_USC28C_SCK_GPIO_PIN        (200)
+#define SPI_USC28C_SEN_GPIO_PIN        (201)
+#define SPI_USC28C_DAT_GPIO_PIN        (202)
+
+#define SPI_USC28C_SCK_GPIO_MASK       (1<<(SPI_USC28C_SCK_GPIO_PIN-ARM_GPIO_BASE_CNT))
+#define SPI_USC28C_SEN_GPIO_MASK       (1<<(SPI_USC28C_SEN_GPIO_PIN-ARM_GPIO_BASE_CNT))
+#define SPI_USC28C_DAT_GPIO_MASK       (1<<(SPI_USC28C_DAT_GPIO_PIN-ARM_GPIO_BASE_CNT))
+#define SPI_CLK_DELAY                  0
+#define SPI_READ_REG                   0x3F
+
+#define GPIO_CHIP_USC28C_OFFSET        (SPRD_GPIO_BASE + 0x600)
+
+#if 0
+struct gpio_ctrl_reg {
+	volatile u32 data; /* bits data */
+	volatile u32 msk; /* bits data mask */
+	volatile u32 dir; /* bits data direction */
+	volatile u32 is; /* bits interrupt sense */
+	volatile u32 ibe; /* bits both edges interrupt */
+	volatile u32 iev; /* bits interrupt event */
+	volatile u32 ie; /* bits interrupt enable */
+	volatile u32 ris; /* bits raw interrupt status */
+	volatile u32 mis; /* bits masked interrupt status */
+	volatile u32 inen; /* input enable */
+};
+#endif
+
+static void gpio_set_dir(u8 port, u8 dir)
+{
+#if 0
+	volatile struct gpio_ctrl_reg *reg;
+
+	reg = (volatile struct gpio_ctrl_reg *)(GPIO_CHIP_USC28C_OFFSET);
+	if (dir) {
+		reg->dir |= 1 << ((u32) (port - ARM_GPIO_BASE_CNT)); // OUTPUT MODE.
+	} else {
+		reg->dir &= ~((u32)(1 << ((u32) (port - ARM_GPIO_BASE_CNT)))); // INPUT MODE.
+	}
+	reg->msk |= (1 << (u32)(port - ARM_GPIO_BASE_CNT)); // OUTPUT MODE.
+#else
+	u32 value;
+
+	if (dir) {
+		value = 1 << ((u32) (port - ARM_GPIO_BASE_CNT));
+		value |= __raw_readl(GPIO_CHIP_USC28C_OFFSET + 0x08);
+	} else {
+		value = ~((u32)(1 << ((u32) (port - ARM_GPIO_BASE_CNT))));
+		value &= __raw_readl(GPIO_CHIP_USC28C_OFFSET + 0x08);
+	}
+	__raw_writel(value, GPIO_CHIP_USC28C_OFFSET + 0x08);
+
+	value = (1 << (u32)(port - ARM_GPIO_BASE_CNT));
+	value |= __raw_readl(GPIO_CHIP_USC28C_OFFSET + 0x04);
+	__raw_writel(value, GPIO_CHIP_USC28C_OFFSET + 0x04);
+#endif
+}
+
+static void gpio_out(u8 port, u8 data)
+{
+#if 0
+	volatile struct gpio_ctrl_reg *reg;
+
+	reg = (volatile struct gpio_ctrl_reg *)(GPIO_CHIP_USC28C_OFFSET);
+	if (data) {
+		reg->data |= (1 << (u32)(port - ARM_GPIO_BASE_CNT)); // set 1.
+	} else {
+		reg->data &= ~(1 << (u32)(port - ARM_GPIO_BASE_CNT)); // set 0.
+	}
+#else
+	u32 value;
+
+	if (data) {
+		value = (1 << (u32)(port - ARM_GPIO_BASE_CNT));
+		value |= __raw_readl(GPIO_CHIP_USC28C_OFFSET);
+	} else {
+		value = ~(1 << (u32)(port - ARM_GPIO_BASE_CNT));
+		value &= __raw_readl(GPIO_CHIP_USC28C_OFFSET);
+	}
+	__raw_writel(value, GPIO_CHIP_USC28C_OFFSET);
+#endif
+}
+
+static void gpio_out_combo(u32 sclk, u32 sen, u32 dat)
+{
+#if 0
+	volatile struct gpio_ctrl_reg *reg;
+	u32 read_dat;
+	u32 reg_set = 0;
+
+	reg = (volatile struct gpio_ctrl_reg *)(GPIO_CHIP_USC28C_OFFSET);
+
+	if (sclk) {
+		reg_set |= SPI_USC28C_SCK_GPIO_MASK;
+	}
+	if (sen) {
+		reg_set |= SPI_USC28C_SEN_GPIO_MASK;
+	}
+	if (dat) {
+		reg_set |= SPI_USC28C_DAT_GPIO_MASK;
+	}
+	read_dat = reg->data;
+	read_dat &= ~(SPI_USC28C_SCK_GPIO_MASK | SPI_USC28C_SEN_GPIO_MASK
+			| SPI_USC28C_DAT_GPIO_MASK);
+	read_dat |= reg_set;
+	reg->data = read_dat;
+#else
+	u32 value;
+	u32 reg_set = 0;
+
+	if (sclk) {
+		reg_set |= SPI_USC28C_SCK_GPIO_MASK;
+	}
+	if (sen) {
+		reg_set |= SPI_USC28C_SEN_GPIO_MASK;
+	}
+	if (dat) {
+		reg_set |= SPI_USC28C_DAT_GPIO_MASK;
+	}
+
+	value = __raw_readl(GPIO_CHIP_USC28C_OFFSET);
+	value &= ~(SPI_USC28C_SCK_GPIO_MASK | SPI_USC28C_SEN_GPIO_MASK
+			| SPI_USC28C_DAT_GPIO_MASK);
+	value |= reg_set;
+	__raw_writel(value, GPIO_CHIP_USC28C_OFFSET);
+#endif
+}
+
+static u8 gpio_in(u8 port)
+{
+#if 0
+	volatile struct gpio_ctrl_reg *reg;
+	u32 data;
+
+	reg = (volatile struct gpio_ctrl_reg *)(GPIO_CHIP_USC28C_OFFSET);
+
+	data = reg->data;
+	if (data & (1 << (port - ARM_GPIO_BASE_CNT))) {
+		return 1;
+	}
+	return 0;
+#else
+	u32 value;
+
+	value = __raw_readl(GPIO_CHIP_USC28C_OFFSET);
+	if (value & (1 << (port - ARM_GPIO_BASE_CNT))) {
+		return 1;
+	}
+	return 0;
+#endif
+}
+
+static void __usc28c_spi_init(void)
+{
+	gpio_set_dir(SPI_USC28C_SCK_GPIO_PIN, 1);
+	gpio_set_dir(SPI_USC28C_SEN_GPIO_PIN, 1);
+	gpio_set_dir(SPI_USC28C_DAT_GPIO_PIN, 1);
+
+	gpio_out(SPI_USC28C_SCK_GPIO_PIN, 0);
+	gpio_out(SPI_USC28C_SEN_GPIO_PIN, 1);
+	gpio_out(SPI_USC28C_DAT_GPIO_PIN, 0);
+}
+
+static void __spi_reg_w(u16 reg, u16 val)
+{
+	s8 i;
+	u8 temp = 0;
+
+	gpio_set_dir(SPI_USC28C_SCK_GPIO_PIN, 1);
+	gpio_set_dir(SPI_USC28C_SEN_GPIO_PIN, 1);
+	gpio_set_dir(SPI_USC28C_DAT_GPIO_PIN, 1);
+
+	gpio_out_combo(0, 1, 0);
+	udelay(SPI_CLK_DELAY);
+	if (val & (1 << 15)) {
+		gpio_out_combo(0, 0, 1);
+	} else {
+		gpio_out_combo(0, 0, 0);
+	}
+	udelay(SPI_CLK_DELAY);
+	gpio_out(SPI_USC28C_SCK_GPIO_PIN, 1);
+	udelay(SPI_CLK_DELAY);
+
+	for (i = 14; i >= 0; i--) {
+		gpio_out_combo(0, 0, val & (1 << i));
+		udelay(SPI_CLK_DELAY);
+		gpio_out(SPI_USC28C_SCK_GPIO_PIN, 1);
+		udelay(SPI_CLK_DELAY);
+	}
+
+	for (i = 1; i >= 0; i--) {
+		gpio_out_combo(0, 0, temp & (1 << i));
+		udelay(SPI_CLK_DELAY);
+		gpio_out(SPI_USC28C_SCK_GPIO_PIN, 1);
+		udelay(SPI_CLK_DELAY);
+	}
+
+	for (i = 15; i >= 0; i--) {
+		gpio_out_combo(0, 0, reg & (1 << i));
+		udelay(SPI_CLK_DELAY);
+		gpio_out(SPI_USC28C_SCK_GPIO_PIN, 1);
+		udelay(SPI_CLK_DELAY);
+	}
+	udelay(SPI_CLK_DELAY);
+	gpio_out_combo(0, 1, 1);
+}
+
+static u16 __spi_reg_r(u16 reg)
+{
+	s8 i;
+	u16 recv = 0;
+
+	__spi_reg_w(SPI_READ_REG, reg);
+	gpio_set_dir(SPI_USC28C_DAT_GPIO_PIN, 0);
+
+	gpio_out(SPI_USC28C_SCK_GPIO_PIN, 1);
+	udelay(SPI_CLK_DELAY);
+	gpio_out(SPI_USC28C_SCK_GPIO_PIN, 0);
+
+	for (i = 15; i >= 0; i--) {
+		udelay(SPI_CLK_DELAY);
+		gpio_out(SPI_USC28C_SCK_GPIO_PIN, 1);
+		recv <<= 1;
+		udelay(SPI_CLK_DELAY);
+		recv |= gpio_in(SPI_USC28C_DAT_GPIO_PIN);
+		gpio_out(SPI_USC28C_SCK_GPIO_PIN, 0);
+	}
+
+	return recv;
+}
+
+void usc28c_csi_init(void)
+{
+	static u32 initialized = 0;
+	u32 base_addr;
+
+	if (initialized) {
+		/* already initialized */
+		return;
+	}
+
+	base_addr = ioremap(CTL_BASE_ENABLE_USC28C_CSI, 0x10);
+	pr_info("%s: usc28c base addr: 0x%x\n", __func__, base_addr);
+	__raw_writel(0x1000, base_addr);
+
+	__usc28c_spi_init();
+
+	/* reg 0x00:
+	    bit0: DSI power switch (normal function set 1)
+	    bit1: CSI power switch for V1 (normal function set 1)
+	    bit2: CSI power switch for V2 (normal function set 1)
+	    bit3: CSI select signal (0 for V1, 1 for V2)
+
+	    reg 0x10:
+	    0x02 for DSI mode, 0x03 for CSI mode
+	*/
+	__spi_reg_w(0x00, 0x0f);
+	__spi_reg_w(0x10, 0x03);
+	pr_info("%s: chip usc28c csi mode is chosen\n", __func__);
+
+	pr_info("Reg0x%04x, value: 0x%04x and Reg0x%04x, value: 0x%04x\n",
+			0x0, __spi_reg_r(0x0), 0x10, __spi_reg_r(0x10));
+
+	initialized = 1;
+}
+