Initial file dump from open source releaseHEADmaster

1 files changed, 139 insertions, 0 deletions

diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
new file mode 100644
index 00000000..92af8386
--- /dev/null
+++ b/drivers/devfreq/Kconfig
@@ -0,0 +1,139 @@
+menuconfig PM_DEVFREQ
+	bool "Generic Dynamic Voltage and Frequency Scaling (DVFS) support"
+	help
+	  A device may have a list of frequencies and voltages available.
+	  devfreq, a generic DVFS framework can be registered for a device
+	  in order to let the governor provided to devfreq choose an
+	  operating frequency based on the device driver's policy.
+
+	  Each device may have its own governor and policy. Devfreq can
+	  reevaluate the device state periodically and/or based on the
+	  notification to "nb", a notifier block, of devfreq.
+
+	  Like some CPUs with CPUfreq, a device may have multiple clocks.
+	  However, because the clock frequencies of a single device are
+	  determined by the single device's state, an instance of devfreq
+	  is attached to a single device and returns a "representative"
+	  clock frequency of the device, which is also attached
+	  to a device by 1-to-1. The device registering devfreq takes the
+	  responsibility to "interpret" the representative frequency and
+	  to set its every clock accordingly with the "target" callback
+	  given to devfreq.
+
+	  When OPP is used with the devfreq device, it is recommended to
+	  register devfreq's nb to the OPP's notifier head.  If OPP is
+	  used with the devfreq device, you may use OPP helper
+	  functions defined in devfreq.h.
+
+if PM_DEVFREQ
+
+comment "DEVFREQ Governors"
+
+config DEVFREQ_GOV_SIMPLE_ONDEMAND
+	tristate "Simple Ondemand"
+	help
+	  Chooses frequency based on the recent load on the device. Works
+	  similar as ONDEMAND governor of CPUFREQ does. A device with
+	  Simple-Ondemand should be able to provide busy/total counter
+	  values that imply the usage rate. A device may provide tuned
+	  values to the governor with data field at devfreq_add_device().
+
+config DEVFREQ_GOV_PERFORMANCE
+	tristate "Performance"
+	help
+	  Sets the frequency at the maximum available frequency.
+	  This governor always returns UINT_MAX as frequency so that
+	  the DEVFREQ framework returns the highest frequency available
+	  at any time.
+
+config DEVFREQ_GOV_POWERSAVE
+	tristate "Powersave"
+	help
+	  Sets the frequency at the minimum available frequency.
+	  This governor always returns 0 as frequency so that
+	  the DEVFREQ framework returns the lowest frequency available
+	  at any time.
+
+config DEVFREQ_GOV_USERSPACE
+	tristate "Userspace"
+	help
+	  Sets the frequency at the user specified one.
+	  This governor returns the user configured frequency if there
+	  has been an input to /sys/devices/.../power/devfreq_set_freq.
+	  Otherwise, the governor does not change the frequnecy
+	  given at the initialization.
+
+config DEVFREQ_GOV_ONDEMAND
+	tristate "Ondemand"
+	help
+	  Chooses frequency based on the recent load on the device. Works
+	  similar as ONDEMAND governor of CPUFREQ does. A device with
+	  Simple-Ondemand should be able to provide busy/total counter
+	  values that imply the usage rate.
+	  Requests from user space and devices drivers can also tune frequency
+comment "DEVFREQ Drivers"
+
+config ARM_EXYNOS4_BUS_DEVFREQ
+	bool "ARM Exynos4210/4212/4412 Memory Bus DEVFREQ Driver"
+	depends on CPU_EXYNOS4210 || CPU_EXYNOS4212 || CPU_EXYNOS4412
+	select ARCH_HAS_OPP
+	select DEVFREQ_GOV_SIMPLE_ONDEMAND
+	help
+	  This adds the DEVFREQ driver for Exynos4210 memory bus (vdd_int)
+	  and Exynos4212/4412 memory interface and bus (vdd_mif + vdd_int).
+	  It reads PPMU counters of memory controllers and adjusts
+	  the operating frequencies and voltages with OPP support.
+	  To operate with optimal voltages, ASV support is required
+	  (CONFIG_EXYNOS_ASV).
+
+config SPRD_SCX35_DMC_FREQ
+	bool "Spreadtrum scx35 Memory Bus DMCFREQ Driver"
+	depends on ARCH_SCX35
+	select ARCH_HAS_OPP
+	select DEVFREQ_GOV_ONDEMAND
+	help
+	  This adds the DMCFREQ driver for Spreadtrum scx35 memory bus (vdd_core)
+	  It reads PPMU counters of memory controllers and adjusts
+	  the operating frequencies with OPP support.
+
+config SCX35_DMC_FREQ_AP
+       bool "Spreadtrum scx35 DDR DFS in AP side"
+       depends on ARCH_SCX35
+       help
+         This adds the DMCFREQ drive, DDR DFS run in AP side
+
+config SCX35_DMC_FREQ_CP0
+	bool "Spreadtrum scx35 DDR DFS in cp0 side"
+	depends on ARCH_SCX35
+	help
+          This adds the DMCFREQ drive, DDR DFS run in cp0.
+	  please make sure the cp0 is free.
+
+config SCX35_DMC_FREQ_CP1
+	bool "Spreadtrum scx35 DDR DFS in cp1 side"
+	depends on ARCH_SCX35
+	help
+          This adds the DMCFREQ drive, DDR DFS run in cp1.
+	  please make sure the cp1 is free.
+
+config SCX35_DMC_FREQ_CP2
+	bool "Spreadtrum scx35 DDR DFS in cp2 side"
+	depends on ARCH_SCX35
+	help
+          This adds the DMCFREQ drive, DDR DFS run in cp2.
+	  please make sure the cp2 is free.
+
+config SCX35_DMC_FREQ_DDR3
+	bool "Spreadtrum scx35 DDR DFS for ddr3 side"
+	depends on ARCH_SCX35
+	help
+          This adds the DMCFREQ drive, DDR DFS run for ddr3.
+	  please make sure the cp1 is free.
+
+config SPRD_SCX35_DMC_FREQ_DEBUG
+	bool "Spreadtrum scx35 Memory Bus DMCFREQ Driver debug"
+	depends on SPRD_SCX35_DMC_FREQ
+	help
+	  DMCFREQ driver for Spreadtrum scx35 memory bus debug.
+
+endif # PM_DEVFREQ