diff options
| author | Yuval Adam <yuv.adm@gmail.com> | 2012-10-29 21:36:23 +0200 |
|---|---|---|
| committer | Yuval Adam <yuv.adm@gmail.com> | 2012-10-29 21:36:23 +0200 |
| commit | 44b979ac3dc53b29ee8176517b7d9a10935630c0 (patch) | |
| tree | 03c256e5e19ac2be9d19b3d4638cdf233b0ee4e9 /inc | |
| parent | 8ced6b65a22e0c392bc31288b2eb3f713a0fc477 (diff) | |
Initial code
Diffstat (limited to 'inc')
| -rw-r--r-- | inc/asmdefs.h | 227 | ||||
| -rw-r--r-- | inc/hw_adc.h | 1352 | ||||
| -rw-r--r-- | inc/hw_can.h | 771 | ||||
| -rw-r--r-- | inc/hw_comp.h | 305 | ||||
| -rw-r--r-- | inc/hw_eeprom.h | 245 | ||||
| -rw-r--r-- | inc/hw_epi.h | 547 | ||||
| -rw-r--r-- | inc/hw_ethernet.h | 703 | ||||
| -rw-r--r-- | inc/hw_fan.h | 688 | ||||
| -rw-r--r-- | inc/hw_flash.h | 474 | ||||
| -rw-r--r-- | inc/hw_gpio.h | 192 | ||||
| -rw-r--r-- | inc/hw_hibernate.h | 286 | ||||
| -rw-r--r-- | inc/hw_i2c.h | 489 | ||||
| -rw-r--r-- | inc/hw_i2s.h | 239 | ||||
| -rw-r--r-- | inc/hw_ints.h | 217 | ||||
| -rw-r--r-- | inc/hw_lpc.h | 909 | ||||
| -rw-r--r-- | inc/hw_memmap.h | 167 | ||||
| -rw-r--r-- | inc/hw_nvic.h | 1717 | ||||
| -rw-r--r-- | inc/hw_peci.h | 376 | ||||
| -rw-r--r-- | inc/hw_pwm.h | 2020 | ||||
| -rw-r--r-- | inc/hw_qei.h | 216 | ||||
| -rw-r--r-- | inc/hw_ssi.h | 244 | ||||
| -rw-r--r-- | inc/hw_sysctl.h | 3676 | ||||
| -rw-r--r-- | inc/hw_sysexc.h | 132 | ||||
| -rw-r--r-- | inc/hw_timer.h | 759 | ||||
| -rw-r--r-- | inc/hw_types.h | 218 | ||||
| -rw-r--r-- | inc/hw_uart.h | 522 | ||||
| -rw-r--r-- | inc/hw_udma.h | 446 | ||||
| -rw-r--r-- | inc/hw_usb.h | 4611 | ||||
| -rw-r--r-- | inc/hw_watchdog.h | 191 | ||||
| -rw-r--r-- | inc/inc.sgxx | bin | 0 -> 1534 bytes | |||
| -rw-r--r-- | inc/lm4f120h5qr.h | 10025 |
31 files changed, 32964 insertions, 0 deletions
diff --git a/inc/asmdefs.h b/inc/asmdefs.h new file mode 100644 index 0000000..d958ab1 --- /dev/null +++ b/inc/asmdefs.h @@ -0,0 +1,227 @@ +//*****************************************************************************
+//
+// asmdefs.h - Macros to allow assembly code be portable among toolchains.
+//
+// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 9453 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __ASMDEFS_H__
+#define __ASMDEFS_H__
+
+//*****************************************************************************
+//
+// The defines required for code_red.
+//
+//*****************************************************************************
+#ifdef codered
+
+//
+// The assembly code preamble required to put the assembler into the correct
+// configuration.
+//
+ .syntax unified
+ .thumb
+
+//
+// Section headers.
+//
+#define __LIBRARY__ @
+#define __TEXT__ .text
+#define __DATA__ .data
+#define __BSS__ .bss
+#define __TEXT_NOROOT__ .text
+
+//
+// Assembler nmenonics.
+//
+#define __ALIGN__ .balign 4
+#define __END__ .end
+#define __EXPORT__ .globl
+#define __IMPORT__ .extern
+#define __LABEL__ :
+#define __STR__ .ascii
+#define __THUMB_LABEL__ .thumb_func
+#define __WORD__ .word
+#define __INLINE_DATA__
+
+#endif // codered
+
+//*****************************************************************************
+//
+// The defines required for EW-ARM.
+//
+//*****************************************************************************
+#ifdef ewarm
+
+//
+// Section headers.
+//
+#define __LIBRARY__ module
+#define __TEXT__ rseg CODE:CODE(2)
+#define __DATA__ rseg DATA:DATA(2)
+#define __BSS__ rseg DATA:DATA(2)
+#define __TEXT_NOROOT__ rseg CODE:CODE:NOROOT(2)
+
+//
+// Assembler nmenonics.
+//
+#define __ALIGN__ alignrom 2
+#define __END__ end
+#define __EXPORT__ export
+#define __IMPORT__ import
+#define __LABEL__
+#define __STR__ dcb
+#define __THUMB_LABEL__ thumb
+#define __WORD__ dcd
+#define __INLINE_DATA__ data
+
+#endif // ewarm
+
+//*****************************************************************************
+//
+// The defines required for GCC.
+//
+//*****************************************************************************
+#if defined(gcc)
+
+//
+// The assembly code preamble required to put the assembler into the correct
+// configuration.
+//
+ .syntax unified
+ .thumb
+
+//
+// Section headers.
+//
+#define __LIBRARY__ @
+#define __TEXT__ .text
+#define __DATA__ .data
+#define __BSS__ .bss
+#define __TEXT_NOROOT__ .text
+
+//
+// Assembler nmenonics.
+//
+#define __ALIGN__ .balign 4
+#define __END__ .end
+#define __EXPORT__ .globl
+#define __IMPORT__ .extern
+#define __LABEL__ :
+#define __STR__ .ascii
+#define __THUMB_LABEL__ .thumb_func
+#define __WORD__ .word
+#define __INLINE_DATA__
+
+#endif // gcc
+
+//*****************************************************************************
+//
+// The defines required for RV-MDK.
+//
+//*****************************************************************************
+#ifdef rvmdk
+
+//
+// The assembly code preamble required to put the assembler into the correct
+// configuration.
+//
+ thumb
+ require8
+ preserve8
+
+//
+// Section headers.
+//
+#define __LIBRARY__ ;
+#define __TEXT__ area ||.text||, code, readonly, align=2
+#define __DATA__ area ||.data||, data, align=2
+#define __BSS__ area ||.bss||, noinit, align=2
+#define __TEXT_NOROOT__ area ||.text||, code, readonly, align=2
+
+//
+// Assembler nmenonics.
+//
+#define __ALIGN__ align 4
+#define __END__ end
+#define __EXPORT__ export
+#define __IMPORT__ import
+#define __LABEL__
+#define __STR__ dcb
+#define __THUMB_LABEL__
+#define __WORD__ dcd
+#define __INLINE_DATA__
+
+#endif // rvmdk
+
+//*****************************************************************************
+//
+// The defines required for Sourcery G++.
+//
+//*****************************************************************************
+#if defined(sourcerygxx)
+
+//
+// The assembly code preamble required to put the assembler into the correct
+// configuration.
+//
+ .syntax unified
+ .thumb
+
+//
+// Section headers.
+//
+#define __LIBRARY__ @
+#define __TEXT__ .text
+#define __DATA__ .data
+#define __BSS__ .bss
+#define __TEXT_NOROOT__ .text
+
+//
+// Assembler nmenonics.
+//
+#define __ALIGN__ .balign 4
+#define __END__ .end
+#define __EXPORT__ .globl
+#define __IMPORT__ .extern
+#define __LABEL__ :
+#define __STR__ .ascii
+#define __THUMB_LABEL__ .thumb_func
+#define __WORD__ .word
+#define __INLINE_DATA__
+
+#endif // sourcerygxx
+
+#endif // __ASMDEF_H__
diff --git a/inc/hw_adc.h b/inc/hw_adc.h new file mode 100644 index 0000000..2c9218d --- /dev/null +++ b/inc/hw_adc.h @@ -0,0 +1,1352 @@ +//*****************************************************************************
+//
+// hw_adc.h - Macros used when accessing the ADC hardware.
+//
+// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 9453 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_ADC_H__
+#define __HW_ADC_H__
+
+//*****************************************************************************
+//
+// The following are defines for the ADC register offsets.
+//
+//*****************************************************************************
+#define ADC_O_ACTSS 0x00000000 // ADC Active Sample Sequencer
+#define ADC_O_RIS 0x00000004 // ADC Raw Interrupt Status
+#define ADC_O_IM 0x00000008 // ADC Interrupt Mask
+#define ADC_O_ISC 0x0000000C // ADC Interrupt Status and Clear
+#define ADC_O_OSTAT 0x00000010 // ADC Overflow Status
+#define ADC_O_EMUX 0x00000014 // ADC Event Multiplexer Select
+#define ADC_O_USTAT 0x00000018 // ADC Underflow Status
+#define ADC_O_TSSEL 0x0000001C // ADC Trigger Source Select
+#define ADC_O_SSPRI 0x00000020 // ADC Sample Sequencer Priority
+#define ADC_O_SPC 0x00000024 // ADC Sample Phase Control
+#define ADC_O_PSSI 0x00000028 // ADC Processor Sample Sequence
+ // Initiate
+#define ADC_O_SAC 0x00000030 // ADC Sample Averaging Control
+#define ADC_O_DCISC 0x00000034 // ADC Digital Comparator Interrupt
+ // Status and Clear
+#define ADC_O_CTL 0x00000038 // ADC Control
+#define ADC_O_SSMUX0 0x00000040 // ADC Sample Sequence Input
+ // Multiplexer Select 0
+#define ADC_O_SSCTL0 0x00000044 // ADC Sample Sequence Control 0
+#define ADC_O_SSFIFO0 0x00000048 // ADC Sample Sequence Result FIFO
+ // 0
+#define ADC_O_SSFSTAT0 0x0000004C // ADC Sample Sequence FIFO 0
+ // Status
+#define ADC_O_SSOP0 0x00000050 // ADC Sample Sequence 0 Operation
+#define ADC_O_SSDC0 0x00000054 // ADC Sample Sequence 0 Digital
+ // Comparator Select
+#define ADC_O_SSEMUX0 0x00000058 // ADC Sample Sequence Extended
+ // Input Multiplexer Select 0
+#define ADC_O_SSMUX1 0x00000060 // ADC Sample Sequence Input
+ // Multiplexer Select 1
+#define ADC_O_SSCTL1 0x00000064 // ADC Sample Sequence Control 1
+#define ADC_O_SSFIFO1 0x00000068 // ADC Sample Sequence Result FIFO
+ // 1
+#define ADC_O_SSFSTAT1 0x0000006C // ADC Sample Sequence FIFO 1
+ // Status
+#define ADC_O_SSOP1 0x00000070 // ADC Sample Sequence 1 Operation
+#define ADC_O_SSDC1 0x00000074 // ADC Sample Sequence 1 Digital
+ // Comparator Select
+#define ADC_O_SSEMUX1 0x00000078 // ADC Sample Sequence Extended
+ // Input Multiplexer Select 1
+#define ADC_O_SSMUX2 0x00000080 // ADC Sample Sequence Input
+ // Multiplexer Select 2
+#define ADC_O_SSCTL2 0x00000084 // ADC Sample Sequence Control 2
+#define ADC_O_SSFIFO2 0x00000088 // ADC Sample Sequence Result FIFO
+ // 2
+#define ADC_O_SSFSTAT2 0x0000008C // ADC Sample Sequence FIFO 2
+ // Status
+#define ADC_O_SSOP2 0x00000090 // ADC Sample Sequence 2 Operation
+#define ADC_O_SSDC2 0x00000094 // ADC Sample Sequence 2 Digital
+ // Comparator Select
+#define ADC_O_SSEMUX2 0x00000098 // ADC Sample Sequence Extended
+ // Input Multiplexer Select 2
+#define ADC_O_SSMUX3 0x000000A0 // ADC Sample Sequence Input
+ // Multiplexer Select 3
+#define ADC_O_SSCTL3 0x000000A4 // ADC Sample Sequence Control 3
+#define ADC_O_SSFIFO3 0x000000A8 // ADC Sample Sequence Result FIFO
+ // 3
+#define ADC_O_SSFSTAT3 0x000000AC // ADC Sample Sequence FIFO 3
+ // Status
+#define ADC_O_SSOP3 0x000000B0 // ADC Sample Sequence 3 Operation
+#define ADC_O_SSDC3 0x000000B4 // ADC Sample Sequence 3 Digital
+ // Comparator Select
+#define ADC_O_SSEMUX3 0x000000B8 // ADC Sample Sequence Extended
+ // Input Multiplexer Select 3
+#define ADC_O_TMLB 0x00000100 // ADC Test Mode Loopback
+#define ADC_O_DCRIC 0x00000D00 // ADC Digital Comparator Reset
+ // Initial Conditions
+#define ADC_O_DCCTL0 0x00000E00 // ADC Digital Comparator Control 0
+#define ADC_O_DCCTL1 0x00000E04 // ADC Digital Comparator Control 1
+#define ADC_O_DCCTL2 0x00000E08 // ADC Digital Comparator Control 2
+#define ADC_O_DCCTL3 0x00000E0C // ADC Digital Comparator Control 3
+#define ADC_O_DCCTL4 0x00000E10 // ADC Digital Comparator Control 4
+#define ADC_O_DCCTL5 0x00000E14 // ADC Digital Comparator Control 5
+#define ADC_O_DCCTL6 0x00000E18 // ADC Digital Comparator Control 6
+#define ADC_O_DCCTL7 0x00000E1C // ADC Digital Comparator Control 7
+#define ADC_O_DCCMP0 0x00000E40 // ADC Digital Comparator Range 0
+#define ADC_O_DCCMP1 0x00000E44 // ADC Digital Comparator Range 1
+#define ADC_O_DCCMP2 0x00000E48 // ADC Digital Comparator Range 2
+#define ADC_O_DCCMP3 0x00000E4C // ADC Digital Comparator Range 3
+#define ADC_O_DCCMP4 0x00000E50 // ADC Digital Comparator Range 4
+#define ADC_O_DCCMP5 0x00000E54 // ADC Digital Comparator Range 5
+#define ADC_O_DCCMP6 0x00000E58 // ADC Digital Comparator Range 6
+#define ADC_O_DCCMP7 0x00000E5C // ADC Digital Comparator Range 7
+#define ADC_O_PP 0x00000FC0 // ADC Peripheral Properties
+#define ADC_O_PC 0x00000FC4 // ADC Peripheral Configuration
+#define ADC_O_CC 0x00000FC8 // ADC Clock Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_ACTSS register.
+//
+//*****************************************************************************
+#define ADC_ACTSS_ASEN3 0x00000008 // ADC SS3 Enable
+#define ADC_ACTSS_ASEN2 0x00000004 // ADC SS2 Enable
+#define ADC_ACTSS_ASEN1 0x00000002 // ADC SS1 Enable
+#define ADC_ACTSS_ASEN0 0x00000001 // ADC SS0 Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_RIS register.
+//
+//*****************************************************************************
+#define ADC_RIS_INRDC 0x00010000 // Digital Comparator Raw Interrupt
+ // Status
+#define ADC_RIS_INR3 0x00000008 // SS3 Raw Interrupt Status
+#define ADC_RIS_INR2 0x00000004 // SS2 Raw Interrupt Status
+#define ADC_RIS_INR1 0x00000002 // SS1 Raw Interrupt Status
+#define ADC_RIS_INR0 0x00000001 // SS0 Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_IM register.
+//
+//*****************************************************************************
+#define ADC_IM_DCONSS3 0x00080000 // Digital Comparator Interrupt on
+ // SS3
+#define ADC_IM_DCONSS2 0x00040000 // Digital Comparator Interrupt on
+ // SS2
+#define ADC_IM_DCONSS1 0x00020000 // Digital Comparator Interrupt on
+ // SS1
+#define ADC_IM_DCONSS0 0x00010000 // Digital Comparator Interrupt on
+ // SS0
+#define ADC_IM_MASK3 0x00000008 // SS3 Interrupt Mask
+#define ADC_IM_MASK2 0x00000004 // SS2 Interrupt Mask
+#define ADC_IM_MASK1 0x00000002 // SS1 Interrupt Mask
+#define ADC_IM_MASK0 0x00000001 // SS0 Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_ISC register.
+//
+//*****************************************************************************
+#define ADC_ISC_DCINSS3 0x00080000 // Digital Comparator Interrupt
+ // Status on SS3
+#define ADC_ISC_DCINSS2 0x00040000 // Digital Comparator Interrupt
+ // Status on SS2
+#define ADC_ISC_DCINSS1 0x00020000 // Digital Comparator Interrupt
+ // Status on SS1
+#define ADC_ISC_DCINSS0 0x00010000 // Digital Comparator Interrupt
+ // Status on SS0
+#define ADC_ISC_IN3 0x00000008 // SS3 Interrupt Status and Clear
+#define ADC_ISC_IN2 0x00000004 // SS2 Interrupt Status and Clear
+#define ADC_ISC_IN1 0x00000002 // SS1 Interrupt Status and Clear
+#define ADC_ISC_IN0 0x00000001 // SS0 Interrupt Status and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_OSTAT register.
+//
+//*****************************************************************************
+#define ADC_OSTAT_OV3 0x00000008 // SS3 FIFO Overflow
+#define ADC_OSTAT_OV2 0x00000004 // SS2 FIFO Overflow
+#define ADC_OSTAT_OV1 0x00000002 // SS1 FIFO Overflow
+#define ADC_OSTAT_OV0 0x00000001 // SS0 FIFO Overflow
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_EMUX register.
+//
+//*****************************************************************************
+#define ADC_EMUX_EM3_M 0x0000F000 // SS3 Trigger Select
+#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor (default)
+#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog Comparator 0
+#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog Comparator 1
+#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog Comparator 2
+#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External (GPIO PB4)
+#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer
+#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0
+#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1
+#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2
+#define ADC_EMUX_EM3_PWM3 0x00009000 // PWM3
+#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always (continuously sample)
+#define ADC_EMUX_EM2_M 0x00000F00 // SS2 Trigger Select
+#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor (default)
+#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog Comparator 0
+#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog Comparator 1
+#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog Comparator 2
+#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External (GPIO PB4)
+#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer
+#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0
+#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1
+#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2
+#define ADC_EMUX_EM2_PWM3 0x00000900 // PWM3
+#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always (continuously sample)
+#define ADC_EMUX_EM1_M 0x000000F0 // SS1 Trigger Select
+#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor (default)
+#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog Comparator 0
+#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog Comparator 1
+#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog Comparator 2
+#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External (GPIO PB4)
+#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer
+#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0
+#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1
+#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2
+#define ADC_EMUX_EM1_PWM3 0x00000090 // PWM3
+#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always (continuously sample)
+#define ADC_EMUX_EM0_M 0x0000000F // SS0 Trigger Select
+#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor (default)
+#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog Comparator 0
+#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog Comparator 1
+#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog Comparator 2
+#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External (GPIO PB4)
+#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer
+#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0
+#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1
+#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2
+#define ADC_EMUX_EM0_PWM3 0x00000009 // PWM3
+#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always (continuously sample)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_USTAT register.
+//
+//*****************************************************************************
+#define ADC_USTAT_UV3 0x00000008 // SS3 FIFO Underflow
+#define ADC_USTAT_UV2 0x00000004 // SS2 FIFO Underflow
+#define ADC_USTAT_UV1 0x00000002 // SS1 FIFO Underflow
+#define ADC_USTAT_UV0 0x00000001 // SS0 FIFO Underflow
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_TSSEL register.
+//
+//*****************************************************************************
+#define ADC_TSSEL_PS3_M 0x30000000 // PWM Unit Select
+#define ADC_TSSEL_PS3_0 0x00000000 // PWM Unit 0
+#define ADC_TSSEL_PS3_1 0x10000000 // PWM Unit 1
+#define ADC_TSSEL_PS2_M 0x00300000 // PWM Unit Select
+#define ADC_TSSEL_PS2_0 0x00000000 // PWM Unit 0
+#define ADC_TSSEL_PS2_1 0x00100000 // PWM Unit 1
+#define ADC_TSSEL_PS1_M 0x00003000 // PWM Unit Select
+#define ADC_TSSEL_PS1_0 0x00000000 // PWM Unit 0
+#define ADC_TSSEL_PS1_1 0x00001000 // PWM Unit 1
+#define ADC_TSSEL_PS0_M 0x00000030 // PWM Unit Select
+#define ADC_TSSEL_PS0_0 0x00000000 // PWM Unit 0
+#define ADC_TSSEL_PS0_1 0x00000010 // PWM Unit 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSPRI register.
+//
+//*****************************************************************************
+#define ADC_SSPRI_SS3_M 0x00003000 // SS3 Priority
+#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority
+#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority
+#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority
+#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority
+#define ADC_SSPRI_SS2_M 0x00000300 // SS2 Priority
+#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority
+#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority
+#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority
+#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority
+#define ADC_SSPRI_SS1_M 0x00000030 // SS1 Priority
+#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority
+#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority
+#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority
+#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority
+#define ADC_SSPRI_SS0_M 0x00000003 // SS0 Priority
+#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority
+#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority
+#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority
+#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SPC register.
+//
+//*****************************************************************************
+#define ADC_SPC_PHASE_M 0x0000000F // Phase Difference
+#define ADC_SPC_PHASE_0 0x00000000 // ADC sample lags by 0.0
+#define ADC_SPC_PHASE_22_5 0x00000001 // ADC sample lags by 22.5
+#define ADC_SPC_PHASE_45 0x00000002 // ADC sample lags by 45.0
+#define ADC_SPC_PHASE_67_5 0x00000003 // ADC sample lags by 67.5
+#define ADC_SPC_PHASE_90 0x00000004 // ADC sample lags by 90.0
+#define ADC_SPC_PHASE_112_5 0x00000005 // ADC sample lags by 112.5
+#define ADC_SPC_PHASE_135 0x00000006 // ADC sample lags by 135.0
+#define ADC_SPC_PHASE_157_5 0x00000007 // ADC sample lags by 157.5
+#define ADC_SPC_PHASE_180 0x00000008 // ADC sample lags by 180.0
+#define ADC_SPC_PHASE_202_5 0x00000009 // ADC sample lags by 202.5
+#define ADC_SPC_PHASE_225 0x0000000A // ADC sample lags by 225.0
+#define ADC_SPC_PHASE_247_5 0x0000000B // ADC sample lags by 247.5
+#define ADC_SPC_PHASE_270 0x0000000C // ADC sample lags by 270.0
+#define ADC_SPC_PHASE_292_5 0x0000000D // ADC sample lags by 292.5
+#define ADC_SPC_PHASE_315 0x0000000E // ADC sample lags by 315.0
+#define ADC_SPC_PHASE_337_5 0x0000000F // ADC sample lags by 337.5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_PSSI register.
+//
+//*****************************************************************************
+#define ADC_PSSI_GSYNC 0x80000000 // Global Synchronize
+#define ADC_PSSI_SYNCWAIT 0x08000000 // Synchronize Wait
+#define ADC_PSSI_SS3 0x00000008 // SS3 Initiate
+#define ADC_PSSI_SS2 0x00000004 // SS2 Initiate
+#define ADC_PSSI_SS1 0x00000002 // SS1 Initiate
+#define ADC_PSSI_SS0 0x00000001 // SS0 Initiate
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SAC register.
+//
+//*****************************************************************************
+#define ADC_SAC_AVG_M 0x00000007 // Hardware Averaging Control
+#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling
+#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling
+#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling
+#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling
+#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling
+#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling
+#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCISC register.
+//
+//*****************************************************************************
+#define ADC_DCISC_DCINT7 0x00000080 // Digital Comparator 7 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT6 0x00000040 // Digital Comparator 6 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT5 0x00000020 // Digital Comparator 5 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT4 0x00000010 // Digital Comparator 4 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT3 0x00000008 // Digital Comparator 3 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT2 0x00000004 // Digital Comparator 2 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT1 0x00000002 // Digital Comparator 1 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT0 0x00000001 // Digital Comparator 0 Interrupt
+ // Status and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_CTL register.
+//
+//*****************************************************************************
+#define ADC_CTL_RES 0x00000010 // Sample Resolution
+#define ADC_CTL_VREF_M 0x00000003 // Voltage Reference Select
+#define ADC_CTL_VREF_INTERNAL 0x00000000 // The internal reference as the
+ // voltage reference
+#define ADC_CTL_VREF_EXT_3V 0x00000001 // A 3.0 V external VREFA input is
+ // the voltage reference. The ADC
+ // conversion range is 0.0 V to the
+ // external reference value
+#define ADC_CTL_VREF_EXT_1V 0x00000003 // A 1.0 V external VREFA input is
+ // the voltage reference. The ADC
+ // conversion range is 0.0 V to
+ // three times the external
+ // reference value
+#define ADC_CTL_VREF 0x00000001 // Voltage Reference Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX0 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX0_MUX7_M 0xF0000000 // 8th Sample Input Select
+#define ADC_SSMUX0_MUX6_M 0x0F000000 // 7th Sample Input Select
+#define ADC_SSMUX0_MUX5_M 0x00F00000 // 6th Sample Input Select
+#define ADC_SSMUX0_MUX4_M 0x000F0000 // 5th Sample Input Select
+#define ADC_SSMUX0_MUX3_M 0x0000F000 // 4th Sample Input Select
+#define ADC_SSMUX0_MUX2_M 0x00000F00 // 3rd Sample Input Select
+#define ADC_SSMUX0_MUX1_M 0x000000F0 // 2nd Sample Input Select
+#define ADC_SSMUX0_MUX0_M 0x0000000F // 1st Sample Input Select
+#define ADC_SSMUX0_MUX7_S 28
+#define ADC_SSMUX0_MUX6_S 24
+#define ADC_SSMUX0_MUX5_S 20
+#define ADC_SSMUX0_MUX4_S 16
+#define ADC_SSMUX0_MUX3_S 12
+#define ADC_SSMUX0_MUX2_S 8
+#define ADC_SSMUX0_MUX1_S 4
+#define ADC_SSMUX0_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL0 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL0_TS7 0x80000000 // 8th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE7 0x40000000 // 8th Sample Interrupt Enable
+#define ADC_SSCTL0_END7 0x20000000 // 8th Sample is End of Sequence
+#define ADC_SSCTL0_D7 0x10000000 // 8th Sample Diff Input Select
+#define ADC_SSCTL0_TS6 0x08000000 // 7th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE6 0x04000000 // 7th Sample Interrupt Enable
+#define ADC_SSCTL0_END6 0x02000000 // 7th Sample is End of Sequence
+#define ADC_SSCTL0_D6 0x01000000 // 7th Sample Diff Input Select
+#define ADC_SSCTL0_TS5 0x00800000 // 6th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE5 0x00400000 // 6th Sample Interrupt Enable
+#define ADC_SSCTL0_END5 0x00200000 // 6th Sample is End of Sequence
+#define ADC_SSCTL0_D5 0x00100000 // 6th Sample Diff Input Select
+#define ADC_SSCTL0_TS4 0x00080000 // 5th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE4 0x00040000 // 5th Sample Interrupt Enable
+#define ADC_SSCTL0_END4 0x00020000 // 5th Sample is End of Sequence
+#define ADC_SSCTL0_D4 0x00010000 // 5th Sample Diff Input Select
+#define ADC_SSCTL0_TS3 0x00008000 // 4th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE3 0x00004000 // 4th Sample Interrupt Enable
+#define ADC_SSCTL0_END3 0x00002000 // 4th Sample is End of Sequence
+#define ADC_SSCTL0_D3 0x00001000 // 4th Sample Diff Input Select
+#define ADC_SSCTL0_TS2 0x00000800 // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL0_IE2 0x00000400 // 3rd Sample Interrupt Enable
+#define ADC_SSCTL0_END2 0x00000200 // 3rd Sample is End of Sequence
+#define ADC_SSCTL0_D2 0x00000100 // 3rd Sample Diff Input Select
+#define ADC_SSCTL0_TS1 0x00000080 // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL0_IE1 0x00000040 // 2nd Sample Interrupt Enable
+#define ADC_SSCTL0_END1 0x00000020 // 2nd Sample is End of Sequence
+#define ADC_SSCTL0_D1 0x00000010 // 2nd Sample Diff Input Select
+#define ADC_SSCTL0_TS0 0x00000008 // 1st Sample Temp Sensor Select
+#define ADC_SSCTL0_IE0 0x00000004 // 1st Sample Interrupt Enable
+#define ADC_SSCTL0_END0 0x00000002 // 1st Sample is End of Sequence
+#define ADC_SSCTL0_D0 0x00000001 // 1st Sample Diff Input Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO0 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO0_DATA_M 0x00000FFF // Conversion Result Data
+#define ADC_SSFIFO0_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT0_FULL 0x00001000 // FIFO Full
+#define ADC_SSFSTAT0_EMPTY 0x00000100 // FIFO Empty
+#define ADC_SSFSTAT0_HPTR_M 0x000000F0 // FIFO Head Pointer
+#define ADC_SSFSTAT0_TPTR_M 0x0000000F // FIFO Tail Pointer
+#define ADC_SSFSTAT0_HPTR_S 4
+#define ADC_SSFSTAT0_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP0 register.
+//
+//*****************************************************************************
+#define ADC_SSOP0_S7DCOP 0x10000000 // Sample 7 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S6DCOP 0x01000000 // Sample 6 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S5DCOP 0x00100000 // Sample 5 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S4DCOP 0x00010000 // Sample 4 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S3DCOP 0x00001000 // Sample 3 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S2DCOP 0x00000100 // Sample 2 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S1DCOP 0x00000010 // Sample 1 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S0DCOP 0x00000001 // Sample 0 Digital Comparator
+ // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC0 register.
+//
+//*****************************************************************************
+#define ADC_SSDC0_S7DCSEL_M 0xF0000000 // Sample 7 Digital Comparator
+ // Select
+#define ADC_SSDC0_S6DCSEL_M 0x0F000000 // Sample 6 Digital Comparator
+ // Select
+#define ADC_SSDC0_S5DCSEL_M 0x00F00000 // Sample 5 Digital Comparator
+ // Select
+#define ADC_SSDC0_S4DCSEL_M 0x000F0000 // Sample 4 Digital Comparator
+ // Select
+#define ADC_SSDC0_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator
+ // Select
+#define ADC_SSDC0_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator
+ // Select
+#define ADC_SSDC0_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator
+ // Select
+#define ADC_SSDC0_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
+ // Select
+#define ADC_SSDC0_S6DCSEL_S 24
+#define ADC_SSDC0_S5DCSEL_S 20
+#define ADC_SSDC0_S4DCSEL_S 16
+#define ADC_SSDC0_S3DCSEL_S 12
+#define ADC_SSDC0_S2DCSEL_S 8
+#define ADC_SSDC0_S1DCSEL_S 4
+#define ADC_SSDC0_S0DCSEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSEMUX0 register.
+//
+//*****************************************************************************
+#define ADC_SSEMUX0_EMUX7 0x10000000 // 8th Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX0_EMUX6 0x01000000 // 7th Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX0_EMUX5 0x00100000 // 6th Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX0_EMUX4 0x00010000 // 5th Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX0_EMUX3 0x00001000 // 4th Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX0_EMUX2 0x00000100 // 3rd Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX0_EMUX1 0x00000010 // 2th Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX0_EMUX0 0x00000001 // 1st Sample Input Select (Upper
+ // Bit)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX1 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX1_MUX3_M 0x0000F000 // 4th Sample Input Select
+#define ADC_SSMUX1_MUX2_M 0x00000F00 // 3rd Sample Input Select
+#define ADC_SSMUX1_MUX1_M 0x000000F0 // 2nd Sample Input Select
+#define ADC_SSMUX1_MUX0_M 0x0000000F // 1st Sample Input Select
+#define ADC_SSMUX1_MUX3_S 12
+#define ADC_SSMUX1_MUX2_S 8
+#define ADC_SSMUX1_MUX1_S 4
+#define ADC_SSMUX1_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL1 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL1_TS3 0x00008000 // 4th Sample Temp Sensor Select
+#define ADC_SSCTL1_IE3 0x00004000 // 4th Sample Interrupt Enable
+#define ADC_SSCTL1_END3 0x00002000 // 4th Sample is End of Sequence
+#define ADC_SSCTL1_D3 0x00001000 // 4th Sample Diff Input Select
+#define ADC_SSCTL1_TS2 0x00000800 // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL1_IE2 0x00000400 // 3rd Sample Interrupt Enable
+#define ADC_SSCTL1_END2 0x00000200 // 3rd Sample is End of Sequence
+#define ADC_SSCTL1_D2 0x00000100 // 3rd Sample Diff Input Select
+#define ADC_SSCTL1_TS1 0x00000080 // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL1_IE1 0x00000040 // 2nd Sample Interrupt Enable
+#define ADC_SSCTL1_END1 0x00000020 // 2nd Sample is End of Sequence
+#define ADC_SSCTL1_D1 0x00000010 // 2nd Sample Diff Input Select
+#define ADC_SSCTL1_TS0 0x00000008 // 1st Sample Temp Sensor Select
+#define ADC_SSCTL1_IE0 0x00000004 // 1st Sample Interrupt Enable
+#define ADC_SSCTL1_END0 0x00000002 // 1st Sample is End of Sequence
+#define ADC_SSCTL1_D0 0x00000001 // 1st Sample Diff Input Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO1 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO1_DATA_M 0x00000FFF // Conversion Result Data
+#define ADC_SSFIFO1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT1_FULL 0x00001000 // FIFO Full
+#define ADC_SSFSTAT1_EMPTY 0x00000100 // FIFO Empty
+#define ADC_SSFSTAT1_HPTR_M 0x000000F0 // FIFO Head Pointer
+#define ADC_SSFSTAT1_TPTR_M 0x0000000F // FIFO Tail Pointer
+#define ADC_SSFSTAT1_HPTR_S 4
+#define ADC_SSFSTAT1_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP1 register.
+//
+//*****************************************************************************
+#define ADC_SSOP1_S3DCOP 0x00001000 // Sample 3 Digital Comparator
+ // Operation
+#define ADC_SSOP1_S2DCOP 0x00000100 // Sample 2 Digital Comparator
+ // Operation
+#define ADC_SSOP1_S1DCOP 0x00000010 // Sample 1 Digital Comparator
+ // Operation
+#define ADC_SSOP1_S0DCOP 0x00000001 // Sample 0 Digital Comparator
+ // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC1 register.
+//
+//*****************************************************************************
+#define ADC_SSDC1_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator
+ // Select
+#define ADC_SSDC1_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator
+ // Select
+#define ADC_SSDC1_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator
+ // Select
+#define ADC_SSDC1_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
+ // Select
+#define ADC_SSDC1_S2DCSEL_S 8
+#define ADC_SSDC1_S1DCSEL_S 4
+#define ADC_SSDC1_S0DCSEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSEMUX1 register.
+//
+//*****************************************************************************
+#define ADC_SSEMUX1_EMUX3 0x00001000 // 4th Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX1_EMUX2 0x00000100 // 3rd Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX1_EMUX1 0x00000010 // 2th Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX1_EMUX0 0x00000001 // 1st Sample Input Select (Upper
+ // Bit)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX2 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX2_MUX3_M 0x0000F000 // 4th Sample Input Select
+#define ADC_SSMUX2_MUX2_M 0x00000F00 // 3rd Sample Input Select
+#define ADC_SSMUX2_MUX1_M 0x000000F0 // 2nd Sample Input Select
+#define ADC_SSMUX2_MUX0_M 0x0000000F // 1st Sample Input Select
+#define ADC_SSMUX2_MUX3_S 12
+#define ADC_SSMUX2_MUX2_S 8
+#define ADC_SSMUX2_MUX1_S 4
+#define ADC_SSMUX2_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL2 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL2_TS3 0x00008000 // 4th Sample Temp Sensor Select
+#define ADC_SSCTL2_IE3 0x00004000 // 4th Sample Interrupt Enable
+#define ADC_SSCTL2_END3 0x00002000 // 4th Sample is End of Sequence
+#define ADC_SSCTL2_D3 0x00001000 // 4th Sample Diff Input Select
+#define ADC_SSCTL2_TS2 0x00000800 // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL2_IE2 0x00000400 // 3rd Sample Interrupt Enable
+#define ADC_SSCTL2_END2 0x00000200 // 3rd Sample is End of Sequence
+#define ADC_SSCTL2_D2 0x00000100 // 3rd Sample Diff Input Select
+#define ADC_SSCTL2_TS1 0x00000080 // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL2_IE1 0x00000040 // 2nd Sample Interrupt Enable
+#define ADC_SSCTL2_END1 0x00000020 // 2nd Sample is End of Sequence
+#define ADC_SSCTL2_D1 0x00000010 // 2nd Sample Diff Input Select
+#define ADC_SSCTL2_TS0 0x00000008 // 1st Sample Temp Sensor Select
+#define ADC_SSCTL2_IE0 0x00000004 // 1st Sample Interrupt Enable
+#define ADC_SSCTL2_END0 0x00000002 // 1st Sample is End of Sequence
+#define ADC_SSCTL2_D0 0x00000001 // 1st Sample Diff Input Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO2 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO2_DATA_M 0x00000FFF // Conversion Result Data
+#define ADC_SSFIFO2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT2_FULL 0x00001000 // FIFO Full
+#define ADC_SSFSTAT2_EMPTY 0x00000100 // FIFO Empty
+#define ADC_SSFSTAT2_HPTR_M 0x000000F0 // FIFO Head Pointer
+#define ADC_SSFSTAT2_TPTR_M 0x0000000F // FIFO Tail Pointer
+#define ADC_SSFSTAT2_HPTR_S 4
+#define ADC_SSFSTAT2_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP2 register.
+//
+//*****************************************************************************
+#define ADC_SSOP2_S3DCOP 0x00001000 // Sample 3 Digital Comparator
+ // Operation
+#define ADC_SSOP2_S2DCOP 0x00000100 // Sample 2 Digital Comparator
+ // Operation
+#define ADC_SSOP2_S1DCOP 0x00000010 // Sample 1 Digital Comparator
+ // Operation
+#define ADC_SSOP2_S0DCOP 0x00000001 // Sample 0 Digital Comparator
+ // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC2 register.
+//
+//*****************************************************************************
+#define ADC_SSDC2_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator
+ // Select
+#define ADC_SSDC2_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator
+ // Select
+#define ADC_SSDC2_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator
+ // Select
+#define ADC_SSDC2_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
+ // Select
+#define ADC_SSDC2_S2DCSEL_S 8
+#define ADC_SSDC2_S1DCSEL_S 4
+#define ADC_SSDC2_S0DCSEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSEMUX2 register.
+//
+//*****************************************************************************
+#define ADC_SSEMUX2_EMUX3 0x00001000 // 4th Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX2_EMUX2 0x00000100 // 3rd Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX2_EMUX1 0x00000010 // 2th Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX2_EMUX0 0x00000001 // 1st Sample Input Select (Upper
+ // Bit)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX3 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX3_MUX0_M 0x0000000F // 1st Sample Input Select
+#define ADC_SSMUX3_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL3 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL3_TS0 0x00000008 // 1st Sample Temp Sensor Select
+#define ADC_SSCTL3_IE0 0x00000004 // 1st Sample Interrupt Enable
+#define ADC_SSCTL3_END0 0x00000002 // 1st Sample is End of Sequence
+#define ADC_SSCTL3_D0 0x00000001 // 1st Sample Diff Input Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO3 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO3_DATA_M 0x00000FFF // Conversion Result Data
+#define ADC_SSFIFO3_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT3_FULL 0x00001000 // FIFO Full
+#define ADC_SSFSTAT3_EMPTY 0x00000100 // FIFO Empty
+#define ADC_SSFSTAT3_HPTR_M 0x000000F0 // FIFO Head Pointer
+#define ADC_SSFSTAT3_TPTR_M 0x0000000F // FIFO Tail Pointer
+#define ADC_SSFSTAT3_HPTR_S 4
+#define ADC_SSFSTAT3_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP3 register.
+//
+//*****************************************************************************
+#define ADC_SSOP3_S0DCOP 0x00000001 // Sample 0 Digital Comparator
+ // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC3 register.
+//
+//*****************************************************************************
+#define ADC_SSDC3_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
+ // Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSEMUX3 register.
+//
+//*****************************************************************************
+#define ADC_SSEMUX3_EMUX0 0x00000001 // 1st Sample Input Select (Upper
+ // Bit)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_TMLB register.
+//
+//*****************************************************************************
+#define ADC_TMLB_LB 0x00000001 // Loopback Mode Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCRIC register.
+//
+//*****************************************************************************
+#define ADC_DCRIC_DCTRIG7 0x00800000 // Digital Comparator Trigger 7
+#define ADC_DCRIC_DCTRIG6 0x00400000 // Digital Comparator Trigger 6
+#define ADC_DCRIC_DCTRIG5 0x00200000 // Digital Comparator Trigger 5
+#define ADC_DCRIC_DCTRIG4 0x00100000 // Digital Comparator Trigger 4
+#define ADC_DCRIC_DCTRIG3 0x00080000 // Digital Comparator Trigger 3
+#define ADC_DCRIC_DCTRIG2 0x00040000 // Digital Comparator Trigger 2
+#define ADC_DCRIC_DCTRIG1 0x00020000 // Digital Comparator Trigger 1
+#define ADC_DCRIC_DCTRIG0 0x00010000 // Digital Comparator Trigger 0
+#define ADC_DCRIC_DCINT7 0x00000080 // Digital Comparator Interrupt 7
+#define ADC_DCRIC_DCINT6 0x00000040 // Digital Comparator Interrupt 6
+#define ADC_DCRIC_DCINT5 0x00000020 // Digital Comparator Interrupt 5
+#define ADC_DCRIC_DCINT4 0x00000010 // Digital Comparator Interrupt 4
+#define ADC_DCRIC_DCINT3 0x00000008 // Digital Comparator Interrupt 3
+#define ADC_DCRIC_DCINT2 0x00000004 // Digital Comparator Interrupt 2
+#define ADC_DCRIC_DCINT1 0x00000002 // Digital Comparator Interrupt 1
+#define ADC_DCRIC_DCINT0 0x00000001 // Digital Comparator Interrupt 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL0 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL0_CTE 0x00001000 // Comparison Trigger Enable
+#define ADC_DCCTL0_CTC_M 0x00000C00 // Comparison Trigger Condition
+#define ADC_DCCTL0_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL0_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL0_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL0_CTM_M 0x00000300 // Comparison Trigger Mode
+#define ADC_DCCTL0_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL0_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL0_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL0_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL0_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL0_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL0_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL0_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL0_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL0_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL0_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL0_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL0_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL0_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL1 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL1_CTE 0x00001000 // Comparison Trigger Enable
+#define ADC_DCCTL1_CTC_M 0x00000C00 // Comparison Trigger Condition
+#define ADC_DCCTL1_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL1_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL1_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL1_CTM_M 0x00000300 // Comparison Trigger Mode
+#define ADC_DCCTL1_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL1_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL1_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL1_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL1_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL1_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL1_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL1_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL1_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL1_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL1_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL1_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL1_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL1_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL2 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL2_CTE 0x00001000 // Comparison Trigger Enable
+#define ADC_DCCTL2_CTC_M 0x00000C00 // Comparison Trigger Condition
+#define ADC_DCCTL2_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL2_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL2_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL2_CTM_M 0x00000300 // Comparison Trigger Mode
+#define ADC_DCCTL2_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL2_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL2_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL2_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL2_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL2_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL2_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL2_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL2_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL2_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL2_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL2_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL2_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL2_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL3 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL3_CTE 0x00001000 // Comparison Trigger Enable
+#define ADC_DCCTL3_CTC_M 0x00000C00 // Comparison Trigger Condition
+#define ADC_DCCTL3_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL3_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL3_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL3_CTM_M 0x00000300 // Comparison Trigger Mode
+#define ADC_DCCTL3_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL3_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL3_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL3_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL3_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL3_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL3_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL3_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL3_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL3_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL3_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL3_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL3_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL3_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL4 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL4_CTE 0x00001000 // Comparison Trigger Enable
+#define ADC_DCCTL4_CTC_M 0x00000C00 // Comparison Trigger Condition
+#define ADC_DCCTL4_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL4_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL4_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL4_CTM_M 0x00000300 // Comparison Trigger Mode
+#define ADC_DCCTL4_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL4_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL4_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL4_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL4_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL4_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL4_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL4_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL4_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL4_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL4_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL4_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL4_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL4_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL5 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL5_CTE 0x00001000 // Comparison Trigger Enable
+#define ADC_DCCTL5_CTC_M 0x00000C00 // Comparison Trigger Condition
+#define ADC_DCCTL5_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL5_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL5_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL5_CTM_M 0x00000300 // Comparison Trigger Mode
+#define ADC_DCCTL5_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL5_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL5_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL5_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL5_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL5_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL5_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL5_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL5_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL5_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL5_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL5_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL5_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL5_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL6 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL6_CTE 0x00001000 // Comparison Trigger Enable
+#define ADC_DCCTL6_CTC_M 0x00000C00 // Comparison Trigger Condition
+#define ADC_DCCTL6_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL6_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL6_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL6_CTM_M 0x00000300 // Comparison Trigger Mode
+#define ADC_DCCTL6_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL6_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL6_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL6_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL6_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL6_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL6_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL6_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL6_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL6_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL6_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL6_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL6_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL6_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL7 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL7_CTE 0x00001000 // Comparison Trigger Enable
+#define ADC_DCCTL7_CTC_M 0x00000C00 // Comparison Trigger Condition
+#define ADC_DCCTL7_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL7_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL7_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL7_CTM_M 0x00000300 // Comparison Trigger Mode
+#define ADC_DCCTL7_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL7_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL7_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL7_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL7_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL7_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL7_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL7_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL7_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL7_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL7_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL7_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL7_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL7_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP0 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP0_COMP1_M 0x0FFF0000 // Compare 1
+#define ADC_DCCMP0_COMP0_M 0x00000FFF // Compare 0
+#define ADC_DCCMP0_COMP1_S 16
+#define ADC_DCCMP0_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP1 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP1_COMP1_M 0x0FFF0000 // Compare 1
+#define ADC_DCCMP1_COMP0_M 0x00000FFF // Compare 0
+#define ADC_DCCMP1_COMP1_S 16
+#define ADC_DCCMP1_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP2 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP2_COMP1_M 0x0FFF0000 // Compare 1
+#define ADC_DCCMP2_COMP0_M 0x00000FFF // Compare 0
+#define ADC_DCCMP2_COMP1_S 16
+#define ADC_DCCMP2_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP3 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP3_COMP1_M 0x0FFF0000 // Compare 1
+#define ADC_DCCMP3_COMP0_M 0x00000FFF // Compare 0
+#define ADC_DCCMP3_COMP1_S 16
+#define ADC_DCCMP3_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP4 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP4_COMP1_M 0x0FFF0000 // Compare 1
+#define ADC_DCCMP4_COMP0_M 0x00000FFF // Compare 0
+#define ADC_DCCMP4_COMP1_S 16
+#define ADC_DCCMP4_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP5 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP5_COMP1_M 0x0FFF0000 // Compare 1
+#define ADC_DCCMP5_COMP0_M 0x00000FFF // Compare 0
+#define ADC_DCCMP5_COMP1_S 16
+#define ADC_DCCMP5_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP6 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP6_COMP1_M 0x0FFF0000 // Compare 1
+#define ADC_DCCMP6_COMP0_M 0x00000FFF // Compare 0
+#define ADC_DCCMP6_COMP1_S 16
+#define ADC_DCCMP6_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP7 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP7_COMP1_M 0x0FFF0000 // Compare 1
+#define ADC_DCCMP7_COMP0_M 0x00000FFF // Compare 0
+#define ADC_DCCMP7_COMP1_S 16
+#define ADC_DCCMP7_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_PP register.
+//
+//*****************************************************************************
+#define ADC_PP_TS 0x00800000 // Temperature Sensor
+#define ADC_PP_RSL_M 0x007C0000 // Resolution
+#define ADC_PP_TYPE_M 0x00030000 // ADC Architecture
+#define ADC_PP_TYPE_SAR 0x00000000 // SAR
+#define ADC_PP_DC_M 0x0000FC00 // Digital Comparator Count
+#define ADC_PP_CH_M 0x000003F0 // ADC Channel Count
+#define ADC_PP_MSR_M 0x0000000F // Maximum ADC Sample Rate
+#define ADC_PP_MSR_125K 0x00000001 // 125 ksps
+#define ADC_PP_MSR_250K 0x00000003 // 250 ksps
+#define ADC_PP_MSR_500K 0x00000005 // 500 ksps
+#define ADC_PP_MSR_1M 0x00000007 // 1 Msps
+#define ADC_PP_RSL_S 18
+#define ADC_PP_DC_S 10
+#define ADC_PP_CH_S 4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_PC register.
+//
+//*****************************************************************************
+#define ADC_PC_SR_M 0x0000000F // ADC Sample Rate
+#define ADC_PC_SR_125K 0x00000001 // 125 ksps
+#define ADC_PC_SR_250K 0x00000003 // 250 ksps
+#define ADC_PC_SR_500K 0x00000005 // 500 ksps
+#define ADC_PC_SR_1M 0x00000007 // 1 Msps
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_CC register.
+//
+//*****************************************************************************
+#define ADC_CC_CS_M 0x0000000F // ADC Clock Source
+#define ADC_CC_CS_SYSPLL 0x00000000 // Either the system clock (if the
+ // PLL bypass is in effect) or the
+ // 16 MHz clock derived from PLL /
+ // 25 (default)
+#define ADC_CC_CS_PIOSC 0x00000001 // PIOSC
+
+//*****************************************************************************
+//
+// The following are defines for the the interpretation of the data in the
+// SSFIFOx when the ADC TMLB is enabled.
+//
+//*****************************************************************************
+#define ADC_SSFIFO_TMLB_CNT_M 0x000003C0 // Continuous Sample Counter
+#define ADC_SSFIFO_TMLB_CONT 0x00000020 // Continuation Sample Indicator
+#define ADC_SSFIFO_TMLB_DIFF 0x00000010 // Differential Sample Indicator
+#define ADC_SSFIFO_TMLB_TS 0x00000008 // Temp Sensor Sample Indicator
+#define ADC_SSFIFO_TMLB_MUX_M 0x00000007 // Analog Input Indicator
+#define ADC_SSFIFO_TMLB_CNT_S 6 // Sample counter shift
+#define ADC_SSFIFO_TMLB_MUX_S 0 // Input channel number shift
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the ADC_O_EMUX
+// register.
+//
+//*****************************************************************************
+#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask
+#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask
+#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask
+#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask
+#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event
+#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event
+#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event
+#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the ADC_O_SSPRI
+// register.
+//
+//*****************************************************************************
+#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask
+#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask
+#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask
+#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the ADC sequence register offsets..
+//
+//*****************************************************************************
+#define ADC_O_SEQ 0x00000040 // Offset to the first sequence
+#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence
+#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register
+#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register
+#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register
+#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the ADC_SSMUX0,
+// ADC_SSMUX1, ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present
+// in all registers..
+//
+//*****************************************************************************
+#define ADC_SSMUX_MUX7_MASK 0x70000000 // 8th mux select mask
+#define ADC_SSMUX_MUX6_MASK 0x07000000 // 7th mux select mask
+#define ADC_SSMUX_MUX5_MASK 0x00700000 // 6th mux select mask
+#define ADC_SSMUX_MUX4_MASK 0x00070000 // 5th mux select mask
+#define ADC_SSMUX_MUX3_MASK 0x00007000 // 4th mux select mask
+#define ADC_SSMUX_MUX2_MASK 0x00000700 // 3rd mux select mask
+#define ADC_SSMUX_MUX1_MASK 0x00000070 // 2nd mux select mask
+#define ADC_SSMUX_MUX0_MASK 0x00000007 // 1st mux select mask
+#define ADC_SSMUX_MUX7_SHIFT 28
+#define ADC_SSMUX_MUX6_SHIFT 24
+#define ADC_SSMUX_MUX5_SHIFT 20
+#define ADC_SSMUX_MUX4_SHIFT 16
+#define ADC_SSMUX_MUX3_SHIFT 12
+#define ADC_SSMUX_MUX2_SHIFT 8
+#define ADC_SSMUX_MUX1_SHIFT 4
+#define ADC_SSMUX_MUX0_SHIFT 0
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the ADC_SSCTL0,
+// ADC_SSCTL1, ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present
+// in all registers.
+//
+//*****************************************************************************
+#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select
+#define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable
+#define ADC_SSCTL_END7 0x20000000 // 8th sequence end select
+#define ADC_SSCTL_D7 0x10000000 // 8th differential select
+#define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select
+#define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable
+#define ADC_SSCTL_END6 0x02000000 // 7th sequence end select
+#define ADC_SSCTL_D6 0x01000000 // 7th differential select
+#define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select
+#define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable
+#define ADC_SSCTL_END5 0x00200000 // 6th sequence end select
+#define ADC_SSCTL_D5 0x00100000 // 6th differential select
+#define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select
+#define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable
+#define ADC_SSCTL_END4 0x00020000 // 5th sequence end select
+#define ADC_SSCTL_D4 0x00010000 // 5th differential select
+#define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select
+#define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable
+#define ADC_SSCTL_END3 0x00002000 // 4th sequence end select
+#define ADC_SSCTL_D3 0x00001000 // 4th differential select
+#define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select
+#define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable
+#define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select
+#define ADC_SSCTL_D2 0x00000100 // 3rd differential select
+#define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select
+#define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable
+#define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select
+#define ADC_SSCTL_D1 0x00000010 // 2nd differential select
+#define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select
+#define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable
+#define ADC_SSCTL_END0 0x00000002 // 1st sequence end select
+#define ADC_SSCTL_D0 0x00000001 // 1st differential select
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the ADC_SSFIFO0,
+// ADC_SSFIFO1, ADC_SSFIFO2, and ADC_SSFIFO3 registers.
+//
+//*****************************************************************************
+#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data
+#define ADC_SSFIFO_DATA_SHIFT 0
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the ADC_SSFSTAT0,
+// ADC_SSFSTAT1, ADC_SSFSTAT2, and ADC_SSFSTAT3 registers.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full
+#define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty
+#define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer
+#define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the the interpretation of the data
+// in the SSFIFOx when the ADC TMLB is enabled.
+//
+//*****************************************************************************
+#define ADC_TMLB_CNT_M 0x000003C0 // Continuous Sample Counter
+#define ADC_TMLB_CONT 0x00000020 // Continuation Sample Indicator
+#define ADC_TMLB_DIFF 0x00000010 // Differential Sample Indicator
+#define ADC_TMLB_TS 0x00000008 // Temp Sensor Sample Indicator
+#define ADC_TMLB_MUX_M 0x00000007 // Analog Input Indicator
+#define ADC_TMLB_CNT_S 6 // Sample counter shift
+#define ADC_TMLB_MUX_S 0 // Input channel number shift
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the loopback ADC
+// data.
+//
+//*****************************************************************************
+#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask
+#define ADC_LB_CONT 0x00000020 // Continuation sample
+#define ADC_LB_DIFF 0x00000010 // Differential sample
+#define ADC_LB_TS 0x00000008 // Temperature sensor sample
+#define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask
+#define ADC_LB_CNT_SHIFT 6 // Sample counter shift
+#define ADC_LB_MUX_SHIFT 0 // Input channel number shift
+
+#endif
+
+#endif // __HW_ADC_H__
diff --git a/inc/hw_can.h b/inc/hw_can.h new file mode 100644 index 0000000..392e037 --- /dev/null +++ b/inc/hw_can.h @@ -0,0 +1,771 @@ +//*****************************************************************************
+//
+// hw_can.h - Defines and macros used when accessing the CAN controllers.
+//
+// Copyright (c) 2006-2012 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 9453 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_CAN_H__
+#define __HW_CAN_H__
+
+//*****************************************************************************
+//
+// The following are defines for the CAN register offsets.
+//
+//*****************************************************************************
+#define CAN_O_CTL 0x00000000 // CAN Control
+#define CAN_O_STS 0x00000004 // CAN Status
+#define CAN_O_ERR 0x00000008 // CAN Error Counter
+#define CAN_O_BIT 0x0000000C // CAN Bit Timing
+#define CAN_O_INT 0x00000010 // CAN Interrupt
+#define CAN_O_TST 0x00000014 // CAN Test
+#define CAN_O_BRPE 0x00000018 // CAN Baud Rate Prescaler
+ // Extension
+#define CAN_O_IF1CRQ 0x00000020 // CAN IF1 Command Request
+#define CAN_O_IF1CMSK 0x00000024 // CAN IF1 Command Mask
+#define CAN_O_IF1MSK1 0x00000028 // CAN IF1 Mask 1
+#define CAN_O_IF1MSK2 0x0000002C // CAN IF1 Mask 2
+#define CAN_O_IF1ARB1 0x00000030 // CAN IF1 Arbitration 1
+#define CAN_O_IF1ARB2 0x00000034 // CAN IF1 Arbitration 2
+#define CAN_O_IF1MCTL 0x00000038 // CAN IF1 Message Control
+#define CAN_O_IF1DA1 0x0000003C // CAN IF1 Data A1
+#define CAN_O_IF1DA2 0x00000040 // CAN IF1 Data A2
+#define CAN_O_IF1DB1 0x00000044 // CAN IF1 Data B1
+#define CAN_O_IF1DB2 0x00000048 // CAN IF1 Data B2
+#define CAN_O_IF2CRQ 0x00000080 // CAN IF2 Command Request
+#define CAN_O_IF2CMSK 0x00000084 // CAN IF2 Command Mask
+#define CAN_O_IF2MSK1 0x00000088 // CAN IF2 Mask 1
+#define CAN_O_IF2MSK2 0x0000008C // CAN IF2 Mask 2
+#define CAN_O_IF2ARB1 0x00000090 // CAN IF2 Arbitration 1
+#define CAN_O_IF2ARB2 0x00000094 // CAN IF2 Arbitration 2
+#define CAN_O_IF2MCTL 0x00000098 // CAN IF2 Message Control
+#define CAN_O_IF2DA1 0x0000009C // CAN IF2 Data A1
+#define CAN_O_IF2DA2 0x000000A0 // CAN IF2 Data A2
+#define CAN_O_IF2DB1 0x000000A4 // CAN IF2 Data B1
+#define CAN_O_IF2DB2 0x000000A8 // CAN IF2 Data B2
+#define CAN_O_TXRQ1 0x00000100 // CAN Transmission Request 1
+#define CAN_O_TXRQ2 0x00000104 // CAN Transmission Request 2
+#define CAN_O_NWDA1 0x00000120 // CAN New Data 1
+#define CAN_O_NWDA2 0x00000124 // CAN New Data 2
+#define CAN_O_MSG1INT 0x00000140 // CAN Message 1 Interrupt Pending
+#define CAN_O_MSG2INT 0x00000144 // CAN Message 2 Interrupt Pending
+#define CAN_O_MSG1VAL 0x00000160 // CAN Message 1 Valid
+#define CAN_O_MSG2VAL 0x00000164 // CAN Message 2 Valid
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_CTL register.
+//
+//*****************************************************************************
+#define CAN_CTL_TEST 0x00000080 // Test Mode Enable
+#define CAN_CTL_CCE 0x00000040 // Configuration Change Enable
+#define CAN_CTL_DAR 0x00000020 // Disable Automatic-Retransmission
+#define CAN_CTL_EIE 0x00000008 // Error Interrupt Enable
+#define CAN_CTL_SIE 0x00000004 // Status Interrupt Enable
+#define CAN_CTL_IE 0x00000002 // CAN Interrupt Enable
+#define CAN_CTL_INIT 0x00000001 // Initialization
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_STS register.
+//
+//*****************************************************************************
+#define CAN_STS_BOFF 0x00000080 // Bus-Off Status
+#define CAN_STS_EWARN 0x00000040 // Warning Status
+#define CAN_STS_EPASS 0x00000020 // Error Passive
+#define CAN_STS_RXOK 0x00000010 // Received a Message Successfully
+#define CAN_STS_TXOK 0x00000008 // Transmitted a Message
+ // Successfully
+#define CAN_STS_LEC_M 0x00000007 // Last Error Code
+#define CAN_STS_LEC_NONE 0x00000000 // No Error
+#define CAN_STS_LEC_STUFF 0x00000001 // Stuff Error
+#define CAN_STS_LEC_FORM 0x00000002 // Format Error
+#define CAN_STS_LEC_ACK 0x00000003 // ACK Error
+#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 Error
+#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 Error
+#define CAN_STS_LEC_CRC 0x00000006 // CRC Error
+#define CAN_STS_LEC_NOEVENT 0x00000007 // No Event
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_ERR register.
+//
+//*****************************************************************************
+#define CAN_ERR_RP 0x00008000 // Received Error Passive
+#define CAN_ERR_REC_M 0x00007F00 // Receive Error Counter
+#define CAN_ERR_TEC_M 0x000000FF // Transmit Error Counter
+#define CAN_ERR_REC_S 8
+#define CAN_ERR_TEC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_BIT register.
+//
+//*****************************************************************************
+#define CAN_BIT_TSEG2_M 0x00007000 // Time Segment after Sample Point
+#define CAN_BIT_TSEG1_M 0x00000F00 // Time Segment Before Sample Point
+#define CAN_BIT_SJW_M 0x000000C0 // (Re)Synchronization Jump Width
+#define CAN_BIT_BRP_M 0x0000003F // Baud Rate Prescaler
+#define CAN_BIT_TSEG2_S 12
+#define CAN_BIT_TSEG1_S 8
+#define CAN_BIT_SJW_S 6
+#define CAN_BIT_BRP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_INT register.
+//
+//*****************************************************************************
+#define CAN_INT_INTID_M 0x0000FFFF // Interrupt Identifier
+#define CAN_INT_INTID_NONE 0x00000000 // No interrupt pending
+#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TST register.
+//
+//*****************************************************************************
+#define CAN_TST_RX 0x00000080 // Receive Observation
+#define CAN_TST_TX_M 0x00000060 // Transmit Control
+#define CAN_TST_TX_CANCTL 0x00000000 // CAN Module Control
+#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point
+#define CAN_TST_TX_DOMINANT 0x00000040 // Driven Low
+#define CAN_TST_TX_RECESSIVE 0x00000060 // Driven High
+#define CAN_TST_LBACK 0x00000010 // Loopback Mode
+#define CAN_TST_SILENT 0x00000008 // Silent Mode
+#define CAN_TST_BASIC 0x00000004 // Basic Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_BRPE register.
+//
+//*****************************************************************************
+#define CAN_BRPE_BRPE_M 0x0000000F // Baud Rate Prescaler Extension
+#define CAN_BRPE_BRPE_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1CRQ register.
+//
+//*****************************************************************************
+#define CAN_IF1CRQ_BUSY 0x00008000 // Busy Flag
+#define CAN_IF1CRQ_MNUM_M 0x0000003F // Message Number
+#define CAN_IF1CRQ_MNUM_RSVD 0x00000000 // 0 is not a valid message number;
+ // it is interpreted as 0x20, or
+ // object 32
+#define CAN_IF1CRQ_MNUM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1CMSK register.
+//
+//*****************************************************************************
+#define CAN_IF1CMSK_WRNRD 0x00000080 // Write, Not Read
+#define CAN_IF1CMSK_MASK 0x00000040 // Access Mask Bits
+#define CAN_IF1CMSK_ARB 0x00000020 // Access Arbitration Bits
+#define CAN_IF1CMSK_CONTROL 0x00000010 // Access Control Bits
+#define CAN_IF1CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit
+#define CAN_IF1CMSK_NEWDAT 0x00000004 // Access New Data
+#define CAN_IF1CMSK_TXRQST 0x00000004 // Access Transmission Request
+#define CAN_IF1CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3
+#define CAN_IF1CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MSK1 register.
+//
+//*****************************************************************************
+#define CAN_IF1MSK1_IDMSK_M 0x0000FFFF // Identifier Mask
+#define CAN_IF1MSK1_IDMSK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MSK2 register.
+//
+//*****************************************************************************
+#define CAN_IF1MSK2_MXTD 0x00008000 // Mask Extended Identifier
+#define CAN_IF1MSK2_MDIR 0x00004000 // Mask Message Direction
+#define CAN_IF1MSK2_IDMSK_M 0x00001FFF // Identifier Mask
+#define CAN_IF1MSK2_IDMSK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1ARB1 register.
+//
+//*****************************************************************************
+#define CAN_IF1ARB1_ID_M 0x0000FFFF // Message Identifier
+#define CAN_IF1ARB1_ID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1ARB2 register.
+//
+//*****************************************************************************
+#define CAN_IF1ARB2_MSGVAL 0x00008000 // Message Valid
+#define CAN_IF1ARB2_XTD 0x00004000 // Extended Identifier
+#define CAN_IF1ARB2_DIR 0x00002000 // Message Direction
+#define CAN_IF1ARB2_ID_M 0x00001FFF // Message Identifier
+#define CAN_IF1ARB2_ID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MCTL register.
+//
+//*****************************************************************************
+#define CAN_IF1MCTL_NEWDAT 0x00008000 // New Data
+#define CAN_IF1MCTL_MSGLST 0x00004000 // Message Lost
+#define CAN_IF1MCTL_INTPND 0x00002000 // Interrupt Pending
+#define CAN_IF1MCTL_UMASK 0x00001000 // Use Acceptance Mask
+#define CAN_IF1MCTL_TXIE 0x00000800 // Transmit Interrupt Enable
+#define CAN_IF1MCTL_RXIE 0x00000400 // Receive Interrupt Enable
+#define CAN_IF1MCTL_RMTEN 0x00000200 // Remote Enable
+#define CAN_IF1MCTL_TXRQST 0x00000100 // Transmit Request
+#define CAN_IF1MCTL_EOB 0x00000080 // End of Buffer
+#define CAN_IF1MCTL_DLC_M 0x0000000F // Data Length Code
+#define CAN_IF1MCTL_DLC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DA1 register.
+//
+//*****************************************************************************
+#define CAN_IF1DA1_DATA_M 0x0000FFFF // Data
+#define CAN_IF1DA1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DA2 register.
+//
+//*****************************************************************************
+#define CAN_IF1DA2_DATA_M 0x0000FFFF // Data
+#define CAN_IF1DA2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DB1 register.
+//
+//*****************************************************************************
+#define CAN_IF1DB1_DATA_M 0x0000FFFF // Data
+#define CAN_IF1DB1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DB2 register.
+//
+//*****************************************************************************
+#define CAN_IF1DB2_DATA_M 0x0000FFFF // Data
+#define CAN_IF1DB2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2CRQ register.
+//
+//*****************************************************************************
+#define CAN_IF2CRQ_BUSY 0x00008000 // Busy Flag
+#define CAN_IF2CRQ_MNUM_M 0x0000003F // Message Number
+#define CAN_IF2CRQ_MNUM_RSVD 0x00000000 // 0 is not a valid message number;
+ // it is interpreted as 0x20, or
+ // object 32
+#define CAN_IF2CRQ_MNUM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2CMSK register.
+//
+//*****************************************************************************
+#define CAN_IF2CMSK_WRNRD 0x00000080 // Write, Not Read
+#define CAN_IF2CMSK_MASK 0x00000040 // Access Mask Bits
+#define CAN_IF2CMSK_ARB 0x00000020 // Access Arbitration Bits
+#define CAN_IF2CMSK_CONTROL 0x00000010 // Access Control Bits
+#define CAN_IF2CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit
+#define CAN_IF2CMSK_NEWDAT 0x00000004 // Access New Data
+#define CAN_IF2CMSK_TXRQST 0x00000004 // Access Transmission Request
+#define CAN_IF2CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3
+#define CAN_IF2CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MSK1 register.
+//
+//*****************************************************************************
+#define CAN_IF2MSK1_IDMSK_M 0x0000FFFF // Identifier Mask
+#define CAN_IF2MSK1_IDMSK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MSK2 register.
+//
+//*****************************************************************************
+#define CAN_IF2MSK2_MXTD 0x00008000 // Mask Extended Identifier
+#define CAN_IF2MSK2_MDIR 0x00004000 // Mask Message Direction
+#define CAN_IF2MSK2_IDMSK_M 0x00001FFF // Identifier Mask
+#define CAN_IF2MSK2_IDMSK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2ARB1 register.
+//
+//*****************************************************************************
+#define CAN_IF2ARB1_ID_M 0x0000FFFF // Message Identifier
+#define CAN_IF2ARB1_ID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2ARB2 register.
+//
+//*****************************************************************************
+#define CAN_IF2ARB2_MSGVAL 0x00008000 // Message Valid
+#define CAN_IF2ARB2_XTD 0x00004000 // Extended Identifier
+#define CAN_IF2ARB2_DIR 0x00002000 // Message Direction
+#define CAN_IF2ARB2_ID_M 0x00001FFF // Message Identifier
+#define CAN_IF2ARB2_ID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MCTL register.
+//
+//*****************************************************************************
+#define CAN_IF2MCTL_NEWDAT 0x00008000 // New Data
+#define CAN_IF2MCTL_MSGLST 0x00004000 // Message Lost
+#define CAN_IF2MCTL_INTPND 0x00002000 // Interrupt Pending
+#define CAN_IF2MCTL_UMASK 0x00001000 // Use Acceptance Mask
+#define CAN_IF2MCTL_TXIE 0x00000800 // Transmit Interrupt Enable
+#define CAN_IF2MCTL_RXIE 0x00000400 // Receive Interrupt Enable
+#define CAN_IF2MCTL_RMTEN 0x00000200 // Remote Enable
+#define CAN_IF2MCTL_TXRQST 0x00000100 // Transmit Request
+#define CAN_IF2MCTL_EOB 0x00000080 // End of Buffer
+#define CAN_IF2MCTL_DLC_M 0x0000000F // Data Length Code
+#define CAN_IF2MCTL_DLC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DA1 register.
+//
+//*****************************************************************************
+#define CAN_IF2DA1_DATA_M 0x0000FFFF // Data
+#define CAN_IF2DA1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DA2 register.
+//
+//*****************************************************************************
+#define CAN_IF2DA2_DATA_M 0x0000FFFF // Data
+#define CAN_IF2DA2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DB1 register.
+//
+//*****************************************************************************
+#define CAN_IF2DB1_DATA_M 0x0000FFFF // Data
+#define CAN_IF2DB1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DB2 register.
+//
+//*****************************************************************************
+#define CAN_IF2DB2_DATA_M 0x0000FFFF // Data
+#define CAN_IF2DB2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TXRQ1 register.
+//
+//*****************************************************************************
+#define CAN_TXRQ1_TXRQST_M 0x0000FFFF // Transmission Request Bits
+#define CAN_TXRQ1_TXRQST_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TXRQ2 register.
+//
+//*****************************************************************************
+#define CAN_TXRQ2_TXRQST_M 0x0000FFFF // Transmission Request Bits
+#define CAN_TXRQ2_TXRQST_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_NWDA1 register.
+//
+//*****************************************************************************
+#define CAN_NWDA1_NEWDAT_M 0x0000FFFF // New Data Bits
+#define CAN_NWDA1_NEWDAT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_NWDA2 register.
+//
+//*****************************************************************************
+#define CAN_NWDA2_NEWDAT_M 0x0000FFFF // New Data Bits
+#define CAN_NWDA2_NEWDAT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG1INT register.
+//
+//*****************************************************************************
+#define CAN_MSG1INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits
+#define CAN_MSG1INT_INTPND_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG2INT register.
+//
+//*****************************************************************************
+#define CAN_MSG2INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits
+#define CAN_MSG2INT_INTPND_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG1VAL register.
+//
+//*****************************************************************************
+#define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits
+#define CAN_MSG1VAL_MSGVAL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG2VAL register.
+//
+//*****************************************************************************
+#define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits
+#define CAN_MSG2VAL_MSGVAL_S 0
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the CAN register offsets.
+//
+//*****************************************************************************
+#define CAN_O_MSGINT1 0x00000140 // Intr. Pending in Msg Obj 1 reg
+#define CAN_O_MSGINT2 0x00000144 // Intr. Pending in Msg Obj 2 reg
+#define CAN_O_MSGVAL1 0x00000160 // Message Valid in Msg Obj 1 reg
+#define CAN_O_MSGVAL2 0x00000164 // Message Valid in Msg Obj 2 reg
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_O_STS
+// register.
+//
+//*****************************************************************************
+#define CAN_STS_LEC_MSK 0x00000007 // Last Error Code
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_O_ERR
+// register.
+//
+//*****************************************************************************
+#define CAN_ERR_REC_MASK 0x00007F00 // Receive error counter status
+#define CAN_ERR_TEC_MASK 0x000000FF // Transmit error counter status
+#define CAN_ERR_REC_SHIFT 8 // Receive error counter bit pos
+#define CAN_ERR_TEC_SHIFT 0 // Transmit error counter bit pos
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_O_BIT
+// register.
+//
+//*****************************************************************************
+#define CAN_BIT_TSEG2 0x00007000 // Time segment after sample point
+#define CAN_BIT_TSEG1 0x00000F00 // Time segment before sample point
+#define CAN_BIT_SJW 0x000000C0 // (Re)Synchronization jump width
+#define CAN_BIT_BRP 0x0000003F // Baud rate prescaler
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_O_INT
+// register.
+//
+//*****************************************************************************
+#define CAN_INT_INTID_MSK 0x0000FFFF // Interrupt Identifier
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_O_TST
+// register.
+//
+//*****************************************************************************
+#define CAN_TST_TX_MSK 0x00000060 // Overide control of CAN_TX pin
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_O_BRPE
+// register.
+//
+//*****************************************************************************
+#define CAN_BRPE_BRPE 0x0000000F // Baud rate prescaler extension
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_O_TXRQ1
+// register.
+//
+//*****************************************************************************
+#define CAN_TXRQ1_TXRQST 0x0000FFFF // Transmission Request Bits
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_O_TXRQ2
+// register.
+//
+//*****************************************************************************
+#define CAN_TXRQ2_TXRQST 0x0000FFFF // Transmission Request Bits
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_O_NWDA1
+// register.
+//
+//*****************************************************************************
+#define CAN_NWDA1_NEWDATA 0x0000FFFF // New Data Bits
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_O_NWDA2
+// register.
+//
+//*****************************************************************************
+#define CAN_NWDA2_NEWDATA 0x0000FFFF // New Data Bits
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_O_MSGINT1
+// register.
+//
+//*****************************************************************************
+#define CAN_MSGINT1_INTPND 0x0000FFFF // Interrupt Pending Bits
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_O_MSGINT2
+// register.
+//
+//*****************************************************************************
+#define CAN_MSGINT2_INTPND 0x0000FFFF // Interrupt Pending Bits
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_O_MSGVAL1
+// register.
+//
+//*****************************************************************************
+#define CAN_MSGVAL1_MSGVAL 0x0000FFFF // Message Valid Bits
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_O_MSGVAL2
+// register.
+//
+//*****************************************************************************
+#define CAN_MSGVAL2_MSGVAL 0x0000FFFF // Message Valid Bits
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the reset values of the can
+// registers.
+//
+//*****************************************************************************
+#define CAN_RV_IF1MSK2 0x0000FFFF
+#define CAN_RV_IF1MSK1 0x0000FFFF
+#define CAN_RV_IF2MSK1 0x0000FFFF
+#define CAN_RV_IF2MSK2 0x0000FFFF
+#define CAN_RV_BIT 0x00002301
+#define CAN_RV_CTL 0x00000001
+#define CAN_RV_IF1CRQ 0x00000001
+#define CAN_RV_IF2CRQ 0x00000001
+#define CAN_RV_TXRQ2 0x00000000
+#define CAN_RV_IF2DB1 0x00000000
+#define CAN_RV_INT 0x00000000
+#define CAN_RV_IF1DB2 0x00000000
+#define CAN_RV_BRPE 0x00000000
+#define CAN_RV_IF2DA2 0x00000000
+#define CAN_RV_MSGVAL2 0x00000000
+#define CAN_RV_TXRQ1 0x00000000
+#define CAN_RV_IF1MCTL 0x00000000
+#define CAN_RV_IF1DB1 0x00000000
+#define CAN_RV_STS 0x00000000
+#define CAN_RV_MSGINT1 0x00000000
+#define CAN_RV_IF1DA2 0x00000000
+#define CAN_RV_TST 0x00000000
+#define CAN_RV_IF1ARB1 0x00000000
+#define CAN_RV_IF1ARB2 0x00000000
+#define CAN_RV_NWDA2 0x00000000
+#define CAN_RV_IF2CMSK 0x00000000
+#define CAN_RV_NWDA1 0x00000000
+#define CAN_RV_IF1DA1 0x00000000
+#define CAN_RV_IF2DA1 0x00000000
+#define CAN_RV_IF2MCTL 0x00000000
+#define CAN_RV_MSGVAL1 0x00000000
+#define CAN_RV_IF1CMSK 0x00000000
+#define CAN_RV_ERR 0x00000000
+#define CAN_RV_IF2ARB2 0x00000000
+#define CAN_RV_MSGINT2 0x00000000
+#define CAN_RV_IF2ARB1 0x00000000
+#define CAN_RV_IF2DB2 0x00000000
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_IF1CRQ
+// and CAN_IF1CRQ registers.
+// Note: All bits may not be available in all registers.
+//
+//*****************************************************************************
+#define CAN_IFCRQ_BUSY 0x00008000 // Busy flag status
+#define CAN_IFCRQ_MNUM_MSK 0x0000003F // Message Number
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_IF1CMSK
+// and CAN_IF2CMSK registers.
+// Note: All bits may not be available in all registers.
+//
+//*****************************************************************************
+#define CAN_IFCMSK_WRNRD 0x00000080 // Write, not Read
+#define CAN_IFCMSK_MASK 0x00000040 // Access Mask Bits
+#define CAN_IFCMSK_ARB 0x00000020 // Access Arbitration Bits
+#define CAN_IFCMSK_CONTROL 0x00000010 // Access Control Bits
+#define CAN_IFCMSK_CLRINTPND 0x00000008 // Clear interrupt pending Bit
+#define CAN_IFCMSK_TXRQST 0x00000004 // Access Tx request bit (WRNRD=1)
+#define CAN_IFCMSK_NEWDAT 0x00000004 // Access New Data bit (WRNRD=0)
+#define CAN_IFCMSK_DATAA 0x00000002 // DataA access - bytes 0 to 3
+#define CAN_IFCMSK_DATAB 0x00000001 // DataB access - bytes 4 to 7
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_IF1MSK1
+// and CAN_IF2MSK1 registers.
+// Note: All bits may not be available in all registers.
+//
+//*****************************************************************************
+#define CAN_IFMSK1_MSK 0x0000FFFF // Identifier Mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_IF1MSK2
+// and CAN_IF2MSK2 registers.
+// Note: All bits may not be available in all registers.
+//
+//*****************************************************************************
+#define CAN_IFMSK2_MXTD 0x00008000 // Mask extended identifier
+#define CAN_IFMSK2_MDIR 0x00004000 // Mask message direction
+#define CAN_IFMSK2_MSK 0x00001FFF // Mask identifier
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_IF1ARB1
+// and CAN_IF2ARB1 registers.
+// Note: All bits may not be available in all registers.
+//
+//*****************************************************************************
+#define CAN_IFARB1_ID 0x0000FFFF // Identifier
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_IF1ARB2
+// and CAN_IF2ARB2 registers.
+// Note: All bits may not be available in all registers.
+//
+//*****************************************************************************
+#define CAN_IFARB2_MSGVAL 0x00008000 // Message valid
+#define CAN_IFARB2_XTD 0x00004000 // Extended identifier
+#define CAN_IFARB2_DIR 0x00002000 // Message direction
+#define CAN_IFARB2_ID 0x00001FFF // Message identifier
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_IF1MCTL
+// and CAN_IF2MCTL registers.
+// Note: All bits may not be available in all registers.
+//
+//*****************************************************************************
+#define CAN_IFMCTL_NEWDAT 0x00008000 // New Data
+#define CAN_IFMCTL_MSGLST 0x00004000 // Message lost
+#define CAN_IFMCTL_INTPND 0x00002000 // Interrupt pending
+#define CAN_IFMCTL_UMASK 0x00001000 // Use acceptance mask
+#define CAN_IFMCTL_TXIE 0x00000800 // Transmit interrupt enable
+#define CAN_IFMCTL_RXIE 0x00000400 // Receive interrupt enable
+#define CAN_IFMCTL_RMTEN 0x00000200 // Remote enable
+#define CAN_IFMCTL_TXRQST 0x00000100 // Transmit request
+#define CAN_IFMCTL_EOB 0x00000080 // End of buffer
+#define CAN_IFMCTL_DLC 0x0000000F // Data length code
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_IF1DA1
+// and CAN_IF2DA1 registers.
+// Note: All bits may not be available in all registers.
+//
+//*****************************************************************************
+#define CAN_IFDA1_DATA 0x0000FFFF // Data - bytes 1 and 0
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_IF1DA2
+// and CAN_IF2DA2 registers.
+// Note: All bits may not be available in all registers.
+//
+//*****************************************************************************
+#define CAN_IFDA2_DATA 0x0000FFFF // Data - bytes 3 and 2
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_IF1DB1
+// and CAN_IF2DB1 registers.
+// Note: All bits may not be available in all registers.
+//
+//*****************************************************************************
+#define CAN_IFDB1_DATA 0x0000FFFF // Data - bytes 5 and 4
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the CAN_IF1DB2
+// and CAN_IF2DB2 registers.
+// Note: All bits may not be available in all registers.
+//
+//*****************************************************************************
+#define CAN_IFDB2_DATA 0x0000FFFF // Data - bytes 7 and 6
+
+#endif
+
+#endif // __HW_CAN_H__
diff --git a/inc/hw_comp.h b/inc/hw_comp.h new file mode 100644 index 0000000..cac24c9 --- /dev/null +++ b/inc/hw_comp.h @@ -0,0 +1,305 @@ +//*****************************************************************************
+//
+// hw_comp.h - Macros used when accessing the comparator hardware.
+//
+// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 9453 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_COMP_H__
+#define __HW_COMP_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Comparator register offsets.
+//
+//*****************************************************************************
+#define COMP_O_ACMIS 0x00000000 // Analog Comparator Masked
+ // Interrupt Status
+#define COMP_O_ACRIS 0x00000004 // Analog Comparator Raw Interrupt
+ // Status
+#define COMP_O_ACINTEN 0x00000008 // Analog Comparator Interrupt
+ // Enable
+#define COMP_O_ACREFCTL 0x00000010 // Analog Comparator Reference
+ // Voltage Control
+#define COMP_O_ACSTAT0 0x00000020 // Analog Comparator Status 0
+#define COMP_O_ACCTL0 0x00000024 // Analog Comparator Control 0
+#define COMP_O_ACSTAT1 0x00000040 // Analog Comparator Status 1
+#define COMP_O_ACCTL1 0x00000044 // Analog Comparator Control 1
+#define COMP_O_ACSTAT2 0x00000060 // Analog Comparator Status 2
+#define COMP_O_ACCTL2 0x00000064 // Analog Comparator Control 2
+#define COMP_O_PP 0x00000FC0 // Analog Comparator Peripheral
+ // Properties
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACMIS register.
+//
+//*****************************************************************************
+#define COMP_ACMIS_IN2 0x00000004 // Comparator 2 Masked Interrupt
+ // Status
+#define COMP_ACMIS_IN1 0x00000002 // Comparator 1 Masked Interrupt
+ // Status
+#define COMP_ACMIS_IN0 0x00000001 // Comparator 0 Masked Interrupt
+ // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACRIS register.
+//
+//*****************************************************************************
+#define COMP_ACRIS_IN2 0x00000004 // Comparator 2 Interrupt Status
+#define COMP_ACRIS_IN1 0x00000002 // Comparator 1 Interrupt Status
+#define COMP_ACRIS_IN0 0x00000001 // Comparator 0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACINTEN register.
+//
+//*****************************************************************************
+#define COMP_ACINTEN_IN2 0x00000004 // Comparator 2 Interrupt Enable
+#define COMP_ACINTEN_IN1 0x00000002 // Comparator 1 Interrupt Enable
+#define COMP_ACINTEN_IN0 0x00000001 // Comparator 0 Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACREFCTL
+// register.
+//
+//*****************************************************************************
+#define COMP_ACREFCTL_EN 0x00000200 // Resistor Ladder Enable
+#define COMP_ACREFCTL_RNG 0x00000100 // Resistor Ladder Range
+#define COMP_ACREFCTL_VREF_M 0x0000000F // Resistor Ladder Voltage Ref
+#define COMP_ACREFCTL_VREF_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT0 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT0_OVAL 0x00000002 // Comparator Output Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL0 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL0_TOEN 0x00000800 // Trigger Output Enable
+#define COMP_ACCTL0_ASRCP_M 0x00000600 // Analog Source Positive
+#define COMP_ACCTL0_ASRCP_PIN 0x00000000 // Pin value of Cn+
+#define COMP_ACCTL0_ASRCP_PIN0 0x00000200 // Pin value of C0+
+#define COMP_ACCTL0_ASRCP_REF 0x00000400 // Internal voltage reference
+#define COMP_ACCTL0_TSLVAL 0x00000080 // Trigger Sense Level Value
+#define COMP_ACCTL0_TSEN_M 0x00000060 // Trigger Sense
+#define COMP_ACCTL0_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
+#define COMP_ACCTL0_TSEN_FALL 0x00000020 // Falling edge
+#define COMP_ACCTL0_TSEN_RISE 0x00000040 // Rising edge
+#define COMP_ACCTL0_TSEN_BOTH 0x00000060 // Either edge
+#define COMP_ACCTL0_ISLVAL 0x00000010 // Interrupt Sense Level Value
+#define COMP_ACCTL0_ISEN_M 0x0000000C // Interrupt Sense
+#define COMP_ACCTL0_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
+#define COMP_ACCTL0_ISEN_FALL 0x00000004 // Falling edge
+#define COMP_ACCTL0_ISEN_RISE 0x00000008 // Rising edge
+#define COMP_ACCTL0_ISEN_BOTH 0x0000000C // Either edge
+#define COMP_ACCTL0_CINV 0x00000002 // Comparator Output Invert
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT1 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT1_OVAL 0x00000002 // Comparator Output Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL1 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL1_TOEN 0x00000800 // Trigger Output Enable
+#define COMP_ACCTL1_ASRCP_M 0x00000600 // Analog Source Positive
+#define COMP_ACCTL1_ASRCP_PIN 0x00000000 // Pin value of Cn+
+#define COMP_ACCTL1_ASRCP_PIN0 0x00000200 // Pin value of C0+
+#define COMP_ACCTL1_ASRCP_REF 0x00000400 // Internal voltage reference
+ // (VIREF)
+#define COMP_ACCTL1_TSLVAL 0x00000080 // Trigger Sense Level Value
+#define COMP_ACCTL1_TSEN_M 0x00000060 // Trigger Sense
+#define COMP_ACCTL1_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
+#define COMP_ACCTL1_TSEN_FALL 0x00000020 // Falling edge
+#define COMP_ACCTL1_TSEN_RISE 0x00000040 // Rising edge
+#define COMP_ACCTL1_TSEN_BOTH 0x00000060 // Either edge
+#define COMP_ACCTL1_ISLVAL 0x00000010 // Interrupt Sense Level Value
+#define COMP_ACCTL1_ISEN_M 0x0000000C // Interrupt Sense
+#define COMP_ACCTL1_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
+#define COMP_ACCTL1_ISEN_FALL 0x00000004 // Falling edge
+#define COMP_ACCTL1_ISEN_RISE 0x00000008 // Rising edge
+#define COMP_ACCTL1_ISEN_BOTH 0x0000000C // Either edge
+#define COMP_ACCTL1_CINV 0x00000002 // Comparator Output Invert
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT2 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT2_OVAL 0x00000002 // Comparator Output Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL2 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL2_TOEN 0x00000800 // Trigger Output Enable
+#define COMP_ACCTL2_ASRCP_M 0x00000600 // Analog Source Positive
+#define COMP_ACCTL2_ASRCP_PIN 0x00000000 // Pin value of Cn+
+#define COMP_ACCTL2_ASRCP_PIN0 0x00000200 // Pin value of C0+
+#define COMP_ACCTL2_ASRCP_REF 0x00000400 // Internal voltage reference
+ // (VIREF)
+#define COMP_ACCTL2_TSLVAL 0x00000080 // Trigger Sense Level Value
+#define COMP_ACCTL2_TSEN_M 0x00000060 // Trigger Sense
+#define COMP_ACCTL2_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
+#define COMP_ACCTL2_TSEN_FALL 0x00000020 // Falling edge
+#define COMP_ACCTL2_TSEN_RISE 0x00000040 // Rising edge
+#define COMP_ACCTL2_TSEN_BOTH 0x00000060 // Either edge
+#define COMP_ACCTL2_ISLVAL 0x00000010 // Interrupt Sense Level Value
+#define COMP_ACCTL2_ISEN_M 0x0000000C // Interrupt Sense
+#define COMP_ACCTL2_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
+#define COMP_ACCTL2_ISEN_FALL 0x00000004 // Falling edge
+#define COMP_ACCTL2_ISEN_RISE 0x00000008 // Rising edge
+#define COMP_ACCTL2_ISEN_BOTH 0x0000000C // Either edge
+#define COMP_ACCTL2_CINV 0x00000002 // Comparator Output Invert
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_PP register.
+//
+//*****************************************************************************
+#define COMP_PP_C2O 0x00040000 // Comparator Output 2 Present
+#define COMP_PP_C1O 0x00020000 // Comparator Output 1 Present
+#define COMP_PP_C0O 0x00010000 // Comparator Output 0 Present
+#define COMP_PP_CMP2 0x00000004 // Comparator 2 Present
+#define COMP_PP_CMP1 0x00000002 // Comparator 1 Present
+#define COMP_PP_CMP0 0x00000001 // Comparator 0 Present
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the Comparator register offsets.
+//
+//*****************************************************************************
+#define COMP_O_MIS 0x00000000 // Interrupt status register
+#define COMP_O_RIS 0x00000004 // Raw interrupt status register
+#define COMP_O_INTEN 0x00000008 // Interrupt enable register
+#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the COMP_O_REFCTL
+// register.
+//
+//*****************************************************************************
+#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable
+#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range
+#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask
+#define COMP_REFCTL_VREF_SHIFT 0
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the COMP_MIS,
+// COMP_RIS, and COMP_INTEN registers.
+//
+//*****************************************************************************
+#define COMP_INT_2 0x00000004 // Comp2 interrupt
+#define COMP_INT_1 0x00000002 // Comp1 interrupt
+#define COMP_INT_0 0x00000001 // Comp0 interrupt
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the COMP_ACSTAT0,
+// COMP_ACSTAT1, and COMP_ACSTAT2 registers.
+//
+//*****************************************************************************
+#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the COMP_ACCTL0,
+// COMP_ACCTL1, and COMP_ACCTL2 registers.
+//
+//*****************************************************************************
+#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable
+#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask
+#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin
+#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin
+#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference
+#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved
+#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable
+#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select
+#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask
+#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense
+#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge
+#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge
+#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges
+#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select
+#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask
+#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense
+#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge
+#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge
+#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges
+#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the reset values for the comparator
+// registers.
+//
+//*****************************************************************************
+#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register
+#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register
+#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register
+#define COMP_RV_RIS 0x00000000 // Raw interrupt status register
+#define COMP_RV_INTEN 0x00000000 // Interrupt enable register
+#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register
+#define COMP_RV_MIS 0x00000000 // Interrupt status register
+#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register
+#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register
+#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg
+
+#endif
+
+#endif // __HW_COMP_H__
diff --git a/inc/hw_eeprom.h b/inc/hw_eeprom.h new file mode 100644 index 0000000..051873f --- /dev/null +++ b/inc/hw_eeprom.h @@ -0,0 +1,245 @@ +//*****************************************************************************
+//
+// hw_eeprom.h - Macros used when accessing the EEPROM controller.
+//
+// Copyright (c) 2011-2012 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 9453 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_EEPROM_H__
+#define __HW_EEPROM_H__
+
+//*****************************************************************************
+//
+// The following are defines for the EEPROM register offsets.
+//
+//*****************************************************************************
+#define EEPROM_EESIZE 0x400AF000 // EEPROM Size Information
+#define EEPROM_EEBLOCK 0x400AF004 // EEPROM Current Block
+#define EEPROM_EEOFFSET 0x400AF008 // EEPROM Current Offset
+#define EEPROM_EERDWR 0x400AF010 // EEPROM Read-Write
+#define EEPROM_EERDWRINC 0x400AF014 // EEPROM Read-Write with Increment
+#define EEPROM_EEDONE 0x400AF018 // EEPROM Done Status
+#define EEPROM_EESUPP 0x400AF01C // EEPROM Support Control and
+ // Status
+#define EEPROM_EEUNLOCK 0x400AF020 // EEPROM Unlock
+#define EEPROM_EEPROT 0x400AF030 // EEPROM Protection
+#define EEPROM_EEPASS0 0x400AF034 // EEPROM Password
+#define EEPROM_EEPASS1 0x400AF038 // EEPROM Password
+#define EEPROM_EEPASS2 0x400AF03C // EEPROM Password
+#define EEPROM_EEINT 0x400AF040 // EEPROM Interrupt
+#define EEPROM_EEHIDE 0x400AF050 // EEPROM Block Hide
+#define EEPROM_EEDBGME 0x400AF080 // EEPROM Debug Mass Erase
+#define EEPROM_PP 0x400AFFC0 // EEPROM Peripheral Properties
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EESIZE register.
+//
+//*****************************************************************************
+#define EEPROM_EESIZE_WORDCNT_M 0x0000FFFF // Number of 32-Bit Words
+#define EEPROM_EESIZE_BLKCNT_M 0x07FF0000 // Number of 16-Word Blocks
+#define EEPROM_EESIZE_WORDCNT_S 0
+#define EEPROM_EESIZE_BLKCNT_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEBLOCK register.
+//
+//*****************************************************************************
+#define EEPROM_EEBLOCK_BLOCK_M 0x0000FFFF // Current Block
+#define EEPROM_EEBLOCK_BLOCK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEOFFSET
+// register.
+//
+//*****************************************************************************
+#define EEPROM_EEOFFSET_OFFSET_M \
+ 0x0000000F // Current Address Offset
+#define EEPROM_EEOFFSET_OFFSET_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EERDWR register.
+//
+//*****************************************************************************
+#define EEPROM_EERDWR_VALUE_M 0xFFFFFFFF // EEPROM Read or Write Data
+#define EEPROM_EERDWR_VALUE_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EERDWRINC
+// register.
+//
+//*****************************************************************************
+#define EEPROM_EERDWRINC_VALUE_M \
+ 0xFFFFFFFF // EEPROM Read or Write Data with
+ // Increment
+#define EEPROM_EERDWRINC_VALUE_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEDONE register.
+//
+//*****************************************************************************
+#define EEPROM_EEDONE_WORKING 0x00000001 // EEPROM Working
+#define EEPROM_EEDONE_WKERASE 0x00000004 // Working on an Erase
+#define EEPROM_EEDONE_WKCOPY 0x00000008 // Working on a Copy
+#define EEPROM_EEDONE_NOPERM 0x00000010 // Write Without Permission
+#define EEPROM_EEDONE_WRBUSY 0x00000020 // Write Busy
+#define EEPROM_EEDONE_INVPL 0x00000100 // Invalid Program Voltage Level
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EESUPP register.
+//
+//*****************************************************************************
+#define EEPROM_EESUPP_START 0x00000001 // Start Erase
+#define EEPROM_EESUPP_EREQ 0x00000002 // Erase Required
+#define EEPROM_EESUPP_ERETRY 0x00000004 // Erase Must Be Retried
+#define EEPROM_EESUPP_PRETRY 0x00000008 // Programming Must Be Retried
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEUNLOCK
+// register.
+//
+//*****************************************************************************
+#define EEPROM_EEUNLOCK_UNLOCK_M \
+ 0xFFFFFFFF // EEPROM Unlock
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEPROT register.
+//
+//*****************************************************************************
+#define EEPROM_EEPROT_PROT_M 0x00000007 // Protection Control
+#define EEPROM_EEPROT_PROT_RWNPW \
+ 0x00000000 // This setting is the default. If
+ // there is no password, the block
+ // is not protected and is readable
+ // and writable
+#define EEPROM_EEPROT_PROT_RWPW 0x00000001 // If there is a password, the
+ // block is readable or writable
+ // only when unlocked
+#define EEPROM_EEPROT_PROT_RONPW \
+ 0x00000002 // If there is no password, the
+ // block is readable, not writable
+#define EEPROM_EEPROT_ACC 0x00000008 // Access Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEPASS0 register.
+//
+//*****************************************************************************
+#define EEPROM_EEPASS0_PASS_M 0xFFFFFFFF // Password
+#define EEPROM_EEPASS0_PASS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEPASS1 register.
+//
+//*****************************************************************************
+#define EEPROM_EEPASS1_PASS_M 0xFFFFFFFF // Password
+#define EEPROM_EEPASS1_PASS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEPASS2 register.
+//
+//*****************************************************************************
+#define EEPROM_EEPASS2_PASS_M 0xFFFFFFFF // Password
+#define EEPROM_EEPASS2_PASS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEINT register.
+//
+//*****************************************************************************
+#define EEPROM_EEINT_INT 0x00000001 // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEHIDE register.
+//
+//*****************************************************************************
+#define EEPROM_EEHIDE_HN_M 0xFFFFFFFE // Hide Block
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEDBGME register.
+//
+//*****************************************************************************
+#define EEPROM_EEDBGME_ME 0x00000001 // Mass Erase
+#define EEPROM_EEDBGME_KEY_M 0xFFFF0000 // Erase Key
+#define EEPROM_EEDBGME_KEY_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_PP register.
+//
+//*****************************************************************************
+#define EEPROM_PP_SIZE_M 0x0000001F // EEPROM Size
+#define EEPROM_PP_SIZE_S 0
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the EEPROM register offsets.
+//
+//*****************************************************************************
+#define EEPROM_EEPROMPP 0x400AFFC0 // EEPROM
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// EEPROM_EEPROMPP register.
+//
+//*****************************************************************************
+#define EEPROM_EEPROMPP_SIZE_M 0x0000001F // EEPROM Size
+#define EEPROM_EEPROMPP_SIZE_S 0
+
+#endif
+
+#endif // __HW_EEPROM_H__
diff --git a/inc/hw_epi.h b/inc/hw_epi.h new file mode 100644 index 0000000..0084715 --- /dev/null +++ b/inc/hw_epi.h @@ -0,0 +1,547 @@ +//*****************************************************************************
+//
+// hw_epi.h - Macros for use in accessing the EPI registers.
+//
+// Copyright (c) 2008-2012 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 9453 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_EPI_H__
+#define __HW_EPI_H__
+
+//*****************************************************************************
+//
+// The following are defines for the External Peripheral Interface register
+// offsets.
+//
+//*****************************************************************************
+#define EPI_O_CFG 0x00000000 // EPI Configuration
+#define EPI_O_BAUD 0x00000004 // EPI Main Baud Rate
+#define EPI_O_HB16CFG 0x00000010 // EPI Host-Bus 16 Configuration
+#define EPI_O_GPCFG 0x00000010 // EPI General-Purpose
+ // Configuration
+#define EPI_O_SDRAMCFG 0x00000010 // EPI SDRAM Configuration
+#define EPI_O_HB8CFG 0x00000010 // EPI Host-Bus 8 Configuration
+#define EPI_O_HB8CFG2 0x00000014 // EPI Host-Bus 8 Configuration 2
+#define EPI_O_HB16CFG2 0x00000014 // EPI Host-Bus 16 Configuration 2
+#define EPI_O_GPCFG2 0x00000014 // EPI General-Purpose
+ // Configuration 2
+#define EPI_O_ADDRMAP 0x0000001C // EPI Address Map
+#define EPI_O_RSIZE0 0x00000020 // EPI Read Size 0
+#define EPI_O_RADDR0 0x00000024 // EPI Read Address 0
+#define EPI_O_RPSTD0 0x00000028 // EPI Non-Blocking Read Data 0
+#define EPI_O_RSIZE1 0x00000030 // EPI Read Size 1
+#define EPI_O_RADDR1 0x00000034 // EPI Read Address 1
+#define EPI_O_RPSTD1 0x00000038 // EPI Non-Blocking Read Data 1
+#define EPI_O_STAT 0x00000060 // EPI Status
+#define EPI_O_RFIFOCNT 0x0000006C // EPI Read FIFO Count
+#define EPI_O_READFIFO0 0x00000070 // EPI Read FIFO
+#define EPI_O_READFIFO 0x00000070 // EPI Read FIFO
+#define EPI_O_READFIFO1 0x00000074 // EPI Read FIFO Alias 1
+#define EPI_O_READFIFO2 0x00000078 // EPI Read FIFO Alias 2
+#define EPI_O_READFIFO3 0x0000007C // EPI Read FIFO Alias 3
+#define EPI_O_READFIFO4 0x00000080 // EPI Read FIFO Alias 4
+#define EPI_O_READFIFO5 0x00000084 // EPI Read FIFO Alias 5
+#define EPI_O_READFIFO6 0x00000088 // EPI Read FIFO Alias 6
+#define EPI_O_READFIFO7 0x0000008C // EPI Read FIFO Alias 7
+#define EPI_O_FIFOLVL 0x00000200 // EPI FIFO Level Selects
+#define EPI_O_WFIFOCNT 0x00000204 // EPI Write FIFO Count
+#define EPI_O_IM 0x00000210 // EPI Interrupt Mask
+#define EPI_O_RIS 0x00000214 // EPI Raw Interrupt Status
+#define EPI_O_MIS 0x00000218 // EPI Masked Interrupt Status
+#define EPI_O_EISC 0x0000021C // EPI Error and Interrupt Status
+ // and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_CFG register.
+//
+//*****************************************************************************
+#define EPI_CFG_BLKEN 0x00000010 // Block Enable
+#define EPI_CFG_MODE_M 0x0000000F // Mode Select
+#define EPI_CFG_MODE_NONE 0x00000000 // General Purpose
+#define EPI_CFG_MODE_SDRAM 0x00000001 // SDRAM
+#define EPI_CFG_MODE_HB8 0x00000002 // 8-Bit Host-Bus (HB8)
+#define EPI_CFG_MODE_HB16 0x00000003 // 16-Bit Host-Bus (HB16)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_BAUD register.
+//
+//*****************************************************************************
+#define EPI_BAUD_COUNT1_M 0xFFFF0000 // Baud Rate Counter 1
+#define EPI_BAUD_COUNT0_M 0x0000FFFF // Baud Rate Counter 0
+#define EPI_BAUD_COUNT1_S 16
+#define EPI_BAUD_COUNT0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16CFG register.
+//
+//*****************************************************************************
+#define EPI_HB16CFG_XFFEN 0x00800000 // External FIFO FULL Enable
+#define EPI_HB16CFG_XFEEN 0x00400000 // External FIFO EMPTY Enable
+#define EPI_HB16CFG_WRHIGH 0x00200000 // WRITE Strobe Polarity
+#define EPI_HB16CFG_RDHIGH 0x00100000 // READ Strobe Polarity
+#define EPI_HB16CFG_MAXWAIT_M 0x0000FF00 // Maximum Wait
+#define EPI_HB16CFG_WRWS_M 0x000000C0 // Write Wait States
+#define EPI_HB16CFG_WRWS_0 0x00000000 // No wait states
+#define EPI_HB16CFG_WRWS_1 0x00000040 // 1 wait state
+#define EPI_HB16CFG_WRWS_2 0x00000080 // 2 wait states
+#define EPI_HB16CFG_WRWS_3 0x000000C0 // 3 wait states
+#define EPI_HB16CFG_RDWS_M 0x00000030 // Read Wait States
+#define EPI_HB16CFG_RDWS_0 0x00000000 // No wait states
+#define EPI_HB16CFG_RDWS_1 0x00000010 // 1 wait state
+#define EPI_HB16CFG_RDWS_2 0x00000020 // 2 wait states
+#define EPI_HB16CFG_RDWS_3 0x00000030 // 3 wait states
+#define EPI_HB16CFG_BSEL 0x00000004 // Byte Select Configuration
+#define EPI_HB16CFG_MODE_M 0x00000003 // Host Bus Sub-Mode
+#define EPI_HB16CFG_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0]
+#define EPI_HB16CFG_MODE_ADNMUX 0x00000001 // ADNONMUX - D[15:0]
+#define EPI_HB16CFG_MODE_SRAM 0x00000002 // Continuous Read - D[15:0]
+#define EPI_HB16CFG_MODE_XFIFO 0x00000003 // XFIFO - D[15:0]
+#define EPI_HB16CFG_MAXWAIT_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_GPCFG register.
+//
+//*****************************************************************************
+#define EPI_GPCFG_CLKPIN 0x80000000 // Clock Pin
+#define EPI_GPCFG_CLKGATE 0x40000000 // Clock Gated
+#define EPI_GPCFG_RDYEN 0x10000000 // Ready Enable
+#define EPI_GPCFG_FRMPIN 0x08000000 // Framing Pin
+#define EPI_GPCFG_FRM50 0x04000000 // 50/50 Frame
+#define EPI_GPCFG_FRMCNT_M 0x03C00000 // Frame Count
+#define EPI_GPCFG_RW 0x00200000 // Read and Write
+#define EPI_GPCFG_WR2CYC 0x00080000 // 2-Cycle Writes
+#define EPI_GPCFG_RD2CYC 0x00040000 // 2-Cycle Reads
+#define EPI_GPCFG_MAXWAIT_M 0x0000FF00 // Maximum Wait
+#define EPI_GPCFG_ASIZE_M 0x00000030 // Address Bus Size
+#define EPI_GPCFG_ASIZE_NONE 0x00000000 // No address
+#define EPI_GPCFG_ASIZE_4BIT 0x00000010 // Up to 4 bits wide
+#define EPI_GPCFG_ASIZE_12BIT 0x00000020 // Up to 12 bits wide. This size
+ // cannot be used with 24-bit data
+#define EPI_GPCFG_ASIZE_20BIT 0x00000030 // Up to 20 bits wide. This size
+ // cannot be used with data sizes
+ // other than 8
+#define EPI_GPCFG_DSIZE_M 0x00000003 // Size of Data Bus
+#define EPI_GPCFG_DSIZE_4BIT 0x00000000 // 8 Bits Wide (EPI0S0 to EPI0S7)
+#define EPI_GPCFG_DSIZE_16BIT 0x00000001 // 16 Bits Wide (EPI0S0 to EPI0S15)
+#define EPI_GPCFG_DSIZE_24BIT 0x00000002 // 24 Bits Wide (EPI0S0 to EPI0S23)
+#define EPI_GPCFG_DSIZE_32BIT 0x00000003 // 32 Bits Wide (EPI0S0 to EPI0S31)
+#define EPI_GPCFG_FRMCNT_S 22
+#define EPI_GPCFG_MAXWAIT_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_SDRAMCFG register.
+//
+//*****************************************************************************
+#define EPI_SDRAMCFG_FREQ_M 0xC0000000 // EPI Frequency Range
+#define EPI_SDRAMCFG_FREQ_NONE 0x00000000 // 0 - 15 MHz
+#define EPI_SDRAMCFG_FREQ_15MHZ 0x40000000 // 15 - 30 MHz
+#define EPI_SDRAMCFG_FREQ_30MHZ 0x80000000 // 30 - 50 MHz
+#define EPI_SDRAMCFG_RFSH_M 0x07FF0000 // Refresh Counter
+#define EPI_SDRAMCFG_SLEEP 0x00000200 // Sleep Mode
+#define EPI_SDRAMCFG_SIZE_M 0x00000003 // Size of SDRAM
+#define EPI_SDRAMCFG_SIZE_8MB 0x00000000 // 64 megabits (8MB)
+#define EPI_SDRAMCFG_SIZE_16MB 0x00000001 // 128 megabits (16MB)
+#define EPI_SDRAMCFG_SIZE_32MB 0x00000002 // 256 megabits (32MB)
+#define EPI_SDRAMCFG_SIZE_64MB 0x00000003 // 512 megabits (64MB)
+#define EPI_SDRAMCFG_RFSH_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8CFG register.
+//
+//*****************************************************************************
+#define EPI_HB8CFG_XFFEN 0x00800000 // External FIFO FULL Enable
+#define EPI_HB8CFG_XFEEN 0x00400000 // External FIFO EMPTY Enable
+#define EPI_HB8CFG_WRHIGH 0x00200000 // WRITE Strobe Polarity
+#define EPI_HB8CFG_RDHIGH 0x00100000 // READ Strobe Polarity
+#define EPI_HB8CFG_MAXWAIT_M 0x0000FF00 // Maximum Wait
+#define EPI_HB8CFG_WRWS_M 0x000000C0 // Write Wait States
+#define EPI_HB8CFG_WRWS_0 0x00000000 // No wait states
+#define EPI_HB8CFG_WRWS_1 0x00000040 // 1 wait state
+#define EPI_HB8CFG_WRWS_2 0x00000080 // 2 wait states
+#define EPI_HB8CFG_WRWS_3 0x000000C0 // 3 wait states
+#define EPI_HB8CFG_RDWS_M 0x00000030 // Read Wait States
+#define EPI_HB8CFG_RDWS_0 0x00000000 // No wait states
+#define EPI_HB8CFG_RDWS_1 0x00000010 // 1 wait state
+#define EPI_HB8CFG_RDWS_2 0x00000020 // 2 wait states
+#define EPI_HB8CFG_RDWS_3 0x00000030 // 3 wait states
+#define EPI_HB8CFG_MODE_M 0x00000003 // Host Bus Sub-Mode
+#define EPI_HB8CFG_MODE_MUX 0x00000000 // ADMUX - AD[7:0]
+#define EPI_HB8CFG_MODE_NMUX 0x00000001 // ADNONMUX - D[7:0]
+#define EPI_HB8CFG_MODE_SRAM 0x00000002 // Continuous Read - D[7:0]
+#define EPI_HB8CFG_MODE_FIFO 0x00000003 // XFIFO - D[7:0]
+#define EPI_HB8CFG_MAXWAIT_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8CFG2 register.
+//
+//*****************************************************************************
+#define EPI_HB8CFG2_WORD 0x80000000 // Word Access Mode
+#define EPI_HB8CFG2_CSBAUD 0x04000000 // Chip Select Baud Rate
+#define EPI_HB8CFG2_CSCFG_M 0x03000000 // Chip Select Configuration
+#define EPI_HB8CFG2_CSCFG_ALE 0x00000000 // ALE Configuration
+#define EPI_HB8CFG2_CSCFG_CS 0x01000000 // CSn Configuration
+#define EPI_HB8CFG2_CSCFG_DCS 0x02000000 // Dual CSn Configuration
+#define EPI_HB8CFG2_CSCFG_ADCS 0x03000000 // ALE with Dual CSn Configuration
+#define EPI_HB8CFG2_WRHIGH 0x00200000 // CS1n WRITE Strobe Polarity
+#define EPI_HB8CFG2_RDHIGH 0x00100000 // CS1n READ Strobe Polarity
+#define EPI_HB8CFG2_WRWS_M 0x000000C0 // CS1n Write Wait States
+#define EPI_HB8CFG2_WRWS_0 0x00000000 // No wait states
+#define EPI_HB8CFG2_WRWS_1 0x00000040 // 1 wait state
+#define EPI_HB8CFG2_WRWS_2 0x00000080 // 2 wait states
+#define EPI_HB8CFG2_WRWS_3 0x000000C0 // 3 wait states
+#define EPI_HB8CFG2_RDWS_M 0x00000030 // CS1n Read Wait States
+#define EPI_HB8CFG2_RDWS_0 0x00000000 // No wait states
+#define EPI_HB8CFG2_RDWS_1 0x00000010 // 1 wait state
+#define EPI_HB8CFG2_RDWS_2 0x00000020 // 2 wait states
+#define EPI_HB8CFG2_RDWS_3 0x00000030 // 3 wait states
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16CFG2 register.
+//
+//*****************************************************************************
+#define EPI_HB16CFG2_WORD 0x80000000 // Word Access Mode
+#define EPI_HB16CFG2_CSBAUD 0x04000000 // Chip Select Baud Rate
+#define EPI_HB16CFG2_CSCFG_M 0x03000000 // Chip Select Configuration
+#define EPI_HB16CFG2_CSCFG_ALE 0x00000000 // ALE Configuration
+#define EPI_HB16CFG2_CSCFG_CS 0x01000000 // CSn Configuration
+#define EPI_HB16CFG2_CSCFG_DCS 0x02000000 // Dual CSn Configuration
+#define EPI_HB16CFG2_CSCFG_ADCS 0x03000000 // ALE with Dual CSn Configuration
+#define EPI_HB16CFG2_WRHIGH 0x00200000 // CS1n WRITE Strobe Polarity
+#define EPI_HB16CFG2_RDHIGH 0x00100000 // CS1n READ Strobe Polarity
+#define EPI_HB16CFG2_WRWS_M 0x000000C0 // CS1n Write Wait States
+#define EPI_HB16CFG2_WRWS_0 0x00000000 // No wait states
+#define EPI_HB16CFG2_WRWS_1 0x00000040 // 1 wait state
+#define EPI_HB16CFG2_WRWS_2 0x00000080 // 2 wait states
+#define EPI_HB16CFG2_WRWS_3 0x000000C0 // 3 wait states
+#define EPI_HB16CFG2_RDWS_M 0x00000030 // CS1n Read Wait States
+#define EPI_HB16CFG2_RDWS_0 0x00000000 // No wait states
+#define EPI_HB16CFG2_RDWS_1 0x00000010 // 1 wait state
+#define EPI_HB16CFG2_RDWS_2 0x00000020 // 2 wait states
+#define EPI_HB16CFG2_RDWS_3 0x00000030 // 3 wait states
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_GPCFG2 register.
+//
+//*****************************************************************************
+#define EPI_GPCFG2_WORD 0x80000000 // Word Access Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_ADDRMAP register.
+//
+//*****************************************************************************
+#define EPI_ADDRMAP_EPSZ_M 0x000000C0 // External Peripheral Size
+#define EPI_ADDRMAP_EPSZ_256B 0x00000000 // 256 bytes; lower address range:
+ // 0x00 to 0xFF
+#define EPI_ADDRMAP_EPSZ_64KB 0x00000040 // 64 KB; lower address range:
+ // 0x0000 to 0xFFFF
+#define EPI_ADDRMAP_EPSZ_16MB 0x00000080 // 16 MB; lower address range:
+ // 0x00.0000 to 0xFF.FFFF
+#define EPI_ADDRMAP_EPSZ_512MB 0x000000C0 // 512 MB; lower address range:
+ // 0x000.0000 to 0x1FFF.FFFF
+#define EPI_ADDRMAP_EPADR_M 0x00000030 // External Peripheral Address
+#define EPI_ADDRMAP_EPADR_NONE 0x00000000 // Not mapped
+#define EPI_ADDRMAP_EPADR_A000 0x00000010 // At 0xA000.0000
+#define EPI_ADDRMAP_EPADR_C000 0x00000020 // At 0xC000.0000
+#define EPI_ADDRMAP_ERSZ_M 0x0000000C // External RAM Size
+#define EPI_ADDRMAP_ERSZ_256B 0x00000000 // 256 bytes; lower address range:
+ // 0x00 to 0xFF
+#define EPI_ADDRMAP_ERSZ_64KB 0x00000004 // 64 KB; lower address range:
+ // 0x0000 to 0xFFFF
+#define EPI_ADDRMAP_ERSZ_16MB 0x00000008 // 16 MB; lower address range:
+ // 0x00.0000 to 0xFF.FFFF
+#define EPI_ADDRMAP_ERSZ_512MB 0x0000000C // 512 MB; lower address range:
+ // 0x000.0000 to 0x1FFF.FFFF
+#define EPI_ADDRMAP_ERADR_M 0x00000003 // External RAM Address
+#define EPI_ADDRMAP_ERADR_NONE 0x00000000 // Not mapped
+#define EPI_ADDRMAP_ERADR_6000 0x00000001 // At 0x6000.0000
+#define EPI_ADDRMAP_ERADR_8000 0x00000002 // At 0x8000.0000
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RSIZE0 register.
+//
+//*****************************************************************************
+#define EPI_RSIZE0_SIZE_M 0x00000003 // Current Size
+#define EPI_RSIZE0_SIZE_8BIT 0x00000001 // Byte (8 bits)
+#define EPI_RSIZE0_SIZE_16BIT 0x00000002 // Half-word (16 bits)
+#define EPI_RSIZE0_SIZE_32BIT 0x00000003 // Word (32 bits)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RADDR0 register.
+//
+//*****************************************************************************
+#define EPI_RADDR0_ADDR_M 0x1FFFFFFF // Current Address
+#define EPI_RADDR0_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RPSTD0 register.
+//
+//*****************************************************************************
+#define EPI_RPSTD0_POSTCNT_M 0x00001FFF // Post Count
+#define EPI_RPSTD0_POSTCNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RSIZE1 register.
+//
+//*****************************************************************************
+#define EPI_RSIZE1_SIZE_M 0x00000003 // Current Size
+#define EPI_RSIZE1_SIZE_8BIT 0x00000001 // Byte (8 bits)
+#define EPI_RSIZE1_SIZE_16BIT 0x00000002 // Half-word (16 bits)
+#define EPI_RSIZE1_SIZE_32BIT 0x00000003 // Word (32 bits)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RADDR1 register.
+//
+//*****************************************************************************
+#define EPI_RADDR1_ADDR_M 0x1FFFFFFF // Current Address
+#define EPI_RADDR1_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RPSTD1 register.
+//
+//*****************************************************************************
+#define EPI_RPSTD1_POSTCNT_M 0x00001FFF // Post Count
+#define EPI_RPSTD1_POSTCNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_STAT register.
+//
+//*****************************************************************************
+#define EPI_STAT_CELOW 0x00000200 // Clock Enable Low
+#define EPI_STAT_XFFULL 0x00000100 // External FIFO Full
+#define EPI_STAT_XFEMPTY 0x00000080 // External FIFO Empty
+#define EPI_STAT_INITSEQ 0x00000040 // Initialization Sequence
+#define EPI_STAT_WBUSY 0x00000020 // Write Busy
+#define EPI_STAT_NBRBUSY 0x00000010 // Non-Blocking Read Busy
+#define EPI_STAT_ACTIVE 0x00000001 // Register Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RFIFOCNT register.
+//
+//*****************************************************************************
+#define EPI_RFIFOCNT_COUNT_M 0x0000000F // FIFO Count
+#define EPI_RFIFOCNT_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO0
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO0_DATA_M 0xFFFFFFFF // Reads Data
+#define EPI_READFIFO0_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO register.
+//
+//*****************************************************************************
+#define EPI_READFIFO_DATA_M 0xFFFFFFFF // Reads Data
+#define EPI_READFIFO_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO1
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO1_DATA_M 0xFFFFFFFF // Reads Data
+#define EPI_READFIFO1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO2
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO2_DATA_M 0xFFFFFFFF // Reads Data
+#define EPI_READFIFO2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO3
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO3_DATA_M 0xFFFFFFFF // Reads Data
+#define EPI_READFIFO3_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO4
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO4_DATA_M 0xFFFFFFFF // Reads Data
+#define EPI_READFIFO4_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO5
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO5_DATA_M 0xFFFFFFFF // Reads Data
+#define EPI_READFIFO5_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO6
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO6_DATA_M 0xFFFFFFFF // Reads Data
+#define EPI_READFIFO6_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO7
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO7_DATA_M 0xFFFFFFFF // Reads Data
+#define EPI_READFIFO7_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_FIFOLVL register.
+//
+//*****************************************************************************
+#define EPI_FIFOLVL_WFERR 0x00020000 // Write Full Error
+#define EPI_FIFOLVL_RSERR 0x00010000 // Read Stall Error
+#define EPI_FIFOLVL_WRFIFO_M 0x00000070 // Write FIFO
+#define EPI_FIFOLVL_WRFIFO_EMPT 0x00000000 // Trigger when there are any
+ // spaces available in the WFIFO
+#define EPI_FIFOLVL_WRFIFO_1_4 0x00000020 // Trigger when there are up to 3
+ // spaces available in the WFIFO
+#define EPI_FIFOLVL_WRFIFO_1_2 0x00000030 // Trigger when there are up to 2
+ // spaces available in the WFIFO
+#define EPI_FIFOLVL_WRFIFO_3_4 0x00000040 // Trigger when there is 1 space
+ // available in the WFIFO
+#define EPI_FIFOLVL_RDFIFO_M 0x00000007 // Read FIFO
+#define EPI_FIFOLVL_RDFIFO_EMPT 0x00000000 // Empty
+#define EPI_FIFOLVL_RDFIFO_1_8 0x00000001 // Trigger when there are 1 or more
+ // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_1_4 0x00000002 // Trigger when there are 2 or more
+ // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_1_2 0x00000003 // Trigger when there are 4 or more
+ // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_3_4 0x00000004 // Trigger when there are 6 or more
+ // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_7_8 0x00000005 // Trigger when there are 7 or more
+ // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_FULL 0x00000006 // Trigger when there are 8 entries
+ // in the NBRFIFO
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_WFIFOCNT register.
+//
+//*****************************************************************************
+#define EPI_WFIFOCNT_WTAV_M 0x00000007 // Available Write Transactions
+#define EPI_WFIFOCNT_WTAV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_IM register.
+//
+//*****************************************************************************
+#define EPI_IM_WRIM 0x00000004 // Write FIFO Empty Interrupt Mask
+#define EPI_IM_RDIM 0x00000002 // Read FIFO Full Interrupt Mask
+#define EPI_IM_ERRIM 0x00000001 // Error Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RIS register.
+//
+//*****************************************************************************
+#define EPI_RIS_WRRIS 0x00000004 // Write Raw Interrupt Status
+#define EPI_RIS_RDRIS 0x00000002 // Read Raw Interrupt Status
+#define EPI_RIS_ERRRIS 0x00000001 // Error Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_MIS register.
+//
+//*****************************************************************************
+#define EPI_MIS_WRMIS 0x00000004 // Write Masked Interrupt Status
+#define EPI_MIS_RDMIS 0x00000002 // Read Masked Interrupt Status
+#define EPI_MIS_ERRMIS 0x00000001 // Error Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_EISC register.
+//
+//*****************************************************************************
+#define EPI_EISC_WTFULL 0x00000004 // Write FIFO Full Error
+#define EPI_EISC_RSTALL 0x00000002 // Read Stalled Error
+#define EPI_EISC_TOUT 0x00000001 // Timeout Error
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the EPI_O_BAUD
+// register.
+//
+//*****************************************************************************
+#define EPI_BAUD_COUNT_M 0x0000FFFF // Baud Rate Counter
+#define EPI_BAUD_COUNT_S 0
+
+#endif
+
+#endif // __HW_EPI_H__
diff --git a/inc/hw_ethernet.h b/inc/hw_ethernet.h new file mode 100644 index 0000000..6b36431 --- /dev/null +++ b/inc/hw_ethernet.h @@ -0,0 +1,703 @@ +//*****************************************************************************
+//
+// hw_ethernet.h - Macros used when accessing the Ethernet hardware.
+//
+// Copyright (c) 2006-2012 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 9453 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_ETHERNET_H__
+#define __HW_ETHERNET_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Ethernet MAC register offsets.
+//
+//*****************************************************************************
+#define MAC_O_RIS 0x00000000 // Ethernet MAC Raw Interrupt
+ // Status/Acknowledge
+#define MAC_O_IACK 0x00000000 // Ethernet MAC Raw Interrupt
+ // Status/Acknowledge
+#define MAC_O_IM 0x00000004 // Ethernet MAC Interrupt Mask
+#define MAC_O_RCTL 0x00000008 // Ethernet MAC Receive Control
+#define MAC_O_TCTL 0x0000000C // Ethernet MAC Transmit Control
+#define MAC_O_DATA 0x00000010 // Ethernet MAC Data
+#define MAC_O_IA0 0x00000014 // Ethernet MAC Individual Address
+ // 0
+#define MAC_O_IA1 0x00000018 // Ethernet MAC Individual Address
+ // 1
+#define MAC_O_THR 0x0000001C // Ethernet MAC Threshold
+#define MAC_O_MCTL 0x00000020 // Ethernet MAC Management Control
+#define MAC_O_MDV 0x00000024 // Ethernet MAC Management Divider
+#define MAC_O_MADD 0x00000028 // Ethernet MAC Management Address
+#define MAC_O_MTXD 0x0000002C // Ethernet MAC Management Transmit
+ // Data
+#define MAC_O_MRXD 0x00000030 // Ethernet MAC Management Receive
+ // Data
+#define MAC_O_NP 0x00000034 // Ethernet MAC Number of Packets
+#define MAC_O_TR 0x00000038 // Ethernet MAC Transmission
+ // Request
+#define MAC_O_TS 0x0000003C // Ethernet MAC Timer Support
+#define MAC_O_LED 0x00000040 // Ethernet MAC LED Encoding
+#define MAC_O_MDIX 0x00000044 // Ethernet PHY MDIX
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_RIS register.
+//
+//*****************************************************************************
+#define MAC_RIS_PHYINT 0x00000040 // PHY Interrupt
+#define MAC_RIS_MDINT 0x00000020 // MII Transaction Complete
+#define MAC_RIS_RXER 0x00000010 // Receive Error
+#define MAC_RIS_FOV 0x00000008 // FIFO Overrun
+#define MAC_RIS_TXEMP 0x00000004 // Transmit FIFO Empty
+#define MAC_RIS_TXER 0x00000002 // Transmit Error
+#define MAC_RIS_RXINT 0x00000001 // Packet Received
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IACK register.
+//
+//*****************************************************************************
+#define MAC_IACK_PHYINT 0x00000040 // Clear PHY Interrupt
+#define MAC_IACK_MDINT 0x00000020 // Clear MII Transaction Complete
+#define MAC_IACK_RXER 0x00000010 // Clear Receive Error
+#define MAC_IACK_FOV 0x00000008 // Clear FIFO Overrun
+#define MAC_IACK_TXEMP 0x00000004 // Clear Transmit FIFO Empty
+#define MAC_IACK_TXER 0x00000002 // Clear Transmit Error
+#define MAC_IACK_RXINT 0x00000001 // Clear Packet Received
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IM register.
+//
+//*****************************************************************************
+#define MAC_IM_PHYINTM 0x00000040 // Mask PHY Interrupt
+#define MAC_IM_MDINTM 0x00000020 // Mask MII Transaction Complete
+#define MAC_IM_RXERM 0x00000010 // Mask Receive Error
+#define MAC_IM_FOVM 0x00000008 // Mask FIFO Overrun
+#define MAC_IM_TXEMPM 0x00000004 // Mask Transmit FIFO Empty
+#define MAC_IM_TXERM 0x00000002 // Mask Transmit Error
+#define MAC_IM_RXINTM 0x00000001 // Mask Packet Received
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_RCTL register.
+//
+//*****************************************************************************
+#define MAC_RCTL_RSTFIFO 0x00000010 // Clear Receive FIFO
+#define MAC_RCTL_BADCRC 0x00000008 // Enable Reject Bad CRC
+#define MAC_RCTL_PRMS 0x00000004 // Enable Promiscuous Mode
+#define MAC_RCTL_AMUL 0x00000002 // Enable Multicast Frames
+#define MAC_RCTL_RXEN 0x00000001 // Enable Receiver
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_TCTL register.
+//
+//*****************************************************************************
+#define MAC_TCTL_DUPLEX 0x00000010 // Enable Duplex Mode
+#define MAC_TCTL_CRC 0x00000004 // Enable CRC Generation
+#define MAC_TCTL_PADEN 0x00000002 // Enable Packet Padding
+#define MAC_TCTL_TXEN 0x00000001 // Enable Transmitter
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_DATA register.
+//
+//*****************************************************************************
+#define MAC_DATA_TXDATA_M 0xFFFFFFFF // Transmit FIFO Data
+#define MAC_DATA_RXDATA_M 0xFFFFFFFF // Receive FIFO Data
+#define MAC_DATA_RXDATA_S 0
+#define MAC_DATA_TXDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IA0 register.
+//
+//*****************************************************************************
+#define MAC_IA0_MACOCT4_M 0xFF000000 // MAC Address Octet 4
+#define MAC_IA0_MACOCT3_M 0x00FF0000 // MAC Address Octet 3
+#define MAC_IA0_MACOCT2_M 0x0000FF00 // MAC Address Octet 2
+#define MAC_IA0_MACOCT1_M 0x000000FF // MAC Address Octet 1
+#define MAC_IA0_MACOCT4_S 24
+#define MAC_IA0_MACOCT3_S 16
+#define MAC_IA0_MACOCT2_S 8
+#define MAC_IA0_MACOCT1_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_IA1 register.
+//
+//*****************************************************************************
+#define MAC_IA1_MACOCT6_M 0x0000FF00 // MAC Address Octet 6
+#define MAC_IA1_MACOCT5_M 0x000000FF // MAC Address Octet 5
+#define MAC_IA1_MACOCT6_S 8
+#define MAC_IA1_MACOCT5_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_THR register.
+//
+//*****************************************************************************
+#define MAC_THR_THRESH_M 0x0000003F // Threshold Value
+#define MAC_THR_THRESH_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MCTL register.
+//
+//*****************************************************************************
+#define MAC_MCTL_REGADR_M 0x000000F8 // MII Register Address
+#define MAC_MCTL_WRITE 0x00000002 // MII Register Transaction Type
+#define MAC_MCTL_START 0x00000001 // MII Register Transaction Enable
+#define MAC_MCTL_REGADR_S 3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MDV register.
+//
+//*****************************************************************************
+#define MAC_MDV_DIV_M 0x000000FF // Clock Divider
+#define MAC_MDV_DIV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MADD register.
+//
+//*****************************************************************************
+#define MAC_MADD_PHYADR_M 0x0000001F // PHY Address
+#define MAC_MADD_PHYADR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MTXD register.
+//
+//*****************************************************************************
+#define MAC_MTXD_MDTX_M 0x0000FFFF // MII Register Transmit Data
+#define MAC_MTXD_MDTX_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MRXD register.
+//
+//*****************************************************************************
+#define MAC_MRXD_MDRX_M 0x0000FFFF // MII Register Receive Data
+#define MAC_MRXD_MDRX_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_NP register.
+//
+//*****************************************************************************
+#define MAC_NP_NPR_M 0x0000003F // Number of Packets in Receive
+ // FIFO
+#define MAC_NP_NPR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_TR register.
+//
+//*****************************************************************************
+#define MAC_TR_NEWTX 0x00000001 // New Transmission
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_TS register.
+//
+//*****************************************************************************
+#define MAC_TS_TSEN 0x00000001 // Time Stamp Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_LED register.
+//
+//*****************************************************************************
+#define MAC_LED_LED1_M 0x00000F00 // LED1 Source
+#define MAC_LED_LED1_LINK 0x00000000 // Link OK
+#define MAC_LED_LED1_RXTX 0x00000100 // RX or TX Activity (Default LED1)
+#define MAC_LED_LED1_100 0x00000500 // 100BASE-TX mode
+#define MAC_LED_LED1_10 0x00000600 // 10BASE-T mode
+#define MAC_LED_LED1_DUPLEX 0x00000700 // Full-Duplex
+#define MAC_LED_LED1_LINKACT 0x00000800 // Link OK & Blink=RX or TX
+ // Activity
+#define MAC_LED_LED0_M 0x0000000F // LED0 Source
+#define MAC_LED_LED0_LINK 0x00000000 // Link OK (Default LED0)
+#define MAC_LED_LED0_RXTX 0x00000001 // RX or TX Activity
+#define MAC_LED_LED0_100 0x00000005 // 100BASE-TX mode
+#define MAC_LED_LED0_10 0x00000006 // 10BASE-T mode
+#define MAC_LED_LED0_DUPLEX 0x00000007 // Full-Duplex
+#define MAC_LED_LED0_LINKACT 0x00000008 // Link OK & Blink=RX or TX
+ // Activity
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the MAC_O_MDIX register.
+//
+//*****************************************************************************
+#define MAC_MDIX_EN 0x00000001 // MDI/MDI-X Enable
+
+//*****************************************************************************
+//
+// The following are defines for the Ethernet Controller PHY registers.
+//
+//*****************************************************************************
+#define PHY_MR0 0x00000000 // Ethernet PHY Management Register
+ // 0 - Control
+#define PHY_MR1 0x00000001 // Ethernet PHY Management Register
+ // 1 - Status
+#define PHY_MR2 0x00000002 // Ethernet PHY Management Register
+ // 2 - PHY Identifier 1
+#define PHY_MR3 0x00000003 // Ethernet PHY Management Register
+ // 3 - PHY Identifier 2
+#define PHY_MR4 0x00000004 // Ethernet PHY Management Register
+ // 4 - Auto-Negotiation
+ // Advertisement
+#define PHY_MR5 0x00000005 // Ethernet PHY Management Register
+ // 5 - Auto-Negotiation Link
+ // Partner Base Page Ability
+#define PHY_MR6 0x00000006 // Ethernet PHY Management Register
+ // 6 - Auto-Negotiation Expansion
+#define PHY_MR16 0x00000010 // Ethernet PHY Management Register
+ // 16 - Vendor-Specific
+#define PHY_MR17 0x00000011 // Ethernet PHY Management Register
+ // 17 - Mode Control/Status
+#define PHY_MR18 0x00000012 // Ethernet PHY Management Register
+ // 18 - Diagnostic
+#define PHY_MR19 0x00000013 // Ethernet PHY Management Register
+ // 19 - Transceiver Control
+#define PHY_MR23 0x00000017 // Ethernet PHY Management Register
+ // 23 - LED Configuration
+#define PHY_MR24 0x00000018 // Ethernet PHY Management Register
+ // 24 -MDI/MDIX Control
+#define PHY_MR27 0x0000001B // Ethernet PHY Management Register
+ // 27 - Special Control/Status
+#define PHY_MR29 0x0000001D // Ethernet PHY Management Register
+ // 29 - Interrupt Status
+#define PHY_MR30 0x0000001E // Ethernet PHY Management Register
+ // 30 - Interrupt Mask
+#define PHY_MR31 0x0000001F // Ethernet PHY Management Register
+ // 31 - PHY Special Control/Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR0 register.
+//
+//*****************************************************************************
+#define PHY_MR0_RESET 0x00008000 // Reset Registers
+#define PHY_MR0_LOOPBK 0x00004000 // Loopback Mode
+#define PHY_MR0_SPEEDSL 0x00002000 // Speed Select
+#define PHY_MR0_ANEGEN 0x00001000 // Auto-Negotiation Enable
+#define PHY_MR0_PWRDN 0x00000800 // Power Down
+#define PHY_MR0_ISO 0x00000400 // Isolate
+#define PHY_MR0_RANEG 0x00000200 // Restart Auto-Negotiation
+#define PHY_MR0_DUPLEX 0x00000100 // Set Duplex Mode
+#define PHY_MR0_COLT 0x00000080 // Collision Test
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR1 register.
+//
+//*****************************************************************************
+#define PHY_MR1_100X_F 0x00004000 // 100BASE-TX Full-Duplex Mode
+#define PHY_MR1_100X_H 0x00002000 // 100BASE-TX Half-Duplex Mode
+#define PHY_MR1_10T_F 0x00001000 // 10BASE-T Full-Duplex Mode
+#define PHY_MR1_10T_H 0x00000800 // 10BASE-T Half-Duplex Mode
+#define PHY_MR1_MFPS 0x00000040 // Management Frames with Preamble
+ // Suppressed
+#define PHY_MR1_ANEGC 0x00000020 // Auto-Negotiation Complete
+#define PHY_MR1_RFAULT 0x00000010 // Remote Fault
+#define PHY_MR1_ANEGA 0x00000008 // Auto-Negotiation
+#define PHY_MR1_LINK 0x00000004 // Link Made
+#define PHY_MR1_JAB 0x00000002 // Jabber Condition
+#define PHY_MR1_EXTD 0x00000001 // Extended Capabilities
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR2 register.
+//
+//*****************************************************************************
+#define PHY_MR2_OUI_M 0x0000FFFF // Organizationally Unique
+ // Identifier[21:6]
+#define PHY_MR2_OUI_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR3 register.
+//
+//*****************************************************************************
+#define PHY_MR3_OUI_M 0x0000FC00 // Organizationally Unique
+ // Identifier[5:0]
+#define PHY_MR3_MN_M 0x000003F0 // Model Number
+#define PHY_MR3_RN_M 0x0000000F // Revision Number
+#define PHY_MR3_OUI_S 10
+#define PHY_MR3_MN_S 4
+#define PHY_MR3_RN_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR4 register.
+//
+//*****************************************************************************
+#define PHY_MR4_NP 0x00008000 // Next Page
+#define PHY_MR4_RF 0x00002000 // Remote Fault
+#define PHY_MR4_A3 0x00000100 // Technology Ability Field [3]
+#define PHY_MR4_A2 0x00000080 // Technology Ability Field [2]
+#define PHY_MR4_A1 0x00000040 // Technology Ability Field [1]
+#define PHY_MR4_A0 0x00000020 // Technology Ability Field [0]
+#define PHY_MR4_S_M 0x0000001F // Selector Field
+#define PHY_MR4_S_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR5 register.
+//
+//*****************************************************************************
+#define PHY_MR5_NP 0x00008000 // Next Page
+#define PHY_MR5_ACK 0x00004000 // Acknowledge
+#define PHY_MR5_RF 0x00002000 // Remote Fault
+#define PHY_MR5_A_M 0x00001FE0 // Technology Ability Field
+#define PHY_MR5_S_M 0x0000001F // Selector Field
+#define PHY_MR5_S_8023 0x00000001 // IEEE Std 802.3
+#define PHY_MR5_S_8029 0x00000002 // IEEE Std 802.9 ISLAN-16T
+#define PHY_MR5_S_8025 0x00000003 // IEEE Std 802.5
+#define PHY_MR5_S_1394 0x00000004 // IEEE Std 1394
+#define PHY_MR5_A_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR6 register.
+//
+//*****************************************************************************
+#define PHY_MR6_PDF 0x00000010 // Parallel Detection Fault
+#define PHY_MR6_LPNPA 0x00000008 // Link Partner is Next Page Able
+#define PHY_MR6_PRX 0x00000002 // New Page Received
+#define PHY_MR6_LPANEGA 0x00000001 // Link Partner is Auto-Negotiation
+ // Able
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR16 register.
+//
+//*****************************************************************************
+#define PHY_MR16_RPTR 0x00008000 // Repeater Mode
+#define PHY_MR16_INPOL 0x00004000 // Interrupt Polarity
+#define PHY_MR16_TXHIM 0x00001000 // Transmit High Impedance Mode
+#define PHY_MR16_SQEI 0x00000800 // SQE Inhibit Testing
+#define PHY_MR16_NL10 0x00000400 // Natural Loopback Mode
+#define PHY_MR16_SR_M 0x000003C0 // Silicon Revision Identifier
+#define PHY_MR16_APOL 0x00000020 // Auto-Polarity Disable
+#define PHY_MR16_RVSPOL 0x00000010 // Receive Data Polarity
+#define PHY_MR16_PCSBP 0x00000002 // PCS Bypass
+#define PHY_MR16_RXCC 0x00000001 // Receive Clock Control
+#define PHY_MR16_SR_S 6
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR17 register.
+//
+//*****************************************************************************
+#define PHY_MR17_JABBER_IE 0x00008000 // Jabber Interrupt Enable
+#define PHY_MR17_FASTRIP 0x00004000 // 10-BASE-T Fast Mode Enable
+#define PHY_MR17_RXER_IE 0x00004000 // Receive Error Interrupt Enable
+#define PHY_MR17_EDPD 0x00002000 // Enable Energy Detect Power Down
+#define PHY_MR17_PRX_IE 0x00002000 // Page Received Interrupt Enable
+#define PHY_MR17_PDF_IE 0x00001000 // Parallel Detection Fault
+ // Interrupt Enable
+#define PHY_MR17_LSQE 0x00000800 // Low Squelch Enable
+#define PHY_MR17_LPACK_IE 0x00000800 // LP Acknowledge Interrupt Enable
+#define PHY_MR17_LSCHG_IE 0x00000400 // Link Status Change Interrupt
+ // Enable
+#define PHY_MR17_RFAULT_IE 0x00000200 // Remote Fault Interrupt Enable
+#define PHY_MR17_ANEGCOMP_IE 0x00000100 // Auto-Negotiation Complete
+ // Interrupt Enable
+#define PHY_MR17_FASTEST 0x00000100 // Auto-Negotiation Test Mode
+#define PHY_MR17_JABBER_INT 0x00000080 // Jabber Event Interrupt
+#define PHY_MR17_RXER_INT 0x00000040 // Receive Error Interrupt
+#define PHY_MR17_PRX_INT 0x00000020 // Page Receive Interrupt
+#define PHY_MR17_PDF_INT 0x00000010 // Parallel Detection Fault
+ // Interrupt
+#define PHY_MR17_LPACK_INT 0x00000008 // LP Acknowledge Interrupt
+#define PHY_MR17_LSCHG_INT 0x00000004 // Link Status Change Interrupt
+#define PHY_MR17_FGLS 0x00000004 // Force Good Link Status
+#define PHY_MR17_RFAULT_INT 0x00000002 // Remote Fault Interrupt
+#define PHY_MR17_ENON 0x00000002 // Energy On
+#define PHY_MR17_ANEGCOMP_INT 0x00000001 // Auto-Negotiation Complete
+ // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR18 register.
+//
+//*****************************************************************************
+#define PHY_MR18_ANEGF 0x00001000 // Auto-Negotiation Failure
+#define PHY_MR18_DPLX 0x00000800 // Duplex Mode
+#define PHY_MR18_RATE 0x00000400 // Rate
+#define PHY_MR18_RXSD 0x00000200 // Receive Detection
+#define PHY_MR18_RX_LOCK 0x00000100 // Receive PLL Lock
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR19 register.
+//
+//*****************************************************************************
+#define PHY_MR19_TXO_M 0x0000C000 // Transmit Amplitude Selection
+#define PHY_MR19_TXO_00DB 0x00000000 // Gain set for 0.0dB of insertion
+ // loss
+#define PHY_MR19_TXO_04DB 0x00004000 // Gain set for 0.4dB of insertion
+ // loss
+#define PHY_MR19_TXO_08DB 0x00008000 // Gain set for 0.8dB of insertion
+ // loss
+#define PHY_MR19_TXO_12DB 0x0000C000 // Gain set for 1.2dB of insertion
+ // loss
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR23 register.
+//
+//*****************************************************************************
+#define PHY_MR23_LED1_M 0x000000F0 // LED1 Source
+#define PHY_MR23_LED1_LINK 0x00000000 // Link OK
+#define PHY_MR23_LED1_RXTX 0x00000010 // RX or TX Activity (Default LED1)
+#define PHY_MR23_LED1_100 0x00000050 // 100BASE-TX mode
+#define PHY_MR23_LED1_10 0x00000060 // 10BASE-T mode
+#define PHY_MR23_LED1_DUPLEX 0x00000070 // Full-Duplex
+#define PHY_MR23_LED1_LINKACT 0x00000080 // Link OK & Blink=RX or TX
+ // Activity
+#define PHY_MR23_LED0_M 0x0000000F // LED0 Source
+#define PHY_MR23_LED0_LINK 0x00000000 // Link OK (Default LED0)
+#define PHY_MR23_LED0_RXTX 0x00000001 // RX or TX Activity
+#define PHY_MR23_LED0_100 0x00000005 // 100BASE-TX mode
+#define PHY_MR23_LED0_10 0x00000006 // 10BASE-T mode
+#define PHY_MR23_LED0_DUPLEX 0x00000007 // Full-Duplex
+#define PHY_MR23_LED0_LINKACT 0x00000008 // Link OK & Blink=RX or TX
+ // Activity
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR24 register.
+//
+//*****************************************************************************
+#define PHY_MR24_PD_MODE 0x00000080 // Parallel Detection Mode
+#define PHY_MR24_AUTO_SW 0x00000040 // Auto-Switching Enable
+#define PHY_MR24_MDIX 0x00000020 // Auto-Switching Configuration
+#define PHY_MR24_MDIX_CM 0x00000010 // Auto-Switching Complete
+#define PHY_MR24_MDIX_SD_M 0x0000000F // Auto-Switching Seed
+#define PHY_MR24_MDIX_SD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR27 register.
+//
+//*****************************************************************************
+#define PHY_MR27_XPOL 0x00000010 // Polarity State of 10 BASE-T
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR29 register.
+//
+//*****************************************************************************
+#define PHY_MR29_EONIS 0x00000080 // ENERGYON Interrupt
+#define PHY_MR29_ANCOMPIS 0x00000040 // Auto-Negotiation Complete
+ // Interrupt
+#define PHY_MR29_RFLTIS 0x00000020 // Remote Fault Interrupt
+#define PHY_MR29_LDIS 0x00000010 // Link Down Interrupt
+#define PHY_MR29_LPACKIS 0x00000008 // Auto-Negotiation LP Acknowledge
+#define PHY_MR29_PDFIS 0x00000004 // Parallel Detection Fault
+#define PHY_MR29_PRXIS 0x00000002 // Auto Negotiation Page Received
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR30 register.
+//
+//*****************************************************************************
+#define PHY_MR30_EONIM 0x00000080 // ENERGYON Interrupt Enabled
+#define PHY_MR30_ANCOMPIM 0x00000040 // Auto-Negotiation Complete
+ // Interrupt Enabled
+#define PHY_MR30_RFLTIM 0x00000020 // Remote Fault Interrupt Enabled
+#define PHY_MR30_LDIM 0x00000010 // Link Down Interrupt Enabled
+#define PHY_MR30_LPACKIM 0x00000008 // Auto-Negotiation LP Acknowledge
+ // Enabled
+#define PHY_MR30_PDFIM 0x00000004 // Parallel Detection Fault Enabled
+#define PHY_MR30_PRXIM 0x00000002 // Auto Negotiation Page Received
+ // Enabled
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PHY_MR31 register.
+//
+//*****************************************************************************
+#define PHY_MR31_AUTODONE 0x00001000 // Auto Negotiation Done
+#define PHY_MR31_SPEED_M 0x0000001C // HCD Speed Value
+#define PHY_MR31_SPEED_10HD 0x00000004 // 10BASE-T half duplex
+#define PHY_MR31_SPEED_100HD 0x00000008 // 100BASE-T half duplex
+#define PHY_MR31_SPEED_10FD 0x00000014 // 10BASE-T full duplex
+#define PHY_MR31_SPEED_100FD 0x00000018 // 100BASE-T full duplex
+#define PHY_MR31_SCRDIS 0x00000001 // Scramble Disable
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the Ethernet MAC register offsets.
+//
+//*****************************************************************************
+#define MAC_O_IS 0x00000000 // Interrupt Status Register
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_O_IS
+// register.
+//
+//*****************************************************************************
+#define MAC_IS_PHYINT 0x00000040 // PHY Interrupt
+#define MAC_IS_MDINT 0x00000020 // MDI Transaction Complete
+#define MAC_IS_RXER 0x00000010 // RX Error
+#define MAC_IS_FOV 0x00000008 // RX FIFO Overrun
+#define MAC_IS_TXEMP 0x00000004 // TX FIFO Empy
+#define MAC_IS_TXER 0x00000002 // TX Error
+#define MAC_IS_RXINT 0x00000001 // RX Packet Available
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_O_IA0
+// register.
+//
+//*****************************************************************************
+#define MAC_IA0_MACOCT4 0xFF000000 // 4th Octet of MAC address
+#define MAC_IA0_MACOCT3 0x00FF0000 // 3rd Octet of MAC address
+#define MAC_IA0_MACOCT2 0x0000FF00 // 2nd Octet of MAC address
+#define MAC_IA0_MACOCT1 0x000000FF // 1st Octet of MAC address
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_O_IA1
+// register.
+//
+//*****************************************************************************
+#define MAC_IA1_MACOCT6 0x0000FF00 // 6th Octet of MAC address
+#define MAC_IA1_MACOCT5 0x000000FF // 5th Octet of MAC address
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_O_THR
+// register.
+//
+//*****************************************************************************
+#define MAC_THR_THRESH 0x0000003F // Transmit Threshold Value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_O_MCTL
+// register.
+//
+//*****************************************************************************
+#define MAC_MCTL_REGADR 0x000000F8 // Address for Next MII Transaction
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_O_MDV
+// register.
+//
+//*****************************************************************************
+#define MAC_MDV_DIV 0x000000FF // Clock Divider for MDC for TX
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_O_MTXD
+// register.
+//
+//*****************************************************************************
+#define MAC_MTXD_MDTX 0x0000FFFF // Data for Next MII Transaction
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_O_MRXD
+// register.
+//
+//*****************************************************************************
+#define MAC_MRXD_MDRX 0x0000FFFF // Data Read from Last MII Trans
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the MAC_O_NP
+// register.
+//
+//*****************************************************************************
+#define MAC_NP_NPR 0x0000003F // Number of RX Frames in FIFO
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the PHY_MR23
+// register.
+//
+//*****************************************************************************
+#define PHY_MR23_LED1_TX 0x00000020 // TX Activity
+#define PHY_MR23_LED1_RX 0x00000030 // RX Activity
+#define PHY_MR23_LED1_COL 0x00000040 // Collision
+#define PHY_MR23_LED0_TX 0x00000002 // TX Activity
+#define PHY_MR23_LED0_RX 0x00000003 // RX Activity
+#define PHY_MR23_LED0_COL 0x00000004 // Collision
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the reset values of the MAC
+// registers.
+//
+//*****************************************************************************
+#define MAC_RV_MDV 0x00000080
+#define MAC_RV_IM 0x0000007F
+#define MAC_RV_THR 0x0000003F
+#define MAC_RV_RCTL 0x00000008
+#define MAC_RV_IA0 0x00000000
+#define MAC_RV_TCTL 0x00000000
+#define MAC_RV_DATA 0x00000000
+#define MAC_RV_MRXD 0x00000000
+#define MAC_RV_TR 0x00000000
+#define MAC_RV_IS 0x00000000
+#define MAC_RV_NP 0x00000000
+#define MAC_RV_MCTL 0x00000000
+#define MAC_RV_MTXD 0x00000000
+#define MAC_RV_IA1 0x00000000
+#define MAC_RV_IACK 0x00000000
+#define MAC_RV_MADD 0x00000000
+
+#endif
+
+#endif // __HW_ETHERNET_H__
diff --git a/inc/hw_fan.h b/inc/hw_fan.h new file mode 100644 index 0000000..b9881f9 --- /dev/null +++ b/inc/hw_fan.h @@ -0,0 +1,688 @@ +//*****************************************************************************
+//
+// hw_fan.h - Macros used when accessing the fan control hardware.
+//
+// Copyright (c) 2010-2012 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 9453 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_FAN_H__
+#define __HW_FAN_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Fan Control register offsets.
+//
+//*****************************************************************************
+#define FAN_O_STS 0x00000000 // FAN Status
+#define FAN_O_CTL 0x00000004 // FAN Control
+#define FAN_O_CH0 0x00000010 // FAN Channel Setup
+#define FAN_O_CMD0 0x00000014 // FAN Channel Command
+#define FAN_O_CST0 0x00000018 // FAN Channel Status
+#define FAN_O_CH1 0x00000020 // FAN Channel Setup
+#define FAN_O_CMD1 0x00000024 // FAN Channel Command
+#define FAN_O_CST1 0x00000028 // FAN Channel Status
+#define FAN_O_CH2 0x00000030 // FAN Channel Setup
+#define FAN_O_CMD2 0x00000034 // FAN Channel Command
+#define FAN_O_CST2 0x00000038 // FAN Channel Status
+#define FAN_O_CH3 0x00000040 // FAN Channel Setup
+#define FAN_O_CMD3 0x00000044 // FAN Channel Command
+#define FAN_O_CST3 0x00000048 // FAN Channel Status
+#define FAN_O_CH4 0x00000050 // FAN Channel Setup
+#define FAN_O_CMD4 0x00000054 // FAN Channel Command
+#define FAN_O_CST4 0x00000058 // FAN Channel Status
+#define FAN_O_CH5 0x00000060 // FAN Channel Setup
+#define FAN_O_CMD5 0x00000064 // FAN Channel Command
+#define FAN_O_CST5 0x00000068 // FAN Channel Status
+#define FAN_O_CH6 0x00000070 // FAN Channel Setup
+#define FAN_O_CMD6 0x00000074 // FAN Channel Command
+#define FAN_O_CST6 0x00000078 // FAN Channel Status
+#define FAN_O_CH7 0x00000080 // FAN Channel Setup
+#define FAN_O_CMD7 0x00000084 // FAN Channel Command
+#define FAN_O_CST7 0x00000088 // FAN Channel Status
+#define FAN_O_IM 0x00000090 // FAN Interrupt Mask
+#define FAN_O_RIS 0x00000094 // FAN Raw Interrupt Status
+#define FAN_O_MIS 0x00000098 // FAN Masked Interrupt Status
+#define FAN_O_IC 0x0000009C // FAN Interrupt Clear
+#define FAN_O_PP 0x00000FC0 // FAN Peripheral Properties
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FAN_O_STS register.
+//
+//*****************************************************************************
+#define FAN_STS_FANCNT_M 0x000F0000 // Fan Count
+#define FAN_STS_ST5_M 0x00000C00 // Fan 5 Status
+#define FAN_STS_ST5_STALLED 0x00000000 // Stalled
+#define FAN_STS_ST5_CHANGING 0x00000400 // Changing
+#define FAN_STS_ST5_LOCKED 0x00000800 // Locked
+#define FAN_STS_ST5_NOATTAIN 0x00000C00 // No Attain
+#define FAN_STS_ST4_M 0x00000300 // Fan 4 Status
+#define FAN_STS_ST4_STALLED 0x00000000 // Stalled
+#define FAN_STS_ST4_CHANGING 0x00000100 // Changing
+#define FAN_STS_ST4_LOCKED 0x00000200 // Locked
+#define FAN_STS_ST4_NOATTAIN 0x00000300 // No Attain
+#define FAN_STS_ST3_M 0x000000C0 // Fan 3 Status
+#define FAN_STS_ST3_STALLED 0x00000000 // Stalled
+#define FAN_STS_ST3_CHANGING 0x00000040 // Changing
+#define FAN_STS_ST3_LOCKED 0x00000080 // Locked
+#define FAN_STS_ST3_NOATTAIN 0x000000C0 // No Attain
+#define FAN_STS_ST2_M 0x00000030 // Fan 2 Status
+#define FAN_STS_ST2_STALLED 0x00000000 // Stalled
+#define FAN_STS_ST2_CHANGING 0x00000010 // Changing
+#define FAN_STS_ST2_LOCKED 0x00000020 // Locked
+#define FAN_STS_ST2_NOATTAIN 0x00000030 // No Attain
+#define FAN_STS_ST1_M 0x0000000C // Fan 1 Status
+#define FAN_STS_ST1_STALLED 0x00000000 // Stalled
+#define FAN_STS_ST1_CHANGING 0x00000004 // Changing
+#define FAN_STS_ST1_LOCKED 0x00000008 // Locked
+#define FAN_STS_ST1_NOATTAIN 0x0000000C // No Attain
+#define FAN_STS_ST0_M 0x00000003 // Fan 0 Status
+#define FAN_STS_ST0_STALLED 0x00000000 // Stalled
+#define FAN_STS_ST0_CHANGING 0x00000001 // Changing
+#define FAN_STS_ST0_LOCKED 0x00000002 // Locked
+#define FAN_STS_ST0_NOATTAIN 0x00000003 // No Attain
+#define FAN_STS_FANCNT_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FAN_O_CTL register.
+//
+//*****************************************************************************
+#define FAN_CTL_E5 0x00000020 // Fan 5 Enable
+#define FAN_CTL_E4 0x00000010 // Fan 4 Enable
+#define FAN_CTL_E3 0x00000008 // Fan 3 Enable
+#define FAN_CTL_E2 0x00000004 // Fan 2 Enable
+#define FAN_CTL_E1 0x00000002 // Fan 1 Enable
+#define FAN_CTL_E0 0x00000001 // Fan 0 Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FAN_O_CH0 register.
+//
+//*****************************************************************************
+#define FAN_CH0_ASTART 0x00008000 // Auto Restart
+#define FAN_CH0_ACCEL 0x00004000 // Acceleration and Deceleration
+ // Rule
+#define FAN_CH0_HYST_M 0x00003800 // Hysteresis Adjustment on PID
+ // Adjust
+#define FAN_CH0_STPER_M 0x00000700 // Start Period
+#define FAN_CH0_START_M 0x000000C0 // Fast Start Rule
+#define FAN_CH0_START_NOFAST 0x00000000 // No fast start
+#define FAN_CH0_START_50DC 0x00000040 // 50% duty cycle
+#define FAN_CH0_START_75DC 0x00000080 // 75% duty cycle
+#define FAN_CH0_START_100DC 0x000000C0 // 100% duty cycle
+#define FAN_CH0_AVG_M 0x00000030 // Averaging of Tachometer
+#define FAN_CH0_AVG_0 0x00000000 // No averaging
+#define FAN_CH0_AVG_2 0x00000010 // Average 2 edges
+#define FAN_CH0_AVG_4 0x00000020 // Average 4 edges
+#define FAN_CH0_AVG_8 0x00000030 // Average 8 edges
+#define FAN_CH0_PPR_M 0x0000000C // Pulse per Revolution on
+ // Tachometer
+#define FAN_CH0_PPR_1 0x00000000 // 1 pulse per revolution
+#define FAN_CH0_PPR_2 0x00000004 // 2 pulses per revolution
+#define FAN_CH0_PPR_4 0x00000008 // 4 pulses per revolution
+#define FAN_CH0_PPR_8 0x0000000C // 8 pulses per revolution
+#define FAN_CH0_MAN 0x00000001 // Control Type
+#define FAN_CH0_HYST_S 11
+#define FAN_CH0_STPER_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FAN_O_CMD0 register.
+//
+//*****************************************************************************
+#define FAN_CMD0_DC_M 0x01FF0000 // PWM Duty Cycle
+#define FAN_CMD0_RPM_M 0x00001FFF // Fan Speed (in RPM)
+#define FAN_CMD0_DC_S 16
+#define FAN_CMD0_RPM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FAN_O_CST0 register.
+//
+//*****************************************************************************
+#define FAN_CST0_COUNT_M 0x07FF0000 // Last Read Tachometer Count
+#define FAN_CST0_RPM_M 0x00001FFF // Last Read RPM Speed Computed
+#define FAN_CST0_COUNT_S 16
+#define FAN_CST0_RPM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FAN_O_CH1 register.
+//
+//*****************************************************************************
+#define FAN_CH1_ASTART 0x00008000 // Auto Restart
+#define FAN_CH1_ACCEL 0x00004000 // Acceleration and Deceleration
+ // Rule
+#define FAN_CH1_HYST_M 0x00003800 // Hysteresis Adjustment on PID
+ // Adjust
+#define FAN_CH1_STPER_M 0x00000700 // Start Period
+#define FAN_CH1_START_M 0x000000C0 // Fast Start Rule
+#define FAN_CH1_START_NOFAST 0x00000000 // No fast start
+#define FAN_CH1_START_50DC 0x00000040 // 50% duty cycle
+#define FAN_CH1_START_75DC 0x00000080 // 75% duty cycle
+#define FAN_CH1_START_100DC 0x000000C0 // 100% duty cycle
+#define FAN_CH1_AVG_M 0x00000030 // Averaging of Tachometer
+#define FAN_CH1_AVG_0 0x00000000 // No averaging
+#define FAN_CH1_AVG_2 0x00000010 // Average 2 edges
+#define FAN_CH1_AVG_4 0x00000020 // Average 4 edges
+#define FAN_CH1_AVG_8 0x00000030 // Average 8 edges
+#define FAN_CH1_PPR_M 0x0000000C // Pulse per Revolution on
+ // Tachometer
+#define FAN_CH1_PPR_1 0x00000000 // 1 pulse per revolution
+#define FAN_CH1_PPR_2 0x00000004 // 2 pulses per revolution
+#define FAN_CH1_PPR_4 0x00000008 // 4 pulses per revolution
+#define FAN_CH1_PPR_8 0x0000000C // 8 pulses per revolution
+#define FAN_CH1_MAN 0x00000001 // Control Type
+#define FAN_CH1_HYST_S 11
+#define FAN_CH1_STPER_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FAN_O_CMD1 register.
+//
+//*****************************************************************************
+#define FAN_CMD1_DC_M 0x01FF0000 // PWM Duty Cycle
+#define FAN_CMD1_RPM_M 0x00001FFF // Fan Speed (in RPM)
+#define FAN_CMD1_DC_S 16
+#define FAN_CMD1_RPM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FAN_O_CST1 register.
+//
+//*****************************************************************************
+#define FAN_CST1_COUNT_M 0x07FF0000 // Last Read Tachometer Count
+#define FAN_CST1_RPM_M 0x00001FFF // Last Read RPM Speed Computed
+#define FAN_CST1_COUNT_S 16
+#define FAN_CST1_RPM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FAN_O_CH2 register.
+//
+//*****************************************************************************
+#define FAN_CH2_ASTART 0x00008000 // Auto Restart
+#define FAN_CH2_ACCEL 0x00004000 // Acceleration and Deceleration
+ // Rule
+#define FAN_CH2_HYST_M 0x00003800 // Hysteresis Adjustment on PID
+ // Adjust
+#define FAN_CH2_STPER_M 0x00000700 // Start Period
+#define FAN_CH2_START_M 0x000000C0 // Fast Start Rule
+#define FAN_CH2_START_NOFAST 0x00000000 // No fast start
+#define FAN_CH2_START_50DC 0x00000040 // 50% duty cycle
+#define FAN_CH2_START_75DC 0x00000080 // 75% duty cycle
+#define FAN_CH2_START_100DC 0x000000C0 // 100% duty cycle
+#define FAN_CH2_AVG_M 0x00000030 // Averaging of Tachometer
+#define FAN_CH2_AVG_0 0x00000000 // No averaging
+#define FAN_CH2_AVG_2 0x00000010 // Average 2 edges
+#define FAN_CH2_AVG_4 0x00000020 // Average 4 edges
+#define FAN_CH2_AVG_8 0x00000030 // Average 8 edges
+#define FAN_CH2_PPR_M 0x0000000C // Pulse per Revolution on
+ // Tachometer
+#define FAN_CH2_PPR_1 0x00000000 // 1 pulse per revolution
+#define FAN_CH2_PPR_2 0x00000004 // 2 pulses per revolution
+#define FAN_CH2_PPR_4 0x00000008 // 4 pulses per revolution
+#define FAN_CH2_PPR_8 0x0000000C // 8 pulses per revolution
+#define FAN_CH2_MAN 0x00000001 // Control Type
+#define FAN_CH2_HYST_S 11
+#define FAN_CH2_STPER_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FAN_O_CMD2 register.
+//
+//*****************************************************************************
+#define FAN_CMD2_DC_M 0x01FF0000 // PWM Duty Cycle
+#define FAN_CMD2_RPM_M 0x00001FFF // Fan Speed (in RPM)
+#define FAN_CMD2_DC_S 16
+#define FAN_CMD2_RPM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FAN_O_CST2 register.
+//
+//*****************************************************************************
+#define FAN_CST2_COUNT_M 0x07FF0000 // Last Read Tachometer Count
+#define FAN_CST2_RPM_M 0x00001FFF // Last Read RPM Speed Computed
+#define FAN_CST2_COUNT_S 16
+#define FAN_CST2_RPM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FAN_O_CH3 register.
+//
+//*****************************************************************************
+#define FAN_CH3_ASTART 0x00008000 // Auto Restart
+#define FAN_CH3_ACCEL 0x00004000 // Acceleration and Deceleration
+ // Rule
+#define FAN_CH3_HYST_M 0x00003800 // Hysteresis Adjustment on PID
+ // Adjust
+#define FAN_CH3_STPER_M 0x00000700 // Start Period
+#define FAN_CH3_START_M 0x000000C0 // Fast Start Rule
+#define FAN_CH3_START_NOFAST 0x00000000 // No fast start
+#define FAN_CH3_START_50DC 0x00000040 // 50% duty cycle
+#define FAN_CH3_START_75DC 0x00000080 // 75% duty cycle
+#define FAN_CH3_START_100DC 0x000000C0 // 100% duty cycle
+#define FAN_CH3_AVG_M 0x00000030 // Averaging of Tachometer
+#define FAN_CH3_AVG_0 0x00000000 // No averaging
+#define FAN_CH3_AVG_2 0x00000010 // Average 2 edges
+#define FAN_CH3_AVG_4 0x00000020 // Average 4 edges
+#define FAN_CH3_AVG_8 0x00000030 // Average 8 edges
+#define FAN_CH3_PPR_M 0x0000000C // Pulse per Revolution on
+ // Tachometer
+#define FAN_CH3_PPR_1 0x00000000 // 1 pulse per revolution
+#define FAN_CH3_PPR_2 0x00000004 // 2 pulses per revolution
+#define FAN_CH3_PPR_4 0x00000008 // 4 pulses per revolution
+#define FAN_CH3_PPR_8 0x0000000C // 8 pulses per revolution
+#define FAN_CH3_MAN 0x00000001 // Control Type
+#define FAN_CH3_HYST_S 11
+#define FAN_CH3_STPER_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FAN_O_CMD3 register.
+//
+//*****************************************************************************
+#define FAN_CMD3_DC_M 0x01FF0000 // PWM Duty Cycle
+#define FAN_CMD3_RPM_M 0x00001FFF // Fan Speed (in RPM)
+#define FAN_CMD3_DC_S 16
+#define FAN_CMD3_RPM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FAN_O_CST3 register.
+//
+//*****************************************************************************
+#define FAN_CST3_COUNT_M 0x07FF0000 // Last Read Tachometer Count
+#define FAN_CST3_RPM_M 0x00001FFF // Last Read RPM Speed Computed
+#define FAN_CST3_COUNT_S 16
+#define FAN_CST3_RPM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FAN_O_CH4 register.
+//
+//*****************************************************************************
+#define FAN_CH4_ASTART 0x00008000 // Auto Restart
+#define FAN_CH4_ACCEL 0x00004000 // Acceleration and Deceleration
+ // Rule
+#define FAN_CH4_HYST_M 0x00003800 // Hysteresis Adjustment on PID
+ // Adjust
+#define FAN_CH4_STPER_M 0x00000700 // Start Period
+#define FAN_CH4_START_M 0x000000C0 // Fast Start Rule
+#define FAN_CH4_START_NOFAST 0x00000000 // No fast start
+#define FAN_CH4_START_50DC 0x00000040 // 50% duty cycle
+#define FAN_CH4_START_75DC 0x00000080 // 75% duty cycle
+#define FAN_CH4_START_100DC 0x000000C0 // 100% duty cycle
+#define FAN_CH4_AVG_M 0x00000030 // Averaging of Tachometer
+#define FAN_CH4_AVG_0 0x00000000 // No averaging
+#define FAN_CH4_AVG_2 0x00000010 // Average 2 edges
+#define FAN_CH4_AVG_4 0x00000020 // Average 4 edges
+#define FAN_CH4_AVG_8 0x00000030 // Average 8 edges
+#define FAN_CH4_PPR_M 0x0000000C // Pulse per Revolution on
+ // Tachometer
+#define FAN_CH4_PPR_1 0x00000000 // 1 pulse per revolution
+#define FAN_CH4_PPR_2 0x00000004 // 2 pulses per revolution
+#define FAN_CH4_PPR_4 0x00000008 // 4 pulses per revolution
+#define FAN_CH4_PPR_8 0x0000000C // 8 pulses per revolution
+#define FAN_CH4_MAN 0x00000001 // Control Type
+#define FAN_CH4_HYST_S 11
+#define FAN_CH4_STPER_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FAN_O_CMD4 register.
+//
+//*****************************************************************************
+#define FAN_CMD4_DC_M 0x01FF0000 // PWM Duty Cycle
+#define FAN_CMD4_RPM_M 0x00001FFF // Fan Speed (in RPM)
+#define FAN_CMD4_DC_S 16
+#define FAN_CMD4_RPM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FAN_O_CST4 register.
+//
+//*****************************************************************************
+#define FAN_CST4_COUNT_M 0x07FF0000 // Last Read Tachometer Count
+#define FAN_CST4_RPM_M 0x00001FFF // Last Read RPM Speed Computed
+#define FAN_CST4_COUNT_S 16
+#define FAN_CST4_RPM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FAN_O_CH5 register.
+//
+//*****************************************************************************
+#define FAN_CH5_ASTART 0x00008000 // Auto Restart
+#define FAN_CH5_ACCEL 0x00004000 // Acceleration and Deceleration
+ // Rule
+#define FAN_CH5_HYST_M 0x00003800 // Hysteresis Adjustment on PID
+ // Adjust
+#define FAN_CH5_STPER_M 0x00000700 // Start Period
+#define FAN_CH5_START_M 0x000000C0 // Fast Start Rule
+#define FAN_CH5_START_NOFAST 0x00000000 // No fast start
+#define FAN_CH5_START_50DC 0x00000040 // 50% duty cycle
+#define FAN_CH5_START_75DC 0x00000080 // 75% duty cycle
+#define FAN_CH5_START_100DC 0x000000C0 // 100% duty cycle
+#define FAN_CH5_AVG_M 0x00000030 // Averaging of Tachometer
+#define FAN_CH5_AVG_0 0x00000000 // No averaging
+#define FAN_CH5_AVG_2 0x00000010 // Average 2 edges
+#define FAN_CH5_AVG_4 0x00000020 // Average 4 edges
+#define FAN_CH5_AVG_8 0x00000030 // Average 8 edges
+#define FAN_CH5_PPR_M 0x0000000C // Pulse per Revolution on
+ // Tachometer
+#define FAN_CH5_PPR_1 0x00000000 // 1 pulse per revolution
+#define FAN_CH5_PPR_2 0x00000004 // 2 pulses per revolution
+#define FAN_CH5_PPR_4 0x00000008 // 4 pulses per revolution
+#define FAN_CH5_PPR_8 0x0000000C // 8 pulses per revolution
+#define FAN_CH5_MAN 0x00000001 // Control Type
+#define FAN_CH5_HYST_S 11
+#define FAN_CH5_STPER_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FAN_O_CMD5 register.
+//
+//*****************************************************************************
+#define FAN_CMD5_DC_M 0x01FF0000 // PWM Duty Cycle
+#define FAN_CMD5_RPM_M 0x00001FFF // Fan Speed (in RPM)
+#define FAN_CMD5_DC_S 16
+#define FAN_CMD5_RPM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FAN_O_CST5 register.
+//
+//*****************************************************************************
+#define FAN_CST5_COUNT_M 0x07FF0000 // Last Read Tachometer Count
+#define FAN_CST5_RPM_M 0x00001FFF // Last Read RPM Speed Computed
+#define FAN_CST5_COUNT_S 16
+#define FAN_CST5_RPM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FAN_O_CH6 register.
+//
+//*****************************************************************************
+#define FAN_CH6_MAN 0x00000001 // Control Type
+#define FAN_CH6_PPR_M 0x0000000C // Pulse per Revolution on
+ // Tachometer
+#define FAN_CH6_PPR_1 0x00000000 // 1 pulse per revolution
+#define FAN_CH6_PPR_2 0x00000004 // 2 pulses per revolution
+#define FAN_CH6_PPR_4 0x00000008 // 4 pulses per revolution
+#define FAN_CH6_PPR_8 0x0000000C // 8 pulses per revolution
+#define FAN_CH6_AVG_M 0x00000030 // Averaging of Tachometer
+#define FAN_CH6_AVG_0 0x00000000 // No averaging
+#define FAN_CH6_AVG_2 0x00000010 // Average 2 edges
+#define FAN_CH6_AVG_4 0x00000020 // Average 4 edges
+#define FAN_CH6_AVG_8 0x00000030 // Average 8 edges
+#define FAN_CH6_START_M 0x000000C0 // Fast Start Rule
+#define FAN_CH6_START_NOFAST 0x00000000 // No fast start
+#define FAN_CH6_START_50DC 0x00000040 // 50% duty cycle
+#define FAN_CH6_START_75DC 0x00000080 // 75% duty cycle
+#define FAN_CH6_START_100DC 0x000000C0 // 100% duty cycle
+#define FAN_CH6_STPER_M 0x00000700 // Start Period
+#define FAN_CH6_HYST_M 0x00003800 // Hysteresis Adjustment on PID
+ // Adjust
+#define FAN_CH6_ACCEL 0x00004000 // Acceleration and Deceleration
+ // Rule
+#define FAN_CH6_ASTART 0x00008000 // Auto Restart
+#define FAN_CH6_STPER_S 8
+#define FAN_CH6_HYST_S 11
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FAN_O_CMD6 register.
+//
+//*****************************************************************************
+#define FAN_CMD6_RPM_M 0x00001FFF // Fan Speed (in RPM)
+#define FAN_CMD6_DC_M 0x01FF0000 // PWM Duty Cycle
+#define FAN_CMD6_RPM_S 0
+#define FAN_CMD6_DC_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FAN_O_CST6 register.
+//
+//*****************************************************************************
+#define FAN_CST6_RPM_M 0x00001FFF // Last Read RPM Speed Computed
+#define FAN_CST6_COUNT_M 0x07FF0000 // Last Read Tachometer Count
+#define FAN_CST6_RPM_S 0
+#define FAN_CST6_COUNT_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FAN_O_CH7 register.
+//
+//*****************************************************************************
+#define FAN_CH7_MAN 0x00000001 // Control Type
+#define FAN_CH7_PPR_M 0x0000000C // Pulse per Revolution on
+ // Tachometer
+#define FAN_CH7_PPR_1 0x00000000 // 1 pulse per revolution
+#define FAN_CH7_PPR_2 0x00000004 // 2 pulses per revolution
+#define FAN_CH7_PPR_4 0x00000008 // 4 pulses per revolution
+#define FAN_CH7_PPR_8 0x0000000C // 8 pulses per revolution
+#define FAN_CH7_AVG_M 0x00000030 // Averaging of Tachometer
+#define FAN_CH7_AVG_0 0x00000000 // No averaging
+#define FAN_CH7_AVG_2 0x00000010 // Average 2 edges
+#define FAN_CH7_AVG_4 0x00000020 // Average 4 edges
+#define FAN_CH7_AVG_8 0x00000030 // Average 8 edges
+#define FAN_CH7_START_M 0x000000C0 // Fast Start Rule
+#define FAN_CH7_START_NOFAST 0x00000000 // No fast start
+#define FAN_CH7_START_50DC 0x00000040 // 50% duty cycle
+#define FAN_CH7_START_75DC 0x00000080 // 75% duty cycle
+#define FAN_CH7_START_100DC 0x000000C0 // 100% duty cycle
+#define FAN_CH7_STPER_M 0x00000700 // Start Period
+#define FAN_CH7_HYST_M 0x00003800 // Hysteresis Adjustment on PID
+ // Adjust
+#define FAN_CH7_ACCEL 0x00004000 // Acceleration and Deceleration
+ // Rule
+#define FAN_CH7_ASTART 0x00008000 // Auto Restart
+#define FAN_CH7_STPER_S 8
+#define FAN_CH7_HYST_S 11
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FAN_O_CMD7 register.
+//
+//*****************************************************************************
+#define FAN_CMD7_RPM_M 0x00001FFF // Fan Speed (in RPM)
+#define FAN_CMD7_DC_M 0x01FF0000 // PWM Duty Cycle
+#define FAN_CMD7_RPM_S 0
+#define FAN_CMD7_DC_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FAN_O_CST7 register.
+//
+//*****************************************************************************
+#define FAN_CST7_RPM_M 0x00001FFF // Last Read RPM Speed Computed
+#define FAN_CST7_COUNT_M 0x07FF0000 // Last Read Tachometer Count
+#define FAN_CST7_RPM_S 0
+#define FAN_CST7_COUNT_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FAN_O_IM register.
+//
+//*****************************************************************************
+#define FAN_IM_C5INT1IM 0x00400000 // Channel 5 Interrupt 1 Mask
+#define FAN_IM_C5INT0IM 0x00200000 // Channel 5 Interrupt 0 Mask
+#define FAN_IM_C5STALLIM 0x00100000 // Channel 5 Stall Interrupt Mask
+#define FAN_IM_C4INT1IM 0x00040000 // Channel 4 Interrupt 1 Mask
+#define FAN_IM_C4INT0IM 0x00020000 // Channel 4 Interrupt 0 Mask
+#define FAN_IM_C4STALLIM 0x00010000 // Channel 4 Stall Interrupt Mask
+#define FAN_IM_C3INT1IM 0x00004000 // Channel 3 Interrupt 1 Mask
+#define FAN_IM_C3INT0IM 0x00002000 // Channel 3 Interrupt 0 Mask
+#define FAN_IM_C3STALLIM 0x00001000 // Channel 3 Stall Interrupt Mask
+#define FAN_IM_C2INT1IM 0x00000400 // Channel 2 Interrupt 1 Mask
+#define FAN_IM_C2INT0IM 0x00000200 // Channel 2 Interrupt 0 Mask
+#define FAN_IM_C2STALLIM 0x00000100 // Channel 2 Stall Interrupt Mask
+#define FAN_IM_C1INT1IM 0x00000040 // Channel 1 Interrupt 1 Mask
+#define FAN_IM_C1INT0IM 0x00000020 // Channel 1 Interrupt 0 Mask
+#define FAN_IM_C1STALLIM 0x00000010 // Channel 1 Stall Interrupt Mask
+#define FAN_IM_C0INT1IM 0x00000004 // Channel 0 Interrupt 1 Mask
+#define FAN_IM_C0INT0IM 0x00000002 // Channel 0 Interrupt 0 Mask
+#define FAN_IM_C0STALLIM 0x00000001 // Channel 0 Stall Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FAN_O_RIS register.
+//
+//*****************************************************************************
+#define FAN_RIS_C5INT1RIS 0x00400000 // Channel 5 Raw Interrupt 1 Status
+#define FAN_RIS_C5INT0RIS 0x00200000 // Channel 5 Raw Interrupt 0 Status
+#define FAN_RIS_C5STALLRIS 0x00100000 // Channel 5 Raw Stall Interrupt
+ // Status
+#define FAN_RIS_C4INT1RIS 0x00040000 // Channel 4 Raw Interrupt 1 Status
+#define FAN_RIS_C4INT0RIS 0x00020000 // Channel 4 Raw Interrupt 0 Status
+#define FAN_RIS_C4STALLRIS 0x00010000 // Channel 4 Raw Stall Interrupt
+ // Status
+#define FAN_RIS_C3INT1RIS 0x00004000 // Channel 3 Raw Interrupt 1 Status
+#define FAN_RIS_C3INT0RIS 0x00002000 // Channel 3 Raw Interrupt 0 Status
+#define FAN_RIS_C3STALLRIS 0x00001000 // Channel 3 Stall Raw Interrupt
+ // Status
+#define FAN_RIS_C2INT1RIS 0x00000400 // Channel 2 Raw Interrupt 1 Status
+#define FAN_RIS_C2INT0RIS 0x00000200 // Channel 2 Raw Interrupt 0 Status
+#define FAN_RIS_C2STALLRIS 0x00000100 // Channel 2 Stall Raw Interrupt
+ // Status
+#define FAN_RIS_C1INT1RIS 0x00000040 // Channel 1 Raw Interrupt 1 Status
+#define FAN_RIS_C1INT0RIS 0x00000020 // Channel 1 Raw Interrupt 0 Status
+#define FAN_RIS_C1STALLRIS 0x00000010 // Channel 1 Stall Raw Interrupt
+ // Status
+#define FAN_RIS_C0INT1RIS 0x00000004 // Channel 0 Raw Interrupt 1 Status
+#define FAN_RIS_C0INT0RIS 0x00000002 // Channel 0 Raw Interrupt 0 Status
+#define FAN_RIS_C0STALLRIS 0x00000001 // Channel 0 Stall Raw Interrupt
+ // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FAN_O_MIS register.
+//
+//*****************************************************************************
+#define FAN_MIS_C5INT1MIS 0x00400000 // Channel 5 Masked Interrupt 1
+ // Status
+#define FAN_MIS_C5INT0MIS 0x00200000 // Channel 5 Masked Interrupt 0
+ // Status
+#define FAN_MIS_C5STALLMIS 0x00100000 // Channel 5 Masked Stall Interrupt
+ // Status
+#define FAN_MIS_C4NT1MIS 0x00040000 // Channel 4 Masked Interrupt 1
+ // Status
+#define FAN_MIS_C4INT0MIS 0x00020000 // Channel 4 Masked Interrupt 0
+ // Status
+#define FAN_MIS_C4STALLMIS 0x00010000 // Channel 4 Masked Stall Interrupt
+ // Status
+#define FAN_MIS_C3INT1MIS 0x00004000 // Channel 3 Masked Interrupt 1
+ // Status
+#define FAN_MIS_C3INT0MIS 0x00002000 // Channel 3 Masked Interrupt 0
+ // Status
+#define FAN_MIS_C3STALLMIS 0x00001000 // Channel 3 Stall Masked Interrupt
+ // Status
+#define FAN_MIS_C2INT1MIS 0x00000400 // Channel 2 Masked Interrupt 1
+ // Status
+#define FAN_MIS_C2INT0MIS 0x00000200 // Channel 2 Masked Interrupt 0
+ // Status
+#define FAN_MIS_C2STALLMIS 0x00000100 // Channel 2 Stall Masked Interrupt
+ // Status
+#define FAN_MIS_C1INT1MIS 0x00000040 // Channel 1 Masked Interrupt 1
+ // Status
+#define FAN_MIS_C1INT0MIS 0x00000020 // Channel 1 Masked Interrupt 0
+ // Status
+#define FAN_MIS_C1STALLMIS 0x00000010 // Channel 1 Stall Masked Interrupt
+ // Status
+#define FAN_MIS_C0INT1MIS 0x00000004 // Channel 0 Masked Interrupt 1
+ // Status
+#define FAN_MIS_C0INT0MIS 0x00000002 // Channel 0 Masked Interrupt 0
+ // Status
+#define FAN_MIS_C0STALLMIS 0x00000001 // Channel 0 Stall Masked Interrupt
+ // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FAN_O_IC register.
+//
+//*****************************************************************************
+#define FAN_IC_C5INT1IC 0x00400000 // Channel 5 Interrupt 1 Clear
+#define FAN_IC_C5INT0IC 0x00200000 // Channel 5 Interrupt 0 Clear
+#define FAN_IC_C5STALLIC 0x00100000 // Channel 5 Stall Interrupt Clear
+#define FAN_IC_C4INT1IC 0x00040000 // Channel 4 Interrupt 1 Clear
+#define FAN_IC_C4INT0IC 0x00020000 // Channel 4 Interrupt 0 Clear
+#define FAN_IC_C4STALLIC 0x00010000 // Channel 4 Stall Interrupt Clear
+#define FAN_IC_C3INT1IC 0x00004000 // Channel 3 Interrupt 1 Clear
+#define FAN_IC_C53INT0IC 0x00002000 // Channel 3 Interrupt 0 Clear
+#define FAN_IC_C3STALLIC 0x00001000 // Channel 3 Stall Interrupt Clear
+#define FAN_IC_C2INT1IC 0x00000400 // Channel 2 Interrupt 1 Clear
+#define FAN_IC_C2INT0IC 0x00000200 // Channel 2 Interrupt 0 Clear
+#define FAN_IC_C2STALLIC 0x00000100 // Channel 2 Stall Interrupt Clear
+#define FAN_IC_C1INT1IC 0x00000040 // Channel 1 Interrupt 1 Clear
+#define FAN_IC_C1INT0IC 0x00000020 // Channel 1 Interrupt 0 Clear
+#define FAN_IC_C1STALLIC 0x00000010 // Channel 1 Stall Interrupt Clear
+#define FAN_IC_C0INT1IC 0x00000004 // Channel 0 Interrupt 1 Clear
+#define FAN_IC_C0INT0IC 0x00000002 // Channel 0 Interrupt 0 Clear
+#define FAN_IC_C0STALLIC 0x00000001 // Channel 0 Stall Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FAN_O_PP register.
+//
+//*****************************************************************************
+#define FAN_PP_CHAN_M 0x0000000F // Channel Count
+#define FAN_PP_CHAN_S 0
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the FAN_O_STS
+// register.
+//
+//*****************************************************************************
+#define FAN_STS_ST5_UNBALANCED 0x00000C00 // Unbalanced Spin
+#define FAN_STS_ST4_S 8
+#define FAN_STS_ST3_S 6
+#define FAN_STS_ST2_S 4
+#define FAN_STS_ST1_S 2
+#define FAN_STS_ST0_S 0
+
+#endif
+
+#endif // __HW_FAN_H__
diff --git a/inc/hw_flash.h b/inc/hw_flash.h new file mode 100644 index 0000000..4295262 --- /dev/null +++ b/inc/hw_flash.h @@ -0,0 +1,474 @@ +//*****************************************************************************
+//
+// hw_flash.h - Macros used when accessing the flash controller.
+//
+// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 9453 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_FLASH_H__
+#define __HW_FLASH_H__
+
+//*****************************************************************************
+//
+// The following are defines for the FLASH register offsets.
+//
+//*****************************************************************************
+#define FLASH_FMA 0x400FD000 // Flash Memory Address
+#define FLASH_FMD 0x400FD004 // Flash Memory Data
+#define FLASH_FMC 0x400FD008 // Flash Memory Control
+#define FLASH_FCRIS 0x400FD00C // Flash Controller Raw Interrupt
+ // Status
+#define FLASH_FCIM 0x400FD010 // Flash Controller Interrupt Mask
+#define FLASH_FCMISC 0x400FD014 // Flash Controller Masked
+ // Interrupt Status and Clear
+#define FLASH_FMC2 0x400FD020 // Flash Memory Control 2
+#define FLASH_FWBVAL 0x400FD030 // Flash Write Buffer Valid
+#define FLASH_FCTL 0x400FD0F8 // Flash Control
+#define FLASH_FWBN 0x400FD100 // Flash Write Buffer n
+#define FLASH_FSIZE 0x400FDFC0 // Flash Size
+#define FLASH_SSIZE 0x400FDFC4 // SRAM Size
+#define FLASH_ROMSWMAP 0x400FDFCC // ROM Software Map
+#define FLASH_RMCTL 0x400FE0F0 // ROM Control
+#define FLASH_FMPRE 0x400FE130 // Flash Memory Protection Read
+ // Enable
+#define FLASH_FMPPE 0x400FE134 // Flash Memory Protection Program
+ // Enable
+#define FLASH_USECRL 0x400FE140 // USec Reload
+#define FLASH_USERDBG 0x400FE1D0 // User Debug
+#define FLASH_BOOTCFG 0x400FE1D0 // Boot Configuration
+#define FLASH_USERREG0 0x400FE1E0 // User Register 0
+#define FLASH_USERREG1 0x400FE1E4 // User Register 1
+#define FLASH_USERREG2 0x400FE1E8 // User Register 2
+#define FLASH_USERREG3 0x400FE1EC // User Register 3
+#define FLASH_FMPRE0 0x400FE200 // Flash Memory Protection Read
+ // Enable 0
+#define FLASH_FMPRE1 0x400FE204 // Flash Memory Protection Read
+ // Enable 1
+#define FLASH_FMPRE2 0x400FE208 // Flash Memory Protection Read
+ // Enable 2
+#define FLASH_FMPRE3 0x400FE20C // Flash Memory Protection Read
+ // Enable 3
+#define FLASH_FMPRE4 0x400FE210 // Flash Memory Protection Read
+ // Enable 4
+#define FLASH_FMPRE5 0x400FE214 // Flash Memory Protection Read
+ // Enable 5
+#define FLASH_FMPRE6 0x400FE218 // Flash Memory Protection Read
+ // Enable 6
+#define FLASH_FMPRE7 0x400FE21C // Flash Memory Protection Read
+ // Enable 7
+#define FLASH_FMPPE0 0x400FE400 // Flash Memory Protection Program
+ // Enable 0
+#define FLASH_FMPPE1 0x400FE404 // Flash Memory Protection Program
+ // Enable 1
+#define FLASH_FMPPE2 0x400FE408 // Flash Memory Protection Program
+ // Enable 2
+#define FLASH_FMPPE3 0x400FE40C // Flash Memory Protection Program
+ // Enable 3
+#define FLASH_FMPPE4 0x400FE410 // Flash Memory Protection Program
+ // Enable 4
+#define FLASH_FMPPE5 0x400FE414 // Flash Memory Protection Program
+ // Enable 5
+#define FLASH_FMPPE6 0x400FE418 // Flash Memory Protection Program
+ // Enable 6
+#define FLASH_FMPPE7 0x400FE41C // Flash Memory Protection Program
+ // Enable 7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMA register.
+//
+//*****************************************************************************
+#define FLASH_FMA_OFFSET_M 0x0007FFFF // Address Offset
+#define FLASH_FMA_OFFSET_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMD register.
+//
+//*****************************************************************************
+#define FLASH_FMD_DATA_M 0xFFFFFFFF // Data Value
+#define FLASH_FMD_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMC register.
+//
+//*****************************************************************************
+#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key
+#define FLASH_FMC_COMT 0x00000008 // Commit Register Value
+#define FLASH_FMC_MERASE 0x00000004 // Mass Erase Flash Memory
+#define FLASH_FMC_ERASE 0x00000002 // Erase a Page of Flash Memory
+#define FLASH_FMC_WRITE 0x00000001 // Write a Word into Flash Memory
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCRIS register.
+//
+//*****************************************************************************
+#define FLASH_FCRIS_PROGRIS 0x00002000 // PROGVER Raw Interrupt Status
+#define FLASH_FCRIS_ERRIS 0x00000800 // ERVER Raw Interrupt Status
+#define FLASH_FCRIS_INVDRIS 0x00000400 // Invalid Data Raw Interrupt
+ // Status
+#define FLASH_FCRIS_VOLTRIS 0x00000200 // VOLTSTAT Raw Interrupt Status
+#define FLASH_FCRIS_ERIS 0x00000004 // EEPROM Raw Interrupt Status
+#define FLASH_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt Status
+#define FLASH_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCIM register.
+//
+//*****************************************************************************
+#define FLASH_FCIM_PROGMASK 0x00002000 // PROGVER Interrupt Mask
+#define FLASH_FCIM_ERMASK 0x00000800 // ERVER Interrupt Mask
+#define FLASH_FCIM_INVDMASK 0x00000400 // Invalid Data Interrupt Mask
+#define FLASH_FCIM_VOLTMASK 0x00000200 // VOLT Interrupt Mask
+#define FLASH_FCIM_EMASK 0x00000004 // EEPROM Interrupt Mask
+#define FLASH_FCIM_PMASK 0x00000002 // Programming Interrupt Mask
+#define FLASH_FCIM_AMASK 0x00000001 // Access Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCMISC register.
+//
+//*****************************************************************************
+#define FLASH_FCMISC_PROGMISC 0x00002000 // PROGVER Masked Interrupt Status
+ // and Clear
+#define FLASH_FCMISC_ERMISC 0x00000800 // ERVER Masked Interrupt Status
+ // and Clear
+#define FLASH_FCMISC_INVDMISC 0x00000400 // Invalid Data Masked Interrupt
+ // Status and Clear
+#define FLASH_FCMISC_VOLTMISC 0x00000200 // VOLT Masked Interrupt Status and
+ // Clear
+#define FLASH_FCMISC_EMISC 0x00000004 // EEPROM Masked Interrupt Status
+ // and Clear
+#define FLASH_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt
+ // Status and Clear
+#define FLASH_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status
+ // and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMC2 register.
+//
+//*****************************************************************************
+#define FLASH_FMC2_WRKEY 0xA4420000 // FLASH write key
+#define FLASH_FMC2_WRBUF 0x00000001 // Buffered Flash Memory Write
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FWBVAL register.
+//
+//*****************************************************************************
+#define FLASH_FWBVAL_FWB_M 0xFFFFFFFF // Flash Memory Write Buffer
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCTL register.
+//
+//*****************************************************************************
+#define FLASH_FCTL_USDACK 0x00000002 // User Shut Down Acknowledge
+#define FLASH_FCTL_USDREQ 0x00000001 // User Shut Down Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FWBN register.
+//
+//*****************************************************************************
+#define FLASH_FWBN_DATA_M 0xFFFFFFFF // Data
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FSIZE register.
+//
+//*****************************************************************************
+#define FLASH_FSIZE_SIZE_M 0x0000FFFF // Flash Size
+#define FLASH_FSIZE_SIZE_8KB 0x00000003 // 8 KB of Flash
+#define FLASH_FSIZE_SIZE_16KB 0x00000007 // 16 KB of Flash
+#define FLASH_FSIZE_SIZE_32KB 0x0000000F // 32 KB of Flash
+#define FLASH_FSIZE_SIZE_64KB 0x0000001F // 64 KB of Flash
+#define FLASH_FSIZE_SIZE_96KB 0x0000002F // 96 KB of Flash
+#define FLASH_FSIZE_SIZE_128KB 0x0000003F // 128 KB of Flash
+#define FLASH_FSIZE_SIZE_192KB 0x0000005F // 192 KB of Flash
+#define FLASH_FSIZE_SIZE_256KB 0x0000007F // 256 KB of Flash
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_SSIZE register.
+//
+//*****************************************************************************
+#define FLASH_SSIZE_SIZE_M 0x0000FFFF // SRAM Size
+#define FLASH_SSIZE_SIZE_2KB 0x00000007 // 2 KB of SRAM
+#define FLASH_SSIZE_SIZE_4KB 0x0000000F // 4 KB of SRAM
+#define FLASH_SSIZE_SIZE_6KB 0x00000017 // 6 KB of SRAM
+#define FLASH_SSIZE_SIZE_8KB 0x0000001F // 8 KB of SRAM
+#define FLASH_SSIZE_SIZE_12KB 0x0000002F // 12 KB of SRAM
+#define FLASH_SSIZE_SIZE_16KB 0x0000003F // 16 KB of SRAM
+#define FLASH_SSIZE_SIZE_20KB 0x0000004F // 20 KB of SRAM
+#define FLASH_SSIZE_SIZE_24KB 0x0000005F // 24 KB of SRAM
+#define FLASH_SSIZE_SIZE_32KB 0x0000007F // 32 KB of SRAM
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_ROMSWMAP register.
+//
+//*****************************************************************************
+#define FLASH_ROMSWMAP_SAFERTOS 0x00000001 // SafeRTOS Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_RMCTL register.
+//
+//*****************************************************************************
+#define FLASH_RMCTL_BA 0x00000001 // Boot Alias
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USECRL register.
+//
+//*****************************************************************************
+#define FLASH_USECRL_M 0x000000FF // Microsecond Reload Value
+#define FLASH_USECRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERDBG register.
+//
+//*****************************************************************************
+#define FLASH_USERDBG_NW 0x80000000 // User Debug Not Written
+#define FLASH_USERDBG_DATA_M 0x7FFFFFFC // User Data
+#define FLASH_USERDBG_DBG1 0x00000002 // Debug Control 1
+#define FLASH_USERDBG_DBG0 0x00000001 // Debug Control 0
+#define FLASH_USERDBG_DATA_S 2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_BOOTCFG register.
+//
+//*****************************************************************************
+#define FLASH_BOOTCFG_NW 0x80000000 // Not Written
+#define FLASH_BOOTCFG_PORT_M 0x0000E000 // Boot GPIO Port
+#define FLASH_BOOTCFG_PORT_A 0x00000000 // Port A
+#define FLASH_BOOTCFG_PORT_B 0x00002000 // Port B
+#define FLASH_BOOTCFG_PORT_C 0x00004000 // Port C
+#define FLASH_BOOTCFG_PORT_D 0x00006000 // Port D
+#define FLASH_BOOTCFG_PORT_E 0x00008000 // Port E
+#define FLASH_BOOTCFG_PORT_F 0x0000A000 // Port F
+#define FLASH_BOOTCFG_PORT_G 0x0000C000 // Port G
+#define FLASH_BOOTCFG_PORT_H 0x0000E000 // Port H
+#define FLASH_BOOTCFG_PIN_M 0x00001C00 // Boot GPIO Pin
+#define FLASH_BOOTCFG_PIN_0 0x00000000 // Pin 0
+#define FLASH_BOOTCFG_PIN_1 0x00000400 // Pin 1
+#define FLASH_BOOTCFG_PIN_2 0x00000800 // Pin 2
+#define FLASH_BOOTCFG_PIN_3 0x00000C00 // Pin 3
+#define FLASH_BOOTCFG_PIN_4 0x00001000 // Pin 4
+#define FLASH_BOOTCFG_PIN_5 0x00001400 // Pin 5
+#define FLASH_BOOTCFG_PIN_6 0x00001800 // Pin 6
+#define FLASH_BOOTCFG_PIN_7 0x00001C00 // Pin 7
+#define FLASH_BOOTCFG_POL 0x00000200 // Boot GPIO Polarity
+#define FLASH_BOOTCFG_EN 0x00000100 // Boot GPIO Enable
+#define FLASH_BOOTCFG_DBG1 0x00000002 // Debug Control 1
+#define FLASH_BOOTCFG_DBG0 0x00000001 // Debug Control 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG0 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG0_DATA_M 0xFFFFFFFF // User Data
+#define FLASH_USERREG0_NW 0x80000000 // Not Written
+#define FLASH_USERREG0_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG1 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG1_DATA_M 0xFFFFFFFF // User Data
+#define FLASH_USERREG1_NW 0x80000000 // Not Written
+#define FLASH_USERREG1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG2 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG2_DATA_M 0xFFFFFFFF // User Data
+#define FLASH_USERREG2_NW 0x80000000 // Not Written
+#define FLASH_USERREG2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG3 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG3_DATA_M 0xFFFFFFFF // User Data
+#define FLASH_USERREG3_NW 0x80000000 // Not Written
+#define FLASH_USERREG3_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPRE and
+// FLASH_FMPPE registers.
+//
+//*****************************************************************************
+#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31
+#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30
+#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29
+#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28
+#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27
+#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26
+#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25
+#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24
+#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23
+#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22
+#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21
+#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20
+#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19
+#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18
+#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17
+#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16
+#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15
+#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14
+#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13
+#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12
+#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11
+#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10
+#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9
+#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8
+#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7
+#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6
+#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5
+#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4
+#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3
+#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2
+#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1
+#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0
+
+//*****************************************************************************
+//
+// The following are defines for the erase size of the FLASH block that is
+// erased by an erase operation, and the protect size is the size of the FLASH
+// block that is protected by each protection register.
+//
+//*****************************************************************************
+#define FLASH_PROTECT_SIZE 0x00000800
+#define FLASH_ERASE_SIZE 0x00000400
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the FLASH register offsets.
+//
+//*****************************************************************************
+#define FLASH_RMVER 0x400FE0F4 // ROM Version Register
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the FLASH_FMC
+// register.
+//
+//*****************************************************************************
+#define FLASH_FMC_WRKEY_M 0xFFFF0000 // Flash Memory Write Key
+#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask
+#define FLASH_FMC_WRKEY_S 16
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the FLASH_FCRIS
+// register.
+//
+//*****************************************************************************
+#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status
+#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the FLASH_FCIM
+// register.
+//
+//*****************************************************************************
+#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask
+#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the FLASH_FCMISC
+// register.
+//
+//*****************************************************************************
+#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status
+#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the FLASH_RMVER
+// register.
+//
+//*****************************************************************************
+#define FLASH_RMVER_CONT_M 0xFF000000 // ROM Contents
+#define FLASH_RMVER_CONT_LM 0x00000000 // Stellaris Boot Loader &
+ // DriverLib
+#define FLASH_RMVER_CONT_LM_AES 0x02000000 // Stellaris Boot Loader &
+ // DriverLib with AES
+#define FLASH_RMVER_CONT_LM_AES_SAFERTOS \
+ 0x03000000 // Stellaris Boot Loader &
+ // DriverLib with AES and SAFERTOS
+#define FLASH_RMVER_CONT_LM_AES2 \
+ 0x05000000 // Stellaris Boot Loader &
+ // DriverLib with AES
+#define FLASH_RMVER_VER_M 0x0000FF00 // ROM Version
+#define FLASH_RMVER_REV_M 0x000000FF // ROM Revision
+#define FLASH_RMVER_VER_S 8
+#define FLASH_RMVER_REV_S 0
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the FLASH_USECRL
+// register.
+//
+//*****************************************************************************
+#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec
+#define FLASH_USECRL_SHIFT 0
+
+#endif
+
+#endif // __HW_FLASH_H__
diff --git a/inc/hw_gpio.h b/inc/hw_gpio.h new file mode 100644 index 0000000..9529e26 --- /dev/null +++ b/inc/hw_gpio.h @@ -0,0 +1,192 @@ +//*****************************************************************************
+//
+// hw_gpio.h - Defines and Macros for GPIO hardware.
+//
+// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 9453 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_GPIO_H__
+#define __HW_GPIO_H__
+
+//*****************************************************************************
+//
+// The following are defines for the GPIO register offsets.
+//
+//*****************************************************************************
+#define GPIO_O_DATA 0x00000000 // GPIO Data
+#define GPIO_O_DIR 0x00000400 // GPIO Direction
+#define GPIO_O_IS 0x00000404 // GPIO Interrupt Sense
+#define GPIO_O_IBE 0x00000408 // GPIO Interrupt Both Edges
+#define GPIO_O_IEV 0x0000040C // GPIO Interrupt Event
+#define GPIO_O_IM 0x00000410 // GPIO Interrupt Mask
+#define GPIO_O_RIS 0x00000414 // GPIO Raw Interrupt Status
+#define GPIO_O_MIS 0x00000418 // GPIO Masked Interrupt Status
+#define GPIO_O_ICR 0x0000041C // GPIO Interrupt Clear
+#define GPIO_O_AFSEL 0x00000420 // GPIO Alternate Function Select
+#define GPIO_O_DR2R 0x00000500 // GPIO 2-mA Drive Select
+#define GPIO_O_DR4R 0x00000504 // GPIO 4-mA Drive Select
+#define GPIO_O_DR8R 0x00000508 // GPIO 8-mA Drive Select
+#define GPIO_O_ODR 0x0000050C // GPIO Open Drain Select
+#define GPIO_O_PUR 0x00000510 // GPIO Pull-Up Select
+#define GPIO_O_PDR 0x00000514 // GPIO Pull-Down Select
+#define GPIO_O_SLR 0x00000518 // GPIO Slew Rate Control Select
+#define GPIO_O_DEN 0x0000051C // GPIO Digital Enable
+#define GPIO_O_LOCK 0x00000520 // GPIO Lock
+#define GPIO_O_CR 0x00000524 // GPIO Commit
+#define GPIO_O_AMSEL 0x00000528 // GPIO Analog Mode Select
+#define GPIO_O_PCTL 0x0000052C // GPIO Port Control
+#define GPIO_O_ADCCTL 0x00000530 // GPIO ADC Control
+#define GPIO_O_DMACTL 0x00000534 // GPIO DMA Control
+#define GPIO_O_SI 0x00000538 // GPIO Select Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_IM register.
+//
+//*****************************************************************************
+#define GPIO_IM_GPIO_M 0x000000FF // GPIO Interrupt Mask Enable
+#define GPIO_IM_GPIO_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_RIS register.
+//
+//*****************************************************************************
+#define GPIO_RIS_GPIO_M 0x000000FF // GPIO Interrupt Raw Status
+#define GPIO_RIS_GPIO_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_MIS register.
+//
+//*****************************************************************************
+#define GPIO_MIS_GPIO_M 0x000000FF // GPIO Masked Interrupt Status
+#define GPIO_MIS_GPIO_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_ICR register.
+//
+//*****************************************************************************
+#define GPIO_ICR_GPIO_M 0x000000FF // GPIO Interrupt Clear
+#define GPIO_ICR_GPIO_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_LOCK register.
+//
+//*****************************************************************************
+#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock
+#define GPIO_LOCK_UNLOCKED 0x00000000 // The GPIOCR register is unlocked
+ // and may be modified
+#define GPIO_LOCK_LOCKED 0x00000001 // The GPIOCR register is locked
+ // and may not be modified
+#define GPIO_LOCK_KEY 0x1ACCE551 // Unlocks the GPIO_CR register
+#define GPIO_LOCK_KEY_DD 0x4C4F434B // Unlocks the GPIO_CR register on
+ // DustDevil-class devices and
+ // later
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_SI register.
+//
+//*****************************************************************************
+#define GPIO_SI_SUM 0x00000001 // Summary Interrupt
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the GPIO register offsets.
+//
+//*****************************************************************************
+#define GPIO_O_PeriphID4 0x00000FD0
+#define GPIO_O_PeriphID5 0x00000FD4
+#define GPIO_O_PeriphID6 0x00000FD8
+#define GPIO_O_PeriphID7 0x00000FDC
+#define GPIO_O_PeriphID0 0x00000FE0
+#define GPIO_O_PeriphID1 0x00000FE4
+#define GPIO_O_PeriphID2 0x00000FE8
+#define GPIO_O_PeriphID3 0x00000FEC
+#define GPIO_O_PCellID0 0x00000FF0
+#define GPIO_O_PCellID1 0x00000FF4
+#define GPIO_O_PCellID2 0x00000FF8
+#define GPIO_O_PCellID3 0x00000FFC
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the GPIO Register reset values.
+//
+//*****************************************************************************
+#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV
+#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV
+#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV
+#define GPIO_RV_PCellID1 0x000000F0
+#define GPIO_RV_PCellID3 0x000000B1
+#define GPIO_RV_PeriphID0 0x00000061
+#define GPIO_RV_PeriphID1 0x00000010
+#define GPIO_RV_PCellID0 0x0000000D
+#define GPIO_RV_PCellID2 0x00000005
+#define GPIO_RV_PeriphID2 0x00000004
+#define GPIO_RV_LOCK 0x00000001 // Lock register RV
+#define GPIO_RV_PeriphID7 0x00000000
+#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV
+#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV
+#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV
+#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV
+#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV
+#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV
+#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV
+#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV
+#define GPIO_RV_PeriphID4 0x00000000
+#define GPIO_RV_PeriphID5 0x00000000
+#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV
+#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV
+#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV
+#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV
+#define GPIO_RV_DIR 0x00000000 // Data direction reg RV
+#define GPIO_RV_PeriphID6 0x00000000
+#define GPIO_RV_PeriphID3 0x00000000
+#define GPIO_RV_DATA 0x00000000 // Data register reset value
+#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV
+
+#endif
+
+#endif // __HW_GPIO_H__
diff --git a/inc/hw_hibernate.h b/inc/hw_hibernate.h new file mode 100644 index 0000000..a9f5df0 --- /dev/null +++ b/inc/hw_hibernate.h @@ -0,0 +1,286 @@ +//*****************************************************************************
+//
+// hw_hibernate.h - Defines and Macros for the Hibernation module.
+//
+// Copyright (c) 2007-2012 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 9453 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_HIBERNATE_H__
+#define __HW_HIBERNATE_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Hibernation module register addresses.
+//
+//*****************************************************************************
+#define HIB_RTCC 0x400FC000 // Hibernation RTC Counter
+#define HIB_RTCM0 0x400FC004 // Hibernation RTC Match 0
+#define HIB_RTCM1 0x400FC008 // Hibernation RTC Match 1
+#define HIB_RTCLD 0x400FC00C // Hibernation RTC Load
+#define HIB_CTL 0x400FC010 // Hibernation Control
+#define HIB_IM 0x400FC014 // Hibernation Interrupt Mask
+#define HIB_RIS 0x400FC018 // Hibernation Raw Interrupt Status
+#define HIB_MIS 0x400FC01C // Hibernation Masked Interrupt
+ // Status
+#define HIB_IC 0x400FC020 // Hibernation Interrupt Clear
+#define HIB_RTCT 0x400FC024 // Hibernation RTC Trim
+#define HIB_RTCSS 0x400FC028 // Hibernation RTC Sub Seconds
+#define HIB_DATA 0x400FC030 // Hibernation Data
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCC register.
+//
+//*****************************************************************************
+#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter
+#define HIB_RTCC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCM0 register.
+//
+//*****************************************************************************
+#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0
+#define HIB_RTCM0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCM1 register.
+//
+//*****************************************************************************
+#define HIB_RTCM1_M 0xFFFFFFFF // RTC Match 1
+#define HIB_RTCM1_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCLD register.
+//
+//*****************************************************************************
+#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load
+#define HIB_RTCLD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CTL register.
+//
+//*****************************************************************************
+#define HIB_CTL_WRC 0x80000000 // Write Complete/Capable
+#define HIB_CTL_OSCDRV 0x00020000 // Oscillator Drive Capability
+#define HIB_CTL_OSCBYP 0x00010000 // Oscillator Bypass
+#define HIB_CTL_VBATSEL_M 0x00006000 // Select for Low-Battery
+ // Comparator
+#define HIB_CTL_VBATSEL_1_9V 0x00000000 // 1.9 Volts
+#define HIB_CTL_VBATSEL_2_1V 0x00002000 // 2.1 Volts (default)
+#define HIB_CTL_VBATSEL_2_3V 0x00004000 // 2.3 Volts
+#define HIB_CTL_VBATSEL_2_5V 0x00006000 // 2.5 Volts
+#define HIB_CTL_BATCHK 0x00000400 // Check Battery Status
+#define HIB_CTL_BATWKEN 0x00000200 // Wake on Low Battery
+#define HIB_CTL_VDD3ON 0x00000100 // VDD Powered
+#define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable
+#define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable
+#define HIB_CTL_LOWBATEN 0x00000020 // Low Battery Monitoring Enable
+#define HIB_CTL_PINWEN 0x00000010 // External WAKE Pin Enable
+#define HIB_CTL_RTCWEN 0x00000008 // RTC Wake-up Enable
+#define HIB_CTL_CLKSEL 0x00000004 // Hibernation Module Clock Select
+#define HIB_CTL_HIBREQ 0x00000002 // Hibernation Request
+#define HIB_CTL_RTCEN 0x00000001 // RTC Timer Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_IM register.
+//
+//*****************************************************************************
+#define HIB_IM_WC 0x00000010 // External Write Complete/Capable
+ // Interrupt Mask
+#define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask
+#define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt
+ // Mask
+#define HIB_IM_RTCALT1 0x00000002 // RTC Alert 1 Interrupt Mask
+#define HIB_IM_RTCALT0 0x00000001 // RTC Alert 0 Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RIS register.
+//
+//*****************************************************************************
+#define HIB_RIS_WC 0x00000010 // Write Complete/Capable Raw
+ // Interrupt Status
+#define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt
+ // Status
+#define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw
+ // Interrupt Status
+#define HIB_RIS_RTCALT1 0x00000002 // RTC Alert 1 Raw Interrupt Status
+#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert 0 Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_MIS register.
+//
+//*****************************************************************************
+#define HIB_MIS_WC 0x00000010 // Write Complete/Capable Masked
+ // Interrupt Status
+#define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked
+ // Interrupt Status
+#define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked
+ // Interrupt Status
+#define HIB_MIS_RTCALT1 0x00000002 // RTC Alert 1 Masked Interrupt
+ // Status
+#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert 0 Masked Interrupt
+ // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_IC register.
+//
+//*****************************************************************************
+#define HIB_IC_WC 0x00000010 // Write Complete/Capable Masked
+ // Interrupt Clear
+#define HIB_IC_EXTW 0x00000008 // External Wake-Up Masked
+ // Interrupt Clear
+#define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Masked
+ // Interrupt Clear
+#define HIB_IC_RTCALT1 0x00000002 // RTC Alert1 Masked Interrupt
+ // Clear
+#define HIB_IC_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt
+ // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCT register.
+//
+//*****************************************************************************
+#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value
+#define HIB_RTCT_TRIM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCSS register.
+//
+//*****************************************************************************
+#define HIB_RTCSS_RTCSSM_M 0x7FFF0000 // RTC Sub Seconds Match
+#define HIB_RTCSS_RTCSSC_M 0x00007FFF // RTC Sub Seconds Count
+#define HIB_RTCSS_RTCSSM_S 16
+#define HIB_RTCSS_RTCSSC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_DATA register.
+//
+//*****************************************************************************
+#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV Data
+#define HIB_DATA_RTD_S 0
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the Hibernation module register
+// addresses.
+//
+//*****************************************************************************
+#define HIB_DATA_END 0x400FC130 // end of data area, exclusive
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the HIB_RTCC
+// register.
+//
+//*****************************************************************************
+#define HIB_RTCC_MASK 0xFFFFFFFF // RTC counter mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the HIB_RTCM0
+// register.
+//
+//*****************************************************************************
+#define HIB_RTCM0_MASK 0xFFFFFFFF // RTC match 0 mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the HIB_RTCM1
+// register.
+//
+//*****************************************************************************
+#define HIB_RTCM1_MASK 0xFFFFFFFF // RTC match 1 mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the HIB_RTCLD
+// register.
+//
+//*****************************************************************************
+#define HIB_RTCLD_MASK 0xFFFFFFFF // RTC load mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the HIB_RIS
+// register.
+//
+//*****************************************************************************
+#define HIB_RID_RTCALT0 0x00000001 // RTC match 0 interrupt
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the HIB_MIS
+// register.
+//
+//*****************************************************************************
+#define HIB_MID_RTCALT0 0x00000001 // RTC match 0 interrupt
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the HIB_RTCT
+// register.
+//
+//*****************************************************************************
+#define HIB_RTCT_MASK 0x0000FFFF // RTC trim mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the HIB_DATA
+// register.
+//
+//*****************************************************************************
+#define HIB_DATA_MASK 0xFFFFFFFF // NV memory data mask
+
+#endif
+
+#endif // __HW_HIBERNATE_H__
diff --git a/inc/hw_i2c.h b/inc/hw_i2c.h new file mode 100644 index 0000000..96f52fb --- /dev/null +++ b/inc/hw_i2c.h @@ -0,0 +1,489 @@ +//*****************************************************************************
+//
+// hw_i2c.h - Macros used when accessing the I2C master and slave hardware.
+//
+// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 9453 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_I2C_H__
+#define __HW_I2C_H__
+
+//*****************************************************************************
+//
+// The following are defines for the I2C register offsets.
+//
+//*****************************************************************************
+#define I2C_O_MSA 0x00000000 // I2C Master Slave Address
+#define I2C_O_SOAR 0x00000000 // I2C Slave Own Address
+#define I2C_O_SCSR 0x00000004 // I2C Slave Control/Status
+#define I2C_O_MCS 0x00000004 // I2C Master Control/Status
+#define I2C_O_SDR 0x00000008 // I2C Slave Data
+#define I2C_O_MDR 0x00000008 // I2C Master Data
+#define I2C_O_MTPR 0x0000000C // I2C Master Timer Period
+#define I2C_O_SIMR 0x0000000C // I2C Slave Interrupt Mask
+#define I2C_O_SRIS 0x00000010 // I2C Slave Raw Interrupt Status
+#define I2C_O_MIMR 0x00000010 // I2C Master Interrupt Mask
+#define I2C_O_MRIS 0x00000014 // I2C Master Raw Interrupt Status
+#define I2C_O_SMIS 0x00000014 // I2C Slave Masked Interrupt
+ // Status
+#define I2C_O_SICR 0x00000018 // I2C Slave Interrupt Clear
+#define I2C_O_MMIS 0x00000018 // I2C Master Masked Interrupt
+ // Status
+#define I2C_O_MICR 0x0000001C // I2C Master Interrupt Clear
+#define I2C_O_SOAR2 0x0000001C // I2C Slave Own Address 2
+#define I2C_O_MCR 0x00000020 // I2C Master Configuration
+#define I2C_O_SACKCTL 0x00000020 // I2C Slave ACK Control
+#define I2C_O_MCLKOCNT 0x00000024 // I2C Master Clock Low Timeout
+ // Count
+#define I2C_O_MBMON 0x0000002C // I2C Master Bus Monitor
+#define I2C_O_PP 0x00000FC0 // I2C Peripheral Properties
+#define I2C_O_PC 0x00000FC4 // I2C Peripheral Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MSA register.
+//
+//*****************************************************************************
+#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address
+#define I2C_MSA_RS 0x00000001 // Receive not send
+#define I2C_MSA_SA_S 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SOAR register.
+//
+//*****************************************************************************
+#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address
+#define I2C_SOAR_OAR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SCSR register.
+//
+//*****************************************************************************
+#define I2C_SCSR_QCMDRW 0x00000020 // Quick Command Read / Write
+#define I2C_SCSR_QCMDST 0x00000010 // Quick Command Status
+#define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched
+#define I2C_SCSR_FBR 0x00000004 // First Byte Received
+#define I2C_SCSR_TREQ 0x00000002 // Transmit Request
+#define I2C_SCSR_DA 0x00000001 // Device Active
+#define I2C_SCSR_RREQ 0x00000001 // Receive Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCS register.
+//
+//*****************************************************************************
+#define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error
+#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy
+#define I2C_MCS_IDLE 0x00000020 // I2C Idle
+#define I2C_MCS_QCMD 0x00000020 // Quick Command
+#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost
+#define I2C_MCS_HS 0x00000010 // High-Speed Enable
+#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable
+#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data
+#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address
+#define I2C_MCS_STOP 0x00000004 // Generate STOP
+#define I2C_MCS_ERROR 0x00000002 // Error
+#define I2C_MCS_START 0x00000002 // Generate START
+#define I2C_MCS_RUN 0x00000001 // I2C Master Enable
+#define I2C_MCS_BUSY 0x00000001 // I2C Busy
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SDR register.
+//
+//*****************************************************************************
+#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer
+#define I2C_SDR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MDR register.
+//
+//*****************************************************************************
+#define I2C_MDR_DATA_M 0x000000FF // Data Transferred
+#define I2C_MDR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MTPR register.
+//
+//*****************************************************************************
+#define I2C_MTPR_HS 0x00000080 // High-Speed Enable
+#define I2C_MTPR_TPR_M 0x0000007F // SCL Clock Period
+#define I2C_MTPR_TPR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SIMR register.
+//
+//*****************************************************************************
+#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask
+#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask
+#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SRIS register.
+//
+//*****************************************************************************
+#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt
+ // Status
+#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt
+ // Status
+#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MIMR register.
+//
+//*****************************************************************************
+#define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask
+#define I2C_MIMR_IM 0x00000001 // Master Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MRIS register.
+//
+//*****************************************************************************
+#define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt
+ // Status
+#define I2C_MRIS_RIS 0x00000001 // Master Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SMIS register.
+//
+//*****************************************************************************
+#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt
+ // Status
+#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt
+ // Status
+#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SICR register.
+//
+//*****************************************************************************
+#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear
+#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear
+#define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MMIS register.
+//
+//*****************************************************************************
+#define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt
+ // Status
+#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MICR register.
+//
+//*****************************************************************************
+#define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear
+#define I2C_MICR_IC 0x00000001 // Master Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SOAR2 register.
+//
+//*****************************************************************************
+#define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable
+#define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2
+#define I2C_SOAR2_OAR2_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCR register.
+//
+//*****************************************************************************
+#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable
+#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable
+#define I2C_MCR_LPBK 0x00000001 // I2C Loopback
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SACKCTL register.
+//
+//*****************************************************************************
+#define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value
+#define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCLKOCNT register.
+//
+//*****************************************************************************
+#define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count
+#define I2C_MCLKOCNT_CNTL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MBMON register.
+//
+//*****************************************************************************
+#define I2C_MBMON_SDA 0x00000002 // I2C SDA Status
+#define I2C_MBMON_SCL 0x00000001 // I2C SCL Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_PP register.
+//
+//*****************************************************************************
+#define I2C_PP_HS 0x00000001 // High-Speed Capable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_PC register.
+//
+//*****************************************************************************
+#define I2C_PC_HS 0x00000001 // High-Speed Capable
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the I2C register offsets.
+//
+//*****************************************************************************
+#define I2C_O_SLAVE 0x00000800 // Offset from master to slave
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C_O_SIMR
+// register.
+//
+//*****************************************************************************
+#define I2C_SIMR_IM 0x00000001 // Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C_O_SRIS
+// register.
+//
+//*****************************************************************************
+#define I2C_SRIS_RIS 0x00000001 // Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C_O_SMIS
+// register.
+//
+//*****************************************************************************
+#define I2C_SMIS_MIS 0x00000001 // Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C_O_SICR
+// register.
+//
+//*****************************************************************************
+#define I2C_SICR_IC 0x00000001 // Clear Interrupt
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the I2C master register offsets.
+//
+//*****************************************************************************
+#define I2C_MASTER_O_SA 0x00000000 // Slave address register
+#define I2C_MASTER_O_CS 0x00000004 // Control and Status register
+#define I2C_MASTER_O_DR 0x00000008 // Data register
+#define I2C_MASTER_O_TPR 0x0000000C // Timer period register
+#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register
+#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register
+#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg
+#define I2C_MASTER_O_MICR 0x0000001C // Interrupt clear register
+#define I2C_MASTER_O_CR 0x00000020 // Configuration register
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the I2C slave register offsets.
+//
+//*****************************************************************************
+#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register
+#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg
+#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register
+#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register
+#define I2C_SLAVE_O_DR 0x00000008 // Data register
+#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register
+#define I2C_SLAVE_O_OAR 0x00000000 // Own address register
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C master
+// slave address register.
+//
+//*****************************************************************************
+#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address
+#define I2C_MASTER_SA_RS 0x00000001 // Receive/send
+#define I2C_MASTER_SA_SA_SHIFT 1
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Master
+// Control and Status register.
+//
+//*****************************************************************************
+#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy
+#define I2C_MASTER_CS_IDLE 0x00000020 // Idle
+#define I2C_MASTER_CS_ERR_MASK 0x0000001C
+#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data
+#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred
+#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged
+#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged
+#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration
+#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde
+#define I2C_MASTER_CS_STOP 0x00000004 // Stop
+#define I2C_MASTER_CS_START 0x00000002 // Start
+#define I2C_MASTER_CS_RUN 0x00000001 // Run
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the values used in determining the
+// contents of the I2C Master Timer Period register.
+//
+//*****************************************************************************
+#define I2C_SCL_FAST 400000 // SCL fast frequency
+#define I2C_SCL_STANDARD 100000 // SCL standard frequency
+#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period
+#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period
+#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP)
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Master
+// Interrupt Mask register.
+//
+//*****************************************************************************
+#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Master
+// Raw Interrupt Status register.
+//
+//*****************************************************************************
+#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Master
+// Masked Interrupt Status register.
+//
+//*****************************************************************************
+#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Master
+// Interrupt Clear register.
+//
+//*****************************************************************************
+#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Master
+// Configuration register.
+//
+//*****************************************************************************
+#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable
+#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable
+#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Slave Own
+// Address register.
+//
+//*****************************************************************************
+#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Slave
+// Control/Status register.
+//
+//*****************************************************************************
+#define I2C_SLAVE_CSR_FBR 0x00000004 // First byte received from master
+#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received
+#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device
+#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Slave
+// Interrupt Mask register.
+//
+//*****************************************************************************
+#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Slave Raw
+// Interrupt Status register.
+//
+//*****************************************************************************
+#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Slave
+// Masked Interrupt Status register.
+//
+//*****************************************************************************
+#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the I2C Slave
+// Interrupt Clear register.
+//
+//*****************************************************************************
+#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear
+
+#endif
+
+#endif // __HW_I2C_H__
diff --git a/inc/hw_i2s.h b/inc/hw_i2s.h new file mode 100644 index 0000000..30b39d9 --- /dev/null +++ b/inc/hw_i2s.h @@ -0,0 +1,239 @@ +//*****************************************************************************
+//
+// hw_i2s.h - Macros for use in accessing the I2S registers.
+//
+// Copyright (c) 2008-2012 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 9453 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_I2S_H__
+#define __HW_I2S_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Inter-Integrated Circuit Sound register
+// offsets.
+//
+//*****************************************************************************
+#define I2S_O_TXFIFO 0x00000000 // I2S Transmit FIFO Data
+#define I2S_O_TXFIFOCFG 0x00000004 // I2S Transmit FIFO Configuration
+#define I2S_O_TXCFG 0x00000008 // I2S Transmit Module
+ // Configuration
+#define I2S_O_TXLIMIT 0x0000000C // I2S Transmit FIFO Limit
+#define I2S_O_TXISM 0x00000010 // I2S Transmit Interrupt Status
+ // and Mask
+#define I2S_O_TXLEV 0x00000018 // I2S Transmit FIFO Level
+#define I2S_O_RXFIFO 0x00000800 // I2S Receive FIFO Data
+#define I2S_O_RXFIFOCFG 0x00000804 // I2S Receive FIFO Configuration
+#define I2S_O_RXCFG 0x00000808 // I2S Receive Module Configuration
+#define I2S_O_RXLIMIT 0x0000080C // I2S Receive FIFO Limit
+#define I2S_O_RXISM 0x00000810 // I2S Receive Interrupt Status and
+ // Mask
+#define I2S_O_RXLEV 0x00000818 // I2S Receive FIFO Level
+#define I2S_O_CFG 0x00000C00 // I2S Module Configuration
+#define I2S_O_IM 0x00000C10 // I2S Interrupt Mask
+#define I2S_O_RIS 0x00000C14 // I2S Raw Interrupt Status
+#define I2S_O_MIS 0x00000C18 // I2S Masked Interrupt Status
+#define I2S_O_IC 0x00000C1C // I2S Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_TXFIFO register.
+//
+//*****************************************************************************
+#define I2S_TXFIFO_M 0xFFFFFFFF // TX Data
+#define I2S_TXFIFO_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_TXFIFOCFG
+// register.
+//
+//*****************************************************************************
+#define I2S_TXFIFOCFG_CSS 0x00000002 // Compact Stereo Sample Size
+#define I2S_TXFIFOCFG_LRS 0x00000001 // Left-Right Sample Indicator
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_TXCFG register.
+//
+//*****************************************************************************
+#define I2S_TXCFG_JST 0x20000000 // Justification of Output Data
+#define I2S_TXCFG_DLY 0x10000000 // Data Delay
+#define I2S_TXCFG_SCP 0x08000000 // SCLK Polarity
+#define I2S_TXCFG_LRP 0x04000000 // Left/Right Clock Polarity
+#define I2S_TXCFG_WM_M 0x03000000 // Write Mode
+#define I2S_TXCFG_WM_DUAL 0x00000000 // Stereo mode
+#define I2S_TXCFG_WM_COMPACT 0x01000000 // Compact Stereo mode
+#define I2S_TXCFG_WM_MONO 0x02000000 // Mono mode
+#define I2S_TXCFG_FMT 0x00800000 // FIFO Empty
+#define I2S_TXCFG_MSL 0x00400000 // SCLK Master/Slave
+#define I2S_TXCFG_SSZ_M 0x0000FC00 // Sample Size
+#define I2S_TXCFG_SDSZ_M 0x000003F0 // System Data Size
+#define I2S_TXCFG_SSZ_S 10
+#define I2S_TXCFG_SDSZ_S 4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_TXLIMIT register.
+//
+//*****************************************************************************
+#define I2S_TXLIMIT_LIMIT_M 0x0000001F // FIFO Limit
+#define I2S_TXLIMIT_LIMIT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_TXISM register.
+//
+//*****************************************************************************
+#define I2S_TXISM_FFI 0x00010000 // Transmit FIFO Service Request
+ // Interrupt
+#define I2S_TXISM_FFM 0x00000001 // FIFO Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_TXLEV register.
+//
+//*****************************************************************************
+#define I2S_TXLEV_LEVEL_M 0x0000001F // Number of Audio Samples
+#define I2S_TXLEV_LEVEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_RXFIFO register.
+//
+//*****************************************************************************
+#define I2S_RXFIFO_M 0xFFFFFFFF // RX Data
+#define I2S_RXFIFO_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_RXFIFOCFG
+// register.
+//
+//*****************************************************************************
+#define I2S_RXFIFOCFG_FMM 0x00000004 // FIFO Mono Mode
+#define I2S_RXFIFOCFG_CSS 0x00000002 // Compact Stereo Sample Size
+#define I2S_RXFIFOCFG_LRS 0x00000001 // Left-Right Sample Indicator
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_RXCFG register.
+//
+//*****************************************************************************
+#define I2S_RXCFG_JST 0x20000000 // Justification of Input Data
+#define I2S_RXCFG_DLY 0x10000000 // Data Delay
+#define I2S_RXCFG_SCP 0x08000000 // SCLK Polarity
+#define I2S_RXCFG_LRP 0x04000000 // Left/Right Clock Polarity
+#define I2S_RXCFG_RM 0x01000000 // Read Mode
+#define I2S_RXCFG_MSL 0x00400000 // SCLK Master/Slave
+#define I2S_RXCFG_SSZ_M 0x0000FC00 // Sample Size
+#define I2S_RXCFG_SDSZ_M 0x000003F0 // System Data Size
+#define I2S_RXCFG_SSZ_S 10
+#define I2S_RXCFG_SDSZ_S 4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_RXLIMIT register.
+//
+//*****************************************************************************
+#define I2S_RXLIMIT_LIMIT_M 0x0000001F // FIFO Limit
+#define I2S_RXLIMIT_LIMIT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_RXISM register.
+//
+//*****************************************************************************
+#define I2S_RXISM_FFI 0x00010000 // Receive FIFO Service Request
+ // Interrupt
+#define I2S_RXISM_FFM 0x00000001 // FIFO Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_RXLEV register.
+//
+//*****************************************************************************
+#define I2S_RXLEV_LEVEL_M 0x0000001F // Number of Audio Samples
+#define I2S_RXLEV_LEVEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_CFG register.
+//
+//*****************************************************************************
+#define I2S_CFG_RXSLV 0x00000020 // Use External I2S0RXMCLK
+#define I2S_CFG_TXSLV 0x00000010 // Use External I2S0TXMCLK
+#define I2S_CFG_RXEN 0x00000002 // Serial Receive Engine Enable
+#define I2S_CFG_TXEN 0x00000001 // Serial Transmit Engine Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_IM register.
+//
+//*****************************************************************************
+#define I2S_IM_RXRE 0x00000020 // Receive FIFO Read Error
+#define I2S_IM_RXFSR 0x00000010 // Receive FIFO Service Request
+#define I2S_IM_TXWE 0x00000002 // Transmit FIFO Write Error
+#define I2S_IM_TXFSR 0x00000001 // Transmit FIFO Service Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_RIS register.
+//
+//*****************************************************************************
+#define I2S_RIS_RXRE 0x00000020 // Receive FIFO Read Error
+#define I2S_RIS_RXFSR 0x00000010 // Receive FIFO Service Request
+#define I2S_RIS_TXWE 0x00000002 // Transmit FIFO Write Error
+#define I2S_RIS_TXFSR 0x00000001 // Transmit FIFO Service Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_MIS register.
+//
+//*****************************************************************************
+#define I2S_MIS_RXRE 0x00000020 // Receive FIFO Read Error
+#define I2S_MIS_RXFSR 0x00000010 // Receive FIFO Service Request
+#define I2S_MIS_TXWE 0x00000002 // Transmit FIFO Write Error
+#define I2S_MIS_TXFSR 0x00000001 // Transmit FIFO Service Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2S_O_IC register.
+//
+//*****************************************************************************
+#define I2S_IC_RXRE 0x00000020 // Receive FIFO Read Error
+#define I2S_IC_TXWE 0x00000002 // Transmit FIFO Write Error
+
+#endif // __HW_I2S_H__
diff --git a/inc/hw_ints.h b/inc/hw_ints.h new file mode 100644 index 0000000..0445c29 --- /dev/null +++ b/inc/hw_ints.h @@ -0,0 +1,217 @@ +//*****************************************************************************
+//
+// hw_ints.h - Macros that define the interrupt assignment on Stellaris.
+//
+// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 9453 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_INTS_H__
+#define __HW_INTS_H__
+
+//*****************************************************************************
+//
+// The following are defines for the fault assignments.
+//
+//*****************************************************************************
+#define FAULT_NMI 2 // NMI fault
+#define FAULT_HARD 3 // Hard fault
+#define FAULT_MPU 4 // MPU fault
+#define FAULT_BUS 5 // Bus fault
+#define FAULT_USAGE 6 // Usage fault
+#define FAULT_SVCALL 11 // SVCall
+#define FAULT_DEBUG 12 // Debug monitor
+#define FAULT_PENDSV 14 // PendSV
+#define FAULT_SYSTICK 15 // System Tick
+
+//*****************************************************************************
+//
+// The following are defines for the interrupt assignments.
+//
+//*****************************************************************************
+#define INT_GPIOA 16 // GPIO Port A
+#define INT_GPIOB 17 // GPIO Port B
+#define INT_GPIOC 18 // GPIO Port C
+#define INT_GPIOD 19 // GPIO Port D
+#define INT_GPIOE 20 // GPIO Port E
+#define INT_UART0 21 // UART0 Rx and Tx
+#define INT_UART1 22 // UART1 Rx and Tx
+#define INT_SSI0 23 // SSI0 Rx and Tx
+#define INT_I2C0 24 // I2C0 Master and Slave
+#define INT_PWM0_FAULT 25 // PWM0 Fault
+#define INT_PWM0_0 26 // PWM0 Generator 0
+#define INT_PWM0_1 27 // PWM0 Generator 1
+#define INT_PWM0_2 28 // PWM0 Generator 2
+#define INT_QEI0 29 // Quadrature Encoder 0
+#define INT_ADC0SS0 30 // ADC0 Sequence 0
+#define INT_ADC0SS1 31 // ADC0 Sequence 1
+#define INT_ADC0SS2 32 // ADC0 Sequence 2
+#define INT_ADC0SS3 33 // ADC0 Sequence 3
+#define INT_WATCHDOG 34 // Watchdog timer
+#define INT_TIMER0A 35 // Timer 0 subtimer A
+#define INT_TIMER0B 36 // Timer 0 subtimer B
+#define INT_TIMER1A 37 // Timer 1 subtimer A
+#define INT_TIMER1B 38 // Timer 1 subtimer B
+#define INT_TIMER2A 39 // Timer 2 subtimer A
+#define INT_TIMER2B 40 // Timer 2 subtimer B
+#define INT_COMP0 41 // Analog Comparator 0
+#define INT_COMP1 42 // Analog Comparator 1
+#define INT_COMP2 43 // Analog Comparator 2
+#define INT_SYSCTL 44 // System Control (PLL, OSC, BO)
+#define INT_FLASH 45 // FLASH Control
+#define INT_GPIOF 46 // GPIO Port F
+#define INT_GPIOG 47 // GPIO Port G
+#define INT_GPIOH 48 // GPIO Port H
+#define INT_UART2 49 // UART2 Rx and Tx
+#define INT_SSI1 50 // SSI1 Rx and Tx
+#define INT_TIMER3A 51 // Timer 3 subtimer A
+#define INT_TIMER3B 52 // Timer 3 subtimer B
+#define INT_I2C1 53 // I2C1 Master and Slave
+#define INT_QEI1 54 // Quadrature Encoder 1
+#define INT_CAN0 55 // CAN0
+#define INT_CAN1 56 // CAN1
+#define INT_CAN2 57 // CAN2
+#define INT_ETH 58 // Ethernet
+#define INT_HIBERNATE 59 // Hibernation module
+#define INT_USB0 60 // USB 0 Controller
+#define INT_PWM0_3 61 // PWM0 Generator 3
+#define INT_UDMA 62 // uDMA controller
+#define INT_UDMAERR 63 // uDMA Error
+#define INT_ADC1SS0 64 // ADC1 Sequence 0
+#define INT_ADC1SS1 65 // ADC1 Sequence 1
+#define INT_ADC1SS2 66 // ADC1 Sequence 2
+#define INT_ADC1SS3 67 // ADC1 Sequence 3
+#define INT_I2S0 68 // I2S0
+#define INT_EPI0 69 // EPI0
+#define INT_GPIOJ 70 // GPIO Port J
+#define INT_GPIOK 71 // GPIO Port K
+#define INT_GPIOL 72 // GPIO Port L
+#define INT_SSI2 73 // SSI2
+#define INT_SSI3 74 // SSI3
+#define INT_UART3 75 // UART3
+#define INT_UART4 76 // UART4
+#define INT_UART5 77 // UART5
+#define INT_UART6 78 // UART6
+#define INT_UART7 79 // UART7
+#define INT_I2C2 84 // I2C2
+#define INT_I2C3 85 // I2C3
+#define INT_TIMER4A 86 // Timer 4A
+#define INT_TIMER4B 87 // Timer 4B
+#define INT_TIMER5A 108 // Timer 5A
+#define INT_TIMER5B 109 // Timer 5B
+#define INT_WTIMER0A 110 // Wide Timer 0A
+#define INT_WTIMER0B 111 // Wide Timer 0B
+#define INT_WTIMER1A 112 // Wide Timer 1A
+#define INT_WTIMER1B 113 // Wide Timer 1B
+#define INT_WTIMER2A 114 // Wide Timer 2A
+#define INT_WTIMER2B 115 // Wide Timer 2B
+#define INT_WTIMER3A 116 // Wide Timer 3A
+#define INT_WTIMER3B 117 // Wide Timer 3B
+#define INT_WTIMER4A 118 // Wide Timer 4A
+#define INT_WTIMER4B 119 // Wide Timer 4B
+#define INT_WTIMER5A 120 // Wide Timer 5A
+#define INT_WTIMER5B 121 // Wide Timer 5B
+#define INT_SYSEXC 122 // System Exception (imprecise)
+#define INT_PECI0 123 // PECI 0
+#define INT_LPC0 124 // LPC 0
+#define INT_I2C4 125 // I2C4
+#define INT_I2C5 126 // I2C5
+#define INT_GPIOM 127 // GPIO Port M
+#define INT_GPION 128 // GPIO Port N
+#define INT_FAN0 130 // FAN 0
+#define INT_GPIOP0 132 // GPIO Port P (Summary or P0)
+#define INT_GPIOP1 133 // GPIO Port P1
+#define INT_GPIOP2 134 // GPIO Port P2
+#define INT_GPIOP3 135 // GPIO Port P3
+#define INT_GPIOP4 136 // GPIO Port P4
+#define INT_GPIOP5 137 // GPIO Port P5
+#define INT_GPIOP6 138 // GPIO Port P6
+#define INT_GPIOP7 139 // GPIO Port P7
+#define INT_GPIOQ0 140 // GPIO Port Q (Summary or Q0)
+#define INT_GPIOQ1 141 // GPIO Port Q1
+#define INT_GPIOQ2 142 // GPIO Port Q2
+#define INT_GPIOQ3 143 // GPIO Port Q3
+#define INT_GPIOQ4 144 // GPIO Port Q4
+#define INT_GPIOQ5 145 // GPIO Port Q5
+#define INT_GPIOQ6 146 // GPIO Port Q6
+#define INT_GPIOQ7 147 // GPIO Port Q7
+#define INT_PWM1_0 150 // PWM1 Generator 0
+#define INT_PWM1_1 151 // PWM1 Generator 1
+#define INT_PWM1_2 152 // PWM1 Generator 2
+#define INT_PWM1_3 153 // PWM1 Generator 3
+#define INT_PWM1_FAULT 154 // PWM1 Fault
+
+//*****************************************************************************
+//
+// The following are defines for the total number of interrupts.
+//
+//*****************************************************************************
+#define NUM_INTERRUPTS 155
+
+//*****************************************************************************
+//
+// The following are defines for the total number of priority levels.
+//
+//*****************************************************************************
+#define NUM_PRIORITY 8
+#define NUM_PRIORITY_BITS 3
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the interrupt assignments.
+//
+//*****************************************************************************
+#define INT_SSI 23 // SSI Rx and Tx
+#define INT_I2C 24 // I2C Master and Slave
+#define INT_PWM_FAULT 25 // PWM Fault
+#define INT_PWM0 26 // PWM Generator 0
+#define INT_PWM1 27 // PWM Generator 1
+#define INT_PWM2 28 // PWM Generator 2
+#define INT_QEI 29 // Quadrature Encoder
+#define INT_ADC0 30 // ADC Sequence 0
+#define INT_ADC1 31 // ADC Sequence 1
+#define INT_ADC2 32 // ADC Sequence 2
+#define INT_ADC3 33 // ADC Sequence 3
+#define INT_PWM3 61 // PWM Generator 3
+
+#endif
+
+#endif // __HW_INTS_H__
diff --git a/inc/hw_lpc.h b/inc/hw_lpc.h new file mode 100644 index 0000000..3033661 --- /dev/null +++ b/inc/hw_lpc.h @@ -0,0 +1,909 @@ +//*****************************************************************************
+//
+// hw_lpc.h - Macros used when accessing the LPC hardware.
+//
+// Copyright (c) 2010-2012 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 9453 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_LPC_H__
+#define __HW_LPC_H__
+
+//*****************************************************************************
+//
+// The following are defines for the LPC register addresses.
+//
+//*****************************************************************************
+#define LPC_O_CTL 0x00000000 // LPC Control
+#define LPC_O_STS 0x00000004 // LPC Status
+#define LPC_O_IRQCTL 0x00000008 // LPC IRQ Control
+#define LPC_O_IRQST 0x0000000C // LPC IRQ Status
+#define LPC_O_CH0CTL 0x00000010 // LPC Channel 0 Control
+#define LPC_O_CH0ST 0x00000014 // LPC Channel 0 Status
+#define LPC_O_CH0ADR 0x00000018 // LPC Channel 0 Address
+#define LPC_O_CH1CTL 0x00000020 // LPC Channel 1 Control
+#define LPC_O_CH1ST 0x00000024 // LPC Channel 1 Status
+#define LPC_O_CH1ADR 0x00000028 // LPC Channel 1 Address
+#define LPC_O_CH2CTL 0x00000030 // LPC Channel 2 Control
+#define LPC_O_CH2ST 0x00000034 // LPC Channel 2 Status
+#define LPC_O_CH2ADR 0x00000038 // LPC Channel 2 Address
+#define LPC_O_CH3CTL 0x00000040 // LPC Channel 3 Control
+#define LPC_O_CH3ST 0x00000044 // LPC Channel 3 Status
+#define LPC_O_CH3ADR 0x00000048 // LPC Channel 3 Address
+#define LPC_O_CH4CTL 0x00000050 // LPC Channel 4 Control
+#define LPC_O_CH4ST 0x00000054 // LPC Channel 4 Status
+#define LPC_O_CH4ADR 0x00000058 // LPC Channel 4 Address
+#define LPC_O_CH5CTL 0x00000060 // LPC Channel 5 Control
+#define LPC_O_CH5ST 0x00000064 // LPC Channel 5 Status
+#define LPC_O_CH5ADR 0x00000068 // LPC Channel 5 Address
+#define LPC_O_CH6CTL 0x00000070 // LPC Channel 6 Control
+#define LPC_O_CH6ST 0x00000074 // LPC Channel 6 Status
+#define LPC_O_CH6ADR 0x00000078 // LPC Channel 6 Address
+#define LPC_O_CH7CTL 0x00000080 // LPC Channel 7 / COMx Control
+#define LPC_O_CH7ST 0x00000084 // LPC Channel 7 / COMx Status
+#define LPC_O_CH7ADR 0x00000088 // LPC Channel 7 / COMx Address
+#define LPC_O_STSADDR 0x000000A0 // LPC Status Block Address
+#define LPC_O_IM 0x00000100 // LPC Interrupt Mask
+#define LPC_O_RIS 0x00000104 // LPC Raw Interrupt Status
+#define LPC_O_MIS 0x00000108 // LPC Masked Interrupt Status
+#define LPC_O_IC 0x0000010C // LPC Interrupt Clear
+#define LPC_O_DMACX 0x00000120 // LPC DMA and COMx Control
+#define LPC_O_POOL 0x00000400 // LPC Register Pool
+#define LPC_O_PP 0x00000FC0 // LPC Peripheral Properties
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LPC_O_CTL register.
+//
+//*****************************************************************************
+#define LPC_CTL_SCICNT_M 0x00000C00 // LPC0SCI Pulse Length
+#define LPC_CTL_SCICNT_0 0x00000000 // No pulse occurs on the LPC0SCI
+ // pin
+#define LPC_CTL_SCICNT_2 0x00000400 // The pulse on the LPC0SCI pin is
+ // 2 LPC0CLK periods
+#define LPC_CTL_SCICNT_4 0x00000800 // The pulse on the LPC0SCI pin is
+ // 4 LPC0CLK periods
+#define LPC_CTL_SCICNT_8 0x00000C00 // The pulse on the LPC0SCI pin is
+ // 8 LPC0CLK periods
+#define LPC_CTL_SCI 0x00000200 // Start SCI Pulse
+#define LPC_CTL_WAKE 0x00000100 // Wake or Keep Awake the LPC Bus
+#define LPC_CTL_CE7 0x00000080 // Enable Channel 7
+#define LPC_CTL_CE6 0x00000040 // Enable Channel 6
+#define LPC_CTL_CE5 0x00000020 // Enable Channel 5
+#define LPC_CTL_CE4 0x00000010 // Enable Channel 4
+#define LPC_CTL_CE3 0x00000008 // Enable Channel 3
+#define LPC_CTL_CE2 0x00000004 // Enable Channel 2
+#define LPC_CTL_CE1 0x00000002 // Enable Channel 1
+#define LPC_CTL_CE0 0x00000001 // Enable Channel 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LPC_O_STS register.
+//
+//*****************************************************************************
+#define LPC_STS_CHCNT_M 0x00700000 // Number of Channels
+#define LPC_STS_POOLSZ_M 0x00070000 // Register Pool Size
+#define LPC_STS_POOLSZ_256 0x00010000 // 256 bytes
+#define LPC_STS_POOLSZ_512 0x00020000 // 512 bytes
+#define LPC_STS_POOLSZ_768 0x00030000 // 768 bytes
+#define LPC_STS_POOLSZ_1024 0x00040000 // 1024 bytes
+#define LPC_STS_RST 0x00000400 // LPC Bus is in Reset
+#define LPC_STS_BUSY 0x00000200 // LPC is Busy
+#define LPC_STS_SLEEP 0x00000100 // LPC is in Sleep Mode
+#define LPC_STS_CA7 0x00000080 // Channel 7 Active
+#define LPC_STS_CA6 0x00000040 // Channel 6 Active
+#define LPC_STS_CA5 0x00000020 // Channel 5 Active
+#define LPC_STS_CA4 0x00000010 // Channel 4 Active
+#define LPC_STS_CA3 0x00000008 // Channel 3 Active
+#define LPC_STS_CA2 0x00000004 // Channel 2 Active
+#define LPC_STS_CA1 0x00000002 // Channel 1 Active
+#define LPC_STS_CA0 0x00000001 // Channel 0 Active
+#define LPC_STS_CHCNT_S 20
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LPC_O_IRQCTL register.
+//
+//*****************************************************************************
+#define LPC_IRQCTL_I15 0x80000000 // Manual IRQ15 State
+#define LPC_IRQCTL_I14 0x40000000 // Manual IRQ14 State
+#define LPC_IRQCTL_I13 0x20000000 // Manual IRQ13 State
+#define LPC_IRQCTL_I12 0x10000000 // Manual IRQ12 State
+#define LPC_IRQCTL_I11 0x08000000 // Manual IRQ11 State
+#define LPC_IRQCTL_I10 0x04000000 // Manual IRQ10 State
+#define LPC_IRQCTL_I9 0x02000000 // Manual IRQ9 State
+#define LPC_IRQCTL_I8 0x01000000 // Manual IRQ8 State
+#define LPC_IRQCTL_I7 0x00800000 // Manual IRQ7 State
+#define LPC_IRQCTL_I6 0x00400000 // Manual IRQ6 State
+#define LPC_IRQCTL_I5 0x00200000 // Manual IRQ5 State
+#define LPC_IRQCTL_I4 0x00100000 // Manual IRQ4 State
+#define LPC_IRQCTL_I3 0x00080000 // Manual IRQ3 State
+#define LPC_IRQCTL_I2 0x00040000 // Manual IRQ2 State
+#define LPC_IRQCTL_I1 0x00020000 // Manual IRQ1 State
+#define LPC_IRQCTL_AH 0x00010000 // Active High Control
+#define LPC_IRQCTL_PULSE 0x00000004 // Pulse IRQ States
+#define LPC_IRQCTL_ONCHG 0x00000002 // Initiate on Change
+#define LPC_IRQCTL_SND 0x00000001 // Initiate Immediately
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LPC_O_IRQST register.
+//
+//*****************************************************************************
+#define LPC_IRQST_I15 0x80000000 // Host IRQ15 State
+#define LPC_IRQST_I14 0x40000000 // IRQ14 State
+#define LPC_IRQST_I13 0x20000000 // IRQ13 State
+#define LPC_IRQST_I12 0x10000000 // IRQ12 State
+#define LPC_IRQST_I11 0x08000000 // IRQ11 State
+#define LPC_IRQST_I10 0x04000000 // IRQ10 State
+#define LPC_IRQST_I9 0x02000000 // IRQ9 State
+#define LPC_IRQST_I8 0x01000000 // IRQ8 State
+#define LPC_IRQST_I7 0x00800000 // IRQ7 State
+#define LPC_IRQST_I6 0x00400000 // IRQ6 State
+#define LPC_IRQST_I5 0x00200000 // IRQ5 State
+#define LPC_IRQST_I4 0x00100000 // IRQ4 State
+#define LPC_IRQST_I3 0x00080000 // IRQ3 State
+#define LPC_IRQST_I2 0x00040000 // IRQ2 State
+#define LPC_IRQST_I1 0x00020000 // IRQ1 State
+#define LPC_IRQST_I0 0x00010000 // IRQ0 State
+#define LPC_IRQST_SIRQ 0x00000004 // Pulse IRQ States
+#define LPC_IRQST_CONT 0x00000001 // Initiate Immediately
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LPC_O_CH0CTL register.
+//
+//*****************************************************************************
+#define LPC_CH0CTL_IRQSEL2_M 0xF0000000 // IRQ Select 2
+#define LPC_CH0CTL_IRQSEL1_M 0x0F000000 // IRQ Select 1
+#define LPC_CH0CTL_IRQSEL0_M 0x00F00000 // IRQ Select 0
+#define LPC_CH0CTL_IRQEN2 0x00080000 // IRQ Enable 2
+#define LPC_CH0CTL_CX 0x00080000 // IRQ Enable 2
+#define LPC_CH0CTL_IRQEN1 0x00040000 // IRQ Enable 1
+#define LPC_CH0CTL_IRQEN0_M 0x00030000 // IRQ Enable 0
+#define LPC_CH0CTL_IRQEN0_DIS 0x00000000 // Trigger disabled
+#define LPC_CH0CTL_IRQEN0_TRIG1 0x00010000 // Trigger 1
+#define LPC_CH0CTL_IRQEN0_TRIG2 0x00020000 // Trigger 2
+#define LPC_CH0CTL_IRQEN0_TRIG3 0x00030000 // Trigger 3
+#define LPC_CH0CTL_ARBDIS 0x00008000 // Arbitration Disabled
+#define LPC_CH0CTL_OFFSET_M 0x00003FE0 // Base Offset in Register Pool
+#define LPC_CH0CTL_AMASK_M 0x0000001C // Address Mask for Ranges
+#define LPC_CH0CTL_AMASK_4 0x00000000 // 4 bytes
+#define LPC_CH0CTL_AMASK_8 0x00000004 // 8 bytes
+#define LPC_CH0CTL_AMASK_16 0x00000008 // 16 bytes
+#define LPC_CH0CTL_AMASK_32 0x0000000C // 32 bytes
+#define LPC_CH0CTL_AMASK_64 0x00000010 // 64 bytes
+#define LPC_CH0CTL_AMASK_128 0x00000014 // 128 bytes
+#define LPC_CH0CTL_AMASK_256 0x00000018 // 256 bytes
+#define LPC_CH0CTL_AMASK_512 0x0000001C // 512 bytes
+#define LPC_CH0CTL_TYPE 0x00000001 // Channel Type
+#define LPC_CH0CTL_IRQSEL2_S 28
+#define LPC_CH0CTL_IRQSEL1_S 24
+#define LPC_CH0CTL_IRQSEL0_S 20
+#define LPC_CH0CTL_OFFSET_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LPC_O_CH0ST register.
+//
+//*****************************************************************************
+#define LPC_CH0ST_USER_M 0x00001F00 // User Data
+#define LPC_CH0ST_LASTHW 0x00000080 // Last Host Write
+#define LPC_CH0ST_HW1ST 0x00000040 // Host Wrote First
+#define LPC_CH0ST_LASTSW 0x00000020 // Last Slave Write
+#define LPC_CH0ST_SW1ST 0x00000010 // Slave Wrote First
+#define LPC_CH0ST_CMD 0x00000008 // Command or Data
+#define LPC_CH0ST_FRMH 0x00000002 // From-Host Transaction
+#define LPC_CH0ST_TOH 0x00000001 // To-Host Transaction
+#define LPC_CH0ST_USER_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LPC_O_CH0ADR register.
+//
+//*****************************************************************************
+#define LPC_CH0ADR_ADDRH_M 0xFFFF0000 // Upper Address Match
+#define LPC_CH0ADR_ADDRL_M 0x0000FFF8 // Lower Address Match
+#define LPC_CH0ADR_ADDRL1 0x00000002 // Endpoint Match Bit 1
+#define LPC_CH0ADR_ADDRH_S 16
+#define LPC_CH0ADR_ADDRL_S 3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LPC_O_CH1CTL register.
+//
+//*****************************************************************************
+#define LPC_CH1CTL_IRQSEL2_M 0xF0000000 // IRQ Select 2
+#define LPC_CH1CTL_IRQSEL1_M 0x0F000000 // IRQ Select 1
+#define LPC_CH1CTL_IRQSEL0_M 0x00F00000 // IRQ Select 0
+#define LPC_CH1CTL_IRQEN2 0x00080000 // IRQ Enable 2
+#define LPC_CH1CTL_CX 0x00080000 // IRQ Enable 2
+#define LPC_CH1CTL_IRQEN1 0x00040000 // IRQ Enable 1
+#define LPC_CH1CTL_IRQEN0_M 0x00030000 // IRQ Enable 0
+#define LPC_CH1CTL_IRQEN0_DIS 0x00000000 // Trigger disabled
+#define LPC_CH1CTL_IRQEN0_TRIG1 0x00010000 // Trigger 1
+#define LPC_CH1CTL_IRQEN0_TRGI2 0x00020000 // Trigger 2
+#define LPC_CH1CTL_IRQEN0_TRGI3 0x00030000 // Trigger 3
+#define LPC_CH1CTL_ARBDIS 0x00008000 // Arbitration Disabled
+#define LPC_CH1CTL_OFFSET_M 0x00003FE0 // Base Offset in Register Pool
+#define LPC_CH1CTL_AMASK_M 0x0000001C // Address Mask for Ranges
+#define LPC_CH1CTL_AMASK_4 0x00000000 // 4 bytes
+#define LPC_CH1CTL_AMASK_8 0x00000004 // 8 bytes
+#define LPC_CH1CTL_AMASK_16 0x00000008 // 16 bytes
+#define LPC_CH1CTL_AMASK_32 0x0000000C // 32 bytes
+#define LPC_CH1CTL_AMASK_64 0x00000010 // 64 bytes
+#define LPC_CH1CTL_AMASK_128 0x00000014 // 128 bytes
+#define LPC_CH1CTL_AMASK_256 0x00000018 // 256 bytes
+#define LPC_CH1CTL_AMASK_512 0x0000001C // 512 bytes
+#define LPC_CH1CTL_TYPE 0x00000001 // Channel Type
+#define LPC_CH1CTL_IRQSEL2_S 28
+#define LPC_CH1CTL_IRQSEL1_S 24
+#define LPC_CH1CTL_IRQSEL0_S 20
+#define LPC_CH1CTL_OFFSET_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LPC_O_CH1ST register.
+//
+//*****************************************************************************
+#define LPC_CH1ST_USER_M 0x00001F00 // User Data
+#define LPC_CH1ST_LASTHW 0x00000080 // Last Host Write
+#define LPC_CH1ST_HW1ST 0x00000040 // Host Wrote First
+#define LPC_CH1ST_LASTSW 0x00000020 // Last Slave Write
+#define LPC_CH1ST_SW1ST 0x00000010 // Slave Wrote First
+#define LPC_CH1ST_CMD 0x00000008 // Command or Data
+#define LPC_CH1ST_FRMH 0x00000002 // From-Host Transaction
+#define LPC_CH1ST_TOH 0x00000001 // To-Host Transaction
+#define LPC_CH1ST_USER_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LPC_O_CH1ADR register.
+//
+//*****************************************************************************
+#define LPC_CH1ADR_ADDRH_M 0xFFFF0000 // Upper Address Match
+#define LPC_CH1ADR_ADDRL_M 0x0000FFF8 // Lower Address Match
+#define LPC_CH1ADR_ADDRL1 0x00000002 // Endpoint Match Bit 1
+#define LPC_CH1ADR_ADDRH_S 16
+#define LPC_CH1ADR_ADDRL_S 3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LPC_O_CH2CTL register.
+//
+//*****************************************************************************
+#define LPC_CH2CTL_IRQSEL2_M 0xF0000000 // IRQ Select 2
+#define LPC_CH2CTL_IRQSEL1_M 0x0F000000 // IRQ Select 1
+#define LPC_CH2CTL_IRQSEL0_M 0x00F00000 // IRQ Select 0
+#define LPC_CH2CTL_CX 0x00080000 // IRQ Enable 2
+#define LPC_CH2CTL_IRQEN2 0x00080000 // IRQ Enable 2
+#define LPC_CH2CTL_IRQEN1 0x00040000 // IRQ Enable 1
+#define LPC_CH2CTL_IRQEN0_M 0x00030000 // IRQ Enable 0
+#define LPC_CH2CTL_IRQEN0_DIS 0x00000000 // Trigger disabled
+#define LPC_CH2CTL_IRQEN0_TRIG1 0x00010000 // Trigger 1
+#define LPC_CH2CTL_IRQEN0_TRIG2 0x00020000 // Trigger 2
+#define LPC_CH2CTL_IRQEN0_TRIG3 0x00030000 // Trigger 3
+#define LPC_CH2CTL_ARBDIS 0x00008000 // Arbitration Disabled
+#define LPC_CH2CTL_OFFSET_M 0x00003FE0 // Base Offset in Register Pool
+#define LPC_CH2CTL_AMASK_M 0x0000001C // Address Mask for Ranges
+#define LPC_CH2CTL_AMASK_4 0x00000000 // 4 bytes
+#define LPC_CH2CTL_AMASK_8 0x00000004 // 8 bytes
+#define LPC_CH2CTL_AMASK_16 0x00000008 // 16 bytes
+#define LPC_CH2CTL_AMASK_32 0x0000000C // 32 bytes
+#define LPC_CH2CTL_AMASK_64 0x00000010 // 64 bytes
+#define LPC_CH2CTL_AMASK_128 0x00000014 // 128 bytes
+#define LPC_CH2CTL_AMASK_256 0x00000018 // 256 bytes
+#define LPC_CH2CTL_AMASK_512 0x0000001C // 512 bytes
+#define LPC_CH2CTL_TYPE 0x00000001 // Channel Type
+#define LPC_CH2CTL_IRQSEL2_S 28
+#define LPC_CH2CTL_IRQSEL1_S 24
+#define LPC_CH2CTL_IRQSEL0_S 20
+#define LPC_CH2CTL_OFFSET_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LPC_O_CH2ST register.
+//
+//*****************************************************************************
+#define LPC_CH2ST_USER_M 0x00001F00 // User Data
+#define LPC_CH2ST_LASTHW 0x00000080 // Last Host Write
+#define LPC_CH2ST_HW1ST 0x00000040 // Host Wrote First
+#define LPC_CH2ST_LASTSW 0x00000020 // Last Slave Write
+#define LPC_CH2ST_SW1ST 0x00000010 // Slave Wrote First
+#define LPC_CH2ST_CMD 0x00000008 // Command or Data
+#define LPC_CH2ST_FRMH 0x00000002 // From-Host Transaction
+#define LPC_CH2ST_TOH 0x00000001 // To-Host Transaction
+#define LPC_CH2ST_USER_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LPC_O_CH2ADR register.
+//
+//*****************************************************************************
+#define LPC_CH2ADR_ADDRH_M 0xFFFF0000 // Upper Address Match
+#define LPC_CH2ADR_ADDRL_M 0x0000FFF8 // Lower Address Match
+#define LPC_CH2ADR_ADDRL1 0x00000002 // Endpoint Match Bit 1
+#define LPC_CH2ADR_ADDRH_S 16
+#define LPC_CH2ADR_ADDRL_S 3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LPC_O_CH3CTL register.
+//
+//*****************************************************************************
+#define LPC_CH3CTL_IRQSEL2_M 0xF0000000 // IRQ Select 2
+#define LPC_CH3CTL_IRQSEL1_M 0x0F000000 // IRQ Select 1
+#define LPC_CH3CTL_IRQSEL0_M 0x00F00000 // IRQ Select 0
+#define LPC_CH3CTL_IRQEN2 0x00080000 // IRQ Enable 2
+#define LPC_CH3CTL_CX 0x00080000 // IRQ Enable 2
+#define LPC_CH3CTL_IRQEN1 0x00040000 // IRQ Enable 1
+#define LPC_CH3CTL_IRQEN0_M 0x00030000 // IRQ Enable 0
+#define LPC_CH3CTL_IRQEN0_DIS 0x00000000 // Trigger disabled
+#define LPC_CH3CTL_IRQEN0_TRIG1 0x00010000 // Trigger 1
+#define LPC_CH3CTL_IRQEN0_TRIG2 0x00020000 // Trigger 2
+#define LPC_CH3CTL_IRQEN0_TRIG3 0x00030000 // Trigger 3
+#define LPC_CH3CTL_ARBDIS 0x00008000 // Arbitration Disabled
+#define LPC_CH3CTL_OFFSET_M 0x00003FE0 // Base Offset in Register Pool
+#define LPC_CH3CTL_AMASK_M 0x0000001C // Address Mask for Ranges
+#define LPC_CH3CTL_AMASK_4 0x00000000 // 4 bytes
+#define LPC_CH3CTL_AMASK_8 0x00000004 // 8 bytes
+#define LPC_CH3CTL_AMASK_16 0x00000008 // 16 bytes
+#define LPC_CH3CTL_AMASK_32 0x0000000C // 32 bytes
+#define LPC_CH3CTL_AMASK_64 0x00000010 // 64 bytes
+#define LPC_CH3CTL_AMASK_128 0x00000014 // 128 bytes
+#define LPC_CH3CTL_AMASK_256 0x00000018 // 256 bytes
+#define LPC_CH3CTL_AMASK_512 0x0000001C // 512 bytes
+#define LPC_CH3CTL_TYPE 0x00000001 // Channel Type
+#define LPC_CH3CTL_IRQSEL2_S 28
+#define LPC_CH3CTL_IRQSEL1_S 24
+#define LPC_CH3CTL_IRQSEL0_S 20
+#define LPC_CH3CTL_OFFSET_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LPC_O_CH3ST register.
+//
+//*****************************************************************************
+#define LPC_CH3ST_USER_M 0x00001F00 // User Data
+#define LPC_CH3ST_LASTHW 0x00000080 // Last Host Write
+#define LPC_CH3ST_HW1ST 0x00000040 // Host Wrote First
+#define LPC_CH3ST_LASTSW 0x00000020 // Last Slave Write
+#define LPC_CH3ST_SW1ST 0x00000010 // Slave Wrote First
+#define LPC_CH3ST_CMD 0x00000008 // Command or Data
+#define LPC_CH3ST_FRMH 0x00000002 // From-Host Transaction
+#define LPC_CH3ST_TOH 0x00000001 // To-Host Transaction
+#define LPC_CH3ST_USER_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LPC_O_CH3ADR register.
+//
+//*****************************************************************************
+#define LPC_CH3ADR_ADDRH_M 0xFFFF0000 // Upper Address Match
+#define LPC_CH3ADR_ADDRL_M 0x0000FFF8 // Lower Address Match
+#define LPC_CH3ADR_ADDRL1 0x00000002 // Endpoint Match Bit 1
+#define LPC_CH3ADR_ADDRH_S 16
+#define LPC_CH3ADR_ADDRL_S 3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LPC_O_CH4CTL register.
+//
+//*****************************************************************************
+#define LPC_CH4CTL_IRQSEL2_M 0xF0000000 // IRQ Select 2
+#define LPC_CH4CTL_IRQSEL1_M 0x0F000000 // IRQ Select 1
+#define LPC_CH4CTL_IRQSEL0_M 0x00F00000 // IRQ Select 0
+#define LPC_CH4CTL_CX 0x00080000 // IRQ Enable 2
+#define LPC_CH4CTL_IRQEN2 0x00080000 // IRQ Enable 2
+#define LPC_CH4CTL_IRQEN1 0x00040000 // IRQ Enable 1
+#define LPC_CH4CTL_IRQEN0_M 0x00030000 // IRQ Enable 0
+#define LPC_CH4CTL_IRQEN0_DIS 0x00000000 // Trigger disabled
+#define LPC_CH4CTL_IRQEN0_TRIG1 0x00010000 // Trigger 1
+#define LPC_CH4CTL_IRQEN0_TRIG2 0x00020000 // Trigger 2
+#define LPC_CH4CTL_IRQEN0_TRIG3 0x00030000 // Trigger 3
+#define LPC_CH4CTL_ARBDIS 0x00008000 // Arbitration Disabled
+#define LPC_CH4CTL_OFFSET_M 0x00003FE0 // Base Offset in Register Pool
+#define LPC_CH4CTL_AMASK_M 0x0000001C // Address Mask for Ranges
+#define LPC_CH4CTL_AMASK_4 0x00000000 // 4 bytes
+#define LPC_CH4CTL_AMASK_8 0x00000004 // 8 bytes
+#define LPC_CH4CTL_AMASK_16 0x00000008 // 16 bytes
+#define LPC_CH4CTL_AMASK_32 0x0000000C // 32 bytes
+#define LPC_CH4CTL_AMASK_64 0x00000010 // 64 bytes
+#define LPC_CH4CTL_AMASK_128 0x00000014 // 128 bytes
+#define LPC_CH4CTL_AMASK_256 0x00000018 // 256 bytes
+#define LPC_CH4CTL_AMASK_512 0x0000001C // 512 bytes
+#define LPC_CH4CTL_TYPE 0x00000001 // Channel Type
+#define LPC_CH4CTL_IRQSEL2_S 28
+#define LPC_CH4CTL_IRQSEL1_S 24
+#define LPC_CH4CTL_IRQSEL0_S 20
+#define LPC_CH4CTL_OFFSET_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LPC_O_CH4ST register.
+//
+//*****************************************************************************
+#define LPC_CH4ST_USER_M 0x00001F00 // User Data
+#define LPC_CH4ST_LASTHW 0x00000080 // Last Host Write
+#define LPC_CH4ST_HW1ST 0x00000040 // Host Wrote First
+#define LPC_CH4ST_LASTSW 0x00000020 // Last Slave Write
+#define LPC_CH4ST_SW1ST 0x00000010 // Slave Wrote First
+#define LPC_CH4ST_CMD 0x00000008 // Command or Data
+#define LPC_CH4ST_FRMH 0x00000002 // From-Host Transaction
+#define LPC_CH4ST_TOH 0x00000001 // To-Host Transaction
+#define LPC_CH4ST_USER_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LPC_O_CH4ADR register.
+//
+//*****************************************************************************
+#define LPC_CH4ADR_ADDRH_M 0xFFFF0000 // Upper Address Match
+#define LPC_CH4ADR_ADDRL_M 0x0000FFF8 // Lower Address Match
+#define LPC_CH4ADR_ADDRH_S 16
+#define LPC_CH4ADR_ADDRL_S 3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LPC_O_CH5CTL register.
+//
+//*****************************************************************************
+#define LPC_CH5CTL_IRQSEL2_M 0xF0000000 // IRQ Select 2
+#define LPC_CH5CTL_IRQSEL1_M 0x0F000000 // IRQ Select 1
+#define LPC_CH5CTL_IRQSEL0_M 0x00F00000 // IRQ Select 0
+#define LPC_CH5CTL_IRQEN2 0x00080000 // IRQ Enable 2
+#define LPC_CH5CTL_CX 0x00080000 // IRQ Enable 2
+#define LPC_CH5CTL_IRQEN1 0x00040000 // IRQ Enable 1
+#define LPC_CH5CTL_IRQEN0_M 0x00030000 // IRQ Enable 0
+#define LPC_CH5CTL_IRQEN0_DIS 0x00000000 // Trigger disabled
+#define LPC_CH5CTL_IRQEN0_TRIG1 0x00010000 // Trigger 1
+#define LPC_CH5CTL_IRQEN0_TRIG2 0x00020000 // Trigger 2
+#define LPC_CH5CTL_IRQEN0_TRIG3 0x00030000 // Trigger 3
+#define LPC_CH5CTL_ARBDIS 0x00008000 // Arbitration Disabled
+#define LPC_CH5CTL_OFFSET_M 0x00003FE0 // Base Offset in Register Pool
+#define LPC_CH5CTL_AMASK_M 0x0000001C // Address Mask for Ranges
+#define LPC_CH5CTL_AMASK_4 0x00000000 // 4 bytes
+#define LPC_CH5CTL_AMASK_8 0x00000004 // 8 bytes
+#define LPC_CH5CTL_AMASK_16 0x00000008 // 16 bytes
+#define LPC_CH5CTL_AMASK_32 0x0000000C // 32 bytes
+#define LPC_CH5CTL_AMASK_64 0x00000010 // 64 bytes
+#define LPC_CH5CTL_AMASK_128 0x00000014 // 128 bytes
+#define LPC_CH5CTL_AMASK_256 0x00000018 // 256 bytes
+#define LPC_CH5CTL_AMASK_512 0x0000001C // 512 bytes
+#define LPC_CH5CTL_TYPE 0x00000001 // Channel Type
+#define LPC_CH5CTL_IRQSEL2_S 28
+#define LPC_CH5CTL_IRQSEL1_S 24
+#define LPC_CH5CTL_IRQSEL0_S 20
+#define LPC_CH5CTL_OFFSET_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LPC_O_CH5ST register.
+//
+//*****************************************************************************
+#define LPC_CH5ST_USER_M 0x00001F00 // User Data
+#define LPC_CH5ST_LASTHW 0x00000080 // Last Host Write
+#define LPC_CH5ST_HW1ST 0x00000040 // Host Wrote First
+#define LPC_CH5ST_LASTSW 0x00000020 // Last Slave Write
+#define LPC_CH5ST_SW1ST 0x00000010 // Slave Wrote First
+#define LPC_CH5ST_CMD 0x00000008 // Command or Data
+#define LPC_CH5ST_FRMH 0x00000002 // From-Host Transaction
+#define LPC_CH5ST_TOH 0x00000001 // To-Host Transaction
+#define LPC_CH5ST_USER_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LPC_O_CH5ADR register.
+//
+//*****************************************************************************
+#define LPC_CH5ADR_ADDRH_M 0xFFFF0000 // Upper Address Match
+#define LPC_CH5ADR_ADDRL_M 0x0000FFF8 // Lower Address Match
+#define LPC_CH5ADR_ADDRH_S 16
+#define LPC_CH5ADR_ADDRL_S 3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LPC_O_CH6CTL register.
+//
+//*****************************************************************************
+#define LPC_CH6CTL_IRQSEL2_M 0xF0000000 // IRQ Select 2
+#define LPC_CH6CTL_IRQSEL1_M 0x0F000000 // IRQ Select 1
+#define LPC_CH6CTL_IRQSEL0_M 0x00F00000 // IRQ Select 0
+#define LPC_CH6CTL_CX 0x00080000 // IRQ Enable 2
+#define LPC_CH6CTL_IRQEN2 0x00080000 // IRQ Enable 2
+#define LPC_CH6CTL_IRQEN1 0x00040000 // IRQ Enable 1
+#define LPC_CH6CTL_IRQEN0_M 0x00030000 // IRQ Enable 0
+#define LPC_CH6CTL_IRQEN0_DIS 0x00000000 // Trigger disabled
+#define LPC_CH6CTL_IRQEN0_TRIG1 0x00010000 // Trigger 1
+#define LPC_CH6CTL_IRQEN0_TRIG2 0x00020000 // Trigger 2
+#define LPC_CH6CTL_IRQEN0_TRIG3 0x00030000 // Trigger 3
+#define LPC_CH6CTL_ARBDIS 0x00008000 // Arbitration Disabled
+#define LPC_CH6CTL_OFFSET_M 0x00003FE0 // Base Offset in Register Pool
+#define LPC_CH6CTL_AMASK_M 0x0000001C // Address Mask for Ranges
+#define LPC_CH6CTL_AMASK_4 0x00000000 // 4 bytes
+#define LPC_CH6CTL_AMASK_8 0x00000004 // 8 bytes
+#define LPC_CH6CTL_AMASK_16 0x00000008 // 16 bytes
+#define LPC_CH6CTL_AMASK_32 0x0000000C // 32 bytes
+#define LPC_CH6CTL_AMASK_64 0x00000010 // 64 bytes
+#define LPC_CH6CTL_AMASK_128 0x00000014 // 128 bytes
+#define LPC_CH6CTL_AMASK_256 0x00000018 // 256 bytes
+#define LPC_CH6CTL_AMASK_512 0x0000001C // 512 bytes
+#define LPC_CH6CTL_TYPE 0x00000001 // Channel Type
+#define LPC_CH6CTL_IRQSEL2_S 28
+#define LPC_CH6CTL_IRQSEL1_S 24
+#define LPC_CH6CTL_IRQSEL0_S 20
+#define LPC_CH6CTL_OFFSET_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LPC_O_CH6ST register.
+//
+//*****************************************************************************
+#define LPC_CH6ST_USER_M 0x00001F00 // User Data
+#define LPC_CH6ST_LASTHW 0x00000080 // Last Host Write
+#define LPC_CH6ST_HW1ST 0x00000040 // Host Wrote First
+#define LPC_CH6ST_LASTSW 0x00000020 // Last Slave Write
+#define LPC_CH6ST_SW1ST 0x00000010 // Slave Wrote First
+#define LPC_CH6ST_CMD 0x00000008 // Command or Data
+#define LPC_CH6ST_FRMH 0x00000002 // From-Host Transaction
+#define LPC_CH6ST_TOH 0x00000001 // To-Host Transaction
+#define LPC_CH6ST_USER_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LPC_O_CH6ADR register.
+//
+//*****************************************************************************
+#define LPC_CH6ADR_ADDRH_M 0xFFFF0000 // Upper Address Match
+#define LPC_CH6ADR_ADDRL_M 0x0000FFF8 // Lower Address Match
+#define LPC_CH6ADR_ADDRH_S 16
+#define LPC_CH6ADR_ADDRL_S 3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LPC_O_CH7CTL register.
+//
+//*****************************************************************************
+#define LPC_CH7CTL_IRQSEL2_M 0xF0000000 // IRQ Select 2
+#define LPC_CH7CTL_IRQSEL1_M 0x0F000000 // IRQ Select 1
+#define LPC_CH7CTL_IRQSEL0_M 0x00F00000 // IRQ Select 0
+#define LPC_CH7CTL_CX 0x00080000 // IRQ Enable 2
+#define LPC_CH7CTL_IRQEN2 0x00080000 // IRQ Enable 2
+#define LPC_CH7CTL_IRQEN1 0x00040000 // IRQ Enable 1
+#define LPC_CH7CTL_IRQEN0_M 0x00030000 // IRQ Enable 0
+#define LPC_CH7CTL_IRQEN0_AUTO 0x00000000 // The automatic IRQ trigger is
+ // disabled
+#define LPC_CH7CTL_IRQEN0_MST 0x00010000 // If TYPE is set, the IRQ selected
+ // by IRQSEL0 is triggered when the
+ // master wins arbitration (the
+ // HW1ST bit is set)
+#define LPC_CH7CTL_IRQEN0_SLV 0x00020000 // If TYPE is set, the IRQ selected
+ // by IRQSEL0 is triggered when the
+ // slave wins arbitration (the
+ // SW1ST bit is set)
+#define LPC_CH7CTL_IRQEN0_TRIG3 0x00030000 // Trigger 3
+#define LPC_CH7CTL_ARBDIS 0x00008000 // Arbitration Disabled
+#define LPC_CH7CTL_OFFSET_M 0x00003FE0 // Base Offset in Register Pool
+#define LPC_CH7CTL_AMASK_M 0x0000001C // Address Mask for Ranges
+#define LPC_CH7CTL_AMASK_4 0x00000000 // 4 bytes
+#define LPC_CH7CTL_AMASK_8 0x00000004 // 8 bytes
+#define LPC_CH7CTL_AMASK_16 0x00000008 // 16 bytes
+#define LPC_CH7CTL_AMASK_32 0x0000000C // 32 bytes
+#define LPC_CH7CTL_AMASK_64 0x00000010 // 64 bytes
+#define LPC_CH7CTL_AMASK_128 0x00000014 // 128 bytes
+#define LPC_CH7CTL_AMASK_256 0x00000018 // 256 bytes
+#define LPC_CH7CTL_AMASK_512 0x0000001C // 512 bytes
+#define LPC_CH7CTL_TYPE 0x00000001 // Channel Type
+#define LPC_CH7CTL_IRQSEL2_S 28
+#define LPC_CH7CTL_IRQSEL1_S 24
+#define LPC_CH7CTL_IRQSEL0_S 20
+#define LPC_CH7CTL_OFFSET_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LPC_O_CH7ST register.
+//
+//*****************************************************************************
+#define LPC_CH7ST_USER_M 0x00001F00 // User Data
+#define LPC_CH7ST_LASTHW 0x00000080 // Last Host Write
+#define LPC_CH7ST_HW1ST 0x00000040 // Host Wrote First
+#define LPC_CH7ST_LASTSW 0x00000020 // Last Slave Write
+#define LPC_CH7ST_SW1ST 0x00000010 // Slave Wrote First
+#define LPC_CH7ST_CMD 0x00000008 // Command or Data
+#define LPC_CH7ST_FRMH 0x00000002 // From-Host Transaction
+#define LPC_CH7ST_TOH 0x00000001 // To-Host Transaction
+#define LPC_CH7ST_USER_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LPC_O_CH7ADR register.
+//
+//*****************************************************************************
+#define LPC_CH7ADR_ADDRH_M 0xFFFF0000 // Upper Address Match
+#define LPC_CH7ADR_ADDRL_M 0x0000FFF8 // Lower Address Match
+#define LPC_CH7ADR_ADDRH_S 16
+#define LPC_CH7ADR_ADDRL_S 3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LPC_O_STSADDR register.
+//
+//*****************************************************************************
+#define LPC_STSADDR_ADDRH_M 0xFFFF0000 // Upper Address Match
+#define LPC_STSADDR_ADDRL_M 0x0000FFF8 // Lower Address Match
+#define LPC_STSADDR_ENA 0x00000001 // Enable Status Block
+#define LPC_STSADDR_ADDRH_S 16
+#define LPC_STSADDR_ADDRL_S 3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LPC_O_IM register.
+//
+//*****************************************************************************
+#define LPC_IM_RSTIM 0x80000000 // Reset State Interrupt Mask
+#define LPC_IM_SLEEPIM 0x40000000 // Sleep State Interrupt Mask
+#define LPC_IM_COMXIM 0x20000000 // COMx Interrupt Mask
+#define LPC_IM_SIRQIM 0x10000000 // SERIRQ Frame Complete Interrupt
+ // Mask
+#define LPC_IM_CH6IM3 0x08000000 // Channel 6 Interrupt Mask 3
+#define LPC_IM_CH6IM2 0x04000000 // Channel 6 Interrupt Mask 2
+#define LPC_IM_CH6IM1 0x02000000 // Channel 6 Interrupt Mask 1
+#define LPC_IM_CH6IM0 0x01000000 // Channel 6 Interrupt Mask 0
+#define LPC_IM_CH5IM3 0x00800000 // Channel 5 Interrupt Mask 3
+#define LPC_IM_CH5IM2 0x00400000 // Channel 5 Interrupt Mask 2
+#define LPC_IM_CH5IM1 0x00200000 // Channel 5 Interrupt Mask 1
+#define LPC_IM_CH5IM0 0x00100000 // Channel 5 Interrupt Mask 0
+#define LPC_IM_CH4IM3 0x00080000 // Channel 4 Interrupt Mask 3
+#define LPC_IM_CH4IM2 0x00040000 // Channel 4 Interrupt Mask 2
+#define LPC_IM_CH4IM1 0x00020000 // Channel 4 Interrupt Mask 1
+#define LPC_IM_CH4IM0 0x00010000 // Channel 4 Interrupt Mask 0
+#define LPC_IM_CH3IM3 0x00008000 // Channel 3 Interrupt Mask 3
+#define LPC_IM_CH3IM2 0x00004000 // Channel 3 Interrupt Mask 2
+#define LPC_IM_CH3IM1 0x00002000 // Channel 3 Interrupt Mask 1
+#define LPC_IM_CH3IM0 0x00001000 // Channel 3 Interrupt Mask 0
+#define LPC_IM_CH2IM3 0x00000800 // Channel 2 Interrupt Mask 3
+#define LPC_IM_CH2IM2 0x00000400 // Channel 2 Interrupt Mask 2
+#define LPC_IM_CH2IM1 0x00000200 // Channel 2 Interrupt Mask 1
+#define LPC_IM_CH2IM0 0x00000100 // Channel 2 Interrupt Mask 0
+#define LPC_IM_CH1IM3 0x00000080 // Channel 1 Interrupt Mask 3
+#define LPC_IM_CH1IM2 0x00000040 // Channel 1 Interrupt Mask 2
+#define LPC_IM_CH1IM1 0x00000020 // Channel 1 Interrupt Mask 1
+#define LPC_IM_CH1IM0 0x00000010 // Channel 1 Interrupt Mask 0
+#define LPC_IM_CH0IM3 0x00000008 // Channel 0 Interrupt Mask 3
+#define LPC_IM_CH0IM2 0x00000004 // Channel 0 Interrupt Mask 2
+#define LPC_IM_CH0IM1 0x00000002 // Channel 0 Interrupt Mask 1
+#define LPC_IM_CH0IM0 0x00000001 // Channel 0 Interrupt Mask 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LPC_O_RIS register.
+//
+//*****************************************************************************
+#define LPC_RIS_RSTRIS 0x80000000 // Reset State Raw Interrupt Status
+#define LPC_RIS_SLEEPRIS 0x40000000 // Sleep State Raw Interrupt Status
+#define LPC_RIS_COMXRIS 0x20000000 // COMx Raw Interrupt Status
+#define LPC_RIS_SIRQRIS 0x10000000 // SERIRQ Frame Complete Raw
+ // Interrupt Status
+#define LPC_RIS_CH6RIS3 0x08000000 // Channel 6 Raw Interrupt Status 3
+#define LPC_RIS_CH6RIS2 0x04000000 // Channel 6 Raw Interrupt Status 2
+#define LPC_RIS_CH6RIS1 0x02000000 // Channel 6 Raw Interrupt Status 1
+#define LPC_RIS_CH6RIS0 0x01000000 // Channel 6 Raw Interrupt Status 0
+#define LPC_RIS_CH5RIS3 0x00800000 // Channel 5 Raw Interrupt Status 3
+#define LPC_RIS_CH5RIS2 0x00400000 // Channel 5 Raw Interrupt Status 2
+#define LPC_RIS_CH5RIS1 0x00200000 // Channel 5 Raw Interrupt Status 1
+#define LPC_RIS_CH5RIS0 0x00100000 // Channel 5 Raw Interrupt Status 0
+#define LPC_RIS_CH4RIS3 0x00080000 // Channel 4 Raw Interrupt Status 3
+#define LPC_RIS_CH4RIS2 0x00040000 // Channel 4 Raw Interrupt Status 2
+#define LPC_RIS_CH4RIS1 0x00020000 // Channel 4 Raw Interrupt Status 1
+#define LPC_RIS_CH4RIS0 0x00010000 // Channel 4 Raw Interrupt Status 0
+#define LPC_RIS_CH3RIS3 0x00008000 // Channel 3 Raw Interrupt Status 3
+#define LPC_RIS_CH3RIS2 0x00004000 // Channel 3 Raw Interrupt Status 2
+#define LPC_RIS_CH3RIS1 0x00002000 // Channel 3 Raw Interrupt Status 1
+#define LPC_RIS_CH3RIS0 0x00001000 // Channel 3 Raw Interrupt Status 0
+#define LPC_RIS_CH2RIS3 0x00000800 // Channel 2 Raw Interrupt Status 3
+#define LPC_RIS_CH2RIS2 0x00000400 // Channel 2 Raw Interrupt Status 2
+#define LPC_RIS_CH2RIS1 0x00000200 // Channel 2 Raw Interrupt Status 1
+#define LPC_RIS_CH2RIS0 0x00000100 // Channel 2 Raw Interrupt Status 0
+#define LPC_RIS_CH1RIS3 0x00000080 // Channel 1 Raw Interrupt Status 3
+#define LPC_RIS_CH1RIS2 0x00000040 // Channel 1 Raw Interrupt Status 2
+#define LPC_RIS_CH1RIS1 0x00000020 // Channel 1 Raw Interrupt Status 1
+#define LPC_RIS_CH1RIS0 0x00000010 // Channel 1 Raw Interrupt Status 0
+#define LPC_RIS_CH0RIS3 0x00000008 // Channel 0 Raw Interrupt Status 3
+#define LPC_RIS_CH0RIS2 0x00000004 // Channel 0 Raw Interrupt Status 2
+#define LPC_RIS_CH0RIS1 0x00000002 // Channel 0 Raw Interrupt Status 1
+#define LPC_RIS_CH0RIS0 0x00000001 // Channel 0 Raw Interrupt Status 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LPC_O_MIS register.
+//
+//*****************************************************************************
+#define LPC_MIS_RSTMIS 0x80000000 // Reset State Masked Interrupt
+ // Status
+#define LPC_MIS_SLEEPMIS 0x40000000 // Sleep State Masked Interrupt
+ // Status
+#define LPC_MIS_COMXMIS 0x20000000 // COMx Masked Interrupt Status
+#define LPC_MIS_SIRQMIS 0x10000000 // SERIRQ Frame Complete Masked
+ // Interrupt Status
+#define LPC_MIS_CH6MIS3 0x08000000 // Channel 6 Masked Interrupt
+ // Status 3
+#define LPC_MIS_CH6MIS2 0x04000000 // Channel 6 Masked Interrupt
+ // Status 2
+#define LPC_MIS_CH6MIS1 0x02000000 // Channel 6 Masked Interrupt
+ // Status 1
+#define LPC_MIS_CH6MIS0 0x01000000 // Channel 6 Masked Interrupt
+ // Status 0
+#define LPC_MIS_CH5MIS3 0x00800000 // Channel 5 Masked Interrupt
+ // Status 3
+#define LPC_MIS_CH5MIS2 0x00400000 // Channel 5 Masked Interrupt
+ // Status 2
+#define LPC_MIS_CH5MIS1 0x00200000 // Channel 5 Masked Interrupt
+ // Status 1
+#define LPC_MIS_CH5MIS0 0x00100000 // Channel 5 Masked Interrupt
+ // Status 0
+#define LPC_MIS_CH4MIS3 0x00080000 // Channel 4 Masked Interrupt
+ // Status 3
+#define LPC_MIS_CH4MIS2 0x00040000 // Channel 4 Masked Interrupt
+ // Status 2
+#define LPC_MIS_CH4MIS1 0x00020000 // Channel 4 Masked Interrupt
+ // Status 1
+#define LPC_MIS_CH4MIS0 0x00010000 // Channel 4 Masked Interrupt
+ // Status 0
+#define LPC_MIS_CH3MIS3 0x00008000 // Channel 3 Masked Interrupt
+ // Status 3
+#define LPC_MIS_CH3MIS2 0x00004000 // Channel 3 Masked Interrupt
+ // Status 2
+#define LPC_MIS_CH3MIS1 0x00002000 // Channel 3 Masked Interrupt
+ // Status 1
+#define LPC_MIS_CH3MIS0 0x00001000 // Channel 3 Masked Interrupt
+ // Status 0
+#define LPC_MIS_CH2MIS3 0x00000800 // Channel 2 Masked Interrupt
+ // Status 3
+#define LPC_MIS_CH2MIS2 0x00000400 // Channel 2 Masked Interrupt
+ // Status 2
+#define LPC_MIS_CH2MIS1 0x00000200 // Channel 2 Masked Interrupt
+ // Status 1
+#define LPC_MIS_CH2MIS0 0x00000100 // Channel 2 Masked Interrupt
+ // Status 0
+#define LPC_MIS_CH1MIS3 0x00000080 // Channel 1 Masked Interrupt
+ // Status 3
+#define LPC_MIS_CH1MIS2 0x00000040 // Channel 1 Masked Interrupt
+ // Status 2
+#define LPC_MIS_CH1MIS1 0x00000020 // Channel 1 Masked Interrupt
+ // Status 1
+#define LPC_MIS_CH1MIS0 0x00000010 // Channel 1 Masked Interrupt
+ // Status 0
+#define LPC_MIS_CH0MIS3 0x00000008 // Channel 0 Masked Interrupt
+ // Status 3
+#define LPC_MIS_CH0MIS2 0x00000004 // Channel 0 Masked Interrupt
+ // Status 2
+#define LPC_MIS_CH0MIS1 0x00000002 // Channel 0 Masked Interrupt
+ // Status 1
+#define LPC_MIS_CH0MIS0 0x00000001 // Channel 0 Masked Interrupt
+ // Status 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LPC_O_IC register.
+//
+//*****************************************************************************
+#define LPC_IC_RSTIC 0x80000000 // Reset State Interrupt Clear
+#define LPC_IC_SLEEPIC 0x40000000 // Sleep State Interrupt Clear
+#define LPC_IC_COMXIC 0x20000000 // COMx Interrupt Clear
+#define LPC_IC_SIRQRIC 0x10000000 // SERIRQ Frame Complete Interrupt
+ // Clear
+#define LPC_IC_CH6IC3 0x08000000 // Channel 6 Interrupt Clear 3
+#define LPC_IC_CH6IC2 0x04000000 // Channel 6 Interrupt Clear 2
+#define LPC_IC_CH6IC1 0x02000000 // Channel 6 Interrupt Clear 1
+#define LPC_IC_CH6IC0 0x01000000 // Channel 6 Interrupt Clear 0
+#define LPC_IC_CH5IC3 0x00800000 // Channel 5 Interrupt Clear 3
+#define LPC_IC_CH5IC2 0x00400000 // Channel 5 Interrupt Clear 2
+#define LPC_IC_CH5IC1 0x00200000 // Channel 5 Interrupt Clear 1
+#define LPC_IC_CH5IC0 0x00100000 // Channel 5 Interrupt Clear 0
+#define LPC_IC_CH4IC3 0x00080000 // Channel 4 Interrupt Clear 3
+#define LPC_IC_CH4IC2 0x00040000 // Channel 4 Interrupt Clear 2
+#define LPC_IC_CH4IC1 0x00020000 // Channel 4 Interrupt Clear 1
+#define LPC_IC_CH4IC0 0x00010000 // Channel 4 Interrupt Clear 0
+#define LPC_IC_CH3IC3 0x00008000 // Channel 3 Interrupt Clear 3
+#define LPC_IC_CH3IC2 0x00004000 // Channel 3 Interrupt Clear 2
+#define LPC_IC_CH3IC1 0x00002000 // Channel 3 Interrupt Clear 1
+#define LPC_IC_CH3IC0 0x00001000 // Channel 3 Interrupt Clear 0
+#define LPC_IC_CH2IC3 0x00000800 // Channel 2 Interrupt Clear 3
+#define LPC_IC_CH2IC2 0x00000400 // Channel 2 Interrupt Clear 2
+#define LPC_IC_CH2IC1 0x00000200 // Channel 2 Interrupt Clear 1
+#define LPC_IC_CH2IC0 0x00000100 // Channel 2 Interrupt Clear 0
+#define LPC_IC_CH1IC3 0x00000080 // Channel 1 Interrupt Clear 3
+#define LPC_IC_CH1IC2 0x00000040 // Channel 1 Interrupt Clear 2
+#define LPC_IC_CH1IC1 0x00000020 // Channel 1 Interrupt Clear 1
+#define LPC_IC_CH1IC0 0x00000010 // Channel 1 Interrupt Clear 0
+#define LPC_IC_CH0IC3 0x00000008 // Channel 0 Interrupt Clear 3
+#define LPC_IC_CH0IC2 0x00000004 // Channel 0 Interrupt Clear 2
+#define LPC_IC_CH0IC1 0x00000002 // Channel 0 Interrupt Clear 1
+#define LPC_IC_CH0IC0 0x00000001 // Channel 0 Interrupt Clear 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LPC_O_DMACX register.
+//
+//*****************************************************************************
+#define LPC_DMACX_CXRES 0x02000000 // Raw Event State for COMx
+#define LPC_DMACX_CXTXRES 0x01000000 // Raw Event State for COMx TX
+#define LPC_DMACX_CXRXRES 0x00800000 // Raw Event State for COMx RX
+#define LPC_DMACX_CXEM 0x00200000 // Event Mask for COMx
+#define LPC_DMACX_CXTXEM 0x00100000 // Event Mask for COMx TX
+#define LPC_DMACX_CXRXEM 0x00080000 // Event Mask for COMx RX
+#define LPC_DMACX_CXACT_M 0x00060000 // COMx Action
+#define LPC_DMACX_CXACT_FRMHNML 0x00000000 // Treat as normal FRMH model and
+ // let be full (and so marked as
+ // full)
+#define LPC_DMACX_CXACT_FRMHIGN 0x00020000 // Ignore FRMH bytes and continue
+ // to mark FRMH as empty
+#define LPC_DMACX_CXACT_FRMHDMA 0x00040000 // COMx DMA on FRMH byte (e.g. to
+ // memory)
+#define LPC_DMACX_CXACT_UARTDMA 0x00060000 // COMx DMA model with UART
+#define LPC_DMACX_COMX 0x00010000 // COMx Handling
+#define LPC_DMACX_C3W 0x00000080 // Channel 3 Write Control
+#define LPC_DMACX_C3R 0x00000040 // Channel 3 Read Control
+#define LPC_DMACX_C2W 0x00000020 // Channel 2 Write Control
+#define LPC_DMACX_C2R 0x00000010 // Channel 2 Read Control
+#define LPC_DMACX_C1W 0x00000008 // Channel 1 Write Control
+#define LPC_DMACX_C1R 0x00000004 // Channel 1 Read Control
+#define LPC_DMACX_C0W 0x00000002 // Channel 0 Write Control
+#define LPC_DMACX_C0R 0x00000001 // Channel 0 Read Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LPC_O_POOL register.
+//
+//*****************************************************************************
+#define LPC_POOL_BYTE3_M 0xFF000000 // Byte 3
+#define LPC_POOL_BYTE2_M 0x00FF0000 // Byte 2
+#define LPC_POOL_BYTE1_M 0x0000FF00 // Byte 1
+#define LPC_POOL_BYTE0_M 0x000000FF // Byte 0
+#define LPC_POOL_BYTE3_S 24
+#define LPC_POOL_BYTE2_S 16
+#define LPC_POOL_BYTE1_S 8
+#define LPC_POOL_BYTE0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LPC_O_PP register.
+//
+//*****************************************************************************
+#define LPC_PP_COMX 0x00000010 // COMx Support Available
+#define LPC_PP_CHANCNT_M 0x0000000F // Number of Channels (Excluding
+ // COMx)
+#define LPC_PP_CHANCNT_S 0
+
+#endif // __HW_LPC_H__
diff --git a/inc/hw_memmap.h b/inc/hw_memmap.h new file mode 100644 index 0000000..64fd8d9 --- /dev/null +++ b/inc/hw_memmap.h @@ -0,0 +1,167 @@ +//*****************************************************************************
+//
+// hw_memmap.h - Macros defining the memory map of Stellaris.
+//
+// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 9453 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_MEMMAP_H__
+#define __HW_MEMMAP_H__
+
+//*****************************************************************************
+//
+// The following are defines for the base address of the memories and
+// peripherals.
+//
+//*****************************************************************************
+#define FLASH_BASE 0x00000000 // FLASH memory
+#define SRAM_BASE 0x20000000 // SRAM memory
+#define WATCHDOG0_BASE 0x40000000 // Watchdog0
+#define WATCHDOG1_BASE 0x40001000 // Watchdog1
+#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A
+#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B
+#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C
+#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D
+#define SSI0_BASE 0x40008000 // SSI0
+#define SSI1_BASE 0x40009000 // SSI1
+#define SSI2_BASE 0x4000A000 // SSI2
+#define SSI3_BASE 0x4000B000 // SSI3
+#define UART0_BASE 0x4000C000 // UART0
+#define UART1_BASE 0x4000D000 // UART1
+#define UART2_BASE 0x4000E000 // UART2
+#define UART3_BASE 0x4000F000 // UART3
+#define UART4_BASE 0x40010000 // UART4
+#define UART5_BASE 0x40011000 // UART5
+#define UART6_BASE 0x40012000 // UART6
+#define UART7_BASE 0x40013000 // UART7
+#define I2C0_MASTER_BASE 0x40020000 // I2C0 Master
+#define I2C0_SLAVE_BASE 0x40020800 // I2C0 Slave
+#define I2C1_MASTER_BASE 0x40021000 // I2C1 Master
+#define I2C1_SLAVE_BASE 0x40021800 // I2C1 Slave
+#define I2C2_MASTER_BASE 0x40022000 // I2C2 Master
+#define I2C2_SLAVE_BASE 0x40022800 // I2C2 Slave
+#define I2C3_MASTER_BASE 0x40023000 // I2C3 Master
+#define I2C3_SLAVE_BASE 0x40023800 // I2C3 Slave
+#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E
+#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F
+#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G
+#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H
+#define PWM0_BASE 0x40028000 // Pulse Width Modulator (PWM)
+#define PWM1_BASE 0x40029000 // Pulse Width Modulator (PWM)
+#define QEI0_BASE 0x4002C000 // QEI0
+#define QEI1_BASE 0x4002D000 // QEI1
+#define TIMER0_BASE 0x40030000 // Timer0
+#define TIMER1_BASE 0x40031000 // Timer1
+#define TIMER2_BASE 0x40032000 // Timer2
+#define TIMER3_BASE 0x40033000 // Timer3
+#define TIMER4_BASE 0x40034000 // Timer4
+#define TIMER5_BASE 0x40035000 // Timer5
+#define WTIMER0_BASE 0x40036000 // Wide Timer0
+#define WTIMER1_BASE 0x40037000 // Wide Timer1
+#define ADC0_BASE 0x40038000 // ADC0
+#define ADC1_BASE 0x40039000 // ADC1
+#define COMP_BASE 0x4003C000 // Analog comparators
+#define GPIO_PORTJ_BASE 0x4003D000 // GPIO Port J
+#define CAN0_BASE 0x40040000 // CAN0
+#define CAN1_BASE 0x40041000 // CAN1
+#define CAN2_BASE 0x40042000 // CAN2
+#define ETH_BASE 0x40048000 // Ethernet
+#define MAC_BASE 0x40048000 // Ethernet
+#define WTIMER2_BASE 0x4004C000 // Wide Timer2
+#define WTIMER3_BASE 0x4004D000 // Wide Timer3
+#define WTIMER4_BASE 0x4004E000 // Wide Timer4
+#define WTIMER5_BASE 0x4004F000 // Wide Timer5
+#define USB0_BASE 0x40050000 // USB 0 Controller
+#define I2S0_BASE 0x40054000 // I2S0
+#define GPIO_PORTA_AHB_BASE 0x40058000 // GPIO Port A (high speed)
+#define GPIO_PORTB_AHB_BASE 0x40059000 // GPIO Port B (high speed)
+#define GPIO_PORTC_AHB_BASE 0x4005A000 // GPIO Port C (high speed)
+#define GPIO_PORTD_AHB_BASE 0x4005B000 // GPIO Port D (high speed)
+#define GPIO_PORTE_AHB_BASE 0x4005C000 // GPIO Port E (high speed)
+#define GPIO_PORTF_AHB_BASE 0x4005D000 // GPIO Port F (high speed)
+#define GPIO_PORTG_AHB_BASE 0x4005E000 // GPIO Port G (high speed)
+#define GPIO_PORTH_AHB_BASE 0x4005F000 // GPIO Port H (high speed)
+#define GPIO_PORTJ_AHB_BASE 0x40060000 // GPIO Port J (high speed)
+#define GPIO_PORTK_BASE 0x40061000 // GPIO Port K
+#define GPIO_PORTL_BASE 0x40062000 // GPIO Port L
+#define GPIO_PORTM_BASE 0x40063000 // GPIO Port M
+#define GPIO_PORTN_BASE 0x40064000 // GPIO Port N
+#define GPIO_PORTP_BASE 0x40065000 // GPIO Port P
+#define GPIO_PORTQ_BASE 0x40066000 // GPIO Port Q
+#define LPC0_BASE 0x40080000 // Low Pin Count Interface (LPC)
+#define FAN0_BASE 0x40084000 // Fan Control (FAN)
+#define EEPROM_BASE 0x400AF000 // EEPROM memory
+#define PECI0_BASE 0x400B0000 // Platform Environment Control
+ // Interface (PECI)
+#define I2C4_MASTER_BASE 0x400C0000 // I2C4 Master
+#define I2C4_SLAVE_BASE 0x400C0800 // I2C4 Slave
+#define I2C5_MASTER_BASE 0x400C1000 // I2C5 Master
+#define I2C5_SLAVE_BASE 0x400C1800 // I2C5 Slave
+#define EPI0_BASE 0x400D0000 // EPI0
+#define SYSEXC_BASE 0x400F9000 // System Exception Module
+#define HIB_BASE 0x400FC000 // Hibernation Module
+#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller
+#define SYSCTL_BASE 0x400FE000 // System Control
+#define UDMA_BASE 0x400FF000 // uDMA Controller
+#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell
+#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace
+#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint
+#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl
+#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the base address of the memories
+// and peripherals.
+//
+//*****************************************************************************
+#define WATCHDOG_BASE 0x40000000 // Watchdog
+#define SSI_BASE 0x40008000 // SSI
+#define I2C_MASTER_BASE 0x40020000 // I2C Master
+#define I2C_SLAVE_BASE 0x40020800 // I2C Slave
+#define PWM_BASE 0x40028000 // PWM
+#define QEI_BASE 0x4002C000 // QEI
+#define ADC_BASE 0x40038000 // ADC
+
+#endif
+
+#endif // __HW_MEMMAP_H__
diff --git a/inc/hw_nvic.h b/inc/hw_nvic.h new file mode 100644 index 0000000..256a8ba --- /dev/null +++ b/inc/hw_nvic.h @@ -0,0 +1,1717 @@ +//*****************************************************************************
+//
+// hw_nvic.h - Macros used when accessing the NVIC hardware.
+//
+// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 9453 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_NVIC_H__
+#define __HW_NVIC_H__
+
+//*****************************************************************************
+//
+// The following are defines for the NVIC register addresses.
+//
+//*****************************************************************************
+#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg
+#define NVIC_ACTLR 0xE000E008 // Auxiliary Control
+#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status
+ // Register
+#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register
+#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register
+#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg
+#define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable
+#define NVIC_EN1 0xE000E104 // Interrupt 32-54 Set Enable
+#define NVIC_EN2 0xE000E108 // Interrupt 64-95 Set Enable
+#define NVIC_EN3 0xE000E10C // Interrupt 96-127 Set Enable
+#define NVIC_EN4 0xE000E110 // Interrupt 128-131 Set Enable
+#define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable
+#define NVIC_DIS1 0xE000E184 // Interrupt 32-54 Clear Enable
+#define NVIC_DIS2 0xE000E188 // Interrupt 64-95 Clear Enable
+#define NVIC_DIS3 0xE000E18C // Interrupt 96-127 Clear Enable
+#define NVIC_DIS4 0xE000E190 // Interrupt 128-131 Clear Enable
+#define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending
+#define NVIC_PEND1 0xE000E204 // Interrupt 32-54 Set Pending
+#define NVIC_PEND2 0xE000E208 // Interrupt 64-95 Set Pending
+#define NVIC_PEND3 0xE000E20C // Interrupt 96-127 Set Pending
+#define NVIC_PEND4 0xE000E210 // Interrupt 128-131 Set Pending
+#define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending
+#define NVIC_UNPEND1 0xE000E284 // Interrupt 32-54 Clear Pending
+#define NVIC_UNPEND2 0xE000E288 // Interrupt 64-95 Clear Pending
+#define NVIC_UNPEND3 0xE000E28C // Interrupt 96-127 Clear Pending
+#define NVIC_UNPEND4 0xE000E290 // Interrupt 128-131 Clear Pending
+#define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit
+#define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-54 Active Bit
+#define NVIC_ACTIVE2 0xE000E308 // Interrupt 64-95 Active Bit
+#define NVIC_ACTIVE3 0xE000E30C // Interrupt 96-127 Active Bit
+#define NVIC_ACTIVE4 0xE000E310 // Interrupt 128-131 Active Bit
+#define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority
+#define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority
+#define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority
+#define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority
+#define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority
+#define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority
+#define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority
+#define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority
+#define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority
+#define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority
+#define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority
+#define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority
+#define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority
+#define NVIC_PRI13 0xE000E434 // Interrupt 52-55 Priority
+#define NVIC_PRI14 0xE000E438 // Interrupt 56-59 Priority
+#define NVIC_PRI15 0xE000E43C // Interrupt 60-63 Priority
+#define NVIC_PRI16 0xE000E440 // Interrupt 64-67 Priority
+#define NVIC_PRI17 0xE000E444 // Interrupt 68-71 Priority
+#define NVIC_PRI18 0xE000E448 // Interrupt 72-75 Priority
+#define NVIC_PRI19 0xE000E44C // Interrupt 76-79 Priority
+#define NVIC_PRI20 0xE000E450 // Interrupt 80-83 Priority
+#define NVIC_PRI21 0xE000E454 // Interrupt 84-87 Priority
+#define NVIC_PRI22 0xE000E458 // Interrupt 88-91 Priority
+#define NVIC_PRI23 0xE000E45C // Interrupt 92-95 Priority
+#define NVIC_PRI24 0xE000E460 // Interrupt 96-99 Priority
+#define NVIC_PRI25 0xE000E464 // Interrupt 100-103 Priority
+#define NVIC_PRI26 0xE000E468 // Interrupt 104-107 Priority
+#define NVIC_PRI27 0xE000E46C // Interrupt 108-111 Priority
+#define NVIC_PRI28 0xE000E470 // Interrupt 112-115 Priority
+#define NVIC_PRI29 0xE000E474 // Interrupt 116-119 Priority
+#define NVIC_PRI30 0xE000E478 // Interrupt 120-123 Priority
+#define NVIC_PRI31 0xE000E47C // Interrupt 124-127 Priority
+#define NVIC_PRI32 0xE000E480 // Interrupt 128-131 Priority
+#define NVIC_PRI33 0xE000E484 // Interrupt 132-135 Priority
+#define NVIC_PRI34 0xE000E488 // Interrupt 136-138 Priority
+#define NVIC_CPUID 0xE000ED00 // CPU ID Base
+#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State
+#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset
+#define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset
+ // Control
+#define NVIC_SYS_CTRL 0xE000ED10 // System Control
+#define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control
+#define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1
+#define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2
+#define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3
+#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State
+#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status
+#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status
+#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register
+#define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address
+#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address
+#define NVIC_CPAC 0xE000ED88 // Coprocessor Access Control
+#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type
+#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control
+#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number
+#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address
+#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size
+#define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1
+#define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size
+ // Alias 1
+#define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2
+#define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size
+ // Alias 2
+#define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3
+#define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size
+ // Alias 3
+#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg
+#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select
+#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data
+#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control
+#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt
+#define NVIC_FPCC 0xE000EF34 // Floating-Point Context Control
+#define NVIC_FPCA 0xE000EF38 // Floating-Point Context Address
+#define NVIC_FPDSC 0xE000EF3C // Floating-Point Default Status
+ // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_INT_TYPE register.
+//
+//*****************************************************************************
+#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32)
+#define NVIC_INT_TYPE_LINES_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTLR register.
+//
+//*****************************************************************************
+#define NVIC_ACTLR_DISOOFP 0x00000200 // Disable Out-Of-Order Floating
+ // Point
+#define NVIC_ACTLR_DISFPCA 0x00000100 // Disable CONTROL
+#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding
+#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer
+#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple
+ // Cycle Instructions
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag
+#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source
+#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable
+#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_RELOAD register.
+//
+//*****************************************************************************
+#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value
+#define NVIC_ST_RELOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CURRENT
+// register.
+//
+//*****************************************************************************
+#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value
+#define NVIC_ST_CURRENT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CAL register.
+//
+//*****************************************************************************
+#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock
+#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew
+#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value
+#define NVIC_ST_CAL_ONEMS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN0 register.
+//
+//*****************************************************************************
+#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable
+#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable
+#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable
+#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable
+#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable
+#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable
+#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable
+#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable
+#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable
+#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable
+#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable
+#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable
+#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable
+#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable
+#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable
+#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable
+#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable
+#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable
+#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable
+#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable
+#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable
+#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable
+#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable
+#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable
+#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable
+#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable
+#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable
+#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable
+#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable
+#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable
+#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable
+#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable
+#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN1 register.
+//
+//*****************************************************************************
+#define NVIC_EN1_INT_M 0xFFFFFFFF // Interrupt Enable
+#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable
+#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable
+#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable
+#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable
+#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable
+#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable
+#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable
+#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable
+#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable
+#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable
+#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable
+#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable
+#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable
+#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable
+#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable
+#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable
+#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable
+#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable
+#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable
+#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable
+#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable
+#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable
+#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN2 register.
+//
+//*****************************************************************************
+#define NVIC_EN2_INT_M 0xFFFFFFFF // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN3 register.
+//
+//*****************************************************************************
+#define NVIC_EN3_INT_M 0xFFFFFFFF // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN4 register.
+//
+//*****************************************************************************
+#define NVIC_EN4_INT_M 0x000007FF // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS0 register.
+//
+//*****************************************************************************
+#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable
+#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable
+#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable
+#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable
+#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable
+#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable
+#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable
+#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable
+#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable
+#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable
+#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable
+#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable
+#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable
+#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable
+#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable
+#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable
+#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable
+#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable
+#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable
+#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable
+#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable
+#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable
+#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable
+#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable
+#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable
+#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable
+#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable
+#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable
+#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable
+#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable
+#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable
+#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable
+#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS1 register.
+//
+//*****************************************************************************
+#define NVIC_DIS1_INT_M 0xFFFFFFFF // Interrupt Disable
+#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable
+#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable
+#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable
+#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable
+#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable
+#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable
+#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable
+#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable
+#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable
+#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable
+#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable
+#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable
+#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable
+#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable
+#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable
+#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable
+#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable
+#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable
+#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable
+#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable
+#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable
+#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable
+#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable
+#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS2 register.
+//
+//*****************************************************************************
+#define NVIC_DIS2_INT_M 0xFFFFFFFF // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS3 register.
+//
+//*****************************************************************************
+#define NVIC_DIS3_INT_M 0xFFFFFFFF // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS4 register.
+//
+//*****************************************************************************
+#define NVIC_DIS4_INT_M 0x000007FF // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND0 register.
+//
+//*****************************************************************************
+#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending
+#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend
+#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend
+#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend
+#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend
+#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend
+#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend
+#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend
+#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend
+#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend
+#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend
+#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend
+#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend
+#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend
+#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend
+#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend
+#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend
+#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend
+#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend
+#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend
+#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend
+#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend
+#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend
+#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend
+#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend
+#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend
+#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend
+#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend
+#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend
+#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend
+#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend
+#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend
+#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND1 register.
+//
+//*****************************************************************************
+#define NVIC_PEND1_INT_M 0xFFFFFFFF // Interrupt Set Pending
+#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend
+#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend
+#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend
+#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend
+#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend
+#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend
+#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend
+#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend
+#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend
+#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend
+#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend
+#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend
+#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend
+#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend
+#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend
+#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend
+#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend
+#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend
+#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend
+#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend
+#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend
+#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend
+#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend
+#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND2 register.
+//
+//*****************************************************************************
+#define NVIC_PEND2_INT_M 0xFFFFFFFF // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND3 register.
+//
+//*****************************************************************************
+#define NVIC_PEND3_INT_M 0xFFFFFFFF // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND4 register.
+//
+//*****************************************************************************
+#define NVIC_PEND4_INT_M 0x000007FF // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND0 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending
+#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend
+#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend
+#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend
+#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend
+#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend
+#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend
+#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend
+#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend
+#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend
+#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend
+#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend
+#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend
+#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend
+#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend
+#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend
+#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend
+#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend
+#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend
+#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend
+#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend
+#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend
+#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend
+#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend
+#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend
+#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend
+#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend
+#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend
+#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend
+#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend
+#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend
+#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend
+#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND1 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND1_INT_M 0xFFFFFFFF // Interrupt Clear Pending
+#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend
+#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend
+#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend
+#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend
+#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend
+#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend
+#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend
+#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend
+#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend
+#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend
+#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend
+#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend
+#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend
+#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend
+#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend
+#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend
+#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend
+#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend
+#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend
+#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend
+#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend
+#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend
+#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend
+#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND2 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND2_INT_M 0xFFFFFFFF // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND3 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND3_INT_M 0xFFFFFFFF // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND4 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND4_INT_M 0x000007FF // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE0 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active
+#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active
+#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active
+#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active
+#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active
+#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active
+#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active
+#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active
+#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active
+#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active
+#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active
+#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active
+#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active
+#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active
+#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active
+#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active
+#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active
+#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active
+#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active
+#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active
+#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active
+#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active
+#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active
+#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active
+#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active
+#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active
+#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active
+#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active
+#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active
+#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active
+#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active
+#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active
+#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE1 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE1_INT_M 0xFFFFFFFF // Interrupt Active
+#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active
+#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active
+#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active
+#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active
+#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active
+#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active
+#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active
+#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active
+#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active
+#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active
+#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active
+#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active
+#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active
+#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active
+#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active
+#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active
+#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active
+#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active
+#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active
+#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active
+#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active
+#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active
+#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active
+#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE2 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE2_INT_M 0xFFFFFFFF // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE3 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE3_INT_M 0xFFFFFFFF // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE4 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE4_INT_M 0x000007FF // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI0 register.
+//
+//*****************************************************************************
+#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask
+#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask
+#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask
+#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask
+#define NVIC_PRI0_INT3_S 29
+#define NVIC_PRI0_INT2_S 21
+#define NVIC_PRI0_INT1_S 13
+#define NVIC_PRI0_INT0_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask
+#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask
+#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask
+#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask
+#define NVIC_PRI1_INT7_S 29
+#define NVIC_PRI1_INT6_S 21
+#define NVIC_PRI1_INT5_S 13
+#define NVIC_PRI1_INT4_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask
+#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask
+#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask
+#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask
+#define NVIC_PRI2_INT11_S 29
+#define NVIC_PRI2_INT10_S 21
+#define NVIC_PRI2_INT9_S 13
+#define NVIC_PRI2_INT8_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask
+#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask
+#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask
+#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask
+#define NVIC_PRI3_INT15_S 29
+#define NVIC_PRI3_INT14_S 21
+#define NVIC_PRI3_INT13_S 13
+#define NVIC_PRI3_INT12_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI4 register.
+//
+//*****************************************************************************
+#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask
+#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask
+#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask
+#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask
+#define NVIC_PRI4_INT19_S 29
+#define NVIC_PRI4_INT18_S 21
+#define NVIC_PRI4_INT17_S 13
+#define NVIC_PRI4_INT16_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI5 register.
+//
+//*****************************************************************************
+#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask
+#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask
+#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask
+#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask
+#define NVIC_PRI5_INT23_S 29
+#define NVIC_PRI5_INT22_S 21
+#define NVIC_PRI5_INT21_S 13
+#define NVIC_PRI5_INT20_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI6 register.
+//
+//*****************************************************************************
+#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask
+#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask
+#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask
+#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask
+#define NVIC_PRI6_INT27_S 29
+#define NVIC_PRI6_INT26_S 21
+#define NVIC_PRI6_INT25_S 13
+#define NVIC_PRI6_INT24_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI7 register.
+//
+//*****************************************************************************
+#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask
+#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask
+#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask
+#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask
+#define NVIC_PRI7_INT31_S 29
+#define NVIC_PRI7_INT30_S 21
+#define NVIC_PRI7_INT29_S 13
+#define NVIC_PRI7_INT28_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI8 register.
+//
+//*****************************************************************************
+#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask
+#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask
+#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask
+#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask
+#define NVIC_PRI8_INT35_S 29
+#define NVIC_PRI8_INT34_S 21
+#define NVIC_PRI8_INT33_S 13
+#define NVIC_PRI8_INT32_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI9 register.
+//
+//*****************************************************************************
+#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask
+#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask
+#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask
+#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask
+#define NVIC_PRI9_INT39_S 29
+#define NVIC_PRI9_INT38_S 21
+#define NVIC_PRI9_INT37_S 13
+#define NVIC_PRI9_INT36_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI10 register.
+//
+//*****************************************************************************
+#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask
+#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask
+#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask
+#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask
+#define NVIC_PRI10_INT43_S 29
+#define NVIC_PRI10_INT42_S 21
+#define NVIC_PRI10_INT41_S 13
+#define NVIC_PRI10_INT40_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI11 register.
+//
+//*****************************************************************************
+#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask
+#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask
+#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask
+#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask
+#define NVIC_PRI11_INT47_S 29
+#define NVIC_PRI11_INT46_S 21
+#define NVIC_PRI11_INT45_S 13
+#define NVIC_PRI11_INT44_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI12 register.
+//
+//*****************************************************************************
+#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask
+#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask
+#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask
+#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask
+#define NVIC_PRI12_INT51_S 29
+#define NVIC_PRI12_INT50_S 21
+#define NVIC_PRI12_INT49_S 13
+#define NVIC_PRI12_INT48_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI13 register.
+//
+//*****************************************************************************
+#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask
+#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask
+#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask
+#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask
+#define NVIC_PRI13_INT55_S 29
+#define NVIC_PRI13_INT54_S 21
+#define NVIC_PRI13_INT53_S 13
+#define NVIC_PRI13_INT52_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI14 register.
+//
+//*****************************************************************************
+#define NVIC_PRI14_INTD_M 0xE0000000 // Interrupt 59 Priority Mask
+#define NVIC_PRI14_INTC_M 0x00E00000 // Interrupt 58 Priority Mask
+#define NVIC_PRI14_INTB_M 0x0000E000 // Interrupt 57 Priority Mask
+#define NVIC_PRI14_INTA_M 0x000000E0 // Interrupt 56 Priority Mask
+#define NVIC_PRI14_INTD_S 29
+#define NVIC_PRI14_INTC_S 21
+#define NVIC_PRI14_INTB_S 13
+#define NVIC_PRI14_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI15 register.
+//
+//*****************************************************************************
+#define NVIC_PRI15_INTD_M 0xE0000000 // Interrupt 63 Priority Mask
+#define NVIC_PRI15_INTC_M 0x00E00000 // Interrupt 62 Priority Mask
+#define NVIC_PRI15_INTB_M 0x0000E000 // Interrupt 61 Priority Mask
+#define NVIC_PRI15_INTA_M 0x000000E0 // Interrupt 60 Priority Mask
+#define NVIC_PRI15_INTD_S 29
+#define NVIC_PRI15_INTC_S 21
+#define NVIC_PRI15_INTB_S 13
+#define NVIC_PRI15_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI16 register.
+//
+//*****************************************************************************
+#define NVIC_PRI16_INTD_M 0xE0000000 // Interrupt 67 Priority Mask
+#define NVIC_PRI16_INTC_M 0x00E00000 // Interrupt 66 Priority Mask
+#define NVIC_PRI16_INTB_M 0x0000E000 // Interrupt 65 Priority Mask
+#define NVIC_PRI16_INTA_M 0x000000E0 // Interrupt 64 Priority Mask
+#define NVIC_PRI16_INTD_S 29
+#define NVIC_PRI16_INTC_S 21
+#define NVIC_PRI16_INTB_S 13
+#define NVIC_PRI16_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI17 register.
+//
+//*****************************************************************************
+#define NVIC_PRI17_INTD_M 0xE0000000 // Interrupt 71 Priority Mask
+#define NVIC_PRI17_INTC_M 0x00E00000 // Interrupt 70 Priority Mask
+#define NVIC_PRI17_INTB_M 0x0000E000 // Interrupt 69 Priority Mask
+#define NVIC_PRI17_INTA_M 0x000000E0 // Interrupt 68 Priority Mask
+#define NVIC_PRI17_INTD_S 29
+#define NVIC_PRI17_INTC_S 21
+#define NVIC_PRI17_INTB_S 13
+#define NVIC_PRI17_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI18 register.
+//
+//*****************************************************************************
+#define NVIC_PRI18_INTD_M 0xE0000000 // Interrupt 75 Priority Mask
+#define NVIC_PRI18_INTC_M 0x00E00000 // Interrupt 74 Priority Mask
+#define NVIC_PRI18_INTB_M 0x0000E000 // Interrupt 73 Priority Mask
+#define NVIC_PRI18_INTA_M 0x000000E0 // Interrupt 72 Priority Mask
+#define NVIC_PRI18_INTD_S 29
+#define NVIC_PRI18_INTC_S 21
+#define NVIC_PRI18_INTB_S 13
+#define NVIC_PRI18_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI19 register.
+//
+//*****************************************************************************
+#define NVIC_PRI19_INTD_M 0xE0000000 // Interrupt 79 Priority Mask
+#define NVIC_PRI19_INTC_M 0x00E00000 // Interrupt 78 Priority Mask
+#define NVIC_PRI19_INTB_M 0x0000E000 // Interrupt 77 Priority Mask
+#define NVIC_PRI19_INTA_M 0x000000E0 // Interrupt 76 Priority Mask
+#define NVIC_PRI19_INTD_S 29
+#define NVIC_PRI19_INTC_S 21
+#define NVIC_PRI19_INTB_S 13
+#define NVIC_PRI19_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI20 register.
+//
+//*****************************************************************************
+#define NVIC_PRI20_INTD_M 0xE0000000 // Interrupt 83 Priority Mask
+#define NVIC_PRI20_INTC_M 0x00E00000 // Interrupt 82 Priority Mask
+#define NVIC_PRI20_INTB_M 0x0000E000 // Interrupt 81 Priority Mask
+#define NVIC_PRI20_INTA_M 0x000000E0 // Interrupt 80 Priority Mask
+#define NVIC_PRI20_INTD_S 29
+#define NVIC_PRI20_INTC_S 21
+#define NVIC_PRI20_INTB_S 13
+#define NVIC_PRI20_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI21 register.
+//
+//*****************************************************************************
+#define NVIC_PRI21_INTD_M 0xE0000000 // Interrupt 87 Priority Mask
+#define NVIC_PRI21_INTC_M 0x00E00000 // Interrupt 86 Priority Mask
+#define NVIC_PRI21_INTB_M 0x0000E000 // Interrupt 85 Priority Mask
+#define NVIC_PRI21_INTA_M 0x000000E0 // Interrupt 84 Priority Mask
+#define NVIC_PRI21_INTD_S 29
+#define NVIC_PRI21_INTC_S 21
+#define NVIC_PRI21_INTB_S 13
+#define NVIC_PRI21_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI22 register.
+//
+//*****************************************************************************
+#define NVIC_PRI22_INTD_M 0xE0000000 // Interrupt 91 Priority Mask
+#define NVIC_PRI22_INTC_M 0x00E00000 // Interrupt 90 Priority Mask
+#define NVIC_PRI22_INTB_M 0x0000E000 // Interrupt 89 Priority Mask
+#define NVIC_PRI22_INTA_M 0x000000E0 // Interrupt 88 Priority Mask
+#define NVIC_PRI22_INTD_S 29
+#define NVIC_PRI22_INTC_S 21
+#define NVIC_PRI22_INTB_S 13
+#define NVIC_PRI22_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI23 register.
+//
+//*****************************************************************************
+#define NVIC_PRI23_INTD_M 0xE0000000 // Interrupt 95 Priority Mask
+#define NVIC_PRI23_INTC_M 0x00E00000 // Interrupt 94 Priority Mask
+#define NVIC_PRI23_INTB_M 0x0000E000 // Interrupt 93 Priority Mask
+#define NVIC_PRI23_INTA_M 0x000000E0 // Interrupt 92 Priority Mask
+#define NVIC_PRI23_INTD_S 29
+#define NVIC_PRI23_INTC_S 21
+#define NVIC_PRI23_INTB_S 13
+#define NVIC_PRI23_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI24 register.
+//
+//*****************************************************************************
+#define NVIC_PRI24_INTD_M 0xE0000000 // Interrupt 99 Priority Mask
+#define NVIC_PRI24_INTC_M 0x00E00000 // Interrupt 98 Priority Mask
+#define NVIC_PRI24_INTB_M 0x0000E000 // Interrupt 97 Priority Mask
+#define NVIC_PRI24_INTA_M 0x000000E0 // Interrupt 96 Priority Mask
+#define NVIC_PRI24_INTD_S 29
+#define NVIC_PRI24_INTC_S 21
+#define NVIC_PRI24_INTB_S 13
+#define NVIC_PRI24_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI25 register.
+//
+//*****************************************************************************
+#define NVIC_PRI25_INTD_M 0xE0000000 // Interrupt 103 Priority Mask
+#define NVIC_PRI25_INTC_M 0x00E00000 // Interrupt 102 Priority Mask
+#define NVIC_PRI25_INTB_M 0x0000E000 // Interrupt 101 Priority Mask
+#define NVIC_PRI25_INTA_M 0x000000E0 // Interrupt 100 Priority Mask
+#define NVIC_PRI25_INTD_S 29
+#define NVIC_PRI25_INTC_S 21
+#define NVIC_PRI25_INTB_S 13
+#define NVIC_PRI25_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI26 register.
+//
+//*****************************************************************************
+#define NVIC_PRI26_INTD_M 0xE0000000 // Interrupt 107 Priority Mask
+#define NVIC_PRI26_INTC_M 0x00E00000 // Interrupt 106 Priority Mask
+#define NVIC_PRI26_INTB_M 0x0000E000 // Interrupt 105 Priority Mask
+#define NVIC_PRI26_INTA_M 0x000000E0 // Interrupt 104 Priority Mask
+#define NVIC_PRI26_INTD_S 29
+#define NVIC_PRI26_INTC_S 21
+#define NVIC_PRI26_INTB_S 13
+#define NVIC_PRI26_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI27 register.
+//
+//*****************************************************************************
+#define NVIC_PRI27_INTD_M 0xE0000000 // Interrupt 111 Priority Mask
+#define NVIC_PRI27_INTC_M 0x00E00000 // Interrupt 110 Priority Mask
+#define NVIC_PRI27_INTB_M 0x0000E000 // Interrupt 109 Priority Mask
+#define NVIC_PRI27_INTA_M 0x000000E0 // Interrupt 108 Priority Mask
+#define NVIC_PRI27_INTD_S 29
+#define NVIC_PRI27_INTC_S 21
+#define NVIC_PRI27_INTB_S 13
+#define NVIC_PRI27_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI28 register.
+//
+//*****************************************************************************
+#define NVIC_PRI28_INTD_M 0xE0000000 // Interrupt 115 Priority Mask
+#define NVIC_PRI28_INTC_M 0x00E00000 // Interrupt 114 Priority Mask
+#define NVIC_PRI28_INTB_M 0x0000E000 // Interrupt 113 Priority Mask
+#define NVIC_PRI28_INTA_M 0x000000E0 // Interrupt 112 Priority Mask
+#define NVIC_PRI28_INTD_S 29
+#define NVIC_PRI28_INTC_S 21
+#define NVIC_PRI28_INTB_S 13
+#define NVIC_PRI28_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI29 register.
+//
+//*****************************************************************************
+#define NVIC_PRI29_INTD_M 0xE0000000 // Interrupt 119 Priority Mask
+#define NVIC_PRI29_INTC_M 0x00E00000 // Interrupt 118 Priority Mask
+#define NVIC_PRI29_INTB_M 0x0000E000 // Interrupt 117 Priority Mask
+#define NVIC_PRI29_INTA_M 0x000000E0 // Interrupt 116 Priority Mask
+#define NVIC_PRI29_INTD_S 29
+#define NVIC_PRI29_INTC_S 21
+#define NVIC_PRI29_INTB_S 13
+#define NVIC_PRI29_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI30 register.
+//
+//*****************************************************************************
+#define NVIC_PRI30_INTD_M 0xE0000000 // Interrupt 123 Priority Mask
+#define NVIC_PRI30_INTC_M 0x00E00000 // Interrupt 122 Priority Mask
+#define NVIC_PRI30_INTB_M 0x0000E000 // Interrupt 121 Priority Mask
+#define NVIC_PRI30_INTA_M 0x000000E0 // Interrupt 120 Priority Mask
+#define NVIC_PRI30_INTD_S 29
+#define NVIC_PRI30_INTC_S 21
+#define NVIC_PRI30_INTB_S 13
+#define NVIC_PRI30_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI31 register.
+//
+//*****************************************************************************
+#define NVIC_PRI31_INTD_M 0xE0000000 // Interrupt 127 Priority Mask
+#define NVIC_PRI31_INTC_M 0x00E00000 // Interrupt 126 Priority Mask
+#define NVIC_PRI31_INTB_M 0x0000E000 // Interrupt 125 Priority Mask
+#define NVIC_PRI31_INTA_M 0x000000E0 // Interrupt 124 Priority Mask
+#define NVIC_PRI31_INTD_S 29
+#define NVIC_PRI31_INTC_S 21
+#define NVIC_PRI31_INTB_S 13
+#define NVIC_PRI31_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI32 register.
+//
+//*****************************************************************************
+#define NVIC_PRI32_INTD_M 0xE0000000 // Interrupt 131 Priority Mask
+#define NVIC_PRI32_INTC_M 0x00E00000 // Interrupt 130 Priority Mask
+#define NVIC_PRI32_INTB_M 0x0000E000 // Interrupt 129 Priority Mask
+#define NVIC_PRI32_INTA_M 0x000000E0 // Interrupt 128 Priority Mask
+#define NVIC_PRI32_INTD_S 29
+#define NVIC_PRI32_INTC_S 21
+#define NVIC_PRI32_INTB_S 13
+#define NVIC_PRI32_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI33 register.
+//
+//*****************************************************************************
+#define NVIC_PRI33_INTD_M 0xE0000000 // Interrupt Priority for Interrupt
+ // [4n+3]
+#define NVIC_PRI33_INTC_M 0x00E00000 // Interrupt Priority for Interrupt
+ // [4n+2]
+#define NVIC_PRI33_INTB_M 0x0000E000 // Interrupt Priority for Interrupt
+ // [4n+1]
+#define NVIC_PRI33_INTA_M 0x000000E0 // Interrupt Priority for Interrupt
+ // [4n]
+#define NVIC_PRI33_INTD_S 29
+#define NVIC_PRI33_INTC_S 21
+#define NVIC_PRI33_INTB_S 13
+#define NVIC_PRI33_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI34 register.
+//
+//*****************************************************************************
+#define NVIC_PRI34_INTD_M 0xE0000000 // Interrupt Priority for Interrupt
+ // [4n+3]
+#define NVIC_PRI34_INTC_M 0x00E00000 // Interrupt Priority for Interrupt
+ // [4n+2]
+#define NVIC_PRI34_INTB_M 0x0000E000 // Interrupt Priority for Interrupt
+ // [4n+1]
+#define NVIC_PRI34_INTA_M 0x000000E0 // Interrupt Priority for Interrupt
+ // [4n]
+#define NVIC_PRI34_INTD_S 29
+#define NVIC_PRI34_INTC_S 21
+#define NVIC_PRI34_INTB_S 13
+#define NVIC_PRI34_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CPUID register.
+//
+//*****************************************************************************
+#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code
+#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM
+#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number
+#define NVIC_CPUID_CON_M 0x000F0000 // Constant
+#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number
+#define NVIC_CPUID_PARTNO_CM3 0x0000C230 // Cortex-M3 processor
+#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor
+#define NVIC_CPUID_REV_M 0x0000000F // Revision Number
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_INT_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending
+#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending
+#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending
+#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending
+#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending
+#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling
+#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending
+#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number
+#define NVIC_INT_CTRL_VEC_PEN_NMI \
+ 0x00002000 // NMI
+#define NVIC_INT_CTRL_VEC_PEN_HARD \
+ 0x00003000 // Hard fault
+#define NVIC_INT_CTRL_VEC_PEN_MEM \
+ 0x00004000 // Memory management fault
+#define NVIC_INT_CTRL_VEC_PEN_BUS \
+ 0x00005000 // Bus fault
+#define NVIC_INT_CTRL_VEC_PEN_USG \
+ 0x00006000 // Usage fault
+#define NVIC_INT_CTRL_VEC_PEN_SVC \
+ 0x0000B000 // SVCall
+#define NVIC_INT_CTRL_VEC_PEN_PNDSV \
+ 0x0000E000 // PendSV
+#define NVIC_INT_CTRL_VEC_PEN_TICK \
+ 0x0000F000 // SysTick
+#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base
+#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number
+#define NVIC_INT_CTRL_VEC_PEN_S 12
+#define NVIC_INT_CTRL_VEC_ACT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_VTABLE register.
+//
+//*****************************************************************************
+#define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base
+#define NVIC_VTABLE_OFFSET_M 0x1FFFFC00 // Vector Table Offset
+#define NVIC_VTABLE_OFFSET_S 10
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_APINT register.
+//
+//*****************************************************************************
+#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key
+#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key
+#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess
+#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping
+#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split
+#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split
+#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split
+#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request
+#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault
+#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending
+#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable
+#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CFG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception
+ // Entry
+#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and
+ // Fault
+#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0
+#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access
+#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger
+#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority
+#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority
+#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority
+#define NVIC_SYS_PRI1_USAGE_S 21
+#define NVIC_SYS_PRI1_BUS_S 13
+#define NVIC_SYS_PRI1_MEM_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority
+#define NVIC_SYS_PRI2_SVC_S 29
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority
+#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority
+#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority
+#define NVIC_SYS_PRI3_TICK_S 29
+#define NVIC_SYS_PRI3_PENDSV_S 21
+#define NVIC_SYS_PRI3_DEBUG_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL
+// register.
+//
+//*****************************************************************************
+#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable
+#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable
+#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable
+#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending
+#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending
+#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending
+#define NVIC_SYS_HND_CTRL_USAGEP \
+ 0x00001000 // Usage Fault Pending
+#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active
+#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active
+#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active
+#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active
+#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active
+#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active
+#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault
+#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault
+#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault
+#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault
+#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault
+#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage
+ // Fault
+#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid
+#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy
+ // State Preservation
+#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault
+#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault
+#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error
+#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error
+#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error
+#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address
+ // Register Valid
+#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on
+ // Floating-Point Lazy State
+ // Preservation
+#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation
+#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation
+#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation
+#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_HFAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event
+#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault
+#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DEBUG_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted
+#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch
+#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match
+#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction
+#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MM_ADDR register.
+//
+//*****************************************************************************
+#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address
+#define NVIC_MM_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_ADDR
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address
+#define NVIC_FAULT_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CPAC register.
+//
+//*****************************************************************************
+#define NVIC_CPAC_CP11_M 0x00C00000 // CP11 Coprocessor Access
+ // Privilege
+#define NVIC_CPAC_CP11_DIS 0x00000000 // Access Denied
+#define NVIC_CPAC_CP11_PRIV 0x00400000 // Privileged Access Only
+#define NVIC_CPAC_CP11_FULL 0x00C00000 // Full Access
+#define NVIC_CPAC_CP10_M 0x00300000 // CP10 Coprocessor Access
+ // Privilege
+#define NVIC_CPAC_CP10_DIS 0x00000000 // Access Denied
+#define NVIC_CPAC_CP10_PRIV 0x00100000 // Privileged Access Only
+#define NVIC_CPAC_CP10_FULL 0x00300000 // Full Access
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_TYPE register.
+//
+//*****************************************************************************
+#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I Regions
+#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D Regions
+#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or Unified MPU
+#define NVIC_MPU_TYPE_IREGION_S 16
+#define NVIC_MPU_TYPE_DREGION_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU Default Region
+#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU Enabled During Faults
+#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_NUMBER
+// register.
+//
+//*****************************************************************************
+#define NVIC_MPU_NUMBER_M 0x00000007 // MPU Region to Access
+#define NVIC_MPU_NUMBER_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base Address Mask
+#define NVIC_MPU_BASE_VALID 0x00000010 // Region Number Valid
+#define NVIC_MPU_BASE_REGION_M 0x00000007 // Region Number
+#define NVIC_MPU_BASE_ADDR_S 5
+#define NVIC_MPU_BASE_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR_M 0xFFFF0000 // Attributes
+#define NVIC_MPU_ATTR_XN 0x10000000 // Instruction Access Disable
+#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access Privilege
+#define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 // prv: no access, usr: no access
+#define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 // prv: rw, usr: none
+#define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 // prv: rw, usr: read-only
+#define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 // prv: rw, usr: rw
+#define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 // prv: ro, usr: none
+#define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 // prv: ro, usr: ro
+#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type Extension Mask
+#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable
+#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable
+#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable
+#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Subregion Disable Bits
+#define NVIC_MPU_ATTR_SRD_0 0x00000100 // Sub-region 0 disable
+#define NVIC_MPU_ATTR_SRD_1 0x00000200 // Sub-region 1 disable
+#define NVIC_MPU_ATTR_SRD_2 0x00000400 // Sub-region 2 disable
+#define NVIC_MPU_ATTR_SRD_3 0x00000800 // Sub-region 3 disable
+#define NVIC_MPU_ATTR_SRD_4 0x00001000 // Sub-region 4 disable
+#define NVIC_MPU_ATTR_SRD_5 0x00002000 // Sub-region 5 disable
+#define NVIC_MPU_ATTR_SRD_6 0x00004000 // Sub-region 6 disable
+#define NVIC_MPU_ATTR_SRD_7 0x00008000 // Sub-region 7 disable
+#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region Size Mask
+#define NVIC_MPU_ATTR_SIZE_32B 0x00000008 // Region size 32 bytes
+#define NVIC_MPU_ATTR_SIZE_64B 0x0000000A // Region size 64 bytes
+#define NVIC_MPU_ATTR_SIZE_128B 0x0000000C // Region size 128 bytes
+#define NVIC_MPU_ATTR_SIZE_256B 0x0000000E // Region size 256 bytes
+#define NVIC_MPU_ATTR_SIZE_512B 0x00000010 // Region size 512 bytes
+#define NVIC_MPU_ATTR_SIZE_1K 0x00000012 // Region size 1 Kbytes
+#define NVIC_MPU_ATTR_SIZE_2K 0x00000014 // Region size 2 Kbytes
+#define NVIC_MPU_ATTR_SIZE_4K 0x00000016 // Region size 4 Kbytes
+#define NVIC_MPU_ATTR_SIZE_8K 0x00000018 // Region size 8 Kbytes
+#define NVIC_MPU_ATTR_SIZE_16K 0x0000001A // Region size 16 Kbytes
+#define NVIC_MPU_ATTR_SIZE_32K 0x0000001C // Region size 32 Kbytes
+#define NVIC_MPU_ATTR_SIZE_64K 0x0000001E // Region size 64 Kbytes
+#define NVIC_MPU_ATTR_SIZE_128K 0x00000020 // Region size 128 Kbytes
+#define NVIC_MPU_ATTR_SIZE_256K 0x00000022 // Region size 256 Kbytes
+#define NVIC_MPU_ATTR_SIZE_512K 0x00000024 // Region size 512 Kbytes
+#define NVIC_MPU_ATTR_SIZE_1M 0x00000026 // Region size 1 Mbytes
+#define NVIC_MPU_ATTR_SIZE_2M 0x00000028 // Region size 2 Mbytes
+#define NVIC_MPU_ATTR_SIZE_4M 0x0000002A // Region size 4 Mbytes
+#define NVIC_MPU_ATTR_SIZE_8M 0x0000002C // Region size 8 Mbytes
+#define NVIC_MPU_ATTR_SIZE_16M 0x0000002E // Region size 16 Mbytes
+#define NVIC_MPU_ATTR_SIZE_32M 0x00000030 // Region size 32 Mbytes
+#define NVIC_MPU_ATTR_SIZE_64M 0x00000032 // Region size 64 Mbytes
+#define NVIC_MPU_ATTR_SIZE_128M 0x00000034 // Region size 128 Mbytes
+#define NVIC_MPU_ATTR_SIZE_256M 0x00000036 // Region size 256 Mbytes
+#define NVIC_MPU_ATTR_SIZE_512M 0x00000038 // Region size 512 Mbytes
+#define NVIC_MPU_ATTR_SIZE_1G 0x0000003A // Region size 1 Gbytes
+#define NVIC_MPU_ATTR_SIZE_2G 0x0000003C // Region size 2 Gbytes
+#define NVIC_MPU_ATTR_SIZE_4G 0x0000003E // Region size 4 Gbytes
+#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE1 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE1_ADDR_M 0xFFFFFFE0 // Base Address Mask
+#define NVIC_MPU_BASE1_VALID 0x00000010 // Region Number Valid
+#define NVIC_MPU_BASE1_REGION_M 0x00000007 // Region Number
+#define NVIC_MPU_BASE1_ADDR_S 5
+#define NVIC_MPU_BASE1_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR1_XN 0x10000000 // Instruction Access Disable
+#define NVIC_MPU_ATTR1_AP_M 0x07000000 // Access Privilege
+#define NVIC_MPU_ATTR1_TEX_M 0x00380000 // Type Extension Mask
+#define NVIC_MPU_ATTR1_SHAREABLE \
+ 0x00040000 // Shareable
+#define NVIC_MPU_ATTR1_CACHEABLE \
+ 0x00020000 // Cacheable
+#define NVIC_MPU_ATTR1_BUFFRABLE \
+ 0x00010000 // Bufferable
+#define NVIC_MPU_ATTR1_SRD_M 0x0000FF00 // Subregion Disable Bits
+#define NVIC_MPU_ATTR1_SIZE_M 0x0000003E // Region Size Mask
+#define NVIC_MPU_ATTR1_ENABLE 0x00000001 // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE2 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE2_ADDR_M 0xFFFFFFE0 // Base Address Mask
+#define NVIC_MPU_BASE2_VALID 0x00000010 // Region Number Valid
+#define NVIC_MPU_BASE2_REGION_M 0x00000007 // Region Number
+#define NVIC_MPU_BASE2_ADDR_S 5
+#define NVIC_MPU_BASE2_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR2_XN 0x10000000 // Instruction Access Disable
+#define NVIC_MPU_ATTR2_AP_M 0x07000000 // Access Privilege
+#define NVIC_MPU_ATTR2_TEX_M 0x00380000 // Type Extension Mask
+#define NVIC_MPU_ATTR2_SHAREABLE \
+ 0x00040000 // Shareable
+#define NVIC_MPU_ATTR2_CACHEABLE \
+ 0x00020000 // Cacheable
+#define NVIC_MPU_ATTR2_BUFFRABLE \
+ 0x00010000 // Bufferable
+#define NVIC_MPU_ATTR2_SRD_M 0x0000FF00 // Subregion Disable Bits
+#define NVIC_MPU_ATTR2_SIZE_M 0x0000003E // Region Size Mask
+#define NVIC_MPU_ATTR2_ENABLE 0x00000001 // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE3 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE3_ADDR_M 0xFFFFFFE0 // Base Address Mask
+#define NVIC_MPU_BASE3_VALID 0x00000010 // Region Number Valid
+#define NVIC_MPU_BASE3_REGION_M 0x00000007 // Region Number
+#define NVIC_MPU_BASE3_ADDR_S 5
+#define NVIC_MPU_BASE3_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR3_XN 0x10000000 // Instruction Access Disable
+#define NVIC_MPU_ATTR3_AP_M 0x07000000 // Access Privilege
+#define NVIC_MPU_ATTR3_TEX_M 0x00380000 // Type Extension Mask
+#define NVIC_MPU_ATTR3_SHAREABLE \
+ 0x00040000 // Shareable
+#define NVIC_MPU_ATTR3_CACHEABLE \
+ 0x00020000 // Cacheable
+#define NVIC_MPU_ATTR3_BUFFRABLE \
+ 0x00010000 // Bufferable
+#define NVIC_MPU_ATTR3_SRD_M 0x0000FF00 // Subregion Disable Bits
+#define NVIC_MPU_ATTR3_SIZE_M 0x0000003E // Region Size Mask
+#define NVIC_MPU_ATTR3_ENABLE 0x00000001 // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask
+#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key
+#define NVIC_DBG_CTRL_S_RESET_ST \
+ 0x02000000 // Core has reset since last read
+#define NVIC_DBG_CTRL_S_RETIRE_ST \
+ 0x01000000 // Core has executed insruction
+ // since last read
+#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up
+#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping
+#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt
+#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available
+#define NVIC_DBG_CTRL_C_SNAPSTALL \
+ 0x00000020 // Breaks a stalled load/store
+#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping
+#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core
+#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core
+#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_XFER register.
+//
+//*****************************************************************************
+#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read
+#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register
+#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0
+#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1
+#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2
+#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3
+#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4
+#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5
+#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6
+#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7
+#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8
+#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9
+#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10
+#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11
+#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12
+#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13
+#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14
+#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15
+#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register
+#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP
+#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP
+#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP
+#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_DATA register.
+//
+//*****************************************************************************
+#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache
+#define NVIC_DBG_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_INT register.
+//
+//*****************************************************************************
+#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault
+#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors
+#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error
+#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state
+#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check
+#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error
+#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault
+#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status
+#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset
+#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending
+#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SW_TRIG register.
+//
+//*****************************************************************************
+#define NVIC_SW_TRIG_INTID_M 0x000000FF // Interrupt ID
+#define NVIC_SW_TRIG_INTID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FPCC register.
+//
+//*****************************************************************************
+#define NVIC_FPCC_ASPEN 0x80000000 // Automatic State Preservation
+ // Enable
+#define NVIC_FPCC_LSPEN 0x40000000 // Lazy State Preservation Enable
+#define NVIC_FPCC_MONRDY 0x00000100 // Monitor Ready
+#define NVIC_FPCC_BFRDY 0x00000040 // Bus Fault Ready
+#define NVIC_FPCC_MMRDY 0x00000020 // Memory Management Fault Ready
+#define NVIC_FPCC_HFRDY 0x00000010 // Hard Fault Ready
+#define NVIC_FPCC_THREAD 0x00000008 // Thread Mode
+#define NVIC_FPCC_USER 0x00000002 // User Privilege Level
+#define NVIC_FPCC_LSPACT 0x00000001 // Lazy State Preservation Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FPCA register.
+//
+//*****************************************************************************
+#define NVIC_FPCA_ADDRESS_M 0xFFFFFFF8 // Address
+#define NVIC_FPCA_ADDRESS_S 3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FPDSC register.
+//
+//*****************************************************************************
+#define NVIC_FPDSC_AHP 0x04000000 // AHP Bit Default
+#define NVIC_FPDSC_DN 0x02000000 // DN Bit Default
+#define NVIC_FPDSC_FZ 0x01000000 // FZ Bit Default
+#define NVIC_FPDSC_RMODE_M 0x00C00000 // RMODE Bit Default
+#define NVIC_FPDSC_RMODE_RN 0x00000000 // Round to Nearest (RN) mode
+#define NVIC_FPDSC_RMODE_RP 0x00400000 // Round towards Plus Infinity (RP)
+ // mode
+#define NVIC_FPDSC_RMODE_RM 0x00800000 // Round towards Minus Infinity
+ // (RM) mode
+#define NVIC_FPDSC_RMODE_RZ 0x00C00000 // Round towards Zero (RZ) mode
+
+#endif // __HW_NVIC_H__
diff --git a/inc/hw_peci.h b/inc/hw_peci.h new file mode 100644 index 0000000..1022e3d --- /dev/null +++ b/inc/hw_peci.h @@ -0,0 +1,376 @@ +//*****************************************************************************
+//
+// hw_peci.h - Macros used when accessing the PECI hardware.
+//
+// Copyright (c) 2010-2012 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 9453 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_PECI_H__
+#define __HW_PECI_H__
+
+//*****************************************************************************
+//
+// The following are defines for the PECI register addresses.
+//
+//*****************************************************************************
+#define PECI_O_CTL 0x00000000 // PECI Control
+#define PECI_O_DIV 0x00000004 // PECI Poll-Rate Divider
+#define PECI_O_M0D0C 0x00000010 // PECI Microprocessor 0 / Domain 0
+ // Control
+#define PECI_O_M0D1C 0x00000014 // PECI Microprocessor 0 / Domain 1
+ // Control
+#define PECI_O_M1D0C 0x00000018 // PECI Microprocessor 1 / Domain 0
+ // Control
+#define PECI_O_M1D1C 0x0000001C // PECI Microprocessor 1 / Domain 1
+ // Control
+#define PECI_O_M0D0 0x00000040 // PECI Microprocessor 0 / Domain 0
+ // Value
+#define PECI_O_M0D1 0x00000044 // PECI Microprocessor 0 / Domain 1
+ // Value
+#define PECI_O_M1D0 0x00000048 // PECI Microprocessor 1 / Domain 0
+ // Value
+#define PECI_O_M1D1 0x0000004C // PECI Microprocessor 1 / Domain 1
+ // Value
+#define PECI_O_IM 0x00000080 // PECI Interrupt Mask
+#define PECI_O_RIS 0x00000084 // PECI Raw Interrupt Status
+#define PECI_O_MIS 0x00000088 // PECI Masked Interrupt Status
+#define PECI_O_IC 0x0000008C // PECI Interrupt Clear
+#define PECI_O_ACADDR 0x00000100 // PECI Advanced Command Address
+#define PECI_O_ACARG 0x00000104 // PECI Advanced Command Argument
+#define PECI_O_ACRDWR0 0x00000108 // PECI Advanced Command Data 0
+#define PECI_O_ACRDWR1 0x0000010C // PECI Advanced Command Data 1
+#define PECI_O_ACCMD 0x00000110 // PECI Advanced Command
+#define PECI_O_ACCODE 0x00000114 // PECI Advanced Command Completion
+ // Code
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PECI_O_CTL register.
+//
+//*****************************************************************************
+#define PECI_CTL_OFFSET_M 0xFFFF0000 // Offset Value
+#define PECI_CTL_CRETRY_M 0x00007000 // Number of Controller Retries
+#define PECI_CTL_BYERR 0x00000800 // Timing Negotiation Error Bypass
+#define PECI_CTL_RXINV 0x00000400 // Invert PECI RX Input
+#define PECI_CTL_M1D1EN 0x00000008 // Enable Microprocessor 1 and
+ // Domain 1
+#define PECI_CTL_M1D0EN 0x00000004 // Enable Microprocessor 1 and
+ // Domain 0
+#define PECI_CTL_M0D1EN 0x00000002 // Enable Microprocessor 0 and
+ // Domain 1
+#define PECI_CTL_M0D0EN 0x00000001 // Enable Microprocessor 0 and
+ // Domain 0
+#define PECI_CTL_OFFSET_S 16
+#define PECI_CTL_CRETRY_S 12
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PECI_O_DIV register.
+//
+//*****************************************************************************
+#define PECI_DIV_BAUD_M 0xFFFF0000 // Baud Rate
+#define PECI_DIV_POLL_M 0x0000FFFF // Counter for Inter-Poll Delay
+#define PECI_DIV_BAUD_S 16
+#define PECI_DIV_POLL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PECI_O_M0D0C register.
+//
+//*****************************************************************************
+#define PECI_M0D0C_HITHR_M 0xFFFF0000 // High Threshold
+#define PECI_M0D0C_LOTHR_M 0x0000FFFF // Low Threshold
+#define PECI_M0D0C_HITHR_S 16
+#define PECI_M0D0C_LOTHR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PECI_O_M0D1C register.
+//
+//*****************************************************************************
+#define PECI_M0D1C_HITHR_M 0xFFFF0000 // High Threshold
+#define PECI_M0D1C_LOTHR_M 0x0000FFFF // Low Threshold
+#define PECI_M0D1C_HITHR_S 16
+#define PECI_M0D1C_LOTHR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PECI_O_M1D0C register.
+//
+//*****************************************************************************
+#define PECI_M1D0C_HITHR_M 0xFFFF0000 // High Threshold
+#define PECI_M1D0C_LOTHR_M 0x0000FFFF // Low Threshold
+#define PECI_M1D0C_HITHR_S 16
+#define PECI_M1D0C_LOTHR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PECI_O_M1D1C register.
+//
+//*****************************************************************************
+#define PECI_M1D1C_HITHR_M 0xFFFF0000 // High Threshold
+#define PECI_M1D1C_LOTHR_M 0x0000FFFF // Low Threshold
+#define PECI_M1D1C_HITHR_S 16
+#define PECI_M1D1C_LOTHR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PECI_O_M0D0 register.
+//
+//*****************************************************************************
+#define PECI_M0D0_MAXREAD_M 0xFFFF0000 // Highest Value Read
+#define PECI_M0D0_VALUE_M 0x0000FFFF // Last Value Read
+#define PECI_M0D0_VALUE_MCRCTX 0x000081F9 // Microprocessor abort CRC error
+ // on transmitted data
+#define PECI_M0D0_VALUE_CRCRX 0x000081FA // CRC error on received data
+#define PECI_M0D0_VALUE_CRCTX 0x000081FB // CRC error on transmitted data
+#define PECI_M0D0_VALUE_NEG 0x000081FC // Negotiation error
+#define PECI_M0D0_VALUE_TO 0x000081FD // Timeout error
+#define PECI_M0D0_MAXREAD_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PECI_O_M0D1 register.
+//
+//*****************************************************************************
+#define PECI_M0D1_MAXREAD_M 0xFFFF0000 // Highest Value Read
+#define PECI_M0D1_VALUE_M 0x0000FFFF // Last Value Read
+#define PECI_M0D1_VALUE_MCRCTX 0x000081F9 // Microprocessor abort CRC error
+ // on transmitted data
+#define PECI_M0D1_VALUE_CRCRX 0x000081FA // CRC error on received data
+#define PECI_M0D1_VALUE_CRCTX 0x000081FB // CRC error on transmitted data
+#define PECI_M0D1_VALUE_NEG 0x000081FC // Negotiation error
+#define PECI_M0D1_VALUE_TO 0x000081FD // Timeout error
+#define PECI_M0D1_MAXREAD_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PECI_O_M1D0 register.
+//
+//*****************************************************************************
+#define PECI_M1D0_MAXREAD_M 0xFFFF0000 // Highest Value Read
+#define PECI_M1D0_VALUE_M 0x0000FFFF // Last Value Read
+#define PECI_M1D0_VALUE_MCRCTX 0x000081F9 // Microprocessor abort CRC error
+ // on transmitted data
+#define PECI_M1D0_VALUE_CRCRX 0x000081FA // CRC error on received data
+#define PECI_M1D0_VALUE_CRCTX 0x000081FB // CRC error on transmitted data
+#define PECI_M1D0_VALUE_NEG 0x000081FC // Negotiation error
+#define PECI_M1D0_VALUE_TO 0x000081FD // Timeout error
+#define PECI_M1D0_MAXREAD_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PECI_O_M1D1 register.
+//
+//*****************************************************************************
+#define PECI_M1D1_MAXREAD_M 0xFFFF0000 // Highest Value Read
+#define PECI_M1D1_VALUE_M 0x0000FFFF // Last Value Read
+#define PECI_M1D1_VALUE_MCRCTX 0x000081F9 // Microprocessor abort CRC error
+ // on transmitted data
+#define PECI_M1D1_VALUE_CRCRX 0x000081FA // CRC error on received data
+#define PECI_M1D1_VALUE_CRCTX 0x000081FB // CRC error on transmitted data
+#define PECI_M1D1_VALUE_NEG 0x000081FC // Negotiation error
+#define PECI_M1D1_VALUE_TO 0x000081FD // Timeout error
+#define PECI_M1D1_MAXREAD_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PECI_O_IM register.
+//
+//*****************************************************************************
+#define PECI_IM_M1D1IM_M 0x00C00000 // Microprocessor 1 and Domain 1
+ // Interrupt Mask
+#define PECI_IM_M1D1IM_HIGH 0x00400000 // Interrupt when crossing above
+ // high threshold
+#define PECI_IM_M1D1IM_CROSSUP 0x00800000 // Interrupt when crossing above
+ // either threshold
+#define PECI_IM_M1D1IM_CROSSANY 0x00C00000 // Interrupt when crossing either
+ // threshold in either direction
+#define PECI_IM_M1D0IM_M 0x00300000 // Microprocessor 1 and Domain 0
+ // Interrupt Mask
+#define PECI_IM_M0D1IM_M 0x000C0000 // Microprocessor 0 and Domain 1
+ // Interrupt Mask
+#define PECI_IM_M0D0IM_M 0x00030000 // Microprocessor 0 and Domain 0
+ // Interrupt Mask
+#define PECI_IM_ACIM 0x00000004 // Advanced Command Interrupt Mask
+#define PECI_IM_ERRIM 0x00000002 // Polling Error Detected Interrupt
+ // Mask
+#define PECI_IM_POLLIM 0x00000001 // Poll Completed Interrupt Mask
+#define PECI_IM_M1D0IM_S 20
+#define PECI_IM_M0D1IM_S 18
+#define PECI_IM_M0D0IM_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PECI_O_RIS register.
+//
+//*****************************************************************************
+#define PECI_RIS_M1D1RIS_M 0x00C00000 // Microprocessor 1 and Domain 1
+ // Raw Interrupt Status
+#define PECI_RIS_M1D0RIS_M 0x00300000 // Microprocessor 1 and Domain 0
+ // Raw Interrupt Status
+#define PECI_RIS_M0D1RIS_M 0x000C0000 // Microprocessor 0 and Domain 1
+ // Raw Interrupt Status
+#define PECI_RIS_M0D0RIS_M 0x00030000 // Microprocessor 0 and Domain 0
+ // Raw Interrupt Status
+#define PECI_RIS_ACRIS 0x00000004 // Advanced Command Raw Interrupt
+ // Status
+#define PECI_RIS_ERRRIS 0x00000002 // Polling Error Detected Raw
+ // Interrupt Status
+#define PECI_RIS_POLLRIS 0x00000001 // Poll Completed Raw Interrupt
+ // Status
+#define PECI_RIS_M1D1RIS_S 22
+#define PECI_RIS_M1D0RIS_S 20
+#define PECI_RIS_M0D1RIS_S 18
+#define PECI_RIS_M0D0RIS_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PECI_O_MIS register.
+//
+//*****************************************************************************
+#define PECI_MIS_M1D1MIS_M 0x00C00000 // Microprocessor 1 and Domain 1
+ // Masked Interrupt Status
+#define PECI_MIS_M1D0MIS_M 0x00300000 // Microprocessor 1 and Domain 0
+ // Masked Interrupt Status
+#define PECI_MIS_M0D1MIS_M 0x000C0000 // Microprocessor 0 and Domain 1
+ // Masked Interrupt Status
+#define PECI_MIS_M0D0MIS_M 0x00030000 // Microprocessor 0 and Domain 0
+ // Masked Interrupt Status
+#define PECI_MIS_ACMIS 0x00000004 // Advanced Command Masked
+ // Interrupt Status
+#define PECI_MIS_ERRMIS 0x00000002 // Polling Error Detected Masked
+ // Interrupt Status
+#define PECI_MIS_POLLMIS 0x00000001 // Poll Completed Masked Interrupt
+ // Status
+#define PECI_MIS_M1D1MIS_S 22
+#define PECI_MIS_M1D0MIS_S 20
+#define PECI_MIS_M0D1MIS_S 18
+#define PECI_MIS_M0D0MIS_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PECI_O_IC register.
+//
+//*****************************************************************************
+#define PECI_IC_M1D1IC_M 0x00C00000 // Microprocessor 1 and Domain 1
+ // Interrupt Clear
+#define PECI_IC_M1D0IC_M 0x00300000 // Microprocessor 1 and Domain 0
+ // Interrupt Clear
+#define PECI_IC_M0D1IC_M 0x000C0000 // Microprocessor 0 and Domain 1
+ // Interrupt Clear
+#define PECI_IC_M0D0IC_M 0x00030000 // Microprocessor 0 and Domain 0
+ // Interrupt Clear
+#define PECI_IC_ACIC 0x00000004 // Advanced Command Interrupt Clear
+#define PECI_IC_ERRIC 0x00000002 // Polling Error Detected Interrupt
+ // Clear
+#define PECI_IC_POLLIC 0x00000001 // Poll Completed Interrupt Clear
+#define PECI_IC_M1D1IC_S 22
+#define PECI_IC_M1D0IC_S 20
+#define PECI_IC_M0D1IC_S 18
+#define PECI_IC_M0D0IC_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PECI_O_ACADDR register.
+//
+//*****************************************************************************
+#define PECI_ACADDR_HIDRE_M 0xFF000000 // HostID and Retry
+#define PECI_ACADDR_SIZE_M 0x00FF0000 // Data Size
+#define PECI_ACADDR_DOMAIN_M 0x0000FF00 // Domain Select
+#define PECI_ACADDR_PROCADD_M 0x000000FF // Processor Address
+#define PECI_ACADDR_HIDRE_S 24
+#define PECI_ACADDR_SIZE_S 16
+#define PECI_ACADDR_DOMAIN_S 8
+#define PECI_ACADDR_PROCADD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PECI_O_ACARG register.
+//
+//*****************************************************************************
+#define PECI_ACARG_ARG3_M 0xFF000000 // Argument 3
+#define PECI_ACARG_ARG2_M 0x00FF0000 // Argument 2
+#define PECI_ACARG_ARG1_M 0x0000FF00 // Argument 1
+#define PECI_ACARG_ARG0_M 0x000000FF // Argument 0
+#define PECI_ACARG_ARG3_S 24
+#define PECI_ACARG_ARG2_S 16
+#define PECI_ACARG_ARG1_S 8
+#define PECI_ACARG_ARG0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PECI_O_ACRDWR0 register.
+//
+//*****************************************************************************
+#define PECI_ACRDWR0_D3_M 0xFF000000 // Data 3
+#define PECI_ACRDWR0_D2_M 0x00FF0000 // Data 2
+#define PECI_ACRDWR0_D1_M 0x0000FF00 // Data 1
+#define PECI_ACRDWR0_D0_M 0x000000FF // Data 0
+#define PECI_ACRDWR0_D3_S 24
+#define PECI_ACRDWR0_D2_S 16
+#define PECI_ACRDWR0_D1_S 8
+#define PECI_ACRDWR0_D0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PECI_O_ACRDWR1 register.
+//
+//*****************************************************************************
+#define PECI_ACRDWR1_D3_M 0xFF000000 // Data 3
+#define PECI_ACRDWR1_D2_M 0x00FF0000 // Data 2
+#define PECI_ACRDWR1_D1_M 0x0000FF00 // Data 1
+#define PECI_ACRDWR1_D0_M 0x000000FF // Data 0
+#define PECI_ACRDWR1_D3_S 24
+#define PECI_ACRDWR1_D2_S 16
+#define PECI_ACRDWR1_D1_S 8
+#define PECI_ACRDWR1_D0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PECI_O_ACCMD register.
+//
+//*****************************************************************************
+#define PECI_ACCMD_CMD_M 0x000000FF // Base Command
+#define PECI_ACCMD_CMD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PECI_O_ACCODE register.
+//
+//*****************************************************************************
+#define PECI_ACCODE_CODE_M 0xFFFFFFFF // Signed Completion Code
+
+#endif // __HW_PECI_H__
diff --git a/inc/hw_pwm.h b/inc/hw_pwm.h new file mode 100644 index 0000000..0d7c825 --- /dev/null +++ b/inc/hw_pwm.h @@ -0,0 +1,2020 @@ +//*****************************************************************************
+//
+// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports.
+//
+// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 9453 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_PWM_H__
+#define __HW_PWM_H__
+
+//*****************************************************************************
+//
+// The following are defines for the PWM register offsets.
+//
+//*****************************************************************************
+#define PWM_O_CTL 0x00000000 // PWM Master Control
+#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync
+#define PWM_O_ENABLE 0x00000008 // PWM Output Enable
+#define PWM_O_INVERT 0x0000000C // PWM Output Inversion
+#define PWM_O_FAULT 0x00000010 // PWM Output Fault
+#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable
+#define PWM_O_RIS 0x00000018 // PWM Raw Interrupt Status
+#define PWM_O_ISC 0x0000001C // PWM Interrupt Status and Clear
+#define PWM_O_STATUS 0x00000020 // PWM Status
+#define PWM_O_FAULTVAL 0x00000024 // PWM Fault Condition Value
+#define PWM_O_ENUPD 0x00000028 // PWM Enable Update
+#define PWM_O_0_CTL 0x00000040 // PWM0 Control
+#define PWM_O_0_INTEN 0x00000044 // PWM0 Interrupt and Trigger
+ // Enable
+#define PWM_O_0_RIS 0x00000048 // PWM0 Raw Interrupt Status
+#define PWM_O_0_ISC 0x0000004C // PWM0 Interrupt Status and Clear
+#define PWM_O_0_LOAD 0x00000050 // PWM0 Load
+#define PWM_O_0_COUNT 0x00000054 // PWM0 Counter
+#define PWM_O_0_CMPA 0x00000058 // PWM0 Compare A
+#define PWM_O_0_CMPB 0x0000005C // PWM0 Compare B
+#define PWM_O_0_GENA 0x00000060 // PWM0 Generator A Control
+#define PWM_O_0_GENB 0x00000064 // PWM0 Generator B Control
+#define PWM_O_0_DBCTL 0x00000068 // PWM0 Dead-Band Control
+#define PWM_O_0_DBRISE 0x0000006C // PWM0 Dead-Band Rising-Edge Delay
+#define PWM_O_0_DBFALL 0x00000070 // PWM0 Dead-Band
+ // Falling-Edge-Delay
+#define PWM_O_0_FLTSRC0 0x00000074 // PWM0 Fault Source 0
+#define PWM_O_0_FLTSRC1 0x00000078 // PWM0 Fault Source 1
+#define PWM_O_0_MINFLTPER 0x0000007C // PWM0 Minimum Fault Period
+#define PWM_O_1_CTL 0x00000080 // PWM1 Control
+#define PWM_O_1_INTEN 0x00000084 // PWM1 Interrupt and Trigger
+ // Enable
+#define PWM_O_1_RIS 0x00000088 // PWM1 Raw Interrupt Status
+#define PWM_O_1_ISC 0x0000008C // PWM1 Interrupt Status and Clear
+#define PWM_O_1_LOAD 0x00000090 // PWM1 Load
+#define PWM_O_1_COUNT 0x00000094 // PWM1 Counter
+#define PWM_O_1_CMPA 0x00000098 // PWM1 Compare A
+#define PWM_O_1_CMPB 0x0000009C // PWM1 Compare B
+#define PWM_O_1_GENA 0x000000A0 // PWM1 Generator A Control
+#define PWM_O_1_GENB 0x000000A4 // PWM1 Generator B Control
+#define PWM_O_1_DBCTL 0x000000A8 // PWM1 Dead-Band Control
+#define PWM_O_1_DBRISE 0x000000AC // PWM1 Dead-Band Rising-Edge Delay
+#define PWM_O_1_DBFALL 0x000000B0 // PWM1 Dead-Band
+ // Falling-Edge-Delay
+#define PWM_O_1_FLTSRC0 0x000000B4 // PWM1 Fault Source 0
+#define PWM_O_1_FLTSRC1 0x000000B8 // PWM1 Fault Source 1
+#define PWM_O_1_MINFLTPER 0x000000BC // PWM1 Minimum Fault Period
+#define PWM_O_2_CTL 0x000000C0 // PWM2 Control
+#define PWM_O_2_INTEN 0x000000C4 // PWM2 Interrupt and Trigger
+ // Enable
+#define PWM_O_2_RIS 0x000000C8 // PWM2 Raw Interrupt Status
+#define PWM_O_2_ISC 0x000000CC // PWM2 Interrupt Status and Clear
+#define PWM_O_2_LOAD 0x000000D0 // PWM2 Load
+#define PWM_O_2_COUNT 0x000000D4 // PWM2 Counter
+#define PWM_O_2_CMPA 0x000000D8 // PWM2 Compare A
+#define PWM_O_2_CMPB 0x000000DC // PWM2 Compare B
+#define PWM_O_2_GENA 0x000000E0 // PWM2 Generator A Control
+#define PWM_O_2_GENB 0x000000E4 // PWM2 Generator B Control
+#define PWM_O_2_DBCTL 0x000000E8 // PWM2 Dead-Band Control
+#define PWM_O_2_DBRISE 0x000000EC // PWM2 Dead-Band Rising-Edge Delay
+#define PWM_O_2_DBFALL 0x000000F0 // PWM2 Dead-Band
+ // Falling-Edge-Delay
+#define PWM_O_2_FLTSRC0 0x000000F4 // PWM2 Fault Source 0
+#define PWM_O_2_FLTSRC1 0x000000F8 // PWM2 Fault Source 1
+#define PWM_O_2_MINFLTPER 0x000000FC // PWM2 Minimum Fault Period
+#define PWM_O_3_CTL 0x00000100 // PWM3 Control
+#define PWM_O_3_INTEN 0x00000104 // PWM3 Interrupt and Trigger
+ // Enable
+#define PWM_O_3_RIS 0x00000108 // PWM3 Raw Interrupt Status
+#define PWM_O_3_ISC 0x0000010C // PWM3 Interrupt Status and Clear
+#define PWM_O_3_LOAD 0x00000110 // PWM3 Load
+#define PWM_O_3_COUNT 0x00000114 // PWM3 Counter
+#define PWM_O_3_CMPA 0x00000118 // PWM3 Compare A
+#define PWM_O_3_CMPB 0x0000011C // PWM3 Compare B
+#define PWM_O_3_GENA 0x00000120 // PWM3 Generator A Control
+#define PWM_O_3_GENB 0x00000124 // PWM3 Generator B Control
+#define PWM_O_3_DBCTL 0x00000128 // PWM3 Dead-Band Control
+#define PWM_O_3_DBRISE 0x0000012C // PWM3 Dead-Band Rising-Edge Delay
+#define PWM_O_3_DBFALL 0x00000130 // PWM3 Dead-Band
+ // Falling-Edge-Delay
+#define PWM_O_3_FLTSRC0 0x00000134 // PWM3 Fault Source 0
+#define PWM_O_3_FLTSRC1 0x00000138 // PWM3 Fault Source 1
+#define PWM_O_3_MINFLTPER 0x0000013C // PWM3 Minimum Fault Period
+#define PWM_O_0_FLTSEN 0x00000800 // PWM0 Fault Pin Logic Sense
+#define PWM_O_0_FLTSTAT0 0x00000804 // PWM0 Fault Status 0
+#define PWM_O_0_FLTSTAT1 0x00000808 // PWM0 Fault Status 1
+#define PWM_O_1_FLTSEN 0x00000880 // PWM1 Fault Pin Logic Sense
+#define PWM_O_1_FLTSTAT0 0x00000884 // PWM1 Fault Status 0
+#define PWM_O_1_FLTSTAT1 0x00000888 // PWM1 Fault Status 1
+#define PWM_O_2_FLTSEN 0x00000900 // PWM2 Fault Pin Logic Sense
+#define PWM_O_2_FLTSTAT0 0x00000904 // PWM2 Fault Status 0
+#define PWM_O_2_FLTSTAT1 0x00000908 // PWM2 Fault Status 1
+#define PWM_O_3_FLTSEN 0x00000980 // PWM3 Fault Pin Logic Sense
+#define PWM_O_3_FLTSTAT0 0x00000984 // PWM3 Fault Status 0
+#define PWM_O_3_FLTSTAT1 0x00000988 // PWM3 Fault Status 1
+#define PWM_O_PP 0x00000FC0 // PWM Peripheral Properties
+#define PWM_O_PC 0x00000FC4 // PWM Peripheral Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_CTL register.
+//
+//*****************************************************************************
+#define PWM_CTL_GLOBALSYNC3 0x00000008 // Update PWM Generator 3
+#define PWM_CTL_GLOBALSYNC2 0x00000004 // Update PWM Generator 2
+#define PWM_CTL_GLOBALSYNC1 0x00000002 // Update PWM Generator 1
+#define PWM_CTL_GLOBALSYNC0 0x00000001 // Update PWM Generator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_SYNC register.
+//
+//*****************************************************************************
+#define PWM_SYNC_SYNC3 0x00000008 // Reset Generator 3 Counter
+#define PWM_SYNC_SYNC2 0x00000004 // Reset Generator 2 Counter
+#define PWM_SYNC_SYNC1 0x00000002 // Reset Generator 1 Counter
+#define PWM_SYNC_SYNC0 0x00000001 // Reset Generator 0 Counter
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ENABLE register.
+//
+//*****************************************************************************
+#define PWM_ENABLE_PWM7EN 0x00000080 // PWM7 Output Enable
+#define PWM_ENABLE_PWM6EN 0x00000040 // PWM6 Output Enable
+#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 Output Enable
+#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 Output Enable
+#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 Output Enable
+#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 Output Enable
+#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 Output Enable
+#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 Output Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_INVERT register.
+//
+//*****************************************************************************
+#define PWM_INVERT_PWM7INV 0x00000080 // Invert PWM7 Signal
+#define PWM_INVERT_PWM6INV 0x00000040 // Invert PWM6 Signal
+#define PWM_INVERT_PWM5INV 0x00000020 // Invert PWM5 Signal
+#define PWM_INVERT_PWM4INV 0x00000010 // Invert PWM4 Signal
+#define PWM_INVERT_PWM3INV 0x00000008 // Invert PWM3 Signal
+#define PWM_INVERT_PWM2INV 0x00000004 // Invert PWM2 Signal
+#define PWM_INVERT_PWM1INV 0x00000002 // Invert PWM1 Signal
+#define PWM_INVERT_PWM0INV 0x00000001 // Invert PWM0 Signal
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_FAULT register.
+//
+//*****************************************************************************
+#define PWM_FAULT_FAULT7 0x00000080 // PWM7 Fault
+#define PWM_FAULT_FAULT6 0x00000040 // PWM6 Fault
+#define PWM_FAULT_FAULT5 0x00000020 // PWM5 Fault
+#define PWM_FAULT_FAULT4 0x00000010 // PWM4 Fault
+#define PWM_FAULT_FAULT3 0x00000008 // PWM3 Fault
+#define PWM_FAULT_FAULT2 0x00000004 // PWM2 Fault
+#define PWM_FAULT_FAULT1 0x00000002 // PWM1 Fault
+#define PWM_FAULT_FAULT0 0x00000001 // PWM0 Fault
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_INTEN register.
+//
+//*****************************************************************************
+#define PWM_INTEN_INTFAULT3 0x00080000 // Interrupt Fault 3
+#define PWM_INTEN_INTFAULT2 0x00040000 // Interrupt Fault 2
+#define PWM_INTEN_INTFAULT1 0x00020000 // Interrupt Fault 1
+#define PWM_INTEN_INTFAULT 0x00010000 // Fault Interrupt Enable
+#define PWM_INTEN_INTFAULT0 0x00010000 // Interrupt Fault 0
+#define PWM_INTEN_INTPWM3 0x00000008 // PWM3 Interrupt Enable
+#define PWM_INTEN_INTPWM2 0x00000004 // PWM2 Interrupt Enable
+#define PWM_INTEN_INTPWM1 0x00000002 // PWM1 Interrupt Enable
+#define PWM_INTEN_INTPWM0 0x00000001 // PWM0 Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_RIS register.
+//
+//*****************************************************************************
+#define PWM_RIS_INTFAULT3 0x00080000 // Interrupt Fault PWM 3
+#define PWM_RIS_INTFAULT2 0x00040000 // Interrupt Fault PWM 2
+#define PWM_RIS_INTFAULT1 0x00020000 // Interrupt Fault PWM 1
+#define PWM_RIS_INTFAULT0 0x00010000 // Interrupt Fault PWM 0
+#define PWM_RIS_INTFAULT 0x00010000 // Fault Interrupt Asserted
+#define PWM_RIS_INTPWM3 0x00000008 // PWM3 Interrupt Asserted
+#define PWM_RIS_INTPWM2 0x00000004 // PWM2 Interrupt Asserted
+#define PWM_RIS_INTPWM1 0x00000002 // PWM1 Interrupt Asserted
+#define PWM_RIS_INTPWM0 0x00000001 // PWM0 Interrupt Asserted
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ISC register.
+//
+//*****************************************************************************
+#define PWM_ISC_INTFAULT3 0x00080000 // FAULT3 Interrupt Asserted
+#define PWM_ISC_INTFAULT2 0x00040000 // FAULT2 Interrupt Asserted
+#define PWM_ISC_INTFAULT1 0x00020000 // FAULT1 Interrupt Asserted
+#define PWM_ISC_INTFAULT 0x00010000 // Fault Interrupt Asserted
+#define PWM_ISC_INTFAULT0 0x00010000 // FAULT0 Interrupt Asserted
+#define PWM_ISC_INTPWM3 0x00000008 // PWM3 Interrupt Status
+#define PWM_ISC_INTPWM2 0x00000004 // PWM2 Interrupt Status
+#define PWM_ISC_INTPWM1 0x00000002 // PWM1 Interrupt Status
+#define PWM_ISC_INTPWM0 0x00000001 // PWM0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_STATUS register.
+//
+//*****************************************************************************
+#define PWM_STATUS_FAULT3 0x00000008 // Generator 3 Fault Status
+#define PWM_STATUS_FAULT2 0x00000004 // Generator 2 Fault Status
+#define PWM_STATUS_FAULT1 0x00000002 // Generator 1 Fault Status
+#define PWM_STATUS_FAULT0 0x00000001 // Generator 0 Fault Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_FAULTVAL register.
+//
+//*****************************************************************************
+#define PWM_FAULTVAL_PWM7 0x00000080 // PWM7 Fault Value
+#define PWM_FAULTVAL_PWM6 0x00000040 // PWM6 Fault Value
+#define PWM_FAULTVAL_PWM5 0x00000020 // PWM5 Fault Value
+#define PWM_FAULTVAL_PWM4 0x00000010 // PWM4 Fault Value
+#define PWM_FAULTVAL_PWM3 0x00000008 // PWM3 Fault Value
+#define PWM_FAULTVAL_PWM2 0x00000004 // PWM2 Fault Value
+#define PWM_FAULTVAL_PWM1 0x00000002 // PWM1 Fault Value
+#define PWM_FAULTVAL_PWM0 0x00000001 // PWM0 Fault Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ENUPD register.
+//
+//*****************************************************************************
+#define PWM_ENUPD_ENUPD7_M 0x0000C000 // PWM7 Enable Update Mode
+#define PWM_ENUPD_ENUPD7_IMM 0x00000000 // Immediate
+#define PWM_ENUPD_ENUPD7_LSYNC 0x00008000 // Locally Synchronized
+#define PWM_ENUPD_ENUPD7_GSYNC 0x0000C000 // Globally Synchronized
+#define PWM_ENUPD_ENUPD6_M 0x00003000 // PWM6 Enable Update Mode
+#define PWM_ENUPD_ENUPD6_IMM 0x00000000 // Immediate
+#define PWM_ENUPD_ENUPD6_LSYNC 0x00002000 // Locally Synchronized
+#define PWM_ENUPD_ENUPD6_GSYNC 0x00003000 // Globally Synchronized
+#define PWM_ENUPD_ENUPD5_M 0x00000C00 // PWM5 Enable Update Mode
+#define PWM_ENUPD_ENUPD5_IMM 0x00000000 // Immediate
+#define PWM_ENUPD_ENUPD5_LSYNC 0x00000800 // Locally Synchronized
+#define PWM_ENUPD_ENUPD5_GSYNC 0x00000C00 // Globally Synchronized
+#define PWM_ENUPD_ENUPD4_M 0x00000300 // PWM4 Enable Update Mode
+#define PWM_ENUPD_ENUPD4_IMM 0x00000000 // Immediate
+#define PWM_ENUPD_ENUPD4_LSYNC 0x00000200 // Locally Synchronized
+#define PWM_ENUPD_ENUPD4_GSYNC 0x00000300 // Globally Synchronized
+#define PWM_ENUPD_ENUPD3_M 0x000000C0 // PWM3 Enable Update Mode
+#define PWM_ENUPD_ENUPD3_IMM 0x00000000 // Immediate
+#define PWM_ENUPD_ENUPD3_LSYNC 0x00000080 // Locally Synchronized
+#define PWM_ENUPD_ENUPD3_GSYNC 0x000000C0 // Globally Synchronized
+#define PWM_ENUPD_ENUPD2_M 0x00000030 // PWM2 Enable Update Mode
+#define PWM_ENUPD_ENUPD2_IMM 0x00000000 // Immediate
+#define PWM_ENUPD_ENUPD2_LSYNC 0x00000020 // Locally Synchronized
+#define PWM_ENUPD_ENUPD2_GSYNC 0x00000030 // Globally Synchronized
+#define PWM_ENUPD_ENUPD1_M 0x0000000C // PWM1 Enable Update Mode
+#define PWM_ENUPD_ENUPD1_IMM 0x00000000 // Immediate
+#define PWM_ENUPD_ENUPD1_LSYNC 0x00000008 // Locally Synchronized
+#define PWM_ENUPD_ENUPD1_GSYNC 0x0000000C // Globally Synchronized
+#define PWM_ENUPD_ENUPD0_M 0x00000003 // PWM0 Enable Update Mode
+#define PWM_ENUPD_ENUPD0_IMM 0x00000000 // Immediate
+#define PWM_ENUPD_ENUPD0_LSYNC 0x00000002 // Locally Synchronized
+#define PWM_ENUPD_ENUPD0_GSYNC 0x00000003 // Globally Synchronized
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_CTL register.
+//
+//*****************************************************************************
+#define PWM_0_CTL_LATCH 0x00040000 // Latch Fault Input
+#define PWM_0_CTL_MINFLTPER 0x00020000 // Minimum Fault Period
+#define PWM_0_CTL_FLTSRC 0x00010000 // Fault Condition Source
+#define PWM_0_CTL_DBFALLUPD_M 0x0000C000 // Specifies the update mode for
+ // the PWMnDBFALL register
+#define PWM_0_CTL_DBFALLUPD_I 0x00000000 // Immediate
+#define PWM_0_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized
+#define PWM_0_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized
+#define PWM_0_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode
+#define PWM_0_CTL_DBRISEUPD_I 0x00000000 // Immediate
+#define PWM_0_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized
+#define PWM_0_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized
+#define PWM_0_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode
+#define PWM_0_CTL_DBCTLUPD_I 0x00000000 // Immediate
+#define PWM_0_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized
+#define PWM_0_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized
+#define PWM_0_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode
+#define PWM_0_CTL_GENBUPD_I 0x00000000 // Immediate
+#define PWM_0_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized
+#define PWM_0_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized
+#define PWM_0_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode
+#define PWM_0_CTL_GENAUPD_I 0x00000000 // Immediate
+#define PWM_0_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized
+#define PWM_0_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized
+#define PWM_0_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode
+#define PWM_0_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode
+#define PWM_0_CTL_LOADUPD 0x00000008 // Load Register Update Mode
+#define PWM_0_CTL_DEBUG 0x00000004 // Debug Mode
+#define PWM_0_CTL_MODE 0x00000002 // Counter Mode
+#define PWM_0_CTL_ENABLE 0x00000001 // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_INTEN register.
+//
+//*****************************************************************************
+#define PWM_0_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=Comparator B
+ // Down
+#define PWM_0_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=Comparator B
+ // Up
+#define PWM_0_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=Comparator A
+ // Down
+#define PWM_0_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=Comparator A
+ // Up
+#define PWM_0_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=Load
+#define PWM_0_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0
+#define PWM_0_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=Comparator
+ // B Down
+#define PWM_0_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=Comparator
+ // B Up
+#define PWM_0_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=Comparator
+ // A Down
+#define PWM_0_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=Comparator
+ // A Up
+#define PWM_0_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=Load
+#define PWM_0_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_RIS register.
+//
+//*****************************************************************************
+#define PWM_0_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+ // Status
+#define PWM_0_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status
+#define PWM_0_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+ // Status
+#define PWM_0_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status
+#define PWM_0_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status
+#define PWM_0_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_ISC register.
+//
+//*****************************************************************************
+#define PWM_0_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+#define PWM_0_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt
+#define PWM_0_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+#define PWM_0_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt
+#define PWM_0_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt
+#define PWM_0_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_LOAD register.
+//
+//*****************************************************************************
+#define PWM_0_LOAD_M 0x0000FFFF // Counter Load Value
+#define PWM_0_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_COUNT register.
+//
+//*****************************************************************************
+#define PWM_0_COUNT_M 0x0000FFFF // Counter Value
+#define PWM_0_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_CMPA register.
+//
+//*****************************************************************************
+#define PWM_0_CMPA_M 0x0000FFFF // Comparator A Value
+#define PWM_0_CMPA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_CMPB register.
+//
+//*****************************************************************************
+#define PWM_0_CMPB_M 0x0000FFFF // Comparator B Value
+#define PWM_0_CMPB_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_GENA register.
+//
+//*****************************************************************************
+#define PWM_0_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_0_GENA_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_0_GENA_ACTCMPBD_INV 0x00000400 // Invert the output signal
+#define PWM_0_GENA_ACTCMPBD_ZERO \
+ 0x00000800 // Set the output signal to 0
+#define PWM_0_GENA_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1
+#define PWM_0_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_0_GENA_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_0_GENA_ACTCMPBU_INV 0x00000100 // Invert the output signal
+#define PWM_0_GENA_ACTCMPBU_ZERO \
+ 0x00000200 // Set the output signal to 0
+#define PWM_0_GENA_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1
+#define PWM_0_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_0_GENA_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_0_GENA_ACTCMPAD_INV 0x00000040 // Invert the output signal
+#define PWM_0_GENA_ACTCMPAD_ZERO \
+ 0x00000080 // Set the output signal to 0
+#define PWM_0_GENA_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1
+#define PWM_0_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_0_GENA_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_0_GENA_ACTCMPAU_INV 0x00000010 // Invert the output signal
+#define PWM_0_GENA_ACTCMPAU_ZERO \
+ 0x00000020 // Set the output signal to 0
+#define PWM_0_GENA_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1
+#define PWM_0_GENA_ACTLOAD_M 0x0000000C // Action for Counter=Load
+#define PWM_0_GENA_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_0_GENA_ACTLOAD_INV 0x00000004 // Invert the output signal
+#define PWM_0_GENA_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0
+#define PWM_0_GENA_ACTLOAD_ONE 0x0000000C // Set the output signal to 1
+#define PWM_0_GENA_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_0_GENA_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_0_GENA_ACTZERO_INV 0x00000001 // Invert the output signal
+#define PWM_0_GENA_ACTZERO_ZERO 0x00000002 // Set the output signal to 0
+#define PWM_0_GENA_ACTZERO_ONE 0x00000003 // Set the output signal to 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_GENB register.
+//
+//*****************************************************************************
+#define PWM_0_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_0_GENB_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_0_GENB_ACTCMPBD_INV 0x00000400 // Invert the output signal
+#define PWM_0_GENB_ACTCMPBD_ZERO \
+ 0x00000800 // Set the output signal to 0
+#define PWM_0_GENB_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1
+#define PWM_0_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_0_GENB_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_0_GENB_ACTCMPBU_INV 0x00000100 // Invert the output signal
+#define PWM_0_GENB_ACTCMPBU_ZERO \
+ 0x00000200 // Set the output signal to 0
+#define PWM_0_GENB_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1
+#define PWM_0_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_0_GENB_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_0_GENB_ACTCMPAD_INV 0x00000040 // Invert the output signal
+#define PWM_0_GENB_ACTCMPAD_ZERO \
+ 0x00000080 // Set the output signal to 0
+#define PWM_0_GENB_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1
+#define PWM_0_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_0_GENB_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_0_GENB_ACTCMPAU_INV 0x00000010 // Invert the output signal
+#define PWM_0_GENB_ACTCMPAU_ZERO \
+ 0x00000020 // Set the output signal to 0
+#define PWM_0_GENB_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1
+#define PWM_0_GENB_ACTLOAD_M 0x0000000C // Action for Counter=Load
+#define PWM_0_GENB_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_0_GENB_ACTLOAD_INV 0x00000004 // Invert the output signal
+#define PWM_0_GENB_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0
+#define PWM_0_GENB_ACTLOAD_ONE 0x0000000C // Set the output signal to 1
+#define PWM_0_GENB_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_0_GENB_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_0_GENB_ACTZERO_INV 0x00000001 // Invert the output signal
+#define PWM_0_GENB_ACTZERO_ZERO 0x00000002 // Set the output signal to 0
+#define PWM_0_GENB_ACTZERO_ONE 0x00000003 // Set the output signal to 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_0_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_0_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay
+#define PWM_0_DBRISE_DELAY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_0_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay
+#define PWM_0_DBFALL_DELAY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_0_FLTSRC0_FAULT3 0x00000008 // Fault3 Input
+#define PWM_0_FLTSRC0_FAULT2 0x00000004 // Fault2 Input
+#define PWM_0_FLTSRC0_FAULT1 0x00000002 // Fault1 Input
+#define PWM_0_FLTSRC0_FAULT0 0x00000001 // Fault0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_0_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7
+#define PWM_0_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6
+#define PWM_0_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5
+#define PWM_0_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4
+#define PWM_0_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3
+#define PWM_0_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2
+#define PWM_0_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1
+#define PWM_0_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_0_MINFLTPER_M 0x0000FFFF // Minimum Fault Period
+#define PWM_0_MINFLTPER_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_CTL register.
+//
+//*****************************************************************************
+#define PWM_1_CTL_LATCH 0x00040000 // Latch Fault Input
+#define PWM_1_CTL_MINFLTPER 0x00020000 // Minimum Fault Period
+#define PWM_1_CTL_FLTSRC 0x00010000 // Fault Condition Source
+#define PWM_1_CTL_DBFALLUPD_M 0x0000C000 // Specifies the update mode for
+ // the PWMnDBFALL register
+#define PWM_1_CTL_DBFALLUPD_I 0x00000000 // Immediate
+#define PWM_1_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized
+#define PWM_1_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized
+#define PWM_1_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode
+#define PWM_1_CTL_DBRISEUPD_I 0x00000000 // Immediate
+#define PWM_1_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized
+#define PWM_1_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized
+#define PWM_1_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode
+#define PWM_1_CTL_DBCTLUPD_I 0x00000000 // Immediate
+#define PWM_1_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized
+#define PWM_1_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized
+#define PWM_1_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode
+#define PWM_1_CTL_GENBUPD_I 0x00000000 // Immediate
+#define PWM_1_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized
+#define PWM_1_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized
+#define PWM_1_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode
+#define PWM_1_CTL_GENAUPD_I 0x00000000 // Immediate
+#define PWM_1_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized
+#define PWM_1_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized
+#define PWM_1_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode
+#define PWM_1_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode
+#define PWM_1_CTL_LOADUPD 0x00000008 // Load Register Update Mode
+#define PWM_1_CTL_DEBUG 0x00000004 // Debug Mode
+#define PWM_1_CTL_MODE 0x00000002 // Counter Mode
+#define PWM_1_CTL_ENABLE 0x00000001 // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_INTEN register.
+//
+//*****************************************************************************
+#define PWM_1_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=Comparator B
+ // Down
+#define PWM_1_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=Comparator B
+ // Up
+#define PWM_1_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=Comparator A
+ // Down
+#define PWM_1_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=Comparator A
+ // Up
+#define PWM_1_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=Load
+#define PWM_1_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0
+#define PWM_1_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=Comparator
+ // B Down
+#define PWM_1_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=Comparator
+ // B Up
+#define PWM_1_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=Comparator
+ // A Down
+#define PWM_1_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=Comparator
+ // A Up
+#define PWM_1_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=Load
+#define PWM_1_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_RIS register.
+//
+//*****************************************************************************
+#define PWM_1_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+ // Status
+#define PWM_1_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status
+#define PWM_1_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+ // Status
+#define PWM_1_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status
+#define PWM_1_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status
+#define PWM_1_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_ISC register.
+//
+//*****************************************************************************
+#define PWM_1_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+#define PWM_1_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt
+#define PWM_1_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+#define PWM_1_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt
+#define PWM_1_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt
+#define PWM_1_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_LOAD register.
+//
+//*****************************************************************************
+#define PWM_1_LOAD_LOAD_M 0x0000FFFF // Counter Load Value
+#define PWM_1_LOAD_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_COUNT register.
+//
+//*****************************************************************************
+#define PWM_1_COUNT_COUNT_M 0x0000FFFF // Counter Value
+#define PWM_1_COUNT_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_CMPA register.
+//
+//*****************************************************************************
+#define PWM_1_CMPA_COMPA_M 0x0000FFFF // Comparator A Value
+#define PWM_1_CMPA_COMPA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_CMPB register.
+//
+//*****************************************************************************
+#define PWM_1_CMPB_COMPB_M 0x0000FFFF // Comparator B Value
+#define PWM_1_CMPB_COMPB_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_GENA register.
+//
+//*****************************************************************************
+#define PWM_1_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_1_GENA_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_1_GENA_ACTCMPBD_INV 0x00000400 // Invert the output signal
+#define PWM_1_GENA_ACTCMPBD_ZERO \
+ 0x00000800 // Set the output signal to 0
+#define PWM_1_GENA_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1
+#define PWM_1_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_1_GENA_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_1_GENA_ACTCMPBU_INV 0x00000100 // Invert the output signal
+#define PWM_1_GENA_ACTCMPBU_ZERO \
+ 0x00000200 // Set the output signal to 0
+#define PWM_1_GENA_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1
+#define PWM_1_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_1_GENA_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_1_GENA_ACTCMPAD_INV 0x00000040 // Invert the output signal
+#define PWM_1_GENA_ACTCMPAD_ZERO \
+ 0x00000080 // Set the output signal to 0
+#define PWM_1_GENA_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1
+#define PWM_1_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_1_GENA_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_1_GENA_ACTCMPAU_INV 0x00000010 // Invert the output signal
+#define PWM_1_GENA_ACTCMPAU_ZERO \
+ 0x00000020 // Set the output signal to 0
+#define PWM_1_GENA_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1
+#define PWM_1_GENA_ACTLOAD_M 0x0000000C // Action for Counter=Load
+#define PWM_1_GENA_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_1_GENA_ACTLOAD_INV 0x00000004 // Invert the output signal
+#define PWM_1_GENA_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0
+#define PWM_1_GENA_ACTLOAD_ONE 0x0000000C // Set the output signal to 1
+#define PWM_1_GENA_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_1_GENA_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_1_GENA_ACTZERO_INV 0x00000001 // Invert the output signal
+#define PWM_1_GENA_ACTZERO_ZERO 0x00000002 // Set the output signal to 0
+#define PWM_1_GENA_ACTZERO_ONE 0x00000003 // Set the output signal to 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_GENB register.
+//
+//*****************************************************************************
+#define PWM_1_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_1_GENB_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_1_GENB_ACTCMPBD_INV 0x00000400 // Invert the output signal
+#define PWM_1_GENB_ACTCMPBD_ZERO \
+ 0x00000800 // Set the output signal to 0
+#define PWM_1_GENB_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1
+#define PWM_1_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_1_GENB_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_1_GENB_ACTCMPBU_INV 0x00000100 // Invert the output signal
+#define PWM_1_GENB_ACTCMPBU_ZERO \
+ 0x00000200 // Set the output signal to 0
+#define PWM_1_GENB_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1
+#define PWM_1_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_1_GENB_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_1_GENB_ACTCMPAD_INV 0x00000040 // Invert the output signal
+#define PWM_1_GENB_ACTCMPAD_ZERO \
+ 0x00000080 // Set the output signal to 0
+#define PWM_1_GENB_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1
+#define PWM_1_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_1_GENB_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_1_GENB_ACTCMPAU_INV 0x00000010 // Invert the output signal
+#define PWM_1_GENB_ACTCMPAU_ZERO \
+ 0x00000020 // Set the output signal to 0
+#define PWM_1_GENB_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1
+#define PWM_1_GENB_ACTLOAD_M 0x0000000C // Action for Counter=Load
+#define PWM_1_GENB_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_1_GENB_ACTLOAD_INV 0x00000004 // Invert the output signal
+#define PWM_1_GENB_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0
+#define PWM_1_GENB_ACTLOAD_ONE 0x0000000C // Set the output signal to 1
+#define PWM_1_GENB_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_1_GENB_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_1_GENB_ACTZERO_INV 0x00000001 // Invert the output signal
+#define PWM_1_GENB_ACTZERO_ZERO 0x00000002 // Set the output signal to 0
+#define PWM_1_GENB_ACTZERO_ONE 0x00000003 // Set the output signal to 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_1_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_1_DBRISE_RISEDELAY_M \
+ 0x00000FFF // Dead-Band Rise Delay
+#define PWM_1_DBRISE_RISEDELAY_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_1_DBFALL_FALLDELAY_M \
+ 0x00000FFF // Dead-Band Fall Delay
+#define PWM_1_DBFALL_FALLDELAY_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_1_FLTSRC0_FAULT3 0x00000008 // Fault3 Input
+#define PWM_1_FLTSRC0_FAULT2 0x00000004 // Fault2 Input
+#define PWM_1_FLTSRC0_FAULT1 0x00000002 // Fault1 Input
+#define PWM_1_FLTSRC0_FAULT0 0x00000001 // Fault0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_1_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7
+#define PWM_1_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6
+#define PWM_1_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5
+#define PWM_1_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4
+#define PWM_1_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3
+#define PWM_1_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2
+#define PWM_1_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1
+#define PWM_1_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_1_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period
+#define PWM_1_MINFLTPER_MFP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_CTL register.
+//
+//*****************************************************************************
+#define PWM_2_CTL_LATCH 0x00040000 // Latch Fault Input
+#define PWM_2_CTL_MINFLTPER 0x00020000 // Minimum Fault Period
+#define PWM_2_CTL_FLTSRC 0x00010000 // Fault Condition Source
+#define PWM_2_CTL_DBFALLUPD_M 0x0000C000 // Specifies the update mode for
+ // the PWMnDBFALL register
+#define PWM_2_CTL_DBFALLUPD_I 0x00000000 // Immediate
+#define PWM_2_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized
+#define PWM_2_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized
+#define PWM_2_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode
+#define PWM_2_CTL_DBRISEUPD_I 0x00000000 // Immediate
+#define PWM_2_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized
+#define PWM_2_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized
+#define PWM_2_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode
+#define PWM_2_CTL_DBCTLUPD_I 0x00000000 // Immediate
+#define PWM_2_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized
+#define PWM_2_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized
+#define PWM_2_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode
+#define PWM_2_CTL_GENBUPD_I 0x00000000 // Immediate
+#define PWM_2_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized
+#define PWM_2_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized
+#define PWM_2_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode
+#define PWM_2_CTL_GENAUPD_I 0x00000000 // Immediate
+#define PWM_2_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized
+#define PWM_2_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized
+#define PWM_2_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode
+#define PWM_2_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode
+#define PWM_2_CTL_LOADUPD 0x00000008 // Load Register Update Mode
+#define PWM_2_CTL_DEBUG 0x00000004 // Debug Mode
+#define PWM_2_CTL_MODE 0x00000002 // Counter Mode
+#define PWM_2_CTL_ENABLE 0x00000001 // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_INTEN register.
+//
+//*****************************************************************************
+#define PWM_2_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=Comparator B
+ // Down
+#define PWM_2_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=Comparator B
+ // Up
+#define PWM_2_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=Comparator A
+ // Down
+#define PWM_2_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=Comparator A
+ // Up
+#define PWM_2_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=Load
+#define PWM_2_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0
+#define PWM_2_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=Comparator
+ // B Down
+#define PWM_2_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=Comparator
+ // B Up
+#define PWM_2_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=Comparator
+ // A Down
+#define PWM_2_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=Comparator
+ // A Up
+#define PWM_2_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=Load
+#define PWM_2_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_RIS register.
+//
+//*****************************************************************************
+#define PWM_2_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+ // Status
+#define PWM_2_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status
+#define PWM_2_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+ // Status
+#define PWM_2_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status
+#define PWM_2_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status
+#define PWM_2_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_ISC register.
+//
+//*****************************************************************************
+#define PWM_2_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+#define PWM_2_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt
+#define PWM_2_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+#define PWM_2_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt
+#define PWM_2_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt
+#define PWM_2_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_LOAD register.
+//
+//*****************************************************************************
+#define PWM_2_LOAD_LOAD_M 0x0000FFFF // Counter Load Value
+#define PWM_2_LOAD_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_COUNT register.
+//
+//*****************************************************************************
+#define PWM_2_COUNT_COUNT_M 0x0000FFFF // Counter Value
+#define PWM_2_COUNT_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_CMPA register.
+//
+//*****************************************************************************
+#define PWM_2_CMPA_COMPA_M 0x0000FFFF // Comparator A Value
+#define PWM_2_CMPA_COMPA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_CMPB register.
+//
+//*****************************************************************************
+#define PWM_2_CMPB_COMPB_M 0x0000FFFF // Comparator B Value
+#define PWM_2_CMPB_COMPB_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_GENA register.
+//
+//*****************************************************************************
+#define PWM_2_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_2_GENA_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_2_GENA_ACTCMPBD_INV 0x00000400 // Invert the output signal
+#define PWM_2_GENA_ACTCMPBD_ZERO \
+ 0x00000800 // Set the output signal to 0
+#define PWM_2_GENA_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1
+#define PWM_2_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_2_GENA_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_2_GENA_ACTCMPBU_INV 0x00000100 // Invert the output signal
+#define PWM_2_GENA_ACTCMPBU_ZERO \
+ 0x00000200 // Set the output signal to 0
+#define PWM_2_GENA_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1
+#define PWM_2_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_2_GENA_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_2_GENA_ACTCMPAD_INV 0x00000040 // Invert the output signal
+#define PWM_2_GENA_ACTCMPAD_ZERO \
+ 0x00000080 // Set the output signal to 0
+#define PWM_2_GENA_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1
+#define PWM_2_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_2_GENA_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_2_GENA_ACTCMPAU_INV 0x00000010 // Invert the output signal
+#define PWM_2_GENA_ACTCMPAU_ZERO \
+ 0x00000020 // Set the output signal to 0
+#define PWM_2_GENA_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1
+#define PWM_2_GENA_ACTLOAD_M 0x0000000C // Action for Counter=Load
+#define PWM_2_GENA_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_2_GENA_ACTLOAD_INV 0x00000004 // Invert the output signal
+#define PWM_2_GENA_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0
+#define PWM_2_GENA_ACTLOAD_ONE 0x0000000C // Set the output signal to 1
+#define PWM_2_GENA_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_2_GENA_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_2_GENA_ACTZERO_INV 0x00000001 // Invert the output signal
+#define PWM_2_GENA_ACTZERO_ZERO 0x00000002 // Set the output signal to 0
+#define PWM_2_GENA_ACTZERO_ONE 0x00000003 // Set the output signal to 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_GENB register.
+//
+//*****************************************************************************
+#define PWM_2_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_2_GENB_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_2_GENB_ACTCMPBD_INV 0x00000400 // Invert the output signal
+#define PWM_2_GENB_ACTCMPBD_ZERO \
+ 0x00000800 // Set the output signal to 0
+#define PWM_2_GENB_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1
+#define PWM_2_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_2_GENB_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_2_GENB_ACTCMPBU_INV 0x00000100 // Invert the output signal
+#define PWM_2_GENB_ACTCMPBU_ZERO \
+ 0x00000200 // Set the output signal to 0
+#define PWM_2_GENB_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1
+#define PWM_2_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_2_GENB_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_2_GENB_ACTCMPAD_INV 0x00000040 // Invert the output signal
+#define PWM_2_GENB_ACTCMPAD_ZERO \
+ 0x00000080 // Set the output signal to 0
+#define PWM_2_GENB_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1
+#define PWM_2_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_2_GENB_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_2_GENB_ACTCMPAU_INV 0x00000010 // Invert the output signal
+#define PWM_2_GENB_ACTCMPAU_ZERO \
+ 0x00000020 // Set the output signal to 0
+#define PWM_2_GENB_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1
+#define PWM_2_GENB_ACTLOAD_M 0x0000000C // Action for Counter=Load
+#define PWM_2_GENB_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_2_GENB_ACTLOAD_INV 0x00000004 // Invert the output signal
+#define PWM_2_GENB_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0
+#define PWM_2_GENB_ACTLOAD_ONE 0x0000000C // Set the output signal to 1
+#define PWM_2_GENB_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_2_GENB_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_2_GENB_ACTZERO_INV 0x00000001 // Invert the output signal
+#define PWM_2_GENB_ACTZERO_ZERO 0x00000002 // Set the output signal to 0
+#define PWM_2_GENB_ACTZERO_ONE 0x00000003 // Set the output signal to 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_2_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_2_DBRISE_RISEDELAY_M \
+ 0x00000FFF // Dead-Band Rise Delay
+#define PWM_2_DBRISE_RISEDELAY_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_2_DBFALL_FALLDELAY_M \
+ 0x00000FFF // Dead-Band Fall Delay
+#define PWM_2_DBFALL_FALLDELAY_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_2_FLTSRC0_FAULT3 0x00000008 // Fault3 Input
+#define PWM_2_FLTSRC0_FAULT2 0x00000004 // Fault2 Input
+#define PWM_2_FLTSRC0_FAULT1 0x00000002 // Fault1 Input
+#define PWM_2_FLTSRC0_FAULT0 0x00000001 // Fault0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_2_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7
+#define PWM_2_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6
+#define PWM_2_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5
+#define PWM_2_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4
+#define PWM_2_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3
+#define PWM_2_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2
+#define PWM_2_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1
+#define PWM_2_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_2_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period
+#define PWM_2_MINFLTPER_MFP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_CTL register.
+//
+//*****************************************************************************
+#define PWM_3_CTL_LATCH 0x00040000 // Latch Fault Input
+#define PWM_3_CTL_MINFLTPER 0x00020000 // Minimum Fault Period
+#define PWM_3_CTL_FLTSRC 0x00010000 // Fault Condition Source
+#define PWM_3_CTL_DBFALLUPD_M 0x0000C000 // Specifies the update mode for
+ // the PWMnDBFALL register
+#define PWM_3_CTL_DBFALLUPD_I 0x00000000 // Immediate
+#define PWM_3_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized
+#define PWM_3_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized
+#define PWM_3_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode
+#define PWM_3_CTL_DBRISEUPD_I 0x00000000 // Immediate
+#define PWM_3_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized
+#define PWM_3_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized
+#define PWM_3_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode
+#define PWM_3_CTL_DBCTLUPD_I 0x00000000 // Immediate
+#define PWM_3_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized
+#define PWM_3_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized
+#define PWM_3_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode
+#define PWM_3_CTL_GENBUPD_I 0x00000000 // Immediate
+#define PWM_3_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized
+#define PWM_3_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized
+#define PWM_3_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode
+#define PWM_3_CTL_GENAUPD_I 0x00000000 // Immediate
+#define PWM_3_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized
+#define PWM_3_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized
+#define PWM_3_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode
+#define PWM_3_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode
+#define PWM_3_CTL_LOADUPD 0x00000008 // Load Register Update Mode
+#define PWM_3_CTL_DEBUG 0x00000004 // Debug Mode
+#define PWM_3_CTL_MODE 0x00000002 // Counter Mode
+#define PWM_3_CTL_ENABLE 0x00000001 // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_INTEN register.
+//
+//*****************************************************************************
+#define PWM_3_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=Comparator B
+ // Down
+#define PWM_3_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=Comparator B
+ // Up
+#define PWM_3_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=Comparator A
+ // Down
+#define PWM_3_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=Comparator A
+ // Up
+#define PWM_3_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=Load
+#define PWM_3_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0
+#define PWM_3_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=Comparator
+ // B Down
+#define PWM_3_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=Comparator
+ // B Up
+#define PWM_3_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=Comparator
+ // A Down
+#define PWM_3_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=Comparator
+ // A Up
+#define PWM_3_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=Load
+#define PWM_3_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_RIS register.
+//
+//*****************************************************************************
+#define PWM_3_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+ // Status
+#define PWM_3_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status
+#define PWM_3_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+ // Status
+#define PWM_3_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status
+#define PWM_3_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status
+#define PWM_3_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_ISC register.
+//
+//*****************************************************************************
+#define PWM_3_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+#define PWM_3_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt
+#define PWM_3_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+#define PWM_3_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt
+#define PWM_3_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt
+#define PWM_3_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_LOAD register.
+//
+//*****************************************************************************
+#define PWM_3_LOAD_LOAD_M 0x0000FFFF // Counter Load Value
+#define PWM_3_LOAD_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_COUNT register.
+//
+//*****************************************************************************
+#define PWM_3_COUNT_COUNT_M 0x0000FFFF // Counter Value
+#define PWM_3_COUNT_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_CMPA register.
+//
+//*****************************************************************************
+#define PWM_3_CMPA_COMPA_M 0x0000FFFF // Comparator A Value
+#define PWM_3_CMPA_COMPA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_CMPB register.
+//
+//*****************************************************************************
+#define PWM_3_CMPB_COMPB_M 0x0000FFFF // Comparator B Value
+#define PWM_3_CMPB_COMPB_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_GENA register.
+//
+//*****************************************************************************
+#define PWM_3_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_3_GENA_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_3_GENA_ACTCMPBD_INV 0x00000400 // Invert the output signal
+#define PWM_3_GENA_ACTCMPBD_ZERO \
+ 0x00000800 // Set the output signal to 0
+#define PWM_3_GENA_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1
+#define PWM_3_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_3_GENA_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_3_GENA_ACTCMPBU_INV 0x00000100 // Invert the output signal
+#define PWM_3_GENA_ACTCMPBU_ZERO \
+ 0x00000200 // Set the output signal to 0
+#define PWM_3_GENA_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1
+#define PWM_3_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_3_GENA_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_3_GENA_ACTCMPAD_INV 0x00000040 // Invert the output signal
+#define PWM_3_GENA_ACTCMPAD_ZERO \
+ 0x00000080 // Set the output signal to 0
+#define PWM_3_GENA_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1
+#define PWM_3_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_3_GENA_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_3_GENA_ACTCMPAU_INV 0x00000010 // Invert the output signal
+#define PWM_3_GENA_ACTCMPAU_ZERO \
+ 0x00000020 // Set the output signal to 0
+#define PWM_3_GENA_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1
+#define PWM_3_GENA_ACTLOAD_M 0x0000000C // Action for Counter=Load
+#define PWM_3_GENA_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_3_GENA_ACTLOAD_INV 0x00000004 // Invert the output signal
+#define PWM_3_GENA_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0
+#define PWM_3_GENA_ACTLOAD_ONE 0x0000000C // Set the output signal to 1
+#define PWM_3_GENA_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_3_GENA_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_3_GENA_ACTZERO_INV 0x00000001 // Invert the output signal
+#define PWM_3_GENA_ACTZERO_ZERO 0x00000002 // Set the output signal to 0
+#define PWM_3_GENA_ACTZERO_ONE 0x00000003 // Set the output signal to 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_GENB register.
+//
+//*****************************************************************************
+#define PWM_3_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_3_GENB_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_3_GENB_ACTCMPBD_INV 0x00000400 // Invert the output signal
+#define PWM_3_GENB_ACTCMPBD_ZERO \
+ 0x00000800 // Set the output signal to 0
+#define PWM_3_GENB_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1
+#define PWM_3_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_3_GENB_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_3_GENB_ACTCMPBU_INV 0x00000100 // Invert the output signal
+#define PWM_3_GENB_ACTCMPBU_ZERO \
+ 0x00000200 // Set the output signal to 0
+#define PWM_3_GENB_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1
+#define PWM_3_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_3_GENB_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_3_GENB_ACTCMPAD_INV 0x00000040 // Invert the output signal
+#define PWM_3_GENB_ACTCMPAD_ZERO \
+ 0x00000080 // Set the output signal to 0
+#define PWM_3_GENB_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1
+#define PWM_3_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_3_GENB_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_3_GENB_ACTCMPAU_INV 0x00000010 // Invert the output signal
+#define PWM_3_GENB_ACTCMPAU_ZERO \
+ 0x00000020 // Set the output signal to 0
+#define PWM_3_GENB_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1
+#define PWM_3_GENB_ACTLOAD_M 0x0000000C // Action for Counter=Load
+#define PWM_3_GENB_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_3_GENB_ACTLOAD_INV 0x00000004 // Invert the output signal
+#define PWM_3_GENB_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0
+#define PWM_3_GENB_ACTLOAD_ONE 0x0000000C // Set the output signal to 1
+#define PWM_3_GENB_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_3_GENB_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_3_GENB_ACTZERO_INV 0x00000001 // Invert the output signal
+#define PWM_3_GENB_ACTZERO_ZERO 0x00000002 // Set the output signal to 0
+#define PWM_3_GENB_ACTZERO_ONE 0x00000003 // Set the output signal to 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_3_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_3_DBRISE_RISEDELAY_M \
+ 0x00000FFF // Dead-Band Rise Delay
+#define PWM_3_DBRISE_RISEDELAY_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_3_DBFALL_FALLDELAY_M \
+ 0x00000FFF // Dead-Band Fall Delay
+#define PWM_3_DBFALL_FALLDELAY_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_3_FLTSRC0_FAULT3 0x00000008 // Fault3 Input
+#define PWM_3_FLTSRC0_FAULT2 0x00000004 // Fault2
+#define PWM_3_FLTSRC0_FAULT1 0x00000002 // Fault1
+#define PWM_3_FLTSRC0_FAULT0 0x00000001 // Fault0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_3_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7
+#define PWM_3_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6
+#define PWM_3_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5
+#define PWM_3_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4
+#define PWM_3_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3
+#define PWM_3_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2
+#define PWM_3_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1
+#define PWM_3_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_3_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period
+#define PWM_3_MINFLTPER_MFP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSEN register.
+//
+//*****************************************************************************
+#define PWM_0_FLTSEN_FAULT3 0x00000008 // Fault3 Sense
+#define PWM_0_FLTSEN_FAULT2 0x00000004 // Fault2 Sense
+#define PWM_0_FLTSEN_FAULT1 0x00000002 // Fault1 Sense
+#define PWM_0_FLTSEN_FAULT0 0x00000001 // Fault0 Sense
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_0_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3
+#define PWM_0_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2
+#define PWM_0_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1
+#define PWM_0_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSTAT1
+// register.
+//
+//*****************************************************************************
+#define PWM_0_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger
+#define PWM_0_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger
+#define PWM_0_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger
+#define PWM_0_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger
+#define PWM_0_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger
+#define PWM_0_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger
+#define PWM_0_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger
+#define PWM_0_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_FLTSEN register.
+//
+//*****************************************************************************
+#define PWM_1_FLTSEN_FAULT3 0x00000008 // Fault3 Sense
+#define PWM_1_FLTSEN_FAULT2 0x00000004 // Fault2 Sense
+#define PWM_1_FLTSEN_FAULT1 0x00000002 // Fault1 Sense
+#define PWM_1_FLTSEN_FAULT0 0x00000001 // Fault0 Sense
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_1_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3
+#define PWM_1_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2
+#define PWM_1_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1
+#define PWM_1_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_FLTSTAT1
+// register.
+//
+//*****************************************************************************
+#define PWM_1_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger
+#define PWM_1_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger
+#define PWM_1_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger
+#define PWM_1_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger
+#define PWM_1_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger
+#define PWM_1_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger
+#define PWM_1_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger
+#define PWM_1_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_FLTSEN register.
+//
+//*****************************************************************************
+#define PWM_2_FLTSEN_FAULT3 0x00000008 // Fault3 Sense
+#define PWM_2_FLTSEN_FAULT2 0x00000004 // Fault2 Sense
+#define PWM_2_FLTSEN_FAULT1 0x00000002 // Fault1 Sense
+#define PWM_2_FLTSEN_FAULT0 0x00000001 // Fault0 Sense
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_2_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3
+#define PWM_2_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2
+#define PWM_2_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1
+#define PWM_2_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_FLTSTAT1
+// register.
+//
+//*****************************************************************************
+#define PWM_2_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger
+#define PWM_2_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger
+#define PWM_2_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger
+#define PWM_2_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger
+#define PWM_2_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger
+#define PWM_2_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger
+#define PWM_2_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger
+#define PWM_2_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_FLTSEN register.
+//
+//*****************************************************************************
+#define PWM_3_FLTSEN_FAULT3 0x00000008 // Fault3 Sense
+#define PWM_3_FLTSEN_FAULT2 0x00000004 // Fault2 Sense
+#define PWM_3_FLTSEN_FAULT1 0x00000002 // Fault1 Sense
+#define PWM_3_FLTSEN_FAULT0 0x00000001 // Fault0 Sense
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_3_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3
+#define PWM_3_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2
+#define PWM_3_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1
+#define PWM_3_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_FLTSTAT1
+// register.
+//
+//*****************************************************************************
+#define PWM_3_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger
+#define PWM_3_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger
+#define PWM_3_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger
+#define PWM_3_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger
+#define PWM_3_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger
+#define PWM_3_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger
+#define PWM_3_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger
+#define PWM_3_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_PP register.
+//
+//*****************************************************************************
+#define PWM_PP_GCNT_M 0x0000000F // Generators
+#define PWM_PP_FCNT_M 0x000000F0 // Fault Inputs
+#define PWM_PP_ESYNC 0x00000100 // Extended Synchronization
+#define PWM_PP_EFAULT 0x00000200 // Extended Fault
+#define PWM_PP_ONE 0x00000400 // One-Shot Mode
+#define PWM_PP_GCNT_S 0
+#define PWM_PP_FCNT_S 4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_PC register.
+//
+//*****************************************************************************
+#define PWM_PC_PWMDIV_M 0x000000FF // PWM Clock Divisor
+#define PWM_PC_PWMDIV_2 0x00000000 // /2
+#define PWM_PC_PWMDIV_4 0x00000001 // /4
+#define PWM_PC_PWMDIV_8 0x00000002 // /8
+#define PWM_PC_PWMDIV_16 0x00000003 // /16
+#define PWM_PC_PWMDIV_32 0x00000004 // /32
+#define PWM_PC_PWMDIV_64 0x00000007 // /64 (default)
+#define PWM_PC_USEPWMDIV 0x00000100 // Enable PWM Clock Divisor
+
+//*****************************************************************************
+//
+// The following are defines for the PWM Generator standard offsets.
+//
+//*****************************************************************************
+#define PWM_O_X_CTL 0x00000000 // Gen Control Reg
+#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg
+#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg
+#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg
+#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg
+#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg
+#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg
+#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg
+#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg
+#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg
+#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg
+#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg
+#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg
+#define PWM_O_X_FLTSRC0 0x00000034 // Fault pin, comparator condition
+#define PWM_O_X_FLTSRC1 0x00000038 // Digital comparator condition
+#define PWM_O_X_MINFLTPER 0x0000003C // Fault minimum period extension
+#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base
+#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base
+#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base
+#define PWM_GEN_3_OFFSET 0x00000100 // PWM3 base
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_CTL register.
+//
+//*****************************************************************************
+#define PWM_X_CTL_LATCH 0x00040000 // Latch Fault Input
+#define PWM_X_CTL_MINFLTPER 0x00020000 // Minimum Fault Period
+#define PWM_X_CTL_FLTSRC 0x00010000 // Fault Condition Source
+#define PWM_X_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode
+#define PWM_X_CTL_DBFALLUPD_I 0x00000000 // Immediate
+#define PWM_X_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized
+#define PWM_X_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized
+#define PWM_X_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode
+#define PWM_X_CTL_DBRISEUPD_I 0x00000000 // Immediate
+#define PWM_X_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized
+#define PWM_X_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized
+#define PWM_X_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode
+#define PWM_X_CTL_DBCTLUPD_I 0x00000000 // Immediate
+#define PWM_X_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized
+#define PWM_X_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized
+#define PWM_X_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode
+#define PWM_X_CTL_GENBUPD_I 0x00000000 // Immediate
+#define PWM_X_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized
+#define PWM_X_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized
+#define PWM_X_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode
+#define PWM_X_CTL_GENAUPD_I 0x00000000 // Immediate
+#define PWM_X_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized
+#define PWM_X_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized
+#define PWM_X_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode
+#define PWM_X_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode
+#define PWM_X_CTL_LOADUPD 0x00000008 // Load Register Update Mode
+#define PWM_X_CTL_DEBUG 0x00000004 // Debug Mode
+#define PWM_X_CTL_MODE 0x00000002 // Counter Mode
+#define PWM_X_CTL_ENABLE 0x00000001 // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_INTEN register.
+//
+//*****************************************************************************
+#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB
+ // Down
+#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up
+#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA
+ // Down
+#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up
+#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD
+#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0
+#define PWM_X_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB
+ // Down
+#define PWM_X_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB
+ // Up
+#define PWM_X_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA
+ // Down
+#define PWM_X_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA
+ // Up
+#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD
+#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_RIS register.
+//
+//*****************************************************************************
+#define PWM_X_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+ // Status
+#define PWM_X_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status
+#define PWM_X_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+ // Status
+#define PWM_X_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status
+#define PWM_X_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status
+#define PWM_X_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_ISC register.
+//
+//*****************************************************************************
+#define PWM_X_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+#define PWM_X_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt
+#define PWM_X_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+#define PWM_X_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt
+#define PWM_X_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt
+#define PWM_X_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_LOAD register.
+//
+//*****************************************************************************
+#define PWM_X_LOAD_M 0x0000FFFF // Counter Load Value
+#define PWM_X_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_COUNT register.
+//
+//*****************************************************************************
+#define PWM_X_COUNT_M 0x0000FFFF // Counter Value
+#define PWM_X_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_CMPA register.
+//
+//*****************************************************************************
+#define PWM_X_CMPA_M 0x0000FFFF // Comparator A Value
+#define PWM_X_CMPA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_CMPB register.
+//
+//*****************************************************************************
+#define PWM_X_CMPB_M 0x0000FFFF // Comparator B Value
+#define PWM_X_CMPB_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_GENA register.
+//
+//*****************************************************************************
+#define PWM_X_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_X_GENA_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_X_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA
+#define PWM_X_GENA_ACTCMPBD_ZERO \
+ 0x00000800 // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High
+#define PWM_X_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_X_GENA_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_X_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA
+#define PWM_X_GENA_ACTCMPBU_ZERO \
+ 0x00000200 // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High
+#define PWM_X_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_X_GENA_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_X_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA
+#define PWM_X_GENA_ACTCMPAD_ZERO \
+ 0x00000080 // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High
+#define PWM_X_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_X_GENA_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_X_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA
+#define PWM_X_GENA_ACTCMPAU_ZERO \
+ 0x00000020 // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High
+#define PWM_X_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD
+#define PWM_X_GENA_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_X_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA
+#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low
+#define PWM_X_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High
+#define PWM_X_GENA_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_X_GENA_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_X_GENA_ACTZERO_INV 0x00000001 // Invert pwmA
+#define PWM_X_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low
+#define PWM_X_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_GENB register.
+//
+//*****************************************************************************
+#define PWM_X_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_X_GENB_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_X_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB
+#define PWM_X_GENB_ACTCMPBD_ZERO \
+ 0x00000800 // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High
+#define PWM_X_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_X_GENB_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_X_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB
+#define PWM_X_GENB_ACTCMPBU_ZERO \
+ 0x00000200 // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High
+#define PWM_X_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_X_GENB_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_X_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB
+#define PWM_X_GENB_ACTCMPAD_ZERO \
+ 0x00000080 // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High
+#define PWM_X_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_X_GENB_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_X_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB
+#define PWM_X_GENB_ACTCMPAU_ZERO \
+ 0x00000020 // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High
+#define PWM_X_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD
+#define PWM_X_GENB_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_X_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB
+#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low
+#define PWM_X_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High
+#define PWM_X_GENB_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_X_GENB_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_X_GENB_ACTZERO_INV 0x00000001 // Invert pwmB
+#define PWM_X_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low
+#define PWM_X_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_X_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_X_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay
+#define PWM_X_DBRISE_DELAY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_X_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay
+#define PWM_X_DBFALL_DELAY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSRC0_FAULT3 0x00000008 // Fault3 Input
+#define PWM_X_FLTSRC0_FAULT2 0x00000004 // Fault2 Input
+#define PWM_X_FLTSRC0_FAULT1 0x00000002 // Fault1 Input
+#define PWM_X_FLTSRC0_FAULT0 0x00000001 // Fault0 Input
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7
+#define PWM_X_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6
+#define PWM_X_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5
+#define PWM_X_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4
+#define PWM_X_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3
+#define PWM_X_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2
+#define PWM_X_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1
+#define PWM_X_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_X_MINFLTPER_M 0x0000FFFF // Minimum Fault Period
+#define PWM_X_MINFLTPER_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the PWM Generator extended offsets.
+//
+//*****************************************************************************
+#define PWM_O_X_FLTSEN 0x00000000 // Fault logic sense
+#define PWM_O_X_FLTSTAT0 0x00000004 // Pin and comparator status
+#define PWM_O_X_FLTSTAT1 0x00000008 // Digital comparator status
+#define PWM_EXT_0_OFFSET 0x00000800 // PWM0 extended base
+#define PWM_EXT_1_OFFSET 0x00000880 // PWM1 extended base
+#define PWM_EXT_2_OFFSET 0x00000900 // PWM2 extended base
+#define PWM_EXT_3_OFFSET 0x00000980 // PWM3 extended base
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSEN register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSEN_FAULT3 0x00000008 // Fault3 Sense
+#define PWM_X_FLTSEN_FAULT2 0x00000004 // Fault2 Sense
+#define PWM_X_FLTSEN_FAULT1 0x00000002 // Fault1 Sense
+#define PWM_X_FLTSEN_FAULT0 0x00000001 // Fault0 Sense
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3
+#define PWM_X_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2
+#define PWM_X_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1
+#define PWM_X_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSTAT1
+// register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger
+#define PWM_X_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger
+#define PWM_X_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger
+#define PWM_X_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger
+#define PWM_X_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger
+#define PWM_X_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger
+#define PWM_X_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger
+#define PWM_X_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the PWM_O_CTL
+// register.
+//
+//*****************************************************************************
+#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2
+#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1
+#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the PWM_O_STATUS
+// register.
+//
+//*****************************************************************************
+#define PWM_STATUS_FAULT 0x00000001 // Fault Interrupt Status
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the PWM Interrupt Register bit
+// definitions.
+//
+//*****************************************************************************
+#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the PWM_X Interrupt Status Register
+// bit definitions.
+//
+//*****************************************************************************
+#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd
+#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd
+#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd
+#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd
+#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd
+#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the PWM_X Generator A/B Control
+// Register bit definitions.
+//
+//*****************************************************************************
+#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D
+#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U
+#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D
+#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U
+#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD
+#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the PWM_X Generator A/B Control
+// Register action definitions.
+//
+//*****************************************************************************
+#define PWM_GEN_ACT_ONE 0x00000003 // Set the output signal to one
+#define PWM_GEN_ACT_ZERO 0x00000002 // Set the output signal to zero
+#define PWM_GEN_ACT_INV 0x00000001 // Invert the output signal
+#define PWM_GEN_ACT_NONE 0x00000000 // Do nothing
+#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action
+#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action
+#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action
+#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action
+#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action
+#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the PWM_X Dead Band Control
+// Register bit definitions.
+//
+//*****************************************************************************
+#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the PWM Register reset values.
+//
+//*****************************************************************************
+#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator
+#define PWM_RV_STATUS 0x00000000 // Status
+#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing
+#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status
+#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM
+ // generator block
+#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators
+#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay
+ // count
+#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable
+#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter
+#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A
+#define PWM_RV_CTL 0x00000000 // Master control of the PWM module
+#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM
+ // output pins
+#define PWM_RV_RIS 0x00000000 // Raw interrupt status
+#define PWM_RV_X_CMPA 0x00000000 // The comparator A value
+#define PWM_RV_INVERT 0x00000000 // Inversion control for PWM output
+ // pins
+#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay
+ // count
+#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM output
+ // pins
+#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B
+#define PWM_RV_X_CMPB 0x00000000 // The comparator B value
+#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing
+#define PWM_RV_INTEN 0x00000000 // Interrupt enable
+#define PWM_RV_X_COUNT 0x00000000 // The current counter value
+
+#endif
+
+#endif // __HW_PWM_H__
diff --git a/inc/hw_qei.h b/inc/hw_qei.h new file mode 100644 index 0000000..2f8cefc --- /dev/null +++ b/inc/hw_qei.h @@ -0,0 +1,216 @@ +//*****************************************************************************
+//
+// hw_qei.h - Macros used when accessing the QEI hardware.
+//
+// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 9453 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_QEI_H__
+#define __HW_QEI_H__
+
+//*****************************************************************************
+//
+// The following are defines for the QEI register offsets.
+//
+//*****************************************************************************
+#define QEI_O_CTL 0x00000000 // QEI Control
+#define QEI_O_STAT 0x00000004 // QEI Status
+#define QEI_O_POS 0x00000008 // QEI Position
+#define QEI_O_MAXPOS 0x0000000C // QEI Maximum Position
+#define QEI_O_LOAD 0x00000010 // QEI Timer Load
+#define QEI_O_TIME 0x00000014 // QEI Timer
+#define QEI_O_COUNT 0x00000018 // QEI Velocity Counter
+#define QEI_O_SPEED 0x0000001C // QEI Velocity
+#define QEI_O_INTEN 0x00000020 // QEI Interrupt Enable
+#define QEI_O_RIS 0x00000024 // QEI Raw Interrupt Status
+#define QEI_O_ISC 0x00000028 // QEI Interrupt Status and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_CTL register.
+//
+//*****************************************************************************
+#define QEI_CTL_FILTCNT_M 0x000F0000 // Input Filter Prescale Count
+#define QEI_CTL_FILTEN 0x00002000 // Enable Input Filter
+#define QEI_CTL_STALLEN 0x00001000 // Stall QEI
+#define QEI_CTL_INVI 0x00000800 // Invert Index Pulse
+#define QEI_CTL_INVB 0x00000400 // Invert PhB
+#define QEI_CTL_INVA 0x00000200 // Invert PhA
+#define QEI_CTL_VELDIV_M 0x000001C0 // Predivide Velocity
+#define QEI_CTL_VELDIV_1 0x00000000 // QEI clock /1
+#define QEI_CTL_VELDIV_2 0x00000040 // QEI clock /2
+#define QEI_CTL_VELDIV_4 0x00000080 // QEI clock /4
+#define QEI_CTL_VELDIV_8 0x000000C0 // QEI clock /8
+#define QEI_CTL_VELDIV_16 0x00000100 // QEI clock /16
+#define QEI_CTL_VELDIV_32 0x00000140 // QEI clock /32
+#define QEI_CTL_VELDIV_64 0x00000180 // QEI clock /64
+#define QEI_CTL_VELDIV_128 0x000001C0 // QEI clock /128
+#define QEI_CTL_VELEN 0x00000020 // Capture Velocity
+#define QEI_CTL_RESMODE 0x00000010 // Reset Mode
+#define QEI_CTL_CAPMODE 0x00000008 // Capture Mode
+#define QEI_CTL_SIGMODE 0x00000004 // Signal Mode
+#define QEI_CTL_SWAP 0x00000002 // Swap Signals
+#define QEI_CTL_ENABLE 0x00000001 // Enable QEI
+#define QEI_CTL_FILTCNT_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_STAT register.
+//
+//*****************************************************************************
+#define QEI_STAT_DIRECTION 0x00000002 // Direction of Rotation
+#define QEI_STAT_ERROR 0x00000001 // Error Detected
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_POS register.
+//
+//*****************************************************************************
+#define QEI_POS_M 0xFFFFFFFF // Current Position Integrator
+ // Value
+#define QEI_POS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_MAXPOS register.
+//
+//*****************************************************************************
+#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum Position Integrator
+ // Value
+#define QEI_MAXPOS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_LOAD register.
+//
+//*****************************************************************************
+#define QEI_LOAD_M 0xFFFFFFFF // Velocity Timer Load Value
+#define QEI_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_TIME register.
+//
+//*****************************************************************************
+#define QEI_TIME_M 0xFFFFFFFF // Velocity Timer Current Value
+#define QEI_TIME_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_COUNT register.
+//
+//*****************************************************************************
+#define QEI_COUNT_M 0xFFFFFFFF // Velocity Pulse Count
+#define QEI_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_SPEED register.
+//
+//*****************************************************************************
+#define QEI_SPEED_M 0xFFFFFFFF // Velocity
+#define QEI_SPEED_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_INTEN register.
+//
+//*****************************************************************************
+#define QEI_INTEN_ERROR 0x00000008 // Phase Error Interrupt Enable
+#define QEI_INTEN_DIR 0x00000004 // Direction Change Interrupt
+ // Enable
+#define QEI_INTEN_TIMER 0x00000002 // Timer Expires Interrupt Enable
+#define QEI_INTEN_INDEX 0x00000001 // Index Pulse Detected Interrupt
+ // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_RIS register.
+//
+//*****************************************************************************
+#define QEI_RIS_ERROR 0x00000008 // Phase Error Detected
+#define QEI_RIS_DIR 0x00000004 // Direction Change Detected
+#define QEI_RIS_TIMER 0x00000002 // Velocity Timer Expired
+#define QEI_RIS_INDEX 0x00000001 // Index Pulse Asserted
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_ISC register.
+//
+//*****************************************************************************
+#define QEI_ISC_ERROR 0x00000008 // Phase Error Interrupt
+#define QEI_ISC_DIR 0x00000004 // Direction Change Interrupt
+#define QEI_ISC_TIMER 0x00000002 // Velocity Timer Expired Interrupt
+#define QEI_ISC_INDEX 0x00000001 // Index Pulse Interrupt
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the QEI_ISC
+// register.
+//
+//*****************************************************************************
+#define QEI_INT_ERROR 0x00000008 // Phase error detected
+#define QEI_INT_DIR 0x00000004 // Direction change
+#define QEI_INT_TIMER 0x00000002 // Velocity timer expired
+#define QEI_INT_INDEX 0x00000001 // Index pulse detected
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the reset values for the QEI
+// registers.
+//
+//*****************************************************************************
+#define QEI_RV_POS 0x00000000 // Current position register
+#define QEI_RV_LOAD 0x00000000 // Velocity timer load register
+#define QEI_RV_CTL 0x00000000 // Configuration and control reg
+#define QEI_RV_RIS 0x00000000 // Raw interrupt status register
+#define QEI_RV_ISC 0x00000000 // Interrupt status register
+#define QEI_RV_SPEED 0x00000000 // Velocity speed register
+#define QEI_RV_INTEN 0x00000000 // Interrupt enable register
+#define QEI_RV_STAT 0x00000000 // Status register
+#define QEI_RV_COUNT 0x00000000 // Velocity pulse count register
+#define QEI_RV_MAXPOS 0x00000000 // Maximum position register
+#define QEI_RV_TIME 0x00000000 // Velocity timer register
+
+#endif
+
+#endif // __HW_QEI_H__
diff --git a/inc/hw_ssi.h b/inc/hw_ssi.h new file mode 100644 index 0000000..6ef4d19 --- /dev/null +++ b/inc/hw_ssi.h @@ -0,0 +1,244 @@ +//*****************************************************************************
+//
+// hw_ssi.h - Macros used when accessing the SSI hardware.
+//
+// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 9453 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_SSI_H__
+#define __HW_SSI_H__
+
+//*****************************************************************************
+//
+// The following are defines for the SSI register offsets.
+//
+//*****************************************************************************
+#define SSI_O_CR0 0x00000000 // SSI Control 0
+#define SSI_O_CR1 0x00000004 // SSI Control 1
+#define SSI_O_DR 0x00000008 // SSI Data
+#define SSI_O_SR 0x0000000C // SSI Status
+#define SSI_O_CPSR 0x00000010 // SSI Clock Prescale
+#define SSI_O_IM 0x00000014 // SSI Interrupt Mask
+#define SSI_O_RIS 0x00000018 // SSI Raw Interrupt Status
+#define SSI_O_MIS 0x0000001C // SSI Masked Interrupt Status
+#define SSI_O_ICR 0x00000020 // SSI Interrupt Clear
+#define SSI_O_DMACTL 0x00000024 // SSI DMA Control
+#define SSI_O_CC 0x00000FC8 // SSI Clock Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CR0 register.
+//
+//*****************************************************************************
+#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate
+#define SSI_CR0_SPH 0x00000080 // SSI Serial Clock Phase
+#define SSI_CR0_SPO 0x00000040 // SSI Serial Clock Polarity
+#define SSI_CR0_FRF_M 0x00000030 // SSI Frame Format Select
+#define SSI_CR0_FRF_MOTO 0x00000000 // Freescale SPI Frame Format
+#define SSI_CR0_FRF_TI 0x00000010 // Texas Instruments Synchronous
+ // Serial Frame Format
+#define SSI_CR0_FRF_NMW 0x00000020 // MICROWIRE Frame Format
+#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select
+#define SSI_CR0_DSS_4 0x00000003 // 4-bit data
+#define SSI_CR0_DSS_5 0x00000004 // 5-bit data
+#define SSI_CR0_DSS_6 0x00000005 // 6-bit data
+#define SSI_CR0_DSS_7 0x00000006 // 7-bit data
+#define SSI_CR0_DSS_8 0x00000007 // 8-bit data
+#define SSI_CR0_DSS_9 0x00000008 // 9-bit data
+#define SSI_CR0_DSS_10 0x00000009 // 10-bit data
+#define SSI_CR0_DSS_11 0x0000000A // 11-bit data
+#define SSI_CR0_DSS_12 0x0000000B // 12-bit data
+#define SSI_CR0_DSS_13 0x0000000C // 13-bit data
+#define SSI_CR0_DSS_14 0x0000000D // 14-bit data
+#define SSI_CR0_DSS_15 0x0000000E // 15-bit data
+#define SSI_CR0_DSS_16 0x0000000F // 16-bit data
+#define SSI_CR0_SCR_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CR1 register.
+//
+//*****************************************************************************
+#define SSI_CR1_EOT 0x00000010 // End of Transmission
+#define SSI_CR1_SOD 0x00000008 // SSI Slave Mode Output Disable
+#define SSI_CR1_MS 0x00000004 // SSI Master/Slave Select
+#define SSI_CR1_SSE 0x00000002 // SSI Synchronous Serial Port
+ // Enable
+#define SSI_CR1_LBM 0x00000001 // SSI Loopback Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_DR register.
+//
+//*****************************************************************************
+#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data
+#define SSI_DR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_SR register.
+//
+//*****************************************************************************
+#define SSI_SR_BSY 0x00000010 // SSI Busy Bit
+#define SSI_SR_RFF 0x00000008 // SSI Receive FIFO Full
+#define SSI_SR_RNE 0x00000004 // SSI Receive FIFO Not Empty
+#define SSI_SR_TNF 0x00000002 // SSI Transmit FIFO Not Full
+#define SSI_SR_TFE 0x00000001 // SSI Transmit FIFO Empty
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CPSR register.
+//
+//*****************************************************************************
+#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor
+#define SSI_CPSR_CPSDVSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_IM register.
+//
+//*****************************************************************************
+#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt Mask
+#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask
+#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt
+ // Mask
+#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt
+ // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_RIS register.
+//
+//*****************************************************************************
+#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt
+ // Status
+#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt
+ // Status
+#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw
+ // Interrupt Status
+#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw
+ // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_MIS register.
+//
+//*****************************************************************************
+#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked
+ // Interrupt Status
+#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked
+ // Interrupt Status
+#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked
+ // Interrupt Status
+#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked
+ // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_ICR register.
+//
+//*****************************************************************************
+#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt
+ // Clear
+#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt
+ // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_DMACTL register.
+//
+//*****************************************************************************
+#define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable
+#define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CC register.
+//
+//*****************************************************************************
+#define SSI_CC_CS_M 0x0000000F // SSI Baud Clock Source
+#define SSI_CC_CS_SYSPLL 0x00000000 // Either the system clock (if the
+ // PLL bypass is in effect) or the
+ // PLL output (default)
+#define SSI_CC_CS_PIOSC 0x00000005 // PIOSC
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SSI_O_CR0
+// register.
+//
+//*****************************************************************************
+#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate
+#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask
+#define SSI_CR0_DSS 0x0000000F // Data size select
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SSI_O_CPSR
+// register.
+//
+//*****************************************************************************
+#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the SSI controller's FIFO size.
+//
+//*****************************************************************************
+#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO
+#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the interrupt
+// mask set and clear, raw interrupt, masked interrupt, and interrupt clear
+// registers.
+//
+//*****************************************************************************
+#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt
+#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt
+#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt
+#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt
+
+#endif
+
+#endif // __HW_SSI_H__
diff --git a/inc/hw_sysctl.h b/inc/hw_sysctl.h new file mode 100644 index 0000000..3f7f30f --- /dev/null +++ b/inc/hw_sysctl.h @@ -0,0 +1,3676 @@ +//*****************************************************************************
+//
+// hw_sysctl.h - Macros used when accessing the system control hardware.
+//
+// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 9453 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_SYSCTL_H__
+#define __HW_SYSCTL_H__
+
+//*****************************************************************************
+//
+// The following are defines for the System Control register addresses.
+//
+//*****************************************************************************
+#define SYSCTL_DID0 0x400FE000 // Device Identification 0
+#define SYSCTL_DID1 0x400FE004 // Device Identification 1
+#define SYSCTL_DC0 0x400FE008 // Device Capabilities 0
+#define SYSCTL_DC1 0x400FE010 // Device Capabilities 1
+#define SYSCTL_DC2 0x400FE014 // Device Capabilities 2
+#define SYSCTL_DC3 0x400FE018 // Device Capabilities 3
+#define SYSCTL_DC4 0x400FE01C // Device Capabilities 4
+#define SYSCTL_DC5 0x400FE020 // Device Capabilities 5
+#define SYSCTL_DC6 0x400FE024 // Device Capabilities 6
+#define SYSCTL_DC7 0x400FE028 // Device Capabilities 7
+#define SYSCTL_DC8 0x400FE02C // Device Capabilities 8 ADC
+ // Channels
+#define SYSCTL_PBORCTL 0x400FE030 // Brown-Out Reset Control
+#define SYSCTL_LDOPCTL 0x400FE034 // LDO Power Control
+#define SYSCTL_SRCR0 0x400FE040 // Software Reset Control 0
+#define SYSCTL_SRCR1 0x400FE044 // Software Reset Control 1
+#define SYSCTL_SRCR2 0x400FE048 // Software Reset Control 2
+#define SYSCTL_RIS 0x400FE050 // Raw Interrupt Status
+#define SYSCTL_IMC 0x400FE054 // Interrupt Mask Control
+#define SYSCTL_MISC 0x400FE058 // Masked Interrupt Status and
+ // Clear
+#define SYSCTL_RESC 0x400FE05C // Reset Cause
+#define SYSCTL_RCC 0x400FE060 // Run-Mode Clock Configuration
+#define SYSCTL_PLLCFG 0x400FE064 // XTAL to PLL Translation
+#define SYSCTL_GPIOHBCTL 0x400FE06C // GPIO High-Performance Bus
+ // Control
+#define SYSCTL_RCC2 0x400FE070 // Run-Mode Clock Configuration 2
+#define SYSCTL_MOSCCTL 0x400FE07C // Main Oscillator Control
+#define SYSCTL_RCGC0 0x400FE100 // Run Mode Clock Gating Control
+ // Register 0
+#define SYSCTL_RCGC1 0x400FE104 // Run Mode Clock Gating Control
+ // Register 1
+#define SYSCTL_RCGC2 0x400FE108 // Run Mode Clock Gating Control
+ // Register 2
+#define SYSCTL_SCGC0 0x400FE110 // Sleep Mode Clock Gating Control
+ // Register 0
+#define SYSCTL_SCGC1 0x400FE114 // Sleep Mode Clock Gating Control
+ // Register 1
+#define SYSCTL_SCGC2 0x400FE118 // Sleep Mode Clock Gating Control
+ // Register 2
+#define SYSCTL_DCGC0 0x400FE120 // Deep Sleep Mode Clock Gating
+ // Control Register 0
+#define SYSCTL_DCGC1 0x400FE124 // Deep-Sleep Mode Clock Gating
+ // Control Register 1
+#define SYSCTL_DCGC2 0x400FE128 // Deep Sleep Mode Clock Gating
+ // Control Register 2
+#define SYSCTL_DSLPCLKCFG 0x400FE144 // Deep Sleep Clock Configuration
+#define SYSCTL_SYSPROP 0x400FE14C // System Properties
+#define SYSCTL_PIOSCCAL 0x400FE150 // Precision Internal Oscillator
+ // Calibration
+#define SYSCTL_CLKVCLR 0x400FE150 // Clock Verification Clear
+#define SYSCTL_PIOSCSTAT 0x400FE154 // Precision Internal Oscillator
+ // Statistics
+#define SYSCTL_LDOARST 0x400FE160 // Allow Unregulated LDO to Reset
+ // the Part
+#define SYSCTL_PLLFREQ0 0x400FE160 // PLL Frequency 0
+#define SYSCTL_PLLFREQ1 0x400FE164 // PLL Frequency 1
+#define SYSCTL_PLLSTAT 0x400FE168 // PLL Status
+#define SYSCTL_I2SMCLKCFG 0x400FE170 // I2S MCLK Configuration
+#define SYSCTL_DC9 0x400FE190 // Device Capabilities 9 ADC
+ // Digital Comparators
+#define SYSCTL_NVMSTAT 0x400FE1A0 // Non-Volatile Memory Information
+#define SYSCTL_PPWD 0x400FE300 // Watchdog Timer Peripheral
+ // Present
+#define SYSCTL_PPTIMER 0x400FE304 // Timer Peripheral Present
+#define SYSCTL_PPGPIO 0x400FE308 // General-Purpose Input/Output
+ // Peripheral Present
+#define SYSCTL_PPDMA 0x400FE30C // Micro Direct Memory Access
+ // Peripheral Present
+#define SYSCTL_PPHIB 0x400FE314 // Hibernation Peripheral Present
+#define SYSCTL_PPUART 0x400FE318 // Universal Asynchronous
+ // Receiver/Transmitter Peripheral
+ // Present
+#define SYSCTL_PPSSI 0x400FE31C // Synchronous Serial Interface
+ // Peripheral Present
+#define SYSCTL_PPI2C 0x400FE320 // Inter-Integrated Circuit
+ // Peripheral Present
+#define SYSCTL_PPUSB 0x400FE328 // Universal Serial Bus Peripheral
+ // Present
+#define SYSCTL_PPCAN 0x400FE334 // Controller Area Network
+ // Peripheral Present
+#define SYSCTL_PPADC 0x400FE338 // Analog-to-Digital Converter
+ // Peripheral Present
+#define SYSCTL_PPACMP 0x400FE33C // Analog Comparator Peripheral
+ // Present
+#define SYSCTL_PPPWM 0x400FE340 // Pulse Width Modulator Peripheral
+ // Present
+#define SYSCTL_PPQEI 0x400FE344 // Quadrature Encoder Interface
+ // Peripheral Present
+#define SYSCTL_PPLPC 0x400FE348 // Low Pin Count Interface
+ // Peripheral Present
+#define SYSCTL_PPPECI 0x400FE350 // Platform Environment Control
+ // Interface Peripheral Present
+#define SYSCTL_PPFAN 0x400FE354 // Fan Control Peripheral Present
+#define SYSCTL_PPEEPROM 0x400FE358 // EEPROM Peripheral Present
+#define SYSCTL_PPWTIMER 0x400FE35C // Wide Timer Peripheral Present
+#define SYSCTL_SRWD 0x400FE500 // Watchdog Timer Software Reset
+#define SYSCTL_SRTIMER 0x400FE504 // Timer Software Reset
+#define SYSCTL_SRGPIO 0x400FE508 // General-Purpose Input/Output
+ // Software Reset
+#define SYSCTL_SRDMA 0x400FE50C // Micro Direct Memory Access
+ // Software Reset
+#define SYSCTL_SRHIB 0x400FE514 // Hibernation Software Reset
+#define SYSCTL_SRUART 0x400FE518 // Universal Asynchronous
+ // Receiver/Transmitter Software
+ // Reset
+#define SYSCTL_SRSSI 0x400FE51C // Synchronous Serial Interface
+ // Software Reset
+#define SYSCTL_SRI2C 0x400FE520 // Inter-Integrated Circuit
+ // Software Reset
+#define SYSCTL_SRUSB 0x400FE528 // Universal Serial Bus Software
+ // Reset
+#define SYSCTL_SRCAN 0x400FE534 // Controller Area Network Software
+ // Reset
+#define SYSCTL_SRADC 0x400FE538 // Analog-to-Digital Converter
+ // Software Reset
+#define SYSCTL_SRACMP 0x400FE53C // Analog Comparator Software Reset
+#define SYSCTL_SRPWM 0x400FE540 // Pulse Width Modulator Software
+ // Reset
+#define SYSCTL_SRQEI 0x400FE544 // Quadrature Encoder Interface
+ // Software Reset
+#define SYSCTL_SRLPC 0x400FE548 // Low Pin Count Interface Software
+ // Reset
+#define SYSCTL_SRPECI 0x400FE550 // Platform Environment Control
+ // Interface Software Reset
+#define SYSCTL_SRFAN 0x400FE554 // Fan Software Reset
+#define SYSCTL_SREEPROM 0x400FE558 // EEPROM Software Reset
+#define SYSCTL_SRWTIMER 0x400FE55C // Wide Timer Software Reset
+#define SYSCTL_RCGCWD 0x400FE600 // Watchdog Timer Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCTIMER 0x400FE604 // Timer Run Mode Clock Gating
+ // Control
+#define SYSCTL_RCGCGPIO 0x400FE608 // General-Purpose Input/Output Run
+ // Mode Clock Gating Control
+#define SYSCTL_RCGCDMA 0x400FE60C // Micro Direct Memory Access Run
+ // Mode Clock Gating Control
+#define SYSCTL_RCGCHIB 0x400FE614 // Hibernation Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCUART 0x400FE618 // Universal Asynchronous
+ // Receiver/Transmitter Run Mode
+ // Clock Gating Control
+#define SYSCTL_RCGCSSI 0x400FE61C // Synchronous Serial Interface Run
+ // Mode Clock Gating Control
+#define SYSCTL_RCGCI2C 0x400FE620 // Inter-Integrated Circuit Run
+ // Mode Clock Gating Control
+#define SYSCTL_RCGCUSB 0x400FE628 // Universal Serial Bus Run Mode
+ // Clock Gating Control
+#define SYSCTL_RCGCCAN 0x400FE634 // Controller Area Network Run Mode
+ // Clock Gating Control
+#define SYSCTL_RCGCADC 0x400FE638 // Analog-to-Digital Converter Run
+ // Mode Clock Gating Control
+#define SYSCTL_RCGCACMP 0x400FE63C // Analog Comparator Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCPWM 0x400FE640 // Pulse Width Modulator Run Mode
+ // Clock Gating Control
+#define SYSCTL_RCGCQEI 0x400FE644 // Quadrature Encoder Interface Run
+ // Mode Clock Gating Control
+#define SYSCTL_RCGCLPC 0x400FE648 // Low Pin Count Interface Run Mode
+ // Clock Gating Control
+#define SYSCTL_RCGCPECI 0x400FE650 // Platform Environment Control
+ // Interface Run Mode Clock Gating
+ // Control
+#define SYSCTL_RCGCFAN 0x400FE654 // Fan Run Mode Clock Gating
+ // Control
+#define SYSCTL_RCGCEEPROM 0x400FE658 // EEPROM Run Mode Clock Gating
+ // Control
+#define SYSCTL_RCGCWTIMER 0x400FE65C // Wide Timer Run Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCWD 0x400FE700 // Watchdog Timer Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCTIMER 0x400FE704 // Timer Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCGPIO 0x400FE708 // General-Purpose Input/Output
+ // Sleep Mode Clock Gating Control
+#define SYSCTL_SCGCDMA 0x400FE70C // Micro Direct Memory Access Sleep
+ // Mode Clock Gating Control
+#define SYSCTL_SCGCHIB 0x400FE714 // Hibernation Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCUART 0x400FE718 // Universal Asynchronous
+ // Receiver/Transmitter Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_SCGCSSI 0x400FE71C // Synchronous Serial Interface
+ // Sleep Mode Clock Gating Control
+#define SYSCTL_SCGCI2C 0x400FE720 // Inter-Integrated Circuit Sleep
+ // Mode Clock Gating Control
+#define SYSCTL_SCGCUSB 0x400FE728 // Universal Serial Bus Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_SCGCCAN 0x400FE734 // Controller Area Network Sleep
+ // Mode Clock Gating Control
+#define SYSCTL_SCGCADC 0x400FE738 // Analog-to-Digital Converter
+ // Sleep Mode Clock Gating Control
+#define SYSCTL_SCGCACMP 0x400FE73C // Analog Comparator Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_SCGCPWM 0x400FE740 // Pulse Width Modulator Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_SCGCQEI 0x400FE744 // Quadrature Encoder Interface
+ // Sleep Mode Clock Gating Control
+#define SYSCTL_SCGCLPC 0x400FE748 // Low Pin Count Interface Sleep
+ // Mode Clock Gating Control
+#define SYSCTL_SCGCPECI 0x400FE750 // Platform Environment Control
+ // Interface Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCFAN 0x400FE754 // Fan Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCEEPROM 0x400FE758 // EEPROM Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCWTIMER 0x400FE75C // Wide Timer Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_DCGCWD 0x400FE800 // Watchdog Timer Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCTIMER 0x400FE804 // Timer Deep-Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_DCGCGPIO 0x400FE808 // General-Purpose Input/Output
+ // Deep-Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_DCGCDMA 0x400FE80C // Micro Direct Memory Access
+ // Deep-Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_DCGCHIB 0x400FE814 // Hibernation Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCUART 0x400FE818 // Universal Asynchronous
+ // Receiver/Transmitter Deep-Sleep
+ // Mode Clock Gating Control
+#define SYSCTL_DCGCSSI 0x400FE81C // Synchronous Serial Interface
+ // Deep-Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_DCGCI2C 0x400FE820 // Inter-Integrated Circuit
+ // Deep-Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_DCGCUSB 0x400FE828 // Universal Serial Bus Deep-Sleep
+ // Mode Clock Gating Control
+#define SYSCTL_DCGCCAN 0x400FE834 // Controller Area Network
+ // Deep-Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_DCGCADC 0x400FE838 // Analog-to-Digital Converter
+ // Deep-Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_DCGCACMP 0x400FE83C // Analog Comparator Deep-Sleep
+ // Mode Clock Gating Control
+#define SYSCTL_DCGCPWM 0x400FE840 // Pulse Width Modulator Deep-Sleep
+ // Mode Clock Gating Control
+#define SYSCTL_DCGCQEI 0x400FE844 // Quadrature Encoder Interface
+ // Deep-Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_DCGCLPC 0x400FE848 // Low Pin Count Interface
+ // Deep-Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_DCGCPECI 0x400FE850 // Platform Environment Control
+ // Interface Deep-Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_DCGCFAN 0x400FE854 // Fan Deep-Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_DCGCEEPROM 0x400FE858 // EEPROM Deep-Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_DCGCWTIMER 0x400FE85C // Wide Timer Deep-Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_PCWD 0x400FE900 // Watchdog Timer Power Control
+#define SYSCTL_PCTIMER 0x400FE904 // Timer Power Control
+#define SYSCTL_PCGPIO 0x400FE908 // General-Purpose Input/Output
+ // Power Control
+#define SYSCTL_PCDMA 0x400FE90C // Micro Direct Memory Access Power
+ // Control
+#define SYSCTL_PCHIB 0x400FE914 // Hibernation Power Control
+#define SYSCTL_PCUART 0x400FE918 // Universal Asynchronous
+ // Receiver/Transmitter Power
+ // Control
+#define SYSCTL_PCSSI 0x400FE91C // Synchronous Serial Interface
+ // Power Control
+#define SYSCTL_PCI2C 0x400FE920 // Inter-Integrated Circuit Power
+ // Control
+#define SYSCTL_PCUSB 0x400FE928 // Universal Serial Bus Power
+ // Control
+#define SYSCTL_PCCAN 0x400FE934 // Controller Area Network Power
+ // Control
+#define SYSCTL_PCADC 0x400FE938 // Analog-to-Digital Converter
+ // Power Control
+#define SYSCTL_PCACMP 0x400FE93C // Analog Comparator Power Control
+#define SYSCTL_PCPWM 0x400FE940 // Pulse Width Modulator Power
+ // Control
+#define SYSCTL_PCQEI 0x400FE944 // Quadrature Encoder Interface
+ // Power Control
+#define SYSCTL_PCLPC 0x400FE948 // Low Pin Count Interface Power
+ // Control
+#define SYSCTL_PCPECI 0x400FE950 // Platform Environment Control
+ // Interface Power Control
+#define SYSCTL_PCFAN 0x400FE954 // Fan Power Control
+#define SYSCTL_PCEEPROM 0x400FE958 // EEPROM Power Control
+#define SYSCTL_PCWTIMER 0x400FE95C // Wide Timer Power Control
+#define SYSCTL_PRWD 0x400FEA00 // Watchdog Timer Peripheral Ready
+#define SYSCTL_PRTIMER 0x400FEA04 // Timer Peripheral Ready
+#define SYSCTL_PRGPIO 0x400FEA08 // General-Purpose Input/Output
+ // Peripheral Ready
+#define SYSCTL_PRDMA 0x400FEA0C // Micro Direct Memory Access
+ // Peripheral Ready
+#define SYSCTL_PRHIB 0x400FEA14 // Hibernation Peripheral Ready
+#define SYSCTL_PRUART 0x400FEA18 // Universal Asynchronous
+ // Receiver/Transmitter Peripheral
+ // Ready
+#define SYSCTL_PRSSI 0x400FEA1C // Synchronous Serial Interface
+ // Peripheral Ready
+#define SYSCTL_PRI2C 0x400FEA20 // Inter-Integrated Circuit
+ // Peripheral Ready
+#define SYSCTL_PRUSB 0x400FEA28 // Universal Serial Bus Peripheral
+ // Ready
+#define SYSCTL_PRCAN 0x400FEA34 // Controller Area Network
+ // Peripheral Ready
+#define SYSCTL_PRADC 0x400FEA38 // Analog-to-Digital Converter
+ // Peripheral Ready
+#define SYSCTL_PRACMP 0x400FEA3C // Analog Comparator Peripheral
+ // Ready
+#define SYSCTL_PRPWM 0x400FEA40 // Pulse Width Modulator Peripheral
+ // Ready
+#define SYSCTL_PRQEI 0x400FEA44 // Quadrature Encoder Interface
+ // Peripheral Ready
+#define SYSCTL_PRLPC 0x400FEA48 // Low Pin Count Interface
+ // Peripheral Ready
+#define SYSCTL_PRPECI 0x400FEA50 // Platform Environment Control
+ // Interface Peripheral Ready
+#define SYSCTL_PRFAN 0x400FEA54 // Fan Peripheral Ready
+#define SYSCTL_PREEPROM 0x400FEA58 // EEPROM Peripheral Ready
+#define SYSCTL_PRWTIMER 0x400FEA5C // Wide Timer Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DID0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID0_VER_M 0x70000000 // DID0 Version
+#define SYSCTL_DID0_VER_0 0x00000000 // Initial DID0 register format
+ // definition for Stellaris(R)
+ // Sandstorm-class devices
+#define SYSCTL_DID0_VER_1 0x10000000 // Second version of the DID0
+ // register format
+#define SYSCTL_DID0_CLASS_M 0x00FF0000 // Device Class
+#define SYSCTL_DID0_CLASS_SANDSTORM \
+ 0x00000000 // Sandstorm-class Device
+#define SYSCTL_DID0_CLASS_FURY 0x00010000 // Stellaris(R) Fury-class devices
+#define SYSCTL_DID0_CLASS_DUSTDEVIL \
+ 0x00030000 // Stellaris(R) DustDevil-class
+ // devices
+#define SYSCTL_DID0_CLASS_TEMPEST \
+ 0x00040000 // Stellaris(R) Tempest-class
+ // microcontrollers
+#define SYSCTL_DID0_CLASS_BLIZZARD \
+ 0x00050000 // Stellaris(R) Blizzard-class
+ // microcontrollers
+#define SYSCTL_DID0_CLASS_FIRESTORM \
+ 0x00060000 // Stellaris(R) Firestorm-class
+ // microcontrollers
+#define SYSCTL_DID0_MAJ_M 0x0000FF00 // Major Revision
+#define SYSCTL_DID0_MAJ_REVA 0x00000000 // Revision A (initial device)
+#define SYSCTL_DID0_MAJ_REVB 0x00000100 // Revision B (first base layer
+ // revision)
+#define SYSCTL_DID0_MAJ_REVC 0x00000200 // Revision C (second base layer
+ // revision)
+#define SYSCTL_DID0_MIN_M 0x000000FF // Minor Revision
+#define SYSCTL_DID0_MIN_0 0x00000000 // Initial device, or a major
+ // revision update
+#define SYSCTL_DID0_MIN_1 0x00000001 // First metal layer change
+#define SYSCTL_DID0_MIN_2 0x00000002 // Second metal layer change
+#define SYSCTL_DID0_MIN_3 0x00000003 // Minor revision 3
+#define SYSCTL_DID0_MIN_4 0x00000004 // Minor revision 4
+#define SYSCTL_DID0_MIN_5 0x00000005 // Minor revision 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DID1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID1_VER_M 0xF0000000 // DID1 Version
+#define SYSCTL_DID1_VER_0 0x00000000 // Initial DID1 register format
+ // definition, indicating a
+ // Stellaris LM3Snnn device
+#define SYSCTL_DID1_VER_1 0x10000000 // Second version of the DID1
+ // register format
+#define SYSCTL_DID1_FAM_M 0x0F000000 // Family
+#define SYSCTL_DID1_FAM_STELLARIS \
+ 0x00000000 // Stellaris family of
+ // microcontollers, that is, all
+ // devices with external part
+ // numbers starting with LM3S
+#define SYSCTL_DID1_PRTNO_M 0x00FF0000 // Part Number
+#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101
+#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102
+#define SYSCTL_DID1_PRTNO_300 0x00190000 // LM3S300
+#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301
+#define SYSCTL_DID1_PRTNO_308 0x001A0000 // LM3S308
+#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310
+#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315
+#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316
+#define SYSCTL_DID1_PRTNO_317 0x00170000 // LM3S317
+#define SYSCTL_DID1_PRTNO_328 0x00150000 // LM3S328
+#define SYSCTL_DID1_PRTNO_600 0x002A0000 // LM3S600
+#define SYSCTL_DID1_PRTNO_601 0x00210000 // LM3S601
+#define SYSCTL_DID1_PRTNO_608 0x002B0000 // LM3S608
+#define SYSCTL_DID1_PRTNO_610 0x00220000 // LM3S610
+#define SYSCTL_DID1_PRTNO_611 0x00230000 // LM3S611
+#define SYSCTL_DID1_PRTNO_612 0x00240000 // LM3S612
+#define SYSCTL_DID1_PRTNO_613 0x00250000 // LM3S613
+#define SYSCTL_DID1_PRTNO_615 0x00260000 // LM3S615
+#define SYSCTL_DID1_PRTNO_617 0x00280000 // LM3S617
+#define SYSCTL_DID1_PRTNO_618 0x00290000 // LM3S618
+#define SYSCTL_DID1_PRTNO_628 0x00270000 // LM3S628
+#define SYSCTL_DID1_PRTNO_800 0x00380000 // LM3S800
+#define SYSCTL_DID1_PRTNO_801 0x00310000 // LM3S801
+#define SYSCTL_DID1_PRTNO_808 0x00390000 // LM3S808
+#define SYSCTL_DID1_PRTNO_811 0x00320000 // LM3S811
+#define SYSCTL_DID1_PRTNO_812 0x00330000 // LM3S812
+#define SYSCTL_DID1_PRTNO_815 0x00340000 // LM3S815
+#define SYSCTL_DID1_PRTNO_817 0x00360000 // LM3S817
+#define SYSCTL_DID1_PRTNO_818 0x00370000 // LM3S818
+#define SYSCTL_DID1_PRTNO_828 0x00350000 // LM3S828
+#define SYSCTL_DID1_PRTNO_1110 0x00BF0000 // LM3S1110
+#define SYSCTL_DID1_PRTNO_1133 0x00C30000 // LM3S1133
+#define SYSCTL_DID1_PRTNO_1138 0x00C50000 // LM3S1138
+#define SYSCTL_DID1_PRTNO_1150 0x00C10000 // LM3S1150
+#define SYSCTL_DID1_PRTNO_1162 0x00C40000 // LM3S1162
+#define SYSCTL_DID1_PRTNO_1165 0x00C20000 // LM3S1165
+#define SYSCTL_DID1_PRTNO_1166 0x00EC0000 // LM3S1166
+#define SYSCTL_DID1_PRTNO_1332 0x00C60000 // LM3S1332
+#define SYSCTL_DID1_PRTNO_1435 0x00BC0000 // LM3S1435
+#define SYSCTL_DID1_PRTNO_1439 0x00BA0000 // LM3S1439
+#define SYSCTL_DID1_PRTNO_1512 0x00BB0000 // LM3S1512
+#define SYSCTL_DID1_PRTNO_1538 0x00C70000 // LM3S1538
+#define SYSCTL_DID1_PRTNO_1601 0x00DB0000 // LM3S1601
+#define SYSCTL_DID1_PRTNO_1607 0x00060000 // LM3S1607
+#define SYSCTL_DID1_PRTNO_1608 0x00DA0000 // LM3S1608
+#define SYSCTL_DID1_PRTNO_1620 0x00C00000 // LM3S1620
+#define SYSCTL_DID1_PRTNO_1621 0x00CD0000 // LM3S1621
+#define SYSCTL_DID1_PRTNO_1625 0x00030000 // LM3S1625
+#define SYSCTL_DID1_PRTNO_1626 0x00040000 // LM3S1626
+#define SYSCTL_DID1_PRTNO_1627 0x00050000 // LM3S1627
+#define SYSCTL_DID1_PRTNO_1635 0x00B30000 // LM3S1635
+#define SYSCTL_DID1_PRTNO_1636 0x00EB0000 // LM3S1636
+#define SYSCTL_DID1_PRTNO_1637 0x00BD0000 // LM3S1637
+#define SYSCTL_DID1_PRTNO_1651 0x00B10000 // LM3S1651
+#define SYSCTL_DID1_PRTNO_1751 0x00B90000 // LM3S1751
+#define SYSCTL_DID1_PRTNO_1776 0x00100000 // LM3S1776
+#define SYSCTL_DID1_PRTNO_1811 0x00160000 // LM3S1811
+#define SYSCTL_DID1_PRTNO_1816 0x003D0000 // LM3S1816
+#define SYSCTL_DID1_PRTNO_1850 0x00B40000 // LM3S1850
+#define SYSCTL_DID1_PRTNO_1911 0x00DD0000 // LM3S1911
+#define SYSCTL_DID1_PRTNO_1918 0x00DC0000 // LM3S1918
+#define SYSCTL_DID1_PRTNO_1937 0x00B70000 // LM3S1937
+#define SYSCTL_DID1_PRTNO_1958 0x00BE0000 // LM3S1958
+#define SYSCTL_DID1_PRTNO_1960 0x00B50000 // LM3S1960
+#define SYSCTL_DID1_PRTNO_1968 0x00B80000 // LM3S1968
+#define SYSCTL_DID1_PRTNO_1969 0x00EA0000 // LM3S1969
+#define SYSCTL_DID1_PRTNO_1B21 0x00CE0000 // LM3S1B21
+#define SYSCTL_DID1_PRTNO_1C21 0x00CA0000 // LM3S1C21
+#define SYSCTL_DID1_PRTNO_1C26 0x00CB0000 // LM3S1C26
+#define SYSCTL_DID1_PRTNO_1C58 0x00980000 // LM3S1C58
+#define SYSCTL_DID1_PRTNO_1D21 0x00B00000 // LM3S1D21
+#define SYSCTL_DID1_PRTNO_1D26 0x00CC0000 // LM3S1D26
+#define SYSCTL_DID1_PRTNO_1F11 0x001D0000 // LM3S1F11
+#define SYSCTL_DID1_PRTNO_1F16 0x001B0000 // LM3S1F16
+#define SYSCTL_DID1_PRTNO_1G21 0x00AF0000 // LM3S1G21
+#define SYSCTL_DID1_PRTNO_1G58 0x00950000 // LM3S1G58
+#define SYSCTL_DID1_PRTNO_1H11 0x001E0000 // LM3S1H11
+#define SYSCTL_DID1_PRTNO_1H16 0x001C0000 // LM3S1H16
+#define SYSCTL_DID1_PRTNO_1J11 0x000F0000 // LM3S1J11
+#define SYSCTL_DID1_PRTNO_1J16 0x003C0000 // LM3S1J16
+#define SYSCTL_DID1_PRTNO_1N11 0x000E0000 // LM3S1N11
+#define SYSCTL_DID1_PRTNO_1N16 0x003B0000 // LM3S1N16
+#define SYSCTL_DID1_PRTNO_1P51 0x00B20000 // LM3S1P51
+#define SYSCTL_DID1_PRTNO_1R21 0x009E0000 // LM3S1R21
+#define SYSCTL_DID1_PRTNO_1R26 0x00C90000 // LM3S1R26
+#define SYSCTL_DID1_PRTNO_1W16 0x00300000 // LM3S1W16
+#define SYSCTL_DID1_PRTNO_1Z16 0x002F0000 // LM3S1Z16
+#define SYSCTL_DID1_PRTNO_2016 0x00D40000 // LM3S2016
+#define SYSCTL_DID1_PRTNO_2110 0x00510000 // LM3S2110
+#define SYSCTL_DID1_PRTNO_2139 0x00840000 // LM3S2139
+#define SYSCTL_DID1_PRTNO_2276 0x00390000 // LM3S2276
+#define SYSCTL_DID1_PRTNO_2410 0x00A20000 // LM3S2410
+#define SYSCTL_DID1_PRTNO_2412 0x00590000 // LM3S2412
+#define SYSCTL_DID1_PRTNO_2432 0x00560000 // LM3S2432
+#define SYSCTL_DID1_PRTNO_2533 0x005A0000 // LM3S2533
+#define SYSCTL_DID1_PRTNO_2601 0x00E10000 // LM3S2601
+#define SYSCTL_DID1_PRTNO_2608 0x00E00000 // LM3S2608
+#define SYSCTL_DID1_PRTNO_2616 0x00330000 // LM3S2616
+#define SYSCTL_DID1_PRTNO_2620 0x00570000 // LM3S2620
+#define SYSCTL_DID1_PRTNO_2637 0x00850000 // LM3S2637
+#define SYSCTL_DID1_PRTNO_2651 0x00530000 // LM3S2651
+#define SYSCTL_DID1_PRTNO_2671 0x00800000 // LM3S2671
+#define SYSCTL_DID1_PRTNO_2678 0x00500000 // LM3S2678
+#define SYSCTL_DID1_PRTNO_2730 0x00A40000 // LM3S2730
+#define SYSCTL_DID1_PRTNO_2739 0x00520000 // LM3S2739
+#define SYSCTL_DID1_PRTNO_2776 0x003A0000 // LM3S2776
+#define SYSCTL_DID1_PRTNO_2793 0x006D0000 // LM3S2793
+#define SYSCTL_DID1_PRTNO_2911 0x00E30000 // LM3S2911
+#define SYSCTL_DID1_PRTNO_2918 0x00E20000 // LM3S2918
+#define SYSCTL_DID1_PRTNO_2919 0x00ED0000 // LM3S2919
+#define SYSCTL_DID1_PRTNO_2939 0x00540000 // LM3S2939
+#define SYSCTL_DID1_PRTNO_2948 0x008F0000 // LM3S2948
+#define SYSCTL_DID1_PRTNO_2950 0x00580000 // LM3S2950
+#define SYSCTL_DID1_PRTNO_2965 0x00550000 // LM3S2965
+#define SYSCTL_DID1_PRTNO_2B93 0x006C0000 // LM3S2B93
+#define SYSCTL_DID1_PRTNO_2D93 0x00940000 // LM3S2D93
+#define SYSCTL_DID1_PRTNO_2U93 0x00930000 // LM3S2U93
+#define SYSCTL_DID1_PRTNO_3634 0x00080000 // LM3S3634
+#define SYSCTL_DID1_PRTNO_3651 0x00430000 // LM3S3651
+#define SYSCTL_DID1_PRTNO_3654 0x00C80000 // LM3S3654
+#define SYSCTL_DID1_PRTNO_3739 0x00440000 // LM3S3739
+#define SYSCTL_DID1_PRTNO_3748 0x00490000 // LM3S3748
+#define SYSCTL_DID1_PRTNO_3749 0x00450000 // LM3S3749
+#define SYSCTL_DID1_PRTNO_3826 0x00420000 // LM3S3826
+#define SYSCTL_DID1_PRTNO_3J26 0x00410000 // LM3S3J26
+#define SYSCTL_DID1_PRTNO_3N26 0x00400000 // LM3S3N26
+#define SYSCTL_DID1_PRTNO_3W26 0x003F0000 // LM3S3W26
+#define SYSCTL_DID1_PRTNO_3Z26 0x003E0000 // LM3S3Z26
+#define SYSCTL_DID1_PRTNO_5632 0x00810000 // LM3S5632
+#define SYSCTL_DID1_PRTNO_5651 0x000C0000 // LM3S5651
+#define SYSCTL_DID1_PRTNO_5652 0x008A0000 // LM3S5652
+#define SYSCTL_DID1_PRTNO_5656 0x004D0000 // LM3S5656
+#define SYSCTL_DID1_PRTNO_5662 0x00910000 // LM3S5662
+#define SYSCTL_DID1_PRTNO_5732 0x00960000 // LM3S5732
+#define SYSCTL_DID1_PRTNO_5737 0x00970000 // LM3S5737
+#define SYSCTL_DID1_PRTNO_5739 0x00A00000 // LM3S5739
+#define SYSCTL_DID1_PRTNO_5747 0x00990000 // LM3S5747
+#define SYSCTL_DID1_PRTNO_5749 0x00A70000 // LM3S5749
+#define SYSCTL_DID1_PRTNO_5752 0x009A0000 // LM3S5752
+#define SYSCTL_DID1_PRTNO_5762 0x009C0000 // LM3S5762
+#define SYSCTL_DID1_PRTNO_5791 0x00690000 // LM3S5791
+#define SYSCTL_DID1_PRTNO_5951 0x000B0000 // LM3S5951
+#define SYSCTL_DID1_PRTNO_5956 0x004E0000 // LM3S5956
+#define SYSCTL_DID1_PRTNO_5B91 0x00680000 // LM3S5B91
+#define SYSCTL_DID1_PRTNO_5C31 0x002E0000 // LM3S5C31
+#define SYSCTL_DID1_PRTNO_5C36 0x002C0000 // LM3S5C36
+#define SYSCTL_DID1_PRTNO_5C51 0x005E0000 // LM3S5C51
+#define SYSCTL_DID1_PRTNO_5C56 0x005B0000 // LM3S5C56
+#define SYSCTL_DID1_PRTNO_5D51 0x005F0000 // LM3S5D51
+#define SYSCTL_DID1_PRTNO_5D56 0x005C0000 // LM3S5D56
+#define SYSCTL_DID1_PRTNO_5D91 0x00870000 // LM3S5D91
+#define SYSCTL_DID1_PRTNO_5G31 0x002D0000 // LM3S5G31
+#define SYSCTL_DID1_PRTNO_5G36 0x001F0000 // LM3S5G36
+#define SYSCTL_DID1_PRTNO_5G51 0x005D0000 // LM3S5G51
+#define SYSCTL_DID1_PRTNO_5G56 0x004F0000 // LM3S5G56
+#define SYSCTL_DID1_PRTNO_5K31 0x00090000 // LM3S5K31
+#define SYSCTL_DID1_PRTNO_5K36 0x004A0000 // LM3S5K36
+#define SYSCTL_DID1_PRTNO_5P31 0x000A0000 // LM3S5P31
+#define SYSCTL_DID1_PRTNO_5P36 0x00480000 // LM3S5P36
+#define SYSCTL_DID1_PRTNO_5P3B 0x00B60000 // LM3S5P3B
+#define SYSCTL_DID1_PRTNO_5P51 0x000D0000 // LM3S5P51
+#define SYSCTL_DID1_PRTNO_5P56 0x004C0000 // LM3S5P56
+#define SYSCTL_DID1_PRTNO_5R31 0x00070000 // LM3S5R31
+#define SYSCTL_DID1_PRTNO_5R36 0x004B0000 // LM3S5R36
+#define SYSCTL_DID1_PRTNO_5T36 0x00470000 // LM3S5T36
+#define SYSCTL_DID1_PRTNO_5U91 0x007F0000 // LM3S5U91
+#define SYSCTL_DID1_PRTNO_5Y36 0x00460000 // LM3S5Y36
+#define SYSCTL_DID1_PRTNO_6100 0x00A10000 // LM3S6100
+#define SYSCTL_DID1_PRTNO_6110 0x00740000 // LM3S6110
+#define SYSCTL_DID1_PRTNO_6420 0x00A50000 // LM3S6420
+#define SYSCTL_DID1_PRTNO_6422 0x00820000 // LM3S6422
+#define SYSCTL_DID1_PRTNO_6432 0x00750000 // LM3S6432
+#define SYSCTL_DID1_PRTNO_6537 0x00760000 // LM3S6537
+#define SYSCTL_DID1_PRTNO_6610 0x00710000 // LM3S6610
+#define SYSCTL_DID1_PRTNO_6611 0x00E70000 // LM3S6611
+#define SYSCTL_DID1_PRTNO_6618 0x00E60000 // LM3S6618
+#define SYSCTL_DID1_PRTNO_6633 0x00830000 // LM3S6633
+#define SYSCTL_DID1_PRTNO_6637 0x008B0000 // LM3S6637
+#define SYSCTL_DID1_PRTNO_6730 0x00A30000 // LM3S6730
+#define SYSCTL_DID1_PRTNO_6753 0x00770000 // LM3S6753
+#define SYSCTL_DID1_PRTNO_6816 0x00D10000 // LM3S6816
+#define SYSCTL_DID1_PRTNO_6911 0x00E90000 // LM3S6911
+#define SYSCTL_DID1_PRTNO_6916 0x00D30000 // LM3S6916
+#define SYSCTL_DID1_PRTNO_6918 0x00E80000 // LM3S6918
+#define SYSCTL_DID1_PRTNO_6938 0x00890000 // LM3S6938
+#define SYSCTL_DID1_PRTNO_6950 0x00720000 // LM3S6950
+#define SYSCTL_DID1_PRTNO_6952 0x00780000 // LM3S6952
+#define SYSCTL_DID1_PRTNO_6965 0x00730000 // LM3S6965
+#define SYSCTL_DID1_PRTNO_6C11 0x00AA0000 // LM3S6C11
+#define SYSCTL_DID1_PRTNO_6C65 0x00AC0000 // LM3S6C65
+#define SYSCTL_DID1_PRTNO_6G11 0x009F0000 // LM3S6G11
+#define SYSCTL_DID1_PRTNO_6G65 0x00AB0000 // LM3S6G65
+#define SYSCTL_DID1_PRTNO_8530 0x00640000 // LM3S8530
+#define SYSCTL_DID1_PRTNO_8538 0x008E0000 // LM3S8538
+#define SYSCTL_DID1_PRTNO_8630 0x00610000 // LM3S8630
+#define SYSCTL_DID1_PRTNO_8730 0x00630000 // LM3S8730
+#define SYSCTL_DID1_PRTNO_8733 0x008D0000 // LM3S8733
+#define SYSCTL_DID1_PRTNO_8738 0x00860000 // LM3S8738
+#define SYSCTL_DID1_PRTNO_8930 0x00650000 // LM3S8930
+#define SYSCTL_DID1_PRTNO_8933 0x008C0000 // LM3S8933
+#define SYSCTL_DID1_PRTNO_8938 0x00880000 // LM3S8938
+#define SYSCTL_DID1_PRTNO_8962 0x00A60000 // LM3S8962
+#define SYSCTL_DID1_PRTNO_8970 0x00620000 // LM3S8970
+#define SYSCTL_DID1_PRTNO_8971 0x00D70000 // LM3S8971
+#define SYSCTL_DID1_PRTNO_8C62 0x00AE0000 // LM3S8C62
+#define SYSCTL_DID1_PRTNO_8G62 0x00AD0000 // LM3S8G62
+#define SYSCTL_DID1_PRTNO_9781 0x00CF0000 // LM3S9781
+#define SYSCTL_DID1_PRTNO_9790 0x00670000 // LM3S9790
+#define SYSCTL_DID1_PRTNO_9792 0x006B0000 // LM3S9792
+#define SYSCTL_DID1_PRTNO_9971 0x002D0000 // LM3S9971
+#define SYSCTL_DID1_PRTNO_9997 0x00200000 // LM3S9997
+#define SYSCTL_DID1_PRTNO_9B81 0x00D00000 // LM3S9B81
+#define SYSCTL_DID1_PRTNO_9B90 0x00660000 // LM3S9B90
+#define SYSCTL_DID1_PRTNO_9B92 0x006A0000 // LM3S9B92
+#define SYSCTL_DID1_PRTNO_9B95 0x006E0000 // LM3S9B95
+#define SYSCTL_DID1_PRTNO_9B96 0x006F0000 // LM3S9B96
+#define SYSCTL_DID1_PRTNO_9BN2 0x001D0000 // LM3S9BN2
+#define SYSCTL_DID1_PRTNO_9BN5 0x001E0000 // LM3S9BN5
+#define SYSCTL_DID1_PRTNO_9BN6 0x001F0000 // LM3S9BN6
+#define SYSCTL_DID1_PRTNO_9C97 0x00700000 // LM3S9C97
+#define SYSCTL_DID1_PRTNO_9CN5 0x007A0000 // LM3S9CN5
+#define SYSCTL_DID1_PRTNO_9D81 0x00A90000 // LM3S9D81
+#define SYSCTL_DID1_PRTNO_9D90 0x007E0000 // LM3S9D90
+#define SYSCTL_DID1_PRTNO_9D92 0x00920000 // LM3S9D92
+#define SYSCTL_DID1_PRTNO_9D95 0x00C80000 // LM3S9D95
+#define SYSCTL_DID1_PRTNO_9D96 0x009D0000 // LM3S9D96
+#define SYSCTL_DID1_PRTNO_9DN5 0x007B0000 // LM3S9DN5
+#define SYSCTL_DID1_PRTNO_9DN6 0x007C0000 // LM3S9DN6
+#define SYSCTL_DID1_PRTNO_9G97 0x00600000 // LM3S9G97
+#define SYSCTL_DID1_PRTNO_9GN5 0x00790000 // LM3S9GN5
+#define SYSCTL_DID1_PRTNO_9L71 0x001B0000 // LM3S9L71
+#define SYSCTL_DID1_PRTNO_9L97 0x00180000 // LM3S9L97
+#define SYSCTL_DID1_PRTNO_9U81 0x00A80000 // LM3S9U81
+#define SYSCTL_DID1_PRTNO_9U90 0x007D0000 // LM3S9U90
+#define SYSCTL_DID1_PRTNO_9U92 0x00900000 // LM3S9U92
+#define SYSCTL_DID1_PRTNO_9U95 0x00B70000 // LM3S9U95
+#define SYSCTL_DID1_PRTNO_9U96 0x009B0000 // LM3S9U96
+#define SYSCTL_DID1_PRTNO_LM4F110B2QR \
+ 0x00180000 // LM4F110B2QR
+#define SYSCTL_DID1_PRTNO_LM4F110C4QR \
+ 0x00190000 // LM4F110C4QR
+#define SYSCTL_DID1_PRTNO_LM4F110E5QR \
+ 0x00100000 // LM4F110E5QR
+#define SYSCTL_DID1_PRTNO_LM4F110H5QR \
+ 0x00110000 // LM4F110H5QR
+#define SYSCTL_DID1_PRTNO_LM4F111B2QR \
+ 0x00220000 // LM4F111B2QR
+#define SYSCTL_DID1_PRTNO_LM4F111C4QR \
+ 0x00230000 // LM4F111C4QR
+#define SYSCTL_DID1_PRTNO_LM4F111E5QR \
+ 0x00200000 // LM4F111E5QR
+#define SYSCTL_DID1_PRTNO_LM4F111H5QR \
+ 0x00210000 // LM4F111H5QR
+#define SYSCTL_DID1_PRTNO_LM4F112C4QC \
+ 0x00360000 // LM4F112C4QC
+#define SYSCTL_DID1_PRTNO_LM4F112E5QC \
+ 0x00300000 // LM4F112E5QC
+#define SYSCTL_DID1_PRTNO_LM4F112H5QC \
+ 0x00310000 // LM4F112H5QC
+#define SYSCTL_DID1_PRTNO_LM4F112H5QD \
+ 0x00350000 // LM4F112H5QD
+#define SYSCTL_DID1_PRTNO_LM4F120B2QR \
+ 0x00010000 // LM4F120B2QR
+#define SYSCTL_DID1_PRTNO_LM4F120C4QR \
+ 0x00020000 // LM4F120C4QR
+#define SYSCTL_DID1_PRTNO_LM4F120E5QR \
+ 0x00030000 // LM4F120E5QR
+#define SYSCTL_DID1_PRTNO_LM4F120H5QR \
+ 0x00040000 // LM4F120H5QR
+#define SYSCTL_DID1_PRTNO_LM4F121B2QR \
+ 0x00080000 // LM4F121B2QR
+#define SYSCTL_DID1_PRTNO_LM4F121C4QR \
+ 0x00090000 // LM4F121C4QR
+#define SYSCTL_DID1_PRTNO_LM4F121E5QR \
+ 0x000A0000 // LM4F121E5QR
+#define SYSCTL_DID1_PRTNO_LM4F121H5QR \
+ 0x000B0000 // LM4F121H5QR
+#define SYSCTL_DID1_PRTNO_LM4F122C4QC \
+ 0x00D00000 // LM4F122C4QC
+#define SYSCTL_DID1_PRTNO_LM4F122E5QC \
+ 0x00D10000 // LM4F122E5QC
+#define SYSCTL_DID1_PRTNO_LM4F122H5QC \
+ 0x00D20000 // LM4F122H5QC
+#define SYSCTL_DID1_PRTNO_LM4F122H5QD \
+ 0x00D60000 // LM4F122H5QD
+#define SYSCTL_DID1_PRTNO_LM4F130C4QR \
+ 0x00480000 // LM4F130C4QR
+#define SYSCTL_DID1_PRTNO_LM4F130E5QR \
+ 0x00400000 // LM4F130E5QR
+#define SYSCTL_DID1_PRTNO_LM4F130H5QR \
+ 0x00410000 // LM4F130H5QR
+#define SYSCTL_DID1_PRTNO_LM4F131C4QR \
+ 0x00520000 // LM4F131C4QR
+#define SYSCTL_DID1_PRTNO_LM4F131E5QR \
+ 0x00500000 // LM4F131E5QR
+#define SYSCTL_DID1_PRTNO_LM4F131H5QR \
+ 0x00510000 // LM4F131H5QR
+#define SYSCTL_DID1_PRTNO_LM4F132C4QC \
+ 0x00660000 // LM4F132C4QC
+#define SYSCTL_DID1_PRTNO_LM4F132E5QC \
+ 0x00600000 // LM4F132E5QC
+#define SYSCTL_DID1_PRTNO_LM4F132H5QC \
+ 0x00610000 // LM4F132H5QC
+#define SYSCTL_DID1_PRTNO_LM4F132H5QD \
+ 0x00650000 // LM4F132H5QD
+#define SYSCTL_DID1_PRTNO_LM4F210E5QR \
+ 0x00700000 // LM4F210E5QR
+#define SYSCTL_DID1_PRTNO_LM4F210H5QR \
+ 0x00730000 // LM4F210H5QR
+#define SYSCTL_DID1_PRTNO_LM4F211E5QR \
+ 0x00800000 // LM4F211E5QR
+#define SYSCTL_DID1_PRTNO_LM4F211H5QR \
+ 0x00830000 // LM4F211H5QR
+#define SYSCTL_DID1_PRTNO_LM4F212H5BB \
+ 0x00E90000 // LM4F212H5BB
+#define SYSCTL_DID1_PRTNO_LM4F212H5QC \
+ 0x00C40000 // LM4F212H5QC
+#define SYSCTL_DID1_PRTNO_LM4F212H5QD \
+ 0x00C60000 // LM4F212H5QD
+#define SYSCTL_DID1_PRTNO_LM4F230E5QR \
+ 0x00A00000 // LM4F230E5QR
+#define SYSCTL_DID1_PRTNO_LM4F230H5QR \
+ 0x00A10000 // LM4F230H5QR
+#define SYSCTL_DID1_PRTNO_LM4F231E5QR \
+ 0x00B00000 // LM4F231E5QR
+#define SYSCTL_DID1_PRTNO_LM4F231H5QR \
+ 0x00B10000 // LM4F231H5QR
+#define SYSCTL_DID1_PRTNO_LM4F232E5QC \
+ 0x00C00000 // LM4F232E5QC
+#define SYSCTL_DID1_PRTNO_LM4F232H5BB \
+ 0x00E30000 // LM4F232H5BB
+#define SYSCTL_DID1_PRTNO_LM4F232H5QC \
+ 0x00C10000 // LM4F232H5QC
+#define SYSCTL_DID1_PRTNO_LM4F232H5QD \
+ 0x00C50000 // LM4F232H5QD
+#define SYSCTL_DID1_PRTNO_LM4FS1AH5BB \
+ 0x00E50000 // LM4FS1AH5BB
+#define SYSCTL_DID1_PRTNO_LM4FS1GH5BB \
+ 0x00EA0000 // LM4FS1GH5BB
+#define SYSCTL_DID1_PRTNO_LM4FS99H5BB \
+ 0x00E40000 // LM4FS99H5BB
+#define SYSCTL_DID1_PRTNO_LM4FSXAH5BB \
+ 0x00E00000 // LM4FSXAH5BB
+#define SYSCTL_DID1_PRTNO_LM4FSXLH5BB \
+ 0x00E10000 // LM4FSXLH5BB
+#define SYSCTL_DID1_PINCNT_M 0x0000E000 // Package Pin Count
+#define SYSCTL_DID1_PINCNT_28 0x00000000 // 28-pin package
+#define SYSCTL_DID1_PINCNT_48 0x00002000 // 48-pin package
+#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100-pin package
+#define SYSCTL_DID1_PINCNT_64 0x00006000 // 64-pin package
+#define SYSCTL_DID1_PINCNT_144 0x00008000 // 144-pin package
+#define SYSCTL_DID1_PINCNT_157 0x0000A000 // 157-pin package
+#define SYSCTL_DID1_TEMP_M 0x000000E0 // Temperature Range
+#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temperature range (0C
+ // to 70C)
+#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temperature range
+ // (-40C to 85C)
+#define SYSCTL_DID1_TEMP_E 0x00000040 // Extended temperature range (-40C
+ // to 105C)
+#define SYSCTL_DID1_PKG_M 0x00000018 // Package Type
+#define SYSCTL_DID1_PKG_SOIC 0x00000000 // SOIC package
+#define SYSCTL_DID1_PKG_QFP 0x00000008 // LQFP package
+#define SYSCTL_DID1_PKG_BGA 0x00000010 // BGA package
+#define SYSCTL_DID1_PKG_QFN 0x00000018 // QFN package
+#define SYSCTL_DID1_ROHS 0x00000004 // RoHS-Compliance
+#define SYSCTL_DID1_QUAL_M 0x00000003 // Qualification Status
+#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering Sample (unqualified)
+#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot Production (unqualified)
+#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully Qualified
+#define SYSCTL_DID1_PRTNO_S 16 // Part number shift
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC0_SRAMSZ_M 0xFFFF0000 // SRAM Size
+#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_6KB 0x00170000 // 6 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_12KB 0x002F0000 // 12 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_20KB 0x004F0000 // 20 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_24KB 0x005F0000 // 24 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_48KB 0x00BF0000 // 48 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_64KB 0x00FF0000 // 64 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_96KB 0x017F0000 // 96 KB of SRAM
+#define SYSCTL_DC0_FLASHSZ_M 0x0000FFFF // Flash Size
+#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_192K 0x0000005F // 192 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_384K 0x000000BF // 384 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_512K 0x000000FF // 512 KB of Flash
+#define SYSCTL_DC0_SRAMSZ_S 16 // SRAM size shift
+#define SYSCTL_DC0_FLASHSZ_S 0 // Flash size shift
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC1_WDT1 0x10000000 // Watchdog Timer1 Present
+#define SYSCTL_DC1_CAN2 0x04000000 // CAN Module 2 Present
+#define SYSCTL_DC1_CAN1 0x02000000 // CAN Module 1 Present
+#define SYSCTL_DC1_CAN0 0x01000000 // CAN Module 0 Present
+#define SYSCTL_DC1_PWM1 0x00200000 // PWM Module 1 Present
+#define SYSCTL_DC1_PWM0 0x00100000 // PWM Module 0 Present
+#define SYSCTL_DC1_ADC1 0x00020000 // ADC Module 1 Present
+#define SYSCTL_DC1_ADC0 0x00010000 // ADC Module 0 Present
+#define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 // System Clock Divider
+#define SYSCTL_DC1_MINSYSDIV_100 \
+ 0x00001000 // Divide VCO (400MHZ) by 5 minimum
+#define SYSCTL_DC1_MINSYSDIV_66 0x00002000 // Divide VCO (400MHZ) by 2*2 + 2 =
+ // 6 minimum
+#define SYSCTL_DC1_MINSYSDIV_50 0x00003000 // Specifies a 50-MHz CPU clock
+ // with a PLL divider of 4
+#define SYSCTL_DC1_MINSYSDIV_40 0x00004000 // Specifies a 40-MHz CPU clock
+ // with a PLL divider of 5
+#define SYSCTL_DC1_MINSYSDIV_25 0x00007000 // Specifies a 25-MHz clock with a
+ // PLL divider of 8
+#define SYSCTL_DC1_MINSYSDIV_20 0x00009000 // Specifies a 20-MHz clock with a
+ // PLL divider of 10
+#define SYSCTL_DC1_ADC1SPD_M 0x00000C00 // Max ADC1 Speed
+#define SYSCTL_DC1_ADC1SPD_125K 0x00000000 // 125K samples/second
+#define SYSCTL_DC1_ADC1SPD_250K 0x00000400 // 250K samples/second
+#define SYSCTL_DC1_ADC1SPD_500K 0x00000800 // 500K samples/second
+#define SYSCTL_DC1_ADC1SPD_1M 0x00000C00 // 1M samples/second
+#define SYSCTL_DC1_ADC0SPD_M 0x00000300 // Max ADC0 Speed
+#define SYSCTL_DC1_ADC0SPD_125K 0x00000000 // 125K samples/second
+#define SYSCTL_DC1_ADC0SPD_250K 0x00000100 // 250K samples/second
+#define SYSCTL_DC1_ADC0SPD_500K 0x00000200 // 500K samples/second
+#define SYSCTL_DC1_ADC0SPD_1M 0x00000300 // 1M samples/second
+#define SYSCTL_DC1_MPU 0x00000080 // MPU Present
+#define SYSCTL_DC1_HIB 0x00000040 // Hibernation Module Present
+#define SYSCTL_DC1_TEMP 0x00000020 // Temp Sensor Present
+#define SYSCTL_DC1_PLL 0x00000010 // PLL Present
+#define SYSCTL_DC1_WDT0 0x00000008 // Watchdog Timer 0 Present
+#define SYSCTL_DC1_SWO 0x00000004 // SWO Trace Port Present
+#define SYSCTL_DC1_SWD 0x00000002 // SWD Present
+#define SYSCTL_DC1_JTAG 0x00000001 // JTAG Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC2_EPI0 0x40000000 // EPI Module 0 Present
+#define SYSCTL_DC2_I2S0 0x10000000 // I2S Module 0 Present
+#define SYSCTL_DC2_COMP2 0x04000000 // Analog Comparator 2 Present
+#define SYSCTL_DC2_COMP1 0x02000000 // Analog Comparator 1 Present
+#define SYSCTL_DC2_COMP0 0x01000000 // Analog Comparator 0 Present
+#define SYSCTL_DC2_TIMER3 0x00080000 // Timer Module 3 Present
+#define SYSCTL_DC2_TIMER2 0x00040000 // Timer Module 2 Present
+#define SYSCTL_DC2_TIMER1 0x00020000 // Timer Module 1 Present
+#define SYSCTL_DC2_TIMER0 0x00010000 // Timer Module 0 Present
+#define SYSCTL_DC2_I2C1HS 0x00008000 // I2C Module 1 Speed
+#define SYSCTL_DC2_I2C1 0x00004000 // I2C Module 1 Present
+#define SYSCTL_DC2_I2C0HS 0x00002000 // I2C Module 0 Speed
+#define SYSCTL_DC2_I2C0 0x00001000 // I2C Module 0 Present
+#define SYSCTL_DC2_QEI1 0x00000200 // QEI Module 1 Present
+#define SYSCTL_DC2_QEI0 0x00000100 // QEI Module 0 Present
+#define SYSCTL_DC2_SSI1 0x00000020 // SSI Module 1 Present
+#define SYSCTL_DC2_SSI0 0x00000010 // SSI Module 0 Present
+#define SYSCTL_DC2_UART2 0x00000004 // UART Module 2 Present
+#define SYSCTL_DC2_UART1 0x00000002 // UART Module 1 Present
+#define SYSCTL_DC2_UART0 0x00000001 // UART Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC3 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC3_32KHZ 0x80000000 // 32KHz Input Clock Available
+#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 Pin Present
+#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 Pin Present
+#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 Pin Present
+#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 Pin Present
+#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 Pin Present
+#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 Pin Present
+#define SYSCTL_DC3_ADC0AIN7 0x00800000 // ADC Module 0 AIN7 Pin Present
+#define SYSCTL_DC3_ADC0AIN6 0x00400000 // ADC Module 0 AIN6 Pin Present
+#define SYSCTL_DC3_ADC0AIN5 0x00200000 // ADC Module 0 AIN5 Pin Present
+#define SYSCTL_DC3_ADC0AIN4 0x00100000 // ADC Module 0 AIN4 Pin Present
+#define SYSCTL_DC3_ADC0AIN3 0x00080000 // ADC Module 0 AIN3 Pin Present
+#define SYSCTL_DC3_ADC0AIN2 0x00040000 // ADC Module 0 AIN2 Pin Present
+#define SYSCTL_DC3_ADC0AIN1 0x00020000 // ADC Module 0 AIN1 Pin Present
+#define SYSCTL_DC3_ADC0AIN0 0x00010000 // ADC Module 0 AIN0 Pin Present
+#define SYSCTL_DC3_PWMFAULT 0x00008000 // PWM Fault Pin Present
+#define SYSCTL_DC3_C2O 0x00004000 // C2o Pin Present
+#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ Pin Present
+#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- Pin Present
+#define SYSCTL_DC3_C1O 0x00000800 // C1o Pin Present
+#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ Pin Present
+#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- Pin Present
+#define SYSCTL_DC3_C0O 0x00000100 // C0o Pin Present
+#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ Pin Present
+#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- Pin Present
+#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 Pin Present
+#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 Pin Present
+#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 Pin Present
+#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 Pin Present
+#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 Pin Present
+#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 Pin Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC4 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC4_ETH 0x50000000 // Ethernet present
+#define SYSCTL_DC4_EPHY0 0x40000000 // Ethernet PHY Layer 0 Present
+#define SYSCTL_DC4_EMAC0 0x10000000 // Ethernet MAC Layer 0 Present
+#define SYSCTL_DC4_E1588 0x01000000 // 1588 Capable
+#define SYSCTL_DC4_PICAL 0x00040000 // PIOSC Calibrate
+#define SYSCTL_DC4_CCP7 0x00008000 // CCP7 Pin Present
+#define SYSCTL_DC4_CCP6 0x00004000 // CCP6 Pin Present
+#define SYSCTL_DC4_UDMA 0x00002000 // Micro-DMA Module Present
+#define SYSCTL_DC4_ROM 0x00001000 // Internal Code ROM Present
+#define SYSCTL_DC4_GPIOJ 0x00000100 // GPIO Port J Present
+#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO Port H Present
+#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO Port G Present
+#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO Port F Present
+#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO Port E Present
+#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO Port D Present
+#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO Port C Present
+#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO Port B Present
+#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO Port A Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC5 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC5_PWMFAULT3 0x08000000 // PWM Fault 3 Pin Present
+#define SYSCTL_DC5_PWMFAULT2 0x04000000 // PWM Fault 2 Pin Present
+#define SYSCTL_DC5_PWMFAULT1 0x02000000 // PWM Fault 1 Pin Present
+#define SYSCTL_DC5_PWMFAULT0 0x01000000 // PWM Fault 0 Pin Present
+#define SYSCTL_DC5_PWMEFLT 0x00200000 // PWM Extended Fault Active
+#define SYSCTL_DC5_PWMESYNC 0x00100000 // PWM Extended SYNC Active
+#define SYSCTL_DC5_PWM7 0x00000080 // PWM7 Pin Present
+#define SYSCTL_DC5_PWM6 0x00000040 // PWM6 Pin Present
+#define SYSCTL_DC5_PWM5 0x00000020 // PWM5 Pin Present
+#define SYSCTL_DC5_PWM4 0x00000010 // PWM4 Pin Present
+#define SYSCTL_DC5_PWM3 0x00000008 // PWM3 Pin Present
+#define SYSCTL_DC5_PWM2 0x00000004 // PWM2 Pin Present
+#define SYSCTL_DC5_PWM1 0x00000002 // PWM1 Pin Present
+#define SYSCTL_DC5_PWM0 0x00000001 // PWM0 Pin Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC6 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC6_USB0PHY 0x00000010 // USB Module 0 PHY Present
+#define SYSCTL_DC6_USB0_M 0x00000003 // USB Module 0 Present
+#define SYSCTL_DC6_USB0_DEV 0x00000001 // USB0 is Device Only
+#define SYSCTL_DC6_USB0_HOSTDEV 0x00000002 // USB is Device or Host
+#define SYSCTL_DC6_USB0_OTG 0x00000003 // USB0 is OTG
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC7 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC7_SW 0x40000000 // Software transfer on uDMA Ch30
+#define SYSCTL_DC7_DMACH30 0x40000000 // SW
+#define SYSCTL_DC7_DMACH29 0x20000000 // I2S0_TX / CAN1_TX
+#define SYSCTL_DC7_DMACH28 0x10000000 // I2S0_RX / CAN1_RX
+#define SYSCTL_DC7_DMACH27 0x08000000 // CAN1_TX / ADC1_SS3
+#define SYSCTL_DC7_DMACH26 0x04000000 // CAN1_RX / ADC1_SS2
+#define SYSCTL_DC7_DMACH25 0x02000000 // SSI1_TX / ADC1_SS1
+#define SYSCTL_DC7_SSI1_TX 0x02000000 // SSI1 TX on uDMA Ch25
+#define SYSCTL_DC7_SSI1_RX 0x01000000 // SSI1 RX on uDMA Ch24
+#define SYSCTL_DC7_DMACH24 0x01000000 // SSI1_RX / ADC1_SS0
+#define SYSCTL_DC7_UART1_TX 0x00800000 // UART1 TX on uDMA Ch23
+#define SYSCTL_DC7_DMACH23 0x00800000 // UART1_TX / CAN2_TX
+#define SYSCTL_DC7_DMACH22 0x00400000 // UART1_RX / CAN2_RX
+#define SYSCTL_DC7_UART1_RX 0x00400000 // UART1 RX on uDMA Ch22
+#define SYSCTL_DC7_DMACH21 0x00200000 // Timer1B / EPI0_WFIFO
+#define SYSCTL_DC7_DMACH20 0x00100000 // Timer1A / EPI0_NBRFIFO
+#define SYSCTL_DC7_DMACH19 0x00080000 // Timer0B / Timer1B
+#define SYSCTL_DC7_DMACH18 0x00040000 // Timer0A / Timer1A
+#define SYSCTL_DC7_DMACH17 0x00020000 // ADC0_SS3
+#define SYSCTL_DC7_DMACH16 0x00010000 // ADC0_SS2
+#define SYSCTL_DC7_DMACH15 0x00008000 // ADC0_SS1 / Timer2B
+#define SYSCTL_DC7_DMACH14 0x00004000 // ADC0_SS0 / Timer2A
+#define SYSCTL_DC7_DMACH13 0x00002000 // CAN0_TX / UART2_TX
+#define SYSCTL_DC7_DMACH12 0x00001000 // CAN0_RX / UART2_RX
+#define SYSCTL_DC7_SSI0_TX 0x00000800 // SSI0 TX on uDMA Ch11
+#define SYSCTL_DC7_DMACH11 0x00000800 // SSI0_TX / SSI1_TX
+#define SYSCTL_DC7_SSI0_RX 0x00000400 // SSI0 RX on uDMA Ch10
+#define SYSCTL_DC7_DMACH10 0x00000400 // SSI0_RX / SSI1_RX
+#define SYSCTL_DC7_UART0_TX 0x00000200 // UART0 TX on uDMA Ch9
+#define SYSCTL_DC7_DMACH9 0x00000200 // UART0_TX / UART1_TX
+#define SYSCTL_DC7_DMACH8 0x00000100 // UART0_RX / UART1_RX
+#define SYSCTL_DC7_UART0_RX 0x00000100 // UART0 RX on uDMA Ch8
+#define SYSCTL_DC7_DMACH7 0x00000080 // ETH_TX / Timer2B
+#define SYSCTL_DC7_DMACH6 0x00000040 // ETH_RX / Timer2A
+#define SYSCTL_DC7_DMACH5 0x00000020 // USB_EP3_TX / Timer2B
+#define SYSCTL_DC7_USB_EP3_TX 0x00000020 // USB EP3 TX on uDMA Ch5
+#define SYSCTL_DC7_USB_EP3_RX 0x00000010 // USB EP3 RX on uDMA Ch4
+#define SYSCTL_DC7_DMACH4 0x00000010 // USB_EP3_RX / Timer2A
+#define SYSCTL_DC7_USB_EP2_TX 0x00000008 // USB EP2 TX on uDMA Ch3
+#define SYSCTL_DC7_DMACH3 0x00000008 // USB_EP2_TX / Timer3B
+#define SYSCTL_DC7_USB_EP2_RX 0x00000004 // USB EP2 RX on uDMA Ch2
+#define SYSCTL_DC7_DMACH2 0x00000004 // USB_EP2_RX / Timer3A
+#define SYSCTL_DC7_USB_EP1_TX 0x00000002 // USB EP1 TX on uDMA Ch1
+#define SYSCTL_DC7_DMACH1 0x00000002 // USB_EP1_TX / UART2_TX
+#define SYSCTL_DC7_DMACH0 0x00000001 // USB_EP1_RX / UART2_RX
+#define SYSCTL_DC7_USB_EP1_RX 0x00000001 // USB EP1 RX on uDMA Ch0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC8 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC8_ADC1AIN15 0x80000000 // ADC Module 1 AIN15 Pin Present
+#define SYSCTL_DC8_ADC1AIN14 0x40000000 // ADC Module 1 AIN14 Pin Present
+#define SYSCTL_DC8_ADC1AIN13 0x20000000 // ADC Module 1 AIN13 Pin Present
+#define SYSCTL_DC8_ADC1AIN12 0x10000000 // ADC Module 1 AIN12 Pin Present
+#define SYSCTL_DC8_ADC1AIN11 0x08000000 // ADC Module 1 AIN11 Pin Present
+#define SYSCTL_DC8_ADC1AIN10 0x04000000 // ADC Module 1 AIN10 Pin Present
+#define SYSCTL_DC8_ADC1AIN9 0x02000000 // ADC Module 1 AIN9 Pin Present
+#define SYSCTL_DC8_ADC1AIN8 0x01000000 // ADC Module 1 AIN8 Pin Present
+#define SYSCTL_DC8_ADC1AIN7 0x00800000 // ADC Module 1 AIN7 Pin Present
+#define SYSCTL_DC8_ADC1AIN6 0x00400000 // ADC Module 1 AIN6 Pin Present
+#define SYSCTL_DC8_ADC1AIN5 0x00200000 // ADC Module 1 AIN5 Pin Present
+#define SYSCTL_DC8_ADC1AIN4 0x00100000 // ADC Module 1 AIN4 Pin Present
+#define SYSCTL_DC8_ADC1AIN3 0x00080000 // ADC Module 1 AIN3 Pin Present
+#define SYSCTL_DC8_ADC1AIN2 0x00040000 // ADC Module 1 AIN2 Pin Present
+#define SYSCTL_DC8_ADC1AIN1 0x00020000 // ADC Module 1 AIN1 Pin Present
+#define SYSCTL_DC8_ADC1AIN0 0x00010000 // ADC Module 1 AIN0 Pin Present
+#define SYSCTL_DC8_ADC0AIN15 0x00008000 // ADC Module 0 AIN15 Pin Present
+#define SYSCTL_DC8_ADC0AIN14 0x00004000 // ADC Module 0 AIN14 Pin Present
+#define SYSCTL_DC8_ADC0AIN13 0x00002000 // ADC Module 0 AIN13 Pin Present
+#define SYSCTL_DC8_ADC0AIN12 0x00001000 // ADC Module 0 AIN12 Pin Present
+#define SYSCTL_DC8_ADC0AIN11 0x00000800 // ADC Module 0 AIN11 Pin Present
+#define SYSCTL_DC8_ADC0AIN10 0x00000400 // ADC Module 0 AIN10 Pin Present
+#define SYSCTL_DC8_ADC0AIN9 0x00000200 // ADC Module 0 AIN9 Pin Present
+#define SYSCTL_DC8_ADC0AIN8 0x00000100 // ADC Module 0 AIN8 Pin Present
+#define SYSCTL_DC8_ADC0AIN7 0x00000080 // ADC Module 0 AIN7 Pin Present
+#define SYSCTL_DC8_ADC0AIN6 0x00000040 // ADC Module 0 AIN6 Pin Present
+#define SYSCTL_DC8_ADC0AIN5 0x00000020 // ADC Module 0 AIN5 Pin Present
+#define SYSCTL_DC8_ADC0AIN4 0x00000010 // ADC Module 0 AIN4 Pin Present
+#define SYSCTL_DC8_ADC0AIN3 0x00000008 // ADC Module 0 AIN3 Pin Present
+#define SYSCTL_DC8_ADC0AIN2 0x00000004 // ADC Module 0 AIN2 Pin Present
+#define SYSCTL_DC8_ADC0AIN1 0x00000002 // ADC Module 0 AIN1 Pin Present
+#define SYSCTL_DC8_ADC0AIN0 0x00000001 // ADC Module 0 AIN0 Pin Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PBORCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_PBORCTL_BORTIM_M 0x0000FFFC // BOR Time Delay
+#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR Interrupt or Reset
+#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR Wait and Check for Noise
+#define SYSCTL_PBORCTL_BORTIM_S 2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_LDOPCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_LDOPCTL_M 0x0000003F // LDO Output Voltage
+#define SYSCTL_LDOPCTL_2_50V 0x00000000 // 2.50
+#define SYSCTL_LDOPCTL_2_45V 0x00000001 // 2.45
+#define SYSCTL_LDOPCTL_2_40V 0x00000002 // 2.40
+#define SYSCTL_LDOPCTL_2_35V 0x00000003 // 2.35
+#define SYSCTL_LDOPCTL_2_30V 0x00000004 // 2.30
+#define SYSCTL_LDOPCTL_2_25V 0x00000005 // 2.25
+#define SYSCTL_LDOPCTL_2_75V 0x0000001B // 2.75
+#define SYSCTL_LDOPCTL_2_70V 0x0000001C // 2.70
+#define SYSCTL_LDOPCTL_2_65V 0x0000001D // 2.65
+#define SYSCTL_LDOPCTL_2_60V 0x0000001E // 2.60
+#define SYSCTL_LDOPCTL_2_55V 0x0000001F // 2.55
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR0 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR0_WDT1 0x10000000 // WDT1 Reset Control
+#define SYSCTL_SRCR0_CAN2 0x04000000 // CAN2 Reset Control
+#define SYSCTL_SRCR0_CAN1 0x02000000 // CAN1 Reset Control
+#define SYSCTL_SRCR0_CAN0 0x01000000 // CAN0 Reset Control
+#define SYSCTL_SRCR0_PWM0 0x00100000 // PWM Reset Control
+#define SYSCTL_SRCR0_ADC1 0x00020000 // ADC1 Reset Control
+#define SYSCTL_SRCR0_ADC0 0x00010000 // ADC0 Reset Control
+#define SYSCTL_SRCR0_HIB 0x00000040 // HIB Reset Control
+#define SYSCTL_SRCR0_WDT0 0x00000008 // WDT0 Reset Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR1 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR1_EPI0 0x40000000 // EPI0 Reset Control
+#define SYSCTL_SRCR1_I2S0 0x10000000 // I2S0 Reset Control
+#define SYSCTL_SRCR1_COMP2 0x04000000 // Analog Comp 2 Reset Control
+#define SYSCTL_SRCR1_COMP1 0x02000000 // Analog Comp 1 Reset Control
+#define SYSCTL_SRCR1_COMP0 0x01000000 // Analog Comp 0 Reset Control
+#define SYSCTL_SRCR1_TIMER3 0x00080000 // Timer 3 Reset Control
+#define SYSCTL_SRCR1_TIMER2 0x00040000 // Timer 2 Reset Control
+#define SYSCTL_SRCR1_TIMER1 0x00020000 // Timer 1 Reset Control
+#define SYSCTL_SRCR1_TIMER0 0x00010000 // Timer 0 Reset Control
+#define SYSCTL_SRCR1_I2C1 0x00004000 // I2C1 Reset Control
+#define SYSCTL_SRCR1_I2C0 0x00001000 // I2C0 Reset Control
+#define SYSCTL_SRCR1_QEI1 0x00000200 // QEI1 Reset Control
+#define SYSCTL_SRCR1_QEI0 0x00000100 // QEI0 Reset Control
+#define SYSCTL_SRCR1_SSI1 0x00000020 // SSI1 Reset Control
+#define SYSCTL_SRCR1_SSI0 0x00000010 // SSI0 Reset Control
+#define SYSCTL_SRCR1_UART2 0x00000004 // UART2 Reset Control
+#define SYSCTL_SRCR1_UART1 0x00000002 // UART1 Reset Control
+#define SYSCTL_SRCR1_UART0 0x00000001 // UART0 Reset Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR2 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR2_EPHY0 0x40000000 // PHY0 Reset Control
+#define SYSCTL_SRCR2_EMAC0 0x10000000 // MAC0 Reset Control
+#define SYSCTL_SRCR2_USB0 0x00010000 // USB0 Reset Control
+#define SYSCTL_SRCR2_UDMA 0x00002000 // Micro-DMA Reset Control
+#define SYSCTL_SRCR2_GPIOJ 0x00000100 // Port J Reset Control
+#define SYSCTL_SRCR2_GPIOH 0x00000080 // Port H Reset Control
+#define SYSCTL_SRCR2_GPIOG 0x00000040 // Port G Reset Control
+#define SYSCTL_SRCR2_GPIOF 0x00000020 // Port F Reset Control
+#define SYSCTL_SRCR2_GPIOE 0x00000010 // Port E Reset Control
+#define SYSCTL_SRCR2_GPIOD 0x00000008 // Port D Reset Control
+#define SYSCTL_SRCR2_GPIOC 0x00000004 // Port C Reset Control
+#define SYSCTL_SRCR2_GPIOB 0x00000002 // Port B Reset Control
+#define SYSCTL_SRCR2_GPIOA 0x00000001 // Port A Reset Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RIS register.
+//
+//*****************************************************************************
+#define SYSCTL_RIS_MOSCPUPRIS 0x00000100 // MOSC Power Up Raw Interrupt
+ // Status
+#define SYSCTL_RIS_USBPLLLRIS 0x00000080 // USB PLL Lock Raw Interrupt
+ // Status
+#define SYSCTL_RIS_PLLLRIS 0x00000040 // PLL Lock Raw Interrupt Status
+#define SYSCTL_RIS_CLRIS 0x00000020 // Current Limit Raw Interrupt
+ // Status
+#define SYSCTL_RIS_IOFRIS 0x00000010 // Internal Oscillator Fault Raw
+ // Interrupt Status
+#define SYSCTL_RIS_MOFRIS 0x00000008 // Main Oscillator Fault Raw
+ // Interrupt Status
+#define SYSCTL_RIS_LDORIS 0x00000004 // LDO Power Unregulated Raw
+ // Interrupt Status
+#define SYSCTL_RIS_BORRIS 0x00000002 // Brown-Out Reset Raw Interrupt
+ // Status
+#define SYSCTL_RIS_PLLFRIS 0x00000001 // PLL Fault Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_IMC register.
+//
+//*****************************************************************************
+#define SYSCTL_IMC_MOSCPUPIM 0x00000100 // MOSC Power Up Interrupt Mask
+#define SYSCTL_IMC_USBPLLLIM 0x00000080 // USB PLL Lock Interrupt Mask
+#define SYSCTL_IMC_PLLLIM 0x00000040 // PLL Lock Interrupt Mask
+#define SYSCTL_IMC_CLIM 0x00000020 // Current Limit Interrupt Mask
+#define SYSCTL_IMC_IOFIM 0x00000010 // Internal Oscillator Fault
+ // Interrupt Mask
+#define SYSCTL_IMC_MOFIM 0x00000008 // Main Oscillator Fault Interrupt
+ // Mask
+#define SYSCTL_IMC_LDOIM 0x00000004 // LDO Power Unregulated Interrupt
+ // Mask
+#define SYSCTL_IMC_BORIM 0x00000002 // Brown-Out Reset Interrupt Mask
+#define SYSCTL_IMC_PLLFIM 0x00000001 // PLL Fault Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_MISC register.
+//
+//*****************************************************************************
+#define SYSCTL_MISC_MOSCPUPMIS 0x00000100 // MOSC Power Up Masked Interrupt
+ // Status
+#define SYSCTL_MISC_USBPLLLMIS 0x00000080 // USB PLL Lock Masked Interrupt
+ // Status
+#define SYSCTL_MISC_PLLLMIS 0x00000040 // PLL Lock Masked Interrupt Status
+#define SYSCTL_MISC_CLMIS 0x00000020 // Current Limit Masked Interrupt
+ // Status
+#define SYSCTL_MISC_IOFMIS 0x00000010 // Internal Oscillator Fault Masked
+ // Interrupt Status
+#define SYSCTL_MISC_MOFMIS 0x00000008 // Main Oscillator Fault Masked
+ // Interrupt Status
+#define SYSCTL_MISC_LDOMIS 0x00000004 // LDO Power Unregulated Masked
+ // Interrupt Status
+#define SYSCTL_MISC_BORMIS 0x00000002 // BOR Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RESC register.
+//
+//*****************************************************************************
+#define SYSCTL_RESC_MOSCFAIL 0x00010000 // MOSC Failure Reset
+#define SYSCTL_RESC_LDO 0x00000020 // LDO Reset
+#define SYSCTL_RESC_WDT1 0x00000020 // Watchdog Timer 1 Reset
+#define SYSCTL_RESC_SW 0x00000010 // Software Reset
+#define SYSCTL_RESC_WDT0 0x00000008 // Watchdog Timer 0 Reset
+#define SYSCTL_RESC_BOR 0x00000004 // Brown-Out Reset
+#define SYSCTL_RESC_POR 0x00000002 // Power-On Reset
+#define SYSCTL_RESC_EXT 0x00000001 // External Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCC register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC_ACG 0x08000000 // Auto Clock Gating
+#define SYSCTL_RCC_SYSDIV_M 0x07800000 // System Clock Divisor
+#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2
+#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3
+#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4
+#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5
+#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6
+#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7
+#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8
+#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9
+#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10
+#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11
+#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12
+#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13
+#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14
+#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15
+#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16
+#define SYSCTL_RCC_USESYSDIV 0x00400000 // Enable System Clock Divider
+#define SYSCTL_RCC_USEPWMDIV 0x00100000 // Enable PWM Clock Divisor
+#define SYSCTL_RCC_PWMDIV_M 0x000E0000 // PWM Unit Clock Divisor
+#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2
+#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4
+#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8
+#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16
+#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32
+#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64
+#define SYSCTL_RCC_PWRDN 0x00002000 // PLL Power Down
+#define SYSCTL_RCC_OEN 0x00001000 // PLL Output Enable
+#define SYSCTL_RCC_BYPASS 0x00000800 // PLL Bypass
+#define SYSCTL_RCC_XTAL_M 0x000007C0 // Crystal Value
+#define SYSCTL_RCC_XTAL_1MHZ 0x00000000 // 1 MHz
+#define SYSCTL_RCC_XTAL_1_84MHZ 0x00000040 // 1.8432 MHz
+#define SYSCTL_RCC_XTAL_2MHZ 0x00000080 // 2 MHz
+#define SYSCTL_RCC_XTAL_2_45MHZ 0x000000C0 // 2.4576 MHz
+#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // 3.579545 MHz
+#define SYSCTL_RCC_XTAL_3_68MHZ 0x00000140 // 3.6864 MHz
+#define SYSCTL_RCC_XTAL_4MHZ 0x00000180 // 4 MHz
+#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // 4.096 MHz
+#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // 4.9152 MHz
+#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // 5 MHz
+#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // 5.12 MHz
+#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // 6 MHz
+#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // 6.144 MHz
+#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // 7.3728 MHz
+#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // 8 MHz
+#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // 8.192 MHz
+#define SYSCTL_RCC_XTAL_10MHZ 0x00000400 // 10 MHz
+#define SYSCTL_RCC_XTAL_12MHZ 0x00000440 // 12 MHz
+#define SYSCTL_RCC_XTAL_12_2MHZ 0x00000480 // 12.288 MHz
+#define SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0 // 13.56 MHz
+#define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500 // 14.31818 MHz
+#define SYSCTL_RCC_XTAL_16MHZ 0x00000540 // 16 MHz
+#define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580 // 16.384 MHz
+#define SYSCTL_RCC_XTAL_18MHZ 0x000005C0 // 18.0 MHz
+#define SYSCTL_RCC_XTAL_20MHZ 0x00000600 // 20.0 MHz
+#define SYSCTL_RCC_XTAL_24MHZ 0x00000640 // 24.0 MHz
+#define SYSCTL_RCC_XTAL_25MHZ 0x00000680 // 25.0 MHz
+#define SYSCTL_RCC_PLLVER 0x00000400 // PLL Verification
+#define SYSCTL_RCC_OSCSRC_M 0x00000030 // Oscillator Source
+#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // MOSC
+#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // IOSC
+#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // IOSC/4
+#define SYSCTL_RCC_OSCSRC_30 0x00000030 // 30 kHz
+#define SYSCTL_RCC_IOSCVER 0x00000008 // Internal Oscillator Verification
+ // Timer
+#define SYSCTL_RCC_MOSCVER 0x00000004 // Main Oscillator Verification
+ // Timer
+#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal Oscillator Disable
+#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main Oscillator Disable
+#define SYSCTL_RCC_SYSDIV_S 23
+#define SYSCTL_RCC_PWMDIV_S 17 // Shift to the PWMDIV field
+#define SYSCTL_RCC_XTAL_S 6 // Shift to the XTAL field
+#define SYSCTL_RCC_OSCSRC_S 4 // Shift to the OSCSRC field
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PLLCFG register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLCFG_OD_M 0x0000C000 // PLL OD Value
+#define SYSCTL_PLLCFG_OD_1 0x00000000 // Divide by 1
+#define SYSCTL_PLLCFG_OD_2 0x00004000 // Divide by 2
+#define SYSCTL_PLLCFG_OD_4 0x00008000 // Divide by 4
+#define SYSCTL_PLLCFG_F_M 0x00003FE0 // PLL F Value
+#define SYSCTL_PLLCFG_R_M 0x0000001F // PLL R Value
+#define SYSCTL_PLLCFG_F_S 5
+#define SYSCTL_PLLCFG_R_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_GPIOHBCTL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_GPIOHBCTL_PORTJ 0x00000100 // Port J Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTH 0x00000080 // Port H Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTG 0x00000040 // Port G Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTF 0x00000020 // Port F Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTE 0x00000010 // Port E Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTD 0x00000008 // Port D Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTC 0x00000004 // Port C Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTB 0x00000002 // Port B Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTA 0x00000001 // Port A Advanced High-Performance
+ // Bus
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2
+#define SYSCTL_RCC2_DIV400 0x40000000 // Divide PLL as 400 MHz vs. 200
+ // MHz
+#define SYSCTL_RCC2_SYSDIV2_M 0x1F800000 // System Clock Divisor 2
+#define SYSCTL_RCC2_SYSDIV2_2 0x00800000 // System clock /2
+#define SYSCTL_RCC2_SYSDIV2_3 0x01000000 // System clock /3
+#define SYSCTL_RCC2_SYSDIV2_4 0x01800000 // System clock /4
+#define SYSCTL_RCC2_SYSDIV2_5 0x02000000 // System clock /5
+#define SYSCTL_RCC2_SYSDIV2_6 0x02800000 // System clock /6
+#define SYSCTL_RCC2_SYSDIV2_7 0x03000000 // System clock /7
+#define SYSCTL_RCC2_SYSDIV2_8 0x03800000 // System clock /8
+#define SYSCTL_RCC2_SYSDIV2_9 0x04000000 // System clock /9
+#define SYSCTL_RCC2_SYSDIV2_10 0x04800000 // System clock /10
+#define SYSCTL_RCC2_SYSDIV2_11 0x05000000 // System clock /11
+#define SYSCTL_RCC2_SYSDIV2_12 0x05800000 // System clock /12
+#define SYSCTL_RCC2_SYSDIV2_13 0x06000000 // System clock /13
+#define SYSCTL_RCC2_SYSDIV2_14 0x06800000 // System clock /14
+#define SYSCTL_RCC2_SYSDIV2_15 0x07000000 // System clock /15
+#define SYSCTL_RCC2_SYSDIV2_16 0x07800000 // System clock /16
+#define SYSCTL_RCC2_SYSDIV2_17 0x08000000 // System clock /17
+#define SYSCTL_RCC2_SYSDIV2_18 0x08800000 // System clock /18
+#define SYSCTL_RCC2_SYSDIV2_19 0x09000000 // System clock /19
+#define SYSCTL_RCC2_SYSDIV2_20 0x09800000 // System clock /20
+#define SYSCTL_RCC2_SYSDIV2_21 0x0A000000 // System clock /21
+#define SYSCTL_RCC2_SYSDIV2_22 0x0A800000 // System clock /22
+#define SYSCTL_RCC2_SYSDIV2_23 0x0B000000 // System clock /23
+#define SYSCTL_RCC2_SYSDIV2_24 0x0B800000 // System clock /24
+#define SYSCTL_RCC2_SYSDIV2_25 0x0C000000 // System clock /25
+#define SYSCTL_RCC2_SYSDIV2_26 0x0C800000 // System clock /26
+#define SYSCTL_RCC2_SYSDIV2_27 0x0D000000 // System clock /27
+#define SYSCTL_RCC2_SYSDIV2_28 0x0D800000 // System clock /28
+#define SYSCTL_RCC2_SYSDIV2_29 0x0E000000 // System clock /29
+#define SYSCTL_RCC2_SYSDIV2_30 0x0E800000 // System clock /30
+#define SYSCTL_RCC2_SYSDIV2_31 0x0F000000 // System clock /31
+#define SYSCTL_RCC2_SYSDIV2_32 0x0F800000 // System clock /32
+#define SYSCTL_RCC2_SYSDIV2_33 0x10000000 // System clock /33
+#define SYSCTL_RCC2_SYSDIV2_34 0x10800000 // System clock /34
+#define SYSCTL_RCC2_SYSDIV2_35 0x11000000 // System clock /35
+#define SYSCTL_RCC2_SYSDIV2_36 0x11800000 // System clock /36
+#define SYSCTL_RCC2_SYSDIV2_37 0x12000000 // System clock /37
+#define SYSCTL_RCC2_SYSDIV2_38 0x12800000 // System clock /38
+#define SYSCTL_RCC2_SYSDIV2_39 0x13000000 // System clock /39
+#define SYSCTL_RCC2_SYSDIV2_40 0x13800000 // System clock /40
+#define SYSCTL_RCC2_SYSDIV2_41 0x14000000 // System clock /41
+#define SYSCTL_RCC2_SYSDIV2_42 0x14800000 // System clock /42
+#define SYSCTL_RCC2_SYSDIV2_43 0x15000000 // System clock /43
+#define SYSCTL_RCC2_SYSDIV2_44 0x15800000 // System clock /44
+#define SYSCTL_RCC2_SYSDIV2_45 0x16000000 // System clock /45
+#define SYSCTL_RCC2_SYSDIV2_46 0x16800000 // System clock /46
+#define SYSCTL_RCC2_SYSDIV2_47 0x17000000 // System clock /47
+#define SYSCTL_RCC2_SYSDIV2_48 0x17800000 // System clock /48
+#define SYSCTL_RCC2_SYSDIV2_49 0x18000000 // System clock /49
+#define SYSCTL_RCC2_SYSDIV2_50 0x18800000 // System clock /50
+#define SYSCTL_RCC2_SYSDIV2_51 0x19000000 // System clock /51
+#define SYSCTL_RCC2_SYSDIV2_52 0x19800000 // System clock /52
+#define SYSCTL_RCC2_SYSDIV2_53 0x1A000000 // System clock /53
+#define SYSCTL_RCC2_SYSDIV2_54 0x1A800000 // System clock /54
+#define SYSCTL_RCC2_SYSDIV2_55 0x1B000000 // System clock /55
+#define SYSCTL_RCC2_SYSDIV2_56 0x1B800000 // System clock /56
+#define SYSCTL_RCC2_SYSDIV2_57 0x1C000000 // System clock /57
+#define SYSCTL_RCC2_SYSDIV2_58 0x1C800000 // System clock /58
+#define SYSCTL_RCC2_SYSDIV2_59 0x1D000000 // System clock /59
+#define SYSCTL_RCC2_SYSDIV2_60 0x1D800000 // System clock /60
+#define SYSCTL_RCC2_SYSDIV2_61 0x1E000000 // System clock /61
+#define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 // System clock /62
+#define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 // System clock /63
+#define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 // System clock /64
+#define SYSCTL_RCC2_SYSDIV2LSB 0x00400000 // Additional LSB for SYSDIV2
+#define SYSCTL_RCC2_USBPWRDN 0x00004000 // Power-Down USB PLL
+#define SYSCTL_RCC2_PWRDN2 0x00002000 // Power-Down PLL 2
+#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL Bypass 2
+#define SYSCTL_RCC2_OSCSRC2_M 0x00000070 // Oscillator Source 2
+#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // MOSC
+#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // PIOSC
+#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // PIOSC/4
+#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // 30 kHz
+#define SYSCTL_RCC2_OSCSRC2_419 0x00000060 // 4.194304 MHz
+#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // 32.768 kHz
+#define SYSCTL_RCC2_SYSDIV2_S 23
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_MOSCCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_MOSCCTL_NOXTAL 0x00000004 // No Crystal Connected
+#define SYSCTL_MOSCCTL_MOSCIM 0x00000002 // MOSC Failure Action
+#define SYSCTL_MOSCCTL_CVAL 0x00000001 // Clock Validation for MOSC
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control
+#define SYSCTL_RCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control
+#define SYSCTL_RCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control
+#define SYSCTL_RCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control
+#define SYSCTL_RCGC0_PWM0 0x00100000 // PWM Clock Gating Control
+#define SYSCTL_RCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control
+#define SYSCTL_RCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control
+#define SYSCTL_RCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed
+#define SYSCTL_RCGC0_ADCSPD125K 0x00000000 // 125K samples/second
+#define SYSCTL_RCGC0_ADCSPD250K 0x00000100 // 250K samples/second
+#define SYSCTL_RCGC0_ADCSPD500K 0x00000200 // 500K samples/second
+#define SYSCTL_RCGC0_ADCSPD1M 0x00000300 // 1M samples/second
+#define SYSCTL_RCGC0_ADC1SPD_M 0x00000C00 // ADC1 Sample Speed
+#define SYSCTL_RCGC0_ADC1SPD_125K \
+ 0x00000000 // 125K samples/second
+#define SYSCTL_RCGC0_ADC1SPD_250K \
+ 0x00000400 // 250K samples/second
+#define SYSCTL_RCGC0_ADC1SPD_500K \
+ 0x00000800 // 500K samples/second
+#define SYSCTL_RCGC0_ADC1SPD_1M 0x00000C00 // 1M samples/second
+#define SYSCTL_RCGC0_ADC0SPD_M 0x00000300 // ADC0 Sample Speed
+#define SYSCTL_RCGC0_ADC0SPD_125K \
+ 0x00000000 // 125K samples/second
+#define SYSCTL_RCGC0_ADC0SPD_250K \
+ 0x00000100 // 250K samples/second
+#define SYSCTL_RCGC0_ADC0SPD_500K \
+ 0x00000200 // 500K samples/second
+#define SYSCTL_RCGC0_ADC0SPD_1M 0x00000300 // 1M samples/second
+#define SYSCTL_RCGC0_HIB 0x00000040 // HIB Clock Gating Control
+#define SYSCTL_RCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC1_EPI0 0x40000000 // EPI0 Clock Gating
+#define SYSCTL_RCGC1_I2S0 0x10000000 // I2S0 Clock Gating
+#define SYSCTL_RCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating
+#define SYSCTL_RCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating
+#define SYSCTL_RCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating
+#define SYSCTL_RCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control
+#define SYSCTL_RCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control
+#define SYSCTL_RCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control
+#define SYSCTL_RCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control
+#define SYSCTL_RCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control
+#define SYSCTL_RCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control
+#define SYSCTL_RCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control
+#define SYSCTL_RCGC1_UART2 0x00000004 // UART2 Clock Gating Control
+#define SYSCTL_RCGC1_UART1 0x00000002 // UART1 Clock Gating Control
+#define SYSCTL_RCGC1_UART0 0x00000001 // UART0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control
+#define SYSCTL_RCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control
+#define SYSCTL_RCGC2_USB0 0x00010000 // USB0 Clock Gating Control
+#define SYSCTL_RCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control
+#define SYSCTL_RCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control
+#define SYSCTL_RCGC2_GPIOH 0x00000080 // Port H Clock Gating Control
+#define SYSCTL_RCGC2_GPIOG 0x00000040 // Port G Clock Gating Control
+#define SYSCTL_RCGC2_GPIOF 0x00000020 // Port F Clock Gating Control
+#define SYSCTL_RCGC2_GPIOE 0x00000010 // Port E Clock Gating Control
+#define SYSCTL_RCGC2_GPIOD 0x00000008 // Port D Clock Gating Control
+#define SYSCTL_RCGC2_GPIOC 0x00000004 // Port C Clock Gating Control
+#define SYSCTL_RCGC2_GPIOB 0x00000002 // Port B Clock Gating Control
+#define SYSCTL_RCGC2_GPIOA 0x00000001 // Port A Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control
+#define SYSCTL_SCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control
+#define SYSCTL_SCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control
+#define SYSCTL_SCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control
+#define SYSCTL_SCGC0_PWM0 0x00100000 // PWM Clock Gating Control
+#define SYSCTL_SCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control
+#define SYSCTL_SCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control
+#define SYSCTL_SCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed
+#define SYSCTL_SCGC0_ADCSPD125K 0x00000000 // 125K samples/second
+#define SYSCTL_SCGC0_ADCSPD250K 0x00000100 // 250K samples/second
+#define SYSCTL_SCGC0_ADCSPD500K 0x00000200 // 500K samples/second
+#define SYSCTL_SCGC0_ADCSPD1M 0x00000300 // 1M samples/second
+#define SYSCTL_SCGC0_ADC1SPD_M 0x00000C00 // ADC1 Sample Speed
+#define SYSCTL_SCGC0_ADC1SPD_125K \
+ 0x00000000 // 125K samples/second
+#define SYSCTL_SCGC0_ADC1SPD_250K \
+ 0x00000400 // 250K samples/second
+#define SYSCTL_SCGC0_ADC1SPD_500K \
+ 0x00000800 // 500K samples/second
+#define SYSCTL_SCGC0_ADC1SPD_1M 0x00000C00 // 1M samples/second
+#define SYSCTL_SCGC0_ADC0SPD_M 0x00000300 // ADC0 Sample Speed
+#define SYSCTL_SCGC0_ADC0SPD_125K \
+ 0x00000000 // 125K samples/second
+#define SYSCTL_SCGC0_ADC0SPD_250K \
+ 0x00000100 // 250K samples/second
+#define SYSCTL_SCGC0_ADC0SPD_500K \
+ 0x00000200 // 500K samples/second
+#define SYSCTL_SCGC0_ADC0SPD_1M 0x00000300 // 1M samples/second
+#define SYSCTL_SCGC0_HIB 0x00000040 // HIB Clock Gating Control
+#define SYSCTL_SCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC1_EPI0 0x40000000 // EPI0 Clock Gating
+#define SYSCTL_SCGC1_I2S0 0x10000000 // I2S0 Clock Gating
+#define SYSCTL_SCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating
+#define SYSCTL_SCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating
+#define SYSCTL_SCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating
+#define SYSCTL_SCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control
+#define SYSCTL_SCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control
+#define SYSCTL_SCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control
+#define SYSCTL_SCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control
+#define SYSCTL_SCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control
+#define SYSCTL_SCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control
+#define SYSCTL_SCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control
+#define SYSCTL_SCGC1_UART2 0x00000004 // UART2 Clock Gating Control
+#define SYSCTL_SCGC1_UART1 0x00000002 // UART1 Clock Gating Control
+#define SYSCTL_SCGC1_UART0 0x00000001 // UART0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control
+#define SYSCTL_SCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control
+#define SYSCTL_SCGC2_USB0 0x00010000 // USB0 Clock Gating Control
+#define SYSCTL_SCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control
+#define SYSCTL_SCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control
+#define SYSCTL_SCGC2_GPIOH 0x00000080 // Port H Clock Gating Control
+#define SYSCTL_SCGC2_GPIOG 0x00000040 // Port G Clock Gating Control
+#define SYSCTL_SCGC2_GPIOF 0x00000020 // Port F Clock Gating Control
+#define SYSCTL_SCGC2_GPIOE 0x00000010 // Port E Clock Gating Control
+#define SYSCTL_SCGC2_GPIOD 0x00000008 // Port D Clock Gating Control
+#define SYSCTL_SCGC2_GPIOC 0x00000004 // Port C Clock Gating Control
+#define SYSCTL_SCGC2_GPIOB 0x00000002 // Port B Clock Gating Control
+#define SYSCTL_SCGC2_GPIOA 0x00000001 // Port A Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control
+#define SYSCTL_DCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control
+#define SYSCTL_DCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control
+#define SYSCTL_DCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control
+#define SYSCTL_DCGC0_PWM0 0x00100000 // PWM Clock Gating Control
+#define SYSCTL_DCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control
+#define SYSCTL_DCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control
+#define SYSCTL_DCGC0_HIB 0x00000040 // HIB Clock Gating Control
+#define SYSCTL_DCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC1_EPI0 0x40000000 // EPI0 Clock Gating
+#define SYSCTL_DCGC1_I2S0 0x10000000 // I2S0 Clock Gating
+#define SYSCTL_DCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating
+#define SYSCTL_DCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating
+#define SYSCTL_DCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating
+#define SYSCTL_DCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control
+#define SYSCTL_DCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control
+#define SYSCTL_DCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control
+#define SYSCTL_DCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control
+#define SYSCTL_DCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control
+#define SYSCTL_DCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control
+#define SYSCTL_DCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control
+#define SYSCTL_DCGC1_UART2 0x00000004 // UART2 Clock Gating Control
+#define SYSCTL_DCGC1_UART1 0x00000002 // UART1 Clock Gating Control
+#define SYSCTL_DCGC1_UART0 0x00000001 // UART0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control
+#define SYSCTL_DCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control
+#define SYSCTL_DCGC2_USB0 0x00010000 // USB0 Clock Gating Control
+#define SYSCTL_DCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control
+#define SYSCTL_DCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control
+#define SYSCTL_DCGC2_GPIOH 0x00000080 // Port H Clock Gating Control
+#define SYSCTL_DCGC2_GPIOG 0x00000040 // Port G Clock Gating Control
+#define SYSCTL_DCGC2_GPIOF 0x00000020 // Port F Clock Gating Control
+#define SYSCTL_DCGC2_GPIOE 0x00000010 // Port E Clock Gating Control
+#define SYSCTL_DCGC2_GPIOD 0x00000008 // Port D Clock Gating Control
+#define SYSCTL_DCGC2_GPIOC 0x00000004 // Port C Clock Gating Control
+#define SYSCTL_DCGC2_GPIOB 0x00000002 // Port B Clock Gating Control
+#define SYSCTL_DCGC2_GPIOA 0x00000001 // Port A Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DSLPCLKCFG_D_M 0x1F800000 // Divider Field Override
+#define SYSCTL_DSLPCLKCFG_D_1 0x00000000 // System clock /1
+#define SYSCTL_DSLPCLKCFG_D_2 0x00800000 // System clock /2
+#define SYSCTL_DSLPCLKCFG_D_3 0x01000000 // System clock /3
+#define SYSCTL_DSLPCLKCFG_D_4 0x01800000 // System clock /4
+#define SYSCTL_DSLPCLKCFG_D_5 0x02000000 // System clock /5
+#define SYSCTL_DSLPCLKCFG_D_6 0x02800000 // System clock /6
+#define SYSCTL_DSLPCLKCFG_D_7 0x03000000 // System clock /7
+#define SYSCTL_DSLPCLKCFG_D_8 0x03800000 // System clock /8
+#define SYSCTL_DSLPCLKCFG_D_9 0x04000000 // System clock /9
+#define SYSCTL_DSLPCLKCFG_D_10 0x04800000 // System clock /10
+#define SYSCTL_DSLPCLKCFG_D_11 0x05000000 // System clock /11
+#define SYSCTL_DSLPCLKCFG_D_12 0x05800000 // System clock /12
+#define SYSCTL_DSLPCLKCFG_D_13 0x06000000 // System clock /13
+#define SYSCTL_DSLPCLKCFG_D_14 0x06800000 // System clock /14
+#define SYSCTL_DSLPCLKCFG_D_15 0x07000000 // System clock /15
+#define SYSCTL_DSLPCLKCFG_D_16 0x07800000 // System clock /16
+#define SYSCTL_DSLPCLKCFG_D_17 0x08000000 // System clock /17
+#define SYSCTL_DSLPCLKCFG_D_18 0x08800000 // System clock /18
+#define SYSCTL_DSLPCLKCFG_D_19 0x09000000 // System clock /19
+#define SYSCTL_DSLPCLKCFG_D_20 0x09800000 // System clock /20
+#define SYSCTL_DSLPCLKCFG_D_21 0x0A000000 // System clock /21
+#define SYSCTL_DSLPCLKCFG_D_22 0x0A800000 // System clock /22
+#define SYSCTL_DSLPCLKCFG_D_23 0x0B000000 // System clock /23
+#define SYSCTL_DSLPCLKCFG_D_24 0x0B800000 // System clock /24
+#define SYSCTL_DSLPCLKCFG_D_25 0x0C000000 // System clock /25
+#define SYSCTL_DSLPCLKCFG_D_26 0x0C800000 // System clock /26
+#define SYSCTL_DSLPCLKCFG_D_27 0x0D000000 // System clock /27
+#define SYSCTL_DSLPCLKCFG_D_28 0x0D800000 // System clock /28
+#define SYSCTL_DSLPCLKCFG_D_29 0x0E000000 // System clock /29
+#define SYSCTL_DSLPCLKCFG_D_30 0x0E800000 // System clock /30
+#define SYSCTL_DSLPCLKCFG_D_31 0x0F000000 // System clock /31
+#define SYSCTL_DSLPCLKCFG_D_32 0x0F800000 // System clock /32
+#define SYSCTL_DSLPCLKCFG_D_33 0x10000000 // System clock /33
+#define SYSCTL_DSLPCLKCFG_D_34 0x10800000 // System clock /34
+#define SYSCTL_DSLPCLKCFG_D_35 0x11000000 // System clock /35
+#define SYSCTL_DSLPCLKCFG_D_36 0x11800000 // System clock /36
+#define SYSCTL_DSLPCLKCFG_D_37 0x12000000 // System clock /37
+#define SYSCTL_DSLPCLKCFG_D_38 0x12800000 // System clock /38
+#define SYSCTL_DSLPCLKCFG_D_39 0x13000000 // System clock /39
+#define SYSCTL_DSLPCLKCFG_D_40 0x13800000 // System clock /40
+#define SYSCTL_DSLPCLKCFG_D_41 0x14000000 // System clock /41
+#define SYSCTL_DSLPCLKCFG_D_42 0x14800000 // System clock /42
+#define SYSCTL_DSLPCLKCFG_D_43 0x15000000 // System clock /43
+#define SYSCTL_DSLPCLKCFG_D_44 0x15800000 // System clock /44
+#define SYSCTL_DSLPCLKCFG_D_45 0x16000000 // System clock /45
+#define SYSCTL_DSLPCLKCFG_D_46 0x16800000 // System clock /46
+#define SYSCTL_DSLPCLKCFG_D_47 0x17000000 // System clock /47
+#define SYSCTL_DSLPCLKCFG_D_48 0x17800000 // System clock /48
+#define SYSCTL_DSLPCLKCFG_D_49 0x18000000 // System clock /49
+#define SYSCTL_DSLPCLKCFG_D_50 0x18800000 // System clock /50
+#define SYSCTL_DSLPCLKCFG_D_51 0x19000000 // System clock /51
+#define SYSCTL_DSLPCLKCFG_D_52 0x19800000 // System clock /52
+#define SYSCTL_DSLPCLKCFG_D_53 0x1A000000 // System clock /53
+#define SYSCTL_DSLPCLKCFG_D_54 0x1A800000 // System clock /54
+#define SYSCTL_DSLPCLKCFG_D_55 0x1B000000 // System clock /55
+#define SYSCTL_DSLPCLKCFG_D_56 0x1B800000 // System clock /56
+#define SYSCTL_DSLPCLKCFG_D_57 0x1C000000 // System clock /57
+#define SYSCTL_DSLPCLKCFG_D_58 0x1C800000 // System clock /58
+#define SYSCTL_DSLPCLKCFG_D_59 0x1D000000 // System clock /59
+#define SYSCTL_DSLPCLKCFG_D_60 0x1D800000 // System clock /60
+#define SYSCTL_DSLPCLKCFG_D_61 0x1E000000 // System clock /61
+#define SYSCTL_DSLPCLKCFG_D_62 0x1E800000 // System clock /62
+#define SYSCTL_DSLPCLKCFG_D_63 0x1F000000 // System clock /63
+#define SYSCTL_DSLPCLKCFG_D_64 0x1F800000 // System clock /64
+#define SYSCTL_DSLPCLKCFG_O_M 0x00000070 // Clock Source
+#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // MOSC
+#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // PIOSC
+#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // 30 kHz
+#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // 32.768 kHz
+#define SYSCTL_DSLPCLKCFG_PIOSCPD \
+ 0x00000002 // PIOSC Power Down Request
+#define SYSCTL_DSLPCLKCFG_IOSC 0x00000001 // IOSC Clock Source
+#define SYSCTL_DSLPCLKCFG_D_S 23
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SYSPROP register.
+//
+//*****************************************************************************
+#define SYSCTL_SYSPROP_FPU 0x00000001 // FPU Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PIOSCCAL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PIOSCCAL_UTEN 0x80000000 // Use User Trim Value
+#define SYSCTL_PIOSCCAL_CAL 0x00000200 // Start Calibration
+#define SYSCTL_PIOSCCAL_UPDATE 0x00000100 // Update Trim
+#define SYSCTL_PIOSCCAL_UT_M 0x0000007F // User Trim Value
+#define SYSCTL_PIOSCCAL_UT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_CLKVCLR register.
+//
+//*****************************************************************************
+#define SYSCTL_CLKVCLR_VERCLR 0x00000001 // Clock Verification Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PIOSCSTAT
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PIOSCSTAT_DT_M 0x007F0000 // Default Trim Value
+#define SYSCTL_PIOSCSTAT_CR_M 0x00000300 // Calibration Result
+#define SYSCTL_PIOSCSTAT_CRNONE 0x00000000 // Calibration has not been
+ // attempted
+#define SYSCTL_PIOSCSTAT_CRPASS 0x00000100 // The last calibration operation
+ // completed to meet 1% accuracy
+#define SYSCTL_PIOSCSTAT_CRFAIL 0x00000200 // The last calibration operation
+ // failed to meet 1% accuracy
+#define SYSCTL_PIOSCSTAT_CT_M 0x0000007F // Calibration Trim Value
+#define SYSCTL_PIOSCSTAT_DT_S 16
+#define SYSCTL_PIOSCSTAT_CT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_LDOARST register.
+//
+//*****************************************************************************
+#define SYSCTL_LDOARST_LDOARST 0x00000001 // LDO Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PLLFREQ0
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLFREQ0_MFRAC_M 0x000FFC00 // PLL M Fractional Value
+#define SYSCTL_PLLFREQ0_MINT_M 0x000003FF // PLL M Integer Value
+#define SYSCTL_PLLFREQ0_MFRAC_S 10
+#define SYSCTL_PLLFREQ0_MINT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PLLFREQ1
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLFREQ1_Q_M 0x00001F00 // PLL Q Value
+#define SYSCTL_PLLFREQ1_N_M 0x0000001F // PLL N Value
+#define SYSCTL_PLLFREQ1_Q_S 8
+#define SYSCTL_PLLFREQ1_N_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PLLSTAT register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLSTAT_LOCK 0x00000001 // PLL Lock
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_I2SMCLKCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_I2SMCLKCFG_RXEN 0x80000000 // RX Clock Enable
+#define SYSCTL_I2SMCLKCFG_RXI_M 0x3FF00000 // RX Clock Integer Input
+#define SYSCTL_I2SMCLKCFG_RXF_M 0x000F0000 // RX Clock Fractional Input
+#define SYSCTL_I2SMCLKCFG_TXEN 0x00008000 // TX Clock Enable
+#define SYSCTL_I2SMCLKCFG_TXI_M 0x00003FF0 // TX Clock Integer Input
+#define SYSCTL_I2SMCLKCFG_TXF_M 0x0000000F // TX Clock Fractional Input
+#define SYSCTL_I2SMCLKCFG_RXI_S 20
+#define SYSCTL_I2SMCLKCFG_RXF_S 16
+#define SYSCTL_I2SMCLKCFG_TXI_S 4
+#define SYSCTL_I2SMCLKCFG_TXF_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC9 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC9_ADC1DC7 0x00800000 // ADC1 DC7 Present
+#define SYSCTL_DC9_ADC1DC6 0x00400000 // ADC1 DC6 Present
+#define SYSCTL_DC9_ADC1DC5 0x00200000 // ADC1 DC5 Present
+#define SYSCTL_DC9_ADC1DC4 0x00100000 // ADC1 DC4 Present
+#define SYSCTL_DC9_ADC1DC3 0x00080000 // ADC1 DC3 Present
+#define SYSCTL_DC9_ADC1DC2 0x00040000 // ADC1 DC2 Present
+#define SYSCTL_DC9_ADC1DC1 0x00020000 // ADC1 DC1 Present
+#define SYSCTL_DC9_ADC1DC0 0x00010000 // ADC1 DC0 Present
+#define SYSCTL_DC9_ADC0DC7 0x00000080 // ADC0 DC7 Present
+#define SYSCTL_DC9_ADC0DC6 0x00000040 // ADC0 DC6 Present
+#define SYSCTL_DC9_ADC0DC5 0x00000020 // ADC0 DC5 Present
+#define SYSCTL_DC9_ADC0DC4 0x00000010 // ADC0 DC4 Present
+#define SYSCTL_DC9_ADC0DC3 0x00000008 // ADC0 DC3 Present
+#define SYSCTL_DC9_ADC0DC2 0x00000004 // ADC0 DC2 Present
+#define SYSCTL_DC9_ADC0DC1 0x00000002 // ADC0 DC1 Present
+#define SYSCTL_DC9_ADC0DC0 0x00000001 // ADC0 DC0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_NVMSTAT register.
+//
+//*****************************************************************************
+#define SYSCTL_NVMSTAT_TPSW 0x00000010 // Third Party Software Present
+#define SYSCTL_NVMSTAT_FWB 0x00000001 // 32 Word Flash Write Buffer
+ // Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPWD register.
+//
+//*****************************************************************************
+#define SYSCTL_PPWD_P1 0x00000002 // Watchdog Timer 1 Present
+#define SYSCTL_PPWD_P0 0x00000001 // Watchdog Timer 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPTIMER register.
+//
+//*****************************************************************************
+#define SYSCTL_PPTIMER_P5 0x00000020 // Timer 5 Present
+#define SYSCTL_PPTIMER_P4 0x00000010 // Timer 4 Present
+#define SYSCTL_PPTIMER_P3 0x00000008 // Timer 3 Present
+#define SYSCTL_PPTIMER_P2 0x00000004 // Timer 2 Present
+#define SYSCTL_PPTIMER_P1 0x00000002 // Timer 1 Present
+#define SYSCTL_PPTIMER_P0 0x00000001 // Timer 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPGPIO register.
+//
+//*****************************************************************************
+#define SYSCTL_PPGPIO_P14 0x00004000 // GPIO Port Q Present
+#define SYSCTL_PPGPIO_P13 0x00002000 // GPIO Port P Present
+#define SYSCTL_PPGPIO_P12 0x00001000 // GPIO Port N Present
+#define SYSCTL_PPGPIO_P11 0x00000800 // GPIO Port M Present
+#define SYSCTL_PPGPIO_P10 0x00000400 // GPIO Port L Present
+#define SYSCTL_PPGPIO_P9 0x00000200 // GPIO Port K Present
+#define SYSCTL_PPGPIO_P8 0x00000100 // GPIO Port J Present
+#define SYSCTL_PPGPIO_P7 0x00000080 // GPIO Port H Present
+#define SYSCTL_PPGPIO_P6 0x00000040 // GPIO Port G Present
+#define SYSCTL_PPGPIO_P5 0x00000020 // GPIO Port F Present
+#define SYSCTL_PPGPIO_P4 0x00000010 // GPIO Port E Present
+#define SYSCTL_PPGPIO_P3 0x00000008 // GPIO Port D Present
+#define SYSCTL_PPGPIO_P2 0x00000004 // GPIO Port C Present
+#define SYSCTL_PPGPIO_P1 0x00000002 // GPIO Port B Present
+#define SYSCTL_PPGPIO_P0 0x00000001 // GPIO Port A Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_PPDMA_P0 0x00000001 // uDMA Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_PPHIB_P0 0x00000001 // Hibernation Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPUART register.
+//
+//*****************************************************************************
+#define SYSCTL_PPUART_P7 0x00000080 // UART Module 7 Present
+#define SYSCTL_PPUART_P6 0x00000040 // UART Module 6 Present
+#define SYSCTL_PPUART_P5 0x00000020 // UART Module 5 Present
+#define SYSCTL_PPUART_P4 0x00000010 // UART Module 4 Present
+#define SYSCTL_PPUART_P3 0x00000008 // UART Module 3 Present
+#define SYSCTL_PPUART_P2 0x00000004 // UART Module 2 Present
+#define SYSCTL_PPUART_P1 0x00000002 // UART Module 1 Present
+#define SYSCTL_PPUART_P0 0x00000001 // UART Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_PPSSI_P3 0x00000008 // SSI Module 3 Present
+#define SYSCTL_PPSSI_P2 0x00000004 // SSI Module 2 Present
+#define SYSCTL_PPSSI_P1 0x00000002 // SSI Module 1 Present
+#define SYSCTL_PPSSI_P0 0x00000001 // SSI Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_PPI2C_P5 0x00000020 // I2C Module 5 Present
+#define SYSCTL_PPI2C_P4 0x00000010 // I2C Module 4 Present
+#define SYSCTL_PPI2C_P3 0x00000008 // I2C Module 3 Present
+#define SYSCTL_PPI2C_P2 0x00000004 // I2C Module 2 Present
+#define SYSCTL_PPI2C_P1 0x00000002 // I2C Module 1 Present
+#define SYSCTL_PPI2C_P0 0x00000001 // I2C Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_PPUSB_P0 0x00000001 // USB Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_PPCAN_P1 0x00000002 // CAN Module 1 Present
+#define SYSCTL_PPCAN_P0 0x00000001 // CAN Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPADC register.
+//
+//*****************************************************************************
+#define SYSCTL_PPADC_P1 0x00000002 // ADC Module 1 Present
+#define SYSCTL_PPADC_P0 0x00000001 // ADC Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPACMP register.
+//
+//*****************************************************************************
+#define SYSCTL_PPACMP_P0 0x00000001 // Analog Comparator Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_PPPWM_P1 0x00000002 // PWM Module 1 Present
+#define SYSCTL_PPPWM_P0 0x00000001 // PWM Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_PPQEI_P1 0x00000002 // QEI Module 1 Present
+#define SYSCTL_PPQEI_P0 0x00000001 // QEI Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPLPC register.
+//
+//*****************************************************************************
+#define SYSCTL_PPLPC_P0 0x00000001 // LPC Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPPECI register.
+//
+//*****************************************************************************
+#define SYSCTL_PPPECI_P0 0x00000001 // PECI Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPFAN register.
+//
+//*****************************************************************************
+#define SYSCTL_PPFAN_P0 0x00000001 // FAN Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PPEEPROM_P0 0x00000001 // EEPROM Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PPWTIMER_P5 0x00000020 // Wide Timer 5 Present
+#define SYSCTL_PPWTIMER_P4 0x00000010 // Wide Timer 4 Present
+#define SYSCTL_PPWTIMER_P3 0x00000008 // Wide Timer 3 Present
+#define SYSCTL_PPWTIMER_P2 0x00000004 // Wide Timer 2 Present
+#define SYSCTL_PPWTIMER_P1 0x00000002 // Wide Timer 1 Present
+#define SYSCTL_PPWTIMER_P0 0x00000001 // Wide Timer 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRWD register.
+//
+//*****************************************************************************
+#define SYSCTL_SRWD_R1 0x00000002 // Watchdog Timer 1 Software Reset
+#define SYSCTL_SRWD_R0 0x00000001 // Watchdog Timer 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRTIMER register.
+//
+//*****************************************************************************
+#define SYSCTL_SRTIMER_R5 0x00000020 // Timer 5 Software Reset
+#define SYSCTL_SRTIMER_R4 0x00000010 // Timer 4 Software Reset
+#define SYSCTL_SRTIMER_R3 0x00000008 // Timer 3 Software Reset
+#define SYSCTL_SRTIMER_R2 0x00000004 // Timer 2 Software Reset
+#define SYSCTL_SRTIMER_R1 0x00000002 // Timer 1 Software Reset
+#define SYSCTL_SRTIMER_R0 0x00000001 // Timer 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRGPIO register.
+//
+//*****************************************************************************
+#define SYSCTL_SRGPIO_R14 0x00004000 // GPIO Port Q Software Reset
+#define SYSCTL_SRGPIO_R13 0x00002000 // GPIO Port P Software Reset
+#define SYSCTL_SRGPIO_R12 0x00001000 // GPIO Port N Software Reset
+#define SYSCTL_SRGPIO_R11 0x00000800 // GPIO Port M Software Reset
+#define SYSCTL_SRGPIO_R10 0x00000400 // GPIO Port L Software Reset
+#define SYSCTL_SRGPIO_R9 0x00000200 // GPIO Port K Software Reset
+#define SYSCTL_SRGPIO_R8 0x00000100 // GPIO Port J Software Reset
+#define SYSCTL_SRGPIO_R7 0x00000080 // GPIO Port H Software Reset
+#define SYSCTL_SRGPIO_R6 0x00000040 // GPIO Port G Software Reset
+#define SYSCTL_SRGPIO_R5 0x00000020 // GPIO Port F Software Reset
+#define SYSCTL_SRGPIO_R4 0x00000010 // GPIO Port E Software Reset
+#define SYSCTL_SRGPIO_R3 0x00000008 // GPIO Port D Software Reset
+#define SYSCTL_SRGPIO_R2 0x00000004 // GPIO Port C Software Reset
+#define SYSCTL_SRGPIO_R1 0x00000002 // GPIO Port B Software Reset
+#define SYSCTL_SRGPIO_R0 0x00000001 // GPIO Port A Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_SRDMA_R0 0x00000001 // uDMA Module Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_SRHIB_R0 0x00000001 // Hibernation Module Software
+ // Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRUART register.
+//
+//*****************************************************************************
+#define SYSCTL_SRUART_R7 0x00000080 // UART Module 7 Software Reset
+#define SYSCTL_SRUART_R6 0x00000040 // UART Module 6 Software Reset
+#define SYSCTL_SRUART_R5 0x00000020 // UART Module 5 Software Reset
+#define SYSCTL_SRUART_R4 0x00000010 // UART Module 4 Software Reset
+#define SYSCTL_SRUART_R3 0x00000008 // UART Module 3 Software Reset
+#define SYSCTL_SRUART_R2 0x00000004 // UART Module 2 Software Reset
+#define SYSCTL_SRUART_R1 0x00000002 // UART Module 1 Software Reset
+#define SYSCTL_SRUART_R0 0x00000001 // UART Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_SRSSI_R3 0x00000008 // SSI Module 3 Software Reset
+#define SYSCTL_SRSSI_R2 0x00000004 // SSI Module 2 Software Reset
+#define SYSCTL_SRSSI_R1 0x00000002 // SSI Module 1 Software Reset
+#define SYSCTL_SRSSI_R0 0x00000001 // SSI Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_SRI2C_R5 0x00000020 // I2C Module 5 Software Reset
+#define SYSCTL_SRI2C_R4 0x00000010 // I2C Module 4 Software Reset
+#define SYSCTL_SRI2C_R3 0x00000008 // I2C Module 3 Software Reset
+#define SYSCTL_SRI2C_R2 0x00000004 // I2C Module 2 Software Reset
+#define SYSCTL_SRI2C_R1 0x00000002 // I2C Module 1 Software Reset
+#define SYSCTL_SRI2C_R0 0x00000001 // I2C Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_SRUSB_R0 0x00000001 // USB Module Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCAN_R1 0x00000002 // CAN Module 1 Software Reset
+#define SYSCTL_SRCAN_R0 0x00000001 // CAN Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRADC register.
+//
+//*****************************************************************************
+#define SYSCTL_SRADC_R1 0x00000002 // ADC Module 1 Software Reset
+#define SYSCTL_SRADC_R0 0x00000001 // ADC Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRACMP register.
+//
+//*****************************************************************************
+#define SYSCTL_SRACMP_R0 0x00000001 // Analog Comparator Module 0
+ // Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_SRPWM_R1 0x00000002 // PWM Module 1 Software Reset
+#define SYSCTL_SRPWM_R0 0x00000001 // PWM Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_SRQEI_R1 0x00000002 // QEI Module 1 Software Reset
+#define SYSCTL_SRQEI_R0 0x00000001 // QEI Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRLPC register.
+//
+//*****************************************************************************
+#define SYSCTL_SRLPC_R0 0x00000001 // LPC Module Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRPECI register.
+//
+//*****************************************************************************
+#define SYSCTL_SRPECI_R0 0x00000001 // PECI Module Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRFAN register.
+//
+//*****************************************************************************
+#define SYSCTL_SRFAN_R0 0x00000001 // FAN Module Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SREEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SREEPROM_R0 0x00000001 // EEPROM Module Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SRWTIMER_R5 0x00000020 // Wide Timer 5 Software Reset
+#define SYSCTL_SRWTIMER_R4 0x00000010 // Wide Timer 4 Software Reset
+#define SYSCTL_SRWTIMER_R3 0x00000008 // Wide Timer 3 Software Reset
+#define SYSCTL_SRWTIMER_R2 0x00000004 // Wide Timer 2 Software Reset
+#define SYSCTL_SRWTIMER_R1 0x00000002 // Wide Timer 1 Software Reset
+#define SYSCTL_SRWTIMER_R0 0x00000001 // Wide Timer 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCWD register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCWD_R1 0x00000002 // Watchdog Timer 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCWD_R0 0x00000001 // Watchdog Timer 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCTIMER_R5 0x00000020 // Timer 5 Run Mode Clock Gating
+ // Control
+#define SYSCTL_RCGCTIMER_R4 0x00000010 // Timer 4 Run Mode Clock Gating
+ // Control
+#define SYSCTL_RCGCTIMER_R3 0x00000008 // Timer 3 Run Mode Clock Gating
+ // Control
+#define SYSCTL_RCGCTIMER_R2 0x00000004 // Timer 2 Run Mode Clock Gating
+ // Control
+#define SYSCTL_RCGCTIMER_R1 0x00000002 // Timer 1 Run Mode Clock Gating
+ // Control
+#define SYSCTL_RCGCTIMER_R0 0x00000001 // Timer 0 Run Mode Clock Gating
+ // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCGPIO
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCGPIO_R14 0x00004000 // GPIO Port Q Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R13 0x00002000 // GPIO Port P Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R12 0x00001000 // GPIO Port N Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R11 0x00000800 // GPIO Port M Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R10 0x00000400 // GPIO Port L Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R9 0x00000200 // GPIO Port K Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R8 0x00000100 // GPIO Port J Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R7 0x00000080 // GPIO Port H Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R6 0x00000040 // GPIO Port G Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R5 0x00000020 // GPIO Port F Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R4 0x00000010 // GPIO Port E Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R3 0x00000008 // GPIO Port D Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R2 0x00000004 // GPIO Port C Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R1 0x00000002 // GPIO Port B Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R0 0x00000001 // GPIO Port A Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCDMA_R0 0x00000001 // uDMA Module Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCHIB_R0 0x00000001 // Hibernation Module Run Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCUART
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCUART_R7 0x00000080 // UART Module 7 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCUART_R6 0x00000040 // UART Module 6 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCUART_R5 0x00000020 // UART Module 5 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCUART_R4 0x00000010 // UART Module 4 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCUART_R3 0x00000008 // UART Module 3 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCUART_R2 0x00000004 // UART Module 2 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCUART_R1 0x00000002 // UART Module 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCUART_R0 0x00000001 // UART Module 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCSSI_R3 0x00000008 // SSI Module 3 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCSSI_R2 0x00000004 // SSI Module 2 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCSSI_R1 0x00000002 // SSI Module 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCSSI_R0 0x00000001 // SSI Module 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCI2C_R5 0x00000020 // I2C Module 5 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCI2C_R4 0x00000010 // I2C Module 4 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCI2C_R3 0x00000008 // I2C Module 3 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCI2C_R2 0x00000004 // I2C Module 2 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCI2C_R1 0x00000002 // I2C Module 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCI2C_R0 0x00000001 // I2C Module 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCUSB_R0 0x00000001 // USB Module Run Mode Clock Gating
+ // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCCAN_R1 0x00000002 // CAN Module 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCCAN_R0 0x00000001 // CAN Module 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCADC register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCADC_R1 0x00000002 // ADC Module 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCADC_R0 0x00000001 // ADC Module 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCACMP
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCACMP_R0 0x00000001 // Analog Comparator Module 0 Run
+ // Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCPWM_R1 0x00000002 // PWM Module 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCPWM_R0 0x00000001 // PWM Module 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCQEI_R1 0x00000002 // QEI Module 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCQEI_R0 0x00000001 // QEI Module 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCLPC register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCLPC_R0 0x00000001 // LPC Module Run Mode Clock Gating
+ // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCPECI
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCPECI_R0 0x00000001 // PECI Module Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCFAN register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCFAN_R0 0x00000001 // FAN Module Run Mode Clock Gating
+ // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCEEPROM_R0 0x00000001 // EEPROM Module Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCWTIMER_R5 0x00000020 // Wide Timer 5 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCWTIMER_R4 0x00000010 // Wide Timer 4 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCWTIMER_R3 0x00000008 // Wide Timer 3 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCWTIMER_R2 0x00000004 // Wide Timer 2 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCWTIMER_R1 0x00000002 // Wide Timer 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCWTIMER_R0 0x00000001 // Wide Timer 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCWD register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCWD_S1 0x00000002 // Watchdog Timer 1 Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_SCGCWD_S0 0x00000001 // Watchdog Timer 0 Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCTIMER_S5 0x00000020 // Timer 5 Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCTIMER_S4 0x00000010 // Timer 4 Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCTIMER_S3 0x00000008 // Timer 3 Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCTIMER_S2 0x00000004 // Timer 2 Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCTIMER_S1 0x00000002 // Timer 1 Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCTIMER_S0 0x00000001 // Timer 0 Sleep Mode Clock Gating
+ // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCGPIO
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCGPIO_S14 0x00004000 // GPIO Port Q Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S13 0x00002000 // GPIO Port P Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S12 0x00001000 // GPIO Port N Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S11 0x00000800 // GPIO Port M Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S10 0x00000400 // GPIO Port L Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S9 0x00000200 // GPIO Port K Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S8 0x00000100 // GPIO Port J Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S7 0x00000080 // GPIO Port H Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S6 0x00000040 // GPIO Port G Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S5 0x00000020 // GPIO Port F Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S4 0x00000010 // GPIO Port E Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S3 0x00000008 // GPIO Port D Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S2 0x00000004 // GPIO Port C Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S1 0x00000002 // GPIO Port B Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S0 0x00000001 // GPIO Port A Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCDMA_S0 0x00000001 // uDMA Module Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCHIB_S0 0x00000001 // Hibernation Module Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCUART
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCUART_S7 0x00000080 // UART Module 7 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCUART_S6 0x00000040 // UART Module 6 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCUART_S5 0x00000020 // UART Module 5 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCUART_S4 0x00000010 // UART Module 4 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCUART_S3 0x00000008 // UART Module 3 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCUART_S2 0x00000004 // UART Module 2 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCUART_S1 0x00000002 // UART Module 1 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCUART_S0 0x00000001 // UART Module 0 Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCSSI_S3 0x00000008 // SSI Module 3 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCSSI_S2 0x00000004 // SSI Module 2 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCSSI_S1 0x00000002 // SSI Module 1 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCSSI_S0 0x00000001 // SSI Module 0 Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCI2C_S5 0x00000020 // I2C Module 5 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCI2C_S4 0x00000010 // I2C Module 4 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCI2C_S3 0x00000008 // I2C Module 3 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCI2C_S2 0x00000004 // I2C Module 2 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCI2C_S1 0x00000002 // I2C Module 1 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCI2C_S0 0x00000001 // I2C Module 0 Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCUSB_S0 0x00000001 // USB Module Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCCAN_S1 0x00000002 // CAN Module 1 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCCAN_S0 0x00000001 // CAN Module 0 Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCADC register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCADC_S1 0x00000002 // ADC Module 1 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCADC_S0 0x00000001 // ADC Module 0 Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCACMP
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCACMP_S0 0x00000001 // Analog Comparator Module 0 Sleep
+ // Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCPWM_S1 0x00000002 // PWM Module 1 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCPWM_S0 0x00000001 // PWM Module 0 Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCQEI_S1 0x00000002 // QEI Module 1 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCQEI_S0 0x00000001 // QEI Module 0 Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCLPC register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCLPC_S0 0x00000001 // LPC Module Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCPECI
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCPECI_S0 0x00000001 // PECI Module Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCFAN register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCFAN_S0 0x00000001 // FAN Module Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCEEPROM_S0 0x00000001 // EEPROM Module Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCWTIMER_S5 0x00000020 // Wide Timer 5 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCWTIMER_S4 0x00000010 // Wide Timer 4 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCWTIMER_S3 0x00000008 // Wide Timer 3 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCWTIMER_S2 0x00000004 // Wide Timer 2 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCWTIMER_S1 0x00000002 // Wide Timer 1 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCWTIMER_S0 0x00000001 // Wide Timer 0 Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCWD register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCWD_D1 0x00000002 // Watchdog Timer 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCWD_D0 0x00000001 // Watchdog Timer 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCTIMER_D5 0x00000020 // Timer 5 Deep-Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_DCGCTIMER_D4 0x00000010 // Timer 4 Deep-Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_DCGCTIMER_D3 0x00000008 // Timer 3 Deep-Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_DCGCTIMER_D2 0x00000004 // Timer 2 Deep-Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_DCGCTIMER_D1 0x00000002 // Timer 1 Deep-Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_DCGCTIMER_D0 0x00000001 // Timer 0 Deep-Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCGPIO
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCGPIO_D14 0x00004000 // GPIO Port Q Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D13 0x00002000 // GPIO Port P Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D12 0x00001000 // GPIO Port N Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D11 0x00000800 // GPIO Port M Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D10 0x00000400 // GPIO Port L Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D9 0x00000200 // GPIO Port K Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D8 0x00000100 // GPIO Port J Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D7 0x00000080 // GPIO Port H Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D6 0x00000040 // GPIO Port G Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D5 0x00000020 // GPIO Port F Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D4 0x00000010 // GPIO Port E Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D3 0x00000008 // GPIO Port D Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D2 0x00000004 // GPIO Port C Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D1 0x00000002 // GPIO Port B Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D0 0x00000001 // GPIO Port A Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCDMA_D0 0x00000001 // uDMA Module Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCHIB_D0 0x00000001 // Hibernation Module Deep-Sleep
+ // Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCUART
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCUART_D7 0x00000080 // UART Module 7 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCUART_D6 0x00000040 // UART Module 6 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCUART_D5 0x00000020 // UART Module 5 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCUART_D4 0x00000010 // UART Module 4 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCUART_D3 0x00000008 // UART Module 3 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCUART_D2 0x00000004 // UART Module 2 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCUART_D1 0x00000002 // UART Module 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCUART_D0 0x00000001 // UART Module 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCSSI_D3 0x00000008 // SSI Module 3 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCSSI_D2 0x00000004 // SSI Module 2 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCSSI_D1 0x00000002 // SSI Module 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCSSI_D0 0x00000001 // SSI Module 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCI2C_D5 0x00000020 // I2C Module 5 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCI2C_D4 0x00000010 // I2C Module 4 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCI2C_D3 0x00000008 // I2C Module 3 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCI2C_D2 0x00000004 // I2C Module 2 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCI2C_D1 0x00000002 // I2C Module 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCI2C_D0 0x00000001 // I2C Module 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCUSB_D0 0x00000001 // USB Module Deep-Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCCAN_D1 0x00000002 // CAN Module 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCCAN_D0 0x00000001 // CAN Module 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCADC register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCADC_D1 0x00000002 // ADC Module 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCADC_D0 0x00000001 // ADC Module 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCACMP
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCACMP_D0 0x00000001 // Analog Comparator Module 0
+ // Deep-Sleep Mode Clock Gating
+ // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCPWM_D1 0x00000002 // PWM Module 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCPWM_D0 0x00000001 // PWM Module 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCQEI_D1 0x00000002 // QEI Module 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCQEI_D0 0x00000001 // QEI Module 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCLPC register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCLPC_D0 0x00000001 // LPC Module Deep-Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCPECI
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCPECI_D0 0x00000001 // PECI Module Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCFAN register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCFAN_D0 0x00000001 // FAN Module Deep-Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCEEPROM_D0 0x00000001 // EEPROM Module Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCWTIMER_D5 0x00000020 // Wide Timer 5 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCWTIMER_D4 0x00000010 // Wide Timer 4 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCWTIMER_D3 0x00000008 // Wide Timer 3 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCWTIMER_D2 0x00000004 // Wide Timer 2 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCWTIMER_D1 0x00000002 // Wide Timer 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCWTIMER_D0 0x00000001 // Wide Timer 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCWD register.
+//
+//*****************************************************************************
+#define SYSCTL_PCWD_P1 0x00000002 // Watchdog Timer 1 Power Control
+#define SYSCTL_PCWD_P0 0x00000001 // Watchdog Timer 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCTIMER register.
+//
+//*****************************************************************************
+#define SYSCTL_PCTIMER_P5 0x00000020 // Timer 5 Power Control
+#define SYSCTL_PCTIMER_P4 0x00000010 // Timer 4 Power Control
+#define SYSCTL_PCTIMER_P3 0x00000008 // Timer 3 Power Control
+#define SYSCTL_PCTIMER_P2 0x00000004 // Timer 2 Power Control
+#define SYSCTL_PCTIMER_P1 0x00000002 // Timer 1 Power Control
+#define SYSCTL_PCTIMER_P0 0x00000001 // Timer 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCGPIO register.
+//
+//*****************************************************************************
+#define SYSCTL_PCGPIO_P14 0x00004000 // GPIO Port Q Power Control
+#define SYSCTL_PCGPIO_P13 0x00002000 // GPIO Port P Power Control
+#define SYSCTL_PCGPIO_P12 0x00001000 // GPIO Port N Power Control
+#define SYSCTL_PCGPIO_P11 0x00000800 // GPIO Port M Power Control
+#define SYSCTL_PCGPIO_P10 0x00000400 // GPIO Port L Power Control
+#define SYSCTL_PCGPIO_P9 0x00000200 // GPIO Port K Power Control
+#define SYSCTL_PCGPIO_P8 0x00000100 // GPIO Port J Power Control
+#define SYSCTL_PCGPIO_P7 0x00000080 // GPIO Port H Power Control
+#define SYSCTL_PCGPIO_P6 0x00000040 // GPIO Port G Power Control
+#define SYSCTL_PCGPIO_P5 0x00000020 // GPIO Port F Power Control
+#define SYSCTL_PCGPIO_P4 0x00000010 // GPIO Port E Power Control
+#define SYSCTL_PCGPIO_P3 0x00000008 // GPIO Port D Power Control
+#define SYSCTL_PCGPIO_P2 0x00000004 // GPIO Port C Power Control
+#define SYSCTL_PCGPIO_P1 0x00000002 // GPIO Port B Power Control
+#define SYSCTL_PCGPIO_P0 0x00000001 // GPIO Port A Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_PCDMA_P0 0x00000001 // uDMA Module Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_PCHIB_P0 0x00000001 // Hibernation Module Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCUART register.
+//
+//*****************************************************************************
+#define SYSCTL_PCUART_P7 0x00000080 // UART Module 7 Power Control
+#define SYSCTL_PCUART_P6 0x00000040 // UART Module 6 Power Control
+#define SYSCTL_PCUART_P5 0x00000020 // UART Module 5 Power Control
+#define SYSCTL_PCUART_P4 0x00000010 // UART Module 4 Power Control
+#define SYSCTL_PCUART_P3 0x00000008 // UART Module 3 Power Control
+#define SYSCTL_PCUART_P2 0x00000004 // UART Module 2 Power Control
+#define SYSCTL_PCUART_P1 0x00000002 // UART Module 1 Power Control
+#define SYSCTL_PCUART_P0 0x00000001 // UART Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_PCSSI_P3 0x00000008 // SSI Module 3 Power Control
+#define SYSCTL_PCSSI_P2 0x00000004 // SSI Module 2 Power Control
+#define SYSCTL_PCSSI_P1 0x00000002 // SSI Module 1 Power Control
+#define SYSCTL_PCSSI_P0 0x00000001 // SSI Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_PCI2C_P5 0x00000020 // I2C Module 5 Power Control
+#define SYSCTL_PCI2C_P4 0x00000010 // I2C Module 4 Power Control
+#define SYSCTL_PCI2C_P3 0x00000008 // I2C Module 3 Power Control
+#define SYSCTL_PCI2C_P2 0x00000004 // I2C Module 2 Power Control
+#define SYSCTL_PCI2C_P1 0x00000002 // I2C Module 1 Power Control
+#define SYSCTL_PCI2C_P0 0x00000001 // I2C Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_PCUSB_P0 0x00000001 // USB Module Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_PCCAN_P1 0x00000002 // CAN Module 1 Power Control
+#define SYSCTL_PCCAN_P0 0x00000001 // CAN Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCADC register.
+//
+//*****************************************************************************
+#define SYSCTL_PCADC_P1 0x00000002 // ADC Module 1 Power Control
+#define SYSCTL_PCADC_P0 0x00000001 // ADC Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCACMP register.
+//
+//*****************************************************************************
+#define SYSCTL_PCACMP_P0 0x00000001 // Analog Comparator Module 0 Power
+ // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_PCPWM_P1 0x00000002 // PWM Module 1 Power Control
+#define SYSCTL_PCPWM_P0 0x00000001 // PWM Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_PCQEI_P1 0x00000002 // QEI Module 1 Power Control
+#define SYSCTL_PCQEI_P0 0x00000001 // QEI Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCLPC register.
+//
+//*****************************************************************************
+#define SYSCTL_PCLPC_P0 0x00000001 // LPC Module Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCPECI register.
+//
+//*****************************************************************************
+#define SYSCTL_PCPECI_P0 0x00000001 // PECI Module Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCFAN register.
+//
+//*****************************************************************************
+#define SYSCTL_PCFAN_P0 0x00000001 // FAN Module Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PCEEPROM_P0 0x00000001 // EEPROM Module Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PCWTIMER_P5 0x00000020 // Wide Timer 5 Power Control
+#define SYSCTL_PCWTIMER_P4 0x00000010 // Wide Timer 4 Power Control
+#define SYSCTL_PCWTIMER_P3 0x00000008 // Wide Timer 3 Power Control
+#define SYSCTL_PCWTIMER_P2 0x00000004 // Wide Timer 2 Power Control
+#define SYSCTL_PCWTIMER_P1 0x00000002 // Wide Timer 1 Power Control
+#define SYSCTL_PCWTIMER_P0 0x00000001 // Wide Timer 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRWD register.
+//
+//*****************************************************************************
+#define SYSCTL_PRWD_R1 0x00000002 // Watchdog Timer 1 Peripheral
+ // Ready
+#define SYSCTL_PRWD_R0 0x00000001 // Watchdog Timer 0 Peripheral
+ // Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRTIMER register.
+//
+//*****************************************************************************
+#define SYSCTL_PRTIMER_R5 0x00000020 // Timer 5 Peripheral Ready
+#define SYSCTL_PRTIMER_R4 0x00000010 // Timer 4 Peripheral Ready
+#define SYSCTL_PRTIMER_R3 0x00000008 // Timer 3 Peripheral Ready
+#define SYSCTL_PRTIMER_R2 0x00000004 // Timer 2 Peripheral Ready
+#define SYSCTL_PRTIMER_R1 0x00000002 // Timer 1 Peripheral Ready
+#define SYSCTL_PRTIMER_R0 0x00000001 // Timer 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRGPIO register.
+//
+//*****************************************************************************
+#define SYSCTL_PRGPIO_R14 0x00004000 // GPIO Port Q Peripheral Ready
+#define SYSCTL_PRGPIO_R13 0x00002000 // GPIO Port P Peripheral Ready
+#define SYSCTL_PRGPIO_R12 0x00001000 // GPIO Port N Peripheral Ready
+#define SYSCTL_PRGPIO_R11 0x00000800 // GPIO Port M Peripheral Ready
+#define SYSCTL_PRGPIO_R10 0x00000400 // GPIO Port L Peripheral Ready
+#define SYSCTL_PRGPIO_R9 0x00000200 // GPIO Port K Peripheral Ready
+#define SYSCTL_PRGPIO_R8 0x00000100 // GPIO Port J Peripheral Ready
+#define SYSCTL_PRGPIO_R7 0x00000080 // GPIO Port H Peripheral Ready
+#define SYSCTL_PRGPIO_R6 0x00000040 // GPIO Port G Peripheral Ready
+#define SYSCTL_PRGPIO_R5 0x00000020 // GPIO Port F Peripheral Ready
+#define SYSCTL_PRGPIO_R4 0x00000010 // GPIO Port E Peripheral Ready
+#define SYSCTL_PRGPIO_R3 0x00000008 // GPIO Port D Peripheral Ready
+#define SYSCTL_PRGPIO_R2 0x00000004 // GPIO Port C Peripheral Ready
+#define SYSCTL_PRGPIO_R1 0x00000002 // GPIO Port B Peripheral Ready
+#define SYSCTL_PRGPIO_R0 0x00000001 // GPIO Port A Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_PRDMA_R0 0x00000001 // uDMA Module Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_PRHIB_R0 0x00000001 // Hibernation Module Peripheral
+ // Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRUART register.
+//
+//*****************************************************************************
+#define SYSCTL_PRUART_R7 0x00000080 // UART Module 7 Peripheral Ready
+#define SYSCTL_PRUART_R6 0x00000040 // UART Module 6 Peripheral Ready
+#define SYSCTL_PRUART_R5 0x00000020 // UART Module 5 Peripheral Ready
+#define SYSCTL_PRUART_R4 0x00000010 // UART Module 4 Peripheral Ready
+#define SYSCTL_PRUART_R3 0x00000008 // UART Module 3 Peripheral Ready
+#define SYSCTL_PRUART_R2 0x00000004 // UART Module 2 Peripheral Ready
+#define SYSCTL_PRUART_R1 0x00000002 // UART Module 1 Peripheral Ready
+#define SYSCTL_PRUART_R0 0x00000001 // UART Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_PRSSI_R3 0x00000008 // SSI Module 3 Peripheral Ready
+#define SYSCTL_PRSSI_R2 0x00000004 // SSI Module 2 Peripheral Ready
+#define SYSCTL_PRSSI_R1 0x00000002 // SSI Module 1 Peripheral Ready
+#define SYSCTL_PRSSI_R0 0x00000001 // SSI Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_PRI2C_R5 0x00000020 // I2C Module 5 Peripheral Ready
+#define SYSCTL_PRI2C_R4 0x00000010 // I2C Module 4 Peripheral Ready
+#define SYSCTL_PRI2C_R3 0x00000008 // I2C Module 3 Peripheral Ready
+#define SYSCTL_PRI2C_R2 0x00000004 // I2C Module 2 Peripheral Ready
+#define SYSCTL_PRI2C_R1 0x00000002 // I2C Module 1 Peripheral Ready
+#define SYSCTL_PRI2C_R0 0x00000001 // I2C Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_PRUSB_R0 0x00000001 // USB Module Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_PRCAN_R1 0x00000002 // CAN Module 1 Peripheral Ready
+#define SYSCTL_PRCAN_R0 0x00000001 // CAN Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRADC register.
+//
+//*****************************************************************************
+#define SYSCTL_PRADC_R1 0x00000002 // ADC Module 1 Peripheral Ready
+#define SYSCTL_PRADC_R0 0x00000001 // ADC Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRACMP register.
+//
+//*****************************************************************************
+#define SYSCTL_PRACMP_R0 0x00000001 // Analog Comparator Module 0
+ // Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_PRPWM_R1 0x00000002 // PWM Module 1 Peripheral Ready
+#define SYSCTL_PRPWM_R0 0x00000001 // PWM Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_PRQEI_R1 0x00000002 // QEI Module 1 Peripheral Ready
+#define SYSCTL_PRQEI_R0 0x00000001 // QEI Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRLPC register.
+//
+//*****************************************************************************
+#define SYSCTL_PRLPC_R0 0x00000001 // LPC Module Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRPECI register.
+//
+//*****************************************************************************
+#define SYSCTL_PRPECI_R0 0x00000001 // PECI Module Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRFAN register.
+//
+//*****************************************************************************
+#define SYSCTL_PRFAN_R0 0x00000001 // FAN Module Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PREEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PREEPROM_R0 0x00000001 // EEPROM Module Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PRWTIMER_R5 0x00000020 // Wide Timer 5 Peripheral Ready
+#define SYSCTL_PRWTIMER_R4 0x00000010 // Wide Timer 4 Peripheral Ready
+#define SYSCTL_PRWTIMER_R3 0x00000008 // Wide Timer 3 Peripheral Ready
+#define SYSCTL_PRWTIMER_R2 0x00000004 // Wide Timer 2 Peripheral Ready
+#define SYSCTL_PRWTIMER_R1 0x00000002 // Wide Timer 1 Peripheral Ready
+#define SYSCTL_PRWTIMER_R0 0x00000001 // Wide Timer 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the System Control register
+// addresses.
+//
+//*****************************************************************************
+#define SYSCTL_GPIOHSCTL 0x400FE06C // GPIO High-Speed Control
+#define SYSCTL_USER0 0x400FE1E0 // NV User Register 0
+#define SYSCTL_USER1 0x400FE1E4 // NV User Register 1
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_DID0
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask
+#define SYSCTL_DID0_CLASS_MASK 0x00FF0000 // Device Class
+#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask
+#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A
+#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B
+#define SYSCTL_DID0_MAJ_C 0x00000200 // Major revision C
+#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_DID1
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask
+#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask
+#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family
+#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask
+#define SYSCTL_DID1_PINCNT_MASK 0x0000E000 // Pin count
+#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask
+#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask
+#define SYSCTL_DID1_PKG_48QFP 0x00000008 // QFP package
+#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask
+#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // SOIC package
+#define SYSCTL_DID1_PRTNO_SHIFT 16
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_DC0
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask
+#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_DC1
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DC1_PWM 0x00100000 // PWM Module Present
+#define SYSCTL_DC1_ADC 0x00010000 // ADC Module Present
+#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask
+#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask
+#define SYSCTL_DC1_ADCSPD_M 0x00000F00 // Max ADC Speed
+#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC
+#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250K samples/second
+#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500K samples/second
+#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1M samples/second
+#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present
+#define SYSCTL_DC1_WDT 0x00000008 // Watchdog Timer Present
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_DC2
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DC2_I2C 0x00001000 // I2C present
+#define SYSCTL_DC2_QEI 0x00000100 // QEI present
+#define SYSCTL_DC2_SSI 0x00000010 // SSI present
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_DC3
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DC3_ADC7 0x00800000 // ADC7 Pin Present
+#define SYSCTL_DC3_ADC6 0x00400000 // ADC6 Pin Present
+#define SYSCTL_DC3_ADC5 0x00200000 // ADC5 Pin Present
+#define SYSCTL_DC3_ADC4 0x00100000 // ADC4 Pin Present
+#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 Pin Present
+#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 Pin Present
+#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 Pin Present
+#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 Pin Present
+#define SYSCTL_DC3_MC_FAULT0 0x00008000 // MC0 fault pin present
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// SYSCTL_PBORCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer
+#define SYSCTL_PBORCTL_BOR_SH 2
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// SYSCTL_LDOPCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_SRCR0
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR0_PWM 0x00100000 // PWM Reset Control
+#define SYSCTL_SRCR0_ADC 0x00010000 // ADC0 Reset Control
+#define SYSCTL_SRCR0_WDT 0x00000008 // WDT Reset Control
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_RESC
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset
+#define SYSCTL_RESC_WDT 0x00000008 // Watchdog Timer Reset
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_RCC
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider
+#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider
+#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider
+#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider
+#define SYSCTL_RCC_OE 0x00001000 // PLL output enable
+#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864 MHz crystal
+#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4 MHz crystal
+#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc
+#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select
+#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field
+#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field
+#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field
+#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_PLLCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider
+#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier
+#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider
+#define SYSCTL_PLLCFG_F_SHIFT 5
+#define SYSCTL_PLLCFG_R_SHIFT 0
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// SYSCTL_GPIOHSCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_GPIOHSCTL_PORTA 0x00000001 // Port A High-Speed
+#define SYSCTL_GPIOHSCTL_PORTB 0x00000002 // Port B High-Speed
+#define SYSCTL_GPIOHSCTL_PORTC 0x00000004 // Port C High-Speed
+#define SYSCTL_GPIOHSCTL_PORTD 0x00000008 // Port D High-Speed
+#define SYSCTL_GPIOHSCTL_PORTE 0x00000010 // Port E High-Speed
+#define SYSCTL_GPIOHSCTL_PORTF 0x00000020 // Port F High-Speed
+#define SYSCTL_GPIOHSCTL_PORTG 0x00000040 // Port G High-Speed
+#define SYSCTL_GPIOHSCTL_PORTH 0x00000080 // Port H High-Speed
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_RCC2
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC2_USEFRACT 0x40000000 // Use fractional divider
+#define SYSCTL_RCC2_SYSDIV2_MSK 0x1F800000 // System clock divider
+#define SYSCTL_RCC2_FRACT 0x00400000 // Fractional divide
+#define SYSCTL_RCC2_OSCSRC2_MSK 0x00000070 // Oscillator input select
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_RCGC0
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC0_PWM 0x00100000 // PWM Clock Gating Control
+#define SYSCTL_RCGC0_ADC 0x00010000 // ADC0 Clock Gating Control
+#define SYSCTL_RCGC0_WDT 0x00000008 // WDT Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_SCGC0
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC0_PWM 0x00100000 // PWM Clock Gating Control
+#define SYSCTL_SCGC0_ADC 0x00010000 // ADC0 Clock Gating Control
+#define SYSCTL_SCGC0_WDT 0x00000008 // WDT Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_DCGC0
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC0_PWM 0x00100000 // PWM Clock Gating Control
+#define SYSCTL_DCGC0_ADC 0x00010000 // ADC0 Clock Gating Control
+#define SYSCTL_DCGC0_WDT 0x00000008 // WDT Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// SYSCTL_DSLPCLKCFG register.
+//
+//*****************************************************************************
+#define SYSCTL_DSLPCLKCFG_D_MSK 0x1F800000 // Deep sleep system clock override
+#define SYSCTL_DSLPCLKCFG_O_MSK 0x00000070 // Deep sleep oscillator override
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// SYSCTL_CLKVCLR register.
+//
+//*****************************************************************************
+#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// SYSCTL_LDOARST register.
+//
+//*****************************************************************************
+#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_SRCR0,
+// SYSCTL_RCGC0, SYSCTL_SCGC0, and SYSCTL_DCGC0 registers.
+//
+//*****************************************************************************
+#define SYSCTL_SET0_CAN2 0x04000000 // CAN 2 module
+#define SYSCTL_SET0_CAN1 0x02000000 // CAN 1 module
+#define SYSCTL_SET0_CAN0 0x01000000 // CAN 0 module
+#define SYSCTL_SET0_PWM 0x00100000 // PWM module
+#define SYSCTL_SET0_ADC 0x00010000 // ADC module
+#define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 // ADC speed mask
+#define SYSCTL_SET0_ADCSPD_125K 0x00000000 // 125Ksps ADC
+#define SYSCTL_SET0_ADCSPD_250K 0x00000100 // 250Ksps ADC
+#define SYSCTL_SET0_ADCSPD_500K 0x00000200 // 500Ksps ADC
+#define SYSCTL_SET0_ADCSPD_1M 0x00000300 // 1Msps ADC
+#define SYSCTL_SET0_HIB 0x00000040 // Hibernation module
+#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_SRCR1,
+// SYSCTL_RCGC1, SYSCTL_SCGC1, and SYSCTL_DCGC1 registers.
+//
+//*****************************************************************************
+#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2
+#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1
+#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0
+#define SYSCTL_SET1_TIMER3 0x00080000 // Timer module 3
+#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2
+#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1
+#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0
+#define SYSCTL_SET1_I2C1 0x00002000 // I2C module 1
+#define SYSCTL_SET1_I2C0 0x00001000 // I2C module 0
+#define SYSCTL_SET1_I2C 0x00001000 // I2C module
+#define SYSCTL_SET1_QEI1 0x00000200 // QEI module 1
+#define SYSCTL_SET1_QEI 0x00000100 // QEI module
+#define SYSCTL_SET1_QEI0 0x00000100 // QEI module 0
+#define SYSCTL_SET1_SSI1 0x00000020 // SSI module 1
+#define SYSCTL_SET1_SSI0 0x00000010 // SSI module 0
+#define SYSCTL_SET1_SSI 0x00000010 // SSI module
+#define SYSCTL_SET1_UART2 0x00000004 // UART module 2
+#define SYSCTL_SET1_UART1 0x00000002 // UART module 1
+#define SYSCTL_SET1_UART0 0x00000001 // UART module 0
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_SRCR2,
+// SYSCTL_RCGC2, SYSCTL_SCGC2, and SYSCTL_DCGC2 registers.
+//
+//*****************************************************************************
+#define SYSCTL_SET2_ETH 0x50000000 // ETH module
+#define SYSCTL_SET2_GPIOH 0x00000080 // GPIO H module
+#define SYSCTL_SET2_GPIOG 0x00000040 // GPIO G module
+#define SYSCTL_SET2_GPIOF 0x00000020 // GPIO F module
+#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module
+#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module
+#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module
+#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module
+#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_RIS,
+// SYSCTL_IMC, and SYSCTL_IMS registers.
+//
+//*****************************************************************************
+#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt
+#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt
+#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int
+#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int
+#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt
+#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt
+#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt
+
+#endif
+
+#endif // __HW_SYSCTL_H__
diff --git a/inc/hw_sysexc.h b/inc/hw_sysexc.h new file mode 100644 index 0000000..fdd0dcc --- /dev/null +++ b/inc/hw_sysexc.h @@ -0,0 +1,132 @@ +//*****************************************************************************
+//
+// hw_sysexc.h - Macros used when accessing the system exception module.
+//
+// Copyright (c) 2011-2012 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 9453 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_SYSEXC_H__
+#define __HW_SYSEXC_H__
+
+//*****************************************************************************
+//
+// The following are defines for the System Exception Module register
+// addresses.
+//
+//*****************************************************************************
+#define SYSEXC_RIS 0x400F9000 // System Exception Raw Interrupt
+ // Status
+#define SYSEXC_IM 0x400F9004 // System Exception Interrupt Mask
+#define SYSEXC_MIS 0x400F9008 // System Exception Masked
+ // Interrupt Status
+#define SYSEXC_IC 0x400F900C // System Exception Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSEXC_RIS register.
+//
+//*****************************************************************************
+#define SYSEXC_RIS_FPIXCRIS 0x00000020 // Floating-Point Inexact Exception
+ // Raw Interrupt Status
+#define SYSEXC_RIS_FPOFCRIS 0x00000010 // Floating-Point Overflow
+ // Exception Raw Interrupt Status
+#define SYSEXC_RIS_FPUFCRIS 0x00000008 // Floating-Point Underflow
+ // Exception Raw Interrupt Status
+#define SYSEXC_RIS_FPIOCRIS 0x00000004 // Floating-Point Invalid Operation
+ // Raw Interrupt Status
+#define SYSEXC_RIS_FPDZCRIS 0x00000002 // Floating-Point Divide By 0
+ // Exception Raw Interrupt Status
+#define SYSEXC_RIS_FPIDCRIS 0x00000001 // Floating-Point Input Denormal
+ // Exception Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSEXC_IM register.
+//
+//*****************************************************************************
+#define SYSEXC_IM_FPIXCIM 0x00000020 // Floating-Point Inexact Exception
+ // Interrupt Mask
+#define SYSEXC_IM_FPOFCIM 0x00000010 // Floating-Point Overflow
+ // Exception Interrupt Mask
+#define SYSEXC_IM_FPUFCIM 0x00000008 // Floating-Point Underflow
+ // Exception Interrupt Mask
+#define SYSEXC_IM_FPIOCIM 0x00000004 // Floating-Point Invalid Operation
+ // Interrupt Mask
+#define SYSEXC_IM_FPDZCIM 0x00000002 // Floating-Point Divide By 0
+ // Exception Interrupt Mask
+#define SYSEXC_IM_FPIDCIM 0x00000001 // Floating-Point Input Denormal
+ // Exception Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSEXC_MIS register.
+//
+//*****************************************************************************
+#define SYSEXC_MIS_FPIXCMIS 0x00000020 // Floating-Point Inexact Exception
+ // Masked Interrupt Status
+#define SYSEXC_MIS_FPOFCMIS 0x00000010 // Floating-Point Overflow
+ // Exception Masked Interrupt
+ // Status
+#define SYSEXC_MIS_FPUFCMIS 0x00000008 // Floating-Point Underflow
+ // Exception Masked Interrupt
+ // Status
+#define SYSEXC_MIS_FPIOCMIS 0x00000004 // Floating-Point Invalid Operation
+ // Masked Interrupt Status
+#define SYSEXC_MIS_FPDZCMIS 0x00000002 // Floating-Point Divide By 0
+ // Exception Masked Interrupt
+ // Status
+#define SYSEXC_MIS_FPIDCMIS 0x00000001 // Floating-Point Input Denormal
+ // Exception Masked Interrupt
+ // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSEXC_IC register.
+//
+//*****************************************************************************
+#define SYSEXC_IC_FPIXCIC 0x00000020 // Floating-Point Inexact Exception
+ // Interrupt Clear
+#define SYSEXC_IC_FPOFCIC 0x00000010 // Floating-Point Overflow
+ // Exception Interrupt Clear
+#define SYSEXC_IC_FPUFCIC 0x00000008 // Floating-Point Underflow
+ // Exception Interrupt Clear
+#define SYSEXC_IC_FPIOCIC 0x00000004 // Floating-Point Invalid Operation
+ // Interrupt Clear
+#define SYSEXC_IC_FPDZCIC 0x00000002 // Floating-Point Divide By 0
+ // Exception Interrupt Clear
+#define SYSEXC_IC_FPIDCIC 0x00000001 // Floating-Point Input Denormal
+ // Exception Interrupt Clear
+
+#endif // __HW_SYSEXC_H__
diff --git a/inc/hw_timer.h b/inc/hw_timer.h new file mode 100644 index 0000000..4c695ff --- /dev/null +++ b/inc/hw_timer.h @@ -0,0 +1,759 @@ +//*****************************************************************************
+//
+// hw_timer.h - Defines and macros used when accessing the timer.
+//
+// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 9453 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_TIMER_H__
+#define __HW_TIMER_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Timer register offsets.
+//
+//*****************************************************************************
+#define TIMER_O_CFG 0x00000000 // GPTM Configuration
+#define TIMER_O_TAMR 0x00000004 // GPTM Timer A Mode
+#define TIMER_O_TBMR 0x00000008 // GPTM Timer B Mode
+#define TIMER_O_CTL 0x0000000C // GPTM Control
+#define TIMER_O_SYNC 0x00000010 // GPTM Synchronize
+#define TIMER_O_IMR 0x00000018 // GPTM Interrupt Mask
+#define TIMER_O_RIS 0x0000001C // GPTM Raw Interrupt Status
+#define TIMER_O_MIS 0x00000020 // GPTM Masked Interrupt Status
+#define TIMER_O_ICR 0x00000024 // GPTM Interrupt Clear
+#define TIMER_O_TAILR 0x00000028 // GPTM Timer A Interval Load
+#define TIMER_O_TBILR 0x0000002C // GPTM Timer B Interval Load
+#define TIMER_O_TAMATCHR 0x00000030 // GPTM Timer A Match
+#define TIMER_O_TBMATCHR 0x00000034 // GPTM Timer B Match
+#define TIMER_O_TAPR 0x00000038 // GPTM Timer A Prescale
+#define TIMER_O_TBPR 0x0000003C // GPTM Timer B Prescale
+#define TIMER_O_TAPMR 0x00000040 // GPTM TimerA Prescale Match
+#define TIMER_O_TBPMR 0x00000044 // GPTM TimerB Prescale Match
+#define TIMER_O_TAR 0x00000048 // GPTM Timer A
+#define TIMER_O_TBR 0x0000004C // GPTM Timer B
+#define TIMER_O_TAV 0x00000050 // GPTM Timer A Value
+#define TIMER_O_TBV 0x00000054 // GPTM Timer B Value
+#define TIMER_O_RTCPD 0x00000058 // GPTM RTC Predivide
+#define TIMER_O_TAPS 0x0000005C // GPTM Timer A Prescale Snapshot
+#define TIMER_O_TBPS 0x00000060 // GPTM Timer B Prescale Snapshot
+#define TIMER_O_TAPV 0x00000064 // GPTM Timer A Prescale Value
+#define TIMER_O_TBPV 0x00000068 // GPTM Timer B Prescale Value
+#define TIMER_O_PP 0x00000FC0 // GPTM Peripheral Properties
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CFG register.
+//
+//*****************************************************************************
+#define TIMER_CFG_M 0x00000007 // GPTM Configuration
+#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32-bit timer configuration
+#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32-bit real-time clock (RTC)
+ // counter configuration
+#define TIMER_CFG_16_BIT 0x00000004 // 16-bit timer configuration. The
+ // function is controlled by bits
+ // 1:0 of GPTMTAMR and GPTMTBMR
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAMR register.
+//
+//*****************************************************************************
+#define TIMER_TAMR_TAPLO 0x00000800 // GPTM Timer A PWM Legacy
+ // Operation
+#define TIMER_TAMR_TAMRSU 0x00000400 // GPTM Timer A Match Register
+ // Update
+#define TIMER_TAMR_TAPWMIE 0x00000200 // GPTM Timer A PWM Interrupt
+ // Enable
+#define TIMER_TAMR_TAILD 0x00000100 // GPTM Timer A Interval Load Write
+#define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode
+#define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger
+#define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt
+ // Enable
+#define TIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A Count Direction
+#define TIMER_TAMR_TAAMS 0x00000008 // GPTM Timer A Alternate Mode
+ // Select
+#define TIMER_TAMR_TACMR 0x00000004 // GPTM Timer A Capture Mode
+#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A Mode
+#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode
+#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode
+#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBMR register.
+//
+//*****************************************************************************
+#define TIMER_TBMR_TBPLO 0x00000800 // GPTM Timer B PWM Legacy
+ // Operation
+#define TIMER_TBMR_TBMRSU 0x00000400 // GPTM Timer B Match Register
+ // Update
+#define TIMER_TBMR_TBPWMIE 0x00000200 // GPTM Timer B PWM Interrupt
+ // Enable
+#define TIMER_TBMR_TBILD 0x00000100 // GPTM Timer B Interval Load Write
+#define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode
+#define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger
+#define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt
+ // Enable
+#define TIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B Count Direction
+#define TIMER_TBMR_TBAMS 0x00000008 // GPTM Timer B Alternate Mode
+ // Select
+#define TIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B Capture Mode
+#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B Mode
+#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode
+#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode
+#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CTL register.
+//
+//*****************************************************************************
+#define TIMER_CTL_TBPWML 0x00004000 // GPTM Timer B PWM Output Level
+#define TIMER_CTL_TBOTE 0x00002000 // GPTM Timer B Output Trigger
+ // Enable
+#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM Timer B Event Mode
+#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge
+#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge
+#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges
+#define TIMER_CTL_TBSTALL 0x00000200 // GPTM Timer B Stall Enable
+#define TIMER_CTL_TBEN 0x00000100 // GPTM Timer B Enable
+#define TIMER_CTL_TAPWML 0x00000040 // GPTM Timer A PWM Output Level
+#define TIMER_CTL_TAOTE 0x00000020 // GPTM Timer A Output Trigger
+ // Enable
+#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Stall Enable
+#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM Timer A Event Mode
+#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge
+#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge
+#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges
+#define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable
+#define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_SYNC register.
+//
+//*****************************************************************************
+#define TIMER_SYNC_SYNCWT5_M 0x00C00000 // Synchronize GPTM 32/64-Bit Timer
+ // 5
+#define TIMER_SYNC_SYNCWT5_NONE 0x00000000 // GPTM 32/64-Bit Timer 5 is not
+ // affected
+#define TIMER_SYNC_SYNCWT5_TA 0x00400000 // A timeout event for Timer A of
+ // GPTM 32/64-Bit Timer 5 is
+ // triggered
+#define TIMER_SYNC_SYNCWT5_TB 0x00800000 // A timeout event for Timer B of
+ // GPTM 32/64-Bit Timer 5 is
+ // triggered
+#define TIMER_SYNC_SYNCWT5_TATB 0x00C00000 // A timeout event for both Timer A
+ // and Timer B of GPTM 32/64-Bit
+ // Timer 5 is triggered
+#define TIMER_SYNC_SYNCWT4_M 0x00300000 // Synchronize GPTM 32/64-Bit Timer
+ // 4
+#define TIMER_SYNC_SYNCWT4_NONE 0x00000000 // GPTM 32/64-Bit Timer 4 is not
+ // affected
+#define TIMER_SYNC_SYNCWT4_TA 0x00100000 // A timeout event for Timer A of
+ // GPTM 32/64-Bit Timer 4 is
+ // triggered
+#define TIMER_SYNC_SYNCWT4_TB 0x00200000 // A timeout event for Timer B of
+ // GPTM 32/64-Bit Timer 4 is
+ // triggered
+#define TIMER_SYNC_SYNCWT4_TATB 0x00300000 // A timeout event for both Timer A
+ // and Timer B of GPTM 32/64-Bit
+ // Timer 4 is triggered
+#define TIMER_SYNC_SYNCWT3_M 0x000C0000 // Synchronize GPTM 32/64-Bit Timer
+ // 3
+#define TIMER_SYNC_SYNCWT3_NONE 0x00000000 // GPTM 32/64-Bit Timer 3 is not
+ // affected
+#define TIMER_SYNC_SYNCWT3_TA 0x00040000 // A timeout event for Timer A of
+ // GPTM 32/64-Bit Timer 3 is
+ // triggered
+#define TIMER_SYNC_SYNCWT3_TB 0x00080000 // A timeout event for Timer B of
+ // GPTM 32/64-Bit Timer 3 is
+ // triggered
+#define TIMER_SYNC_SYNCWT3_TATB 0x000C0000 // A timeout event for both Timer A
+ // and Timer B of GPTM 32/64-Bit
+ // Timer 3 is triggered
+#define TIMER_SYNC_SYNCWT2_M 0x00030000 // Synchronize GPTM 32/64-Bit Timer
+ // 2
+#define TIMER_SYNC_SYNCWT2_NONE 0x00000000 // GPTM 32/64-Bit Timer 2 is not
+ // affected
+#define TIMER_SYNC_SYNCWT2_TA 0x00010000 // A timeout event for Timer A of
+ // GPTM 32/64-Bit Timer 2 is
+ // triggered
+#define TIMER_SYNC_SYNCWT2_TB 0x00020000 // A timeout event for Timer B of
+ // GPTM 32/64-Bit Timer 2 is
+ // triggered
+#define TIMER_SYNC_SYNCWT2_TATB 0x00030000 // A timeout event for both Timer A
+ // and Timer B of GPTM 32/64-Bit
+ // Timer 2 is triggered
+#define TIMER_SYNC_SYNCWT1_M 0x0000C000 // Synchronize GPTM 32/64-Bit Timer
+ // 1
+#define TIMER_SYNC_SYNCWT1_NONE 0x00000000 // GPTM 32/64-Bit Timer 1 is not
+ // affected
+#define TIMER_SYNC_SYNCWT1_TA 0x00004000 // A timeout event for Timer A of
+ // GPTM 32/64-Bit Timer 1 is
+ // triggered
+#define TIMER_SYNC_SYNCWT1_TB 0x00008000 // A timeout event for Timer B of
+ // GPTM 32/64-Bit Timer 1 is
+ // triggered
+#define TIMER_SYNC_SYNCWT1_TATB 0x0000C000 // A timeout event for both Timer A
+ // and Timer B of GPTM 32/64-Bit
+ // Timer 1 is triggered
+#define TIMER_SYNC_SYNCWT0_M 0x00003000 // Synchronize GPTM 32/64-Bit Timer
+ // 0
+#define TIMER_SYNC_SYNCWT0_NONE 0x00000000 // GPTM 32/64-Bit Timer 0 is not
+ // affected
+#define TIMER_SYNC_SYNCWT0_TA 0x00001000 // A timeout event for Timer A of
+ // GPTM 32/64-Bit Timer 0 is
+ // triggered
+#define TIMER_SYNC_SYNCWT0_TB 0x00002000 // A timeout event for Timer B of
+ // GPTM 32/64-Bit Timer 0 is
+ // triggered
+#define TIMER_SYNC_SYNCWT0_TATB 0x00003000 // A timeout event for both Timer A
+ // and Timer B of GPTM 32/64-Bit
+ // Timer 0 is triggered
+#define TIMER_SYNC_SYNCT5_M 0x00000C00 // Synchronize GPTM 16/32-Bit Timer
+ // 5
+#define TIMER_SYNC_SYNCT5_NONE 0x00000000 // GPTM 16/32-Bit Timer 5 is not
+ // affected
+#define TIMER_SYNC_SYNCT5_TA 0x00000400 // A timeout event for Timer A of
+ // GPTM 16/32-Bit Timer 5 is
+ // triggered
+#define TIMER_SYNC_SYNCT5_TB 0x00000800 // A timeout event for Timer B of
+ // GPTM 16/32-Bit Timer 5 is
+ // triggered
+#define TIMER_SYNC_SYNCT5_TATB 0x00000C00 // A timeout event for both Timer A
+ // and Timer B of GPTM 16/32-Bit
+ // Timer 5 is triggered
+#define TIMER_SYNC_SYNCT4_M 0x00000300 // Synchronize GPTM 16/32-Bit Timer
+ // 4
+#define TIMER_SYNC_SYNCT4_NONE 0x00000000 // GPTM 16/32-Bit Timer 4 is not
+ // affected
+#define TIMER_SYNC_SYNCT4_TA 0x00000100 // A timeout event for Timer A of
+ // GPTM 16/32-Bit Timer 4 is
+ // triggered
+#define TIMER_SYNC_SYNCT4_TB 0x00000200 // A timeout event for Timer B of
+ // GPTM 16/32-Bit Timer 4 is
+ // triggered
+#define TIMER_SYNC_SYNCT4_TATB 0x00000300 // A timeout event for both Timer A
+ // and Timer B of GPTM 16/32-Bit
+ // Timer 4 is triggered
+#define TIMER_SYNC_SYNCT3_M 0x000000C0 // Synchronize GPTM 16/32-Bit Timer
+ // 3
+#define TIMER_SYNC_SYNCT3_NONE 0x00000000 // GPTM 16/32-Bit Timer 3 is not
+ // affected
+#define TIMER_SYNC_SYNCT3_TA 0x00000040 // A timeout event for Timer A of
+ // GPTM 16/32-Bit Timer 3 is
+ // triggered
+#define TIMER_SYNC_SYNCT3_TB 0x00000080 // A timeout event for Timer B of
+ // GPTM 16/32-Bit Timer 3 is
+ // triggered
+#define TIMER_SYNC_SYNCT3_TATB 0x000000C0 // A timeout event for both Timer A
+ // and Timer B of GPTM 16/32-Bit
+ // Timer 3 is triggered
+#define TIMER_SYNC_SYNCT2_M 0x00000030 // Synchronize GPTM 16/32-Bit Timer
+ // 2
+#define TIMER_SYNC_SYNCT2_NONE 0x00000000 // GPTM 16/32-Bit Timer 2 is not
+ // affected
+#define TIMER_SYNC_SYNCT2_TA 0x00000010 // A timeout event for Timer A of
+ // GPTM 16/32-Bit Timer 2 is
+ // triggered
+#define TIMER_SYNC_SYNCT2_TB 0x00000020 // A timeout event for Timer B of
+ // GPTM 16/32-Bit Timer 2 is
+ // triggered
+#define TIMER_SYNC_SYNCT2_TATB 0x00000030 // A timeout event for both Timer A
+ // and Timer B of GPTM 16/32-Bit
+ // Timer 2 is triggered
+#define TIMER_SYNC_SYNCT1_M 0x0000000C // Synchronize GPTM 16/32-Bit Timer
+ // 1
+#define TIMER_SYNC_SYNCT1_NONE 0x00000000 // GPTM 16/32-Bit Timer 1 is not
+ // affected
+#define TIMER_SYNC_SYNCT1_TA 0x00000004 // A timeout event for Timer A of
+ // GPTM 16/32-Bit Timer 1 is
+ // triggered
+#define TIMER_SYNC_SYNCT1_TB 0x00000008 // A timeout event for Timer B of
+ // GPTM 16/32-Bit Timer 1 is
+ // triggered
+#define TIMER_SYNC_SYNCT1_TATB 0x0000000C // A timeout event for both Timer A
+ // and Timer B of GPTM 16/32-Bit
+ // Timer 1 is triggered
+#define TIMER_SYNC_SYNCT0_M 0x00000003 // Synchronize GPTM 16/32-Bit Timer
+ // 0
+#define TIMER_SYNC_SYNCT0_NONE 0x00000000 // GPTM 16/32-Bit Timer 0 is not
+ // affected
+#define TIMER_SYNC_SYNCT0_TA 0x00000001 // A timeout event for Timer A of
+ // GPTM 16/32-Bit Timer 0 is
+ // triggered
+#define TIMER_SYNC_SYNCT0_TB 0x00000002 // A timeout event for Timer B of
+ // GPTM 16/32-Bit Timer 0 is
+ // triggered
+#define TIMER_SYNC_SYNCT0_TATB 0x00000003 // A timeout event for both Timer A
+ // and Timer B of GPTM 16/32-Bit
+ // Timer 0 is triggered
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_IMR register.
+//
+//*****************************************************************************
+#define TIMER_IMR_WUEIM 0x00010000 // GPTM Write Update Error
+ // Interrupt Mask
+#define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Match Interrupt
+ // Mask
+#define TIMER_IMR_CBEIM 0x00000400 // GPTM Timer B Capture Mode Event
+ // Interrupt Mask
+#define TIMER_IMR_CBMIM 0x00000200 // GPTM Timer B Capture Mode Match
+ // Interrupt Mask
+#define TIMER_IMR_TBTOIM 0x00000100 // GPTM Timer B Time-Out Interrupt
+ // Mask
+#define TIMER_IMR_TAMIM 0x00000010 // GPTM Timer A Match Interrupt
+ // Mask
+#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask
+#define TIMER_IMR_CAEIM 0x00000004 // GPTM Timer A Capture Mode Event
+ // Interrupt Mask
+#define TIMER_IMR_CAMIM 0x00000002 // GPTM Timer A Capture Mode Match
+ // Interrupt Mask
+#define TIMER_IMR_TATOIM 0x00000001 // GPTM Timer A Time-Out Interrupt
+ // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_RIS register.
+//
+//*****************************************************************************
+#define TIMER_RIS_WUERIS 0x00010000 // GPTM Write Update Error Raw
+ // Interrupt
+#define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Match Raw Interrupt
+#define TIMER_RIS_CBERIS 0x00000400 // GPTM Timer B Capture Mode Event
+ // Raw Interrupt
+#define TIMER_RIS_CBMRIS 0x00000200 // GPTM Timer B Capture Mode Match
+ // Raw Interrupt
+#define TIMER_RIS_TBTORIS 0x00000100 // GPTM Timer B Time-Out Raw
+ // Interrupt
+#define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Match Raw Interrupt
+#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt
+#define TIMER_RIS_CAERIS 0x00000004 // GPTM Timer A Capture Mode Event
+ // Raw Interrupt
+#define TIMER_RIS_CAMRIS 0x00000002 // GPTM Timer A Capture Mode Match
+ // Raw Interrupt
+#define TIMER_RIS_TATORIS 0x00000001 // GPTM Timer A Time-Out Raw
+ // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_MIS register.
+//
+//*****************************************************************************
+#define TIMER_MIS_WUEMIS 0x00010000 // GPTM Write Update Error Masked
+ // Interrupt
+#define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Match Masked
+ // Interrupt
+#define TIMER_MIS_CBEMIS 0x00000400 // GPTM Timer B Capture Mode Event
+ // Masked Interrupt
+#define TIMER_MIS_CBMMIS 0x00000200 // GPTM Timer B Capture Mode Match
+ // Masked Interrupt
+#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM Timer B Time-Out Masked
+ // Interrupt
+#define TIMER_MIS_TAMMIS 0x00000010 // GPTM Timer A Match Masked
+ // Interrupt
+#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt
+#define TIMER_MIS_CAEMIS 0x00000004 // GPTM Timer A Capture Mode Event
+ // Masked Interrupt
+#define TIMER_MIS_CAMMIS 0x00000002 // GPTM Timer A Capture Mode Match
+ // Masked Interrupt
+#define TIMER_MIS_TATOMIS 0x00000001 // GPTM Timer A Time-Out Masked
+ // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_ICR register.
+//
+//*****************************************************************************
+#define TIMER_ICR_WUECINT 0x00010000 // 32/64-Bit GPTM Write Update
+ // Error Interrupt Clear
+#define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Match Interrupt
+ // Clear
+#define TIMER_ICR_CBECINT 0x00000400 // GPTM Timer B Capture Mode Event
+ // Interrupt Clear
+#define TIMER_ICR_CBMCINT 0x00000200 // GPTM Timer B Capture Mode Match
+ // Interrupt Clear
+#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM Timer B Time-Out Interrupt
+ // Clear
+#define TIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A Match Interrupt
+ // Clear
+#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear
+#define TIMER_ICR_CAECINT 0x00000004 // GPTM Timer A Capture Mode Event
+ // Interrupt Clear
+#define TIMER_ICR_CAMCINT 0x00000002 // GPTM Timer A Capture Mode Match
+ // Interrupt Clear
+#define TIMER_ICR_TATOCINT 0x00000001 // GPTM Timer A Time-Out Raw
+ // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAILR register.
+//
+//*****************************************************************************
+#define TIMER_TAILR_M 0xFFFFFFFF // GPTM Timer A Interval Load
+ // Register
+#define TIMER_TAILR_TAILRH_M 0xFFFF0000 // GPTM Timer A Interval Load
+ // Register High
+#define TIMER_TAILR_TAILRL_M 0x0000FFFF // GPTM Timer A Interval Load
+ // Register Low
+#define TIMER_TAILR_TAILRH_S 16
+#define TIMER_TAILR_TAILRL_S 0
+#define TIMER_TAILR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBILR register.
+//
+//*****************************************************************************
+#define TIMER_TBILR_M 0xFFFFFFFF // GPTM Timer B Interval Load
+ // Register
+#define TIMER_TBILR_TBILRL_M 0x0000FFFF // GPTM Timer B Interval Load
+ // Register
+#define TIMER_TBILR_TBILRL_S 0
+#define TIMER_TBILR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAMATCHR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF // GPTM Timer A Match Register
+#define TIMER_TAMATCHR_TAMRH_M 0xFFFF0000 // GPTM Timer A Match Register High
+#define TIMER_TAMATCHR_TAMRL_M 0x0000FFFF // GPTM Timer A Match Register Low
+#define TIMER_TAMATCHR_TAMRH_S 16
+#define TIMER_TAMATCHR_TAMRL_S 0
+#define TIMER_TAMATCHR_TAMR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBMATCHR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF // GPTM Timer B Match Register
+#define TIMER_TBMATCHR_TBMRL_M 0x0000FFFF // GPTM Timer B Match Register Low
+#define TIMER_TBMATCHR_TBMR_S 0
+#define TIMER_TBMATCHR_TBMRL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPR register.
+//
+//*****************************************************************************
+#define TIMER_TAPR_TAPSRH_M 0x0000FF00 // GPTM Timer A Prescale High Byte
+#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale
+#define TIMER_TAPR_TAPSRH_S 8
+#define TIMER_TAPR_TAPSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPR register.
+//
+//*****************************************************************************
+#define TIMER_TBPR_TBPSRH_M 0x0000FF00 // GPTM Timer B Prescale High Byte
+#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale
+#define TIMER_TBPR_TBPSRH_S 8
+#define TIMER_TBPR_TBPSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPMR register.
+//
+//*****************************************************************************
+#define TIMER_TAPMR_TAPSMRH_M 0x0000FF00 // GPTM Timer A Prescale Match High
+ // Byte
+#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match
+#define TIMER_TAPMR_TAPSMRH_S 8
+#define TIMER_TAPMR_TAPSMR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPMR register.
+//
+//*****************************************************************************
+#define TIMER_TBPMR_TBPSMRH_M 0x0000FF00 // GPTM Timer B Prescale Match High
+ // Byte
+#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match
+#define TIMER_TBPMR_TBPSMRH_S 8
+#define TIMER_TBPMR_TBPSMR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAR register.
+//
+//*****************************************************************************
+#define TIMER_TAR_M 0xFFFFFFFF // GPTM Timer A Register
+#define TIMER_TAR_TARH_M 0xFFFF0000 // GPTM Timer A Register High
+#define TIMER_TAR_TARL_M 0x0000FFFF // GPTM Timer A Register Low
+#define TIMER_TAR_TARH_S 16
+#define TIMER_TAR_TARL_S 0
+#define TIMER_TAR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBR register.
+//
+//*****************************************************************************
+#define TIMER_TBR_M 0xFFFFFFFF // GPTM Timer B Register
+#define TIMER_TBR_TBRL_M 0x00FFFFFF // GPTM Timer B
+#define TIMER_TBR_TBRL_S 0
+#define TIMER_TBR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAV register.
+//
+//*****************************************************************************
+#define TIMER_TAV_M 0xFFFFFFFF // GPTM Timer A Value
+#define TIMER_TAV_TAVH_M 0xFFFF0000 // GPTM Timer A Value High
+#define TIMER_TAV_TAVL_M 0x0000FFFF // GPTM Timer A Register Low
+#define TIMER_TAV_TAVH_S 16
+#define TIMER_TAV_TAVL_S 0
+#define TIMER_TAV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBV register.
+//
+//*****************************************************************************
+#define TIMER_TBV_M 0xFFFFFFFF // GPTM Timer B Value
+#define TIMER_TBV_TBVL_M 0x0000FFFF // GPTM Timer B Register
+#define TIMER_TBV_TBVL_S 0
+#define TIMER_TBV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_RTCPD register.
+//
+//*****************************************************************************
+#define TIMER_RTCPD_RTCPD_M 0x0000FFFF // RTC Predivide Counter Value
+#define TIMER_RTCPD_RTCPD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPS register.
+//
+//*****************************************************************************
+#define TIMER_TAPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Snapshot
+#define TIMER_TAPS_PSS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPS register.
+//
+//*****************************************************************************
+#define TIMER_TBPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Value
+#define TIMER_TBPS_PSS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPV register.
+//
+//*****************************************************************************
+#define TIMER_TAPV_PSV_M 0x0000FFFF // GPTM Timer A Prescaler Value
+#define TIMER_TAPV_PSV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPV register.
+//
+//*****************************************************************************
+#define TIMER_TBPV_PSV_M 0x0000FFFF // GPTM Timer B Prescaler Value
+#define TIMER_TBPV_PSV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_PP register.
+//
+//*****************************************************************************
+#define TIMER_PP_SIZE_M 0x0000000F // Count Size
+#define TIMER_PP_SIZE_16 0x00000000 // Timer A and Timer B counters are
+ // 16 bits each with an 8-bit
+ // prescale counter
+#define TIMER_PP_SIZE_32 0x00000001 // Timer A and Timer B counters are
+ // 32 bits each with a 16-bit
+ // prescale counter
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_O_CFG
+// register.
+//
+//*****************************************************************************
+#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_O_CTL
+// register.
+//
+//*****************************************************************************
+#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask
+#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_O_RIS
+// register.
+//
+//*****************************************************************************
+#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status
+#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status
+#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat
+#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status
+#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status
+#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status
+#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_O_TAILR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode
+#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_O_TBILR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// TIMER_O_TAMATCHR register.
+//
+//*****************************************************************************
+#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode
+#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// TIMER_O_TBMATCHR register.
+//
+//*****************************************************************************
+#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_O_TAR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode
+#define TIMER_TAR_TARL 0x0000FFFF // TimerA value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_O_TBR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the reset values of the timer
+// registers.
+//
+//*****************************************************************************
+#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV
+#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV
+#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV
+#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV
+#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV
+#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV
+#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV
+#define TIMER_RV_CFG 0x00000000 // Configuration register RV
+#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV
+#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV
+#define TIMER_RV_CTL 0x00000000 // Control register RV
+#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV
+#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV
+#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV
+#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV
+#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV
+#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV
+#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_TnMR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select
+#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time
+#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask
+#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot
+#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic
+#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_TnPR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the TIMER_TnPMR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value
+
+#endif
+
+#endif // __HW_TIMER_H__
diff --git a/inc/hw_types.h b/inc/hw_types.h new file mode 100644 index 0000000..6f87f14 --- /dev/null +++ b/inc/hw_types.h @@ -0,0 +1,218 @@ +//*****************************************************************************
+//
+// hw_types.h - Common types and macros.
+//
+// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 9453 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_TYPES_H__
+#define __HW_TYPES_H__
+
+//*****************************************************************************
+//
+// Define a boolean type, and values for true and false.
+//
+//*****************************************************************************
+typedef unsigned char tBoolean;
+
+#ifndef true
+#define true 1
+#endif
+
+#ifndef false
+#define false 0
+#endif
+
+//*****************************************************************************
+//
+// Macros for hardware access, both direct and via the bit-band region.
+//
+//*****************************************************************************
+#define HWREG(x) \
+ (*((volatile unsigned long *)(x)))
+#define HWREGH(x) \
+ (*((volatile unsigned short *)(x)))
+#define HWREGB(x) \
+ (*((volatile unsigned char *)(x)))
+#define HWREGBITW(x, b) \
+ HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
+#define HWREGBITH(x, b) \
+ HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
+#define HWREGBITB(x, b) \
+ HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
+
+//*****************************************************************************
+//
+// Helper Macros for determining silicon revisions, etc.
+//
+// These macros will be used by Driverlib at "run-time" to create necessary
+// conditional code blocks that will allow a single version of the Driverlib
+// "binary" code to support multiple(all) Stellaris silicon revisions.
+//
+// It is expected that these macros will be used inside of a standard 'C'
+// conditional block of code, e.g.
+//
+// if(CLASS_IS_SANDSTORM)
+// {
+// do some Sandstorm-class specific code here.
+// }
+//
+// By default, these macros will be defined as run-time checks of the
+// appropriate register(s) to allow creation of run-time conditional code
+// blocks for a common DriverLib across the entire Stellaris family.
+//
+// However, if code-space optimization is required, these macros can be "hard-
+// coded" for a specific version of Stellaris silicon. Many compilers will
+// then detect the "hard-coded" conditionals, and appropriately optimize the
+// code blocks, eliminating any "unreachable" code. This would result in
+// a smaller Driverlib, thus producing a smaller final application size, but
+// at the cost of limiting the Driverlib binary to a specific Stellaris
+// silicon revision.
+//
+//*****************************************************************************
+#ifndef CLASS_IS_SANDSTORM
+#define CLASS_IS_SANDSTORM \
+ (((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_M) == SYSCTL_DID0_VER_0) || \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
+ (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_SANDSTORM)))
+#endif
+
+#ifndef CLASS_IS_FURY
+#define CLASS_IS_FURY \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
+ (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_FURY))
+#endif
+
+#ifndef CLASS_IS_DUSTDEVIL
+#define CLASS_IS_DUSTDEVIL \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
+ (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_DUSTDEVIL))
+#endif
+
+#ifndef CLASS_IS_TEMPEST
+#define CLASS_IS_TEMPEST \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
+ (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_TEMPEST))
+#endif
+
+#ifndef CLASS_IS_FIRESTORM
+#define CLASS_IS_FIRESTORM \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
+ (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_FIRESTORM))
+#endif
+
+#ifndef CLASS_IS_BLIZZARD
+#define CLASS_IS_BLIZZARD \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
+ (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_BLIZZARD))
+#endif
+
+#ifndef REVISION_IS_A0
+#define REVISION_IS_A0 \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+ (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0))
+#endif
+
+#ifndef REVISION_IS_A1
+#define REVISION_IS_A1 \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+ (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0))
+#endif
+
+#ifndef REVISION_IS_A2
+#define REVISION_IS_A2 \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+ (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_2))
+#endif
+
+#ifndef REVISION_IS_B0
+#define REVISION_IS_B0 \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+ (SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_0))
+#endif
+
+#ifndef REVISION_IS_B1
+#define REVISION_IS_B1 \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+ (SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_1))
+#endif
+
+#ifndef REVISION_IS_C0
+#define REVISION_IS_C0 \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+ (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_0))
+#endif
+
+#ifndef REVISION_IS_C1
+#define REVISION_IS_C1 \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+ (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_1))
+#endif
+
+#ifndef REVISION_IS_C2
+#define REVISION_IS_C2 \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+ (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_2))
+#endif
+
+#ifndef REVISION_IS_C3
+#define REVISION_IS_C3 \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+ (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_3))
+#endif
+
+#ifndef REVISION_IS_C5
+#define REVISION_IS_C5 \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+ (SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_5))
+#endif
+
+//*****************************************************************************
+//
+// Deprecated silicon class and revision detection macros.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#define DEVICE_IS_SANDSTORM CLASS_IS_SANDSTORM
+#define DEVICE_IS_FURY CLASS_IS_FURY
+#define DEVICE_IS_REVA2 REVISION_IS_A2
+#define DEVICE_IS_REVC1 REVISION_IS_C1
+#define DEVICE_IS_REVC2 REVISION_IS_C2
+#endif
+
+#endif // __HW_TYPES_H__
diff --git a/inc/hw_uart.h b/inc/hw_uart.h new file mode 100644 index 0000000..7926049 --- /dev/null +++ b/inc/hw_uart.h @@ -0,0 +1,522 @@ +//*****************************************************************************
+//
+// hw_uart.h - Macros and defines used when accessing the UART hardware.
+//
+// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 9453 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_UART_H__
+#define __HW_UART_H__
+
+//*****************************************************************************
+//
+// The following are defines for the UART register offsets.
+//
+//*****************************************************************************
+#define UART_O_DR 0x00000000 // UART Data
+#define UART_O_RSR 0x00000004 // UART Receive Status/Error Clear
+#define UART_O_ECR 0x00000004 // UART Receive Status/Error Clear
+#define UART_O_FR 0x00000018 // UART Flag
+#define UART_O_ILPR 0x00000020 // UART IrDA Low-Power Register
+#define UART_O_IBRD 0x00000024 // UART Integer Baud-Rate Divisor
+#define UART_O_FBRD 0x00000028 // UART Fractional Baud-Rate
+ // Divisor
+#define UART_O_LCRH 0x0000002C // UART Line Control
+#define UART_O_CTL 0x00000030 // UART Control
+#define UART_O_IFLS 0x00000034 // UART Interrupt FIFO Level Select
+#define UART_O_IM 0x00000038 // UART Interrupt Mask
+#define UART_O_RIS 0x0000003C // UART Raw Interrupt Status
+#define UART_O_MIS 0x00000040 // UART Masked Interrupt Status
+#define UART_O_ICR 0x00000044 // UART Interrupt Clear
+#define UART_O_DMACTL 0x00000048 // UART DMA Control
+#define UART_O_LCTL 0x00000090 // UART LIN Control
+#define UART_O_LSS 0x00000094 // UART LIN Snap Shot
+#define UART_O_LTIM 0x00000098 // UART LIN Timer
+#define UART_O_9BITADDR 0x000000A4 // UART 9-Bit Self Address
+#define UART_O_9BITAMASK 0x000000A8 // UART 9-Bit Self Address Mask
+#define UART_O_PP 0x00000FC0 // UART Peripheral Properties
+#define UART_O_CC 0x00000FC8 // UART Clock Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_DR register.
+//
+//*****************************************************************************
+#define UART_DR_OE 0x00000800 // UART Overrun Error
+#define UART_DR_BE 0x00000400 // UART Break Error
+#define UART_DR_PE 0x00000200 // UART Parity Error
+#define UART_DR_FE 0x00000100 // UART Framing Error
+#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received
+#define UART_DR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_RSR register.
+//
+//*****************************************************************************
+#define UART_RSR_OE 0x00000008 // UART Overrun Error
+#define UART_RSR_BE 0x00000004 // UART Break Error
+#define UART_RSR_PE 0x00000002 // UART Parity Error
+#define UART_RSR_FE 0x00000001 // UART Framing Error
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ECR register.
+//
+//*****************************************************************************
+#define UART_ECR_DATA_M 0x000000FF // Error Clear
+#define UART_ECR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_FR register.
+//
+//*****************************************************************************
+#define UART_FR_RI 0x00000100 // Ring Indicator
+#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty
+#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full
+#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full
+#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty
+#define UART_FR_BUSY 0x00000008 // UART Busy
+#define UART_FR_DCD 0x00000004 // Data Carrier Detect
+#define UART_FR_DSR 0x00000002 // Data Set Ready
+#define UART_FR_CTS 0x00000001 // Clear To Send
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ILPR register.
+//
+//*****************************************************************************
+#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor
+#define UART_ILPR_ILPDVSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IBRD register.
+//
+//*****************************************************************************
+#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor
+#define UART_IBRD_DIVINT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_FBRD register.
+//
+//*****************************************************************************
+#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor
+#define UART_FBRD_DIVFRAC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LCRH register.
+//
+//*****************************************************************************
+#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select
+#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length
+#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default)
+#define UART_LCRH_WLEN_6 0x00000020 // 6 bits
+#define UART_LCRH_WLEN_7 0x00000040 // 7 bits
+#define UART_LCRH_WLEN_8 0x00000060 // 8 bits
+#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs
+#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select
+#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select
+#define UART_LCRH_PEN 0x00000002 // UART Parity Enable
+#define UART_LCRH_BRK 0x00000001 // UART Send Break
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_CTL register.
+//
+//*****************************************************************************
+#define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send
+#define UART_CTL_RTSEN 0x00004000 // Enable Request to Send
+#define UART_CTL_RTS 0x00000800 // Request to Send
+#define UART_CTL_DTR 0x00000400 // Data Terminal Ready
+#define UART_CTL_RXE 0x00000200 // UART Receive Enable
+#define UART_CTL_TXE 0x00000100 // UART Transmit Enable
+#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable
+#define UART_CTL_LIN 0x00000040 // LIN Mode Enable
+#define UART_CTL_HSE 0x00000020 // High-Speed Enable
+#define UART_CTL_EOT 0x00000010 // End of Transmission
+#define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support
+#define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode
+#define UART_CTL_SIREN 0x00000002 // UART SIR Enable
+#define UART_CTL_UARTEN 0x00000001 // UART Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IFLS register.
+//
+//*****************************************************************************
+#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO
+ // Level Select
+#define UART_IFLS_RX1_8 0x00000000 // RX FIFO >= 1/8 full
+#define UART_IFLS_RX2_8 0x00000008 // RX FIFO >= 1/4 full
+#define UART_IFLS_RX4_8 0x00000010 // RX FIFO >= 1/2 full (default)
+#define UART_IFLS_RX6_8 0x00000018 // RX FIFO >= 3/4 full
+#define UART_IFLS_RX7_8 0x00000020 // RX FIFO >= 7/8 full
+#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO
+ // Level Select
+#define UART_IFLS_TX1_8 0x00000000 // TX FIFO <= 1/8 full
+#define UART_IFLS_TX2_8 0x00000001 // TX FIFO <= 1/4 full
+#define UART_IFLS_TX4_8 0x00000002 // TX FIFO <= 1/2 full (default)
+#define UART_IFLS_TX6_8 0x00000003 // TX FIFO <= 3/4 full
+#define UART_IFLS_TX7_8 0x00000004 // TX FIFO <= 7/8 full
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IM register.
+//
+//*****************************************************************************
+#define UART_IM_LME5IM 0x00008000 // LIN Mode Edge 5 Interrupt Mask
+#define UART_IM_LME1IM 0x00004000 // LIN Mode Edge 1 Interrupt Mask
+#define UART_IM_LMSBIM 0x00002000 // LIN Mode Sync Break Interrupt
+ // Mask
+#define UART_IM_9BITIM 0x00001000 // 9-Bit Mode Interrupt Mask
+#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt
+ // Mask
+#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask
+#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask
+#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt
+ // Mask
+#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt
+ // Mask
+#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask
+#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask
+#define UART_IM_DSRMIM 0x00000008 // UART Data Set Ready Modem
+ // Interrupt Mask
+#define UART_IM_DCDMIM 0x00000004 // UART Data Carrier Detect Modem
+ // Interrupt Mask
+#define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem
+ // Interrupt Mask
+#define UART_IM_RIMIM 0x00000001 // UART Ring Indicator Modem
+ // Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_RIS register.
+//
+//*****************************************************************************
+#define UART_RIS_LME5RIS 0x00008000 // LIN Mode Edge 5 Raw Interrupt
+ // Status
+#define UART_RIS_LME1RIS 0x00004000 // LIN Mode Edge 1 Raw Interrupt
+ // Status
+#define UART_RIS_LMSBRIS 0x00002000 // LIN Mode Sync Break Raw
+ // Interrupt Status
+#define UART_RIS_9BITRIS 0x00001000 // 9-Bit Mode Raw Interrupt Status
+#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt
+ // Status
+#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt
+ // Status
+#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt
+ // Status
+#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt
+ // Status
+#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw
+ // Interrupt Status
+#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt
+ // Status
+#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt
+ // Status
+#define UART_RIS_DSRRIS 0x00000008 // UART Data Set Ready Modem Raw
+ // Interrupt Status
+#define UART_RIS_DCDRIS 0x00000004 // UART Data Carrier Detect Modem
+ // Raw Interrupt Status
+#define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw
+ // Interrupt Status
+#define UART_RIS_RIRIS 0x00000001 // UART Ring Indicator Modem Raw
+ // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_MIS register.
+//
+//*****************************************************************************
+#define UART_MIS_LME5MIS 0x00008000 // LIN Mode Edge 5 Masked Interrupt
+ // Status
+#define UART_MIS_LME1MIS 0x00004000 // LIN Mode Edge 1 Masked Interrupt
+ // Status
+#define UART_MIS_LMSBMIS 0x00002000 // LIN Mode Sync Break Masked
+ // Interrupt Status
+#define UART_MIS_9BITMIS 0x00001000 // 9-Bit Mode Masked Interrupt
+ // Status
+#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked
+ // Interrupt Status
+#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked
+ // Interrupt Status
+#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked
+ // Interrupt Status
+#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked
+ // Interrupt Status
+#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked
+ // Interrupt Status
+#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt
+ // Status
+#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt
+ // Status
+#define UART_MIS_DSRMIS 0x00000008 // UART Data Set Ready Modem Masked
+ // Interrupt Status
+#define UART_MIS_DCDMIS 0x00000004 // UART Data Carrier Detect Modem
+ // Masked Interrupt Status
+#define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked
+ // Interrupt Status
+#define UART_MIS_RIMIS 0x00000001 // UART Ring Indicator Modem Masked
+ // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ICR register.
+//
+//*****************************************************************************
+#define UART_ICR_LME5IC 0x00008000 // LIN Mode Edge 5 Interrupt Clear
+#define UART_ICR_LME1IC 0x00004000 // LIN Mode Edge 1 Interrupt Clear
+#define UART_ICR_LMSBIC 0x00002000 // LIN Mode Sync Break Interrupt
+ // Clear
+#define UART_ICR_9BITIC 0x00001000 // 9-Bit Mode Interrupt Clear
+#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear
+#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear
+#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear
+#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear
+#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear
+#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear
+#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear
+#define UART_ICR_DSRMIC 0x00000008 // UART Data Set Ready Modem
+ // Interrupt Clear
+#define UART_ICR_DCDMIC 0x00000004 // UART Data Carrier Detect Modem
+ // Interrupt Clear
+#define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem
+ // Interrupt Clear
+#define UART_ICR_RIMIC 0x00000001 // UART Ring Indicator Modem
+ // Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_DMACTL register.
+//
+//*****************************************************************************
+#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error
+#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable
+#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LCTL register.
+//
+//*****************************************************************************
+#define UART_LCTL_BLEN_M 0x00000030 // Sync Break Length
+#define UART_LCTL_BLEN_13T 0x00000000 // Sync break length is 13T bits
+ // (default)
+#define UART_LCTL_BLEN_14T 0x00000010 // Sync break length is 14T bits
+#define UART_LCTL_BLEN_15T 0x00000020 // Sync break length is 15T bits
+#define UART_LCTL_BLEN_16T 0x00000030 // Sync break length is 16T bits
+#define UART_LCTL_MASTER 0x00000001 // LIN Master Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LSS register.
+//
+//*****************************************************************************
+#define UART_LSS_TSS_M 0x0000FFFF // Timer Snap Shot
+#define UART_LSS_TSS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LTIM register.
+//
+//*****************************************************************************
+#define UART_LTIM_TIMER_M 0x0000FFFF // Timer Value
+#define UART_LTIM_TIMER_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_9BITADDR
+// register.
+//
+//*****************************************************************************
+#define UART_9BITADDR_9BITEN 0x00008000 // Enable 9-Bit Mode
+#define UART_9BITADDR_ADDR_M 0x000000FF // Self Address for 9-Bit Mode
+#define UART_9BITADDR_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_9BITAMASK
+// register.
+//
+//*****************************************************************************
+#define UART_9BITAMASK_MASK_M 0x000000FF // Self Address Mask for 9-Bit Mode
+#define UART_9BITAMASK_MASK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_PP register.
+//
+//*****************************************************************************
+#define UART_PP_NB 0x00000002 // 9-Bit Support
+#define UART_PP_SC 0x00000001 // Smart Card Support
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_CC register.
+//
+//*****************************************************************************
+#define UART_CC_CS_M 0x0000000F // UART Baud Clock Source
+#define UART_CC_CS_SYSCLK 0x00000000 // The system clock (default)
+#define UART_CC_CS_PIOSC 0x00000005 // PIOSC
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the UART register offsets.
+//
+//*****************************************************************************
+#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte
+#define UART_O_PeriphID4 0x00000FD0
+#define UART_O_PeriphID5 0x00000FD4
+#define UART_O_PeriphID6 0x00000FD8
+#define UART_O_PeriphID7 0x00000FDC
+#define UART_O_PeriphID0 0x00000FE0
+#define UART_O_PeriphID1 0x00000FE4
+#define UART_O_PeriphID2 0x00000FE8
+#define UART_O_PeriphID3 0x00000FEC
+#define UART_O_PCellID0 0x00000FF0
+#define UART_O_PCellID1 0x00000FF4
+#define UART_O_PCellID2 0x00000FF8
+#define UART_O_PCellID3 0x00000FFC
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the UART_O_DR
+// register.
+//
+//*****************************************************************************
+#define UART_DR_DATA_MASK 0x000000FF // UART data
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the UART_O_IBRD
+// register.
+//
+//*****************************************************************************
+#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the UART_O_FBRD
+// register.
+//
+//*****************************************************************************
+#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the UART_O_LCR_H
+// register.
+//
+//*****************************************************************************
+#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select
+#define UART_LCR_H_WLEN 0x00000060 // Word length
+#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data
+#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data
+#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data
+#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data
+#define UART_LCR_H_FEN 0x00000010 // Enable FIFO
+#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select
+#define UART_LCR_H_EPS 0x00000004 // Even Parity Select
+#define UART_LCR_H_PEN 0x00000002 // Parity Enable
+#define UART_LCR_H_BRK 0x00000001 // Send Break
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the UART_O_IFLS
+// register.
+//
+//*****************************************************************************
+#define UART_IFLS_RX_MASK 0x00000038 // RX FIFO level mask
+#define UART_IFLS_TX_MASK 0x00000007 // TX FIFO level mask
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the UART_O_ICR
+// register.
+//
+//*****************************************************************************
+#define UART_ICR_LME5MIC 0x00008000 // LIN Mode Edge 5 Interrupt Clear
+#define UART_ICR_LME1MIC 0x00004000 // LIN Mode Edge 1 Interrupt Clear
+#define UART_ICR_LMSBMIC 0x00002000 // LIN Mode Sync Break Interrupt
+ // Clear
+#define UART_RSR_ANY (UART_RSR_OE | UART_RSR_BE | UART_RSR_PE | \
+ UART_RSR_FE)
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the Reset Values for UART
+// Registers.
+//
+//*****************************************************************************
+#define UART_RV_CTL 0x00000300
+#define UART_RV_PCellID1 0x000000F0
+#define UART_RV_PCellID3 0x000000B1
+#define UART_RV_FR 0x00000090
+#define UART_RV_PeriphID2 0x00000018
+#define UART_RV_IFLS 0x00000012
+#define UART_RV_PeriphID0 0x00000011
+#define UART_RV_PCellID0 0x0000000D
+#define UART_RV_PCellID2 0x00000005
+#define UART_RV_PeriphID3 0x00000001
+#define UART_RV_PeriphID4 0x00000000
+#define UART_RV_LCR_H 0x00000000
+#define UART_RV_PeriphID6 0x00000000
+#define UART_RV_DR 0x00000000
+#define UART_RV_RSR 0x00000000
+#define UART_RV_ECR 0x00000000
+#define UART_RV_PeriphID5 0x00000000
+#define UART_RV_RIS 0x00000000
+#define UART_RV_FBRD 0x00000000
+#define UART_RV_IM 0x00000000
+#define UART_RV_MIS 0x00000000
+#define UART_RV_ICR 0x00000000
+#define UART_RV_PeriphID1 0x00000000
+#define UART_RV_PeriphID7 0x00000000
+#define UART_RV_IBRD 0x00000000
+
+#endif
+
+#endif // __HW_UART_H__
diff --git a/inc/hw_udma.h b/inc/hw_udma.h new file mode 100644 index 0000000..c562cdf --- /dev/null +++ b/inc/hw_udma.h @@ -0,0 +1,446 @@ +//*****************************************************************************
+//
+// hw_udma.h - Macros for use in accessing the UDMA registers.
+//
+// Copyright (c) 2007-2012 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 9453 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_UDMA_H__
+#define __HW_UDMA_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Micro Direct Memory Access register
+// addresses.
+//
+//*****************************************************************************
+#define UDMA_STAT 0x400FF000 // DMA Status
+#define UDMA_CFG 0x400FF004 // DMA Configuration
+#define UDMA_CTLBASE 0x400FF008 // DMA Channel Control Base Pointer
+#define UDMA_ALTBASE 0x400FF00C // DMA Alternate Channel Control
+ // Base Pointer
+#define UDMA_WAITSTAT 0x400FF010 // DMA Channel Wait-on-Request
+ // Status
+#define UDMA_SWREQ 0x400FF014 // DMA Channel Software Request
+#define UDMA_USEBURSTSET 0x400FF018 // DMA Channel Useburst Set
+#define UDMA_USEBURSTCLR 0x400FF01C // DMA Channel Useburst Clear
+#define UDMA_REQMASKSET 0x400FF020 // DMA Channel Request Mask Set
+#define UDMA_REQMASKCLR 0x400FF024 // DMA Channel Request Mask Clear
+#define UDMA_ENASET 0x400FF028 // DMA Channel Enable Set
+#define UDMA_ENACLR 0x400FF02C // DMA Channel Enable Clear
+#define UDMA_ALTSET 0x400FF030 // DMA Channel Primary Alternate
+ // Set
+#define UDMA_ALTCLR 0x400FF034 // DMA Channel Primary Alternate
+ // Clear
+#define UDMA_PRIOSET 0x400FF038 // DMA Channel Priority Set
+#define UDMA_PRIOCLR 0x400FF03C // DMA Channel Priority Clear
+#define UDMA_ERRCLR 0x400FF04C // DMA Bus Error Clear
+#define UDMA_CHASGN 0x400FF500 // DMA Channel Assignment
+#define UDMA_CHIS 0x400FF504 // DMA Channel Interrupt Status
+#define UDMA_CHMAP0 0x400FF510 // DMA Channel Map Select 0
+#define UDMA_CHMAP1 0x400FF514 // DMA Channel Map Select 1
+#define UDMA_CHMAP2 0x400FF518 // DMA Channel Map Select 2
+#define UDMA_CHMAP3 0x400FF51C // DMA Channel Map Select 3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_STAT register.
+//
+//*****************************************************************************
+#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available uDMA Channels Minus 1
+#define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine Status
+#define UDMA_STAT_STATE_IDLE 0x00000000 // Idle
+#define UDMA_STAT_STATE_RD_CTRL 0x00000010 // Reading channel controller data
+#define UDMA_STAT_STATE_RD_SRCENDP \
+ 0x00000020 // Reading source end pointer
+#define UDMA_STAT_STATE_RD_DSTENDP \
+ 0x00000030 // Reading destination end pointer
+#define UDMA_STAT_STATE_RD_SRCDAT \
+ 0x00000040 // Reading source data
+#define UDMA_STAT_STATE_WR_DSTDAT \
+ 0x00000050 // Writing destination data
+#define UDMA_STAT_STATE_WAIT 0x00000060 // Waiting for uDMA request to
+ // clear
+#define UDMA_STAT_STATE_WR_CTRL 0x00000070 // Writing channel controller data
+#define UDMA_STAT_STATE_STALL 0x00000080 // Stalled
+#define UDMA_STAT_STATE_DONE 0x00000090 // Done
+#define UDMA_STAT_STATE_UNDEF 0x000000A0 // Undefined
+#define UDMA_STAT_MASTEN 0x00000001 // Master Enable Status
+#define UDMA_STAT_DMACHANS_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CFG register.
+//
+//*****************************************************************************
+#define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CTLBASE register.
+//
+//*****************************************************************************
+#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address
+#define UDMA_CTLBASE_ADDR_S 10
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTBASE register.
+//
+//*****************************************************************************
+#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address
+ // Pointer
+#define UDMA_ALTBASE_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_WAITSTAT register.
+//
+//*****************************************************************************
+#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF // Channel [n] Wait Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_SWREQ register.
+//
+//*****************************************************************************
+#define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_USEBURSTSET
+// register.
+//
+//*****************************************************************************
+#define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF // Channel [n] Useburst Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_USEBURSTCLR
+// register.
+//
+//*****************************************************************************
+#define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF // Channel [n] Useburst Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_REQMASKSET
+// register.
+//
+//*****************************************************************************
+#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_REQMASKCLR
+// register.
+//
+//*****************************************************************************
+#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ENASET register.
+//
+//*****************************************************************************
+#define UDMA_ENASET_SET_M 0xFFFFFFFF // Channel [n] Enable Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ENACLR register.
+//
+//*****************************************************************************
+#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTSET register.
+//
+//*****************************************************************************
+#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTCLR register.
+//
+//*****************************************************************************
+#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_PRIOSET register.
+//
+//*****************************************************************************
+#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_PRIOCLR register.
+//
+//*****************************************************************************
+#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ERRCLR register.
+//
+//*****************************************************************************
+#define UDMA_ERRCLR_ERRCLR 0x00000001 // uDMA Bus Error Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHASGN register.
+//
+//*****************************************************************************
+#define UDMA_CHASGN_M 0xFFFFFFFF // Channel [n] Assignment Select
+#define UDMA_CHASGN_PRIMARY 0x00000000 // Use the primary channel
+ // assignment
+#define UDMA_CHASGN_SECONDARY 0x00000001 // Use the secondary channel
+ // assignment
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHIS register.
+//
+//*****************************************************************************
+#define UDMA_CHIS_M 0xFFFFFFFF // Channel [n] Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHMAP0 register.
+//
+//*****************************************************************************
+#define UDMA_CHMAP0_CH7SEL_M 0xF0000000 // uDMA Channel 7 Source Select
+#define UDMA_CHMAP0_CH6SEL_M 0x0F000000 // uDMA Channel 6 Source Select
+#define UDMA_CHMAP0_CH5SEL_M 0x00F00000 // uDMA Channel 5 Source Select
+#define UDMA_CHMAP0_CH4SEL_M 0x000F0000 // uDMA Channel 4 Source Select
+#define UDMA_CHMAP0_CH3SEL_M 0x0000F000 // uDMA Channel 3 Source Select
+#define UDMA_CHMAP0_CH2SEL_M 0x00000F00 // uDMA Channel 2 Source Select
+#define UDMA_CHMAP0_CH1SEL_M 0x000000F0 // uDMA Channel 1 Source Select
+#define UDMA_CHMAP0_CH0SEL_M 0x0000000F // uDMA Channel 0 Source Select
+#define UDMA_CHMAP0_CH7SEL_S 28
+#define UDMA_CHMAP0_CH6SEL_S 24
+#define UDMA_CHMAP0_CH5SEL_S 20
+#define UDMA_CHMAP0_CH4SEL_S 16
+#define UDMA_CHMAP0_CH3SEL_S 12
+#define UDMA_CHMAP0_CH2SEL_S 8
+#define UDMA_CHMAP0_CH1SEL_S 4
+#define UDMA_CHMAP0_CH0SEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHMAP1 register.
+//
+//*****************************************************************************
+#define UDMA_CHMAP1_CH15SEL_M 0xF0000000 // uDMA Channel 15 Source Select
+#define UDMA_CHMAP1_CH14SEL_M 0x0F000000 // uDMA Channel 14 Source Select
+#define UDMA_CHMAP1_CH13SEL_M 0x00F00000 // uDMA Channel 13 Source Select
+#define UDMA_CHMAP1_CH12SEL_M 0x000F0000 // uDMA Channel 12 Source Select
+#define UDMA_CHMAP1_CH11SEL_M 0x0000F000 // uDMA Channel 11 Source Select
+#define UDMA_CHMAP1_CH10SEL_M 0x00000F00 // uDMA Channel 10 Source Select
+#define UDMA_CHMAP1_CH9SEL_M 0x000000F0 // uDMA Channel 9 Source Select
+#define UDMA_CHMAP1_CH8SEL_M 0x0000000F // uDMA Channel 8 Source Select
+#define UDMA_CHMAP1_CH15SEL_S 28
+#define UDMA_CHMAP1_CH14SEL_S 24
+#define UDMA_CHMAP1_CH13SEL_S 20
+#define UDMA_CHMAP1_CH12SEL_S 16
+#define UDMA_CHMAP1_CH11SEL_S 12
+#define UDMA_CHMAP1_CH10SEL_S 8
+#define UDMA_CHMAP1_CH9SEL_S 4
+#define UDMA_CHMAP1_CH8SEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHMAP2 register.
+//
+//*****************************************************************************
+#define UDMA_CHMAP2_CH23SEL_M 0xF0000000 // uDMA Channel 23 Source Select
+#define UDMA_CHMAP2_CH22SEL_M 0x0F000000 // uDMA Channel 22 Source Select
+#define UDMA_CHMAP2_CH21SEL_M 0x00F00000 // uDMA Channel 21 Source Select
+#define UDMA_CHMAP2_CH20SEL_M 0x000F0000 // uDMA Channel 20 Source Select
+#define UDMA_CHMAP2_CH19SEL_M 0x0000F000 // uDMA Channel 19 Source Select
+#define UDMA_CHMAP2_CH18SEL_M 0x00000F00 // uDMA Channel 18 Source Select
+#define UDMA_CHMAP2_CH17SEL_M 0x000000F0 // uDMA Channel 17 Source Select
+#define UDMA_CHMAP2_CH16SEL_M 0x0000000F // uDMA Channel 16 Source Select
+#define UDMA_CHMAP2_CH23SEL_S 28
+#define UDMA_CHMAP2_CH22SEL_S 24
+#define UDMA_CHMAP2_CH21SEL_S 20
+#define UDMA_CHMAP2_CH20SEL_S 16
+#define UDMA_CHMAP2_CH19SEL_S 12
+#define UDMA_CHMAP2_CH18SEL_S 8
+#define UDMA_CHMAP2_CH17SEL_S 4
+#define UDMA_CHMAP2_CH16SEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHMAP3 register.
+//
+//*****************************************************************************
+#define UDMA_CHMAP3_CH31SEL_M 0xF0000000 // uDMA Channel 31 Source Select
+#define UDMA_CHMAP3_CH30SEL_M 0x0F000000 // uDMA Channel 30 Source Select
+#define UDMA_CHMAP3_CH29SEL_M 0x00F00000 // uDMA Channel 29 Source Select
+#define UDMA_CHMAP3_CH28SEL_M 0x000F0000 // uDMA Channel 28 Source Select
+#define UDMA_CHMAP3_CH27SEL_M 0x0000F000 // uDMA Channel 27 Source Select
+#define UDMA_CHMAP3_CH26SEL_M 0x00000F00 // uDMA Channel 26 Source Select
+#define UDMA_CHMAP3_CH25SEL_M 0x000000F0 // uDMA Channel 25 Source Select
+#define UDMA_CHMAP3_CH24SEL_M 0x0000000F // uDMA Channel 24 Source Select
+#define UDMA_CHMAP3_CH31SEL_S 28
+#define UDMA_CHMAP3_CH30SEL_S 24
+#define UDMA_CHMAP3_CH29SEL_S 20
+#define UDMA_CHMAP3_CH28SEL_S 16
+#define UDMA_CHMAP3_CH27SEL_S 12
+#define UDMA_CHMAP3_CH26SEL_S 8
+#define UDMA_CHMAP3_CH25SEL_S 4
+#define UDMA_CHMAP3_CH24SEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the Micro Direct Memory Access (uDMA) offsets.
+//
+//*****************************************************************************
+#define UDMA_O_SRCENDP 0x00000000 // DMA Channel Source Address End
+ // Pointer
+#define UDMA_O_DSTENDP 0x00000004 // DMA Channel Destination Address
+ // End Pointer
+#define UDMA_O_CHCTL 0x00000008 // DMA Channel Control Word
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_SRCENDP register.
+//
+//*****************************************************************************
+#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer
+#define UDMA_SRCENDP_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_DSTENDP register.
+//
+//*****************************************************************************
+#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer
+#define UDMA_DSTENDP_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_CHCTL register.
+//
+//*****************************************************************************
+#define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment
+#define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte
+#define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word
+#define UDMA_CHCTL_DSTINC_32 0x80000000 // Word
+#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment
+#define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size
+#define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte
+#define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word
+#define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word
+#define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment
+#define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte
+#define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word
+#define UDMA_CHCTL_SRCINC_32 0x08000000 // Word
+#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment
+#define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size
+#define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte
+#define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word
+#define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word
+#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size
+#define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer
+#define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers
+#define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers
+#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers
+#define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers
+#define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers
+#define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers
+#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers
+#define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers
+#define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers
+#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers
+#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1)
+#define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst
+#define UDMA_CHCTL_XFERMODE_M 0x00000007 // uDMA Transfer Mode
+#define UDMA_CHCTL_XFERMODE_STOP \
+ 0x00000000 // Stop
+#define UDMA_CHCTL_XFERMODE_BASIC \
+ 0x00000001 // Basic
+#define UDMA_CHCTL_XFERMODE_AUTO \
+ 0x00000002 // Auto-Request
+#define UDMA_CHCTL_XFERMODE_PINGPONG \
+ 0x00000003 // Ping-Pong
+#define UDMA_CHCTL_XFERMODE_MEM_SG \
+ 0x00000004 // Memory Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_MEM_SGA \
+ 0x00000005 // Alternate Memory Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_PER_SG \
+ 0x00000006 // Peripheral Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_PER_SGA \
+ 0x00000007 // Alternate Peripheral
+ // Scatter-Gather
+#define UDMA_CHCTL_XFERSIZE_S 4
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the Micro Direct Memory Access
+// register addresses.
+//
+//*****************************************************************************
+#define UDMA_CHALT 0x400FF500 // DMA Channel Alternate Select
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the UDMA_ENASET
+// register.
+//
+//*****************************************************************************
+#define UDMA_ENASET_CHENSET_M 0xFFFFFFFF // Channel [n] Enable Set
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the UDMA_CHALT
+// register.
+//
+//*****************************************************************************
+#define UDMA_CHALT_M 0xFFFFFFFF // Channel [n] Alternate Assignment
+ // Select
+
+#endif
+
+#endif // __HW_UDMA_H__
diff --git a/inc/hw_usb.h b/inc/hw_usb.h new file mode 100644 index 0000000..cd5cbb5 --- /dev/null +++ b/inc/hw_usb.h @@ -0,0 +1,4611 @@ +//*****************************************************************************
+//
+// hw_usb.h - Macros for use in accessing the USB registers.
+//
+// Copyright (c) 2007-2012 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 9453 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_USB_H__
+#define __HW_USB_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Univeral Serial Bus register offsets.
+//
+//*****************************************************************************
+#define USB_O_FADDR 0x00000000 // USB Device Functional Address
+#define USB_O_POWER 0x00000001 // USB Power
+#define USB_O_TXIS 0x00000002 // USB Transmit Interrupt Status
+#define USB_O_RXIS 0x00000004 // USB Receive Interrupt Status
+#define USB_O_TXIE 0x00000006 // USB Transmit Interrupt Enable
+#define USB_O_RXIE 0x00000008 // USB Receive Interrupt Enable
+#define USB_O_IS 0x0000000A // USB General Interrupt Status
+#define USB_O_IE 0x0000000B // USB Interrupt Enable
+#define USB_O_FRAME 0x0000000C // USB Frame Value
+#define USB_O_EPIDX 0x0000000E // USB Endpoint Index
+#define USB_O_TEST 0x0000000F // USB Test Mode
+#define USB_O_FIFO0 0x00000020 // USB FIFO Endpoint 0
+#define USB_O_FIFO1 0x00000024 // USB FIFO Endpoint 1
+#define USB_O_FIFO2 0x00000028 // USB FIFO Endpoint 2
+#define USB_O_FIFO3 0x0000002C // USB FIFO Endpoint 3
+#define USB_O_FIFO4 0x00000030 // USB FIFO Endpoint 4
+#define USB_O_FIFO5 0x00000034 // USB FIFO Endpoint 5
+#define USB_O_FIFO6 0x00000038 // USB FIFO Endpoint 6
+#define USB_O_FIFO7 0x0000003C // USB FIFO Endpoint 7
+#define USB_O_FIFO8 0x00000040 // USB FIFO Endpoint 8
+#define USB_O_FIFO9 0x00000044 // USB FIFO Endpoint 9
+#define USB_O_FIFO10 0x00000048 // USB FIFO Endpoint 10
+#define USB_O_FIFO11 0x0000004C // USB FIFO Endpoint 11
+#define USB_O_FIFO12 0x00000050 // USB FIFO Endpoint 12
+#define USB_O_FIFO13 0x00000054 // USB FIFO Endpoint 13
+#define USB_O_FIFO14 0x00000058 // USB FIFO Endpoint 14
+#define USB_O_FIFO15 0x0000005C // USB FIFO Endpoint 15
+#define USB_O_DEVCTL 0x00000060 // USB Device Control
+#define USB_O_TXFIFOSZ 0x00000062 // USB Transmit Dynamic FIFO Sizing
+#define USB_O_RXFIFOSZ 0x00000063 // USB Receive Dynamic FIFO Sizing
+#define USB_O_TXFIFOADD 0x00000064 // USB Transmit FIFO Start Address
+#define USB_O_RXFIFOADD 0x00000066 // USB Receive FIFO Start Address
+#define USB_O_CONTIM 0x0000007A // USB Connect Timing
+#define USB_O_VPLEN 0x0000007B // USB OTG VBUS Pulse Timing
+#define USB_O_FSEOF 0x0000007D // USB Full-Speed Last Transaction
+ // to End of Frame Timing
+#define USB_O_LSEOF 0x0000007E // USB Low-Speed Last Transaction
+ // to End of Frame Timing
+#define USB_O_TXFUNCADDR0 0x00000080 // USB Transmit Functional Address
+ // Endpoint 0
+#define USB_O_TXHUBADDR0 0x00000082 // USB Transmit Hub Address
+ // Endpoint 0
+#define USB_O_TXHUBPORT0 0x00000083 // USB Transmit Hub Port Endpoint 0
+#define USB_O_TXFUNCADDR1 0x00000088 // USB Transmit Functional Address
+ // Endpoint 1
+#define USB_O_TXHUBADDR1 0x0000008A // USB Transmit Hub Address
+ // Endpoint 1
+#define USB_O_TXHUBPORT1 0x0000008B // USB Transmit Hub Port Endpoint 1
+#define USB_O_RXFUNCADDR1 0x0000008C // USB Receive Functional Address
+ // Endpoint 1
+#define USB_O_RXHUBADDR1 0x0000008E // USB Receive Hub Address Endpoint
+ // 1
+#define USB_O_RXHUBPORT1 0x0000008F // USB Receive Hub Port Endpoint 1
+#define USB_O_TXFUNCADDR2 0x00000090 // USB Transmit Functional Address
+ // Endpoint 2
+#define USB_O_TXHUBADDR2 0x00000092 // USB Transmit Hub Address
+ // Endpoint 2
+#define USB_O_TXHUBPORT2 0x00000093 // USB Transmit Hub Port Endpoint 2
+#define USB_O_RXFUNCADDR2 0x00000094 // USB Receive Functional Address
+ // Endpoint 2
+#define USB_O_RXHUBADDR2 0x00000096 // USB Receive Hub Address Endpoint
+ // 2
+#define USB_O_RXHUBPORT2 0x00000097 // USB Receive Hub Port Endpoint 2
+#define USB_O_TXFUNCADDR3 0x00000098 // USB Transmit Functional Address
+ // Endpoint 3
+#define USB_O_TXHUBADDR3 0x0000009A // USB Transmit Hub Address
+ // Endpoint 3
+#define USB_O_TXHUBPORT3 0x0000009B // USB Transmit Hub Port Endpoint 3
+#define USB_O_RXFUNCADDR3 0x0000009C // USB Receive Functional Address
+ // Endpoint 3
+#define USB_O_RXHUBADDR3 0x0000009E // USB Receive Hub Address Endpoint
+ // 3
+#define USB_O_RXHUBPORT3 0x0000009F // USB Receive Hub Port Endpoint 3
+#define USB_O_TXFUNCADDR4 0x000000A0 // USB Transmit Functional Address
+ // Endpoint 4
+#define USB_O_TXHUBADDR4 0x000000A2 // USB Transmit Hub Address
+ // Endpoint 4
+#define USB_O_TXHUBPORT4 0x000000A3 // USB Transmit Hub Port Endpoint 4
+#define USB_O_RXFUNCADDR4 0x000000A4 // USB Receive Functional Address
+ // Endpoint 4
+#define USB_O_RXHUBADDR4 0x000000A6 // USB Receive Hub Address Endpoint
+ // 4
+#define USB_O_RXHUBPORT4 0x000000A7 // USB Receive Hub Port Endpoint 4
+#define USB_O_TXFUNCADDR5 0x000000A8 // USB Transmit Functional Address
+ // Endpoint 5
+#define USB_O_TXHUBADDR5 0x000000AA // USB Transmit Hub Address
+ // Endpoint 5
+#define USB_O_TXHUBPORT5 0x000000AB // USB Transmit Hub Port Endpoint 5
+#define USB_O_RXFUNCADDR5 0x000000AC // USB Receive Functional Address
+ // Endpoint 5
+#define USB_O_RXHUBADDR5 0x000000AE // USB Receive Hub Address Endpoint
+ // 5
+#define USB_O_RXHUBPORT5 0x000000AF // USB Receive Hub Port Endpoint 5
+#define USB_O_TXFUNCADDR6 0x000000B0 // USB Transmit Functional Address
+ // Endpoint 6
+#define USB_O_TXHUBADDR6 0x000000B2 // USB Transmit Hub Address
+ // Endpoint 6
+#define USB_O_TXHUBPORT6 0x000000B3 // USB Transmit Hub Port Endpoint 6
+#define USB_O_RXFUNCADDR6 0x000000B4 // USB Receive Functional Address
+ // Endpoint 6
+#define USB_O_RXHUBADDR6 0x000000B6 // USB Receive Hub Address Endpoint
+ // 6
+#define USB_O_RXHUBPORT6 0x000000B7 // USB Receive Hub Port Endpoint 6
+#define USB_O_TXFUNCADDR7 0x000000B8 // USB Transmit Functional Address
+ // Endpoint 7
+#define USB_O_TXHUBADDR7 0x000000BA // USB Transmit Hub Address
+ // Endpoint 7
+#define USB_O_TXHUBPORT7 0x000000BB // USB Transmit Hub Port Endpoint 7
+#define USB_O_RXFUNCADDR7 0x000000BC // USB Receive Functional Address
+ // Endpoint 7
+#define USB_O_RXHUBADDR7 0x000000BE // USB Receive Hub Address Endpoint
+ // 7
+#define USB_O_RXHUBPORT7 0x000000BF // USB Receive Hub Port Endpoint 7
+#define USB_O_TXFUNCADDR8 0x000000C0 // USB Transmit Functional Address
+ // Endpoint 8
+#define USB_O_TXHUBADDR8 0x000000C2 // USB Transmit Hub Address
+ // Endpoint 8
+#define USB_O_TXHUBPORT8 0x000000C3 // USB Transmit Hub Port Endpoint 8
+#define USB_O_RXFUNCADDR8 0x000000C4 // USB Receive Functional Address
+ // Endpoint 8
+#define USB_O_RXHUBADDR8 0x000000C6 // USB Receive Hub Address Endpoint
+ // 8
+#define USB_O_RXHUBPORT8 0x000000C7 // USB Receive Hub Port Endpoint 8
+#define USB_O_TXFUNCADDR9 0x000000C8 // USB Transmit Functional Address
+ // Endpoint 9
+#define USB_O_TXHUBADDR9 0x000000CA // USB Transmit Hub Address
+ // Endpoint 9
+#define USB_O_TXHUBPORT9 0x000000CB // USB Transmit Hub Port Endpoint 9
+#define USB_O_RXFUNCADDR9 0x000000CC // USB Receive Functional Address
+ // Endpoint 9
+#define USB_O_RXHUBADDR9 0x000000CE // USB Receive Hub Address Endpoint
+ // 9
+#define USB_O_RXHUBPORT9 0x000000CF // USB Receive Hub Port Endpoint 9
+#define USB_O_TXFUNCADDR10 0x000000D0 // USB Transmit Functional Address
+ // Endpoint 10
+#define USB_O_TXHUBADDR10 0x000000D2 // USB Transmit Hub Address
+ // Endpoint 10
+#define USB_O_TXHUBPORT10 0x000000D3 // USB Transmit Hub Port Endpoint
+ // 10
+#define USB_O_RXFUNCADDR10 0x000000D4 // USB Receive Functional Address
+ // Endpoint 10
+#define USB_O_RXHUBADDR10 0x000000D6 // USB Receive Hub Address Endpoint
+ // 10
+#define USB_O_RXHUBPORT10 0x000000D7 // USB Receive Hub Port Endpoint 10
+#define USB_O_TXFUNCADDR11 0x000000D8 // USB Transmit Functional Address
+ // Endpoint 11
+#define USB_O_TXHUBADDR11 0x000000DA // USB Transmit Hub Address
+ // Endpoint 11
+#define USB_O_TXHUBPORT11 0x000000DB // USB Transmit Hub Port Endpoint
+ // 11
+#define USB_O_RXFUNCADDR11 0x000000DC // USB Receive Functional Address
+ // Endpoint 11
+#define USB_O_RXHUBADDR11 0x000000DE // USB Receive Hub Address Endpoint
+ // 11
+#define USB_O_RXHUBPORT11 0x000000DF // USB Receive Hub Port Endpoint 11
+#define USB_O_TXFUNCADDR12 0x000000E0 // USB Transmit Functional Address
+ // Endpoint 12
+#define USB_O_TXHUBADDR12 0x000000E2 // USB Transmit Hub Address
+ // Endpoint 12
+#define USB_O_TXHUBPORT12 0x000000E3 // USB Transmit Hub Port Endpoint
+ // 12
+#define USB_O_RXFUNCADDR12 0x000000E4 // USB Receive Functional Address
+ // Endpoint 12
+#define USB_O_RXHUBADDR12 0x000000E6 // USB Receive Hub Address Endpoint
+ // 12
+#define USB_O_RXHUBPORT12 0x000000E7 // USB Receive Hub Port Endpoint 12
+#define USB_O_TXFUNCADDR13 0x000000E8 // USB Transmit Functional Address
+ // Endpoint 13
+#define USB_O_TXHUBADDR13 0x000000EA // USB Transmit Hub Address
+ // Endpoint 13
+#define USB_O_TXHUBPORT13 0x000000EB // USB Transmit Hub Port Endpoint
+ // 13
+#define USB_O_RXFUNCADDR13 0x000000EC // USB Receive Functional Address
+ // Endpoint 13
+#define USB_O_RXHUBADDR13 0x000000EE // USB Receive Hub Address Endpoint
+ // 13
+#define USB_O_RXHUBPORT13 0x000000EF // USB Receive Hub Port Endpoint 13
+#define USB_O_TXFUNCADDR14 0x000000F0 // USB Transmit Functional Address
+ // Endpoint 14
+#define USB_O_TXHUBADDR14 0x000000F2 // USB Transmit Hub Address
+ // Endpoint 14
+#define USB_O_TXHUBPORT14 0x000000F3 // USB Transmit Hub Port Endpoint
+ // 14
+#define USB_O_RXFUNCADDR14 0x000000F4 // USB Receive Functional Address
+ // Endpoint 14
+#define USB_O_RXHUBADDR14 0x000000F6 // USB Receive Hub Address Endpoint
+ // 14
+#define USB_O_RXHUBPORT14 0x000000F7 // USB Receive Hub Port Endpoint 14
+#define USB_O_TXFUNCADDR15 0x000000F8 // USB Transmit Functional Address
+ // Endpoint 15
+#define USB_O_TXHUBADDR15 0x000000FA // USB Transmit Hub Address
+ // Endpoint 15
+#define USB_O_TXHUBPORT15 0x000000FB // USB Transmit Hub Port Endpoint
+ // 15
+#define USB_O_RXFUNCADDR15 0x000000FC // USB Receive Functional Address
+ // Endpoint 15
+#define USB_O_RXHUBADDR15 0x000000FE // USB Receive Hub Address Endpoint
+ // 15
+#define USB_O_RXHUBPORT15 0x000000FF // USB Receive Hub Port Endpoint 15
+#define USB_O_CSRL0 0x00000102 // USB Control and Status Endpoint
+ // 0 Low
+#define USB_O_CSRH0 0x00000103 // USB Control and Status Endpoint
+ // 0 High
+#define USB_O_COUNT0 0x00000108 // USB Receive Byte Count Endpoint
+ // 0
+#define USB_O_TYPE0 0x0000010A // USB Type Endpoint 0
+#define USB_O_NAKLMT 0x0000010B // USB NAK Limit
+#define USB_O_TXMAXP1 0x00000110 // USB Maximum Transmit Data
+ // Endpoint 1
+#define USB_O_TXCSRL1 0x00000112 // USB Transmit Control and Status
+ // Endpoint 1 Low
+#define USB_O_TXCSRH1 0x00000113 // USB Transmit Control and Status
+ // Endpoint 1 High
+#define USB_O_RXMAXP1 0x00000114 // USB Maximum Receive Data
+ // Endpoint 1
+#define USB_O_RXCSRL1 0x00000116 // USB Receive Control and Status
+ // Endpoint 1 Low
+#define USB_O_RXCSRH1 0x00000117 // USB Receive Control and Status
+ // Endpoint 1 High
+#define USB_O_RXCOUNT1 0x00000118 // USB Receive Byte Count Endpoint
+ // 1
+#define USB_O_TXTYPE1 0x0000011A // USB Host Transmit Configure Type
+ // Endpoint 1
+#define USB_O_TXINTERVAL1 0x0000011B // USB Host Transmit Interval
+ // Endpoint 1
+#define USB_O_RXTYPE1 0x0000011C // USB Host Configure Receive Type
+ // Endpoint 1
+#define USB_O_RXINTERVAL1 0x0000011D // USB Host Receive Polling
+ // Interval Endpoint 1
+#define USB_O_TXMAXP2 0x00000120 // USB Maximum Transmit Data
+ // Endpoint 2
+#define USB_O_TXCSRL2 0x00000122 // USB Transmit Control and Status
+ // Endpoint 2 Low
+#define USB_O_TXCSRH2 0x00000123 // USB Transmit Control and Status
+ // Endpoint 2 High
+#define USB_O_RXMAXP2 0x00000124 // USB Maximum Receive Data
+ // Endpoint 2
+#define USB_O_RXCSRL2 0x00000126 // USB Receive Control and Status
+ // Endpoint 2 Low
+#define USB_O_RXCSRH2 0x00000127 // USB Receive Control and Status
+ // Endpoint 2 High
+#define USB_O_RXCOUNT2 0x00000128 // USB Receive Byte Count Endpoint
+ // 2
+#define USB_O_TXTYPE2 0x0000012A // USB Host Transmit Configure Type
+ // Endpoint 2
+#define USB_O_TXINTERVAL2 0x0000012B // USB Host Transmit Interval
+ // Endpoint 2
+#define USB_O_RXTYPE2 0x0000012C // USB Host Configure Receive Type
+ // Endpoint 2
+#define USB_O_RXINTERVAL2 0x0000012D // USB Host Receive Polling
+ // Interval Endpoint 2
+#define USB_O_TXMAXP3 0x00000130 // USB Maximum Transmit Data
+ // Endpoint 3
+#define USB_O_TXCSRL3 0x00000132 // USB Transmit Control and Status
+ // Endpoint 3 Low
+#define USB_O_TXCSRH3 0x00000133 // USB Transmit Control and Status
+ // Endpoint 3 High
+#define USB_O_RXMAXP3 0x00000134 // USB Maximum Receive Data
+ // Endpoint 3
+#define USB_O_RXCSRL3 0x00000136 // USB Receive Control and Status
+ // Endpoint 3 Low
+#define USB_O_RXCSRH3 0x00000137 // USB Receive Control and Status
+ // Endpoint 3 High
+#define USB_O_RXCOUNT3 0x00000138 // USB Receive Byte Count Endpoint
+ // 3
+#define USB_O_TXTYPE3 0x0000013A // USB Host Transmit Configure Type
+ // Endpoint 3
+#define USB_O_TXINTERVAL3 0x0000013B // USB Host Transmit Interval
+ // Endpoint 3
+#define USB_O_RXTYPE3 0x0000013C // USB Host Configure Receive Type
+ // Endpoint 3
+#define USB_O_RXINTERVAL3 0x0000013D // USB Host Receive Polling
+ // Interval Endpoint 3
+#define USB_O_TXMAXP4 0x00000140 // USB Maximum Transmit Data
+ // Endpoint 4
+#define USB_O_TXCSRL4 0x00000142 // USB Transmit Control and Status
+ // Endpoint 4 Low
+#define USB_O_TXCSRH4 0x00000143 // USB Transmit Control and Status
+ // Endpoint 4 High
+#define USB_O_RXMAXP4 0x00000144 // USB Maximum Receive Data
+ // Endpoint 4
+#define USB_O_RXCSRL4 0x00000146 // USB Receive Control and Status
+ // Endpoint 4 Low
+#define USB_O_RXCSRH4 0x00000147 // USB Receive Control and Status
+ // Endpoint 4 High
+#define USB_O_RXCOUNT4 0x00000148 // USB Receive Byte Count Endpoint
+ // 4
+#define USB_O_TXTYPE4 0x0000014A // USB Host Transmit Configure Type
+ // Endpoint 4
+#define USB_O_TXINTERVAL4 0x0000014B // USB Host Transmit Interval
+ // Endpoint 4
+#define USB_O_RXTYPE4 0x0000014C // USB Host Configure Receive Type
+ // Endpoint 4
+#define USB_O_RXINTERVAL4 0x0000014D // USB Host Receive Polling
+ // Interval Endpoint 4
+#define USB_O_TXMAXP5 0x00000150 // USB Maximum Transmit Data
+ // Endpoint 5
+#define USB_O_TXCSRL5 0x00000152 // USB Transmit Control and Status
+ // Endpoint 5 Low
+#define USB_O_TXCSRH5 0x00000153 // USB Transmit Control and Status
+ // Endpoint 5 High
+#define USB_O_RXMAXP5 0x00000154 // USB Maximum Receive Data
+ // Endpoint 5
+#define USB_O_RXCSRL5 0x00000156 // USB Receive Control and Status
+ // Endpoint 5 Low
+#define USB_O_RXCSRH5 0x00000157 // USB Receive Control and Status
+ // Endpoint 5 High
+#define USB_O_RXCOUNT5 0x00000158 // USB Receive Byte Count Endpoint
+ // 5
+#define USB_O_TXTYPE5 0x0000015A // USB Host Transmit Configure Type
+ // Endpoint 5
+#define USB_O_TXINTERVAL5 0x0000015B // USB Host Transmit Interval
+ // Endpoint 5
+#define USB_O_RXTYPE5 0x0000015C // USB Host Configure Receive Type
+ // Endpoint 5
+#define USB_O_RXINTERVAL5 0x0000015D // USB Host Receive Polling
+ // Interval Endpoint 5
+#define USB_O_TXMAXP6 0x00000160 // USB Maximum Transmit Data
+ // Endpoint 6
+#define USB_O_TXCSRL6 0x00000162 // USB Transmit Control and Status
+ // Endpoint 6 Low
+#define USB_O_TXCSRH6 0x00000163 // USB Transmit Control and Status
+ // Endpoint 6 High
+#define USB_O_RXMAXP6 0x00000164 // USB Maximum Receive Data
+ // Endpoint 6
+#define USB_O_RXCSRL6 0x00000166 // USB Receive Control and Status
+ // Endpoint 6 Low
+#define USB_O_RXCSRH6 0x00000167 // USB Receive Control and Status
+ // Endpoint 6 High
+#define USB_O_RXCOUNT6 0x00000168 // USB Receive Byte Count Endpoint
+ // 6
+#define USB_O_TXTYPE6 0x0000016A // USB Host Transmit Configure Type
+ // Endpoint 6
+#define USB_O_TXINTERVAL6 0x0000016B // USB Host Transmit Interval
+ // Endpoint 6
+#define USB_O_RXTYPE6 0x0000016C // USB Host Configure Receive Type
+ // Endpoint 6
+#define USB_O_RXINTERVAL6 0x0000016D // USB Host Receive Polling
+ // Interval Endpoint 6
+#define USB_O_TXMAXP7 0x00000170 // USB Maximum Transmit Data
+ // Endpoint 7
+#define USB_O_TXCSRL7 0x00000172 // USB Transmit Control and Status
+ // Endpoint 7 Low
+#define USB_O_TXCSRH7 0x00000173 // USB Transmit Control and Status
+ // Endpoint 7 High
+#define USB_O_RXMAXP7 0x00000174 // USB Maximum Receive Data
+ // Endpoint 7
+#define USB_O_RXCSRL7 0x00000176 // USB Receive Control and Status
+ // Endpoint 7 Low
+#define USB_O_RXCSRH7 0x00000177 // USB Receive Control and Status
+ // Endpoint 7 High
+#define USB_O_RXCOUNT7 0x00000178 // USB Receive Byte Count Endpoint
+ // 7
+#define USB_O_TXTYPE7 0x0000017A // USB Host Transmit Configure Type
+ // Endpoint 7
+#define USB_O_TXINTERVAL7 0x0000017B // USB Host Transmit Interval
+ // Endpoint 7
+#define USB_O_RXTYPE7 0x0000017C // USB Host Configure Receive Type
+ // Endpoint 7
+#define USB_O_RXINTERVAL7 0x0000017D // USB Host Receive Polling
+ // Interval Endpoint 7
+#define USB_O_TXMAXP8 0x00000180 // USB Maximum Transmit Data
+ // Endpoint 8
+#define USB_O_TXCSRL8 0x00000182 // USB Transmit Control and Status
+ // Endpoint 8 Low
+#define USB_O_TXCSRH8 0x00000183 // USB Transmit Control and Status
+ // Endpoint 8 High
+#define USB_O_RXMAXP8 0x00000184 // USB Maximum Receive Data
+ // Endpoint 8
+#define USB_O_RXCSRL8 0x00000186 // USB Receive Control and Status
+ // Endpoint 8 Low
+#define USB_O_RXCSRH8 0x00000187 // USB Receive Control and Status
+ // Endpoint 8 High
+#define USB_O_RXCOUNT8 0x00000188 // USB Receive Byte Count Endpoint
+ // 8
+#define USB_O_TXTYPE8 0x0000018A // USB Host Transmit Configure Type
+ // Endpoint 8
+#define USB_O_TXINTERVAL8 0x0000018B // USB Host Transmit Interval
+ // Endpoint 8
+#define USB_O_RXTYPE8 0x0000018C // USB Host Configure Receive Type
+ // Endpoint 8
+#define USB_O_RXINTERVAL8 0x0000018D // USB Host Receive Polling
+ // Interval Endpoint 8
+#define USB_O_TXMAXP9 0x00000190 // USB Maximum Transmit Data
+ // Endpoint 9
+#define USB_O_TXCSRL9 0x00000192 // USB Transmit Control and Status
+ // Endpoint 9 Low
+#define USB_O_TXCSRH9 0x00000193 // USB Transmit Control and Status
+ // Endpoint 9 High
+#define USB_O_RXMAXP9 0x00000194 // USB Maximum Receive Data
+ // Endpoint 9
+#define USB_O_RXCSRL9 0x00000196 // USB Receive Control and Status
+ // Endpoint 9 Low
+#define USB_O_RXCSRH9 0x00000197 // USB Receive Control and Status
+ // Endpoint 9 High
+#define USB_O_RXCOUNT9 0x00000198 // USB Receive Byte Count Endpoint
+ // 9
+#define USB_O_TXTYPE9 0x0000019A // USB Host Transmit Configure Type
+ // Endpoint 9
+#define USB_O_TXINTERVAL9 0x0000019B // USB Host Transmit Interval
+ // Endpoint 9
+#define USB_O_RXTYPE9 0x0000019C // USB Host Configure Receive Type
+ // Endpoint 9
+#define USB_O_RXINTERVAL9 0x0000019D // USB Host Receive Polling
+ // Interval Endpoint 9
+#define USB_O_TXMAXP10 0x000001A0 // USB Maximum Transmit Data
+ // Endpoint 10
+#define USB_O_TXCSRL10 0x000001A2 // USB Transmit Control and Status
+ // Endpoint 10 Low
+#define USB_O_TXCSRH10 0x000001A3 // USB Transmit Control and Status
+ // Endpoint 10 High
+#define USB_O_RXMAXP10 0x000001A4 // USB Maximum Receive Data
+ // Endpoint 10
+#define USB_O_RXCSRL10 0x000001A6 // USB Receive Control and Status
+ // Endpoint 10 Low
+#define USB_O_RXCSRH10 0x000001A7 // USB Receive Control and Status
+ // Endpoint 10 High
+#define USB_O_RXCOUNT10 0x000001A8 // USB Receive Byte Count Endpoint
+ // 10
+#define USB_O_TXTYPE10 0x000001AA // USB Host Transmit Configure Type
+ // Endpoint 10
+#define USB_O_TXINTERVAL10 0x000001AB // USB Host Transmit Interval
+ // Endpoint 10
+#define USB_O_RXTYPE10 0x000001AC // USB Host Configure Receive Type
+ // Endpoint 10
+#define USB_O_RXINTERVAL10 0x000001AD // USB Host Receive Polling
+ // Interval Endpoint 10
+#define USB_O_TXMAXP11 0x000001B0 // USB Maximum Transmit Data
+ // Endpoint 11
+#define USB_O_TXCSRL11 0x000001B2 // USB Transmit Control and Status
+ // Endpoint 11 Low
+#define USB_O_TXCSRH11 0x000001B3 // USB Transmit Control and Status
+ // Endpoint 11 High
+#define USB_O_RXMAXP11 0x000001B4 // USB Maximum Receive Data
+ // Endpoint 11
+#define USB_O_RXCSRL11 0x000001B6 // USB Receive Control and Status
+ // Endpoint 11 Low
+#define USB_O_RXCSRH11 0x000001B7 // USB Receive Control and Status
+ // Endpoint 11 High
+#define USB_O_RXCOUNT11 0x000001B8 // USB Receive Byte Count Endpoint
+ // 11
+#define USB_O_TXTYPE11 0x000001BA // USB Host Transmit Configure Type
+ // Endpoint 11
+#define USB_O_TXINTERVAL11 0x000001BB // USB Host Transmit Interval
+ // Endpoint 11
+#define USB_O_RXTYPE11 0x000001BC // USB Host Configure Receive Type
+ // Endpoint 11
+#define USB_O_RXINTERVAL11 0x000001BD // USB Host Receive Polling
+ // Interval Endpoint 11
+#define USB_O_TXMAXP12 0x000001C0 // USB Maximum Transmit Data
+ // Endpoint 12
+#define USB_O_TXCSRL12 0x000001C2 // USB Transmit Control and Status
+ // Endpoint 12 Low
+#define USB_O_TXCSRH12 0x000001C3 // USB Transmit Control and Status
+ // Endpoint 12 High
+#define USB_O_RXMAXP12 0x000001C4 // USB Maximum Receive Data
+ // Endpoint 12
+#define USB_O_RXCSRL12 0x000001C6 // USB Receive Control and Status
+ // Endpoint 12 Low
+#define USB_O_RXCSRH12 0x000001C7 // USB Receive Control and Status
+ // Endpoint 12 High
+#define USB_O_RXCOUNT12 0x000001C8 // USB Receive Byte Count Endpoint
+ // 12
+#define USB_O_TXTYPE12 0x000001CA // USB Host Transmit Configure Type
+ // Endpoint 12
+#define USB_O_TXINTERVAL12 0x000001CB // USB Host Transmit Interval
+ // Endpoint 12
+#define USB_O_RXTYPE12 0x000001CC // USB Host Configure Receive Type
+ // Endpoint 12
+#define USB_O_RXINTERVAL12 0x000001CD // USB Host Receive Polling
+ // Interval Endpoint 12
+#define USB_O_TXMAXP13 0x000001D0 // USB Maximum Transmit Data
+ // Endpoint 13
+#define USB_O_TXCSRL13 0x000001D2 // USB Transmit Control and Status
+ // Endpoint 13 Low
+#define USB_O_TXCSRH13 0x000001D3 // USB Transmit Control and Status
+ // Endpoint 13 High
+#define USB_O_RXMAXP13 0x000001D4 // USB Maximum Receive Data
+ // Endpoint 13
+#define USB_O_RXCSRL13 0x000001D6 // USB Receive Control and Status
+ // Endpoint 13 Low
+#define USB_O_RXCSRH13 0x000001D7 // USB Receive Control and Status
+ // Endpoint 13 High
+#define USB_O_RXCOUNT13 0x000001D8 // USB Receive Byte Count Endpoint
+ // 13
+#define USB_O_TXTYPE13 0x000001DA // USB Host Transmit Configure Type
+ // Endpoint 13
+#define USB_O_TXINTERVAL13 0x000001DB // USB Host Transmit Interval
+ // Endpoint 13
+#define USB_O_RXTYPE13 0x000001DC // USB Host Configure Receive Type
+ // Endpoint 13
+#define USB_O_RXINTERVAL13 0x000001DD // USB Host Receive Polling
+ // Interval Endpoint 13
+#define USB_O_TXMAXP14 0x000001E0 // USB Maximum Transmit Data
+ // Endpoint 14
+#define USB_O_TXCSRL14 0x000001E2 // USB Transmit Control and Status
+ // Endpoint 14 Low
+#define USB_O_TXCSRH14 0x000001E3 // USB Transmit Control and Status
+ // Endpoint 14 High
+#define USB_O_RXMAXP14 0x000001E4 // USB Maximum Receive Data
+ // Endpoint 14
+#define USB_O_RXCSRL14 0x000001E6 // USB Receive Control and Status
+ // Endpoint 14 Low
+#define USB_O_RXCSRH14 0x000001E7 // USB Receive Control and Status
+ // Endpoint 14 High
+#define USB_O_RXCOUNT14 0x000001E8 // USB Receive Byte Count Endpoint
+ // 14
+#define USB_O_TXTYPE14 0x000001EA // USB Host Transmit Configure Type
+ // Endpoint 14
+#define USB_O_TXINTERVAL14 0x000001EB // USB Host Transmit Interval
+ // Endpoint 14
+#define USB_O_RXTYPE14 0x000001EC // USB Host Configure Receive Type
+ // Endpoint 14
+#define USB_O_RXINTERVAL14 0x000001ED // USB Host Receive Polling
+ // Interval Endpoint 14
+#define USB_O_TXMAXP15 0x000001F0 // USB Maximum Transmit Data
+ // Endpoint 15
+#define USB_O_TXCSRL15 0x000001F2 // USB Transmit Control and Status
+ // Endpoint 15 Low
+#define USB_O_TXCSRH15 0x000001F3 // USB Transmit Control and Status
+ // Endpoint 15 High
+#define USB_O_RXMAXP15 0x000001F4 // USB Maximum Receive Data
+ // Endpoint 15
+#define USB_O_RXCSRL15 0x000001F6 // USB Receive Control and Status
+ // Endpoint 15 Low
+#define USB_O_RXCSRH15 0x000001F7 // USB Receive Control and Status
+ // Endpoint 15 High
+#define USB_O_RXCOUNT15 0x000001F8 // USB Receive Byte Count Endpoint
+ // 15
+#define USB_O_TXTYPE15 0x000001FA // USB Host Transmit Configure Type
+ // Endpoint 15
+#define USB_O_TXINTERVAL15 0x000001FB // USB Host Transmit Interval
+ // Endpoint 15
+#define USB_O_RXTYPE15 0x000001FC // USB Host Configure Receive Type
+ // Endpoint 15
+#define USB_O_RXINTERVAL15 0x000001FD // USB Host Receive Polling
+ // Interval Endpoint 15
+#define USB_O_RQPKTCOUNT1 0x00000304 // USB Request Packet Count in
+ // Block Transfer Endpoint 1
+#define USB_O_RQPKTCOUNT2 0x00000308 // USB Request Packet Count in
+ // Block Transfer Endpoint 2
+#define USB_O_RQPKTCOUNT3 0x0000030C // USB Request Packet Count in
+ // Block Transfer Endpoint 3
+#define USB_O_RQPKTCOUNT4 0x00000310 // USB Request Packet Count in
+ // Block Transfer Endpoint 4
+#define USB_O_RQPKTCOUNT5 0x00000314 // USB Request Packet Count in
+ // Block Transfer Endpoint 5
+#define USB_O_RQPKTCOUNT6 0x00000318 // USB Request Packet Count in
+ // Block Transfer Endpoint 6
+#define USB_O_RQPKTCOUNT7 0x0000031C // USB Request Packet Count in
+ // Block Transfer Endpoint 7
+#define USB_O_RQPKTCOUNT8 0x00000320 // USB Request Packet Count in
+ // Block Transfer Endpoint 8
+#define USB_O_RQPKTCOUNT9 0x00000324 // USB Request Packet Count in
+ // Block Transfer Endpoint 9
+#define USB_O_RQPKTCOUNT10 0x00000328 // USB Request Packet Count in
+ // Block Transfer Endpoint 10
+#define USB_O_RQPKTCOUNT11 0x0000032C // USB Request Packet Count in
+ // Block Transfer Endpoint 11
+#define USB_O_RQPKTCOUNT12 0x00000330 // USB Request Packet Count in
+ // Block Transfer Endpoint 12
+#define USB_O_RQPKTCOUNT13 0x00000334 // USB Request Packet Count in
+ // Block Transfer Endpoint 13
+#define USB_O_RQPKTCOUNT14 0x00000338 // USB Request Packet Count in
+ // Block Transfer Endpoint 14
+#define USB_O_RQPKTCOUNT15 0x0000033C // USB Request Packet Count in
+ // Block Transfer Endpoint 15
+#define USB_O_RXDPKTBUFDIS 0x00000340 // USB Receive Double Packet Buffer
+ // Disable
+#define USB_O_TXDPKTBUFDIS 0x00000342 // USB Transmit Double Packet
+ // Buffer Disable
+#define USB_O_EPC 0x00000400 // USB External Power Control
+#define USB_O_EPCRIS 0x00000404 // USB External Power Control Raw
+ // Interrupt Status
+#define USB_O_EPCIM 0x00000408 // USB External Power Control
+ // Interrupt Mask
+#define USB_O_EPCISC 0x0000040C // USB External Power Control
+ // Interrupt Status and Clear
+#define USB_O_DRRIS 0x00000410 // USB Device RESUME Raw Interrupt
+ // Status
+#define USB_O_DRIM 0x00000414 // USB Device RESUME Interrupt Mask
+#define USB_O_DRISC 0x00000418 // USB Device RESUME Interrupt
+ // Status and Clear
+#define USB_O_GPCS 0x0000041C // USB General-Purpose Control and
+ // Status
+#define USB_O_VDC 0x00000430 // USB VBUS Droop Control
+#define USB_O_VDCRIS 0x00000434 // USB VBUS Droop Control Raw
+ // Interrupt Status
+#define USB_O_VDCIM 0x00000438 // USB VBUS Droop Control Interrupt
+ // Mask
+#define USB_O_VDCISC 0x0000043C // USB VBUS Droop Control Interrupt
+ // Status and Clear
+#define USB_O_IDVRIS 0x00000444 // USB ID Valid Detect Raw
+ // Interrupt Status
+#define USB_O_IDVIM 0x00000448 // USB ID Valid Detect Interrupt
+ // Mask
+#define USB_O_IDVISC 0x0000044C // USB ID Valid Detect Interrupt
+ // Status and Clear
+#define USB_O_DMASEL 0x00000450 // USB DMA Select
+#define USB_O_PP 0x00000FC0 // USB Peripheral Properties
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FADDR register.
+//
+//*****************************************************************************
+#define USB_FADDR_M 0x0000007F // Function Address
+#define USB_FADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_POWER register.
+//
+//*****************************************************************************
+#define USB_POWER_ISOUP 0x00000080 // Isochronous Update
+#define USB_POWER_SOFTCONN 0x00000040 // Soft Connect/Disconnect
+#define USB_POWER_RESET 0x00000008 // RESET Signaling
+#define USB_POWER_RESUME 0x00000004 // RESUME Signaling
+#define USB_POWER_SUSPEND 0x00000002 // SUSPEND Mode
+#define USB_POWER_PWRDNPHY 0x00000001 // Power Down PHY
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXIS register.
+//
+//*****************************************************************************
+#define USB_TXIS_EP15 0x00008000 // TX Endpoint 15 Interrupt
+#define USB_TXIS_EP14 0x00004000 // TX Endpoint 14 Interrupt
+#define USB_TXIS_EP13 0x00002000 // TX Endpoint 13 Interrupt
+#define USB_TXIS_EP12 0x00001000 // TX Endpoint 12 Interrupt
+#define USB_TXIS_EP11 0x00000800 // TX Endpoint 11 Interrupt
+#define USB_TXIS_EP10 0x00000400 // TX Endpoint 10 Interrupt
+#define USB_TXIS_EP9 0x00000200 // TX Endpoint 9 Interrupt
+#define USB_TXIS_EP8 0x00000100 // TX Endpoint 8 Interrupt
+#define USB_TXIS_EP7 0x00000080 // TX Endpoint 7 Interrupt
+#define USB_TXIS_EP6 0x00000040 // TX Endpoint 6 Interrupt
+#define USB_TXIS_EP5 0x00000020 // TX Endpoint 5 Interrupt
+#define USB_TXIS_EP4 0x00000010 // TX Endpoint 4 Interrupt
+#define USB_TXIS_EP3 0x00000008 // TX Endpoint 3 Interrupt
+#define USB_TXIS_EP2 0x00000004 // TX Endpoint 2 Interrupt
+#define USB_TXIS_EP1 0x00000002 // TX Endpoint 1 Interrupt
+#define USB_TXIS_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXIS register.
+//
+//*****************************************************************************
+#define USB_RXIS_EP15 0x00008000 // RX Endpoint 15 Interrupt
+#define USB_RXIS_EP14 0x00004000 // RX Endpoint 14 Interrupt
+#define USB_RXIS_EP13 0x00002000 // RX Endpoint 13 Interrupt
+#define USB_RXIS_EP12 0x00001000 // RX Endpoint 12 Interrupt
+#define USB_RXIS_EP11 0x00000800 // RX Endpoint 11 Interrupt
+#define USB_RXIS_EP10 0x00000400 // RX Endpoint 10 Interrupt
+#define USB_RXIS_EP9 0x00000200 // RX Endpoint 9 Interrupt
+#define USB_RXIS_EP8 0x00000100 // RX Endpoint 8 Interrupt
+#define USB_RXIS_EP7 0x00000080 // RX Endpoint 7 Interrupt
+#define USB_RXIS_EP6 0x00000040 // RX Endpoint 6 Interrupt
+#define USB_RXIS_EP5 0x00000020 // RX Endpoint 5 Interrupt
+#define USB_RXIS_EP4 0x00000010 // RX Endpoint 4 Interrupt
+#define USB_RXIS_EP3 0x00000008 // RX Endpoint 3 Interrupt
+#define USB_RXIS_EP2 0x00000004 // RX Endpoint 2 Interrupt
+#define USB_RXIS_EP1 0x00000002 // RX Endpoint 1 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXIE register.
+//
+//*****************************************************************************
+#define USB_TXIE_EP15 0x00008000 // TX Endpoint 15 Interrupt Enable
+#define USB_TXIE_EP14 0x00004000 // TX Endpoint 14 Interrupt Enable
+#define USB_TXIE_EP13 0x00002000 // TX Endpoint 13 Interrupt Enable
+#define USB_TXIE_EP12 0x00001000 // TX Endpoint 12 Interrupt Enable
+#define USB_TXIE_EP11 0x00000800 // TX Endpoint 11 Interrupt Enable
+#define USB_TXIE_EP10 0x00000400 // TX Endpoint 10 Interrupt Enable
+#define USB_TXIE_EP9 0x00000200 // TX Endpoint 9 Interrupt Enable
+#define USB_TXIE_EP8 0x00000100 // TX Endpoint 8 Interrupt Enable
+#define USB_TXIE_EP7 0x00000080 // TX Endpoint 7 Interrupt Enable
+#define USB_TXIE_EP6 0x00000040 // TX Endpoint 6 Interrupt Enable
+#define USB_TXIE_EP5 0x00000020 // TX Endpoint 5 Interrupt Enable
+#define USB_TXIE_EP4 0x00000010 // TX Endpoint 4 Interrupt Enable
+#define USB_TXIE_EP3 0x00000008 // TX Endpoint 3 Interrupt Enable
+#define USB_TXIE_EP2 0x00000004 // TX Endpoint 2 Interrupt Enable
+#define USB_TXIE_EP1 0x00000002 // TX Endpoint 1 Interrupt Enable
+#define USB_TXIE_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt
+ // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXIE register.
+//
+//*****************************************************************************
+#define USB_RXIE_EP15 0x00008000 // RX Endpoint 15 Interrupt Enable
+#define USB_RXIE_EP14 0x00004000 // RX Endpoint 14 Interrupt Enable
+#define USB_RXIE_EP13 0x00002000 // RX Endpoint 13 Interrupt Enable
+#define USB_RXIE_EP12 0x00001000 // RX Endpoint 12 Interrupt Enable
+#define USB_RXIE_EP11 0x00000800 // RX Endpoint 11 Interrupt Enable
+#define USB_RXIE_EP10 0x00000400 // RX Endpoint 10 Interrupt Enable
+#define USB_RXIE_EP9 0x00000200 // RX Endpoint 9 Interrupt Enable
+#define USB_RXIE_EP8 0x00000100 // RX Endpoint 8 Interrupt Enable
+#define USB_RXIE_EP7 0x00000080 // RX Endpoint 7 Interrupt Enable
+#define USB_RXIE_EP6 0x00000040 // RX Endpoint 6 Interrupt Enable
+#define USB_RXIE_EP5 0x00000020 // RX Endpoint 5 Interrupt Enable
+#define USB_RXIE_EP4 0x00000010 // RX Endpoint 4 Interrupt Enable
+#define USB_RXIE_EP3 0x00000008 // RX Endpoint 3 Interrupt Enable
+#define USB_RXIE_EP2 0x00000004 // RX Endpoint 2 Interrupt Enable
+#define USB_RXIE_EP1 0x00000002 // RX Endpoint 1 Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IS register.
+//
+//*****************************************************************************
+#define USB_IS_VBUSERR 0x00000080 // VBUS Error
+#define USB_IS_SESREQ 0x00000040 // SESSION REQUEST
+#define USB_IS_DISCON 0x00000020 // Session Disconnect
+#define USB_IS_CONN 0x00000010 // Session Connect
+#define USB_IS_SOF 0x00000008 // Start of Frame
+#define USB_IS_BABBLE 0x00000004 // Babble Detected
+#define USB_IS_RESET 0x00000004 // RESET Signaling Detected
+#define USB_IS_RESUME 0x00000002 // RESUME Signaling Detected
+#define USB_IS_SUSPEND 0x00000001 // SUSPEND Signaling Detected
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IE register.
+//
+//*****************************************************************************
+#define USB_IE_VBUSERR 0x00000080 // Enable VBUS Error Interrupt
+#define USB_IE_SESREQ 0x00000040 // Enable Session Request
+#define USB_IE_DISCON 0x00000020 // Enable Disconnect Interrupt
+#define USB_IE_CONN 0x00000010 // Enable Connect Interrupt
+#define USB_IE_SOF 0x00000008 // Enable Start-of-Frame Interrupt
+#define USB_IE_BABBLE 0x00000004 // Enable Babble Interrupt
+#define USB_IE_RESET 0x00000004 // Enable RESET Interrupt
+#define USB_IE_RESUME 0x00000002 // Enable RESUME Interrupt
+#define USB_IE_SUSPND 0x00000001 // Enable SUSPEND Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FRAME register.
+//
+//*****************************************************************************
+#define USB_FRAME_M 0x000007FF // Frame Number
+#define USB_FRAME_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPIDX register.
+//
+//*****************************************************************************
+#define USB_EPIDX_EPIDX_M 0x0000000F // Endpoint Index
+#define USB_EPIDX_EPIDX_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TEST register.
+//
+//*****************************************************************************
+#define USB_TEST_FORCEH 0x00000080 // Force Host Mode
+#define USB_TEST_FIFOACC 0x00000040 // FIFO Access
+#define USB_TEST_FORCEFS 0x00000020 // Force Full-Speed Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO0 register.
+//
+//*****************************************************************************
+#define USB_FIFO0_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO0_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO1 register.
+//
+//*****************************************************************************
+#define USB_FIFO1_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO1_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO2 register.
+//
+//*****************************************************************************
+#define USB_FIFO2_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO2_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO3 register.
+//
+//*****************************************************************************
+#define USB_FIFO3_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO3_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO4 register.
+//
+//*****************************************************************************
+#define USB_FIFO4_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO4_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO5 register.
+//
+//*****************************************************************************
+#define USB_FIFO5_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO5_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO6 register.
+//
+//*****************************************************************************
+#define USB_FIFO6_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO6_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO7 register.
+//
+//*****************************************************************************
+#define USB_FIFO7_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO7_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO8 register.
+//
+//*****************************************************************************
+#define USB_FIFO8_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO8_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO9 register.
+//
+//*****************************************************************************
+#define USB_FIFO9_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO9_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO10 register.
+//
+//*****************************************************************************
+#define USB_FIFO10_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO10_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO11 register.
+//
+//*****************************************************************************
+#define USB_FIFO11_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO11_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO12 register.
+//
+//*****************************************************************************
+#define USB_FIFO12_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO12_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO13 register.
+//
+//*****************************************************************************
+#define USB_FIFO13_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO13_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO14 register.
+//
+//*****************************************************************************
+#define USB_FIFO14_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO14_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO15 register.
+//
+//*****************************************************************************
+#define USB_FIFO15_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO15_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DEVCTL register.
+//
+//*****************************************************************************
+#define USB_DEVCTL_DEV 0x00000080 // Device Mode
+#define USB_DEVCTL_FSDEV 0x00000040 // Full-Speed Device Detected
+#define USB_DEVCTL_LSDEV 0x00000020 // Low-Speed Device Detected
+#define USB_DEVCTL_VBUS_M 0x00000018 // VBUS Level
+#define USB_DEVCTL_VBUS_NONE 0x00000000 // Below SessionEnd
+#define USB_DEVCTL_VBUS_SEND 0x00000008 // Above SessionEnd, below AValid
+#define USB_DEVCTL_VBUS_AVALID 0x00000010 // Above AValid, below VBUSValid
+#define USB_DEVCTL_VBUS_VALID 0x00000018 // Above VBUSValid
+#define USB_DEVCTL_HOST 0x00000004 // Host Mode
+#define USB_DEVCTL_HOSTREQ 0x00000002 // Host Request
+#define USB_DEVCTL_SESSION 0x00000001 // Session Start/End
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFIFOSZ register.
+//
+//*****************************************************************************
+#define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support
+#define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size
+#define USB_TXFIFOSZ_SIZE_8 0x00000000 // 8
+#define USB_TXFIFOSZ_SIZE_16 0x00000001 // 16
+#define USB_TXFIFOSZ_SIZE_32 0x00000002 // 32
+#define USB_TXFIFOSZ_SIZE_64 0x00000003 // 64
+#define USB_TXFIFOSZ_SIZE_128 0x00000004 // 128
+#define USB_TXFIFOSZ_SIZE_256 0x00000005 // 256
+#define USB_TXFIFOSZ_SIZE_512 0x00000006 // 512
+#define USB_TXFIFOSZ_SIZE_1024 0x00000007 // 1024
+#define USB_TXFIFOSZ_SIZE_2048 0x00000008 // 2048
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFIFOSZ register.
+//
+//*****************************************************************************
+#define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support
+#define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size
+#define USB_RXFIFOSZ_SIZE_8 0x00000000 // 8
+#define USB_RXFIFOSZ_SIZE_16 0x00000001 // 16
+#define USB_RXFIFOSZ_SIZE_32 0x00000002 // 32
+#define USB_RXFIFOSZ_SIZE_64 0x00000003 // 64
+#define USB_RXFIFOSZ_SIZE_128 0x00000004 // 128
+#define USB_RXFIFOSZ_SIZE_256 0x00000005 // 256
+#define USB_RXFIFOSZ_SIZE_512 0x00000006 // 512
+#define USB_RXFIFOSZ_SIZE_1024 0x00000007 // 1024
+#define USB_RXFIFOSZ_SIZE_2048 0x00000008 // 2048
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFIFOADD
+// register.
+//
+//*****************************************************************************
+#define USB_TXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address
+#define USB_TXFIFOADD_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFIFOADD
+// register.
+//
+//*****************************************************************************
+#define USB_RXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address
+#define USB_RXFIFOADD_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CONTIM register.
+//
+//*****************************************************************************
+#define USB_CONTIM_WTCON_M 0x000000F0 // Connect Wait
+#define USB_CONTIM_WTID_M 0x0000000F // Wait ID
+#define USB_CONTIM_WTCON_S 4
+#define USB_CONTIM_WTID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VPLEN register.
+//
+//*****************************************************************************
+#define USB_VPLEN_VPLEN_M 0x000000FF // VBUS Pulse Length
+#define USB_VPLEN_VPLEN_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FSEOF register.
+//
+//*****************************************************************************
+#define USB_FSEOF_FSEOFG_M 0x000000FF // Full-Speed End-of-Frame Gap
+#define USB_FSEOF_FSEOFG_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_LSEOF register.
+//
+//*****************************************************************************
+#define USB_LSEOF_LSEOFG_M 0x000000FF // Low-Speed End-of-Frame Gap
+#define USB_LSEOF_LSEOFG_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR0
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR0_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR0_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR0
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR0_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR0_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT0
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT0_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT0_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR1_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR1_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR1_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR1_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT1
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT1_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT1_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR1_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR1_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR1_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR1_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT1
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT1_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT1_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR2_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR2_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR2_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR2_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT2
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT2_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT2_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR2_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR2_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR2_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR2_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT2
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT2_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT2_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR3_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR3_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR3_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR3_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT3
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT3_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT3_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR3_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR3_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR3_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR3_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT3
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT3_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT3_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR4_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR4_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR4_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR4_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT4
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT4_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT4_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR4_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR4_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR4_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR4_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT4
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT4_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT4_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR5_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR5_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR5_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR5_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT5
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT5_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT5_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR5_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR5_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR5_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR5_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT5
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT5_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT5_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR6_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR6_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR6_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR6_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT6
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT6_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT6_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR6_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR6_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR6_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR6_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT6
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT6_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT6_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR7_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR7_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR7_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR7_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT7
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT7_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT7_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR7_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR7_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR7_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR7_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT7
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT7_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT7_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR8
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR8_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR8_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR8
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR8_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR8_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT8
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT8_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT8_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR8
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR8_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR8_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR8
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR8_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR8_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT8
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT8_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT8_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR9
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR9_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR9_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR9
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR9_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR9_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT9
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT9_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT9_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR9
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR9_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR9_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR9
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR9_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR9_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT9
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT9_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT9_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR10
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR10_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR10_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR10
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR10_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR10_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT10
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT10_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT10_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR10
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR10_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR10_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR10
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR10_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR10_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT10
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT10_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT10_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR11
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR11_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR11_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR11
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR11_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR11_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT11
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT11_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT11_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR11
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR11_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR11_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR11
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR11_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR11_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT11
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT11_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT11_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR12
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR12_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR12_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR12
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR12_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR12_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT12
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT12_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT12_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR12
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR12_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR12_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR12
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR12_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR12_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT12
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT12_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT12_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR13
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR13_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR13_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR13
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR13_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR13_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT13
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT13_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT13_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR13
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR13_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR13_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR13
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR13_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR13_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT13
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT13_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT13_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR14
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR14_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR14_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR14
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR14_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR14_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT14
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT14_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT14_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR14
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR14_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR14_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR14
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR14_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR14_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT14
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT14_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT14_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR15
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR15_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR15_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR15
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR15_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR15_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT15
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT15_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT15_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR15
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR15_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR15_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR15
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR15_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR15_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT15
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT15_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT15_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CSRL0 register.
+//
+//*****************************************************************************
+#define USB_CSRL0_NAKTO 0x00000080 // NAK Timeout
+#define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear
+#define USB_CSRL0_STATUS 0x00000040 // STATUS Packet
+#define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear
+#define USB_CSRL0_REQPKT 0x00000020 // Request Packet
+#define USB_CSRL0_STALL 0x00000020 // Send Stall
+#define USB_CSRL0_SETEND 0x00000010 // Setup End
+#define USB_CSRL0_ERROR 0x00000010 // Error
+#define USB_CSRL0_DATAEND 0x00000008 // Data End
+#define USB_CSRL0_SETUP 0x00000008 // Setup Packet
+#define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled
+#define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready
+#define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CSRH0 register.
+//
+//*****************************************************************************
+#define USB_CSRH0_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_CSRH0_DT 0x00000002 // Data Toggle
+#define USB_CSRH0_FLUSH 0x00000001 // Flush FIFO
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_COUNT0 register.
+//
+//*****************************************************************************
+#define USB_COUNT0_COUNT_M 0x0000007F // FIFO Count
+#define USB_COUNT0_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TYPE0 register.
+//
+//*****************************************************************************
+#define USB_TYPE0_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TYPE0_SPEED_FULL 0x00000080 // Full
+#define USB_TYPE0_SPEED_LOW 0x000000C0 // Low
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_NAKLMT register.
+//
+//*****************************************************************************
+#define USB_NAKLMT_NAKLMT_M 0x0000001F // EP0 NAK Limit
+#define USB_NAKLMT_NAKLMT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP1 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP1_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL1 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL1_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL1_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL1_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL1_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL1_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL1_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL1_ERROR 0x00000004 // Error
+#define USB_TXCSRL1_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL1_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL1_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH1 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH1_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH1_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH1_MODE 0x00000020 // Mode
+#define USB_TXCSRH1_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH1_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH1_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH1_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH1_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP1 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP1_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL1 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL1_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL1_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL1_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL1_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL1_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL1_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL1_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL1_OVER 0x00000004 // Overrun
+#define USB_RXCSRL1_ERROR 0x00000004 // Error
+#define USB_RXCSRL1_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL1_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH1 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH1_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH1_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH1_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH1_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH1_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH1_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH1_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH1_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH1_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT1 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT1_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT1_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE1 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE1_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE1_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE1_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE1_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE1_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE1_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE1_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE1_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE1_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE1_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE1_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL1
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL1_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL1_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL1_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL1_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE1 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE1_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE1_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE1_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE1_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE1_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE1_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE1_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE1_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE1_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE1_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE1_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL1
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL1_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL1_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL1_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL1_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP2 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP2_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL2 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL2_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL2_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL2_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL2_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL2_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL2_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL2_ERROR 0x00000004 // Error
+#define USB_TXCSRL2_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL2_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL2_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH2 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH2_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH2_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH2_MODE 0x00000020 // Mode
+#define USB_TXCSRH2_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH2_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH2_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH2_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH2_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP2 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP2_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL2 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL2_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL2_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL2_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL2_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL2_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL2_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL2_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL2_ERROR 0x00000004 // Error
+#define USB_RXCSRL2_OVER 0x00000004 // Overrun
+#define USB_RXCSRL2_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL2_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH2 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH2_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH2_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH2_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH2_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH2_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH2_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH2_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH2_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH2_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT2 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT2_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT2_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE2 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE2_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE2_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE2_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE2_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE2_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE2_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE2_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE2_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE2_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE2_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE2_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL2
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL2_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL2_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL2_NAKLMT_S \
+ 0
+#define USB_TXINTERVAL2_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE2 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE2_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE2_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE2_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE2_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE2_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE2_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE2_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE2_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE2_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE2_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE2_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL2
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL2_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL2_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL2_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL2_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP3 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP3_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL3 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL3_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL3_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL3_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL3_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL3_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL3_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL3_ERROR 0x00000004 // Error
+#define USB_TXCSRL3_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL3_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL3_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH3 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH3_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH3_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH3_MODE 0x00000020 // Mode
+#define USB_TXCSRH3_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH3_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH3_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH3_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH3_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP3 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP3_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL3 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL3_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL3_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL3_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL3_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL3_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL3_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL3_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL3_ERROR 0x00000004 // Error
+#define USB_RXCSRL3_OVER 0x00000004 // Overrun
+#define USB_RXCSRL3_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL3_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH3 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH3_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH3_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH3_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH3_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH3_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH3_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH3_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH3_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH3_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT3 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT3_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT3_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE3 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE3_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE3_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE3_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE3_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE3_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE3_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE3_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE3_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE3_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE3_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE3_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL3
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL3_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL3_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL3_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL3_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE3 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE3_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE3_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE3_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE3_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE3_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE3_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE3_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE3_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE3_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE3_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE3_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL3
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL3_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL3_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL3_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL3_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP4 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP4_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL4 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL4_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL4_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL4_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL4_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL4_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL4_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL4_ERROR 0x00000004 // Error
+#define USB_TXCSRL4_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL4_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL4_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH4 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH4_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH4_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH4_MODE 0x00000020 // Mode
+#define USB_TXCSRH4_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH4_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH4_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH4_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH4_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP4 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP4_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL4 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL4_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL4_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL4_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL4_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL4_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL4_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL4_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL4_OVER 0x00000004 // Overrun
+#define USB_RXCSRL4_ERROR 0x00000004 // Error
+#define USB_RXCSRL4_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL4_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH4 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH4_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH4_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH4_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH4_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH4_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH4_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH4_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH4_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH4_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT4 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT4_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT4_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE4 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE4_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE4_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE4_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE4_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE4_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE4_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE4_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE4_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE4_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE4_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE4_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL4
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL4_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL4_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL4_NAKLMT_S \
+ 0
+#define USB_TXINTERVAL4_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE4 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE4_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE4_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE4_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE4_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE4_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE4_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE4_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE4_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE4_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE4_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE4_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL4
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL4_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL4_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL4_NAKLMT_S \
+ 0
+#define USB_RXINTERVAL4_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP5 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP5_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL5 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL5_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL5_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL5_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL5_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL5_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL5_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL5_ERROR 0x00000004 // Error
+#define USB_TXCSRL5_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL5_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL5_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH5 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH5_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH5_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH5_MODE 0x00000020 // Mode
+#define USB_TXCSRH5_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH5_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH5_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH5_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH5_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP5 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP5_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL5 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL5_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL5_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL5_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL5_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL5_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL5_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL5_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL5_ERROR 0x00000004 // Error
+#define USB_RXCSRL5_OVER 0x00000004 // Overrun
+#define USB_RXCSRL5_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL5_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH5 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH5_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH5_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH5_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH5_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH5_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH5_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH5_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH5_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH5_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT5 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT5_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT5_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE5 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE5_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE5_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE5_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE5_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE5_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE5_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE5_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE5_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE5_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE5_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE5_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL5
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL5_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL5_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL5_NAKLMT_S \
+ 0
+#define USB_TXINTERVAL5_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE5 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE5_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE5_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE5_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE5_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE5_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE5_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE5_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE5_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE5_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE5_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE5_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL5
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL5_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL5_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL5_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL5_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP6 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP6_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL6 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL6_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL6_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL6_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL6_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL6_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL6_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL6_ERROR 0x00000004 // Error
+#define USB_TXCSRL6_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL6_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL6_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH6 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH6_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH6_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH6_MODE 0x00000020 // Mode
+#define USB_TXCSRH6_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH6_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH6_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH6_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH6_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP6 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP6_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL6 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL6_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL6_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL6_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL6_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL6_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL6_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL6_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL6_ERROR 0x00000004 // Error
+#define USB_RXCSRL6_OVER 0x00000004 // Overrun
+#define USB_RXCSRL6_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL6_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH6 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH6_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH6_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH6_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH6_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH6_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH6_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH6_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH6_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH6_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT6 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT6_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT6_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE6 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE6_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE6_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE6_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE6_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE6_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE6_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE6_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE6_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE6_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE6_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE6_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL6
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL6_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL6_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL6_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL6_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE6 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE6_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE6_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE6_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE6_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE6_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE6_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE6_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE6_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE6_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE6_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE6_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL6
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL6_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL6_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL6_NAKLMT_S \
+ 0
+#define USB_RXINTERVAL6_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP7 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP7_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL7 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL7_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL7_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL7_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL7_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL7_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL7_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL7_ERROR 0x00000004 // Error
+#define USB_TXCSRL7_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL7_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL7_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH7 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH7_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH7_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH7_MODE 0x00000020 // Mode
+#define USB_TXCSRH7_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH7_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH7_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH7_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH7_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP7 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP7_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL7 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL7_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL7_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL7_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL7_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL7_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL7_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL7_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL7_ERROR 0x00000004 // Error
+#define USB_RXCSRL7_OVER 0x00000004 // Overrun
+#define USB_RXCSRL7_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL7_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH7 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH7_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH7_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH7_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH7_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH7_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH7_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH7_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH7_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH7_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT7 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT7_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT7_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE7 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE7_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE7_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE7_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE7_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE7_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE7_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE7_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE7_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE7_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE7_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE7_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL7
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL7_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL7_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL7_NAKLMT_S \
+ 0
+#define USB_TXINTERVAL7_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE7 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE7_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE7_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE7_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE7_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE7_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE7_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE7_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE7_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE7_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE7_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE7_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL7
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL7_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL7_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL7_NAKLMT_S \
+ 0
+#define USB_RXINTERVAL7_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP8 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP8_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP8_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL8 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL8_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL8_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL8_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL8_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL8_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL8_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL8_ERROR 0x00000004 // Error
+#define USB_TXCSRL8_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL8_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL8_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH8 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH8_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH8_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH8_MODE 0x00000020 // Mode
+#define USB_TXCSRH8_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH8_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH8_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH8_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH8_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP8 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP8_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP8_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL8 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL8_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL8_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL8_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL8_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL8_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL8_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL8_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL8_OVER 0x00000004 // Overrun
+#define USB_RXCSRL8_ERROR 0x00000004 // Error
+#define USB_RXCSRL8_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL8_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH8 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH8_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH8_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH8_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH8_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH8_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH8_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH8_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH8_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH8_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT8 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT8_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT8_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE8 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE8_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE8_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE8_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE8_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE8_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE8_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE8_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE8_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE8_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE8_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE8_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL8
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL8_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL8_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL8_NAKLMT_S \
+ 0
+#define USB_TXINTERVAL8_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE8 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE8_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE8_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE8_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE8_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE8_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE8_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE8_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE8_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE8_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE8_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE8_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL8
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL8_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL8_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL8_NAKLMT_S \
+ 0
+#define USB_RXINTERVAL8_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP9 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP9_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP9_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL9 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL9_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL9_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL9_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL9_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL9_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL9_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL9_ERROR 0x00000004 // Error
+#define USB_TXCSRL9_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL9_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL9_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH9 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH9_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH9_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH9_MODE 0x00000020 // Mode
+#define USB_TXCSRH9_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH9_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH9_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH9_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH9_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP9 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP9_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP9_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL9 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL9_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL9_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL9_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL9_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL9_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL9_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL9_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL9_ERROR 0x00000004 // Error
+#define USB_RXCSRL9_OVER 0x00000004 // Overrun
+#define USB_RXCSRL9_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL9_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH9 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH9_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH9_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH9_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH9_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH9_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH9_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH9_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH9_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH9_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT9 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT9_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT9_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE9 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE9_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE9_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE9_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE9_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE9_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE9_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE9_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE9_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE9_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE9_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE9_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL9
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL9_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL9_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL9_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL9_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE9 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE9_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE9_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE9_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE9_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE9_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE9_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE9_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE9_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE9_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE9_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE9_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL9
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL9_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL9_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL9_NAKLMT_S \
+ 0
+#define USB_RXINTERVAL9_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP10 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP10_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP10_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL10 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL10_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL10_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL10_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL10_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL10_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL10_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL10_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL10_ERROR 0x00000004 // Error
+#define USB_TXCSRL10_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL10_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH10 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH10_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH10_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH10_MODE 0x00000020 // Mode
+#define USB_TXCSRH10_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH10_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH10_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH10_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH10_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP10 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP10_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP10_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL10 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL10_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL10_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL10_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL10_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL10_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL10_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL10_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL10_OVER 0x00000004 // Overrun
+#define USB_RXCSRL10_ERROR 0x00000004 // Error
+#define USB_RXCSRL10_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL10_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH10 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH10_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH10_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH10_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH10_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH10_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH10_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH10_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH10_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH10_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT10
+// register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT10_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT10_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE10 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE10_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE10_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE10_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE10_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE10_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE10_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE10_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE10_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE10_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE10_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE10_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL10
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL10_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL10_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL10_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL10_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE10 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE10_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE10_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE10_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE10_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE10_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE10_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE10_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE10_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE10_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE10_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE10_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL10
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL10_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL10_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL10_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL10_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP11 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP11_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP11_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL11 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL11_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL11_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL11_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL11_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL11_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL11_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL11_ERROR 0x00000004 // Error
+#define USB_TXCSRL11_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL11_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL11_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH11 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH11_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH11_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH11_MODE 0x00000020 // Mode
+#define USB_TXCSRH11_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH11_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH11_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH11_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH11_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP11 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP11_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP11_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL11 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL11_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL11_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL11_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL11_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL11_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL11_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL11_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL11_OVER 0x00000004 // Overrun
+#define USB_RXCSRL11_ERROR 0x00000004 // Error
+#define USB_RXCSRL11_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL11_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH11 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH11_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH11_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH11_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH11_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH11_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH11_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH11_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH11_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH11_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT11
+// register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT11_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT11_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE11 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE11_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE11_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE11_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE11_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE11_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE11_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE11_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE11_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE11_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE11_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE11_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL11
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL11_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL11_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL11_NAKLMT_S \
+ 0
+#define USB_TXINTERVAL11_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE11 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE11_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE11_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE11_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE11_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE11_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE11_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE11_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE11_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE11_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE11_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE11_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL11
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL11_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL11_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL11_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL11_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP12 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP12_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP12_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL12 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL12_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL12_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL12_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL12_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL12_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL12_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL12_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL12_ERROR 0x00000004 // Error
+#define USB_TXCSRL12_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL12_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH12 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH12_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH12_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH12_MODE 0x00000020 // Mode
+#define USB_TXCSRH12_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH12_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH12_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH12_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH12_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP12 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP12_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP12_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL12 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL12_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL12_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL12_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL12_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL12_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL12_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL12_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL12_ERROR 0x00000004 // Error
+#define USB_RXCSRL12_OVER 0x00000004 // Overrun
+#define USB_RXCSRL12_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL12_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH12 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH12_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH12_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH12_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH12_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH12_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH12_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH12_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH12_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH12_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT12
+// register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT12_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT12_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE12 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE12_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE12_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE12_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE12_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE12_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE12_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE12_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE12_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE12_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE12_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE12_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL12
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL12_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL12_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL12_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL12_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE12 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE12_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE12_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE12_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE12_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE12_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE12_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE12_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE12_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE12_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE12_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE12_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL12
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL12_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL12_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL12_NAKLMT_S \
+ 0
+#define USB_RXINTERVAL12_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP13 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP13_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP13_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL13 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL13_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL13_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL13_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL13_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL13_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL13_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL13_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL13_ERROR 0x00000004 // Error
+#define USB_TXCSRL13_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL13_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH13 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH13_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH13_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH13_MODE 0x00000020 // Mode
+#define USB_TXCSRH13_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH13_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH13_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH13_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH13_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP13 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP13_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP13_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL13 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL13_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL13_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL13_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL13_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL13_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL13_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL13_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL13_OVER 0x00000004 // Overrun
+#define USB_RXCSRL13_ERROR 0x00000004 // Error
+#define USB_RXCSRL13_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL13_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH13 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH13_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH13_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH13_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH13_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH13_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH13_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH13_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH13_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH13_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT13
+// register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT13_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT13_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE13 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE13_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE13_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE13_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE13_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE13_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE13_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE13_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE13_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE13_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE13_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE13_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL13
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL13_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL13_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL13_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL13_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE13 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE13_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE13_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE13_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE13_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE13_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE13_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE13_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE13_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE13_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE13_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE13_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL13
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL13_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL13_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL13_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL13_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP14 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP14_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP14_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL14 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL14_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL14_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL14_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL14_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL14_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL14_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL14_ERROR 0x00000004 // Error
+#define USB_TXCSRL14_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL14_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL14_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH14 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH14_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH14_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH14_MODE 0x00000020 // Mode
+#define USB_TXCSRH14_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH14_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH14_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH14_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH14_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP14 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP14_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP14_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL14 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL14_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL14_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL14_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL14_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL14_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL14_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL14_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL14_OVER 0x00000004 // Overrun
+#define USB_RXCSRL14_ERROR 0x00000004 // Error
+#define USB_RXCSRL14_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL14_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH14 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH14_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH14_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH14_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH14_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH14_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH14_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH14_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH14_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH14_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT14
+// register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT14_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT14_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE14 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE14_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE14_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE14_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE14_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE14_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE14_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE14_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE14_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE14_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE14_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE14_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL14
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL14_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL14_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL14_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL14_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE14 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE14_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE14_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE14_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE14_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE14_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE14_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE14_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE14_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE14_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE14_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE14_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL14
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL14_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL14_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL14_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL14_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP15 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP15_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP15_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL15 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL15_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL15_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL15_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL15_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL15_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL15_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL15_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL15_ERROR 0x00000004 // Error
+#define USB_TXCSRL15_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL15_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH15 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH15_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH15_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH15_MODE 0x00000020 // Mode
+#define USB_TXCSRH15_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH15_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH15_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH15_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH15_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP15 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP15_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP15_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL15 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL15_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL15_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL15_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL15_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL15_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL15_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL15_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL15_ERROR 0x00000004 // Error
+#define USB_RXCSRL15_OVER 0x00000004 // Overrun
+#define USB_RXCSRL15_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL15_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH15 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH15_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH15_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH15_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH15_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH15_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH15_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH15_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH15_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH15_DT 0x00000002 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT15
+// register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT15_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT15_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE15 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE15_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE15_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE15_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE15_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE15_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE15_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE15_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE15_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE15_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE15_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE15_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL15
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL15_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL15_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL15_NAKLMT_S \
+ 0
+#define USB_TXINTERVAL15_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE15 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE15_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE15_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE15_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE15_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE15_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE15_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE15_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE15_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE15_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE15_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE15_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL15
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL15_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL15_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL15_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL15_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT1_M 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT1_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT2_M 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT2_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT3_M 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT3_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT4
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT4_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT5
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT5_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT6
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT6_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT7
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT7_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT8
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT8_COUNT_M 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT8_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT9
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT9_COUNT_M 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT9_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT10
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT10_COUNT_M \
+ 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT10_COUNT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT11
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT11_COUNT_M \
+ 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT11_COUNT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT12
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT12_COUNT_M \
+ 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT12_COUNT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT13
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT13_COUNT_M \
+ 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT13_COUNT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT14
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT14_COUNT_M \
+ 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT14_COUNT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT15
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT15_COUNT_M \
+ 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT15_COUNT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS
+// register.
+//
+//*****************************************************************************
+#define USB_RXDPKTBUFDIS_EP15 0x00008000 // EP15 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP14 0x00004000 // EP14 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP13 0x00002000 // EP13 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP12 0x00001000 // EP12 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP11 0x00000800 // EP11 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP10 0x00000400 // EP10 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP9 0x00000200 // EP9 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP8 0x00000100 // EP8 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP7 0x00000080 // EP7 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP6 0x00000040 // EP6 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP5 0x00000020 // EP5 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP4 0x00000010 // EP4 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP3 0x00000008 // EP3 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP2 0x00000004 // EP2 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP1 0x00000002 // EP1 RX Double-Packet Buffer
+ // Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS
+// register.
+//
+//*****************************************************************************
+#define USB_TXDPKTBUFDIS_EP15 0x00008000 // EP15 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP14 0x00004000 // EP14 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP13 0x00002000 // EP13 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP12 0x00001000 // EP12 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP11 0x00000800 // EP11 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP10 0x00000400 // EP10 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP9 0x00000200 // EP9 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP8 0x00000100 // EP8 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP7 0x00000080 // EP7 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP6 0x00000040 // EP6 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP5 0x00000020 // EP5 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP4 0x00000010 // EP4 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP3 0x00000008 // EP3 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP2 0x00000004 // EP2 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP1 0x00000002 // EP1 TX Double-Packet Buffer
+ // Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPC register.
+//
+//*****************************************************************************
+#define USB_EPC_PFLTACT_M 0x00000300 // Power Fault Action
+#define USB_EPC_PFLTACT_UNCHG 0x00000000 // Unchanged
+#define USB_EPC_PFLTACT_TRIS 0x00000100 // Tristate
+#define USB_EPC_PFLTACT_LOW 0x00000200 // Low
+#define USB_EPC_PFLTACT_HIGH 0x00000300 // High
+#define USB_EPC_PFLTAEN 0x00000040 // Power Fault Action Enable
+#define USB_EPC_PFLTSEN_HIGH 0x00000020 // Power Fault Sense
+#define USB_EPC_PFLTEN 0x00000010 // Power Fault Input Enable
+#define USB_EPC_EPENDE 0x00000004 // EPEN Drive Enable
+#define USB_EPC_EPEN_M 0x00000003 // External Power Supply Enable
+ // Configuration
+#define USB_EPC_EPEN_LOW 0x00000000 // Power Enable Active Low
+#define USB_EPC_EPEN_HIGH 0x00000001 // Power Enable Active High
+#define USB_EPC_EPEN_VBLOW 0x00000002 // Power Enable High if VBUS Low
+#define USB_EPC_EPEN_VBHIGH 0x00000003 // Power Enable High if VBUS High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCRIS register.
+//
+//*****************************************************************************
+#define USB_EPCRIS_PF 0x00000001 // USB Power Fault Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCIM register.
+//
+//*****************************************************************************
+#define USB_EPCIM_PF 0x00000001 // USB Power Fault Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCISC register.
+//
+//*****************************************************************************
+#define USB_EPCISC_PF 0x00000001 // USB Power Fault Interrupt Status
+ // and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRRIS register.
+//
+//*****************************************************************************
+#define USB_DRRIS_RESUME 0x00000001 // RESUME Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRIM register.
+//
+//*****************************************************************************
+#define USB_DRIM_RESUME 0x00000001 // RESUME Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRISC register.
+//
+//*****************************************************************************
+#define USB_DRISC_RESUME 0x00000001 // RESUME Interrupt Status and
+ // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_GPCS register.
+//
+//*****************************************************************************
+#define USB_GPCS_DEVMODOTG 0x00000002 // Enable Device Mode
+#define USB_GPCS_DEVMOD 0x00000001 // Device Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDC register.
+//
+//*****************************************************************************
+#define USB_VDC_VBDEN 0x00000001 // VBUS Droop Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCRIS register.
+//
+//*****************************************************************************
+#define USB_VDCRIS_VD 0x00000001 // VBUS Droop Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCIM register.
+//
+//*****************************************************************************
+#define USB_VDCIM_VD 0x00000001 // VBUS Droop Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCISC register.
+//
+//*****************************************************************************
+#define USB_VDCISC_VD 0x00000001 // VBUS Droop Interrupt Status and
+ // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IDVRIS register.
+//
+//*****************************************************************************
+#define USB_IDVRIS_ID 0x00000001 // ID Valid Detect Raw Interrupt
+ // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IDVIM register.
+//
+//*****************************************************************************
+#define USB_IDVIM_ID 0x00000001 // ID Valid Detect Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IDVISC register.
+//
+//*****************************************************************************
+#define USB_IDVISC_ID 0x00000001 // ID Valid Detect Interrupt Status
+ // and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMASEL register.
+//
+//*****************************************************************************
+#define USB_DMASEL_DMACTX_M 0x00F00000 // DMA C TX Select
+#define USB_DMASEL_DMACRX_M 0x000F0000 // DMA C RX Select
+#define USB_DMASEL_DMABTX_M 0x0000F000 // DMA B TX Select
+#define USB_DMASEL_DMABRX_M 0x00000F00 // DMA B RX Select
+#define USB_DMASEL_DMAATX_M 0x000000F0 // DMA A TX Select
+#define USB_DMASEL_DMAARX_M 0x0000000F // DMA A RX Select
+#define USB_DMASEL_DMACTX_S 20
+#define USB_DMASEL_DMACRX_S 16
+#define USB_DMASEL_DMABTX_S 12
+#define USB_DMASEL_DMABRX_S 8
+#define USB_DMASEL_DMAATX_S 4
+#define USB_DMASEL_DMAARX_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_PP register.
+//
+//*****************************************************************************
+#define USB_PP_ECNT_M 0x0000FF00 // Endpoint Count
+#define USB_PP_USB_M 0x000000C0 // USB Capability
+#define USB_PP_USB_DEVICE 0x00000040 // DEVICE
+#define USB_PP_USB_HOSTDEVICE 0x00000080 // HOST
+#define USB_PP_USB_OTG 0x000000C0 // OTG
+#define USB_PP_PHY 0x00000010 // PHY Present
+#define USB_PP_TYPE_M 0x0000000F // Controller Type
+#define USB_PP_TYPE_0 0x00000000 // The first-generation USB
+ // controller
+#define USB_PP_ECNT_S 8
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// USB_O_TXFIFOADD register.
+//
+//*****************************************************************************
+#define USB_TXFIFOADD_ADDR_2048 0x00000009 // 2048
+#define USB_TXFIFOADD_ADDR_1024 0x00000008 // 1024
+#define USB_TXFIFOADD_ADDR_512 0x00000007 // 512
+#define USB_TXFIFOADD_ADDR_256 0x00000006 // 256
+#define USB_TXFIFOADD_ADDR_128 0x00000005 // 128
+#define USB_TXFIFOADD_ADDR_64 0x00000004 // 64
+#define USB_TXFIFOADD_ADDR_32 0x00000003 // 32
+#define USB_TXFIFOADD_ADDR_16 0x00000002 // 16
+#define USB_TXFIFOADD_ADDR_8 0x00000001 // 8
+#define USB_TXFIFOADD_ADDR_0 0x00000000 // 0
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// USB_O_RXFIFOADD register.
+//
+//*****************************************************************************
+#define USB_RXFIFOADD_ADDR_2048 0x00000009 // 2048
+#define USB_RXFIFOADD_ADDR_1024 0x00000008 // 1024
+#define USB_RXFIFOADD_ADDR_512 0x00000007 // 512
+#define USB_RXFIFOADD_ADDR_256 0x00000006 // 256
+#define USB_RXFIFOADD_ADDR_128 0x00000005 // 128
+#define USB_RXFIFOADD_ADDR_64 0x00000004 // 64
+#define USB_RXFIFOADD_ADDR_32 0x00000003 // 32
+#define USB_RXFIFOADD_ADDR_16 0x00000002 // 16
+#define USB_RXFIFOADD_ADDR_8 0x00000001 // 8
+#define USB_RXFIFOADD_ADDR_0 0x00000000 // 0
+
+#endif
+
+#endif // __HW_USB_H__
diff --git a/inc/hw_watchdog.h b/inc/hw_watchdog.h new file mode 100644 index 0000000..c208031 --- /dev/null +++ b/inc/hw_watchdog.h @@ -0,0 +1,191 @@ +//*****************************************************************************
+//
+// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.
+//
+// Copyright (c) 2005-2012 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 9453 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_WATCHDOG_H__
+#define __HW_WATCHDOG_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Watchdog Timer register offsets.
+//
+//*****************************************************************************
+#define WDT_O_LOAD 0x00000000 // Watchdog Load
+#define WDT_O_VALUE 0x00000004 // Watchdog Value
+#define WDT_O_CTL 0x00000008 // Watchdog Control
+#define WDT_O_ICR 0x0000000C // Watchdog Interrupt Clear
+#define WDT_O_RIS 0x00000010 // Watchdog Raw Interrupt Status
+#define WDT_O_MIS 0x00000014 // Watchdog Masked Interrupt Status
+#define WDT_O_TEST 0x00000418 // Watchdog Test
+#define WDT_O_LOCK 0x00000C00 // Watchdog Lock
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOAD register.
+//
+//*****************************************************************************
+#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value
+#define WDT_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_VALUE register.
+//
+//*****************************************************************************
+#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value
+#define WDT_VALUE_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_CTL register.
+//
+//*****************************************************************************
+#define WDT_CTL_WRC 0x80000000 // Write Complete
+#define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type
+#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable
+#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_ICR register.
+//
+//*****************************************************************************
+#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear
+#define WDT_ICR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_RIS register.
+//
+//*****************************************************************************
+#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_MIS register.
+//
+//*****************************************************************************
+#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_TEST register.
+//
+//*****************************************************************************
+#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOCK register.
+//
+//*****************************************************************************
+#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock
+#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked
+#define WDT_LOCK_LOCKED 0x00000001 // Locked
+#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_ISR, WDT_RIS, and
+// WDT_MIS registers.
+//
+//*****************************************************************************
+#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the Watchdog Timer register
+// offsets.
+//
+//*****************************************************************************
+#define WDT_O_PeriphID4 0x00000FD0
+#define WDT_O_PeriphID5 0x00000FD4
+#define WDT_O_PeriphID6 0x00000FD8
+#define WDT_O_PeriphID7 0x00000FDC
+#define WDT_O_PeriphID0 0x00000FE0
+#define WDT_O_PeriphID1 0x00000FE4
+#define WDT_O_PeriphID2 0x00000FE8
+#define WDT_O_PeriphID3 0x00000FEC
+#define WDT_O_PCellID0 0x00000FF0
+#define WDT_O_PCellID1 0x00000FF4
+#define WDT_O_PCellID2 0x00000FF8
+#define WDT_O_PCellID3 0x00000FFC
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the WDT_O_TEST
+// register.
+//
+//*****************************************************************************
+#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the reset values for the WDT
+// registers.
+//
+//*****************************************************************************
+#define WDT_RV_VALUE 0xFFFFFFFF // Current value register
+#define WDT_RV_LOAD 0xFFFFFFFF // Load register
+#define WDT_RV_PCellID1 0x000000F0
+#define WDT_RV_PCellID3 0x000000B1
+#define WDT_RV_PeriphID1 0x00000018
+#define WDT_RV_PeriphID2 0x00000018
+#define WDT_RV_PCellID0 0x0000000D
+#define WDT_RV_PCellID2 0x00000005
+#define WDT_RV_PeriphID0 0x00000005
+#define WDT_RV_PeriphID3 0x00000001
+#define WDT_RV_PeriphID5 0x00000000
+#define WDT_RV_RIS 0x00000000 // Raw interrupt status register
+#define WDT_RV_CTL 0x00000000 // Control register
+#define WDT_RV_PeriphID4 0x00000000
+#define WDT_RV_PeriphID6 0x00000000
+#define WDT_RV_PeriphID7 0x00000000
+#define WDT_RV_LOCK 0x00000000 // Lock register
+#define WDT_RV_MIS 0x00000000 // Masked interrupt status register
+
+#endif
+
+#endif // __HW_WATCHDOG_H__
diff --git a/inc/inc.sgxx b/inc/inc.sgxx Binary files differnew file mode 100644 index 0000000..c552e11 --- /dev/null +++ b/inc/inc.sgxx diff --git a/inc/lm4f120h5qr.h b/inc/lm4f120h5qr.h new file mode 100644 index 0000000..5383a90 --- /dev/null +++ b/inc/lm4f120h5qr.h @@ -0,0 +1,10025 @@ +//*****************************************************************************
+//
+// lm4f120h5qr.h - LM4F120H5QR Register Definitions
+//
+// Copyright (c) 2011-2012 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 9453 of the Stellaris Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __LM4F120H5QR_H__
+#define __LM4F120H5QR_H__
+
+//*****************************************************************************
+//
+// Watchdog Timer registers (WATCHDOG0)
+//
+//*****************************************************************************
+#define WATCHDOG0_LOAD_R (*((volatile unsigned long *)0x40000000))
+#define WATCHDOG0_VALUE_R (*((volatile unsigned long *)0x40000004))
+#define WATCHDOG0_CTL_R (*((volatile unsigned long *)0x40000008))
+#define WATCHDOG0_ICR_R (*((volatile unsigned long *)0x4000000C))
+#define WATCHDOG0_RIS_R (*((volatile unsigned long *)0x40000010))
+#define WATCHDOG0_MIS_R (*((volatile unsigned long *)0x40000014))
+#define WATCHDOG0_TEST_R (*((volatile unsigned long *)0x40000418))
+#define WATCHDOG0_LOCK_R (*((volatile unsigned long *)0x40000C00))
+
+//*****************************************************************************
+//
+// Watchdog Timer registers (WATCHDOG1)
+//
+//*****************************************************************************
+#define WATCHDOG1_LOAD_R (*((volatile unsigned long *)0x40001000))
+#define WATCHDOG1_VALUE_R (*((volatile unsigned long *)0x40001004))
+#define WATCHDOG1_CTL_R (*((volatile unsigned long *)0x40001008))
+#define WATCHDOG1_ICR_R (*((volatile unsigned long *)0x4000100C))
+#define WATCHDOG1_RIS_R (*((volatile unsigned long *)0x40001010))
+#define WATCHDOG1_MIS_R (*((volatile unsigned long *)0x40001014))
+#define WATCHDOG1_TEST_R (*((volatile unsigned long *)0x40001418))
+#define WATCHDOG1_LOCK_R (*((volatile unsigned long *)0x40001C00))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTA)
+//
+//*****************************************************************************
+#define GPIO_PORTA_DATA_BITS_R ((volatile unsigned long *)0x40004000)
+#define GPIO_PORTA_DATA_R (*((volatile unsigned long *)0x400043FC))
+#define GPIO_PORTA_DIR_R (*((volatile unsigned long *)0x40004400))
+#define GPIO_PORTA_IS_R (*((volatile unsigned long *)0x40004404))
+#define GPIO_PORTA_IBE_R (*((volatile unsigned long *)0x40004408))
+#define GPIO_PORTA_IEV_R (*((volatile unsigned long *)0x4000440C))
+#define GPIO_PORTA_IM_R (*((volatile unsigned long *)0x40004410))
+#define GPIO_PORTA_RIS_R (*((volatile unsigned long *)0x40004414))
+#define GPIO_PORTA_MIS_R (*((volatile unsigned long *)0x40004418))
+#define GPIO_PORTA_ICR_R (*((volatile unsigned long *)0x4000441C))
+#define GPIO_PORTA_AFSEL_R (*((volatile unsigned long *)0x40004420))
+#define GPIO_PORTA_DR2R_R (*((volatile unsigned long *)0x40004500))
+#define GPIO_PORTA_DR4R_R (*((volatile unsigned long *)0x40004504))
+#define GPIO_PORTA_DR8R_R (*((volatile unsigned long *)0x40004508))
+#define GPIO_PORTA_ODR_R (*((volatile unsigned long *)0x4000450C))
+#define GPIO_PORTA_PUR_R (*((volatile unsigned long *)0x40004510))
+#define GPIO_PORTA_PDR_R (*((volatile unsigned long *)0x40004514))
+#define GPIO_PORTA_SLR_R (*((volatile unsigned long *)0x40004518))
+#define GPIO_PORTA_DEN_R (*((volatile unsigned long *)0x4000451C))
+#define GPIO_PORTA_LOCK_R (*((volatile unsigned long *)0x40004520))
+#define GPIO_PORTA_CR_R (*((volatile unsigned long *)0x40004524))
+#define GPIO_PORTA_AMSEL_R (*((volatile unsigned long *)0x40004528))
+#define GPIO_PORTA_PCTL_R (*((volatile unsigned long *)0x4000452C))
+#define GPIO_PORTA_ADCCTL_R (*((volatile unsigned long *)0x40004530))
+#define GPIO_PORTA_DMACTL_R (*((volatile unsigned long *)0x40004534))
+#define GPIO_PORTA_SI_R (*((volatile unsigned long *)0x40004538))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTB)
+//
+//*****************************************************************************
+#define GPIO_PORTB_DATA_BITS_R ((volatile unsigned long *)0x40005000)
+#define GPIO_PORTB_DATA_R (*((volatile unsigned long *)0x400053FC))
+#define GPIO_PORTB_DIR_R (*((volatile unsigned long *)0x40005400))
+#define GPIO_PORTB_IS_R (*((volatile unsigned long *)0x40005404))
+#define GPIO_PORTB_IBE_R (*((volatile unsigned long *)0x40005408))
+#define GPIO_PORTB_IEV_R (*((volatile unsigned long *)0x4000540C))
+#define GPIO_PORTB_IM_R (*((volatile unsigned long *)0x40005410))
+#define GPIO_PORTB_RIS_R (*((volatile unsigned long *)0x40005414))
+#define GPIO_PORTB_MIS_R (*((volatile unsigned long *)0x40005418))
+#define GPIO_PORTB_ICR_R (*((volatile unsigned long *)0x4000541C))
+#define GPIO_PORTB_AFSEL_R (*((volatile unsigned long *)0x40005420))
+#define GPIO_PORTB_DR2R_R (*((volatile unsigned long *)0x40005500))
+#define GPIO_PORTB_DR4R_R (*((volatile unsigned long *)0x40005504))
+#define GPIO_PORTB_DR8R_R (*((volatile unsigned long *)0x40005508))
+#define GPIO_PORTB_ODR_R (*((volatile unsigned long *)0x4000550C))
+#define GPIO_PORTB_PUR_R (*((volatile unsigned long *)0x40005510))
+#define GPIO_PORTB_PDR_R (*((volatile unsigned long *)0x40005514))
+#define GPIO_PORTB_SLR_R (*((volatile unsigned long *)0x40005518))
+#define GPIO_PORTB_DEN_R (*((volatile unsigned long *)0x4000551C))
+#define GPIO_PORTB_LOCK_R (*((volatile unsigned long *)0x40005520))
+#define GPIO_PORTB_CR_R (*((volatile unsigned long *)0x40005524))
+#define GPIO_PORTB_AMSEL_R (*((volatile unsigned long *)0x40005528))
+#define GPIO_PORTB_PCTL_R (*((volatile unsigned long *)0x4000552C))
+#define GPIO_PORTB_ADCCTL_R (*((volatile unsigned long *)0x40005530))
+#define GPIO_PORTB_DMACTL_R (*((volatile unsigned long *)0x40005534))
+#define GPIO_PORTB_SI_R (*((volatile unsigned long *)0x40005538))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTC)
+//
+//*****************************************************************************
+#define GPIO_PORTC_DATA_BITS_R ((volatile unsigned long *)0x40006000)
+#define GPIO_PORTC_DATA_R (*((volatile unsigned long *)0x400063FC))
+#define GPIO_PORTC_DIR_R (*((volatile unsigned long *)0x40006400))
+#define GPIO_PORTC_IS_R (*((volatile unsigned long *)0x40006404))
+#define GPIO_PORTC_IBE_R (*((volatile unsigned long *)0x40006408))
+#define GPIO_PORTC_IEV_R (*((volatile unsigned long *)0x4000640C))
+#define GPIO_PORTC_IM_R (*((volatile unsigned long *)0x40006410))
+#define GPIO_PORTC_RIS_R (*((volatile unsigned long *)0x40006414))
+#define GPIO_PORTC_MIS_R (*((volatile unsigned long *)0x40006418))
+#define GPIO_PORTC_ICR_R (*((volatile unsigned long *)0x4000641C))
+#define GPIO_PORTC_AFSEL_R (*((volatile unsigned long *)0x40006420))
+#define GPIO_PORTC_DR2R_R (*((volatile unsigned long *)0x40006500))
+#define GPIO_PORTC_DR4R_R (*((volatile unsigned long *)0x40006504))
+#define GPIO_PORTC_DR8R_R (*((volatile unsigned long *)0x40006508))
+#define GPIO_PORTC_ODR_R (*((volatile unsigned long *)0x4000650C))
+#define GPIO_PORTC_PUR_R (*((volatile unsigned long *)0x40006510))
+#define GPIO_PORTC_PDR_R (*((volatile unsigned long *)0x40006514))
+#define GPIO_PORTC_SLR_R (*((volatile unsigned long *)0x40006518))
+#define GPIO_PORTC_DEN_R (*((volatile unsigned long *)0x4000651C))
+#define GPIO_PORTC_LOCK_R (*((volatile unsigned long *)0x40006520))
+#define GPIO_PORTC_CR_R (*((volatile unsigned long *)0x40006524))
+#define GPIO_PORTC_AMSEL_R (*((volatile unsigned long *)0x40006528))
+#define GPIO_PORTC_PCTL_R (*((volatile unsigned long *)0x4000652C))
+#define GPIO_PORTC_ADCCTL_R (*((volatile unsigned long *)0x40006530))
+#define GPIO_PORTC_DMACTL_R (*((volatile unsigned long *)0x40006534))
+#define GPIO_PORTC_SI_R (*((volatile unsigned long *)0x40006538))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTD)
+//
+//*****************************************************************************
+#define GPIO_PORTD_DATA_BITS_R ((volatile unsigned long *)0x40007000)
+#define GPIO_PORTD_DATA_R (*((volatile unsigned long *)0x400073FC))
+#define GPIO_PORTD_DIR_R (*((volatile unsigned long *)0x40007400))
+#define GPIO_PORTD_IS_R (*((volatile unsigned long *)0x40007404))
+#define GPIO_PORTD_IBE_R (*((volatile unsigned long *)0x40007408))
+#define GPIO_PORTD_IEV_R (*((volatile unsigned long *)0x4000740C))
+#define GPIO_PORTD_IM_R (*((volatile unsigned long *)0x40007410))
+#define GPIO_PORTD_RIS_R (*((volatile unsigned long *)0x40007414))
+#define GPIO_PORTD_MIS_R (*((volatile unsigned long *)0x40007418))
+#define GPIO_PORTD_ICR_R (*((volatile unsigned long *)0x4000741C))
+#define GPIO_PORTD_AFSEL_R (*((volatile unsigned long *)0x40007420))
+#define GPIO_PORTD_DR2R_R (*((volatile unsigned long *)0x40007500))
+#define GPIO_PORTD_DR4R_R (*((volatile unsigned long *)0x40007504))
+#define GPIO_PORTD_DR8R_R (*((volatile unsigned long *)0x40007508))
+#define GPIO_PORTD_ODR_R (*((volatile unsigned long *)0x4000750C))
+#define GPIO_PORTD_PUR_R (*((volatile unsigned long *)0x40007510))
+#define GPIO_PORTD_PDR_R (*((volatile unsigned long *)0x40007514))
+#define GPIO_PORTD_SLR_R (*((volatile unsigned long *)0x40007518))
+#define GPIO_PORTD_DEN_R (*((volatile unsigned long *)0x4000751C))
+#define GPIO_PORTD_LOCK_R (*((volatile unsigned long *)0x40007520))
+#define GPIO_PORTD_CR_R (*((volatile unsigned long *)0x40007524))
+#define GPIO_PORTD_AMSEL_R (*((volatile unsigned long *)0x40007528))
+#define GPIO_PORTD_PCTL_R (*((volatile unsigned long *)0x4000752C))
+#define GPIO_PORTD_ADCCTL_R (*((volatile unsigned long *)0x40007530))
+#define GPIO_PORTD_DMACTL_R (*((volatile unsigned long *)0x40007534))
+#define GPIO_PORTD_SI_R (*((volatile unsigned long *)0x40007538))
+
+//*****************************************************************************
+//
+// SSI registers (SSI0)
+//
+//*****************************************************************************
+#define SSI0_CR0_R (*((volatile unsigned long *)0x40008000))
+#define SSI0_CR1_R (*((volatile unsigned long *)0x40008004))
+#define SSI0_DR_R (*((volatile unsigned long *)0x40008008))
+#define SSI0_SR_R (*((volatile unsigned long *)0x4000800C))
+#define SSI0_CPSR_R (*((volatile unsigned long *)0x40008010))
+#define SSI0_IM_R (*((volatile unsigned long *)0x40008014))
+#define SSI0_RIS_R (*((volatile unsigned long *)0x40008018))
+#define SSI0_MIS_R (*((volatile unsigned long *)0x4000801C))
+#define SSI0_ICR_R (*((volatile unsigned long *)0x40008020))
+#define SSI0_DMACTL_R (*((volatile unsigned long *)0x40008024))
+#define SSI0_CC_R (*((volatile unsigned long *)0x40008FC8))
+
+//*****************************************************************************
+//
+// SSI registers (SSI1)
+//
+//*****************************************************************************
+#define SSI1_CR0_R (*((volatile unsigned long *)0x40009000))
+#define SSI1_CR1_R (*((volatile unsigned long *)0x40009004))
+#define SSI1_DR_R (*((volatile unsigned long *)0x40009008))
+#define SSI1_SR_R (*((volatile unsigned long *)0x4000900C))
+#define SSI1_CPSR_R (*((volatile unsigned long *)0x40009010))
+#define SSI1_IM_R (*((volatile unsigned long *)0x40009014))
+#define SSI1_RIS_R (*((volatile unsigned long *)0x40009018))
+#define SSI1_MIS_R (*((volatile unsigned long *)0x4000901C))
+#define SSI1_ICR_R (*((volatile unsigned long *)0x40009020))
+#define SSI1_DMACTL_R (*((volatile unsigned long *)0x40009024))
+#define SSI1_CC_R (*((volatile unsigned long *)0x40009FC8))
+
+//*****************************************************************************
+//
+// SSI registers (SSI2)
+//
+//*****************************************************************************
+#define SSI2_CR0_R (*((volatile unsigned long *)0x4000A000))
+#define SSI2_CR1_R (*((volatile unsigned long *)0x4000A004))
+#define SSI2_DR_R (*((volatile unsigned long *)0x4000A008))
+#define SSI2_SR_R (*((volatile unsigned long *)0x4000A00C))
+#define SSI2_CPSR_R (*((volatile unsigned long *)0x4000A010))
+#define SSI2_IM_R (*((volatile unsigned long *)0x4000A014))
+#define SSI2_RIS_R (*((volatile unsigned long *)0x4000A018))
+#define SSI2_MIS_R (*((volatile unsigned long *)0x4000A01C))
+#define SSI2_ICR_R (*((volatile unsigned long *)0x4000A020))
+#define SSI2_DMACTL_R (*((volatile unsigned long *)0x4000A024))
+#define SSI2_CC_R (*((volatile unsigned long *)0x4000AFC8))
+
+//*****************************************************************************
+//
+// SSI registers (SSI3)
+//
+//*****************************************************************************
+#define SSI3_CR0_R (*((volatile unsigned long *)0x4000B000))
+#define SSI3_CR1_R (*((volatile unsigned long *)0x4000B004))
+#define SSI3_DR_R (*((volatile unsigned long *)0x4000B008))
+#define SSI3_SR_R (*((volatile unsigned long *)0x4000B00C))
+#define SSI3_CPSR_R (*((volatile unsigned long *)0x4000B010))
+#define SSI3_IM_R (*((volatile unsigned long *)0x4000B014))
+#define SSI3_RIS_R (*((volatile unsigned long *)0x4000B018))
+#define SSI3_MIS_R (*((volatile unsigned long *)0x4000B01C))
+#define SSI3_ICR_R (*((volatile unsigned long *)0x4000B020))
+#define SSI3_DMACTL_R (*((volatile unsigned long *)0x4000B024))
+#define SSI3_CC_R (*((volatile unsigned long *)0x4000BFC8))
+
+//*****************************************************************************
+//
+// UART registers (UART0)
+//
+//*****************************************************************************
+#define UART0_DR_R (*((volatile unsigned long *)0x4000C000))
+#define UART0_RSR_R (*((volatile unsigned long *)0x4000C004))
+#define UART0_ECR_R (*((volatile unsigned long *)0x4000C004))
+#define UART0_FR_R (*((volatile unsigned long *)0x4000C018))
+#define UART0_ILPR_R (*((volatile unsigned long *)0x4000C020))
+#define UART0_IBRD_R (*((volatile unsigned long *)0x4000C024))
+#define UART0_FBRD_R (*((volatile unsigned long *)0x4000C028))
+#define UART0_LCRH_R (*((volatile unsigned long *)0x4000C02C))
+#define UART0_CTL_R (*((volatile unsigned long *)0x4000C030))
+#define UART0_IFLS_R (*((volatile unsigned long *)0x4000C034))
+#define UART0_IM_R (*((volatile unsigned long *)0x4000C038))
+#define UART0_RIS_R (*((volatile unsigned long *)0x4000C03C))
+#define UART0_MIS_R (*((volatile unsigned long *)0x4000C040))
+#define UART0_ICR_R (*((volatile unsigned long *)0x4000C044))
+#define UART0_DMACTL_R (*((volatile unsigned long *)0x4000C048))
+#define UART0_LCTL_R (*((volatile unsigned long *)0x4000C090))
+#define UART0_LSS_R (*((volatile unsigned long *)0x4000C094))
+#define UART0_LTIM_R (*((volatile unsigned long *)0x4000C098))
+#define UART0_9BITADDR_R (*((volatile unsigned long *)0x4000C0A4))
+#define UART0_9BITAMASK_R (*((volatile unsigned long *)0x4000C0A8))
+#define UART0_PP_R (*((volatile unsigned long *)0x4000CFC0))
+#define UART0_CC_R (*((volatile unsigned long *)0x4000CFC8))
+
+//*****************************************************************************
+//
+// UART registers (UART1)
+//
+//*****************************************************************************
+#define UART1_DR_R (*((volatile unsigned long *)0x4000D000))
+#define UART1_RSR_R (*((volatile unsigned long *)0x4000D004))
+#define UART1_ECR_R (*((volatile unsigned long *)0x4000D004))
+#define UART1_FR_R (*((volatile unsigned long *)0x4000D018))
+#define UART1_ILPR_R (*((volatile unsigned long *)0x4000D020))
+#define UART1_IBRD_R (*((volatile unsigned long *)0x4000D024))
+#define UART1_FBRD_R (*((volatile unsigned long *)0x4000D028))
+#define UART1_LCRH_R (*((volatile unsigned long *)0x4000D02C))
+#define UART1_CTL_R (*((volatile unsigned long *)0x4000D030))
+#define UART1_IFLS_R (*((volatile unsigned long *)0x4000D034))
+#define UART1_IM_R (*((volatile unsigned long *)0x4000D038))
+#define UART1_RIS_R (*((volatile unsigned long *)0x4000D03C))
+#define UART1_MIS_R (*((volatile unsigned long *)0x4000D040))
+#define UART1_ICR_R (*((volatile unsigned long *)0x4000D044))
+#define UART1_DMACTL_R (*((volatile unsigned long *)0x4000D048))
+#define UART1_LCTL_R (*((volatile unsigned long *)0x4000D090))
+#define UART1_LSS_R (*((volatile unsigned long *)0x4000D094))
+#define UART1_LTIM_R (*((volatile unsigned long *)0x4000D098))
+#define UART1_9BITADDR_R (*((volatile unsigned long *)0x4000D0A4))
+#define UART1_9BITAMASK_R (*((volatile unsigned long *)0x4000D0A8))
+#define UART1_PP_R (*((volatile unsigned long *)0x4000DFC0))
+#define UART1_CC_R (*((volatile unsigned long *)0x4000DFC8))
+
+//*****************************************************************************
+//
+// UART registers (UART2)
+//
+//*****************************************************************************
+#define UART2_DR_R (*((volatile unsigned long *)0x4000E000))
+#define UART2_RSR_R (*((volatile unsigned long *)0x4000E004))
+#define UART2_ECR_R (*((volatile unsigned long *)0x4000E004))
+#define UART2_FR_R (*((volatile unsigned long *)0x4000E018))
+#define UART2_ILPR_R (*((volatile unsigned long *)0x4000E020))
+#define UART2_IBRD_R (*((volatile unsigned long *)0x4000E024))
+#define UART2_FBRD_R (*((volatile unsigned long *)0x4000E028))
+#define UART2_LCRH_R (*((volatile unsigned long *)0x4000E02C))
+#define UART2_CTL_R (*((volatile unsigned long *)0x4000E030))
+#define UART2_IFLS_R (*((volatile unsigned long *)0x4000E034))
+#define UART2_IM_R (*((volatile unsigned long *)0x4000E038))
+#define UART2_RIS_R (*((volatile unsigned long *)0x4000E03C))
+#define UART2_MIS_R (*((volatile unsigned long *)0x4000E040))
+#define UART2_ICR_R (*((volatile unsigned long *)0x4000E044))
+#define UART2_DMACTL_R (*((volatile unsigned long *)0x4000E048))
+#define UART2_LCTL_R (*((volatile unsigned long *)0x4000E090))
+#define UART2_LSS_R (*((volatile unsigned long *)0x4000E094))
+#define UART2_LTIM_R (*((volatile unsigned long *)0x4000E098))
+#define UART2_9BITADDR_R (*((volatile unsigned long *)0x4000E0A4))
+#define UART2_9BITAMASK_R (*((volatile unsigned long *)0x4000E0A8))
+#define UART2_PP_R (*((volatile unsigned long *)0x4000EFC0))
+#define UART2_CC_R (*((volatile unsigned long *)0x4000EFC8))
+
+//*****************************************************************************
+//
+// UART registers (UART3)
+//
+//*****************************************************************************
+#define UART3_DR_R (*((volatile unsigned long *)0x4000F000))
+#define UART3_RSR_R (*((volatile unsigned long *)0x4000F004))
+#define UART3_ECR_R (*((volatile unsigned long *)0x4000F004))
+#define UART3_FR_R (*((volatile unsigned long *)0x4000F018))
+#define UART3_ILPR_R (*((volatile unsigned long *)0x4000F020))
+#define UART3_IBRD_R (*((volatile unsigned long *)0x4000F024))
+#define UART3_FBRD_R (*((volatile unsigned long *)0x4000F028))
+#define UART3_LCRH_R (*((volatile unsigned long *)0x4000F02C))
+#define UART3_CTL_R (*((volatile unsigned long *)0x4000F030))
+#define UART3_IFLS_R (*((volatile unsigned long *)0x4000F034))
+#define UART3_IM_R (*((volatile unsigned long *)0x4000F038))
+#define UART3_RIS_R (*((volatile unsigned long *)0x4000F03C))
+#define UART3_MIS_R (*((volatile unsigned long *)0x4000F040))
+#define UART3_ICR_R (*((volatile unsigned long *)0x4000F044))
+#define UART3_DMACTL_R (*((volatile unsigned long *)0x4000F048))
+#define UART3_LCTL_R (*((volatile unsigned long *)0x4000F090))
+#define UART3_LSS_R (*((volatile unsigned long *)0x4000F094))
+#define UART3_LTIM_R (*((volatile unsigned long *)0x4000F098))
+#define UART3_9BITADDR_R (*((volatile unsigned long *)0x4000F0A4))
+#define UART3_9BITAMASK_R (*((volatile unsigned long *)0x4000F0A8))
+#define UART3_PP_R (*((volatile unsigned long *)0x4000FFC0))
+#define UART3_CC_R (*((volatile unsigned long *)0x4000FFC8))
+
+//*****************************************************************************
+//
+// UART registers (UART4)
+//
+//*****************************************************************************
+#define UART4_DR_R (*((volatile unsigned long *)0x40010000))
+#define UART4_RSR_R (*((volatile unsigned long *)0x40010004))
+#define UART4_ECR_R (*((volatile unsigned long *)0x40010004))
+#define UART4_FR_R (*((volatile unsigned long *)0x40010018))
+#define UART4_ILPR_R (*((volatile unsigned long *)0x40010020))
+#define UART4_IBRD_R (*((volatile unsigned long *)0x40010024))
+#define UART4_FBRD_R (*((volatile unsigned long *)0x40010028))
+#define UART4_LCRH_R (*((volatile unsigned long *)0x4001002C))
+#define UART4_CTL_R (*((volatile unsigned long *)0x40010030))
+#define UART4_IFLS_R (*((volatile unsigned long *)0x40010034))
+#define UART4_IM_R (*((volatile unsigned long *)0x40010038))
+#define UART4_RIS_R (*((volatile unsigned long *)0x4001003C))
+#define UART4_MIS_R (*((volatile unsigned long *)0x40010040))
+#define UART4_ICR_R (*((volatile unsigned long *)0x40010044))
+#define UART4_DMACTL_R (*((volatile unsigned long *)0x40010048))
+#define UART4_LCTL_R (*((volatile unsigned long *)0x40010090))
+#define UART4_LSS_R (*((volatile unsigned long *)0x40010094))
+#define UART4_LTIM_R (*((volatile unsigned long *)0x40010098))
+#define UART4_9BITADDR_R (*((volatile unsigned long *)0x400100A4))
+#define UART4_9BITAMASK_R (*((volatile unsigned long *)0x400100A8))
+#define UART4_PP_R (*((volatile unsigned long *)0x40010FC0))
+#define UART4_CC_R (*((volatile unsigned long *)0x40010FC8))
+
+//*****************************************************************************
+//
+// UART registers (UART5)
+//
+//*****************************************************************************
+#define UART5_DR_R (*((volatile unsigned long *)0x40011000))
+#define UART5_RSR_R (*((volatile unsigned long *)0x40011004))
+#define UART5_ECR_R (*((volatile unsigned long *)0x40011004))
+#define UART5_FR_R (*((volatile unsigned long *)0x40011018))
+#define UART5_ILPR_R (*((volatile unsigned long *)0x40011020))
+#define UART5_IBRD_R (*((volatile unsigned long *)0x40011024))
+#define UART5_FBRD_R (*((volatile unsigned long *)0x40011028))
+#define UART5_LCRH_R (*((volatile unsigned long *)0x4001102C))
+#define UART5_CTL_R (*((volatile unsigned long *)0x40011030))
+#define UART5_IFLS_R (*((volatile unsigned long *)0x40011034))
+#define UART5_IM_R (*((volatile unsigned long *)0x40011038))
+#define UART5_RIS_R (*((volatile unsigned long *)0x4001103C))
+#define UART5_MIS_R (*((volatile unsigned long *)0x40011040))
+#define UART5_ICR_R (*((volatile unsigned long *)0x40011044))
+#define UART5_DMACTL_R (*((volatile unsigned long *)0x40011048))
+#define UART5_LCTL_R (*((volatile unsigned long *)0x40011090))
+#define UART5_LSS_R (*((volatile unsigned long *)0x40011094))
+#define UART5_LTIM_R (*((volatile unsigned long *)0x40011098))
+#define UART5_9BITADDR_R (*((volatile unsigned long *)0x400110A4))
+#define UART5_9BITAMASK_R (*((volatile unsigned long *)0x400110A8))
+#define UART5_PP_R (*((volatile unsigned long *)0x40011FC0))
+#define UART5_CC_R (*((volatile unsigned long *)0x40011FC8))
+
+//*****************************************************************************
+//
+// UART registers (UART6)
+//
+//*****************************************************************************
+#define UART6_DR_R (*((volatile unsigned long *)0x40012000))
+#define UART6_RSR_R (*((volatile unsigned long *)0x40012004))
+#define UART6_ECR_R (*((volatile unsigned long *)0x40012004))
+#define UART6_FR_R (*((volatile unsigned long *)0x40012018))
+#define UART6_ILPR_R (*((volatile unsigned long *)0x40012020))
+#define UART6_IBRD_R (*((volatile unsigned long *)0x40012024))
+#define UART6_FBRD_R (*((volatile unsigned long *)0x40012028))
+#define UART6_LCRH_R (*((volatile unsigned long *)0x4001202C))
+#define UART6_CTL_R (*((volatile unsigned long *)0x40012030))
+#define UART6_IFLS_R (*((volatile unsigned long *)0x40012034))
+#define UART6_IM_R (*((volatile unsigned long *)0x40012038))
+#define UART6_RIS_R (*((volatile unsigned long *)0x4001203C))
+#define UART6_MIS_R (*((volatile unsigned long *)0x40012040))
+#define UART6_ICR_R (*((volatile unsigned long *)0x40012044))
+#define UART6_DMACTL_R (*((volatile unsigned long *)0x40012048))
+#define UART6_LCTL_R (*((volatile unsigned long *)0x40012090))
+#define UART6_LSS_R (*((volatile unsigned long *)0x40012094))
+#define UART6_LTIM_R (*((volatile unsigned long *)0x40012098))
+#define UART6_9BITADDR_R (*((volatile unsigned long *)0x400120A4))
+#define UART6_9BITAMASK_R (*((volatile unsigned long *)0x400120A8))
+#define UART6_PP_R (*((volatile unsigned long *)0x40012FC0))
+#define UART6_CC_R (*((volatile unsigned long *)0x40012FC8))
+
+//*****************************************************************************
+//
+// UART registers (UART7)
+//
+//*****************************************************************************
+#define UART7_DR_R (*((volatile unsigned long *)0x40013000))
+#define UART7_RSR_R (*((volatile unsigned long *)0x40013004))
+#define UART7_ECR_R (*((volatile unsigned long *)0x40013004))
+#define UART7_FR_R (*((volatile unsigned long *)0x40013018))
+#define UART7_ILPR_R (*((volatile unsigned long *)0x40013020))
+#define UART7_IBRD_R (*((volatile unsigned long *)0x40013024))
+#define UART7_FBRD_R (*((volatile unsigned long *)0x40013028))
+#define UART7_LCRH_R (*((volatile unsigned long *)0x4001302C))
+#define UART7_CTL_R (*((volatile unsigned long *)0x40013030))
+#define UART7_IFLS_R (*((volatile unsigned long *)0x40013034))
+#define UART7_IM_R (*((volatile unsigned long *)0x40013038))
+#define UART7_RIS_R (*((volatile unsigned long *)0x4001303C))
+#define UART7_MIS_R (*((volatile unsigned long *)0x40013040))
+#define UART7_ICR_R (*((volatile unsigned long *)0x40013044))
+#define UART7_DMACTL_R (*((volatile unsigned long *)0x40013048))
+#define UART7_LCTL_R (*((volatile unsigned long *)0x40013090))
+#define UART7_LSS_R (*((volatile unsigned long *)0x40013094))
+#define UART7_LTIM_R (*((volatile unsigned long *)0x40013098))
+#define UART7_9BITADDR_R (*((volatile unsigned long *)0x400130A4))
+#define UART7_9BITAMASK_R (*((volatile unsigned long *)0x400130A8))
+#define UART7_PP_R (*((volatile unsigned long *)0x40013FC0))
+#define UART7_CC_R (*((volatile unsigned long *)0x40013FC8))
+
+//*****************************************************************************
+//
+// I2C registers (I2C0 MASTER)
+//
+//*****************************************************************************
+#define I2C0_MASTER_MSA_R (*((volatile unsigned long *)0x40020000))
+#define I2C0_MASTER_MCS_R (*((volatile unsigned long *)0x40020004))
+#define I2C0_MASTER_MDR_R (*((volatile unsigned long *)0x40020008))
+#define I2C0_MASTER_MTPR_R (*((volatile unsigned long *)0x4002000C))
+#define I2C0_MASTER_MIMR_R (*((volatile unsigned long *)0x40020010))
+#define I2C0_MASTER_MRIS_R (*((volatile unsigned long *)0x40020014))
+#define I2C0_MASTER_MMIS_R (*((volatile unsigned long *)0x40020018))
+#define I2C0_MASTER_MICR_R (*((volatile unsigned long *)0x4002001C))
+#define I2C0_MASTER_MCR_R (*((volatile unsigned long *)0x40020020))
+#define I2C0_MASTER_MCLKOCNT_R (*((volatile unsigned long *)0x40020024))
+#define I2C0_MASTER_MBMON_R (*((volatile unsigned long *)0x4002002C))
+
+//*****************************************************************************
+//
+// I2C registers (I2C0 SLAVE)
+//
+//*****************************************************************************
+#define I2C0_SLAVE_SOAR_R (*((volatile unsigned long *)0x40020800))
+#define I2C0_SLAVE_SCSR_R (*((volatile unsigned long *)0x40020804))
+#define I2C0_SLAVE_SDR_R (*((volatile unsigned long *)0x40020808))
+#define I2C0_SLAVE_SIMR_R (*((volatile unsigned long *)0x4002080C))
+#define I2C0_SLAVE_SRIS_R (*((volatile unsigned long *)0x40020810))
+#define I2C0_SLAVE_SMIS_R (*((volatile unsigned long *)0x40020814))
+#define I2C0_SLAVE_SICR_R (*((volatile unsigned long *)0x40020818))
+#define I2C0_SLAVE_SOAR2_R (*((volatile unsigned long *)0x4002081C))
+#define I2C0_SLAVE_SACKCTL_R (*((volatile unsigned long *)0x40020820))
+
+//*****************************************************************************
+//
+// I2C registers (I2C1 MASTER)
+//
+//*****************************************************************************
+#define I2C1_MASTER_MSA_R (*((volatile unsigned long *)0x40021000))
+#define I2C1_MASTER_MCS_R (*((volatile unsigned long *)0x40021004))
+#define I2C1_MASTER_MDR_R (*((volatile unsigned long *)0x40021008))
+#define I2C1_MASTER_MTPR_R (*((volatile unsigned long *)0x4002100C))
+#define I2C1_MASTER_MIMR_R (*((volatile unsigned long *)0x40021010))
+#define I2C1_MASTER_MRIS_R (*((volatile unsigned long *)0x40021014))
+#define I2C1_MASTER_MMIS_R (*((volatile unsigned long *)0x40021018))
+#define I2C1_MASTER_MICR_R (*((volatile unsigned long *)0x4002101C))
+#define I2C1_MASTER_MCR_R (*((volatile unsigned long *)0x40021020))
+#define I2C1_MASTER_MCLKOCNT_R (*((volatile unsigned long *)0x40021024))
+#define I2C1_MASTER_MBMON_R (*((volatile unsigned long *)0x4002102C))
+
+//*****************************************************************************
+//
+// I2C registers (I2C1 SLAVE)
+//
+//*****************************************************************************
+#define I2C1_SLAVE_SOAR_R (*((volatile unsigned long *)0x40021800))
+#define I2C1_SLAVE_SCSR_R (*((volatile unsigned long *)0x40021804))
+#define I2C1_SLAVE_SDR_R (*((volatile unsigned long *)0x40021808))
+#define I2C1_SLAVE_SIMR_R (*((volatile unsigned long *)0x4002180C))
+#define I2C1_SLAVE_SRIS_R (*((volatile unsigned long *)0x40021810))
+#define I2C1_SLAVE_SMIS_R (*((volatile unsigned long *)0x40021814))
+#define I2C1_SLAVE_SICR_R (*((volatile unsigned long *)0x40021818))
+#define I2C1_SLAVE_SOAR2_R (*((volatile unsigned long *)0x4002181C))
+#define I2C1_SLAVE_SACKCTL_R (*((volatile unsigned long *)0x40021820))
+
+//*****************************************************************************
+//
+// I2C registers (I2C2 MASTER)
+//
+//*****************************************************************************
+#define I2C2_MASTER_MSA_R (*((volatile unsigned long *)0x40022000))
+#define I2C2_MASTER_MCS_R (*((volatile unsigned long *)0x40022004))
+#define I2C2_MASTER_MDR_R (*((volatile unsigned long *)0x40022008))
+#define I2C2_MASTER_MTPR_R (*((volatile unsigned long *)0x4002200C))
+#define I2C2_MASTER_MIMR_R (*((volatile unsigned long *)0x40022010))
+#define I2C2_MASTER_MRIS_R (*((volatile unsigned long *)0x40022014))
+#define I2C2_MASTER_MMIS_R (*((volatile unsigned long *)0x40022018))
+#define I2C2_MASTER_MICR_R (*((volatile unsigned long *)0x4002201C))
+#define I2C2_MASTER_MCR_R (*((volatile unsigned long *)0x40022020))
+#define I2C2_MASTER_MCLKOCNT_R (*((volatile unsigned long *)0x40022024))
+#define I2C2_MASTER_MBMON_R (*((volatile unsigned long *)0x4002202C))
+
+//*****************************************************************************
+//
+// I2C registers (I2C2 SLAVE)
+//
+//*****************************************************************************
+#define I2C2_SLAVE_SOAR_R (*((volatile unsigned long *)0x40022800))
+#define I2C2_SLAVE_SCSR_R (*((volatile unsigned long *)0x40022804))
+#define I2C2_SLAVE_SDR_R (*((volatile unsigned long *)0x40022808))
+#define I2C2_SLAVE_SIMR_R (*((volatile unsigned long *)0x4002280C))
+#define I2C2_SLAVE_SRIS_R (*((volatile unsigned long *)0x40022810))
+#define I2C2_SLAVE_SMIS_R (*((volatile unsigned long *)0x40022814))
+#define I2C2_SLAVE_SICR_R (*((volatile unsigned long *)0x40022818))
+#define I2C2_SLAVE_SOAR2_R (*((volatile unsigned long *)0x4002281C))
+#define I2C2_SLAVE_SACKCTL_R (*((volatile unsigned long *)0x40022820))
+
+//*****************************************************************************
+//
+// I2C registers (I2C3 MASTER)
+//
+//*****************************************************************************
+#define I2C3_MASTER_MSA_R (*((volatile unsigned long *)0x40023000))
+#define I2C3_MASTER_MCS_R (*((volatile unsigned long *)0x40023004))
+#define I2C3_MASTER_MDR_R (*((volatile unsigned long *)0x40023008))
+#define I2C3_MASTER_MTPR_R (*((volatile unsigned long *)0x4002300C))
+#define I2C3_MASTER_MIMR_R (*((volatile unsigned long *)0x40023010))
+#define I2C3_MASTER_MRIS_R (*((volatile unsigned long *)0x40023014))
+#define I2C3_MASTER_MMIS_R (*((volatile unsigned long *)0x40023018))
+#define I2C3_MASTER_MICR_R (*((volatile unsigned long *)0x4002301C))
+#define I2C3_MASTER_MCR_R (*((volatile unsigned long *)0x40023020))
+#define I2C3_MASTER_MCLKOCNT_R (*((volatile unsigned long *)0x40023024))
+#define I2C3_MASTER_MBMON_R (*((volatile unsigned long *)0x4002302C))
+
+//*****************************************************************************
+//
+// I2C registers (I2C3 SLAVE)
+//
+//*****************************************************************************
+#define I2C3_SLAVE_SOAR_R (*((volatile unsigned long *)0x40023800))
+#define I2C3_SLAVE_SCSR_R (*((volatile unsigned long *)0x40023804))
+#define I2C3_SLAVE_SDR_R (*((volatile unsigned long *)0x40023808))
+#define I2C3_SLAVE_SIMR_R (*((volatile unsigned long *)0x4002380C))
+#define I2C3_SLAVE_SRIS_R (*((volatile unsigned long *)0x40023810))
+#define I2C3_SLAVE_SMIS_R (*((volatile unsigned long *)0x40023814))
+#define I2C3_SLAVE_SICR_R (*((volatile unsigned long *)0x40023818))
+#define I2C3_SLAVE_SOAR2_R (*((volatile unsigned long *)0x4002381C))
+#define I2C3_SLAVE_SACKCTL_R (*((volatile unsigned long *)0x40023820))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTE)
+//
+//*****************************************************************************
+#define GPIO_PORTE_DATA_BITS_R ((volatile unsigned long *)0x40024000)
+#define GPIO_PORTE_DATA_R (*((volatile unsigned long *)0x400243FC))
+#define GPIO_PORTE_DIR_R (*((volatile unsigned long *)0x40024400))
+#define GPIO_PORTE_IS_R (*((volatile unsigned long *)0x40024404))
+#define GPIO_PORTE_IBE_R (*((volatile unsigned long *)0x40024408))
+#define GPIO_PORTE_IEV_R (*((volatile unsigned long *)0x4002440C))
+#define GPIO_PORTE_IM_R (*((volatile unsigned long *)0x40024410))
+#define GPIO_PORTE_RIS_R (*((volatile unsigned long *)0x40024414))
+#define GPIO_PORTE_MIS_R (*((volatile unsigned long *)0x40024418))
+#define GPIO_PORTE_ICR_R (*((volatile unsigned long *)0x4002441C))
+#define GPIO_PORTE_AFSEL_R (*((volatile unsigned long *)0x40024420))
+#define GPIO_PORTE_DR2R_R (*((volatile unsigned long *)0x40024500))
+#define GPIO_PORTE_DR4R_R (*((volatile unsigned long *)0x40024504))
+#define GPIO_PORTE_DR8R_R (*((volatile unsigned long *)0x40024508))
+#define GPIO_PORTE_ODR_R (*((volatile unsigned long *)0x4002450C))
+#define GPIO_PORTE_PUR_R (*((volatile unsigned long *)0x40024510))
+#define GPIO_PORTE_PDR_R (*((volatile unsigned long *)0x40024514))
+#define GPIO_PORTE_SLR_R (*((volatile unsigned long *)0x40024518))
+#define GPIO_PORTE_DEN_R (*((volatile unsigned long *)0x4002451C))
+#define GPIO_PORTE_LOCK_R (*((volatile unsigned long *)0x40024520))
+#define GPIO_PORTE_CR_R (*((volatile unsigned long *)0x40024524))
+#define GPIO_PORTE_AMSEL_R (*((volatile unsigned long *)0x40024528))
+#define GPIO_PORTE_PCTL_R (*((volatile unsigned long *)0x4002452C))
+#define GPIO_PORTE_ADCCTL_R (*((volatile unsigned long *)0x40024530))
+#define GPIO_PORTE_DMACTL_R (*((volatile unsigned long *)0x40024534))
+#define GPIO_PORTE_SI_R (*((volatile unsigned long *)0x40024538))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTF)
+//
+//*****************************************************************************
+#define GPIO_PORTF_DATA_BITS_R ((volatile unsigned long *)0x40025000)
+#define GPIO_PORTF_DATA_R (*((volatile unsigned long *)0x400253FC))
+#define GPIO_PORTF_DIR_R (*((volatile unsigned long *)0x40025400))
+#define GPIO_PORTF_IS_R (*((volatile unsigned long *)0x40025404))
+#define GPIO_PORTF_IBE_R (*((volatile unsigned long *)0x40025408))
+#define GPIO_PORTF_IEV_R (*((volatile unsigned long *)0x4002540C))
+#define GPIO_PORTF_IM_R (*((volatile unsigned long *)0x40025410))
+#define GPIO_PORTF_RIS_R (*((volatile unsigned long *)0x40025414))
+#define GPIO_PORTF_MIS_R (*((volatile unsigned long *)0x40025418))
+#define GPIO_PORTF_ICR_R (*((volatile unsigned long *)0x4002541C))
+#define GPIO_PORTF_AFSEL_R (*((volatile unsigned long *)0x40025420))
+#define GPIO_PORTF_DR2R_R (*((volatile unsigned long *)0x40025500))
+#define GPIO_PORTF_DR4R_R (*((volatile unsigned long *)0x40025504))
+#define GPIO_PORTF_DR8R_R (*((volatile unsigned long *)0x40025508))
+#define GPIO_PORTF_ODR_R (*((volatile unsigned long *)0x4002550C))
+#define GPIO_PORTF_PUR_R (*((volatile unsigned long *)0x40025510))
+#define GPIO_PORTF_PDR_R (*((volatile unsigned long *)0x40025514))
+#define GPIO_PORTF_SLR_R (*((volatile unsigned long *)0x40025518))
+#define GPIO_PORTF_DEN_R (*((volatile unsigned long *)0x4002551C))
+#define GPIO_PORTF_LOCK_R (*((volatile unsigned long *)0x40025520))
+#define GPIO_PORTF_CR_R (*((volatile unsigned long *)0x40025524))
+#define GPIO_PORTF_AMSEL_R (*((volatile unsigned long *)0x40025528))
+#define GPIO_PORTF_PCTL_R (*((volatile unsigned long *)0x4002552C))
+#define GPIO_PORTF_ADCCTL_R (*((volatile unsigned long *)0x40025530))
+#define GPIO_PORTF_DMACTL_R (*((volatile unsigned long *)0x40025534))
+#define GPIO_PORTF_SI_R (*((volatile unsigned long *)0x40025538))
+
+//*****************************************************************************
+//
+// Timer registers (TIMER0)
+//
+//*****************************************************************************
+#define TIMER0_CFG_R (*((volatile unsigned long *)0x40030000))
+#define TIMER0_TAMR_R (*((volatile unsigned long *)0x40030004))
+#define TIMER0_TBMR_R (*((volatile unsigned long *)0x40030008))
+#define TIMER0_CTL_R (*((volatile unsigned long *)0x4003000C))
+#define TIMER0_SYNC_R (*((volatile unsigned long *)0x40030010))
+#define TIMER0_IMR_R (*((volatile unsigned long *)0x40030018))
+#define TIMER0_RIS_R (*((volatile unsigned long *)0x4003001C))
+#define TIMER0_MIS_R (*((volatile unsigned long *)0x40030020))
+#define TIMER0_ICR_R (*((volatile unsigned long *)0x40030024))
+#define TIMER0_TAILR_R (*((volatile unsigned long *)0x40030028))
+#define TIMER0_TBILR_R (*((volatile unsigned long *)0x4003002C))
+#define TIMER0_TAMATCHR_R (*((volatile unsigned long *)0x40030030))
+#define TIMER0_TBMATCHR_R (*((volatile unsigned long *)0x40030034))
+#define TIMER0_TAPR_R (*((volatile unsigned long *)0x40030038))
+#define TIMER0_TBPR_R (*((volatile unsigned long *)0x4003003C))
+#define TIMER0_TAPMR_R (*((volatile unsigned long *)0x40030040))
+#define TIMER0_TBPMR_R (*((volatile unsigned long *)0x40030044))
+#define TIMER0_TAR_R (*((volatile unsigned long *)0x40030048))
+#define TIMER0_TBR_R (*((volatile unsigned long *)0x4003004C))
+#define TIMER0_TAV_R (*((volatile unsigned long *)0x40030050))
+#define TIMER0_TBV_R (*((volatile unsigned long *)0x40030054))
+#define TIMER0_RTCPD_R (*((volatile unsigned long *)0x40030058))
+#define TIMER0_TAPS_R (*((volatile unsigned long *)0x4003005C))
+#define TIMER0_TBPS_R (*((volatile unsigned long *)0x40030060))
+#define TIMER0_TAPV_R (*((volatile unsigned long *)0x40030064))
+#define TIMER0_TBPV_R (*((volatile unsigned long *)0x40030068))
+#define TIMER0_PP_R (*((volatile unsigned long *)0x40030FC0))
+
+//*****************************************************************************
+//
+// Timer registers (TIMER1)
+//
+//*****************************************************************************
+#define TIMER1_CFG_R (*((volatile unsigned long *)0x40031000))
+#define TIMER1_TAMR_R (*((volatile unsigned long *)0x40031004))
+#define TIMER1_TBMR_R (*((volatile unsigned long *)0x40031008))
+#define TIMER1_CTL_R (*((volatile unsigned long *)0x4003100C))
+#define TIMER1_SYNC_R (*((volatile unsigned long *)0x40031010))
+#define TIMER1_IMR_R (*((volatile unsigned long *)0x40031018))
+#define TIMER1_RIS_R (*((volatile unsigned long *)0x4003101C))
+#define TIMER1_MIS_R (*((volatile unsigned long *)0x40031020))
+#define TIMER1_ICR_R (*((volatile unsigned long *)0x40031024))
+#define TIMER1_TAILR_R (*((volatile unsigned long *)0x40031028))
+#define TIMER1_TBILR_R (*((volatile unsigned long *)0x4003102C))
+#define TIMER1_TAMATCHR_R (*((volatile unsigned long *)0x40031030))
+#define TIMER1_TBMATCHR_R (*((volatile unsigned long *)0x40031034))
+#define TIMER1_TAPR_R (*((volatile unsigned long *)0x40031038))
+#define TIMER1_TBPR_R (*((volatile unsigned long *)0x4003103C))
+#define TIMER1_TAPMR_R (*((volatile unsigned long *)0x40031040))
+#define TIMER1_TBPMR_R (*((volatile unsigned long *)0x40031044))
+#define TIMER1_TAR_R (*((volatile unsigned long *)0x40031048))
+#define TIMER1_TBR_R (*((volatile unsigned long *)0x4003104C))
+#define TIMER1_TAV_R (*((volatile unsigned long *)0x40031050))
+#define TIMER1_TBV_R (*((volatile unsigned long *)0x40031054))
+#define TIMER1_RTCPD_R (*((volatile unsigned long *)0x40031058))
+#define TIMER1_TAPS_R (*((volatile unsigned long *)0x4003105C))
+#define TIMER1_TBPS_R (*((volatile unsigned long *)0x40031060))
+#define TIMER1_TAPV_R (*((volatile unsigned long *)0x40031064))
+#define TIMER1_TBPV_R (*((volatile unsigned long *)0x40031068))
+#define TIMER1_PP_R (*((volatile unsigned long *)0x40031FC0))
+
+//*****************************************************************************
+//
+// Timer registers (TIMER2)
+//
+//*****************************************************************************
+#define TIMER2_CFG_R (*((volatile unsigned long *)0x40032000))
+#define TIMER2_TAMR_R (*((volatile unsigned long *)0x40032004))
+#define TIMER2_TBMR_R (*((volatile unsigned long *)0x40032008))
+#define TIMER2_CTL_R (*((volatile unsigned long *)0x4003200C))
+#define TIMER2_SYNC_R (*((volatile unsigned long *)0x40032010))
+#define TIMER2_IMR_R (*((volatile unsigned long *)0x40032018))
+#define TIMER2_RIS_R (*((volatile unsigned long *)0x4003201C))
+#define TIMER2_MIS_R (*((volatile unsigned long *)0x40032020))
+#define TIMER2_ICR_R (*((volatile unsigned long *)0x40032024))
+#define TIMER2_TAILR_R (*((volatile unsigned long *)0x40032028))
+#define TIMER2_TBILR_R (*((volatile unsigned long *)0x4003202C))
+#define TIMER2_TAMATCHR_R (*((volatile unsigned long *)0x40032030))
+#define TIMER2_TBMATCHR_R (*((volatile unsigned long *)0x40032034))
+#define TIMER2_TAPR_R (*((volatile unsigned long *)0x40032038))
+#define TIMER2_TBPR_R (*((volatile unsigned long *)0x4003203C))
+#define TIMER2_TAPMR_R (*((volatile unsigned long *)0x40032040))
+#define TIMER2_TBPMR_R (*((volatile unsigned long *)0x40032044))
+#define TIMER2_TAR_R (*((volatile unsigned long *)0x40032048))
+#define TIMER2_TBR_R (*((volatile unsigned long *)0x4003204C))
+#define TIMER2_TAV_R (*((volatile unsigned long *)0x40032050))
+#define TIMER2_TBV_R (*((volatile unsigned long *)0x40032054))
+#define TIMER2_RTCPD_R (*((volatile unsigned long *)0x40032058))
+#define TIMER2_TAPS_R (*((volatile unsigned long *)0x4003205C))
+#define TIMER2_TBPS_R (*((volatile unsigned long *)0x40032060))
+#define TIMER2_TAPV_R (*((volatile unsigned long *)0x40032064))
+#define TIMER2_TBPV_R (*((volatile unsigned long *)0x40032068))
+#define TIMER2_PP_R (*((volatile unsigned long *)0x40032FC0))
+
+//*****************************************************************************
+//
+// Timer registers (TIMER3)
+//
+//*****************************************************************************
+#define TIMER3_CFG_R (*((volatile unsigned long *)0x40033000))
+#define TIMER3_TAMR_R (*((volatile unsigned long *)0x40033004))
+#define TIMER3_TBMR_R (*((volatile unsigned long *)0x40033008))
+#define TIMER3_CTL_R (*((volatile unsigned long *)0x4003300C))
+#define TIMER3_SYNC_R (*((volatile unsigned long *)0x40033010))
+#define TIMER3_IMR_R (*((volatile unsigned long *)0x40033018))
+#define TIMER3_RIS_R (*((volatile unsigned long *)0x4003301C))
+#define TIMER3_MIS_R (*((volatile unsigned long *)0x40033020))
+#define TIMER3_ICR_R (*((volatile unsigned long *)0x40033024))
+#define TIMER3_TAILR_R (*((volatile unsigned long *)0x40033028))
+#define TIMER3_TBILR_R (*((volatile unsigned long *)0x4003302C))
+#define TIMER3_TAMATCHR_R (*((volatile unsigned long *)0x40033030))
+#define TIMER3_TBMATCHR_R (*((volatile unsigned long *)0x40033034))
+#define TIMER3_TAPR_R (*((volatile unsigned long *)0x40033038))
+#define TIMER3_TBPR_R (*((volatile unsigned long *)0x4003303C))
+#define TIMER3_TAPMR_R (*((volatile unsigned long *)0x40033040))
+#define TIMER3_TBPMR_R (*((volatile unsigned long *)0x40033044))
+#define TIMER3_TAR_R (*((volatile unsigned long *)0x40033048))
+#define TIMER3_TBR_R (*((volatile unsigned long *)0x4003304C))
+#define TIMER3_TAV_R (*((volatile unsigned long *)0x40033050))
+#define TIMER3_TBV_R (*((volatile unsigned long *)0x40033054))
+#define TIMER3_RTCPD_R (*((volatile unsigned long *)0x40033058))
+#define TIMER3_TAPS_R (*((volatile unsigned long *)0x4003305C))
+#define TIMER3_TBPS_R (*((volatile unsigned long *)0x40033060))
+#define TIMER3_TAPV_R (*((volatile unsigned long *)0x40033064))
+#define TIMER3_TBPV_R (*((volatile unsigned long *)0x40033068))
+#define TIMER3_PP_R (*((volatile unsigned long *)0x40033FC0))
+
+//*****************************************************************************
+//
+// Timer registers (TIMER4)
+//
+//*****************************************************************************
+#define TIMER4_CFG_R (*((volatile unsigned long *)0x40034000))
+#define TIMER4_TAMR_R (*((volatile unsigned long *)0x40034004))
+#define TIMER4_TBMR_R (*((volatile unsigned long *)0x40034008))
+#define TIMER4_CTL_R (*((volatile unsigned long *)0x4003400C))
+#define TIMER4_SYNC_R (*((volatile unsigned long *)0x40034010))
+#define TIMER4_IMR_R (*((volatile unsigned long *)0x40034018))
+#define TIMER4_RIS_R (*((volatile unsigned long *)0x4003401C))
+#define TIMER4_MIS_R (*((volatile unsigned long *)0x40034020))
+#define TIMER4_ICR_R (*((volatile unsigned long *)0x40034024))
+#define TIMER4_TAILR_R (*((volatile unsigned long *)0x40034028))
+#define TIMER4_TBILR_R (*((volatile unsigned long *)0x4003402C))
+#define TIMER4_TAMATCHR_R (*((volatile unsigned long *)0x40034030))
+#define TIMER4_TBMATCHR_R (*((volatile unsigned long *)0x40034034))
+#define TIMER4_TAPR_R (*((volatile unsigned long *)0x40034038))
+#define TIMER4_TBPR_R (*((volatile unsigned long *)0x4003403C))
+#define TIMER4_TAPMR_R (*((volatile unsigned long *)0x40034040))
+#define TIMER4_TBPMR_R (*((volatile unsigned long *)0x40034044))
+#define TIMER4_TAR_R (*((volatile unsigned long *)0x40034048))
+#define TIMER4_TBR_R (*((volatile unsigned long *)0x4003404C))
+#define TIMER4_TAV_R (*((volatile unsigned long *)0x40034050))
+#define TIMER4_TBV_R (*((volatile unsigned long *)0x40034054))
+#define TIMER4_RTCPD_R (*((volatile unsigned long *)0x40034058))
+#define TIMER4_TAPS_R (*((volatile unsigned long *)0x4003405C))
+#define TIMER4_TBPS_R (*((volatile unsigned long *)0x40034060))
+#define TIMER4_TAPV_R (*((volatile unsigned long *)0x40034064))
+#define TIMER4_TBPV_R (*((volatile unsigned long *)0x40034068))
+#define TIMER4_PP_R (*((volatile unsigned long *)0x40034FC0))
+
+//*****************************************************************************
+//
+// Timer registers (TIMER5)
+//
+//*****************************************************************************
+#define TIMER5_CFG_R (*((volatile unsigned long *)0x40035000))
+#define TIMER5_TAMR_R (*((volatile unsigned long *)0x40035004))
+#define TIMER5_TBMR_R (*((volatile unsigned long *)0x40035008))
+#define TIMER5_CTL_R (*((volatile unsigned long *)0x4003500C))
+#define TIMER5_SYNC_R (*((volatile unsigned long *)0x40035010))
+#define TIMER5_IMR_R (*((volatile unsigned long *)0x40035018))
+#define TIMER5_RIS_R (*((volatile unsigned long *)0x4003501C))
+#define TIMER5_MIS_R (*((volatile unsigned long *)0x40035020))
+#define TIMER5_ICR_R (*((volatile unsigned long *)0x40035024))
+#define TIMER5_TAILR_R (*((volatile unsigned long *)0x40035028))
+#define TIMER5_TBILR_R (*((volatile unsigned long *)0x4003502C))
+#define TIMER5_TAMATCHR_R (*((volatile unsigned long *)0x40035030))
+#define TIMER5_TBMATCHR_R (*((volatile unsigned long *)0x40035034))
+#define TIMER5_TAPR_R (*((volatile unsigned long *)0x40035038))
+#define TIMER5_TBPR_R (*((volatile unsigned long *)0x4003503C))
+#define TIMER5_TAPMR_R (*((volatile unsigned long *)0x40035040))
+#define TIMER5_TBPMR_R (*((volatile unsigned long *)0x40035044))
+#define TIMER5_TAR_R (*((volatile unsigned long *)0x40035048))
+#define TIMER5_TBR_R (*((volatile unsigned long *)0x4003504C))
+#define TIMER5_TAV_R (*((volatile unsigned long *)0x40035050))
+#define TIMER5_TBV_R (*((volatile unsigned long *)0x40035054))
+#define TIMER5_RTCPD_R (*((volatile unsigned long *)0x40035058))
+#define TIMER5_TAPS_R (*((volatile unsigned long *)0x4003505C))
+#define TIMER5_TBPS_R (*((volatile unsigned long *)0x40035060))
+#define TIMER5_TAPV_R (*((volatile unsigned long *)0x40035064))
+#define TIMER5_TBPV_R (*((volatile unsigned long *)0x40035068))
+#define TIMER5_PP_R (*((volatile unsigned long *)0x40035FC0))
+
+//*****************************************************************************
+//
+// Timer registers (WTIMER0)
+//
+//*****************************************************************************
+#define WTIMER0_CFG_R (*((volatile unsigned long *)0x40036000))
+#define WTIMER0_TAMR_R (*((volatile unsigned long *)0x40036004))
+#define WTIMER0_TBMR_R (*((volatile unsigned long *)0x40036008))
+#define WTIMER0_CTL_R (*((volatile unsigned long *)0x4003600C))
+#define WTIMER0_SYNC_R (*((volatile unsigned long *)0x40036010))
+#define WTIMER0_IMR_R (*((volatile unsigned long *)0x40036018))
+#define WTIMER0_RIS_R (*((volatile unsigned long *)0x4003601C))
+#define WTIMER0_MIS_R (*((volatile unsigned long *)0x40036020))
+#define WTIMER0_ICR_R (*((volatile unsigned long *)0x40036024))
+#define WTIMER0_TAILR_R (*((volatile unsigned long *)0x40036028))
+#define WTIMER0_TBILR_R (*((volatile unsigned long *)0x4003602C))
+#define WTIMER0_TAMATCHR_R (*((volatile unsigned long *)0x40036030))
+#define WTIMER0_TBMATCHR_R (*((volatile unsigned long *)0x40036034))
+#define WTIMER0_TAPR_R (*((volatile unsigned long *)0x40036038))
+#define WTIMER0_TBPR_R (*((volatile unsigned long *)0x4003603C))
+#define WTIMER0_TAPMR_R (*((volatile unsigned long *)0x40036040))
+#define WTIMER0_TBPMR_R (*((volatile unsigned long *)0x40036044))
+#define WTIMER0_TAR_R (*((volatile unsigned long *)0x40036048))
+#define WTIMER0_TBR_R (*((volatile unsigned long *)0x4003604C))
+#define WTIMER0_TAV_R (*((volatile unsigned long *)0x40036050))
+#define WTIMER0_TBV_R (*((volatile unsigned long *)0x40036054))
+#define WTIMER0_RTCPD_R (*((volatile unsigned long *)0x40036058))
+#define WTIMER0_TAPS_R (*((volatile unsigned long *)0x4003605C))
+#define WTIMER0_TBPS_R (*((volatile unsigned long *)0x40036060))
+#define WTIMER0_TAPV_R (*((volatile unsigned long *)0x40036064))
+#define WTIMER0_TBPV_R (*((volatile unsigned long *)0x40036068))
+#define WTIMER0_PP_R (*((volatile unsigned long *)0x40036FC0))
+
+//*****************************************************************************
+//
+// Timer registers (WTIMER1)
+//
+//*****************************************************************************
+#define WTIMER1_CFG_R (*((volatile unsigned long *)0x40037000))
+#define WTIMER1_TAMR_R (*((volatile unsigned long *)0x40037004))
+#define WTIMER1_TBMR_R (*((volatile unsigned long *)0x40037008))
+#define WTIMER1_CTL_R (*((volatile unsigned long *)0x4003700C))
+#define WTIMER1_SYNC_R (*((volatile unsigned long *)0x40037010))
+#define WTIMER1_IMR_R (*((volatile unsigned long *)0x40037018))
+#define WTIMER1_RIS_R (*((volatile unsigned long *)0x4003701C))
+#define WTIMER1_MIS_R (*((volatile unsigned long *)0x40037020))
+#define WTIMER1_ICR_R (*((volatile unsigned long *)0x40037024))
+#define WTIMER1_TAILR_R (*((volatile unsigned long *)0x40037028))
+#define WTIMER1_TBILR_R (*((volatile unsigned long *)0x4003702C))
+#define WTIMER1_TAMATCHR_R (*((volatile unsigned long *)0x40037030))
+#define WTIMER1_TBMATCHR_R (*((volatile unsigned long *)0x40037034))
+#define WTIMER1_TAPR_R (*((volatile unsigned long *)0x40037038))
+#define WTIMER1_TBPR_R (*((volatile unsigned long *)0x4003703C))
+#define WTIMER1_TAPMR_R (*((volatile unsigned long *)0x40037040))
+#define WTIMER1_TBPMR_R (*((volatile unsigned long *)0x40037044))
+#define WTIMER1_TAR_R (*((volatile unsigned long *)0x40037048))
+#define WTIMER1_TBR_R (*((volatile unsigned long *)0x4003704C))
+#define WTIMER1_TAV_R (*((volatile unsigned long *)0x40037050))
+#define WTIMER1_TBV_R (*((volatile unsigned long *)0x40037054))
+#define WTIMER1_RTCPD_R (*((volatile unsigned long *)0x40037058))
+#define WTIMER1_TAPS_R (*((volatile unsigned long *)0x4003705C))
+#define WTIMER1_TBPS_R (*((volatile unsigned long *)0x40037060))
+#define WTIMER1_TAPV_R (*((volatile unsigned long *)0x40037064))
+#define WTIMER1_TBPV_R (*((volatile unsigned long *)0x40037068))
+#define WTIMER1_PP_R (*((volatile unsigned long *)0x40037FC0))
+
+//*****************************************************************************
+//
+// ADC registers (ADC0)
+//
+//*****************************************************************************
+#define ADC0_ACTSS_R (*((volatile unsigned long *)0x40038000))
+#define ADC0_RIS_R (*((volatile unsigned long *)0x40038004))
+#define ADC0_IM_R (*((volatile unsigned long *)0x40038008))
+#define ADC0_ISC_R (*((volatile unsigned long *)0x4003800C))
+#define ADC0_OSTAT_R (*((volatile unsigned long *)0x40038010))
+#define ADC0_EMUX_R (*((volatile unsigned long *)0x40038014))
+#define ADC0_USTAT_R (*((volatile unsigned long *)0x40038018))
+#define ADC0_SSPRI_R (*((volatile unsigned long *)0x40038020))
+#define ADC0_SPC_R (*((volatile unsigned long *)0x40038024))
+#define ADC0_PSSI_R (*((volatile unsigned long *)0x40038028))
+#define ADC0_SAC_R (*((volatile unsigned long *)0x40038030))
+#define ADC0_DCISC_R (*((volatile unsigned long *)0x40038034))
+#define ADC0_SSMUX0_R (*((volatile unsigned long *)0x40038040))
+#define ADC0_SSCTL0_R (*((volatile unsigned long *)0x40038044))
+#define ADC0_SSFIFO0_R (*((volatile unsigned long *)0x40038048))
+#define ADC0_SSFSTAT0_R (*((volatile unsigned long *)0x4003804C))
+#define ADC0_SSOP0_R (*((volatile unsigned long *)0x40038050))
+#define ADC0_SSDC0_R (*((volatile unsigned long *)0x40038054))
+#define ADC0_SSMUX1_R (*((volatile unsigned long *)0x40038060))
+#define ADC0_SSCTL1_R (*((volatile unsigned long *)0x40038064))
+#define ADC0_SSFIFO1_R (*((volatile unsigned long *)0x40038068))
+#define ADC0_SSFSTAT1_R (*((volatile unsigned long *)0x4003806C))
+#define ADC0_SSOP1_R (*((volatile unsigned long *)0x40038070))
+#define ADC0_SSDC1_R (*((volatile unsigned long *)0x40038074))
+#define ADC0_SSMUX2_R (*((volatile unsigned long *)0x40038080))
+#define ADC0_SSCTL2_R (*((volatile unsigned long *)0x40038084))
+#define ADC0_SSFIFO2_R (*((volatile unsigned long *)0x40038088))
+#define ADC0_SSFSTAT2_R (*((volatile unsigned long *)0x4003808C))
+#define ADC0_SSOP2_R (*((volatile unsigned long *)0x40038090))
+#define ADC0_SSDC2_R (*((volatile unsigned long *)0x40038094))
+#define ADC0_SSMUX3_R (*((volatile unsigned long *)0x400380A0))
+#define ADC0_SSCTL3_R (*((volatile unsigned long *)0x400380A4))
+#define ADC0_SSFIFO3_R (*((volatile unsigned long *)0x400380A8))
+#define ADC0_SSFSTAT3_R (*((volatile unsigned long *)0x400380AC))
+#define ADC0_SSOP3_R (*((volatile unsigned long *)0x400380B0))
+#define ADC0_SSDC3_R (*((volatile unsigned long *)0x400380B4))
+#define ADC0_DCRIC_R (*((volatile unsigned long *)0x40038D00))
+#define ADC0_DCCTL0_R (*((volatile unsigned long *)0x40038E00))
+#define ADC0_DCCTL1_R (*((volatile unsigned long *)0x40038E04))
+#define ADC0_DCCTL2_R (*((volatile unsigned long *)0x40038E08))
+#define ADC0_DCCTL3_R (*((volatile unsigned long *)0x40038E0C))
+#define ADC0_DCCTL4_R (*((volatile unsigned long *)0x40038E10))
+#define ADC0_DCCTL5_R (*((volatile unsigned long *)0x40038E14))
+#define ADC0_DCCTL6_R (*((volatile unsigned long *)0x40038E18))
+#define ADC0_DCCTL7_R (*((volatile unsigned long *)0x40038E1C))
+#define ADC0_DCCMP0_R (*((volatile unsigned long *)0x40038E40))
+#define ADC0_DCCMP1_R (*((volatile unsigned long *)0x40038E44))
+#define ADC0_DCCMP2_R (*((volatile unsigned long *)0x40038E48))
+#define ADC0_DCCMP3_R (*((volatile unsigned long *)0x40038E4C))
+#define ADC0_DCCMP4_R (*((volatile unsigned long *)0x40038E50))
+#define ADC0_DCCMP5_R (*((volatile unsigned long *)0x40038E54))
+#define ADC0_DCCMP6_R (*((volatile unsigned long *)0x40038E58))
+#define ADC0_DCCMP7_R (*((volatile unsigned long *)0x40038E5C))
+#define ADC0_PP_R (*((volatile unsigned long *)0x40038FC0))
+#define ADC0_PC_R (*((volatile unsigned long *)0x40038FC4))
+#define ADC0_CC_R (*((volatile unsigned long *)0x40038FC8))
+
+//*****************************************************************************
+//
+// ADC registers (ADC1)
+//
+//*****************************************************************************
+#define ADC1_ACTSS_R (*((volatile unsigned long *)0x40039000))
+#define ADC1_RIS_R (*((volatile unsigned long *)0x40039004))
+#define ADC1_IM_R (*((volatile unsigned long *)0x40039008))
+#define ADC1_ISC_R (*((volatile unsigned long *)0x4003900C))
+#define ADC1_OSTAT_R (*((volatile unsigned long *)0x40039010))
+#define ADC1_EMUX_R (*((volatile unsigned long *)0x40039014))
+#define ADC1_USTAT_R (*((volatile unsigned long *)0x40039018))
+#define ADC1_SSPRI_R (*((volatile unsigned long *)0x40039020))
+#define ADC1_SPC_R (*((volatile unsigned long *)0x40039024))
+#define ADC1_PSSI_R (*((volatile unsigned long *)0x40039028))
+#define ADC1_SAC_R (*((volatile unsigned long *)0x40039030))
+#define ADC1_DCISC_R (*((volatile unsigned long *)0x40039034))
+#define ADC1_SSMUX0_R (*((volatile unsigned long *)0x40039040))
+#define ADC1_SSCTL0_R (*((volatile unsigned long *)0x40039044))
+#define ADC1_SSFIFO0_R (*((volatile unsigned long *)0x40039048))
+#define ADC1_SSFSTAT0_R (*((volatile unsigned long *)0x4003904C))
+#define ADC1_SSOP0_R (*((volatile unsigned long *)0x40039050))
+#define ADC1_SSDC0_R (*((volatile unsigned long *)0x40039054))
+#define ADC1_SSMUX1_R (*((volatile unsigned long *)0x40039060))
+#define ADC1_SSCTL1_R (*((volatile unsigned long *)0x40039064))
+#define ADC1_SSFIFO1_R (*((volatile unsigned long *)0x40039068))
+#define ADC1_SSFSTAT1_R (*((volatile unsigned long *)0x4003906C))
+#define ADC1_SSOP1_R (*((volatile unsigned long *)0x40039070))
+#define ADC1_SSDC1_R (*((volatile unsigned long *)0x40039074))
+#define ADC1_SSMUX2_R (*((volatile unsigned long *)0x40039080))
+#define ADC1_SSCTL2_R (*((volatile unsigned long *)0x40039084))
+#define ADC1_SSFIFO2_R (*((volatile unsigned long *)0x40039088))
+#define ADC1_SSFSTAT2_R (*((volatile unsigned long *)0x4003908C))
+#define ADC1_SSOP2_R (*((volatile unsigned long *)0x40039090))
+#define ADC1_SSDC2_R (*((volatile unsigned long *)0x40039094))
+#define ADC1_SSMUX3_R (*((volatile unsigned long *)0x400390A0))
+#define ADC1_SSCTL3_R (*((volatile unsigned long *)0x400390A4))
+#define ADC1_SSFIFO3_R (*((volatile unsigned long *)0x400390A8))
+#define ADC1_SSFSTAT3_R (*((volatile unsigned long *)0x400390AC))
+#define ADC1_SSOP3_R (*((volatile unsigned long *)0x400390B0))
+#define ADC1_SSDC3_R (*((volatile unsigned long *)0x400390B4))
+#define ADC1_DCRIC_R (*((volatile unsigned long *)0x40039D00))
+#define ADC1_DCCTL0_R (*((volatile unsigned long *)0x40039E00))
+#define ADC1_DCCTL1_R (*((volatile unsigned long *)0x40039E04))
+#define ADC1_DCCTL2_R (*((volatile unsigned long *)0x40039E08))
+#define ADC1_DCCTL3_R (*((volatile unsigned long *)0x40039E0C))
+#define ADC1_DCCTL4_R (*((volatile unsigned long *)0x40039E10))
+#define ADC1_DCCTL5_R (*((volatile unsigned long *)0x40039E14))
+#define ADC1_DCCTL6_R (*((volatile unsigned long *)0x40039E18))
+#define ADC1_DCCTL7_R (*((volatile unsigned long *)0x40039E1C))
+#define ADC1_DCCMP0_R (*((volatile unsigned long *)0x40039E40))
+#define ADC1_DCCMP1_R (*((volatile unsigned long *)0x40039E44))
+#define ADC1_DCCMP2_R (*((volatile unsigned long *)0x40039E48))
+#define ADC1_DCCMP3_R (*((volatile unsigned long *)0x40039E4C))
+#define ADC1_DCCMP4_R (*((volatile unsigned long *)0x40039E50))
+#define ADC1_DCCMP5_R (*((volatile unsigned long *)0x40039E54))
+#define ADC1_DCCMP6_R (*((volatile unsigned long *)0x40039E58))
+#define ADC1_DCCMP7_R (*((volatile unsigned long *)0x40039E5C))
+#define ADC1_PP_R (*((volatile unsigned long *)0x40039FC0))
+#define ADC1_PC_R (*((volatile unsigned long *)0x40039FC4))
+#define ADC1_CC_R (*((volatile unsigned long *)0x40039FC8))
+
+//*****************************************************************************
+//
+// Comparator registers (COMP)
+//
+//*****************************************************************************
+#define COMP_ACMIS_R (*((volatile unsigned long *)0x4003C000))
+#define COMP_ACRIS_R (*((volatile unsigned long *)0x4003C004))
+#define COMP_ACINTEN_R (*((volatile unsigned long *)0x4003C008))
+#define COMP_ACREFCTL_R (*((volatile unsigned long *)0x4003C010))
+#define COMP_ACSTAT0_R (*((volatile unsigned long *)0x4003C020))
+#define COMP_ACCTL0_R (*((volatile unsigned long *)0x4003C024))
+#define COMP_ACSTAT1_R (*((volatile unsigned long *)0x4003C040))
+#define COMP_ACCTL1_R (*((volatile unsigned long *)0x4003C044))
+#define COMP_PP_R (*((volatile unsigned long *)0x4003CFC0))
+
+//*****************************************************************************
+//
+// CAN registers (CAN0)
+//
+//*****************************************************************************
+#define CAN0_CTL_R (*((volatile unsigned long *)0x40040000))
+#define CAN0_STS_R (*((volatile unsigned long *)0x40040004))
+#define CAN0_ERR_R (*((volatile unsigned long *)0x40040008))
+#define CAN0_BIT_R (*((volatile unsigned long *)0x4004000C))
+#define CAN0_INT_R (*((volatile unsigned long *)0x40040010))
+#define CAN0_TST_R (*((volatile unsigned long *)0x40040014))
+#define CAN0_BRPE_R (*((volatile unsigned long *)0x40040018))
+#define CAN0_IF1CRQ_R (*((volatile unsigned long *)0x40040020))
+#define CAN0_IF1CMSK_R (*((volatile unsigned long *)0x40040024))
+#define CAN0_IF1MSK1_R (*((volatile unsigned long *)0x40040028))
+#define CAN0_IF1MSK2_R (*((volatile unsigned long *)0x4004002C))
+#define CAN0_IF1ARB1_R (*((volatile unsigned long *)0x40040030))
+#define CAN0_IF1ARB2_R (*((volatile unsigned long *)0x40040034))
+#define CAN0_IF1MCTL_R (*((volatile unsigned long *)0x40040038))
+#define CAN0_IF1DA1_R (*((volatile unsigned long *)0x4004003C))
+#define CAN0_IF1DA2_R (*((volatile unsigned long *)0x40040040))
+#define CAN0_IF1DB1_R (*((volatile unsigned long *)0x40040044))
+#define CAN0_IF1DB2_R (*((volatile unsigned long *)0x40040048))
+#define CAN0_IF2CRQ_R (*((volatile unsigned long *)0x40040080))
+#define CAN0_IF2CMSK_R (*((volatile unsigned long *)0x40040084))
+#define CAN0_IF2MSK1_R (*((volatile unsigned long *)0x40040088))
+#define CAN0_IF2MSK2_R (*((volatile unsigned long *)0x4004008C))
+#define CAN0_IF2ARB1_R (*((volatile unsigned long *)0x40040090))
+#define CAN0_IF2ARB2_R (*((volatile unsigned long *)0x40040094))
+#define CAN0_IF2MCTL_R (*((volatile unsigned long *)0x40040098))
+#define CAN0_IF2DA1_R (*((volatile unsigned long *)0x4004009C))
+#define CAN0_IF2DA2_R (*((volatile unsigned long *)0x400400A0))
+#define CAN0_IF2DB1_R (*((volatile unsigned long *)0x400400A4))
+#define CAN0_IF2DB2_R (*((volatile unsigned long *)0x400400A8))
+#define CAN0_TXRQ1_R (*((volatile unsigned long *)0x40040100))
+#define CAN0_TXRQ2_R (*((volatile unsigned long *)0x40040104))
+#define CAN0_NWDA1_R (*((volatile unsigned long *)0x40040120))
+#define CAN0_NWDA2_R (*((volatile unsigned long *)0x40040124))
+#define CAN0_MSG1INT_R (*((volatile unsigned long *)0x40040140))
+#define CAN0_MSG2INT_R (*((volatile unsigned long *)0x40040144))
+#define CAN0_MSG1VAL_R (*((volatile unsigned long *)0x40040160))
+#define CAN0_MSG2VAL_R (*((volatile unsigned long *)0x40040164))
+
+//*****************************************************************************
+//
+// Timer registers (WTIMER2)
+//
+//*****************************************************************************
+#define WTIMER2_CFG_R (*((volatile unsigned long *)0x4004C000))
+#define WTIMER2_TAMR_R (*((volatile unsigned long *)0x4004C004))
+#define WTIMER2_TBMR_R (*((volatile unsigned long *)0x4004C008))
+#define WTIMER2_CTL_R (*((volatile unsigned long *)0x4004C00C))
+#define WTIMER2_SYNC_R (*((volatile unsigned long *)0x4004C010))
+#define WTIMER2_IMR_R (*((volatile unsigned long *)0x4004C018))
+#define WTIMER2_RIS_R (*((volatile unsigned long *)0x4004C01C))
+#define WTIMER2_MIS_R (*((volatile unsigned long *)0x4004C020))
+#define WTIMER2_ICR_R (*((volatile unsigned long *)0x4004C024))
+#define WTIMER2_TAILR_R (*((volatile unsigned long *)0x4004C028))
+#define WTIMER2_TBILR_R (*((volatile unsigned long *)0x4004C02C))
+#define WTIMER2_TAMATCHR_R (*((volatile unsigned long *)0x4004C030))
+#define WTIMER2_TBMATCHR_R (*((volatile unsigned long *)0x4004C034))
+#define WTIMER2_TAPR_R (*((volatile unsigned long *)0x4004C038))
+#define WTIMER2_TBPR_R (*((volatile unsigned long *)0x4004C03C))
+#define WTIMER2_TAPMR_R (*((volatile unsigned long *)0x4004C040))
+#define WTIMER2_TBPMR_R (*((volatile unsigned long *)0x4004C044))
+#define WTIMER2_TAR_R (*((volatile unsigned long *)0x4004C048))
+#define WTIMER2_TBR_R (*((volatile unsigned long *)0x4004C04C))
+#define WTIMER2_TAV_R (*((volatile unsigned long *)0x4004C050))
+#define WTIMER2_TBV_R (*((volatile unsigned long *)0x4004C054))
+#define WTIMER2_RTCPD_R (*((volatile unsigned long *)0x4004C058))
+#define WTIMER2_TAPS_R (*((volatile unsigned long *)0x4004C05C))
+#define WTIMER2_TBPS_R (*((volatile unsigned long *)0x4004C060))
+#define WTIMER2_TAPV_R (*((volatile unsigned long *)0x4004C064))
+#define WTIMER2_TBPV_R (*((volatile unsigned long *)0x4004C068))
+#define WTIMER2_PP_R (*((volatile unsigned long *)0x4004CFC0))
+
+//*****************************************************************************
+//
+// Timer registers (WTIMER3)
+//
+//*****************************************************************************
+#define WTIMER3_CFG_R (*((volatile unsigned long *)0x4004D000))
+#define WTIMER3_TAMR_R (*((volatile unsigned long *)0x4004D004))
+#define WTIMER3_TBMR_R (*((volatile unsigned long *)0x4004D008))
+#define WTIMER3_CTL_R (*((volatile unsigned long *)0x4004D00C))
+#define WTIMER3_SYNC_R (*((volatile unsigned long *)0x4004D010))
+#define WTIMER3_IMR_R (*((volatile unsigned long *)0x4004D018))
+#define WTIMER3_RIS_R (*((volatile unsigned long *)0x4004D01C))
+#define WTIMER3_MIS_R (*((volatile unsigned long *)0x4004D020))
+#define WTIMER3_ICR_R (*((volatile unsigned long *)0x4004D024))
+#define WTIMER3_TAILR_R (*((volatile unsigned long *)0x4004D028))
+#define WTIMER3_TBILR_R (*((volatile unsigned long *)0x4004D02C))
+#define WTIMER3_TAMATCHR_R (*((volatile unsigned long *)0x4004D030))
+#define WTIMER3_TBMATCHR_R (*((volatile unsigned long *)0x4004D034))
+#define WTIMER3_TAPR_R (*((volatile unsigned long *)0x4004D038))
+#define WTIMER3_TBPR_R (*((volatile unsigned long *)0x4004D03C))
+#define WTIMER3_TAPMR_R (*((volatile unsigned long *)0x4004D040))
+#define WTIMER3_TBPMR_R (*((volatile unsigned long *)0x4004D044))
+#define WTIMER3_TAR_R (*((volatile unsigned long *)0x4004D048))
+#define WTIMER3_TBR_R (*((volatile unsigned long *)0x4004D04C))
+#define WTIMER3_TAV_R (*((volatile unsigned long *)0x4004D050))
+#define WTIMER3_TBV_R (*((volatile unsigned long *)0x4004D054))
+#define WTIMER3_RTCPD_R (*((volatile unsigned long *)0x4004D058))
+#define WTIMER3_TAPS_R (*((volatile unsigned long *)0x4004D05C))
+#define WTIMER3_TBPS_R (*((volatile unsigned long *)0x4004D060))
+#define WTIMER3_TAPV_R (*((volatile unsigned long *)0x4004D064))
+#define WTIMER3_TBPV_R (*((volatile unsigned long *)0x4004D068))
+#define WTIMER3_PP_R (*((volatile unsigned long *)0x4004DFC0))
+
+//*****************************************************************************
+//
+// Timer registers (WTIMER4)
+//
+//*****************************************************************************
+#define WTIMER4_CFG_R (*((volatile unsigned long *)0x4004E000))
+#define WTIMER4_TAMR_R (*((volatile unsigned long *)0x4004E004))
+#define WTIMER4_TBMR_R (*((volatile unsigned long *)0x4004E008))
+#define WTIMER4_CTL_R (*((volatile unsigned long *)0x4004E00C))
+#define WTIMER4_SYNC_R (*((volatile unsigned long *)0x4004E010))
+#define WTIMER4_IMR_R (*((volatile unsigned long *)0x4004E018))
+#define WTIMER4_RIS_R (*((volatile unsigned long *)0x4004E01C))
+#define WTIMER4_MIS_R (*((volatile unsigned long *)0x4004E020))
+#define WTIMER4_ICR_R (*((volatile unsigned long *)0x4004E024))
+#define WTIMER4_TAILR_R (*((volatile unsigned long *)0x4004E028))
+#define WTIMER4_TBILR_R (*((volatile unsigned long *)0x4004E02C))
+#define WTIMER4_TAMATCHR_R (*((volatile unsigned long *)0x4004E030))
+#define WTIMER4_TBMATCHR_R (*((volatile unsigned long *)0x4004E034))
+#define WTIMER4_TAPR_R (*((volatile unsigned long *)0x4004E038))
+#define WTIMER4_TBPR_R (*((volatile unsigned long *)0x4004E03C))
+#define WTIMER4_TAPMR_R (*((volatile unsigned long *)0x4004E040))
+#define WTIMER4_TBPMR_R (*((volatile unsigned long *)0x4004E044))
+#define WTIMER4_TAR_R (*((volatile unsigned long *)0x4004E048))
+#define WTIMER4_TBR_R (*((volatile unsigned long *)0x4004E04C))
+#define WTIMER4_TAV_R (*((volatile unsigned long *)0x4004E050))
+#define WTIMER4_TBV_R (*((volatile unsigned long *)0x4004E054))
+#define WTIMER4_RTCPD_R (*((volatile unsigned long *)0x4004E058))
+#define WTIMER4_TAPS_R (*((volatile unsigned long *)0x4004E05C))
+#define WTIMER4_TBPS_R (*((volatile unsigned long *)0x4004E060))
+#define WTIMER4_TAPV_R (*((volatile unsigned long *)0x4004E064))
+#define WTIMER4_TBPV_R (*((volatile unsigned long *)0x4004E068))
+#define WTIMER4_PP_R (*((volatile unsigned long *)0x4004EFC0))
+
+//*****************************************************************************
+//
+// Timer registers (WTIMER5)
+//
+//*****************************************************************************
+#define WTIMER5_CFG_R (*((volatile unsigned long *)0x4004F000))
+#define WTIMER5_TAMR_R (*((volatile unsigned long *)0x4004F004))
+#define WTIMER5_TBMR_R (*((volatile unsigned long *)0x4004F008))
+#define WTIMER5_CTL_R (*((volatile unsigned long *)0x4004F00C))
+#define WTIMER5_SYNC_R (*((volatile unsigned long *)0x4004F010))
+#define WTIMER5_IMR_R (*((volatile unsigned long *)0x4004F018))
+#define WTIMER5_RIS_R (*((volatile unsigned long *)0x4004F01C))
+#define WTIMER5_MIS_R (*((volatile unsigned long *)0x4004F020))
+#define WTIMER5_ICR_R (*((volatile unsigned long *)0x4004F024))
+#define WTIMER5_TAILR_R (*((volatile unsigned long *)0x4004F028))
+#define WTIMER5_TBILR_R (*((volatile unsigned long *)0x4004F02C))
+#define WTIMER5_TAMATCHR_R (*((volatile unsigned long *)0x4004F030))
+#define WTIMER5_TBMATCHR_R (*((volatile unsigned long *)0x4004F034))
+#define WTIMER5_TAPR_R (*((volatile unsigned long *)0x4004F038))
+#define WTIMER5_TBPR_R (*((volatile unsigned long *)0x4004F03C))
+#define WTIMER5_TAPMR_R (*((volatile unsigned long *)0x4004F040))
+#define WTIMER5_TBPMR_R (*((volatile unsigned long *)0x4004F044))
+#define WTIMER5_TAR_R (*((volatile unsigned long *)0x4004F048))
+#define WTIMER5_TBR_R (*((volatile unsigned long *)0x4004F04C))
+#define WTIMER5_TAV_R (*((volatile unsigned long *)0x4004F050))
+#define WTIMER5_TBV_R (*((volatile unsigned long *)0x4004F054))
+#define WTIMER5_RTCPD_R (*((volatile unsigned long *)0x4004F058))
+#define WTIMER5_TAPS_R (*((volatile unsigned long *)0x4004F05C))
+#define WTIMER5_TBPS_R (*((volatile unsigned long *)0x4004F060))
+#define WTIMER5_TAPV_R (*((volatile unsigned long *)0x4004F064))
+#define WTIMER5_TBPV_R (*((volatile unsigned long *)0x4004F068))
+#define WTIMER5_PP_R (*((volatile unsigned long *)0x4004FFC0))
+
+//*****************************************************************************
+//
+// Univeral Serial Bus registers (USB0)
+//
+//*****************************************************************************
+#define USB0_FADDR_R (*((volatile unsigned char *)0x40050000))
+#define USB0_POWER_R (*((volatile unsigned char *)0x40050001))
+#define USB0_TXIS_R (*((volatile unsigned short *)0x40050002))
+#define USB0_RXIS_R (*((volatile unsigned short *)0x40050004))
+#define USB0_TXIE_R (*((volatile unsigned short *)0x40050006))
+#define USB0_RXIE_R (*((volatile unsigned short *)0x40050008))
+#define USB0_IS_R (*((volatile unsigned char *)0x4005000A))
+#define USB0_IE_R (*((volatile unsigned char *)0x4005000B))
+#define USB0_FRAME_R (*((volatile unsigned short *)0x4005000C))
+#define USB0_EPIDX_R (*((volatile unsigned char *)0x4005000E))
+#define USB0_TEST_R (*((volatile unsigned char *)0x4005000F))
+#define USB0_FIFO0_R (*((volatile unsigned long *)0x40050020))
+#define USB0_FIFO1_R (*((volatile unsigned long *)0x40050024))
+#define USB0_FIFO2_R (*((volatile unsigned long *)0x40050028))
+#define USB0_FIFO3_R (*((volatile unsigned long *)0x4005002C))
+#define USB0_FIFO4_R (*((volatile unsigned long *)0x40050030))
+#define USB0_FIFO5_R (*((volatile unsigned long *)0x40050034))
+#define USB0_FIFO6_R (*((volatile unsigned long *)0x40050038))
+#define USB0_FIFO7_R (*((volatile unsigned long *)0x4005003C))
+#define USB0_TXFIFOSZ_R (*((volatile unsigned char *)0x40050062))
+#define USB0_RXFIFOSZ_R (*((volatile unsigned char *)0x40050063))
+#define USB0_TXFIFOADD_R (*((volatile unsigned short *)0x40050064))
+#define USB0_RXFIFOADD_R (*((volatile unsigned short *)0x40050066))
+#define USB0_CONTIM_R (*((volatile unsigned char *)0x4005007A))
+#define USB0_FSEOF_R (*((volatile unsigned char *)0x4005007D))
+#define USB0_LSEOF_R (*((volatile unsigned char *)0x4005007E))
+#define USB0_CSRL0_R (*((volatile unsigned char *)0x40050102))
+#define USB0_CSRH0_R (*((volatile unsigned char *)0x40050103))
+#define USB0_COUNT0_R (*((volatile unsigned char *)0x40050108))
+#define USB0_TXMAXP1_R (*((volatile unsigned short *)0x40050110))
+#define USB0_TXCSRL1_R (*((volatile unsigned char *)0x40050112))
+#define USB0_TXCSRH1_R (*((volatile unsigned char *)0x40050113))
+#define USB0_RXMAXP1_R (*((volatile unsigned short *)0x40050114))
+#define USB0_RXCSRL1_R (*((volatile unsigned char *)0x40050116))
+#define USB0_RXCSRH1_R (*((volatile unsigned char *)0x40050117))
+#define USB0_RXCOUNT1_R (*((volatile unsigned short *)0x40050118))
+#define USB0_TXMAXP2_R (*((volatile unsigned short *)0x40050120))
+#define USB0_TXCSRL2_R (*((volatile unsigned char *)0x40050122))
+#define USB0_TXCSRH2_R (*((volatile unsigned char *)0x40050123))
+#define USB0_RXMAXP2_R (*((volatile unsigned short *)0x40050124))
+#define USB0_RXCSRL2_R (*((volatile unsigned char *)0x40050126))
+#define USB0_RXCSRH2_R (*((volatile unsigned char *)0x40050127))
+#define USB0_RXCOUNT2_R (*((volatile unsigned short *)0x40050128))
+#define USB0_TXMAXP3_R (*((volatile unsigned short *)0x40050130))
+#define USB0_TXCSRL3_R (*((volatile unsigned char *)0x40050132))
+#define USB0_TXCSRH3_R (*((volatile unsigned char *)0x40050133))
+#define USB0_RXMAXP3_R (*((volatile unsigned short *)0x40050134))
+#define USB0_RXCSRL3_R (*((volatile unsigned char *)0x40050136))
+#define USB0_RXCSRH3_R (*((volatile unsigned char *)0x40050137))
+#define USB0_RXCOUNT3_R (*((volatile unsigned short *)0x40050138))
+#define USB0_TXMAXP4_R (*((volatile unsigned short *)0x40050140))
+#define USB0_TXCSRL4_R (*((volatile unsigned char *)0x40050142))
+#define USB0_TXCSRH4_R (*((volatile unsigned char *)0x40050143))
+#define USB0_RXMAXP4_R (*((volatile unsigned short *)0x40050144))
+#define USB0_RXCSRL4_R (*((volatile unsigned char *)0x40050146))
+#define USB0_RXCSRH4_R (*((volatile unsigned char *)0x40050147))
+#define USB0_RXCOUNT4_R (*((volatile unsigned short *)0x40050148))
+#define USB0_TXMAXP5_R (*((volatile unsigned short *)0x40050150))
+#define USB0_TXCSRL5_R (*((volatile unsigned char *)0x40050152))
+#define USB0_TXCSRH5_R (*((volatile unsigned char *)0x40050153))
+#define USB0_RXMAXP5_R (*((volatile unsigned short *)0x40050154))
+#define USB0_RXCSRL5_R (*((volatile unsigned char *)0x40050156))
+#define USB0_RXCSRH5_R (*((volatile unsigned char *)0x40050157))
+#define USB0_RXCOUNT5_R (*((volatile unsigned short *)0x40050158))
+#define USB0_TXMAXP6_R (*((volatile unsigned short *)0x40050160))
+#define USB0_TXCSRL6_R (*((volatile unsigned char *)0x40050162))
+#define USB0_TXCSRH6_R (*((volatile unsigned char *)0x40050163))
+#define USB0_RXMAXP6_R (*((volatile unsigned short *)0x40050164))
+#define USB0_RXCSRL6_R (*((volatile unsigned char *)0x40050166))
+#define USB0_RXCSRH6_R (*((volatile unsigned char *)0x40050167))
+#define USB0_RXCOUNT6_R (*((volatile unsigned short *)0x40050168))
+#define USB0_TXMAXP7_R (*((volatile unsigned short *)0x40050170))
+#define USB0_TXCSRL7_R (*((volatile unsigned char *)0x40050172))
+#define USB0_TXCSRH7_R (*((volatile unsigned char *)0x40050173))
+#define USB0_RXMAXP7_R (*((volatile unsigned short *)0x40050174))
+#define USB0_RXCSRL7_R (*((volatile unsigned char *)0x40050176))
+#define USB0_RXCSRH7_R (*((volatile unsigned char *)0x40050177))
+#define USB0_RXCOUNT7_R (*((volatile unsigned short *)0x40050178))
+#define USB0_RXDPKTBUFDIS_R (*((volatile unsigned short *)0x40050340))
+#define USB0_TXDPKTBUFDIS_R (*((volatile unsigned short *)0x40050342))
+#define USB0_DRRIS_R (*((volatile unsigned long *)0x40050410))
+#define USB0_DRIM_R (*((volatile unsigned long *)0x40050414))
+#define USB0_DRISC_R (*((volatile unsigned long *)0x40050418))
+#define USB0_DMASEL_R (*((volatile unsigned long *)0x40050450))
+#define USB0_PP_R (*((volatile unsigned long *)0x40050FC0))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTA AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTA_AHB_DATA_BITS_R \
+ ((volatile unsigned long *)0x40058000)
+#define GPIO_PORTA_AHB_DATA_R (*((volatile unsigned long *)0x400583FC))
+#define GPIO_PORTA_AHB_DIR_R (*((volatile unsigned long *)0x40058400))
+#define GPIO_PORTA_AHB_IS_R (*((volatile unsigned long *)0x40058404))
+#define GPIO_PORTA_AHB_IBE_R (*((volatile unsigned long *)0x40058408))
+#define GPIO_PORTA_AHB_IEV_R (*((volatile unsigned long *)0x4005840C))
+#define GPIO_PORTA_AHB_IM_R (*((volatile unsigned long *)0x40058410))
+#define GPIO_PORTA_AHB_RIS_R (*((volatile unsigned long *)0x40058414))
+#define GPIO_PORTA_AHB_MIS_R (*((volatile unsigned long *)0x40058418))
+#define GPIO_PORTA_AHB_ICR_R (*((volatile unsigned long *)0x4005841C))
+#define GPIO_PORTA_AHB_AFSEL_R (*((volatile unsigned long *)0x40058420))
+#define GPIO_PORTA_AHB_DR2R_R (*((volatile unsigned long *)0x40058500))
+#define GPIO_PORTA_AHB_DR4R_R (*((volatile unsigned long *)0x40058504))
+#define GPIO_PORTA_AHB_DR8R_R (*((volatile unsigned long *)0x40058508))
+#define GPIO_PORTA_AHB_ODR_R (*((volatile unsigned long *)0x4005850C))
+#define GPIO_PORTA_AHB_PUR_R (*((volatile unsigned long *)0x40058510))
+#define GPIO_PORTA_AHB_PDR_R (*((volatile unsigned long *)0x40058514))
+#define GPIO_PORTA_AHB_SLR_R (*((volatile unsigned long *)0x40058518))
+#define GPIO_PORTA_AHB_DEN_R (*((volatile unsigned long *)0x4005851C))
+#define GPIO_PORTA_AHB_LOCK_R (*((volatile unsigned long *)0x40058520))
+#define GPIO_PORTA_AHB_CR_R (*((volatile unsigned long *)0x40058524))
+#define GPIO_PORTA_AHB_AMSEL_R (*((volatile unsigned long *)0x40058528))
+#define GPIO_PORTA_AHB_PCTL_R (*((volatile unsigned long *)0x4005852C))
+#define GPIO_PORTA_AHB_ADCCTL_R (*((volatile unsigned long *)0x40058530))
+#define GPIO_PORTA_AHB_DMACTL_R (*((volatile unsigned long *)0x40058534))
+#define GPIO_PORTA_AHB_SI_R (*((volatile unsigned long *)0x40058538))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTB AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTB_AHB_DATA_BITS_R \
+ ((volatile unsigned long *)0x40059000)
+#define GPIO_PORTB_AHB_DATA_R (*((volatile unsigned long *)0x400593FC))
+#define GPIO_PORTB_AHB_DIR_R (*((volatile unsigned long *)0x40059400))
+#define GPIO_PORTB_AHB_IS_R (*((volatile unsigned long *)0x40059404))
+#define GPIO_PORTB_AHB_IBE_R (*((volatile unsigned long *)0x40059408))
+#define GPIO_PORTB_AHB_IEV_R (*((volatile unsigned long *)0x4005940C))
+#define GPIO_PORTB_AHB_IM_R (*((volatile unsigned long *)0x40059410))
+#define GPIO_PORTB_AHB_RIS_R (*((volatile unsigned long *)0x40059414))
+#define GPIO_PORTB_AHB_MIS_R (*((volatile unsigned long *)0x40059418))
+#define GPIO_PORTB_AHB_ICR_R (*((volatile unsigned long *)0x4005941C))
+#define GPIO_PORTB_AHB_AFSEL_R (*((volatile unsigned long *)0x40059420))
+#define GPIO_PORTB_AHB_DR2R_R (*((volatile unsigned long *)0x40059500))
+#define GPIO_PORTB_AHB_DR4R_R (*((volatile unsigned long *)0x40059504))
+#define GPIO_PORTB_AHB_DR8R_R (*((volatile unsigned long *)0x40059508))
+#define GPIO_PORTB_AHB_ODR_R (*((volatile unsigned long *)0x4005950C))
+#define GPIO_PORTB_AHB_PUR_R (*((volatile unsigned long *)0x40059510))
+#define GPIO_PORTB_AHB_PDR_R (*((volatile unsigned long *)0x40059514))
+#define GPIO_PORTB_AHB_SLR_R (*((volatile unsigned long *)0x40059518))
+#define GPIO_PORTB_AHB_DEN_R (*((volatile unsigned long *)0x4005951C))
+#define GPIO_PORTB_AHB_LOCK_R (*((volatile unsigned long *)0x40059520))
+#define GPIO_PORTB_AHB_CR_R (*((volatile unsigned long *)0x40059524))
+#define GPIO_PORTB_AHB_AMSEL_R (*((volatile unsigned long *)0x40059528))
+#define GPIO_PORTB_AHB_PCTL_R (*((volatile unsigned long *)0x4005952C))
+#define GPIO_PORTB_AHB_ADCCTL_R (*((volatile unsigned long *)0x40059530))
+#define GPIO_PORTB_AHB_DMACTL_R (*((volatile unsigned long *)0x40059534))
+#define GPIO_PORTB_AHB_SI_R (*((volatile unsigned long *)0x40059538))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTC AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTC_AHB_DATA_BITS_R \
+ ((volatile unsigned long *)0x4005A000)
+#define GPIO_PORTC_AHB_DATA_R (*((volatile unsigned long *)0x4005A3FC))
+#define GPIO_PORTC_AHB_DIR_R (*((volatile unsigned long *)0x4005A400))
+#define GPIO_PORTC_AHB_IS_R (*((volatile unsigned long *)0x4005A404))
+#define GPIO_PORTC_AHB_IBE_R (*((volatile unsigned long *)0x4005A408))
+#define GPIO_PORTC_AHB_IEV_R (*((volatile unsigned long *)0x4005A40C))
+#define GPIO_PORTC_AHB_IM_R (*((volatile unsigned long *)0x4005A410))
+#define GPIO_PORTC_AHB_RIS_R (*((volatile unsigned long *)0x4005A414))
+#define GPIO_PORTC_AHB_MIS_R (*((volatile unsigned long *)0x4005A418))
+#define GPIO_PORTC_AHB_ICR_R (*((volatile unsigned long *)0x4005A41C))
+#define GPIO_PORTC_AHB_AFSEL_R (*((volatile unsigned long *)0x4005A420))
+#define GPIO_PORTC_AHB_DR2R_R (*((volatile unsigned long *)0x4005A500))
+#define GPIO_PORTC_AHB_DR4R_R (*((volatile unsigned long *)0x4005A504))
+#define GPIO_PORTC_AHB_DR8R_R (*((volatile unsigned long *)0x4005A508))
+#define GPIO_PORTC_AHB_ODR_R (*((volatile unsigned long *)0x4005A50C))
+#define GPIO_PORTC_AHB_PUR_R (*((volatile unsigned long *)0x4005A510))
+#define GPIO_PORTC_AHB_PDR_R (*((volatile unsigned long *)0x4005A514))
+#define GPIO_PORTC_AHB_SLR_R (*((volatile unsigned long *)0x4005A518))
+#define GPIO_PORTC_AHB_DEN_R (*((volatile unsigned long *)0x4005A51C))
+#define GPIO_PORTC_AHB_LOCK_R (*((volatile unsigned long *)0x4005A520))
+#define GPIO_PORTC_AHB_CR_R (*((volatile unsigned long *)0x4005A524))
+#define GPIO_PORTC_AHB_AMSEL_R (*((volatile unsigned long *)0x4005A528))
+#define GPIO_PORTC_AHB_PCTL_R (*((volatile unsigned long *)0x4005A52C))
+#define GPIO_PORTC_AHB_ADCCTL_R (*((volatile unsigned long *)0x4005A530))
+#define GPIO_PORTC_AHB_DMACTL_R (*((volatile unsigned long *)0x4005A534))
+#define GPIO_PORTC_AHB_SI_R (*((volatile unsigned long *)0x4005A538))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTD AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTD_AHB_DATA_BITS_R \
+ ((volatile unsigned long *)0x4005B000)
+#define GPIO_PORTD_AHB_DATA_R (*((volatile unsigned long *)0x4005B3FC))
+#define GPIO_PORTD_AHB_DIR_R (*((volatile unsigned long *)0x4005B400))
+#define GPIO_PORTD_AHB_IS_R (*((volatile unsigned long *)0x4005B404))
+#define GPIO_PORTD_AHB_IBE_R (*((volatile unsigned long *)0x4005B408))
+#define GPIO_PORTD_AHB_IEV_R (*((volatile unsigned long *)0x4005B40C))
+#define GPIO_PORTD_AHB_IM_R (*((volatile unsigned long *)0x4005B410))
+#define GPIO_PORTD_AHB_RIS_R (*((volatile unsigned long *)0x4005B414))
+#define GPIO_PORTD_AHB_MIS_R (*((volatile unsigned long *)0x4005B418))
+#define GPIO_PORTD_AHB_ICR_R (*((volatile unsigned long *)0x4005B41C))
+#define GPIO_PORTD_AHB_AFSEL_R (*((volatile unsigned long *)0x4005B420))
+#define GPIO_PORTD_AHB_DR2R_R (*((volatile unsigned long *)0x4005B500))
+#define GPIO_PORTD_AHB_DR4R_R (*((volatile unsigned long *)0x4005B504))
+#define GPIO_PORTD_AHB_DR8R_R (*((volatile unsigned long *)0x4005B508))
+#define GPIO_PORTD_AHB_ODR_R (*((volatile unsigned long *)0x4005B50C))
+#define GPIO_PORTD_AHB_PUR_R (*((volatile unsigned long *)0x4005B510))
+#define GPIO_PORTD_AHB_PDR_R (*((volatile unsigned long *)0x4005B514))
+#define GPIO_PORTD_AHB_SLR_R (*((volatile unsigned long *)0x4005B518))
+#define GPIO_PORTD_AHB_DEN_R (*((volatile unsigned long *)0x4005B51C))
+#define GPIO_PORTD_AHB_LOCK_R (*((volatile unsigned long *)0x4005B520))
+#define GPIO_PORTD_AHB_CR_R (*((volatile unsigned long *)0x4005B524))
+#define GPIO_PORTD_AHB_AMSEL_R (*((volatile unsigned long *)0x4005B528))
+#define GPIO_PORTD_AHB_PCTL_R (*((volatile unsigned long *)0x4005B52C))
+#define GPIO_PORTD_AHB_ADCCTL_R (*((volatile unsigned long *)0x4005B530))
+#define GPIO_PORTD_AHB_DMACTL_R (*((volatile unsigned long *)0x4005B534))
+#define GPIO_PORTD_AHB_SI_R (*((volatile unsigned long *)0x4005B538))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTE AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTE_AHB_DATA_BITS_R \
+ ((volatile unsigned long *)0x4005C000)
+#define GPIO_PORTE_AHB_DATA_R (*((volatile unsigned long *)0x4005C3FC))
+#define GPIO_PORTE_AHB_DIR_R (*((volatile unsigned long *)0x4005C400))
+#define GPIO_PORTE_AHB_IS_R (*((volatile unsigned long *)0x4005C404))
+#define GPIO_PORTE_AHB_IBE_R (*((volatile unsigned long *)0x4005C408))
+#define GPIO_PORTE_AHB_IEV_R (*((volatile unsigned long *)0x4005C40C))
+#define GPIO_PORTE_AHB_IM_R (*((volatile unsigned long *)0x4005C410))
+#define GPIO_PORTE_AHB_RIS_R (*((volatile unsigned long *)0x4005C414))
+#define GPIO_PORTE_AHB_MIS_R (*((volatile unsigned long *)0x4005C418))
+#define GPIO_PORTE_AHB_ICR_R (*((volatile unsigned long *)0x4005C41C))
+#define GPIO_PORTE_AHB_AFSEL_R (*((volatile unsigned long *)0x4005C420))
+#define GPIO_PORTE_AHB_DR2R_R (*((volatile unsigned long *)0x4005C500))
+#define GPIO_PORTE_AHB_DR4R_R (*((volatile unsigned long *)0x4005C504))
+#define GPIO_PORTE_AHB_DR8R_R (*((volatile unsigned long *)0x4005C508))
+#define GPIO_PORTE_AHB_ODR_R (*((volatile unsigned long *)0x4005C50C))
+#define GPIO_PORTE_AHB_PUR_R (*((volatile unsigned long *)0x4005C510))
+#define GPIO_PORTE_AHB_PDR_R (*((volatile unsigned long *)0x4005C514))
+#define GPIO_PORTE_AHB_SLR_R (*((volatile unsigned long *)0x4005C518))
+#define GPIO_PORTE_AHB_DEN_R (*((volatile unsigned long *)0x4005C51C))
+#define GPIO_PORTE_AHB_LOCK_R (*((volatile unsigned long *)0x4005C520))
+#define GPIO_PORTE_AHB_CR_R (*((volatile unsigned long *)0x4005C524))
+#define GPIO_PORTE_AHB_AMSEL_R (*((volatile unsigned long *)0x4005C528))
+#define GPIO_PORTE_AHB_PCTL_R (*((volatile unsigned long *)0x4005C52C))
+#define GPIO_PORTE_AHB_ADCCTL_R (*((volatile unsigned long *)0x4005C530))
+#define GPIO_PORTE_AHB_DMACTL_R (*((volatile unsigned long *)0x4005C534))
+#define GPIO_PORTE_AHB_SI_R (*((volatile unsigned long *)0x4005C538))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTF AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTF_AHB_DATA_BITS_R \
+ ((volatile unsigned long *)0x4005D000)
+#define GPIO_PORTF_AHB_DATA_R (*((volatile unsigned long *)0x4005D3FC))
+#define GPIO_PORTF_AHB_DIR_R (*((volatile unsigned long *)0x4005D400))
+#define GPIO_PORTF_AHB_IS_R (*((volatile unsigned long *)0x4005D404))
+#define GPIO_PORTF_AHB_IBE_R (*((volatile unsigned long *)0x4005D408))
+#define GPIO_PORTF_AHB_IEV_R (*((volatile unsigned long *)0x4005D40C))
+#define GPIO_PORTF_AHB_IM_R (*((volatile unsigned long *)0x4005D410))
+#define GPIO_PORTF_AHB_RIS_R (*((volatile unsigned long *)0x4005D414))
+#define GPIO_PORTF_AHB_MIS_R (*((volatile unsigned long *)0x4005D418))
+#define GPIO_PORTF_AHB_ICR_R (*((volatile unsigned long *)0x4005D41C))
+#define GPIO_PORTF_AHB_AFSEL_R (*((volatile unsigned long *)0x4005D420))
+#define GPIO_PORTF_AHB_DR2R_R (*((volatile unsigned long *)0x4005D500))
+#define GPIO_PORTF_AHB_DR4R_R (*((volatile unsigned long *)0x4005D504))
+#define GPIO_PORTF_AHB_DR8R_R (*((volatile unsigned long *)0x4005D508))
+#define GPIO_PORTF_AHB_ODR_R (*((volatile unsigned long *)0x4005D50C))
+#define GPIO_PORTF_AHB_PUR_R (*((volatile unsigned long *)0x4005D510))
+#define GPIO_PORTF_AHB_PDR_R (*((volatile unsigned long *)0x4005D514))
+#define GPIO_PORTF_AHB_SLR_R (*((volatile unsigned long *)0x4005D518))
+#define GPIO_PORTF_AHB_DEN_R (*((volatile unsigned long *)0x4005D51C))
+#define GPIO_PORTF_AHB_LOCK_R (*((volatile unsigned long *)0x4005D520))
+#define GPIO_PORTF_AHB_CR_R (*((volatile unsigned long *)0x4005D524))
+#define GPIO_PORTF_AHB_AMSEL_R (*((volatile unsigned long *)0x4005D528))
+#define GPIO_PORTF_AHB_PCTL_R (*((volatile unsigned long *)0x4005D52C))
+#define GPIO_PORTF_AHB_ADCCTL_R (*((volatile unsigned long *)0x4005D530))
+#define GPIO_PORTF_AHB_DMACTL_R (*((volatile unsigned long *)0x4005D534))
+#define GPIO_PORTF_AHB_SI_R (*((volatile unsigned long *)0x4005D538))
+
+//*****************************************************************************
+//
+// EEPROM registers (EEPROM)
+//
+//*****************************************************************************
+#define EEPROM_EESIZE_R (*((volatile unsigned long *)0x400AF000))
+#define EEPROM_EEBLOCK_R (*((volatile unsigned long *)0x400AF004))
+#define EEPROM_EEOFFSET_R (*((volatile unsigned long *)0x400AF008))
+#define EEPROM_EERDWR_R (*((volatile unsigned long *)0x400AF010))
+#define EEPROM_EERDWRINC_R (*((volatile unsigned long *)0x400AF014))
+#define EEPROM_EEDONE_R (*((volatile unsigned long *)0x400AF018))
+#define EEPROM_EESUPP_R (*((volatile unsigned long *)0x400AF01C))
+#define EEPROM_EEUNLOCK_R (*((volatile unsigned long *)0x400AF020))
+#define EEPROM_EEPROT_R (*((volatile unsigned long *)0x400AF030))
+#define EEPROM_EEPASS0_R (*((volatile unsigned long *)0x400AF034))
+#define EEPROM_EEPASS1_R (*((volatile unsigned long *)0x400AF038))
+#define EEPROM_EEPASS2_R (*((volatile unsigned long *)0x400AF03C))
+#define EEPROM_EEINT_R (*((volatile unsigned long *)0x400AF040))
+#define EEPROM_EEHIDE_R (*((volatile unsigned long *)0x400AF050))
+#define EEPROM_EEDBGME_R (*((volatile unsigned long *)0x400AF080))
+#define EEPROM_PP_R (*((volatile unsigned long *)0x400AFFC0))
+
+//*****************************************************************************
+//
+// System Exception Module registers (SYSEXC)
+//
+//*****************************************************************************
+#define SYSEXC_RIS_R (*((volatile unsigned long *)0x400F9000))
+#define SYSEXC_IM_R (*((volatile unsigned long *)0x400F9004))
+#define SYSEXC_MIS_R (*((volatile unsigned long *)0x400F9008))
+#define SYSEXC_IC_R (*((volatile unsigned long *)0x400F900C))
+
+//*****************************************************************************
+//
+// Hibernation module registers (HIB)
+//
+//*****************************************************************************
+#define HIB_RTCC_R (*((volatile unsigned long *)0x400FC000))
+#define HIB_RTCM0_R (*((volatile unsigned long *)0x400FC004))
+#define HIB_RTCLD_R (*((volatile unsigned long *)0x400FC00C))
+#define HIB_CTL_R (*((volatile unsigned long *)0x400FC010))
+#define HIB_IM_R (*((volatile unsigned long *)0x400FC014))
+#define HIB_RIS_R (*((volatile unsigned long *)0x400FC018))
+#define HIB_MIS_R (*((volatile unsigned long *)0x400FC01C))
+#define HIB_IC_R (*((volatile unsigned long *)0x400FC020))
+#define HIB_RTCT_R (*((volatile unsigned long *)0x400FC024))
+#define HIB_RTCSS_R (*((volatile unsigned long *)0x400FC028))
+#define HIB_DATA_R (*((volatile unsigned long *)0x400FC030))
+
+//*****************************************************************************
+//
+// FLASH registers (FLASH CTRL)
+//
+//*****************************************************************************
+#define FLASH_FMA_R (*((volatile unsigned long *)0x400FD000))
+#define FLASH_FMD_R (*((volatile unsigned long *)0x400FD004))
+#define FLASH_FMC_R (*((volatile unsigned long *)0x400FD008))
+#define FLASH_FCRIS_R (*((volatile unsigned long *)0x400FD00C))
+#define FLASH_FCIM_R (*((volatile unsigned long *)0x400FD010))
+#define FLASH_FCMISC_R (*((volatile unsigned long *)0x400FD014))
+#define FLASH_FMC2_R (*((volatile unsigned long *)0x400FD020))
+#define FLASH_FWBVAL_R (*((volatile unsigned long *)0x400FD030))
+#define FLASH_FWBN_R (*((volatile unsigned long *)0x400FD100))
+#define FLASH_FSIZE_R (*((volatile unsigned long *)0x400FDFC0))
+#define FLASH_SSIZE_R (*((volatile unsigned long *)0x400FDFC4))
+#define FLASH_ROMSWMAP_R (*((volatile unsigned long *)0x400FDFCC))
+#define FLASH_RMCTL_R (*((volatile unsigned long *)0x400FE0F0))
+#define FLASH_BOOTCFG_R (*((volatile unsigned long *)0x400FE1D0))
+#define FLASH_USERREG0_R (*((volatile unsigned long *)0x400FE1E0))
+#define FLASH_USERREG1_R (*((volatile unsigned long *)0x400FE1E4))
+#define FLASH_USERREG2_R (*((volatile unsigned long *)0x400FE1E8))
+#define FLASH_USERREG3_R (*((volatile unsigned long *)0x400FE1EC))
+#define FLASH_FMPRE0_R (*((volatile unsigned long *)0x400FE200))
+#define FLASH_FMPRE1_R (*((volatile unsigned long *)0x400FE204))
+#define FLASH_FMPRE2_R (*((volatile unsigned long *)0x400FE208))
+#define FLASH_FMPRE3_R (*((volatile unsigned long *)0x400FE20C))
+#define FLASH_FMPPE0_R (*((volatile unsigned long *)0x400FE400))
+#define FLASH_FMPPE1_R (*((volatile unsigned long *)0x400FE404))
+#define FLASH_FMPPE2_R (*((volatile unsigned long *)0x400FE408))
+#define FLASH_FMPPE3_R (*((volatile unsigned long *)0x400FE40C))
+
+//*****************************************************************************
+//
+// System Control registers (SYSCTL)
+//
+//*****************************************************************************
+#define SYSCTL_DID0_R (*((volatile unsigned long *)0x400FE000))
+#define SYSCTL_DID1_R (*((volatile unsigned long *)0x400FE004))
+#define SYSCTL_DC0_R (*((volatile unsigned long *)0x400FE008))
+#define SYSCTL_DC1_R (*((volatile unsigned long *)0x400FE010))
+#define SYSCTL_DC2_R (*((volatile unsigned long *)0x400FE014))
+#define SYSCTL_DC3_R (*((volatile unsigned long *)0x400FE018))
+#define SYSCTL_DC4_R (*((volatile unsigned long *)0x400FE01C))
+#define SYSCTL_DC5_R (*((volatile unsigned long *)0x400FE020))
+#define SYSCTL_DC6_R (*((volatile unsigned long *)0x400FE024))
+#define SYSCTL_DC7_R (*((volatile unsigned long *)0x400FE028))
+#define SYSCTL_DC8_R (*((volatile unsigned long *)0x400FE02C))
+#define SYSCTL_PBORCTL_R (*((volatile unsigned long *)0x400FE030))
+#define SYSCTL_SRCR0_R (*((volatile unsigned long *)0x400FE040))
+#define SYSCTL_SRCR1_R (*((volatile unsigned long *)0x400FE044))
+#define SYSCTL_SRCR2_R (*((volatile unsigned long *)0x400FE048))
+#define SYSCTL_RIS_R (*((volatile unsigned long *)0x400FE050))
+#define SYSCTL_IMC_R (*((volatile unsigned long *)0x400FE054))
+#define SYSCTL_MISC_R (*((volatile unsigned long *)0x400FE058))
+#define SYSCTL_RESC_R (*((volatile unsigned long *)0x400FE05C))
+#define SYSCTL_RCC_R (*((volatile unsigned long *)0x400FE060))
+#define SYSCTL_GPIOHBCTL_R (*((volatile unsigned long *)0x400FE06C))
+#define SYSCTL_RCC2_R (*((volatile unsigned long *)0x400FE070))
+#define SYSCTL_MOSCCTL_R (*((volatile unsigned long *)0x400FE07C))
+#define SYSCTL_RCGC0_R (*((volatile unsigned long *)0x400FE100))
+#define SYSCTL_RCGC1_R (*((volatile unsigned long *)0x400FE104))
+#define SYSCTL_RCGC2_R (*((volatile unsigned long *)0x400FE108))
+#define SYSCTL_SCGC0_R (*((volatile unsigned long *)0x400FE110))
+#define SYSCTL_SCGC1_R (*((volatile unsigned long *)0x400FE114))
+#define SYSCTL_SCGC2_R (*((volatile unsigned long *)0x400FE118))
+#define SYSCTL_DCGC0_R (*((volatile unsigned long *)0x400FE120))
+#define SYSCTL_DCGC1_R (*((volatile unsigned long *)0x400FE124))
+#define SYSCTL_DCGC2_R (*((volatile unsigned long *)0x400FE128))
+#define SYSCTL_DSLPCLKCFG_R (*((volatile unsigned long *)0x400FE144))
+#define SYSCTL_SYSPROP_R (*((volatile unsigned long *)0x400FE14C))
+#define SYSCTL_PIOSCCAL_R (*((volatile unsigned long *)0x400FE150))
+#define SYSCTL_PIOSCSTAT_R (*((volatile unsigned long *)0x400FE154))
+#define SYSCTL_PLLFREQ0_R (*((volatile unsigned long *)0x400FE160))
+#define SYSCTL_PLLFREQ1_R (*((volatile unsigned long *)0x400FE164))
+#define SYSCTL_PLLSTAT_R (*((volatile unsigned long *)0x400FE168))
+#define SYSCTL_DC9_R (*((volatile unsigned long *)0x400FE190))
+#define SYSCTL_NVMSTAT_R (*((volatile unsigned long *)0x400FE1A0))
+#define SYSCTL_PPWD_R (*((volatile unsigned long *)0x400FE300))
+#define SYSCTL_PPTIMER_R (*((volatile unsigned long *)0x400FE304))
+#define SYSCTL_PPGPIO_R (*((volatile unsigned long *)0x400FE308))
+#define SYSCTL_PPDMA_R (*((volatile unsigned long *)0x400FE30C))
+#define SYSCTL_PPHIB_R (*((volatile unsigned long *)0x400FE314))
+#define SYSCTL_PPUART_R (*((volatile unsigned long *)0x400FE318))
+#define SYSCTL_PPSSI_R (*((volatile unsigned long *)0x400FE31C))
+#define SYSCTL_PPI2C_R (*((volatile unsigned long *)0x400FE320))
+#define SYSCTL_PPUSB_R (*((volatile unsigned long *)0x400FE328))
+#define SYSCTL_PPCAN_R (*((volatile unsigned long *)0x400FE334))
+#define SYSCTL_PPADC_R (*((volatile unsigned long *)0x400FE338))
+#define SYSCTL_PPACMP_R (*((volatile unsigned long *)0x400FE33C))
+#define SYSCTL_PPPWM_R (*((volatile unsigned long *)0x400FE340))
+#define SYSCTL_PPQEI_R (*((volatile unsigned long *)0x400FE344))
+#define SYSCTL_PPEEPROM_R (*((volatile unsigned long *)0x400FE358))
+#define SYSCTL_PPWTIMER_R (*((volatile unsigned long *)0x400FE35C))
+#define SYSCTL_SRWD_R (*((volatile unsigned long *)0x400FE500))
+#define SYSCTL_SRTIMER_R (*((volatile unsigned long *)0x400FE504))
+#define SYSCTL_SRGPIO_R (*((volatile unsigned long *)0x400FE508))
+#define SYSCTL_SRDMA_R (*((volatile unsigned long *)0x400FE50C))
+#define SYSCTL_SRHIB_R (*((volatile unsigned long *)0x400FE514))
+#define SYSCTL_SRUART_R (*((volatile unsigned long *)0x400FE518))
+#define SYSCTL_SRSSI_R (*((volatile unsigned long *)0x400FE51C))
+#define SYSCTL_SRI2C_R (*((volatile unsigned long *)0x400FE520))
+#define SYSCTL_SRUSB_R (*((volatile unsigned long *)0x400FE528))
+#define SYSCTL_SRCAN_R (*((volatile unsigned long *)0x400FE534))
+#define SYSCTL_SRADC_R (*((volatile unsigned long *)0x400FE538))
+#define SYSCTL_SRACMP_R (*((volatile unsigned long *)0x400FE53C))
+#define SYSCTL_SREEPROM_R (*((volatile unsigned long *)0x400FE558))
+#define SYSCTL_SRWTIMER_R (*((volatile unsigned long *)0x400FE55C))
+#define SYSCTL_RCGCWD_R (*((volatile unsigned long *)0x400FE600))
+#define SYSCTL_RCGCTIMER_R (*((volatile unsigned long *)0x400FE604))
+#define SYSCTL_RCGCGPIO_R (*((volatile unsigned long *)0x400FE608))
+#define SYSCTL_RCGCDMA_R (*((volatile unsigned long *)0x400FE60C))
+#define SYSCTL_RCGCHIB_R (*((volatile unsigned long *)0x400FE614))
+#define SYSCTL_RCGCUART_R (*((volatile unsigned long *)0x400FE618))
+#define SYSCTL_RCGCSSI_R (*((volatile unsigned long *)0x400FE61C))
+#define SYSCTL_RCGCI2C_R (*((volatile unsigned long *)0x400FE620))
+#define SYSCTL_RCGCUSB_R (*((volatile unsigned long *)0x400FE628))
+#define SYSCTL_RCGCCAN_R (*((volatile unsigned long *)0x400FE634))
+#define SYSCTL_RCGCADC_R (*((volatile unsigned long *)0x400FE638))
+#define SYSCTL_RCGCACMP_R (*((volatile unsigned long *)0x400FE63C))
+#define SYSCTL_RCGCEEPROM_R (*((volatile unsigned long *)0x400FE658))
+#define SYSCTL_RCGCWTIMER_R (*((volatile unsigned long *)0x400FE65C))
+#define SYSCTL_SCGCWD_R (*((volatile unsigned long *)0x400FE700))
+#define SYSCTL_SCGCTIMER_R (*((volatile unsigned long *)0x400FE704))
+#define SYSCTL_SCGCGPIO_R (*((volatile unsigned long *)0x400FE708))
+#define SYSCTL_SCGCDMA_R (*((volatile unsigned long *)0x400FE70C))
+#define SYSCTL_SCGCHIB_R (*((volatile unsigned long *)0x400FE714))
+#define SYSCTL_SCGCUART_R (*((volatile unsigned long *)0x400FE718))
+#define SYSCTL_SCGCSSI_R (*((volatile unsigned long *)0x400FE71C))
+#define SYSCTL_SCGCI2C_R (*((volatile unsigned long *)0x400FE720))
+#define SYSCTL_SCGCUSB_R (*((volatile unsigned long *)0x400FE728))
+#define SYSCTL_SCGCCAN_R (*((volatile unsigned long *)0x400FE734))
+#define SYSCTL_SCGCADC_R (*((volatile unsigned long *)0x400FE738))
+#define SYSCTL_SCGCACMP_R (*((volatile unsigned long *)0x400FE73C))
+#define SYSCTL_SCGCEEPROM_R (*((volatile unsigned long *)0x400FE758))
+#define SYSCTL_SCGCWTIMER_R (*((volatile unsigned long *)0x400FE75C))
+#define SYSCTL_DCGCWD_R (*((volatile unsigned long *)0x400FE800))
+#define SYSCTL_DCGCTIMER_R (*((volatile unsigned long *)0x400FE804))
+#define SYSCTL_DCGCGPIO_R (*((volatile unsigned long *)0x400FE808))
+#define SYSCTL_DCGCDMA_R (*((volatile unsigned long *)0x400FE80C))
+#define SYSCTL_DCGCHIB_R (*((volatile unsigned long *)0x400FE814))
+#define SYSCTL_DCGCUART_R (*((volatile unsigned long *)0x400FE818))
+#define SYSCTL_DCGCSSI_R (*((volatile unsigned long *)0x400FE81C))
+#define SYSCTL_DCGCI2C_R (*((volatile unsigned long *)0x400FE820))
+#define SYSCTL_DCGCUSB_R (*((volatile unsigned long *)0x400FE828))
+#define SYSCTL_DCGCCAN_R (*((volatile unsigned long *)0x400FE834))
+#define SYSCTL_DCGCADC_R (*((volatile unsigned long *)0x400FE838))
+#define SYSCTL_DCGCACMP_R (*((volatile unsigned long *)0x400FE83C))
+#define SYSCTL_DCGCEEPROM_R (*((volatile unsigned long *)0x400FE858))
+#define SYSCTL_DCGCWTIMER_R (*((volatile unsigned long *)0x400FE85C))
+#define SYSCTL_PCWD_R (*((volatile unsigned long *)0x400FE900))
+#define SYSCTL_PCTIMER_R (*((volatile unsigned long *)0x400FE904))
+#define SYSCTL_PCGPIO_R (*((volatile unsigned long *)0x400FE908))
+#define SYSCTL_PCDMA_R (*((volatile unsigned long *)0x400FE90C))
+#define SYSCTL_PCHIB_R (*((volatile unsigned long *)0x400FE914))
+#define SYSCTL_PCUART_R (*((volatile unsigned long *)0x400FE918))
+#define SYSCTL_PCSSI_R (*((volatile unsigned long *)0x400FE91C))
+#define SYSCTL_PCI2C_R (*((volatile unsigned long *)0x400FE920))
+#define SYSCTL_PCUSB_R (*((volatile unsigned long *)0x400FE928))
+#define SYSCTL_PCCAN_R (*((volatile unsigned long *)0x400FE934))
+#define SYSCTL_PCADC_R (*((volatile unsigned long *)0x400FE938))
+#define SYSCTL_PCACMP_R (*((volatile unsigned long *)0x400FE93C))
+#define SYSCTL_PCEEPROM_R (*((volatile unsigned long *)0x400FE958))
+#define SYSCTL_PCWTIMER_R (*((volatile unsigned long *)0x400FE95C))
+#define SYSCTL_PRWD_R (*((volatile unsigned long *)0x400FEA00))
+#define SYSCTL_PRTIMER_R (*((volatile unsigned long *)0x400FEA04))
+#define SYSCTL_PRGPIO_R (*((volatile unsigned long *)0x400FEA08))
+#define SYSCTL_PRDMA_R (*((volatile unsigned long *)0x400FEA0C))
+#define SYSCTL_PRHIB_R (*((volatile unsigned long *)0x400FEA14))
+#define SYSCTL_PRUART_R (*((volatile unsigned long *)0x400FEA18))
+#define SYSCTL_PRSSI_R (*((volatile unsigned long *)0x400FEA1C))
+#define SYSCTL_PRI2C_R (*((volatile unsigned long *)0x400FEA20))
+#define SYSCTL_PRUSB_R (*((volatile unsigned long *)0x400FEA28))
+#define SYSCTL_PRCAN_R (*((volatile unsigned long *)0x400FEA34))
+#define SYSCTL_PRADC_R (*((volatile unsigned long *)0x400FEA38))
+#define SYSCTL_PRACMP_R (*((volatile unsigned long *)0x400FEA3C))
+#define SYSCTL_PREEPROM_R (*((volatile unsigned long *)0x400FEA58))
+#define SYSCTL_PRWTIMER_R (*((volatile unsigned long *)0x400FEA5C))
+
+//*****************************************************************************
+//
+// Micro Direct Memory Access registers (UDMA)
+//
+//*****************************************************************************
+#define UDMA_STAT_R (*((volatile unsigned long *)0x400FF000))
+#define UDMA_CFG_R (*((volatile unsigned long *)0x400FF004))
+#define UDMA_CTLBASE_R (*((volatile unsigned long *)0x400FF008))
+#define UDMA_ALTBASE_R (*((volatile unsigned long *)0x400FF00C))
+#define UDMA_WAITSTAT_R (*((volatile unsigned long *)0x400FF010))
+#define UDMA_SWREQ_R (*((volatile unsigned long *)0x400FF014))
+#define UDMA_USEBURSTSET_R (*((volatile unsigned long *)0x400FF018))
+#define UDMA_USEBURSTCLR_R (*((volatile unsigned long *)0x400FF01C))
+#define UDMA_REQMASKSET_R (*((volatile unsigned long *)0x400FF020))
+#define UDMA_REQMASKCLR_R (*((volatile unsigned long *)0x400FF024))
+#define UDMA_ENASET_R (*((volatile unsigned long *)0x400FF028))
+#define UDMA_ENACLR_R (*((volatile unsigned long *)0x400FF02C))
+#define UDMA_ALTSET_R (*((volatile unsigned long *)0x400FF030))
+#define UDMA_ALTCLR_R (*((volatile unsigned long *)0x400FF034))
+#define UDMA_PRIOSET_R (*((volatile unsigned long *)0x400FF038))
+#define UDMA_PRIOCLR_R (*((volatile unsigned long *)0x400FF03C))
+#define UDMA_ERRCLR_R (*((volatile unsigned long *)0x400FF04C))
+#define UDMA_CHASGN_R (*((volatile unsigned long *)0x400FF500))
+#define UDMA_CHIS_R (*((volatile unsigned long *)0x400FF504))
+#define UDMA_CHMAP0_R (*((volatile unsigned long *)0x400FF510))
+#define UDMA_CHMAP1_R (*((volatile unsigned long *)0x400FF514))
+#define UDMA_CHMAP2_R (*((volatile unsigned long *)0x400FF518))
+#define UDMA_CHMAP3_R (*((volatile unsigned long *)0x400FF51C))
+
+//*****************************************************************************
+//
+// Micro Direct Memory Access (uDMA) offsets (UDMA)
+//
+//*****************************************************************************
+#define UDMA_SRCENDP 0x00000000 // DMA Channel Source Address End
+ // Pointer
+#define UDMA_DSTENDP 0x00000004 // DMA Channel Destination Address
+ // End Pointer
+#define UDMA_CHCTL 0x00000008 // DMA Channel Control Word
+
+//*****************************************************************************
+//
+// NVIC registers (NVIC)
+//
+//*****************************************************************************
+#define NVIC_INT_TYPE_R (*((volatile unsigned long *)0xE000E004))
+#define NVIC_ACTLR_R (*((volatile unsigned long *)0xE000E008))
+#define NVIC_ST_CTRL_R (*((volatile unsigned long *)0xE000E010))
+#define NVIC_ST_RELOAD_R (*((volatile unsigned long *)0xE000E014))
+#define NVIC_ST_CURRENT_R (*((volatile unsigned long *)0xE000E018))
+#define NVIC_ST_CAL_R (*((volatile unsigned long *)0xE000E01C))
+#define NVIC_EN0_R (*((volatile unsigned long *)0xE000E100))
+#define NVIC_EN1_R (*((volatile unsigned long *)0xE000E104))
+#define NVIC_EN2_R (*((volatile unsigned long *)0xE000E108))
+#define NVIC_EN3_R (*((volatile unsigned long *)0xE000E10C))
+#define NVIC_EN4_R (*((volatile unsigned long *)0xE000E110))
+#define NVIC_DIS0_R (*((volatile unsigned long *)0xE000E180))
+#define NVIC_DIS1_R (*((volatile unsigned long *)0xE000E184))
+#define NVIC_DIS2_R (*((volatile unsigned long *)0xE000E188))
+#define NVIC_DIS3_R (*((volatile unsigned long *)0xE000E18C))
+#define NVIC_DIS4_R (*((volatile unsigned long *)0xE000E190))
+#define NVIC_PEND0_R (*((volatile unsigned long *)0xE000E200))
+#define NVIC_PEND1_R (*((volatile unsigned long *)0xE000E204))
+#define NVIC_PEND2_R (*((volatile unsigned long *)0xE000E208))
+#define NVIC_PEND3_R (*((volatile unsigned long *)0xE000E20C))
+#define NVIC_PEND4_R (*((volatile unsigned long *)0xE000E210))
+#define NVIC_UNPEND0_R (*((volatile unsigned long *)0xE000E280))
+#define NVIC_UNPEND1_R (*((volatile unsigned long *)0xE000E284))
+#define NVIC_UNPEND2_R (*((volatile unsigned long *)0xE000E288))
+#define NVIC_UNPEND3_R (*((volatile unsigned long *)0xE000E28C))
+#define NVIC_UNPEND4_R (*((volatile unsigned long *)0xE000E290))
+#define NVIC_ACTIVE0_R (*((volatile unsigned long *)0xE000E300))
+#define NVIC_ACTIVE1_R (*((volatile unsigned long *)0xE000E304))
+#define NVIC_ACTIVE2_R (*((volatile unsigned long *)0xE000E308))
+#define NVIC_ACTIVE3_R (*((volatile unsigned long *)0xE000E30C))
+#define NVIC_ACTIVE4_R (*((volatile unsigned long *)0xE000E310))
+#define NVIC_PRI0_R (*((volatile unsigned long *)0xE000E400))
+#define NVIC_PRI1_R (*((volatile unsigned long *)0xE000E404))
+#define NVIC_PRI2_R (*((volatile unsigned long *)0xE000E408))
+#define NVIC_PRI3_R (*((volatile unsigned long *)0xE000E40C))
+#define NVIC_PRI4_R (*((volatile unsigned long *)0xE000E410))
+#define NVIC_PRI5_R (*((volatile unsigned long *)0xE000E414))
+#define NVIC_PRI6_R (*((volatile unsigned long *)0xE000E418))
+#define NVIC_PRI7_R (*((volatile unsigned long *)0xE000E41C))
+#define NVIC_PRI8_R (*((volatile unsigned long *)0xE000E420))
+#define NVIC_PRI9_R (*((volatile unsigned long *)0xE000E424))
+#define NVIC_PRI10_R (*((volatile unsigned long *)0xE000E428))
+#define NVIC_PRI11_R (*((volatile unsigned long *)0xE000E42C))
+#define NVIC_PRI12_R (*((volatile unsigned long *)0xE000E430))
+#define NVIC_PRI13_R (*((volatile unsigned long *)0xE000E434))
+#define NVIC_PRI14_R (*((volatile unsigned long *)0xE000E438))
+#define NVIC_PRI15_R (*((volatile unsigned long *)0xE000E43C))
+#define NVIC_PRI16_R (*((volatile unsigned long *)0xE000E440))
+#define NVIC_PRI17_R (*((volatile unsigned long *)0xE000E444))
+#define NVIC_PRI18_R (*((volatile unsigned long *)0xE000E448))
+#define NVIC_PRI19_R (*((volatile unsigned long *)0xE000E44C))
+#define NVIC_PRI20_R (*((volatile unsigned long *)0xE000E450))
+#define NVIC_PRI21_R (*((volatile unsigned long *)0xE000E454))
+#define NVIC_PRI22_R (*((volatile unsigned long *)0xE000E458))
+#define NVIC_PRI23_R (*((volatile unsigned long *)0xE000E45C))
+#define NVIC_PRI24_R (*((volatile unsigned long *)0xE000E460))
+#define NVIC_PRI25_R (*((volatile unsigned long *)0xE000E464))
+#define NVIC_PRI26_R (*((volatile unsigned long *)0xE000E468))
+#define NVIC_PRI27_R (*((volatile unsigned long *)0xE000E46C))
+#define NVIC_PRI28_R (*((volatile unsigned long *)0xE000E470))
+#define NVIC_PRI29_R (*((volatile unsigned long *)0xE000E474))
+#define NVIC_PRI30_R (*((volatile unsigned long *)0xE000E478))
+#define NVIC_PRI31_R (*((volatile unsigned long *)0xE000E47C))
+#define NVIC_PRI32_R (*((volatile unsigned long *)0xE000E480))
+#define NVIC_PRI33_R (*((volatile unsigned long *)0xE000E484))
+#define NVIC_PRI34_R (*((volatile unsigned long *)0xE000E488))
+#define NVIC_CPUID_R (*((volatile unsigned long *)0xE000ED00))
+#define NVIC_INT_CTRL_R (*((volatile unsigned long *)0xE000ED04))
+#define NVIC_VTABLE_R (*((volatile unsigned long *)0xE000ED08))
+#define NVIC_APINT_R (*((volatile unsigned long *)0xE000ED0C))
+#define NVIC_SYS_CTRL_R (*((volatile unsigned long *)0xE000ED10))
+#define NVIC_CFG_CTRL_R (*((volatile unsigned long *)0xE000ED14))
+#define NVIC_SYS_PRI1_R (*((volatile unsigned long *)0xE000ED18))
+#define NVIC_SYS_PRI2_R (*((volatile unsigned long *)0xE000ED1C))
+#define NVIC_SYS_PRI3_R (*((volatile unsigned long *)0xE000ED20))
+#define NVIC_SYS_HND_CTRL_R (*((volatile unsigned long *)0xE000ED24))
+#define NVIC_FAULT_STAT_R (*((volatile unsigned long *)0xE000ED28))
+#define NVIC_HFAULT_STAT_R (*((volatile unsigned long *)0xE000ED2C))
+#define NVIC_DEBUG_STAT_R (*((volatile unsigned long *)0xE000ED30))
+#define NVIC_MM_ADDR_R (*((volatile unsigned long *)0xE000ED34))
+#define NVIC_FAULT_ADDR_R (*((volatile unsigned long *)0xE000ED38))
+#define NVIC_CPAC_R (*((volatile unsigned long *)0xE000ED88))
+#define NVIC_MPU_TYPE_R (*((volatile unsigned long *)0xE000ED90))
+#define NVIC_MPU_CTRL_R (*((volatile unsigned long *)0xE000ED94))
+#define NVIC_MPU_NUMBER_R (*((volatile unsigned long *)0xE000ED98))
+#define NVIC_MPU_BASE_R (*((volatile unsigned long *)0xE000ED9C))
+#define NVIC_MPU_ATTR_R (*((volatile unsigned long *)0xE000EDA0))
+#define NVIC_MPU_BASE1_R (*((volatile unsigned long *)0xE000EDA4))
+#define NVIC_MPU_ATTR1_R (*((volatile unsigned long *)0xE000EDA8))
+#define NVIC_MPU_BASE2_R (*((volatile unsigned long *)0xE000EDAC))
+#define NVIC_MPU_ATTR2_R (*((volatile unsigned long *)0xE000EDB0))
+#define NVIC_MPU_BASE3_R (*((volatile unsigned long *)0xE000EDB4))
+#define NVIC_MPU_ATTR3_R (*((volatile unsigned long *)0xE000EDB8))
+#define NVIC_DBG_CTRL_R (*((volatile unsigned long *)0xE000EDF0))
+#define NVIC_DBG_XFER_R (*((volatile unsigned long *)0xE000EDF4))
+#define NVIC_DBG_DATA_R (*((volatile unsigned long *)0xE000EDF8))
+#define NVIC_DBG_INT_R (*((volatile unsigned long *)0xE000EDFC))
+#define NVIC_SW_TRIG_R (*((volatile unsigned long *)0xE000EF00))
+#define NVIC_FPCC_R (*((volatile unsigned long *)0xE000EF34))
+#define NVIC_FPCA_R (*((volatile unsigned long *)0xE000EF38))
+#define NVIC_FPDSC_R (*((volatile unsigned long *)0xE000EF3C))
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOAD register.
+//
+//*****************************************************************************
+#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value
+#define WDT_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_VALUE register.
+//
+//*****************************************************************************
+#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value
+#define WDT_VALUE_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_CTL register.
+//
+//*****************************************************************************
+#define WDT_CTL_WRC 0x80000000 // Write Complete
+#define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type
+#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable
+#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_ICR register.
+//
+//*****************************************************************************
+#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear
+#define WDT_ICR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_RIS register.
+//
+//*****************************************************************************
+#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_MIS register.
+//
+//*****************************************************************************
+#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_TEST register.
+//
+//*****************************************************************************
+#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOCK register.
+//
+//*****************************************************************************
+#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock
+#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked
+#define WDT_LOCK_LOCKED 0x00000001 // Locked
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_IM register.
+//
+//*****************************************************************************
+#define GPIO_IM_GPIO_M 0x000000FF // GPIO Interrupt Mask Enable
+#define GPIO_IM_GPIO_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_RIS register.
+//
+//*****************************************************************************
+#define GPIO_RIS_GPIO_M 0x000000FF // GPIO Interrupt Raw Status
+#define GPIO_RIS_GPIO_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_MIS register.
+//
+//*****************************************************************************
+#define GPIO_MIS_GPIO_M 0x000000FF // GPIO Masked Interrupt Status
+#define GPIO_MIS_GPIO_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_ICR register.
+//
+//*****************************************************************************
+#define GPIO_ICR_GPIO_M 0x000000FF // GPIO Interrupt Clear
+#define GPIO_ICR_GPIO_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_LOCK register.
+//
+//*****************************************************************************
+#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock
+#define GPIO_LOCK_UNLOCKED 0x00000000 // The GPIOCR register is unlocked
+ // and may be modified
+#define GPIO_LOCK_LOCKED 0x00000001 // The GPIOCR register is locked
+ // and may not be modified
+#define GPIO_LOCK_KEY 0x4C4F434B // Unlocks the GPIO_CR register
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_SI register.
+//
+//*****************************************************************************
+#define GPIO_SI_SUM 0x00000001 // Summary Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port A.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PA7_M 0xF0000000 // PA7 mask
+#define GPIO_PCTL_PA7_I2C1SDA 0x30000000 // I2C1SDA on PA7
+#define GPIO_PCTL_PA6_M 0x0F000000 // PA6 mask
+#define GPIO_PCTL_PA6_I2C1SCL 0x03000000 // I2C1SCL on PA6
+#define GPIO_PCTL_PA5_M 0x00F00000 // PA5 mask
+#define GPIO_PCTL_PA5_SSI0TX 0x00200000 // SSI0TX on PA5
+#define GPIO_PCTL_PA4_M 0x000F0000 // PA4 mask
+#define GPIO_PCTL_PA4_SSI0RX 0x00020000 // SSI0RX on PA4
+#define GPIO_PCTL_PA3_M 0x0000F000 // PA3 mask
+#define GPIO_PCTL_PA3_SSI0FSS 0x00002000 // SSI0FSS on PA3
+#define GPIO_PCTL_PA2_M 0x00000F00 // PA2 mask
+#define GPIO_PCTL_PA2_SSI0CLK 0x00000200 // SSI0CLK on PA2
+#define GPIO_PCTL_PA1_M 0x000000F0 // PA1 mask
+#define GPIO_PCTL_PA1_U0TX 0x00000010 // U0TX on PA1
+#define GPIO_PCTL_PA0_M 0x0000000F // PA0 mask
+#define GPIO_PCTL_PA0_U0RX 0x00000001 // U0RX on PA0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port B.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PB7_M 0xF0000000 // PB7 mask
+#define GPIO_PCTL_PB7_SSI2TX 0x20000000 // SSI2TX on PB7
+#define GPIO_PCTL_PB7_T0CCP1 0x70000000 // T0CCP1 on PB7
+#define GPIO_PCTL_PB6_M 0x0F000000 // PB6 mask
+#define GPIO_PCTL_PB6_SSI2RX 0x02000000 // SSI2RX on PB6
+#define GPIO_PCTL_PB6_T0CCP0 0x07000000 // T0CCP0 on PB6
+#define GPIO_PCTL_PB5_M 0x00F00000 // PB5 mask
+#define GPIO_PCTL_PB5_SSI2FSS 0x00200000 // SSI2FSS on PB5
+#define GPIO_PCTL_PB5_T1CCP1 0x00700000 // T1CCP1 on PB5
+#define GPIO_PCTL_PB5_CAN0TX 0x00800000 // CAN0TX on PB5
+#define GPIO_PCTL_PB4_M 0x000F0000 // PB4 mask
+#define GPIO_PCTL_PB4_SSI2CLK 0x00020000 // SSI2CLK on PB4
+#define GPIO_PCTL_PB4_T1CCP0 0x00070000 // T1CCP0 on PB4
+#define GPIO_PCTL_PB4_CAN0RX 0x00080000 // CAN0RX on PB4
+#define GPIO_PCTL_PB3_M 0x0000F000 // PB3 mask
+#define GPIO_PCTL_PB3_I2C0SDA 0x00003000 // I2C0SDA on PB3
+#define GPIO_PCTL_PB3_T3CCP1 0x00007000 // T3CCP1 on PB3
+#define GPIO_PCTL_PB2_M 0x00000F00 // PB2 mask
+#define GPIO_PCTL_PB2_I2C0SCL 0x00000300 // I2C0SCL on PB2
+#define GPIO_PCTL_PB2_T3CCP0 0x00000700 // T3CCP0 on PB2
+#define GPIO_PCTL_PB1_M 0x000000F0 // PB1 mask
+#define GPIO_PCTL_PB1_U1TX 0x00000010 // U1TX on PB1
+#define GPIO_PCTL_PB1_T2CCP1 0x00000070 // T2CCP1 on PB1
+#define GPIO_PCTL_PB0_M 0x0000000F // PB0 mask
+#define GPIO_PCTL_PB0_U1RX 0x00000001 // U1RX on PB0
+#define GPIO_PCTL_PB0_T2CCP0 0x00000007 // T2CCP0 on PB0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port C.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PC7_M 0xF0000000 // PC7 mask
+#define GPIO_PCTL_PC7_U3TX 0x10000000 // U3TX on PC7
+#define GPIO_PCTL_PC7_WT1CCP1 0x70000000 // WT1CCP1 on PC7
+#define GPIO_PCTL_PC6_M 0x0F000000 // PC6 mask
+#define GPIO_PCTL_PC6_U3RX 0x01000000 // U3RX on PC6
+#define GPIO_PCTL_PC6_WT1CCP0 0x07000000 // WT1CCP0 on PC6
+#define GPIO_PCTL_PC5_M 0x00F00000 // PC5 mask
+#define GPIO_PCTL_PC5_U4TX 0x00100000 // U4TX on PC5
+#define GPIO_PCTL_PC5_U1TX 0x00200000 // U1TX on PC5
+#define GPIO_PCTL_PC5_WT0CCP1 0x00700000 // WT0CCP1 on PC5
+#define GPIO_PCTL_PC5_U1CTS 0x00800000 // U1CTS on PC5
+#define GPIO_PCTL_PC4_M 0x000F0000 // PC4 mask
+#define GPIO_PCTL_PC4_U4RX 0x00010000 // U4RX on PC4
+#define GPIO_PCTL_PC4_U1RX 0x00020000 // U1RX on PC4
+#define GPIO_PCTL_PC4_WT0CCP0 0x00070000 // WT0CCP0 on PC4
+#define GPIO_PCTL_PC4_U1RTS 0x00080000 // U1RTS on PC4
+#define GPIO_PCTL_PC3_M 0x0000F000 // PC3 mask
+#define GPIO_PCTL_PC3_TDO 0x00001000 // TDO on PC3
+#define GPIO_PCTL_PC3_T5CCP1 0x00007000 // T5CCP1 on PC3
+#define GPIO_PCTL_PC2_M 0x00000F00 // PC2 mask
+#define GPIO_PCTL_PC2_TDI 0x00000100 // TDI on PC2
+#define GPIO_PCTL_PC2_T5CCP0 0x00000700 // T5CCP0 on PC2
+#define GPIO_PCTL_PC1_M 0x000000F0 // PC1 mask
+#define GPIO_PCTL_PC1_TMS 0x00000010 // TMS on PC1
+#define GPIO_PCTL_PC1_T4CCP1 0x00000070 // T4CCP1 on PC1
+#define GPIO_PCTL_PC0_M 0x0000000F // PC0 mask
+#define GPIO_PCTL_PC0_TCK 0x00000001 // TCK on PC0
+#define GPIO_PCTL_PC0_T4CCP0 0x00000007 // T4CCP0 on PC0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port D.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PD7_M 0xF0000000 // PD7 mask
+#define GPIO_PCTL_PD7_U2TX 0x10000000 // U2TX on PD7
+#define GPIO_PCTL_PD7_WT5CCP1 0x70000000 // WT5CCP1 on PD7
+#define GPIO_PCTL_PD7_NMI 0x80000000 // NMI on PD7
+#define GPIO_PCTL_PD6_M 0x0F000000 // PD6 mask
+#define GPIO_PCTL_PD6_U2RX 0x01000000 // U2RX on PD6
+#define GPIO_PCTL_PD6_WT5CCP0 0x07000000 // WT5CCP0 on PD6
+#define GPIO_PCTL_PD5_M 0x00F00000 // PD5 mask
+#define GPIO_PCTL_PD5_U6TX 0x00100000 // U6TX on PD5
+#define GPIO_PCTL_PD5_WT4CCP1 0x00700000 // WT4CCP1 on PD5
+#define GPIO_PCTL_PD4_M 0x000F0000 // PD4 mask
+#define GPIO_PCTL_PD4_U6RX 0x00010000 // U6RX on PD4
+#define GPIO_PCTL_PD4_WT4CCP0 0x00070000 // WT4CCP0 on PD4
+#define GPIO_PCTL_PD3_M 0x0000F000 // PD3 mask
+#define GPIO_PCTL_PD3_SSI3TX 0x00001000 // SSI3TX on PD3
+#define GPIO_PCTL_PD3_SSI1TX 0x00002000 // SSI1TX on PD3
+#define GPIO_PCTL_PD3_WT3CCP1 0x00007000 // WT3CCP1 on PD3
+#define GPIO_PCTL_PD2_M 0x00000F00 // PD2 mask
+#define GPIO_PCTL_PD2_SSI3RX 0x00000100 // SSI3RX on PD2
+#define GPIO_PCTL_PD2_SSI1RX 0x00000200 // SSI1RX on PD2
+#define GPIO_PCTL_PD2_WT3CCP0 0x00000700 // WT3CCP0 on PD2
+#define GPIO_PCTL_PD1_M 0x000000F0 // PD1 mask
+#define GPIO_PCTL_PD1_SSI3FSS 0x00000010 // SSI3FSS on PD1
+#define GPIO_PCTL_PD1_SSI1FSS 0x00000020 // SSI1FSS on PD1
+#define GPIO_PCTL_PD1_I2C3SDA 0x00000030 // I2C3SDA on PD1
+#define GPIO_PCTL_PD1_WT2CCP1 0x00000070 // WT2CCP1 on PD1
+#define GPIO_PCTL_PD0_M 0x0000000F // PD0 mask
+#define GPIO_PCTL_PD0_SSI3CLK 0x00000001 // SSI3CLK on PD0
+#define GPIO_PCTL_PD0_SSI1CLK 0x00000002 // SSI1CLK on PD0
+#define GPIO_PCTL_PD0_I2C3SCL 0x00000003 // I2C3SCL on PD0
+#define GPIO_PCTL_PD0_WT2CCP0 0x00000007 // WT2CCP0 on PD0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port E.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PE5_M 0x00F00000 // PE5 mask
+#define GPIO_PCTL_PE5_U5TX 0x00100000 // U5TX on PE5
+#define GPIO_PCTL_PE5_I2C2SDA 0x00300000 // I2C2SDA on PE5
+#define GPIO_PCTL_PE5_CAN0TX 0x00800000 // CAN0TX on PE5
+#define GPIO_PCTL_PE4_M 0x000F0000 // PE4 mask
+#define GPIO_PCTL_PE4_U5RX 0x00010000 // U5RX on PE4
+#define GPIO_PCTL_PE4_I2C2SCL 0x00030000 // I2C2SCL on PE4
+#define GPIO_PCTL_PE4_CAN0RX 0x00080000 // CAN0RX on PE4
+#define GPIO_PCTL_PE3_M 0x0000F000 // PE3 mask
+#define GPIO_PCTL_PE2_M 0x00000F00 // PE2 mask
+#define GPIO_PCTL_PE1_M 0x000000F0 // PE1 mask
+#define GPIO_PCTL_PE1_U7TX 0x00000010 // U7TX on PE1
+#define GPIO_PCTL_PE0_M 0x0000000F // PE0 mask
+#define GPIO_PCTL_PE0_U7RX 0x00000001 // U7RX on PE0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port F.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PF4_M 0x000F0000 // PF4 mask
+#define GPIO_PCTL_PF4_T2CCP0 0x00070000 // T2CCP0 on PF4
+#define GPIO_PCTL_PF3_M 0x0000F000 // PF3 mask
+#define GPIO_PCTL_PF3_SSI1FSS 0x00002000 // SSI1FSS on PF3
+#define GPIO_PCTL_PF3_CAN0TX 0x00003000 // CAN0TX on PF3
+#define GPIO_PCTL_PF3_T1CCP1 0x00007000 // T1CCP1 on PF3
+#define GPIO_PCTL_PF3_TRCLK 0x0000E000 // TRCLK on PF3
+#define GPIO_PCTL_PF2_M 0x00000F00 // PF2 mask
+#define GPIO_PCTL_PF2_SSI1CLK 0x00000200 // SSI1CLK on PF2
+#define GPIO_PCTL_PF2_T1CCP0 0x00000700 // T1CCP0 on PF2
+#define GPIO_PCTL_PF2_TRD0 0x00000E00 // TRD0 on PF2
+#define GPIO_PCTL_PF1_M 0x000000F0 // PF1 mask
+#define GPIO_PCTL_PF1_U1CTS 0x00000010 // U1CTS on PF1
+#define GPIO_PCTL_PF1_SSI1TX 0x00000020 // SSI1TX on PF1
+#define GPIO_PCTL_PF1_T0CCP1 0x00000070 // T0CCP1 on PF1
+#define GPIO_PCTL_PF1_C1O 0x00000090 // C1O on PF1
+#define GPIO_PCTL_PF1_TRD1 0x000000E0 // TRD1 on PF1
+#define GPIO_PCTL_PF0_M 0x0000000F // PF0 mask
+#define GPIO_PCTL_PF0_U1RTS 0x00000001 // U1RTS on PF0
+#define GPIO_PCTL_PF0_SSI1RX 0x00000002 // SSI1RX on PF0
+#define GPIO_PCTL_PF0_CAN0RX 0x00000003 // CAN0RX on PF0
+#define GPIO_PCTL_PF0_T0CCP0 0x00000007 // T0CCP0 on PF0
+#define GPIO_PCTL_PF0_NMI 0x00000008 // NMI on PF0
+#define GPIO_PCTL_PF0_C0O 0x00000009 // C0O on PF0
+#define GPIO_PCTL_PF0_TRD2 0x0000000E // TRD2 on PF0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CR0 register.
+//
+//*****************************************************************************
+#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate
+#define SSI_CR0_SPH 0x00000080 // SSI Serial Clock Phase
+#define SSI_CR0_SPO 0x00000040 // SSI Serial Clock Polarity
+#define SSI_CR0_FRF_M 0x00000030 // SSI Frame Format Select
+#define SSI_CR0_FRF_MOTO 0x00000000 // Freescale SPI Frame Format
+#define SSI_CR0_FRF_TI 0x00000010 // Texas Instruments Synchronous
+ // Serial Frame Format
+#define SSI_CR0_FRF_NMW 0x00000020 // MICROWIRE Frame Format
+#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select
+#define SSI_CR0_DSS_4 0x00000003 // 4-bit data
+#define SSI_CR0_DSS_5 0x00000004 // 5-bit data
+#define SSI_CR0_DSS_6 0x00000005 // 6-bit data
+#define SSI_CR0_DSS_7 0x00000006 // 7-bit data
+#define SSI_CR0_DSS_8 0x00000007 // 8-bit data
+#define SSI_CR0_DSS_9 0x00000008 // 9-bit data
+#define SSI_CR0_DSS_10 0x00000009 // 10-bit data
+#define SSI_CR0_DSS_11 0x0000000A // 11-bit data
+#define SSI_CR0_DSS_12 0x0000000B // 12-bit data
+#define SSI_CR0_DSS_13 0x0000000C // 13-bit data
+#define SSI_CR0_DSS_14 0x0000000D // 14-bit data
+#define SSI_CR0_DSS_15 0x0000000E // 15-bit data
+#define SSI_CR0_DSS_16 0x0000000F // 16-bit data
+#define SSI_CR0_SCR_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CR1 register.
+//
+//*****************************************************************************
+#define SSI_CR1_EOT 0x00000010 // End of Transmission
+#define SSI_CR1_SOD 0x00000008 // SSI Slave Mode Output Disable
+#define SSI_CR1_MS 0x00000004 // SSI Master/Slave Select
+#define SSI_CR1_SSE 0x00000002 // SSI Synchronous Serial Port
+ // Enable
+#define SSI_CR1_LBM 0x00000001 // SSI Loopback Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_DR register.
+//
+//*****************************************************************************
+#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data
+#define SSI_DR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_SR register.
+//
+//*****************************************************************************
+#define SSI_SR_BSY 0x00000010 // SSI Busy Bit
+#define SSI_SR_RFF 0x00000008 // SSI Receive FIFO Full
+#define SSI_SR_RNE 0x00000004 // SSI Receive FIFO Not Empty
+#define SSI_SR_TNF 0x00000002 // SSI Transmit FIFO Not Full
+#define SSI_SR_TFE 0x00000001 // SSI Transmit FIFO Empty
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CPSR register.
+//
+//*****************************************************************************
+#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor
+#define SSI_CPSR_CPSDVSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_IM register.
+//
+//*****************************************************************************
+#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt Mask
+#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask
+#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt
+ // Mask
+#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt
+ // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_RIS register.
+//
+//*****************************************************************************
+#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt
+ // Status
+#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt
+ // Status
+#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw
+ // Interrupt Status
+#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw
+ // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_MIS register.
+//
+//*****************************************************************************
+#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked
+ // Interrupt Status
+#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked
+ // Interrupt Status
+#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked
+ // Interrupt Status
+#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked
+ // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_ICR register.
+//
+//*****************************************************************************
+#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt
+ // Clear
+#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt
+ // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_DMACTL register.
+//
+//*****************************************************************************
+#define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable
+#define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CC register.
+//
+//*****************************************************************************
+#define SSI_CC_CS_M 0x0000000F // SSI Baud Clock Source
+#define SSI_CC_CS_SYSPLL 0x00000000 // Either the system clock (if the
+ // PLL bypass is in effect) or the
+ // PLL output (default)
+#define SSI_CC_CS_PIOSC 0x00000005 // PIOSC
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_DR register.
+//
+//*****************************************************************************
+#define UART_DR_OE 0x00000800 // UART Overrun Error
+#define UART_DR_BE 0x00000400 // UART Break Error
+#define UART_DR_PE 0x00000200 // UART Parity Error
+#define UART_DR_FE 0x00000100 // UART Framing Error
+#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received
+#define UART_DR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_RSR register.
+//
+//*****************************************************************************
+#define UART_RSR_OE 0x00000008 // UART Overrun Error
+#define UART_RSR_BE 0x00000004 // UART Break Error
+#define UART_RSR_PE 0x00000002 // UART Parity Error
+#define UART_RSR_FE 0x00000001 // UART Framing Error
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ECR register.
+//
+//*****************************************************************************
+#define UART_ECR_DATA_M 0x000000FF // Error Clear
+#define UART_ECR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_FR register.
+//
+//*****************************************************************************
+#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty
+#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full
+#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full
+#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty
+#define UART_FR_BUSY 0x00000008 // UART Busy
+#define UART_FR_CTS 0x00000001 // Clear To Send
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ILPR register.
+//
+//*****************************************************************************
+#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor
+#define UART_ILPR_ILPDVSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IBRD register.
+//
+//*****************************************************************************
+#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor
+#define UART_IBRD_DIVINT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_FBRD register.
+//
+//*****************************************************************************
+#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor
+#define UART_FBRD_DIVFRAC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LCRH register.
+//
+//*****************************************************************************
+#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select
+#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length
+#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default)
+#define UART_LCRH_WLEN_6 0x00000020 // 6 bits
+#define UART_LCRH_WLEN_7 0x00000040 // 7 bits
+#define UART_LCRH_WLEN_8 0x00000060 // 8 bits
+#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs
+#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select
+#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select
+#define UART_LCRH_PEN 0x00000002 // UART Parity Enable
+#define UART_LCRH_BRK 0x00000001 // UART Send Break
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_CTL register.
+//
+//*****************************************************************************
+#define UART_CTL_RXE 0x00000200 // UART Receive Enable
+#define UART_CTL_TXE 0x00000100 // UART Transmit Enable
+#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable
+#define UART_CTL_LIN 0x00000040 // LIN Mode Enable
+#define UART_CTL_HSE 0x00000020 // High-Speed Enable
+#define UART_CTL_EOT 0x00000010 // End of Transmission
+#define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support
+#define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode
+#define UART_CTL_SIREN 0x00000002 // UART SIR Enable
+#define UART_CTL_UARTEN 0x00000001 // UART Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IFLS register.
+//
+//*****************************************************************************
+#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO
+ // Level Select
+#define UART_IFLS_RX1_8 0x00000000 // RX FIFO >= 1/8 full
+#define UART_IFLS_RX2_8 0x00000008 // RX FIFO >= 1/4 full
+#define UART_IFLS_RX4_8 0x00000010 // RX FIFO >= 1/2 full (default)
+#define UART_IFLS_RX6_8 0x00000018 // RX FIFO >= 3/4 full
+#define UART_IFLS_RX7_8 0x00000020 // RX FIFO >= 7/8 full
+#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO
+ // Level Select
+#define UART_IFLS_TX1_8 0x00000000 // TX FIFO <= 1/8 full
+#define UART_IFLS_TX2_8 0x00000001 // TX FIFO <= 1/4 full
+#define UART_IFLS_TX4_8 0x00000002 // TX FIFO <= 1/2 full (default)
+#define UART_IFLS_TX6_8 0x00000003 // TX FIFO <= 3/4 full
+#define UART_IFLS_TX7_8 0x00000004 // TX FIFO <= 7/8 full
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IM register.
+//
+//*****************************************************************************
+#define UART_IM_LME5IM 0x00008000 // LIN Mode Edge 5 Interrupt Mask
+#define UART_IM_LME1IM 0x00004000 // LIN Mode Edge 1 Interrupt Mask
+#define UART_IM_LMSBIM 0x00002000 // LIN Mode Sync Break Interrupt
+ // Mask
+#define UART_IM_9BITIM 0x00001000 // 9-Bit Mode Interrupt Mask
+#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt
+ // Mask
+#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask
+#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask
+#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt
+ // Mask
+#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt
+ // Mask
+#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask
+#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask
+#define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem
+ // Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_RIS register.
+//
+//*****************************************************************************
+#define UART_RIS_LME5RIS 0x00008000 // LIN Mode Edge 5 Raw Interrupt
+ // Status
+#define UART_RIS_LME1RIS 0x00004000 // LIN Mode Edge 1 Raw Interrupt
+ // Status
+#define UART_RIS_LMSBRIS 0x00002000 // LIN Mode Sync Break Raw
+ // Interrupt Status
+#define UART_RIS_9BITRIS 0x00001000 // 9-Bit Mode Raw Interrupt Status
+#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt
+ // Status
+#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt
+ // Status
+#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt
+ // Status
+#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt
+ // Status
+#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw
+ // Interrupt Status
+#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt
+ // Status
+#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt
+ // Status
+#define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw
+ // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_MIS register.
+//
+//*****************************************************************************
+#define UART_MIS_LME5MIS 0x00008000 // LIN Mode Edge 5 Masked Interrupt
+ // Status
+#define UART_MIS_LME1MIS 0x00004000 // LIN Mode Edge 1 Masked Interrupt
+ // Status
+#define UART_MIS_LMSBMIS 0x00002000 // LIN Mode Sync Break Masked
+ // Interrupt Status
+#define UART_MIS_9BITMIS 0x00001000 // 9-Bit Mode Masked Interrupt
+ // Status
+#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked
+ // Interrupt Status
+#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked
+ // Interrupt Status
+#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked
+ // Interrupt Status
+#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked
+ // Interrupt Status
+#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked
+ // Interrupt Status
+#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt
+ // Status
+#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt
+ // Status
+#define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked
+ // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ICR register.
+//
+//*****************************************************************************
+#define UART_ICR_LME5IC 0x00008000 // LIN Mode Edge 5 Interrupt Clear
+#define UART_ICR_LME1IC 0x00004000 // LIN Mode Edge 1 Interrupt Clear
+#define UART_ICR_LMSBIC 0x00002000 // LIN Mode Sync Break Interrupt
+ // Clear
+#define UART_ICR_9BITIC 0x00001000 // 9-Bit Mode Interrupt Clear
+#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear
+#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear
+#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear
+#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear
+#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear
+#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear
+#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear
+#define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem
+ // Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_DMACTL register.
+//
+//*****************************************************************************
+#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error
+#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable
+#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LCTL register.
+//
+//*****************************************************************************
+#define UART_LCTL_BLEN_M 0x00000030 // Sync Break Length
+#define UART_LCTL_BLEN_13T 0x00000000 // Sync break length is 13T bits
+ // (default)
+#define UART_LCTL_BLEN_14T 0x00000010 // Sync break length is 14T bits
+#define UART_LCTL_BLEN_15T 0x00000020 // Sync break length is 15T bits
+#define UART_LCTL_BLEN_16T 0x00000030 // Sync break length is 16T bits
+#define UART_LCTL_MASTER 0x00000001 // LIN Master Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LSS register.
+//
+//*****************************************************************************
+#define UART_LSS_TSS_M 0x0000FFFF // Timer Snap Shot
+#define UART_LSS_TSS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LTIM register.
+//
+//*****************************************************************************
+#define UART_LTIM_TIMER_M 0x0000FFFF // Timer Value
+#define UART_LTIM_TIMER_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_9BITADDR
+// register.
+//
+//*****************************************************************************
+#define UART_9BITADDR_9BITEN 0x00008000 // Enable 9-Bit Mode
+#define UART_9BITADDR_ADDR_M 0x000000FF // Self Address for 9-Bit Mode
+#define UART_9BITADDR_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_9BITAMASK
+// register.
+//
+//*****************************************************************************
+#define UART_9BITAMASK_MASK_M 0x000000FF // Self Address Mask for 9-Bit Mode
+#define UART_9BITAMASK_MASK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_PP register.
+//
+//*****************************************************************************
+#define UART_PP_NB 0x00000002 // 9-Bit Support
+#define UART_PP_SC 0x00000001 // Smart Card Support
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_CC register.
+//
+//*****************************************************************************
+#define UART_CC_CS_M 0x0000000F // UART Baud Clock Source
+#define UART_CC_CS_SYSCLK 0x00000000 // The system clock (default)
+#define UART_CC_CS_PIOSC 0x00000005 // PIOSC
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MSA register.
+//
+//*****************************************************************************
+#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address
+#define I2C_MSA_RS 0x00000001 // Receive not send
+#define I2C_MSA_SA_S 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SOAR register.
+//
+//*****************************************************************************
+#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address
+#define I2C_SOAR_OAR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SCSR register.
+//
+//*****************************************************************************
+#define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched
+#define I2C_SCSR_FBR 0x00000004 // First Byte Received
+#define I2C_SCSR_TREQ 0x00000002 // Transmit Request
+#define I2C_SCSR_DA 0x00000001 // Device Active
+#define I2C_SCSR_RREQ 0x00000001 // Receive Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCS register.
+//
+//*****************************************************************************
+#define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error
+#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy
+#define I2C_MCS_IDLE 0x00000020 // I2C Idle
+#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost
+#define I2C_MCS_HS 0x00000010 // High-Speed Enable
+#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable
+#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data
+#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address
+#define I2C_MCS_STOP 0x00000004 // Generate STOP
+#define I2C_MCS_ERROR 0x00000002 // Error
+#define I2C_MCS_START 0x00000002 // Generate START
+#define I2C_MCS_RUN 0x00000001 // I2C Master Enable
+#define I2C_MCS_BUSY 0x00000001 // I2C Busy
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SDR register.
+//
+//*****************************************************************************
+#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer
+#define I2C_SDR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MDR register.
+//
+//*****************************************************************************
+#define I2C_MDR_DATA_M 0x000000FF // Data Transferred
+#define I2C_MDR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MTPR register.
+//
+//*****************************************************************************
+#define I2C_MTPR_HS 0x00000080 // High-Speed Enable
+#define I2C_MTPR_TPR_M 0x0000007F // SCL Clock Period
+#define I2C_MTPR_TPR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SIMR register.
+//
+//*****************************************************************************
+#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask
+#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask
+#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SRIS register.
+//
+//*****************************************************************************
+#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt
+ // Status
+#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt
+ // Status
+#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MIMR register.
+//
+//*****************************************************************************
+#define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask
+#define I2C_MIMR_IM 0x00000001 // Master Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MRIS register.
+//
+//*****************************************************************************
+#define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt
+ // Status
+#define I2C_MRIS_RIS 0x00000001 // Master Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SMIS register.
+//
+//*****************************************************************************
+#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt
+ // Status
+#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt
+ // Status
+#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SICR register.
+//
+//*****************************************************************************
+#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear
+#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear
+#define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MMIS register.
+//
+//*****************************************************************************
+#define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt
+ // Status
+#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MICR register.
+//
+//*****************************************************************************
+#define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear
+#define I2C_MICR_IC 0x00000001 // Master Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SOAR2 register.
+//
+//*****************************************************************************
+#define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable
+#define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2
+#define I2C_SOAR2_OAR2_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCR register.
+//
+//*****************************************************************************
+#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable
+#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable
+#define I2C_MCR_LPBK 0x00000001 // I2C Loopback
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SACKCTL register.
+//
+//*****************************************************************************
+#define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value
+#define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCLKOCNT register.
+//
+//*****************************************************************************
+#define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count
+#define I2C_MCLKOCNT_CNTL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MBMON register.
+//
+//*****************************************************************************
+#define I2C_MBMON_SDA 0x00000002 // I2C SDA Status
+#define I2C_MBMON_SCL 0x00000001 // I2C SCL Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_PP register.
+//
+//*****************************************************************************
+#define I2C_PP_HS 0x00000001 // High-Speed Capable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_PC register.
+//
+//*****************************************************************************
+#define I2C_PC_HS 0x00000001 // High-Speed Capable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CFG register.
+//
+//*****************************************************************************
+#define TIMER_CFG_M 0x00000007 // GPTM Configuration
+#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32-bit timer configuration
+#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32-bit real-time clock (RTC)
+ // counter configuration
+#define TIMER_CFG_16_BIT 0x00000004 // 16-bit timer configuration. The
+ // function is controlled by bits
+ // 1:0 of GPTMTAMR and GPTMTBMR
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAMR register.
+//
+//*****************************************************************************
+#define TIMER_TAMR_TAPLO 0x00000800 // GPTM Timer A PWM Legacy
+ // Operation
+#define TIMER_TAMR_TAMRSU 0x00000400 // GPTM Timer A Match Register
+ // Update
+#define TIMER_TAMR_TAPWMIE 0x00000200 // GPTM Timer A PWM Interrupt
+ // Enable
+#define TIMER_TAMR_TAILD 0x00000100 // GPTM Timer A Interval Load Write
+#define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode
+#define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger
+#define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt
+ // Enable
+#define TIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A Count Direction
+#define TIMER_TAMR_TAAMS 0x00000008 // GPTM Timer A Alternate Mode
+ // Select
+#define TIMER_TAMR_TACMR 0x00000004 // GPTM Timer A Capture Mode
+#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A Mode
+#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode
+#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode
+#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBMR register.
+//
+//*****************************************************************************
+#define TIMER_TBMR_TBPLO 0x00000800 // GPTM Timer B PWM Legacy
+ // Operation
+#define TIMER_TBMR_TBMRSU 0x00000400 // GPTM Timer B Match Register
+ // Update
+#define TIMER_TBMR_TBPWMIE 0x00000200 // GPTM Timer B PWM Interrupt
+ // Enable
+#define TIMER_TBMR_TBILD 0x00000100 // GPTM Timer B Interval Load Write
+#define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode
+#define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger
+#define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt
+ // Enable
+#define TIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B Count Direction
+#define TIMER_TBMR_TBAMS 0x00000008 // GPTM Timer B Alternate Mode
+ // Select
+#define TIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B Capture Mode
+#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B Mode
+#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode
+#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode
+#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CTL register.
+//
+//*****************************************************************************
+#define TIMER_CTL_TBPWML 0x00004000 // GPTM Timer B PWM Output Level
+#define TIMER_CTL_TBOTE 0x00002000 // GPTM Timer B Output Trigger
+ // Enable
+#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM Timer B Event Mode
+#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge
+#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge
+#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges
+#define TIMER_CTL_TBSTALL 0x00000200 // GPTM Timer B Stall Enable
+#define TIMER_CTL_TBEN 0x00000100 // GPTM Timer B Enable
+#define TIMER_CTL_TAPWML 0x00000040 // GPTM Timer A PWM Output Level
+#define TIMER_CTL_TAOTE 0x00000020 // GPTM Timer A Output Trigger
+ // Enable
+#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Stall Enable
+#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM Timer A Event Mode
+#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge
+#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge
+#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges
+#define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable
+#define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_SYNC register.
+//
+//*****************************************************************************
+#define TIMER_SYNC_SYNCWT5_M 0x00C00000 // Synchronize GPTM 32/64-Bit Timer
+ // 5
+#define TIMER_SYNC_SYNCWT5_NONE 0x00000000 // GPTM 32/64-Bit Timer 5 is not
+ // affected
+#define TIMER_SYNC_SYNCWT5_TA 0x00400000 // A timeout event for Timer A of
+ // GPTM 32/64-Bit Timer 5 is
+ // triggered
+#define TIMER_SYNC_SYNCWT5_TB 0x00800000 // A timeout event for Timer B of
+ // GPTM 32/64-Bit Timer 5 is
+ // triggered
+#define TIMER_SYNC_SYNCWT5_TATB 0x00C00000 // A timeout event for both Timer A
+ // and Timer B of GPTM 32/64-Bit
+ // Timer 5 is triggered
+#define TIMER_SYNC_SYNCWT4_M 0x00300000 // Synchronize GPTM 32/64-Bit Timer
+ // 4
+#define TIMER_SYNC_SYNCWT4_NONE 0x00000000 // GPTM 32/64-Bit Timer 4 is not
+ // affected
+#define TIMER_SYNC_SYNCWT4_TA 0x00100000 // A timeout event for Timer A of
+ // GPTM 32/64-Bit Timer 4 is
+ // triggered
+#define TIMER_SYNC_SYNCWT4_TB 0x00200000 // A timeout event for Timer B of
+ // GPTM 32/64-Bit Timer 4 is
+ // triggered
+#define TIMER_SYNC_SYNCWT4_TATB 0x00300000 // A timeout event for both Timer A
+ // and Timer B of GPTM 32/64-Bit
+ // Timer 4 is triggered
+#define TIMER_SYNC_SYNCWT3_M 0x000C0000 // Synchronize GPTM 32/64-Bit Timer
+ // 3
+#define TIMER_SYNC_SYNCWT3_NONE 0x00000000 // GPTM 32/64-Bit Timer 3 is not
+ // affected
+#define TIMER_SYNC_SYNCWT3_TA 0x00040000 // A timeout event for Timer A of
+ // GPTM 32/64-Bit Timer 3 is
+ // triggered
+#define TIMER_SYNC_SYNCWT3_TB 0x00080000 // A timeout event for Timer B of
+ // GPTM 32/64-Bit Timer 3 is
+ // triggered
+#define TIMER_SYNC_SYNCWT3_TATB 0x000C0000 // A timeout event for both Timer A
+ // and Timer B of GPTM 32/64-Bit
+ // Timer 3 is triggered
+#define TIMER_SYNC_SYNCWT2_M 0x00030000 // Synchronize GPTM 32/64-Bit Timer
+ // 2
+#define TIMER_SYNC_SYNCWT2_NONE 0x00000000 // GPTM 32/64-Bit Timer 2 is not
+ // affected
+#define TIMER_SYNC_SYNCWT2_TA 0x00010000 // A timeout event for Timer A of
+ // GPTM 32/64-Bit Timer 2 is
+ // triggered
+#define TIMER_SYNC_SYNCWT2_TB 0x00020000 // A timeout event for Timer B of
+ // GPTM 32/64-Bit Timer 2 is
+ // triggered
+#define TIMER_SYNC_SYNCWT2_TATB 0x00030000 // A timeout event for both Timer A
+ // and Timer B of GPTM 32/64-Bit
+ // Timer 2 is triggered
+#define TIMER_SYNC_SYNCWT1_M 0x0000C000 // Synchronize GPTM 32/64-Bit Timer
+ // 1
+#define TIMER_SYNC_SYNCWT1_NONE 0x00000000 // GPTM 32/64-Bit Timer 1 is not
+ // affected
+#define TIMER_SYNC_SYNCWT1_TA 0x00004000 // A timeout event for Timer A of
+ // GPTM 32/64-Bit Timer 1 is
+ // triggered
+#define TIMER_SYNC_SYNCWT1_TB 0x00008000 // A timeout event for Timer B of
+ // GPTM 32/64-Bit Timer 1 is
+ // triggered
+#define TIMER_SYNC_SYNCWT1_TATB 0x0000C000 // A timeout event for both Timer A
+ // and Timer B of GPTM 32/64-Bit
+ // Timer 1 is triggered
+#define TIMER_SYNC_SYNCWT0_M 0x00003000 // Synchronize GPTM 32/64-Bit Timer
+ // 0
+#define TIMER_SYNC_SYNCWT0_NONE 0x00000000 // GPTM 32/64-Bit Timer 0 is not
+ // affected
+#define TIMER_SYNC_SYNCWT0_TA 0x00001000 // A timeout event for Timer A of
+ // GPTM 32/64-Bit Timer 0 is
+ // triggered
+#define TIMER_SYNC_SYNCWT0_TB 0x00002000 // A timeout event for Timer B of
+ // GPTM 32/64-Bit Timer 0 is
+ // triggered
+#define TIMER_SYNC_SYNCWT0_TATB 0x00003000 // A timeout event for both Timer A
+ // and Timer B of GPTM 32/64-Bit
+ // Timer 0 is triggered
+#define TIMER_SYNC_SYNCT5_M 0x00000C00 // Synchronize GPTM 16/32-Bit Timer
+ // 5
+#define TIMER_SYNC_SYNCT5_NONE 0x00000000 // GPTM 16/32-Bit Timer 5 is not
+ // affected
+#define TIMER_SYNC_SYNCT5_TA 0x00000400 // A timeout event for Timer A of
+ // GPTM 16/32-Bit Timer 5 is
+ // triggered
+#define TIMER_SYNC_SYNCT5_TB 0x00000800 // A timeout event for Timer B of
+ // GPTM 16/32-Bit Timer 5 is
+ // triggered
+#define TIMER_SYNC_SYNCT5_TATB 0x00000C00 // A timeout event for both Timer A
+ // and Timer B of GPTM 16/32-Bit
+ // Timer 5 is triggered
+#define TIMER_SYNC_SYNCT4_M 0x00000300 // Synchronize GPTM 16/32-Bit Timer
+ // 4
+#define TIMER_SYNC_SYNCT4_NONE 0x00000000 // GPTM 16/32-Bit Timer 4 is not
+ // affected
+#define TIMER_SYNC_SYNCT4_TA 0x00000100 // A timeout event for Timer A of
+ // GPTM 16/32-Bit Timer 4 is
+ // triggered
+#define TIMER_SYNC_SYNCT4_TB 0x00000200 // A timeout event for Timer B of
+ // GPTM 16/32-Bit Timer 4 is
+ // triggered
+#define TIMER_SYNC_SYNCT4_TATB 0x00000300 // A timeout event for both Timer A
+ // and Timer B of GPTM 16/32-Bit
+ // Timer 4 is triggered
+#define TIMER_SYNC_SYNCT3_M 0x000000C0 // Synchronize GPTM 16/32-Bit Timer
+ // 3
+#define TIMER_SYNC_SYNCT3_NONE 0x00000000 // GPTM 16/32-Bit Timer 3 is not
+ // affected
+#define TIMER_SYNC_SYNCT3_TA 0x00000040 // A timeout event for Timer A of
+ // GPTM 16/32-Bit Timer 3 is
+ // triggered
+#define TIMER_SYNC_SYNCT3_TB 0x00000080 // A timeout event for Timer B of
+ // GPTM 16/32-Bit Timer 3 is
+ // triggered
+#define TIMER_SYNC_SYNCT3_TATB 0x000000C0 // A timeout event for both Timer A
+ // and Timer B of GPTM 16/32-Bit
+ // Timer 3 is triggered
+#define TIMER_SYNC_SYNCT2_M 0x00000030 // Synchronize GPTM 16/32-Bit Timer
+ // 2
+#define TIMER_SYNC_SYNCT2_NONE 0x00000000 // GPTM 16/32-Bit Timer 2 is not
+ // affected
+#define TIMER_SYNC_SYNCT2_TA 0x00000010 // A timeout event for Timer A of
+ // GPTM 16/32-Bit Timer 2 is
+ // triggered
+#define TIMER_SYNC_SYNCT2_TB 0x00000020 // A timeout event for Timer B of
+ // GPTM 16/32-Bit Timer 2 is
+ // triggered
+#define TIMER_SYNC_SYNCT2_TATB 0x00000030 // A timeout event for both Timer A
+ // and Timer B of GPTM 16/32-Bit
+ // Timer 2 is triggered
+#define TIMER_SYNC_SYNCT1_M 0x0000000C // Synchronize GPTM 16/32-Bit Timer
+ // 1
+#define TIMER_SYNC_SYNCT1_NONE 0x00000000 // GPTM 16/32-Bit Timer 1 is not
+ // affected
+#define TIMER_SYNC_SYNCT1_TA 0x00000004 // A timeout event for Timer A of
+ // GPTM 16/32-Bit Timer 1 is
+ // triggered
+#define TIMER_SYNC_SYNCT1_TB 0x00000008 // A timeout event for Timer B of
+ // GPTM 16/32-Bit Timer 1 is
+ // triggered
+#define TIMER_SYNC_SYNCT1_TATB 0x0000000C // A timeout event for both Timer A
+ // and Timer B of GPTM 16/32-Bit
+ // Timer 1 is triggered
+#define TIMER_SYNC_SYNCT0_M 0x00000003 // Synchronize GPTM 16/32-Bit Timer
+ // 0
+#define TIMER_SYNC_SYNCT0_NONE 0x00000000 // GPTM 16/32-Bit Timer 0 is not
+ // affected
+#define TIMER_SYNC_SYNCT0_TA 0x00000001 // A timeout event for Timer A of
+ // GPTM 16/32-Bit Timer 0 is
+ // triggered
+#define TIMER_SYNC_SYNCT0_TB 0x00000002 // A timeout event for Timer B of
+ // GPTM 16/32-Bit Timer 0 is
+ // triggered
+#define TIMER_SYNC_SYNCT0_TATB 0x00000003 // A timeout event for both Timer A
+ // and Timer B of GPTM 16/32-Bit
+ // Timer 0 is triggered
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_IMR register.
+//
+//*****************************************************************************
+#define TIMER_IMR_WUEIM 0x00010000 // GPTM Write Update Error
+ // Interrupt Mask
+#define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Match Interrupt
+ // Mask
+#define TIMER_IMR_CBEIM 0x00000400 // GPTM Timer B Capture Mode Event
+ // Interrupt Mask
+#define TIMER_IMR_CBMIM 0x00000200 // GPTM Timer B Capture Mode Match
+ // Interrupt Mask
+#define TIMER_IMR_TBTOIM 0x00000100 // GPTM Timer B Time-Out Interrupt
+ // Mask
+#define TIMER_IMR_TAMIM 0x00000010 // GPTM Timer A Match Interrupt
+ // Mask
+#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask
+#define TIMER_IMR_CAEIM 0x00000004 // GPTM Timer A Capture Mode Event
+ // Interrupt Mask
+#define TIMER_IMR_CAMIM 0x00000002 // GPTM Timer A Capture Mode Match
+ // Interrupt Mask
+#define TIMER_IMR_TATOIM 0x00000001 // GPTM Timer A Time-Out Interrupt
+ // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_RIS register.
+//
+//*****************************************************************************
+#define TIMER_RIS_WUERIS 0x00010000 // GPTM Write Update Error Raw
+ // Interrupt
+#define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Match Raw Interrupt
+#define TIMER_RIS_CBERIS 0x00000400 // GPTM Timer B Capture Mode Event
+ // Raw Interrupt
+#define TIMER_RIS_CBMRIS 0x00000200 // GPTM Timer B Capture Mode Match
+ // Raw Interrupt
+#define TIMER_RIS_TBTORIS 0x00000100 // GPTM Timer B Time-Out Raw
+ // Interrupt
+#define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Match Raw Interrupt
+#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt
+#define TIMER_RIS_CAERIS 0x00000004 // GPTM Timer A Capture Mode Event
+ // Raw Interrupt
+#define TIMER_RIS_CAMRIS 0x00000002 // GPTM Timer A Capture Mode Match
+ // Raw Interrupt
+#define TIMER_RIS_TATORIS 0x00000001 // GPTM Timer A Time-Out Raw
+ // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_MIS register.
+//
+//*****************************************************************************
+#define TIMER_MIS_WUEMIS 0x00010000 // GPTM Write Update Error Masked
+ // Interrupt
+#define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Match Masked
+ // Interrupt
+#define TIMER_MIS_CBEMIS 0x00000400 // GPTM Timer B Capture Mode Event
+ // Masked Interrupt
+#define TIMER_MIS_CBMMIS 0x00000200 // GPTM Timer B Capture Mode Match
+ // Masked Interrupt
+#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM Timer B Time-Out Masked
+ // Interrupt
+#define TIMER_MIS_TAMMIS 0x00000010 // GPTM Timer A Match Masked
+ // Interrupt
+#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt
+#define TIMER_MIS_CAEMIS 0x00000004 // GPTM Timer A Capture Mode Event
+ // Masked Interrupt
+#define TIMER_MIS_CAMMIS 0x00000002 // GPTM Timer A Capture Mode Match
+ // Masked Interrupt
+#define TIMER_MIS_TATOMIS 0x00000001 // GPTM Timer A Time-Out Masked
+ // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_ICR register.
+//
+//*****************************************************************************
+#define TIMER_ICR_WUECINT 0x00010000 // 32/64-Bit GPTM Write Update
+ // Error Interrupt Clear
+#define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Match Interrupt
+ // Clear
+#define TIMER_ICR_CBECINT 0x00000400 // GPTM Timer B Capture Mode Event
+ // Interrupt Clear
+#define TIMER_ICR_CBMCINT 0x00000200 // GPTM Timer B Capture Mode Match
+ // Interrupt Clear
+#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM Timer B Time-Out Interrupt
+ // Clear
+#define TIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A Match Interrupt
+ // Clear
+#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear
+#define TIMER_ICR_CAECINT 0x00000004 // GPTM Timer A Capture Mode Event
+ // Interrupt Clear
+#define TIMER_ICR_CAMCINT 0x00000002 // GPTM Timer A Capture Mode Match
+ // Interrupt Clear
+#define TIMER_ICR_TATOCINT 0x00000001 // GPTM Timer A Time-Out Raw
+ // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAILR register.
+//
+//*****************************************************************************
+#define TIMER_TAILR_M 0xFFFFFFFF // GPTM Timer A Interval Load
+ // Register
+#define TIMER_TAILR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBILR register.
+//
+//*****************************************************************************
+#define TIMER_TBILR_M 0xFFFFFFFF // GPTM Timer B Interval Load
+ // Register
+#define TIMER_TBILR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAMATCHR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF // GPTM Timer A Match Register
+#define TIMER_TAMATCHR_TAMR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBMATCHR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF // GPTM Timer B Match Register
+#define TIMER_TBMATCHR_TBMR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPR register.
+//
+//*****************************************************************************
+#define TIMER_TAPR_TAPSRH_M 0x0000FF00 // GPTM Timer A Prescale High Byte
+#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale
+#define TIMER_TAPR_TAPSRH_S 8
+#define TIMER_TAPR_TAPSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPR register.
+//
+//*****************************************************************************
+#define TIMER_TBPR_TBPSRH_M 0x0000FF00 // GPTM Timer B Prescale High Byte
+#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale
+#define TIMER_TBPR_TBPSRH_S 8
+#define TIMER_TBPR_TBPSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPMR register.
+//
+//*****************************************************************************
+#define TIMER_TAPMR_TAPSMRH_M 0x0000FF00 // GPTM Timer A Prescale Match High
+ // Byte
+#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match
+#define TIMER_TAPMR_TAPSMRH_S 8
+#define TIMER_TAPMR_TAPSMR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPMR register.
+//
+//*****************************************************************************
+#define TIMER_TBPMR_TBPSMRH_M 0x0000FF00 // GPTM Timer B Prescale Match High
+ // Byte
+#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match
+#define TIMER_TBPMR_TBPSMRH_S 8
+#define TIMER_TBPMR_TBPSMR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAR register.
+//
+//*****************************************************************************
+#define TIMER_TAR_M 0xFFFFFFFF // GPTM Timer A Register
+#define TIMER_TAR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBR register.
+//
+//*****************************************************************************
+#define TIMER_TBR_M 0xFFFFFFFF // GPTM Timer B Register
+#define TIMER_TBR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAV register.
+//
+//*****************************************************************************
+#define TIMER_TAV_M 0xFFFFFFFF // GPTM Timer A Value
+#define TIMER_TAV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBV register.
+//
+//*****************************************************************************
+#define TIMER_TBV_M 0xFFFFFFFF // GPTM Timer B Value
+#define TIMER_TBV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_RTCPD register.
+//
+//*****************************************************************************
+#define TIMER_RTCPD_RTCPD_M 0x0000FFFF // RTC Predivide Counter Value
+#define TIMER_RTCPD_RTCPD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPS register.
+//
+//*****************************************************************************
+#define TIMER_TAPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Snapshot
+#define TIMER_TAPS_PSS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPS register.
+//
+//*****************************************************************************
+#define TIMER_TBPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Value
+#define TIMER_TBPS_PSS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPV register.
+//
+//*****************************************************************************
+#define TIMER_TAPV_PSV_M 0x0000FFFF // GPTM Timer A Prescaler Value
+#define TIMER_TAPV_PSV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPV register.
+//
+//*****************************************************************************
+#define TIMER_TBPV_PSV_M 0x0000FFFF // GPTM Timer B Prescaler Value
+#define TIMER_TBPV_PSV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_PP register.
+//
+//*****************************************************************************
+#define TIMER_PP_SIZE_M 0x0000000F // Count Size
+#define TIMER_PP_SIZE_16 0x00000000 // Timer A and Timer B counters are
+ // 16 bits each with an 8-bit
+ // prescale counter
+#define TIMER_PP_SIZE_32 0x00000001 // Timer A and Timer B counters are
+ // 32 bits each with a 16-bit
+ // prescale counter
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_ACTSS register.
+//
+//*****************************************************************************
+#define ADC_ACTSS_ASEN3 0x00000008 // ADC SS3 Enable
+#define ADC_ACTSS_ASEN2 0x00000004 // ADC SS2 Enable
+#define ADC_ACTSS_ASEN1 0x00000002 // ADC SS1 Enable
+#define ADC_ACTSS_ASEN0 0x00000001 // ADC SS0 Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_RIS register.
+//
+//*****************************************************************************
+#define ADC_RIS_INRDC 0x00010000 // Digital Comparator Raw Interrupt
+ // Status
+#define ADC_RIS_INR3 0x00000008 // SS3 Raw Interrupt Status
+#define ADC_RIS_INR2 0x00000004 // SS2 Raw Interrupt Status
+#define ADC_RIS_INR1 0x00000002 // SS1 Raw Interrupt Status
+#define ADC_RIS_INR0 0x00000001 // SS0 Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_IM register.
+//
+//*****************************************************************************
+#define ADC_IM_DCONSS3 0x00080000 // Digital Comparator Interrupt on
+ // SS3
+#define ADC_IM_DCONSS2 0x00040000 // Digital Comparator Interrupt on
+ // SS2
+#define ADC_IM_DCONSS1 0x00020000 // Digital Comparator Interrupt on
+ // SS1
+#define ADC_IM_DCONSS0 0x00010000 // Digital Comparator Interrupt on
+ // SS0
+#define ADC_IM_MASK3 0x00000008 // SS3 Interrupt Mask
+#define ADC_IM_MASK2 0x00000004 // SS2 Interrupt Mask
+#define ADC_IM_MASK1 0x00000002 // SS1 Interrupt Mask
+#define ADC_IM_MASK0 0x00000001 // SS0 Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_ISC register.
+//
+//*****************************************************************************
+#define ADC_ISC_DCINSS3 0x00080000 // Digital Comparator Interrupt
+ // Status on SS3
+#define ADC_ISC_DCINSS2 0x00040000 // Digital Comparator Interrupt
+ // Status on SS2
+#define ADC_ISC_DCINSS1 0x00020000 // Digital Comparator Interrupt
+ // Status on SS1
+#define ADC_ISC_DCINSS0 0x00010000 // Digital Comparator Interrupt
+ // Status on SS0
+#define ADC_ISC_IN3 0x00000008 // SS3 Interrupt Status and Clear
+#define ADC_ISC_IN2 0x00000004 // SS2 Interrupt Status and Clear
+#define ADC_ISC_IN1 0x00000002 // SS1 Interrupt Status and Clear
+#define ADC_ISC_IN0 0x00000001 // SS0 Interrupt Status and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_OSTAT register.
+//
+//*****************************************************************************
+#define ADC_OSTAT_OV3 0x00000008 // SS3 FIFO Overflow
+#define ADC_OSTAT_OV2 0x00000004 // SS2 FIFO Overflow
+#define ADC_OSTAT_OV1 0x00000002 // SS1 FIFO Overflow
+#define ADC_OSTAT_OV0 0x00000001 // SS0 FIFO Overflow
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_EMUX register.
+//
+//*****************************************************************************
+#define ADC_EMUX_EM3_M 0x0000F000 // SS3 Trigger Select
+#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor (default)
+#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog Comparator 0
+#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog Comparator 1
+#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External (GPIO PB4)
+#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer
+#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always (continuously sample)
+#define ADC_EMUX_EM2_M 0x00000F00 // SS2 Trigger Select
+#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor (default)
+#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog Comparator 0
+#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog Comparator 1
+#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External (GPIO PB4)
+#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer
+#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always (continuously sample)
+#define ADC_EMUX_EM1_M 0x000000F0 // SS1 Trigger Select
+#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor (default)
+#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog Comparator 0
+#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog Comparator 1
+#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External (GPIO PB4)
+#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer
+#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always (continuously sample)
+#define ADC_EMUX_EM0_M 0x0000000F // SS0 Trigger Select
+#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor (default)
+#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog Comparator 0
+#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog Comparator 1
+#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External (GPIO PB4)
+#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer
+#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always (continuously sample)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_USTAT register.
+//
+//*****************************************************************************
+#define ADC_USTAT_UV3 0x00000008 // SS3 FIFO Underflow
+#define ADC_USTAT_UV2 0x00000004 // SS2 FIFO Underflow
+#define ADC_USTAT_UV1 0x00000002 // SS1 FIFO Underflow
+#define ADC_USTAT_UV0 0x00000001 // SS0 FIFO Underflow
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSPRI register.
+//
+//*****************************************************************************
+#define ADC_SSPRI_SS3_M 0x00003000 // SS3 Priority
+#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority
+#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority
+#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority
+#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority
+#define ADC_SSPRI_SS2_M 0x00000300 // SS2 Priority
+#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority
+#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority
+#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority
+#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority
+#define ADC_SSPRI_SS1_M 0x00000030 // SS1 Priority
+#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority
+#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority
+#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority
+#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority
+#define ADC_SSPRI_SS0_M 0x00000003 // SS0 Priority
+#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority
+#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority
+#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority
+#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SPC register.
+//
+//*****************************************************************************
+#define ADC_SPC_PHASE_M 0x0000000F // Phase Difference
+#define ADC_SPC_PHASE_0 0x00000000 // ADC sample lags by 0.0
+#define ADC_SPC_PHASE_22_5 0x00000001 // ADC sample lags by 22.5
+#define ADC_SPC_PHASE_45 0x00000002 // ADC sample lags by 45.0
+#define ADC_SPC_PHASE_67_5 0x00000003 // ADC sample lags by 67.5
+#define ADC_SPC_PHASE_90 0x00000004 // ADC sample lags by 90.0
+#define ADC_SPC_PHASE_112_5 0x00000005 // ADC sample lags by 112.5
+#define ADC_SPC_PHASE_135 0x00000006 // ADC sample lags by 135.0
+#define ADC_SPC_PHASE_157_5 0x00000007 // ADC sample lags by 157.5
+#define ADC_SPC_PHASE_180 0x00000008 // ADC sample lags by 180.0
+#define ADC_SPC_PHASE_202_5 0x00000009 // ADC sample lags by 202.5
+#define ADC_SPC_PHASE_225 0x0000000A // ADC sample lags by 225.0
+#define ADC_SPC_PHASE_247_5 0x0000000B // ADC sample lags by 247.5
+#define ADC_SPC_PHASE_270 0x0000000C // ADC sample lags by 270.0
+#define ADC_SPC_PHASE_292_5 0x0000000D // ADC sample lags by 292.5
+#define ADC_SPC_PHASE_315 0x0000000E // ADC sample lags by 315.0
+#define ADC_SPC_PHASE_337_5 0x0000000F // ADC sample lags by 337.5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_PSSI register.
+//
+//*****************************************************************************
+#define ADC_PSSI_GSYNC 0x80000000 // Global Synchronize
+#define ADC_PSSI_SYNCWAIT 0x08000000 // Synchronize Wait
+#define ADC_PSSI_SS3 0x00000008 // SS3 Initiate
+#define ADC_PSSI_SS2 0x00000004 // SS2 Initiate
+#define ADC_PSSI_SS1 0x00000002 // SS1 Initiate
+#define ADC_PSSI_SS0 0x00000001 // SS0 Initiate
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SAC register.
+//
+//*****************************************************************************
+#define ADC_SAC_AVG_M 0x00000007 // Hardware Averaging Control
+#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling
+#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling
+#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling
+#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling
+#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling
+#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling
+#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCISC register.
+//
+//*****************************************************************************
+#define ADC_DCISC_DCINT7 0x00000080 // Digital Comparator 7 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT6 0x00000040 // Digital Comparator 6 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT5 0x00000020 // Digital Comparator 5 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT4 0x00000010 // Digital Comparator 4 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT3 0x00000008 // Digital Comparator 3 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT2 0x00000004 // Digital Comparator 2 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT1 0x00000002 // Digital Comparator 1 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT0 0x00000001 // Digital Comparator 0 Interrupt
+ // Status and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX0 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX0_MUX7_M 0xF0000000 // 8th Sample Input Select
+#define ADC_SSMUX0_MUX6_M 0x0F000000 // 7th Sample Input Select
+#define ADC_SSMUX0_MUX5_M 0x00F00000 // 6th Sample Input Select
+#define ADC_SSMUX0_MUX4_M 0x000F0000 // 5th Sample Input Select
+#define ADC_SSMUX0_MUX3_M 0x0000F000 // 4th Sample Input Select
+#define ADC_SSMUX0_MUX2_M 0x00000F00 // 3rd Sample Input Select
+#define ADC_SSMUX0_MUX1_M 0x000000F0 // 2nd Sample Input Select
+#define ADC_SSMUX0_MUX0_M 0x0000000F // 1st Sample Input Select
+#define ADC_SSMUX0_MUX7_S 28
+#define ADC_SSMUX0_MUX6_S 24
+#define ADC_SSMUX0_MUX5_S 20
+#define ADC_SSMUX0_MUX4_S 16
+#define ADC_SSMUX0_MUX3_S 12
+#define ADC_SSMUX0_MUX2_S 8
+#define ADC_SSMUX0_MUX1_S 4
+#define ADC_SSMUX0_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL0 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL0_TS7 0x80000000 // 8th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE7 0x40000000 // 8th Sample Interrupt Enable
+#define ADC_SSCTL0_END7 0x20000000 // 8th Sample is End of Sequence
+#define ADC_SSCTL0_D7 0x10000000 // 8th Sample Diff Input Select
+#define ADC_SSCTL0_TS6 0x08000000 // 7th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE6 0x04000000 // 7th Sample Interrupt Enable
+#define ADC_SSCTL0_END6 0x02000000 // 7th Sample is End of Sequence
+#define ADC_SSCTL0_D6 0x01000000 // 7th Sample Diff Input Select
+#define ADC_SSCTL0_TS5 0x00800000 // 6th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE5 0x00400000 // 6th Sample Interrupt Enable
+#define ADC_SSCTL0_END5 0x00200000 // 6th Sample is End of Sequence
+#define ADC_SSCTL0_D5 0x00100000 // 6th Sample Diff Input Select
+#define ADC_SSCTL0_TS4 0x00080000 // 5th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE4 0x00040000 // 5th Sample Interrupt Enable
+#define ADC_SSCTL0_END4 0x00020000 // 5th Sample is End of Sequence
+#define ADC_SSCTL0_D4 0x00010000 // 5th Sample Diff Input Select
+#define ADC_SSCTL0_TS3 0x00008000 // 4th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE3 0x00004000 // 4th Sample Interrupt Enable
+#define ADC_SSCTL0_END3 0x00002000 // 4th Sample is End of Sequence
+#define ADC_SSCTL0_D3 0x00001000 // 4th Sample Diff Input Select
+#define ADC_SSCTL0_TS2 0x00000800 // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL0_IE2 0x00000400 // 3rd Sample Interrupt Enable
+#define ADC_SSCTL0_END2 0x00000200 // 3rd Sample is End of Sequence
+#define ADC_SSCTL0_D2 0x00000100 // 3rd Sample Diff Input Select
+#define ADC_SSCTL0_TS1 0x00000080 // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL0_IE1 0x00000040 // 2nd Sample Interrupt Enable
+#define ADC_SSCTL0_END1 0x00000020 // 2nd Sample is End of Sequence
+#define ADC_SSCTL0_D1 0x00000010 // 2nd Sample Diff Input Select
+#define ADC_SSCTL0_TS0 0x00000008 // 1st Sample Temp Sensor Select
+#define ADC_SSCTL0_IE0 0x00000004 // 1st Sample Interrupt Enable
+#define ADC_SSCTL0_END0 0x00000002 // 1st Sample is End of Sequence
+#define ADC_SSCTL0_D0 0x00000001 // 1st Sample Diff Input Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO0 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO0_DATA_M 0x00000FFF // Conversion Result Data
+#define ADC_SSFIFO0_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT0_FULL 0x00001000 // FIFO Full
+#define ADC_SSFSTAT0_EMPTY 0x00000100 // FIFO Empty
+#define ADC_SSFSTAT0_HPTR_M 0x000000F0 // FIFO Head Pointer
+#define ADC_SSFSTAT0_TPTR_M 0x0000000F // FIFO Tail Pointer
+#define ADC_SSFSTAT0_HPTR_S 4
+#define ADC_SSFSTAT0_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP0 register.
+//
+//*****************************************************************************
+#define ADC_SSOP0_S7DCOP 0x10000000 // Sample 7 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S6DCOP 0x01000000 // Sample 6 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S5DCOP 0x00100000 // Sample 5 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S4DCOP 0x00010000 // Sample 4 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S3DCOP 0x00001000 // Sample 3 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S2DCOP 0x00000100 // Sample 2 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S1DCOP 0x00000010 // Sample 1 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S0DCOP 0x00000001 // Sample 0 Digital Comparator
+ // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC0 register.
+//
+//*****************************************************************************
+#define ADC_SSDC0_S7DCSEL_M 0xF0000000 // Sample 7 Digital Comparator
+ // Select
+#define ADC_SSDC0_S6DCSEL_M 0x0F000000 // Sample 6 Digital Comparator
+ // Select
+#define ADC_SSDC0_S5DCSEL_M 0x00F00000 // Sample 5 Digital Comparator
+ // Select
+#define ADC_SSDC0_S4DCSEL_M 0x000F0000 // Sample 4 Digital Comparator
+ // Select
+#define ADC_SSDC0_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator
+ // Select
+#define ADC_SSDC0_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator
+ // Select
+#define ADC_SSDC0_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator
+ // Select
+#define ADC_SSDC0_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
+ // Select
+#define ADC_SSDC0_S6DCSEL_S 24
+#define ADC_SSDC0_S5DCSEL_S 20
+#define ADC_SSDC0_S4DCSEL_S 16
+#define ADC_SSDC0_S3DCSEL_S 12
+#define ADC_SSDC0_S2DCSEL_S 8
+#define ADC_SSDC0_S1DCSEL_S 4
+#define ADC_SSDC0_S0DCSEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX1 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX1_MUX3_M 0x0000F000 // 4th Sample Input Select
+#define ADC_SSMUX1_MUX2_M 0x00000F00 // 3rd Sample Input Select
+#define ADC_SSMUX1_MUX1_M 0x000000F0 // 2nd Sample Input Select
+#define ADC_SSMUX1_MUX0_M 0x0000000F // 1st Sample Input Select
+#define ADC_SSMUX1_MUX3_S 12
+#define ADC_SSMUX1_MUX2_S 8
+#define ADC_SSMUX1_MUX1_S 4
+#define ADC_SSMUX1_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL1 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL1_TS3 0x00008000 // 4th Sample Temp Sensor Select
+#define ADC_SSCTL1_IE3 0x00004000 // 4th Sample Interrupt Enable
+#define ADC_SSCTL1_END3 0x00002000 // 4th Sample is End of Sequence
+#define ADC_SSCTL1_D3 0x00001000 // 4th Sample Diff Input Select
+#define ADC_SSCTL1_TS2 0x00000800 // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL1_IE2 0x00000400 // 3rd Sample Interrupt Enable
+#define ADC_SSCTL1_END2 0x00000200 // 3rd Sample is End of Sequence
+#define ADC_SSCTL1_D2 0x00000100 // 3rd Sample Diff Input Select
+#define ADC_SSCTL1_TS1 0x00000080 // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL1_IE1 0x00000040 // 2nd Sample Interrupt Enable
+#define ADC_SSCTL1_END1 0x00000020 // 2nd Sample is End of Sequence
+#define ADC_SSCTL1_D1 0x00000010 // 2nd Sample Diff Input Select
+#define ADC_SSCTL1_TS0 0x00000008 // 1st Sample Temp Sensor Select
+#define ADC_SSCTL1_IE0 0x00000004 // 1st Sample Interrupt Enable
+#define ADC_SSCTL1_END0 0x00000002 // 1st Sample is End of Sequence
+#define ADC_SSCTL1_D0 0x00000001 // 1st Sample Diff Input Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO1 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO1_DATA_M 0x00000FFF // Conversion Result Data
+#define ADC_SSFIFO1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT1_FULL 0x00001000 // FIFO Full
+#define ADC_SSFSTAT1_EMPTY 0x00000100 // FIFO Empty
+#define ADC_SSFSTAT1_HPTR_M 0x000000F0 // FIFO Head Pointer
+#define ADC_SSFSTAT1_TPTR_M 0x0000000F // FIFO Tail Pointer
+#define ADC_SSFSTAT1_HPTR_S 4
+#define ADC_SSFSTAT1_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP1 register.
+//
+//*****************************************************************************
+#define ADC_SSOP1_S3DCOP 0x00001000 // Sample 3 Digital Comparator
+ // Operation
+#define ADC_SSOP1_S2DCOP 0x00000100 // Sample 2 Digital Comparator
+ // Operation
+#define ADC_SSOP1_S1DCOP 0x00000010 // Sample 1 Digital Comparator
+ // Operation
+#define ADC_SSOP1_S0DCOP 0x00000001 // Sample 0 Digital Comparator
+ // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC1 register.
+//
+//*****************************************************************************
+#define ADC_SSDC1_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator
+ // Select
+#define ADC_SSDC1_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator
+ // Select
+#define ADC_SSDC1_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator
+ // Select
+#define ADC_SSDC1_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
+ // Select
+#define ADC_SSDC1_S2DCSEL_S 8
+#define ADC_SSDC1_S1DCSEL_S 4
+#define ADC_SSDC1_S0DCSEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX2 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX2_MUX3_M 0x0000F000 // 4th Sample Input Select
+#define ADC_SSMUX2_MUX2_M 0x00000F00 // 3rd Sample Input Select
+#define ADC_SSMUX2_MUX1_M 0x000000F0 // 2nd Sample Input Select
+#define ADC_SSMUX2_MUX0_M 0x0000000F // 1st Sample Input Select
+#define ADC_SSMUX2_MUX3_S 12
+#define ADC_SSMUX2_MUX2_S 8
+#define ADC_SSMUX2_MUX1_S 4
+#define ADC_SSMUX2_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL2 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL2_TS3 0x00008000 // 4th Sample Temp Sensor Select
+#define ADC_SSCTL2_IE3 0x00004000 // 4th Sample Interrupt Enable
+#define ADC_SSCTL2_END3 0x00002000 // 4th Sample is End of Sequence
+#define ADC_SSCTL2_D3 0x00001000 // 4th Sample Diff Input Select
+#define ADC_SSCTL2_TS2 0x00000800 // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL2_IE2 0x00000400 // 3rd Sample Interrupt Enable
+#define ADC_SSCTL2_END2 0x00000200 // 3rd Sample is End of Sequence
+#define ADC_SSCTL2_D2 0x00000100 // 3rd Sample Diff Input Select
+#define ADC_SSCTL2_TS1 0x00000080 // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL2_IE1 0x00000040 // 2nd Sample Interrupt Enable
+#define ADC_SSCTL2_END1 0x00000020 // 2nd Sample is End of Sequence
+#define ADC_SSCTL2_D1 0x00000010 // 2nd Sample Diff Input Select
+#define ADC_SSCTL2_TS0 0x00000008 // 1st Sample Temp Sensor Select
+#define ADC_SSCTL2_IE0 0x00000004 // 1st Sample Interrupt Enable
+#define ADC_SSCTL2_END0 0x00000002 // 1st Sample is End of Sequence
+#define ADC_SSCTL2_D0 0x00000001 // 1st Sample Diff Input Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO2 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO2_DATA_M 0x00000FFF // Conversion Result Data
+#define ADC_SSFIFO2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT2_FULL 0x00001000 // FIFO Full
+#define ADC_SSFSTAT2_EMPTY 0x00000100 // FIFO Empty
+#define ADC_SSFSTAT2_HPTR_M 0x000000F0 // FIFO Head Pointer
+#define ADC_SSFSTAT2_TPTR_M 0x0000000F // FIFO Tail Pointer
+#define ADC_SSFSTAT2_HPTR_S 4
+#define ADC_SSFSTAT2_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP2 register.
+//
+//*****************************************************************************
+#define ADC_SSOP2_S3DCOP 0x00001000 // Sample 3 Digital Comparator
+ // Operation
+#define ADC_SSOP2_S2DCOP 0x00000100 // Sample 2 Digital Comparator
+ // Operation
+#define ADC_SSOP2_S1DCOP 0x00000010 // Sample 1 Digital Comparator
+ // Operation
+#define ADC_SSOP2_S0DCOP 0x00000001 // Sample 0 Digital Comparator
+ // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC2 register.
+//
+//*****************************************************************************
+#define ADC_SSDC2_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator
+ // Select
+#define ADC_SSDC2_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator
+ // Select
+#define ADC_SSDC2_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator
+ // Select
+#define ADC_SSDC2_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
+ // Select
+#define ADC_SSDC2_S2DCSEL_S 8
+#define ADC_SSDC2_S1DCSEL_S 4
+#define ADC_SSDC2_S0DCSEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX3 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX3_MUX0_M 0x0000000F // 1st Sample Input Select
+#define ADC_SSMUX3_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL3 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL3_TS0 0x00000008 // 1st Sample Temp Sensor Select
+#define ADC_SSCTL3_IE0 0x00000004 // 1st Sample Interrupt Enable
+#define ADC_SSCTL3_END0 0x00000002 // 1st Sample is End of Sequence
+#define ADC_SSCTL3_D0 0x00000001 // 1st Sample Diff Input Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO3 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO3_DATA_M 0x00000FFF // Conversion Result Data
+#define ADC_SSFIFO3_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT3_FULL 0x00001000 // FIFO Full
+#define ADC_SSFSTAT3_EMPTY 0x00000100 // FIFO Empty
+#define ADC_SSFSTAT3_HPTR_M 0x000000F0 // FIFO Head Pointer
+#define ADC_SSFSTAT3_TPTR_M 0x0000000F // FIFO Tail Pointer
+#define ADC_SSFSTAT3_HPTR_S 4
+#define ADC_SSFSTAT3_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP3 register.
+//
+//*****************************************************************************
+#define ADC_SSOP3_S0DCOP 0x00000001 // Sample 0 Digital Comparator
+ // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC3 register.
+//
+//*****************************************************************************
+#define ADC_SSDC3_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
+ // Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCRIC register.
+//
+//*****************************************************************************
+#define ADC_DCRIC_DCTRIG7 0x00800000 // Digital Comparator Trigger 7
+#define ADC_DCRIC_DCTRIG6 0x00400000 // Digital Comparator Trigger 6
+#define ADC_DCRIC_DCTRIG5 0x00200000 // Digital Comparator Trigger 5
+#define ADC_DCRIC_DCTRIG4 0x00100000 // Digital Comparator Trigger 4
+#define ADC_DCRIC_DCTRIG3 0x00080000 // Digital Comparator Trigger 3
+#define ADC_DCRIC_DCTRIG2 0x00040000 // Digital Comparator Trigger 2
+#define ADC_DCRIC_DCTRIG1 0x00020000 // Digital Comparator Trigger 1
+#define ADC_DCRIC_DCTRIG0 0x00010000 // Digital Comparator Trigger 0
+#define ADC_DCRIC_DCINT7 0x00000080 // Digital Comparator Interrupt 7
+#define ADC_DCRIC_DCINT6 0x00000040 // Digital Comparator Interrupt 6
+#define ADC_DCRIC_DCINT5 0x00000020 // Digital Comparator Interrupt 5
+#define ADC_DCRIC_DCINT4 0x00000010 // Digital Comparator Interrupt 4
+#define ADC_DCRIC_DCINT3 0x00000008 // Digital Comparator Interrupt 3
+#define ADC_DCRIC_DCINT2 0x00000004 // Digital Comparator Interrupt 2
+#define ADC_DCRIC_DCINT1 0x00000002 // Digital Comparator Interrupt 1
+#define ADC_DCRIC_DCINT0 0x00000001 // Digital Comparator Interrupt 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL0 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL0_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL0_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL0_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL0_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL0_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL0_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL0_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL0_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL0_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL0_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL1 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL1_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL1_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL1_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL1_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL1_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL1_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL1_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL1_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL1_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL1_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL2 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL2_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL2_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL2_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL2_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL2_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL2_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL2_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL2_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL2_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL2_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL3 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL3_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL3_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL3_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL3_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL3_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL3_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL3_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL3_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL3_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL3_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL4 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL4_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL4_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL4_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL4_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL4_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL4_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL4_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL4_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL4_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL4_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL5 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL5_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL5_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL5_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL5_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL5_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL5_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL5_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL5_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL5_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL5_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL6 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL6_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL6_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL6_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL6_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL6_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL6_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL6_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL6_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL6_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL6_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL7 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL7_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL7_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL7_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL7_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL7_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL7_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL7_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL7_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL7_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL7_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP0 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP0_COMP1_M 0x0FFF0000 // Compare 1
+#define ADC_DCCMP0_COMP0_M 0x00000FFF // Compare 0
+#define ADC_DCCMP0_COMP1_S 16
+#define ADC_DCCMP0_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP1 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP1_COMP1_M 0x0FFF0000 // Compare 1
+#define ADC_DCCMP1_COMP0_M 0x00000FFF // Compare 0
+#define ADC_DCCMP1_COMP1_S 16
+#define ADC_DCCMP1_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP2 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP2_COMP1_M 0x0FFF0000 // Compare 1
+#define ADC_DCCMP2_COMP0_M 0x00000FFF // Compare 0
+#define ADC_DCCMP2_COMP1_S 16
+#define ADC_DCCMP2_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP3 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP3_COMP1_M 0x0FFF0000 // Compare 1
+#define ADC_DCCMP3_COMP0_M 0x00000FFF // Compare 0
+#define ADC_DCCMP3_COMP1_S 16
+#define ADC_DCCMP3_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP4 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP4_COMP1_M 0x0FFF0000 // Compare 1
+#define ADC_DCCMP4_COMP0_M 0x00000FFF // Compare 0
+#define ADC_DCCMP4_COMP1_S 16
+#define ADC_DCCMP4_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP5 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP5_COMP1_M 0x0FFF0000 // Compare 1
+#define ADC_DCCMP5_COMP0_M 0x00000FFF // Compare 0
+#define ADC_DCCMP5_COMP1_S 16
+#define ADC_DCCMP5_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP6 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP6_COMP1_M 0x0FFF0000 // Compare 1
+#define ADC_DCCMP6_COMP0_M 0x00000FFF // Compare 0
+#define ADC_DCCMP6_COMP1_S 16
+#define ADC_DCCMP6_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP7 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP7_COMP1_M 0x0FFF0000 // Compare 1
+#define ADC_DCCMP7_COMP0_M 0x00000FFF // Compare 0
+#define ADC_DCCMP7_COMP1_S 16
+#define ADC_DCCMP7_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_PP register.
+//
+//*****************************************************************************
+#define ADC_PP_TS 0x00800000 // Temperature Sensor
+#define ADC_PP_RSL_M 0x007C0000 // Resolution
+#define ADC_PP_TYPE_M 0x00030000 // ADC Architecture
+#define ADC_PP_TYPE_SAR 0x00000000 // SAR
+#define ADC_PP_DC_M 0x0000FC00 // Digital Comparator Count
+#define ADC_PP_CH_M 0x000003F0 // ADC Channel Count
+#define ADC_PP_MSR_M 0x0000000F // Maximum ADC Sample Rate
+#define ADC_PP_MSR_125K 0x00000001 // 125 ksps
+#define ADC_PP_MSR_250K 0x00000003 // 250 ksps
+#define ADC_PP_MSR_500K 0x00000005 // 500 ksps
+#define ADC_PP_MSR_1M 0x00000007 // 1 Msps
+#define ADC_PP_RSL_S 18
+#define ADC_PP_DC_S 10
+#define ADC_PP_CH_S 4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_PC register.
+//
+//*****************************************************************************
+#define ADC_PC_SR_M 0x0000000F // ADC Sample Rate
+#define ADC_PC_SR_125K 0x00000001 // 125 ksps
+#define ADC_PC_SR_250K 0x00000003 // 250 ksps
+#define ADC_PC_SR_500K 0x00000005 // 500 ksps
+#define ADC_PC_SR_1M 0x00000007 // 1 Msps
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_CC register.
+//
+//*****************************************************************************
+#define ADC_CC_CS_M 0x0000000F // ADC Clock Source
+#define ADC_CC_CS_SYSPLL 0x00000000 // Either the system clock (if the
+ // PLL bypass is in effect) or the
+ // 16 MHz clock derived from PLL /
+ // 25 (default)
+#define ADC_CC_CS_PIOSC 0x00000001 // PIOSC
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACMIS register.
+//
+//*****************************************************************************
+#define COMP_ACMIS_IN1 0x00000002 // Comparator 1 Masked Interrupt
+ // Status
+#define COMP_ACMIS_IN0 0x00000001 // Comparator 0 Masked Interrupt
+ // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACRIS register.
+//
+//*****************************************************************************
+#define COMP_ACRIS_IN1 0x00000002 // Comparator 1 Interrupt Status
+#define COMP_ACRIS_IN0 0x00000001 // Comparator 0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACINTEN register.
+//
+//*****************************************************************************
+#define COMP_ACINTEN_IN1 0x00000002 // Comparator 1 Interrupt Enable
+#define COMP_ACINTEN_IN0 0x00000001 // Comparator 0 Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACREFCTL
+// register.
+//
+//*****************************************************************************
+#define COMP_ACREFCTL_EN 0x00000200 // Resistor Ladder Enable
+#define COMP_ACREFCTL_RNG 0x00000100 // Resistor Ladder Range
+#define COMP_ACREFCTL_VREF_M 0x0000000F // Resistor Ladder Voltage Ref
+#define COMP_ACREFCTL_VREF_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT0 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT0_OVAL 0x00000002 // Comparator Output Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL0 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL0_TOEN 0x00000800 // Trigger Output Enable
+#define COMP_ACCTL0_ASRCP_M 0x00000600 // Analog Source Positive
+#define COMP_ACCTL0_ASRCP_PIN 0x00000000 // Pin value of Cn+
+#define COMP_ACCTL0_ASRCP_PIN0 0x00000200 // Pin value of C0+
+#define COMP_ACCTL0_ASRCP_REF 0x00000400 // Internal voltage reference
+#define COMP_ACCTL0_TSLVAL 0x00000080 // Trigger Sense Level Value
+#define COMP_ACCTL0_TSEN_M 0x00000060 // Trigger Sense
+#define COMP_ACCTL0_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
+#define COMP_ACCTL0_TSEN_FALL 0x00000020 // Falling edge
+#define COMP_ACCTL0_TSEN_RISE 0x00000040 // Rising edge
+#define COMP_ACCTL0_TSEN_BOTH 0x00000060 // Either edge
+#define COMP_ACCTL0_ISLVAL 0x00000010 // Interrupt Sense Level Value
+#define COMP_ACCTL0_ISEN_M 0x0000000C // Interrupt Sense
+#define COMP_ACCTL0_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
+#define COMP_ACCTL0_ISEN_FALL 0x00000004 // Falling edge
+#define COMP_ACCTL0_ISEN_RISE 0x00000008 // Rising edge
+#define COMP_ACCTL0_ISEN_BOTH 0x0000000C // Either edge
+#define COMP_ACCTL0_CINV 0x00000002 // Comparator Output Invert
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT1 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT1_OVAL 0x00000002 // Comparator Output Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL1 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL1_TOEN 0x00000800 // Trigger Output Enable
+#define COMP_ACCTL1_ASRCP_M 0x00000600 // Analog Source Positive
+#define COMP_ACCTL1_ASRCP_PIN 0x00000000 // Pin value of Cn+
+#define COMP_ACCTL1_ASRCP_PIN0 0x00000200 // Pin value of C0+
+#define COMP_ACCTL1_ASRCP_REF 0x00000400 // Internal voltage reference
+ // (VIREF)
+#define COMP_ACCTL1_TSLVAL 0x00000080 // Trigger Sense Level Value
+#define COMP_ACCTL1_TSEN_M 0x00000060 // Trigger Sense
+#define COMP_ACCTL1_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
+#define COMP_ACCTL1_TSEN_FALL 0x00000020 // Falling edge
+#define COMP_ACCTL1_TSEN_RISE 0x00000040 // Rising edge
+#define COMP_ACCTL1_TSEN_BOTH 0x00000060 // Either edge
+#define COMP_ACCTL1_ISLVAL 0x00000010 // Interrupt Sense Level Value
+#define COMP_ACCTL1_ISEN_M 0x0000000C // Interrupt Sense
+#define COMP_ACCTL1_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
+#define COMP_ACCTL1_ISEN_FALL 0x00000004 // Falling edge
+#define COMP_ACCTL1_ISEN_RISE 0x00000008 // Rising edge
+#define COMP_ACCTL1_ISEN_BOTH 0x0000000C // Either edge
+#define COMP_ACCTL1_CINV 0x00000002 // Comparator Output Invert
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_PP register.
+//
+//*****************************************************************************
+#define COMP_PP_C2O 0x00040000 // Comparator Output 2 Present
+#define COMP_PP_C1O 0x00020000 // Comparator Output 1 Present
+#define COMP_PP_C0O 0x00010000 // Comparator Output 0 Present
+#define COMP_PP_CMP2 0x00000004 // Comparator 2 Present
+#define COMP_PP_CMP1 0x00000002 // Comparator 1 Present
+#define COMP_PP_CMP0 0x00000001 // Comparator 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_CTL register.
+//
+//*****************************************************************************
+#define CAN_CTL_TEST 0x00000080 // Test Mode Enable
+#define CAN_CTL_CCE 0x00000040 // Configuration Change Enable
+#define CAN_CTL_DAR 0x00000020 // Disable Automatic-Retransmission
+#define CAN_CTL_EIE 0x00000008 // Error Interrupt Enable
+#define CAN_CTL_SIE 0x00000004 // Status Interrupt Enable
+#define CAN_CTL_IE 0x00000002 // CAN Interrupt Enable
+#define CAN_CTL_INIT 0x00000001 // Initialization
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_STS register.
+//
+//*****************************************************************************
+#define CAN_STS_BOFF 0x00000080 // Bus-Off Status
+#define CAN_STS_EWARN 0x00000040 // Warning Status
+#define CAN_STS_EPASS 0x00000020 // Error Passive
+#define CAN_STS_RXOK 0x00000010 // Received a Message Successfully
+#define CAN_STS_TXOK 0x00000008 // Transmitted a Message
+ // Successfully
+#define CAN_STS_LEC_M 0x00000007 // Last Error Code
+#define CAN_STS_LEC_NONE 0x00000000 // No Error
+#define CAN_STS_LEC_STUFF 0x00000001 // Stuff Error
+#define CAN_STS_LEC_FORM 0x00000002 // Format Error
+#define CAN_STS_LEC_ACK 0x00000003 // ACK Error
+#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 Error
+#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 Error
+#define CAN_STS_LEC_CRC 0x00000006 // CRC Error
+#define CAN_STS_LEC_NOEVENT 0x00000007 // No Event
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_ERR register.
+//
+//*****************************************************************************
+#define CAN_ERR_RP 0x00008000 // Received Error Passive
+#define CAN_ERR_REC_M 0x00007F00 // Receive Error Counter
+#define CAN_ERR_TEC_M 0x000000FF // Transmit Error Counter
+#define CAN_ERR_REC_S 8
+#define CAN_ERR_TEC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_BIT register.
+//
+//*****************************************************************************
+#define CAN_BIT_TSEG2_M 0x00007000 // Time Segment after Sample Point
+#define CAN_BIT_TSEG1_M 0x00000F00 // Time Segment Before Sample Point
+#define CAN_BIT_SJW_M 0x000000C0 // (Re)Synchronization Jump Width
+#define CAN_BIT_BRP_M 0x0000003F // Baud Rate Prescaler
+#define CAN_BIT_TSEG2_S 12
+#define CAN_BIT_TSEG1_S 8
+#define CAN_BIT_SJW_S 6
+#define CAN_BIT_BRP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_INT register.
+//
+//*****************************************************************************
+#define CAN_INT_INTID_M 0x0000FFFF // Interrupt Identifier
+#define CAN_INT_INTID_NONE 0x00000000 // No interrupt pending
+#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TST register.
+//
+//*****************************************************************************
+#define CAN_TST_RX 0x00000080 // Receive Observation
+#define CAN_TST_TX_M 0x00000060 // Transmit Control
+#define CAN_TST_TX_CANCTL 0x00000000 // CAN Module Control
+#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point
+#define CAN_TST_TX_DOMINANT 0x00000040 // Driven Low
+#define CAN_TST_TX_RECESSIVE 0x00000060 // Driven High
+#define CAN_TST_LBACK 0x00000010 // Loopback Mode
+#define CAN_TST_SILENT 0x00000008 // Silent Mode
+#define CAN_TST_BASIC 0x00000004 // Basic Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_BRPE register.
+//
+//*****************************************************************************
+#define CAN_BRPE_BRPE_M 0x0000000F // Baud Rate Prescaler Extension
+#define CAN_BRPE_BRPE_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1CRQ register.
+//
+//*****************************************************************************
+#define CAN_IF1CRQ_BUSY 0x00008000 // Busy Flag
+#define CAN_IF1CRQ_MNUM_M 0x0000003F // Message Number
+#define CAN_IF1CRQ_MNUM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1CMSK register.
+//
+//*****************************************************************************
+#define CAN_IF1CMSK_WRNRD 0x00000080 // Write, Not Read
+#define CAN_IF1CMSK_MASK 0x00000040 // Access Mask Bits
+#define CAN_IF1CMSK_ARB 0x00000020 // Access Arbitration Bits
+#define CAN_IF1CMSK_CONTROL 0x00000010 // Access Control Bits
+#define CAN_IF1CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit
+#define CAN_IF1CMSK_NEWDAT 0x00000004 // Access New Data
+#define CAN_IF1CMSK_TXRQST 0x00000004 // Access Transmission Request
+#define CAN_IF1CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3
+#define CAN_IF1CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MSK1 register.
+//
+//*****************************************************************************
+#define CAN_IF1MSK1_IDMSK_M 0x0000FFFF // Identifier Mask
+#define CAN_IF1MSK1_IDMSK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MSK2 register.
+//
+//*****************************************************************************
+#define CAN_IF1MSK2_MXTD 0x00008000 // Mask Extended Identifier
+#define CAN_IF1MSK2_MDIR 0x00004000 // Mask Message Direction
+#define CAN_IF1MSK2_IDMSK_M 0x00001FFF // Identifier Mask
+#define CAN_IF1MSK2_IDMSK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1ARB1 register.
+//
+//*****************************************************************************
+#define CAN_IF1ARB1_ID_M 0x0000FFFF // Message Identifier
+#define CAN_IF1ARB1_ID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1ARB2 register.
+//
+//*****************************************************************************
+#define CAN_IF1ARB2_MSGVAL 0x00008000 // Message Valid
+#define CAN_IF1ARB2_XTD 0x00004000 // Extended Identifier
+#define CAN_IF1ARB2_DIR 0x00002000 // Message Direction
+#define CAN_IF1ARB2_ID_M 0x00001FFF // Message Identifier
+#define CAN_IF1ARB2_ID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MCTL register.
+//
+//*****************************************************************************
+#define CAN_IF1MCTL_NEWDAT 0x00008000 // New Data
+#define CAN_IF1MCTL_MSGLST 0x00004000 // Message Lost
+#define CAN_IF1MCTL_INTPND 0x00002000 // Interrupt Pending
+#define CAN_IF1MCTL_UMASK 0x00001000 // Use Acceptance Mask
+#define CAN_IF1MCTL_TXIE 0x00000800 // Transmit Interrupt Enable
+#define CAN_IF1MCTL_RXIE 0x00000400 // Receive Interrupt Enable
+#define CAN_IF1MCTL_RMTEN 0x00000200 // Remote Enable
+#define CAN_IF1MCTL_TXRQST 0x00000100 // Transmit Request
+#define CAN_IF1MCTL_EOB 0x00000080 // End of Buffer
+#define CAN_IF1MCTL_DLC_M 0x0000000F // Data Length Code
+#define CAN_IF1MCTL_DLC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DA1 register.
+//
+//*****************************************************************************
+#define CAN_IF1DA1_DATA_M 0x0000FFFF // Data
+#define CAN_IF1DA1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DA2 register.
+//
+//*****************************************************************************
+#define CAN_IF1DA2_DATA_M 0x0000FFFF // Data
+#define CAN_IF1DA2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DB1 register.
+//
+//*****************************************************************************
+#define CAN_IF1DB1_DATA_M 0x0000FFFF // Data
+#define CAN_IF1DB1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DB2 register.
+//
+//*****************************************************************************
+#define CAN_IF1DB2_DATA_M 0x0000FFFF // Data
+#define CAN_IF1DB2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2CRQ register.
+//
+//*****************************************************************************
+#define CAN_IF2CRQ_BUSY 0x00008000 // Busy Flag
+#define CAN_IF2CRQ_MNUM_M 0x0000003F // Message Number
+#define CAN_IF2CRQ_MNUM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2CMSK register.
+//
+//*****************************************************************************
+#define CAN_IF2CMSK_WRNRD 0x00000080 // Write, Not Read
+#define CAN_IF2CMSK_MASK 0x00000040 // Access Mask Bits
+#define CAN_IF2CMSK_ARB 0x00000020 // Access Arbitration Bits
+#define CAN_IF2CMSK_CONTROL 0x00000010 // Access Control Bits
+#define CAN_IF2CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit
+#define CAN_IF2CMSK_NEWDAT 0x00000004 // Access New Data
+#define CAN_IF2CMSK_TXRQST 0x00000004 // Access Transmission Request
+#define CAN_IF2CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3
+#define CAN_IF2CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MSK1 register.
+//
+//*****************************************************************************
+#define CAN_IF2MSK1_IDMSK_M 0x0000FFFF // Identifier Mask
+#define CAN_IF2MSK1_IDMSK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MSK2 register.
+//
+//*****************************************************************************
+#define CAN_IF2MSK2_MXTD 0x00008000 // Mask Extended Identifier
+#define CAN_IF2MSK2_MDIR 0x00004000 // Mask Message Direction
+#define CAN_IF2MSK2_IDMSK_M 0x00001FFF // Identifier Mask
+#define CAN_IF2MSK2_IDMSK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2ARB1 register.
+//
+//*****************************************************************************
+#define CAN_IF2ARB1_ID_M 0x0000FFFF // Message Identifier
+#define CAN_IF2ARB1_ID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2ARB2 register.
+//
+//*****************************************************************************
+#define CAN_IF2ARB2_MSGVAL 0x00008000 // Message Valid
+#define CAN_IF2ARB2_XTD 0x00004000 // Extended Identifier
+#define CAN_IF2ARB2_DIR 0x00002000 // Message Direction
+#define CAN_IF2ARB2_ID_M 0x00001FFF // Message Identifier
+#define CAN_IF2ARB2_ID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MCTL register.
+//
+//*****************************************************************************
+#define CAN_IF2MCTL_NEWDAT 0x00008000 // New Data
+#define CAN_IF2MCTL_MSGLST 0x00004000 // Message Lost
+#define CAN_IF2MCTL_INTPND 0x00002000 // Interrupt Pending
+#define CAN_IF2MCTL_UMASK 0x00001000 // Use Acceptance Mask
+#define CAN_IF2MCTL_TXIE 0x00000800 // Transmit Interrupt Enable
+#define CAN_IF2MCTL_RXIE 0x00000400 // Receive Interrupt Enable
+#define CAN_IF2MCTL_RMTEN 0x00000200 // Remote Enable
+#define CAN_IF2MCTL_TXRQST 0x00000100 // Transmit Request
+#define CAN_IF2MCTL_EOB 0x00000080 // End of Buffer
+#define CAN_IF2MCTL_DLC_M 0x0000000F // Data Length Code
+#define CAN_IF2MCTL_DLC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DA1 register.
+//
+//*****************************************************************************
+#define CAN_IF2DA1_DATA_M 0x0000FFFF // Data
+#define CAN_IF2DA1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DA2 register.
+//
+//*****************************************************************************
+#define CAN_IF2DA2_DATA_M 0x0000FFFF // Data
+#define CAN_IF2DA2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DB1 register.
+//
+//*****************************************************************************
+#define CAN_IF2DB1_DATA_M 0x0000FFFF // Data
+#define CAN_IF2DB1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DB2 register.
+//
+//*****************************************************************************
+#define CAN_IF2DB2_DATA_M 0x0000FFFF // Data
+#define CAN_IF2DB2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TXRQ1 register.
+//
+//*****************************************************************************
+#define CAN_TXRQ1_TXRQST_M 0x0000FFFF // Transmission Request Bits
+#define CAN_TXRQ1_TXRQST_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TXRQ2 register.
+//
+//*****************************************************************************
+#define CAN_TXRQ2_TXRQST_M 0x0000FFFF // Transmission Request Bits
+#define CAN_TXRQ2_TXRQST_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_NWDA1 register.
+//
+//*****************************************************************************
+#define CAN_NWDA1_NEWDAT_M 0x0000FFFF // New Data Bits
+#define CAN_NWDA1_NEWDAT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_NWDA2 register.
+//
+//*****************************************************************************
+#define CAN_NWDA2_NEWDAT_M 0x0000FFFF // New Data Bits
+#define CAN_NWDA2_NEWDAT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG1INT register.
+//
+//*****************************************************************************
+#define CAN_MSG1INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits
+#define CAN_MSG1INT_INTPND_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG2INT register.
+//
+//*****************************************************************************
+#define CAN_MSG2INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits
+#define CAN_MSG2INT_INTPND_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG1VAL register.
+//
+//*****************************************************************************
+#define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits
+#define CAN_MSG1VAL_MSGVAL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG2VAL register.
+//
+//*****************************************************************************
+#define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits
+#define CAN_MSG2VAL_MSGVAL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FADDR register.
+//
+//*****************************************************************************
+#define USB_FADDR_M 0x0000007F // Function Address
+#define USB_FADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_POWER register.
+//
+//*****************************************************************************
+#define USB_POWER_ISOUP 0x00000080 // Isochronous Update
+#define USB_POWER_SOFTCONN 0x00000040 // Soft Connect/Disconnect
+#define USB_POWER_RESET 0x00000008 // RESET Signaling
+#define USB_POWER_RESUME 0x00000004 // RESUME Signaling
+#define USB_POWER_SUSPEND 0x00000002 // SUSPEND Mode
+#define USB_POWER_PWRDNPHY 0x00000001 // Power Down PHY
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXIS register.
+//
+//*****************************************************************************
+#define USB_TXIS_EP7 0x00000080 // TX Endpoint 7 Interrupt
+#define USB_TXIS_EP6 0x00000040 // TX Endpoint 6 Interrupt
+#define USB_TXIS_EP5 0x00000020 // TX Endpoint 5 Interrupt
+#define USB_TXIS_EP4 0x00000010 // TX Endpoint 4 Interrupt
+#define USB_TXIS_EP3 0x00000008 // TX Endpoint 3 Interrupt
+#define USB_TXIS_EP2 0x00000004 // TX Endpoint 2 Interrupt
+#define USB_TXIS_EP1 0x00000002 // TX Endpoint 1 Interrupt
+#define USB_TXIS_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXIS register.
+//
+//*****************************************************************************
+#define USB_RXIS_EP7 0x00000080 // RX Endpoint 7 Interrupt
+#define USB_RXIS_EP6 0x00000040 // RX Endpoint 6 Interrupt
+#define USB_RXIS_EP5 0x00000020 // RX Endpoint 5 Interrupt
+#define USB_RXIS_EP4 0x00000010 // RX Endpoint 4 Interrupt
+#define USB_RXIS_EP3 0x00000008 // RX Endpoint 3 Interrupt
+#define USB_RXIS_EP2 0x00000004 // RX Endpoint 2 Interrupt
+#define USB_RXIS_EP1 0x00000002 // RX Endpoint 1 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXIE register.
+//
+//*****************************************************************************
+#define USB_TXIE_EP7 0x00000080 // TX Endpoint 7 Interrupt Enable
+#define USB_TXIE_EP6 0x00000040 // TX Endpoint 6 Interrupt Enable
+#define USB_TXIE_EP5 0x00000020 // TX Endpoint 5 Interrupt Enable
+#define USB_TXIE_EP4 0x00000010 // TX Endpoint 4 Interrupt Enable
+#define USB_TXIE_EP3 0x00000008 // TX Endpoint 3 Interrupt Enable
+#define USB_TXIE_EP2 0x00000004 // TX Endpoint 2 Interrupt Enable
+#define USB_TXIE_EP1 0x00000002 // TX Endpoint 1 Interrupt Enable
+#define USB_TXIE_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt
+ // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXIE register.
+//
+//*****************************************************************************
+#define USB_RXIE_EP7 0x00000080 // RX Endpoint 7 Interrupt Enable
+#define USB_RXIE_EP6 0x00000040 // RX Endpoint 6 Interrupt Enable
+#define USB_RXIE_EP5 0x00000020 // RX Endpoint 5 Interrupt Enable
+#define USB_RXIE_EP4 0x00000010 // RX Endpoint 4 Interrupt Enable
+#define USB_RXIE_EP3 0x00000008 // RX Endpoint 3 Interrupt Enable
+#define USB_RXIE_EP2 0x00000004 // RX Endpoint 2 Interrupt Enable
+#define USB_RXIE_EP1 0x00000002 // RX Endpoint 1 Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IS register.
+//
+//*****************************************************************************
+#define USB_IS_DISCON 0x00000020 // Session Disconnect
+#define USB_IS_SOF 0x00000008 // Start of Frame
+#define USB_IS_RESET 0x00000004 // RESET Signaling Detected
+#define USB_IS_RESUME 0x00000002 // RESUME Signaling Detected
+#define USB_IS_SUSPEND 0x00000001 // SUSPEND Signaling Detected
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IE register.
+//
+//*****************************************************************************
+#define USB_IE_DISCON 0x00000020 // Enable Disconnect Interrupt
+#define USB_IE_SOF 0x00000008 // Enable Start-of-Frame Interrupt
+#define USB_IE_RESET 0x00000004 // Enable RESET Interrupt
+#define USB_IE_RESUME 0x00000002 // Enable RESUME Interrupt
+#define USB_IE_SUSPND 0x00000001 // Enable SUSPEND Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FRAME register.
+//
+//*****************************************************************************
+#define USB_FRAME_M 0x000007FF // Frame Number
+#define USB_FRAME_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPIDX register.
+//
+//*****************************************************************************
+#define USB_EPIDX_EPIDX_M 0x0000000F // Endpoint Index
+#define USB_EPIDX_EPIDX_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TEST register.
+//
+//*****************************************************************************
+#define USB_TEST_FIFOACC 0x00000040 // FIFO Access
+#define USB_TEST_FORCEFS 0x00000020 // Force Full-Speed Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO0 register.
+//
+//*****************************************************************************
+#define USB_FIFO0_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO0_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO1 register.
+//
+//*****************************************************************************
+#define USB_FIFO1_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO1_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO2 register.
+//
+//*****************************************************************************
+#define USB_FIFO2_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO2_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO3 register.
+//
+//*****************************************************************************
+#define USB_FIFO3_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO3_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO4 register.
+//
+//*****************************************************************************
+#define USB_FIFO4_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO4_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO5 register.
+//
+//*****************************************************************************
+#define USB_FIFO5_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO5_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO6 register.
+//
+//*****************************************************************************
+#define USB_FIFO6_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO6_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO7 register.
+//
+//*****************************************************************************
+#define USB_FIFO7_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO7_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFIFOSZ register.
+//
+//*****************************************************************************
+#define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support
+#define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size
+#define USB_TXFIFOSZ_SIZE_8 0x00000000 // 8
+#define USB_TXFIFOSZ_SIZE_16 0x00000001 // 16
+#define USB_TXFIFOSZ_SIZE_32 0x00000002 // 32
+#define USB_TXFIFOSZ_SIZE_64 0x00000003 // 64
+#define USB_TXFIFOSZ_SIZE_128 0x00000004 // 128
+#define USB_TXFIFOSZ_SIZE_256 0x00000005 // 256
+#define USB_TXFIFOSZ_SIZE_512 0x00000006 // 512
+#define USB_TXFIFOSZ_SIZE_1024 0x00000007 // 1024
+#define USB_TXFIFOSZ_SIZE_2048 0x00000008 // 2048
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFIFOSZ register.
+//
+//*****************************************************************************
+#define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support
+#define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size
+#define USB_RXFIFOSZ_SIZE_8 0x00000000 // 8
+#define USB_RXFIFOSZ_SIZE_16 0x00000001 // 16
+#define USB_RXFIFOSZ_SIZE_32 0x00000002 // 32
+#define USB_RXFIFOSZ_SIZE_64 0x00000003 // 64
+#define USB_RXFIFOSZ_SIZE_128 0x00000004 // 128
+#define USB_RXFIFOSZ_SIZE_256 0x00000005 // 256
+#define USB_RXFIFOSZ_SIZE_512 0x00000006 // 512
+#define USB_RXFIFOSZ_SIZE_1024 0x00000007 // 1024
+#define USB_RXFIFOSZ_SIZE_2048 0x00000008 // 2048
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFIFOADD
+// register.
+//
+//*****************************************************************************
+#define USB_TXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address
+#define USB_TXFIFOADD_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFIFOADD
+// register.
+//
+//*****************************************************************************
+#define USB_RXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address
+#define USB_RXFIFOADD_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CONTIM register.
+//
+//*****************************************************************************
+#define USB_CONTIM_WTCON_M 0x000000F0 // Connect Wait
+#define USB_CONTIM_WTID_M 0x0000000F // Wait ID
+#define USB_CONTIM_WTCON_S 4
+#define USB_CONTIM_WTID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FSEOF register.
+//
+//*****************************************************************************
+#define USB_FSEOF_FSEOFG_M 0x000000FF // Full-Speed End-of-Frame Gap
+#define USB_FSEOF_FSEOFG_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_LSEOF register.
+//
+//*****************************************************************************
+#define USB_LSEOF_LSEOFG_M 0x000000FF // Low-Speed End-of-Frame Gap
+#define USB_LSEOF_LSEOFG_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CSRL0 register.
+//
+//*****************************************************************************
+#define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear
+#define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear
+#define USB_CSRL0_STALL 0x00000020 // Send Stall
+#define USB_CSRL0_SETEND 0x00000010 // Setup End
+#define USB_CSRL0_DATAEND 0x00000008 // Data End
+#define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled
+#define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready
+#define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CSRH0 register.
+//
+//*****************************************************************************
+#define USB_CSRH0_FLUSH 0x00000001 // Flush FIFO
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_COUNT0 register.
+//
+//*****************************************************************************
+#define USB_COUNT0_COUNT_M 0x0000007F // FIFO Count
+#define USB_COUNT0_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP1 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP1_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL1 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL1_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL1_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL1_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL1_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL1_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL1_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL1_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH1 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH1_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH1_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH1_MODE 0x00000020 // Mode
+#define USB_TXCSRH1_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH1_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH1_DMAMOD 0x00000004 // DMA Request Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP1 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP1_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL1 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL1_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL1_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL1_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL1_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL1_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL1_OVER 0x00000004 // Overrun
+#define USB_RXCSRL1_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL1_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH1 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH1_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH1_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH1_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH1_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH1_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH1_DMAMOD 0x00000008 // DMA Request Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT1 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT1_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT1_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP2 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP2_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL2 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL2_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL2_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL2_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL2_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL2_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL2_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL2_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH2 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH2_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH2_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH2_MODE 0x00000020 // Mode
+#define USB_TXCSRH2_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH2_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH2_DMAMOD 0x00000004 // DMA Request Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP2 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP2_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL2 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL2_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL2_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL2_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL2_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL2_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL2_OVER 0x00000004 // Overrun
+#define USB_RXCSRL2_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL2_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH2 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH2_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH2_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH2_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH2_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH2_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH2_DMAMOD 0x00000008 // DMA Request Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT2 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT2_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT2_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP3 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP3_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL3 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL3_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL3_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL3_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL3_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL3_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL3_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL3_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH3 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH3_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH3_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH3_MODE 0x00000020 // Mode
+#define USB_TXCSRH3_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH3_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH3_DMAMOD 0x00000004 // DMA Request Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP3 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP3_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL3 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL3_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL3_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL3_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL3_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL3_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL3_OVER 0x00000004 // Overrun
+#define USB_RXCSRL3_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL3_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH3 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH3_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH3_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH3_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH3_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH3_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH3_DMAMOD 0x00000008 // DMA Request Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT3 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT3_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT3_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP4 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP4_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL4 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL4_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL4_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL4_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL4_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL4_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL4_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL4_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH4 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH4_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH4_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH4_MODE 0x00000020 // Mode
+#define USB_TXCSRH4_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH4_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH4_DMAMOD 0x00000004 // DMA Request Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP4 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP4_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL4 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL4_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL4_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL4_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL4_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL4_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL4_OVER 0x00000004 // Overrun
+#define USB_RXCSRL4_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL4_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH4 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH4_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH4_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH4_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH4_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH4_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH4_DMAMOD 0x00000008 // DMA Request Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT4 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT4_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT4_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP5 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP5_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL5 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL5_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL5_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL5_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL5_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL5_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL5_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL5_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH5 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH5_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH5_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH5_MODE 0x00000020 // Mode
+#define USB_TXCSRH5_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH5_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH5_DMAMOD 0x00000004 // DMA Request Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP5 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP5_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL5 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL5_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL5_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL5_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL5_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL5_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL5_OVER 0x00000004 // Overrun
+#define USB_RXCSRL5_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL5_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH5 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH5_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH5_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH5_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH5_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH5_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH5_DMAMOD 0x00000008 // DMA Request Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT5 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT5_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT5_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP6 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP6_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL6 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL6_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL6_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL6_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL6_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL6_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL6_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL6_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH6 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH6_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH6_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH6_MODE 0x00000020 // Mode
+#define USB_TXCSRH6_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH6_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH6_DMAMOD 0x00000004 // DMA Request Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP6 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP6_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL6 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL6_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL6_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL6_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL6_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL6_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL6_OVER 0x00000004 // Overrun
+#define USB_RXCSRL6_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL6_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH6 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH6_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH6_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH6_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH6_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH6_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH6_DMAMOD 0x00000008 // DMA Request Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT6 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT6_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT6_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP7 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP7_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL7 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL7_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL7_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL7_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL7_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL7_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL7_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL7_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH7 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH7_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH7_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH7_MODE 0x00000020 // Mode
+#define USB_TXCSRH7_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH7_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH7_DMAMOD 0x00000004 // DMA Request Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP7 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP7_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL7 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL7_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL7_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL7_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL7_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL7_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL7_OVER 0x00000004 // Overrun
+#define USB_RXCSRL7_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL7_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH7 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH7_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH7_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH7_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH7_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH7_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH7_DMAMOD 0x00000008 // DMA Request Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT7 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT7_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT7_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS
+// register.
+//
+//*****************************************************************************
+#define USB_RXDPKTBUFDIS_EP7 0x00000080 // EP7 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP6 0x00000040 // EP6 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP5 0x00000020 // EP5 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP4 0x00000010 // EP4 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP3 0x00000008 // EP3 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP2 0x00000004 // EP2 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP1 0x00000002 // EP1 RX Double-Packet Buffer
+ // Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS
+// register.
+//
+//*****************************************************************************
+#define USB_TXDPKTBUFDIS_EP7 0x00000080 // EP7 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP6 0x00000040 // EP6 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP5 0x00000020 // EP5 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP4 0x00000010 // EP4 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP3 0x00000008 // EP3 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP2 0x00000004 // EP2 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP1 0x00000002 // EP1 TX Double-Packet Buffer
+ // Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRRIS register.
+//
+//*****************************************************************************
+#define USB_DRRIS_RESUME 0x00000001 // RESUME Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRIM register.
+//
+//*****************************************************************************
+#define USB_DRIM_RESUME 0x00000001 // RESUME Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRISC register.
+//
+//*****************************************************************************
+#define USB_DRISC_RESUME 0x00000001 // RESUME Interrupt Status and
+ // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMASEL register.
+//
+//*****************************************************************************
+#define USB_DMASEL_DMACTX_M 0x00F00000 // DMA C TX Select
+#define USB_DMASEL_DMACRX_M 0x000F0000 // DMA C RX Select
+#define USB_DMASEL_DMABTX_M 0x0000F000 // DMA B TX Select
+#define USB_DMASEL_DMABRX_M 0x00000F00 // DMA B RX Select
+#define USB_DMASEL_DMAATX_M 0x000000F0 // DMA A TX Select
+#define USB_DMASEL_DMAARX_M 0x0000000F // DMA A RX Select
+#define USB_DMASEL_DMACTX_S 20
+#define USB_DMASEL_DMACRX_S 16
+#define USB_DMASEL_DMABTX_S 12
+#define USB_DMASEL_DMABRX_S 8
+#define USB_DMASEL_DMAATX_S 4
+#define USB_DMASEL_DMAARX_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_PP register.
+//
+//*****************************************************************************
+#define USB_PP_ECNT_M 0x0000FF00 // Endpoint Count
+#define USB_PP_USB_M 0x000000C0 // USB Capability
+#define USB_PP_USB_DEVICE 0x00000040 // DEVICE
+#define USB_PP_USB_HOSTDEVICE 0x00000080 // HOST
+#define USB_PP_USB_OTG 0x000000C0 // OTG
+#define USB_PP_PHY 0x00000010 // PHY Present
+#define USB_PP_TYPE_M 0x0000000F // Controller Type
+#define USB_PP_TYPE_0 0x00000000 // The first-generation USB
+ // controller
+#define USB_PP_ECNT_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EESIZE register.
+//
+//*****************************************************************************
+#define EEPROM_EESIZE_BLKCNT_M 0x07FF0000 // Number of 16-Word Blocks
+#define EEPROM_EESIZE_WORDCNT_M 0x0000FFFF // Number of 32-Bit Words
+#define EEPROM_EESIZE_BLKCNT_S 16
+#define EEPROM_EESIZE_WORDCNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEBLOCK register.
+//
+//*****************************************************************************
+#define EEPROM_EEBLOCK_BLOCK_M 0x0000FFFF // Current Block
+#define EEPROM_EEBLOCK_BLOCK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEOFFSET
+// register.
+//
+//*****************************************************************************
+#define EEPROM_EEOFFSET_OFFSET_M \
+ 0x0000000F // Current Address Offset
+#define EEPROM_EEOFFSET_OFFSET_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EERDWR register.
+//
+//*****************************************************************************
+#define EEPROM_EERDWR_VALUE_M 0xFFFFFFFF // EEPROM Read or Write Data
+#define EEPROM_EERDWR_VALUE_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EERDWRINC
+// register.
+//
+//*****************************************************************************
+#define EEPROM_EERDWRINC_VALUE_M \
+ 0xFFFFFFFF // EEPROM Read or Write Data with
+ // Increment
+#define EEPROM_EERDWRINC_VALUE_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEDONE register.
+//
+//*****************************************************************************
+#define EEPROM_EEDONE_INVPL 0x00000100 // Invalid Program Voltage Level
+#define EEPROM_EEDONE_WRBUSY 0x00000020 // Write Busy
+#define EEPROM_EEDONE_NOPERM 0x00000010 // Write Without Permission
+#define EEPROM_EEDONE_WKCOPY 0x00000008 // Working on a Copy
+#define EEPROM_EEDONE_WKERASE 0x00000004 // Working on an Erase
+#define EEPROM_EEDONE_WORKING 0x00000001 // EEPROM Working
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EESUPP register.
+//
+//*****************************************************************************
+#define EEPROM_EESUPP_PRETRY 0x00000008 // Programming Must Be Retried
+#define EEPROM_EESUPP_ERETRY 0x00000004 // Erase Must Be Retried
+#define EEPROM_EESUPP_EREQ 0x00000002 // Erase Required
+#define EEPROM_EESUPP_START 0x00000001 // Start Erase
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEUNLOCK
+// register.
+//
+//*****************************************************************************
+#define EEPROM_EEUNLOCK_UNLOCK_M \
+ 0xFFFFFFFF // EEPROM Unlock
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEPROT register.
+//
+//*****************************************************************************
+#define EEPROM_EEPROT_ACC 0x00000008 // Access Control
+#define EEPROM_EEPROT_PROT_M 0x00000007 // Protection Control
+#define EEPROM_EEPROT_PROT_RWNPW \
+ 0x00000000 // This setting is the default. If
+ // there is no password, the block
+ // is not protected and is readable
+ // and writable
+#define EEPROM_EEPROT_PROT_RWPW 0x00000001 // If there is a password, the
+ // block is readable or writable
+ // only when unlocked
+#define EEPROM_EEPROT_PROT_RONPW \
+ 0x00000002 // If there is no password, the
+ // block is readable, not writable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEPASS0 register.
+//
+//*****************************************************************************
+#define EEPROM_EEPASS0_PASS_M 0xFFFFFFFF // Password
+#define EEPROM_EEPASS0_PASS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEPASS1 register.
+//
+//*****************************************************************************
+#define EEPROM_EEPASS1_PASS_M 0xFFFFFFFF // Password
+#define EEPROM_EEPASS1_PASS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEPASS2 register.
+//
+//*****************************************************************************
+#define EEPROM_EEPASS2_PASS_M 0xFFFFFFFF // Password
+#define EEPROM_EEPASS2_PASS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEINT register.
+//
+//*****************************************************************************
+#define EEPROM_EEINT_INT 0x00000001 // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEHIDE register.
+//
+//*****************************************************************************
+#define EEPROM_EEHIDE_HN_M 0xFFFFFFFE // Hide Block
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEDBGME register.
+//
+//*****************************************************************************
+#define EEPROM_EEDBGME_KEY_M 0xFFFF0000 // Erase Key
+#define EEPROM_EEDBGME_ME 0x00000001 // Mass Erase
+#define EEPROM_EEDBGME_KEY_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_PP register.
+//
+//*****************************************************************************
+#define EEPROM_PP_SIZE_M 0x0000001F // EEPROM Size
+#define EEPROM_PP_SIZE_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSEXC_RIS register.
+//
+//*****************************************************************************
+#define SYSEXC_RIS_FPIXCRIS 0x00000020 // Floating-Point Inexact Exception
+ // Raw Interrupt Status
+#define SYSEXC_RIS_FPOFCRIS 0x00000010 // Floating-Point Overflow
+ // Exception Raw Interrupt Status
+#define SYSEXC_RIS_FPUFCRIS 0x00000008 // Floating-Point Underflow
+ // Exception Raw Interrupt Status
+#define SYSEXC_RIS_FPIOCRIS 0x00000004 // Floating-Point Invalid Operation
+ // Raw Interrupt Status
+#define SYSEXC_RIS_FPDZCRIS 0x00000002 // Floating-Point Divide By 0
+ // Exception Raw Interrupt Status
+#define SYSEXC_RIS_FPIDCRIS 0x00000001 // Floating-Point Input Denormal
+ // Exception Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSEXC_IM register.
+//
+//*****************************************************************************
+#define SYSEXC_IM_FPIXCIM 0x00000020 // Floating-Point Inexact Exception
+ // Interrupt Mask
+#define SYSEXC_IM_FPOFCIM 0x00000010 // Floating-Point Overflow
+ // Exception Interrupt Mask
+#define SYSEXC_IM_FPUFCIM 0x00000008 // Floating-Point Underflow
+ // Exception Interrupt Mask
+#define SYSEXC_IM_FPIOCIM 0x00000004 // Floating-Point Invalid Operation
+ // Interrupt Mask
+#define SYSEXC_IM_FPDZCIM 0x00000002 // Floating-Point Divide By 0
+ // Exception Interrupt Mask
+#define SYSEXC_IM_FPIDCIM 0x00000001 // Floating-Point Input Denormal
+ // Exception Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSEXC_MIS register.
+//
+//*****************************************************************************
+#define SYSEXC_MIS_FPIXCMIS 0x00000020 // Floating-Point Inexact Exception
+ // Masked Interrupt Status
+#define SYSEXC_MIS_FPOFCMIS 0x00000010 // Floating-Point Overflow
+ // Exception Masked Interrupt
+ // Status
+#define SYSEXC_MIS_FPUFCMIS 0x00000008 // Floating-Point Underflow
+ // Exception Masked Interrupt
+ // Status
+#define SYSEXC_MIS_FPIOCMIS 0x00000004 // Floating-Point Invalid Operation
+ // Masked Interrupt Status
+#define SYSEXC_MIS_FPDZCMIS 0x00000002 // Floating-Point Divide By 0
+ // Exception Masked Interrupt
+ // Status
+#define SYSEXC_MIS_FPIDCMIS 0x00000001 // Floating-Point Input Denormal
+ // Exception Masked Interrupt
+ // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSEXC_IC register.
+//
+//*****************************************************************************
+#define SYSEXC_IC_FPIXCIC 0x00000020 // Floating-Point Inexact Exception
+ // Interrupt Clear
+#define SYSEXC_IC_FPOFCIC 0x00000010 // Floating-Point Overflow
+ // Exception Interrupt Clear
+#define SYSEXC_IC_FPUFCIC 0x00000008 // Floating-Point Underflow
+ // Exception Interrupt Clear
+#define SYSEXC_IC_FPIOCIC 0x00000004 // Floating-Point Invalid Operation
+ // Interrupt Clear
+#define SYSEXC_IC_FPDZCIC 0x00000002 // Floating-Point Divide By 0
+ // Exception Interrupt Clear
+#define SYSEXC_IC_FPIDCIC 0x00000001 // Floating-Point Input Denormal
+ // Exception Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCC register.
+//
+//*****************************************************************************
+#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter
+#define HIB_RTCC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCM0 register.
+//
+//*****************************************************************************
+#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0
+#define HIB_RTCM0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCLD register.
+//
+//*****************************************************************************
+#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load
+#define HIB_RTCLD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CTL register.
+//
+//*****************************************************************************
+#define HIB_CTL_WRC 0x80000000 // Write Complete/Capable
+#define HIB_CTL_OSCDRV 0x00020000 // Oscillator Drive Capability
+#define HIB_CTL_OSCBYP 0x00010000 // Oscillator Bypass
+#define HIB_CTL_VBATSEL_M 0x00006000 // Select for Low-Battery
+ // Comparator
+#define HIB_CTL_VBATSEL_1_9V 0x00000000 // 1.9 Volts
+#define HIB_CTL_VBATSEL_2_1V 0x00002000 // 2.1 Volts (default)
+#define HIB_CTL_VBATSEL_2_3V 0x00004000 // 2.3 Volts
+#define HIB_CTL_VBATSEL_2_5V 0x00006000 // 2.5 Volts
+#define HIB_CTL_BATCHK 0x00000400 // Check Battery Status
+#define HIB_CTL_BATWKEN 0x00000200 // Wake on Low Battery
+#define HIB_CTL_VDD3ON 0x00000100 // VDD Powered
+#define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable
+#define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable
+#define HIB_CTL_LOWBATEN 0x00000020 // Low Battery Monitoring Enable
+#define HIB_CTL_PINWEN 0x00000010 // External WAKE Pin Enable
+#define HIB_CTL_RTCWEN 0x00000008 // RTC Wake-up Enable
+#define HIB_CTL_HIBREQ 0x00000002 // Hibernation Request
+#define HIB_CTL_RTCEN 0x00000001 // RTC Timer Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_IM register.
+//
+//*****************************************************************************
+#define HIB_IM_WC 0x00000010 // External Write Complete/Capable
+ // Interrupt Mask
+#define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask
+#define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt
+ // Mask
+#define HIB_IM_RTCALT0 0x00000001 // RTC Alert 0 Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RIS register.
+//
+//*****************************************************************************
+#define HIB_RIS_WC 0x00000010 // Write Complete/Capable Raw
+ // Interrupt Status
+#define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt
+ // Status
+#define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw
+ // Interrupt Status
+#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert 0 Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_MIS register.
+//
+//*****************************************************************************
+#define HIB_MIS_WC 0x00000010 // Write Complete/Capable Masked
+ // Interrupt Status
+#define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked
+ // Interrupt Status
+#define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked
+ // Interrupt Status
+#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert 0 Masked Interrupt
+ // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_IC register.
+//
+//*****************************************************************************
+#define HIB_IC_WC 0x00000010 // Write Complete/Capable Masked
+ // Interrupt Clear
+#define HIB_IC_EXTW 0x00000008 // External Wake-Up Masked
+ // Interrupt Clear
+#define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Masked
+ // Interrupt Clear
+#define HIB_IC_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt
+ // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCT register.
+//
+//*****************************************************************************
+#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value
+#define HIB_RTCT_TRIM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCSS register.
+//
+//*****************************************************************************
+#define HIB_RTCSS_RTCSSM_M 0x7FFF0000 // RTC Sub Seconds Match
+#define HIB_RTCSS_RTCSSC_M 0x00007FFF // RTC Sub Seconds Count
+#define HIB_RTCSS_RTCSSM_S 16
+#define HIB_RTCSS_RTCSSC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_DATA register.
+//
+//*****************************************************************************
+#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV Data
+#define HIB_DATA_RTD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMA register.
+//
+//*****************************************************************************
+#define FLASH_FMA_OFFSET_M 0x0003FFFF // Address Offset
+#define FLASH_FMA_OFFSET_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMD register.
+//
+//*****************************************************************************
+#define FLASH_FMD_DATA_M 0xFFFFFFFF // Data Value
+#define FLASH_FMD_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMC register.
+//
+//*****************************************************************************
+#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key
+#define FLASH_FMC_COMT 0x00000008 // Commit Register Value
+#define FLASH_FMC_MERASE 0x00000004 // Mass Erase Flash Memory
+#define FLASH_FMC_ERASE 0x00000002 // Erase a Page of Flash Memory
+#define FLASH_FMC_WRITE 0x00000001 // Write a Word into Flash Memory
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCRIS register.
+//
+//*****************************************************************************
+#define FLASH_FCRIS_PROGRIS 0x00002000 // PROGVER Raw Interrupt Status
+#define FLASH_FCRIS_ERRIS 0x00000800 // ERVER Raw Interrupt Status
+#define FLASH_FCRIS_INVDRIS 0x00000400 // Invalid Data Raw Interrupt
+ // Status
+#define FLASH_FCRIS_VOLTRIS 0x00000200 // VOLTSTAT Raw Interrupt Status
+#define FLASH_FCRIS_ERIS 0x00000004 // EEPROM Raw Interrupt Status
+#define FLASH_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt Status
+#define FLASH_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCIM register.
+//
+//*****************************************************************************
+#define FLASH_FCIM_PROGMASK 0x00002000 // PROGVER Interrupt Mask
+#define FLASH_FCIM_ERMASK 0x00000800 // ERVER Interrupt Mask
+#define FLASH_FCIM_INVDMASK 0x00000400 // Invalid Data Interrupt Mask
+#define FLASH_FCIM_VOLTMASK 0x00000200 // VOLT Interrupt Mask
+#define FLASH_FCIM_EMASK 0x00000004 // EEPROM Interrupt Mask
+#define FLASH_FCIM_PMASK 0x00000002 // Programming Interrupt Mask
+#define FLASH_FCIM_AMASK 0x00000001 // Access Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCMISC register.
+//
+//*****************************************************************************
+#define FLASH_FCMISC_PROGMISC 0x00002000 // PROGVER Masked Interrupt Status
+ // and Clear
+#define FLASH_FCMISC_ERMISC 0x00000800 // ERVER Masked Interrupt Status
+ // and Clear
+#define FLASH_FCMISC_INVDMISC 0x00000400 // Invalid Data Masked Interrupt
+ // Status and Clear
+#define FLASH_FCMISC_VOLTMISC 0x00000200 // VOLT Masked Interrupt Status and
+ // Clear
+#define FLASH_FCMISC_EMISC 0x00000004 // EEPROM Masked Interrupt Status
+ // and Clear
+#define FLASH_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt
+ // Status and Clear
+#define FLASH_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status
+ // and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMC2 register.
+//
+//*****************************************************************************
+#define FLASH_FMC2_WRKEY 0xA4420000 // FLASH write key
+#define FLASH_FMC2_WRBUF 0x00000001 // Buffered Flash Memory Write
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FWBVAL register.
+//
+//*****************************************************************************
+#define FLASH_FWBVAL_FWB_M 0xFFFFFFFF // Flash Memory Write Buffer
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FWBN register.
+//
+//*****************************************************************************
+#define FLASH_FWBN_DATA_M 0xFFFFFFFF // Data
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FSIZE register.
+//
+//*****************************************************************************
+#define FLASH_FSIZE_SIZE_M 0x0000FFFF // Flash Size
+#define FLASH_FSIZE_SIZE_8KB 0x00000003 // 8 KB of Flash
+#define FLASH_FSIZE_SIZE_16KB 0x00000007 // 16 KB of Flash
+#define FLASH_FSIZE_SIZE_32KB 0x0000000F // 32 KB of Flash
+#define FLASH_FSIZE_SIZE_64KB 0x0000001F // 64 KB of Flash
+#define FLASH_FSIZE_SIZE_96KB 0x0000002F // 96 KB of Flash
+#define FLASH_FSIZE_SIZE_128KB 0x0000003F // 128 KB of Flash
+#define FLASH_FSIZE_SIZE_192KB 0x0000005F // 192 KB of Flash
+#define FLASH_FSIZE_SIZE_256KB 0x0000007F // 256 KB of Flash
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_SSIZE register.
+//
+//*****************************************************************************
+#define FLASH_SSIZE_SIZE_M 0x0000FFFF // SRAM Size
+#define FLASH_SSIZE_SIZE_2KB 0x00000007 // 2 KB of SRAM
+#define FLASH_SSIZE_SIZE_4KB 0x0000000F // 4 KB of SRAM
+#define FLASH_SSIZE_SIZE_6KB 0x00000017 // 6 KB of SRAM
+#define FLASH_SSIZE_SIZE_8KB 0x0000001F // 8 KB of SRAM
+#define FLASH_SSIZE_SIZE_12KB 0x0000002F // 12 KB of SRAM
+#define FLASH_SSIZE_SIZE_16KB 0x0000003F // 16 KB of SRAM
+#define FLASH_SSIZE_SIZE_20KB 0x0000004F // 20 KB of SRAM
+#define FLASH_SSIZE_SIZE_24KB 0x0000005F // 24 KB of SRAM
+#define FLASH_SSIZE_SIZE_32KB 0x0000007F // 32 KB of SRAM
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_ROMSWMAP register.
+//
+//*****************************************************************************
+#define FLASH_ROMSWMAP_SAFERTOS 0x00000001 // SafeRTOS Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_RMCTL register.
+//
+//*****************************************************************************
+#define FLASH_RMCTL_BA 0x00000001 // Boot Alias
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_BOOTCFG register.
+//
+//*****************************************************************************
+#define FLASH_BOOTCFG_NW 0x80000000 // Not Written
+#define FLASH_BOOTCFG_PORT_M 0x0000E000 // Boot GPIO Port
+#define FLASH_BOOTCFG_PORT_A 0x00000000 // Port A
+#define FLASH_BOOTCFG_PORT_B 0x00002000 // Port B
+#define FLASH_BOOTCFG_PORT_C 0x00004000 // Port C
+#define FLASH_BOOTCFG_PORT_D 0x00006000 // Port D
+#define FLASH_BOOTCFG_PORT_E 0x00008000 // Port E
+#define FLASH_BOOTCFG_PORT_F 0x0000A000 // Port F
+#define FLASH_BOOTCFG_PORT_G 0x0000C000 // Port G
+#define FLASH_BOOTCFG_PORT_H 0x0000E000 // Port H
+#define FLASH_BOOTCFG_PIN_M 0x00001C00 // Boot GPIO Pin
+#define FLASH_BOOTCFG_PIN_0 0x00000000 // Pin 0
+#define FLASH_BOOTCFG_PIN_1 0x00000400 // Pin 1
+#define FLASH_BOOTCFG_PIN_2 0x00000800 // Pin 2
+#define FLASH_BOOTCFG_PIN_3 0x00000C00 // Pin 3
+#define FLASH_BOOTCFG_PIN_4 0x00001000 // Pin 4
+#define FLASH_BOOTCFG_PIN_5 0x00001400 // Pin 5
+#define FLASH_BOOTCFG_PIN_6 0x00001800 // Pin 6
+#define FLASH_BOOTCFG_PIN_7 0x00001C00 // Pin 7
+#define FLASH_BOOTCFG_POL 0x00000200 // Boot GPIO Polarity
+#define FLASH_BOOTCFG_EN 0x00000100 // Boot GPIO Enable
+#define FLASH_BOOTCFG_DBG1 0x00000002 // Debug Control 1
+#define FLASH_BOOTCFG_DBG0 0x00000001 // Debug Control 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG0 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG0_DATA_M 0xFFFFFFFF // User Data
+#define FLASH_USERREG0_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG1 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG1_DATA_M 0xFFFFFFFF // User Data
+#define FLASH_USERREG1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG2 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG2_DATA_M 0xFFFFFFFF // User Data
+#define FLASH_USERREG2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG3 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG3_DATA_M 0xFFFFFFFF // User Data
+#define FLASH_USERREG3_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DID0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID0_VER_M 0x70000000 // DID0 Version
+#define SYSCTL_DID0_VER_1 0x10000000 // Second version of the DID0
+ // register format
+#define SYSCTL_DID0_CLASS_M 0x00FF0000 // Device Class
+#define SYSCTL_DID0_CLASS_BLIZZARD \
+ 0x00050000 // Stellaris(R) Blizzard-class
+ // microcontrollers
+#define SYSCTL_DID0_MAJ_M 0x0000FF00 // Major Revision
+#define SYSCTL_DID0_MAJ_REVA 0x00000000 // Revision A (initial device)
+#define SYSCTL_DID0_MAJ_REVB 0x00000100 // Revision B (first base layer
+ // revision)
+#define SYSCTL_DID0_MAJ_REVC 0x00000200 // Revision C (second base layer
+ // revision)
+#define SYSCTL_DID0_MIN_M 0x000000FF // Minor Revision
+#define SYSCTL_DID0_MIN_0 0x00000000 // Initial device, or a major
+ // revision update
+#define SYSCTL_DID0_MIN_1 0x00000001 // First metal layer change
+#define SYSCTL_DID0_MIN_2 0x00000002 // Second metal layer change
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DID1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID1_VER_M 0xF0000000 // DID1 Version
+#define SYSCTL_DID1_VER_0 0x00000000 // Initial DID1 register format
+ // definition, indicating a
+ // Stellaris LM3Snnn device
+#define SYSCTL_DID1_VER_1 0x10000000 // Second version of the DID1
+ // register format
+#define SYSCTL_DID1_FAM_M 0x0F000000 // Family
+#define SYSCTL_DID1_FAM_STELLARIS \
+ 0x00000000 // Stellaris family of
+ // microcontollers, that is, all
+ // devices with external part
+ // numbers starting with LM3S
+#define SYSCTL_DID1_PRTNO_M 0x00FF0000 // Part Number
+#define SYSCTL_DID1_PRTNO_LM4F120H5QR \
+ 0x00040000 // LM4F120H5QR
+#define SYSCTL_DID1_PINCNT_M 0x0000E000 // Package Pin Count
+#define SYSCTL_DID1_PINCNT_28 0x00000000 // 28-pin package
+#define SYSCTL_DID1_PINCNT_48 0x00002000 // 48-pin package
+#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100-pin package
+#define SYSCTL_DID1_PINCNT_64 0x00006000 // 64-pin package
+#define SYSCTL_DID1_PINCNT_144 0x00008000 // 144-pin package
+#define SYSCTL_DID1_PINCNT_157 0x0000A000 // 157-pin package
+#define SYSCTL_DID1_TEMP_M 0x000000E0 // Temperature Range
+#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temperature range (0C
+ // to 70C)
+#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temperature range
+ // (-40C to 85C)
+#define SYSCTL_DID1_TEMP_E 0x00000040 // Extended temperature range (-40C
+ // to 105C)
+#define SYSCTL_DID1_PKG_M 0x00000018 // Package Type
+#define SYSCTL_DID1_PKG_SOIC 0x00000000 // SOIC package
+#define SYSCTL_DID1_PKG_QFP 0x00000008 // LQFP package
+#define SYSCTL_DID1_PKG_BGA 0x00000010 // BGA package
+#define SYSCTL_DID1_ROHS 0x00000004 // RoHS-Compliance
+#define SYSCTL_DID1_QUAL_M 0x00000003 // Qualification Status
+#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering Sample (unqualified)
+#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot Production (unqualified)
+#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully Qualified
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC0_SRAMSZ_M 0xFFFF0000 // SRAM Size
+#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_6KB 0x00170000 // 6 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_12KB 0x002F0000 // 12 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_20KB 0x004F0000 // 20 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_24KB 0x005F0000 // 24 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM
+#define SYSCTL_DC0_FLASHSZ_M 0x0000FFFF // Flash Size
+#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_192K 0x0000005F // 192 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of Flash
+#define SYSCTL_DC0_SRAMSZ_S 16 // SRAM size shift
+#define SYSCTL_DC0_FLASHSZ_S 0 // Flash size shift
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC1_WDT1 0x10000000 // Watchdog Timer1 Present
+#define SYSCTL_DC1_CAN1 0x02000000 // CAN Module 1 Present
+#define SYSCTL_DC1_CAN0 0x01000000 // CAN Module 0 Present
+#define SYSCTL_DC1_PWM1 0x00200000 // PWM Module 1 Present
+#define SYSCTL_DC1_PWM0 0x00100000 // PWM Module 0 Present
+#define SYSCTL_DC1_ADC1 0x00020000 // ADC Module 1 Present
+#define SYSCTL_DC1_ADC0 0x00010000 // ADC Module 0 Present
+#define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 // System Clock Divider
+#define SYSCTL_DC1_MINSYSDIV_100 \
+ 0x00001000 // Divide VCO (400MHZ) by 5 minimum
+#define SYSCTL_DC1_MINSYSDIV_66 0x00002000 // Divide VCO (400MHZ) by 2*2 + 2 =
+ // 6 minimum
+#define SYSCTL_DC1_MINSYSDIV_50 0x00003000 // Specifies a 50-MHz CPU clock
+ // with a PLL divider of 4
+#define SYSCTL_DC1_MINSYSDIV_40 0x00004000 // Specifies a 40-MHz CPU clock
+ // with a PLL divider of 5
+#define SYSCTL_DC1_MINSYSDIV_25 0x00007000 // Specifies a 25-MHz clock with a
+ // PLL divider of 8
+#define SYSCTL_DC1_MINSYSDIV_20 0x00009000 // Specifies a 20-MHz clock with a
+ // PLL divider of 10
+#define SYSCTL_DC1_ADC1SPD_M 0x00000C00 // Max ADC1 Speed
+#define SYSCTL_DC1_ADC1SPD_125K 0x00000000 // 125K samples/second
+#define SYSCTL_DC1_ADC1SPD_250K 0x00000400 // 250K samples/second
+#define SYSCTL_DC1_ADC1SPD_500K 0x00000800 // 500K samples/second
+#define SYSCTL_DC1_ADC1SPD_1M 0x00000C00 // 1M samples/second
+#define SYSCTL_DC1_ADC0SPD_M 0x00000300 // Max ADC0 Speed
+#define SYSCTL_DC1_ADC0SPD_125K 0x00000000 // 125K samples/second
+#define SYSCTL_DC1_ADC0SPD_250K 0x00000100 // 250K samples/second
+#define SYSCTL_DC1_ADC0SPD_500K 0x00000200 // 500K samples/second
+#define SYSCTL_DC1_ADC0SPD_1M 0x00000300 // 1M samples/second
+#define SYSCTL_DC1_MPU 0x00000080 // MPU Present
+#define SYSCTL_DC1_HIB 0x00000040 // Hibernation Module Present
+#define SYSCTL_DC1_TEMP 0x00000020 // Temp Sensor Present
+#define SYSCTL_DC1_PLL 0x00000010 // PLL Present
+#define SYSCTL_DC1_WDT0 0x00000008 // Watchdog Timer 0 Present
+#define SYSCTL_DC1_SWO 0x00000004 // SWO Trace Port Present
+#define SYSCTL_DC1_SWD 0x00000002 // SWD Present
+#define SYSCTL_DC1_JTAG 0x00000001 // JTAG Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC2_EPI0 0x40000000 // EPI Module 0 Present
+#define SYSCTL_DC2_I2S0 0x10000000 // I2S Module 0 Present
+#define SYSCTL_DC2_COMP2 0x04000000 // Analog Comparator 2 Present
+#define SYSCTL_DC2_COMP1 0x02000000 // Analog Comparator 1 Present
+#define SYSCTL_DC2_COMP0 0x01000000 // Analog Comparator 0 Present
+#define SYSCTL_DC2_TIMER3 0x00080000 // Timer Module 3 Present
+#define SYSCTL_DC2_TIMER2 0x00040000 // Timer Module 2 Present
+#define SYSCTL_DC2_TIMER1 0x00020000 // Timer Module 1 Present
+#define SYSCTL_DC2_TIMER0 0x00010000 // Timer Module 0 Present
+#define SYSCTL_DC2_I2C1HS 0x00008000 // I2C Module 1 Speed
+#define SYSCTL_DC2_I2C1 0x00004000 // I2C Module 1 Present
+#define SYSCTL_DC2_I2C0HS 0x00002000 // I2C Module 0 Speed
+#define SYSCTL_DC2_I2C0 0x00001000 // I2C Module 0 Present
+#define SYSCTL_DC2_QEI1 0x00000200 // QEI Module 1 Present
+#define SYSCTL_DC2_QEI0 0x00000100 // QEI Module 0 Present
+#define SYSCTL_DC2_SSI1 0x00000020 // SSI Module 1 Present
+#define SYSCTL_DC2_SSI0 0x00000010 // SSI Module 0 Present
+#define SYSCTL_DC2_UART2 0x00000004 // UART Module 2 Present
+#define SYSCTL_DC2_UART1 0x00000002 // UART Module 1 Present
+#define SYSCTL_DC2_UART0 0x00000001 // UART Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC3 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC3_32KHZ 0x80000000 // 32KHz Input Clock Available
+#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 Pin Present
+#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 Pin Present
+#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 Pin Present
+#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 Pin Present
+#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 Pin Present
+#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 Pin Present
+#define SYSCTL_DC3_ADC0AIN7 0x00800000 // ADC Module 0 AIN7 Pin Present
+#define SYSCTL_DC3_ADC0AIN6 0x00400000 // ADC Module 0 AIN6 Pin Present
+#define SYSCTL_DC3_ADC0AIN5 0x00200000 // ADC Module 0 AIN5 Pin Present
+#define SYSCTL_DC3_ADC0AIN4 0x00100000 // ADC Module 0 AIN4 Pin Present
+#define SYSCTL_DC3_ADC0AIN3 0x00080000 // ADC Module 0 AIN3 Pin Present
+#define SYSCTL_DC3_ADC0AIN2 0x00040000 // ADC Module 0 AIN2 Pin Present
+#define SYSCTL_DC3_ADC0AIN1 0x00020000 // ADC Module 0 AIN1 Pin Present
+#define SYSCTL_DC3_ADC0AIN0 0x00010000 // ADC Module 0 AIN0 Pin Present
+#define SYSCTL_DC3_PWMFAULT 0x00008000 // PWM Fault Pin Present
+#define SYSCTL_DC3_C2O 0x00004000 // C2o Pin Present
+#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ Pin Present
+#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- Pin Present
+#define SYSCTL_DC3_C1O 0x00000800 // C1o Pin Present
+#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ Pin Present
+#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- Pin Present
+#define SYSCTL_DC3_C0O 0x00000100 // C0o Pin Present
+#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ Pin Present
+#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- Pin Present
+#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 Pin Present
+#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 Pin Present
+#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 Pin Present
+#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 Pin Present
+#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 Pin Present
+#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 Pin Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC4 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC4_EPHY0 0x40000000 // Ethernet PHY Layer 0 Present
+#define SYSCTL_DC4_EMAC0 0x10000000 // Ethernet MAC Layer 0 Present
+#define SYSCTL_DC4_E1588 0x01000000 // 1588 Capable
+#define SYSCTL_DC4_PICAL 0x00040000 // PIOSC Calibrate
+#define SYSCTL_DC4_CCP7 0x00008000 // CCP7 Pin Present
+#define SYSCTL_DC4_CCP6 0x00004000 // CCP6 Pin Present
+#define SYSCTL_DC4_UDMA 0x00002000 // Micro-DMA Module Present
+#define SYSCTL_DC4_ROM 0x00001000 // Internal Code ROM Present
+#define SYSCTL_DC4_GPIOJ 0x00000100 // GPIO Port J Present
+#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO Port H Present
+#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO Port G Present
+#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO Port F Present
+#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO Port E Present
+#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO Port D Present
+#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO Port C Present
+#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO Port B Present
+#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO Port A Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC5 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC5_PWMFAULT3 0x08000000 // PWM Fault 3 Pin Present
+#define SYSCTL_DC5_PWMFAULT2 0x04000000 // PWM Fault 2 Pin Present
+#define SYSCTL_DC5_PWMFAULT1 0x02000000 // PWM Fault 1 Pin Present
+#define SYSCTL_DC5_PWMFAULT0 0x01000000 // PWM Fault 0 Pin Present
+#define SYSCTL_DC5_PWMEFLT 0x00200000 // PWM Extended Fault Active
+#define SYSCTL_DC5_PWMESYNC 0x00100000 // PWM Extended SYNC Active
+#define SYSCTL_DC5_PWM7 0x00000080 // PWM7 Pin Present
+#define SYSCTL_DC5_PWM6 0x00000040 // PWM6 Pin Present
+#define SYSCTL_DC5_PWM5 0x00000020 // PWM5 Pin Present
+#define SYSCTL_DC5_PWM4 0x00000010 // PWM4 Pin Present
+#define SYSCTL_DC5_PWM3 0x00000008 // PWM3 Pin Present
+#define SYSCTL_DC5_PWM2 0x00000004 // PWM2 Pin Present
+#define SYSCTL_DC5_PWM1 0x00000002 // PWM1 Pin Present
+#define SYSCTL_DC5_PWM0 0x00000001 // PWM0 Pin Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC6 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC6_USB0PHY 0x00000010 // USB Module 0 PHY Present
+#define SYSCTL_DC6_USB0_M 0x00000003 // USB Module 0 Present
+#define SYSCTL_DC6_USB0_DEV 0x00000001 // USB0 is Device Only
+#define SYSCTL_DC6_USB0_HOSTDEV 0x00000002 // USB is Device or Host
+#define SYSCTL_DC6_USB0_OTG 0x00000003 // USB0 is OTG
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC7 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC7_DMACH30 0x40000000 // SW
+#define SYSCTL_DC7_DMACH29 0x20000000 // I2S0_TX / CAN1_TX
+#define SYSCTL_DC7_DMACH28 0x10000000 // I2S0_RX / CAN1_RX
+#define SYSCTL_DC7_DMACH27 0x08000000 // CAN1_TX / ADC1_SS3
+#define SYSCTL_DC7_DMACH26 0x04000000 // CAN1_RX / ADC1_SS2
+#define SYSCTL_DC7_DMACH25 0x02000000 // SSI1_TX / ADC1_SS1
+#define SYSCTL_DC7_DMACH24 0x01000000 // SSI1_RX / ADC1_SS0
+#define SYSCTL_DC7_DMACH23 0x00800000 // UART1_TX / CAN2_TX
+#define SYSCTL_DC7_DMACH22 0x00400000 // UART1_RX / CAN2_RX
+#define SYSCTL_DC7_DMACH21 0x00200000 // Timer1B / EPI0_WFIFO
+#define SYSCTL_DC7_DMACH20 0x00100000 // Timer1A / EPI0_NBRFIFO
+#define SYSCTL_DC7_DMACH19 0x00080000 // Timer0B / Timer1B
+#define SYSCTL_DC7_DMACH18 0x00040000 // Timer0A / Timer1A
+#define SYSCTL_DC7_DMACH17 0x00020000 // ADC0_SS3
+#define SYSCTL_DC7_DMACH16 0x00010000 // ADC0_SS2
+#define SYSCTL_DC7_DMACH15 0x00008000 // ADC0_SS1 / Timer2B
+#define SYSCTL_DC7_DMACH14 0x00004000 // ADC0_SS0 / Timer2A
+#define SYSCTL_DC7_DMACH13 0x00002000 // CAN0_TX / UART2_TX
+#define SYSCTL_DC7_DMACH12 0x00001000 // CAN0_RX / UART2_RX
+#define SYSCTL_DC7_DMACH11 0x00000800 // SSI0_TX / SSI1_TX
+#define SYSCTL_DC7_DMACH10 0x00000400 // SSI0_RX / SSI1_RX
+#define SYSCTL_DC7_DMACH9 0x00000200 // UART0_TX / UART1_TX
+#define SYSCTL_DC7_DMACH8 0x00000100 // UART0_RX / UART1_RX
+#define SYSCTL_DC7_DMACH7 0x00000080 // ETH_TX / Timer2B
+#define SYSCTL_DC7_DMACH6 0x00000040 // ETH_RX / Timer2A
+#define SYSCTL_DC7_DMACH5 0x00000020 // USB_EP3_TX / Timer2B
+#define SYSCTL_DC7_DMACH4 0x00000010 // USB_EP3_RX / Timer2A
+#define SYSCTL_DC7_DMACH3 0x00000008 // USB_EP2_TX / Timer3B
+#define SYSCTL_DC7_DMACH2 0x00000004 // USB_EP2_RX / Timer3A
+#define SYSCTL_DC7_DMACH1 0x00000002 // USB_EP1_TX / UART2_TX
+#define SYSCTL_DC7_DMACH0 0x00000001 // USB_EP1_RX / UART2_RX
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC8 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC8_ADC1AIN15 0x80000000 // ADC Module 1 AIN15 Pin Present
+#define SYSCTL_DC8_ADC1AIN14 0x40000000 // ADC Module 1 AIN14 Pin Present
+#define SYSCTL_DC8_ADC1AIN13 0x20000000 // ADC Module 1 AIN13 Pin Present
+#define SYSCTL_DC8_ADC1AIN12 0x10000000 // ADC Module 1 AIN12 Pin Present
+#define SYSCTL_DC8_ADC1AIN11 0x08000000 // ADC Module 1 AIN11 Pin Present
+#define SYSCTL_DC8_ADC1AIN10 0x04000000 // ADC Module 1 AIN10 Pin Present
+#define SYSCTL_DC8_ADC1AIN9 0x02000000 // ADC Module 1 AIN9 Pin Present
+#define SYSCTL_DC8_ADC1AIN8 0x01000000 // ADC Module 1 AIN8 Pin Present
+#define SYSCTL_DC8_ADC1AIN7 0x00800000 // ADC Module 1 AIN7 Pin Present
+#define SYSCTL_DC8_ADC1AIN6 0x00400000 // ADC Module 1 AIN6 Pin Present
+#define SYSCTL_DC8_ADC1AIN5 0x00200000 // ADC Module 1 AIN5 Pin Present
+#define SYSCTL_DC8_ADC1AIN4 0x00100000 // ADC Module 1 AIN4 Pin Present
+#define SYSCTL_DC8_ADC1AIN3 0x00080000 // ADC Module 1 AIN3 Pin Present
+#define SYSCTL_DC8_ADC1AIN2 0x00040000 // ADC Module 1 AIN2 Pin Present
+#define SYSCTL_DC8_ADC1AIN1 0x00020000 // ADC Module 1 AIN1 Pin Present
+#define SYSCTL_DC8_ADC1AIN0 0x00010000 // ADC Module 1 AIN0 Pin Present
+#define SYSCTL_DC8_ADC0AIN15 0x00008000 // ADC Module 0 AIN15 Pin Present
+#define SYSCTL_DC8_ADC0AIN14 0x00004000 // ADC Module 0 AIN14 Pin Present
+#define SYSCTL_DC8_ADC0AIN13 0x00002000 // ADC Module 0 AIN13 Pin Present
+#define SYSCTL_DC8_ADC0AIN12 0x00001000 // ADC Module 0 AIN12 Pin Present
+#define SYSCTL_DC8_ADC0AIN11 0x00000800 // ADC Module 0 AIN11 Pin Present
+#define SYSCTL_DC8_ADC0AIN10 0x00000400 // ADC Module 0 AIN10 Pin Present
+#define SYSCTL_DC8_ADC0AIN9 0x00000200 // ADC Module 0 AIN9 Pin Present
+#define SYSCTL_DC8_ADC0AIN8 0x00000100 // ADC Module 0 AIN8 Pin Present
+#define SYSCTL_DC8_ADC0AIN7 0x00000080 // ADC Module 0 AIN7 Pin Present
+#define SYSCTL_DC8_ADC0AIN6 0x00000040 // ADC Module 0 AIN6 Pin Present
+#define SYSCTL_DC8_ADC0AIN5 0x00000020 // ADC Module 0 AIN5 Pin Present
+#define SYSCTL_DC8_ADC0AIN4 0x00000010 // ADC Module 0 AIN4 Pin Present
+#define SYSCTL_DC8_ADC0AIN3 0x00000008 // ADC Module 0 AIN3 Pin Present
+#define SYSCTL_DC8_ADC0AIN2 0x00000004 // ADC Module 0 AIN2 Pin Present
+#define SYSCTL_DC8_ADC0AIN1 0x00000002 // ADC Module 0 AIN1 Pin Present
+#define SYSCTL_DC8_ADC0AIN0 0x00000001 // ADC Module 0 AIN0 Pin Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PBORCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR Interrupt or Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR0 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR0_WDT1 0x10000000 // WDT1 Reset Control
+#define SYSCTL_SRCR0_CAN1 0x02000000 // CAN1 Reset Control
+#define SYSCTL_SRCR0_CAN0 0x01000000 // CAN0 Reset Control
+#define SYSCTL_SRCR0_PWM0 0x00100000 // PWM Reset Control
+#define SYSCTL_SRCR0_ADC1 0x00020000 // ADC1 Reset Control
+#define SYSCTL_SRCR0_ADC0 0x00010000 // ADC0 Reset Control
+#define SYSCTL_SRCR0_HIB 0x00000040 // HIB Reset Control
+#define SYSCTL_SRCR0_WDT0 0x00000008 // WDT0 Reset Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR1 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR1_COMP2 0x04000000 // Analog Comp 2 Reset Control
+#define SYSCTL_SRCR1_COMP1 0x02000000 // Analog Comp 1 Reset Control
+#define SYSCTL_SRCR1_COMP0 0x01000000 // Analog Comp 0 Reset Control
+#define SYSCTL_SRCR1_TIMER3 0x00080000 // Timer 3 Reset Control
+#define SYSCTL_SRCR1_TIMER2 0x00040000 // Timer 2 Reset Control
+#define SYSCTL_SRCR1_TIMER1 0x00020000 // Timer 1 Reset Control
+#define SYSCTL_SRCR1_TIMER0 0x00010000 // Timer 0 Reset Control
+#define SYSCTL_SRCR1_I2C1 0x00004000 // I2C1 Reset Control
+#define SYSCTL_SRCR1_I2C0 0x00001000 // I2C0 Reset Control
+#define SYSCTL_SRCR1_QEI1 0x00000200 // QEI1 Reset Control
+#define SYSCTL_SRCR1_QEI0 0x00000100 // QEI0 Reset Control
+#define SYSCTL_SRCR1_SSI1 0x00000020 // SSI1 Reset Control
+#define SYSCTL_SRCR1_SSI0 0x00000010 // SSI0 Reset Control
+#define SYSCTL_SRCR1_UART2 0x00000004 // UART2 Reset Control
+#define SYSCTL_SRCR1_UART1 0x00000002 // UART1 Reset Control
+#define SYSCTL_SRCR1_UART0 0x00000001 // UART0 Reset Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR2 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR2_USB0 0x00010000 // USB0 Reset Control
+#define SYSCTL_SRCR2_UDMA 0x00002000 // Micro-DMA Reset Control
+#define SYSCTL_SRCR2_GPIOJ 0x00000100 // Port J Reset Control
+#define SYSCTL_SRCR2_GPIOH 0x00000080 // Port H Reset Control
+#define SYSCTL_SRCR2_GPIOG 0x00000040 // Port G Reset Control
+#define SYSCTL_SRCR2_GPIOF 0x00000020 // Port F Reset Control
+#define SYSCTL_SRCR2_GPIOE 0x00000010 // Port E Reset Control
+#define SYSCTL_SRCR2_GPIOD 0x00000008 // Port D Reset Control
+#define SYSCTL_SRCR2_GPIOC 0x00000004 // Port C Reset Control
+#define SYSCTL_SRCR2_GPIOB 0x00000002 // Port B Reset Control
+#define SYSCTL_SRCR2_GPIOA 0x00000001 // Port A Reset Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RIS register.
+//
+//*****************************************************************************
+#define SYSCTL_RIS_MOSCPUPRIS 0x00000100 // MOSC Power Up Raw Interrupt
+ // Status
+#define SYSCTL_RIS_USBPLLLRIS 0x00000080 // USB PLL Lock Raw Interrupt
+ // Status
+#define SYSCTL_RIS_PLLLRIS 0x00000040 // PLL Lock Raw Interrupt Status
+#define SYSCTL_RIS_MOFRIS 0x00000008 // Main Oscillator Fault Raw
+ // Interrupt Status
+#define SYSCTL_RIS_BORRIS 0x00000002 // Brown-Out Reset Raw Interrupt
+ // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_IMC register.
+//
+//*****************************************************************************
+#define SYSCTL_IMC_MOSCPUPIM 0x00000100 // MOSC Power Up Interrupt Mask
+#define SYSCTL_IMC_USBPLLLIM 0x00000080 // USB PLL Lock Interrupt Mask
+#define SYSCTL_IMC_PLLLIM 0x00000040 // PLL Lock Interrupt Mask
+#define SYSCTL_IMC_MOFIM 0x00000008 // Main Oscillator Fault Interrupt
+ // Mask
+#define SYSCTL_IMC_BORIM 0x00000002 // Brown-Out Reset Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_MISC register.
+//
+//*****************************************************************************
+#define SYSCTL_MISC_MOSCPUPMIS 0x00000100 // MOSC Power Up Masked Interrupt
+ // Status
+#define SYSCTL_MISC_USBPLLLMIS 0x00000080 // USB PLL Lock Masked Interrupt
+ // Status
+#define SYSCTL_MISC_PLLLMIS 0x00000040 // PLL Lock Masked Interrupt Status
+#define SYSCTL_MISC_MOFMIS 0x00000008 // Main Oscillator Fault Masked
+ // Interrupt Status
+#define SYSCTL_MISC_BORMIS 0x00000002 // BOR Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RESC register.
+//
+//*****************************************************************************
+#define SYSCTL_RESC_MOSCFAIL 0x00010000 // MOSC Failure Reset
+#define SYSCTL_RESC_WDT1 0x00000020 // Watchdog Timer 1 Reset
+#define SYSCTL_RESC_SW 0x00000010 // Software Reset
+#define SYSCTL_RESC_WDT0 0x00000008 // Watchdog Timer 0 Reset
+#define SYSCTL_RESC_BOR 0x00000004 // Brown-Out Reset
+#define SYSCTL_RESC_POR 0x00000002 // Power-On Reset
+#define SYSCTL_RESC_EXT 0x00000001 // External Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCC register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC_ACG 0x08000000 // Auto Clock Gating
+#define SYSCTL_RCC_SYSDIV_M 0x07800000 // System Clock Divisor
+#define SYSCTL_RCC_USESYSDIV 0x00400000 // Enable System Clock Divider
+#define SYSCTL_RCC_PWRDN 0x00002000 // PLL Power Down
+#define SYSCTL_RCC_BYPASS 0x00000800 // PLL Bypass
+#define SYSCTL_RCC_XTAL_M 0x000007C0 // Crystal Value
+#define SYSCTL_RCC_XTAL_4MHZ 0x00000180 // 4 MHz
+#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // 4.096 MHz
+#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // 4.9152 MHz
+#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // 5 MHz
+#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // 5.12 MHz
+#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // 6 MHz
+#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // 6.144 MHz
+#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // 7.3728 MHz
+#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // 8 MHz
+#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // 8.192 MHz
+#define SYSCTL_RCC_XTAL_10MHZ 0x00000400 // 10 MHz
+#define SYSCTL_RCC_XTAL_12MHZ 0x00000440 // 12 MHz
+#define SYSCTL_RCC_XTAL_12_2MHZ 0x00000480 // 12.288 MHz
+#define SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0 // 13.56 MHz
+#define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500 // 14.31818 MHz
+#define SYSCTL_RCC_XTAL_16MHZ 0x00000540 // 16 MHz
+#define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580 // 16.384 MHz
+#define SYSCTL_RCC_XTAL_18MHZ 0x000005C0 // 18.0 MHz
+#define SYSCTL_RCC_XTAL_20MHZ 0x00000600 // 20.0 MHz
+#define SYSCTL_RCC_XTAL_24MHZ 0x00000640 // 24.0 MHz
+#define SYSCTL_RCC_XTAL_25MHZ 0x00000680 // 25.0 MHz
+#define SYSCTL_RCC_OSCSRC_M 0x00000030 // Oscillator Source
+#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // MOSC
+#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // IOSC
+#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // IOSC/4
+#define SYSCTL_RCC_OSCSRC_30 0x00000030 // 30 kHz
+#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal Oscillator Disable
+#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main Oscillator Disable
+#define SYSCTL_RCC_SYSDIV_S 23
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_GPIOHBCTL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_GPIOHBCTL_PORTF 0x00000020 // Port F Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTE 0x00000010 // Port E Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTD 0x00000008 // Port D Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTC 0x00000004 // Port C Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTB 0x00000002 // Port B Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTA 0x00000001 // Port A Advanced High-Performance
+ // Bus
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2
+#define SYSCTL_RCC2_DIV400 0x40000000 // Divide PLL as 400 MHz vs. 200
+ // MHz
+#define SYSCTL_RCC2_SYSDIV2_M 0x1F800000 // System Clock Divisor 2
+#define SYSCTL_RCC2_SYSDIV2_2 0x00800000 // System clock /2
+#define SYSCTL_RCC2_SYSDIV2_3 0x01000000 // System clock /3
+#define SYSCTL_RCC2_SYSDIV2_4 0x01800000 // System clock /4
+#define SYSCTL_RCC2_SYSDIV2_5 0x02000000 // System clock /5
+#define SYSCTL_RCC2_SYSDIV2_6 0x02800000 // System clock /6
+#define SYSCTL_RCC2_SYSDIV2_7 0x03000000 // System clock /7
+#define SYSCTL_RCC2_SYSDIV2_8 0x03800000 // System clock /8
+#define SYSCTL_RCC2_SYSDIV2_9 0x04000000 // System clock /9
+#define SYSCTL_RCC2_SYSDIV2_10 0x04800000 // System clock /10
+#define SYSCTL_RCC2_SYSDIV2_11 0x05000000 // System clock /11
+#define SYSCTL_RCC2_SYSDIV2_12 0x05800000 // System clock /12
+#define SYSCTL_RCC2_SYSDIV2_13 0x06000000 // System clock /13
+#define SYSCTL_RCC2_SYSDIV2_14 0x06800000 // System clock /14
+#define SYSCTL_RCC2_SYSDIV2_15 0x07000000 // System clock /15
+#define SYSCTL_RCC2_SYSDIV2_16 0x07800000 // System clock /16
+#define SYSCTL_RCC2_SYSDIV2_17 0x08000000 // System clock /17
+#define SYSCTL_RCC2_SYSDIV2_18 0x08800000 // System clock /18
+#define SYSCTL_RCC2_SYSDIV2_19 0x09000000 // System clock /19
+#define SYSCTL_RCC2_SYSDIV2_20 0x09800000 // System clock /20
+#define SYSCTL_RCC2_SYSDIV2_21 0x0A000000 // System clock /21
+#define SYSCTL_RCC2_SYSDIV2_22 0x0A800000 // System clock /22
+#define SYSCTL_RCC2_SYSDIV2_23 0x0B000000 // System clock /23
+#define SYSCTL_RCC2_SYSDIV2_24 0x0B800000 // System clock /24
+#define SYSCTL_RCC2_SYSDIV2_25 0x0C000000 // System clock /25
+#define SYSCTL_RCC2_SYSDIV2_26 0x0C800000 // System clock /26
+#define SYSCTL_RCC2_SYSDIV2_27 0x0D000000 // System clock /27
+#define SYSCTL_RCC2_SYSDIV2_28 0x0D800000 // System clock /28
+#define SYSCTL_RCC2_SYSDIV2_29 0x0E000000 // System clock /29
+#define SYSCTL_RCC2_SYSDIV2_30 0x0E800000 // System clock /30
+#define SYSCTL_RCC2_SYSDIV2_31 0x0F000000 // System clock /31
+#define SYSCTL_RCC2_SYSDIV2_32 0x0F800000 // System clock /32
+#define SYSCTL_RCC2_SYSDIV2_33 0x10000000 // System clock /33
+#define SYSCTL_RCC2_SYSDIV2_34 0x10800000 // System clock /34
+#define SYSCTL_RCC2_SYSDIV2_35 0x11000000 // System clock /35
+#define SYSCTL_RCC2_SYSDIV2_36 0x11800000 // System clock /36
+#define SYSCTL_RCC2_SYSDIV2_37 0x12000000 // System clock /37
+#define SYSCTL_RCC2_SYSDIV2_38 0x12800000 // System clock /38
+#define SYSCTL_RCC2_SYSDIV2_39 0x13000000 // System clock /39
+#define SYSCTL_RCC2_SYSDIV2_40 0x13800000 // System clock /40
+#define SYSCTL_RCC2_SYSDIV2_41 0x14000000 // System clock /41
+#define SYSCTL_RCC2_SYSDIV2_42 0x14800000 // System clock /42
+#define SYSCTL_RCC2_SYSDIV2_43 0x15000000 // System clock /43
+#define SYSCTL_RCC2_SYSDIV2_44 0x15800000 // System clock /44
+#define SYSCTL_RCC2_SYSDIV2_45 0x16000000 // System clock /45
+#define SYSCTL_RCC2_SYSDIV2_46 0x16800000 // System clock /46
+#define SYSCTL_RCC2_SYSDIV2_47 0x17000000 // System clock /47
+#define SYSCTL_RCC2_SYSDIV2_48 0x17800000 // System clock /48
+#define SYSCTL_RCC2_SYSDIV2_49 0x18000000 // System clock /49
+#define SYSCTL_RCC2_SYSDIV2_50 0x18800000 // System clock /50
+#define SYSCTL_RCC2_SYSDIV2_51 0x19000000 // System clock /51
+#define SYSCTL_RCC2_SYSDIV2_52 0x19800000 // System clock /52
+#define SYSCTL_RCC2_SYSDIV2_53 0x1A000000 // System clock /53
+#define SYSCTL_RCC2_SYSDIV2_54 0x1A800000 // System clock /54
+#define SYSCTL_RCC2_SYSDIV2_55 0x1B000000 // System clock /55
+#define SYSCTL_RCC2_SYSDIV2_56 0x1B800000 // System clock /56
+#define SYSCTL_RCC2_SYSDIV2_57 0x1C000000 // System clock /57
+#define SYSCTL_RCC2_SYSDIV2_58 0x1C800000 // System clock /58
+#define SYSCTL_RCC2_SYSDIV2_59 0x1D000000 // System clock /59
+#define SYSCTL_RCC2_SYSDIV2_60 0x1D800000 // System clock /60
+#define SYSCTL_RCC2_SYSDIV2_61 0x1E000000 // System clock /61
+#define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 // System clock /62
+#define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 // System clock /63
+#define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 // System clock /64
+#define SYSCTL_RCC2_SYSDIV2LSB 0x00400000 // Additional LSB for SYSDIV2
+#define SYSCTL_RCC2_USBPWRDN 0x00004000 // Power-Down USB PLL
+#define SYSCTL_RCC2_PWRDN2 0x00002000 // Power-Down PLL 2
+#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL Bypass 2
+#define SYSCTL_RCC2_OSCSRC2_M 0x00000070 // Oscillator Source 2
+#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // MOSC
+#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // PIOSC
+#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // PIOSC/4
+#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // 30 kHz
+#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // 32.768 kHz
+#define SYSCTL_RCC2_SYSDIV2_S 23
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_MOSCCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_MOSCCTL_NOXTAL 0x00000004 // No Crystal Connected
+#define SYSCTL_MOSCCTL_MOSCIM 0x00000002 // MOSC Failure Action
+#define SYSCTL_MOSCCTL_CVAL 0x00000001 // Clock Validation for MOSC
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control
+#define SYSCTL_RCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control
+#define SYSCTL_RCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control
+#define SYSCTL_RCGC0_PWM0 0x00100000 // PWM Clock Gating Control
+#define SYSCTL_RCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control
+#define SYSCTL_RCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control
+#define SYSCTL_RCGC0_ADC1SPD_M 0x00000C00 // ADC1 Sample Speed
+#define SYSCTL_RCGC0_ADC1SPD_125K \
+ 0x00000000 // 125K samples/second
+#define SYSCTL_RCGC0_ADC1SPD_250K \
+ 0x00000400 // 250K samples/second
+#define SYSCTL_RCGC0_ADC1SPD_500K \
+ 0x00000800 // 500K samples/second
+#define SYSCTL_RCGC0_ADC1SPD_1M 0x00000C00 // 1M samples/second
+#define SYSCTL_RCGC0_ADC0SPD_M 0x00000300 // ADC0 Sample Speed
+#define SYSCTL_RCGC0_ADC0SPD_125K \
+ 0x00000000 // 125K samples/second
+#define SYSCTL_RCGC0_ADC0SPD_250K \
+ 0x00000100 // 250K samples/second
+#define SYSCTL_RCGC0_ADC0SPD_500K \
+ 0x00000200 // 500K samples/second
+#define SYSCTL_RCGC0_ADC0SPD_1M 0x00000300 // 1M samples/second
+#define SYSCTL_RCGC0_HIB 0x00000040 // HIB Clock Gating Control
+#define SYSCTL_RCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating
+#define SYSCTL_RCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating
+#define SYSCTL_RCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating
+#define SYSCTL_RCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control
+#define SYSCTL_RCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control
+#define SYSCTL_RCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control
+#define SYSCTL_RCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control
+#define SYSCTL_RCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control
+#define SYSCTL_RCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control
+#define SYSCTL_RCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control
+#define SYSCTL_RCGC1_UART2 0x00000004 // UART2 Clock Gating Control
+#define SYSCTL_RCGC1_UART1 0x00000002 // UART1 Clock Gating Control
+#define SYSCTL_RCGC1_UART0 0x00000001 // UART0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC2_USB0 0x00010000 // USB0 Clock Gating Control
+#define SYSCTL_RCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control
+#define SYSCTL_RCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control
+#define SYSCTL_RCGC2_GPIOH 0x00000080 // Port H Clock Gating Control
+#define SYSCTL_RCGC2_GPIOG 0x00000040 // Port G Clock Gating Control
+#define SYSCTL_RCGC2_GPIOF 0x00000020 // Port F Clock Gating Control
+#define SYSCTL_RCGC2_GPIOE 0x00000010 // Port E Clock Gating Control
+#define SYSCTL_RCGC2_GPIOD 0x00000008 // Port D Clock Gating Control
+#define SYSCTL_RCGC2_GPIOC 0x00000004 // Port C Clock Gating Control
+#define SYSCTL_RCGC2_GPIOB 0x00000002 // Port B Clock Gating Control
+#define SYSCTL_RCGC2_GPIOA 0x00000001 // Port A Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control
+#define SYSCTL_SCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control
+#define SYSCTL_SCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control
+#define SYSCTL_SCGC0_PWM0 0x00100000 // PWM Clock Gating Control
+#define SYSCTL_SCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control
+#define SYSCTL_SCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control
+#define SYSCTL_SCGC0_HIB 0x00000040 // HIB Clock Gating Control
+#define SYSCTL_SCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating
+#define SYSCTL_SCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating
+#define SYSCTL_SCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating
+#define SYSCTL_SCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control
+#define SYSCTL_SCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control
+#define SYSCTL_SCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control
+#define SYSCTL_SCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control
+#define SYSCTL_SCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control
+#define SYSCTL_SCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control
+#define SYSCTL_SCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control
+#define SYSCTL_SCGC1_UART2 0x00000004 // UART2 Clock Gating Control
+#define SYSCTL_SCGC1_UART1 0x00000002 // UART1 Clock Gating Control
+#define SYSCTL_SCGC1_UART0 0x00000001 // UART0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC2_USB0 0x00010000 // USB0 Clock Gating Control
+#define SYSCTL_SCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control
+#define SYSCTL_SCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control
+#define SYSCTL_SCGC2_GPIOH 0x00000080 // Port H Clock Gating Control
+#define SYSCTL_SCGC2_GPIOG 0x00000040 // Port G Clock Gating Control
+#define SYSCTL_SCGC2_GPIOF 0x00000020 // Port F Clock Gating Control
+#define SYSCTL_SCGC2_GPIOE 0x00000010 // Port E Clock Gating Control
+#define SYSCTL_SCGC2_GPIOD 0x00000008 // Port D Clock Gating Control
+#define SYSCTL_SCGC2_GPIOC 0x00000004 // Port C Clock Gating Control
+#define SYSCTL_SCGC2_GPIOB 0x00000002 // Port B Clock Gating Control
+#define SYSCTL_SCGC2_GPIOA 0x00000001 // Port A Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control
+#define SYSCTL_DCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control
+#define SYSCTL_DCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control
+#define SYSCTL_DCGC0_PWM0 0x00100000 // PWM Clock Gating Control
+#define SYSCTL_DCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control
+#define SYSCTL_DCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control
+#define SYSCTL_DCGC0_HIB 0x00000040 // HIB Clock Gating Control
+#define SYSCTL_DCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating
+#define SYSCTL_DCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating
+#define SYSCTL_DCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating
+#define SYSCTL_DCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control
+#define SYSCTL_DCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control
+#define SYSCTL_DCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control
+#define SYSCTL_DCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control
+#define SYSCTL_DCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control
+#define SYSCTL_DCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control
+#define SYSCTL_DCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control
+#define SYSCTL_DCGC1_UART2 0x00000004 // UART2 Clock Gating Control
+#define SYSCTL_DCGC1_UART1 0x00000002 // UART1 Clock Gating Control
+#define SYSCTL_DCGC1_UART0 0x00000001 // UART0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC2_USB0 0x00010000 // USB0 Clock Gating Control
+#define SYSCTL_DCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control
+#define SYSCTL_DCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control
+#define SYSCTL_DCGC2_GPIOH 0x00000080 // Port H Clock Gating Control
+#define SYSCTL_DCGC2_GPIOG 0x00000040 // Port G Clock Gating Control
+#define SYSCTL_DCGC2_GPIOF 0x00000020 // Port F Clock Gating Control
+#define SYSCTL_DCGC2_GPIOE 0x00000010 // Port E Clock Gating Control
+#define SYSCTL_DCGC2_GPIOD 0x00000008 // Port D Clock Gating Control
+#define SYSCTL_DCGC2_GPIOC 0x00000004 // Port C Clock Gating Control
+#define SYSCTL_DCGC2_GPIOB 0x00000002 // Port B Clock Gating Control
+#define SYSCTL_DCGC2_GPIOA 0x00000001 // Port A Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DSLPCLKCFG_D_M 0x1F800000 // Divider Field Override
+#define SYSCTL_DSLPCLKCFG_D_1 0x00000000 // System clock /1
+#define SYSCTL_DSLPCLKCFG_D_2 0x00800000 // System clock /2
+#define SYSCTL_DSLPCLKCFG_D_3 0x01000000 // System clock /3
+#define SYSCTL_DSLPCLKCFG_D_4 0x01800000 // System clock /4
+#define SYSCTL_DSLPCLKCFG_D_64 0x1F800000 // System clock /64
+#define SYSCTL_DSLPCLKCFG_O_M 0x00000070 // Clock Source
+#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // MOSC
+#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // PIOSC
+#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // 30 kHz
+#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // 32.768 kHz
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SYSPROP register.
+//
+//*****************************************************************************
+#define SYSCTL_SYSPROP_FPU 0x00000001 // FPU Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PIOSCCAL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PIOSCCAL_UTEN 0x80000000 // Use User Trim Value
+#define SYSCTL_PIOSCCAL_CAL 0x00000200 // Start Calibration
+#define SYSCTL_PIOSCCAL_UPDATE 0x00000100 // Update Trim
+#define SYSCTL_PIOSCCAL_UT_M 0x0000007F // User Trim Value
+#define SYSCTL_PIOSCCAL_UT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PIOSCSTAT
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PIOSCSTAT_DT_M 0x007F0000 // Default Trim Value
+#define SYSCTL_PIOSCSTAT_CR_M 0x00000300 // Calibration Result
+#define SYSCTL_PIOSCSTAT_CRNONE 0x00000000 // Calibration has not been
+ // attempted
+#define SYSCTL_PIOSCSTAT_CRPASS 0x00000100 // The last calibration operation
+ // completed to meet 1% accuracy
+#define SYSCTL_PIOSCSTAT_CRFAIL 0x00000200 // The last calibration operation
+ // failed to meet 1% accuracy
+#define SYSCTL_PIOSCSTAT_CT_M 0x0000007F // Calibration Trim Value
+#define SYSCTL_PIOSCSTAT_DT_S 16
+#define SYSCTL_PIOSCSTAT_CT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PLLFREQ0
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLFREQ0_MFRAC_M 0x000FFC00 // PLL M Fractional Value
+#define SYSCTL_PLLFREQ0_MINT_M 0x000003FF // PLL M Integer Value
+#define SYSCTL_PLLFREQ0_MFRAC_S 10
+#define SYSCTL_PLLFREQ0_MINT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PLLFREQ1
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLFREQ1_Q_M 0x00001F00 // PLL Q Value
+#define SYSCTL_PLLFREQ1_N_M 0x0000001F // PLL N Value
+#define SYSCTL_PLLFREQ1_Q_S 8
+#define SYSCTL_PLLFREQ1_N_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PLLSTAT register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLSTAT_LOCK 0x00000001 // PLL Lock
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC9 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC9_ADC1DC7 0x00800000 // ADC1 DC7 Present
+#define SYSCTL_DC9_ADC1DC6 0x00400000 // ADC1 DC6 Present
+#define SYSCTL_DC9_ADC1DC5 0x00200000 // ADC1 DC5 Present
+#define SYSCTL_DC9_ADC1DC4 0x00100000 // ADC1 DC4 Present
+#define SYSCTL_DC9_ADC1DC3 0x00080000 // ADC1 DC3 Present
+#define SYSCTL_DC9_ADC1DC2 0x00040000 // ADC1 DC2 Present
+#define SYSCTL_DC9_ADC1DC1 0x00020000 // ADC1 DC1 Present
+#define SYSCTL_DC9_ADC1DC0 0x00010000 // ADC1 DC0 Present
+#define SYSCTL_DC9_ADC0DC7 0x00000080 // ADC0 DC7 Present
+#define SYSCTL_DC9_ADC0DC6 0x00000040 // ADC0 DC6 Present
+#define SYSCTL_DC9_ADC0DC5 0x00000020 // ADC0 DC5 Present
+#define SYSCTL_DC9_ADC0DC4 0x00000010 // ADC0 DC4 Present
+#define SYSCTL_DC9_ADC0DC3 0x00000008 // ADC0 DC3 Present
+#define SYSCTL_DC9_ADC0DC2 0x00000004 // ADC0 DC2 Present
+#define SYSCTL_DC9_ADC0DC1 0x00000002 // ADC0 DC1 Present
+#define SYSCTL_DC9_ADC0DC0 0x00000001 // ADC0 DC0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_NVMSTAT register.
+//
+//*****************************************************************************
+#define SYSCTL_NVMSTAT_TPSW 0x00000010 // Third Party Software Present
+#define SYSCTL_NVMSTAT_FWB 0x00000001 // 32 Word Flash Write Buffer
+ // Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPWD register.
+//
+//*****************************************************************************
+#define SYSCTL_PPWD_P1 0x00000002 // Watchdog Timer 1 Present
+#define SYSCTL_PPWD_P0 0x00000001 // Watchdog Timer 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPTIMER register.
+//
+//*****************************************************************************
+#define SYSCTL_PPTIMER_P5 0x00000020 // Timer 5 Present
+#define SYSCTL_PPTIMER_P4 0x00000010 // Timer 4 Present
+#define SYSCTL_PPTIMER_P3 0x00000008 // Timer 3 Present
+#define SYSCTL_PPTIMER_P2 0x00000004 // Timer 2 Present
+#define SYSCTL_PPTIMER_P1 0x00000002 // Timer 1 Present
+#define SYSCTL_PPTIMER_P0 0x00000001 // Timer 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPGPIO register.
+//
+//*****************************************************************************
+#define SYSCTL_PPGPIO_P14 0x00004000 // GPIO Port Q Present
+#define SYSCTL_PPGPIO_P13 0x00002000 // GPIO Port P Present
+#define SYSCTL_PPGPIO_P12 0x00001000 // GPIO Port N Present
+#define SYSCTL_PPGPIO_P11 0x00000800 // GPIO Port M Present
+#define SYSCTL_PPGPIO_P10 0x00000400 // GPIO Port L Present
+#define SYSCTL_PPGPIO_P9 0x00000200 // GPIO Port K Present
+#define SYSCTL_PPGPIO_P8 0x00000100 // GPIO Port J Present
+#define SYSCTL_PPGPIO_P7 0x00000080 // GPIO Port H Present
+#define SYSCTL_PPGPIO_P6 0x00000040 // GPIO Port G Present
+#define SYSCTL_PPGPIO_P5 0x00000020 // GPIO Port F Present
+#define SYSCTL_PPGPIO_P4 0x00000010 // GPIO Port E Present
+#define SYSCTL_PPGPIO_P3 0x00000008 // GPIO Port D Present
+#define SYSCTL_PPGPIO_P2 0x00000004 // GPIO Port C Present
+#define SYSCTL_PPGPIO_P1 0x00000002 // GPIO Port B Present
+#define SYSCTL_PPGPIO_P0 0x00000001 // GPIO Port A Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_PPDMA_P0 0x00000001 // uDMA Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_PPHIB_P0 0x00000001 // Hibernation Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPUART register.
+//
+//*****************************************************************************
+#define SYSCTL_PPUART_P7 0x00000080 // UART Module 7 Present
+#define SYSCTL_PPUART_P6 0x00000040 // UART Module 6 Present
+#define SYSCTL_PPUART_P5 0x00000020 // UART Module 5 Present
+#define SYSCTL_PPUART_P4 0x00000010 // UART Module 4 Present
+#define SYSCTL_PPUART_P3 0x00000008 // UART Module 3 Present
+#define SYSCTL_PPUART_P2 0x00000004 // UART Module 2 Present
+#define SYSCTL_PPUART_P1 0x00000002 // UART Module 1 Present
+#define SYSCTL_PPUART_P0 0x00000001 // UART Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_PPSSI_P3 0x00000008 // SSI Module 3 Present
+#define SYSCTL_PPSSI_P2 0x00000004 // SSI Module 2 Present
+#define SYSCTL_PPSSI_P1 0x00000002 // SSI Module 1 Present
+#define SYSCTL_PPSSI_P0 0x00000001 // SSI Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_PPI2C_P5 0x00000020 // I2C Module 5 Present
+#define SYSCTL_PPI2C_P4 0x00000010 // I2C Module 4 Present
+#define SYSCTL_PPI2C_P3 0x00000008 // I2C Module 3 Present
+#define SYSCTL_PPI2C_P2 0x00000004 // I2C Module 2 Present
+#define SYSCTL_PPI2C_P1 0x00000002 // I2C Module 1 Present
+#define SYSCTL_PPI2C_P0 0x00000001 // I2C Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_PPUSB_P0 0x00000001 // USB Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_PPCAN_P1 0x00000002 // CAN Module 1 Present
+#define SYSCTL_PPCAN_P0 0x00000001 // CAN Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPADC register.
+//
+//*****************************************************************************
+#define SYSCTL_PPADC_P1 0x00000002 // ADC Module 1 Present
+#define SYSCTL_PPADC_P0 0x00000001 // ADC Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPACMP register.
+//
+//*****************************************************************************
+#define SYSCTL_PPACMP_P0 0x00000001 // Analog Comparator Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_PPPWM_P1 0x00000002 // PWM Module 1 Present
+#define SYSCTL_PPPWM_P0 0x00000001 // PWM Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_PPQEI_P1 0x00000002 // QEI Module 1 Present
+#define SYSCTL_PPQEI_P0 0x00000001 // QEI Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PPEEPROM_P0 0x00000001 // EEPROM Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PPWTIMER_P5 0x00000020 // Wide Timer 5 Present
+#define SYSCTL_PPWTIMER_P4 0x00000010 // Wide Timer 4 Present
+#define SYSCTL_PPWTIMER_P3 0x00000008 // Wide Timer 3 Present
+#define SYSCTL_PPWTIMER_P2 0x00000004 // Wide Timer 2 Present
+#define SYSCTL_PPWTIMER_P1 0x00000002 // Wide Timer 1 Present
+#define SYSCTL_PPWTIMER_P0 0x00000001 // Wide Timer 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRWD register.
+//
+//*****************************************************************************
+#define SYSCTL_SRWD_R1 0x00000002 // Watchdog Timer 1 Software Reset
+#define SYSCTL_SRWD_R0 0x00000001 // Watchdog Timer 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRTIMER register.
+//
+//*****************************************************************************
+#define SYSCTL_SRTIMER_R5 0x00000020 // Timer 5 Software Reset
+#define SYSCTL_SRTIMER_R4 0x00000010 // Timer 4 Software Reset
+#define SYSCTL_SRTIMER_R3 0x00000008 // Timer 3 Software Reset
+#define SYSCTL_SRTIMER_R2 0x00000004 // Timer 2 Software Reset
+#define SYSCTL_SRTIMER_R1 0x00000002 // Timer 1 Software Reset
+#define SYSCTL_SRTIMER_R0 0x00000001 // Timer 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRGPIO register.
+//
+//*****************************************************************************
+#define SYSCTL_SRGPIO_R14 0x00004000 // GPIO Port Q Software Reset
+#define SYSCTL_SRGPIO_R13 0x00002000 // GPIO Port P Software Reset
+#define SYSCTL_SRGPIO_R12 0x00001000 // GPIO Port N Software Reset
+#define SYSCTL_SRGPIO_R11 0x00000800 // GPIO Port M Software Reset
+#define SYSCTL_SRGPIO_R10 0x00000400 // GPIO Port L Software Reset
+#define SYSCTL_SRGPIO_R9 0x00000200 // GPIO Port K Software Reset
+#define SYSCTL_SRGPIO_R8 0x00000100 // GPIO Port J Software Reset
+#define SYSCTL_SRGPIO_R7 0x00000080 // GPIO Port H Software Reset
+#define SYSCTL_SRGPIO_R6 0x00000040 // GPIO Port G Software Reset
+#define SYSCTL_SRGPIO_R5 0x00000020 // GPIO Port F Software Reset
+#define SYSCTL_SRGPIO_R4 0x00000010 // GPIO Port E Software Reset
+#define SYSCTL_SRGPIO_R3 0x00000008 // GPIO Port D Software Reset
+#define SYSCTL_SRGPIO_R2 0x00000004 // GPIO Port C Software Reset
+#define SYSCTL_SRGPIO_R1 0x00000002 // GPIO Port B Software Reset
+#define SYSCTL_SRGPIO_R0 0x00000001 // GPIO Port A Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_SRDMA_R0 0x00000001 // uDMA Module Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_SRHIB_R0 0x00000001 // Hibernation Module Software
+ // Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRUART register.
+//
+//*****************************************************************************
+#define SYSCTL_SRUART_R7 0x00000080 // UART Module 7 Software Reset
+#define SYSCTL_SRUART_R6 0x00000040 // UART Module 6 Software Reset
+#define SYSCTL_SRUART_R5 0x00000020 // UART Module 5 Software Reset
+#define SYSCTL_SRUART_R4 0x00000010 // UART Module 4 Software Reset
+#define SYSCTL_SRUART_R3 0x00000008 // UART Module 3 Software Reset
+#define SYSCTL_SRUART_R2 0x00000004 // UART Module 2 Software Reset
+#define SYSCTL_SRUART_R1 0x00000002 // UART Module 1 Software Reset
+#define SYSCTL_SRUART_R0 0x00000001 // UART Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_SRSSI_R3 0x00000008 // SSI Module 3 Software Reset
+#define SYSCTL_SRSSI_R2 0x00000004 // SSI Module 2 Software Reset
+#define SYSCTL_SRSSI_R1 0x00000002 // SSI Module 1 Software Reset
+#define SYSCTL_SRSSI_R0 0x00000001 // SSI Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_SRI2C_R5 0x00000020 // I2C Module 5 Software Reset
+#define SYSCTL_SRI2C_R4 0x00000010 // I2C Module 4 Software Reset
+#define SYSCTL_SRI2C_R3 0x00000008 // I2C Module 3 Software Reset
+#define SYSCTL_SRI2C_R2 0x00000004 // I2C Module 2 Software Reset
+#define SYSCTL_SRI2C_R1 0x00000002 // I2C Module 1 Software Reset
+#define SYSCTL_SRI2C_R0 0x00000001 // I2C Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_SRUSB_R0 0x00000001 // USB Module Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCAN_R1 0x00000002 // CAN Module 1 Software Reset
+#define SYSCTL_SRCAN_R0 0x00000001 // CAN Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRADC register.
+//
+//*****************************************************************************
+#define SYSCTL_SRADC_R1 0x00000002 // ADC Module 1 Software Reset
+#define SYSCTL_SRADC_R0 0x00000001 // ADC Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRACMP register.
+//
+//*****************************************************************************
+#define SYSCTL_SRACMP_R0 0x00000001 // Analog Comparator Module 0
+ // Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SREEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SREEPROM_R0 0x00000001 // EEPROM Module Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SRWTIMER_R5 0x00000020 // Wide Timer 5 Software Reset
+#define SYSCTL_SRWTIMER_R4 0x00000010 // Wide Timer 4 Software Reset
+#define SYSCTL_SRWTIMER_R3 0x00000008 // Wide Timer 3 Software Reset
+#define SYSCTL_SRWTIMER_R2 0x00000004 // Wide Timer 2 Software Reset
+#define SYSCTL_SRWTIMER_R1 0x00000002 // Wide Timer 1 Software Reset
+#define SYSCTL_SRWTIMER_R0 0x00000001 // Wide Timer 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCWD register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCWD_R1 0x00000002 // Watchdog Timer 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCWD_R0 0x00000001 // Watchdog Timer 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCTIMER_R5 0x00000020 // Timer 5 Run Mode Clock Gating
+ // Control
+#define SYSCTL_RCGCTIMER_R4 0x00000010 // Timer 4 Run Mode Clock Gating
+ // Control
+#define SYSCTL_RCGCTIMER_R3 0x00000008 // Timer 3 Run Mode Clock Gating
+ // Control
+#define SYSCTL_RCGCTIMER_R2 0x00000004 // Timer 2 Run Mode Clock Gating
+ // Control
+#define SYSCTL_RCGCTIMER_R1 0x00000002 // Timer 1 Run Mode Clock Gating
+ // Control
+#define SYSCTL_RCGCTIMER_R0 0x00000001 // Timer 0 Run Mode Clock Gating
+ // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCGPIO
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCGPIO_R14 0x00004000 // GPIO Port Q Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R13 0x00002000 // GPIO Port P Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R12 0x00001000 // GPIO Port N Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R11 0x00000800 // GPIO Port M Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R10 0x00000400 // GPIO Port L Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R9 0x00000200 // GPIO Port K Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R8 0x00000100 // GPIO Port J Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R7 0x00000080 // GPIO Port H Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R6 0x00000040 // GPIO Port G Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R5 0x00000020 // GPIO Port F Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R4 0x00000010 // GPIO Port E Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R3 0x00000008 // GPIO Port D Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R2 0x00000004 // GPIO Port C Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R1 0x00000002 // GPIO Port B Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R0 0x00000001 // GPIO Port A Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCDMA_R0 0x00000001 // uDMA Module Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCHIB_R0 0x00000001 // Hibernation Module Run Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCUART
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCUART_R7 0x00000080 // UART Module 7 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCUART_R6 0x00000040 // UART Module 6 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCUART_R5 0x00000020 // UART Module 5 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCUART_R4 0x00000010 // UART Module 4 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCUART_R3 0x00000008 // UART Module 3 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCUART_R2 0x00000004 // UART Module 2 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCUART_R1 0x00000002 // UART Module 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCUART_R0 0x00000001 // UART Module 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCSSI_R3 0x00000008 // SSI Module 3 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCSSI_R2 0x00000004 // SSI Module 2 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCSSI_R1 0x00000002 // SSI Module 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCSSI_R0 0x00000001 // SSI Module 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCI2C_R5 0x00000020 // I2C Module 5 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCI2C_R4 0x00000010 // I2C Module 4 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCI2C_R3 0x00000008 // I2C Module 3 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCI2C_R2 0x00000004 // I2C Module 2 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCI2C_R1 0x00000002 // I2C Module 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCI2C_R0 0x00000001 // I2C Module 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCUSB_R0 0x00000001 // USB Module Run Mode Clock Gating
+ // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCCAN_R1 0x00000002 // CAN Module 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCCAN_R0 0x00000001 // CAN Module 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCADC register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCADC_R1 0x00000002 // ADC Module 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCADC_R0 0x00000001 // ADC Module 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCACMP
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCACMP_R0 0x00000001 // Analog Comparator Module 0 Run
+ // Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCEEPROM_R0 0x00000001 // EEPROM Module Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCWTIMER_R5 0x00000020 // Wide Timer 5 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCWTIMER_R4 0x00000010 // Wide Timer 4 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCWTIMER_R3 0x00000008 // Wide Timer 3 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCWTIMER_R2 0x00000004 // Wide Timer 2 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCWTIMER_R1 0x00000002 // Wide Timer 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCWTIMER_R0 0x00000001 // Wide Timer 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCWD register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCWD_S1 0x00000002 // Watchdog Timer 1 Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_SCGCWD_S0 0x00000001 // Watchdog Timer 0 Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCTIMER_S5 0x00000020 // Timer 5 Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCTIMER_S4 0x00000010 // Timer 4 Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCTIMER_S3 0x00000008 // Timer 3 Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCTIMER_S2 0x00000004 // Timer 2 Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCTIMER_S1 0x00000002 // Timer 1 Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCTIMER_S0 0x00000001 // Timer 0 Sleep Mode Clock Gating
+ // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCGPIO
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCGPIO_S14 0x00004000 // GPIO Port Q Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S13 0x00002000 // GPIO Port P Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S12 0x00001000 // GPIO Port N Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S11 0x00000800 // GPIO Port M Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S10 0x00000400 // GPIO Port L Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S9 0x00000200 // GPIO Port K Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S8 0x00000100 // GPIO Port J Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S7 0x00000080 // GPIO Port H Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S6 0x00000040 // GPIO Port G Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S5 0x00000020 // GPIO Port F Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S4 0x00000010 // GPIO Port E Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S3 0x00000008 // GPIO Port D Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S2 0x00000004 // GPIO Port C Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S1 0x00000002 // GPIO Port B Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S0 0x00000001 // GPIO Port A Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCDMA_S0 0x00000001 // uDMA Module Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCHIB_S0 0x00000001 // Hibernation Module Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCUART
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCUART_S7 0x00000080 // UART Module 7 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCUART_S6 0x00000040 // UART Module 6 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCUART_S5 0x00000020 // UART Module 5 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCUART_S4 0x00000010 // UART Module 4 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCUART_S3 0x00000008 // UART Module 3 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCUART_S2 0x00000004 // UART Module 2 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCUART_S1 0x00000002 // UART Module 1 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCUART_S0 0x00000001 // UART Module 0 Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCSSI_S3 0x00000008 // SSI Module 3 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCSSI_S2 0x00000004 // SSI Module 2 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCSSI_S1 0x00000002 // SSI Module 1 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCSSI_S0 0x00000001 // SSI Module 0 Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCI2C_S5 0x00000020 // I2C Module 5 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCI2C_S4 0x00000010 // I2C Module 4 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCI2C_S3 0x00000008 // I2C Module 3 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCI2C_S2 0x00000004 // I2C Module 2 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCI2C_S1 0x00000002 // I2C Module 1 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCI2C_S0 0x00000001 // I2C Module 0 Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCUSB_S0 0x00000001 // USB Module Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCCAN_S1 0x00000002 // CAN Module 1 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCCAN_S0 0x00000001 // CAN Module 0 Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCADC register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCADC_S1 0x00000002 // ADC Module 1 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCADC_S0 0x00000001 // ADC Module 0 Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCACMP
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCACMP_S0 0x00000001 // Analog Comparator Module 0 Sleep
+ // Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCEEPROM_S0 0x00000001 // EEPROM Module Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCWTIMER_S5 0x00000020 // Wide Timer 5 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCWTIMER_S4 0x00000010 // Wide Timer 4 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCWTIMER_S3 0x00000008 // Wide Timer 3 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCWTIMER_S2 0x00000004 // Wide Timer 2 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCWTIMER_S1 0x00000002 // Wide Timer 1 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCWTIMER_S0 0x00000001 // Wide Timer 0 Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCWD register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCWD_D1 0x00000002 // Watchdog Timer 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCWD_D0 0x00000001 // Watchdog Timer 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCTIMER_D5 0x00000020 // Timer 5 Deep-Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_DCGCTIMER_D4 0x00000010 // Timer 4 Deep-Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_DCGCTIMER_D3 0x00000008 // Timer 3 Deep-Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_DCGCTIMER_D2 0x00000004 // Timer 2 Deep-Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_DCGCTIMER_D1 0x00000002 // Timer 1 Deep-Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_DCGCTIMER_D0 0x00000001 // Timer 0 Deep-Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCGPIO
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCGPIO_D14 0x00004000 // GPIO Port Q Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D13 0x00002000 // GPIO Port P Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D12 0x00001000 // GPIO Port N Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D11 0x00000800 // GPIO Port M Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D10 0x00000400 // GPIO Port L Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D9 0x00000200 // GPIO Port K Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D8 0x00000100 // GPIO Port J Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D7 0x00000080 // GPIO Port H Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D6 0x00000040 // GPIO Port G Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D5 0x00000020 // GPIO Port F Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D4 0x00000010 // GPIO Port E Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D3 0x00000008 // GPIO Port D Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D2 0x00000004 // GPIO Port C Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D1 0x00000002 // GPIO Port B Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D0 0x00000001 // GPIO Port A Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCDMA_D0 0x00000001 // uDMA Module Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCHIB_D0 0x00000001 // Hibernation Module Deep-Sleep
+ // Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCUART
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCUART_D7 0x00000080 // UART Module 7 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCUART_D6 0x00000040 // UART Module 6 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCUART_D5 0x00000020 // UART Module 5 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCUART_D4 0x00000010 // UART Module 4 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCUART_D3 0x00000008 // UART Module 3 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCUART_D2 0x00000004 // UART Module 2 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCUART_D1 0x00000002 // UART Module 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCUART_D0 0x00000001 // UART Module 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCSSI_D3 0x00000008 // SSI Module 3 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCSSI_D2 0x00000004 // SSI Module 2 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCSSI_D1 0x00000002 // SSI Module 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCSSI_D0 0x00000001 // SSI Module 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCI2C_D5 0x00000020 // I2C Module 5 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCI2C_D4 0x00000010 // I2C Module 4 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCI2C_D3 0x00000008 // I2C Module 3 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCI2C_D2 0x00000004 // I2C Module 2 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCI2C_D1 0x00000002 // I2C Module 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCI2C_D0 0x00000001 // I2C Module 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCUSB_D0 0x00000001 // USB Module Deep-Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCCAN_D1 0x00000002 // CAN Module 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCCAN_D0 0x00000001 // CAN Module 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCADC register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCADC_D1 0x00000002 // ADC Module 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCADC_D0 0x00000001 // ADC Module 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCACMP
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCACMP_D0 0x00000001 // Analog Comparator Module 0
+ // Deep-Sleep Mode Clock Gating
+ // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCEEPROM_D0 0x00000001 // EEPROM Module Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCWTIMER_D5 0x00000020 // Wide Timer 5 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCWTIMER_D4 0x00000010 // Wide Timer 4 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCWTIMER_D3 0x00000008 // Wide Timer 3 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCWTIMER_D2 0x00000004 // Wide Timer 2 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCWTIMER_D1 0x00000002 // Wide Timer 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCWTIMER_D0 0x00000001 // Wide Timer 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCWD register.
+//
+//*****************************************************************************
+#define SYSCTL_PCWD_P1 0x00000002 // Watchdog Timer 1 Power Control
+#define SYSCTL_PCWD_P0 0x00000001 // Watchdog Timer 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCTIMER register.
+//
+//*****************************************************************************
+#define SYSCTL_PCTIMER_P5 0x00000020 // Timer 5 Power Control
+#define SYSCTL_PCTIMER_P4 0x00000010 // Timer 4 Power Control
+#define SYSCTL_PCTIMER_P3 0x00000008 // Timer 3 Power Control
+#define SYSCTL_PCTIMER_P2 0x00000004 // Timer 2 Power Control
+#define SYSCTL_PCTIMER_P1 0x00000002 // Timer 1 Power Control
+#define SYSCTL_PCTIMER_P0 0x00000001 // Timer 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCGPIO register.
+//
+//*****************************************************************************
+#define SYSCTL_PCGPIO_P14 0x00004000 // GPIO Port Q Power Control
+#define SYSCTL_PCGPIO_P13 0x00002000 // GPIO Port P Power Control
+#define SYSCTL_PCGPIO_P12 0x00001000 // GPIO Port N Power Control
+#define SYSCTL_PCGPIO_P11 0x00000800 // GPIO Port M Power Control
+#define SYSCTL_PCGPIO_P10 0x00000400 // GPIO Port L Power Control
+#define SYSCTL_PCGPIO_P9 0x00000200 // GPIO Port K Power Control
+#define SYSCTL_PCGPIO_P8 0x00000100 // GPIO Port J Power Control
+#define SYSCTL_PCGPIO_P7 0x00000080 // GPIO Port H Power Control
+#define SYSCTL_PCGPIO_P6 0x00000040 // GPIO Port G Power Control
+#define SYSCTL_PCGPIO_P5 0x00000020 // GPIO Port F Power Control
+#define SYSCTL_PCGPIO_P4 0x00000010 // GPIO Port E Power Control
+#define SYSCTL_PCGPIO_P3 0x00000008 // GPIO Port D Power Control
+#define SYSCTL_PCGPIO_P2 0x00000004 // GPIO Port C Power Control
+#define SYSCTL_PCGPIO_P1 0x00000002 // GPIO Port B Power Control
+#define SYSCTL_PCGPIO_P0 0x00000001 // GPIO Port A Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_PCDMA_P0 0x00000001 // uDMA Module Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_PCHIB_P0 0x00000001 // Hibernation Module Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCUART register.
+//
+//*****************************************************************************
+#define SYSCTL_PCUART_P7 0x00000080 // UART Module 7 Power Control
+#define SYSCTL_PCUART_P6 0x00000040 // UART Module 6 Power Control
+#define SYSCTL_PCUART_P5 0x00000020 // UART Module 5 Power Control
+#define SYSCTL_PCUART_P4 0x00000010 // UART Module 4 Power Control
+#define SYSCTL_PCUART_P3 0x00000008 // UART Module 3 Power Control
+#define SYSCTL_PCUART_P2 0x00000004 // UART Module 2 Power Control
+#define SYSCTL_PCUART_P1 0x00000002 // UART Module 1 Power Control
+#define SYSCTL_PCUART_P0 0x00000001 // UART Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_PCSSI_P3 0x00000008 // SSI Module 3 Power Control
+#define SYSCTL_PCSSI_P2 0x00000004 // SSI Module 2 Power Control
+#define SYSCTL_PCSSI_P1 0x00000002 // SSI Module 1 Power Control
+#define SYSCTL_PCSSI_P0 0x00000001 // SSI Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_PCI2C_P5 0x00000020 // I2C Module 5 Power Control
+#define SYSCTL_PCI2C_P4 0x00000010 // I2C Module 4 Power Control
+#define SYSCTL_PCI2C_P3 0x00000008 // I2C Module 3 Power Control
+#define SYSCTL_PCI2C_P2 0x00000004 // I2C Module 2 Power Control
+#define SYSCTL_PCI2C_P1 0x00000002 // I2C Module 1 Power Control
+#define SYSCTL_PCI2C_P0 0x00000001 // I2C Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_PCUSB_P0 0x00000001 // USB Module Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_PCCAN_P1 0x00000002 // CAN Module 1 Power Control
+#define SYSCTL_PCCAN_P0 0x00000001 // CAN Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCADC register.
+//
+//*****************************************************************************
+#define SYSCTL_PCADC_P1 0x00000002 // ADC Module 1 Power Control
+#define SYSCTL_PCADC_P0 0x00000001 // ADC Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCACMP register.
+//
+//*****************************************************************************
+#define SYSCTL_PCACMP_P0 0x00000001 // Analog Comparator Module 0 Power
+ // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PCEEPROM_P0 0x00000001 // EEPROM Module Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PCWTIMER_P5 0x00000020 // Wide Timer 5 Power Control
+#define SYSCTL_PCWTIMER_P4 0x00000010 // Wide Timer 4 Power Control
+#define SYSCTL_PCWTIMER_P3 0x00000008 // Wide Timer 3 Power Control
+#define SYSCTL_PCWTIMER_P2 0x00000004 // Wide Timer 2 Power Control
+#define SYSCTL_PCWTIMER_P1 0x00000002 // Wide Timer 1 Power Control
+#define SYSCTL_PCWTIMER_P0 0x00000001 // Wide Timer 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRWD register.
+//
+//*****************************************************************************
+#define SYSCTL_PRWD_R1 0x00000002 // Watchdog Timer 1 Peripheral
+ // Ready
+#define SYSCTL_PRWD_R0 0x00000001 // Watchdog Timer 0 Peripheral
+ // Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRTIMER register.
+//
+//*****************************************************************************
+#define SYSCTL_PRTIMER_R5 0x00000020 // Timer 5 Peripheral Ready
+#define SYSCTL_PRTIMER_R4 0x00000010 // Timer 4 Peripheral Ready
+#define SYSCTL_PRTIMER_R3 0x00000008 // Timer 3 Peripheral Ready
+#define SYSCTL_PRTIMER_R2 0x00000004 // Timer 2 Peripheral Ready
+#define SYSCTL_PRTIMER_R1 0x00000002 // Timer 1 Peripheral Ready
+#define SYSCTL_PRTIMER_R0 0x00000001 // Timer 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRGPIO register.
+//
+//*****************************************************************************
+#define SYSCTL_PRGPIO_R14 0x00004000 // GPIO Port Q Peripheral Ready
+#define SYSCTL_PRGPIO_R13 0x00002000 // GPIO Port P Peripheral Ready
+#define SYSCTL_PRGPIO_R12 0x00001000 // GPIO Port N Peripheral Ready
+#define SYSCTL_PRGPIO_R11 0x00000800 // GPIO Port M Peripheral Ready
+#define SYSCTL_PRGPIO_R10 0x00000400 // GPIO Port L Peripheral Ready
+#define SYSCTL_PRGPIO_R9 0x00000200 // GPIO Port K Peripheral Ready
+#define SYSCTL_PRGPIO_R8 0x00000100 // GPIO Port J Peripheral Ready
+#define SYSCTL_PRGPIO_R7 0x00000080 // GPIO Port H Peripheral Ready
+#define SYSCTL_PRGPIO_R6 0x00000040 // GPIO Port G Peripheral Ready
+#define SYSCTL_PRGPIO_R5 0x00000020 // GPIO Port F Peripheral Ready
+#define SYSCTL_PRGPIO_R4 0x00000010 // GPIO Port E Peripheral Ready
+#define SYSCTL_PRGPIO_R3 0x00000008 // GPIO Port D Peripheral Ready
+#define SYSCTL_PRGPIO_R2 0x00000004 // GPIO Port C Peripheral Ready
+#define SYSCTL_PRGPIO_R1 0x00000002 // GPIO Port B Peripheral Ready
+#define SYSCTL_PRGPIO_R0 0x00000001 // GPIO Port A Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_PRDMA_R0 0x00000001 // uDMA Module Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_PRHIB_R0 0x00000001 // Hibernation Module Peripheral
+ // Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRUART register.
+//
+//*****************************************************************************
+#define SYSCTL_PRUART_R7 0x00000080 // UART Module 7 Peripheral Ready
+#define SYSCTL_PRUART_R6 0x00000040 // UART Module 6 Peripheral Ready
+#define SYSCTL_PRUART_R5 0x00000020 // UART Module 5 Peripheral Ready
+#define SYSCTL_PRUART_R4 0x00000010 // UART Module 4 Peripheral Ready
+#define SYSCTL_PRUART_R3 0x00000008 // UART Module 3 Peripheral Ready
+#define SYSCTL_PRUART_R2 0x00000004 // UART Module 2 Peripheral Ready
+#define SYSCTL_PRUART_R1 0x00000002 // UART Module 1 Peripheral Ready
+#define SYSCTL_PRUART_R0 0x00000001 // UART Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_PRSSI_R3 0x00000008 // SSI Module 3 Peripheral Ready
+#define SYSCTL_PRSSI_R2 0x00000004 // SSI Module 2 Peripheral Ready
+#define SYSCTL_PRSSI_R1 0x00000002 // SSI Module 1 Peripheral Ready
+#define SYSCTL_PRSSI_R0 0x00000001 // SSI Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_PRI2C_R5 0x00000020 // I2C Module 5 Peripheral Ready
+#define SYSCTL_PRI2C_R4 0x00000010 // I2C Module 4 Peripheral Ready
+#define SYSCTL_PRI2C_R3 0x00000008 // I2C Module 3 Peripheral Ready
+#define SYSCTL_PRI2C_R2 0x00000004 // I2C Module 2 Peripheral Ready
+#define SYSCTL_PRI2C_R1 0x00000002 // I2C Module 1 Peripheral Ready
+#define SYSCTL_PRI2C_R0 0x00000001 // I2C Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_PRUSB_R0 0x00000001 // USB Module Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_PRCAN_R1 0x00000002 // CAN Module 1 Peripheral Ready
+#define SYSCTL_PRCAN_R0 0x00000001 // CAN Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRADC register.
+//
+//*****************************************************************************
+#define SYSCTL_PRADC_R1 0x00000002 // ADC Module 1 Peripheral Ready
+#define SYSCTL_PRADC_R0 0x00000001 // ADC Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRACMP register.
+//
+//*****************************************************************************
+#define SYSCTL_PRACMP_R0 0x00000001 // Analog Comparator Module 0
+ // Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PREEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PREEPROM_R0 0x00000001 // EEPROM Module Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PRWTIMER_R5 0x00000020 // Wide Timer 5 Peripheral Ready
+#define SYSCTL_PRWTIMER_R4 0x00000010 // Wide Timer 4 Peripheral Ready
+#define SYSCTL_PRWTIMER_R3 0x00000008 // Wide Timer 3 Peripheral Ready
+#define SYSCTL_PRWTIMER_R2 0x00000004 // Wide Timer 2 Peripheral Ready
+#define SYSCTL_PRWTIMER_R1 0x00000002 // Wide Timer 1 Peripheral Ready
+#define SYSCTL_PRWTIMER_R0 0x00000001 // Wide Timer 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_STAT register.
+//
+//*****************************************************************************
+#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available uDMA Channels Minus 1
+#define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine Status
+#define UDMA_STAT_STATE_IDLE 0x00000000 // Idle
+#define UDMA_STAT_STATE_RD_CTRL 0x00000010 // Reading channel controller data
+#define UDMA_STAT_STATE_RD_SRCENDP \
+ 0x00000020 // Reading source end pointer
+#define UDMA_STAT_STATE_RD_DSTENDP \
+ 0x00000030 // Reading destination end pointer
+#define UDMA_STAT_STATE_RD_SRCDAT \
+ 0x00000040 // Reading source data
+#define UDMA_STAT_STATE_WR_DSTDAT \
+ 0x00000050 // Writing destination data
+#define UDMA_STAT_STATE_WAIT 0x00000060 // Waiting for uDMA request to
+ // clear
+#define UDMA_STAT_STATE_WR_CTRL 0x00000070 // Writing channel controller data
+#define UDMA_STAT_STATE_STALL 0x00000080 // Stalled
+#define UDMA_STAT_STATE_DONE 0x00000090 // Done
+#define UDMA_STAT_STATE_UNDEF 0x000000A0 // Undefined
+#define UDMA_STAT_MASTEN 0x00000001 // Master Enable Status
+#define UDMA_STAT_DMACHANS_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CFG register.
+//
+//*****************************************************************************
+#define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CTLBASE register.
+//
+//*****************************************************************************
+#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address
+#define UDMA_CTLBASE_ADDR_S 10
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTBASE register.
+//
+//*****************************************************************************
+#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address
+ // Pointer
+#define UDMA_ALTBASE_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_WAITSTAT register.
+//
+//*****************************************************************************
+#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF // Channel [n] Wait Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_SWREQ register.
+//
+//*****************************************************************************
+#define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_USEBURSTSET
+// register.
+//
+//*****************************************************************************
+#define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF // Channel [n] Useburst Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_USEBURSTCLR
+// register.
+//
+//*****************************************************************************
+#define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF // Channel [n] Useburst Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_REQMASKSET
+// register.
+//
+//*****************************************************************************
+#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_REQMASKCLR
+// register.
+//
+//*****************************************************************************
+#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ENASET register.
+//
+//*****************************************************************************
+#define UDMA_ENASET_SET_M 0xFFFFFFFF // Channel [n] Enable Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ENACLR register.
+//
+//*****************************************************************************
+#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTSET register.
+//
+//*****************************************************************************
+#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTCLR register.
+//
+//*****************************************************************************
+#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_PRIOSET register.
+//
+//*****************************************************************************
+#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_PRIOCLR register.
+//
+//*****************************************************************************
+#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ERRCLR register.
+//
+//*****************************************************************************
+#define UDMA_ERRCLR_ERRCLR 0x00000001 // uDMA Bus Error Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHASGN register.
+//
+//*****************************************************************************
+#define UDMA_CHASGN_M 0xFFFFFFFF // Channel [n] Assignment Select
+#define UDMA_CHASGN_PRIMARY 0x00000000 // Use the primary channel
+ // assignment
+#define UDMA_CHASGN_SECONDARY 0x00000001 // Use the secondary channel
+ // assignment
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHIS register.
+//
+//*****************************************************************************
+#define UDMA_CHIS_M 0xFFFFFFFF // Channel [n] Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHMAP0 register.
+//
+//*****************************************************************************
+#define UDMA_CHMAP0_CH7SEL_M 0xF0000000 // uDMA Channel 7 Source Select
+#define UDMA_CHMAP0_CH6SEL_M 0x0F000000 // uDMA Channel 6 Source Select
+#define UDMA_CHMAP0_CH5SEL_M 0x00F00000 // uDMA Channel 5 Source Select
+#define UDMA_CHMAP0_CH4SEL_M 0x000F0000 // uDMA Channel 4 Source Select
+#define UDMA_CHMAP0_CH3SEL_M 0x0000F000 // uDMA Channel 3 Source Select
+#define UDMA_CHMAP0_CH2SEL_M 0x00000F00 // uDMA Channel 2 Source Select
+#define UDMA_CHMAP0_CH1SEL_M 0x000000F0 // uDMA Channel 1 Source Select
+#define UDMA_CHMAP0_CH0SEL_M 0x0000000F // uDMA Channel 0 Source Select
+#define UDMA_CHMAP0_CH7SEL_S 28
+#define UDMA_CHMAP0_CH6SEL_S 24
+#define UDMA_CHMAP0_CH5SEL_S 20
+#define UDMA_CHMAP0_CH4SEL_S 16
+#define UDMA_CHMAP0_CH3SEL_S 12
+#define UDMA_CHMAP0_CH2SEL_S 8
+#define UDMA_CHMAP0_CH1SEL_S 4
+#define UDMA_CHMAP0_CH0SEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHMAP1 register.
+//
+//*****************************************************************************
+#define UDMA_CHMAP1_CH15SEL_M 0xF0000000 // uDMA Channel 15 Source Select
+#define UDMA_CHMAP1_CH14SEL_M 0x0F000000 // uDMA Channel 14 Source Select
+#define UDMA_CHMAP1_CH13SEL_M 0x00F00000 // uDMA Channel 13 Source Select
+#define UDMA_CHMAP1_CH12SEL_M 0x000F0000 // uDMA Channel 12 Source Select
+#define UDMA_CHMAP1_CH11SEL_M 0x0000F000 // uDMA Channel 11 Source Select
+#define UDMA_CHMAP1_CH10SEL_M 0x00000F00 // uDMA Channel 10 Source Select
+#define UDMA_CHMAP1_CH9SEL_M 0x000000F0 // uDMA Channel 9 Source Select
+#define UDMA_CHMAP1_CH8SEL_M 0x0000000F // uDMA Channel 8 Source Select
+#define UDMA_CHMAP1_CH15SEL_S 28
+#define UDMA_CHMAP1_CH14SEL_S 24
+#define UDMA_CHMAP1_CH13SEL_S 20
+#define UDMA_CHMAP1_CH12SEL_S 16
+#define UDMA_CHMAP1_CH11SEL_S 12
+#define UDMA_CHMAP1_CH10SEL_S 8
+#define UDMA_CHMAP1_CH9SEL_S 4
+#define UDMA_CHMAP1_CH8SEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHMAP2 register.
+//
+//*****************************************************************************
+#define UDMA_CHMAP2_CH23SEL_M 0xF0000000 // uDMA Channel 23 Source Select
+#define UDMA_CHMAP2_CH22SEL_M 0x0F000000 // uDMA Channel 22 Source Select
+#define UDMA_CHMAP2_CH21SEL_M 0x00F00000 // uDMA Channel 21 Source Select
+#define UDMA_CHMAP2_CH20SEL_M 0x000F0000 // uDMA Channel 20 Source Select
+#define UDMA_CHMAP2_CH19SEL_M 0x0000F000 // uDMA Channel 19 Source Select
+#define UDMA_CHMAP2_CH18SEL_M 0x00000F00 // uDMA Channel 18 Source Select
+#define UDMA_CHMAP2_CH17SEL_M 0x000000F0 // uDMA Channel 17 Source Select
+#define UDMA_CHMAP2_CH16SEL_M 0x0000000F // uDMA Channel 16 Source Select
+#define UDMA_CHMAP2_CH23SEL_S 28
+#define UDMA_CHMAP2_CH22SEL_S 24
+#define UDMA_CHMAP2_CH21SEL_S 20
+#define UDMA_CHMAP2_CH20SEL_S 16
+#define UDMA_CHMAP2_CH19SEL_S 12
+#define UDMA_CHMAP2_CH18SEL_S 8
+#define UDMA_CHMAP2_CH17SEL_S 4
+#define UDMA_CHMAP2_CH16SEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHMAP3 register.
+//
+//*****************************************************************************
+#define UDMA_CHMAP3_CH31SEL_M 0xF0000000 // uDMA Channel 31 Source Select
+#define UDMA_CHMAP3_CH30SEL_M 0x0F000000 // uDMA Channel 30 Source Select
+#define UDMA_CHMAP3_CH29SEL_M 0x00F00000 // uDMA Channel 29 Source Select
+#define UDMA_CHMAP3_CH28SEL_M 0x000F0000 // uDMA Channel 28 Source Select
+#define UDMA_CHMAP3_CH27SEL_M 0x0000F000 // uDMA Channel 27 Source Select
+#define UDMA_CHMAP3_CH26SEL_M 0x00000F00 // uDMA Channel 26 Source Select
+#define UDMA_CHMAP3_CH25SEL_M 0x000000F0 // uDMA Channel 25 Source Select
+#define UDMA_CHMAP3_CH24SEL_M 0x0000000F // uDMA Channel 24 Source Select
+#define UDMA_CHMAP3_CH31SEL_S 28
+#define UDMA_CHMAP3_CH30SEL_S 24
+#define UDMA_CHMAP3_CH29SEL_S 20
+#define UDMA_CHMAP3_CH28SEL_S 16
+#define UDMA_CHMAP3_CH27SEL_S 12
+#define UDMA_CHMAP3_CH26SEL_S 8
+#define UDMA_CHMAP3_CH25SEL_S 4
+#define UDMA_CHMAP3_CH24SEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_SRCENDP register.
+//
+//*****************************************************************************
+#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer
+#define UDMA_SRCENDP_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_DSTENDP register.
+//
+//*****************************************************************************
+#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer
+#define UDMA_DSTENDP_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_CHCTL register.
+//
+//*****************************************************************************
+#define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment
+#define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte
+#define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word
+#define UDMA_CHCTL_DSTINC_32 0x80000000 // Word
+#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment
+#define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size
+#define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte
+#define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word
+#define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word
+#define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment
+#define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte
+#define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word
+#define UDMA_CHCTL_SRCINC_32 0x08000000 // Word
+#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment
+#define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size
+#define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte
+#define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word
+#define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word
+#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size
+#define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer
+#define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers
+#define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers
+#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers
+#define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers
+#define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers
+#define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers
+#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers
+#define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers
+#define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers
+#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers
+#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1)
+#define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst
+#define UDMA_CHCTL_XFERMODE_M 0x00000007 // uDMA Transfer Mode
+#define UDMA_CHCTL_XFERMODE_STOP \
+ 0x00000000 // Stop
+#define UDMA_CHCTL_XFERMODE_BASIC \
+ 0x00000001 // Basic
+#define UDMA_CHCTL_XFERMODE_AUTO \
+ 0x00000002 // Auto-Request
+#define UDMA_CHCTL_XFERMODE_PINGPONG \
+ 0x00000003 // Ping-Pong
+#define UDMA_CHCTL_XFERMODE_MEM_SG \
+ 0x00000004 // Memory Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_MEM_SGA \
+ 0x00000005 // Alternate Memory Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_PER_SG \
+ 0x00000006 // Peripheral Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_PER_SGA \
+ 0x00000007 // Alternate Peripheral
+ // Scatter-Gather
+#define UDMA_CHCTL_XFERSIZE_S 4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_INT_TYPE register.
+//
+//*****************************************************************************
+#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32)
+#define NVIC_INT_TYPE_LINES_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTLR register.
+//
+//*****************************************************************************
+#define NVIC_ACTLR_DISOOFP 0x00000200 // Disable Out-Of-Order Floating
+ // Point
+#define NVIC_ACTLR_DISFPCA 0x00000100 // Disable CONTROL
+#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding
+#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer
+#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple
+ // Cycle Instructions
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag
+#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source
+#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable
+#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_RELOAD register.
+//
+//*****************************************************************************
+#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value
+#define NVIC_ST_RELOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CURRENT
+// register.
+//
+//*****************************************************************************
+#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value
+#define NVIC_ST_CURRENT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CAL register.
+//
+//*****************************************************************************
+#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock
+#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew
+#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value
+#define NVIC_ST_CAL_ONEMS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN0 register.
+//
+//*****************************************************************************
+#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable
+#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable
+#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable
+#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable
+#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable
+#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable
+#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable
+#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable
+#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable
+#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable
+#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable
+#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable
+#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable
+#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable
+#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable
+#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable
+#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable
+#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable
+#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable
+#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable
+#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable
+#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable
+#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable
+#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable
+#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable
+#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable
+#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable
+#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable
+#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable
+#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable
+#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable
+#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable
+#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN1 register.
+//
+//*****************************************************************************
+#define NVIC_EN1_INT_M 0xFFFFFFFF // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN2 register.
+//
+//*****************************************************************************
+#define NVIC_EN2_INT_M 0xFFFFFFFF // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN3 register.
+//
+//*****************************************************************************
+#define NVIC_EN3_INT_M 0xFFFFFFFF // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN4 register.
+//
+//*****************************************************************************
+#define NVIC_EN4_INT_M 0x000007FF // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS0 register.
+//
+//*****************************************************************************
+#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable
+#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable
+#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable
+#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable
+#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable
+#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable
+#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable
+#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable
+#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable
+#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable
+#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable
+#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable
+#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable
+#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable
+#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable
+#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable
+#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable
+#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable
+#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable
+#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable
+#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable
+#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable
+#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable
+#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable
+#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable
+#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable
+#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable
+#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable
+#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable
+#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable
+#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable
+#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable
+#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS1 register.
+//
+//*****************************************************************************
+#define NVIC_DIS1_INT_M 0xFFFFFFFF // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS2 register.
+//
+//*****************************************************************************
+#define NVIC_DIS2_INT_M 0xFFFFFFFF // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS3 register.
+//
+//*****************************************************************************
+#define NVIC_DIS3_INT_M 0xFFFFFFFF // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS4 register.
+//
+//*****************************************************************************
+#define NVIC_DIS4_INT_M 0x000007FF // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND0 register.
+//
+//*****************************************************************************
+#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending
+#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend
+#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend
+#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend
+#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend
+#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend
+#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend
+#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend
+#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend
+#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend
+#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend
+#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend
+#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend
+#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend
+#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend
+#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend
+#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend
+#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend
+#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend
+#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend
+#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend
+#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend
+#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend
+#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend
+#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend
+#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend
+#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend
+#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend
+#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend
+#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend
+#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend
+#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend
+#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND1 register.
+//
+//*****************************************************************************
+#define NVIC_PEND1_INT_M 0xFFFFFFFF // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND2 register.
+//
+//*****************************************************************************
+#define NVIC_PEND2_INT_M 0xFFFFFFFF // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND3 register.
+//
+//*****************************************************************************
+#define NVIC_PEND3_INT_M 0xFFFFFFFF // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND4 register.
+//
+//*****************************************************************************
+#define NVIC_PEND4_INT_M 0x000007FF // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND0 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending
+#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend
+#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend
+#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend
+#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend
+#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend
+#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend
+#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend
+#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend
+#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend
+#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend
+#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend
+#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend
+#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend
+#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend
+#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend
+#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend
+#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend
+#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend
+#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend
+#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend
+#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend
+#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend
+#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend
+#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend
+#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend
+#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend
+#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend
+#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend
+#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend
+#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend
+#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend
+#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND1 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND1_INT_M 0xFFFFFFFF // Interrupt Clear Pending
+#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend
+#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend
+#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend
+#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend
+#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend
+#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend
+#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend
+#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend
+#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend
+#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend
+#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend
+#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend
+#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend
+#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend
+#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend
+#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend
+#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend
+#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend
+#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend
+#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend
+#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend
+#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend
+#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend
+#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND2 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND2_INT_M 0xFFFFFFFF // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND3 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND3_INT_M 0xFFFFFFFF // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND4 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND4_INT_M 0x000007FF // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE0 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active
+#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active
+#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active
+#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active
+#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active
+#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active
+#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active
+#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active
+#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active
+#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active
+#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active
+#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active
+#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active
+#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active
+#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active
+#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active
+#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active
+#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active
+#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active
+#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active
+#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active
+#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active
+#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active
+#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active
+#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active
+#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active
+#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active
+#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active
+#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active
+#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active
+#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active
+#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active
+#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE1 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE1_INT_M 0xFFFFFFFF // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE2 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE2_INT_M 0xFFFFFFFF // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE3 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE3_INT_M 0xFFFFFFFF // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE4 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE4_INT_M 0x000007FF // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI0 register.
+//
+//*****************************************************************************
+#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask
+#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask
+#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask
+#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask
+#define NVIC_PRI0_INT3_S 29
+#define NVIC_PRI0_INT2_S 21
+#define NVIC_PRI0_INT1_S 13
+#define NVIC_PRI0_INT0_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask
+#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask
+#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask
+#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask
+#define NVIC_PRI1_INT7_S 29
+#define NVIC_PRI1_INT6_S 21
+#define NVIC_PRI1_INT5_S 13
+#define NVIC_PRI1_INT4_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask
+#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask
+#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask
+#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask
+#define NVIC_PRI2_INT11_S 29
+#define NVIC_PRI2_INT10_S 21
+#define NVIC_PRI2_INT9_S 13
+#define NVIC_PRI2_INT8_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask
+#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask
+#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask
+#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask
+#define NVIC_PRI3_INT15_S 29
+#define NVIC_PRI3_INT14_S 21
+#define NVIC_PRI3_INT13_S 13
+#define NVIC_PRI3_INT12_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI4 register.
+//
+//*****************************************************************************
+#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask
+#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask
+#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask
+#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask
+#define NVIC_PRI4_INT19_S 29
+#define NVIC_PRI4_INT18_S 21
+#define NVIC_PRI4_INT17_S 13
+#define NVIC_PRI4_INT16_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI5 register.
+//
+//*****************************************************************************
+#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask
+#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask
+#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask
+#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask
+#define NVIC_PRI5_INT23_S 29
+#define NVIC_PRI5_INT22_S 21
+#define NVIC_PRI5_INT21_S 13
+#define NVIC_PRI5_INT20_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI6 register.
+//
+//*****************************************************************************
+#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask
+#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask
+#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask
+#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask
+#define NVIC_PRI6_INT27_S 29
+#define NVIC_PRI6_INT26_S 21
+#define NVIC_PRI6_INT25_S 13
+#define NVIC_PRI6_INT24_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI7 register.
+//
+//*****************************************************************************
+#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask
+#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask
+#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask
+#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask
+#define NVIC_PRI7_INT31_S 29
+#define NVIC_PRI7_INT30_S 21
+#define NVIC_PRI7_INT29_S 13
+#define NVIC_PRI7_INT28_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI8 register.
+//
+//*****************************************************************************
+#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask
+#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask
+#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask
+#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask
+#define NVIC_PRI8_INT35_S 29
+#define NVIC_PRI8_INT34_S 21
+#define NVIC_PRI8_INT33_S 13
+#define NVIC_PRI8_INT32_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI9 register.
+//
+//*****************************************************************************
+#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask
+#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask
+#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask
+#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask
+#define NVIC_PRI9_INT39_S 29
+#define NVIC_PRI9_INT38_S 21
+#define NVIC_PRI9_INT37_S 13
+#define NVIC_PRI9_INT36_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI10 register.
+//
+//*****************************************************************************
+#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask
+#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask
+#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask
+#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask
+#define NVIC_PRI10_INT43_S 29
+#define NVIC_PRI10_INT42_S 21
+#define NVIC_PRI10_INT41_S 13
+#define NVIC_PRI10_INT40_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI11 register.
+//
+//*****************************************************************************
+#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask
+#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask
+#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask
+#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask
+#define NVIC_PRI11_INT47_S 29
+#define NVIC_PRI11_INT46_S 21
+#define NVIC_PRI11_INT45_S 13
+#define NVIC_PRI11_INT44_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI12 register.
+//
+//*****************************************************************************
+#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask
+#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask
+#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask
+#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask
+#define NVIC_PRI12_INT51_S 29
+#define NVIC_PRI12_INT50_S 21
+#define NVIC_PRI12_INT49_S 13
+#define NVIC_PRI12_INT48_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI13 register.
+//
+//*****************************************************************************
+#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask
+#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask
+#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask
+#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask
+#define NVIC_PRI13_INT55_S 29
+#define NVIC_PRI13_INT54_S 21
+#define NVIC_PRI13_INT53_S 13
+#define NVIC_PRI13_INT52_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI14 register.
+//
+//*****************************************************************************
+#define NVIC_PRI14_INTD_M 0xE0000000 // Interrupt 59 Priority Mask
+#define NVIC_PRI14_INTC_M 0x00E00000 // Interrupt 58 Priority Mask
+#define NVIC_PRI14_INTB_M 0x0000E000 // Interrupt 57 Priority Mask
+#define NVIC_PRI14_INTA_M 0x000000E0 // Interrupt 56 Priority Mask
+#define NVIC_PRI14_INTD_S 29
+#define NVIC_PRI14_INTC_S 21
+#define NVIC_PRI14_INTB_S 13
+#define NVIC_PRI14_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI15 register.
+//
+//*****************************************************************************
+#define NVIC_PRI15_INTD_M 0xE0000000 // Interrupt 63 Priority Mask
+#define NVIC_PRI15_INTC_M 0x00E00000 // Interrupt 62 Priority Mask
+#define NVIC_PRI15_INTB_M 0x0000E000 // Interrupt 61 Priority Mask
+#define NVIC_PRI15_INTA_M 0x000000E0 // Interrupt 60 Priority Mask
+#define NVIC_PRI15_INTD_S 29
+#define NVIC_PRI15_INTC_S 21
+#define NVIC_PRI15_INTB_S 13
+#define NVIC_PRI15_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI16 register.
+//
+//*****************************************************************************
+#define NVIC_PRI16_INTD_M 0xE0000000 // Interrupt 67 Priority Mask
+#define NVIC_PRI16_INTC_M 0x00E00000 // Interrupt 66 Priority Mask
+#define NVIC_PRI16_INTB_M 0x0000E000 // Interrupt 65 Priority Mask
+#define NVIC_PRI16_INTA_M 0x000000E0 // Interrupt 64 Priority Mask
+#define NVIC_PRI16_INTD_S 29
+#define NVIC_PRI16_INTC_S 21
+#define NVIC_PRI16_INTB_S 13
+#define NVIC_PRI16_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI17 register.
+//
+//*****************************************************************************
+#define NVIC_PRI17_INTD_M 0xE0000000 // Interrupt 71 Priority Mask
+#define NVIC_PRI17_INTC_M 0x00E00000 // Interrupt 70 Priority Mask
+#define NVIC_PRI17_INTB_M 0x0000E000 // Interrupt 69 Priority Mask
+#define NVIC_PRI17_INTA_M 0x000000E0 // Interrupt 68 Priority Mask
+#define NVIC_PRI17_INTD_S 29
+#define NVIC_PRI17_INTC_S 21
+#define NVIC_PRI17_INTB_S 13
+#define NVIC_PRI17_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI18 register.
+//
+//*****************************************************************************
+#define NVIC_PRI18_INTD_M 0xE0000000 // Interrupt 75 Priority Mask
+#define NVIC_PRI18_INTC_M 0x00E00000 // Interrupt 74 Priority Mask
+#define NVIC_PRI18_INTB_M 0x0000E000 // Interrupt 73 Priority Mask
+#define NVIC_PRI18_INTA_M 0x000000E0 // Interrupt 72 Priority Mask
+#define NVIC_PRI18_INTD_S 29
+#define NVIC_PRI18_INTC_S 21
+#define NVIC_PRI18_INTB_S 13
+#define NVIC_PRI18_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI19 register.
+//
+//*****************************************************************************
+#define NVIC_PRI19_INTD_M 0xE0000000 // Interrupt 79 Priority Mask
+#define NVIC_PRI19_INTC_M 0x00E00000 // Interrupt 78 Priority Mask
+#define NVIC_PRI19_INTB_M 0x0000E000 // Interrupt 77 Priority Mask
+#define NVIC_PRI19_INTA_M 0x000000E0 // Interrupt 76 Priority Mask
+#define NVIC_PRI19_INTD_S 29
+#define NVIC_PRI19_INTC_S 21
+#define NVIC_PRI19_INTB_S 13
+#define NVIC_PRI19_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI20 register.
+//
+//*****************************************************************************
+#define NVIC_PRI20_INTD_M 0xE0000000 // Interrupt 83 Priority Mask
+#define NVIC_PRI20_INTC_M 0x00E00000 // Interrupt 82 Priority Mask
+#define NVIC_PRI20_INTB_M 0x0000E000 // Interrupt 81 Priority Mask
+#define NVIC_PRI20_INTA_M 0x000000E0 // Interrupt 80 Priority Mask
+#define NVIC_PRI20_INTD_S 29
+#define NVIC_PRI20_INTC_S 21
+#define NVIC_PRI20_INTB_S 13
+#define NVIC_PRI20_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI21 register.
+//
+//*****************************************************************************
+#define NVIC_PRI21_INTD_M 0xE0000000 // Interrupt 87 Priority Mask
+#define NVIC_PRI21_INTC_M 0x00E00000 // Interrupt 86 Priority Mask
+#define NVIC_PRI21_INTB_M 0x0000E000 // Interrupt 85 Priority Mask
+#define NVIC_PRI21_INTA_M 0x000000E0 // Interrupt 84 Priority Mask
+#define NVIC_PRI21_INTD_S 29
+#define NVIC_PRI21_INTC_S 21
+#define NVIC_PRI21_INTB_S 13
+#define NVIC_PRI21_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI22 register.
+//
+//*****************************************************************************
+#define NVIC_PRI22_INTD_M 0xE0000000 // Interrupt 91 Priority Mask
+#define NVIC_PRI22_INTC_M 0x00E00000 // Interrupt 90 Priority Mask
+#define NVIC_PRI22_INTB_M 0x0000E000 // Interrupt 89 Priority Mask
+#define NVIC_PRI22_INTA_M 0x000000E0 // Interrupt 88 Priority Mask
+#define NVIC_PRI22_INTD_S 29
+#define NVIC_PRI22_INTC_S 21
+#define NVIC_PRI22_INTB_S 13
+#define NVIC_PRI22_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI23 register.
+//
+//*****************************************************************************
+#define NVIC_PRI23_INTD_M 0xE0000000 // Interrupt 95 Priority Mask
+#define NVIC_PRI23_INTC_M 0x00E00000 // Interrupt 94 Priority Mask
+#define NVIC_PRI23_INTB_M 0x0000E000 // Interrupt 93 Priority Mask
+#define NVIC_PRI23_INTA_M 0x000000E0 // Interrupt 92 Priority Mask
+#define NVIC_PRI23_INTD_S 29
+#define NVIC_PRI23_INTC_S 21
+#define NVIC_PRI23_INTB_S 13
+#define NVIC_PRI23_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI24 register.
+//
+//*****************************************************************************
+#define NVIC_PRI24_INTD_M 0xE0000000 // Interrupt 99 Priority Mask
+#define NVIC_PRI24_INTC_M 0x00E00000 // Interrupt 98 Priority Mask
+#define NVIC_PRI24_INTB_M 0x0000E000 // Interrupt 97 Priority Mask
+#define NVIC_PRI24_INTA_M 0x000000E0 // Interrupt 96 Priority Mask
+#define NVIC_PRI24_INTD_S 29
+#define NVIC_PRI24_INTC_S 21
+#define NVIC_PRI24_INTB_S 13
+#define NVIC_PRI24_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI25 register.
+//
+//*****************************************************************************
+#define NVIC_PRI25_INTD_M 0xE0000000 // Interrupt 103 Priority Mask
+#define NVIC_PRI25_INTC_M 0x00E00000 // Interrupt 102 Priority Mask
+#define NVIC_PRI25_INTB_M 0x0000E000 // Interrupt 101 Priority Mask
+#define NVIC_PRI25_INTA_M 0x000000E0 // Interrupt 100 Priority Mask
+#define NVIC_PRI25_INTD_S 29
+#define NVIC_PRI25_INTC_S 21
+#define NVIC_PRI25_INTB_S 13
+#define NVIC_PRI25_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI26 register.
+//
+//*****************************************************************************
+#define NVIC_PRI26_INTD_M 0xE0000000 // Interrupt 107 Priority Mask
+#define NVIC_PRI26_INTC_M 0x00E00000 // Interrupt 106 Priority Mask
+#define NVIC_PRI26_INTB_M 0x0000E000 // Interrupt 105 Priority Mask
+#define NVIC_PRI26_INTA_M 0x000000E0 // Interrupt 104 Priority Mask
+#define NVIC_PRI26_INTD_S 29
+#define NVIC_PRI26_INTC_S 21
+#define NVIC_PRI26_INTB_S 13
+#define NVIC_PRI26_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI27 register.
+//
+//*****************************************************************************
+#define NVIC_PRI27_INTD_M 0xE0000000 // Interrupt 111 Priority Mask
+#define NVIC_PRI27_INTC_M 0x00E00000 // Interrupt 110 Priority Mask
+#define NVIC_PRI27_INTB_M 0x0000E000 // Interrupt 109 Priority Mask
+#define NVIC_PRI27_INTA_M 0x000000E0 // Interrupt 108 Priority Mask
+#define NVIC_PRI27_INTD_S 29
+#define NVIC_PRI27_INTC_S 21
+#define NVIC_PRI27_INTB_S 13
+#define NVIC_PRI27_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI28 register.
+//
+//*****************************************************************************
+#define NVIC_PRI28_INTD_M 0xE0000000 // Interrupt 115 Priority Mask
+#define NVIC_PRI28_INTC_M 0x00E00000 // Interrupt 114 Priority Mask
+#define NVIC_PRI28_INTB_M 0x0000E000 // Interrupt 113 Priority Mask
+#define NVIC_PRI28_INTA_M 0x000000E0 // Interrupt 112 Priority Mask
+#define NVIC_PRI28_INTD_S 29
+#define NVIC_PRI28_INTC_S 21
+#define NVIC_PRI28_INTB_S 13
+#define NVIC_PRI28_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI29 register.
+//
+//*****************************************************************************
+#define NVIC_PRI29_INTD_M 0xE0000000 // Interrupt 119 Priority Mask
+#define NVIC_PRI29_INTC_M 0x00E00000 // Interrupt 118 Priority Mask
+#define NVIC_PRI29_INTB_M 0x0000E000 // Interrupt 117 Priority Mask
+#define NVIC_PRI29_INTA_M 0x000000E0 // Interrupt 116 Priority Mask
+#define NVIC_PRI29_INTD_S 29
+#define NVIC_PRI29_INTC_S 21
+#define NVIC_PRI29_INTB_S 13
+#define NVIC_PRI29_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI30 register.
+//
+//*****************************************************************************
+#define NVIC_PRI30_INTD_M 0xE0000000 // Interrupt 123 Priority Mask
+#define NVIC_PRI30_INTC_M 0x00E00000 // Interrupt 122 Priority Mask
+#define NVIC_PRI30_INTB_M 0x0000E000 // Interrupt 121 Priority Mask
+#define NVIC_PRI30_INTA_M 0x000000E0 // Interrupt 120 Priority Mask
+#define NVIC_PRI30_INTD_S 29
+#define NVIC_PRI30_INTC_S 21
+#define NVIC_PRI30_INTB_S 13
+#define NVIC_PRI30_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI31 register.
+//
+//*****************************************************************************
+#define NVIC_PRI31_INTD_M 0xE0000000 // Interrupt 127 Priority Mask
+#define NVIC_PRI31_INTC_M 0x00E00000 // Interrupt 126 Priority Mask
+#define NVIC_PRI31_INTB_M 0x0000E000 // Interrupt 125 Priority Mask
+#define NVIC_PRI31_INTA_M 0x000000E0 // Interrupt 124 Priority Mask
+#define NVIC_PRI31_INTD_S 29
+#define NVIC_PRI31_INTC_S 21
+#define NVIC_PRI31_INTB_S 13
+#define NVIC_PRI31_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI32 register.
+//
+//*****************************************************************************
+#define NVIC_PRI32_INTD_M 0xE0000000 // Interrupt 131 Priority Mask
+#define NVIC_PRI32_INTC_M 0x00E00000 // Interrupt 130 Priority Mask
+#define NVIC_PRI32_INTB_M 0x0000E000 // Interrupt 129 Priority Mask
+#define NVIC_PRI32_INTA_M 0x000000E0 // Interrupt 128 Priority Mask
+#define NVIC_PRI32_INTD_S 29
+#define NVIC_PRI32_INTC_S 21
+#define NVIC_PRI32_INTB_S 13
+#define NVIC_PRI32_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI33 register.
+//
+//*****************************************************************************
+#define NVIC_PRI33_INTD_M 0xE0000000 // Interrupt Priority for Interrupt
+ // [4n+3]
+#define NVIC_PRI33_INTC_M 0x00E00000 // Interrupt Priority for Interrupt
+ // [4n+2]
+#define NVIC_PRI33_INTB_M 0x0000E000 // Interrupt Priority for Interrupt
+ // [4n+1]
+#define NVIC_PRI33_INTA_M 0x000000E0 // Interrupt Priority for Interrupt
+ // [4n]
+#define NVIC_PRI33_INTD_S 29
+#define NVIC_PRI33_INTC_S 21
+#define NVIC_PRI33_INTB_S 13
+#define NVIC_PRI33_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI34 register.
+//
+//*****************************************************************************
+#define NVIC_PRI34_INTD_M 0xE0000000 // Interrupt Priority for Interrupt
+ // [4n+3]
+#define NVIC_PRI34_INTC_M 0x00E00000 // Interrupt Priority for Interrupt
+ // [4n+2]
+#define NVIC_PRI34_INTB_M 0x0000E000 // Interrupt Priority for Interrupt
+ // [4n+1]
+#define NVIC_PRI34_INTA_M 0x000000E0 // Interrupt Priority for Interrupt
+ // [4n]
+#define NVIC_PRI34_INTD_S 29
+#define NVIC_PRI34_INTC_S 21
+#define NVIC_PRI34_INTB_S 13
+#define NVIC_PRI34_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CPUID register.
+//
+//*****************************************************************************
+#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code
+#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM
+#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number
+#define NVIC_CPUID_CON_M 0x000F0000 // Constant
+#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number
+#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor
+#define NVIC_CPUID_REV_M 0x0000000F // Revision Number
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_INT_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending
+#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending
+#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending
+#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending
+#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending
+#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling
+#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending
+#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number
+#define NVIC_INT_CTRL_VEC_PEN_NMI \
+ 0x00002000 // NMI
+#define NVIC_INT_CTRL_VEC_PEN_HARD \
+ 0x00003000 // Hard fault
+#define NVIC_INT_CTRL_VEC_PEN_MEM \
+ 0x00004000 // Memory management fault
+#define NVIC_INT_CTRL_VEC_PEN_BUS \
+ 0x00005000 // Bus fault
+#define NVIC_INT_CTRL_VEC_PEN_USG \
+ 0x00006000 // Usage fault
+#define NVIC_INT_CTRL_VEC_PEN_SVC \
+ 0x0000B000 // SVCall
+#define NVIC_INT_CTRL_VEC_PEN_PNDSV \
+ 0x0000E000 // PendSV
+#define NVIC_INT_CTRL_VEC_PEN_TICK \
+ 0x0000F000 // SysTick
+#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base
+#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number
+#define NVIC_INT_CTRL_VEC_ACT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_VTABLE register.
+//
+//*****************************************************************************
+#define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base
+#define NVIC_VTABLE_OFFSET_M 0x1FFFFC00 // Vector Table Offset
+#define NVIC_VTABLE_OFFSET_S 10
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_APINT register.
+//
+//*****************************************************************************
+#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key
+#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key
+#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess
+#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping
+#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split
+#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split
+#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split
+#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request
+#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault
+#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending
+#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable
+#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CFG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception
+ // Entry
+#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and
+ // Fault
+#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0
+#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access
+#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger
+#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority
+#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority
+#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority
+#define NVIC_SYS_PRI1_USAGE_S 21
+#define NVIC_SYS_PRI1_BUS_S 13
+#define NVIC_SYS_PRI1_MEM_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority
+#define NVIC_SYS_PRI2_SVC_S 29
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority
+#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority
+#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority
+#define NVIC_SYS_PRI3_TICK_S 29
+#define NVIC_SYS_PRI3_PENDSV_S 21
+#define NVIC_SYS_PRI3_DEBUG_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL
+// register.
+//
+//*****************************************************************************
+#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable
+#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable
+#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable
+#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending
+#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending
+#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending
+#define NVIC_SYS_HND_CTRL_USAGEP \
+ 0x00001000 // Usage Fault Pending
+#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active
+#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active
+#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active
+#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active
+#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active
+#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active
+#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault
+#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault
+#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault
+#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault
+#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault
+#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage
+ // Fault
+#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid
+#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy
+ // State Preservation
+#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault
+#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault
+#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error
+#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error
+#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error
+#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address
+ // Register Valid
+#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on
+ // Floating-Point Lazy State
+ // Preservation
+#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation
+#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation
+#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation
+#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_HFAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event
+#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault
+#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DEBUG_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted
+#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch
+#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match
+#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction
+#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MM_ADDR register.
+//
+//*****************************************************************************
+#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address
+#define NVIC_MM_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_ADDR
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address
+#define NVIC_FAULT_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CPAC register.
+//
+//*****************************************************************************
+#define NVIC_CPAC_CP11_M 0x00C00000 // CP11 Coprocessor Access
+ // Privilege
+#define NVIC_CPAC_CP11_DIS 0x00000000 // Access Denied
+#define NVIC_CPAC_CP11_PRIV 0x00400000 // Privileged Access Only
+#define NVIC_CPAC_CP11_FULL 0x00C00000 // Full Access
+#define NVIC_CPAC_CP10_M 0x00300000 // CP10 Coprocessor Access
+ // Privilege
+#define NVIC_CPAC_CP10_DIS 0x00000000 // Access Denied
+#define NVIC_CPAC_CP10_PRIV 0x00100000 // Privileged Access Only
+#define NVIC_CPAC_CP10_FULL 0x00300000 // Full Access
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_TYPE register.
+//
+//*****************************************************************************
+#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I Regions
+#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D Regions
+#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or Unified MPU
+#define NVIC_MPU_TYPE_IREGION_S 16
+#define NVIC_MPU_TYPE_DREGION_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU Default Region
+#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU Enabled During Faults
+#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_NUMBER
+// register.
+//
+//*****************************************************************************
+#define NVIC_MPU_NUMBER_M 0x00000007 // MPU Region to Access
+#define NVIC_MPU_NUMBER_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base Address Mask
+#define NVIC_MPU_BASE_VALID 0x00000010 // Region Number Valid
+#define NVIC_MPU_BASE_REGION_M 0x00000007 // Region Number
+#define NVIC_MPU_BASE_ADDR_S 5
+#define NVIC_MPU_BASE_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR_XN 0x10000000 // Instruction Access Disable
+#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access Privilege
+#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type Extension Mask
+#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable
+#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable
+#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable
+#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Subregion Disable Bits
+#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region Size Mask
+#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE1 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE1_ADDR_M 0xFFFFFFE0 // Base Address Mask
+#define NVIC_MPU_BASE1_VALID 0x00000010 // Region Number Valid
+#define NVIC_MPU_BASE1_REGION_M 0x00000007 // Region Number
+#define NVIC_MPU_BASE1_ADDR_S 5
+#define NVIC_MPU_BASE1_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR1_XN 0x10000000 // Instruction Access Disable
+#define NVIC_MPU_ATTR1_AP_M 0x07000000 // Access Privilege
+#define NVIC_MPU_ATTR1_TEX_M 0x00380000 // Type Extension Mask
+#define NVIC_MPU_ATTR1_SHAREABLE \
+ 0x00040000 // Shareable
+#define NVIC_MPU_ATTR1_CACHEABLE \
+ 0x00020000 // Cacheable
+#define NVIC_MPU_ATTR1_BUFFRABLE \
+ 0x00010000 // Bufferable
+#define NVIC_MPU_ATTR1_SRD_M 0x0000FF00 // Subregion Disable Bits
+#define NVIC_MPU_ATTR1_SIZE_M 0x0000003E // Region Size Mask
+#define NVIC_MPU_ATTR1_ENABLE 0x00000001 // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE2 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE2_ADDR_M 0xFFFFFFE0 // Base Address Mask
+#define NVIC_MPU_BASE2_VALID 0x00000010 // Region Number Valid
+#define NVIC_MPU_BASE2_REGION_M 0x00000007 // Region Number
+#define NVIC_MPU_BASE2_ADDR_S 5
+#define NVIC_MPU_BASE2_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR2_XN 0x10000000 // Instruction Access Disable
+#define NVIC_MPU_ATTR2_AP_M 0x07000000 // Access Privilege
+#define NVIC_MPU_ATTR2_TEX_M 0x00380000 // Type Extension Mask
+#define NVIC_MPU_ATTR2_SHAREABLE \
+ 0x00040000 // Shareable
+#define NVIC_MPU_ATTR2_CACHEABLE \
+ 0x00020000 // Cacheable
+#define NVIC_MPU_ATTR2_BUFFRABLE \
+ 0x00010000 // Bufferable
+#define NVIC_MPU_ATTR2_SRD_M 0x0000FF00 // Subregion Disable Bits
+#define NVIC_MPU_ATTR2_SIZE_M 0x0000003E // Region Size Mask
+#define NVIC_MPU_ATTR2_ENABLE 0x00000001 // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE3 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE3_ADDR_M 0xFFFFFFE0 // Base Address Mask
+#define NVIC_MPU_BASE3_VALID 0x00000010 // Region Number Valid
+#define NVIC_MPU_BASE3_REGION_M 0x00000007 // Region Number
+#define NVIC_MPU_BASE3_ADDR_S 5
+#define NVIC_MPU_BASE3_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR3_XN 0x10000000 // Instruction Access Disable
+#define NVIC_MPU_ATTR3_AP_M 0x07000000 // Access Privilege
+#define NVIC_MPU_ATTR3_TEX_M 0x00380000 // Type Extension Mask
+#define NVIC_MPU_ATTR3_SHAREABLE \
+ 0x00040000 // Shareable
+#define NVIC_MPU_ATTR3_CACHEABLE \
+ 0x00020000 // Cacheable
+#define NVIC_MPU_ATTR3_BUFFRABLE \
+ 0x00010000 // Bufferable
+#define NVIC_MPU_ATTR3_SRD_M 0x0000FF00 // Subregion Disable Bits
+#define NVIC_MPU_ATTR3_SIZE_M 0x0000003E // Region Size Mask
+#define NVIC_MPU_ATTR3_ENABLE 0x00000001 // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask
+#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key
+#define NVIC_DBG_CTRL_S_RESET_ST \
+ 0x02000000 // Core has reset since last read
+#define NVIC_DBG_CTRL_S_RETIRE_ST \
+ 0x01000000 // Core has executed insruction
+ // since last read
+#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up
+#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping
+#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt
+#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available
+#define NVIC_DBG_CTRL_C_SNAPSTALL \
+ 0x00000020 // Breaks a stalled load/store
+#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping
+#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core
+#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core
+#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_XFER register.
+//
+//*****************************************************************************
+#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read
+#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register
+#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0
+#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1
+#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2
+#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3
+#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4
+#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5
+#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6
+#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7
+#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8
+#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9
+#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10
+#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11
+#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12
+#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13
+#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14
+#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15
+#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register
+#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP
+#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP
+#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP
+#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_DATA register.
+//
+//*****************************************************************************
+#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache
+#define NVIC_DBG_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_INT register.
+//
+//*****************************************************************************
+#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault
+#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors
+#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error
+#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state
+#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check
+#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error
+#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault
+#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status
+#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset
+#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending
+#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SW_TRIG register.
+//
+//*****************************************************************************
+#define NVIC_SW_TRIG_INTID_M 0x000000FF // Interrupt ID
+#define NVIC_SW_TRIG_INTID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FPCC register.
+//
+//*****************************************************************************
+#define NVIC_FPCC_ASPEN 0x80000000 // Automatic State Preservation
+ // Enable
+#define NVIC_FPCC_LSPEN 0x40000000 // Lazy State Preservation Enable
+#define NVIC_FPCC_MONRDY 0x00000100 // Monitor Ready
+#define NVIC_FPCC_BFRDY 0x00000040 // Bus Fault Ready
+#define NVIC_FPCC_MMRDY 0x00000020 // Memory Management Fault Ready
+#define NVIC_FPCC_HFRDY 0x00000010 // Hard Fault Ready
+#define NVIC_FPCC_THREAD 0x00000008 // Thread Mode
+#define NVIC_FPCC_USER 0x00000002 // User Privilege Level
+#define NVIC_FPCC_LSPACT 0x00000001 // Lazy State Preservation Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FPCA register.
+//
+//*****************************************************************************
+#define NVIC_FPCA_ADDRESS_M 0xFFFFFFF8 // Address
+#define NVIC_FPCA_ADDRESS_S 3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FPDSC register.
+//
+//*****************************************************************************
+#define NVIC_FPDSC_AHP 0x04000000 // AHP Bit Default
+#define NVIC_FPDSC_DN 0x02000000 // DN Bit Default
+#define NVIC_FPDSC_FZ 0x01000000 // FZ Bit Default
+#define NVIC_FPDSC_RMODE_M 0x00C00000 // RMODE Bit Default
+#define NVIC_FPDSC_RMODE_RN 0x00000000 // Round to Nearest (RN) mode
+#define NVIC_FPDSC_RMODE_RP 0x00400000 // Round towards Plus Infinity (RP)
+ // mode
+#define NVIC_FPDSC_RMODE_RM 0x00800000 // Round towards Minus Infinity
+ // (RM) mode
+#define NVIC_FPDSC_RMODE_RZ 0x00C00000 // Round towards Zero (RZ) mode
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// Deprecated defines for the EEPROM register offsets.
+//
+//*****************************************************************************
+#define EEPROM_EEPROMPP_R (*((volatile unsigned long *)0x400AFFC0))
+
+//*****************************************************************************
+//
+// Deprecated defines for the bit fields in the EEPROM_EEPROMPP register.
+//
+//*****************************************************************************
+#define EEPROM_EEPROMPP_SIZE_M 0x0000001F // EEPROM Size
+#define EEPROM_EEPROMPP_SIZE_S 0
+
+#endif
+
+#endif // __LM4F120H5QR_H__
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