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authorYuval Adam <_@yuv.al>2025-08-29 20:06:55 +0200
committerYuval Adam <_@yuv.al>2025-08-29 20:06:55 +0200
commitd096f707822967aa99d37605198fc9acd5f6a90d (patch)
treedd22876cbde04b2ae27b21817622a2fe5f163204
parent4f9dc0d6456ff9da22b44ff46d4ac52500fbeb27 (diff)
Blinky works
-rw-r--r--.gitignore5
-rw-r--r--99-alchitry-xilinx.rules25
-rw-r--r--build_and_program.py16
-rw-r--r--list_targets.tcl8
-rw-r--r--platform_alchitry_pt.py9
-rw-r--r--test_connection.tcl7
6 files changed, 66 insertions, 4 deletions
diff --git a/.gitignore b/.gitignore
index ae4e658..a8cdd35 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,4 +1,7 @@
.venv/
build/
-__pycache__ \ No newline at end of file
+__pycache__
+
+*.log
+*.jou \ No newline at end of file
diff --git a/99-alchitry-xilinx.rules b/99-alchitry-xilinx.rules
new file mode 100644
index 0000000..4b443f7
--- /dev/null
+++ b/99-alchitry-xilinx.rules
@@ -0,0 +1,25 @@
+# Alchitry Pt v2 and Xilinx programming cables udev rules
+# Install to /etc/udev/rules.d/ and run: sudo udevadm control --reload-rules && sudo udevadm trigger
+
+# FTDI FT2232 (used by Alchitry boards)
+SUBSYSTEM=="usb", ATTR{idVendor}=="0403", ATTR{idProduct}=="6010", MODE="0666"
+SUBSYSTEM=="usb", ATTR{idVendor}=="0403", ATTR{idProduct}=="6014", MODE="0666"
+
+# Xilinx Platform Cable USB II
+SUBSYSTEM=="usb", ATTR{idVendor}=="03fd", ATTR{idProduct}=="0008", MODE="0666"
+SUBSYSTEM=="usb", ATTR{idVendor}=="03fd", ATTR{idProduct}=="0007", MODE="0666"
+SUBSYSTEM=="usb", ATTR{idVendor}=="03fd", ATTR{idProduct}=="0009", MODE="0666"
+SUBSYSTEM=="usb", ATTR{idVendor}=="03fd", ATTR{idProduct}=="000d", MODE="0666"
+SUBSYSTEM=="usb", ATTR{idVendor}=="03fd", ATTR{idProduct}=="000f", MODE="0666"
+SUBSYSTEM=="usb", ATTR{idVendor}=="03fd", ATTR{idProduct}=="0013", MODE="0666"
+SUBSYSTEM=="usb", ATTR{idVendor}=="03fd", ATTR{idProduct}=="0015", MODE="0666"
+
+# Xilinx JTAG cables
+SUBSYSTEM=="usb", ATTR{idVendor}=="03fd", ATTR{idProduct}=="0017", MODE="0666"
+SUBSYSTEM=="usb", ATTR{idVendor}=="03fd", ATTR{idProduct}=="001b", MODE="0666"
+
+# Digilent cables (sometimes used with Xilinx)
+SUBSYSTEM=="usb", ATTR{idVendor}=="1443", ATTR{idProduct}=="0007", MODE="0666"
+
+# Generic FTDI devices (backup for unknown FTDI variants)
+SUBSYSTEM=="usb", ATTR{idVendor}=="0403", MODE="0666" \ No newline at end of file
diff --git a/build_and_program.py b/build_and_program.py
new file mode 100644
index 0000000..ba6c139
--- /dev/null
+++ b/build_and_program.py
@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+
+import os
+import sys
+
+# Add Vivado to PATH
+vivado_bin = os.path.expanduser("~/Xilinx/2025.1/Vivado/bin")
+os.environ["PATH"] = vivado_bin + ":" + os.environ.get("PATH", "")
+
+# Now run the original blinky script
+from blinky import Blinky
+from platform_alchitry_pt import AlchitryPtPlatform
+
+if __name__ == "__main__":
+ platform = AlchitryPtPlatform()
+ platform.build(Blinky(), do_program=True) \ No newline at end of file
diff --git a/list_targets.tcl b/list_targets.tcl
new file mode 100644
index 0000000..5cbbc4c
--- /dev/null
+++ b/list_targets.tcl
@@ -0,0 +1,8 @@
+open_hw_manager
+connect_hw_server
+puts "Available targets:"
+foreach target [get_hw_targets] {
+ puts "Target: $target"
+}
+close_hw_manager
+exit \ No newline at end of file
diff --git a/platform_alchitry_pt.py b/platform_alchitry_pt.py
index 8a2c895..0b9d814 100644
--- a/platform_alchitry_pt.py
+++ b/platform_alchitry_pt.py
@@ -74,6 +74,8 @@ class AlchitryPtPlatform(XilinxPlatform):
import subprocess
import os
+ vivado_path = os.path.expanduser("~/Xilinx/2025.1/Vivado/bin/vivado")
+
with products.extract("{}.bit".format(name)) as bitstream_filename:
# Create TCL script for programming
tcl_content = f"""
@@ -88,10 +90,11 @@ program_hw_devices [get_hw_devices xc7a100t_0]
close_hw_manager
exit
"""
- tcl_script = os.path.join("build", "program_fpga.tcl")
- with open(tcl_script, "w") as f:
+ tcl_script = "program_fpga.tcl"
+ tcl_full_path = os.path.join("build", tcl_script)
+ with open(tcl_full_path, "w") as f:
f.write(tcl_content)
# Run vivado to program the FPGA
- subprocess.run(["vivado", "-mode", "batch", "-source", tcl_script],
+ subprocess.run([vivado_path, "-mode", "batch", "-source", tcl_script],
cwd="build", check=True) \ No newline at end of file
diff --git a/test_connection.tcl b/test_connection.tcl
new file mode 100644
index 0000000..f2858c0
--- /dev/null
+++ b/test_connection.tcl
@@ -0,0 +1,7 @@
+open_hw_manager
+connect_hw_server
+open_hw_target
+get_hw_targets
+get_hw_devices
+close_hw_manager
+exit \ No newline at end of file