/*
 * Copyright (C) 2013 Spreadtrum Communications Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 *************************************************
 * Automatically generated C header: do not edit *
 *************************************************
 */

#define REG_0X20E0(_o_) SCI_ADDR(SPRD_AHB_BASE, (_o_))
#define REG_0X2150(_o_) SCI_ADDR(SPRD_APBCKG_BASE, (_o_))
#define REG_0X402E(_o_) SCI_ADDR(SPRD_AONAPB_BASE, (_o_))
#define REG_0X402D(_o_) SCI_ADDR(SPRD_AONCKG_BASE, (_o_))
#define REG_0X6010(_o_) SCI_ADDR(SPRD_GPUAPB_BASE, (_o_))
#define REG_0X60D0(_o_) SCI_ADDR(SPRD_MMAHB_BASE, (_o_))
#define REG_0X60E0(_o_) SCI_ADDR(SPRD_MMCKG_BASE, (_o_))
#define REG_0X7130(_o_) SCI_ADDR(SPRD_APBREG_BASE, (_o_))

#define REG_0X402E0044 REG_0X402E(0x0044)
#define REG_0X402E004C REG_0X402E(0x004C)
#define REG_0X402E005C REG_0X402E(0x005C)
#define REG_0X402E0054 REG_0X402E(0x0054)
#define REG_0X402E0064 REG_0X402E(0x0064)
#define REG_0X20E00038 REG_0X20E0(0x0038)
#define REG_0X20E00054 REG_0X20E0(0x0054)
#define REG_0X402D0020 REG_0X402D(0x0020)
#define REG_0X402D002C REG_0X402D(0x002C)
#define REG_0X402D0030 REG_0X402D(0x0030)
#define REG_0X402E0000 REG_0X402E(0x0000)
#define REG_0X402D0034 REG_0X402D(0x0034)
#define REG_0X402E0004 REG_0X402E(0x0004)
#define REG_0X402D0038 REG_0X402D(0x0038)
#define REG_0X402D003C REG_0X402D(0x003C)
#define REG_0X402D0040 REG_0X402D(0x0040)
#define REG_0X402D0044 REG_0X402D(0x0044)
#define REG_0X402D0048 REG_0X402D(0x0048)
#define REG_0X402D004C REG_0X402D(0x004C)
#define REG_0X402D0050 REG_0X402D(0x0050)
#define REG_0X402D0054 REG_0X402D(0x0054)
#define REG_0X402D0058 REG_0X402D(0x0058)
#define REG_0X402D0068 REG_0X402D(0x0068)
#define REG_0X402D006C REG_0X402D(0x006C)
#define REG_0X402D0070 REG_0X402D(0x0070)
#define REG_0X402D0074 REG_0X402D(0x0074)
#define REG_0X402D0078 REG_0X402D(0x0078)
#define REG_0X402D007C REG_0X402D(0x007C)
#define REG_0X402D0080 REG_0X402D(0x0080)
#define REG_0X402D0090 REG_0X402D(0x0090)
#define REG_0X402D0098 REG_0X402D(0x0098)
#define REG_0X402D00C8 REG_0X402D(0x00C8)
#define REG_0X402D00CC REG_0X402D(0x00CC)
#define REG_0X402D00D0 REG_0X402D(0x00D0)
#define REG_0X21500020 REG_0X2150(0x0020)
#define REG_0X21500024 REG_0X2150(0x0024)
#define REG_0X20E00000 REG_0X20E0(0x0000)
#define REG_0X21500028 REG_0X2150(0x0028)
#define REG_0X2150002C REG_0X2150(0x002C)
#define REG_0X21500030 REG_0X2150(0x0030)
#define REG_0X21500034 REG_0X2150(0x0034)
#define REG_0X21500054 REG_0X2150(0x0054)
#define REG_0X21500058 REG_0X2150(0x0058)
#define REG_0X2150005C REG_0X2150(0x005C)
#define REG_0X21500060 REG_0X2150(0x0060)
#define REG_0X21500068 REG_0X2150(0x0068)
#define REG_0X21500070 REG_0X2150(0x0070)
#define REG_0X21500074 REG_0X2150(0x0074)
#define REG_0X2150007C REG_0X2150(0x007C)
#define REG_0X71300000 REG_0X7130(0x0000)
#define REG_0X21500084 REG_0X2150(0x0084)
#define REG_0X21500088 REG_0X2150(0x0088)
#define REG_0X2150008C REG_0X2150(0x008C)
#define REG_0X21500090 REG_0X2150(0x0090)
#define REG_0X21500094 REG_0X2150(0x0094)
#define REG_0X21500098 REG_0X2150(0x0098)
#define REG_0X2150009C REG_0X2150(0x009C)
#define REG_0X215000A0 REG_0X2150(0x00A0)
#define REG_0X215000A4 REG_0X2150(0x00A4)
#define REG_0X215000A8 REG_0X2150(0x00A8)
#define REG_0X215000AC REG_0X2150(0x00AC)
#define REG_0X215000B0 REG_0X2150(0x00B0)
#define REG_0X215000B4 REG_0X2150(0x00B4)
#define REG_0X215000B8 REG_0X2150(0x00B8)
#define REG_0X215000BC REG_0X2150(0x00BC)
#define REG_0X215000C0 REG_0X2150(0x00C0)
#define REG_0X215000C4 REG_0X2150(0x00C4)
#define REG_0X215000C8 REG_0X2150(0x00C8)
#define REG_0X215000CC REG_0X2150(0x00CC)
#define REG_0X60100020 REG_0X6010(0x0020)
#define REG_0X60E00020 REG_0X60E0(0x0020)
#define REG_0X60D00008 REG_0X60D0(0x0008)
#define REG_0X60D00000 REG_0X60D0(0x0000)
#define REG_0X60E00038 REG_0X60E0(0x0038)
#define REG_0X60E00030 REG_0X60E0(0x0030)
#define REG_0X60E00034 REG_0X60E0(0x0034)
#define REG_0X60E00028 REG_0X60E0(0x0028)
#define REG_0X60E00024 REG_0X60E0(0x0024)
#define REG_0X60E0002C REG_0X60E0(0x002C)

/*
 * Clock (0)Name, Clock (1)fixed rate, Clock Enable (2)Ctrl and (3)Bit,
 * Clock Divisor (4)Ctrl and (5)Bit, Clock Parent (6)Ctrl and (7)Bit,
 * and Parent Select (15)Count and (16)Lists[ ... ...]
 */

SCI_CLK_ADD(ext_26m, 26000000, 0, 0,
	0, 0, 0, 0, 0);

SCI_CLK_ADD(ext_32k, 32768, 0, 0,
	0, 0, 0, 0, 0);

SCI_CLK_ADD(ext_26m_rf1, 26000000, 0, 0,
	0, 0, 0, 0, 0);

SCI_CLK_ADD(ext_1m, 1000000, 0, 0,
	0, 0, 0, 0, 0);

SCI_CLK_ADD(ext_2m, 2000000, 0, 0,
	0, 0, 0, 0, 0);

SCI_CLK_ADD(ext_4m, 4000000, 0, 0,
	0, 0, 0, 0, 0);

SCI_CLK_ADD(clk_pad, 64000000, 0, 0,
	0, 0, 0, 0, 0);

SCI_CLK_ADD(clk_mpll, 0, 0, 0,
	REG_0X402E0044, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, 0);

SCI_CLK_ADD(clk_dpll, 0, 0, 0,
	REG_0X402E004C, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, 0);

SCI_CLK_ADD(clk_ltepll, 0, 0, 0,
	REG_0X402E005C, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, 0);

SCI_CLK_ADD(clk_twpll, 0, 0, 0,
	REG_0X402E0054, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, 0);

SCI_CLK_ADD(clk_lvdspll, 0, 0, 0,
	REG_0X402E0064, BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10), 0, 0, 0);

SCI_CLK_ADD(clk_768m, 0, 0, 0,
	2, 0, 0, 0,
	1, &clk_twpll);

SCI_CLK_ADD(clk_512m, 0, 0, 0,
	3, 0, 0, 0,
	1, &clk_twpll);

SCI_CLK_ADD(clk_384m, 0, 0, 0,
	4, 0, 0, 0,
	1, &clk_twpll);

SCI_CLK_ADD(clk_312m, 0, 0, 0,
	5, 0, 0, 0,
	1, &clk_twpll);

SCI_CLK_ADD(clk_307m2, 0, 0, 0,
	5, 0, 0, 0,
	1, &clk_twpll);

SCI_CLK_ADD(clk_256m, 0, 0, 0,
	6, 0, 0, 0,
	1, &clk_twpll);

SCI_CLK_ADD(clk_192m, 0, 0, 0,
	8, 0, 0, 0,
	1, &clk_twpll);

SCI_CLK_ADD(clk_153m6, 0, 0, 0,
	10, 0, 0, 0,
	1, &clk_twpll);

SCI_CLK_ADD(clk_128m, 0, 0, 0,
	12, 0, 0, 0,
	1, &clk_twpll);

SCI_CLK_ADD(clk_96m, 0, 0, 0,
	16, 0, 0, 0,
	1, &clk_twpll);

SCI_CLK_ADD(clk_76m8, 0, 0, 0,
	20, 0, 0, 0,
	1, &clk_twpll);

SCI_CLK_ADD(clk_64m, 0, 0, 0,
	24, 0, 0, 0,
	1, &clk_twpll);

SCI_CLK_ADD(clk_51m2, 0, 0, 0,
	30, 0, 0, 0,
	1, &clk_twpll);

SCI_CLK_ADD(clk_48m, 0, 0, 0,
	32, 0, 0, 0,
	1, &clk_twpll);

SCI_CLK_ADD(clk_38m4, 0, 0, 0,
	40, 0, 0, 0,
	1, &clk_twpll);

SCI_CLK_ADD(clk_24m, 0, 0, 0,
	64, 0, 0, 0,
	1, &clk_twpll);

SCI_CLK_ADD(clk_12m, 0, 0, 0,
	128, 0, 0, 0,
	1, &clk_twpll);

SCI_CLK_ADD(clk_42m_d, 0, 0, 0,
	32, 0, 0, 0,
	1, &clk_dpll);

SCI_CLK_ADD(clk_56m_m, 0, 0, 0,
	32, 0, 0, 0,
	1, &clk_mpll);

SCI_CLK_ADD(clk_38m4_lte, 0, 0, 0,
	32, 0, 0, 0,
	1, &clk_ltepll);

SCI_CLK_ADD(clk_44m_lvds, 0, 0, 0,
	32, 0, 0, 0,
	1, &clk_lvdspll);

SCI_CLK_ADD(clk_614m4, 0, 0, 0,
	2, 0, 0, 0,
	1, &clk_ltepll);

SCI_CLK_ADD(clk_mcu, 0, 0, 0,
	REG_0X20E00038, BIT(4)|BIT(5)|BIT(6), REG_0X20E00054, BIT(0)|BIT(1)|BIT(2),
	7, &ext_26m, &clk_512m, &clk_768m, &clk_dpll, &clk_ltepll, &clk_twpll, &clk_mpll);

SCI_CLK_ADD(clk_ca7_core, 0, 0, 0,
	0, 0, 0, 0,
	1, &clk_mcu);

SCI_CLK_ADD(clk_ca7_axi, 0, 0, 0,
	REG_0X20E00038, BIT(8)|BIT(9)|BIT(10), 0, 0,
	1, &clk_mcu);

SCI_CLK_ADD(clk_ca7_dbg, 0, 0, 0,
	REG_0X20E00038, BIT(16)|BIT(17)|BIT(18), 0, 0,
	1, &clk_mcu);

SCI_CLK_ADD(clk_emc_4x, 0, 0, 0,
	REG_0X402D0020, BIT(8)|BIT(9), REG_0X402D0020, BIT(0)|BIT(1)|BIT(2),
	8, &ext_26m, &clk_192m, &clk_307m2, &clk_384m, &clk_512m, &clk_614m4, &clk_768m, &clk_dpll);

SCI_CLK_ADD(clk_pub_ahb, 0, 0, 0,
	REG_0X402D002C, BIT(8)|BIT(9), REG_0X402D002C, BIT(0)|BIT(1),
	4, &ext_26m, &ext_4m, &clk_96m, &clk_128m);

SCI_CLK_ADD(clk_aon_apb, 0, 0, 0,
	REG_0X402D0030, BIT(8)|BIT(9), REG_0X402D0030, BIT(0)|BIT(1),
	4, &ext_4m, &ext_26m, &clk_96m, &clk_128m);

SCI_CLK_ADD(clk_adi, 0, REG_0X402E0000, BIT(16),
	0, 0, REG_0X402D0034, BIT(0)|BIT(1),
	4, &ext_26m, &ext_4m, &clk_38m4, &clk_51m2);

SCI_CLK_ADD(clk_aux0, 0, REG_0X402E0004, BIT(2),
	0, 0, REG_0X402D0038, BIT(0)|BIT(1)|BIT(2),
	7, &ext_32k, &ext_26m, &ext_26m_rf1, &ext_4m, &clk_42m_d, &clk_48m, &clk_56m_m);

SCI_CLK_ADD(clk_aux1, 0, REG_0X402E0004, BIT(3),
	0, 0, REG_0X402D003C, BIT(0)|BIT(1)|BIT(2)|BIT(3),
	9, &ext_32k, &ext_26m, &ext_26m_rf1, &ext_4m, &clk_42m_d, &clk_48m, &clk_56m_m, &clk_38m4_lte, &clk_44m_lvds);

SCI_CLK_ADD(clk_aux2, 0, REG_0X402E0004, BIT(4),
	0, 0, REG_0X402D0040, BIT(0)|BIT(1)|BIT(2)|BIT(3),
	9, &ext_32k, &ext_26m, &ext_26m_rf1, &ext_4m, &clk_42m_d, &clk_48m, &clk_56m_m, &clk_38m4_lte, &clk_44m_lvds);

SCI_CLK_ADD(clk_probe, 0, REG_0X402E0004, BIT(5),
	0, 0, REG_0X402D0044, BIT(0)|BIT(1)|BIT(2)|BIT(3),
	9, &ext_32k, &ext_26m, &ext_26m_rf1, &ext_4m, &clk_42m_d, &clk_48m, &clk_56m_m, &clk_38m4_lte, &clk_44m_lvds);

SCI_CLK_ADD(clk_pwm0, 0, REG_0X402E0000, BIT(4),
	0, 0, REG_0X402D0048, BIT(0)|BIT(1),
	4, &ext_32k, &ext_26m, &ext_26m_rf1, &clk_48m);

SCI_CLK_ADD(clk_pwm1, 0, REG_0X402E0000, BIT(5),
	0, 0, REG_0X402D004C, BIT(0)|BIT(1),
	4, &ext_32k, &ext_26m, &ext_26m_rf1, &clk_48m);

SCI_CLK_ADD(clk_pwm2, 0, REG_0X402E0000, BIT(6),
	0, 0, REG_0X402D0050, BIT(0)|BIT(1),
	4, &ext_32k, &ext_26m, &ext_26m_rf1, &clk_48m);

SCI_CLK_ADD(clk_pwm3, 0, REG_0X402E0000, BIT(7),
	0, 0, REG_0X402D0054, BIT(0)|BIT(1),
	4, &ext_32k, &ext_26m, &ext_26m_rf1, &clk_48m);

SCI_CLK_ADD(clk_efuse, 0, REG_0X402E0000, BIT(13),
	0, 0, REG_0X402D0058, BIT(0),
	1, &ext_26m);

SCI_CLK_ADD(clk_thm, 0, REG_0X402E0004, BIT(1),
	0, 0, REG_0X402D0068, BIT(0),
	2, &ext_32k, &ext_1m);

SCI_CLK_ADD(clk_mspi, 0, REG_0X402E0000, BIT(23),
	0, 0, REG_0X402D006C, BIT(0),
	4, &ext_26m, &clk_51m2, &clk_76m8, &clk_96m);

SCI_CLK_ADD(clk_i2c, 0, REG_0X402E0000, BIT(31),
	0, 0, REG_0X402D0070, BIT(0)|BIT(1),
	4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6);

SCI_CLK_ADD(clk_avs, 0, REG_0X402E0004, BIT(6),
	0, 0, REG_0X402D0074, BIT(0)|BIT(1),
	4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m);

SCI_CLK_ADD(clk_aud, 0, REG_0X402E0000, BIT(18),
	0, 0, REG_0X402D0078, BIT(0),
	1, &ext_26m);

SCI_CLK_ADD(clk_audif, 0, REG_0X402E0000, BIT(17),
	0, 0, REG_0X402D007C, BIT(0)|BIT(1),
	3, &ext_26m, &clk_38m4, &clk_51m2);

SCI_CLK_ADD(clk_vbc, 0, REG_0X402E0000, BIT(19),
	0, 0, REG_0X402D0080, BIT(0),
	1, &ext_26m);

SCI_CLK_ADD(clk_ca7_dap, 0, REG_0X402E0000, BIT(30),
	0, 0, REG_0X402D0090, BIT(0)|BIT(1),
	4, &ext_26m, &clk_76m8, &clk_128m, &clk_153m6);

SCI_CLK_ADD(clk_ca7_ts, 0, REG_0X402E0000, BIT(28),
	0, 0, REG_0X402D0098, BIT(0)|BIT(1),
	4, &ext_32k, &ext_26m, &clk_128m, &clk_153m6);

SCI_CLK_ADD(clk_djtag_tck, 0, 0, 0,
	0, 0, REG_0X402D00C8, BIT(0),
	3, &ext_26m, &ext_4m, &clk_pad);

SCI_CLK_ADD(clk_arm7_ahb, 0, 0, 0,
	REG_0X402D00CC, BIT(8)|BIT(9), REG_0X402D00CC, BIT(0)|BIT(1),
	4, &ext_4m, &ext_26m, &clk_96m, &clk_128m);

SCI_CLK_ADD(clk_ca5_ts, 0, REG_0X402E0004, BIT(26),
	0, 0, REG_0X402D00D0, BIT(0)|BIT(1),
	4, &ext_32k, &ext_26m, &clk_128m, &clk_153m6);

SCI_CLK_ADD(clk_disp_emc, 0, REG_0X402E0004, BIT(11),
	0, 0, 0, 0,
	1, &clk_aon_apb);

SCI_CLK_ADD(clk_gsp_emc, 0, REG_0X402E0004, BIT(13),
	0, 0, 0, 0,
	1, &clk_aon_apb);

SCI_CLK_ADD(clk_ap_ahb, 0, 0, 0,
	0, 0, REG_0X21500020, BIT(0)|BIT(1),
	4, &ext_26m, &clk_76m8, &clk_128m, &clk_192m);

SCI_CLK_ADD(clk_ap_apb, 0, 0, 0,
	0, 0, REG_0X21500024, BIT(0)|BIT(1),
	4, &ext_26m, &clk_64m, &clk_96m, &clk_128m);

SCI_CLK_ADD(clk_gsp, 0, REG_0X20E00000, BIT(3),
	0, 0, REG_0X21500028, BIT(0)|BIT(1),
	4, &clk_96m, &clk_153m6, &clk_192m, &clk_256m);

SCI_CLK_ADD(clk_dispc0, 0, REG_0X20E00000, BIT(1),
	REG_0X2150002C, BIT(8)|BIT(9)|BIT(10), REG_0X2150002C, BIT(0)|BIT(1),
	4, &clk_153m6, &clk_192m, &clk_256m, &clk_307m2);

SCI_CLK_ADD(clk_dispc0_dbi, 0, 0, 0,
	REG_0X21500030, BIT(8)|BIT(9)|BIT(10), REG_0X21500030, BIT(0)|BIT(1),
	4, &clk_128m, &clk_153m6, &clk_192m, &clk_256m);

SCI_CLK_ADD(clk_dispc0_dpi, 0, 0, 0,
	REG_0X21500034, BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15), REG_0X21500034, BIT(0)|BIT(1),
	5, &clk_128m, &clk_153m6, &clk_192m, &clk_384m, &clk_pad);

SCI_CLK_ADD(clk_nandc_2x, 0, REG_0X20E00000, BIT(18),
	0, 0, REG_0X21500054, BIT(0)|BIT(1),
	4, &clk_192m, &clk_256m, &clk_307m2, &clk_384m);

SCI_CLK_ADD(clk_nandc_ecc, 0, REG_0X20E00000, BIT(19),
	0, 0, REG_0X21500058, BIT(0),
	2, &clk_153m6, &clk_192m);

SCI_CLK_ADD(clk_sdio0, 0, REG_0X20E00000, BIT(8),
	REG_0X2150005C, BIT(8)|BIT(9)|BIT(10), REG_0X2150005C, BIT(0)|BIT(1),
	4, &ext_26m, &clk_256m, &clk_307m2, &clk_384m);

SCI_CLK_ADD(clk_sdio1, 0, REG_0X20E00000, BIT(9),
	0, 0, REG_0X21500060, BIT(0)|BIT(1),
	4, &clk_48m, &clk_76m8, &clk_96m, &clk_128m);

SCI_CLK_ADD(clk_sdio2, 0, REG_0X20E00000, BIT(10),
	0, 0, REG_0X21500068, BIT(0)|BIT(1),
	4, &clk_48m, &clk_76m8, &clk_96m, &clk_128m);

SCI_CLK_ADD(clk_emmc, 0, REG_0X20E00000, BIT(11),
	0, 0, REG_0X21500070, BIT(0)|BIT(1),
	4, &ext_26m, &clk_256m, &clk_307m2, &clk_384m);

SCI_CLK_ADD(clk_otg_ref, 0, REG_0X20E00000, BIT(4),
	0, 0, REG_0X21500074, BIT(0),
	2, &clk_12m, &clk_24m);

SCI_CLK_ADD(clk_hsic_ref, 0, REG_0X20E00000, BIT(2),
	0, 0, REG_0X2150007C, BIT(0),
	2, &clk_12m, &clk_24m);

SCI_CLK_ADD(clk_uart0, 0, REG_0X71300000, BIT(13),
	REG_0X21500084, BIT(8)|BIT(9)|BIT(10), REG_0X21500084, BIT(0)|BIT(1),
	4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m);

SCI_CLK_ADD(clk_uart1, 0, REG_0X71300000, BIT(14),
	REG_0X21500088, BIT(8)|BIT(9)|BIT(10), REG_0X21500088, BIT(0)|BIT(1),
	4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m);

SCI_CLK_ADD(clk_uart2, 0, REG_0X71300000, BIT(15),
	REG_0X2150008C, BIT(8)|BIT(9)|BIT(10), REG_0X2150008C, BIT(0)|BIT(1),
	4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m);

SCI_CLK_ADD(clk_uart3, 0, REG_0X71300000, BIT(16),
	REG_0X21500090, BIT(8)|BIT(9)|BIT(10), REG_0X21500090, BIT(0)|BIT(1),
	4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m);

SCI_CLK_ADD(clk_uart4, 0, REG_0X71300000, BIT(17),
	REG_0X21500094, BIT(8)|BIT(9)|BIT(10), REG_0X21500094, BIT(0)|BIT(1),
	4, &ext_26m, &clk_48m, &clk_51m2, &clk_96m);

SCI_CLK_ADD(clk_i2c0, 0, REG_0X71300000, BIT(8),
	REG_0X21500098, BIT(8)|BIT(9)|BIT(10), REG_0X21500098, BIT(0)|BIT(1),
	4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6);

SCI_CLK_ADD(clk_i2c1, 0, REG_0X71300000, BIT(9),
	REG_0X2150009C, BIT(8)|BIT(9)|BIT(10), REG_0X2150009C, BIT(0)|BIT(1),
	4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6);

SCI_CLK_ADD(clk_i2c2, 0, REG_0X71300000, BIT(10),
	REG_0X215000A0, BIT(8)|BIT(9)|BIT(10), REG_0X215000A0, BIT(0)|BIT(1),
	4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6);

SCI_CLK_ADD(clk_i2c3, 0, REG_0X71300000, BIT(11),
	REG_0X215000A4, BIT(8)|BIT(9)|BIT(10), REG_0X215000A4, BIT(0)|BIT(1),
	4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6);

SCI_CLK_ADD(clk_i2c4, 0, REG_0X71300000, BIT(12),
	REG_0X215000A8, BIT(8)|BIT(9)|BIT(10), REG_0X215000A8, BIT(0)|BIT(1),
	4, &ext_26m, &clk_48m, &clk_51m2, &clk_153m6);

SCI_CLK_ADD(clk_spi0, 0, REG_0X71300000, BIT(5),
	REG_0X215000AC, BIT(8)|BIT(9)|BIT(10), REG_0X215000AC, BIT(0)|BIT(1),
	5, &ext_26m, &clk_96m, &clk_153m6, &clk_192m, &clk_pad);

SCI_CLK_ADD(clk_spi1, 0, REG_0X71300000, BIT(6),
	REG_0X215000B0, BIT(8)|BIT(9)|BIT(10), REG_0X215000B0, BIT(0)|BIT(1),
	5, &ext_26m, &clk_96m, &clk_153m6, &clk_192m, &clk_pad);

SCI_CLK_ADD(clk_spi2, 0, REG_0X71300000, BIT(7),
	REG_0X215000B4, BIT(8)|BIT(9)|BIT(10), REG_0X215000B4, BIT(0)|BIT(1),
	5, &ext_26m, &clk_96m, &clk_153m6, &clk_192m, &clk_pad);

SCI_CLK_ADD(clk_iis0, 0, REG_0X71300000, BIT(1),
	REG_0X215000B8, BIT(8)|BIT(9)|BIT(10), REG_0X215000B8, BIT(0)|BIT(1),
	4, &ext_26m, &clk_128m, &clk_153m6, &clk_pad);

SCI_CLK_ADD(clk_iis1, 0, REG_0X71300000, BIT(2),
	REG_0X215000BC, BIT(8)|BIT(9)|BIT(10), REG_0X215000BC, BIT(0)|BIT(1),
	4, &ext_26m, &clk_128m, &clk_153m6, &clk_pad);

SCI_CLK_ADD(clk_iis2, 0, REG_0X71300000, BIT(3),
	REG_0X215000C0, BIT(8)|BIT(9)|BIT(10), REG_0X215000C0, BIT(0)|BIT(1),
	4, &ext_26m, &clk_128m, &clk_153m6, &clk_pad);

SCI_CLK_ADD(clk_iis3, 0, REG_0X71300000, BIT(4),
	REG_0X215000C4, BIT(8)|BIT(9)|BIT(10), REG_0X215000C4, BIT(0)|BIT(1),
	4, &ext_26m, &clk_128m, &clk_153m6, &clk_pad);

SCI_CLK_ADD(clk_zipenc, 0, REG_0X20E00000, BIT(20),
	0, 0, REG_0X215000C8, BIT(0)|BIT(1),
	4, &clk_96m, &clk_153m6, &clk_192m, &clk_256m);

SCI_CLK_ADD(clk_zipdec, 0, REG_0X20E00000, BIT(21),
	0, 0, REG_0X215000CC, BIT(0)|BIT(1),
	4, &clk_96m, &clk_153m6, &clk_192m, &clk_256m);

SCI_CLK_ADD(clk_gpu_i, 0, REG_0X402E0000, BIT(27),
	0, 0, 0, 0,
	1, &clk_aon_apb);

SCI_CLK_ADD(clk_gpu, 0, REG_0X402E0000, BIT(27),
	REG_0X60100020, BIT(8)|BIT(9), REG_0X60100020, BIT(0)|BIT(1)|BIT(2),
	6, &clk_153m6, &clk_192m, &clk_256m, &clk_307m2, &clk_384m, &clk_512m);

SCI_CLK_ADD(clk_mm_i, 0, REG_0X402E0000, BIT(25),
	0, 0, 0, 0,
	1, &clk_aon_apb);

SCI_CLK_ADD(clk_mm_ahb, 0, 0, 0,
	0, 0, REG_0X60E00020, BIT(0)|BIT(1),
	4, &ext_26m, &clk_96m, &clk_128m, &clk_153m6);

SCI_CLK_ADD(clk_mm_axi, 0, REG_0X60D00008, BIT(7),
	0, 0, 0, 0,
	1, &clk_mm_i);

SCI_CLK_ADD(clk_mm_mtx_axi, 0, REG_0X60D00008, BIT(8),
	0, 0, 0, 0,
	1, &clk_mm_axi);

SCI_CLK_ADD(clk_mmu, 0, REG_0X60D00000, BIT(7),
	0, 0, 0, 0,
	1, &clk_mm_ahb);

SCI_CLK_ADD(clk_mm_ckg, 0, REG_0X60D00000, BIT(6),
	0, 0, 0, 0,
	1, &clk_mm_ahb);

SCI_CLK_ADD(clk_jpg, 0, REG_0X60D00008, BIT(6),
	0, 0, REG_0X60E00038, BIT(0)|BIT(1),
	4, &clk_76m8, &clk_128m, &clk_256m, &clk_312m);

SCI_CLK_ADD(clk_csi, 0, REG_0X60D00008, BIT(1),
	0, 0, 0, 0,
	1, &clk_mm_ahb);

SCI_CLK_ADD(clk_dcam_mipi, 0, REG_0X60D00008, BIT(0),
	0, 0, 0, 0,
	1, &clk_csi);

SCI_CLK_ADD(clk_vsp, 0, REG_0X60D00008, BIT(5),
	0, 0, REG_0X60E00030, BIT(0)|BIT(1),
	4, &clk_76m8, &clk_128m, &clk_256m, &clk_312m);

SCI_CLK_ADD(clk_isp, 0, REG_0X60D00008, BIT(4),
	0, 0, REG_0X60E00034, BIT(0)|BIT(1),
	4, &clk_76m8, &clk_128m, &clk_256m, &clk_312m);

SCI_CLK_ADD(clk_ccir, 0, REG_0X60D00000, BIT(1),
	0, 0, REG_0X60E00028, BIT(16),
	2, &clk_24m, &clk_pad);

SCI_CLK_ADD(clk_sensor, 0, REG_0X60D00008, BIT(2),
	REG_0X60E00024, BIT(8)|BIT(9)|BIT(10), REG_0X60E00024, BIT(0)|BIT(1),
	4, &ext_26m, &clk_48m, &clk_76m8, &clk_96m);

SCI_CLK_ADD(clk_dcam, 0, REG_0X60D00008, BIT(3),
	0, 0, REG_0X60E0002C, BIT(0)|BIT(1),
	4, &clk_76m8, &clk_128m, &clk_256m, &clk_312m);