/* * @file mipi_dsih_hal.h * * Synopsys Inc. * SG DWC PT02 */ /* The Synopsys Software Driver and documentation (hereinafter "Software") is an unsupported work of Synopsys, Inc. unless otherwise expressly agreed to in writing between Synopsys and you. The Software IS NOT an item of Licensed Software or Licensed Product under any End User Software License Agreement or Agreement for Licensed Product with Synopsys or any supplement thereto. Permission is hereby granted, free of charge, to any person obtaining a copy of this software annotated with this license and the Software, to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef MIPI_DSIH_HAL_H_ #define MIPI_DSIH_HAL_H_ #include "mipi_dsih_local.h" #define R_DSI_HOST_VERSION 0x00UL #define R_DSI_HOST_PWR_UP 0x04UL #define R_DSI_HOST_CLK_MGR 0x08UL #define R_DSI_HOST_DPI_CFG 0x0CUL #define R_DSI_HOST_DBI_CFG 0x10UL #define R_DSI_HOST_DBI_CMDSIZE 0x14UL #define R_DSI_HOST_PCKHDL_CFG 0x18UL #define R_DSI_HOST_VID_MODE_CFG 0x1CUL #define R_DSI_HOST_VID_PKT_CFG 0x20UL #define R_DSI_HOST_CMD_MODE_CFG 0x24UL #define R_DSI_HOST_TMR_LINE_CFG 0x28UL #define R_DSI_HOST_VTIMING_CFG 0x2CUL #define R_DSI_HOST_PHY_TMR_CFG 0x30UL #define R_DSI_HOST_GEN_HDR 0x34UL #define R_DSI_HOST_GEN_PLD_DATA 0x38UL #define R_DSI_HOST_CMD_PKT_STATUS 0x3CUL #define R_DSI_HOST_TO_CNT_CFG 0x40UL #define R_DSI_HOST_ERROR_ST0 0x44UL #define R_DSI_HOST_ERROR_ST1 0x48UL #define R_DSI_HOST_ERROR_MSK0 0x4CUL #define R_DSI_HOST_ERROR_MSK1 0x50UL #ifdef CONFIG_OF extern uint32_t g_dsi_base_addr; #endif typedef enum _Dsi_Int0_Type_ { ack_with_err_0, ack_with_err_1, ack_with_err_2, ack_with_err_3, ack_with_err_4, ack_with_err_5, ack_with_err_6, ack_with_err_7, ack_with_err_8, ack_with_err_9, ack_with_err_10, ack_with_err_11, ack_with_err_12, ack_with_err_13, ack_with_err_14, ack_with_err_15, dphy_errors_0, dphy_errors_1, dphy_errors_2, dphy_errors_3, dphy_errors_4, DSI_INT0_MAX, }Dsi_Int0_Type; typedef enum _Dsi_Int1_Type_ { to_hs_tx, to_lp_rx, ecc_single_err, ecc_multi_err, crc_err, pkt_size_err, eopt_err, dpi_pld_wr_err, gen_cmd_wr_err, gen_pld_wr_err, gen_pld_send_err, gen_pld_rd_err, gen_pld_recv_err, dbi_cmd_wr_err, dbi_pld_wr_err, dbi_pld_rd_err, dbi_pld_recv_err, dbi_illegal_comm_err, DSI_INT1_MAX, }Dsi_Int1_Type; #define DSI_INT_MASK0_SET(bit,val)\ {\ uint32_t reg_val = dsi_core_read_function(SPRD_MIPI_DSIC_BASE, R_DSI_HOST_ERROR_MSK0);\ reg_val = (val == 1)?(reg_val | (1UL<