From 8e4bff4cab0ddac6060645b0715210484d02ff40 Mon Sep 17 00:00:00 2001 From: Yuval Adam <_@yuv.al> Date: Wed, 30 Aug 2017 08:25:59 +0000 Subject: Initial file dump from open source release --- arch/sh/Kconfig | 935 +++++++++ arch/sh/Kconfig.cpu | 108 ++ arch/sh/Kconfig.debug | 91 + arch/sh/Makefile | 241 +++ arch/sh/boards/Kconfig | 382 ++++ arch/sh/boards/Makefile | 17 + arch/sh/boards/board-apsh4a3a.c | 185 ++ arch/sh/boards/board-apsh4ad0a.c | 135 ++ arch/sh/boards/board-edosk7705.c | 78 + arch/sh/boards/board-edosk7760.c | 191 ++ arch/sh/boards/board-espt.c | 110 ++ arch/sh/boards/board-magicpanelr2.c | 393 ++++ arch/sh/boards/board-polaris.c | 155 ++ arch/sh/boards/board-secureedge5410.c | 75 + arch/sh/boards/board-sh2007.c | 145 ++ arch/sh/boards/board-sh7757lcr.c | 615 ++++++ arch/sh/boards/board-sh7785lcr.c | 378 ++++ arch/sh/boards/board-shmin.c | 34 + arch/sh/boards/board-titan.c | 24 + arch/sh/boards/board-urquell.c | 221 +++ arch/sh/boards/mach-ap325rxa/Makefile | 2 + arch/sh/boards/mach-ap325rxa/sdram.S | 69 + arch/sh/boards/mach-ap325rxa/setup.c | 695 +++++++ arch/sh/boards/mach-cayman/Makefile | 4 + arch/sh/boards/mach-cayman/irq.c | 157 ++ arch/sh/boards/mach-cayman/panic.c | 49 + arch/sh/boards/mach-cayman/setup.c | 186 ++ arch/sh/boards/mach-dreamcast/Makefile | 6 + arch/sh/boards/mach-dreamcast/irq.c | 156 ++ arch/sh/boards/mach-dreamcast/rtc.c | 81 + arch/sh/boards/mach-dreamcast/setup.c | 41 + arch/sh/boards/mach-ecovec24/Makefile | 9 + arch/sh/boards/mach-ecovec24/sdram.S | 111 ++ arch/sh/boards/mach-ecovec24/setup.c | 1520 +++++++++++++++ arch/sh/boards/mach-highlander/Kconfig | 25 + arch/sh/boards/mach-highlander/Makefile | 11 + arch/sh/boards/mach-highlander/irq-r7780mp.c | 74 + arch/sh/boards/mach-highlander/irq-r7780rp.c | 67 + arch/sh/boards/mach-highlander/irq-r7785rp.c | 86 + arch/sh/boards/mach-highlander/pinmux-r7785rp.c | 20 + arch/sh/boards/mach-highlander/psw.c | 122 ++ arch/sh/boards/mach-highlander/setup.c | 419 ++++ arch/sh/boards/mach-hp6xx/Makefile | 7 + arch/sh/boards/mach-hp6xx/hp6xx_apm.c | 111 ++ arch/sh/boards/mach-hp6xx/pm.c | 158 ++ arch/sh/boards/mach-hp6xx/pm_wakeup.S | 43 + arch/sh/boards/mach-hp6xx/setup.c | 174 ++ arch/sh/boards/mach-kfr2r09/Makefile | 4 + arch/sh/boards/mach-kfr2r09/lcd_wqvga.c | 326 ++++ arch/sh/boards/mach-kfr2r09/sdram.S | 80 + arch/sh/boards/mach-kfr2r09/setup.c | 652 +++++++ arch/sh/boards/mach-landisk/Makefile | 5 + arch/sh/boards/mach-landisk/gio.c | 170 ++ arch/sh/boards/mach-landisk/irq.c | 66 + arch/sh/boards/mach-landisk/psw.c | 143 ++ arch/sh/boards/mach-landisk/setup.c | 102 + arch/sh/boards/mach-lboxre2/Makefile | 5 + arch/sh/boards/mach-lboxre2/irq.c | 31 + arch/sh/boards/mach-lboxre2/setup.c | 83 + arch/sh/boards/mach-microdev/Makefile | 5 + arch/sh/boards/mach-microdev/fdc37c93xapm.c | 160 ++ arch/sh/boards/mach-microdev/io.c | 125 ++ arch/sh/boards/mach-microdev/irq.c | 152 ++ arch/sh/boards/mach-microdev/setup.c | 199 ++ arch/sh/boards/mach-migor/Kconfig | 15 + arch/sh/boards/mach-migor/Makefile | 2 + arch/sh/boards/mach-migor/lcd_qvga.c | 166 ++ arch/sh/boards/mach-migor/sdram.S | 69 + arch/sh/boards/mach-migor/setup.c | 674 +++++++ arch/sh/boards/mach-r2d/Kconfig | 23 + arch/sh/boards/mach-r2d/Makefile | 5 + arch/sh/boards/mach-r2d/irq.c | 155 ++ arch/sh/boards/mach-r2d/setup.c | 308 +++ arch/sh/boards/mach-rsk/Kconfig | 28 + arch/sh/boards/mach-rsk/Makefile | 4 + arch/sh/boards/mach-rsk/devices-rsk7203.c | 140 ++ arch/sh/boards/mach-rsk/devices-rsk7264.c | 58 + arch/sh/boards/mach-rsk/devices-rsk7269.c | 60 + arch/sh/boards/mach-rsk/setup.c | 90 + arch/sh/boards/mach-sdk7780/Kconfig | 16 + arch/sh/boards/mach-sdk7780/Makefile | 5 + arch/sh/boards/mach-sdk7780/irq.c | 46 + arch/sh/boards/mach-sdk7780/setup.c | 99 + arch/sh/boards/mach-sdk7786/Makefile | 4 + arch/sh/boards/mach-sdk7786/fpga.c | 72 + arch/sh/boards/mach-sdk7786/gpio.c | 49 + arch/sh/boards/mach-sdk7786/irq.c | 48 + arch/sh/boards/mach-sdk7786/nmi.c | 83 + arch/sh/boards/mach-sdk7786/setup.c | 269 +++ arch/sh/boards/mach-sdk7786/sram.c | 72 + arch/sh/boards/mach-se/7206/Makefile | 5 + arch/sh/boards/mach-se/7206/irq.c | 150 ++ arch/sh/boards/mach-se/7206/setup.c | 95 + arch/sh/boards/mach-se/7343/Makefile | 5 + arch/sh/boards/mach-se/7343/irq.c | 129 ++ arch/sh/boards/mach-se/7343/setup.c | 181 ++ arch/sh/boards/mach-se/770x/Makefile | 5 + arch/sh/boards/mach-se/770x/irq.c | 108 ++ arch/sh/boards/mach-se/770x/setup.c | 188 ++ arch/sh/boards/mach-se/7721/Makefile | 1 + arch/sh/boards/mach-se/7721/irq.c | 45 + arch/sh/boards/mach-se/7721/setup.c | 96 + arch/sh/boards/mach-se/7722/Makefile | 10 + arch/sh/boards/mach-se/7722/irq.c | 122 ++ arch/sh/boards/mach-se/7722/setup.c | 194 ++ arch/sh/boards/mach-se/7724/Makefile | 10 + arch/sh/boards/mach-se/7724/irq.c | 145 ++ arch/sh/boards/mach-se/7724/sdram.S | 131 ++ arch/sh/boards/mach-se/7724/setup.c | 947 +++++++++ arch/sh/boards/mach-se/7751/Makefile | 5 + arch/sh/boards/mach-se/7751/irq.c | 50 + arch/sh/boards/mach-se/7751/setup.c | 59 + arch/sh/boards/mach-se/7780/Makefile | 10 + arch/sh/boards/mach-se/7780/irq.c | 68 + arch/sh/boards/mach-se/7780/setup.c | 114 ++ arch/sh/boards/mach-se/Makefile | 10 + arch/sh/boards/mach-se/board-se7619.c | 26 + arch/sh/boards/mach-sh03/Makefile | 5 + arch/sh/boards/mach-sh03/rtc.c | 132 ++ arch/sh/boards/mach-sh03/setup.c | 105 + arch/sh/boards/mach-sh7763rdp/Makefile | 1 + arch/sh/boards/mach-sh7763rdp/irq.c | 45 + arch/sh/boards/mach-sh7763rdp/setup.c | 218 +++ arch/sh/boards/mach-x3proto/Makefile | 3 + arch/sh/boards/mach-x3proto/gpio.c | 141 ++ arch/sh/boards/mach-x3proto/ilsel.c | 159 ++ arch/sh/boards/mach-x3proto/setup.c | 273 +++ arch/sh/boot/.gitignore | 3 + arch/sh/boot/Makefile | 115 ++ arch/sh/boot/compressed/.gitignore | 1 + arch/sh/boot/compressed/Makefile | 81 + arch/sh/boot/compressed/cache.c | 12 + arch/sh/boot/compressed/head_32.S | 125 ++ arch/sh/boot/compressed/head_64.S | 159 ++ arch/sh/boot/compressed/install.sh | 56 + arch/sh/boot/compressed/misc.c | 138 ++ arch/sh/boot/romimage/Makefile | 30 + arch/sh/boot/romimage/head.S | 84 + arch/sh/boot/romimage/mmcif-sh7724.c | 72 + arch/sh/cchips/Kconfig | 45 + arch/sh/cchips/hd6446x/Makefile | 3 + arch/sh/cchips/hd6446x/hd64461.c | 111 ++ arch/sh/configs/ap325rxa_defconfig | 118 ++ arch/sh/configs/apsh4a3a_defconfig | 102 + arch/sh/configs/apsh4ad0a_defconfig | 131 ++ arch/sh/configs/cayman_defconfig | 71 + arch/sh/configs/dreamcast_defconfig | 78 + arch/sh/configs/ecovec24-romimage_defconfig | 67 + arch/sh/configs/ecovec24_defconfig | 149 ++ arch/sh/configs/edosk7705_defconfig | 39 + arch/sh/configs/edosk7760_defconfig | 127 ++ arch/sh/configs/espt_defconfig | 128 ++ arch/sh/configs/hp6xx_defconfig | 67 + arch/sh/configs/kfr2r09-romimage_defconfig | 59 + arch/sh/configs/kfr2r09_defconfig | 94 + arch/sh/configs/landisk_defconfig | 125 ++ arch/sh/configs/lboxre2_defconfig | 67 + arch/sh/configs/magicpanelr2_defconfig | 102 + arch/sh/configs/microdev_defconfig | 50 + arch/sh/configs/migor_defconfig | 108 ++ arch/sh/configs/polaris_defconfig | 95 + arch/sh/configs/r7780mp_defconfig | 118 ++ arch/sh/configs/r7785rp_defconfig | 115 ++ arch/sh/configs/rsk7201_defconfig | 75 + arch/sh/configs/rsk7203_defconfig | 137 ++ arch/sh/configs/rsk7264_defconfig | 80 + arch/sh/configs/rsk7269_defconfig | 65 + arch/sh/configs/rts7751r2d1_defconfig | 99 + arch/sh/configs/rts7751r2dplus_defconfig | 107 ++ arch/sh/configs/sdk7780_defconfig | 154 ++ arch/sh/configs/sdk7786_defconfig | 235 +++ arch/sh/configs/se7206_defconfig | 123 ++ arch/sh/configs/se7343_defconfig | 110 ++ arch/sh/configs/se7619_defconfig | 51 + arch/sh/configs/se7705_defconfig | 62 + arch/sh/configs/se7712_defconfig | 112 ++ arch/sh/configs/se7721_defconfig | 137 ++ arch/sh/configs/se7722_defconfig | 62 + arch/sh/configs/se7724_defconfig | 145 ++ arch/sh/configs/se7750_defconfig | 62 + arch/sh/configs/se7751_defconfig | 53 + arch/sh/configs/se7780_defconfig | 115 ++ arch/sh/configs/secureedge5410_defconfig | 63 + arch/sh/configs/sh03_defconfig | 136 ++ arch/sh/configs/sh2007_defconfig | 212 +++ arch/sh/configs/sh7710voipgw_defconfig | 63 + arch/sh/configs/sh7724_generic_defconfig | 48 + arch/sh/configs/sh7757lcr_defconfig | 91 + arch/sh/configs/sh7763rdp_defconfig | 129 ++ arch/sh/configs/sh7770_generic_defconfig | 50 + arch/sh/configs/sh7785lcr_32bit_defconfig | 163 ++ arch/sh/configs/sh7785lcr_defconfig | 129 ++ arch/sh/configs/shmin_defconfig | 58 + arch/sh/configs/shx3_defconfig | 111 ++ arch/sh/configs/titan_defconfig | 286 +++ arch/sh/configs/ul2_defconfig | 97 + arch/sh/configs/urquell_defconfig | 161 ++ arch/sh/drivers/Kconfig | 19 + arch/sh/drivers/Makefile | 10 + arch/sh/drivers/dma/Kconfig | 75 + arch/sh/drivers/dma/Makefile | 8 + arch/sh/drivers/dma/dma-api.c | 432 +++++ arch/sh/drivers/dma/dma-g2.c | 200 ++ arch/sh/drivers/dma/dma-pvr2.c | 108 ++ arch/sh/drivers/dma/dma-sh.c | 417 ++++ arch/sh/drivers/dma/dma-sysfs.c | 167 ++ arch/sh/drivers/dma/dmabrg.c | 197 ++ arch/sh/drivers/heartbeat.c | 180 ++ arch/sh/drivers/pci/Makefile | 28 + arch/sh/drivers/pci/common.c | 162 ++ arch/sh/drivers/pci/fixups-cayman.c | 77 + arch/sh/drivers/pci/fixups-dreamcast.c | 77 + arch/sh/drivers/pci/fixups-landisk.c | 59 + arch/sh/drivers/pci/fixups-r7780rp.c | 21 + arch/sh/drivers/pci/fixups-rts7751r2d.c | 67 + arch/sh/drivers/pci/fixups-sdk7780.c | 43 + arch/sh/drivers/pci/fixups-sdk7786.c | 67 + arch/sh/drivers/pci/fixups-se7751.c | 112 ++ arch/sh/drivers/pci/fixups-sh03.c | 32 + arch/sh/drivers/pci/fixups-snapgear.c | 39 + arch/sh/drivers/pci/fixups-titan.c | 38 + arch/sh/drivers/pci/ops-dreamcast.c | 82 + arch/sh/drivers/pci/ops-sh4.c | 108 ++ arch/sh/drivers/pci/ops-sh5.c | 68 + arch/sh/drivers/pci/ops-sh7786.c | 171 ++ arch/sh/drivers/pci/pci-dreamcast.c | 100 + arch/sh/drivers/pci/pci-sh4.h | 189 ++ arch/sh/drivers/pci/pci-sh5.c | 220 +++ arch/sh/drivers/pci/pci-sh5.h | 110 ++ arch/sh/drivers/pci/pci-sh7751.c | 182 ++ arch/sh/drivers/pci/pci-sh7751.h | 129 ++ arch/sh/drivers/pci/pci-sh7780.c | 411 ++++ arch/sh/drivers/pci/pci-sh7780.h | 46 + arch/sh/drivers/pci/pci.c | 323 ++++ arch/sh/drivers/pci/pcie-sh7786.c | 579 ++++++ arch/sh/drivers/pci/pcie-sh7786.h | 583 ++++++ arch/sh/drivers/push-switch.c | 142 ++ arch/sh/drivers/superhyway/Makefile | 6 + arch/sh/drivers/superhyway/ops-sh4-202.c | 171 ++ arch/sh/include/asm/Kbuild | 36 + arch/sh/include/asm/adc.h | 13 + arch/sh/include/asm/addrspace.h | 69 + arch/sh/include/asm/alignment.h | 21 + arch/sh/include/asm/asm-offsets.h | 1 + arch/sh/include/asm/atomic-grb.h | 123 ++ arch/sh/include/asm/atomic-irq.h | 73 + arch/sh/include/asm/atomic-llsc.h | 107 ++ arch/sh/include/asm/atomic.h | 70 + arch/sh/include/asm/barrier.h | 54 + arch/sh/include/asm/bitops-grb.h | 172 ++ arch/sh/include/asm/bitops-llsc.h | 146 ++ arch/sh/include/asm/bitops-op32.h | 142 ++ arch/sh/include/asm/bitops.h | 104 + arch/sh/include/asm/bl_bit.h | 10 + arch/sh/include/asm/bl_bit_32.h | 33 + arch/sh/include/asm/bl_bit_64.h | 40 + arch/sh/include/asm/bug.h | 119 ++ arch/sh/include/asm/bugs.h | 77 + arch/sh/include/asm/cache.h | 47 + arch/sh/include/asm/cache_insns.h | 11 + arch/sh/include/asm/cache_insns_32.h | 21 + arch/sh/include/asm/cache_insns_64.h | 23 + arch/sh/include/asm/cacheflush.h | 104 + arch/sh/include/asm/checksum.h | 5 + arch/sh/include/asm/checksum_32.h | 215 +++ arch/sh/include/asm/clkdev.h | 31 + arch/sh/include/asm/clock.h | 16 + arch/sh/include/asm/cmpxchg-grb.h | 72 + arch/sh/include/asm/cmpxchg-irq.h | 42 + arch/sh/include/asm/cmpxchg-llsc.h | 71 + arch/sh/include/asm/cmpxchg.h | 70 + arch/sh/include/asm/device.h | 18 + arch/sh/include/asm/dma-mapping.h | 100 + arch/sh/include/asm/dma-register.h | 51 + arch/sh/include/asm/dma.h | 151 ++ arch/sh/include/asm/dmabrg.h | 23 + arch/sh/include/asm/dwarf.h | 421 ++++ arch/sh/include/asm/elf.h | 235 +++ arch/sh/include/asm/entry-macros.S | 122 ++ arch/sh/include/asm/fb.h | 19 + arch/sh/include/asm/fixmap.h | 136 ++ arch/sh/include/asm/flat.h | 30 + arch/sh/include/asm/fpu.h | 71 + arch/sh/include/asm/freq.h | 18 + arch/sh/include/asm/ftrace.h | 47 + arch/sh/include/asm/futex-irq.h | 110 ++ arch/sh/include/asm/futex.h | 78 + arch/sh/include/asm/gpio.h | 54 + arch/sh/include/asm/hardirq.h | 16 + arch/sh/include/asm/hd64461.h | 251 +++ arch/sh/include/asm/heartbeat.h | 18 + arch/sh/include/asm/hugetlb.h | 99 + arch/sh/include/asm/hw_breakpoint.h | 70 + arch/sh/include/asm/hw_irq.h | 35 + arch/sh/include/asm/i2c-sh7760.h | 20 + arch/sh/include/asm/io.h | 390 ++++ arch/sh/include/asm/io_generic.h | 18 + arch/sh/include/asm/io_noioport.h | 52 + arch/sh/include/asm/io_trapped.h | 58 + arch/sh/include/asm/irq.h | 72 + arch/sh/include/asm/irqflags.h | 9 + arch/sh/include/asm/kdebug.h | 17 + arch/sh/include/asm/kexec.h | 70 + arch/sh/include/asm/kgdb.h | 37 + arch/sh/include/asm/kmap_types.h | 14 + arch/sh/include/asm/kprobes.h | 57 + arch/sh/include/asm/linkage.h | 7 + arch/sh/include/asm/machvec.h | 43 + arch/sh/include/asm/mc146818rtc.h | 7 + arch/sh/include/asm/mmu.h | 106 ++ arch/sh/include/asm/mmu_context.h | 190 ++ arch/sh/include/asm/mmu_context_32.h | 59 + arch/sh/include/asm/mmu_context_64.h | 78 + arch/sh/include/asm/mmzone.h | 47 + arch/sh/include/asm/module.h | 41 + arch/sh/include/asm/mutex-llsc.h | 109 ++ arch/sh/include/asm/mutex.h | 12 + arch/sh/include/asm/page.h | 211 +++ arch/sh/include/asm/pci.h | 136 ++ arch/sh/include/asm/perf_event.h | 29 + arch/sh/include/asm/pgalloc.h | 76 + arch/sh/include/asm/pgtable-2level.h | 23 + arch/sh/include/asm/pgtable-3level.h | 56 + arch/sh/include/asm/pgtable.h | 166 ++ arch/sh/include/asm/pgtable_32.h | 498 +++++ arch/sh/include/asm/pgtable_64.h | 317 ++++ arch/sh/include/asm/posix_types.h | 5 + arch/sh/include/asm/processor.h | 183 ++ arch/sh/include/asm/processor_32.h | 206 ++ arch/sh/include/asm/processor_64.h | 224 +++ arch/sh/include/asm/ptrace.h | 117 ++ arch/sh/include/asm/ptrace_32.h | 13 + arch/sh/include/asm/ptrace_64.h | 13 + arch/sh/include/asm/push-switch.h | 31 + arch/sh/include/asm/reboot.h | 21 + arch/sh/include/asm/romimage-macros.h | 73 + arch/sh/include/asm/rtc.h | 28 + arch/sh/include/asm/rwsem.h | 132 ++ arch/sh/include/asm/seccomp.h | 10 + arch/sh/include/asm/sections.h | 12 + arch/sh/include/asm/segment.h | 34 + arch/sh/include/asm/setup.h | 24 + arch/sh/include/asm/sfp-machine.h | 84 + arch/sh/include/asm/sh7760fb.h | 197 ++ arch/sh/include/asm/sh_bios.h | 27 + arch/sh/include/asm/shmparam.h | 22 + arch/sh/include/asm/siu.h | 23 + arch/sh/include/asm/smc37c93x.h | 190 ++ arch/sh/include/asm/smp-ops.h | 51 + arch/sh/include/asm/smp.h | 78 + arch/sh/include/asm/sparsemem.h | 16 + arch/sh/include/asm/spi.h | 13 + arch/sh/include/asm/spinlock.h | 226 +++ arch/sh/include/asm/spinlock_types.h | 21 + arch/sh/include/asm/sram.h | 38 + arch/sh/include/asm/stackprotector.h | 27 + arch/sh/include/asm/stacktrace.h | 22 + arch/sh/include/asm/string.h | 5 + arch/sh/include/asm/string_32.h | 131 ++ arch/sh/include/asm/string_64.h | 20 + arch/sh/include/asm/suspend.h | 96 + arch/sh/include/asm/switch_to.h | 19 + arch/sh/include/asm/switch_to_32.h | 134 ++ arch/sh/include/asm/switch_to_64.h | 35 + arch/sh/include/asm/syscall.h | 12 + arch/sh/include/asm/syscall_32.h | 96 + arch/sh/include/asm/syscall_64.h | 64 + arch/sh/include/asm/syscalls.h | 20 + arch/sh/include/asm/syscalls_32.h | 35 + arch/sh/include/asm/syscalls_64.h | 17 + arch/sh/include/asm/thread_info.h | 214 +++ arch/sh/include/asm/timex.h | 23 + arch/sh/include/asm/tlb.h | 137 ++ arch/sh/include/asm/tlb_64.h | 71 + arch/sh/include/asm/tlbflush.h | 51 + arch/sh/include/asm/topology.h | 28 + arch/sh/include/asm/traps.h | 21 + arch/sh/include/asm/traps_32.h | 68 + arch/sh/include/asm/traps_64.h | 38 + arch/sh/include/asm/types.h | 20 + arch/sh/include/asm/uaccess.h | 211 +++ arch/sh/include/asm/uaccess_32.h | 173 ++ arch/sh/include/asm/uaccess_64.h | 87 + arch/sh/include/asm/unaligned-sh4a.h | 198 ++ arch/sh/include/asm/unaligned.h | 12 + arch/sh/include/asm/uncached.h | 58 + arch/sh/include/asm/unistd.h | 33 + arch/sh/include/asm/unwinder.h | 31 + arch/sh/include/asm/user.h | 67 + arch/sh/include/asm/vga.h | 6 + arch/sh/include/asm/vmlinux.lds.h | 25 + arch/sh/include/asm/watchdog.h | 165 ++ arch/sh/include/asm/word-at-a-time.h | 53 + arch/sh/include/cpu-common/cpu/addrspace.h | 19 + arch/sh/include/cpu-common/cpu/mmu_context.h | 16 + arch/sh/include/cpu-common/cpu/pfc.h | 26 + arch/sh/include/cpu-common/cpu/rtc.h | 8 + arch/sh/include/cpu-common/cpu/sigcontext.h | 17 + arch/sh/include/cpu-common/cpu/timer.h | 6 + arch/sh/include/cpu-sh2/cpu/cache.h | 43 + arch/sh/include/cpu-sh2/cpu/freq.h | 18 + arch/sh/include/cpu-sh2/cpu/watchdog.h | 69 + arch/sh/include/cpu-sh2a/cpu/addrspace.h | 10 + arch/sh/include/cpu-sh2a/cpu/cache.h | 43 + arch/sh/include/cpu-sh2a/cpu/freq.h | 16 + arch/sh/include/cpu-sh2a/cpu/rtc.h | 8 + arch/sh/include/cpu-sh2a/cpu/sh7203.h | 143 ++ arch/sh/include/cpu-sh2a/cpu/sh7264.h | 176 ++ arch/sh/include/cpu-sh2a/cpu/sh7269.h | 213 +++ arch/sh/include/cpu-sh2a/cpu/watchdog.h | 1 + arch/sh/include/cpu-sh3/cpu/adc.h | 28 + arch/sh/include/cpu-sh3/cpu/cache.h | 43 + arch/sh/include/cpu-sh3/cpu/dac.h | 41 + arch/sh/include/cpu-sh3/cpu/dma-register.h | 41 + arch/sh/include/cpu-sh3/cpu/dma.h | 18 + arch/sh/include/cpu-sh3/cpu/freq.h | 27 + arch/sh/include/cpu-sh3/cpu/gpio.h | 81 + arch/sh/include/cpu-sh3/cpu/mmu_context.h | 45 + arch/sh/include/cpu-sh3/cpu/serial.h | 10 + arch/sh/include/cpu-sh3/cpu/sh7720.h | 174 ++ arch/sh/include/cpu-sh3/cpu/watchdog.h | 25 + arch/sh/include/cpu-sh4/cpu/addrspace.h | 44 + arch/sh/include/cpu-sh4/cpu/cache.h | 44 + arch/sh/include/cpu-sh4/cpu/dma-register.h | 102 + arch/sh/include/cpu-sh4/cpu/dma.h | 17 + arch/sh/include/cpu-sh4/cpu/fpu.h | 32 + arch/sh/include/cpu-sh4/cpu/freq.h | 77 + arch/sh/include/cpu-sh4/cpu/mmu_context.h | 82 + arch/sh/include/cpu-sh4/cpu/rtc.h | 13 + arch/sh/include/cpu-sh4/cpu/sh7722.h | 251 +++ arch/sh/include/cpu-sh4/cpu/sh7723.h | 284 +++ arch/sh/include/cpu-sh4/cpu/sh7724.h | 318 ++++ arch/sh/include/cpu-sh4/cpu/sh7734.h | 306 +++ arch/sh/include/cpu-sh4/cpu/sh7757.h | 289 +++ arch/sh/include/cpu-sh4/cpu/sh7785.h | 259 +++ arch/sh/include/cpu-sh4/cpu/sh7786.h | 134 ++ arch/sh/include/cpu-sh4/cpu/shx3.h | 64 + arch/sh/include/cpu-sh4/cpu/sigcontext.h | 24 + arch/sh/include/cpu-sh4/cpu/sq.h | 36 + arch/sh/include/cpu-sh4/cpu/watchdog.h | 44 + arch/sh/include/cpu-sh4a/cpu/dma.h | 72 + arch/sh/include/cpu-sh4a/cpu/serial.h | 7 + arch/sh/include/cpu-sh5/cpu/addrspace.h | 11 + arch/sh/include/cpu-sh5/cpu/cache.h | 97 + arch/sh/include/cpu-sh5/cpu/irq.h | 116 ++ arch/sh/include/cpu-sh5/cpu/mmu_context.h | 21 + arch/sh/include/cpu-sh5/cpu/registers.h | 106 ++ arch/sh/include/cpu-sh5/cpu/rtc.h | 8 + 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arch/sh/mm/pgtable.c create mode 100644 arch/sh/mm/pmb.c create mode 100644 arch/sh/mm/sram.c create mode 100644 arch/sh/mm/tlb-debugfs.c create mode 100644 arch/sh/mm/tlb-pteaex.c create mode 100644 arch/sh/mm/tlb-sh3.c create mode 100644 arch/sh/mm/tlb-sh4.c create mode 100644 arch/sh/mm/tlb-sh5.c create mode 100644 arch/sh/mm/tlb-urb.c create mode 100644 arch/sh/mm/tlbex_32.c create mode 100644 arch/sh/mm/tlbex_64.c create mode 100644 arch/sh/mm/tlbflush_32.c create mode 100644 arch/sh/mm/tlbflush_64.c create mode 100644 arch/sh/mm/uncached.c create mode 100644 arch/sh/oprofile/Makefile create mode 100644 arch/sh/oprofile/backtrace.c create mode 100644 arch/sh/oprofile/common.c create mode 100644 arch/sh/tools/Makefile create mode 100644 arch/sh/tools/gen-mach-types create mode 100644 arch/sh/tools/mach-types (limited to 'arch/sh') diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig new file mode 100644 index 00000000..8c868cf2 --- /dev/null +++ b/arch/sh/Kconfig @@ -0,0 +1,935 @@ +config SUPERH + def_bool y + select EXPERT + select CLKDEV_LOOKUP + select HAVE_IDE if HAS_IOPORT + select HAVE_MEMBLOCK + select HAVE_MEMBLOCK_NODE_MAP + select ARCH_DISCARD_MEMBLOCK + select HAVE_OPROFILE + select HAVE_GENERIC_DMA_COHERENT + select HAVE_ARCH_TRACEHOOK + select HAVE_DMA_API_DEBUG + select HAVE_DMA_ATTRS + select HAVE_PERF_EVENTS + select HAVE_DEBUG_BUGVERBOSE + select ARCH_HAVE_CUSTOM_GPIO_H + select ARCH_HAVE_NMI_SAFE_CMPXCHG if (GUSA_RB || CPU_SH4A) + select PERF_USE_VMALLOC + select HAVE_DEBUG_KMEMLEAK + select HAVE_KERNEL_GZIP + select HAVE_KERNEL_BZIP2 + select HAVE_KERNEL_LZMA + select HAVE_KERNEL_XZ + select HAVE_KERNEL_LZO + select HAVE_UID16 + select ARCH_WANT_IPC_PARSE_VERSION + select HAVE_SYSCALL_TRACEPOINTS + select HAVE_REGS_AND_STACK_ACCESS_API + select HAVE_GENERIC_HARDIRQS + select MAY_HAVE_SPARSE_IRQ + select IRQ_FORCED_THREADING + select RTC_LIB + select GENERIC_ATOMIC64 + select GENERIC_IRQ_SHOW + select GENERIC_SMP_IDLE_THREAD + select GENERIC_IDLE_POLL_SETUP + select GENERIC_CLOCKEVENTS + select GENERIC_CMOS_UPDATE if SH_SH03 || SH_DREAMCAST + select GENERIC_STRNCPY_FROM_USER + select GENERIC_STRNLEN_USER + select HAVE_MOD_ARCH_SPECIFIC if DWARF_UNWINDER + select MODULES_USE_ELF_RELA + select OLD_SIGSUSPEND + select OLD_SIGACTION + help + The SuperH is a RISC processor targeted for use in embedded systems + and consumer electronics; it was also used in the Sega Dreamcast + gaming console. The SuperH port has a home page at + . + +config SUPERH32 + def_bool ARCH = "sh" + select HAVE_KPROBES + select HAVE_KRETPROBES + select HAVE_IOREMAP_PROT if MMU && !X2TLB + select HAVE_FUNCTION_TRACER + select HAVE_FTRACE_MCOUNT_RECORD + select HAVE_DYNAMIC_FTRACE + select HAVE_FUNCTION_TRACE_MCOUNT_TEST + select HAVE_FTRACE_NMI_ENTER if DYNAMIC_FTRACE + select ARCH_WANT_IPC_PARSE_VERSION + select HAVE_FUNCTION_GRAPH_TRACER + select HAVE_ARCH_KGDB + select HAVE_HW_BREAKPOINT + select HAVE_MIXED_BREAKPOINTS_REGS + select PERF_EVENTS + select ARCH_HIBERNATION_POSSIBLE if MMU + select SPARSE_IRQ + +config SUPERH64 + def_bool ARCH = "sh64" + select KALLSYMS + +config ARCH_DEFCONFIG + string + default "arch/sh/configs/shx3_defconfig" if SUPERH32 + default "arch/sh/configs/cayman_defconfig" if SUPERH64 + +config RWSEM_GENERIC_SPINLOCK + def_bool y + +config RWSEM_XCHGADD_ALGORITHM + bool + +config GENERIC_BUG + def_bool y + depends on BUG && SUPERH32 + +config GENERIC_CSUM + def_bool y + depends on SUPERH64 + +config GENERIC_HWEIGHT + def_bool y + +config GENERIC_CALIBRATE_DELAY + bool + +config GENERIC_LOCKBREAK + def_bool y + depends on SMP && PREEMPT + +config ARCH_SUSPEND_POSSIBLE + def_bool n + +config ARCH_HIBERNATION_POSSIBLE + def_bool n + +config SYS_SUPPORTS_APM_EMULATION + bool + select ARCH_SUSPEND_POSSIBLE + +config SYS_SUPPORTS_HUGETLBFS + bool + +config SYS_SUPPORTS_SMP + bool + +config SYS_SUPPORTS_NUMA + bool + +config SYS_SUPPORTS_PCI + bool + +config SYS_SUPPORTS_CMT + bool + +config SYS_SUPPORTS_MTU2 + bool + +config SYS_SUPPORTS_TMU + bool + +config STACKTRACE_SUPPORT + def_bool y + +config LOCKDEP_SUPPORT + def_bool y + +config HAVE_LATENCYTOP_SUPPORT + def_bool y + +config ARCH_HAS_ILOG2_U32 + def_bool n + +config ARCH_HAS_ILOG2_U64 + def_bool n + +config NO_IOPORT + def_bool !PCI + depends on !SH_CAYMAN && !SH_SH4202_MICRODEV && !SH_SHMIN && \ + !SH_HP6XX && !SH_SOLUTION_ENGINE + +config IO_TRAPPED + bool + +config SWAP_IO_SPACE + bool + +config DMA_COHERENT + bool + +config DMA_NONCOHERENT + def_bool !DMA_COHERENT + +config NEED_DMA_MAP_STATE + def_bool DMA_NONCOHERENT + +config NEED_SG_DMA_LENGTH + def_bool y + +source "init/Kconfig" + +source "kernel/Kconfig.freezer" + +menu "System type" + +# +# Processor families +# +config CPU_SH2 + bool + +config CPU_SH2A + bool + select CPU_SH2 + select UNCACHED_MAPPING + +config CPU_SH3 + bool + select CPU_HAS_INTEVT + select CPU_HAS_SR_RB + select SYS_SUPPORTS_TMU + +config CPU_SH4 + bool + select CPU_HAS_INTEVT + select CPU_HAS_SR_RB + select CPU_HAS_FPU if !CPU_SH4AL_DSP + select SYS_SUPPORTS_TMU + select SYS_SUPPORTS_HUGETLBFS if MMU + +config CPU_SH4A + bool + select CPU_SH4 + +config CPU_SH4AL_DSP + bool + select CPU_SH4A + select CPU_HAS_DSP + +config CPU_SH5 + bool + select CPU_HAS_FPU + select SYS_SUPPORTS_TMU + select SYS_SUPPORTS_HUGETLBFS if MMU + +config CPU_SHX2 + bool + +config CPU_SHX3 + bool + select DMA_COHERENT + select SYS_SUPPORTS_SMP + select SYS_SUPPORTS_NUMA + +config ARCH_SHMOBILE + bool + select ARCH_SUSPEND_POSSIBLE + select PM + select PM_RUNTIME + +config CPU_HAS_PMU + depends on CPU_SH4 || CPU_SH4A + default y + bool + +if SUPERH32 + +choice + prompt "Processor sub-type selection" + +# +# Processor subtypes +# + +# SH-2 Processor Support + +config CPU_SUBTYPE_SH7619 + bool "Support SH7619 processor" + select CPU_SH2 + select SYS_SUPPORTS_CMT + +# SH-2A Processor Support + +config CPU_SUBTYPE_SH7201 + bool "Support SH7201 processor" + select CPU_SH2A + select CPU_HAS_FPU + select SYS_SUPPORTS_MTU2 + +config CPU_SUBTYPE_SH7203 + bool "Support SH7203 processor" + select CPU_SH2A + select CPU_HAS_FPU + select SYS_SUPPORTS_CMT + select SYS_SUPPORTS_MTU2 + select ARCH_WANT_OPTIONAL_GPIOLIB + select PINCTRL + +config CPU_SUBTYPE_SH7206 + bool "Support SH7206 processor" + select CPU_SH2A + select SYS_SUPPORTS_CMT + select SYS_SUPPORTS_MTU2 + +config CPU_SUBTYPE_SH7263 + bool "Support SH7263 processor" + select CPU_SH2A + select CPU_HAS_FPU + select SYS_SUPPORTS_CMT + select SYS_SUPPORTS_MTU2 + +config CPU_SUBTYPE_SH7264 + bool "Support SH7264 processor" + select CPU_SH2A + select CPU_HAS_FPU + select SYS_SUPPORTS_CMT + select SYS_SUPPORTS_MTU2 + select PINCTRL + +config CPU_SUBTYPE_SH7269 + bool "Support SH7269 processor" + select CPU_SH2A + select CPU_HAS_FPU + select SYS_SUPPORTS_CMT + select SYS_SUPPORTS_MTU2 + select PINCTRL + +config CPU_SUBTYPE_MXG + bool "Support MX-G processor" + select CPU_SH2A + select SYS_SUPPORTS_MTU2 + help + Select MX-G if running on an R8A03022BG part. + +# SH-3 Processor Support + +config CPU_SUBTYPE_SH7705 + bool "Support SH7705 processor" + select CPU_SH3 + +config CPU_SUBTYPE_SH7706 + bool "Support SH7706 processor" + select CPU_SH3 + help + Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU. + +config CPU_SUBTYPE_SH7707 + bool "Support SH7707 processor" + select CPU_SH3 + help + Select SH7707 if you have a 60 Mhz SH-3 HD6417707 CPU. + +config CPU_SUBTYPE_SH7708 + bool "Support SH7708 processor" + select CPU_SH3 + help + Select SH7708 if you have a 60 Mhz SH-3 HD6417708S or + if you have a 100 Mhz SH-3 HD6417708R CPU. + +config CPU_SUBTYPE_SH7709 + bool "Support SH7709 processor" + select CPU_SH3 + help + Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU. + +config CPU_SUBTYPE_SH7710 + bool "Support SH7710 processor" + select CPU_SH3 + select CPU_HAS_DSP + help + Select SH7710 if you have a SH3-DSP SH7710 CPU. + +config CPU_SUBTYPE_SH7712 + bool "Support SH7712 processor" + select CPU_SH3 + select CPU_HAS_DSP + help + Select SH7712 if you have a SH3-DSP SH7712 CPU. + +config CPU_SUBTYPE_SH7720 + bool "Support SH7720 processor" + select CPU_SH3 + select CPU_HAS_DSP + select SYS_SUPPORTS_CMT + select ARCH_WANT_OPTIONAL_GPIOLIB + select USB_ARCH_HAS_OHCI + select USB_OHCI_SH if USB_OHCI_HCD + select PINCTRL + help + Select SH7720 if you have a SH3-DSP SH7720 CPU. + +config CPU_SUBTYPE_SH7721 + bool "Support SH7721 processor" + select CPU_SH3 + select CPU_HAS_DSP + select SYS_SUPPORTS_CMT + select USB_ARCH_HAS_OHCI + select USB_OHCI_SH if USB_OHCI_HCD + help + Select SH7721 if you have a SH3-DSP SH7721 CPU. + +# SH-4 Processor Support + +config CPU_SUBTYPE_SH7750 + bool "Support SH7750 processor" + select CPU_SH4 + help + Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU. + +config CPU_SUBTYPE_SH7091 + bool "Support SH7091 processor" + select CPU_SH4 + help + Select SH7091 if you have an SH-4 based Sega device (such as + the Dreamcast, Naomi, and Naomi 2). + +config CPU_SUBTYPE_SH7750R + bool "Support SH7750R processor" + select CPU_SH4 + +config CPU_SUBTYPE_SH7750S + bool "Support SH7750S processor" + select CPU_SH4 + +config CPU_SUBTYPE_SH7751 + bool "Support SH7751 processor" + select CPU_SH4 + help + Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU, + or if you have a HD6417751R CPU. + +config CPU_SUBTYPE_SH7751R + bool "Support SH7751R processor" + select CPU_SH4 + +config CPU_SUBTYPE_SH7760 + bool "Support SH7760 processor" + select CPU_SH4 + +config CPU_SUBTYPE_SH4_202 + bool "Support SH4-202 processor" + select CPU_SH4 + +# SH-4A Processor Support + +config CPU_SUBTYPE_SH7723 + bool "Support SH7723 processor" + select CPU_SH4A + select CPU_SHX2 + select ARCH_SHMOBILE + select ARCH_SPARSEMEM_ENABLE + select SYS_SUPPORTS_CMT + select ARCH_WANT_OPTIONAL_GPIOLIB + select PINCTRL + help + Select SH7723 if you have an SH-MobileR2 CPU. + +config CPU_SUBTYPE_SH7724 + bool "Support SH7724 processor" + select CPU_SH4A + select CPU_SHX2 + select ARCH_SHMOBILE + select ARCH_SPARSEMEM_ENABLE + select SYS_SUPPORTS_CMT + select ARCH_WANT_OPTIONAL_GPIOLIB + select PINCTRL + help + Select SH7724 if you have an SH-MobileR2R CPU. + +config CPU_SUBTYPE_SH7734 + bool "Support SH7734 processor" + select CPU_SH4A + select CPU_SHX2 + select ARCH_WANT_OPTIONAL_GPIOLIB + select USB_ARCH_HAS_OHCI + select USB_ARCH_HAS_EHCI + select PINCTRL + help + Select SH7734 if you have a SH4A SH7734 CPU. + +config CPU_SUBTYPE_SH7757 + bool "Support SH7757 processor" + select CPU_SH4A + select CPU_SHX2 + select ARCH_WANT_OPTIONAL_GPIOLIB + select USB_ARCH_HAS_OHCI + select USB_ARCH_HAS_EHCI + select PINCTRL + help + Select SH7757 if you have a SH4A SH7757 CPU. + +config CPU_SUBTYPE_SH7763 + bool "Support SH7763 processor" + select CPU_SH4A + select USB_ARCH_HAS_OHCI + select USB_OHCI_SH if USB_OHCI_HCD + help + Select SH7763 if you have a SH4A SH7763(R5S77631) CPU. + +config CPU_SUBTYPE_SH7770 + bool "Support SH7770 processor" + select CPU_SH4A + +config CPU_SUBTYPE_SH7780 + bool "Support SH7780 processor" + select CPU_SH4A + +config CPU_SUBTYPE_SH7785 + bool "Support SH7785 processor" + select CPU_SH4A + select CPU_SHX2 + select ARCH_SPARSEMEM_ENABLE + select SYS_SUPPORTS_NUMA + select ARCH_WANT_OPTIONAL_GPIOLIB + select PINCTRL + +config CPU_SUBTYPE_SH7786 + bool "Support SH7786 processor" + select CPU_SH4A + select CPU_SHX3 + select CPU_HAS_PTEAEX + select GENERIC_CLOCKEVENTS_BROADCAST if SMP + select ARCH_WANT_OPTIONAL_GPIOLIB + select USB_ARCH_HAS_OHCI + select USB_OHCI_SH if USB_OHCI_HCD + select USB_ARCH_HAS_EHCI + select USB_EHCI_SH if USB_EHCI_HCD + select PINCTRL + +config CPU_SUBTYPE_SHX3 + bool "Support SH-X3 processor" + select CPU_SH4A + select CPU_SHX3 + select GENERIC_CLOCKEVENTS_BROADCAST if SMP + select ARCH_REQUIRE_GPIOLIB + select PINCTRL + +# SH4AL-DSP Processor Support + +config CPU_SUBTYPE_SH7343 + bool "Support SH7343 processor" + select CPU_SH4AL_DSP + select ARCH_SHMOBILE + select SYS_SUPPORTS_CMT + +config CPU_SUBTYPE_SH7722 + bool "Support SH7722 processor" + select CPU_SH4AL_DSP + select CPU_SHX2 + select ARCH_SHMOBILE + select ARCH_SPARSEMEM_ENABLE + select SYS_SUPPORTS_NUMA + select SYS_SUPPORTS_CMT + select ARCH_WANT_OPTIONAL_GPIOLIB + select PINCTRL + +config CPU_SUBTYPE_SH7366 + bool "Support SH7366 processor" + select CPU_SH4AL_DSP + select CPU_SHX2 + select ARCH_SHMOBILE + select ARCH_SPARSEMEM_ENABLE + select SYS_SUPPORTS_NUMA + select SYS_SUPPORTS_CMT + +endchoice + +endif + +if SUPERH64 + +choice + prompt "Processor sub-type selection" + +# SH-5 Processor Support + +config CPU_SUBTYPE_SH5_101 + bool "Support SH5-101 processor" + select CPU_SH5 + +config CPU_SUBTYPE_SH5_103 + bool "Support SH5-103 processor" + select CPU_SH5 + +endchoice + +endif + +source "arch/sh/mm/Kconfig" + +source "arch/sh/Kconfig.cpu" + +source "arch/sh/boards/Kconfig" + +menu "Timer and clock configuration" + +config SH_TIMER_TMU + bool "TMU timer driver" + depends on SYS_SUPPORTS_TMU + default y + help + This enables the build of the TMU timer driver. + +config SH_TIMER_CMT + bool "CMT timer driver" + depends on SYS_SUPPORTS_CMT + default y + help + This enables build of the CMT timer driver. + +config SH_TIMER_MTU2 + bool "MTU2 timer driver" + depends on SYS_SUPPORTS_MTU2 + default y + help + This enables build of the MTU2 timer driver. + +config SH_PCLK_FREQ + int "Peripheral clock frequency (in Hz)" + depends on SH_CLK_CPG_LEGACY + default "31250000" if CPU_SUBTYPE_SH7619 + default "33333333" if CPU_SUBTYPE_SH7770 || \ + CPU_SUBTYPE_SH7760 || \ + CPU_SUBTYPE_SH7705 || \ + CPU_SUBTYPE_SH7203 || \ + CPU_SUBTYPE_SH7206 || \ + CPU_SUBTYPE_SH7263 || \ + CPU_SUBTYPE_MXG + default "60000000" if CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R + default "66000000" if CPU_SUBTYPE_SH4_202 + default "50000000" + help + This option is used to specify the peripheral clock frequency. + This is necessary for determining the reference clock value on + platforms lacking an RTC. + +config SH_CLK_CPG + def_bool y + +config SH_CLK_CPG_LEGACY + depends on SH_CLK_CPG + def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE && \ + !CPU_SHX3 && !CPU_SUBTYPE_SH7757 && \ + !CPU_SUBTYPE_SH7734 && !CPU_SUBTYPE_SH7264 && \ + !CPU_SUBTYPE_SH7269 + +endmenu + +menu "CPU Frequency scaling" +source "drivers/cpufreq/Kconfig" +endmenu + +source "arch/sh/drivers/Kconfig" + +endmenu + +menu "Kernel features" + +source kernel/Kconfig.hz + +config KEXEC + bool "kexec system call (EXPERIMENTAL)" + depends on SUPERH32 && MMU + help + kexec is a system call that implements the ability to shutdown your + current kernel, and to start another kernel. It is like a reboot + but it is independent of the system firmware. And like a reboot + you can start any kernel with it, not just Linux. + + The name comes from the similarity to the exec system call. + + It is an ongoing process to be certain the hardware in a machine + is properly shutdown, so do not be surprised if this code does not + initially work for you. It may help to enable device hotplugging + support. As of this writing the exact hardware interface is + strongly in flux, so no good recommendation can be made. + +config CRASH_DUMP + bool "kernel crash dumps (EXPERIMENTAL)" + depends on SUPERH32 && BROKEN_ON_SMP + help + Generate crash dump after being started by kexec. + This should be normally only set in special crash dump kernels + which are loaded in the main kernel with kexec-tools into + a specially reserved region and then later executed after + a crash by kdump/kexec. The crash dump kernel must be compiled + to a memory address not used by the main kernel using + PHYSICAL_START. + + For more details see Documentation/kdump/kdump.txt + +config KEXEC_JUMP + bool "kexec jump (EXPERIMENTAL)" + depends on SUPERH32 && KEXEC && HIBERNATION + help + Jump between original kernel and kexeced kernel and invoke + code via KEXEC + +config PHYSICAL_START + hex "Physical address where the kernel is loaded" if (EXPERT || CRASH_DUMP) + default MEMORY_START + ---help--- + This gives the physical address where the kernel is loaded + and is ordinarily the same as MEMORY_START. + + Different values are primarily used in the case of kexec on panic + where the fail safe kernel needs to run at a different address + than the panic-ed kernel. + +config SECCOMP + bool "Enable seccomp to safely compute untrusted bytecode" + depends on PROC_FS + help + This kernel feature is useful for number crunching applications + that may need to compute untrusted bytecode during their + execution. By using pipes or other transports made available to + the process as file descriptors supporting the read/write + syscalls, it's possible to isolate those applications in + their own address space using seccomp. Once seccomp is + enabled via prctl, it cannot be disabled and the task is only + allowed to execute a few safe syscalls defined by each seccomp + mode. + + If unsure, say N. + +config CC_STACKPROTECTOR + bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)" + depends on SUPERH32 + help + This option turns on the -fstack-protector GCC feature. This + feature puts, at the beginning of functions, a canary value on + the stack just before the return address, and validates + the value just before actually returning. Stack based buffer + overflows (that need to overwrite this return address) now also + overwrite the canary, which gets detected and the attack is then + neutralized via a kernel panic. + + This feature requires gcc version 4.2 or above. + +config SMP + bool "Symmetric multi-processing support" + depends on SYS_SUPPORTS_SMP + select USE_GENERIC_SMP_HELPERS + ---help--- + This enables support for systems with more than one CPU. If you have + a system with only one CPU, like most personal computers, say N. If + you have a system with more than one CPU, say Y. + + If you say N here, the kernel will run on single and multiprocessor + machines, but will use only one CPU of a multiprocessor machine. If + you say Y here, the kernel will run on many, but not all, + singleprocessor machines. On a singleprocessor machine, the kernel + will run faster if you say N here. + + People using multiprocessor machines who say Y here should also say + Y to "Enhanced Real Time Clock Support", below. + + See also and the SMP-HOWTO + available at . + + If you don't know what to do here, say N. + +config NR_CPUS + int "Maximum number of CPUs (2-32)" + range 2 32 + depends on SMP + default "4" if CPU_SUBTYPE_SHX3 + default "2" + help + This allows you to specify the maximum number of CPUs which this + kernel will support. The maximum supported value is 32 and the + minimum value which makes sense is 2. + + This is purely to save memory - each supported CPU adds + approximately eight kilobytes to the kernel image. + +config HOTPLUG_CPU + bool "Support for hot-pluggable CPUs (EXPERIMENTAL)" + depends on SMP && HOTPLUG + help + Say Y here to experiment with turning CPUs off and on. CPUs + can be controlled through /sys/devices/system/cpu. + +source "kernel/Kconfig.preempt" + +config GUSA + def_bool y + depends on !SMP && SUPERH32 + help + This enables support for gUSA (general UserSpace Atomicity). + This is the default implementation for both UP and non-ll/sc + CPUs, and is used by the libc, amongst others. + + For additional information, design information can be found + in . + + This should only be disabled for special cases where alternate + atomicity implementations exist. + +config GUSA_RB + bool "Implement atomic operations by roll-back (gRB) (EXPERIMENTAL)" + depends on GUSA && CPU_SH3 || (CPU_SH4 && !CPU_SH4A) + help + Enabling this option will allow the kernel to implement some + atomic operations using a software implementation of load-locked/ + store-conditional (LLSC). On machines which do not have hardware + LLSC, this should be more efficient than the other alternative of + disabling interrupts around the atomic sequence. + +config HW_PERF_EVENTS + bool "Enable hardware performance counter support for perf events" + depends on PERF_EVENTS && CPU_HAS_PMU + default y + help + Enable hardware performance counter support for perf events. If + disabled, perf events will use software events only. + +source "drivers/sh/Kconfig" + +endmenu + +menu "Boot options" + +config ZERO_PAGE_OFFSET + hex + default "0x00010000" if PAGE_SIZE_64KB || SH_RTS7751R2D || \ + SH_7751_SOLUTION_ENGINE + default "0x00004000" if PAGE_SIZE_16KB || SH_SH03 + default "0x00002000" if PAGE_SIZE_8KB + default "0x00001000" + help + This sets the default offset of zero page. + +config BOOT_LINK_OFFSET + hex + default "0x00210000" if SH_SHMIN + default "0x00400000" if SH_CAYMAN + default "0x00810000" if SH_7780_SOLUTION_ENGINE + default "0x009e0000" if SH_TITAN + default "0x01800000" if SH_SDK7780 + default "0x02000000" if SH_EDOSK7760 + default "0x00800000" + help + This option allows you to set the link address offset of the zImage. + This can be useful if you are on a board which has a small amount of + memory. + +config ENTRY_OFFSET + hex + default "0x00001000" if PAGE_SIZE_4KB + default "0x00002000" if PAGE_SIZE_8KB + default "0x00004000" if PAGE_SIZE_16KB + default "0x00010000" if PAGE_SIZE_64KB + default "0x00000000" + +config ROMIMAGE_MMCIF + bool "Include MMCIF loader in romImage (EXPERIMENTAL)" + depends on CPU_SUBTYPE_SH7724 + help + Say Y here to include experimental MMCIF loading code in + romImage. With this enabled it is possible to write the romImage + kernel image to an MMC card and boot the kernel straight from + the reset vector. At reset the processor Mask ROM will load the + first part of the romImage which in turn loads the rest the kernel + image to RAM using the MMCIF hardware block. + +choice + prompt "Kernel command line" + optional + default CMDLINE_OVERWRITE + help + Setting this option allows the kernel command line arguments + to be set. + +config CMDLINE_OVERWRITE + bool "Overwrite bootloader kernel arguments" + help + Given string will overwrite any arguments passed in by + a bootloader. + +config CMDLINE_EXTEND + bool "Extend bootloader kernel arguments" + help + Given string will be concatenated with arguments passed in + by a bootloader. + +endchoice + +config CMDLINE + string "Kernel command line arguments string" + depends on CMDLINE_OVERWRITE || CMDLINE_EXTEND + default "console=ttySC1,115200" + +endmenu + +menu "Bus options" + +config SUPERHYWAY + tristate "SuperHyway Bus support" + depends on CPU_SUBTYPE_SH4_202 + +config MAPLE + bool "Maple Bus support" + depends on SH_DREAMCAST + help + The Maple Bus is SEGA's serial communication bus for peripherals + on the Dreamcast. Without this bus support you won't be able to + get your Dreamcast keyboard etc to work, so most users + probably want to say 'Y' here, unless you are only using the + Dreamcast with a serial line terminal or a remote network + connection. + +config PCI + bool "PCI support" + depends on SYS_SUPPORTS_PCI + select PCI_DOMAINS + select GENERIC_PCI_IOMAP + select NO_GENERIC_PCI_IOPORT_MAP + help + Find out whether you have a PCI motherboard. PCI is the name of a + bus system, i.e. the way the CPU talks to the other stuff inside + your box. If you have PCI, say Y, otherwise N. + +config PCI_DOMAINS + bool + +source "drivers/pci/pcie/Kconfig" + +source "drivers/pci/Kconfig" + +source "drivers/pcmcia/Kconfig" + +source "drivers/pci/hotplug/Kconfig" + +endmenu + +menu "Executable file formats" + +source "fs/Kconfig.binfmt" + +endmenu + +menu "Power management options (EXPERIMENTAL)" + +source "kernel/power/Kconfig" + +source "drivers/cpuidle/Kconfig" + +endmenu + +source "net/Kconfig" + +source "drivers/Kconfig" + +source "fs/Kconfig" + +source "arch/sh/Kconfig.debug" + +source "security/Kconfig" + +source "crypto/Kconfig" + +source "lib/Kconfig" diff --git a/arch/sh/Kconfig.cpu b/arch/sh/Kconfig.cpu new file mode 100644 index 00000000..05b518e9 --- /dev/null +++ b/arch/sh/Kconfig.cpu @@ -0,0 +1,108 @@ +menu "Processor features" + +choice + prompt "Endianness selection" + default CPU_LITTLE_ENDIAN + help + Some SuperH machines can be configured for either little or big + endian byte order. These modes require different kernels. + +config CPU_LITTLE_ENDIAN + bool "Little Endian" + +config CPU_BIG_ENDIAN + bool "Big Endian" + depends on !CPU_SH5 + +endchoice + +config SH_FPU + def_bool y + prompt "FPU support" + depends on CPU_HAS_FPU + help + Selecting this option will enable support for SH processors that + have FPU units (ie, SH77xx). + + This option must be set in order to enable the FPU. + +config SH64_FPU_DENORM_FLUSH + bool "Flush floating point denorms to zero" + depends on SH_FPU && SUPERH64 + +config SH_FPU_EMU + def_bool n + prompt "FPU emulation support" + depends on !SH_FPU + help + Selecting this option will enable support for software FPU emulation. + Most SH-3 users will want to say Y here, whereas most SH-4 users will + want to say N. + +config SH_DSP + def_bool y + prompt "DSP support" + depends on CPU_HAS_DSP + help + Selecting this option will enable support for SH processors that + have DSP units (ie, SH2-DSP, SH3-DSP, and SH4AL-DSP). + + This option must be set in order to enable the DSP. + +config SH_ADC + def_bool y + prompt "ADC support" + depends on CPU_SH3 + help + Selecting this option will allow the Linux kernel to use SH3 on-chip + ADC module. + + If unsure, say N. + +config SH_STORE_QUEUES + bool "Support for Store Queues" + depends on CPU_SH4 + help + Selecting this option will enable an in-kernel API for manipulating + the store queues integrated in the SH-4 processors. + +config SPECULATIVE_EXECUTION + bool "Speculative subroutine return" + depends on CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785 || CPU_SUBTYPE_SH7786 + help + This enables support for a speculative instruction fetch for + subroutine return. There are various pitfalls associated with + this, as outlined in the SH7780 hardware manual. + + If unsure, say N. + +config SH64_ID2815_WORKAROUND + bool "Include workaround for SH5-101 cut2 silicon defect ID2815" + depends on CPU_SUBTYPE_SH5_101 + +config CPU_HAS_INTEVT + bool + +config CPU_HAS_IPR_IRQ + bool + +config CPU_HAS_SR_RB + bool + help + This will enable the use of SR.RB register bank usage. Processors + that are lacking this bit must have another method in place for + accomplishing what is taken care of by the banked registers. + + See for further + information on SR.RB and register banking in the kernel in general. + +config CPU_HAS_PTEAEX + bool + +config CPU_HAS_DSP + bool + +config CPU_HAS_FPU + bool + +endmenu diff --git a/arch/sh/Kconfig.debug b/arch/sh/Kconfig.debug new file mode 100644 index 00000000..5f2bb424 --- /dev/null +++ b/arch/sh/Kconfig.debug @@ -0,0 +1,91 @@ +menu "Kernel hacking" + +config TRACE_IRQFLAGS_SUPPORT + def_bool y + +source "lib/Kconfig.debug" + +config SH_STANDARD_BIOS + bool "Use LinuxSH standard BIOS" + depends on SUPERH32 + help + Say Y here if your target has the gdb-sh-stub + package from www.m17n.org (or any conforming standard LinuxSH BIOS) + in FLASH or EPROM. The kernel will use standard BIOS calls during + boot for various housekeeping tasks (including calls to read and + write characters to a system console, get a MAC address from an + on-board Ethernet interface, and shut down the hardware). Note this + does not work with machines with an existing operating system in + mask ROM and no flash (WindowsCE machines fall in this category). + If unsure, say N. + +config STACK_DEBUG + bool "Check for stack overflows" + depends on DEBUG_KERNEL && SUPERH32 + help + This option will cause messages to be printed if free stack space + drops below a certain limit. Saying Y here will add overhead to + every function call and will therefore incur a major + performance hit. Most users should say N. + +config 4KSTACKS + bool "Use 4Kb for kernel stacks instead of 8Kb" + depends on DEBUG_KERNEL && (MMU || BROKEN) && !PAGE_SIZE_64KB + help + If you say Y here the kernel will use a 4Kb stacksize for the + kernel stack attached to each process/thread. This facilitates + running more threads on a system and also reduces the pressure + on the VM subsystem for higher order allocations. This option + will also use IRQ stacks to compensate for the reduced stackspace. + +config IRQSTACKS + bool "Use separate kernel stacks when processing interrupts" + depends on DEBUG_KERNEL && SUPERH32 && BROKEN + help + If you say Y here the kernel will use separate kernel stacks + for handling hard and soft interrupts. This can help avoid + overflowing the process kernel stacks. + +config DUMP_CODE + bool "Show disassembly of nearby code in register dumps" + depends on DEBUG_KERNEL && SUPERH32 + default y if DEBUG_BUGVERBOSE + default n + help + This prints out a code trace of the instructions leading up to + the faulting instruction as a debugging aid. As this does grow + the kernel in size a bit, most users will want to say N here. + + Those looking for more verbose debugging output should say Y. + +config DWARF_UNWINDER + bool "Enable the DWARF unwinder for stacktraces" + select FRAME_POINTER + depends on SUPERH32 + default n + help + Enabling this option will make stacktraces more accurate, at + the cost of an increase in overall kernel size. + +config SH_NO_BSS_INIT + bool "Avoid zeroing BSS (to speed-up startup on suitable platforms)" + depends on DEBUG_KERNEL + default n + help + If running in painfully slow environments, such as an RTL + simulation or from remote memory via SHdebug, where the memory + can already be guaranteed to ber zeroed on boot, say Y. + + For all other cases, say N. If this option seems perplexing, or + you aren't sure, say N. + +config SH64_SR_WATCH + bool "Debug: set SR.WATCH to enable hardware watchpoints and trace" + depends on SUPERH64 + +config MCOUNT + def_bool y + depends on SUPERH32 + depends on STACK_DEBUG || FUNCTION_TRACER + +endmenu diff --git a/arch/sh/Makefile b/arch/sh/Makefile new file mode 100644 index 00000000..aed701c7 --- /dev/null +++ b/arch/sh/Makefile @@ -0,0 +1,241 @@ +# +# arch/sh/Makefile +# +# Copyright (C) 1999 Kaz Kojima +# Copyright (C) 2002 - 2008 Paul Mundt +# Copyright (C) 2002 M. R. Brown +# +# This file is subject to the terms and conditions of the GNU General Public +# License. See the file "COPYING" in the main directory of this archive +# for more details. +# +ifneq ($(SUBARCH),$(ARCH)) + ifeq ($(CROSS_COMPILE),) + CROSS_COMPILE := $(call cc-cross-prefix, $(UTS_MACHINE)-linux- $(UTS_MACHINE)-linux-gnu- $(UTS_MACHINE)-unknown-linux-gnu-) + endif +endif + +isa-y := any +isa-$(CONFIG_SH_DSP) := sh +isa-$(CONFIG_CPU_SH2) := sh2 +isa-$(CONFIG_CPU_SH2A) := sh2a +isa-$(CONFIG_CPU_SH3) := sh3 +isa-$(CONFIG_CPU_SH4) := sh4 +isa-$(CONFIG_CPU_SH4A) := sh4a +isa-$(CONFIG_CPU_SH4AL_DSP) := sh4al +isa-$(CONFIG_CPU_SH5) := shmedia + +ifeq ($(CONFIG_SUPERH32),y) +isa-$(CONFIG_SH_DSP) := $(isa-y)-dsp +isa-y := $(isa-y)-up +endif + +cflags-$(CONFIG_CPU_SH2) := $(call cc-option,-m2,) +cflags-$(CONFIG_CPU_SH2A) += $(call cc-option,-m2a,) \ + $(call cc-option,-m2a-nofpu,) +cflags-$(CONFIG_CPU_SH3) := $(call cc-option,-m3,) +cflags-$(CONFIG_CPU_SH4) := $(call cc-option,-m4,) \ + $(call cc-option,-mno-implicit-fp,-m4-nofpu) +cflags-$(CONFIG_CPU_SH4A) += $(call cc-option,-m4a,) \ + $(call cc-option,-m4a-nofpu,) +cflags-$(CONFIG_CPU_SH4AL_DSP) += $(call cc-option,-m4al,) +cflags-$(CONFIG_CPU_SH5) := $(call cc-option,-m5-32media-nofpu,) + +ifeq ($(cflags-y),) +# +# In the case where we are stuck with a compiler that has been uselessly +# restricted to a particular ISA, a favourite default of newer GCCs when +# extensive multilib targets are not provided, ensure we get the best fit +# regarding FP generation. This is intentionally stupid (albeit many +# orders of magnitude less than GCC's default behaviour), as anything +# with a large number of multilib targets better have been built +# correctly for the target in mind. +# +cflags-y += $(shell $(CC) $(KBUILD_CFLAGS) -print-multi-lib | \ + grep nofpu | sed q | sed -e 's/^/-/;s/;.*$$//') +# At this point, anything goes. +isaflags-y := $(call as-option,-Wa$(comma)-isa=any,) +else +# +# -Wa,-isa= tuning implies -Wa,-dsp for the versions of binutils that +# support it, while -Wa,-dsp by itself limits the range of usable opcodes +# on certain CPU subtypes. Try the ISA variant first, and if that fails, +# fall back on -Wa,-dsp for the old binutils versions. Even without DSP +# opcodes, we always want the best ISA tuning the version of binutils +# will provide. +# +isaflags-y := $(call as-option,-Wa$(comma)-isa=$(isa-y),) + +isaflags-$(CONFIG_SH_DSP) := \ + $(call as-option,-Wa$(comma)-isa=$(isa-y),-Wa$(comma)-dsp) +endif + +cflags-$(CONFIG_CPU_BIG_ENDIAN) += -mb +cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += -ml + +cflags-y += $(call cc-option,-mno-fdpic) +cflags-y += $(isaflags-y) -ffreestanding + +OBJCOPYFLAGS := -O binary -R .note -R .note.gnu.build-id -R .comment \ + -R .stab -R .stabstr -S + +# Give the various platforms the opportunity to set default image types +defaultimage-$(CONFIG_SUPERH32) := zImage +defaultimage-$(CONFIG_SH_SH7785LCR) := uImage +defaultimage-$(CONFIG_SH_RSK) := uImage +defaultimage-$(CONFIG_SH_URQUELL) := uImage +defaultimage-$(CONFIG_SH_MIGOR) := uImage +defaultimage-$(CONFIG_SH_AP325RXA) := uImage +defaultimage-$(CONFIG_SH_SH7757LCR) := uImage +defaultimage-$(CONFIG_SH_7724_SOLUTION_ENGINE) := uImage +defaultimage-$(CONFIG_SH_7206_SOLUTION_ENGINE) := vmlinux +defaultimage-$(CONFIG_SH_7619_SOLUTION_ENGINE) := vmlinux + +# Set some sensible Kbuild defaults +KBUILD_IMAGE := $(defaultimage-y) + +# +# Choosing incompatible machines durings configuration will result in +# error messages during linking. +# +ifdef CONFIG_SUPERH32 +UTS_MACHINE := sh +BITS := 32 +LDFLAGS_vmlinux += -e _stext +KBUILD_DEFCONFIG := shx3_defconfig +else +UTS_MACHINE := sh64 +BITS := 64 +LDFLAGS_vmlinux += --defsym phys_stext=_stext-$(CONFIG_PAGE_OFFSET) \ + --defsym phys_stext_shmedia=phys_stext+1 \ + -e phys_stext_shmedia +KBUILD_DEFCONFIG := cayman_defconfig +endif + +ifdef CONFIG_CPU_LITTLE_ENDIAN +ld-bfd := elf32-$(UTS_MACHINE)-linux +LDFLAGS_vmlinux += --defsym jiffies=jiffies_64 --oformat $(ld-bfd) +LDFLAGS += -EL +else +ld-bfd := elf32-$(UTS_MACHINE)big-linux +LDFLAGS_vmlinux += --defsym jiffies=jiffies_64+4 --oformat $(ld-bfd) +LDFLAGS += -EB +endif + +export ld-bfd BITS + +head-y := arch/sh/kernel/head_$(BITS).o + +core-y += arch/sh/kernel/ arch/sh/mm/ arch/sh/boards/ +core-$(CONFIG_SH_FPU_EMU) += arch/sh/math-emu/ + +# Mach groups +machdir-$(CONFIG_SOLUTION_ENGINE) += mach-se +machdir-$(CONFIG_SH_HP6XX) += mach-hp6xx +machdir-$(CONFIG_SH_DREAMCAST) += mach-dreamcast +machdir-$(CONFIG_SH_SH03) += mach-sh03 +machdir-$(CONFIG_SH_RTS7751R2D) += mach-r2d +machdir-$(CONFIG_SH_HIGHLANDER) += mach-highlander +machdir-$(CONFIG_SH_MIGOR) += mach-migor +machdir-$(CONFIG_SH_AP325RXA) += mach-ap325rxa +machdir-$(CONFIG_SH_KFR2R09) += mach-kfr2r09 +machdir-$(CONFIG_SH_ECOVEC) += mach-ecovec24 +machdir-$(CONFIG_SH_SDK7780) += mach-sdk7780 +machdir-$(CONFIG_SH_SDK7786) += mach-sdk7786 +machdir-$(CONFIG_SH_X3PROTO) += mach-x3proto +machdir-$(CONFIG_SH_SH7763RDP) += mach-sh7763rdp +machdir-$(CONFIG_SH_SH4202_MICRODEV) += mach-microdev +machdir-$(CONFIG_SH_LANDISK) += mach-landisk +machdir-$(CONFIG_SH_LBOX_RE2) += mach-lboxre2 +machdir-$(CONFIG_SH_CAYMAN) += mach-cayman +machdir-$(CONFIG_SH_RSK) += mach-rsk + +ifneq ($(machdir-y),) +core-y += $(addprefix arch/sh/boards/, \ + $(filter-out ., $(patsubst %,%/,$(machdir-y)))) +endif + +# Common machine type headers. Not part of the arch/sh/boards/ hierarchy. +machdir-y += mach-common + +# Companion chips +core-$(CONFIG_HD6446X_SERIES) += arch/sh/cchips/hd6446x/ + +# +# CPU header paths +# +# These are ordered by optimization level. A CPU family that is a subset +# of another (ie, SH-2A / SH-2), is picked up first, with increasing +# levels of genericness if nothing more suitable is situated in the +# hierarchy. +# +# As an example, in order of preference, SH-2A > SH-2 > common definitions. +# +cpuincdir-$(CONFIG_CPU_SH2A) += cpu-sh2a +cpuincdir-$(CONFIG_CPU_SH2) += cpu-sh2 +cpuincdir-$(CONFIG_CPU_SH3) += cpu-sh3 +cpuincdir-$(CONFIG_CPU_SH4A) += cpu-sh4a +cpuincdir-$(CONFIG_CPU_SH4) += cpu-sh4 +cpuincdir-$(CONFIG_CPU_SH5) += cpu-sh5 +cpuincdir-y += cpu-common # Must be last + +drivers-y += arch/sh/drivers/ +drivers-$(CONFIG_OPROFILE) += arch/sh/oprofile/ + +boot := arch/sh/boot + +cflags-y += $(foreach d, $(cpuincdir-y), -Iarch/sh/include/$(d)) \ + $(foreach d, $(machdir-y), -Iarch/sh/include/$(d)) + +KBUILD_CFLAGS += -pipe $(cflags-y) +KBUILD_CPPFLAGS += $(cflags-y) +KBUILD_AFLAGS += $(cflags-y) + +ifeq ($(CONFIG_MCOUNT),y) + KBUILD_CFLAGS += -pg +endif + +ifeq ($(CONFIG_DWARF_UNWINDER),y) + KBUILD_CFLAGS += -fasynchronous-unwind-tables +endif + +ifeq ($(CONFIG_CC_STACKPROTECTOR),y) + KBUILD_CFLAGS += -fstack-protector +endif + +libs-$(CONFIG_SUPERH32) := arch/sh/lib/ $(libs-y) +libs-$(CONFIG_SUPERH64) := arch/sh/lib64/ $(libs-y) + +BOOT_TARGETS = uImage uImage.bz2 uImage.gz uImage.lzma uImage.xz uImage.lzo \ + uImage.srec uImage.bin zImage vmlinux.bin vmlinux.srec \ + romImage +PHONY += $(BOOT_TARGETS) + +all: $(KBUILD_IMAGE) + +$(BOOT_TARGETS): vmlinux + $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@ + +compressed: zImage + +archprepare: + $(Q)$(MAKE) $(build)=arch/sh/tools include/generated/machtypes.h + +archclean: + $(Q)$(MAKE) $(clean)=$(boot) + $(Q)$(MAKE) $(clean)=arch/sh/kernel/vsyscall + +define archhelp + @echo ' zImage - Compressed kernel image' + @echo ' romImage - Compressed ROM image, if supported' + @echo ' vmlinux.srec - Create an ELF S-record' + @echo ' vmlinux.bin - Create an uncompressed binary image' + @echo '* uImage - Alias to bootable U-Boot image' + @echo ' uImage.srec - Create an S-record for U-Boot' + @echo ' uImage.bin - Kernel-only image for U-Boot (bin)' + @echo '* uImage.gz - Kernel-only image for U-Boot (gzip)' + @echo ' uImage.bz2 - Kernel-only image for U-Boot (bzip2)' + @echo ' uImage.lzma - Kernel-only image for U-Boot (lzma)' + @echo ' uImage.xz - Kernel-only image for U-Boot (xz)' + @echo ' uImage.lzo - Kernel-only image for U-Boot (lzo)' +endef diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig new file mode 100644 index 00000000..fb580574 --- /dev/null +++ b/arch/sh/boards/Kconfig @@ -0,0 +1,382 @@ +menu "Board support" + +config SOLUTION_ENGINE + bool + +config SH_ALPHA_BOARD + bool + +config SH_SOLUTION_ENGINE + bool "SolutionEngine" + select SOLUTION_ENGINE + select CPU_HAS_IPR_IRQ + depends on CPU_SUBTYPE_SH7705 || CPU_SUBTYPE_SH7709 || CPU_SUBTYPE_SH7710 || \ + CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7750S || \ + CPU_SUBTYPE_SH7750R + help + Select SolutionEngine if configuring for a Hitachi SH7705, SH7709, + SH7710, SH7712, SH7750, SH7750S or SH7750R evaluation board. + +config SH_7206_SOLUTION_ENGINE + bool "SolutionEngine7206" + select SOLUTION_ENGINE + depends on CPU_SUBTYPE_SH7206 + help + Select 7206 SolutionEngine if configuring for a Hitachi SH7206 + evaluation board. + +config SH_7619_SOLUTION_ENGINE + bool "SolutionEngine7619" + select SOLUTION_ENGINE + depends on CPU_SUBTYPE_SH7619 + help + Select 7619 SolutionEngine if configuring for a Hitachi SH7619 + evaluation board. + +config SH_7721_SOLUTION_ENGINE + bool "SolutionEngine7721" + select SOLUTION_ENGINE + depends on CPU_SUBTYPE_SH7721 + help + Select 7721 SolutionEngine if configuring for a Hitachi SH7721 + evaluation board. + +config SH_7722_SOLUTION_ENGINE + bool "SolutionEngine7722" + select SOLUTION_ENGINE + select GENERIC_IRQ_CHIP + select IRQ_DOMAIN + depends on CPU_SUBTYPE_SH7722 + help + Select 7722 SolutionEngine if configuring for a Hitachi SH772 + evaluation board. + +config SH_7724_SOLUTION_ENGINE + bool "SolutionEngine7724" + select SOLUTION_ENGINE + depends on CPU_SUBTYPE_SH7724 + select ARCH_REQUIRE_GPIOLIB + select SND_SOC_AK4642 if SND_SIMPLE_CARD + select REGULATOR_FIXED_VOLTAGE if REGULATOR + help + Select 7724 SolutionEngine if configuring for a Hitachi SH7724 + evaluation board. + +config SH_7751_SOLUTION_ENGINE + bool "SolutionEngine7751" + select SOLUTION_ENGINE + select CPU_HAS_IPR_IRQ + depends on CPU_SUBTYPE_SH7751 + help + Select 7751 SolutionEngine if configuring for a Hitachi SH7751 + evaluation board. + +config SH_7780_SOLUTION_ENGINE + bool "SolutionEngine7780" + select SOLUTION_ENGINE + select SYS_SUPPORTS_PCI + depends on CPU_SUBTYPE_SH7780 + help + Select 7780 SolutionEngine if configuring for a Renesas SH7780 + evaluation board. + +config SH_7343_SOLUTION_ENGINE + bool "SolutionEngine7343" + select SOLUTION_ENGINE + select GENERIC_IRQ_CHIP + select IRQ_DOMAIN + depends on CPU_SUBTYPE_SH7343 + help + Select 7343 SolutionEngine if configuring for a Hitachi + SH7343 (SH-Mobile 3AS) evaluation board. + +config SH_HP6XX + bool "HP6XX" + select SYS_SUPPORTS_APM_EMULATION + select HD6446X_SERIES + depends on CPU_SUBTYPE_SH7709 + help + Select HP6XX if configuring for a HP jornada HP6xx. + More information (hardware only) at + . + +config SH_DREAMCAST + bool "Dreamcast" + select SYS_SUPPORTS_PCI + depends on CPU_SUBTYPE_SH7091 + help + Select Dreamcast if configuring for a SEGA Dreamcast. + More information at + +config SH_SH03 + bool "Interface CTP/PCI-SH03" + depends on CPU_SUBTYPE_SH7751 + select CPU_HAS_IPR_IRQ + select SYS_SUPPORTS_PCI + help + CTP/PCI-SH03 is a CPU module computer that is produced + by Interface Corporation. + More information at + +config SH_SECUREEDGE5410 + bool "SecureEdge5410" + depends on CPU_SUBTYPE_SH7751R + select CPU_HAS_IPR_IRQ + select SYS_SUPPORTS_PCI + help + Select SecureEdge5410 if configuring for a SnapGear SH board. + This includes both the OEM SecureEdge products as well as the + SME product line. + +config SH_RTS7751R2D + bool "RTS7751R2D" + depends on CPU_SUBTYPE_SH7751R + select SYS_SUPPORTS_PCI + select IO_TRAPPED if MMU + help + Select RTS7751R2D if configuring for a Renesas Technology + Sales SH-Graphics board. + +config SH_RSK + bool "Renesas Starter Kit" + depends on CPU_SUBTYPE_SH7201 || CPU_SUBTYPE_SH7203 || \ + CPU_SUBTYPE_SH7264 || CPU_SUBTYPE_SH7269 + select REGULATOR_FIXED_VOLTAGE if REGULATOR + help + Select this option if configuring for any of the RSK+ MCU + evaluation platforms. + +config SH_SDK7780 + bool "SDK7780R3" + depends on CPU_SUBTYPE_SH7780 + select SYS_SUPPORTS_PCI + help + Select SDK7780 if configuring for a Renesas SH7780 SDK7780R3 + evaluation board. + +config SH_SDK7786 + bool "SDK7786" + depends on CPU_SUBTYPE_SH7786 + select SYS_SUPPORTS_PCI + select NO_IOPORT if !PCI + select ARCH_WANT_OPTIONAL_GPIOLIB + select HAVE_SRAM_POOL + select REGULATOR_FIXED_VOLTAGE if REGULATOR + help + Select SDK7786 if configuring for a Renesas Technology Europe + SH7786-65nm board. + +config SH_HIGHLANDER + bool "Highlander" + depends on CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785 + select SYS_SUPPORTS_PCI + select IO_TRAPPED if MMU + +config SH_SH7757LCR + bool "SH7757LCR" + depends on CPU_SUBTYPE_SH7757 + select ARCH_REQUIRE_GPIOLIB + select REGULATOR_FIXED_VOLTAGE if REGULATOR + +config SH_SH7785LCR + bool "SH7785LCR" + depends on CPU_SUBTYPE_SH7785 + select SYS_SUPPORTS_PCI + +config SH_SH7785LCR_29BIT_PHYSMAPS + bool "SH7785LCR 29bit physmaps" + depends on SH_SH7785LCR && 29BIT + default y + help + This board has 2 physical memory maps. It can be changed with + DIP switch(S2-5). If you set the DIP switch for S2-5 = ON, + you can access all on-board device in 29bit address mode. + +config SH_SH7785LCR_PT + bool "SH7785LCR prototype board on 32-bit MMU mode" + depends on SH_SH7785LCR && 32BIT + default n + help + If you use prototype board, this option is enabled. + +config SH_URQUELL + bool "Urquell" + depends on CPU_SUBTYPE_SH7786 + select ARCH_REQUIRE_GPIOLIB + select SYS_SUPPORTS_PCI + select NO_IOPORT if !PCI + +config SH_MIGOR + bool "Migo-R" + depends on CPU_SUBTYPE_SH7722 + select ARCH_REQUIRE_GPIOLIB + select REGULATOR_FIXED_VOLTAGE if REGULATOR + help + Select Migo-R if configuring for the SH7722 Migo-R platform + by Renesas System Solutions Asia Pte. Ltd. + +config SH_AP325RXA + bool "AP-325RXA" + depends on CPU_SUBTYPE_SH7723 + select ARCH_REQUIRE_GPIOLIB + select REGULATOR_FIXED_VOLTAGE if REGULATOR + help + Renesas "AP-325RXA" support. + Compatible with ALGO SYSTEM CO.,LTD. "AP-320A" + +config SH_KFR2R09 + bool "KFR2R09" + depends on CPU_SUBTYPE_SH7724 + select ARCH_REQUIRE_GPIOLIB + select REGULATOR_FIXED_VOLTAGE if REGULATOR + help + "Kit For R2R for 2009" support. + +config SH_ECOVEC + bool "EcoVec" + depends on CPU_SUBTYPE_SH7724 + select ARCH_REQUIRE_GPIOLIB + select SND_SOC_DA7210 if SND_SIMPLE_CARD + select REGULATOR_FIXED_VOLTAGE if REGULATOR + help + Renesas "R0P7724LC0011/21RL (EcoVec)" support. + +config SH_SH7763RDP + bool "SH7763RDP" + depends on CPU_SUBTYPE_SH7763 + help + Select SH7763RDP if configuring for a Renesas SH7763 + evaluation board. + +config SH_ESPT + bool "ESPT" + depends on CPU_SUBTYPE_SH7763 + help + Select ESPT if configuring for a Renesas SH7763 + with gigabit ether evaluation board. + +config SH_EDOSK7705 + bool "EDOSK7705" + depends on CPU_SUBTYPE_SH7705 + +config SH_EDOSK7760 + bool "EDOSK7760" + depends on CPU_SUBTYPE_SH7760 + help + Select if configuring for a Renesas EDOSK7760 + evaluation board. + +config SH_SH4202_MICRODEV + bool "SH4-202 MicroDev" + depends on CPU_SUBTYPE_SH4_202 + help + Select SH4-202 MicroDev if configuring for a SuperH MicroDev board + with an SH4-202 CPU. + +config SH_LANDISK + bool "LANDISK" + depends on CPU_SUBTYPE_SH7751R + select SYS_SUPPORTS_PCI + help + I-O DATA DEVICE, INC. "LANDISK Series" support. + +config SH_TITAN + bool "TITAN" + depends on CPU_SUBTYPE_SH7751R + select CPU_HAS_IPR_IRQ + select SYS_SUPPORTS_PCI + help + Select Titan if you are configuring for a Nimble Microsystems + NetEngine NP51R. + +config SH_SHMIN + bool "SHMIN" + depends on CPU_SUBTYPE_SH7706 + select CPU_HAS_IPR_IRQ + help + Select SHMIN if configuring for the SHMIN board. + +config SH_LBOX_RE2 + bool "L-BOX RE2" + depends on CPU_SUBTYPE_SH7751R + select SYS_SUPPORTS_PCI + help + Select L-BOX RE2 if configuring for the NTT COMWARE L-BOX RE2. + +config SH_X3PROTO + bool "SH-X3 Prototype board" + depends on CPU_SUBTYPE_SHX3 + select NO_IOPORT if !PCI + select IRQ_DOMAIN + +config SH_MAGIC_PANEL_R2 + bool "Magic Panel R2" + depends on CPU_SUBTYPE_SH7720 + select ARCH_REQUIRE_GPIOLIB + select REGULATOR_FIXED_VOLTAGE if REGULATOR + help + Select Magic Panel R2 if configuring for Magic Panel R2. + +config SH_CAYMAN + bool "Hitachi Cayman" + depends on CPU_SUBTYPE_SH5_101 || CPU_SUBTYPE_SH5_103 + select SYS_SUPPORTS_PCI + +config SH_POLARIS + bool "SMSC Polaris" + select CPU_HAS_IPR_IRQ + select REGULATOR_FIXED_VOLTAGE if REGULATOR + depends on CPU_SUBTYPE_SH7709 + help + Select if configuring for an SMSC Polaris development board + +config SH_SH2007 + bool "SH-2007 board" + select NO_IOPORT + select REGULATOR_FIXED_VOLTAGE if REGULATOR + depends on CPU_SUBTYPE_SH7780 + help + SH-2007 is a single-board computer based around SH7780 chip + intended for embedded applications. + It has an Ethernet interface (SMC9118), direct connected + Compact Flash socket, two serial ports and PC-104 bus. + More information at . + +config SH_APSH4A3A + bool "AP-SH4A-3A" + select SH_ALPHA_BOARD + select REGULATOR_FIXED_VOLTAGE if REGULATOR + depends on CPU_SUBTYPE_SH7785 + help + Select AP-SH4A-3A if configuring for an ALPHAPROJECT AP-SH4A-3A. + +config SH_APSH4AD0A + bool "AP-SH4AD-0A" + select SH_ALPHA_BOARD + select SYS_SUPPORTS_PCI + select REGULATOR_FIXED_VOLTAGE if REGULATOR + depends on CPU_SUBTYPE_SH7786 + help + Select AP-SH4AD-0A if configuring for an ALPHAPROJECT AP-SH4AD-0A. + +source "arch/sh/boards/mach-r2d/Kconfig" +source "arch/sh/boards/mach-highlander/Kconfig" +source "arch/sh/boards/mach-sdk7780/Kconfig" +source "arch/sh/boards/mach-migor/Kconfig" +source "arch/sh/boards/mach-rsk/Kconfig" + +if SH_MAGIC_PANEL_R2 + +menu "Magic Panel R2 options" + +config SH_MAGIC_PANEL_R2_VERSION + int SH_MAGIC_PANEL_R2_VERSION + default "3" + help + Set the version of the Magic Panel R2 + +endmenu + +endif + +endmenu diff --git a/arch/sh/boards/Makefile b/arch/sh/boards/Makefile new file mode 100644 index 00000000..975a0f64 --- /dev/null +++ b/arch/sh/boards/Makefile @@ -0,0 +1,17 @@ +# +# Specific board support, not covered by a mach group. +# +obj-$(CONFIG_SH_MAGIC_PANEL_R2) += board-magicpanelr2.o +obj-$(CONFIG_SH_SECUREEDGE5410) += board-secureedge5410.o +obj-$(CONFIG_SH_SH2007) += board-sh2007.o +obj-$(CONFIG_SH_SH7785LCR) += board-sh7785lcr.o +obj-$(CONFIG_SH_URQUELL) += board-urquell.o +obj-$(CONFIG_SH_SHMIN) += board-shmin.o +obj-$(CONFIG_SH_EDOSK7705) += board-edosk7705.o +obj-$(CONFIG_SH_EDOSK7760) += board-edosk7760.o +obj-$(CONFIG_SH_ESPT) += board-espt.o +obj-$(CONFIG_SH_POLARIS) += board-polaris.o +obj-$(CONFIG_SH_TITAN) += board-titan.o +obj-$(CONFIG_SH_SH7757LCR) += board-sh7757lcr.o +obj-$(CONFIG_SH_APSH4A3A) += board-apsh4a3a.o +obj-$(CONFIG_SH_APSH4AD0A) += board-apsh4ad0a.o diff --git a/arch/sh/boards/board-apsh4a3a.c b/arch/sh/boards/board-apsh4a3a.c new file mode 100644 index 00000000..0a39c241 --- /dev/null +++ b/arch/sh/boards/board-apsh4a3a.c @@ -0,0 +1,185 @@ +/* + * ALPHAPROJECT AP-SH4A-3A Support. + * + * Copyright (C) 2010 ALPHAPROJECT Co.,Ltd. + * Copyright (C) 2008 Yoshihiro Shimoda + * Copyright (C) 2009 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct mtd_partition nor_flash_partitions[] = { + { + .name = "loader", + .offset = 0x00000000, + .size = 512 * 1024, + }, + { + .name = "bootenv", + .offset = MTDPART_OFS_APPEND, + .size = 512 * 1024, + }, + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = 4 * 1024 * 1024, + }, + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data nor_flash_data = { + .width = 4, + .parts = nor_flash_partitions, + .nr_parts = ARRAY_SIZE(nor_flash_partitions), +}; + +static struct resource nor_flash_resources[] = { + [0] = { + .start = 0x00000000, + .end = 0x01000000 - 1, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device nor_flash_device = { + .name = "physmap-flash", + .dev = { + .platform_data = &nor_flash_data, + }, + .num_resources = ARRAY_SIZE(nor_flash_resources), + .resource = nor_flash_resources, +}; + +/* Dummy supplies, where voltage doesn't matter */ +static struct regulator_consumer_supply dummy_supplies[] = { + REGULATOR_SUPPLY("vddvario", "smsc911x"), + REGULATOR_SUPPLY("vdd33a", "smsc911x"), +}; + +static struct resource smsc911x_resources[] = { + [0] = { + .name = "smsc911x-memory", + .start = 0xA4000000, + .end = 0xA4000000 + SZ_256 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .name = "smsc911x-irq", + .start = evt2irq(0x200), + .end = evt2irq(0x200), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct smsc911x_platform_config smsc911x_config = { + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, + .flags = SMSC911X_USE_16BIT, + .phy_interface = PHY_INTERFACE_MODE_MII, +}; + +static struct platform_device smsc911x_device = { + .name = "smsc911x", + .id = -1, + .num_resources = ARRAY_SIZE(smsc911x_resources), + .resource = smsc911x_resources, + .dev = { + .platform_data = &smsc911x_config, + }, +}; + +static struct platform_device *apsh4a3a_devices[] __initdata = { + &nor_flash_device, + &smsc911x_device, +}; + +static int __init apsh4a3a_devices_setup(void) +{ + regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); + + return platform_add_devices(apsh4a3a_devices, + ARRAY_SIZE(apsh4a3a_devices)); +} +device_initcall(apsh4a3a_devices_setup); + +static int apsh4a3a_clk_init(void) +{ + struct clk *clk; + int ret; + + clk = clk_get(NULL, "extal"); + if (IS_ERR(clk)) + return PTR_ERR(clk); + ret = clk_set_rate(clk, 33333000); + clk_put(clk); + + return ret; +} + +/* Initialize the board */ +static void __init apsh4a3a_setup(char **cmdline_p) +{ + printk(KERN_INFO "Alpha Project AP-SH4A-3A support:\n"); +} + +static void __init apsh4a3a_init_irq(void) +{ + plat_irq_setup_pins(IRQ_MODE_IRQ7654); +} + +/* Return the board specific boot mode pin configuration */ +static int apsh4a3a_mode_pins(void) +{ + int value = 0; + + /* These are the factory default settings of SW1 and SW2. + * If you change these dip switches then you will need to + * adjust the values below as well. + */ + value &= ~MODE_PIN0; /* Clock Mode 16 */ + value &= ~MODE_PIN1; + value &= ~MODE_PIN2; + value &= ~MODE_PIN3; + value |= MODE_PIN4; + value &= ~MODE_PIN5; /* 16-bit Area0 bus width */ + value |= MODE_PIN6; /* Area 0 SRAM interface */ + value |= MODE_PIN7; + value |= MODE_PIN8; /* Little Endian */ + value |= MODE_PIN9; /* Master Mode */ + value |= MODE_PIN10; /* Crystal resonator */ + value |= MODE_PIN11; /* Display Unit */ + value |= MODE_PIN12; + value &= ~MODE_PIN13; /* 29-bit address mode */ + value |= MODE_PIN14; /* No PLL step-up */ + + return value; +} + +/* + * The Machine Vector + */ +static struct sh_machine_vector mv_apsh4a3a __initmv = { + .mv_name = "AP-SH4A-3A", + .mv_setup = apsh4a3a_setup, + .mv_clk_init = apsh4a3a_clk_init, + .mv_init_irq = apsh4a3a_init_irq, + .mv_mode_pins = apsh4a3a_mode_pins, +}; diff --git a/arch/sh/boards/board-apsh4ad0a.c b/arch/sh/boards/board-apsh4ad0a.c new file mode 100644 index 00000000..92eac3a9 --- /dev/null +++ b/arch/sh/boards/board-apsh4ad0a.c @@ -0,0 +1,135 @@ +/* + * ALPHAPROJECT AP-SH4AD-0A Support. + * + * Copyright (C) 2010 ALPHAPROJECT Co.,Ltd. + * Copyright (C) 2010 Matt Fleming + * Copyright (C) 2010 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Dummy supplies, where voltage doesn't matter */ +static struct regulator_consumer_supply dummy_supplies[] = { + REGULATOR_SUPPLY("vddvario", "smsc911x"), + REGULATOR_SUPPLY("vdd33a", "smsc911x"), +}; + +static struct resource smsc911x_resources[] = { + [0] = { + .name = "smsc911x-memory", + .start = 0xA4000000, + .end = 0xA4000000 + SZ_256 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .name = "smsc911x-irq", + .start = evt2irq(0x200), + .end = evt2irq(0x200), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct smsc911x_platform_config smsc911x_config = { + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, + .flags = SMSC911X_USE_16BIT, + .phy_interface = PHY_INTERFACE_MODE_MII, +}; + +static struct platform_device smsc911x_device = { + .name = "smsc911x", + .id = -1, + .num_resources = ARRAY_SIZE(smsc911x_resources), + .resource = smsc911x_resources, + .dev = { + .platform_data = &smsc911x_config, + }, +}; + +static struct platform_device *apsh4ad0a_devices[] __initdata = { + &smsc911x_device, +}; + +static int __init apsh4ad0a_devices_setup(void) +{ + regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); + + return platform_add_devices(apsh4ad0a_devices, + ARRAY_SIZE(apsh4ad0a_devices)); +} +device_initcall(apsh4ad0a_devices_setup); + +static int apsh4ad0a_mode_pins(void) +{ + int value = 0; + + /* These are the factory default settings of SW1 and SW2. + * If you change these dip switches then you will need to + * adjust the values below as well. + */ + value |= MODE_PIN0; /* Clock Mode 3 */ + value |= MODE_PIN1; + value &= ~MODE_PIN2; + value &= ~MODE_PIN3; + value &= ~MODE_PIN4; /* 16-bit Area0 bus width */ + value |= MODE_PIN5; + value |= MODE_PIN6; + value |= MODE_PIN7; /* Normal mode */ + value |= MODE_PIN8; /* Little Endian */ + value |= MODE_PIN9; /* Crystal resonator */ + value &= ~MODE_PIN10; /* 29-bit address mode */ + value &= ~MODE_PIN11; /* PCI-E Root port */ + value &= ~MODE_PIN12; /* 4 lane + 1 lane */ + value |= MODE_PIN13; /* AUD Enable */ + value &= ~MODE_PIN14; /* Normal Operation */ + + return value; +} + +static int apsh4ad0a_clk_init(void) +{ + struct clk *clk; + int ret; + + clk = clk_get(NULL, "extal"); + if (IS_ERR(clk)) + return PTR_ERR(clk); + ret = clk_set_rate(clk, 33333000); + clk_put(clk); + + return ret; +} + +/* Initialize the board */ +static void __init apsh4ad0a_setup(char **cmdline_p) +{ + pr_info("Alpha Project AP-SH4AD-0A support:\n"); +} + +static void __init apsh4ad0a_init_irq(void) +{ + plat_irq_setup_pins(IRQ_MODE_IRQ3210); +} + +/* + * The Machine Vector + */ +static struct sh_machine_vector mv_apsh4ad0a __initmv = { + .mv_name = "AP-SH4AD-0A", + .mv_setup = apsh4ad0a_setup, + .mv_mode_pins = apsh4ad0a_mode_pins, + .mv_clk_init = apsh4ad0a_clk_init, + .mv_init_irq = apsh4ad0a_init_irq, +}; diff --git a/arch/sh/boards/board-edosk7705.c b/arch/sh/boards/board-edosk7705.c new file mode 100644 index 00000000..5e24c17b --- /dev/null +++ b/arch/sh/boards/board-edosk7705.c @@ -0,0 +1,78 @@ +/* + * arch/sh/boards/renesas/edosk7705/setup.c + * + * Copyright (C) 2000 Kazumoto Kojima + * + * Hitachi SolutionEngine Support. + * + * Modified for edosk7705 development + * board by S. Dunn, 2003. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#define SMC_IOBASE 0xA2000000 +#define SMC_IO_OFFSET 0x300 +#define SMC_IOADDR (SMC_IOBASE + SMC_IO_OFFSET) + +#define ETHERNET_IRQ evt2irq(0x320) + +static void __init sh_edosk7705_init_irq(void) +{ + make_imask_irq(ETHERNET_IRQ); +} + +/* eth initialization functions */ +static struct smc91x_platdata smc91x_info = { + .flags = SMC91X_USE_16BIT | SMC91X_IO_SHIFT_1 | IORESOURCE_IRQ_LOWLEVEL, +}; + +static struct resource smc91x_res[] = { + [0] = { + .start = SMC_IOADDR, + .end = SMC_IOADDR + SZ_32 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = ETHERNET_IRQ, + .end = ETHERNET_IRQ, + .flags = IORESOURCE_IRQ , + } +}; + +static struct platform_device smc91x_dev = { + .name = "smc91x", + .id = -1, + .num_resources = ARRAY_SIZE(smc91x_res), + .resource = smc91x_res, + + .dev = { + .platform_data = &smc91x_info, + }, +}; + +/* platform init code */ +static struct platform_device *edosk7705_devices[] __initdata = { + &smc91x_dev, +}; + +static int __init init_edosk7705_devices(void) +{ + return platform_add_devices(edosk7705_devices, + ARRAY_SIZE(edosk7705_devices)); +} +device_initcall(init_edosk7705_devices); + +/* + * The Machine Vector + */ +static struct sh_machine_vector mv_edosk7705 __initmv = { + .mv_name = "EDOSK7705", + .mv_init_irq = sh_edosk7705_init_irq, +}; diff --git a/arch/sh/boards/board-edosk7760.c b/arch/sh/boards/board-edosk7760.c new file mode 100644 index 00000000..bab5b951 --- /dev/null +++ b/arch/sh/boards/board-edosk7760.c @@ -0,0 +1,191 @@ +/* + * Renesas Europe EDOSK7760 Board Support + * + * Copyright (C) 2008 SPES Societa' Progettazione Elettronica e Software Ltd. + * Author: Luca Santini + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Bus state controller registers for CS4 area */ +#define BSC_CS4BCR 0xA4FD0010 +#define BSC_CS4WCR 0xA4FD0030 + +#define SMC_IOBASE 0xA2000000 +#define SMC_IO_OFFSET 0x300 +#define SMC_IOADDR (SMC_IOBASE + SMC_IO_OFFSET) + +/* NOR flash */ +static struct mtd_partition edosk7760_nor_flash_partitions[] = { + { + .name = "bootloader", + .offset = 0, + .size = SZ_256K, + .mask_flags = MTD_WRITEABLE, /* Read-only */ + }, { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = SZ_2M, + }, { + .name = "fs", + .offset = MTDPART_OFS_APPEND, + .size = (26 << 20), + }, { + .name = "other", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data edosk7760_nor_flash_data = { + .width = 4, + .parts = edosk7760_nor_flash_partitions, + .nr_parts = ARRAY_SIZE(edosk7760_nor_flash_partitions), +}; + +static struct resource edosk7760_nor_flash_resources[] = { + [0] = { + .name = "NOR Flash", + .start = 0x00000000, + .end = 0x00000000 + SZ_32M - 1, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device edosk7760_nor_flash_device = { + .name = "physmap-flash", + .resource = edosk7760_nor_flash_resources, + .num_resources = ARRAY_SIZE(edosk7760_nor_flash_resources), + .dev = { + .platform_data = &edosk7760_nor_flash_data, + }, +}; + +/* i2c initialization functions */ +static struct sh7760_i2c_platdata i2c_pd = { + .speed_khz = 400, +}; + +static struct resource sh7760_i2c1_res[] = { + { + .start = SH7760_I2C1_MMIO, + .end = SH7760_I2C1_MMIOEND, + .flags = IORESOURCE_MEM, + },{ + .start = evt2irq(0x9e0), + .end = evt2irq(0x9e0), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device sh7760_i2c1_dev = { + .dev = { + .platform_data = &i2c_pd, + }, + + .name = SH7760_I2C_DEVNAME, + .id = 1, + .resource = sh7760_i2c1_res, + .num_resources = ARRAY_SIZE(sh7760_i2c1_res), +}; + +static struct resource sh7760_i2c0_res[] = { + { + .start = SH7760_I2C0_MMIO, + .end = SH7760_I2C0_MMIOEND, + .flags = IORESOURCE_MEM, + }, { + .start = evt2irq(0x9c0), + .end = evt2irq(0x9c0), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device sh7760_i2c0_dev = { + .dev = { + .platform_data = &i2c_pd, + }, + .name = SH7760_I2C_DEVNAME, + .id = 0, + .resource = sh7760_i2c0_res, + .num_resources = ARRAY_SIZE(sh7760_i2c0_res), +}; + +/* eth initialization functions */ +static struct smc91x_platdata smc91x_info = { + .flags = SMC91X_USE_16BIT | SMC91X_IO_SHIFT_1 | IORESOURCE_IRQ_LOWLEVEL, +}; + +static struct resource smc91x_res[] = { + [0] = { + .start = SMC_IOADDR, + .end = SMC_IOADDR + SZ_32 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x2a0), + .end = evt2irq(0x2a0), + .flags = IORESOURCE_IRQ , + } +}; + +static struct platform_device smc91x_dev = { + .name = "smc91x", + .id = -1, + .num_resources = ARRAY_SIZE(smc91x_res), + .resource = smc91x_res, + + .dev = { + .platform_data = &smc91x_info, + }, +}; + +/* platform init code */ +static struct platform_device *edosk7760_devices[] __initdata = { + &smc91x_dev, + &edosk7760_nor_flash_device, + &sh7760_i2c0_dev, + &sh7760_i2c1_dev, +}; + +static int __init init_edosk7760_devices(void) +{ + plat_irq_setup_pins(IRQ_MODE_IRQ); + + return platform_add_devices(edosk7760_devices, + ARRAY_SIZE(edosk7760_devices)); +} +device_initcall(init_edosk7760_devices); + +/* + * The Machine Vector + */ +struct sh_machine_vector mv_edosk7760 __initmv = { + .mv_name = "EDOSK7760", +}; diff --git a/arch/sh/boards/board-espt.c b/arch/sh/boards/board-espt.c new file mode 100644 index 00000000..d71a0bcf --- /dev/null +++ b/arch/sh/boards/board-espt.c @@ -0,0 +1,110 @@ +/* + * Data Technology Inc. ESPT-GIGA board support + * + * Copyright (C) 2008, 2009 Renesas Solutions Corp. + * Copyright (C) 2008, 2009 Nobuhiro Iwamatsu + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* NOR Flash */ +static struct mtd_partition espt_nor_flash_partitions[] = { + { + .name = "U-Boot", + .offset = 0, + .size = (2 * SZ_128K), + .mask_flags = MTD_WRITEABLE, /* Read-only */ + }, { + .name = "Linux-Kernel", + .offset = MTDPART_OFS_APPEND, + .size = (20 * SZ_128K), + }, { + .name = "Root Filesystem", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data espt_nor_flash_data = { + .width = 2, + .parts = espt_nor_flash_partitions, + .nr_parts = ARRAY_SIZE(espt_nor_flash_partitions), +}; + +static struct resource espt_nor_flash_resources[] = { + [0] = { + .name = "NOR Flash", + .start = 0, + .end = SZ_8M - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device espt_nor_flash_device = { + .name = "physmap-flash", + .resource = espt_nor_flash_resources, + .num_resources = ARRAY_SIZE(espt_nor_flash_resources), + .dev = { + .platform_data = &espt_nor_flash_data, + }, +}; + +/* SH-Ether */ +static struct resource sh_eth_resources[] = { + { + .start = 0xFEE00800, /* use eth1 */ + .end = 0xFEE00F7C - 1, + .flags = IORESOURCE_MEM, + }, { + .start = 0xFEE01800, /* TSU */ + .end = 0xFEE01FFF, + .flags = IORESOURCE_MEM, + }, { + + .start = evt2irq(0x920), /* irq number */ + .flags = IORESOURCE_IRQ, + }, +}; + +static struct sh_eth_plat_data sh7763_eth_pdata = { + .phy = 0, + .edmac_endian = EDMAC_LITTLE_ENDIAN, + .register_type = SH_ETH_REG_GIGABIT, + .phy_interface = PHY_INTERFACE_MODE_MII, +}; + +static struct platform_device espt_eth_device = { + .name = "sh-eth", + .resource = sh_eth_resources, + .num_resources = ARRAY_SIZE(sh_eth_resources), + .dev = { + .platform_data = &sh7763_eth_pdata, + }, +}; + +static struct platform_device *espt_devices[] __initdata = { + &espt_nor_flash_device, + &espt_eth_device, +}; + +static int __init espt_devices_setup(void) +{ + return platform_add_devices(espt_devices, + ARRAY_SIZE(espt_devices)); +} +device_initcall(espt_devices_setup); + +static struct sh_machine_vector mv_espt __initmv = { + .mv_name = "ESPT-GIGA", +}; diff --git a/arch/sh/boards/board-magicpanelr2.c b/arch/sh/boards/board-magicpanelr2.c new file mode 100644 index 00000000..20500858 --- /dev/null +++ b/arch/sh/boards/board-magicpanelr2.c @@ -0,0 +1,393 @@ +/* + * linux/arch/sh/boards/magicpanel/setup.c + * + * Copyright (C) 2007 Markus Brunner, Mark Jonas + * + * Magic Panel Release 2 board setup + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Dummy supplies, where voltage doesn't matter */ +static struct regulator_consumer_supply dummy_supplies[] = { + REGULATOR_SUPPLY("vddvario", "smsc911x"), + REGULATOR_SUPPLY("vdd33a", "smsc911x"), +}; + +#define LAN9115_READY (__raw_readl(0xA8000084UL) & 0x00000001UL) + +/* Wait until reset finished. Timeout is 100ms. */ +static int __init ethernet_reset_finished(void) +{ + int i; + + if (LAN9115_READY) + return 1; + + for (i = 0; i < 10; ++i) { + mdelay(10); + if (LAN9115_READY) + return 1; + } + + return 0; +} + +static void __init reset_ethernet(void) +{ + /* PMDR: LAN_RESET=on */ + CLRBITS_OUTB(0x10, PORT_PMDR); + + udelay(200); + + /* PMDR: LAN_RESET=off */ + SETBITS_OUTB(0x10, PORT_PMDR); +} + +static void __init setup_chip_select(void) +{ + /* CS2: LAN (0x08000000 - 0x0bffffff) */ + /* no idle cycles, normal space, 8 bit data bus */ + __raw_writel(0x36db0400, CS2BCR); + /* (SW:1.5 WR:3 HW:1.5), ext. wait */ + __raw_writel(0x000003c0, CS2WCR); + + /* CS4: CAN1 (0xb0000000 - 0xb3ffffff) */ + /* no idle cycles, normal space, 8 bit data bus */ + __raw_writel(0x00000200, CS4BCR); + /* (SW:1.5 WR:3 HW:1.5), ext. wait */ + __raw_writel(0x00100981, CS4WCR); + + /* CS5a: CAN2 (0xb4000000 - 0xb5ffffff) */ + /* no idle cycles, normal space, 8 bit data bus */ + __raw_writel(0x00000200, CS5ABCR); + /* (SW:1.5 WR:3 HW:1.5), ext. wait */ + __raw_writel(0x00100981, CS5AWCR); + + /* CS5b: CAN3 (0xb6000000 - 0xb7ffffff) */ + /* no idle cycles, normal space, 8 bit data bus */ + __raw_writel(0x00000200, CS5BBCR); + /* (SW:1.5 WR:3 HW:1.5), ext. wait */ + __raw_writel(0x00100981, CS5BWCR); + + /* CS6a: Rotary (0xb8000000 - 0xb9ffffff) */ + /* no idle cycles, normal space, 8 bit data bus */ + __raw_writel(0x00000200, CS6ABCR); + /* (SW:1.5 WR:3 HW:1.5), no ext. wait */ + __raw_writel(0x001009C1, CS6AWCR); +} + +static void __init setup_port_multiplexing(void) +{ + /* A7 GPO(LED8); A6 GPO(LED7); A5 GPO(LED6); A4 GPO(LED5); + * A3 GPO(LED4); A2 GPO(LED3); A1 GPO(LED2); A0 GPO(LED1); + */ + __raw_writew(0x5555, PORT_PACR); /* 01 01 01 01 01 01 01 01 */ + + /* B7 GPO(RST4); B6 GPO(RST3); B5 GPO(RST2); B4 GPO(RST1); + * B3 GPO(PB3); B2 GPO(PB2); B1 GPO(PB1); B0 GPO(PB0); + */ + __raw_writew(0x5555, PORT_PBCR); /* 01 01 01 01 01 01 01 01 */ + + /* C7 GPO(PC7); C6 GPO(PC6); C5 GPO(PC5); C4 GPO(PC4); + * C3 LCD_DATA3; C2 LCD_DATA2; C1 LCD_DATA1; C0 LCD_DATA0; + */ + __raw_writew(0x5500, PORT_PCCR); /* 01 01 01 01 00 00 00 00 */ + + /* D7 GPO(PD7); D6 GPO(PD6); D5 GPO(PD5); D4 GPO(PD4); + * D3 GPO(PD3); D2 GPO(PD2); D1 GPO(PD1); D0 GPO(PD0); + */ + __raw_writew(0x5555, PORT_PDCR); /* 01 01 01 01 01 01 01 01 */ + + /* E7 (x); E6 GPI(nu); E5 GPI(nu); E4 LCD_M_DISP; + * E3 LCD_CL1; E2 LCD_CL2; E1 LCD_DON; E0 LCD_FLM; + */ + __raw_writew(0x3C00, PORT_PECR); /* 00 11 11 00 00 00 00 00 */ + + /* F7 (x); F6 DA1(VLCD); F5 DA0(nc); F4 AN3; + * F3 AN2(MID_AD); F2 AN1(EARTH_AD); F1 AN0(TEMP); F0 GPI+(nc); + */ + __raw_writew(0x0002, PORT_PFCR); /* 00 00 00 00 00 00 00 10 */ + + /* G7 (x); G6 IRQ5(TOUCH_BUSY); G5 IRQ4(TOUCH_IRQ); G4 GPI(KEY2); + * G3 GPI(KEY1); G2 GPO(LED11); G1 GPO(LED10); G0 GPO(LED9); + */ + __raw_writew(0x03D5, PORT_PGCR); /* 00 00 00 11 11 01 01 01 */ + + /* H7 (x); H6 /RAS(BRAS); H5 /CAS(BCAS); H4 CKE(BCKE); + * H3 GPO(EARTH_OFF); H2 GPO(EARTH_TEST); H1 USB2_PWR; H0 USB1_PWR; + */ + __raw_writew(0x0050, PORT_PHCR); /* 00 00 00 00 01 01 00 00 */ + + /* J7 (x); J6 AUDCK; J5 ASEBRKAK; J4 AUDATA3; + * J3 AUDATA2; J2 AUDATA1; J1 AUDATA0; J0 AUDSYNC; + */ + __raw_writew(0x0000, PORT_PJCR); /* 00 00 00 00 00 00 00 00 */ + + /* K7 (x); K6 (x); K5 (x); K4 (x); + * K3 PINT7(/PWR2); K2 PINT6(/PWR1); K1 PINT5(nu); K0 PINT4(FLASH_READY) + */ + __raw_writew(0x00FF, PORT_PKCR); /* 00 00 00 00 11 11 11 11 */ + + /* L7 TRST; L6 TMS; L5 TDO; L4 TDI; + * L3 TCK; L2 (x); L1 (x); L0 (x); + */ + __raw_writew(0x0000, PORT_PLCR); /* 00 00 00 00 00 00 00 00 */ + + /* M7 GPO(CURRENT_SINK); M6 GPO(PWR_SWITCH); M5 GPO(LAN_SPEED); + * M4 GPO(LAN_RESET); M3 GPO(BUZZER); M2 GPO(LCD_BL); + * M1 CS5B(CAN3_CS); M0 GPI+(nc); + */ + __raw_writew(0x5552, PORT_PMCR); /* 01 01 01 01 01 01 00 10 */ + + /* CURRENT_SINK=off, PWR_SWITCH=off, LAN_SPEED=100MBit, + * LAN_RESET=off, BUZZER=off, LCD_BL=off + */ +#if CONFIG_SH_MAGIC_PANEL_R2_VERSION == 2 + __raw_writeb(0x30, PORT_PMDR); +#elif CONFIG_SH_MAGIC_PANEL_R2_VERSION == 3 + __raw_writeb(0xF0, PORT_PMDR); +#else +#error Unknown revision of PLATFORM_MP_R2 +#endif + + /* P7 (x); P6 (x); P5 (x); + * P4 GPO(nu); P3 IRQ3(LAN_IRQ); P2 IRQ2(CAN3_IRQ); + * P1 IRQ1(CAN2_IRQ); P0 IRQ0(CAN1_IRQ) + */ + __raw_writew(0x0100, PORT_PPCR); /* 00 00 00 01 00 00 00 00 */ + __raw_writeb(0x10, PORT_PPDR); + + /* R7 A25; R6 A24; R5 A23; R4 A22; + * R3 A21; R2 A20; R1 A19; R0 A0; + */ + gpio_request(GPIO_FN_A25, NULL); + gpio_request(GPIO_FN_A24, NULL); + gpio_request(GPIO_FN_A23, NULL); + gpio_request(GPIO_FN_A22, NULL); + gpio_request(GPIO_FN_A21, NULL); + gpio_request(GPIO_FN_A20, NULL); + gpio_request(GPIO_FN_A19, NULL); + gpio_request(GPIO_FN_A0, NULL); + + /* S7 (x); S6 (x); S5 (x); S4 GPO(EEPROM_CS2); + * S3 GPO(EEPROM_CS1); S2 SIOF0_TXD; S1 SIOF0_RXD; S0 SIOF0_SCK; + */ + __raw_writew(0x0140, PORT_PSCR); /* 00 00 00 01 01 00 00 00 */ + + /* T7 (x); T6 (x); T5 (x); T4 COM1_CTS; + * T3 COM1_RTS; T2 COM1_TXD; T1 COM1_RXD; T0 GPO(WDOG) + */ + __raw_writew(0x0001, PORT_PTCR); /* 00 00 00 00 00 00 00 01 */ + + /* U7 (x); U6 (x); U5 (x); U4 GPI+(/AC_FAULT); + * U3 GPO(TOUCH_CS); U2 TOUCH_TXD; U1 TOUCH_RXD; U0 TOUCH_SCK; + */ + __raw_writew(0x0240, PORT_PUCR); /* 00 00 00 10 01 00 00 00 */ + + /* V7 (x); V6 (x); V5 (x); V4 GPO(MID2); + * V3 GPO(MID1); V2 CARD_TxD; V1 CARD_RxD; V0 GPI+(/BAT_FAULT); + */ + __raw_writew(0x0142, PORT_PVCR); /* 00 00 00 01 01 00 00 10 */ +} + +static void __init mpr2_setup(char **cmdline_p) +{ + /* set Pin Select Register A: + * /PCC_CD1, /PCC_CD2, PCC_BVD1, PCC_BVD2, + * /IOIS16, IRQ4, IRQ5, USB1d_SUSPEND + */ + __raw_writew(0xAABC, PORT_PSELA); + /* set Pin Select Register B: + * /SCIF0_RTS, /SCIF0_CTS, LCD_VCPWC, + * LCD_VEPWC, IIC_SDA, IIC_SCL, Reserved + */ + __raw_writew(0x3C00, PORT_PSELB); + /* set Pin Select Register C: + * SIOF1_SCK, SIOF1_RxD, SCIF1_RxD, SCIF1_TxD, Reserved + */ + __raw_writew(0x0000, PORT_PSELC); + /* set Pin Select Register D: Reserved, SIOF1_TxD, Reserved, SIOF1_MCLK, + * Reserved, SIOF1_SYNC, Reserved, SCIF1_SCK, Reserved + */ + __raw_writew(0x0000, PORT_PSELD); + /* set USB TxRx Control: Reserved, DRV, Reserved, USB_TRANS, USB_SEL */ + __raw_writew(0x0101, PORT_UTRCTL); + /* set USB Clock Control: USSCS, USSTB, Reserved (HighByte always A5) */ + __raw_writew(0xA5C0, PORT_UCLKCR_W); + + setup_chip_select(); + + setup_port_multiplexing(); + + reset_ethernet(); + + printk(KERN_INFO "Magic Panel Release 2 A.%i\n", + CONFIG_SH_MAGIC_PANEL_R2_VERSION); + + if (ethernet_reset_finished() == 0) + printk(KERN_WARNING "Ethernet not ready\n"); +} + +static struct resource smsc911x_resources[] = { + [0] = { + .start = 0xa8000000, + .end = 0xabffffff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x660), + .end = evt2irq(0x660), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct smsc911x_platform_config smsc911x_config = { + .phy_interface = PHY_INTERFACE_MODE_MII, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, + .flags = SMSC911X_USE_32BIT, +}; + +static struct platform_device smsc911x_device = { + .name = "smsc911x", + .id = -1, + .num_resources = ARRAY_SIZE(smsc911x_resources), + .resource = smsc911x_resources, + .dev = { + .platform_data = &smsc911x_config, + }, +}; + +static struct resource heartbeat_resources[] = { + [0] = { + .start = PA_LED, + .end = PA_LED, + .flags = IORESOURCE_MEM, + }, +}; + +static struct heartbeat_data heartbeat_data = { + .flags = HEARTBEAT_INVERTED, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .dev = { + .platform_data = &heartbeat_data, + }, + .num_resources = ARRAY_SIZE(heartbeat_resources), + .resource = heartbeat_resources, +}; + +static struct mtd_partition mpr2_partitions[] = { + /* Reserved for bootloader, read-only */ + { + .name = "Bootloader", + .offset = 0x00000000UL, + .size = MPR2_MTD_BOOTLOADER_SIZE, + .mask_flags = MTD_WRITEABLE, + }, + /* Reserved for kernel image */ + { + .name = "Kernel", + .offset = MTDPART_OFS_NXTBLK, + .size = MPR2_MTD_KERNEL_SIZE, + }, + /* Rest is used for Flash FS */ + { + .name = "Flash_FS", + .offset = MTDPART_OFS_NXTBLK, + .size = MTDPART_SIZ_FULL, + } +}; + +static struct physmap_flash_data flash_data = { + .parts = mpr2_partitions, + .nr_parts = ARRAY_SIZE(mpr2_partitions), + .width = 2, +}; + +static struct resource flash_resource = { + .start = 0x00000000, + .end = 0x2000000UL, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device flash_device = { + .name = "physmap-flash", + .id = -1, + .resource = &flash_resource, + .num_resources = 1, + .dev = { + .platform_data = &flash_data, + }, +}; + +/* + * Add all resources to the platform_device + */ + +static struct platform_device *mpr2_devices[] __initdata = { + &heartbeat_device, + &smsc911x_device, + &flash_device, +}; + + +static int __init mpr2_devices_setup(void) +{ + regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); + + return platform_add_devices(mpr2_devices, ARRAY_SIZE(mpr2_devices)); +} +device_initcall(mpr2_devices_setup); + +/* + * Initialize IRQ setting + */ +static void __init init_mpr2_IRQ(void) +{ + plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-5 */ + + irq_set_irq_type(evt2irq(0x600), IRQ_TYPE_LEVEL_LOW); /* IRQ0 CAN1 */ + irq_set_irq_type(evt2irq(0x620), IRQ_TYPE_LEVEL_LOW); /* IRQ1 CAN2 */ + irq_set_irq_type(evt2irq(0x640), IRQ_TYPE_LEVEL_LOW); /* IRQ2 CAN3 */ + irq_set_irq_type(evt2irq(0x660), IRQ_TYPE_LEVEL_LOW); /* IRQ3 SMSC9115 */ + irq_set_irq_type(evt2irq(0x680), IRQ_TYPE_EDGE_RISING); /* IRQ4 touchscreen */ + irq_set_irq_type(evt2irq(0x6a0), IRQ_TYPE_EDGE_FALLING); /* IRQ5 touchscreen */ + + intc_set_priority(evt2irq(0x600), 13); /* IRQ0 CAN1 */ + intc_set_priority(evt2irq(0x620), 13); /* IRQ0 CAN2 */ + intc_set_priority(evt2irq(0x640), 13); /* IRQ0 CAN3 */ + intc_set_priority(evt2irq(0x660), 6); /* IRQ3 SMSC9115 */ +} + +/* + * The Machine Vector + */ + +static struct sh_machine_vector mv_mpr2 __initmv = { + .mv_name = "mpr2", + .mv_setup = mpr2_setup, + .mv_init_irq = init_mpr2_IRQ, +}; diff --git a/arch/sh/boards/board-polaris.c b/arch/sh/boards/board-polaris.c new file mode 100644 index 00000000..37a08d09 --- /dev/null +++ b/arch/sh/boards/board-polaris.c @@ -0,0 +1,155 @@ +/* + * June 2006 Steve Glendinning + * + * Polaris-specific resource declaration + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define BCR2 (0xFFFFFF62) +#define WCR2 (0xFFFFFF66) +#define AREA5_WAIT_CTRL (0x1C00) +#define WAIT_STATES_10 (0x7) + +/* Dummy supplies, where voltage doesn't matter */ +static struct regulator_consumer_supply dummy_supplies[] = { + REGULATOR_SUPPLY("vddvario", "smsc911x.0"), + REGULATOR_SUPPLY("vdd33a", "smsc911x.0"), +}; + +static struct resource smsc911x_resources[] = { + [0] = { + .name = "smsc911x-memory", + .start = PA_EXT5, + .end = PA_EXT5 + 0x1fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .name = "smsc911x-irq", + .start = IRQ0_IRQ, + .end = IRQ0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct smsc911x_platform_config smsc911x_config = { + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, + .flags = SMSC911X_USE_32BIT, + .phy_interface = PHY_INTERFACE_MODE_MII, +}; + +static struct platform_device smsc911x_device = { + .name = "smsc911x", + .id = 0, + .num_resources = ARRAY_SIZE(smsc911x_resources), + .resource = smsc911x_resources, + .dev = { + .platform_data = &smsc911x_config, + }, +}; + +static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3 }; + +static struct heartbeat_data heartbeat_data = { + .bit_pos = heartbeat_bit_pos, + .nr_bits = ARRAY_SIZE(heartbeat_bit_pos), +}; + +static struct resource heartbeat_resource = { + .start = PORT_PCDR, + .end = PORT_PCDR, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .dev = { + .platform_data = &heartbeat_data, + }, + .num_resources = 1, + .resource = &heartbeat_resource, +}; + +static struct platform_device *polaris_devices[] __initdata = { + &smsc911x_device, + &heartbeat_device, +}; + +static int __init polaris_initialise(void) +{ + u16 wcr, bcr_mask; + + printk(KERN_INFO "Configuring Polaris external bus\n"); + + regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); + + /* Configure area 5 with 2 wait states */ + wcr = __raw_readw(WCR2); + wcr &= (~AREA5_WAIT_CTRL); + wcr |= (WAIT_STATES_10 << 10); + __raw_writew(wcr, WCR2); + + /* Configure area 5 for 32-bit access */ + bcr_mask = __raw_readw(BCR2); + bcr_mask |= 1 << 10; + __raw_writew(bcr_mask, BCR2); + + return platform_add_devices(polaris_devices, + ARRAY_SIZE(polaris_devices)); +} +arch_initcall(polaris_initialise); + +static struct ipr_data ipr_irq_table[] = { + /* External IRQs */ + { IRQ0_IRQ, 0, 0, 1, }, /* IRQ0 */ + { IRQ1_IRQ, 0, 4, 1, }, /* IRQ1 */ +}; + +static unsigned long ipr_offsets[] = { + INTC_IPRC +}; + +static struct ipr_desc ipr_irq_desc = { + .ipr_offsets = ipr_offsets, + .nr_offsets = ARRAY_SIZE(ipr_offsets), + + .ipr_data = ipr_irq_table, + .nr_irqs = ARRAY_SIZE(ipr_irq_table), + .chip = { + .name = "sh7709-ext", + }, +}; + +static void __init init_polaris_irq(void) +{ + /* Disable all interrupts */ + __raw_writew(0, BCR_ILCRA); + __raw_writew(0, BCR_ILCRB); + __raw_writew(0, BCR_ILCRC); + __raw_writew(0, BCR_ILCRD); + __raw_writew(0, BCR_ILCRE); + __raw_writew(0, BCR_ILCRF); + __raw_writew(0, BCR_ILCRG); + + register_ipr_controller(&ipr_irq_desc); +} + +static struct sh_machine_vector mv_polaris __initmv = { + .mv_name = "Polaris", + .mv_init_irq = init_polaris_irq, +}; diff --git a/arch/sh/boards/board-secureedge5410.c b/arch/sh/boards/board-secureedge5410.c new file mode 100644 index 00000000..98b36205 --- /dev/null +++ b/arch/sh/boards/board-secureedge5410.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2002 David McCullough + * Copyright (C) 2003 Paul Mundt + * + * Based on files with the following comments: + * + * Copyright (C) 2000 Kazumoto Kojima + * + * Modified for 7751 Solution Engine by + * Ian da Silva and Jeremy Siegel, 2001. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +unsigned short secureedge5410_ioport; + +/* + * EraseConfig handling functions + */ +static irqreturn_t eraseconfig_interrupt(int irq, void *dev_id) +{ + printk("SnapGear: erase switch interrupt!\n"); + + return IRQ_HANDLED; +} + +static int __init eraseconfig_init(void) +{ + unsigned int irq = evt2irq(0x240); + + printk("SnapGear: EraseConfig init\n"); + + /* Setup "EraseConfig" switch on external IRQ 0 */ + if (request_irq(irq, eraseconfig_interrupt, 0, "Erase Config", NULL)) + printk("SnapGear: failed to register IRQ%d for Reset witch\n", + irq); + else + printk("SnapGear: registered EraseConfig switch on IRQ%d\n", + irq); + return 0; +} +module_init(eraseconfig_init); + +/* + * Initialize IRQ setting + * + * IRL0 = erase switch + * IRL1 = eth0 + * IRL2 = eth1 + * IRL3 = crypto + */ +static void __init init_snapgear_IRQ(void) +{ + printk("Setup SnapGear IRQ/IPR ...\n"); + /* enable individual interrupt mode for externals */ + plat_irq_setup_pins(IRQ_MODE_IRQ); +} + +/* + * The Machine Vector + */ +static struct sh_machine_vector mv_snapgear __initmv = { + .mv_name = "SnapGear SecureEdge5410", + .mv_init_irq = init_snapgear_IRQ, +}; diff --git a/arch/sh/boards/board-sh2007.c b/arch/sh/boards/board-sh2007.c new file mode 100644 index 00000000..1980bb7e --- /dev/null +++ b/arch/sh/boards/board-sh2007.c @@ -0,0 +1,145 @@ +/* + * SH-2007 board support. + * + * Copyright (C) 2003, 2004 SUGIOKA Toshinobu + * Copyright (C) 2010 Hitoshi Mitake + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Dummy supplies, where voltage doesn't matter */ +static struct regulator_consumer_supply dummy_supplies[] = { + REGULATOR_SUPPLY("vddvario", "smsc911x.0"), + REGULATOR_SUPPLY("vdd33a", "smsc911x.0"), + REGULATOR_SUPPLY("vddvario", "smsc911x.1"), + REGULATOR_SUPPLY("vdd33a", "smsc911x.1"), +}; + +struct smsc911x_platform_config smc911x_info = { + .flags = SMSC911X_USE_32BIT, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, +}; + +static struct resource smsc9118_0_resources[] = { + [0] = { + .start = SMC0_BASE, + .end = SMC0_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x240), + .end = evt2irq(0x240), + .flags = IORESOURCE_IRQ, + } +}; + +static struct resource smsc9118_1_resources[] = { + [0] = { + .start = SMC1_BASE, + .end = SMC1_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x280), + .end = evt2irq(0x280), + .flags = IORESOURCE_IRQ, + } +}; + +static struct platform_device smsc9118_0_device = { + .name = "smsc911x", + .id = 0, + .num_resources = ARRAY_SIZE(smsc9118_0_resources), + .resource = smsc9118_0_resources, + .dev = { + .platform_data = &smc911x_info, + }, +}; + +static struct platform_device smsc9118_1_device = { + .name = "smsc911x", + .id = 1, + .num_resources = ARRAY_SIZE(smsc9118_1_resources), + .resource = smsc9118_1_resources, + .dev = { + .platform_data = &smc911x_info, + }, +}; + +static struct resource cf_resources[] = { + [0] = { + .start = CF_BASE + CF_OFFSET, + .end = CF_BASE + CF_OFFSET + 0x0f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = CF_BASE + CF_OFFSET + 0x206, + .end = CF_BASE + CF_OFFSET + 0x20f, + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = evt2irq(0x2c0), + .end = evt2irq(0x2c0), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device cf_device = { + .name = "pata_platform", + .id = 0, + .num_resources = ARRAY_SIZE(cf_resources), + .resource = cf_resources, +}; + +static struct platform_device *sh2007_devices[] __initdata = { + &smsc9118_0_device, + &smsc9118_1_device, + &cf_device, +}; + +static int __init sh2007_io_init(void) +{ + regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); + + platform_add_devices(sh2007_devices, ARRAY_SIZE(sh2007_devices)); + return 0; +} +subsys_initcall(sh2007_io_init); + +static void __init sh2007_init_irq(void) +{ + plat_irq_setup_pins(IRQ_MODE_IRQ); +} + +/* + * Initialize the board + */ +static void __init sh2007_setup(char **cmdline_p) +{ + printk(KERN_INFO "SH-2007 Setup..."); + + /* setup wait control registers for area 5 */ + __raw_writel(CS5BCR_D, CS5BCR); + __raw_writel(CS5WCR_D, CS5WCR); + __raw_writel(CS5PCR_D, CS5PCR); + + printk(KERN_INFO " done.\n"); +} + +/* + * The Machine Vector + */ +struct sh_machine_vector mv_sh2007 __initmv = { + .mv_setup = sh2007_setup, + .mv_name = "sh2007", + .mv_init_irq = sh2007_init_irq, +}; diff --git a/arch/sh/boards/board-sh7757lcr.c b/arch/sh/boards/board-sh7757lcr.c new file mode 100644 index 00000000..41f86702 --- /dev/null +++ b/arch/sh/boards/board-sh7757lcr.c @@ -0,0 +1,615 @@ +/* + * Renesas R0P7757LC0012RL Support. + * + * Copyright (C) 2009 - 2010 Renesas Solutions Corp. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct resource heartbeat_resource = { + .start = 0xffec005c, /* PUDR */ + .end = 0xffec005c, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT, +}; + +static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3 }; + +static struct heartbeat_data heartbeat_data = { + .bit_pos = heartbeat_bit_pos, + .nr_bits = ARRAY_SIZE(heartbeat_bit_pos), + .flags = HEARTBEAT_INVERTED, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .dev = { + .platform_data = &heartbeat_data, + }, + .num_resources = 1, + .resource = &heartbeat_resource, +}; + +/* Fast Ethernet */ +#define GBECONT 0xffc10100 +#define GBECONT_RMII1 BIT(17) +#define GBECONT_RMII0 BIT(16) +static void sh7757_eth_set_mdio_gate(void *addr) +{ + if (((unsigned long)addr & 0x00000fff) < 0x0800) + writel(readl(GBECONT) | GBECONT_RMII0, GBECONT); + else + writel(readl(GBECONT) | GBECONT_RMII1, GBECONT); +} + +static struct resource sh_eth0_resources[] = { + { + .start = 0xfef00000, + .end = 0xfef001ff, + .flags = IORESOURCE_MEM, + }, { + .start = evt2irq(0xc80), + .end = evt2irq(0xc80), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct sh_eth_plat_data sh7757_eth0_pdata = { + .phy = 1, + .edmac_endian = EDMAC_LITTLE_ENDIAN, + .register_type = SH_ETH_REG_FAST_SH4, + .set_mdio_gate = sh7757_eth_set_mdio_gate, +}; + +static struct platform_device sh7757_eth0_device = { + .name = "sh-eth", + .resource = sh_eth0_resources, + .id = 0, + .num_resources = ARRAY_SIZE(sh_eth0_resources), + .dev = { + .platform_data = &sh7757_eth0_pdata, + }, +}; + +static struct resource sh_eth1_resources[] = { + { + .start = 0xfef00800, + .end = 0xfef009ff, + .flags = IORESOURCE_MEM, + }, { + .start = evt2irq(0xc80), + .end = evt2irq(0xc80), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct sh_eth_plat_data sh7757_eth1_pdata = { + .phy = 1, + .edmac_endian = EDMAC_LITTLE_ENDIAN, + .register_type = SH_ETH_REG_FAST_SH4, + .set_mdio_gate = sh7757_eth_set_mdio_gate, +}; + +static struct platform_device sh7757_eth1_device = { + .name = "sh-eth", + .resource = sh_eth1_resources, + .id = 1, + .num_resources = ARRAY_SIZE(sh_eth1_resources), + .dev = { + .platform_data = &sh7757_eth1_pdata, + }, +}; + +static void sh7757_eth_giga_set_mdio_gate(void *addr) +{ + if (((unsigned long)addr & 0x00000fff) < 0x0800) { + gpio_set_value(GPIO_PTT4, 1); + writel(readl(GBECONT) & ~GBECONT_RMII0, GBECONT); + } else { + gpio_set_value(GPIO_PTT4, 0); + writel(readl(GBECONT) & ~GBECONT_RMII1, GBECONT); + } +} + +static struct resource sh_eth_giga0_resources[] = { + { + .start = 0xfee00000, + .end = 0xfee007ff, + .flags = IORESOURCE_MEM, + }, { + /* TSU */ + .start = 0xfee01800, + .end = 0xfee01fff, + .flags = IORESOURCE_MEM, + }, { + .start = evt2irq(0x2960), + .end = evt2irq(0x2960), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct sh_eth_plat_data sh7757_eth_giga0_pdata = { + .phy = 18, + .edmac_endian = EDMAC_LITTLE_ENDIAN, + .register_type = SH_ETH_REG_GIGABIT, + .set_mdio_gate = sh7757_eth_giga_set_mdio_gate, + .phy_interface = PHY_INTERFACE_MODE_RGMII_ID, +}; + +static struct platform_device sh7757_eth_giga0_device = { + .name = "sh-eth", + .resource = sh_eth_giga0_resources, + .id = 2, + .num_resources = ARRAY_SIZE(sh_eth_giga0_resources), + .dev = { + .platform_data = &sh7757_eth_giga0_pdata, + }, +}; + +static struct resource sh_eth_giga1_resources[] = { + { + .start = 0xfee00800, + .end = 0xfee00fff, + .flags = IORESOURCE_MEM, + }, { + /* TSU */ + .start = 0xfee01800, + .end = 0xfee01fff, + .flags = IORESOURCE_MEM, + }, { + .start = evt2irq(0x2980), + .end = evt2irq(0x2980), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct sh_eth_plat_data sh7757_eth_giga1_pdata = { + .phy = 19, + .edmac_endian = EDMAC_LITTLE_ENDIAN, + .register_type = SH_ETH_REG_GIGABIT, + .set_mdio_gate = sh7757_eth_giga_set_mdio_gate, + .phy_interface = PHY_INTERFACE_MODE_RGMII_ID, +}; + +static struct platform_device sh7757_eth_giga1_device = { + .name = "sh-eth", + .resource = sh_eth_giga1_resources, + .id = 3, + .num_resources = ARRAY_SIZE(sh_eth_giga1_resources), + .dev = { + .platform_data = &sh7757_eth_giga1_pdata, + }, +}; + +/* Fixed 3.3V regulator to be used by SDHI0, MMCIF */ +static struct regulator_consumer_supply fixed3v3_power_consumers[] = +{ + REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"), + REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"), + REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"), + REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"), +}; + +/* SH_MMCIF */ +static struct resource sh_mmcif_resources[] = { + [0] = { + .start = 0xffcb0000, + .end = 0xffcb00ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x1c60), + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = evt2irq(0x1c80), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct sh_mmcif_plat_data sh_mmcif_plat = { + .sup_pclk = 0x0f, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | + MMC_CAP_NONREMOVABLE, + .ocr = MMC_VDD_32_33 | MMC_VDD_33_34, + .slave_id_tx = SHDMA_SLAVE_MMCIF_TX, + .slave_id_rx = SHDMA_SLAVE_MMCIF_RX, +}; + +static struct platform_device sh_mmcif_device = { + .name = "sh_mmcif", + .id = 0, + .dev = { + .platform_data = &sh_mmcif_plat, + }, + .num_resources = ARRAY_SIZE(sh_mmcif_resources), + .resource = sh_mmcif_resources, +}; + +/* SDHI0 */ +static struct sh_mobile_sdhi_info sdhi_info = { + .dma_slave_tx = SHDMA_SLAVE_SDHI_TX, + .dma_slave_rx = SHDMA_SLAVE_SDHI_RX, + .tmio_caps = MMC_CAP_SD_HIGHSPEED, +}; + +static struct resource sdhi_resources[] = { + [0] = { + .start = 0xffe50000, + .end = 0xffe501ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x480), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device sdhi_device = { + .name = "sh_mobile_sdhi", + .num_resources = ARRAY_SIZE(sdhi_resources), + .resource = sdhi_resources, + .id = 0, + .dev = { + .platform_data = &sdhi_info, + }, +}; + +static int usbhs0_get_id(struct platform_device *pdev) +{ + return USBHS_GADGET; +} + +static struct renesas_usbhs_platform_info usb0_data = { + .platform_callback = { + .get_id = usbhs0_get_id, + }, + .driver_param = { + .buswait_bwait = 5, + } +}; + +static struct resource usb0_resources[] = { + [0] = { + .start = 0xfe450000, + .end = 0xfe4501ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x840), + .end = evt2irq(0x840), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device usb0_device = { + .name = "renesas_usbhs", + .id = 0, + .dev = { + .platform_data = &usb0_data, + }, + .num_resources = ARRAY_SIZE(usb0_resources), + .resource = usb0_resources, +}; + +static struct platform_device *sh7757lcr_devices[] __initdata = { + &heartbeat_device, + &sh7757_eth0_device, + &sh7757_eth1_device, + &sh7757_eth_giga0_device, + &sh7757_eth_giga1_device, + &sh_mmcif_device, + &sdhi_device, + &usb0_device, +}; + +static struct flash_platform_data spi_flash_data = { + .name = "m25p80", + .type = "m25px64", +}; + +static struct spi_board_info spi_board_info[] = { + { + .modalias = "m25p80", + .max_speed_hz = 25000000, + .bus_num = 0, + .chip_select = 1, + .platform_data = &spi_flash_data, + }, +}; + +static int __init sh7757lcr_devices_setup(void) +{ + regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers, + ARRAY_SIZE(fixed3v3_power_consumers), 3300000); + + /* RGMII (PTA) */ + gpio_request(GPIO_FN_ET0_MDC, NULL); + gpio_request(GPIO_FN_ET0_MDIO, NULL); + gpio_request(GPIO_FN_ET1_MDC, NULL); + gpio_request(GPIO_FN_ET1_MDIO, NULL); + + /* ONFI (PTB, PTZ) */ + gpio_request(GPIO_FN_ON_NRE, NULL); + gpio_request(GPIO_FN_ON_NWE, NULL); + gpio_request(GPIO_FN_ON_NWP, NULL); + gpio_request(GPIO_FN_ON_NCE0, NULL); + gpio_request(GPIO_FN_ON_R_B0, NULL); + gpio_request(GPIO_FN_ON_ALE, NULL); + gpio_request(GPIO_FN_ON_CLE, NULL); + + gpio_request(GPIO_FN_ON_DQ7, NULL); + gpio_request(GPIO_FN_ON_DQ6, NULL); + gpio_request(GPIO_FN_ON_DQ5, NULL); + gpio_request(GPIO_FN_ON_DQ4, NULL); + gpio_request(GPIO_FN_ON_DQ3, NULL); + gpio_request(GPIO_FN_ON_DQ2, NULL); + gpio_request(GPIO_FN_ON_DQ1, NULL); + gpio_request(GPIO_FN_ON_DQ0, NULL); + + /* IRQ8 to 0 (PTB, PTC) */ + gpio_request(GPIO_FN_IRQ8, NULL); + gpio_request(GPIO_FN_IRQ7, NULL); + gpio_request(GPIO_FN_IRQ6, NULL); + gpio_request(GPIO_FN_IRQ5, NULL); + gpio_request(GPIO_FN_IRQ4, NULL); + gpio_request(GPIO_FN_IRQ3, NULL); + gpio_request(GPIO_FN_IRQ2, NULL); + gpio_request(GPIO_FN_IRQ1, NULL); + gpio_request(GPIO_FN_IRQ0, NULL); + + /* SPI0 (PTD) */ + gpio_request(GPIO_FN_SP0_MOSI, NULL); + gpio_request(GPIO_FN_SP0_MISO, NULL); + gpio_request(GPIO_FN_SP0_SCK, NULL); + gpio_request(GPIO_FN_SP0_SCK_FB, NULL); + gpio_request(GPIO_FN_SP0_SS0, NULL); + gpio_request(GPIO_FN_SP0_SS1, NULL); + gpio_request(GPIO_FN_SP0_SS2, NULL); + gpio_request(GPIO_FN_SP0_SS3, NULL); + + /* RMII 0/1 (PTE, PTF) */ + gpio_request(GPIO_FN_RMII0_CRS_DV, NULL); + gpio_request(GPIO_FN_RMII0_TXD1, NULL); + gpio_request(GPIO_FN_RMII0_TXD0, NULL); + gpio_request(GPIO_FN_RMII0_TXEN, NULL); + gpio_request(GPIO_FN_RMII0_REFCLK, NULL); + gpio_request(GPIO_FN_RMII0_RXD1, NULL); + gpio_request(GPIO_FN_RMII0_RXD0, NULL); + gpio_request(GPIO_FN_RMII0_RX_ER, NULL); + gpio_request(GPIO_FN_RMII1_CRS_DV, NULL); + gpio_request(GPIO_FN_RMII1_TXD1, NULL); + gpio_request(GPIO_FN_RMII1_TXD0, NULL); + gpio_request(GPIO_FN_RMII1_TXEN, NULL); + gpio_request(GPIO_FN_RMII1_REFCLK, NULL); + gpio_request(GPIO_FN_RMII1_RXD1, NULL); + gpio_request(GPIO_FN_RMII1_RXD0, NULL); + gpio_request(GPIO_FN_RMII1_RX_ER, NULL); + + /* eMMC (PTG) */ + gpio_request(GPIO_FN_MMCCLK, NULL); + gpio_request(GPIO_FN_MMCCMD, NULL); + gpio_request(GPIO_FN_MMCDAT7, NULL); + gpio_request(GPIO_FN_MMCDAT6, NULL); + gpio_request(GPIO_FN_MMCDAT5, NULL); + gpio_request(GPIO_FN_MMCDAT4, NULL); + gpio_request(GPIO_FN_MMCDAT3, NULL); + gpio_request(GPIO_FN_MMCDAT2, NULL); + gpio_request(GPIO_FN_MMCDAT1, NULL); + gpio_request(GPIO_FN_MMCDAT0, NULL); + + /* LPC (PTG, PTH, PTQ, PTU) */ + gpio_request(GPIO_FN_SERIRQ, NULL); + gpio_request(GPIO_FN_LPCPD, NULL); + gpio_request(GPIO_FN_LDRQ, NULL); + gpio_request(GPIO_FN_WP, NULL); + gpio_request(GPIO_FN_FMS0, NULL); + gpio_request(GPIO_FN_LAD3, NULL); + gpio_request(GPIO_FN_LAD2, NULL); + gpio_request(GPIO_FN_LAD1, NULL); + gpio_request(GPIO_FN_LAD0, NULL); + gpio_request(GPIO_FN_LFRAME, NULL); + gpio_request(GPIO_FN_LRESET, NULL); + gpio_request(GPIO_FN_LCLK, NULL); + gpio_request(GPIO_FN_LGPIO7, NULL); + gpio_request(GPIO_FN_LGPIO6, NULL); + gpio_request(GPIO_FN_LGPIO5, NULL); + gpio_request(GPIO_FN_LGPIO4, NULL); + + /* SPI1 (PTH) */ + gpio_request(GPIO_FN_SP1_MOSI, NULL); + gpio_request(GPIO_FN_SP1_MISO, NULL); + gpio_request(GPIO_FN_SP1_SCK, NULL); + gpio_request(GPIO_FN_SP1_SCK_FB, NULL); + gpio_request(GPIO_FN_SP1_SS0, NULL); + gpio_request(GPIO_FN_SP1_SS1, NULL); + + /* SDHI (PTI) */ + gpio_request(GPIO_FN_SD_WP, NULL); + gpio_request(GPIO_FN_SD_CD, NULL); + gpio_request(GPIO_FN_SD_CLK, NULL); + gpio_request(GPIO_FN_SD_CMD, NULL); + gpio_request(GPIO_FN_SD_D3, NULL); + gpio_request(GPIO_FN_SD_D2, NULL); + gpio_request(GPIO_FN_SD_D1, NULL); + gpio_request(GPIO_FN_SD_D0, NULL); + + /* SCIF3/4 (PTJ, PTW) */ + gpio_request(GPIO_FN_RTS3, NULL); + gpio_request(GPIO_FN_CTS3, NULL); + gpio_request(GPIO_FN_TXD3, NULL); + gpio_request(GPIO_FN_RXD3, NULL); + gpio_request(GPIO_FN_RTS4, NULL); + gpio_request(GPIO_FN_RXD4, NULL); + gpio_request(GPIO_FN_TXD4, NULL); + gpio_request(GPIO_FN_CTS4, NULL); + + /* SERMUX (PTK, PTL, PTO, PTV) */ + gpio_request(GPIO_FN_COM2_TXD, NULL); + gpio_request(GPIO_FN_COM2_RXD, NULL); + gpio_request(GPIO_FN_COM2_RTS, NULL); + gpio_request(GPIO_FN_COM2_CTS, NULL); + gpio_request(GPIO_FN_COM2_DTR, NULL); + gpio_request(GPIO_FN_COM2_DSR, NULL); + gpio_request(GPIO_FN_COM2_DCD, NULL); + gpio_request(GPIO_FN_COM2_RI, NULL); + gpio_request(GPIO_FN_RAC_RXD, NULL); + gpio_request(GPIO_FN_RAC_RTS, NULL); + gpio_request(GPIO_FN_RAC_CTS, NULL); + gpio_request(GPIO_FN_RAC_DTR, NULL); + gpio_request(GPIO_FN_RAC_DSR, NULL); + gpio_request(GPIO_FN_RAC_DCD, NULL); + gpio_request(GPIO_FN_RAC_TXD, NULL); + gpio_request(GPIO_FN_COM1_TXD, NULL); + gpio_request(GPIO_FN_COM1_RXD, NULL); + gpio_request(GPIO_FN_COM1_RTS, NULL); + gpio_request(GPIO_FN_COM1_CTS, NULL); + + writeb(0x10, 0xfe470000); /* SMR0: SerMux mode 0 */ + + /* IIC (PTM, PTR, PTS) */ + gpio_request(GPIO_FN_SDA7, NULL); + gpio_request(GPIO_FN_SCL7, NULL); + gpio_request(GPIO_FN_SDA6, NULL); + gpio_request(GPIO_FN_SCL6, NULL); + gpio_request(GPIO_FN_SDA5, NULL); + gpio_request(GPIO_FN_SCL5, NULL); + gpio_request(GPIO_FN_SDA4, NULL); + gpio_request(GPIO_FN_SCL4, NULL); + gpio_request(GPIO_FN_SDA3, NULL); + gpio_request(GPIO_FN_SCL3, NULL); + gpio_request(GPIO_FN_SDA2, NULL); + gpio_request(GPIO_FN_SCL2, NULL); + gpio_request(GPIO_FN_SDA1, NULL); + gpio_request(GPIO_FN_SCL1, NULL); + gpio_request(GPIO_FN_SDA0, NULL); + gpio_request(GPIO_FN_SCL0, NULL); + + /* USB (PTN) */ + gpio_request(GPIO_FN_VBUS_EN, NULL); + gpio_request(GPIO_FN_VBUS_OC, NULL); + + /* SGPIO1/0 (PTN, PTO) */ + gpio_request(GPIO_FN_SGPIO1_CLK, NULL); + gpio_request(GPIO_FN_SGPIO1_LOAD, NULL); + gpio_request(GPIO_FN_SGPIO1_DI, NULL); + gpio_request(GPIO_FN_SGPIO1_DO, NULL); + gpio_request(GPIO_FN_SGPIO0_CLK, NULL); + gpio_request(GPIO_FN_SGPIO0_LOAD, NULL); + gpio_request(GPIO_FN_SGPIO0_DI, NULL); + gpio_request(GPIO_FN_SGPIO0_DO, NULL); + + /* WDT (PTN) */ + gpio_request(GPIO_FN_SUB_CLKIN, NULL); + + /* System (PTT) */ + gpio_request(GPIO_FN_STATUS1, NULL); + gpio_request(GPIO_FN_STATUS0, NULL); + + /* PWMX (PTT) */ + gpio_request(GPIO_FN_PWMX1, NULL); + gpio_request(GPIO_FN_PWMX0, NULL); + + /* R-SPI (PTV) */ + gpio_request(GPIO_FN_R_SPI_MOSI, NULL); + gpio_request(GPIO_FN_R_SPI_MISO, NULL); + gpio_request(GPIO_FN_R_SPI_RSPCK, NULL); + gpio_request(GPIO_FN_R_SPI_SSL0, NULL); + gpio_request(GPIO_FN_R_SPI_SSL1, NULL); + + /* EVC (PTV, PTW) */ + gpio_request(GPIO_FN_EVENT7, NULL); + gpio_request(GPIO_FN_EVENT6, NULL); + gpio_request(GPIO_FN_EVENT5, NULL); + gpio_request(GPIO_FN_EVENT4, NULL); + gpio_request(GPIO_FN_EVENT3, NULL); + gpio_request(GPIO_FN_EVENT2, NULL); + gpio_request(GPIO_FN_EVENT1, NULL); + gpio_request(GPIO_FN_EVENT0, NULL); + + /* LED for heartbeat */ + gpio_request(GPIO_PTU3, NULL); + gpio_direction_output(GPIO_PTU3, 1); + gpio_request(GPIO_PTU2, NULL); + gpio_direction_output(GPIO_PTU2, 1); + gpio_request(GPIO_PTU1, NULL); + gpio_direction_output(GPIO_PTU1, 1); + gpio_request(GPIO_PTU0, NULL); + gpio_direction_output(GPIO_PTU0, 1); + + /* control for MDIO of Gigabit Ethernet */ + gpio_request(GPIO_PTT4, NULL); + gpio_direction_output(GPIO_PTT4, 1); + + /* control for eMMC */ + gpio_request(GPIO_PTT7, NULL); /* eMMC_RST# */ + gpio_direction_output(GPIO_PTT7, 0); + gpio_request(GPIO_PTT6, NULL); /* eMMC_INDEX# */ + gpio_direction_output(GPIO_PTT6, 0); + gpio_request(GPIO_PTT5, NULL); /* eMMC_PRST# */ + gpio_direction_output(GPIO_PTT5, 1); + + /* register SPI device information */ + spi_register_board_info(spi_board_info, + ARRAY_SIZE(spi_board_info)); + + /* General platform */ + return platform_add_devices(sh7757lcr_devices, + ARRAY_SIZE(sh7757lcr_devices)); +} +arch_initcall(sh7757lcr_devices_setup); + +/* Initialize IRQ setting */ +void __init init_sh7757lcr_IRQ(void) +{ + plat_irq_setup_pins(IRQ_MODE_IRQ7654); + plat_irq_setup_pins(IRQ_MODE_IRQ3210); +} + +/* Initialize the board */ +static void __init sh7757lcr_setup(char **cmdline_p) +{ + printk(KERN_INFO "Renesas R0P7757LC0012RL support.\n"); +} + +static int sh7757lcr_mode_pins(void) +{ + int value = 0; + + /* These are the factory default settings of S3 (Low active). + * If you change these dip switches then you will need to + * adjust the values below as well. + */ + value |= MODE_PIN0; /* Clock Mode: 1 */ + + return value; +} + +/* The Machine Vector */ +static struct sh_machine_vector mv_sh7757lcr __initmv = { + .mv_name = "SH7757LCR", + .mv_setup = sh7757lcr_setup, + .mv_init_irq = init_sh7757lcr_IRQ, + .mv_mode_pins = sh7757lcr_mode_pins, +}; + diff --git a/arch/sh/boards/board-sh7785lcr.c b/arch/sh/boards/board-sh7785lcr.c new file mode 100644 index 00000000..2c4771ee --- /dev/null +++ b/arch/sh/boards/board-sh7785lcr.c @@ -0,0 +1,378 @@ +/* + * Renesas Technology Corp. R0P7785LC0011RL Support. + * + * Copyright (C) 2008 Yoshihiro Shimoda + * Copyright (C) 2009 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * NOTE: This board has 2 physical memory maps. + * Please look at include/asm-sh/sh7785lcr.h or hardware manual. + */ +static struct resource heartbeat_resource = { + .start = PLD_LEDCR, + .end = PLD_LEDCR, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .num_resources = 1, + .resource = &heartbeat_resource, +}; + +static struct mtd_partition nor_flash_partitions[] = { + { + .name = "loader", + .offset = 0x00000000, + .size = 512 * 1024, + }, + { + .name = "bootenv", + .offset = MTDPART_OFS_APPEND, + .size = 512 * 1024, + }, + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = 4 * 1024 * 1024, + }, + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data nor_flash_data = { + .width = 4, + .parts = nor_flash_partitions, + .nr_parts = ARRAY_SIZE(nor_flash_partitions), +}; + +static struct resource nor_flash_resources[] = { + [0] = { + .start = NOR_FLASH_ADDR, + .end = NOR_FLASH_ADDR + NOR_FLASH_SIZE - 1, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device nor_flash_device = { + .name = "physmap-flash", + .dev = { + .platform_data = &nor_flash_data, + }, + .num_resources = ARRAY_SIZE(nor_flash_resources), + .resource = nor_flash_resources, +}; + +static struct r8a66597_platdata r8a66597_data = { + .xtal = R8A66597_PLATDATA_XTAL_12MHZ, + .vif = 1, +}; + +static struct resource r8a66597_usb_host_resources[] = { + [0] = { + .start = R8A66597_ADDR, + .end = R8A66597_ADDR + R8A66597_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x240), + .end = evt2irq(0x240), + .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, + }, +}; + +static struct platform_device r8a66597_usb_host_device = { + .name = "r8a66597_hcd", + .id = -1, + .dev = { + .dma_mask = NULL, + .coherent_dma_mask = 0xffffffff, + .platform_data = &r8a66597_data, + }, + .num_resources = ARRAY_SIZE(r8a66597_usb_host_resources), + .resource = r8a66597_usb_host_resources, +}; + +static struct resource sm501_resources[] = { + [0] = { + .start = SM107_MEM_ADDR, + .end = SM107_MEM_ADDR + SM107_MEM_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = SM107_REG_ADDR, + .end = SM107_REG_ADDR + SM107_REG_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = evt2irq(0x340), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct fb_videomode sm501_default_mode_crt = { + .pixclock = 35714, /* 28MHz */ + .xres = 640, + .yres = 480, + .left_margin = 105, + .right_margin = 16, + .upper_margin = 33, + .lower_margin = 10, + .hsync_len = 39, + .vsync_len = 2, + .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, +}; + +static struct fb_videomode sm501_default_mode_pnl = { + .pixclock = 40000, /* 25MHz */ + .xres = 640, + .yres = 480, + .left_margin = 2, + .right_margin = 16, + .upper_margin = 33, + .lower_margin = 10, + .hsync_len = 39, + .vsync_len = 2, + .sync = 0, +}; + +static struct sm501_platdata_fbsub sm501_pdata_fbsub_pnl = { + .def_bpp = 16, + .def_mode = &sm501_default_mode_pnl, + .flags = SM501FB_FLAG_USE_INIT_MODE | + SM501FB_FLAG_USE_HWCURSOR | + SM501FB_FLAG_USE_HWACCEL | + SM501FB_FLAG_DISABLE_AT_EXIT | + SM501FB_FLAG_PANEL_NO_VBIASEN, +}; + +static struct sm501_platdata_fbsub sm501_pdata_fbsub_crt = { + .def_bpp = 16, + .def_mode = &sm501_default_mode_crt, + .flags = SM501FB_FLAG_USE_INIT_MODE | + SM501FB_FLAG_USE_HWCURSOR | + SM501FB_FLAG_USE_HWACCEL | + SM501FB_FLAG_DISABLE_AT_EXIT, +}; + +static struct sm501_platdata_fb sm501_fb_pdata = { + .fb_route = SM501_FB_OWN, + .fb_crt = &sm501_pdata_fbsub_crt, + .fb_pnl = &sm501_pdata_fbsub_pnl, +}; + +static struct sm501_initdata sm501_initdata = { + .gpio_high = { + .set = 0x00001fe0, + .mask = 0x0, + }, + .devices = 0, + .mclk = 84 * 1000000, + .m1xclk = 112 * 1000000, +}; + +static struct sm501_platdata sm501_platform_data = { + .init = &sm501_initdata, + .fb = &sm501_fb_pdata, +}; + +static struct platform_device sm501_device = { + .name = "sm501", + .id = -1, + .dev = { + .platform_data = &sm501_platform_data, + }, + .num_resources = ARRAY_SIZE(sm501_resources), + .resource = sm501_resources, +}; + +static struct resource i2c_proto_resources[] = { + [0] = { + .start = PCA9564_PROTO_32BIT_ADDR, + .end = PCA9564_PROTO_32BIT_ADDR + PCA9564_SIZE - 1, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT, + }, + [1] = { + .start = evt2irq(0x380), + .end = evt2irq(0x380), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource i2c_resources[] = { + [0] = { + .start = PCA9564_ADDR, + .end = PCA9564_ADDR + PCA9564_SIZE - 1, + .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT, + }, + [1] = { + .start = evt2irq(0x380), + .end = evt2irq(0x380), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct i2c_pca9564_pf_platform_data i2c_platform_data = { + .gpio = 0, + .i2c_clock_speed = I2C_PCA_CON_330kHz, + .timeout = HZ, +}; + +static struct platform_device i2c_device = { + .name = "i2c-pca-platform", + .id = -1, + .dev = { + .platform_data = &i2c_platform_data, + }, + .num_resources = ARRAY_SIZE(i2c_resources), + .resource = i2c_resources, +}; + +static struct platform_device *sh7785lcr_devices[] __initdata = { + &heartbeat_device, + &nor_flash_device, + &r8a66597_usb_host_device, + &sm501_device, + &i2c_device, +}; + +static struct i2c_board_info __initdata sh7785lcr_i2c_devices[] = { + { + I2C_BOARD_INFO("r2025sd", 0x32), + }, +}; + +static int __init sh7785lcr_devices_setup(void) +{ + i2c_register_board_info(0, sh7785lcr_i2c_devices, + ARRAY_SIZE(sh7785lcr_i2c_devices)); + + if (mach_is_sh7785lcr_pt()) { + i2c_device.resource = i2c_proto_resources; + i2c_device.num_resources = ARRAY_SIZE(i2c_proto_resources); + } + + return platform_add_devices(sh7785lcr_devices, + ARRAY_SIZE(sh7785lcr_devices)); +} +device_initcall(sh7785lcr_devices_setup); + +/* Initialize IRQ setting */ +void __init init_sh7785lcr_IRQ(void) +{ + plat_irq_setup_pins(IRQ_MODE_IRQ7654); + plat_irq_setup_pins(IRQ_MODE_IRQ3210); +} + +static int sh7785lcr_clk_init(void) +{ + struct clk *clk; + int ret; + + clk = clk_get(NULL, "extal"); + if (IS_ERR(clk)) + return PTR_ERR(clk); + ret = clk_set_rate(clk, 33333333); + clk_put(clk); + + return ret; +} + +static void sh7785lcr_power_off(void) +{ + unsigned char *p; + + p = ioremap(PLD_POFCR, PLD_POFCR + 1); + if (!p) { + printk(KERN_ERR "%s: ioremap error.\n", __func__); + return; + } + *p = 0x01; + iounmap(p); + set_bl_bit(); + while (1) + cpu_relax(); +} + +/* Initialize the board */ +static void __init sh7785lcr_setup(char **cmdline_p) +{ + void __iomem *sm501_reg; + + printk(KERN_INFO "Renesas Technology Corp. R0P7785LC0011RL support.\n"); + + pm_power_off = sh7785lcr_power_off; + + /* sm501 DRAM configuration */ + sm501_reg = ioremap_nocache(SM107_REG_ADDR, SM501_DRAM_CONTROL); + if (!sm501_reg) { + printk(KERN_ERR "%s: ioremap error.\n", __func__); + return; + } + + writel(0x000307c2, sm501_reg + SM501_DRAM_CONTROL); + iounmap(sm501_reg); +} + +/* Return the board specific boot mode pin configuration */ +static int sh7785lcr_mode_pins(void) +{ + int value = 0; + + /* These are the factory default settings of S1 and S2. + * If you change these dip switches then you will need to + * adjust the values below as well. + */ + value |= MODE_PIN4; /* Clock Mode 16 */ + value |= MODE_PIN5; /* 32-bit Area0 bus width */ + value |= MODE_PIN6; /* 32-bit Area0 bus width */ + value |= MODE_PIN7; /* Area 0 SRAM interface [fixed] */ + value |= MODE_PIN8; /* Little Endian */ + value |= MODE_PIN9; /* Master Mode */ + value |= MODE_PIN14; /* No PLL step-up */ + + return value; +} + +/* + * The Machine Vector + */ +static struct sh_machine_vector mv_sh7785lcr __initmv = { + .mv_name = "SH7785LCR", + .mv_setup = sh7785lcr_setup, + .mv_clk_init = sh7785lcr_clk_init, + .mv_init_irq = init_sh7785lcr_IRQ, + .mv_mode_pins = sh7785lcr_mode_pins, +}; + diff --git a/arch/sh/boards/board-shmin.c b/arch/sh/boards/board-shmin.c new file mode 100644 index 00000000..325bed53 --- /dev/null +++ b/arch/sh/boards/board-shmin.c @@ -0,0 +1,34 @@ +/* + * arch/sh/boards/shmin/setup.c + * + * Copyright (C) 2006 Takashi YOSHII + * + * SHMIN Support. + */ +#include +#include +#include +#include +#include +#include + +#define PFC_PHCR 0xa400010eUL +#define INTC_ICR1 0xa4000010UL + +static void __init init_shmin_irq(void) +{ + __raw_writew(0x2a00, PFC_PHCR); // IRQ0-3=IRQ + __raw_writew(0x0aaa, INTC_ICR1); // IRQ0-3=IRQ-mode,Low-active. + plat_irq_setup_pins(IRQ_MODE_IRQ); +} + +static void __init shmin_setup(char **cmdline_p) +{ + __set_io_port_base(SHMIN_IO_BASE); +} + +static struct sh_machine_vector mv_shmin __initmv = { + .mv_name = "SHMIN", + .mv_setup = shmin_setup, + .mv_init_irq = init_shmin_irq, +}; diff --git a/arch/sh/boards/board-titan.c b/arch/sh/boards/board-titan.c new file mode 100644 index 00000000..94c36c7b --- /dev/null +++ b/arch/sh/boards/board-titan.c @@ -0,0 +1,24 @@ +/* + * arch/sh/boards/titan/setup.c - Setup for Titan + * + * Copyright (C) 2006 Jamie Lenehan + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include + +static void __init init_titan_irq(void) +{ + /* enable individual interrupt mode for externals */ + plat_irq_setup_pins(IRQ_MODE_IRQ); +} + +static struct sh_machine_vector mv_titan __initmv = { + .mv_name = "Titan", + .mv_init_irq = init_titan_irq, +}; diff --git a/arch/sh/boards/board-urquell.c b/arch/sh/boards/board-urquell.c new file mode 100644 index 00000000..b52abcc5 --- /dev/null +++ b/arch/sh/boards/board-urquell.c @@ -0,0 +1,221 @@ +/* + * Renesas Technology Corp. SH7786 Urquell Support. + * + * Copyright (C) 2008 Kuninori Morimoto + * Copyright (C) 2009, 2010 Paul Mundt + * + * Based on board-sh7785lcr.c + * Copyright (C) 2008 Yoshihiro Shimoda + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * bit 1234 5678 + *---------------------------- + * SW1 0101 0010 -> Pck 33MHz version + * (1101 0010) Pck 66MHz version + * SW2 0x1x xxxx -> little endian + * 29bit mode + * SW47 0001 1000 -> CS0 : on-board flash + * CS1 : SRAM, registers, LAN, PCMCIA + * 38400 bps for SCIF1 + * + * Address + * 0x00000000 - 0x04000000 (CS0) Nor Flash + * 0x04000000 - 0x04200000 (CS1) SRAM + * 0x05000000 - 0x05800000 (CS1) on board register + * 0x05800000 - 0x06000000 (CS1) LAN91C111 + * 0x06000000 - 0x06400000 (CS1) PCMCIA + * 0x08000000 - 0x10000000 (CS2-CS3) DDR3 + * 0x10000000 - 0x14000000 (CS4) PCIe + * 0x14000000 - 0x14800000 (CS5) Core0 LRAM/URAM + * 0x14800000 - 0x15000000 (CS5) Core1 LRAM/URAM + * 0x18000000 - 0x1C000000 (CS6) ATA/NAND-Flash + * 0x1C000000 - (CS7) SH7786 Control register + */ + +/* HeartBeat */ +static struct resource heartbeat_resource = { + .start = BOARDREG(SLEDR), + .end = BOARDREG(SLEDR), + .flags = IORESOURCE_MEM | IORESOURCE_MEM_16BIT, +}; + +static struct platform_device heartbeat_device = { + .name = "heartbeat", + .id = -1, + .num_resources = 1, + .resource = &heartbeat_resource, +}; + +/* LAN91C111 */ +static struct smc91x_platdata smc91x_info = { + .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, +}; + +static struct resource smc91x_eth_resources[] = { + [0] = { + .name = "SMC91C111" , + .start = 0x05800300, + .end = 0x0580030f, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = evt2irq(0x360), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device smc91x_eth_device = { + .name = "smc91x", + .num_resources = ARRAY_SIZE(smc91x_eth_resources), + .resource = smc91x_eth_resources, + .dev = { + .platform_data = &smc91x_info, + }, +}; + +/* Nor Flash */ +static struct mtd_partition nor_flash_partitions[] = { + { + .name = "loader", + .offset = 0x00000000, + .size = SZ_512K, + .mask_flags = MTD_WRITEABLE, /* Read-only */ + }, + { + .name = "bootenv", + .offset = MTDPART_OFS_APPEND, + .size = SZ_512K, + .mask_flags = MTD_WRITEABLE, /* Read-only */ + }, + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = SZ_4M, + }, + { + .name = "data", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct physmap_flash_data nor_flash_data = { + .width = 2, + .parts = nor_flash_partitions, + .nr_parts = ARRAY_SIZE(nor_flash_partitions), +}; + +static struct resource nor_flash_resources[] = { + [0] = { + .start = NOR_FLASH_ADDR, + .end = NOR_FLASH_ADDR + NOR_FLASH_SIZE - 1, + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device nor_flash_device = { + .name = "physmap-flash", + .dev = { + .platform_data = &nor_flash_data, + }, + .num_resources = ARRAY_SIZE(nor_flash_resources), + .resource = nor_flash_resources, +}; + +static struct platform_device *urquell_devices[] __initdata = { + &heartbeat_device, + &smc91x_eth_device, + &nor_flash_device, +}; + +static int __init urquell_devices_setup(void) +{ + /* USB */ + gpio_request(GPIO_FN_USB_OVC0, NULL); + gpio_request(GPIO_FN_USB_PENC0, NULL); + + /* enable LAN */ + __raw_writew(__raw_readw(UBOARDREG(IRL2MSKR)) & ~0x00000001, + UBOARDREG(IRL2MSKR)); + + return platform_add_devices(urquell_devices, + ARRAY_SIZE(urquell_devices)); +} +device_initcall(urquell_devices_setup); + +static void urquell_power_off(void) +{ + __raw_writew(0xa5a5, UBOARDREG(SRSTR)); +} + +static void __init urquell_init_irq(void) +{ + plat_irq_setup_pins(IRQ_MODE_IRL3210_MASK); +} + +static int urquell_mode_pins(void) +{ + return __raw_readw(UBOARDREG(MDSWMR)); +} + +static int urquell_clk_init(void) +{ + struct clk *clk; + int ret; + + /* + * Only handle the EXTAL case, anyone interfacing a crystal + * resonator will need to provide their own input clock. + */ + if (test_mode_pin(MODE_PIN9)) + return -EINVAL; + + clk = clk_get(NULL, "extal"); + if (IS_ERR(clk)) + return PTR_ERR(clk); + ret = clk_set_rate(clk, 33333333); + clk_put(clk); + + return ret; +} + +/* Initialize the board */ +static void __init urquell_setup(char **cmdline_p) +{ + printk(KERN_INFO "Renesas Technology Corp. Urquell support.\n"); + + pm_power_off = urquell_power_off; + + register_smp_ops(&shx3_smp_ops); +} + +/* + * The Machine Vector + */ +static struct sh_machine_vector mv_urquell __initmv = { + .mv_name = "Urquell", + .mv_setup = urquell_setup, + .mv_init_irq = urquell_init_irq, + .mv_mode_pins = urquell_mode_pins, + .mv_clk_init = urquell_clk_init, +}; diff --git a/arch/sh/boards/mach-ap325rxa/Makefile b/arch/sh/boards/mach-ap325rxa/Makefile new file mode 100644 index 00000000..4cf1774d --- /dev/null +++ b/arch/sh/boards/mach-ap325rxa/Makefile @@ -0,0 +1,2 @@ +obj-y := setup.o sdram.o + diff --git a/arch/sh/boards/mach-ap325rxa/sdram.S b/arch/sh/boards/mach-ap325rxa/sdram.S new file mode 100644 index 00000000..db24fbed --- /dev/null +++ b/arch/sh/boards/mach-ap325rxa/sdram.S @@ -0,0 +1,69 @@ +/* + * AP325RXA sdram self/auto-refresh setup code + * + * Copyright (C) 2009 Magnus Damm + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include +#include +#include +#include +#include +#include + +/* code to enter and leave self-refresh. must be self-contained. + * this code will be copied to on-chip memory and executed from there. + */ + .balign 4 +ENTRY(ap325rxa_sdram_enter_start) + + /* SBSC: disable power down and put in self-refresh mode */ + mov.l 1f, r4 + mov.l 2f, r1 + mov.l @r4, r2 + or r1, r2 + mov.l 3f, r3 + and r3, r2 + mov.l r2, @r4 + + rts + nop + + .balign 4 +1: .long 0xfe400008 /* SDCR0 */ +2: .long 0x00000400 +3: .long 0xffff7fff +ENTRY(ap325rxa_sdram_enter_end) + + .balign 4 +ENTRY(ap325rxa_sdram_leave_start) + + /* SBSC: set auto-refresh mode */ + mov.l 1f, r4 + mov.l @r4, r0 + mov.l 4f, r1 + and r1, r0 + mov.l r0, @r4 + mov.l 6f, r4 + mov.l 8f, r0 + mov.l @r4, r1 + mov #-1, r4 + add r4, r1 + or r1, r0 + mov.l 7f, r1 + mov.l r0, @r1 + + rts + nop + + .balign 4 +1: .long 0xfe400008 /* SDCR0 */ +4: .long 0xfffffbff +6: .long 0xfe40001c /* RTCOR */ +7: .long 0xfe400018 /* RTCNT */ +8: .long 0xa55a0000 +ENTRY(ap325rxa_sdram_leave_end) diff --git a/arch/sh/boards/mach-ap325rxa/setup.c b/arch/sh/boards/mach-ap325rxa/setup.c new file mode 100644 index 00000000..5620e33c --- /dev/null +++ b/arch/sh/boards/mach-ap325rxa/setup.c @@ -0,0 +1,695 @@ +/* + * Renesas - AP-325RXA + * (Compatible with Algo System ., LTD. - AP-320A) + * + * Copyright (C) 2008 Renesas Solutions Corp. + * Author : Yusuke Goda + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include