Interrupts

This example application demonstrates the interrupt preemption and
tail-chaining capabilities of Cortex-M4 microprocessor and NVIC.  Nested
interrupts are synthesized when the interrupts have the same priority,
increasing priorities, and decreasing priorities.  With increasing
priorities, preemption will occur; in the other two cases tail-chaining
will occur.  The currently pending interrupts and the currently executing
interrupt will be displayed on the display; GPIO pins B3, L1 and L0 (the
GPIO on jumper J27 on the left edge of the board) will be asserted upon
interrupt handler entry and de-asserted before interrupt handler exit so
that the off-to-on time can be observed with a scope or logic analyzer to
see the speed of tail-chaining (for the two cases where tail-chaining is
occurring).

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Copyright (c) 2013-2014 Texas Instruments Incorporated.  All rights reserved.
Software License Agreement

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exclusively on TI's microcontroller products. The software is owned by
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software in order to form a larger program.

THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
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DAMAGES, FOR ANY REASON WHATSOEVER.

This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package.